tomahawk3.h (57834B)
1 2 /* 3 * 4 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 5 * 6 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 7 * 8 * File: tomahawk.h 9 */ 10 11 #ifndef _soc_tomahawk3_H_ 12 #define _soc_tomahawk3_H_ 13 14 #include <soc/drv.h> 15 #include <soc/tomahawk.h> 16 #include <soc/esw/port.h> 17 18 #define SOC_TH3_PM4X10_COUNT 1 19 #define SOC_TH3_PM8X50_COUNT 32 20 21 #define SOC_TH3_PM4X10_PORT_1 257 22 23 #define SOC_TH3_MMU_BASE_TYPE_IPORT 0 24 #define SOC_TH3_MMU_BASE_TYPE_EPORT 1 25 #define SOC_TH3_MMU_BASE_TYPE_IPIPE 2 26 #define SOC_TH3_MMU_BASE_TYPE_EPIPE 3 27 #define SOC_TH3_MMU_BASE_TYPE_CHIP 4 28 #define SOC_TH3_MMU_BASE_TYPE_ITM 5 29 30 #define soc_th3_MEM_CHK_IFP_TCAM(mem) \ 31 (mem == IFP_TCAMm || \ 32 mem == IFP_TCAM_PIPE0m || mem == IFP_TCAM_PIPE1m || \ 33 mem == IFP_TCAM_PIPE2m || mem == IFP_TCAM_PIPE3m) 34 #define soc_th3_MEM_CHK_IFP_TCAM_WIDE(mem) \ 35 (mem == IFP_TCAM_WIDEm || \ 36 mem == IFP_TCAM_WIDE_PIPE0m || mem == IFP_TCAM_WIDE_PIPE1m || \ 37 mem == IFP_TCAM_WIDE_PIPE2m || mem == IFP_TCAM_WIDE_PIPE3m) 38 #define soc_th3_MEM_CHK_TCAM_GLOBAL_UNIQUE_MODE(mem) \ 39 (mem == SRC_COMPRESSIONm || mem == DST_COMPRESSIONm || \ 40 mem == FP_UDF_TCAMm || mem == VFP_TCAMm || \ 41 mem == IFP_LOGICAL_TABLE_SELECTm || \ 42 mem == EXACT_MATCH_LOGICAL_TABLE_SELECTm || \ 43 mem == EFP_TCAMm || mem == IFP_TCAMm || mem == IFP_TCAM_WIDEm) \ 44 /* Field multi-size slices */ 45 #define _BCM_FIELD_TH3_INGRESS_MAX_SMALL_SLICES 6 46 #define _BCM_FIELD_TH3_INGRESS_SMALL_SLICE_SZ 256 47 #define _BCM_FIELD_TH3_INGRESS_LARGE_SLICE_SZ 512 48 49 #define IS_HG2_SPEED(speed) ((106000 == speed) || (53000 == speed) || \ 50 (42000 == speed) || (27000 == speed) || \ 51 (21000 == speed) || (11000 == speed)) 52 53 #define CCLK_FREQ_850MHZ 850 54 55 #define SOC_TH3_MMU_PORT_STRIDE 32 /* MMU Port number space per pipe */ 56 #define SOC_TH3_NUM_COS_QUEUES_PER_PIPE 276 /* Num UC Q's Per pipe 19*12 + 48 */ 57 #define SOC_TH3_NUM_CPU_QUEUES 48 /* CPU port has 48 MC Queues */ 58 #define SOC_TH3_NUM_GP_QUEUES 12 /*GPs includingLB/mgmt has 12 Queues*/ 59 #define SOC_TH3_MAX_DEV_PORTS_PER_PIPE 20 /*Max device/MMU ports per pipe*/ 60 #define SOC_TH3_LB_PORT_LOCAL_PHY_NUM 33 /*Local phy port number for LB port*/ 61 #define SOC_TH3_LB_PORT_LOCAL_DEV_NUM 19 /*Local dev port number for LB port*/ 62 #define SOC_TH3_MGMT_PORT_LOCAL_PHY_NUM 32 /*Local phy port number for Mgmt port*/ 63 #define SOC_TH3_MGMT_PORT_LOCAL_DEV_NUM 18 /*Local dev port number for Mgmt port*/ 64 #define SOC_TH3_COS_MAX 12 /*Max number of cos*/ 65 66 /* Device port 67 * 32 General device port + 1 CPU/Mng + 1 Loopback*/ 68 #define _TH3_GDEV_PORTS_PER_PIPE 18 69 #define _TH3_DEV_PORTS_PER_PIPE (_TH3_GDEV_PORTS_PER_PIPE + 2) 70 #define _TH3_DEV_PORTS_PER_DEV \ 71 (_TH3_DEV_PORTS_PER_PIPE * _TH3_PIPES_PER_DEV) 72 73 /* L2 learn cache defaults. Refer to L2_LEARN_COPY_CACHE_CTRL's fields for range 74 * of values that can be defined, and the meaning of 1 bit fields which will be 75 * programmed by values below 76 */ 77 /* Default cache fill level is set to 50%; may be changed after testing 78 * determines a more accurate value 79 */ 80 #define SOC_TH3_LRN_CACHE_THRESHOLD_DEFAULT 8 81 /* No clear-on-read of cache entries by default */ 82 #define SOC_TH3_LRN_CACHE_CLR_ON_RD_DEFAULT 0 83 /* Interrupt only if cache fill level exceeds threshold value (0) */ 84 #define SOC_TH3_LRN_CACHE_INTR_CTL_DEFAULT 0 85 /* Default priority of learn thread */ 86 #define SOC_TH3_LRN_THREAD_PRI_DEFAULT 50 87 88 #define SOC_TH3_MAC_IS_MCAST(_mac_) (_mac_[0] & 0x1) 89 90 /* Beginning interrupt number for low pri interrupts */ 91 #define TH3_LP_INTR_START_NUM 128 92 93 /* Bits 8-15 */ 94 #define SOC_TH3_L2_LEARN_CACHE_INTR_MASK 0x0000FF00 95 /* Bits 1,4-20 */ 96 #define SOC_TH3_SER_REG0_INTR_MASK 0x001FFFF3 97 /* Bits 16-31 */ 98 #define SOC_TH3_SER_REG1_INTR_MASK 0xFFFF0000 99 /* Bits 0-31 */ 100 #define SOC_TH3_SER_REG2_INTR_MASK 0xFFFFFFFF 101 /* Bits 0-16 */ 102 #define SOC_TH3_SER_REG3_INTR_MASK 0x0001FFFF 103 104 extern uint32 _soc_mem_entry_reset_value[1]; 105 106 extern int 107 soc_th3_check_scrub_info(int unit, soc_mem_t mem, int blk, int copyno, 108 int *num_inst_to_scrub, int *acc_type_list); 109 extern int soc_tomahawk3_clear_mmu_counters(int unit); 110 extern int soc_tomahawk3_init_mmu_memory(int unit); 111 extern int soc_th3_mmu_mem_blk_remap(soc_mem_t mem, uint32 *block); 112 extern int soc_th3_tcam_engine_enable(int unit, int enable); 113 extern int 114 soc_tomahawk3_parity_bit_enable(int unit, soc_reg_t enreg, 115 soc_mem_t enmem, soc_field_t enfld, 116 int enfld_position, int enable); 117 extern int soc_tomahawk3_ser_enable_parity_table_all(int unit, int enable); 118 extern int soc_th3_mem_parity_control(int unit, soc_mem_t mem, int copyno, 119 int en, int en_1b); 120 extern int soc_th3_ser_reg_field32_modify(int unit, soc_reg_t reg, 121 soc_port_t port, soc_field_t field, 122 uint32 value, int index, 123 int mmu_base_index); 124 extern int soc_th3_ser_test_skip_by_at(int unit, soc_mem_t mem, soc_acc_type_t at); 125 extern int soc_th3_ser_pipe_skip(int unit, soc_pipe_select_t pipe); 126 #ifdef BCM_CMICX_SUPPORT 127 extern void soc_th3_ser_intr_handler(int unit,uint32 cmic_val,int reg_num); 128 #endif 129 extern int 130 soc_th3_lp_to_fv_index_remap(int unit, soc_mem_t mem, int *rpt_index); 131 132 extern int 133 soc_th3_scan_idb_mem_ecc_status(int unit); 134 135 extern int soc_th3_check_scrub_skip(int unit, soc_mem_t mem, 136 int check_hw_global_mode); 137 extern int soc_th3_mem_is_eligible_for_scan(int unit, soc_mem_t mem); 138 extern void soc_th3_mem_scan_info_get(int unit, soc_mem_t mem, int block, 139 int *num_pipe, int *ser_flag); 140 extern int soc_th3_check_cache_skip(int unit, soc_mem_t mem); 141 extern int soc_th3_check_hw_global_mode(int unit, soc_mem_t mem, int *mem_mode); 142 extern int 143 soc_th3_ifp_tcam_dma_read(int unit, soc_mem_t mem, int blk, uint32 *table, 144 int en_per_pipe_read); 145 146 #if defined(SER_TR_TEST_SUPPORT) 147 extern int ser_test_TH3_mem_index_remap(int unit, ser_test_data_t *test_data, 148 int *mem_has_ecc); 149 #endif /*defined(SER_TR_TEST_SUPPORT*/ 150 151 extern int soc_th3_mem_index_invalid(int unit, soc_mem_t mem, int index, 152 uint8 dual_mode, soc_mem_t in_mem, 153 int in_pipe); 154 155 extern int soc_th3_mem_is_dual_mode(int unit, soc_mem_t mem, 156 soc_mem_t *base_mem, int *pipe); 157 extern int soc_th3_ifp_tcam_range_dma_read(int unit, soc_mem_t mem, int blk, 158 int start_addr, uint32 num_entry, uint32 *table); 159 extern int soc_th3_dual_tcam_index_valid(int unit, soc_mem_t mem, int index); 160 extern int 161 soc_tomahawk3_show_ring_osc(int unit); 162 163 extern int 164 soc_th3_ifp_slice_mode_hw_get(int unit, int pipe, int slice_num, int *slice_type, 165 int *slice_enabled); 166 extern int 167 soc_th3_ifp_slice_mode_get(int unit, int pipe, int slice_num, int *slice_type, 168 int *slice_enabled); 169 extern int 170 soc_th3_mmu_non_ser_intr_handler(int unit, soc_block_t blocktype, 171 int mmu_base_index, 172 uint32 rval_intr_status_reg); 173 extern int soc_th3_mmu_get_shared_size(int unit, int *thd_shared); 174 extern int soc_th3_mmu_config_shared_buf_recalc(int unit, int res, int ing_shd, 175 int egr_db_shd, int egr_qe_shd, 176 int flags); 177 extern int soc_th3_mmu_config_res_limits_update(int unit, int* delta, 178 int pool, int post_update); 179 extern int soc_th3_cal_egress_rsvd_limit(int unit, int* total_egr_rsvd_limit); 180 extern int soc_th3_mmu_config_flex_thresholds(int unit, int port, int shared_limit); 181 extern int _soc_th3_mmu_config_shared_limit_chk_set(int unit, 182 soc_reg_t reg, soc_mem_t mem, soc_field_t field, int index, 183 int itm, uint32 val, int decrease, int chk_zero); 184 185 186 extern soc_functions_t soc_tomahawk3_drv_funs; 187 extern int soc_tomahawk3_tcam_ser_init(int unit); 188 extern int soc_tomahawk3_ser_enable_all(int unit, int enable); 189 extern void soc_tomahawk3_ser_fail(int unit); 190 extern void soc_tomahawk3_ser_error(void *unit_vp, void *d1, void *d2, 191 void *d3, void *d4); 192 extern int soc_tomahawk3_mem_ser_control(int unit, soc_mem_t mem, 193 int copyno, int enable); 194 extern int soc_tomahawk3_mem_cpu_write_control(int unit, soc_mem_t mem, int copyno, 195 int enable, int *orig_enable); 196 extern int soc_tomahawk3_reg_cpu_write_control(int unit, int enable); 197 extern int soc_tomahawk3_ser_mem_clear(int unit, soc_mem_t mem); 198 extern void soc_tomahawk3_ser_register(int unit); 199 extern int soc_tomahawk3_process_ser_fifo(int unit, soc_block_t blk, int pipe, 200 char *prefix_str, int l2_mgmt_ser_fifo); 201 extern int soc_tomahawk3_alpm_scrub(int unit); 202 extern int soc_tomahawk3_mem_config(int unit); 203 extern int soc_tomahawk3_port_config_init(int unit, uint16 dev_id); 204 extern int soc_tomahawk3_chip_reset(int unit); 205 extern int soc_tomahawk3_port_reset(int unit); 206 extern int soc_tomahawk3_mem_basetype_get(int unit, soc_mem_t mem); 207 extern int _soc_th3_ports_per_pm_get(int unit, int pm_id); 208 extern uint32 _soc_th3_piped_mem_index(int unit, soc_port_t port, 209 soc_mem_t mem, int arr_off); 210 211 extern int soc_th3_l2_age_start(int unit, int interval); 212 extern int soc_th3_l2_age_stop(int unit); 213 214 /* Counter */ 215 extern int soc_counter_tomahawk3_obm_drop_to_phy_port(int unit,int pipe, 216 soc_reg_t reg, int obm_port); 217 extern int soc_counter_tomahawk3_status_enable(int unit, int enable); 218 extern int soc_counter_tomahawk3_non_dma_init(int unit, int nports, 219 int non_dma_start_index, 220 int *non_dma_entries); 221 extern int soc_counter_tomahawk3_eviction_enable(int unit, int enable); 222 extern void soc_counter_tomahawk3_eviction_flags_update(int unit, 223 uint32 flags, 224 int enable); 225 226 227 extern soc_error_t 228 soc_th3_granular_speed_get(int unit, soc_port_t port, int *speed); 229 230 #define TH3_FLEXPORT_SPEED_SET_NUM_LANES -1 231 typedef struct soc_th3_port_lanes_s { 232 int port_base; /* Base port number */ 233 int lanes; /* New number of lanes */ 234 int cur_lanes; /* Current number of lanes */ 235 int mode; /* New mode */ 236 int cur_mode; /* Current mode */ 237 int class; /* Speed class for new group */ 238 int cur_class; /* Speed class for current group */ 239 int idb_group; /* New IDB oversub group number */ 240 int cur_idb_group; /* Current IDB oversub group number */ 241 int idb_slots[4]; /* New IDB oversub group slot number */ 242 int cur_idb_slots[4]; /* Current IDB oversub group slot number */ 243 int cur_idb_empty; /* Current IDB oversub group become empty after flex */ 244 int mmu_group; /* New MMU oversub group number */ 245 int cur_mmu_group; /* Current MMU oversub group number */ 246 int mmu_slots[4]; /* New MMU oversub group slot number */ 247 int cur_mmu_slots[4]; /* Current MMU oversub group slot number */ 248 int cur_mmu_empty; /* Current MMU oversub group become empty after flex */ 249 int bindex; /* Base port subport index */ 250 int oversub; /* Oversub status for the ports */ 251 int phy_ports_len; /* Length of valid entries in phy_ports array */ 252 int phy_ports[3]; /* Array of added/removed physical port number */ 253 int speed; /* Port speed to be used during speed set */ 254 } soc_th3_port_lanes_t; 255 256 extern int soc_tomahawk3_port_speed_update(int unit, soc_port_t port, int speed); 257 258 extern int soc_th3_port_hg_speed_get(int unit, soc_port_t port, int *speed); 259 260 extern soc_error_t 261 soc_th3_subsidiary_ports_get(int unit, soc_port_t port, soc_pbmp_t *pbmp); 262 263 extern soc_error_t 264 soc_th3_flexport_recover(int unit, soc_port_t port); 265 266 extern soc_error_t 267 soc_th3_port_speed_supported(int unit, soc_port_t port, int speed); 268 extern soc_error_t 269 soc_th3_speed_set_init_ctrl(int unit, soc_th_port_lanes_t *lanes_ctrl); 270 271 typedef int (*_soc_th3_bst_hw_cb)(int unit); 272 extern int soc_th3_set_bst_callback(int unit, _soc_th3_bst_hw_cb cb); 273 extern int soc_th3_process_mmu_bst(int unit, int itm, soc_field_t field); 274 275 extern int 276 soc_th3_port_oversub_ratio_get( 277 int unit, 278 soc_port_t port, 279 int* const ratio); 280 281 extern void soc_nanosync_intr(void *unit_vp, void *d1, void *d2, 282 void *d3, void *d4); 283 284 #define SOC_TH3_MMU_PORT(u, p) _soc_th3_mmu_port((u),(p)) 285 #define SOC_TH3_MMU_PIPED_MEM_INDEX(u,p,m,off) \ 286 _soc_th3_piped_mem_index((u),(p),(m),(off)) 287 288 /* Port Block Base Port is the first physical port of each PM: 1, 9, 17, etc */ 289 #define SOC_TH3_PORT_BLOCK_BASE_PORT(port) \ 290 (1 + ((SOC_INFO(unit).port_l2p_mapping[port] - 1) & ~0x7)); 291 292 #define SOC_TH3_MMU_LOCAL_PORT(u,p) soc_th3_mmu_local_port_num((u),(p)) 293 #define SOC_TH3_MMU_CHIP_PORT(u,p) soc_th3_mmu_chip_port_num((u),(p)) 294 #define SOC_TH3_MMU_LOSSLESS_DEFAULT_DISABLE 0 295 296 enum soc_th3_port_ratio_e { 297 SOC_TH3_PORT_RATIO_SINGLE, 298 SOC_TH3_PORT_RATIO_DUAL_1_1, 299 SOC_TH3_PORT_RATIO_DUAL_2_1, 300 SOC_TH3_PORT_RATIO_DUAL_1_2, 301 SOC_TH3_PORT_RATIO_TRI_023_2_1_1, 302 SOC_TH3_PORT_RATIO_TRI_012_1_1_2, 303 SOC_TH3_PORT_RATIO_QUAD, 304 SOC_TH3_PORT_RATIO_COUNT 305 }; 306 307 enum soc_th3_port_mode_e { 308 /* WARNING: values given match hardware register; do not modify */ 309 soc_th3_PORT_MODE_QUAD = 0, 310 soc_th3_PORT_MODE_TRI_012 = 1, 311 soc_th3_PORT_MODE_TRI_023 = 2, 312 soc_th3_PORT_MODE_DUAL = 3, 313 soc_th3_PORT_MODE_SINGLE = 4 314 }; 315 316 enum TH3_l2_hash_key_type_e { 317 /* WARNING: values given match hardware register; do not modify */ 318 TH3_L2_HASH_KEY_TYPE_BRIDGE = 0, 319 TH3_L2_HASH_KEY_TYPE_SINGLE_CROSS_CONNECT = 1, 320 TH3_L2_HASH_KEY_TYPE_COUNT 321 }; 322 323 enum TH3_l3_hash_key_type_e { 324 /* WARNING: values given match hardware register; do not modify */ 325 TH3_L3_HASH_KEY_TYPE_V4UC = 0, 326 TH3_L3_HASH_KEY_TYPE_V6UC = 2, 327 TH3_L3_HASH_KEY_TYPE_V4MC = 4, 328 TH3_L3_HASH_KEY_TYPE_V6MC = 5, 329 TH3_L3_HASH_KEY_TYPE_COUNT 330 }; 331 332 enum TH3_tunnel_hash_key_type_e { 333 /* WARNING: values given match hardware register; do not modify */ 334 TH3_TUNNEL_HASH_KEY_TYPE_MPLS = 0, 335 TH3_TUNNEL_HASH_KEY_TYPE_V4 = 1, 336 TH3_TUNNEL_HASH_KEY_TYPE_V6 = 2, 337 TH3_TUNNEL_HASH_KEY_TYPE_COUNT 338 }; 339 340 enum TH3_fpem_hash_key_type_e { 341 /* WARNING: values given match hardware register; do not modify */ 342 TH3_FPEM_HASH_KEY_TYPE_128B = 0, 343 TH3_FPEM_HASH_KEY_TYPE_160B = 1, 344 TH3_FPEM_HASH_KEY_TYPE_320B = 2, 345 TH3_FPEM_HASH_KEY_TYPE_COUNT 346 }; 347 348 enum TH3_mpls_hash_key_type_e { 349 /* WARNING: values given match hardware register; do not modify */ 350 TH3_MPLS_HASH_KEY_TYPE_MPLS = 0, 351 TH3_MPLS_HASH_KEY_TYPE_COUNT 352 }; 353 354 /* Maximum Flex Key Width for hash table in TH3 */ 355 #define SOC_TH3_L2_ENTRY_MAX_KEY_WIDTH (64) 356 #define SOC_TH3_EXACT_MATCH_MAX_KEY_WIDTH (322) 357 #define SOC_TH3_L3_TUNNEL_MAX_KEY_WIDTH (311) 358 #define SOC_TH3_L3_MPLS_MAX_KEY_WIDTH (32) 359 #define SOC_TH3_L3_MAX_KEY_WIDTH (288) 360 361 extern int soc_tomahawk3_hash_init(int unit); 362 extern int soc_tomahawk3_hash_bank_count_get(int unit, soc_mem_t mem, 363 int *num_banks); 364 extern int soc_tomahawk3_hash_bank_phy_bitmap_get(int unit, soc_mem_t mem, 365 uint32 *bitmap); 366 extern int soc_tomahawk3_hash_bank_number_get(int unit, soc_mem_t mem, 367 int seq_num, int *bank_num); 368 extern int soc_tomahawk3_hash_seq_number_get(int unit, soc_mem_t mem, 369 int bank_num, int *seq_num); 370 extern int soc_tomahawk3_hash_bank_info_get(int unit, soc_mem_t mem, 371 int bank, 372 int *entries_per_bank, 373 int *entries_per_row, 374 int *entries_per_bucket, 375 int *bank_base, 376 int *bucket_offset); 377 extern int soc_tomahawk3_hash_bucket_get(int unit, int mem, int bank, 378 uint32 *entry, uint32 *bucket); 379 extern int soc_tomahawk3_hash_index_get(int unit, int mem, int bank, int bucket); 380 extern int soc_tomahawk3_hash_offset_get(int unit, soc_mem_t mem, int bank, 381 int *hash_offset, int *use_lsb); 382 extern int soc_tomahawk3_hash_offset_set(int unit, soc_mem_t mem, int bank, 383 int hash_offset, int use_lsb); 384 extern uint32 soc_tomahawk3_l2x_hash(int unit, int bank, int hash_offset, 385 int use_lsb, int key_nbits, void *base_entry, 386 uint8 *key1, uint8 *key2); 387 extern int soc_tomahawk3_l2x_base_entry_to_key(int unit, int bank, uint32 *entry, 388 uint8 *key); 389 extern uint32 soc_tomahawk3_l2x_entry_hash(int unit, int bank, int hash_offset, 390 int use_lsb, uint32 *entry); 391 extern uint32 soc_tomahawk3_l2x_bank_entry_hash(int unit, int bank, uint32 *entry); 392 extern uint32 soc_tomahawk3_l3x_hash(int unit, int bank, int hash_offset, int use_lsb, 393 int key_nbits, void *base_entry, uint8 *key1, uint8 *key2); 394 extern int soc_tomahawk3_l3x_base_entry_to_key(int unit, int bank, uint32 *entry, 395 uint8 *key); 396 extern uint32 soc_tomahawk3_l3x_entry_hash(int unit, int bank, int hash_offset, 397 int use_lsb, uint32 *entry); 398 extern uint32 soc_tomahawk3_l3x_bank_entry_hash(int unit, int bank, uint32 *entry); 399 extern int soc_tomahawk3_hash_l3_init(int unit); 400 extern uint32 soc_tomahawk3_exact_match_hash(int unit, int bank, int hash_offset, 401 int use_lsb, int key_nbits, 402 void *base_entry, uint8 *key1, 403 uint8 *key2); 404 extern int soc_tomahawk3_exact_match_base_entry_to_key(int unit, int bank, 405 uint32 *entry, 406 uint8 *key); 407 extern uint32 soc_tomahawk3_exact_match_entry_hash(int unit, int bank, 408 int hash_offset, int use_lsb, 409 uint32 *entry); 410 extern uint32 soc_tomahawk3_exact_match_bank_entry_hash(int unit, int bank, 411 uint32 *entry); 412 extern uint32 soc_tomahawk3_mpls_hash(int unit, int bank, int hash_offset, 413 int use_lsb, int key_nbits, void *base_entry, 414 uint8 *key1, uint8 *key2); 415 extern int soc_tomahawk3_mpls_base_entry_to_key(int unit, int bank, void *entry, 416 uint8 *key); 417 extern uint32 soc_tomahawk3_mpls_entry_hash(int unit, int bank, int hash_offset, 418 int use_lsb, uint32 *entry); 419 extern uint32 soc_tomahawk3_mpls_bank_entry_hash(int unit, int bank, uint32 *entry); 420 extern uint32 soc_tomahawk3_vlan_xlate_hash(int unit, soc_mem_t mem, int bank, int hash_offset, 421 int use_lsb, int key_nbits, void *base_entry, 422 uint8 *key1, uint8 *key2); 423 extern int soc_tomahawk3_vlan_xlate_base_entry_to_key(int unit, soc_mem_t mem, int bank, 424 void *entry, uint8 *key); 425 extern uint32 soc_tomahawk3_vlan_xlate_entry_hash(int unit, soc_mem_t mem, int bank, int hash_offset, 426 int use_lsb, uint32 *entry); 427 extern uint32 soc_tomahawk3_vlan_xlate_bank_entry_hash(int unit, soc_mem_t mem, int bank, 428 uint32 *entry); 429 extern uint32 soc_tomahawk3_egr_vlan_xlate_hash(int unit, soc_mem_t mem, int bank, int hash_offset, 430 int use_lsb, int key_nbits, void *base_entry, 431 uint8 *key1, uint8 *key2); 432 extern int soc_tomahawk3_egr_vlan_xlate_base_entry_to_key(int unit, soc_mem_t mem, int bank, 433 void *entry, uint8 *key); 434 extern uint32 soc_tomahawk3_egr_vlan_xlate_entry_hash(int unit, soc_mem_t mem, int bank, 435 int hash_offset, int use_lsb, uint32 *entry); 436 extern uint32 soc_tomahawk3_egr_vlan_xlate_bank_entry_hash(int unit, soc_mem_t mem, int bank, 437 uint32 *entry); 438 extern uint32 soc_tomahawk3_ing_vp_vlan_member_hash(int unit, int bank, int hash_offset, 439 int use_lsb, int key_nbits, void *base_entry, 440 uint8 *key1, uint8 *key2); 441 extern int soc_tomahawk3_ing_vp_vlan_member_base_entry_to_key(int unit, int bank, 442 void *entry, 443 uint8 *key); 444 extern uint32 soc_tomahawk3_ing_vp_vlan_member_entry_hash(int unit, int bank, int hash_offset, 445 int use_lsb, uint32 *entry); 446 extern uint32 soc_tomahawk3_egr_vp_vlan_member_hash(int unit, int bank, int hash_offset, 447 int use_lsb, int key_nbits, void *base_entry, 448 uint8 *key1, uint8 *key2); 449 extern int soc_tomahawk3_egr_vp_vlan_member_base_entry_to_key(int unit, int bank, 450 void *entry, 451 uint8 *key); 452 extern uint32 soc_tomahawk3_egr_vp_vlan_member_entry_hash(int unit, int bank, int hash_offset, 453 int use_lsb, uint32 *entry); 454 extern uint32 soc_tomahawk3_ing_dnat_address_type_hash(int unit, int bank, int hash_offset, 455 int use_lsb, int key_nbits, 456 void *base_entry, uint8 *key1, uint8 *key2); 457 extern int soc_tomahawk3_ing_dnat_address_type_base_entry_to_key(int unit, 458 int bank, 459 void *entry, 460 uint8 *key); 461 extern uint32 soc_tomahawk3_ing_dnat_address_type_entry_hash(int unit, int bank, int hash_offset, 462 int use_lsb, uint32 *entry); 463 extern uint32 soc_tomahawk3_tunnel_hash(int unit, int bank, int hash_offset, int use_lsb, 464 int key_nbits, void *base_entry, uint8 *key1, uint8 *key2); 465 466 extern int soc_tomahawk3_tunnel_base_entry_to_key(int unit, 467 int bank, 468 uint32 *entry, 469 uint8 *key); 470 471 extern uint32 soc_tomahawk3_tunnel_entry_hash(int unit, int bank, int hash_offset, int use_lsb, 472 uint32 *entry); 473 474 extern uint32 soc_tomahawk3_tunnel_bank_entry_hash(int unit, int bank, uint32 *entry); 475 476 extern int soc_tomahawk3_hash_mem_status_get(int unit, soc_mem_t mem, void* entry, uint32 *v); 477 extern int soc_tomahawk3_shared_hash_mem_bucket_read(int unit, int ent, int entry_width, int *width, 478 soc_mem_t base_mem, soc_mem_t *mem, void *bkt_entry, void *entry); 479 480 /* SCB */ 481 extern int soc_tomahawk3_scb_init(int unit); 482 483 /* WRED */ 484 extern int soc_tomahawk3_wred_init(int unit); 485 486 /* Read Launcher */ 487 extern int soc_tomahawk3_rl_init(int unit); 488 489 /* MMU interrupts Enable */ 490 extern int soc_th3_mmu_enable_non_func_intr(int unit); 491 492 /* MMU per-block non-func interrupt handlers */ 493 extern int soc_th3_process_itm_cfap_int(int unit, int itm, soc_field_t 494 itm_intr_field); 495 extern int soc_th3_process_itm_thdi_int(int unit, int itm, soc_field_t 496 itm_intr_field); 497 extern int soc_th3_process_itm_thdo_int(int unit, int itm, soc_field_t 498 itm_intr_field); 499 extern int soc_th3_process_itm_thdr_int(int unit, int itm, soc_field_t 500 itm_intr_field); 501 extern int soc_th3_process_itm_crb_int(int unit, int itm, soc_field_t 502 itm_intr_field); 503 extern int soc_th3_process_itm_rqe_int(int unit, int itm, soc_field_t 504 itm_intr_field); 505 506 extern int soc_th3_process_eb_ebctm_int(int unit, int pipe, soc_field_t 507 eb_intr_field); 508 extern int soc_th3_process_eb_ebcfp_int(int unit, int pipe, soc_field_t 509 eb_intr_field); 510 extern int soc_th3_process_eb_mtro_int(int unit, int pipe, soc_field_t 511 eb_intr_field); 512 513 514 /* Special port number used by H/W */ 515 #define _soc_th3_TDM_OVERSUB_TOKEN 0x22 516 #define _soc_th3_TDM_NULL_TOKEN 0x23 517 #define _soc_th3_TDM_IDL1_TOKEN 0x24 518 #define _soc_th3_TDM_IDL2_TOKEN 0x25 519 #define _soc_th3_TDM_UNUSED_TOKEN 0x3f 520 521 /* scheduler internal data structure */ 522 #define SOC_TH3_MAX_NUM_PORTS 160 523 #define SOC_TH3_MAX_NUM_SCHED_PROFILE 8 524 #define TH3_MMU_LB_MCQ_OFFSET 216 525 #define TH3_MMU_MGMT_Q_OFFSET 228 526 #define TH3_MMU_CPU_MCQ_OFFSET 228 527 528 /* Added for Queue scheduler mapping */ 529 typedef struct _soc_mmu_cfg_scheduler_profile_s 530 { 531 int num_unicast_queue[SOC_TH3_COS_MAX]; 532 int num_multicast_queue[SOC_TH3_COS_MAX]; 533 int strict_priority[SOC_TH3_COS_MAX]; 534 int flow_control_only_unicast[SOC_TH3_COS_MAX]; 535 int valid; 536 } _soc_mmu_cfg_scheduler_profile_t; 537 538 /* Fixed attributes for PG headroom calculation */ 539 #define SOC_TH3_IPG_SIZE 20 540 #define SOC_TH3_PFC_FRAME_SIZE 64 541 542 543 extern int _soc_th3_get_num_ucq(int unit); 544 extern int _soc_th3_get_num_mcq(int unit); 545 extern int soc_th3_chip_queue_num_get(int unit, soc_port_t port, int qid, int type, 546 int *hw_index); 547 extern _soc_mmu_cfg_scheduler_profile_t* soc_mmu_cfg_scheduler_profile_alloc(int unit); 548 extern void soc_mmu_cfg_scheduler_profile_free(int unit, _soc_mmu_cfg_scheduler_profile_t *cfg); 549 extern int _soc_mmu_cfg_scheduler_profile_read(int unit, _soc_mmu_cfg_scheduler_profile_t *sched_profile, 550 int *scheduler_port_profile_map); 551 extern int _soc_mmu_tomahawk3_scheduler_profile_reset(int unit, 552 _soc_mmu_cfg_scheduler_profile_t *sched_profile); 553 extern int _soc_mmu_tomahawk3_scheduler_profile_config_check(int unit, int idx, 554 _soc_mmu_cfg_scheduler_profile_t *sched_profile); 555 extern int _soc_mmu_tomahawk3_scheduler_profile_check(int unit, 556 _soc_mmu_cfg_scheduler_profile_t *sched_profile); 557 extern int soc_tomahawk3_cosq_port_info_init(int unit, int port_num); 558 559 560 extern int soc_tomahawk3_scheduler_init(int unit); 561 extern int soc_tomahawk3_sched_update_init(int unit, int profile, int *L0, int *schedq, 562 int *mmuq, int *cos, int *strict_priority, int* fc_is_us_only); 563 extern int 564 soc_profile_port_list_get(int unit, int profile, int port_in_profile[]); 565 extern int 566 soc_cosq_sched_policy_init(int unit, int profile); 567 extern int soc_tomahawk3_schduler_hier_show(int unit, int port); 568 extern int soc_tomahawk3_sched_update_flex_per_port(int unit, int port, int profile, int *L0, int *schedq, 569 int *mmuq, int *cos); 570 extern int soc_tomahawk3_get_cos_for_mmu_queue(int unit, int profile, int mmuq); 571 572 extern int soc_tomahawk3_get_fc_only_uc_for_cos(int unit, int profile, int cos); 573 extern int soc_tomahawk3_get_sp_for_cos(int unit, int profile, int cos); 574 extern int soc_tomahawk3_get_sched_profile_max_cos(int unit, int profile); 575 576 /* Warmboot helper functions */ 577 extern int soc_tomahawk3_sched_update_reinit(int unit, int profile, int *L0, int *schedq, 578 int *mmuq, int *cos, int *strict_priority, int* fc_is_us_only); 579 extern int 580 soc_cosq_sched_policy_reinit(int unit, int profile); 581 extern int soc_tomahawk3_sched_profile_attach_reinit(int unit, soc_port_t port, int profile); 582 583 typedef enum { 584 SOC_TH3_SCHED_MODE_UNKNOWN = 0, 585 SOC_TH3_SCHED_MODE_STRICT, 586 SOC_TH3_SCHED_MODE_WRR, 587 SOC_TH3_SCHED_MODE_WERR 588 } soc_th3_sched_mode_e; 589 590 typedef enum { 591 SOC_TH3_NODE_LVL_ROOT = 0, 592 SOC_TH3_NODE_LVL_L0, 593 SOC_TH3_NODE_LVL_L1, 594 SOC_TH3_NODE_LVL_L2, 595 SOC_TH3_NODE_LVL_MAX 596 } soc_th3_node_lvl_e; 597 598 typedef struct soc_th3_cosq_node_s { 599 int level; 600 int in_use; 601 int fc_is_uc_only; 602 soc_th3_sched_mode_e sched_policy; 603 int weight; 604 int hw_index; 605 soc_cos_t cos; 606 struct soc_th3_cosq_node_s *parent; /*only one parent*/ 607 struct soc_th3_cosq_node_s *children[2]; /*child*/ 608 } soc_th3_cosq_node_t; 609 610 typedef struct soc_th3_cosq_cpu_node_s { 611 int level; 612 int in_use; 613 soc_th3_sched_mode_e sched_policy; 614 int weight; 615 int hw_index; 616 soc_cos_t cos; 617 struct soc_th3_cosq_cpu_node_s *parent; /*only one parent*/ 618 struct soc_th3_cosq_cpu_node_s *children[SOC_TH3_NUM_CPU_QUEUES]; /*child*/ 619 } soc_th3_cosq_cpu_node_t; 620 621 typedef struct soc_th3_cosq_port_info_s { 622 soc_th3_cosq_node_t L0[SOC_TH3_NUM_GP_QUEUES]; 623 soc_th3_cosq_node_t L1[SOC_TH3_NUM_GP_QUEUES]; 624 soc_th3_cosq_node_t mmuq[SOC_TH3_NUM_GP_QUEUES]; 625 } soc_th3_cosq_port_info_t; 626 627 typedef struct soc_th3_cosq_cpu_port_info_s { 628 soc_th3_cosq_cpu_node_t L0[SOC_TH3_NUM_GP_QUEUES]; 629 soc_th3_cosq_cpu_node_t L1[SOC_TH3_NUM_CPU_QUEUES]; 630 } soc_th3_cosq_cpu_port_info_t; 631 632 typedef struct soc_th3_mmu_info_s { 633 soc_th3_cosq_port_info_t th3_port_info[SOC_TH3_MAX_NUM_PORTS]; 634 soc_th3_cosq_cpu_port_info_t th3_cpu_port_info; 635 } soc_th3_mmu_info_t; 636 637 typedef struct soc_th3_sched_profile_info_s { 638 int mmuq[2]; 639 int strict_priority; 640 int cos; 641 int fc_is_uc_only; 642 } soc_th3_sched_profile_info_t; 643 644 extern soc_th3_mmu_info_t *th3_cosq_mmu_info[SOC_MAX_NUM_DEVICES]; 645 extern soc_th3_sched_profile_info_t th3_sched_profile_info[SOC_MAX_NUM_DEVICES] 646 [SOC_TH3_MAX_NUM_SCHED_PROFILE][SOC_TH3_NUM_GP_QUEUES]; 647 extern int L1_TO_L0_MAPPING[SOC_MAX_NUM_DEVICES][SOC_TH3_MAX_NUM_SCHED_PROFILE] 648 [SOC_TH3_NUM_GP_QUEUES]; 649 extern int L0_TO_L1_MAPPING_NUM[SOC_MAX_NUM_DEVICES][SOC_TH3_MAX_NUM_SCHED_PROFILE] 650 [SOC_TH3_NUM_GP_QUEUES]; 651 extern int L0_TO_COSQ_MAPPING[SOC_MAX_NUM_DEVICES][SOC_TH3_MAX_NUM_SCHED_PROFILE] 652 [SOC_TH3_NUM_GP_QUEUES]; 653 654 typedef enum { 655 _soc_th3_INDEX_STYLE_BUCKET, 656 _soc_th3_INDEX_STYLE_BUCKET_MODE, 657 _soc_th3_INDEX_STYLE_WRED, 658 _soc_th3_INDEX_STYLE_WRED_DROP_THRESH, 659 _soc_th3_INDEX_STYLE_SCHEDULER, 660 _soc_th3_INDEX_STYLE_PERQ_XMT, 661 _soc_th3_INDEX_STYLE_UCAST_DROP, 662 _soc_th3_INDEX_STYLE_UCAST_QUEUE, 663 _soc_th3_INDEX_STYLE_MCAST_QUEUE, 664 _soc_th3_INDEX_STYLE_EXT_UCAST_QUEUE, 665 _soc_th3_INDEX_STYLE_EGR_POOL, 666 _soc_th3_INDEX_STYLE_COUNT 667 } soc_th3_index_style_t; 668 669 typedef enum soc_th3_drop_limit_alpha_value_e { 670 SOC_TH3_COSQ_DROP_LIMIT_ALPHA_1_128, /* Use 1/128 as the alpha value for 671 dynamic threshold */ 672 SOC_TH3_COSQ_DROP_LIMIT_ALPHA_1_64, /* Use 1/64 as the alpha value for 673 dynamic threshold */ 674 SOC_TH3_COSQ_DROP_LIMIT_ALPHA_1_32, /* Use 1/32 as the alpha value for 675 dynamic threshold */ 676 SOC_TH3_COSQ_DROP_LIMIT_ALPHA_1_16, /* Use 1/16 as the alpha value for 677 dynamic threshold */ 678 SOC_TH3_COSQ_DROP_LIMIT_ALPHA_1_8, /* Use 1/8 as the alpha value for 679 dynamic threshold */ 680 SOC_TH3_COSQ_DROP_LIMIT_ALPHA_1_4, /* Use 1/4 as the alpha value for 681 dynamic threshold */ 682 SOC_TH3_COSQ_DROP_LIMIT_ALPHA_1_2, /* Use 1/2 as the alpha value for 683 dynamic threshold */ 684 SOC_TH3_COSQ_DROP_LIMIT_ALPHA_1, /* Use 1 as the alpha value for dynamic 685 threshold */ 686 SOC_TH3_COSQ_DROP_LIMIT_ALPHA_2, /* Use 2 as the alpha value for dynamic 687 threshold */ 688 SOC_TH3_COSQ_DROP_LIMIT_ALPHA_4, /* Use 4 as the alpha value for dynamic 689 threshold */ 690 SOC_TH3_COSQ_DROP_LIMIT_ALPHA_8, /* Use 8 as the alpha value for dynamic 691 threshold */ 692 SOC_TH3_COSQ_DROP_LIMIT_ALPHA_COUNT /* Must be the last entry! */ 693 } soc_th3_drop_limit_alpha_value_t; 694 695 #define _TH3_PORTS_PER_PBLK 8 696 #define _TH3_PBLKS_PER_PIPE 4 697 #define _TH3_PIPES_PER_DEV 8 698 699 #define _TH3_GPHY_PORTS_PER_PIPE \ 700 (_TH3_PORTS_PER_PBLK * _TH3_PBLKS_PER_PIPE) 701 #define _TH3_GPHY_PORTS_PER_DEV \ 702 (_TH3_GPHY_PORTS_PER_PIPE * _TH3_PIPES_PER_DEV) 703 #define _TH3_PHY_PORTS_PER_PIPE (_TH3_GPHY_PORTS_PER_PIPE + 2) 704 #define _TH3_ITMS_PER_DEV 2 705 706 #define _TH3_PBLKS_PER_DEV (_TH3_PBLKS_PER_PIPE * _TH3_PIPES_PER_DEV) 707 708 #define _TH3_PORTS_PER_PIPE (_TH3_PORTS_PER_PBLK * _TH3_PBLKS_PER_PIPE) 709 #define _TH3_PORTS_PER_DEV (_TH3_PORTS_PER_PIPE * _TH3_PIPES_PER_DEV) 710 #define _TH3_PHY_PORTS_PER_DEV \ 711 (_TH3_PHY_PORTS_PER_PIPE * _TH3_PIPES_PER_DEV) 712 713 /* MMU port */ 714 #define _TH3_MMU_PORTS_OFFSET_PER_PIPE 32 715 #define _TH3_MMU_PORTS_PER_DEV (32 * 8) 716 717 #define _TH3_SECTION_SIZE 32768 718 719 #define _TH3_MMU_MAX_PACKET_BYTES 9416 /* bytes */ 720 #define _TH3_MMU_PACKET_HEADER_BYTES 40 /* bytes */ 721 #define _TH3_MMU_JUMBO_FRAME_BYTES 9216 /* bytes */ 722 #define _TH3_MMU_DEFAULT_MTU_BYTES 1536 /* bytes */ 723 724 #define _TH3_MMU_PHYSICAL_CELLS_PER_ITM 139264 /* Total Physical cells per ITM */ 725 #define _TH3_MMU_TOTAL_CELLS_AVAIL_PER_ITM 134169 /* Total cells cells/ITM */ 726 #define _TH3_MMU_RSVD_CELLS_CFAP_PER_ITM 408 /* Reserved CFAP cells/ITM */ 727 #define SOC_TH3_MMU_MCQ_ENTRY_PER_ITM 13600 728 #define SOC_TH3_MMU_RQE_ENTRY_PER_ITM 2048 729 #define SOC_TH3_MMU_RQE_ENTRY_RSVD_PER_ITM 63 /* Reserved RQE QE per ITM */ 730 #define _TH3_MMU_TOTAL_CELLS_PER_ITM (_TH3_MMU_TOTAL_CELLS_AVAIL_PER_ITM - \ 731 SOC_TH3_MMU_RQE_ENTRY_PER_ITM) 732 733 734 #define _TH3_THDI_BUFFER_CELL_LIMIT_SP_MAX _TH3_MMU_TOTAL_CELLS_PER_ITM 735 #define _TH3_THDI_HDRM_BUFFER_CELL_LIMIT_HP_MAX _TH3_MMU_TOTAL_CELLS_PER_ITM 736 737 738 #define _TH3_MMU_BYTES_PER_CELL 254 /* bytes (1664 bits) */ 739 #define _TH3_MMU_NUM_PG 8 740 #define _TH3_MMU_NUM_POOL 4 741 #define _TH3_MMU_NUM_INT_PRI 16 742 #define _TH3_MMU_NUM_MAX_PROFILES 8 743 744 #define _TH3_A0_MMU_NUM_RQE_QUEUES 3 745 #define _TH3_A0_CPU_HI_RQE_Q_NUM 0 746 #define _TH3_A0_CPU_LO_RQE_Q_NUM 1 747 #define _TH3_A0_MIRR_RQE_Q_NUM 2 748 749 #define _TH3_MMU_NUM_RQE_QUEUES 9 750 #define _TH3_CPU_HI_RQE_Q_NUM 6 751 #define _TH3_CPU_LO_RQE_Q_NUM 7 752 #define _TH3_MIRR_RQE_Q_NUM 8 753 754 #define SOC_TH3_MMU_CFG_QGROUP_MAX 160 755 756 #define _TH3_MMU_JUMBO_PACKET_SIZE _MMU_CFG_MMU_BYTES_TO_CELLS(_TH3_MMU_JUMBO_FRAME_BYTES + \ 757 _TH3_MMU_PACKET_HEADER_BYTES, \ 758 _TH3_MMU_BYTES_PER_CELL) 759 760 #define SOC_TH3_NUM_UC_QUEUES_PER_PIPE 330 /* Num UC Q's Per pipe 33 * 10 */ 761 #define SOC_TH3_NUM_MC_QUEUES_PER_PIPE 378 /* Num MC Q's Per pipe (33 * 10) 762 + 48 CPU queues */ 763 #define SOC_TH3_MAX_PHY_PORTS_PER_PIPE 32 764 #define SOC_TH3_PHY_PORTS_PER_DEV \ 765 (SOC_TH3_MAX_PHY_PORTS_PER_PIPE * _TH3_PIPES_PER_DEV) 766 #define SOC_TH3_DEV_PORTS_PER_DEV \ 767 (SOC_TH3_MAX_DEV_PORTS_PER_PIPE * _TH3_PIPES_PER_DEV) 768 #define SOC_TH3_MMU_PORTS_PER_DEV \ 769 ( SOC_TH3_MAX_DEV_PORTS_PER_PIPE * _TH3_PIPES_PER_DEV) 770 771 #define _TH3_MMU_TOTAL_MCQ_ENTRY(unit) SOC_TH3_MMU_MCQ_ENTRY_PER_ITM 772 #define _TH3_MMU_TOTAL_RQE_ENTRY(unit) SOC_TH3_MMU_RQE_ENTRY_PER_ITM 773 774 /* Default values for thresholds */ 775 #define _TH3_CFAP_BANK_FULL_LIMIT 2044 776 #define _TH3_LAST_PKT_ACCEPT_MODE_DEFAULT 1 777 #define _TH3_LAST_PKT_ACCEPT_MODE_POOL_DEFAULT 15 778 #define _TH3_COLOR_AWARE_DEFAULT 0 779 #define _TH3_HDRM_LIMIT_DEFAULT 0 780 #define _TH3_SPID_OVERRIDE_ENABLE_DEFAULT 0 781 #define _TH3_SPAP_YELLOW_OFFSET_DEFAULT 0 782 #define _TH3_SPAP_RED_OFFSET_DEFAULT 0 783 #define _TH3_MC_Q_MODE_DEFAULT 2 784 #define _TH3_OUTPUT_PORT_EN_DEFAULT 1048575 785 #define _TH3_PAUSE_EN_DEFAULT 0 786 #define _TH3_SPID_DEFAULT 0 787 788 /*defines added for SDK-142748*/ 789 #define _TH3_MMU_SPARE_SRC_PORT 98 790 #define _TH3_MMU_SPARE_SRC_PORT_PIPE 4 791 #define _TH3_MMU_SPARE_DST_PORT 158 792 #define _TH3_IFP_COS_MAP_RSVD_PROF 3 793 794 #define soc_th3_STAT_ING_FLEX_POOL_MAX 20 795 796 #define _TH3_ARRAY_MIN(arr, len, bmp, min) \ 797 do { \ 798 int i; \ 799 min = 0x7fffffff; \ 800 if (arr) { \ 801 for (i = 0; i < len; i ++) { \ 802 if ((bmp & (1 << i)) && (arr[i] < min)) { \ 803 min = arr[i]; \ 804 } \ 805 } \ 806 } \ 807 } while (0) 808 809 /* TDM */ 810 #define _TH3_TDM_LENGTH 33 811 #define _TH3_OVS_HPIPE_COUNT_PER_PIPE 1 812 813 typedef struct _soc_tomahawk3_tdm_pblk_info_s { 814 int pblk_hpipe_num; /* half pipeline info */ 815 int pblk_cal_idx; /* index to 8 HPIPEx_PBLK_CALENDARr */ 816 } _soc_tomahawk3_tdm_pblk_info_t; 817 818 typedef struct _soc_tomahawk3_tdm_pipe_s { 819 int idb_tdm[_TH3_TDM_LENGTH]; 820 int mmu_tdm[_TH3_TDM_LENGTH]; 821 } _soc_tomahawk3_tdm_pipe_t; 822 823 typedef struct _soc_tomahawk3_tdm_s { 824 _soc_tomahawk3_tdm_pipe_t tdm_pipe[_TH3_PIPES_PER_DEV]; 825 _soc_tomahawk3_tdm_pblk_info_t pblk_info[_TH3_PHY_PORTS_PER_DEV]; 826 int port_ratio[_TH3_PBLKS_PER_DEV]; 827 int ovs_ratio_x1000[_TH3_PIPES_PER_DEV][_TH3_OVS_HPIPE_COUNT_PER_PIPE]; 828 } _soc_tomahawk3_tdm_t; 829 830 /* Oversub XON/XOFF Threshold */ 831 #define _TH3_XON_THRESHOLD_10G 4672 832 #define _TH3_XON_THRESHOLD_25G 4672 833 #define _TH3_XON_THRESHOLD_50G 4672 834 #define _TH3_XON_THRESHOLD_100G 11776 835 #define _TH3_XON_THRESHOLD_200G 24064 836 #define _TH3_XON_THRESHOLD_400G 48640 837 838 #define _TH3_XOFF_THRESHOLD_10G 5184 839 #define _TH3_XOFF_THRESHOLD_25G 5184 840 #define _TH3_XOFF_THRESHOLD_50G 5184 841 #define _TH3_XOFF_THRESHOLD_100G 12288 842 #define _TH3_XOFF_THRESHOLD_200G 24576 843 #define _TH3_XOFF_THRESHOLD_400G 49152 844 845 846 /*PG headroom*/ 847 #define _TH3_PG_HEADROOM_LINERATE_10G 167 848 #define _TH3_PG_HEADROOM_LINERATE_25G 256 849 #define _TH3_PG_HEADROOM_LINERATE_50G 360 850 #define _TH3_PG_HEADROOM_LINERATE_100G 580 851 #define _TH3_PG_HEADROOM_LINERATE_200G 1061 852 #define _TH3_PG_HEADROOM_LINERATE_400G 1962 853 854 #define _TH3_PG_HEADROOM_OVERSUB_10G \ 855 (_TH3_PG_HEADROOM_LINERATE_10G + CEIL(_TH3_XOFF_THRESHOLD_10G, 64)) 856 #define _TH3_PG_HEADROOM_OVERSUB_25G \ 857 (_TH3_PG_HEADROOM_LINERATE_25G + CEIL(_TH3_XOFF_THRESHOLD_25G, 64)) 858 #define _TH3_PG_HEADROOM_OVERSUB_50G \ 859 (_TH3_PG_HEADROOM_LINERATE_50G + CEIL(_TH3_XOFF_THRESHOLD_50G, 64)) 860 #define _TH3_PG_HEADROOM_OVERSUB_100G \ 861 (_TH3_PG_HEADROOM_LINERATE_100G + CEIL(_TH3_XOFF_THRESHOLD_100G, 64)) 862 #define _TH3_PG_HEADROOM_OVERSUB_200G \ 863 (_TH3_PG_HEADROOM_LINERATE_200G + CEIL(_TH3_XOFF_THRESHOLD_200G, 64)) 864 #define _TH3_PG_HEADROOM_OVERSUB_400G \ 865 (_TH3_PG_HEADROOM_LINERATE_400G + CEIL(_TH3_XOFF_THRESHOLD_400G, 64)) 866 867 /* Function to Retrieve IFP memory mode. */ 868 extern int 869 soc_th3_field_mem_mode_get(int unit, soc_mem_t mem, int *mode); 870 871 extern int 872 soc_th3_ser_mem_mode_get(int unit, soc_mem_t mem, int *mode); 873 874 extern int 875 soc_th3_cosq_sched_mode_set(int unit, soc_port_t port, int level, int index, 876 soc_th3_sched_mode_e mode, int weight, int mc); 877 extern int 878 soc_th3_cosq_sched_mode_get(int unit, soc_port_t port, int level, int index, 879 soc_th3_sched_mode_e *mode, int *weight, int mc); 880 extern int 881 soc_th3_cosq_cpu_parent_set(int unit, int child_index, int child_level, 882 int parent_index); 883 extern int 884 soc_th3_cosq_cpu_parent_get(int unit, int child_index, int child_level, 885 int *parent_index); 886 887 extern int 888 soc_th3_cosq_parent_get(int unit, int port, int child_index, int child_level, 889 int *parent_index); 890 extern int 891 soc_tomahawk3_mem_sram_info_get(int unit, soc_mem_t mem, int index, 892 _soc_ser_sram_info_t *sram_info); 893 894 #if defined(SER_TR_TEST_SUPPORT) 895 extern void soc_th3_ser_test_register(int unit); 896 #endif /*defined(SER_TR_TEST_SUPPORT*/ 897 898 extern int soc_tomahawk3_clear_all_port_data(int unit); 899 900 #define SOC_TH3_NUM_EL_VLAN_XLATE 4 901 902 #define SOC_TH3_NUM_EL_EGR_VLAN_XLATE 4 903 904 #define SOC_TH3_NUM_EL_ING_L3_NEXT_HOP 4 905 #define SOC_TH3_RAM_OFFSET_ING_L3_NEXT_HOP 8192 906 907 #define SOC_TH3_NUM_ENTRIES_L2_BANK 8192 908 #define SOC_TH3_NUM_ENTRIES_L3_BANK 16384 909 910 #define SOC_TH3_NUM_EL_SHARED 4 911 #define SOC_TH3_NUM_ENTRIES_XOR_BANK 2048 912 #define SOC_TH3_LP_ENTRIES_IN_XOR_BANK 2048 913 #define SOC_TH3_LP_ENTRIES_IN_UFT_BANK 8192 914 915 #define SOC_TH3_ALPM_MAX_BKTS(u) 8192 916 #define SOC_TH3_ALPM_BKT_MASK(u) 0x1FFF 917 #define SOC_TH3_ALPM_BKT_OFFFSET 2048 918 #define SOC_TH3_ALPM_MODE_BKT_MASK 0x38003 919 920 #define _soc_th3_L2_MGMT_INTR_MASK 0x2 921 #define _soc_th3_FUNC_INTR_MASK _soc_th3_L2_MGMT_INTR_MASK 922 923 extern int soc_th3_get_alpm_banks(int unit); 924 extern int soc_tomahawk3_alpm_mode_get(int unit); 925 926 extern void _soc_th3_lpm_view_set(int unit, int index, soc_mem_t view, int pair_lpm); 927 extern soc_mem_t _soc_th3_lpm_view_get(int unit, int index, int pair_lpm); 928 929 extern int 930 soc_tomahawk3_temperature_monitor_get(int unit, int temperature_max, 931 soc_switch_temperature_monitor_t *temperature_array, 932 int *temperature_count); 933 extern void 934 soc_tomahawk3_temperature_intr(void *unit_vp, void *d1, void *d2, 935 void *d3, void *d4); 936 extern void 937 soc_tomahawk3_process_func_intr(void *unit_vp, void *d1, void *d2, void *d3, void *d4); 938 939 #define _soc_th3_UNIT_VALIDATE(unit) \ 940 if ( !(((unit) >= 0) && ((unit) <= SOC_MAX_NUM_DEVICES)) ) \ 941 return SOC_E_UNIT; 942 943 #define OUT 944 #define IN_OUT 945 946 /* 947 ============================= 948 TH3 ASF (cut-thru forwarding) 949 ============================= 950 */ 951 /* ASF Modes */ 952 typedef enum soc_th3_asf_mode_e{ 953 SOC_TH3_ASF_MODE_SAF = 0, 954 SOC_TH3_ASF_MODE_CT = 1, 955 SOC_TH3_ASF_MODE_CFG_UPDATE = 2, 956 SOC_TH3_ASF_MODE_INIT = 3, 957 SOC_TH3_ASF_MODE_MAX = 4 958 } soc_th3_asf_mode_t; 959 960 int 961 soc_th3_asf_init(int unit); 962 963 int 964 soc_th3_asf_deinit(int unit); 965 966 int 967 soc_th3_port_asf_mode_get( 968 int unit, 969 soc_port_t port, 970 int port_speed, 971 soc_th3_asf_mode_t *mode); 972 973 int 974 soc_th3_port_asf_mode_set( 975 int unit, 976 soc_port_t port, 977 int port_speed, 978 soc_th3_asf_mode_t mode); 979 980 int 981 soc_th3_port_asf_detach(int unit, soc_port_t port); 982 983 int 984 soc_th3_port_asf_valid( 985 int unit, 986 soc_port_t port); 987 988 /* diag shell debug functions */ 989 int 990 soc_th3_asf_config_dump(int unit); 991 992 int 993 soc_th3_port_asf_show(int unit, soc_port_t port, int speed); 994 995 int 996 soc_th3_port_asf_config_dump( 997 int unit, 998 soc_port_t port, 999 int port_speed); 1000 1001 /* EDB config*/ 1002 int 1003 soc_th3_port_asf_xmit_start_count_set( 1004 int unit, 1005 soc_port_t port, 1006 int port_speed, 1007 soc_th3_asf_mode_t mode, 1008 uint8 extra_cells); 1009 1010 int 1011 soc_th3_port_asf_xmit_start_count_get( 1012 int unit, 1013 soc_port_t port, 1014 int sc, 1015 int dc, 1016 soc_th3_asf_mode_t mode, 1017 uint8* xmit_cnt); 1018 1019 #ifdef BCM_WARM_BOOT_SUPPORT 1020 /* TH3 ASF Warmboot functions */ 1021 extern int 1022 soc_th3_asf_wb_memsz_get( 1023 int unit, 1024 OUT uint32* const wb_mem_sz, 1025 uint16 scache_ver); 1026 1027 extern int 1028 soc_th3_asf_wb_sync( 1029 int unit, 1030 IN_OUT uint8* const wb_data); 1031 1032 extern int 1033 soc_th3_asf_wb_recover( 1034 int unit, 1035 uint8* const wb_data, 1036 uint16 scache_ver); 1037 #endif /* BCM_WARM_BOOT_SUPPORT */ 1038 1039 /* 1040 ========================== 1041 TH Switch Latency Bypass 1042 ========================== 1043 */ 1044 1045 /* resource type */ 1046 typedef enum { 1047 _soc_th3_REG = 0, 1048 _soc_th3_MEM = 1 1049 } soc_th3_resource_e; 1050 1051 /* protocol table configs */ 1052 typedef struct _soc_th3_latency_table_cfg_s { 1053 int l2_entries; 1054 int fixed_l2_entries; 1055 int shared_l2_banks; 1056 int l3_entries; 1057 int fixed_l3_entries; 1058 int shared_l3_banks; 1059 int fpem_entries; 1060 int shared_fpem_banks; 1061 int alpm_enable; 1062 int max_tcams; 1063 int tcam_depth; 1064 } soc_th3_latency_table_cfg_t; 1065 1066 1067 extern int 1068 soc_th3_latency_init(int unit); 1069 1070 extern int 1071 soc_th3_latency_deinit(int unit); 1072 1073 extern int 1074 soc_th3_latency_get( 1075 int unit, 1076 OUT int* const latency); 1077 1078 extern int 1079 soc_th3_latency_bypassed( 1080 int unit, 1081 soc_feature_t feature); 1082 1083 extern int 1084 soc_th3_latency_mem_avail( 1085 int unit, 1086 soc_mem_t mem); 1087 1088 extern int 1089 soc_th3_latency_reg_avail( 1090 int unit, 1091 soc_reg_t reg); 1092 1093 extern int 1094 soc_th3_latency_mem_filter(int unit); 1095 1096 extern int 1097 soc_th3_latency_reg_filter(int unit); 1098 1099 #ifdef BCM_WARM_BOOT_SUPPORT 1100 extern int 1101 soc_th3_latency_wb_memsz_get( 1102 int unit, 1103 OUT uint32* const wb_mem_sz, 1104 uint16 scache_ver); 1105 1106 extern int 1107 soc_th3_latency_wb_sync( 1108 int unit, 1109 IN_OUT uint8* const wb_data); 1110 1111 extern int 1112 soc_th3_latency_wb_recover( 1113 int unit, 1114 uint8* const wb_data, 1115 uint16 scache_ver); 1116 1117 extern int 1118 soc_th3_latency_wb_reinit(int unit, int level); 1119 #endif 1120 1121 extern int 1122 soc_th3_latency_show(int unit); 1123 1124 extern int 1125 soc_th3_latency_diag(int unit); 1126 1127 1128 #ifdef INCLUDE_AVS 1129 extern int soc_th3_avs_init(int unit); 1130 extern soc_error_t soc_th3_avs_vcore_get(int unit, uint32 *voltage); 1131 extern soc_error_t soc_th3_avs_vcore_set(int unit, uint32 voltage); 1132 extern soc_error_t soc_th3_avs_vcore_init(int unit); 1133 extern soc_error_t soc_th3_avs_vcore_deinit(int unit); 1134 #endif /* INCLUDE_AVS */ 1135 1136 #ifdef PORTMOD_SUPPORT 1137 extern int soc_th3_portctrl_pm_portmod_init(int unit); 1138 extern int soc_th3_portctrl_pm_portmod_deinit(int unit); 1139 extern int soc_th3_portctrl_pm_port_config_get(int unit, soc_port_t port, void *port_config_info); 1140 extern int soc_th3_portctrl_pm_port_phyaddr_get(int unit, soc_port_t port); 1141 extern int soc_th3_portctrl_pm_type_get(int unit, soc_port_t phy_port, int * pm_type); 1142 extern int soc_th3_portctrl_vco_soc_info_update(int unit); 1143 extern int soc_th3_portctrl_pm_vco_store_clear(int unit); 1144 extern int soc_th3_portctrl_pm_vco_store(int unit, int index, const void *pm_vco_info); 1145 extern int soc_th3_portctrl_pm_vco_fetch(int unit, int index, void *pm_vco_info); 1146 extern int soc_th3_portctrl_pm_vco_reconfigure(int unit); 1147 extern int soc_th3_portctrl_pm_is_active(int unit, int phy_port, int *is_active); 1148 1149 #endif 1150 1151 extern int soc_th3_port_schedule_tdm_init(int unit, 1152 soc_port_schedule_state_t *port_schedule_state); 1153 extern int soc_th3_soc_tdm_update(int unit, 1154 soc_port_schedule_state_t *port_schedule_state); 1155 extern int soc_th3_support_speeds(int unit, int lanes, uint32 *speed_mask); 1156 1157 #ifdef BCM_WARM_BOOT_SUPPORT 1158 extern int soc_th3_flexport_scache_allocate(int unit); 1159 extern int soc_th3_flexport_scache_sync(int unit); 1160 extern int soc_th3_flexport_scache_recovery(int unit); 1161 #endif /* BCM_WARM_BOOT_SUPPORT */ 1162 1163 extern void soc_th3_flexport_sw_dump(int unit); 1164 1165 extern int soc_th3_ifp_mem_write(int unit, soc_mem_t mem, int copyno, int index, 1166 void *entry_data); 1167 extern int soc_th3_ifp_mem_read(int unit, soc_mem_t mem, int copyno, int index, 1168 void *entry_data); 1169 /* 1170 ========================== 1171 TH3 TM Functions 1172 ========================== 1173 */ 1174 extern int soc_tomahawk3_num_cosq_init(int unit, int port); 1175 extern int soc_tomahawk3_port_pg_headroom_update(int unit, soc_port_t port); 1176 extern int soc_tomahawk3_cpu_tx_rqe_queues_for_flush(int unit, int itm); 1177 /* 1178 ========================== 1179 TH3 MMU SBus Functions 1180 ========================== 1181 */ 1182 extern int soc_tomahawk3_itm_base_index_check(int unit, int base_type, int itm, 1183 int base_index, char *msg); 1184 extern int soc_tomahawk3_mem_is_itm(int unit, soc_mem_t mem); 1185 extern int soc_tomahawk3_reg_is_itm(int unit, soc_reg_t reg); 1186 extern int soc_tomahawk3_itm_reg32_set(int unit, soc_reg_t reg, int itm, 1187 int base_index, int index, uint32 data); 1188 extern int soc_tomahawk3_itm_reg32_get(int unit, soc_reg_t reg, int itm, 1189 int base_index, int index, uint32 *data); 1190 extern int soc_tomahawk3_itm_reg_set(int unit, soc_reg_t reg, int itm, 1191 int base_index, int index, uint64 data); 1192 extern int soc_tomahawk3_itm_reg_get(int unit, soc_reg_t reg, int itm, 1193 int base_index, int index, uint64 *data); 1194 extern int soc_tomahawk3_eb_base_index_check(int unit, int base_type, int eb, 1195 int base_index, char *msg); 1196 extern int soc_tomahawk3_eb_reg32_set(int unit, soc_reg_t reg, int eb, 1197 int base_index, int index, uint32 data); 1198 extern int soc_tomahawk3_eb_reg32_get(int unit, soc_reg_t reg, int eb, 1199 int base_index, int index, uint32 *data); 1200 extern int soc_tomahawk3_eb_reg_set(int unit, soc_reg_t reg, int eb, 1201 int base_index, int index, uint64 data); 1202 extern int soc_tomahawk3_eb_reg_get(int unit, soc_reg_t reg, int eb, 1203 int base_index, int index, uint64 *data); 1204 extern int soc_tomahawk3_itm_mem_write(int unit, soc_mem_t mem, int itm, 1205 int base_index, int copyno, int offset_in_section, void *entry_data); 1206 extern int soc_tomahawk3_itm_mem_read(int unit, soc_mem_t mem, int itm, 1207 int base_index, int copyno, int offset_in_section, void *entry_data); 1208 extern int 1209 soc_tomahawk3_itm_mem_read_range(int unit, soc_mem_t mem, int itm, int base_index, 1210 int copyno, int idx_min, int idx_max, void *entry_data); 1211 extern int soc_tomahawk3_eb_mem_write(int unit, soc_mem_t mem, int eb, 1212 int base_index, int copyno, int offset_in_section, void *entry_data); 1213 extern int soc_tomahawk3_eb_mem_read(int unit, soc_mem_t mem, int eb, 1214 int base_index, int copyno, int offset_in_section, void *entry_data); 1215 1216 /* 1217 ========================== 1218 TH3 TM Init Misc Functions 1219 ========================== 1220 */ 1221 extern int soc_tomahawk3_mmu_port_mapping_init (int unit); 1222 extern int soc_tomahawk3_en_mmu_refresh (int unit); 1223 extern int soc_th3_mmu_config_init_thresholds(int unit, int test_only); 1224 extern int soc_tomahawk3_init_tm_memory(int unit); 1225 extern int soc_tomahawk3_ep_top_init(int unit); 1226 1227 /* 1228 ========================== 1229 TH3 TM Init MMU Functions 1230 ========================== 1231 */ 1232 extern int soc_tomahawk3_tm_port_speed_encoding(int unit); 1233 extern int soc_tomahawk3_cell_pointer_init(int unit); 1234 extern int soc_tomahawk3_mmu_port_rx_enables(int unit); 1235 extern int soc_th3_mmu_rqe_queue_number_init(int unit); 1236 1237 extern uint32 _soc_th3_mmu_port(int unit, int port); 1238 extern uint32 soc_th3_mmu_chip_port_num (int unit, int port); 1239 extern uint32 soc_th3_mmu_local_port_num (int unit, int port); 1240 extern void soc_tomahawk3_pipe_map_get(int unit, uint32 *pipe_map); 1241 extern int soc_tomahawk3_itm_valid(int unit, int itm); 1242 extern int soc_th3_ports_per_pm_get(int unit, int pm_id); 1243 1244 extern int soc_th3_l2x_attach(int unit); 1245 extern int soc_th3_l2x_detach(int unit); 1246 extern int soc_th3_l2_learn_thread_running(int unit, sal_usecs_t* interval); 1247 extern int soc_th3_l2_learn_thread_start(int unit, int interval); 1248 extern int soc_th3_l2_learn_thread_stop(int unit); 1249 extern int soc_th3_l2_learn_alloc_resources(int unit); 1250 extern int soc_th3_lrn_shadow_insert(int unit, l2x_entry_t *entry); 1251 extern int soc_th3_lrn_shadow_delete(int unit, l2x_entry_t *entry); 1252 extern int soc_th3_lrn_shadow_show(void *user_data, shr_avl_datum_t *datum, 1253 void *extra_data); 1254 extern void soc_th3_lrn_cache_intr_handler(int unit, void *data); 1255 extern void soc_tomahawk3_port_ratio_get_schedule_state(int unit, 1256 soc_port_schedule_state_t *port_schedule_state, 1257 int cdport, int *mode, 1258 int prev_or_new); 1259 1260 extern int soc_tomahawk3_idb_init_update(int unit); 1261 extern int soc_tomahawk3_cdport_init(int unit); 1262 extern int soc_tomahawk3_tsc_clock_init(int unit); 1263 extern int soc_tomahawk3_slot_pipeline_config(int unit); 1264 extern int soc_tomahawk3_enable_ingress_forwarding(int unit); 1265 1266 /* 1267 ========================== 1268 TH3 PSTATS MMU Functions 1269 ========================== 1270 */ 1271 1272 #define _TH3_MMU_PSTATS_ENABLE_ING 0x0001 /* Packetized Stat ING is enabled */ 1273 #define _TH3_MMU_PSTATS_ENABLE_EGR 0x0002 /* Packetized Stat EGR is enabled */ 1274 #define _TH3_MMU_PSTATS_ENABLE 0x0003 1275 #define _TH3_MMU_PSTATS_HWM_MOD_ING 0x0004 /* Report High Watermark values for INGRESS */ 1276 #define _TH3_MMU_PSTATS_HWM_MOD_EGR 0x0008 /* Report High Watermark values for EGRESS */ 1277 #define _TH3_MMU_PSTATS_HWM_MOD 0x000c 1278 #define _TH3_MMU_PSTATS_RESET_ON_READ_ING 0x0010 /* Enable Hardware clear-on read for INGRESS*/ 1279 #define _TH3_MMU_PSTATS_RESET_ON_READ_EGR 0x0020 /* Enable Hardware clear-on read for EGRESS*/ 1280 #define _TH3_MMU_PSTATS_RESET_ON_READ 0x0030 1281 #define _TH3_MMU_PSTATS_MOR_EN 0x0100 /* Enable MOR capability */ 1282 #define _TH3_MMU_PSTATS_SYNC 0x8000 /* Read from device else the buffer */ 1283 1284 extern void soc_tomahawk3_mmu_pstats_tbl_config_all(int unit); 1285 extern void soc_tomahawk3_mmu_pstats_tbl_config(int unit); 1286 extern int soc_tomahawk3_mmu_pstats_mode_set(int unit, uint32 flags); 1287 extern int soc_tomahawk3_mmu_pstats_mode_get(int unit, uint32 *flags); 1288 extern int soc_tomahawk3_mmu_pstats_mor_enable(int unit); 1289 extern int soc_tomahawk3_mmu_pstats_mor_disable(int unit); 1290 extern int soc_tomahawk3_mmu_splitter_reset(int unit); 1291 1292 /**************** TDM start ***********************/ 1293 #define _TH3_PKT_SCH_LENGTH 160 1294 #define _TH3_TDM_CALENDAR_UNIVERSAL 0 1295 #define _TH3_TDM_CALENDAR_ETHERNET_OPTIMIZED 1 1296 #define _TH3_TDM_SPEED_CLASS_MAX 7 1297 1298 extern int soc_tomahawk3_tdm_update(int unit); 1299 1300 extern int soc_th3_retrieve_mmu_mem_list_for_port(int unit, int port, soc_mem_t mem, 1301 int blk_num, soc_mem_t *mem_list, int max_mem_cnt, int *mem_cnt); 1302 extern int soc_tomahawk3_dpr_frequency_range_check(int unit, int dpr_freq); 1303 extern void soc_th3_check_idb_portmap(int unit); 1304 extern void soc_th3_check_mmu_portmap(int unit); 1305 extern void soc_th3_check_settings_from_file(int unit, char* file_name); 1306 1307 /* Thresholds */ 1308 extern void _soc_th3_mmu_init_dev_config(int unit, _soc_mmu_device_info_t *devcfg, 1309 int lossless); 1310 1311 /* Scheduler */ 1312 extern int soc_tomahawk3_sched_profile_set(int unit, int profile, int L0, int schedq, 1313 int mmuq); 1314 extern int _soc_scheduler_profile_mapping_setup(int unit, _soc_mmu_cfg_scheduler_profile_t *sched_profile, 1315 int profile_index, int *L0, int *schedq, int *mmuq, 1316 int *cos_list, int *strict_priority, int *fc_is_uc_only); 1317 1318 extern int soc_tomahawk3_profile_exists(int unit, int profile); 1319 extern int soc_tomahawk3_sched_profile_attach(int unit, soc_port_t port, int profile); 1320 extern int soc_tomahawk3_sched_profile_get(int unit, soc_port_t port, int *profile); 1321 extern int soc_tomahawk3_l1_to_l0_profile_set_per_port(int unit, int port, int profile, int L0, int schedq); 1322 extern int soc_tomahawk3_l1_to_l0_profile_update_per_port(int unit, int port, int profile); 1323 1324 1325 extern int soc_tomahawk3_tbl_entries_per_sram_entry_get(int unit, soc_mem_t mem, 1326 int *table_entries_per_sram_entry); 1327 1328 extern int soc_tomahawk3_hash_mutex_init (int unit); 1329 1330 /* Flowtracker (ETRAP) */ 1331 extern int _bcm_th3_ft_dump_stats(int unit, int clear); 1332 1333 extern int _bcm_th3_ft_dump_flow_table(int unit, int pipe, int start_idx, int end_idx, int valid); 1334 extern int soc_th3_skip_obm_mem_if_pm_down(int unit, soc_mem_t mem, int *skip); 1335 1336 1337 extern int 1338 soc_tomahawk3_bond_info_init(int unit); 1339 1340 #ifdef INCLUDE_AVS 1341 extern soc_error_t 1342 soc_tomahawk3_avs_init(int unit); 1343 #endif /* INCLUDE_AVS */ 1344 1345 typedef struct _soc_pkt_size_dist_s 1346 { 1347 /* Packet size in bytes; distribution percentage */ 1348 int pkt_size; 1349 int dist_perc; 1350 } _soc_pkt_size_dist_t; 1351 1352 extern int 1353 soc_th3_get_port_pg_headroom (int unit, int port_speed, 1354 int cable_length, int array_size, _soc_pkt_size_dist_t *pkt_size_dst, 1355 int *pg_hdrm); 1356 1357 #endif /* !_soc_tomahawk3_H_ */