tomahawk2.h (14549B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * File: tomahawk2.h 8 */ 9 10 #ifndef _SOC_TOMAHAWK2_H_ 11 #define _SOC_TOMAHAWK2_H_ 12 13 #include <soc/drv.h> 14 #include <soc/mem.h> 15 #include <soc/error.h> 16 #include <soc/mmu_config.h> 17 #include <soc/esw/port.h> 18 19 extern int soc_th2_post_mmu_init_update(int unit); 20 extern int soc_th2_vfp_ser_correction(int unit, soc_mem_t mem, int index, 21 int copyno, int entry_dw); 22 extern int soc_tomahawk2_port_config_init(int unit, uint16 dev_id); 23 extern int _soc_tomahawk2_port_mapping_init(int unit); 24 extern void _soc_th2_mmu_init_dev_config(int unit, 25 _soc_mmu_device_info_t *devcfg, 26 int lossless); 27 extern int soc_th2_slot_pipeline_latency_get(int dpp_ratio_x10, int lmode); 28 extern int soc_tomahawk2_clear_mmu_memory(int unit); 29 extern int soc_tomahawk2_init_mmu_memory(int unit); 30 extern void soc_tomahawk2_sbus_ring_map_config(int unit); 31 extern int soc_tomahawk2_chip_reset(int unit); 32 extern int soc_th2_mmu_config_init(int unit, int test_only); 33 34 #ifdef BCM_WARM_BOOT_SUPPORT 35 extern int soc_tomahawk2_chip_warmboot_reset(int unit); 36 #endif 37 38 extern int soc_tomahawk2_sed_base_index_check(int unit, int base_type, int sed, 39 int base_index, char *msg); 40 extern int soc_tomahawk2_sed_reg32_set(int unit, soc_reg_t reg, int sed, 41 int base_index, int index, uint32 data); 42 extern int soc_tomahawk2_sed_reg32_get(int unit, soc_reg_t reg, int sed, 43 int base_index, int index, uint32 *data); 44 extern int soc_tomahawk2_sed_reg_set(int unit, soc_reg_t reg, int sed, 45 int base_index, int index, uint64 data); 46 extern int soc_tomahawk2_sed_reg_get(int unit, soc_reg_t reg, int sed, 47 int base_index, int index, uint64 *data); 48 extern int _soc_tomahawk2_tdm_init(int unit); 49 50 extern void soc_tomahawk2_mmu_pstats_tbl_config(int unit); 51 extern int soc_tomahawk2_mmu_pstats_mode_set(int unit, uint32 flags); 52 extern int soc_tomahawk2_mmu_pstats_mode_get(int unit, uint32 *flags); 53 extern int soc_tomahawk2_mmu_pstats_mor_enable(int unit); 54 extern int soc_tomahawk2_mmu_pstats_mor_disable(int unit); 55 extern int soc_tomahawk2_mmu_splitter_reset(int unit); 56 extern int soc_tomahawk2_mdio_addr_to_port(uint32 phy_addr); 57 extern int soc_th2_ledup_init(int unit); 58 extern int soc_tomahawk2_bond_info_init(int unit); 59 extern int soc_tomahawk2_port_obm_info_get(int unit, soc_port_t port, 60 int *obm_id, int *lane); 61 extern int soc_th2_latency_bypassed(int unit, soc_feature_t feature); 62 extern int 63 soc_th2_mmu_non_ser_intr_handler(int unit, soc_block_t blocktype, 64 int mmu_base_index, 65 uint32 rval_intr_status_reg); 66 extern int 67 soc_tomahawk2_clear_enabled_port_data(int unit); 68 69 /* General Physical port */ 70 #define _TH2_PORTS_PER_PBLK 4 71 #define _TH2_PBLKS_PER_PIPE 16 72 #define _TH2_PBLKS_PER_HPIPE 8 73 #define _TH2_PIPES_PER_DEV 4 74 #define _TH2_XPES_PER_DEV 4 75 76 #define _TH2_PBLKS_PER_DEV \ 77 (_TH2_PBLKS_PER_PIPE * _TH2_PIPES_PER_DEV) 78 79 #define _TH2_PORTS_PER_PIPE \ 80 (_TH2_PORTS_PER_PBLK * _TH2_PBLKS_PER_PIPE) 81 #define _TH2_PORTS_PER_DEV \ 82 (_TH2_PORTS_PER_PIPE * _TH2_PIPES_PER_DEV) 83 84 /* 64 Falcon + 1 Eagle core*/ 85 #define _TH2_PM_PER_DEV (_TH2_PBLKS_PER_DEV + 1) 86 87 #define _TH2_GPHY_PORTS_PER_PIPE \ 88 (_TH2_PORTS_PER_PBLK * _TH2_PBLKS_PER_PIPE) 89 #define _TH2_GPHY_PORTS_PER_DEV \ 90 (_TH2_GPHY_PORTS_PER_PIPE * _TH2_PIPES_PER_DEV) 91 92 #define PORT_BLOCK_BASE_PORT(port) \ 93 (1 + ((SOC_INFO(unit).port_l2p_mapping[port] - 1) & ~0x3)); 94 95 /* 64 General_phy_port + 1 CPU/Magagement + 1 Loopback 96 * Note: phy port id range: 97 * General phy port 1-256 98 * CPU 0 99 * LB 260-263 100 * Mng 257,259 101 */ 102 #define _TH2_PHY_PORTS_PER_PIPE (_TH2_GPHY_PORTS_PER_PIPE + 2) 103 #define _TH2_PHY_PORTS_PER_DEV \ 104 (_TH2_PHY_PORTS_PER_PIPE * _TH2_PIPES_PER_DEV) 105 #define _TH2_PHY_PORT_MNG0 257 106 #define _TH2_PHY_PORT_MNG1 259 107 108 /* Device port */ 109 /* 32 General device port + 1 CPU/Mng + 1 Loopback*/ 110 #define _TH2_GDEV_PORTS_PER_PIPE 32 111 #define _TH2_DEV_PORTS_PER_PIPE (_TH2_GDEV_PORTS_PER_PIPE + 2) 112 #define _TH2_DEV_PORTS_PER_DEV \ 113 (_TH2_DEV_PORTS_PER_PIPE * _TH2_PIPES_PER_DEV) 114 #define _TH2_DEV_RSV_PORT 134 /* Reserved Port */ 115 #define _TH2_DEV_PORT_MNG0 66 116 #define _TH2_DEV_PORT_MNG1 100 117 118 119 /* MMU port */ 120 #define _TH2_MMU_PORTS_OFFSET_PER_PIPE 64 121 #define _TH2_MMU_PORTS_PER_DEV (64 * 4) 122 #define _TH2_MMU_GPORTS_PER_PIPE 32 /* General Ethernet or Higig Ports*/ 123 #define _TH2_MMU_PORT_MNG0 96 124 #define _TH2_MMU_PORT_MNG1 160 125 126 /* MMU spec */ 127 #define _TH2_MMU_PHYSICAL_CELLS_PER_XPE 57344 /* Total Physical cells per XPE 14*4K */ 128 #define _TH2_MMU_TOTAL_CELLS_PER_XPE 53248 /* usable cell pointer 13*4K cells */ 129 #define _TH2_MMU_RSVD_CELLS_CFAP_PER_XPE 286 /* Reserved CFAP cells per XPE */ 130 131 #define _TH2_THDI_BUFFER_CELL_LIMIT_SP_MAX _TH2_MMU_TOTAL_CELLS_PER_XPE 132 #define _TH2_THDI_HDRM_BUFFER_CELL_LIMIT_HP_MAX _TH2_MMU_TOTAL_CELLS_PER_XPE 133 134 #define _TH2_MMU_TOTAL_CELLS (_TH2_MMU_TOTAL_CELLS_PER_XPE * _TH2_XPES_PER_DEV) 135 #define _TH2_MMU_PHYSICAL_CELLS (_TH2_MMU_PHYSICAL_CELLS_PER_XPE * _TH2_XPES_PER_DEV) 136 137 #define SOC_TH2_NUM_UC_QUEUES_PER_PIPE 330 /* Num UC Q's Per pipe 33 * 10 */ 138 #define SOC_TH2_MMU_MCQ_ENTRY_PER_XPE 8192 139 #define SOC_TH2_MMU_RQE_ENTRY_PER_XPE 2048 140 #define SOC_TH2_MMU_MCQ_ENTRY_RESERVED_TDM_OVERSHOOT 12 141 142 #define _TH2_MMU_TOTAL_MCQ_ENTRY(unit) SOC_TH2_MMU_MCQ_ENTRY_PER_XPE 143 #define _TH2_MMU_TOTAL_RQE_ENTRY(unit) SOC_TH2_MMU_RQE_ENTRY_PER_XPE 144 145 /* MMU pktstats control flags */ 146 #define _TH2_MMU_PSTATS_ENABLE 0x0001 /* Packetized/OOB Stat mode is enabled */ 147 #define _TH2_MMU_PSTATS_PKT_MOD 0x0002 /* Packetized mode is enabled. OOB Stat mode is disabled */ 148 #define _TH2_MMU_PSTATS_HWM_MOD 0x0004 /* Report High Watermark values */ 149 #define _TH2_MMU_PSTATS_RESET_ON_READ 0x0008 /* Enable Hardware clear-on read */ 150 #define _TH2_MMU_PSTATS_MOR_EN 0x0010 /* Enable MOR capability */ 151 #define _TH2_MMU_PSTATS_SYNC 0x8000 /* Read from device else the buffer */ 152 153 /* IDB port */ 154 #define _TH2_IDB_PORT_CPU_MNG 32 155 156 /**************** TDM start ***********************/ 157 #define _TH2_TDM_LENGTH 512 158 #define _TH2_OVS_GROUP_COUNT_PER_HPIPE 6 159 #define _TH2_OVS_GROUP_COUNT_PER_PIPE 12 160 #define _TH2_OVS_GROUP_TDM_LENGTH 12 161 #define _TH2_OVS_HPIPE_COUNT_PER_PIPE 2 162 #define _TH2_PKT_SCH_LENGTH 160 163 164 #define _TH2_TDM_CALENDAR_UNIVERSAL 0 165 #define _TH2_TDM_CALENDAR_ETHERNET_OPTIMIZED 1 166 167 #define _TH2_TDM_LR_SPEED_CLASS_MAX 4 168 #define _TH2_TDM_OS_SPEED_CLASS_MAX 5 169 170 /* Special port number used by TDM */ 171 #define _SOC_TH2_TDM_CPU_MNG_TOKEN 0x20 172 #define _SOC_TH2_TDM_LB_TOKEN 0x21 173 #define _SOC_TH2_TDM_OVERSUB_TOKEN 0x22 174 #define _SOC_TH2_TDM_NULL_TOKEN 0x23 175 #define _SOC_TH2_TDM_IDL1_TOKEN 0x24 176 #define _SOC_TH2_TDM_IDL2_TOKEN 0x25 177 #define _SOC_TH2_TDM_UNUSED_TOKEN 0x3f 178 179 typedef struct _soc_tomahawk2_tdm_pblk_info_s { 180 int pblk_hpipe_num; /* half pipeline info */ 181 int pblk_cal_idx; /* index to 8 HPIPEx_PBLK_CALENDARr */ 182 } _soc_tomahawk2_tdm_pblk_info_t; 183 184 typedef struct _soc_tomahawk2_tdm_pipe_s { 185 int idb_tdm[_TH2_TDM_LENGTH]; 186 int mmu_tdm[_TH2_TDM_LENGTH]; 187 int ovs_tdm[_TH2_OVS_HPIPE_COUNT_PER_PIPE][_TH2_OVS_GROUP_COUNT_PER_HPIPE][_TH2_OVS_GROUP_TDM_LENGTH]; 188 int pkt_shaper_tdm[_TH2_OVS_HPIPE_COUNT_PER_PIPE][_TH2_PKT_SCH_LENGTH]; 189 } _soc_tomahawk2_tdm_pipe_t; 190 191 typedef struct _soc_tomahawk2_tdm_s { 192 _soc_tomahawk2_tdm_pipe_t tdm_pipe[_TH2_PIPES_PER_DEV]; 193 _soc_tomahawk2_tdm_pblk_info_t pblk_info[_TH2_PHY_PORTS_PER_DEV]; 194 int port_ratio[_TH2_PBLKS_PER_DEV]; 195 int ovs_ratio_x1000[_TH2_PIPES_PER_DEV][_TH2_OVS_HPIPE_COUNT_PER_PIPE]; 196 } _soc_tomahawk2_tdm_t; 197 198 extern int _soc_tomahawk2_idb_init(int unit); 199 extern int _soc_tomahawk2_ing_fsaf_init(int unit); 200 #ifdef BCM_WARM_BOOT_SUPPORT 201 extern int soc_th2_tdm_scache_allocate(int unit); 202 extern int soc_th2_tdm_scache_sync(int unit); 203 extern int soc_th2_tdm_scache_recovery(int unit); 204 #endif /* BCM_WARM_BOOT_SUPPORT */ 205 206 /**************** TDM end ***********************/ 207 208 /* Oversub XON/XOFF Threshold */ 209 #define _TH2_XON_THRESHOLD_10G 1584 210 #define _TH2_XON_THRESHOLD_25G 1584 211 #define _TH2_XON_THRESHOLD_40G 4656 212 #define _TH2_XON_THRESHOLD_50G 4656 213 #define _TH2_XON_THRESHOLD_100G 11808 214 #define _TH2_XOFF_THRESHOLD_10G 2064 215 #define _TH2_XOFF_THRESHOLD_25G 2064 216 #define _TH2_XOFF_THRESHOLD_40G 5136 217 #define _TH2_XOFF_THRESHOLD_50G 5136 218 #define _TH2_XOFF_THRESHOLD_100G 12288 219 220 /*PG headroom*/ 221 #define _TH2_PG_HEADROOM_LINERATE_10G 166 222 #define _TH2_PG_HEADROOM_LINERATE_25G 194 223 #define _TH2_PG_HEADROOM_LINERATE_40G 280 224 #define _TH2_PG_HEADROOM_LINERATE_50G 298 225 #define _TH2_PG_HEADROOM_LINERATE_100G 507 226 #define _TH2_PG_HEADROOM_OVERSUB_10G \ 227 (_TH2_PG_HEADROOM_LINERATE_10G + CEIL(_TH2_XOFF_THRESHOLD_10G, 64)) 228 #define _TH2_PG_HEADROOM_OVERSUB_25G \ 229 (_TH2_PG_HEADROOM_LINERATE_25G + CEIL(_TH2_XOFF_THRESHOLD_25G, 64)) 230 #define _TH2_PG_HEADROOM_OVERSUB_40G \ 231 (_TH2_PG_HEADROOM_LINERATE_40G + CEIL(_TH2_XOFF_THRESHOLD_40G, 64)) 232 #define _TH2_PG_HEADROOM_OVERSUB_50G \ 233 (_TH2_PG_HEADROOM_LINERATE_50G + CEIL(_TH2_XOFF_THRESHOLD_50G, 64)) 234 #define _TH2_PG_HEADROOM_OVERSUB_100G \ 235 (_TH2_PG_HEADROOM_LINERATE_100G + CEIL(_TH2_XOFF_THRESHOLD_100G, 64)) 236 237 /* CFAP */ 238 #define _TH2_CFAP_BANK_FULL_LIMIT 2047 239 240 #define _TH2_POLL_SCALE_TO_LIMIT(size, scale) \ 241 (((scale) > 0) && ((scale) < 8) ? \ 242 (((size) * (scale) * 125) / 1000) : (size)) 243 244 extern int soc_tomahawk2_edb_buf_reset(int unit, soc_port_t port, int reset); 245 extern int soc_tomahawk2_idb_buf_reset(int unit, soc_port_t port, int reset); 246 247 enum soc_th2_port_mode_e { 248 /* WARNING: values given match hardware register; do not modify */ 249 SOC_TH2_PORT_MODE_QUAD = 0, 250 SOC_TH2_PORT_MODE_TRI_012 = 1, 251 SOC_TH2_PORT_MODE_TRI_023 = 2, 252 SOC_TH2_PORT_MODE_DUAL = 3, 253 SOC_TH2_PORT_MODE_SINGLE = 4 254 }; 255 256 extern int soc_th2_port_mode_get(int unit, int logical_port, int *mode); 257 258 #ifdef PORTMOD_SUPPORT 259 extern int soc_th2_portctrl_pm_portmod_init(int unit); 260 extern int soc_th2_portctrl_pm_portmod_deinit(int unit); 261 extern int soc_th2_portctrl_pm_port_config_get(int unit, soc_port_t port, void *port_config_info); 262 extern int soc_th2_portctrl_pm_port_phyaddr_get(int unit, soc_port_t port); 263 extern int soc_th2_portctrl_port_ability_update(int unit, soc_port_t port, 264 soc_port_ability_t *ability); 265 extern int soc_th2_portctrl_pm_type_get(int unit, soc_port_t phy_port, int* pm_type); 266 #ifdef FW_BCAST_DOWNLOAD 267 extern int soc_th2_portctrl_sbus_ring_info_get(int unit, soc_port_t port, int* bcast_id, int* position); 268 extern int soc_th2_portctrl_sbus_bcast_id_get(int unit, int sbus_ch, int* bcast_id); 269 #endif 270 #endif 271 272 /************ FlexPort Start ********************/ 273 extern int soc_th2_port_schedule_tdm_init(int unit, 274 soc_port_schedule_state_t *port_schedule_state); 275 extern int soc_th2_soc_tdm_update(int unit, 276 soc_port_schedule_state_t *port_schedule_state); 277 extern int soc_th2_mmu_config_init_port(int unit, int port); 278 extern int soc_th2_max_lr_bandwidth(int unit, uint32 *max_lr_bw); 279 extern int soc_th2_support_speeds(int unit, int lanes, uint32 *speed_mask); 280 extern int soc_th2_speed_mix_validate(int unit, uint32 speed_mask); 281 #ifdef BCM_WARM_BOOT_SUPPORT 282 extern int soc_th2_flexport_scache_allocate(int unit); 283 extern int soc_th2_flexport_scache_sync(int unit); 284 extern int soc_th2_flexport_scache_recovery(int unit); 285 #endif /* BCM_WARM_BOOT_SUPPORT */ 286 #ifndef BCM_SW_STATE_DUMP_DISABLE 287 extern void soc_th2_flexport_sw_dump(int unit); 288 #endif /* BCM_SW_STATE_DUMP_DISABLE */ 289 /************ FlexPort End ********************/ 290 typedef int (*_soc_th2_tcb_hw_cb)(int unit); 291 extern int soc_th2_set_tcb_callback(int unit, _soc_th2_tcb_hw_cb cb); 292 extern int soc_th2_process_mmu_tcb(int unit, int xpe, soc_field_t field); 293 extern soc_error_t soc_th2_port_speed_supported(int unit, soc_port_t port, 294 int speed); 295 296 extern int soc_th2_mmu_config_shared_buf_set_hw(int unit, int res, 297 int *thdi_shd, int *thdo_db_shd, int *thdo_qe_shd, 298 int post_update); 299 extern int soc_th2_mmu_config_shared_buf_set_hw_port(int unit, int port, 300 int *thdi_shd, 301 int *thdo_db_shd, 302 int *thdo_qe_shd); 303 extern int soc_th2_max_lr_bandwidth_validate(int unit); 304 extern int soc_th2_speed_class_validate(int unit); 305 306 /************ Untethered OTP Start *************/ 307 typedef struct _soc_tomahawk2_tsc_otp_info_s{ 308 int disable; /* TSC_DISABLE */ 309 int max_lane_speed; /* TSC_MAX_LANE_SPEED */ 310 int force_loopback; /* TSC_FORCE_LOOPBACK */ 311 int force_hg; /* FORCE_HG */ 312 } _soc_tomahawk2_tsc_otp_info_t; 313 314 extern int soc_tomahawk2_tsc_otp_info_get(int unit, int tsc_id, 315 _soc_tomahawk2_tsc_otp_info_t *info); 316 extern void soc_th2_uft_otp_info_get(int unit, 317 int *num_share_banks_enabled, int *share_banks_bitmap_enabled); 318 extern int soc_th2_set_uft_bank_map(int unit); 319 320 /************* Untethered OTP End **************/ 321 322 /************ SRAM info Start *************/ 323 #define SOC_TH2_NUM_EL_SHARED 8 324 #define SOC_TH2_LP_ENTRIES_IN_UFT_BANK 16384 325 #define SOC_TH2_NUM_EL_ING_L3_NEXT_HOP 6 326 /************* SRAM info End **************/ 327 328 /************* AVS Start **************/ 329 #ifdef INCLUDE_AVS 330 extern soc_error_t soc_th2_avs_init(int unit); 331 #endif /* INCLUDE_AVS */ 332 /************* AVS End **************/ 333 334 #endif /* !_SOC_TOMAHAWK2_H_ */