tomahawk.h (48794B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * File: tomahawk.h 8 */ 9 10 #ifndef _SOC_TOMAHAWK_H_ 11 #define _SOC_TOMAHAWK_H_ 12 13 #include <soc/drv.h> 14 #include <soc/trident2.h> 15 16 #define UPDATE_ALL_PIPES -1 17 18 #define SOC_TH_MMU_BASE_TYPE_IPORT 0 19 #define SOC_TH_MMU_BASE_TYPE_EPORT 1 20 #define SOC_TH_MMU_BASE_TYPE_IPIPE 2 21 #define SOC_TH_MMU_BASE_TYPE_EPIPE 3 22 #define SOC_TH_MMU_BASE_TYPE_CHIP 4 23 #define SOC_TH_MMU_BASE_TYPE_XPE 5 24 #define SOC_TH_MMU_BASE_TYPE_SLICE 6 25 #define SOC_TH_MMU_BASE_TYPE_LAYER 7 26 27 #define SOC_TH_MEM_CHK_IFP_TCAM(mem) \ 28 (mem == IFP_TCAMm || \ 29 mem == IFP_TCAM_PIPE0m || mem == IFP_TCAM_PIPE1m || \ 30 mem == IFP_TCAM_PIPE2m || mem == IFP_TCAM_PIPE3m) 31 #define SOC_TH_MEM_CHK_IFP_TCAM_WIDE(mem) \ 32 (mem == IFP_TCAM_WIDEm || \ 33 mem == IFP_TCAM_WIDE_PIPE0m || mem == IFP_TCAM_WIDE_PIPE1m || \ 34 mem == IFP_TCAM_WIDE_PIPE2m || mem == IFP_TCAM_WIDE_PIPE3m) 35 #define SOC_TH_MEM_CHK_TCAM_GLOBAL_UNIQUE_MODE(mem) \ 36 (mem == SRC_COMPRESSIONm || mem == DST_COMPRESSIONm || \ 37 mem == FP_UDF_TCAMm || mem == VFP_TCAMm || \ 38 mem == IFP_LOGICAL_TABLE_SELECTm || \ 39 mem == EXACT_MATCH_LOGICAL_TABLE_SELECTm || \ 40 mem == EFP_TCAMm || mem == IFP_TCAMm || mem == IFP_TCAM_WIDEm) \ 41 42 #define IS_HG2_SPEED(speed) ((106000 == speed) || (53000 == speed) || \ 43 (42000 == speed) || (27000 == speed) || \ 44 (21000 == speed) || (11000 == speed)) 45 46 #define CCLK_FREQ_850MHZ 850 47 48 #define SOC_TH_MMU_LOSSLESS_DEFAULT_ENABLE 1 49 #define SOC_TH_MMU_LOSSLESS_DEFAULT_DISABLE 0 50 51 extern soc_pbmp_t loopback_disable[SOC_MAX_NUM_DEVICES]; 52 53 extern int soc_tomahawk_clear_mmu_memory(int unit); 54 55 extern int soc_th_mem_parity_control(int unit, soc_mem_t mem, int copyno, 56 int en, int en_1b); 57 58 extern int soc_th_ser_reg_field32_modify(int unit, soc_reg_t reg, 59 soc_port_t port, soc_field_t field, 60 uint32 value, int index, 61 int mmu_base_index); 62 extern int soc_th_ser_reg_field_modify(int unit, soc_reg_t reg, 63 soc_port_t port, soc_field_t field, 64 uint32 value, int index, 65 int mmu_base_index); 66 extern int 67 soc_tomahawk_mmu_port_flush_hw(int unit, soc_port_t port, uint32 drain_timeout); 68 69 extern int 70 soc_th_lp_to_fv_index_remap(int unit, soc_mem_t mem, int *rpt_index); 71 72 extern int 73 soc_th_scan_idb_mem_ecc_status(int unit); 74 75 extern int 76 soc_th_check_scrub_info(int unit, soc_mem_t mem, int blk, int copyno, 77 int *num_inst_to_scrub, int *acc_type_list); 78 extern int soc_th_check_scrub_skip(int unit, soc_mem_t mem, 79 int check_hw_global_mode); 80 extern int soc_th_mem_is_eligible_for_scan(int unit, soc_mem_t mem); 81 extern void soc_th_mem_scan_info_get(int unit, soc_mem_t mem, int block, 82 int *num_pipe, int *ser_flag); 83 extern int soc_th_check_cache_skip(int unit, soc_mem_t mem); 84 extern int soc_th_check_hw_global_mode(int unit, soc_mem_t mem, int *mem_mode); 85 extern int 86 soc_th_ifp_tcam_dma_read(int unit, soc_mem_t mem, int blk, uint32 *table, 87 int en_per_pipe_read, uint8 *vmap); 88 89 #if defined(SER_TR_TEST_SUPPORT) 90 extern int ser_test_th_mem_index_remap(int unit, ser_test_data_t *test_data, 91 int *mem_has_ecc); 92 #endif /*defined(SER_TR_TEST_SUPPORT*/ 93 94 extern int soc_th_mem_index_invalid(int unit, soc_mem_t mem, int index, 95 uint8 dual_mode, soc_mem_t in_mem, 96 int in_pipe); 97 98 extern int soc_th_mem_is_dual_mode(int unit, soc_mem_t mem, 99 soc_mem_t *base_mem, int *pipe); 100 extern int soc_th_ifp_tcam_range_dma_read(int unit, soc_mem_t mem, int blk, 101 int start_addr, uint32 num_entry, uint32 *table); 102 extern int soc_th_dual_tcam_index_valid(int unit, soc_mem_t mem, int index); 103 extern int 104 soc_tomahawk_show_ring_osc(int unit); 105 106 extern int 107 soc_th_ifp_slice_mode_hw_get(int unit, int pipe, int slice_num, int *slice_type, 108 int *slice_enabled); 109 extern int 110 soc_th_ifp_slice_mode_get(int unit, int pipe, int slice_num, int *slice_type, 111 int *slice_enabled); 112 extern int 113 soc_th_mmu_non_ser_intr_handler(int unit, soc_block_t blocktype, 114 int mmu_base_index, 115 uint32 rval_intr_status_reg); 116 extern int soc_th_mmu_get_shared_size(int unit, int *ing_shd, 117 int *egr_db_shd, int *egr_qe_shd); 118 extern int soc_th_mmu_config_shared_buf_recalc(int unit, int res, int *ing_shd, 119 int *egr_db_shd, int *egr_qe_shd, 120 int flags); 121 extern int soc_th_mmu_config_res_limits_update(int unit, int res, int *ing_shd, 122 int *egr_db_shd, int *egr_qe_shd, 123 int flags); 124 extern int soc_th_mmu_additional_buffer_reserve(int unit, int pipe, int flex, 125 int lossless, int asf_profile, 126 _soc_mmu_rsvd_buffer_t *rsvd_buffer); 127 128 extern int soc_th_mmu_get_egr_rsvd(int unit, int pipe, int *egr_rsvd); 129 extern int soc_th_recalc_new_egress_shared_limit(int unit, int pipe, 130 int *new_shared_limit); 131 132 extern soc_functions_t soc_tomahawk_drv_funs; 133 extern int soc_tomahawk_tcam_ser_init(int unit); 134 extern int soc_tomahawk_ser_enable_all(int unit, int enable); 135 extern void soc_tomahawk_ser_fail(int unit); 136 extern void soc_tomahawk_ser_error(void *unit_vp, void *d1, void *d2, 137 void *d3, void *d4); 138 extern int soc_tomahawk_mem_ser_control(int unit, soc_mem_t mem, 139 int copyno, int enable); 140 #if defined(INCLUDE_FLOWTRACKER) 141 typedef int (*soc_th_ft_em_ser_handler_t)(int unit, int pipe, soc_mem_t mem, int index); 142 void soc_th_ft_em_ser_handler_register(int unit, soc_th_ft_em_ser_handler_t handler); 143 int soc_th_ft_em_ser_process(int unit, int pipe, soc_mem_t mem, int index); 144 #endif /* INCLUDE_FLOWTRACKER */ 145 146 #ifdef BCM_TOMAHAWK2_SUPPORT 147 extern int soc_th2_tcam_engine_enable(int unit, int enable); 148 #endif 149 150 extern int soc_tomahawk_mem_cpu_write_control(int unit, soc_mem_t mem, int copyno, 151 int enable, int *orig_enable); 152 extern int soc_tomahawk_reg_cpu_write_control(int unit, int enable); 153 extern int soc_tomahawk_ser_mem_clear(int unit, soc_mem_t mem); 154 extern void soc_tomahawk_ser_register(int unit); 155 extern int soc_tomahawk_process_ser_fifo(int unit, soc_block_t blk, int pipe, 156 char *prefix_str, int l2_mgmt_ser_fifo, 157 int reg_type, int cmic_bit); 158 extern int soc_tomahawk_alpm_scrub(int unit); 159 extern int soc_tomahawk_mem_config(int unit); 160 extern int soc_tomahawk_num_cosq_init_port(int unit, int port); 161 extern int soc_tomahawk_num_cosq_init(int unit); 162 extern void soc_tomahawk_pipe_map_get(int unit, uint32 *pipe_map); 163 extern void soc_tomahawk_port_ratio_get(int unit, int initTime, int clport, int *mode); 164 165 extern int soc_tomahawk_port_config_init(int unit, uint16 dev_id); 166 extern int soc_tomahawk_chip_reset(int unit); 167 #ifdef BCM_WARM_BOOT_SUPPORT 168 extern int soc_tomahawk_chip_warmboot_reset(int unit); 169 #endif 170 extern int soc_tomahawk_port_reset(int unit); 171 extern int soc_tomahawkplus_port_reset(int unit); 172 extern int soc_tomahawk_xpe_base_index_check(int unit, int base_type, int xpe, 173 int base_index, char *msg); 174 extern int soc_tomahawk_mmu_layer_get(int unit, int pipe, int *layer); 175 extern int soc_tomahawk_xpe_reg32_set(int unit, soc_reg_t reg, int xpe, 176 int base_index, int index, uint32 data); 177 extern int soc_tomahawk_xpe_reg32_get(int unit, soc_reg_t reg, int xpe, 178 int base_index, int index, uint32 *data); 179 extern int soc_tomahawk_xpe_reg_set(int unit, soc_reg_t reg, int xpe, 180 int base_index, int index, uint64 data); 181 extern int soc_tomahawk_xpe_reg_get(int unit, soc_reg_t reg, int xpe, 182 int base_index, int index, uint64 *data); 183 extern int soc_tomahawk_xpe_mem_write(int unit, soc_mem_t mem, int xpe, 184 int base_index, int copyno, 185 int offset_in_section, void *entry_data); 186 extern int soc_tomahawk_xpe_mem_read(int unit, soc_mem_t mem, int xpe, 187 int base_index, int copyno, 188 int offset_in_section, void *entry_data); 189 extern int soc_tomahawk_mem_xpe_pipe_check(int unit, soc_mem_t mem, 190 int xpe, int pipe); 191 extern int soc_tomahawk_mem_basetype_get(int unit, soc_mem_t mem); 192 extern int soc_tomahawk_mem_is_xpe(int unit, soc_mem_t mem); 193 extern int soc_tomahawk_sc_base_index_check(int unit, int base_type, int sc, 194 int base_index, char *msg); 195 extern int soc_tomahawk_sc_reg32_set(int unit, soc_reg_t reg, int sc, 196 int base_index, int index, uint32 data); 197 extern int soc_tomahawk_sc_reg32_get(int unit, soc_reg_t reg, int sc, 198 int base_index, int index, uint32 *data); 199 extern int soc_tomahawk_sc_reg_set(int unit, soc_reg_t reg, int sc, 200 int base_index, int index, uint64 data); 201 extern int soc_tomahawk_sc_reg_get(int unit, soc_reg_t reg, int sc, 202 int base_index, int index, uint64 *data); 203 extern int soc_tomahawk_port_obm_info_get(int unit, soc_port_t port, 204 int *obm_id, int *lane); 205 206 extern int soc_tomahawk_port_traffic_egr_enable_set(int unit, int port, int enable); 207 208 #if 0 209 extern int soc_tomahawk_sc_mem_write(int unit, soc_mem_t mem, int sc, 210 int base_index, int copyno, 211 int offset_in_section, void *entry_data); 212 extern int soc_tomahawk_sc_mem_read(int unit, soc_mem_t mem, int sc, 213 int base_index, int copyno, 214 int offset_in_section, void *entry_data); 215 #endif 216 extern uint32 _soc_th_piped_mem_index(int unit, soc_port_t port, 217 soc_mem_t mem, int arr_off); 218 219 extern int soc_th_l2_bulk_age_start(int unit, int interval); 220 extern int soc_th_l2_bulk_age_stop(int unit); 221 222 /* Counter */ 223 extern int soc_counter_tomahawk_status_enable(int unit, int enable); 224 extern int soc_counter_tomahawk_non_dma_init(int unit, int nports, 225 int non_dma_start_index, 226 int *non_dma_entries); 227 extern int soc_counter_tomahawk_get_info(int unit, soc_port_t port, 228 soc_reg_t id, int *base_index, 229 int *num_entries); 230 extern int soc_counter_tomahawk_eviction_enable(int unit, int enable); 231 extern void soc_counter_tomahawk_eviction_flags_update(int unit, 232 uint32 flags, 233 int enable); 234 extern int soc_counter_tomahawk_generic_get_info(int unit, soc_ctr_control_info_t ctrl_info, 235 soc_reg_t id, int *base_index, int *num_entries); 236 extern int soc_counter_tomahawk_eviction_init(int unit); 237 extern int soc_counter_tomahawk_get_child_dma(int unit, soc_reg_t id, 238 soc_ctr_control_info_t ctrl_info, 239 soc_counter_non_dma_t **child_dma); 240 extern int soc_counter_tomahawk_dma_flags_update(int unit, 241 soc_counter_non_dma_t *ctr_dma, 242 uint32 flags, int val); 243 244 extern int 245 soc_counter_th_extra_sflow_ctrs_init(int unit, 246 soc_counter_non_dma_t *non_dma_parent, 247 soc_counter_non_dma_t *non_dma_extra, 248 uint32 extra_ctr_ct, 249 int *total_entries); 250 extern int 251 soc_counter_th_extra_ctrs_init(int unit, soc_reg_t id, 252 soc_counter_non_dma_t *non_dma_parent, 253 soc_counter_non_dma_t *non_dma_extra, 254 uint32 extra_ctr_ct, 255 int *total_entries); 256 extern int 257 soc_counter_th_extra_obm_ctrs_init(int unit, 258 soc_counter_non_dma_t *non_dma_parent, 259 soc_counter_non_dma_t *non_dma_extra, 260 uint32 extra_ctr_ct, 261 int *total_entries); 262 extern int soc_counter_tomahawk_ctr_dma_post_init(int unit); 263 264 #if defined(INCLUDE_TELEMETRY) 265 extern int soc_counter_tomahawk_telemetry_init(int unit); 266 267 extern int soc_counter_tomahawk_telemetry_detach(int unit); 268 #endif /* INCLUDE_TELEMETRY */ 269 270 extern soc_error_t 271 soc_th_granular_speed_get(int unit, soc_port_t port, int *speed); 272 273 typedef enum { 274 /* WARNING: values given match hardware register; do not modify */ 275 SOC_TH_SPEED_CLASS_0 = 0, 276 SOC_TH_SPEED_CLASS_10G = 1, 277 SOC_TH_SPEED_CLASS_20G = 2, 278 SOC_TH_SPEED_CLASS_25G = 3, 279 SOC_TH_SPEED_CLASS_40G = 4, 280 SOC_TH_SPEED_CLASS_50G = 5, 281 SOC_TH_SPEED_CLASS_100G = 6 282 } soc_th_speed_classes_e; 283 284 typedef enum { 285 /* WARNING: values given match hardware register; do not modify */ 286 SOC_TH_PORT_MODE_QUAD = 0, 287 SOC_TH_PORT_MODE_TRI_012 = 1, 288 SOC_TH_PORT_MODE_TRI_023 = 2, 289 SOC_TH_PORT_MODE_DUAL = 3, 290 SOC_TH_PORT_MODE_SINGLE = 4 291 } soc_th_port_mode_e; 292 293 #define TH_FLEXPORT_SPEED_SET_NUM_LANES -1 294 295 typedef struct soc_th_port_lanes_s { 296 int port_base; /* Base port number */ 297 int lanes; /* New number of lanes */ 298 int cur_lanes; /* Current number of lanes */ 299 int mode; /* New mode */ 300 int cur_mode; /* Current mode */ 301 int class; /* Speed class for new group */ 302 int cur_class; /* Speed class for current group */ 303 int idb_group; /* New IDB oversub group number */ 304 int cur_idb_group; /* Current IDB oversub group number */ 305 int idb_slots[4]; /* New IDB oversub group slot number */ 306 int cur_idb_slots[4]; /* Current IDB oversub group slot number */ 307 int cur_idb_empty; /* Current IDB oversub group become empty after flex */ 308 int mmu_group; /* New MMU oversub group number */ 309 int cur_mmu_group; /* Current MMU oversub group number */ 310 int mmu_slots[4]; /* New MMU oversub group slot number */ 311 int cur_mmu_slots[4]; /* Current MMU oversub group slot number */ 312 int cur_mmu_empty; /* Current MMU oversub group become empty after flex */ 313 int bindex; /* Base port subport index */ 314 int oversub; /* Oversub status for the ports */ 315 int phy_ports_len; /* Length of valid entries in phy_ports array */ 316 int phy_ports[3]; /* Array of added/removed physical port number */ 317 int speed; /* Port speed to be used during speed set */ 318 int os_mixed_sister; /* enable or disable mixed sister port */ 319 int mixed_port_mode; /* mixed sister port mode */ 320 321 int action_id; 322 int pipe; 323 int speed_id; 324 int port_mode; 325 int src_idb_group; 326 int dst_idb_group; 327 int src_mmu_group; 328 int dst_mmu_group; 329 } soc_th_port_lanes_t; 330 331 typedef struct soc_th_speed_group_slot_s { 332 int slot; 333 int pm_id; 334 int port_id; 335 } soc_th_speed_group_slot_t; 336 337 typedef struct soc_th_speed_group_count_s { 338 int group_id; 339 int count_ports; 340 } soc_th_speed_group_count_t; 341 342 typedef struct soc_speed_group_info_s { 343 soc_th_speed_classes_e speed_id; 344 soc_th_port_mode_e port_mode; 345 int p_pm; /* the maximum number of ports of that port speed in one PM */ 346 int n_group; /* the maximum number of PMs of that speed group */ 347 char *des; 348 } soc_speed_group_info_t; 349 350 extern int soc_tomahawk_port_lanes_consolidation(int unit, 351 soc_th_port_lanes_t *lanes_ctrl); 352 extern int soc_tomahawk_port_lanes_validate(int unit, 353 soc_th_port_lanes_t *lanes_ctrl); 354 extern int soc_tomahawk_port_lanes_set(int unit, 355 soc_th_port_lanes_t *lanes_ctrl); 356 extern int soc_tomahawk_port_lanes_get(int unit, soc_port_t port_base, 357 int *cur_lanes); 358 extern int soc_tomahawk_port_speed_update(int unit, soc_port_t port, int speed); 359 360 extern int soc_th_port_ie_speed_get(int unit, soc_port_t port, int *speed); 361 extern int soc_th_port_hg_speed_get(int unit, soc_port_t port, int *speed); 362 363 #ifndef BCM_SW_STATE_DUMP_DISABLE 364 extern void soc_th_flexport_sw_dump(int unit); 365 extern void soc_th_flexport_sw_pipe_speed_group_dump(int unit, 366 int pipe, 367 int speed_id); 368 #endif /* BCM_SW_STATE_DUMP_DISABLE */ 369 370 extern soc_error_t 371 soc_th_subsidiary_ports_get(int unit, soc_port_t port, soc_pbmp_t *pbmp); 372 373 soc_error_t 374 soc_th_port_speed_recover(int unit, soc_port_t port); 375 376 extern soc_error_t 377 soc_th_flexport_recover(int unit, soc_port_t port); 378 379 extern soc_error_t 380 soc_th_port_speed_supported(int unit, soc_port_t port, int speed); 381 extern soc_error_t 382 soc_th_speed_set_init_ctrl(int unit, soc_th_port_lanes_t *lanes_ctrl); 383 384 extern soc_error_t 385 soc_tomahawk_edb_buf_reset(int unit, soc_port_t port, int reset); 386 387 extern soc_error_t 388 soc_tomahawk_idb_buf_reset(int unit, soc_port_t port, int reset); 389 typedef int (*_soc_th_bst_hw_cb)(int unit); 390 extern int soc_th_set_bst_callback(int unit, _soc_th_bst_hw_cb cb); 391 extern int _soc_th_process_mmu_bst(int unit, int xpe, soc_field_t field); 392 393 extern int soc_th_ports_per_pm_get(int unit, int pm_id); 394 395 typedef void (*soc_th_mmu_config_buf_default_f)(int unit, 396 _soc_mmu_cfg_buf_t *buf, _soc_mmu_device_info_t *devcfg, 397 int lossless); 398 399 extern int 400 soc_th_port_oversub_ratio_get( 401 int unit, 402 soc_port_t port, 403 int* const ratio); 404 405 #define SOC_TH_MMU_PORT(u, p) _soc_th_mmu_port((u),(p)) 406 #define SOC_TH_MMU_PIPED_MEM_INDEX(u,p,m,off) \ 407 _soc_th_piped_mem_index((u),(p),(m),(off)) 408 #define PORT_BLOCK_BASE_PORT(port) \ 409 (1 + ((SOC_INFO(unit).port_l2p_mapping[port] - 1) & ~0x3)); 410 411 enum soc_th_port_ratio_e { 412 SOC_TH_PORT_RATIO_SINGLE, 413 SOC_TH_PORT_RATIO_DUAL_1_1, 414 SOC_TH_PORT_RATIO_DUAL_2_1, 415 SOC_TH_PORT_RATIO_DUAL_1_2, 416 SOC_TH_PORT_RATIO_TRI_023_2_1_1, 417 SOC_TH_PORT_RATIO_TRI_023_4_1_1, 418 SOC_TH_PORT_RATIO_TRI_012_1_1_2, 419 SOC_TH_PORT_RATIO_TRI_012_1_1_4, 420 SOC_TH_PORT_RATIO_QUAD, 421 SOC_TH_PORT_RATIO_COUNT 422 }; 423 424 enum soc_th_mixed_port_mode_e { 425 MIXED_DUAL_MODE_0 = 0, 426 MIXED_DUAL_MODE_20_0_20_0 = 1, 427 MIXED_DUAL_MODE_40_0_40_0 = 2, 428 MIXED_DUAL_MODE_50_0_50_0 = 3, 429 MIXED_DUAL_MODE_25_0_50_0 = 4, 430 MIXED_DUAL_MODE_50_0_25_0 = 5, 431 MIXED_DUAL_MODE_25_0_25_0 = 6 432 }; 433 434 enum soc_th_port_lanes_action_e { 435 ACT_NONE, 436 ACT_CONSOLIDATE, 437 ACT_MIGRATE 438 }; 439 440 enum th_l2_hash_key_type_e { 441 /* WARNING: values given match hardware register; do not modify */ 442 TH_L2_HASH_KEY_TYPE_BRIDGE = 0, 443 TH_L2_HASH_KEY_TYPE_SINGLE_CROSS_CONNECT = 1, 444 TH_L2_HASH_KEY_TYPE_DOUBLE_CROSS_CONNECT = 2, 445 TH_L2_HASH_KEY_TYPE_VFI = 3, 446 TH_L2_HASH_KEY_TYPE_VIF = 4, 447 TH_L2_HASH_KEY_TYPE_TRILL_NONUC_ACCESS = 5, 448 TH_L2_HASH_KEY_TYPE_TRILL_NONUC_NETWORK_LONG = 6, 449 TH_L2_HASH_KEY_TYPE_TRILL_NONUC_NETWORK_SHORT = 7, 450 TH_L2_HASH_KEY_TYPE_BFD = 8, 451 TH_L2_HASH_KEY_TYPE_PE_VID = 9, 452 TH_L2_HASH_KEY_TYPE_COUNT 453 }; 454 455 enum th_l3_hash_key_type_e { 456 /* WARNING: values given match hardware register; do not modify */ 457 TH_L3_HASH_KEY_TYPE_V4UC = 0, 458 TH_L3_HASH_KEY_TYPE_V4UC_EXT = 1, 459 TH_L3_HASH_KEY_TYPE_V6UC = 2, 460 TH_L3_HASH_KEY_TYPE_V6UC_EXT = 3, 461 TH_L3_HASH_KEY_TYPE_V4MC = 4, 462 TH_L3_HASH_KEY_TYPE_V6MC = 5, 463 /* 6 to 7 are not used */ 464 TH_L3_HASH_KEY_TYPE_TRILL = 8, 465 /* 9 to 17 are not used */ 466 TH_L3_HASH_KEY_TYPE_DST_NAT = 18, 467 TH_L3_HASH_KEY_TYPE_DST_NAPT = 19, 468 TH_L3_HASH_KEY_TYPE_COUNT 469 }; 470 471 enum th_fpem_hash_key_type_e { 472 /* WARNING: values given match hardware register; do not modify */ 473 TH_FPEM_HASH_KEY_TYPE_128B = 0, 474 TH_FPEM_HASH_KEY_TYPE_160B = 1, 475 TH_FPEM_HASH_KEY_TYPE_320B = 2, 476 TH_FPEM_HASH_KEY_TYPE_COUNT 477 }; 478 479 enum th_mpls_hash_key_type_e { 480 /* WARNING: values given match hardware register; do not modify */ 481 TH_MPLS_HASH_KEY_TYPE_MPLS = 0, 482 TH_MPLS_HASH_KEY_TYPE_MIM_NVP = 1, 483 TH_MPLS_HASH_KEY_TYPE_MIM_ISID = 2, 484 TH_MPLS_HASH_KEY_TYPE_MIM_ISID_SVP = 3, 485 TH_MPLS_HASH_KEY_TYPE_L2GRE_VPNID_SIP = 4, 486 TH_MPLS_HASH_KEY_TYPE_TRILL = 5, 487 TH_MPLS_HASH_KEY_TYPE_L2GRE_SIP = 6, 488 TH_MPLS_HASH_KEY_TYPE_L2GRE_VPNID = 7, 489 TH_MPLS_HASH_KEY_TYPE_VXLAN_SIP = 8, 490 TH_MPLS_HASH_KEY_TYPE_VXLAN_VPNID = 9, 491 TH_MPLS_HASH_KEY_TYPE_VXLAN_VPNID_SIP = 10, 492 TH_MPLS_HASH_KEY_TYPE_COUNT 493 }; 494 495 enum th_vlxlt_hash_key_type_e { 496 /* WARNING: values given match hardware register; do not modify */ 497 TH_VLXLT_HASH_KEY_TYPE_IVID_OVID = 0, 498 TH_VLXLT_HASH_KEY_TYPE_OTAG = 1, 499 TH_VLXLT_HASH_KEY_TYPE_ITAG = 2, 500 TH_VLXLT_HASH_KEY_TYPE_VLAN_MAC = 3, 501 TH_VLXLT_HASH_KEY_TYPE_OVID = 4, 502 TH_VLXLT_HASH_KEY_TYPE_IVID = 5, 503 TH_VLXLT_HASH_KEY_TYPE_PRI_CFI = 6, 504 TH_VLXLT_HASH_KEY_TYPE_HPAE = 7, 505 TH_VLXLT_HASH_KEY_TYPE_VIF = 8, 506 TH_VLXLT_HASH_KEY_TYPE_VIF_VLAN = 9, 507 TH_VLXLT_HASH_KEY_TYPE_VIF_CVLAN = 10, 508 TH_VLXLT_HASH_KEY_TYPE_VIF_OTAG = 11, 509 TH_VLXLT_HASH_KEY_TYPE_VIF_ITAG = 12, 510 TH_VLXLT_HASH_KEY_TYPE_L2GRE_DIP = 13, 511 TH_VLXLT_HASH_KEY_TYPE_VLAN_MAC_PORT = 14, 512 /* 15 to 17 are not used */ 513 TH_VLXLT_HASH_KEY_TYPE_VXLAN_DIP = 18, 514 TH_VLXLT_HASH_KEY_TYPE_COUNT 515 }; 516 517 enum th_evlxlt_hash_key_type_e { 518 /* WARNING: values given match hardware register; do not modify */ 519 TH_EVLXLT_HASH_KEY_TYPE_VLAN_XLATE = 0, 520 TH_EVLXLT_HASH_KEY_TYPE_VLAN_XLATE_DVP = 1, 521 /* 2 is not used */ 522 TH_EVLXLT_HASH_KEY_TYPE_ISID_XLATE = 3, 523 TH_EVLXLT_HASH_KEY_TYPE_ISID_DVP_XLATE = 4, 524 TH_EVLXLT_HASH_KEY_TYPE_L2GRE_VFI = 5, 525 TH_EVLXLT_HASH_KEY_TYPE_L2GRE_VFI_DVP = 6, 526 /* 7 is not used */ 527 TH_EVLXLT_HASH_KEY_TYPE_VXLAN_VFI = 8, 528 TH_EVLXLT_HASH_KEY_TYPE_VXLAN_VFI_DVP = 9, 529 TH_VELXLT_HASH_KEY_TYPE_COUNT 530 }; 531 532 extern int soc_tomahawk_hash_bank_count_get(int unit, soc_mem_t mem, 533 int *num_banks); 534 extern int soc_tomahawk_hash_bank_phy_bitmap_get(int unit, soc_mem_t mem, 535 uint32 *bitmap); 536 extern int soc_tomahawk_hash_bank_number_get(int unit, soc_mem_t mem, 537 int seq_num, int *bank_num); 538 extern int soc_tomahawk_hash_seq_number_get(int unit, soc_mem_t mem, 539 int bank_num, int *seq_num); 540 extern int soc_tomahawk_hash_bank_info_get(int unit, soc_mem_t mem, 541 int bank, 542 int *entries_per_bank, 543 int *entries_per_row, 544 int *entries_per_bucket, 545 int *bank_base, 546 int *bucket_offset); 547 extern int soc_th_hash_bucket_get(int unit, int mem, int bank, 548 uint32 *entry, uint32 *bucket); 549 extern int soc_th_hash_index_get(int unit, int mem, int bank, int bucket); 550 extern int soc_th_hash_offset_get(int unit, soc_mem_t mem, int bank, 551 int *hash_offset, int *use_lsb); 552 extern int soc_th_hash_offset_set(int unit, soc_mem_t mem, int bank, 553 int hash_offset, int use_lsb); 554 extern uint32 soc_th_l2x_hash(int unit, int bank, int hash_offset, 555 int use_lsb, int key_nbits, void *base_entry, 556 uint8 *key); 557 extern int soc_th_l2x_base_entry_to_key(int unit, int bank, uint32 *entry, 558 uint8 *key); 559 extern uint32 soc_th_l2x_entry_hash(int unit, int bank, int hash_offset, 560 int use_lsb, uint32 *entry); 561 extern uint32 soc_th_l2x_bank_entry_hash(int unit, int bank, uint32 *entry); 562 extern uint32 soc_th_l3x_hash(int unit, int bank, int hash_offset, 563 int use_lsb, int key_nbits, void *base_entry, 564 uint8 *key); 565 extern int soc_th_l3x_base_entry_to_key(int unit, int bank, uint32 *entry, 566 uint8 *key); 567 extern uint32 soc_th_l3x_entry_hash(int unit, int bank, int hash_offset, 568 int use_lsb, uint32 *entry); 569 extern uint32 soc_th_l3x_bank_entry_hash(int unit, int bank, uint32 *entry); 570 extern uint32 soc_th_exact_match_hash(int unit, int bank, int hash_offset, 571 int use_lsb, int key_nbits, 572 void *base_entry, uint8 *key); 573 extern int soc_th_exact_match_base_entry_to_key(int unit, int bank, 574 uint32 *entry, 575 uint8 *key); 576 extern uint32 soc_th_exact_match_entry_hash(int unit, int bank, 577 int hash_offset, int use_lsb, 578 uint32 *entry); 579 extern uint32 soc_th_exact_match_bank_entry_hash(int unit, int bank, 580 uint32 *entry); 581 extern uint32 soc_th_mpls_hash(int unit, int hash_sel, int key_nbits, 582 void *base_entry, uint8 *key); 583 extern int soc_th_mpls_base_entry_to_key(int unit, int bank, void *entry, 584 uint8 *key); 585 extern uint32 soc_th_mpls_entry_hash(int unit, int hash_sel, int bank, 586 uint32 *entry); 587 extern uint32 soc_th_mpls_bank_entry_hash(int unit, int bank, uint32 *entry); 588 extern uint32 soc_th_vlan_xlate_hash(int unit, int hash_sel, int key_nbits, 589 void *base_entry, uint8 *key); 590 extern int soc_th_vlan_xlate_base_entry_to_key(int unit, int bank, 591 void *entry, 592 uint8 *key); 593 extern uint32 soc_th_vlan_xlate_entry_hash(int unit, int hash_sel, int bank, 594 uint32 *entry); 595 extern uint32 soc_th_vlan_xlate_bank_entry_hash(int unit, int bank, 596 uint32 *entry); 597 extern uint32 soc_th_egr_vlan_xlate_hash(int unit, int hash_sel, 598 int key_nbits, void *base_entry, 599 uint8 *key); 600 extern int soc_th_egr_vlan_xlate_base_entry_to_key(int unit, int bank, 601 void *entry, 602 uint8 *key); 603 extern uint32 soc_th_egr_vlan_xlate_entry_hash(int unit, int hash_sel, 604 int bank, uint32 *entry); 605 extern uint32 soc_th_egr_vlan_xlate_bank_entry_hash(int unit, int bank, 606 uint32 *entry); 607 extern uint32 soc_th_ing_vp_vlan_member_hash(int unit, int hash_sel, 608 int key_nbits, void *base_entry, 609 uint8 *key); 610 extern int soc_th_ing_vp_vlan_member_base_entry_to_key(int unit, int bank, 611 void *entry, 612 uint8 *key); 613 extern uint32 soc_th_ing_vp_vlan_member_entry_hash(int unit, int hash_sel, 614 int bank, 615 uint32 *entry); 616 extern uint32 soc_th_ing_vp_vlan_member_bank_entry_hash(int unit, 617 int bank, 618 uint32 *entry); 619 extern uint32 soc_th_egr_vp_vlan_member_hash(int unit, int hash_sel, 620 int key_nbits, void *base_entry, 621 uint8 *key); 622 extern int soc_th_egr_vp_vlan_member_base_entry_to_key(int unit, int bank, 623 void *entry, 624 uint8 *key); 625 extern uint32 soc_th_egr_vp_vlan_member_entry_hash(int unit, int hash_sel, 626 int bank, 627 uint32 *entry); 628 extern uint32 soc_th_egr_vp_vlan_member_bank_entry_hash(int unit, 629 int bank, 630 uint32 *entry); 631 extern uint32 soc_th_ing_dnat_address_type_hash(int unit, int hash_sel, 632 int key_nbits, 633 void *base_entry, 634 uint8 *key); 635 extern int soc_th_ing_dnat_address_type_base_entry_to_key(int unit, 636 int bank, 637 void *entry, 638 uint8 *key); 639 extern uint32 soc_th_ing_dnat_address_type_entry_hash(int unit, 640 int hash_sel, 641 int bank, 642 uint32 *entry); 643 extern uint32 soc_th_ing_dnat_address_type_bank_entry_hash(int unit, 644 int bank, 645 uint32 *entry); 646 647 /* Special port number used by H/W */ 648 #define _SOC_TH_TDM_OVERSUB_TOKEN 0x22 649 #define _SOC_TH_TDM_NULL_TOKEN 0x23 650 #define _SOC_TH_TDM_IDL1_TOKEN 0x24 651 #define _SOC_TH_TDM_IDL2_TOKEN 0x25 652 #define _SOC_TH_TDM_UNUSED_TOKEN 0x3f 653 654 typedef enum { 655 SOC_TH_SCHED_MODE_UNKNOWN = 0, 656 SOC_TH_SCHED_MODE_STRICT, 657 SOC_TH_SCHED_MODE_WRR, 658 SOC_TH_SCHED_MODE_WERR 659 } soc_th_sched_mode_e; 660 661 typedef enum { 662 SOC_TH_NODE_LVL_ROOT = 0, 663 SOC_TH_NODE_LVL_L0, 664 SOC_TH_NODE_LVL_L1, 665 SOC_TH_NODE_LVL_L2, 666 SOC_TH_NODE_LVL_MAX 667 } soc_th_node_lvl_e; 668 669 typedef enum { 670 _SOC_TH_INDEX_STYLE_BUCKET, 671 _SOC_TH_INDEX_STYLE_BUCKET_MODE, 672 _SOC_TH_INDEX_STYLE_WRED, 673 _SOC_TH_INDEX_STYLE_WRED_DROP_THRESH, 674 _SOC_TH_INDEX_STYLE_SCHEDULER, 675 _SOC_TH_INDEX_STYLE_PERQ_XMT, 676 _SOC_TH_INDEX_STYLE_UCAST_DROP, 677 _SOC_TH_INDEX_STYLE_UCAST_QUEUE, 678 _SOC_TH_INDEX_STYLE_MCAST_QUEUE, 679 _SOC_TH_INDEX_STYLE_EXT_UCAST_QUEUE, 680 _SOC_TH_INDEX_STYLE_EGR_POOL, 681 _SOC_TH_INDEX_STYLE_COUNT 682 } soc_th_index_style_t; 683 684 typedef enum soc_th_drop_limit_alpha_value_e { 685 SOC_TH_COSQ_DROP_LIMIT_ALPHA_1_128, /* Use 1/128 as the alpha value for 686 dynamic threshold */ 687 SOC_TH_COSQ_DROP_LIMIT_ALPHA_1_64, /* Use 1/64 as the alpha value for 688 dynamic threshold */ 689 SOC_TH_COSQ_DROP_LIMIT_ALPHA_1_32, /* Use 1/32 as the alpha value for 690 dynamic threshold */ 691 SOC_TH_COSQ_DROP_LIMIT_ALPHA_1_16, /* Use 1/16 as the alpha value for 692 dynamic threshold */ 693 SOC_TH_COSQ_DROP_LIMIT_ALPHA_1_8, /* Use 1/8 as the alpha value for 694 dynamic threshold */ 695 SOC_TH_COSQ_DROP_LIMIT_ALPHA_1_4, /* Use 1/4 as the alpha value for 696 dynamic threshold */ 697 SOC_TH_COSQ_DROP_LIMIT_ALPHA_1_2, /* Use 1/2 as the alpha value for 698 dynamic threshold */ 699 SOC_TH_COSQ_DROP_LIMIT_ALPHA_1, /* Use 1 as the alpha value for dynamic 700 threshold */ 701 SOC_TH_COSQ_DROP_LIMIT_ALPHA_2, /* Use 2 as the alpha value for dynamic 702 threshold */ 703 SOC_TH_COSQ_DROP_LIMIT_ALPHA_4, /* Use 4 as the alpha value for dynamic 704 threshold */ 705 SOC_TH_COSQ_DROP_LIMIT_ALPHA_8, /* Use 8 as the alpha value for dynamic 706 threshold */ 707 SOC_TH_COSQ_DROP_LIMIT_ALPHA_COUNT /* Must be the last entry! */ 708 } soc_th_drop_limit_alpha_value_t; 709 710 #define _TH_PORTS_PER_PBLK 4 711 #define _TH_PBLKS_PER_PIPE 8 712 #define _TH_PIPES_PER_DEV 4 713 #define _TH_XPES_PER_DEV 4 714 #define _TH_MMU_PORTS_PER_PIPE 34 715 716 #define _TH_PBLKS_PER_DEV (_TH_PBLKS_PER_PIPE * _TH_PIPES_PER_DEV) 717 718 #define _TH_PORTS_PER_PIPE (_TH_PORTS_PER_PBLK * _TH_PBLKS_PER_PIPE) 719 #define _TH_PORTS_PER_DEV (_TH_PORTS_PER_PIPE * _TH_PIPES_PER_DEV) 720 /* Device port */ 721 /* 32 General device port + 1 CPU/Mng + 1 Loopback*/ 722 #define _TH_GDEV_PORTS_PER_PIPE 32 723 #define _TH_DEV_PORTS_PER_PIPE (_TH_GDEV_PORTS_PER_PIPE + 2) 724 725 #define _TH_SECTION_SIZE 32768 726 727 #define _TH_MMU_MAX_PACKET_BYTES 9416 /* bytes */ 728 #define _TH_MMU_PACKET_HEADER_BYTES 64 /* bytes */ 729 #define _TH_MMU_JUMBO_FRAME_BYTES 9216 /* bytes */ 730 #define _TH_MMU_DEFAULT_MTU_BYTES 1536 /* bytes */ 731 732 #define _TH_MMU_PHYSICAL_CELLS_PER_XPE 23040 /* Total Physical cells per XPE */ 733 #define _THP_MMU_PHYSICAL_CELLS_PER_XPE 29184 /* Total Physical cells per XPE for TH+*/ 734 735 #define _TH_MMU_TOTAL_CELLS_PER_XPE 20165 /* 4MB/XPE = 20165 cells/XPE */ 736 #define _THP_MMU_TOTAL_CELLS_PER_XPE 27727 /* 5.5MB/XPE = 27727 cells/XPE for TH+*/ 737 738 #define _TH_MMU_RSVD_CELLS_CFAP_PER_XPE 720 /* Reserved CFAP cells per XPE */ 739 #define _THP_MMU_RSVD_CELLS_CFAP_PER_XPE 912 /* Reserved CFAP cells per XPE for TH+*/ 740 741 #define _TH_MMU_TOTAL_CELLS (_TH_MMU_TOTAL_CELLS_PER_XPE * _TH_XPES_PER_DEV) 742 #define _THP_MMU_TOTAL_CELLS (_THP_MMU_TOTAL_CELLS_PER_XPE * _TH_XPES_PER_DEV) 743 744 #define _TH_MMU_PHYSICAL_CELLS (_TH_MMU_PHYSICAL_CELLS_PER_XPE * _TH_XPES_PER_DEV) 745 #define _THP_MMU_PHYSICAL_CELLS (_THP_MMU_PHYSICAL_CELLS_PER_XPE * _TH_XPES_PER_DEV) 746 747 #define _TH_MMU_BYTES_PER_CELL 208 /* bytes (1664 bits) */ 748 #define _TH_MMU_NUM_PG 8 749 #define _TH_MMU_NUM_POOL 4 750 #define _TH_MMU_NUM_RQE_QUEUES 11 751 #define _TH_MMU_NUM_INT_PRI 16 752 753 #define _TH_THDI_BUFFER_CELL_LIMIT_SP_MAX 19968 754 #define _THP_THDI_BUFFER_CELL_LIMIT_SP_MAX 27727 /* Higher for TH+ as per MMU settings 2.0 from Arch */ 755 #define _TH_THDI_HDRM_BUFFER_CELL_LIMIT_HP_MAX 19968 756 #define _THP_THDI_HDRM_BUFFER_CELL_LIMIT_HP_MAX 27727 /* Higher for TH+ as per MMU settings 2.0 from Arch */ 757 758 #define SOC_TH_MMU_CFG_QGROUP_MAX 36 759 760 #define SOC_TH_MMU_PORT_STRIDE 64 /* MMU Port number space per pipe */ 761 762 #define SOC_TH_MMU_GP_UCQ_NUM 320 /* Generl ports UC Queue Num in per Pipe Queue Space */ 763 #define SOC_TH_MMU_MGMT_UCQ_NUM 10 /* Management port UC Queues Num in Pipe Queue */ 764 #define SOC_TH_MMU_GP_MCQ_NUM 320 /* Generl ports MC Queue Num in per Pipe Queue Space */ 765 #define SOC_TH_MMU_LB_MCQ_NUM 10 /* Loopback port MC Queue Num in per Pipe Queue Space */ 766 #define SOC_TH_NUM_CPU_QUEUES 48 /* CPU port has 48 MC Queues */ 767 #define SOC_TH_NUM_UC_QUEUES_PER_PIPE ((SOC_TH_MMU_GP_UCQ_NUM) + \ 768 (SOC_TH_MMU_MGMT_UCQ_NUM)) /* Num UC Q's Per pipe 33*10 */ 769 #define SOC_TH_NUM_MC_QUEUES_PER_PIPE ((SOC_TH_MMU_GP_MCQ_NUM) + (SOC_TH_MMU_LB_MCQ_NUM) + \ 770 (SOC_TH_NUM_CPU_QUEUES)) /* Num MC Q's Per pipe (33*10)+48 */ 771 #define SOC_TH_MMU_CPU_MCQ_OFFSET ((SOC_TH_MMU_GP_UCQ_NUM) + (SOC_TH_MMU_MGMT_UCQ_NUM) + \ 772 (SOC_TH_MMU_GP_MCQ_NUM) + (SOC_TH_MMU_LB_MCQ_NUM)) 773 #define SOC_TH_MMU_MGMT_UCQ_OFFSET (SOC_TH_MMU_GP_UCQ_NUM) 774 #define SOC_TH_MMU_MGMT_MCQ_OFFSET ((SOC_TH_MMU_GP_UCQ_NUM) + (SOC_TH_MMU_MGMT_UCQ_NUM) + \ 775 (SOC_TH_MMU_GP_MCQ_NUM) + (SOC_TH_MMU_LB_MCQ_NUM)) 776 777 #define SOC_TH_MMU_MCQ_ENTRY_PER_XPE 8192 778 #define SOC_TH_MMU_RQE_ENTRY_PER_XPE 1024 779 #define SOC_TH_MMU_RQE_ENTRY_RSVD_PER_XPE 160 /* Reserved RQE QE per XPE */ 780 781 #define _TH_MMU_TOTAL_MCQ_ENTRY(unit) SOC_TH_MMU_MCQ_ENTRY_PER_XPE 782 #define _TH_MMU_TOTAL_RQE_ENTRY(unit) SOC_TH_MMU_RQE_ENTRY_PER_XPE 783 784 #define SOC_TH_STAT_ING_FLEX_POOL_MAX 20 785 786 #define _TH_ARRAY_MIN(arr, len, bmp, min) \ 787 do { \ 788 int i; \ 789 min = 0x7fffffff; \ 790 if (arr) { \ 791 for (i = 0; i < len; i ++) { \ 792 if ((bmp & (1 << i)) && (arr[i] < min)) { \ 793 min = arr[i]; \ 794 } \ 795 } \ 796 } \ 797 } while (0) 798 799 800 /* Function to Retrieve IFP memory mode. */ 801 extern int 802 soc_th_ser_mem_mode_get(int unit, soc_mem_t mem, int *mode); 803 804 extern int 805 soc_th_cosq_sched_mode_set(int unit, soc_port_t port, int level, int index, 806 soc_th_sched_mode_e mode, int weight, int mc); 807 extern int 808 soc_th_cosq_sched_mode_get(int unit, soc_port_t port, int level, int index, 809 soc_th_sched_mode_e *mode, int *weight, int mc); 810 extern int 811 soc_th_cosq_cpu_parent_set(int unit, int child_index, int child_level, 812 int parent_index); 813 extern int 814 soc_th_cosq_cpu_parent_get(int unit, int child_index, int child_level, 815 int *parent_index); 816 817 extern int 818 soc_tomahawk_mem_sram_info_get(int unit, soc_mem_t mem, int index, 819 _soc_ser_sram_info_t *sram_info); 820 821 #if defined(SER_TR_TEST_SUPPORT) 822 extern void soc_th_ser_test_register(int unit); 823 #endif /*defined(SER_TR_TEST_SUPPORT*/ 824 825 extern int soc_tomahawk_clear_all_port_data(int unit); 826 827 #define SOC_TH_NUM_EL_VLAN_XLATE 4 828 829 #define SOC_TH_NUM_EL_EGR_VLAN_XLATE 4 830 831 #define SOC_TH_NUM_EL_ING_L3_NEXT_HOP 4 832 #define SOC_TH_RAM_OFFSET_ING_L3_NEXT_HOP 8192 833 834 #define SOC_TH_NUM_ENTRIES_L2_BANK 8192 835 #define SOC_TH_NUM_ENTRIES_L3_BANK(u) (SOC_IS_TOMAHAWK3(u) ? 16384 : 8192) 836 837 #define SOC_TH_NUM_EL_SHARED 4 838 #define SOC_TH_NUM_ENTRIES_XOR_BANK 8192 839 #define SOC_TH_LP_ENTRIES_IN_XOR_BANK 2048 840 #define SOC_TH_LP_ENTRIES_IN_UFT_BANK 8192 841 842 #define SOC_TH_ALPM_MAX_BKTS(u) (SOC_IS_TOMAHAWK(u) ? 8192 : 16384) 843 #define SOC_TH_ALPM_BKT_MASK(u) (SOC_IS_TOMAHAWK(u) ? 0x1FFF : 0x3FFF) 844 #define SOC_TH_ALPM_BKT_OFFFSET 2048 845 #define SOC_TH_ALPM_MODE0_BKT_MASK 0x38003 846 #define SOC_TH_ALPM_MODE1_BKT_MASK SOC_TH_ALPM_MODE0_BKT_MASK >> 1 847 848 #define _SOC_TH_L2_MGMT_INTR_MASK 0x2 849 #define _SOC_TH_FUNC_INTR_MASK _SOC_TH_L2_MGMT_INTR_MASK 850 851 extern void soc_th_set_alpm_banks(int unit, int alpm_banks); 852 extern int soc_th_get_alpm_banks(int unit); 853 extern int soc_tomahawk_alpm_mode_get(int unit); 854 855 extern int 856 soc_tomahawk_temperature_monitor_get(int unit, int temperature_max, 857 soc_switch_temperature_monitor_t *temperature_array, 858 int *temperature_count); 859 extern void 860 soc_tomahawk_temperature_intr(void *unit_vp, void *d1, void *d2, 861 void *d3, void *d4); 862 extern int 863 soc_tomahawk_show_voltage(int unit); 864 extern void 865 soc_tomahawk_process_func_intr(void *unit_vp, void *d1, void *d2, void *d3, void *d4); 866 867 extern void 868 _soc_tomahawk_alpm_bkt_view_set(int unit, int index, soc_mem_t view); 869 extern soc_mem_t 870 _soc_tomahawk_alpm_bkt_view_get(int unit, int index); 871 872 #define _SOC_TH_UNIT_VALIDATE(unit) \ 873 if ( !(((unit) >= 0) && ((unit) <= SOC_MAX_NUM_DEVICES)) ) \ 874 return SOC_E_UNIT; 875 876 #define OUT 877 #define IN_OUT 878 879 /* 880 ============================= 881 TH ASF (cut-thru forwarding) 882 ============================= 883 */ 884 885 /* ASF Modes */ 886 typedef enum { 887 _SOC_TH_ASF_MODE_SAF = 0, /* store-and-forward */ 888 _SOC_TH_ASF_MODE_SAME_SPEED = 1, /* same speed CT */ 889 _SOC_TH_ASF_MODE_SLOW_TO_FAST = 2, /* slow to fast CT */ 890 _SOC_TH_ASF_MODE_FAST_TO_SLOW = 3, /* fast to slow CT */ 891 _SOC_TH_ASF_MODE_CFG_UPDATE = 4, /* internal cfg updates */ 892 _SOC_TH_ASF_MODE_INIT = 5, /* init */ 893 _SOC_TH_ASF_MODE_UNSUPPORTED = 6 894 } soc_th_asf_mode_e; 895 896 /* ASF MMU Cell Buffer Allocation Profiles */ 897 typedef enum { 898 _SOC_TH_ASF_MEM_PROFILE_NONE = 0, /* No cut-through support */ 899 _SOC_TH_ASF_MEM_PROFILE_SIMILAR = 1, /* Similar Speed Alloc Profile */ 900 _SOC_TH_ASF_MEM_PROFILE_EXTREME = 2 /* Extreme Speed Alloc Profile */ 901 } soc_th_asf_mem_profile_e; 902 903 extern int 904 soc_th_asf_init_start(int unit); 905 906 extern int 907 soc_th_asf_init_done(int unit); 908 909 extern int 910 soc_th_port_asf_init( 911 int unit, 912 soc_port_t port, 913 int port_speed, 914 soc_th_asf_mode_e mode); 915 916 extern int 917 soc_th_asf_deinit(int unit); 918 919 extern int 920 soc_th_port_asf_xmit_start_count_set( 921 int unit, 922 soc_port_t port, 923 int port_speed, 924 soc_th_asf_mode_e mode, 925 uint8 extra_cells); 926 927 extern int 928 soc_th_port_asf_mode_get( 929 int unit, 930 soc_port_t port, 931 int port_speed, 932 OUT soc_th_asf_mode_e* const mode); 933 934 extern int 935 soc_th_port_asf_mode_set( 936 int unit, 937 soc_port_t port, 938 int port_speed, 939 soc_th_asf_mode_e mode); 940 941 extern int 942 soc_th_port_asf_params_set( 943 int unit, 944 soc_port_t port, 945 int port_speed, 946 soc_th_asf_mode_e mode, 947 uint8 bubble_mop_disable, 948 uint8 ca_thresh, 949 int speed_encoding); 950 951 extern int 952 soc_th_port_asf_speed_to_mmu_cell_credit( 953 int unit, 954 soc_port_t port, 955 int port_speed, 956 OUT uint32 *mmu_cell_credit); 957 extern int 958 soc_th_port_asf_mmu_cell_credit_to_speed( 959 int unit, 960 soc_port_t port, 961 uint8 mmu_cell_credit, 962 OUT int *port_speed); 963 964 extern pbmp_t * 965 soc_th_port_asf_pause_bpmp_get(int unit); 966 967 #ifdef BCM_WARM_BOOT_SUPPORT 968 extern int 969 soc_th_asf_wb_memsz_get( 970 int unit, 971 OUT uint32* const wb_mem_sz, 972 uint16 scache_ver); 973 974 extern int 975 soc_th_asf_wb_sync( 976 int unit, 977 IN_OUT uint8* const wb_data); 978 979 extern int 980 soc_th_asf_wb_recover( 981 int unit, 982 uint8* const wb_data, 983 uint16 scache_ver); 984 #endif 985 986 extern int 987 soc_th_asf_pbmp_get(int unit); 988 989 extern int 990 soc_th_port_asf_show( 991 int unit, 992 soc_port_t port, 993 int port_speed); 994 995 extern int 996 soc_th_asf_config_dump(int unit); 997 998 extern int 999 soc_th_port_asf_config_dump( 1000 int unit, 1001 soc_port_t port, 1002 int port_speed); 1003 1004 extern int 1005 soc_th_port_asf_detach( 1006 int unit, 1007 soc_port_t port); 1008 1009 /* 1010 ========================== 1011 TH Switch Latency Bypass 1012 ========================== 1013 */ 1014 1015 /* resource type */ 1016 typedef enum { 1017 _SOC_TH_REG = 0, 1018 _SOC_TH_MEM = 1 1019 } soc_th_resource_e; 1020 1021 /* protocol table configs */ 1022 typedef struct _soc_th_latency_table_cfg_s { 1023 int l2_entries; 1024 int fixed_l2_entries; 1025 int shared_l2_banks; 1026 int l3_entries; 1027 int fixed_l3_entries; 1028 int shared_l3_banks; 1029 int fpem_entries; 1030 int shared_fpem_banks; 1031 int alpm_enable; 1032 int max_tcams; 1033 int tcam_depth; 1034 } soc_th_latency_table_cfg_t; 1035 1036 1037 extern int 1038 soc_th_latency_init(int unit); 1039 1040 extern int 1041 soc_th_latency_deinit(int unit); 1042 1043 extern int 1044 soc_th_latency_get( 1045 int unit, 1046 OUT int* const latency); 1047 1048 extern int 1049 soc_th_latency_bypassed( 1050 int unit, 1051 soc_feature_t feature); 1052 1053 extern int 1054 soc_th_latency_mem_avail( 1055 int unit, 1056 soc_mem_t mem, 1057 int latency); 1058 1059 extern int 1060 soc_th_latency_reg_avail( 1061 int unit, 1062 soc_reg_t reg, 1063 int latency); 1064 1065 extern int 1066 soc_th_latency_mem_filter(int unit); 1067 1068 extern int 1069 soc_th_latency_reg_filter(int unit); 1070 1071 #ifdef BCM_WARM_BOOT_SUPPORT 1072 extern int 1073 soc_th_latency_wb_memsz_get( 1074 int unit, 1075 OUT uint32* const wb_mem_sz, 1076 uint16 scache_ver); 1077 1078 extern int 1079 soc_th_latency_wb_sync( 1080 int unit, 1081 IN_OUT uint8* const wb_data); 1082 1083 extern int 1084 soc_th_latency_wb_recover( 1085 int unit, 1086 uint8* const wb_data, 1087 uint16 scache_ver); 1088 1089 extern int 1090 soc_th_latency_wb_reinit(int unit, int level); 1091 #endif 1092 1093 extern int 1094 soc_th_latency_show(int unit); 1095 1096 extern int 1097 soc_th_latency_diag(int unit); 1098 1099 1100 extern uint32 _soc_th_temp_mon_mask[SOC_MAX_NUM_DEVICES]; 1101 1102 #ifdef INCLUDE_AVS 1103 extern int soc_th_avs_init(int unit); 1104 extern soc_error_t soc_th_avs_vcore_get(int unit, uint32 *voltage); 1105 extern soc_error_t soc_th_avs_vcore_set(int unit, uint32 voltage); 1106 extern soc_error_t soc_th_avs_vcore_init(int unit); 1107 extern soc_error_t soc_th_avs_vcore_deinit(int unit); 1108 #endif /* INCLUDE_AVS */ 1109 1110 extern void _soc_tomahawk_speed_to_ovs_class_mapping(int unit, int speed, int *ovs_class); 1111 extern void _soc_tomahawk_speed_to_slot_mapping(int unit, int speed, int *slot); 1112 extern int _soc_tomahawk_tdm_idb_opportunistic_set(int unit, int enable); 1113 extern int _soc_tomahawk_tdm_idb_hsp_set(int unit, int all_pipes); 1114 extern int _soc_tomahawk_tdm_mmu_opportunistic_set(int unit, int enable); 1115 extern int _soc_tomahawk_tdm_mmu_hsp_set(int unit, int all_pipes); 1116 1117 #ifdef PORTMOD_SUPPORT 1118 extern int soc_th_portctrl_pm_portmod_init(int unit); 1119 extern int soc_th_portctrl_pm_portmod_deinit(int unit); 1120 extern int soc_th_portctrl_pm_port_phyaddr_get(int unit, soc_port_t port); 1121 #endif 1122 1123 extern int soc_th_field_mem_mode_get(int unit, soc_mem_t mem, int *mode); 1124 extern int soc_mem_field_nw_tcam_prio_order_index_get(int unit, soc_mem_t mem, 1125 int *tcam_idx); 1126 extern int soc_th_ifp_mem_write(int unit, soc_mem_t mem, int copyno, int index, 1127 void *entry_data); 1128 extern int soc_th_ifp_mem_read(int unit, soc_mem_t mem, int copyno, int index, 1129 void *entry_data); 1130 1131 extern int soc_th_iss_log_to_phy_bank_map_shadow_get(int unit, uint32 *shadow_val); 1132 extern int soc_th_iss_log_to_phy_bank_map_shadow_set(int unit, uint32 shadow_val); 1133 1134 extern int soc_th_ser_single_bit_error_enable_set(int unit, int enable); 1135 1136 extern int soc_th_ser_single_bit_error_enable_get(int unit, int *enable); 1137 1138 extern int soc_asf_register_linkscan_cb(int unit); 1139 1140 extern int soc_th_reset_serdes(int unit, int port, int reset_delay_us); 1141 1142 extern void _soc_th_lpm_view_set(int unit, int index, soc_mem_t view, int pair_lpm); 1143 extern soc_mem_t _soc_th_lpm_view_get(int unit, int index, int pair_lpm); 1144 1145 #endif /* !_SOC_TOMAHAWK_H_ */