timesync.h (32433B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * This file defines common network port modes. 8 * 9 * Its contents are not used directly by applications; it is used only 10 * by header files of parent APIs which need to define port modes. 11 */ 12 13 #ifndef _SOC_TIMESYNC_H 14 #define _SOC_TIMESYNC_H 15 16 #include <shared/port.h> 17 18 typedef enum soc_port_phy_timesync_timer_mode_e { 19 SOC_PORT_PHY_TIMESYNC_TIMER_MODE_NONE = 20 _SHR_PORT_PHY_TIMESYNC_TIMER_MODE_NONE, 21 SOC_PORT_PHY_TIMESYNC_TIMER_MODE_32BIT = 22 _SHR_PORT_PHY_TIMESYNC_TIMER_MODE_32BIT, 23 SOC_PORT_PHY_TIMESYNC_TIMER_MODE_48BIT = 24 _SHR_PORT_PHY_TIMESYNC_TIMER_MODE_48BIT, 25 SOC_PORT_PHY_TIMESYNC_TIMER_MODE_64BIT = 26 _SHR_PORT_PHY_TIMESYNC_TIMER_MODE_64BIT, 27 SOC_PORT_PHY_TIMESYNC_TIMER_MODE_80BIT = 28 _SHR_PORT_PHY_TIMESYNC_TIMER_MODE_80BIT 29 } soc_port_phy_timesync_timer_mode_t; 30 31 /* Definitions for compatibility with old drivers */ 32 33 #define SOC_PORT_TIMESYNC_ENABLE _SHR_PORT_PHY_TIMESYNC_ENABLE 34 #define SOC_PORT_TIMESYNC_CAPTURE_TS_ENABLE _SHR_PORT_PHY_TIMESYNC_CAPTURE_TS_ENABLE 35 #define SOC_PORT_TIMESYNC_HEARTBEAT_TS_ENABLE _SHR_PORT_PHY_TIMESYNC_HEARTBEAT_TS_ENABLE 36 #define SOC_PORT_TIMESYNC_RX_CRC_ENABLE _SHR_PORT_PHY_TIMESYNC_RX_CRC_ENABLE 37 #define SOC_PORT_TIMESYNC_8021AS_ENABLE _SHR_PORT_PHY_TIMESYNC_8021AS_ENABLE 38 #define SOC_PORT_TIMESYNC_L2_ENABLE _SHR_PORT_PHY_TIMESYNC_L2_ENABLE 39 #define SOC_PORT_TIMESYNC_IP4_ENABLE _SHR_PORT_PHY_TIMESYNC_IP4_ENABLE 40 #define SOC_PORT_TIMESYNC_IP6_ENABLE _SHR_PORT_PHY_TIMESYNC_IP6_ENABLE 41 #define SOC_PORT_TIMESYNC_CLOCK_SRC_EXT _SHR_PORT_PHY_TIMESYNC_CLOCK_SRC_EXT 42 43 44 #define SOC_PORT_TIMESYNC_EVENT_MESSAGE_EGRESS_MODE_NONE \ 45 _SHR_PORT_PHY_TIMESYNC_EVENT_MESSAGE_EGRESS_MODE_NONE 46 #define SOC_PORT_TIMESYNC_EVENT_MESSAGE_EGRESS_MODE_UPDATE_CORRECTIONFIELD \ 47 _SHR_PORT_PHY_TIMESYNC_EVENT_MESSAGE_EGRESS_MODE_UPDATE_CORRECTIONFIELD 48 #define SOC_PORT_TIMESYNC_EVENT_MESSAGE_EGRESS_MODE_REPLACE_CORRECTIONFIELD_ORIGIN \ 49 _SHR_PORT_PHY_TIMESYNC_EVENT_MESSAGE_EGRESS_MODE_REPLACE_CORRECTIONFIELD_ORIGIN 50 #define SOC_PORT_TIMESYNC_EVENT_MESSAGE_EGRESS_MODE_CAPTURE_TIMESTAMP \ 51 _SHR_PORT_PHY_TIMESYNC_EVENT_MESSAGE_EGRESS_MODE_CAPTURE_TIMESTAMP 52 53 #define SOC_PORT_TIMESYNC_EVENT_MESSAGE_INGRESS_MODE_NONE \ 54 _SHR_PORT_PHY_TIMESYNC_EVENT_MESSAGE_INGRESS_MODE_NONE 55 #define SOC_PORT_TIMESYNC_EVENT_MESSAGE_INGRESS_MODE_UPDATE_CORRECTIONFIELD \ 56 _SHR_PORT_PHY_TIMESYNC_EVENT_MESSAGE_INGRESS_MODE_UPDATE_CORRECTIONFIELD 57 #define SOC_PORT_TIMESYNC_EVENT_MESSAGE_INGRESS_MODE_INSERT_TIMESTAMP \ 58 _SHR_PORT_PHY_TIMESYNC_EVENT_MESSAGE_INGRESS_MODE_INSERT_TIMESTAMP 59 #define SOC_PORT_TIMESYNC_EVENT_MESSAGE_INGRESS_MODE_INSERT_DELAYTIME \ 60 _SHR_PORT_PHY_TIMESYNC_EVENT_MESSAGE_INGRESS_MODE_INSERT_DELAYTIME 61 62 #define SOC_PORT_TIMESYNC_MODE_FREE \ 63 _SHR_PORT_PHY_TIMESYNC_MODE_FREE 64 #define SOC_PORT_TIMESYNC_MODE_SYNCIN \ 65 _SHR_PORT_PHY_TIMESYNC_MODE_SYNCIN 66 #define SOC_PORT_TIMESYNC_MODE_CPU \ 67 _SHR_PORT_PHY_TIMESYNC_MODE_CPU 68 69 #define SOC_PORT_CONTROL_TIMESYNC_CAPTURE_TIMESTAMP \ 70 _SHR_PORT_CONTROL_PHY_TIMESYNC_CAPTURE_TIMESTAMP 71 #define SOC_PORT_CONTROL_TIMESYNC_HEARTBEAT_TIMESTAMP \ 72 _SHR_PORT_CONTROL_PHY_TIMESYNC_HEARTBEAT_TIMESTAMP 73 #define SOC_PORT_CONTROL_TIMESYNC_NCOADDEND \ 74 _SHR_PORT_CONTROL_PHY_TIMESYNC_NCOADDEND 75 #define SOC_PORT_CONTROL_TIMESYNC_FRAMESYNC \ 76 _SHR_PORT_CONTROL_PHY_TIMESYNC_FRAMESYNC 77 #define SOC_PORT_CONTROL_TIMESYNC_LOCAL_TIME \ 78 _SHR_PORT_CONTROL_PHY_TIMESYNC_LOCAL_TIME 79 80 typedef _shr_port_phy_timesync_event_message_egress_mode_t soc_port_timesync_event_message_egress_mode_t; 81 typedef _shr_port_phy_timesync_event_message_ingress_mode_t soc_port_timesync_event_message_ingress_mode_t; 82 typedef _shr_port_phy_timesync_global_mode_t soc_port_timesync_global_mode_t; 83 typedef _shr_port_control_phy_timesync_t soc_port_control_timesync_t; 84 85 /* End of compatibility definitions */ 86 87 #define SOC_PORT_PHY_TIMESYNC_EVENT_MESSAGE_EGRESS_MODE_NONE \ 88 _SHR_PORT_PHY_TIMESYNC_EVENT_MESSAGE_EGRESS_MODE_NONE 89 #define SOC_PORT_PHY_TIMESYNC_EVENT_MESSAGE_EGRESS_MODE_UPDATE_CORRECTIONFIELD \ 90 _SHR_PORT_PHY_TIMESYNC_EVENT_MESSAGE_EGRESS_MODE_UPDATE_CORRECTIONFIELD 91 #define SOC_PORT_PHY_TIMESYNC_EVENT_MESSAGE_EGRESS_MODE_REPLACE_CORRECTIONFIELD_ORIGIN \ 92 _SHR_PORT_PHY_TIMESYNC_EVENT_MESSAGE_EGRESS_MODE_REPLACE_CORRECTIONFIELD_ORIGIN 93 #define SOC_PORT_PHY_TIMESYNC_EVENT_MESSAGE_EGRESS_MODE_CAPTURE_TIMESTAMP \ 94 _SHR_PORT_PHY_TIMESYNC_EVENT_MESSAGE_EGRESS_MODE_CAPTURE_TIMESTAMP 95 96 #define SOC_PORT_PHY_TIMESYNC_EVENT_MESSAGE_INGRESS_MODE_NONE \ 97 _SHR_PORT_PHY_TIMESYNC_EVENT_MESSAGE_INGRESS_MODE_NONE 98 #define SOC_PORT_PHY_TIMESYNC_EVENT_MESSAGE_INGRESS_MODE_UPDATE_CORRECTIONFIELD \ 99 _SHR_PORT_PHY_TIMESYNC_EVENT_MESSAGE_INGRESS_MODE_UPDATE_CORRECTIONFIELD 100 #define SOC_PORT_PHY_TIMESYNC_EVENT_MESSAGE_INGRESS_MODE_INSERT_TIMESTAMP \ 101 _SHR_PORT_PHY_TIMESYNC_EVENT_MESSAGE_INGRESS_MODE_INSERT_TIMESTAMP 102 #define SOC_PORT_PHY_TIMESYNC_EVENT_MESSAGE_INGRESS_MODE_INSERT_DELAYTIME \ 103 _SHR_PORT_PHY_TIMESYNC_EVENT_MESSAGE_INGRESS_MODE_INSERT_DELAYTIME 104 105 #define SOC_PORT_PHY_TIMESYNC_MODE_FREE _SHR_PORT_PHY_TIMESYNC_MODE_FREE 106 #define SOC_PORT_PHY_TIMESYNC_MODE_SYNCIN _SHR_PORT_PHY_TIMESYNC_MODE_SYNCIN 107 #define SOC_PORT_PHY_TIMESYNC_MODE_CPU _SHR_PORT_PHY_TIMESYNC_MODE_CPU 108 109 #define SOC_PORT_PHY_TIMESYNC_FRAMESYNC_NONE _SHR_PORT_PHY_TIMESYNC_FRAMESYNC_NONE 110 #define SOC_PORT_PHY_TIMESYNC_FRAMESYNC_SYNCIN0 _SHR_PORT_PHY_TIMESYNC_FRAMESYNC_SYNCIN0 111 #define SOC_PORT_PHY_TIMESYNC_FRAMESYNC_SYNCIN1 _SHR_PORT_PHY_TIMESYNC_FRAMESYNC_SYNCIN1 112 #define SOC_PORT_PHY_TIMESYNC_FRAMESYNC_SYNCOUT _SHR_PORT_PHY_TIMESYNC_FRAMESYNC_SYNCOUT 113 #define SOC_PORT_PHY_TIMESYNC_FRAMESYNC_CPU _SHR_PORT_PHY_TIMESYNC_FRAMESYNC_CPU 114 115 116 #define SOC_PORT_PHY_TIMESYNC_SYNCOUT_DISABLE _SHR_PORT_PHY_TIMESYNC_SYNCOUT_DISABLE 117 #define SOC_PORT_PHY_TIMESYNC_SYNCOUT_ONE_TIME _SHR_PORT_PHY_TIMESYNC_SYNCOUT_ONE_TIME 118 #define SOC_PORT_PHY_TIMESYNC_SYNCOUT_PULSE_TRAIN _SHR_PORT_PHY_TIMESYNC_SYNCOUT_PULSE_TRAIN 119 #define SOC_PORT_PHY_TIMESYNC_SYNCOUT_PULSE_TRAIN_WITH_SYNC _SHR_PORT_PHY_TIMESYNC_SYNCOUT_PULSE_TRAIN_WITH_SYNC 120 121 122 #define SOC_PORT_PHY_TIMESYNC_VALID_FLAGS _SHR_PORT_PHY_TIMESYNC_VALID_FLAGS /* Flags field is valid */ 123 #define SOC_PORT_PHY_TIMESYNC_VALID_ITPID _SHR_PORT_PHY_TIMESYNC_VALID_ITPID /* itpid is valid */ 124 #define SOC_PORT_PHY_TIMESYNC_VALID_OTPID _SHR_PORT_PHY_TIMESYNC_VALID_OTPID /* otpid is valid */ 125 #define SOC_PORT_PHY_TIMESYNC_VALID_OTPID2 _SHR_PORT_PHY_TIMESYNC_VALID_OTPID2 /* otpid2 is valid */ 126 #define SOC_PORT_PHY_TIMESYNC_VALID_GMODE _SHR_PORT_PHY_TIMESYNC_VALID_GMODE /* gmode is valid */ 127 #define SOC_PORT_PHY_TIMESYNC_VALID_FRAMESYNC_MODE _SHR_PORT_PHY_TIMESYNC_VALID_FRAMESYNC_MODE /* framesync mode is 128 valid */ 129 #define SOC_PORT_PHY_TIMESYNC_VALID_SYNCOUT_MODE _SHR_PORT_PHY_TIMESYNC_VALID_SYNCOUT_MODE /* syncout mode is valid */ 130 #define SOC_PORT_PHY_TIMESYNC_VALID_TS_DIVIDER _SHR_PORT_PHY_TIMESYNC_VALID_TS_DIVIDER /* ts divider mode is 131 valid */ 132 #define SOC_PORT_PHY_TIMESYNC_VALID_ORIGINAL_TIMECODE _SHR_PORT_PHY_TIMESYNC_VALID_ORIGINAL_TIMECODE /* original timecode is 133 valid */ 134 #define SOC_PORT_PHY_TIMESYNC_VALID_TX_TIMESTAMP_OFFSET _SHR_PORT_PHY_TIMESYNC_VALID_TX_TIMESTAMP_OFFSET /* tx timestamp offset is 135 valid */ 136 #define SOC_PORT_PHY_TIMESYNC_VALID_RX_TIMESTAMP_OFFSET _SHR_PORT_PHY_TIMESYNC_VALID_RX_TIMESTAMP_OFFSET /* rx timestamp offset is 137 valid */ 138 #define SOC_PORT_PHY_TIMESYNC_VALID_TX_SYNC_MODE _SHR_PORT_PHY_TIMESYNC_VALID_TX_SYNC_MODE /* tx sync mode is valid */ 139 #define SOC_PORT_PHY_TIMESYNC_VALID_TX_DELAY_REQUEST_MODE _SHR_PORT_PHY_TIMESYNC_VALID_TX_DELAY_REQUEST_MODE /* tx delay request mode 140 is valid */ 141 #define SOC_PORT_PHY_TIMESYNC_VALID_TX_PDELAY_REQUEST_MODE _SHR_PORT_PHY_TIMESYNC_VALID_TX_PDELAY_REQUEST_MODE /* tx pdelay request mode 142 is valid */ 143 #define SOC_PORT_PHY_TIMESYNC_VALID_TX_PDELAY_RESPONSE_MODE _SHR_PORT_PHY_TIMESYNC_VALID_TX_PDELAY_RESPONSE_MODE /* tx pdelay response 144 mode is valid */ 145 #define SOC_PORT_PHY_TIMESYNC_VALID_RX_SYNC_MODE _SHR_PORT_PHY_TIMESYNC_VALID_RX_SYNC_MODE /* rx sync mode is valid */ 146 #define SOC_PORT_PHY_TIMESYNC_VALID_RX_DELAY_REQUEST_MODE _SHR_PORT_PHY_TIMESYNC_VALID_RX_DELAY_REQUEST_MODE /* rx delay request mode 147 is valid */ 148 #define SOC_PORT_PHY_TIMESYNC_VALID_RX_PDELAY_REQUEST_MODE _SHR_PORT_PHY_TIMESYNC_VALID_RX_PDELAY_REQUEST_MODE /* rx pdelay request mode 149 is valid */ 150 #define SOC_PORT_PHY_TIMESYNC_VALID_RX_PDELAY_RESPONSE_MODE _SHR_PORT_PHY_TIMESYNC_VALID_RX_PDELAY_RESPONSE_MODE /* rx pdelay response 151 mode is valid */ 152 #define SOC_PORT_PHY_TIMESYNC_VALID_MPLS_CONTROL _SHR_PORT_PHY_TIMESYNC_VALID_MPLS_CONTROL /* mpls control is valid */ 153 #define SOC_PORT_PHY_TIMESYNC_VALID_RX_LINK_DELAY _SHR_PORT_PHY_TIMESYNC_VALID_RX_LINK_DELAY /* rx link delay is valid */ 154 #define SOC_PORT_PHY_TIMESYNC_VALID_PHY_1588_SYNC_FREQ _SHR_PORT_PHY_TIMESYNC_VALID_PHY_1588_SYNC_FREQ /* sync freq is valid */ 155 #define SOC_PORT_PHY_TIMESYNC_VALID_PHY_1588_DPLL_K1 _SHR_PORT_PHY_TIMESYNC_VALID_PHY_1588_DPLL_K1 /* phy 1588 dpll k1 is 156 valid */ 157 #define SOC_PORT_PHY_TIMESYNC_VALID_PHY_1588_DPLL_K2 _SHR_PORT_PHY_TIMESYNC_VALID_PHY_1588_DPLL_K2 /* phy 1588 dpll k2 is 158 valid */ 159 #define SOC_PORT_PHY_TIMESYNC_VALID_PHY_1588_DPLL_K3 _SHR_PORT_PHY_TIMESYNC_VALID_PHY_1588_DPLL_K3 /* phy 1588 dpll k3 is 160 valid */ 161 #define SOC_PORT_PHY_TIMESYNC_VALID_PHY_1588_DPLL_LOOP_FILTER _SHR_PORT_PHY_TIMESYNC_VALID_PHY_1588_DPLL_LOOP_FILTER /* phy 1588 dpll loop 162 filter is valid */ 163 #define SOC_PORT_PHY_TIMESYNC_VALID_PHY_1588_DPLL_REF_PHASE _SHR_PORT_PHY_TIMESYNC_VALID_PHY_1588_DPLL_REF_PHASE /* phy 1588 dpll ref 164 phase is valid */ 165 #define SOC_PORT_PHY_TIMESYNC_VALID_PHY_1588_DPLL_REF_PHASE_DELTA _SHR_PORT_PHY_TIMESYNC_VALID_PHY_1588_DPLL_REF_PHASE_DELTA /* phy 1588 dpll ref 166 phase delta is valid */ 167 #define SOC_PORT_PHY_TIMESYNC_VALID_PHY_1588_INBAND_CONTROL _SHR_PORT_PHY_TIMESYNC_VALID_PHY_1588_INBAND_CONTROL /* inband ts control is valid */ 168 #define SOC_PORT_PHY_TIMESYNC_VALID_TIMER_ADJUSTMENT _SHR_PORT_PHY_TIMESYNC_VALID_TIMER_ADJUSTMENT /* direct timer adjustment is valid */ 169 170 #define SOC_PORT_PHY_TIMESYNC_ENABLE _SHR_PORT_PHY_TIMESYNC_ENABLE /* Enable Time Synchronization Interface */ 171 #define SOC_PORT_PHY_TIMESYNC_ONE_STEP_ENABLE _SHR_PORT_PHY_TIMESYNC_ONE_STEP_ENABLE /* Enable One step Timesamping in Serdes */ 172 #define SOC_PORT_PHY_TIMESYNC_CAPTURE_TS_ENABLE _SHR_PORT_PHY_TIMESYNC_CAPTURE_TS_ENABLE /* Enable Packet Timestamping */ 173 #define SOC_PORT_PHY_TIMESYNC_HEARTBEAT_TS_ENABLE _SHR_PORT_PHY_TIMESYNC_HEARTBEAT_TS_ENABLE /* Enable Heartbeat Timestamping */ 174 #define SOC_PORT_PHY_TIMESYNC_RX_CRC_ENABLE _SHR_PORT_PHY_TIMESYNC_RX_CRC_ENABLE /* Enable CRC checking */ 175 #define SOC_PORT_PHY_TIMESYNC_8021AS_ENABLE _SHR_PORT_PHY_TIMESYNC_8021AS_ENABLE /* Enable IEEE802.1AS mode */ 176 #define SOC_PORT_PHY_TIMESYNC_L2_ENABLE _SHR_PORT_PHY_TIMESYNC_L2_ENABLE /* IEEE1588 over Layer 2 */ 177 #define SOC_PORT_PHY_TIMESYNC_IP4_ENABLE _SHR_PORT_PHY_TIMESYNC_IP4_ENABLE /* IEEE1588 over IPV4 UDP */ 178 #define SOC_PORT_PHY_TIMESYNC_IP6_ENABLE _SHR_PORT_PHY_TIMESYNC_IP6_ENABLE /* IEEE1588 over IPV6 UDP */ 179 #define SOC_PORT_PHY_TIMESYNC_CLOCK_SRC_EXT _SHR_PORT_PHY_TIMESYNC_CLOCK_SRC_EXT /* Use external clock source (DPLL) */ 180 #define SOC_PORT_PHY_TIMESYNC_CLOCK_SRC_EXT_MODE _SHR_PORT_PHY_TIMESYNC_CLOCK_SRC_EXT_MODE /* DPLL mode, 181 0 - phase lock, 1 - frequency lock */ 182 #define SOC_PORT_PHY_TIMESYNC_1588_ENCRYPTED_MODE _SHR_PORT_PHY_TIMESYNC_1588_ENCRYPTED_MODE 183 #define SOC_PORT_PHY_TIMESYNC_FOLLOW_UP_ASSIST_ENABLE _SHR_PORT_PHY_TIMESYNC_FOLLOW_UP_ASSIST_ENABLE 184 #define SOC_PORT_PHY_TIMESYNC_DELAY_RESP_ASSIST_ENABLE _SHR_PORT_PHY_TIMESYNC_DELAY_RESP_ASSIST_ENABLE 185 #define SOC_PORT_PHY_TIMESYNC_64BIT_TIMESTAMP_ENABLE _SHR_PORT_PHY_TIMESYNC_64BIT_TIMESTAMP_ENABLE 186 #define SOC_PORT_PHY_TIMESYNC_1588_OVER_HSR_ENABLE _SHR_PORT_PHY_TIMESYNC_1588_OVER_HSR_ENABLE 187 #define SOC_PORT_PHY_TIMESYNC_CAPTURE_TIMESTAMP_TX_SYNC _SHR_PORT_PHY_TIMESYNC_CAPTURE_TIMESTAMP_TX_SYNC 188 #define SOC_PORT_PHY_TIMESYNC_CAPTURE_TIMESTAMP_TX_DELAY_REQ _SHR_PORT_PHY_TIMESYNC_CAPTURE_TIMESTAMP_TX_DELAY_REQ 189 #define SOC_PORT_PHY_TIMESYNC_CAPTURE_TIMESTAMP_TX_PDELAY_REQ _SHR_PORT_PHY_TIMESYNC_CAPTURE_TIMESTAMP_TX_PDELAY_REQ 190 #define SOC_PORT_PHY_TIMESYNC_CAPTURE_TIMESTAMP_TX_PDELAY_RESP _SHR_PORT_PHY_TIMESYNC_CAPTURE_TIMESTAMP_TX_PDELAY_RESP 191 #define SOC_PORT_PHY_TIMESYNC_CAPTURE_TIMESTAMP_RX_SYNC _SHR_PORT_PHY_TIMESYNC_CAPTURE_TIMESTAMP_RX_SYNC 192 #define SOC_PORT_PHY_TIMESYNC_CAPTURE_TIMESTAMP_RX_DELAY_REQ _SHR_PORT_PHY_TIMESYNC_CAPTURE_TIMESTAMP_RX_DELAY_REQ 193 #define SOC_PORT_PHY_TIMESYNC_CAPTURE_TIMESTAMP_RX_PDELAY_REQ _SHR_PORT_PHY_TIMESYNC_CAPTURE_TIMESTAMP_RX_PDELAY_REQ 194 #define SOC_PORT_PHY_TIMESYNC_CAPTURE_TIMESTAMP_RX_PDELAY_RESP _SHR_PORT_PHY_TIMESYNC_CAPTURE_TIMESTAMP_RX_PDELAY_RESP 195 196 #define SOC_PORT_PHY_TIMESYNC_CAPTURE_FULL_SOURCE_PORT 0xfffe 197 #define SOC_PORT_PHY_TIMESYNC_CAPTURE_LONG_TIMESTAMP 0xffff 198 199 #define SOC_PORT_PHY_TIMESYNC_CAP_MPLS _SHR_PORT_PHY_TIMESYNC_CAP_MPLS 200 #define SOC_PORT_PHY_TIMESYNC_CAP_ENHANCED_TSFIFO _SHR_PORT_PHY_TIMESYNC_CAP_ENHANCED_TSFIFO 201 #define SOC_PORT_PHY_TIMESYNC_CAP_INBAND_TS _SHR_PORT_PHY_TIMESYNC_CAP_INBAND_TS 202 #define SOC_PORT_PHY_TIMESYNC_CAP_FOLLOW_UP_ASSIST _SHR_PORT_PHY_TIMESYNC_CAP_FOLLOW_UP_ASSIST 203 #define SOC_PORT_PHY_TIMESYNC_CAP_DELAY_RESP_ASSIST _SHR_PORT_PHY_TIMESYNC_CAP_DELAY_RESP_ASSIST 204 #define SOC_PORT_PHY_TIMESYNC_CAP_CAPTURE_TIMESTAMP_MSG _SHR_PORT_PHY_TIMESYNC_CAP_CAPTURE_TIMESTAMP_MSG 205 206 #define SOC_PORT_PHY_TIMESYNC_INBAND_RESV0_ID_CHECK _SHR_PORT_PHY_TIMESYNC_INBAND_RESV0_ID_CHECK 207 #define SOC_PORT_PHY_TIMESYNC_INBAND_SYNC_ENABLE _SHR_PORT_PHY_TIMESYNC_INBAND_SYNC_ENABLE 208 #define SOC_PORT_PHY_TIMESYNC_INBAND_DELAY_RQ_ENABLE _SHR_PORT_PHY_TIMESYNC_INBAND_DELAY_RQ_ENABLE 209 #define SOC_PORT_PHY_TIMESYNC_INBAND_PDELAY_RQ_ENABLE _SHR_PORT_PHY_TIMESYNC_INBAND_PDELAY_RQ_ENABLE 210 #define SOC_PORT_PHY_TIMESYNC_INBAND_PDELAY_RESP_ENABLE _SHR_PORT_PHY_TIMESYNC_INBAND_PDELAY_RESP_ENABLE 211 #define SOC_PORT_PHY_TIMESYNC_INBAND_RESV0_ID_UPDATE _SHR_PORT_PHY_TIMESYNC_INBAND_RESV0_ID_UPDATE 212 #define SOC_PORT_PHY_TIMESYNC_INBAND_FOLLOW_UP_ASSIST _SHR_PORT_PHY_TIMESYNC_INBAND_FOLLOW_UP_ASSIST 213 #define SOC_PORT_PHY_TIMESYNC_INBAND_DELAY_RESP_ASSIST _SHR_PORT_PHY_TIMESYNC_INBAND_DELAY_RESP_ASSIST 214 #define SOC_PORT_PHY_TIMESYNC_INBAND_TIMER_MODE_SELECT _SHR_PORT_PHY_TIMESYNC_INBAND_TIMER_MODE_SELECT 215 216 #define SOC_PORT_PHY_TIMESYNC_INBAND_CAP_SRC_PORT_CLK_ID _SHR_PORT_PHY_TIMESYNC_INBAND_CAP_SRC_PORT_CLK_ID 217 #define SOC_PORT_PHY_TIMESYNC_INBAND_MATCH_VLAN_ID _SHR_PORT_PHY_TIMESYNC_INBAND_MATCH_VLAN_ID 218 #define SOC_PORT_PHY_TIMESYNC_INBAND_MATCH_SRC_PORT_NUM _SHR_PORT_PHY_TIMESYNC_INBAND_MATCH_SRC_PORT_NUM 219 #define SOC_PORT_PHY_TIMESYNC_INBAND_MATCH_MAC_ADDR _SHR_PORT_PHY_TIMESYNC_INBAND_MATCH_MAC_ADDR 220 #define SOC_PORT_PHY_TIMESYNC_INBAND_MATCH_IP_ADDR _SHR_PORT_PHY_TIMESYNC_INBAND_MATCH_IP_ADDR 221 222 223 #define SOC_PORT_PHY_TIMESYNC_MSG_SYNC _SHR_PORT_PHY_TIMESYNC_MSG_SYNC 224 #define SOC_PORT_PHY_TIMESYNC_MSG_DELAY_REQ _SHR_PORT_PHY_TIMESYNC_MSG_DELAY_REQ 225 #define SOC_PORT_PHY_TIMESYNC_MSG_PDELAY_REQ _SHR_PORT_PHY_TIMESYNC_MSG_PDELAY_REQ 226 #define SOC_PORT_PHY_TIMESYNC_MSG_PDELAY_RESP _SHR_PORT_PHY_TIMESYNC_MSG_PDELAY_RESP 227 228 #define SOC_PORT_PHY_TIMESYNC_PROT_LAYER2 _SHR_PORT_PHY_TIMESYNC_PROT_LAYER2 229 #define SOC_PORT_PHY_TIMESYNC_PROT_IPV4_UDP _SHR_PORT_PHY_TIMESYNC_PROT_IPV4_UDP 230 #define SOC_PORT_PHY_TIMESYNC_PROT_IPV6_UDP _SHR_PORT_PHY_TIMESYNC_PROT_IPV6_UDP 231 232 #define SOC_PORT_PHY_TIMESYNC_DIR_EGRESS _SHR_PORT_PHY_TIMESYNC_DIR_EGRESS 233 #define SOC_PORT_PHY_TIMESYNC_DIR_INGRESS _SHR_PORT_PHY_TIMESYNC_DIR_INGRESS 234 235 236 #define SOC_PORT_PHY_TIMESYNC_MPLS_LABEL_IN _SHR_PORT_PHY_TIMESYNC_MPLS_LABEL_IN /* MPLS label applies to 237 ingress packets */ 238 #define SOC_PORT_PHY_TIMESYNC_MPLS_LABEL_OUT _SHR_PORT_PHY_TIMESYNC_MPLS_LABEL_OUT /* MPLS label applies to 239 egress packets */ 240 #define SOC_PORT_PHY_TIMESYNC_MPLS_ENABLE _SHR_PORT_PHY_TIMESYNC_MPLS_ENABLE /* Enable processing of 241 MPLS 1588 packets */ 242 #define SOC_PORT_PHY_TIMESYNC_MPLS_ENTROPY_ENABLE _SHR_PORT_PHY_TIMESYNC_MPLS_ENTROPY_ENABLE /* Enable MPLS entropy on 243 1588 packets */ 244 #define SOC_PORT_PHY_TIMESYNC_MPLS_SPECIAL_LABEL_ENABLE _SHR_PORT_PHY_TIMESYNC_MPLS_SPECIAL_LABEL_ENABLE /* Enable MPLS special 245 label on 1588 packets */ 246 #define SOC_PORT_PHY_TIMESYNC_MPLS_CONTROL_WORD_ENABLE _SHR_PORT_PHY_TIMESYNC_MPLS_CONTROL_WORD_ENABLE /* Enable MPLS control 247 word on 1588 packets */ 248 #define SOC_PORT_PHY_TIMESYNC_TN_LOAD _SHR_PORT_PHY_TIMESYNC_TN_LOAD /* Load Tn upon framesync */ 249 #define SOC_PORT_PHY_TIMESYNC_TN_ALWAYS_LOAD _SHR_PORT_PHY_TIMESYNC_TN_ALWAYS_LOAD /* Always load Tn upon 250 framesync */ 251 #define SOC_PORT_PHY_TIMESYNC_TIMECODE_LOAD _SHR_PORT_PHY_TIMESYNC_TIMECODE_LOAD /* Load timecode upon 252 framesync */ 253 #define SOC_PORT_PHY_TIMESYNC_TIMECODE_ALWAYS_LOAD _SHR_PORT_PHY_TIMESYNC_TIMECODE_ALWAYS_LOAD /* Always load timecode 254 upon framesync */ 255 #define SOC_PORT_PHY_TIMESYNC_SYNCOUT_LOAD _SHR_PORT_PHY_TIMESYNC_SYNCOUT_LOAD /* Load syncout upon 256 framesync */ 257 #define SOC_PORT_PHY_TIMESYNC_SYNCOUT_ALWAYS_LOAD _SHR_PORT_PHY_TIMESYNC_SYNCOUT_ALWAYS_LOAD /* Always load syncout 258 upon framesync */ 259 #define SOC_PORT_PHY_TIMESYNC_NCO_DIVIDER_LOAD _SHR_PORT_PHY_TIMESYNC_NCO_DIVIDER_LOAD /* Load NCO divider upon 260 framesync */ 261 #define SOC_PORT_PHY_TIMESYNC_NCO_DIVIDER_ALWAYS_LOAD _SHR_PORT_PHY_TIMESYNC_NCO_DIVIDER_ALWAYS_LOAD /* Always load NCO 262 divider upon framesync */ 263 #define SOC_PORT_PHY_TIMESYNC_LOCAL_TIME_LOAD _SHR_PORT_PHY_TIMESYNC_LOCAL_TIME_LOAD /* Load local time upon 264 framesync */ 265 #define SOC_PORT_PHY_TIMESYNC_LOCAL_TIME_ALWAYS_LOAD _SHR_PORT_PHY_TIMESYNC_LOCAL_TIME_ALWAYS_LOAD /* Always load local time 266 upon framesync */ 267 #define SOC_PORT_PHY_TIMESYNC_NCO_ADDEND_LOAD _SHR_PORT_PHY_TIMESYNC_NCO_ADDEND_LOAD /* Load NCO addend upon 268 framesync */ 269 #define SOC_PORT_PHY_TIMESYNC_NCO_ADDEND_ALWAYS_LOAD _SHR_PORT_PHY_TIMESYNC_NCO_ADDEND_ALWAYS_LOAD /* Always load NCO addend 270 upon framesync */ 271 #define SOC_PORT_PHY_TIMESYNC_DPLL_LOOP_FILTER_LOAD _SHR_PORT_PHY_TIMESYNC_DPLL_LOOP_FILTER_LOAD /* Load DPLL loop filter 272 upon framesync */ 273 #define SOC_PORT_PHY_TIMESYNC_DPLL_LOOP_FILTER_ALWAYS_LOAD _SHR_PORT_PHY_TIMESYNC_DPLL_LOOP_FILTER_ALWAYS_LOAD /* Always load DPLL loop 274 filter upon framesync */ 275 #define SOC_PORT_PHY_TIMESYNC_DPLL_REF_PHASE_LOAD _SHR_PORT_PHY_TIMESYNC_DPLL_REF_PHASE_LOAD /* Load DPLL ref phase 276 upon framesync */ 277 #define SOC_PORT_PHY_TIMESYNC_DPLL_REF_PHASE_ALWAYS_LOAD _SHR_PORT_PHY_TIMESYNC_DPLL_REF_PHASE_ALWAYS_LOAD /* Always load DPLL ref 278 phase upon framesync */ 279 #define SOC_PORT_PHY_TIMESYNC_DPLL_REF_PHASE_DELTA_LOAD _SHR_PORT_PHY_TIMESYNC_DPLL_REF_PHASE_DELTA_LOAD /* Load DPLL ref phase 280 delta upon framesync */ 281 #define SOC_PORT_PHY_TIMESYNC_DPLL_REF_PHASE_DELTA_ALWAYS_LOAD _SHR_PORT_PHY_TIMESYNC_DPLL_REF_PHASE_DELTA_ALWAYS_LOAD /* Always load DPLL ref 282 phase delta upon 283 framesync */ 284 #define SOC_PORT_PHY_TIMESYNC_DPLL_K3_LOAD _SHR_PORT_PHY_TIMESYNC_DPLL_K3_LOAD /* Load DPLL coefficient 285 K3 upon framesync */ 286 #define SOC_PORT_PHY_TIMESYNC_DPLL_K3_ALWAYS_LOAD _SHR_PORT_PHY_TIMESYNC_DPLL_K3_ALWAYS_LOAD /* Always load DPLL 287 coefficient K3 upon 288 framesync */ 289 #define SOC_PORT_PHY_TIMESYNC_DPLL_K2_LOAD _SHR_PORT_PHY_TIMESYNC_DPLL_K2_LOAD /* Load DPLL coefficient 290 K2 upon framesync */ 291 #define SOC_PORT_PHY_TIMESYNC_DPLL_K2_ALWAYS_LOAD _SHR_PORT_PHY_TIMESYNC_DPLL_K2_ALWAYS_LOAD /* Always load DPLL 292 coefficient K2 upon 293 framesync */ 294 #define SOC_PORT_PHY_TIMESYNC_DPLL_K1_LOAD _SHR_PORT_PHY_TIMESYNC_DPLL_K1_LOAD /* Load DPLL coefficient 295 K1 upon framesync */ 296 #define SOC_PORT_PHY_TIMESYNC_DPLL_K1_ALWAYS_LOAD _SHR_PORT_PHY_TIMESYNC_DPLL_K1_ALWAYS_LOAD /* Always load DPLL 297 coefficient K1 upon 298 framesync */ 299 #define SOC_PORT_PHY_TIMESYNC_TIMESTAMP_INTERRUPT _SHR_PORT_PHY_TIMESYNC_TIMESTAMP_INTERRUPT /* Packet timestamp 300 interrupt */ 301 #define SOC_PORT_PHY_TIMESYNC_TIMESTAMP_INTERRUPT_0 _SHR_PORT_PHY_TIMESYNC_TIMESTAMP_INTERRUPT_0 /* Packet 302 timestamp interrupt from port 0 */ 303 #define SOC_PORT_PHY_TIMESYNC_TIMESTAMP_INTERRUPT_1 _SHR_PORT_PHY_TIMESYNC_TIMESTAMP_INTERRUPT_1 /* Packet 304 timestamp interrupt from port 1 */ 305 #define SOC_PORT_PHY_TIMESYNC_TIMESTAMP_INTERRUPT_2 _SHR_PORT_PHY_TIMESYNC_TIMESTAMP_INTERRUPT_2 /* Packet 306 timestamp interrupt from port 2 */ 307 #define SOC_PORT_PHY_TIMESYNC_TIMESTAMP_INTERRUPT_3 _SHR_PORT_PHY_TIMESYNC_TIMESTAMP_INTERRUPT_3 /* Packet 308 timestamp interrupt from port 3 */ 309 #define SOC_PORT_PHY_TIMESYNC_TIMESTAMP_INTERRUPT_4 _SHR_PORT_PHY_TIMESYNC_TIMESTAMP_INTERRUPT_4 /* Packet 310 timestamp interrupt from port 4 */ 311 #define SOC_PORT_PHY_TIMESYNC_TIMESTAMP_INTERRUPT_5 _SHR_PORT_PHY_TIMESYNC_TIMESTAMP_INTERRUPT_5 /* Packet 312 timestamp interrupt from port 5 */ 313 #define SOC_PORT_PHY_TIMESYNC_TIMESTAMP_INTERRUPT_6 _SHR_PORT_PHY_TIMESYNC_TIMESTAMP_INTERRUPT_6 /* Packet 314 timestamp interrupt from port 6 */ 315 #define SOC_PORT_PHY_TIMESYNC_TIMESTAMP_INTERRUPT_7 _SHR_PORT_PHY_TIMESYNC_TIMESTAMP_INTERRUPT_7 /* Packet 316 timestamp interrupt from port 7 */ 317 #define SOC_PORT_PHY_TIMESYNC_FRAMESYNC_INTERRUPT _SHR_PORT_PHY_TIMESYNC_FRAMESYNC_INTERRUPT /* Framesync interrupt */ 318 #define SOC_PORT_PHY_TIMESYNC_TIMESTAMP_INTERRUPT_MASK _SHR_PORT_PHY_TIMESYNC_TIMESTAMP_INTERRUPT_MASK /* Packet timestamp 319 interrupt mask */ 320 #define SOC_PORT_PHY_TIMESYNC_FRAMESYNC_INTERRUPT_MASK _SHR_PORT_PHY_TIMESYNC_FRAMESYNC_INTERRUPT_MASK /* Framesync interrupt 321 mask */ 322 323 #define SOC_PORT_CONTROL_PHY_TIMESYNC_CAPTURE_TIMESTAMP \ 324 _SHR_PORT_CONTROL_PHY_TIMESYNC_CAPTURE_TIMESTAMP 325 #define SOC_PORT_CONTROL_PHY_TIMESYNC_HEARTBEAT_TIMESTAMP \ 326 _SHR_PORT_CONTROL_PHY_TIMESYNC_HEARTBEAT_TIMESTAMP 327 #define SOC_PORT_CONTROL_PHY_TIMESYNC_NCOADDEND \ 328 _SHR_PORT_CONTROL_PHY_TIMESYNC_NCOADDEND 329 #define SOC_PORT_CONTROL_PHY_TIMESYNC_FRAMESYNC \ 330 _SHR_PORT_CONTROL_PHY_TIMESYNC_FRAMESYNC 331 #define SOC_PORT_CONTROL_PHY_TIMESYNC_LOCAL_TIME \ 332 _SHR_PORT_CONTROL_PHY_TIMESYNC_LOCAL_TIME 333 #define SOC_PORT_CONTROL_PHY_TIMESYNC_LOAD_CONTROL \ 334 _SHR_PORT_CONTROL_PHY_TIMESYNC_LOAD_CONTROL 335 #define SOC_PORT_CONTROL_PHY_TIMESYNC_INTERRUPT \ 336 _SHR_PORT_CONTROL_PHY_TIMESYNC_INTERRUPT 337 #define SOC_PORT_CONTROL_PHY_TIMESYNC_INTERRUPT_MASK \ 338 _SHR_PORT_CONTROL_PHY_TIMESYNC_INTERRUPT_MASK 339 #define SOC_PORT_CONTROL_PHY_TIMESYNC_TX_TIMESTAMP_OFFSET \ 340 _SHR_PORT_CONTROL_PHY_TIMESYNC_TX_TIMESTAMP_OFFSET 341 #define SOC_PORT_CONTROL_PHY_TIMESYNC_RX_TIMESTAMP_OFFSET \ 342 _SHR_PORT_CONTROL_PHY_TIMESYNC_RX_TIMESTAMP_OFFSET 343 #define SOC_PORT_CONTROL_PHY_TIMESYNC_NSE_TIME_OFFSET \ 344 _SHR_PORT_CONTROL_PHY_TIMESYNC_NSE_TIME_OFFSET 345 #define SOC_PORT_CONTROL_PHY_TIMESYNC_TIMESTAMP_OFFSET \ 346 _SHR_PORT_CONTROL_PHY_TIMESYNC_TIMESTAMP_OFFSET 347 #define SOC_PORT_CONTROL_PHY_TIMESYNC_TIMESTAMP_ADJUST \ 348 _SHR_PORT_CONTROL_PHY_TIMESYNC_TIMESTAMP_ADJUST 349 #define SOC_PORT_CONTROL_PHY_TIMESYNC_ONE_STEP_ENABLE \ 350 _SHR_PORT_CONTROL_PHY_TIMESYNC_ONE_STEP_ENABLE 351 352 #define SOC_PORT_PHY_TIMESYNC_COMPENSATION_MODE_NONE \ 353 _SHR_PORT_PHY_TIMESYNC_COMPENSATION_MODE_NONE 354 #define SOC_PORT_PHY_TIMESYNC_COMPENSATION_MODE_EARLIEST_LANE \ 355 _SHR_PORT_PHY_TIMESYNC_COMPENSATION_MODE_EARLIEST_LANE 356 #define SOC_PORT_PHY_TIMESYNC_COMPENSATION_MODE_LATEST_LANE \ 357 _SHR_PORT_PHY_TIMESYNC_COMPENSATION_MODE_LATEST_LANE 358 359 /* time_spec type */ 360 typedef _shr_time_spec_t soc_time_spec_t; 361 362 /* Actions on Egress event messages */ 363 typedef _shr_port_phy_timesync_event_message_egress_mode_t soc_port_phy_timesync_event_message_egress_mode_t; 364 /* Actions on ingress event messages */ 365 typedef _shr_port_phy_timesync_event_message_ingress_mode_t soc_port_phy_timesync_event_message_ingress_mode_t; 366 367 /* Global mode actions */ 368 typedef _shr_port_phy_timesync_global_mode_t soc_port_phy_timesync_global_mode_t; 369 /* Fast call actions */ 370 typedef _shr_port_control_phy_timesync_t soc_port_control_phy_timesync_t; 371 372 typedef _shr_port_phy_timesync_framesync_mode_t soc_port_phy_timesync_framesync_mode_t; 373 typedef _shr_port_phy_timesync_syncout_mode_t soc_port_phy_timesync_syncout_mode_t; 374 375 typedef _shr_port_phy_timesync_framesync_t soc_port_phy_timesync_framesync_t; 376 typedef _shr_port_phy_timesync_syncout_t soc_port_phy_timesync_syncout_t; 377 typedef _shr_port_phy_timesync_mpls_control_t soc_port_phy_timesync_mpls_control_t; 378 379 typedef _shr_port_phy_timesync_timer_adjust_t soc_port_phy_timesync_timer_adjust_t; 380 typedef _shr_port_phy_timesync_inband_control_t soc_port_phy_timesync_inband_control_t; 381 382 typedef _shr_port_phy_timesync_msg_t soc_port_phy_timesync_msg_t; 383 typedef _shr_port_phy_timesync_prot_t soc_port_phy_timesync_prot_t; 384 typedef _shr_port_phy_timesync_dir_t soc_port_phy_timesync_dir_t; 385 typedef _shr_port_phy_timesync_enhanced_capture_t soc_port_phy_timesync_enhanced_capture_t; 386 387 /* Base timesync configuration type. */ 388 typedef struct soc_port_phy_timesync_config_s { 389 uint32 capabilities; /* Flags BCM_PORT_PHY_TIMESYNC_CAP_* */ 390 uint32 validity_mask; /* Flags BCM_PORT_PHY_TIMESYNC_VALID_* */ 391 uint32 flags; /* Flags BCM_PORT_PHY_TIMESYNC_* */ 392 uint16 itpid; /* 1588 inner tag */ 393 uint16 otpid; /* 1588 outer tag */ 394 uint16 otpid2; /* 1588 outer tag2 */ 395 soc_port_phy_timesync_timer_adjust_t timer_adjust; /* Timer adjusting mode & delta */ 396 soc_port_phy_timesync_inband_control_t inband_control; /* Inband TS control */ 397 soc_port_phy_timesync_global_mode_t gmode; /* Global mode */ 398 soc_port_phy_timesync_framesync_t framesync; /* Framesync */ 399 soc_port_phy_timesync_syncout_t syncout; /* SyncIN/SyncOut mode */ 400 uint16 ts_divider; /* Timestamp divider */ 401 soc_time_spec_t original_timecode; /* Original timecode to be inserted */ 402 uint32 tx_timestamp_offset; /* TX AFE delay in ns - per port */ 403 uint32 rx_timestamp_offset; /* RX AFE delay in ns - per port */ 404 uint32 rx_link_delay; /* RX link delay */ 405 soc_port_phy_timesync_event_message_egress_mode_t tx_sync_mode; /* sync */ 406 soc_port_phy_timesync_event_message_egress_mode_t tx_delay_request_mode; /* delay request */ 407 soc_port_phy_timesync_event_message_egress_mode_t tx_pdelay_request_mode; /* pdelay request */ 408 soc_port_phy_timesync_event_message_egress_mode_t tx_pdelay_response_mode; /* pdelay response */ 409 soc_port_phy_timesync_event_message_ingress_mode_t rx_sync_mode; /* sync */ 410 soc_port_phy_timesync_event_message_ingress_mode_t rx_delay_request_mode; /* delay request */ 411 soc_port_phy_timesync_event_message_ingress_mode_t rx_pdelay_request_mode; /* pdelay request */ 412 soc_port_phy_timesync_event_message_ingress_mode_t rx_pdelay_response_mode; /* pdelay response */ 413 soc_port_phy_timesync_mpls_control_t mpls_control; /* MPLS control */ 414 uint32 sync_freq; /* sync frequency */ 415 uint16 phy_1588_dpll_k1; /* DPLL K1 */ 416 uint16 phy_1588_dpll_k2; /* DPLL K2 */ 417 uint16 phy_1588_dpll_k3; /* DPLL K3 */ 418 uint64 phy_1588_dpll_loop_filter; /* DPLL loop filter */ 419 uint64 phy_1588_dpll_ref_phase; /* DPLL ref phase */ 420 uint32 phy_1588_dpll_ref_phase_delta; /* DPLL ref phase delta */ 421 } soc_port_phy_timesync_config_t; 422 423 424 /* soc_port_phy_timesync_config_set */ 425 extern int soc_port_phy_timesync_config_set( 426 int unit, 427 soc_port_t port, 428 soc_port_phy_timesync_config_t *conf); 429 430 /* soc_port_phy_timesync_config_get */ 431 extern int soc_port_phy_timesync_config_get( 432 int unit, 433 soc_port_t port, 434 soc_port_phy_timesync_config_t *conf); 435 436 /* soc_port_control_phy_timesync_set */ 437 extern int soc_port_control_phy_timesync_set( 438 int unit, 439 soc_port_t port, 440 soc_port_control_phy_timesync_t type, 441 uint64 value); 442 443 /* soc_port_control_phy_timesync_get */ 444 extern int soc_port_control_phy_timesync_get( 445 int unit, 446 soc_port_t port, 447 soc_port_control_phy_timesync_t type, 448 uint64 *value); 449 450 /* soc_port_phy_timesync_enhanced_capture_get */ 451 extern int soc_port_phy_timesync_enhanced_capture_get( 452 int unit, 453 soc_port_t port, 454 soc_port_phy_timesync_enhanced_capture_t *value); 455 456 #endif /* !_SOC_TIMESYNC_H */