tdm_td3_defines.h (6773B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * All Rights Reserved.$ 7 * 8 * TDM macro values for BCM56870 9 */ 10 11 #ifndef TDM_TD3_PREPROCESSOR_MACROS_H 12 #define TDM_TD3_PREPROCESSOR_MACROS_H 13 14 /* Frequency */ 15 #define TD3_CLK_1700MHZ 1700 16 #define TD3_CLK_1625MHZ 1625 17 #define TD3_CLK_1525MHZ 1525 18 #define TD3_CLK_1425MHZ 1425 19 #define TD3_CLK_1325MHZ 1325 20 #define TD3_CLK_1275MHZ 1275 21 #define TD3_CLK_1133MHZ 1133 22 #define TD3_CLK_1125MHZ 1125 23 #define TD3_CLK_1083MHZ 1083 24 #define TD3_CLK_1016MHZ 1016 25 #define TD3_CLK_1012MHZ 1012 26 #define TD3_CLK_950MHZ 950 27 #define TD3_CLK_883MHZ 883 28 #define TD3_CLK_850MHZ 850 29 30 /* Calendar Length */ 31 #define TD3_LEN_1700MHZ_HG 430 32 #define TD3_LEN_1700MHZ_EN 456 33 #define TD3_LEN_1625MHZ_HG 411 34 #define TD3_LEN_1625MHZ_EN 436 35 #define TD3_LEN_1525MHZ_HG 386 36 #define TD3_LEN_1525MHZ_EN 408 37 #define TD3_LEN_1425MHZ_HG 361 38 #define TD3_LEN_1425MHZ_EN 383 39 #define TD3_LEN_1325MHZ_HG 335 40 #define TD3_LEN_1325MHZ_EN 356 41 #define TD3_LEN_1275MHZ_HG 323 42 #define TD3_LEN_1275MHZ_EN 342 43 #define TD3_LEN_1133MHZ_HG 287 44 #define TD3_LEN_1133MHZ_EN 304 45 #define TD3_LEN_1125MHZ_HG 285 46 #define TD3_LEN_1125MHZ_EN 302 47 #define TD3_LEN_1083MHZ_HG 274 48 #define TD3_LEN_1083MHZ_EN 291 49 #define TD3_LEN_1016MHZ_HG 257 50 #define TD3_LEN_1016MHZ_EN 273 51 #define TD3_LEN_1012MHZ_HG 256 52 #define TD3_LEN_1012MHZ_EN 272 53 #define TD3_LEN_950MHZ_HG 240 54 #define TD3_LEN_950MHZ_EN 255 55 #define TD3_LEN_883MHZ_HG 223 56 #define TD3_LEN_883MHZ_EN 237 57 #define TD3_LEN_850MHZ_HG 215 58 #define TD3_LEN_850MHZ_EN 228 59 60 /* Default number of PM in chip */ 61 #define TD3_NUM_PM_MOD 33 62 #define TD3_NUM_PHY_PM 32 63 /* Default number of lanes per PM in chip */ 64 #define TD3_NUM_PM_LNS 4 65 /* Allocation length of port lookup tables */ 66 #define TD3_NUM_EXT_PORTS 132 67 68 /* Number of possible physical ports */ 69 #define TD3_NUM_PHY_PORTS 128 70 /* Number of scheduling blocks */ 71 #define TD3_NUM_QUAD 2 72 /* Number of scheduling blocks */ 73 #define TD3_NUM_PIPE 2 74 /* Number of Subpipes per pipe */ 75 #define TD3_NUM_SPIPE 2 76 /* Number of possible physical ports per pipe */ 77 #define TD3_NUM_PHY_PORTS_PER_PIPE 64 78 /* Number of possible physical ports per subpipe */ 79 #define TD3_NUM_PHY_PORTS_PER_SPIPE 32 80 81 /* Number of slots per lane in OVSB Packet Scheduler */ 82 #define TD3_NUM_PKT_SLOTS_PER_LANE 5 83 /* Number of slots per PM in OVSB Packet Scheduler */ 84 #define TD3_NUM_PKT_SLOTS_PER_PM 20 85 86 /* Number of PMs per pipe : 16 */ 87 #define TD3_NUM_PMS_PER_PIPE (TD3_NUM_PHY_PM / TD3_NUM_PIPE) 88 /* Number of PMs per subpipe : 8 */ 89 #define TD3_NUM_PMS_PER_SPIPE (TD3_NUM_PMS_PER_PIPE / TD3_NUM_SPIPE) 90 91 /* Default number of ancillary ports in calendar */ 92 #define TD3_NUM_ANCL 16 93 #define TD3_NUM_ANCL_CPU 8 94 #define TD3_NUM_ANCL_MGMT 8 95 #define TD3_NUM_ANCL_LPBK 4 96 #define TD3_NUM_ANCL_IDB_OPT1 1 97 #define TD3_NUM_ANCL_IDB_NULL 1 98 #define TD3_NUM_ANCL_IDB_IDLE 2 99 #define TD3_NUM_ANCL_MMU_OPT1 0 100 #define TD3_NUM_ANCL_MMU_NULL 3 101 #define TD3_NUM_ANCL_MMU_IDLE 1 102 103 /* Allocation length of VBS line rate calendar */ 104 #define TD3_LR_VBS_LEN 512 105 /* Allocation area of VBS port groups */ 106 #define TD3_OS_VBS_GRP_NUM 12 107 #define TD3_OS_VBS_GRP_LEN 12 108 109 /* Architecturally specific allocation area of VBS vector map */ 110 #define TD3_VMAP_MAX_LEN TD3_LR_VBS_LEN 111 #define TD3_VMAP_MAX_WID 128 112 113 /* Min sister port spacing (VBS scheduler req) */ 114 #define TD3_MIN_SPACING_SISTER_PORT 4 115 /* Min sister port spacing (VBS scheduler req) */ 116 #define TD3_MIN_SPACING_SAME_PORT_HSP 8 117 #define TD3_MIN_SPACING_SAME_PORT_LSP 14 118 119 /* static port identities 120 TD3_CMIC_TOKEN ( 0): Pipe 0 - CPU slot 121 TD3_MGM1_TOKEN (129): Pipe 1 - management port 1 slot 122 TD3_MGM2_TOKEN (128): Pipe 1 - management port 2 slot 123 TD3_LPB0_TOKEN (130): Pipe 0 - loopback slot 124 TD3_LPB1_TOKEN (131): Pipe 1 - loopback slot 125 */ 126 #define TD3_CMIC_TOKEN 0 127 #define TD3_MGM1_TOKEN (TD3_NUM_EXT_PORTS-3) 128 #define TD3_MGM2_TOKEN (TD3_NUM_EXT_PORTS-4) 129 #define TD3_LPB0_TOKEN (TD3_NUM_EXT_PORTS-2) 130 #define TD3_LPB1_TOKEN (TD3_NUM_EXT_PORTS-1) 131 /* Tokenization values 132 TD3_OVSB_TOKEN (133): token for oversub round robin 133 TD3_IDL1_TOKEN (134): idle slot for memreset, L2 management, other 134 TD3_IDL2_TOKEN (135): idle slot guaranteed for refresh 135 TD3_NULL_TOKEN (136): null slot, no pick, no opportunistic 136 TD3_ANCL_TOKEN (142): reservation for ancillary soc functions 137 */ 138 #define TD3_OVSB_TOKEN (TD3_NUM_EXT_PORTS+1) 139 #define TD3_IDL1_TOKEN (TD3_NUM_EXT_PORTS+2) 140 #define TD3_IDL2_TOKEN (TD3_NUM_EXT_PORTS+3) 141 #define TD3_NULL_TOKEN (TD3_NUM_EXT_PORTS+4) 142 #define TD3_ANCL_TOKEN (TD3_NUM_EXT_PORTS+10) 143 144 /* Calendar ID */ 145 #define TD3_IDB_PIPE_0_CAL_ID 0 146 #define TD3_IDB_PIPE_1_CAL_ID 1 147 #define TD3_IDB_PIPE_2_CAL_ID 2 148 #define TD3_IDB_PIPE_3_CAL_ID 3 149 #define TD3_MMU_PIPE_0_CAL_ID 4 150 #define TD3_MMU_PIPE_1_CAL_ID 5 151 #define TD3_MMU_PIPE_2_CAL_ID 6 152 #define TD3_MMU_PIPE_3_CAL_ID 7 153 154 /* Physical port number range of each pipe */ 155 #define TD3_CAL_0_PORT_LO 1 156 #define TD3_CAL_0_PORT_HI 64 157 #define TD3_CAL_1_PORT_LO 65 158 #define TD3_CAL_1_PORT_HI 128 159 #define TD3_CAL_2_PORT_LO 0 160 #define TD3_CAL_2_PORT_HI 0 161 #define TD3_CAL_3_PORT_LO 0 162 #define TD3_CAL_3_PORT_HI 0 163 #define TD3_CAL_4_PORT_LO 1 164 #define TD3_CAL_4_PORT_HI 64 165 #define TD3_CAL_5_PORT_LO 65 166 #define TD3_CAL_5_PORT_HI 128 167 #define TD3_CAL_6_PORT_LO 0 168 #define TD3_CAL_6_PORT_HI 0 169 #define TD3_CAL_7_PORT_LO 0 170 #define TD3_CAL_7_PORT_HI 0 171 172 /* Management port mode (10G per management port) 173 0 -> two Etherner management ports (default) 174 1 -> one Ethernet management port 175 2 -> two HiGig management ports (reserved) 176 3 -> one HiGig management port (reserved) 177 */ 178 enum td3_mgmt_mode_e { 179 TD3_MGMT_MODE_2_PORT_EN=0, 180 TD3_MGMT_MODE_1_PORT_EN=1, 181 TD3_MGMT_MODE_2_PORT_HG=2, 182 TD3_MGMT_MODE_1_PORT_HG=3 183 }; 184 185 /* Index and length of shaping calendar within each inst */ 186 #define TD3_SHAPING_GRP_NUM 2 187 #define TD3_SHAPING_GRP_LEN 160 188 #define TD3_SHAPING_GRP_IDX_0 TD3_OS_VBS_GRP_NUM 189 #define TD3_SHAPING_GRP_IDX_1 (TD3_OS_VBS_GRP_NUM+1) 190 /* granularity of packet shaper calendar (in Mbps): 5000 */ 191 #define TD3_SHAPER_SLOT_UNIT (SPEED_5G) 192 /* max speed per lane within each PM (in Mbps): 25000 */ 193 #define TD3_SHAPER_MAX_SPD_PER_LN (SPEED_25G) 194 /* number of slots per sublane: 5*/ 195 #define TD3_SHAPER_NUM_LN_SLOTS 5 196 /* number of slots per PM: 20*/ 197 #define TD3_SHAPER_NUM_PM_SLOTS (TD3_SHAPER_NUM_LN_SLOTS*TD3_NUM_PM_LNS) 198 /* number of slots packet shaper calendar: 160 */ 199 #define TD3_SHAPER_LEN (TD3_SHAPER_NUM_PM_SLOTS*TD3_NUM_PMS_PER_SPIPE) 200 201 /* Linerate jitter threshold */ 202 #define TD3_LR_JITTER_LO 5 203 #define TD3_LR_JITTER_MD 2 204 #define TD3_LR_JITTER_HI 1 205 #define TD3_LR_CHK_TRHD TD3_LR_JITTER_HI 206 207 #endif /* TDM_TD3_PREPROCESSOR_MACROS_H */