tdm_td2p_top.h (5378B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * All Rights Reserved.$ 7 * 8 * TDM top header for BCM56860 9 */ 10 11 #ifndef TDM_TD2P_PREPROCESSOR_DIRECTIVES_H 12 #define TDM_TD2P_PREPROCESSOR_DIRECTIVES_H 13 14 #ifdef _TDM_STANDALONE 15 #include <tdm_td2p_defines.h> 16 #else 17 #include <soc/tdm/trident2p/tdm_td2p_defines.h> 18 #endif 19 20 21 /* Excludes the management ports which are also physical port numbers */ 22 #define TD2P_MGMT_CHECK(a) \ 23 if (a!=TD2P_MGMT_PORT_0 && \ 24 a!=TD2P_MGMT_PORT_1 && \ 25 a!=TD2P_MGMT_PORT_2 && \ 26 a!=TD2P_MGMT_PORT_3) \ 27 28 /* Excludes all tokenized port numbers */ 29 #define TD2P_TOKEN_CHECK(a) \ 30 if (a!=TD2P_NUM_EXT_PORTS && \ 31 a!=TD2P_OVSB_TOKEN && \ 32 a!=TD2P_IDL1_TOKEN && \ 33 a!=TD2P_IDL2_TOKEN && \ 34 a!=TD2P_ANCL_TOKEN && \ 35 a!=TD2P_MGMT_TOKEN && \ 36 a!=TD2P_US1G_TOKEN && \ 37 a!=TD2P_LOOPBACK_PORT && \ 38 a!=TD2P_CPU_PORT) \ 39 40 #define TD2P_CMIC(a) { \ 41 mmu_tdm_tbl[a]=TD2P_CPU_PORT; \ 42 TDM_PRINT0("CMIC\n"); \ 43 break; \ 44 } 45 #define TD2P_LPBK(a) { \ 46 mmu_tdm_tbl[a]=TD2P_LOOPBACK_PORT; \ 47 TDM_PRINT0("LOOPBACK\n"); \ 48 break; \ 49 } 50 #define TD2P_ANCL(a) { \ 51 mmu_tdm_tbl[a]=TD2P_IDL1_TOKEN; \ 52 TDM_PRINT0("OPPORTUNISTIC\n"); \ 53 break; \ 54 } 55 #define TD2P_REFR(a) { \ 56 mmu_tdm_tbl[a]=TD2P_IDL2_TOKEN; \ 57 TDM_PRINT0("REFRESH\n"); \ 58 break; \ 59 } 60 #define TD2P_MM13(a) { \ 61 mmu_tdm_tbl[a]=TD2P_MGMT_PORT_0; \ 62 TDM_PRINT0("management phyport 13\n"); \ 63 break; \ 64 } 65 #define TD2P_MM14(a) { \ 66 mmu_tdm_tbl[a]=TD2P_MGMT_PORT_1; \ 67 TDM_PRINT0("management phyport 14\n"); \ 68 break; \ 69 } 70 #define TD2P_MM15(a) { \ 71 mmu_tdm_tbl[a]=TD2P_MGMT_PORT_2; \ 72 TDM_PRINT0("management phyport 15\n"); \ 73 break; \ 74 } 75 #define TD2P_MM16(a) { \ 76 mmu_tdm_tbl[a]=TD2P_MGMT_PORT_3; \ 77 TDM_PRINT0("management phyport 16\n"); \ 78 break; \ 79 } 80 81 #define IARB_MAIN_TDM__TDM_SLOT_PGW_0 0 82 #define IARB_MAIN_TDM__TDM_SLOT_PGW_1 1 83 #define IARB_MAIN_TDM__TDM_SLOT_CMIC_PORT 2 84 #define IARB_MAIN_TDM__TDM_SLOT_EP_LOOPBACK 3 85 #define IARB_MAIN_TDM__TDM_SLOT_QGP_PORT 4 86 #define IARB_MAIN_TDM__TDM_SLOT_RESERVED 6 87 #define IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT 7 88 89 typedef struct ll_node { 90 unsigned short port; 91 struct ll_node *next; 92 } ll_node; 93 94 typedef struct { 95 int pgw_tdm_tbl_x0[TD2P_LR_LLS_LEN]; 96 int ovs_tdm_tbl_x0[TD2P_OS_LLS_GRP_LEN]; 97 int ovs_spacing_x0[TD2P_OS_LLS_GRP_LEN]; 98 int pgw_tdm_tbl_x1[TD2P_LR_LLS_LEN]; 99 int ovs_tdm_tbl_x1[TD2P_OS_LLS_GRP_LEN]; 100 int ovs_spacing_x1[TD2P_OS_LLS_GRP_LEN]; 101 int pgw_tdm_tbl_y0[TD2P_LR_LLS_LEN]; 102 int ovs_tdm_tbl_y0[TD2P_OS_LLS_GRP_LEN]; 103 int ovs_spacing_y0[TD2P_OS_LLS_GRP_LEN]; 104 int pgw_tdm_tbl_y1[TD2P_LR_LLS_LEN]; 105 int ovs_tdm_tbl_y1[TD2P_OS_LLS_GRP_LEN]; 106 int ovs_spacing_y1[TD2P_OS_LLS_GRP_LEN]; 107 int iarb_tdm_tbl_x[TD2P_LR_IARB_STATIC_LEN]; 108 int iarb_tdm_tbl_y[TD2P_LR_IARB_STATIC_LEN]; 109 int op_flags_x[NUM_OP_FLAGS]; 110 int op_flags_y[NUM_OP_FLAGS]; 111 } td2p_tdm_pgw_t; 112 113 typedef struct { 114 int tdm_pipe_main[TD2P_LR_VBS_LEN]; 115 int tdm_ovs_grp_0[TD2P_OS_VBS_GRP_LEN]; 116 int tdm_ovs_grp_1[TD2P_OS_VBS_GRP_LEN]; 117 int tdm_ovs_grp_2[TD2P_OS_VBS_GRP_LEN]; 118 int tdm_ovs_grp_3[TD2P_OS_VBS_GRP_LEN]; 119 int tdm_ovs_grp_4[TD2P_OS_VBS_GRP_LEN]; 120 int tdm_ovs_grp_5[TD2P_OS_VBS_GRP_LEN]; 121 int tdm_ovs_grp_6[TD2P_OS_VBS_GRP_LEN]; 122 int tdm_ovs_grp_7[TD2P_OS_VBS_GRP_LEN]; 123 } tdm_pipe_t; 124 125 typedef struct { 126 enum port_speed_e speed[TD2P_NUM_EXT_PORTS]; 127 int clk_freq; 128 enum port_state_e port_rates_array[TD2P_NUM_EXT_PORTS]; 129 int pm_encap_type[TD2P_NUM_PM_MOD]; 130 } tdm_globals_t; 131 132 typedef struct { 133 int pmap[TD2P_NUM_PHY_PM][TD2P_NUM_PM_LNS]; 134 tdm_pipe_t tdm_pipe_table_x; 135 tdm_pipe_t tdm_pipe_table_y; 136 tdm_globals_t tdm_globals; 137 td2p_tdm_pgw_t tdm_pgw; 138 } tdm_chip_legacy_t; 139 140 #ifdef _TDM_STANDALONE 141 #include <tdm_td2p_methods.h> 142 #else 143 #include <soc/tdm/trident2p/tdm_td2p_methods.h> 144 #endif 145 146 /* API shim layer */ 147 LINKER_DECL int tdm_chip_td2p_shim_core( tdm_mod_t *_tdm, tdm_chip_legacy_t *_tdm_td2p ); 148 LINKER_DECL int tdm_chip_td2p_shim__ing_wrap( tdm_mod_t *_tdm, tdm_chip_legacy_t *_tdm_td2p ); 149 LINKER_DECL int tdm_chip_td2p_shim__egr_wrap( tdm_mod_t *_tdm, tdm_chip_legacy_t *_tdm_td2p ); 150 LINKER_DECL tdm_mod_t* tdm_chip_td2p_shim__which_tsc( int port, int tsc[TD2P_NUM_PHY_PM][TD2P_NUM_PM_LNS] ); 151 LINKER_DECL tdm_mod_t* tdm_chip_td2p_shim__check_ethernet( int port, enum port_speed_e speed[TD2P_NUM_EXT_PORTS], int tsc[TD2P_NUM_PHY_PM][TD2P_NUM_PM_LNS], int traffic[TD2P_NUM_PM_MOD] ); 152 LINKER_DECL tdm_mod_t* tdm_chip_td2p_shim__check_ethernet_d( int port, enum port_speed_e speed[TD2P_NUM_EXT_PORTS], int **tsc, int traffic[TD2P_NUM_PM_MOD] ); 153 LINKER_DECL tdm_mod_t* tdm_chip_td2p_shim__scan_which_tsc_alloc( int port, int tsc[TD2P_NUM_PHY_PM][TD2P_NUM_PM_LNS] ); 154 LINKER_DECL int tdm_chip_td2p_shim__scan_which_tsc_free(tdm_mod_t *_tdm ); 155 LINKER_DECL tdm_mod_t* tdm_chip_td2p_shim__check_pipe_ethernet_alloc( int port, enum port_speed_e speed[TD2P_NUM_EXT_PORTS], int **tsc, int traffic[TD2P_NUM_PM_MOD] ); 156 LINKER_DECL int tdm_chip_td2p_shim__check_pipe_ethernet_free(tdm_mod_t *_tdm); 157 158 #endif /* TDM_TD2P_PREPROCESSOR_DIRECTIVES_H */