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tdm_th_defines.h (3470B)


      1 /*
      2  * 
      3  * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file.
      4  * 
      5  * Copyright 2007-2019 Broadcom Inc. All rights reserved.
      6  * All Rights Reserved.$
      7  *
      8  * TDM macro values for BCM56960
      9  */
     10 
     11 #ifndef TDM_TH_PREPROCESSOR_MACROS_H
     12 #define TDM_TH_PREPROCESSOR_MACROS_H
     13 
     14 /* Frequency */
     15 #define TH_CLK_950MHZ 950
     16 #define TH_CLK_850MHZ 850
     17 #define TH_CLK_765MHZ 765
     18 #define TH_CLK_672MHZ 672
     19 #define TH_CLK_645MHZ 645
     20 #define TH_CLK_545MHZ 545
     21 
     22 /* Calendar length */
     23 #define TH_LEN_950MHZ_HG 243
     24 #define TH_LEN_950MHZ_EN 250
     25 #define TH_LEN_850MHZ_HG 215
     26 #define TH_LEN_850MHZ_EN 224
     27 #define TH_LEN_765MHZ_HG 194
     28 #define TH_LEN_765MHZ_EN 202
     29 #define TH_LEN_672MHZ_HG 170
     30 #define TH_LEN_672MHZ_EN 177
     31 #define TH_LEN_645MHZ_HG 163
     32 #define TH_LEN_645MHZ_EN 170
     33 #define TH_LEN_545MHZ_HG 138
     34 #define TH_LEN_545MHZ_EN 143
     35 
     36 /* Default number of PM in chip */
     37 #define TH_NUM_PM_MOD 33
     38 #define TH_NUM_PHY_PM 32
     39 /* Default number of lanes per PM in chip */
     40 #define TH_NUM_PM_LNS 4
     41 /* Allocation length of port lookup tables */
     42 #define TH_NUM_EXT_PORTS 136
     43 
     44 /* Number of possible physical ports */
     45 #define TH_NUM_PHY_PORTS 128
     46 /* Number of scheduling blocks */
     47 #define TH_NUM_QUAD 2
     48 
     49 /* Default number of ancillary ports in calendar */
     50 #define TH_ACC_PORT_NUM 10
     51 
     52 /* Allocation length of VBS line rate calendar */
     53 #define TH_LR_VBS_LEN 256
     54 /* Allocation area of VBS port groups */
     55 #define TH_OS_VBS_GRP_NUM 8
     56 #define TH_OS_VBS_GRP_LEN 12
     57 
     58 /* Architecturally specific allocation area of VBS vector map */
     59 #define TH_VMAP_MAX_LEN TH_LR_VBS_LEN
     60 #define TH_VMAP_MAX_WID 64
     61 
     62 /* Min sister port spacing (VBS scheduler req) */
     63 #define TH_MIN_SPACING_SISTER_PORT 4
     64 /* Min same port spacing (VBS scheduler req) */
     65 #define TH_MIN_SPACING_SAME_PORT 4
     66 
     67 /* Tokenization values 
     68 		TH_OVSB_TOKEN: token for oversub round robin
     69 		TH_IDL1_TOKEN: idle slot for memreset, L2 management, other
     70 		TH_IDL2_TOKEN: idle slot guaranteed for refresh
     71 		TH_NULL_TOKEN: null slot, no pick, no opportunistic
     72 		TH_ANCL_TOKEN: reservation for ancillary soc functions
     73 */
     74 #ifdef _TDM_STANDALONE
     75 	#define TH_OVSB_TOKEN 137 
     76 	#define TH_IDL1_TOKEN 138 
     77 	#define TH_IDL2_TOKEN 139 
     78 	#define TH_NULL_TOKEN 140 
     79 	#define TH_ANCL_TOKEN (TH_NUM_EXT_PORTS+9) 
     80 #else
     81 	#define TH_OVSB_TOKEN 250 
     82 	#define TH_IDL1_TOKEN 251 
     83 	#define TH_IDL2_TOKEN 252 
     84 	#define TH_NULL_TOKEN 253 
     85 	#define TH_ANCL_TOKEN (TH_NUM_EXT_PORTS+9) 
     86 #endif
     87 
     88 /* Static port identities */
     89 #define TH_CMIC_TOKEN 0 /* Pipe 0 - CPU slot */
     90 #define TH_LPB0_TOKEN (TH_NUM_EXT_PORTS-4) /* Pipe 0 - loopback slot */
     91 #define TH_LPB1_TOKEN (TH_NUM_EXT_PORTS-3) /* Pipe 1 - loopback slot */
     92 #define TH_MGM1_TOKEN (TH_NUM_EXT_PORTS-7) /* Pipe 1 - management slot */
     93 #define TH_MGM2_TOKEN (TH_NUM_EXT_PORTS-5) /* Pipe 2 - management slot */
     94 #define TH_LPB2_TOKEN (TH_NUM_EXT_PORTS-2) /* Pipe 2 - loopback slot */
     95 #define TH_RSVD_TOKEN (TH_NUM_EXT_PORTS-6) /* Reserved slot */
     96 #define TH_LPB3_TOKEN (TH_NUM_EXT_PORTS-1) /* Pipe 3 - loopback slot */
     97 
     98 #define TH_IDB_PIPE_0_CAL_ID 0
     99 #define TH_IDB_PIPE_1_CAL_ID 1
    100 #define TH_IDB_PIPE_2_CAL_ID 2
    101 #define TH_IDB_PIPE_3_CAL_ID 3
    102 #define TH_MMU_PIPE_0_CAL_ID 4
    103 #define TH_MMU_PIPE_1_CAL_ID 5
    104 #define TH_MMU_PIPE_2_CAL_ID 6
    105 #define TH_MMU_PIPE_3_CAL_ID 7
    106 
    107 /* Linerate jitter threshold */
    108 #define TH_LR_JITTER_LO 5
    109 #define TH_LR_JITTER_MD 2
    110 #define TH_LR_JITTER_HI 1
    111 #define TH_LR_CHK_TRHD  TH_LR_JITTER_HI 
    112 
    113 #endif /* TDM_TH_PREPROCESSOR_MACROS_H */