tdm_mn_defines.h (5115B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * All Rights Reserved.$ 7 * 8 * TDM macro values for BCM56860 9 */ 10 11 #ifndef TDM_MN_PREPROCESSOR_MACROS_H 12 #define TDM_MN_PREPROCESSOR_MACROS_H 13 14 /* Default number of PM in chip */ 15 #define MN_NUM_PM_MOD 17 16 #define MN_NUM_PHY_PM 16 17 /* Default number of lanes per PM in chip */ 18 #define MN_NUM_PM_LNS 4 19 /* Allocation length of port lookup tables */ 20 #define MN_NUM_EXT_PORTS 130 21 /* Number of the hardware designated management PM */ 22 #define MN_MGMT_TSC_ID 3 23 24 #define MN_CL1_TSC_ID 7 25 #define MN_CL2_TSC_ID 8 26 #define MN_CL4_TSC_ID 16 27 #define MN_CL5_TSC_ID 17 28 #define MN_CL1_PORT 1 29 #define MN_CL2_PORT 5 30 #define MN_CL3_PORT 5 31 #define MN_CL4_PORT 13 32 #define MN_CL5_PORT 17 33 #define MN_CL6_PORT 45 34 #define MN_CL7_PORT 49 35 #define MN_CL8_PORT 53 36 #define MN_CL9_PORT 57 37 #define MN_CL10_PORT 61 38 #define MN_PGW_PER_SLOT_IO_BW 2.5 39 #define MN_PGW_NUM_SLOTS_100G 20 40 #define MN_PGW_NUM_SLOTS_50G 10 41 #define MN_PGW_NUM_SLOTS_40G 8 42 #define MN_PGW_NUM_SLOTS_25G 5 43 #define MN_PGW_NUM_SLOTS_20G 4 44 #define MN_PGW_NUM_SLOTS_12p5G 2 45 #define MN_PGW_NUM_SLOTS_10G 2 46 #define MN_PGW_NUM_SLOTS_5G 1 47 #define MN_PGW_NUM_SLOTS_2p5G 1 48 #define MN_PGW_JITTER_PERCENT_LOWER 0.3 49 #define MN_PGW_JITTER_PERCENT_UPPER 0.3 50 #define MN_MMU_JITTER_PERCENT_LOWER 0.3 51 #define MN_MMU_JITTER_PERCENT_UPPER 0.3 52 #define MMU_AUX_MIN_SPACING 8 53 #define MN_PGW_OS_TDM_DEPTH 48 54 #define MN_PGW_JITTER_PERCENT_LOWER 0.3 55 #define MN_PGW_JITTER_PERCENT_UPPER 0.3 56 #define MN_MMU_JITTER_PERCENT_LOWER 0.3 57 #define MN_MMU_JITTER_PERCENT_UPPER 0.3 58 #define MN_LEN_415MHZ_HG 109 59 #define MN_LEN_415MHZ_EN 109 60 #define MN_LEN_705MHZ_HG 186 61 #define MN_LEN_705MHZ_EN 186 62 #define MN_LEN_815MHZ_HG 321 63 #define MN_LEN_815MHZ_EN 321 64 #define MN_LEN_525MHZ_HG 138 65 #define MN_LEN_525MHZ_EN 138 66 #define MN_LEN_816MHZ_HG 297 67 #define MN_LEN_816MHZ_EN 297 68 #define MN_LEN_817MHZ_HG 302 69 #define MN_LEN_817MHZ_EN 302 70 #define MN_LEN_818MHZ_EN 334 71 #define MN_LEN_819MHZ_EN 283 72 #define MN_LEN_820MHZ_EN 335 73 #define MN_LEN_861MHZ_EN 227 74 #define MN_LEN_862MHZ_EN 227 75 #define MN_LEN_550MHZ_EN 217 76 #define MN_LEN_550MHZ_HG 217 77 #define MN_LEN_666MHZ_EN 160 78 #define MN_LEN_667MHZ_EN 160 79 80 /* Number of possible physical ports */ 81 #define MN_NUM_PHY_PORTS 64 82 #define MN_EXT_PLUS_CPU_PORT (MN_NUM_PHY_PORTS+1) 83 #define MN_EXT_PLUS_CPU_MACSEC_PORT (MN_EXT_PLUS_CPU_PORT+1) 84 /* Number of scheduling blocks */ 85 #define MN_NUM_QUAD 2 86 87 /* Default number of ancillary ports in calendar */ 88 #define MN_ACC_PORT_NUM 14 89 90 91 #define MN_MIN_SPACING_SAME_PORT_HSP 4 92 #define MN_MIN_SPACING_SISTER_PORT 0 93 94 /* Allocation length of LLS line rate calendar */ 95 #define MN_TDM_AUX_SIZE 320 96 #define MN_LR_LLS_LEN 160 /* Monterey PGW has LR TDM depth of 128 which was 64 in Apache */ 97 #define MN_PM_PER_PGW 8 /* Monterey has 8 PM per PGW */ 98 /* Allocation length of VBS line rate calendar */ 99 #define MN_LR_VBS_LEN 512 100 /* Allocation length of IARB static calendar */ 101 #define MN_LR_IARB_STATIC_LEN 512 102 /* Allocation area of LLS port groups */ 103 #define MN_OS_LLS_GRP_NUM 2 104 #define MN_OS_LLS_GRP_LEN 48 105 /* Allocation area of VBS port groups */ 106 #define MN_OS_VBS_GRP_NUM 8 107 #define MN_OS_VBS_GRP_LEN 16 108 109 /* Architecturally specific allocation area of VBS vector map */ 110 #define MN_VMAP_MAX_LEN 512 111 #define MN_VMAP_MAX_WID 67 112 113 /* Tokenization values */ 114 #ifdef _TDM_STANDALONE 115 /* Token for pmap management port */ 116 #define MN_MGMT_TOKEN (MN_NUM_EXT_PORTS+3) 117 /* Token for granularity scaling */ 118 #define MN_US1G_TOKEN (MN_NUM_EXT_PORTS+4) 119 /* Token for ancillary soc functions */ 120 #define MN_ANCL_TOKEN (MN_NUM_PHY_PORTS+5) 121 /* Token for oversub round robin */ 122 #define MN_OVSB_TOKEN (MN_EXT_PLUS_CPU_PORT+3) 123 /* Memreset, L2 management, other */ 124 #define MN_IDL1_TOKEN 69 125 /* EP refresh, idle cycle */ 126 #define MN_IDL2_TOKEN MN_IDL1_TOKEN 127 /* EP aux cycle */ 128 #define MN_AUX_TOKEN 70 129 /* Dedicated SBUS Op */ 130 #define MN_SBUS_TOKEN 74 131 #else 132 /* Token for pmap management port */ 133 #define MN_MGMT_TOKEN (MN_NUM_EXT_PORTS+3) 134 /* Token for granularity scaling */ 135 #define MN_US1G_TOKEN (MN_NUM_EXT_PORTS+4) 136 /* Token for ancillary soc functions */ 137 #define MN_ANCL_TOKEN (MN_NUM_EXT_PORTS+5) 138 /* Token for oversub round robin */ 139 #define MN_OVSB_TOKEN 250 140 /* Memreset, L2 management, other */ 141 #define MN_IDL1_TOKEN 251 142 /* EP refresh, idle cycle */ 143 #define MN_IDL2_TOKEN MN_IDL1_TOKEN 144 /* EP aux cycle */ 145 #define MN_AUX_TOKEN 253 146 #define MN_SBUS_TOKEN 254 147 #endif 148 149 #define MMU_OVRSUB_PORT 57 150 #define MMU_NULL_PORT 58 151 152 /* Static port identities */ 153 /*#define MN_MGMT_PORT_0 103 */ /*nak,dummy MGMT PORT defines*/ 154 /*#define MN_MGMT_PORT_1 104 155 #define MN_MGMT_PORT_2 105 156 #define MN_MGMT_PORT_3 106*/ 157 #define MN_LOOPBACK_PORT 65 158 #define MN_MACSEC_PORT 66 159 #define MN_CPU_PORT 0 160 161 /* Macro definitions */ 162 #define MN_PIPE_X_ID 0 163 #define MN_PIPE_Y_ID 1 164 165 #define MN_XPIPE_CAL_ID 2 166 #define MN_YPIPE_CAL_ID 5 167 168 169 #endif /* TDM_MN_PREPROCESSOR_MACROS_H */