tdm_mv2_defines.h (6660B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * All Rights Reserved.$ 7 * 8 * TDM macro values for Maverick2 9 */ 10 11 #ifndef TDM_MV2_PREPROCESSOR_MACROS_H 12 #define TDM_MV2_PREPROCESSOR_MACROS_H 13 14 /* Device ID */ 15 #ifdef _TDM_STANDALONE 16 #define TDM_MV2_DEV_ID_MASK 0xffff 17 #define TDM_MV2_DEV_ID_BCM56770 56770 18 #define TDM_MV2_DEV_ID_BCM56771 56771 19 #else 20 #define TDM_MV2_DEV_ID_MASK 0x0fff 21 #define TDM_MV2_DEV_ID_BCM56770 0x56770 22 #define TDM_MV2_DEV_ID_BCM56771 0x56771 23 #endif 24 25 /* Frequency */ 26 #define MV2_CLK_1700MHZ 1700 27 #define MV2_CLK_1625MHZ 1625 28 #define MV2_CLK_1525MHZ 1525 29 #define MV2_CLK_1425MHZ 1425 30 #define MV2_CLK_1325MHZ 1325 31 #define MV2_CLK_1275MHZ 1275 32 #define MV2_CLK_1133MHZ 1133 33 #define MV2_CLK_1125MHZ 1125 34 #define MV2_CLK_1083MHZ 1083 35 #define MV2_CLK_1016MHZ 1016 36 #define MV2_CLK_1012MHZ 1012 37 #define MV2_CLK_950MHZ 950 38 #define MV2_CLK_883MHZ 883 39 #define MV2_CLK_850MHZ 850 40 41 /* Calendar Length */ 42 #define MV2_LEN_1700MHZ_HG 430 43 #define MV2_LEN_1700MHZ_EN 456 44 #define MV2_LEN_1625MHZ_HG 411 45 #define MV2_LEN_1625MHZ_EN 436 46 #define MV2_LEN_1525MHZ_HG 386 47 #define MV2_LEN_1525MHZ_EN 408 48 #define MV2_LEN_1425MHZ_HG 361 49 #define MV2_LEN_1425MHZ_EN 383 50 #define MV2_LEN_1325MHZ_HG 335 51 #define MV2_LEN_1325MHZ_EN 356 52 #define MV2_LEN_1275MHZ_HG 323 53 #define MV2_LEN_1275MHZ_EN 342 54 #define MV2_LEN_1133MHZ_HG 287 55 #define MV2_LEN_1133MHZ_EN 304 56 #define MV2_LEN_1125MHZ_HG 285 57 #define MV2_LEN_1125MHZ_EN 302 58 #define MV2_LEN_1083MHZ_HG 274 59 #define MV2_LEN_1083MHZ_EN 291 60 #define MV2_LEN_1016MHZ_HG 257 61 #define MV2_LEN_1016MHZ_EN 273 62 #define MV2_LEN_1012MHZ_HG 256 63 #define MV2_LEN_1012MHZ_EN 272 64 #define MV2_LEN_950MHZ_HG 240 65 #define MV2_LEN_950MHZ_EN 255 66 #define MV2_LEN_883MHZ_HG 223 67 #define MV2_LEN_883MHZ_EN 237 68 #define MV2_LEN_850MHZ_HG 215 69 #define MV2_LEN_850MHZ_EN 228 70 71 /* Default number of PM in chip */ 72 #define MV2_NUM_PHY_PM 20 /* 20 -> 18 */ 73 #define MV2_NUM_PM_MOD 21 /* 21 -> 19 */ 74 /* Default number of lanes per PM in chip */ 75 #define MV2_NUM_PM_LNS 4 76 /* Number of logical ports: phy ports + cpu + mgmt + lpbk : 83 -> 75 */ 77 #define MV2_NUM_EXT_PORTS 83 78 79 /* Number of physical ports : 80 -> 72 */ 80 #define MV2_NUM_PHY_PORTS 80 81 /* Number of scheduling blocks */ 82 #define MV2_NUM_QUAD 1 83 /* Number of scheduling blocks */ 84 #define MV2_NUM_PIPE 1 85 /* Number of possible physical ports per pipe : 80 -> 72 */ 86 #define MV2_NUM_PHY_PORTS_PER_PIPE (MV2_NUM_PHY_PORTS / MV2_NUM_PIPE) 87 /* Number of possible physical ports per halfpipe: 40 -> 36 */ 88 #define MV2_NUM_PHY_PORTS_PER_HPIPE (MV2_NUM_PHY_PORTS_PER_PIPE / 2) 89 /* Number of PMs per pipe : 20 -> 18 */ 90 #define MV2_NUM_PMS_PER_PIPE (MV2_NUM_PHY_PM / MV2_NUM_PIPE) 91 /* Number of PMs per halfpipe : 10 -> 9 */ 92 #define MV2_NUM_PMS_PER_HPIPE (MV2_NUM_PHY_PM / MV2_NUM_PIPE / 2) 93 94 /* Number of slots per lane in OVSB Packet Scheduler */ 95 #define MV2_NUM_PKT_SLOTS_PER_LANE 5 96 /* Number of slots per PM in OVSB Packet Scheduler */ 97 #define MV2_NUM_PKT_SLOTS_PER_PM 20 98 99 /* Default number of ancillary ports in calendar */ 100 #define MV2_NUM_ANCL 16 101 #define MV2_NUM_ANCL_CPU 4 102 #define MV2_NUM_ANCL_MGMT 4 103 #define MV2_NUM_ANCL_LPBK 4 104 #define MV2_NUM_ANCL_IDB_OPT1 1 105 #define MV2_NUM_ANCL_IDB_NULL 1 106 #define MV2_NUM_ANCL_IDB_IDLE 2 107 #define MV2_NUM_ANCL_MMU_OPT1 0 108 #define MV2_NUM_ANCL_MMU_NULL 3 109 #define MV2_NUM_ANCL_MMU_IDLE 1 110 111 /* Allocation length of VBS line rate calendar */ 112 #define MV2_LR_VBS_LEN 512 113 /* Allocation area of VBS port groups */ 114 #define MV2_OS_VBS_GRP_NUM 12 115 #define MV2_OS_VBS_GRP_LEN 12 116 117 /* Architecturally specific allocation area of VBS vector map */ 118 #define MV2_VMAP_MAX_LEN MV2_LR_VBS_LEN 119 #define MV2_VMAP_MAX_WID 128 120 121 /* Min sister port spacing (VBS scheduler req) */ 122 #define MV2_MIN_SPACING_SISTER_PORT 4 123 /* Min sister port spacing (VBS scheduler req) */ 124 #define MV2_MIN_SPACING_SAME_PORT_HSP 8 125 #define MV2_MIN_SPACING_SAME_PORT_LSP 14 126 127 /* Static port identities (global) 128 MV2_CMIC_TOKEN ( 0): Pipe 0 - CPU slot 129 MV2_MGM1_TOKEN (81): Pipe 0 - management slot 130 MV2_LPB0_TOKEN (82): Pipe 0 - loopback slot 131 132 MV2_MGM2_TOKEN (900): unused 133 MV2_LPB1_TOKEN (901): unused 134 */ 135 #define MV2_CMIC_TOKEN 0 136 #define MV2_MGM1_TOKEN (MV2_NUM_EXT_PORTS-2) 137 #define MV2_LPB0_TOKEN (MV2_NUM_EXT_PORTS-1) 138 #define MV2_MGM2_TOKEN 900 139 #define MV2_LPB1_TOKEN 901 140 141 /* Tokenization values (global) 142 MV2_OVSB_TOKEN (84): token for oversub round robin 143 MV2_IDL1_TOKEN (85): idle slot for memreset, L2 management, SBus 144 MV2_IDL2_TOKEN (86): idle slot guaranteed for refresh 145 MV2_NULL_TOKEN (87): null slot, no pick, no opportunistic 146 */ 147 #define MV2_OVSB_TOKEN (MV2_NUM_EXT_PORTS+1) 148 #define MV2_IDL1_TOKEN (MV2_NUM_EXT_PORTS+2) 149 #define MV2_IDL2_TOKEN (MV2_NUM_EXT_PORTS+3) 150 #define MV2_NULL_TOKEN (MV2_NUM_EXT_PORTS+4) 151 152 /* Tokenization values (for TDM internal usage) 153 MV2_ANCL_TOKEN (93): reservation for ancillary soc functions 154 */ 155 #define MV2_ANCL_TOKEN (MV2_NUM_EXT_PORTS+10) 156 157 /* Calendar ID */ 158 #define MV2_IDB_PIPE_0_CAL_ID 0 159 #define MV2_IDB_PIPE_1_CAL_ID 1 160 #define MV2_IDB_PIPE_2_CAL_ID 2 161 #define MV2_IDB_PIPE_3_CAL_ID 3 162 #define MV2_MMU_PIPE_0_CAL_ID 4 163 #define MV2_MMU_PIPE_1_CAL_ID 5 164 #define MV2_MMU_PIPE_2_CAL_ID 6 165 #define MV2_MMU_PIPE_3_CAL_ID 7 166 167 /* Physical port number range of each pipe */ 168 #define MV2_CAL_0_PORT_LO 1 169 #define MV2_CAL_0_PORT_HI 80 170 #define MV2_CAL_1_PORT_LO 0 171 #define MV2_CAL_1_PORT_HI 0 172 #define MV2_CAL_2_PORT_LO 0 173 #define MV2_CAL_2_PORT_HI 0 174 #define MV2_CAL_3_PORT_LO 0 175 #define MV2_CAL_3_PORT_HI 0 176 #define MV2_CAL_4_PORT_LO 1 177 #define MV2_CAL_4_PORT_HI 80 178 #define MV2_CAL_5_PORT_LO 0 179 #define MV2_CAL_5_PORT_HI 0 180 #define MV2_CAL_6_PORT_LO 0 181 #define MV2_CAL_6_PORT_HI 0 182 #define MV2_CAL_7_PORT_LO 0 183 #define MV2_CAL_7_PORT_HI 0 184 185 /* Management port mode (10G per management port) 186 0 -> Etherner management port (default) 187 1 -> Disable management port 188 2 -> HiGig management port 189 */ 190 enum mv2_mgmt_mode_e { 191 MV2_MGMT_MODE_PORT_EN=0, 192 MV2_MGMT_MODE_PORT_DISABLE=1, 193 MV2_MGMT_MODE_PORT_HG=2 194 }; 195 196 /* Index and length of shaping calendar within each inst */ 197 #define MV2_SHAPING_GRP_NUM 2 198 #define MV2_SHAPING_GRP_LEN (MV2_NUM_PMS_PER_HPIPE * MV2_NUM_PKT_SLOTS_PER_PM) 199 #define MV2_SHAPING_GRP_IDX_0 MV2_OS_VBS_GRP_NUM 200 #define MV2_SHAPING_GRP_IDX_1 (MV2_OS_VBS_GRP_NUM+1) 201 202 /* Linerate jitter threshold */ 203 #define MV2_LR_JITTER_LO 5 204 #define MV2_LR_JITTER_MD 2 205 #define MV2_LR_JITTER_HI 1 206 #define MV2_LR_CHK_TRHD 0 207 208 /* Number of speed types in enum mv2_port_speed_indx_e */ 209 #define MV2_PORT_SPEED_INDX_SIZE 6 210 211 #endif /* TDM_MV2_PREPROCESSOR_MACROS_H */