tdm_hx5_defines.h (5650B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * All Rights Reserved.$ 7 * 8 * TDM macro values for BCM56870 9 */ 10 11 #ifndef TDM_HX5_PREPROCESSOR_MACROS_H 12 #define TDM_HX5_PREPROCESSOR_MACROS_H 13 14 15 16 /* Frequency */ 17 18 #define HX5_CLK_450MHZ 450 19 #define HX5_CLK_400MHZ 400 20 #define HX5_CLK_543MHZ 543 21 #define HX5_CLK_587MHZ 587 22 #define HX5_CLK_668MHZ 668 23 #define HX5_CLK_812MHZ 812 24 #define HX5_CLK_893MHZ 893 25 #define HX5_CLK_931MHZ 931 26 27 /* Calendar Length */ 28 29 #define HX5_LEN_400MHZ 214 30 #define HX5_LEN_400HMHZ 202 31 #define HX5_LEN_450MHZ 240 32 #define HX5_LEN_450HMHZ 228 33 #define HX5_LEN_543MHZ 292 34 #define HX5_LEN_587MHZ 314 35 #define HX5_LEN_587HMHZ 297 36 #define HX5_LEN_668MHZ 358 37 #define HX5_LEN_812MHZ 436 38 #define HX5_LEN_893MHZ 480 39 #define HX5_LEN_931MHZ 472 40 41 42 43 /* Default number of PM in chip */ 44 #define HX5_NUM_PM_MOD 19 45 #define HX5_NUM_PHY_PM 19 46 #define HX5_NUM_PHY_GPORTS 48 47 /* Default number of lanes per PM in chip */ 48 #define HX5_NUM_PM_LNS 4 49 /* Allocation length of port lookup tables */ 50 #define HX5_NUM_EXT_PORTS 79 51 52 /* Number of possible physical ports */ 53 #define HX5_NUM_PHY_PORTS 76 54 /* Number of scheduling blocks */ 55 #define HX5_NUM_QUAD 2 56 /* Number of scheduling blocks */ 57 #define HX5_NUM_PIPE 1 58 /* Number of possible physical ports per pipe */ 59 #define HX5_NUM_PHY_PORTS_PER_PIPE 76 60 /* Number of possible physical ports per halfpipe */ 61 #define HX5_NUM_PHY_PORTS_PER_HPIPE 38 62 63 /* Number of slots per lane in OVSB Packet Scheduler */ 64 #define HX5_NUM_PKT_SLOTS_PER_PM 16 65 66 /* Default number of ancillary ports in calendar */ 67 #define HX5_NUM_ANCL 24 68 #define HX5_NUM_ANCL_CPU 4 69 #define HX5_NUM_ANCL_FAE 4 70 #define HX5_NUM_ANCL_LPBK 8 71 #define HX5_NUM_ANCL_IDB_OPT1 2 72 #define HX5_NUM_ANCL_IDB_NULL 2 73 #define HX5_NUM_ANCL_IDB_IDLE 4 74 75 #define HX5_NUM_ANCL_MMU_OPT1 0 76 #define HX5_NUM_ANCL_MMU_NULL 6 77 #define HX5_NUM_ANCL_MMU_IDLE 4 78 79 /* Allocation length of VBS line rate calendar */ 80 #define HX5_LR_VBS_LEN 512 81 /* Allocation area of VBS port groups */ 82 #define HX5_OS_VBS_GRP_NUM 12 83 #define HX5_OS_VBS_GRP_LEN 12 84 85 /* Architecturally specific allocation area of VBS vector map */ 86 #define HX5_VMAP_MAX_LEN HX5_LR_VBS_LEN 87 /* num of physical ports for vmap scheduler */ 88 #define HX5_VMAP_MAX_WID 76 89 90 /* Min sister port spacing (VBS scheduler req) 4-2 */ 91 #define HX5_MIN_SPACING_SISTER_PORT 2 92 #define HX5_MIN_SPACING_SISTER_FALCON_PORT 2 93 #define HX5_MIN_SPACING_SISTER_EAGLE_PORT 4 94 /* Min sister port spacing (VBS scheduler req) 8 - 6 , 14 - 6*/ 95 #define HX5_MIN_SPACING_SAME_PORT_HSP 6 96 #define HX5_MIN_SPACING_SAME_PORT_LSP 6 97 98 /* static port identities 99 HX5_CMIC_TOKEN ( 0): Pipe 0 - CPU slot 100 HX5_MGM1_TOKEN (129): Pipe 1 - management port 1 slot 101 HX5_MGM2_TOKEN (128): Pipe 1 - management port 2 slot 102 HX5_LPB0_TOKEN (130): Pipe 0 - loopback slot 103 HX5_LPB1_TOKEN (131): Pipe 1 - loopback slot 104 */ 105 #define HX5_CMIC_TOKEN 0 106 #define HX5_FAE_TOKEN 78 107 /* #define HX5_MGM2_TOKEN (HX5_NUM_EXT_PORTS+3) */ 108 /*#define HX5_LPB0_TOKEN (HX5_NUM_EXT_PORTS+1)*/ 109 #define HX5_LPB0_TOKEN 77 110 /*#define HX5_LPB1_TOKEN (HX5_NUM_EXT_PORTS+1)*/ 111 /* Tokenization values 112 HX5_OVSB_TOKEN (133): token for oversub round robin 113 HX5_IDL1_TOKEN (134): idle slot for memreset, L2 management, other 114 HX5_IDL2_TOKEN (135): idle slot guaranteed for refresh 115 HX5_NULL_TOKEN (136): null slot, no pick, no opportunistic 116 HX5_ANCL_TOKEN (142): reservation for ancillary soc functions 117 */ 118 #define HX5_OVSB_TOKEN (HX5_NUM_EXT_PORTS+4) 119 #define HX5_IDL1_TOKEN (HX5_NUM_EXT_PORTS+5) 120 #define HX5_IDL2_TOKEN (HX5_NUM_EXT_PORTS+6) 121 #define HX5_NULL_TOKEN (HX5_NUM_EXT_PORTS+7) 122 #define HX5_ANCL_TOKEN (HX5_NUM_EXT_PORTS+10) 123 124 /* Calendar ID */ 125 #define HX5_IDB_PIPE_0_CAL_ID 0 126 #define HX5_IDB_PIPE_1_CAL_ID 1 127 #define HX5_IDB_PIPE_2_CAL_ID 2 128 #define HX5_IDB_PIPE_3_CAL_ID 3 129 #define HX5_MMU_PIPE_0_CAL_ID 4 130 #define HX5_MMU_PIPE_1_CAL_ID 5 131 #define HX5_MMU_PIPE_2_CAL_ID 6 132 #define HX5_MMU_PIPE_3_CAL_ID 7 133 134 /* Physical port number range of each pipe */ 135 #define HX5_CAL_0_PORT_LO 1 136 #define HX5_CAL_0_PORT_HI 76 137 #define HX5_CAL_1_PORT_LO 0 138 #define HX5_CAL_1_PORT_HI 0 139 #define HX5_CAL_2_PORT_LO 0 140 #define HX5_CAL_2_PORT_HI 0 141 #define HX5_CAL_3_PORT_LO 0 142 #define HX5_CAL_3_PORT_HI 0 143 #define HX5_CAL_4_PORT_LO 1 144 #define HX5_CAL_4_PORT_HI 76 145 #define HX5_CAL_5_PORT_LO 0 146 #define HX5_CAL_5_PORT_HI 0 147 #define HX5_CAL_6_PORT_LO 0 148 #define HX5_CAL_6_PORT_HI 0 149 #define HX5_CAL_7_PORT_LO 0 150 #define HX5_CAL_7_PORT_HI 0 151 152 /* Management port mode (10G per management port) 153 0 -> two Etherner management ports (default) 154 1 -> one Ethernet management port 155 2 -> two HiGig management ports (reserved) 156 3 -> one HiGig management port (reserved) 157 */ 158 enum hx5_mgmt_mode_e { 159 HX5_MGMT_MODE_2_PORT_EN=0, 160 HX5_MGMT_MODE_1_PORT_EN=1, 161 HX5_MGMT_MODE_2_PORT_HG=2, 162 HX5_MGMT_MODE_1_PORT_HG=3 163 }; 164 165 /* 1G port state 166 0 -> None 1G port 167 1 -> Regular 1G port 168 2 -> PM4x10Q 1G port (16x1G super PM subport) 169 */ 170 enum hx5_1g_port_state_e { 171 HX5_1G_PORT_STATE_NONE=0, 172 HX5_1G_PORT_STATE_REGULAR=1, 173 HX5_1G_PORT_STATE_16x1G=2, 174 HX5_1G_PORT_STATE_16x2G=3 175 }; 176 /* Index and length of shaping calendar within each inst */ 177 #define HX5_SHAPING_GRP_NUM 2 178 #define HX5_SHAPING_GRP_LEN 160 179 #define HX5_SHAPING_GRP_IDX_0 HX5_OS_VBS_GRP_NUM 180 #define HX5_SHAPING_GRP_IDX_1 (HX5_OS_VBS_GRP_NUM+1) 181 182 /* Linerate jitter threshold */ 183 #define HX5_LR_JITTER_LO 5 184 #define HX5_LR_JITTER_MD 2 185 #define HX5_LR_JITTER_HI 1 186 #define HX5_LR_CHK_TRHD 0 187 188 #endif /* TDM_HX5_PREPROCESSOR_MACROS_H */