tdm_gh2_soc.h (6039B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * All Rights Reserved.$ 7 * 8 * TDM soc header for BCM53570 9 */ 10 11 #ifndef TDM_BCM53570_PREPROCESSOR_SOC_DEFINES_H 12 #define TDM_BCM53570_PREPROCESSOR_SOC_DEFINES_H 13 14 #ifdef _TDM_STANDALONE 15 #include <tdm_gh2_defines.h> 16 #else 17 #include <soc/tdm/greyhound2/tdm_gh2_defines.h> 18 #endif 19 20 #define _SOC_GH2_TDM_LR_VBS_LEN 256 21 #define _SOC_GH2_TDM_OS_VBS_GRP_LEN 12 22 #define _SOC_GH2_TDM_NUM_EXT_PORTS 136 23 #define _SOC_GH2_TDM_NUM_PM_MOD 33 24 25 typedef struct _tdm_gh2_pipes_s { 26 int idb_tdm_tbl_0[_SOC_GH2_TDM_LR_VBS_LEN]; 27 int idb_tdm_ovs_0_a[_SOC_GH2_TDM_OS_VBS_GRP_LEN]; 28 int idb_tdm_ovs_0_b[_SOC_GH2_TDM_OS_VBS_GRP_LEN]; 29 int idb_tdm_ovs_0_c[_SOC_GH2_TDM_OS_VBS_GRP_LEN]; 30 int idb_tdm_ovs_0_d[_SOC_GH2_TDM_OS_VBS_GRP_LEN]; 31 int idb_tdm_ovs_0_e[_SOC_GH2_TDM_OS_VBS_GRP_LEN]; 32 int idb_tdm_ovs_0_f[_SOC_GH2_TDM_OS_VBS_GRP_LEN]; 33 int idb_tdm_ovs_0_g[_SOC_GH2_TDM_OS_VBS_GRP_LEN]; 34 int idb_tdm_ovs_0_h[_SOC_GH2_TDM_OS_VBS_GRP_LEN]; 35 int idb_tdm_tbl_1[_SOC_GH2_TDM_LR_VBS_LEN]; 36 int idb_tdm_ovs_1_a[_SOC_GH2_TDM_OS_VBS_GRP_LEN]; 37 int idb_tdm_ovs_1_b[_SOC_GH2_TDM_OS_VBS_GRP_LEN]; 38 int idb_tdm_ovs_1_c[_SOC_GH2_TDM_OS_VBS_GRP_LEN]; 39 int idb_tdm_ovs_1_d[_SOC_GH2_TDM_OS_VBS_GRP_LEN]; 40 int idb_tdm_ovs_1_e[_SOC_GH2_TDM_OS_VBS_GRP_LEN]; 41 int idb_tdm_ovs_1_f[_SOC_GH2_TDM_OS_VBS_GRP_LEN]; 42 int idb_tdm_ovs_1_g[_SOC_GH2_TDM_OS_VBS_GRP_LEN]; 43 int idb_tdm_ovs_1_h[_SOC_GH2_TDM_OS_VBS_GRP_LEN]; 44 int idb_tdm_tbl_2[_SOC_GH2_TDM_LR_VBS_LEN]; 45 int idb_tdm_ovs_2_a[_SOC_GH2_TDM_OS_VBS_GRP_LEN]; 46 int idb_tdm_ovs_2_b[_SOC_GH2_TDM_OS_VBS_GRP_LEN]; 47 int idb_tdm_ovs_2_c[_SOC_GH2_TDM_OS_VBS_GRP_LEN]; 48 int idb_tdm_ovs_2_d[_SOC_GH2_TDM_OS_VBS_GRP_LEN]; 49 int idb_tdm_ovs_2_e[_SOC_GH2_TDM_OS_VBS_GRP_LEN]; 50 int idb_tdm_ovs_2_f[_SOC_GH2_TDM_OS_VBS_GRP_LEN]; 51 int idb_tdm_ovs_2_g[_SOC_GH2_TDM_OS_VBS_GRP_LEN]; 52 int idb_tdm_ovs_2_h[_SOC_GH2_TDM_OS_VBS_GRP_LEN]; 53 int idb_tdm_tbl_3[_SOC_GH2_TDM_LR_VBS_LEN]; 54 int idb_tdm_ovs_3_a[_SOC_GH2_TDM_OS_VBS_GRP_LEN]; 55 int idb_tdm_ovs_3_b[_SOC_GH2_TDM_OS_VBS_GRP_LEN]; 56 int idb_tdm_ovs_3_c[_SOC_GH2_TDM_OS_VBS_GRP_LEN]; 57 int idb_tdm_ovs_3_d[_SOC_GH2_TDM_OS_VBS_GRP_LEN]; 58 int idb_tdm_ovs_3_e[_SOC_GH2_TDM_OS_VBS_GRP_LEN]; 59 int idb_tdm_ovs_3_f[_SOC_GH2_TDM_OS_VBS_GRP_LEN]; 60 int idb_tdm_ovs_3_g[_SOC_GH2_TDM_OS_VBS_GRP_LEN]; 61 int idb_tdm_ovs_3_h[_SOC_GH2_TDM_OS_VBS_GRP_LEN]; 62 int mmu_tdm_tbl_0[_SOC_GH2_TDM_LR_VBS_LEN]; 63 int mmu_tdm_ovs_0_a[_SOC_GH2_TDM_OS_VBS_GRP_LEN]; 64 int mmu_tdm_ovs_0_b[_SOC_GH2_TDM_OS_VBS_GRP_LEN]; 65 int mmu_tdm_ovs_0_c[_SOC_GH2_TDM_OS_VBS_GRP_LEN]; 66 int mmu_tdm_ovs_0_d[_SOC_GH2_TDM_OS_VBS_GRP_LEN]; 67 int mmu_tdm_ovs_0_e[_SOC_GH2_TDM_OS_VBS_GRP_LEN]; 68 int mmu_tdm_ovs_0_f[_SOC_GH2_TDM_OS_VBS_GRP_LEN]; 69 int mmu_tdm_ovs_0_g[_SOC_GH2_TDM_OS_VBS_GRP_LEN]; 70 int mmu_tdm_ovs_0_h[_SOC_GH2_TDM_OS_VBS_GRP_LEN]; 71 int mmu_tdm_tbl_1[_SOC_GH2_TDM_LR_VBS_LEN]; 72 int mmu_tdm_ovs_1_a[_SOC_GH2_TDM_OS_VBS_GRP_LEN]; 73 int mmu_tdm_ovs_1_b[_SOC_GH2_TDM_OS_VBS_GRP_LEN]; 74 int mmu_tdm_ovs_1_c[_SOC_GH2_TDM_OS_VBS_GRP_LEN]; 75 int mmu_tdm_ovs_1_d[_SOC_GH2_TDM_OS_VBS_GRP_LEN]; 76 int mmu_tdm_ovs_1_e[_SOC_GH2_TDM_OS_VBS_GRP_LEN]; 77 int mmu_tdm_ovs_1_f[_SOC_GH2_TDM_OS_VBS_GRP_LEN]; 78 int mmu_tdm_ovs_1_g[_SOC_GH2_TDM_OS_VBS_GRP_LEN]; 79 int mmu_tdm_ovs_1_h[_SOC_GH2_TDM_OS_VBS_GRP_LEN]; 80 int mmu_tdm_tbl_2[_SOC_GH2_TDM_LR_VBS_LEN]; 81 int mmu_tdm_ovs_2_a[_SOC_GH2_TDM_OS_VBS_GRP_LEN]; 82 int mmu_tdm_ovs_2_b[_SOC_GH2_TDM_OS_VBS_GRP_LEN]; 83 int mmu_tdm_ovs_2_c[_SOC_GH2_TDM_OS_VBS_GRP_LEN]; 84 int mmu_tdm_ovs_2_d[_SOC_GH2_TDM_OS_VBS_GRP_LEN]; 85 int mmu_tdm_ovs_2_e[_SOC_GH2_TDM_OS_VBS_GRP_LEN]; 86 int mmu_tdm_ovs_2_f[_SOC_GH2_TDM_OS_VBS_GRP_LEN]; 87 int mmu_tdm_ovs_2_g[_SOC_GH2_TDM_OS_VBS_GRP_LEN]; 88 int mmu_tdm_ovs_2_h[_SOC_GH2_TDM_OS_VBS_GRP_LEN]; 89 int mmu_tdm_tbl_3[_SOC_GH2_TDM_LR_VBS_LEN]; 90 int mmu_tdm_ovs_3_a[_SOC_GH2_TDM_OS_VBS_GRP_LEN]; 91 int mmu_tdm_ovs_3_b[_SOC_GH2_TDM_OS_VBS_GRP_LEN]; 92 int mmu_tdm_ovs_3_c[_SOC_GH2_TDM_OS_VBS_GRP_LEN]; 93 int mmu_tdm_ovs_3_d[_SOC_GH2_TDM_OS_VBS_GRP_LEN]; 94 int mmu_tdm_ovs_3_e[_SOC_GH2_TDM_OS_VBS_GRP_LEN]; 95 int mmu_tdm_ovs_3_f[_SOC_GH2_TDM_OS_VBS_GRP_LEN]; 96 int mmu_tdm_ovs_3_g[_SOC_GH2_TDM_OS_VBS_GRP_LEN]; 97 int mmu_tdm_ovs_3_h[_SOC_GH2_TDM_OS_VBS_GRP_LEN]; 98 } _tdm_gh2_pipes_t; 99 100 #define _TDM_LENGTH 256 101 #define _OVS_GROUP_COUNT 6 102 #define _OVS_GROUP_TDM_LENGTH 12 103 #define NULL_TOKEN 253 104 105 #define PORT_HIGIG2 999 106 #define PORT_ETHERNET 998 107 108 /* Value hardcoded in set_tdm.c, definition needs to be matched */ 109 #define PORT_STATE_UNUSED 0 110 #define PORT_STATE_LINERATE 1 111 #define PORT_STATE_OVERSUB 2 112 #define PORT_STATE_CONTINUATION 3 /* part of other port */ 113 114 #define GH2_PIPES_PER_DEV 4 115 #define GH2_PBLKS_PER_DEV 32 116 117 typedef struct _tdm_gh2_globals_s { 118 enum port_speed_e speed[_SOC_GH2_TDM_NUM_EXT_PORTS]; 119 int clk_freq; 120 int port_rates_array[_SOC_GH2_TDM_NUM_EXT_PORTS]; 121 int pm_encap_type[_SOC_GH2_TDM_NUM_PM_MOD]; 122 } _tdm_gh2_globals_t; 123 124 typedef struct _soc_gh2_tdm_s { 125 int speed[GH2_NUM_EXT_PORTS]; 126 int port_state[GH2_NUM_EXT_PORTS]; /* 0-unused, 1-line rate, 2-oversub, 127 * 3-part of other port 128 */ 129 /* 130 int idb_tdm[GH2_PIPES_PER_DEV][_TDM_LENGTH]; 131 int idb_ovs_tdm[GH2_PIPES_PER_DEV][_OVS_GROUP_COUNT][_OVS_GROUP_TDM_LENGTH]; 132 int mmu_tdm[GH2_PIPES_PER_DEV][_TDM_LENGTH]; 133 int mmu_ovs_tdm[GH2_PIPES_PER_DEV][_OVS_GROUP_COUNT][_OVS_GROUP_TDM_LENGTH]; 134 */ 135 int *idb_tdm[GH2_PIPES_PER_DEV]; 136 int *idb_ovs_tdm[GH2_PIPES_PER_DEV][_OVS_GROUP_COUNT]; 137 int *mmu_tdm[GH2_PIPES_PER_DEV]; 138 int *mmu_ovs_tdm[GH2_PIPES_PER_DEV][_OVS_GROUP_COUNT]; 139 140 int pm_encap_type[GH2_NUM_PM_MOD]; 141 142 _tdm_gh2_globals_t tdm_globals; 143 _tdm_gh2_pipes_t tdm_pipe_tables; 144 145 /* Following fields are not arguments to the TDM code */ 146 int port_ratio[GH2_PBLKS_PER_DEV]; 147 int ovs_ratio_x1000[GH2_PIPES_PER_DEV]; 148 } _soc_gh2_tdm_t; 149 150 #endif