td2_td2p.h (24330B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * File: td2_td2p.h 8 * Purpose: 9 * Requires: 10 */ 11 #ifndef _TD2_TD2P_H_ 12 #define _TD2_TD2P_H_ 13 14 #include <soc/types.h> 15 #include <soc/mmu_config.h> 16 #include <soc/esw/port.h> 17 #include <soc/portmod/portmod_defs.h> 18 19 /* TDM algorithm */ 20 #define _TD2P_NUM_PORT_MODULES 33 21 #define OVSB_TOKEN 250 22 #define IDL1_TOKEN 251 23 #define IDL2_TOKEN 252 24 #define NUM_EXT_PORTS 130 25 #define OS_GROUP_LEN 16 26 #define NUM_TSC 32 27 #define PGW_LR_UNUSED_SLOT 129 28 29 30 #define _TD2_OVS_TOKEN (NUM_EXT_PORTS+1) 31 #define _TD2_IDL_TOKEN (NUM_EXT_PORTS+2) 32 33 #define _TD2_PGW_TDM_LENGTH 32 34 #define _TD2_IARB_TDM_LENGTH 512 35 #define _TD2_TD2_CELLS_PER_OBM 1020 36 #define _MMU_OVS_GROUP_COUNT 4 37 #define _TD2_MMU_OVS_GROUP_COUNT _MMU_OVS_GROUP_COUNT 38 39 40 #ifdef BCM_TRIDENT2PLUS_SUPPORT 41 42 extern int get_mmu_mode (int unit); 43 extern int soc_td2p_if_full_chip (int unit); 44 45 #define _TD2P_PGW_TDM_LENGTH 64 46 #define MAX_PGW_TDM_LENGTH 64 47 48 #define _TD2P_TD2_CELLS_PER_OBM 2044 49 50 51 #define _TD2P_MMU_OVS_GROUP_COUNT 8 52 #define MAX_MMU_OVS_GROUP_COUNT 8 53 54 #define GET_PGW_TDM_LENGTH(unit)\ 55 ((SOC_IS_TD2P_TT2P(unit)) ? _TD2P_PGW_TDM_LENGTH : _TD2_PGW_TDM_LENGTH ) 56 57 #define GET_MMU_OVS_GCOUNT(unit)\ 58 ((SOC_IS_TD2P_TT2P(unit)) ? _TD2P_MMU_OVS_GROUP_COUNT : _TD2_MMU_OVS_GROUP_COUNT ) 59 60 #define GET_NUM_CELLS_PER_OBM(unit)\ 61 ((SOC_IS_TD2P_TT2P(unit)) ? _TD2P_TD2_CELLS_PER_OBM : _TD2_TD2_CELLS_PER_OBM ) 62 63 #define _TD2P_OVS_TOKEN OVSB_TOKEN 64 #define _TD2P_IDL_TOKEN IDL1_TOKEN 65 66 #define GET_OVS_TOKEN(unit)\ 67 ((SOC_IS_TD2P_TT2P(unit)) ? _TD2P_OVS_TOKEN : _TD2_OVS_TOKEN ) 68 #define GET_IDL_TOKEN(unit)\ 69 ((SOC_IS_TD2P_TT2P(unit)) ? _TD2P_IDL_TOKEN : _TD2_IDL_TOKEN ) 70 71 #else 72 73 #define GET_PGW_TDM_LENGTH(unit) _TD2_PGW_TDM_LENGTH 74 #define GET_MMU_OVS_GCOUNT(unit) _MMU_OVS_GROUP_COUNT 75 #define GET_NUM_CELLS_PER_OBM(unit) _TD2_TD2_CELLS_PER_OBM 76 77 #define MAX_PGW_TDM_LENGTH 32 78 #define MAX_MMU_OVS_GROUP_COUNT 4 79 80 #define GET_OVS_TOKEN(unit) _TD2_OVS_TOKEN 81 #define GET_IDL_TOKEN(unit) _TD2_IDL_TOKEN 82 83 #endif 84 85 #define _PGW_TDM_OVS_SIZE 32 86 87 #define _PGW_MASTER_COUNT 4 88 #define _PGW_TDM_SLOTS_PER_REG 4 89 #define _MMU_TDM_LENGTH 256 90 #define _MMU_OVS_GROUP_TDM_LENGTH 16 91 #define _IARB_TDM_LENGTH 512 92 #define _MMU_OVS_WT_GROUP_COUNT 4 93 94 #define PGW_OBM_INIT_HW_DEFAULT (0) 95 #define PGW_OBM_INIT_SW_DEFAULT (1) 96 97 #define SOC_TD2P_MAX_MMU_PORTS_PER_PIPE 52 98 99 #define _SOC_TD2_MAX_PORT (_TD2_LOG_PORTS_PER_PIPE * \ 100 _TD2_PIPES_PER_DEV) 101 102 #define _TD2_MMU_PACKET_HEADER_BYTES 64 /* bytes */ 103 #define _TD2_MMU_JUMBO_FRAME_BYTES 9216 /* bytes */ 104 #define _TD2_MMU_DEFAULT_MTU_BYTES 1536 /* bytes */ 105 106 #define _TD2_MMU_BYTES_PER_CELL 208 /* bytes (1664 bits) */ 107 #define _TD2_MMU_NUM_PG 8 108 #define _TD2_MMU_NUM_POOL 4 109 #define _TD2_MMU_NUM_RQE_QUEUES 11 110 #define _TD2P_MMU_RSVD_BUF_FLEX_PGMIN_LOSSLESS 8 111 112 #define SOC_TD2_MMU_CFG_QGROUP_MAX 128 113 114 /* quantization loss + TOQ reserved 115 * quantization loss = MC queue count * 6 116 * TOQ reserved = TOQ_MC_CFG0.MCQE_FULL_THRESHOLD * 4 117 */ 118 #define SOC_TD2_MMU_MCQ_RSVD_ENTRY ((52 * 10 * 2 + 48 + 10) * 6 + (164 * 4)) 119 #define SOC_TD2_MMU_RQE_TOTAL_RSVD_ENTRY (SOC_IS_TD2P_TT2P(unit) ? 76 : 88) 120 #define SOC_TD2_MMU_RQE_USER_RSVD_ENTRY (SOC_IS_TD2P_TT2P(unit) ? (11*8) : 0) 121 #define SOC_TD2_MMU_MCQ_ENTRY 49152 122 #define SOC_TD2_MMU_RQE_ENTRY 4096 123 124 #define _TD2P_MMU_GLOBAL_HEADROOM 50 /* per pipe */ 125 #define _TD2P_MMU_CPU_HEADROOM 50 /* per device */ 126 #define SOC_TD2_MMU_QGROUP_MIN_RSVD (SOC_IS_TD2P_TT2P(unit) ? 16 : 8) 127 #define SOC_TD2_MMU_Q_MIN_RSVD (SOC_IS_TD2P_TT2P(unit) ? 0 : 8) 128 129 #define _TD2_MMU_TOTAL_MCQ_ENTRY(unit) SOC_TD2_MMU_MCQ_ENTRY 130 131 #define _TD2P_MMU_NUM_MCQ_PORT_MACRO 10 132 #define _TD2P_MMU_PER_COSQ_EGRESS_QENTRY_RSVD 4 133 134 #define _TD2_MMU_TOTAL_RQE_ENTRY(unit) SOC_TD2_MMU_RQE_ENTRY 135 136 #define _TD2_MMU_PORT_CREDIT_100G (SOC_IS_TD2P_TT2P(unit) ? 96 : 144) 137 #define _TD2_MMU_PORT_CREDIT_40G 48 138 #define _TD2_MMU_PORT_CREDIT_20G 24 139 #define _TD2_MMU_PORT_CREDIT_10G 12 140 141 #define _TD2_MMU_PORT_CREDIT(speed) _TD2_MMU_PORT_CREDIT_##speed 142 143 #define _TD2_MMU_ASF_CREDIT_THRESH_LO_100G (SOC_IS_TD2P_TT2P(unit) ? 30 : 64) 144 #define _TD2_MMU_ASF_CREDIT_THRESH_HI_100G (SOC_IS_TD2P_TT2P(unit) ? 30 : 108) 145 #define _TD2_MMU_ASF_CREDIT_THRESH_LO_40G 18 146 #define _TD2_MMU_ASF_CREDIT_THRESH_HI_40G (SOC_IS_TD2P_TT2P(unit) ? 18 : 36) 147 #define _TD2_MMU_ASF_CREDIT_THRESH_LO_20G 8 148 #define _TD2_MMU_ASF_CREDIT_THRESH_HI_20G (SOC_IS_TD2P_TT2P(unit) ? 8 : 18) 149 #define _TD2_MMU_ASF_CREDIT_THRESH_LO_10G 4 150 #define _TD2_MMU_ASF_CREDIT_THRESH_HI_10G (SOC_IS_TD2P_TT2P(unit) ? 4 : 9) 151 152 #define _TD2_MMU_ASF_CREDIT_THRESH(param, speed) _TD2_MMU_ASF_CREDIT_THRESH_##param##_##speed 153 154 #define _TD2P_MMU_ASF_CREDIT_THRESH_OPTIMIZED_LO_100G 10 155 #define _TD2P_MMU_ASF_CREDIT_THRESH_OPTIMIZED_HI_100G 10 156 #define _TD2P_MMU_ASF_CREDIT_THRESH_OPTIMIZED_LO_40G 5 157 #define _TD2P_MMU_ASF_CREDIT_THRESH_OPTIMIZED_HI_40G 5 158 #define _TD2P_MMU_ASF_CREDIT_THRESH_OPTIMIZED_LO_20G 4 159 #define _TD2P_MMU_ASF_CREDIT_THRESH_OPTIMIZED_HI_20G 4 160 #define _TD2P_MMU_ASF_CREDIT_THRESH_OPTIMIZED_LO_10G 3 161 #define _TD2P_MMU_ASF_CREDIT_THRESH_OPTIMIZED_HI_10G 3 162 #define _TD2P_MMU_ASF_CREDIT_THRESH_OPTIMIZED_OVERSUB_LO_40G 8 163 #define _TD2P_MMU_ASF_CREDIT_THRESH_OPTIMIZED_OVERSUB_HI_40G 8 164 165 #define _TD2P_MMU_ASF_CREDIT_THRESH_OPTIMIZED(param, speed) \ 166 _TD2P_MMU_ASF_CREDIT_THRESH_OPTIMIZED_##param##_##speed 167 #define _TD2P_MMU_ASF_CREDIT_THRESH_OPTIMIZED_OVERSUB(param, speed) \ 168 _TD2P_MMU_ASF_CREDIT_THRESH_OPTIMIZED_OVERSUB_##param##_##speed 169 170 /* The actual limits are 43, 22, 15, and 11, but EGR_MMU_CREDIT_REQUEST uses 171 <= for credit comparison, so we set the credit limit to 1 less 172 than the expected value.*/ 173 #define _TD2P_MMU_EGR_MMU_CREDIT_LIMIT_LINERATE_100G 42 /* 43 */ 174 #define _TD2P_MMU_EGR_MMU_CREDIT_LIMIT_LINERATE_40G 21 /* 22 */ 175 #define _TD2P_MMU_EGR_MMU_CREDIT_LIMIT_LINERATE_20G 14 /* 15 */ 176 #define _TD2P_MMU_EGR_MMU_CREDIT_LIMIT_LINERATE_10G 10 /* 11 */ 177 178 #define _TD2P_MMU_EGR_MMU_CREDIT_LIMIT_LINERATE(speed) \ 179 _TD2P_MMU_EGR_MMU_CREDIT_LIMIT_LINERATE_##speed 180 181 /* The actual limits are 23, 11, and 8, but EGR_MMU_CREDIT_REQUEST uses 182 <= for credit comparison, so we set the credit limit to 1 less 183 than the expected value.*/ 184 #define _TD2P_MMU_EGR_MMU_CREDIT_LIMIT_OVERSUB_40G 22 /* 23 */ 185 #define _TD2P_MMU_EGR_MMU_CREDIT_LIMIT_OVERSUB_20G 10 /* 11 */ 186 #define _TD2P_MMU_EGR_MMU_CREDIT_LIMIT_OVERSUB_10G 7 /* 8 */ 187 188 #define _TD2P_MMU_EGR_MMU_CREDIT_LIMIT_OVERSUB(speed) \ 189 _TD2P_MMU_EGR_MMU_CREDIT_LIMIT_OVERSUB_##speed 190 191 #define _TD2P_EGR_PFC_WATERMARK_THRESH_LINERATE_100G 61 192 #define _TD2P_EGR_PFC_WATERMARK_THRESH_LINERATE_40G 31 193 #define _TD2P_EGR_PFC_WATERMARK_THRESH_LINERATE_20G 19 194 #define _TD2P_EGR_PFC_WATERMARK_THRESH_LINERATE_10G 13 195 196 #define _TD2P_EGR_PFC_WATERMARK_THRESH_LINERATE(speed) \ 197 _TD2P_EGR_PFC_WATERMARK_THRESH_LINERATE_##speed 198 199 #define _TD2P_EGR_PFC_WATERMARK_THRESH_OVERSUB_40G 42 200 #define _TD2P_EGR_PFC_WATERMARK_THRESH_OVERSUB_20G 19 201 #define _TD2P_EGR_PFC_WATERMARK_THRESH_OVERSUB_10G 13 202 203 #define _TD2P_EGR_PFC_WATERMARK_THRESH_OVERSUB(speed) \ 204 _TD2P_EGR_PFC_WATERMARK_THRESH_OVERSUB_##speed 205 206 #define _TD2_MMU_ASF_FIFO_THRESHOLD 3 207 #define _TD2_MMU_ASF_HS_FIFO_THRESHOLD 13 208 209 #define _TD2_TD2_MMU_XMIT_START_CNT_OVERSUB (si->frequency >= 608 ? 9 :\ 210 (si->frequency >= 500 ? 11 : 12)) 211 212 #define _TD2P_TD2_MMU_XMIT_START_CNT_OVERSUB ((si->frequency >= 760 ? 11 :\ 213 (si->frequency >= 608 ? 12 : \ 214 (si->frequency >= 500 ? 14 : 15)))) 215 216 #define XMIT_START_CNT_OVERSUB(param)\ 217 ((SOC_IS_TD2P_TT2P(unit))? _TD2P##param : _TD2##param) 218 219 #define _TD2_MMU_XMIT_START_CNT_OVERSUB XMIT_START_CNT_OVERSUB(_TD2_MMU_XMIT_START_CNT_OVERSUB) 220 221 222 #define _TD2_TD2_MMU_XMIT_START_CNT_LINERATE(speed) \ 223 (speed > 42000 ? 3 : ((si->frequency <= 415) && (speed > 11000) ? 8 : 7)) 224 225 #define _TD2P_TD2_MMU_XMIT_START_CNT_LINERATE(speed) \ 226 (speed > 42000 ? 10 : ((si->frequency <= 415) && (speed > 21000) ? 8 : 7)) 227 228 #define XMIT_START_CNT_LINERATE(param,speed)\ 229 ((SOC_IS_TD2P_TT2P(unit))? _TD2P##param(speed) : _TD2##param(speed)) 230 231 #define _TD2_MMU_XMIT_START_CNT_LINERATE(speed) XMIT_START_CNT_LINERATE(_TD2_MMU_XMIT_START_CNT_LINERATE, speed) 232 233 #define _TD2_PGW_CELL_ASM_CUT_THRU_THRESHOLD (SOC_IS_TD2P_TT2P(unit) ? 4 : 6) 234 235 /* 236 * Define: 237 * TD2P_PHY_PORT_ADDRESSABLE 238 * Purpose: 239 * Checks that physical port is addressable (within valid range). 240 */ 241 #define TD2P_PHY_PORT_ADDRESSABLE(_u, _phy_port) \ 242 (soc_td2p_phy_port_addressable((_u), (_phy_port)) == SOC_E_NONE) 243 244 245 #define _SOC_TD2P_DEFIP_REDUCED_TCAMS 2 246 #define _SOC_TD2_DEFIP_MAX_TCAMS 8 247 #define _SOC_TD2_DEFIP_TCAM_DEPTH 1024 248 249 #define _SOC_TD2_MAX_INTERNAL_PRIORITY 15 250 #define _SOC_TD2_MAX_PRIORITY 7 251 252 #define PORT_STATE_UNUSED 0 253 #define PORT_STATE_LINERATE 1 254 #define PORT_STATE_OVERSUB 2 255 #define PORT_STATE_SUBPORT 3 /* part of other port */ 256 257 typedef struct _soc_trident2_tdm_s { 258 int speed[NUM_EXT_PORTS]; 259 int tdm_bw; 260 int port_state[NUM_EXT_PORTS]; /* 0-unused, 1-line rate, 2-oversub, 261 * 3-part of other port */ 262 int pipe_ovs_state[2]; 263 int manage_port_type; /* 0-none, 1-4x1g, 2-4x2.5g, 3-1x10g */ 264 265 int pgw_tdm[_PGW_MASTER_COUNT][MAX_PGW_TDM_LENGTH]; 266 int pgw_ovs_tdm[_PGW_MASTER_COUNT][_PGW_TDM_OVS_SIZE]; 267 int pgw_ovs_spacing[_PGW_MASTER_COUNT][_PGW_TDM_OVS_SIZE]; 268 int mmu_tdm[2][_MMU_TDM_LENGTH + 1]; 269 int mmu_ovs_group_tdm[2][MAX_MMU_OVS_GROUP_COUNT][_MMU_OVS_GROUP_TDM_LENGTH]; 270 int iarb_tdm_wrap_ptr[2]; 271 int iarb_tdm[2][_IARB_TDM_LENGTH]; 272 #ifdef BCM_TRIDENT2PLUS_SUPPORT 273 int encap_type[_TD2P_NUM_PORT_MODULES]; 274 #endif 275 int ancillary_bandwidth_mode;/* 0-none, 1-CPU, 2-LOOPBACK, 3-CPU_and_LOOPBACK */ 276 } _soc_trident2_tdm_t; 277 278 typedef soc_reg_t(*mmu_ovs_group_wt_regs_t)[_MMU_OVS_WT_GROUP_COUNT]; 279 280 281 #ifdef BCM_TRIDENT2PLUS_SUPPORT 282 283 #define TD2P_SUBPORT_COE_GROUP_MAX (512) 284 #define TD2P_SUBPORT_COE_PORT_MAX (512) 285 #define TD2P_MAX_SUBPORT_COE_PORT_PER_CASPORT (80) 286 #define TD2P_MAX_SUBPORT_COE_PORT_PER_MOD (128) 287 #define TD2P_MAX_COE_MODULES (5) 288 289 290 #define TD2P_X_PIPE 0 291 #define TD2P_Y_PIPE 1 292 293 #define TD2P_PIPES_PER_DEV 2 294 #define TD2P_PGWS_PER_QUAD 2 295 #define TD2P_QUADS_PER_PIPE 2 296 297 #define TD2P_PGWS_PER_PIPE (TD2P_PGWS_PER_QUAD * TD2P_QUADS_PER_PIPE) 298 #define TD2P_PGWS_PER_DEV (TD2P_PGWS_PER_PIPE * TD2P_PIPES_PER_DEV) 299 300 #define TD2P_XLPS_PER_PGW 4 301 #define TD2P_PORTS_PER_XLP 4 302 303 #define TD2P_PHY_PORTS_PER_PIPE 65 304 305 #define TD2P_PHY_PORT_CPU 0 /* CPU physical port */ 306 #define TD2P_PHY_PORT_LB 129 /* Loopback physical port */ 307 308 #define SOC_TD2P_PORT_CT_SPEED_NONE 0x0 309 #define SOC_TD2P_PORT_CT_SPEED_10M_FULL 0x1 310 #define SOC_TD2P_PORT_CT_SPEED_100M_FULL 0x2 311 #define SOC_TD2P_PORT_CT_SPEED_1000M_FULL 0x3 312 #define SOC_TD2P_PORT_CT_SPEED_2500M_FULL 0x4 313 #define SOC_TD2P_PORT_CT_SPEED_10000M_FULL 0x5 314 #define SOC_TD2P_PORT_CT_SPEED_11000M_FULL 0x6 315 #define SOC_TD2P_PORT_CT_SPEED_12000M_FULL 0x7 316 #define SOC_TD2P_PORT_CT_SPEED_13000M_FULL 0x8 317 #define SOC_TD2P_PORT_CT_SPEED_15000M_FULL 0x9 318 #define SOC_TD2P_PORT_CT_SPEED_16000M_FULL 0xa 319 #define SOC_TD2P_PORT_CT_SPEED_20000M_FULL 0xb 320 #define SOC_TD2P_PORT_CT_SPEED_21000M_FULL 0xc 321 #define SOC_TD2P_PORT_CT_SPEED_25000M_FULL 0xd 322 #define SOC_TD2P_PORT_CT_SPEED_30000M_FULL 0xe 323 #define SOC_TD2P_PORT_CT_SPEED_40000M_FULL 0xf 324 #define SOC_TD2P_PORT_CT_SPEED_42000M_FULL 0x10 325 #define SOC_TD2P_PORT_CT_SPEED_100000M_FULL 0x11 326 #define SOC_TD2P_PORT_CT_SPEED_106000M_FULL 0x12 327 #define SOC_TD2P_PORT_CT_SPEED_120000M_FULL 0x13 328 #define SOC_TD2P_PORT_CT_SPEED_127000M_FULL 0x14 329 330 enum td2plus_evlxlt_hash_key_type_e { 331 /* WARNING: values given match hardware register; do not modify */ 332 TD2PLUS_EVLXLT_HASH_KEY_TYPE_VLAN_XLATE = 0, 333 TD2PLUS_EVLXLT_HASH_KEY_TYPE_VLAN_XLATE_DVP = 1, 334 TD2PLUS_EVLXLT_HASH_KEY_TYPE_FCOE_XLATE = 2, 335 TD2PLUS_EVLXLT_HASH_KEY_TYPE_ISID_XLATE = 3, 336 TD2PLUS_EVLXLT_HASH_KEY_TYPE_ISID_DVP_XLATE = 4, 337 TD2PLUS_EVLXLT_HASH_KEY_TYPE_L2GRE_VFI = 5, 338 TD2PLUS_EVLXLT_HASH_KEY_TYPE_L2GRE_VFI_DVP = 6, 339 TD2PLUS_EVLXLT_HASH_KEY_TYPE_FCOE_XLATE_DVP = 7, 340 TD2PLUS_EVLXLT_HASH_KEY_TYPE_VXLAN_VFI = 8, 341 TD2PLUS_EVLXLT_HASH_KEY_TYPE_VXLAN_VFI_DVP = 9, 342 TD2PLUS_EVLXLT_HASH_KEY_TYPE_VFI_DVP_GROUP = 10, 343 TD2PLUS_EVLXLT_HASH_KEY_TYPE_VRF_MAPPING = 11, 344 TD2PLUS_EVLXLT_HASH_KEY_TYPE_VLAN_XLATE_VFI =12, 345 TD2PLUS_EVLXLT_HASH_KEY_TYPE_COUNT 346 }; 347 348 enum td2plus_dvp_evlxlt_hash_key_type_e { 349 /* WARNING: values given match hardware register; do not modify */ 350 TD2PLUS_DVP_EVLXLT_HASH_KEY_TYPE_NOOP = 0, 351 TD2PLUS_DVP_EVLXLT_HASH_KEY_TYPE_VFI = 1, 352 TD2PLUS_DVP_EVLXLT_HASH_KEY_TYPE_DVP_VFI = 2, 353 TD2PLUS_DVP_EVLXLT_HASH_KEY_TYPE_GID_VFI = 3, 354 TD2PLUS_DVP_EVLXLT_HASH_KEY_TYPE_DVP_OL_VLAN = 4, 355 TD2PLUS_DVP_EVLXLT_HASH_KEY_TYPE_PORT_UL_VLAN = 5, 356 TD2PLUS_DVP_EVLXLT_HASH_KEY_TYPE_COUNT 357 }; 358 359 /* 360 * Data structure use for storing part of the SOC data information 361 * which is needed during later phases of a FlexPort operation. 362 */ 363 typedef struct soc_td2p_info_s { 364 int port_l2p_mapping[SOC_MAX_NUM_PORTS]; /* Logic to physical */ 365 int port_p2l_mapping[SOC_MAX_NUM_PORTS]; /* Physical to logic */ 366 int port_p2m_mapping[SOC_MAX_NUM_PORTS]; /* Physical to MMU */ 367 int port_m2p_mapping[SOC_MAX_NUM_MMU_PORTS]; /* MMU to physical */ 368 int port_group[SOC_MAX_NUM_PORTS]; /* Group number */ 369 int port_speed_max[SOC_MAX_NUM_PORTS]; /* Max port speed */ 370 int port_num_lanes[SOC_MAX_NUM_PORTS]; /* Number of lanes */ 371 pbmp_t xpipe_pbm; /* Ports in X-pipe */ 372 pbmp_t ypipe_pbm; /* Ports in Y-pipe */ 373 pbmp_t oversub_pbm; /* Oversubscription ports */ 374 } soc_td2p_info_t; 375 376 extern _soc_trident2_tdm_t * 377 soc_td2_td2p_tdm_sched_info_get(int unit, int create); 378 379 extern mmu_ovs_group_wt_regs_t 380 get_mmu_ovs_group_wt_regs(int unit, mmu_ovs_group_wt_regs_t old); 381 382 extern int 383 soc_td2p_set_obm_registers(int unit, soc_reg_t reg, int speed, 384 int index, int obm_inst, int lossless, int 385 default_flag ); 386 extern int 387 soc_td2p_obm_prob_drop_default_set(int unit, int xlp, int index, 388 int obm_inst, int default_flag); 389 extern 390 int soc_td2p_obm_cut_through_threshold_set (int unit, int xlp, int index, 391 int obm_inst, int default_flag); 392 extern int 393 soc_td2p_mmu_delay_insertion_set(int unit, int port, int speed); 394 395 extern int 396 soc_td2p_mem_config(int unit, uint16 dev_id, uint8 rev_id); 397 398 extern int 399 soc_td2p_get_shared_bank_size(int unit, uint16 dev_id, uint8 rev_id); 400 401 extern uint32* 402 soc_td2p_mmu_params_arr_get(uint16 dev_id, uint8 rev_id); 403 404 extern int 405 tdm_td2p_set_iarb_tdm_table(int core_bw, int is_x_ovs, int is_y_ovs, 406 int mgm4x1, int mgm4x2p5, int mgm1x10, 407 int *iarb_tdm_wrap_ptr_x, int *iarb_tdm_wrap_ptr_y, 408 int *iarb_tdm_tbl_x, int *iarb_tdm_tbl_y); 409 410 extern int 411 soc_td2p_show_voltage(int unit); 412 413 extern int 414 soc_td2p_idb_buf_reset(int unit, soc_port_t port, int reset); 415 416 extern int 417 soc_td2p_set_mmu_credit_limit(int unit, soc_port_t port); 418 419 extern int 420 soc_td2p_use_pfc_optimized_settings(int unit); 421 422 extern int 423 soc_td2p_set_edb_pfc_watermark_threshold(int unit, soc_port_t port); 424 425 extern int 426 soc_td2p_edb_buf_reset(int unit, soc_port_t port, int reset); 427 428 extern int 429 soc_td2p_is_cut_thru_enabled(int unit, soc_port_t port, int *enable); 430 431 extern int 432 soc_td2p_egr_edb_xmit_ctrl_set(int unit, int phy_port, int speed, 433 int oversub, int cut_thru_enable); 434 435 extern int 436 soc_td2p_phy_info_init(int unit); 437 438 extern int 439 soc_td2p_port_mixed_sister_speed_validate(int unit); 440 441 extern int 442 soc_td2p_port_oversub_get(int unit, int phy_port, soc_port_t logical_port, 443 int *oversub); 444 445 extern int 446 soc_td2p_port_lanes_valid(int unit, soc_port_t port, int lanes); 447 448 extern int 449 soc_td2p_port_resource_speed_max_get(int unit, int *speed); 450 451 extern int 452 soc_td2p_port_resource_speed_max_x_get(int unit, int *speed); 453 454 extern int 455 soc_td2p_port_resource_speed_max_y_get(int unit, int *speed); 456 457 extern int 458 soc_td2p_port_addressable(int unit, soc_port_t port); 459 460 extern int 461 soc_td2p_phy_port_addressable(int unit, int phy_port); 462 463 extern int 464 soc_td2p_phy_port_pgw_info_get(int unit, int phy_port, 465 int *pgw, int *xlp, int *port_index); 466 467 extern int 468 soc_td2p_port_macro_first_phy_port_get(int unit, int phy_port, 469 int *first_phy_port); 470 471 extern int 472 soc_td2p_subsidiary_ports_get(int unit, soc_port_t port, soc_pbmp_t *pbmp); 473 474 extern int 475 soc_td2p_port_resource_validate(int unit, int nport, 476 soc_port_resource_t *resource); 477 478 extern int 479 soc_td2p_port_resource_configure(int unit, int nport, 480 soc_port_resource_t *resource, int flag); 481 482 extern int 483 soc_td2p_pgw_obm_set(int unit, 484 int pre_num_res, soc_port_resource_t *pre_res, 485 int post_num_res, soc_port_resource_t *post_res); 486 487 extern int 488 soc_td2p_port_resource_tdm_set(int unit, int curr_port_info_size, 489 soc_port_resource_t *curr_port_info, 490 int new_port_info_size, 491 soc_port_resource_t *new_port_info, 492 soc_td2p_info_t *si, 493 int lossless); 494 495 extern int 496 soc_td2p_port_resource_pgw_set(int unit, 497 int pre_num_res, soc_port_resource_t *pre_res, 498 int post_num_res, soc_port_resource_t *post_res, 499 int lossless); 500 501 extern int 502 soc_td2p_port_resource_ip_set(int unit, int curr_port_info_size, 503 soc_port_resource_t *curr_port_info, 504 int new_port_info_size, 505 soc_port_resource_t *new_port_info, 506 soc_td2p_info_t *si); 507 508 extern int 509 soc_td2p_port_resource_ep_set(int unit, int curr_port_info_size, 510 soc_port_resource_t *curr_port_info, 511 int new_port_info_size, 512 soc_port_resource_t *new_port_info, 513 soc_td2p_info_t *si); 514 515 extern int 516 soc_td2p_port_resource_mmu_mapping_set(int unit, int nport, 517 soc_port_resource_t *resource); 518 519 extern int 520 soc_td2p_port_resource_mmu_set(int unit, int nport, 521 soc_port_resource_t * flexport_data); 522 extern int 523 soc_td2p_port_lane_config_get(int unit, int phy_port, int *mode_lane, 524 int *found); 525 526 extern int 527 soc_td2p_port_autoneg_core_get(int unit, int phy_port, int *an_core, 528 int *found); 529 530 extern int 531 soc_td2p_mmu_rqe_phy_port_mapping_set(int unit, 532 int pre_num_res, soc_port_resource_t *pre_res); 533 534 extern int 535 soc_td2p_lls_reinit_invalid_pointers(int unit); 536 extern int 537 soc_td2p_lls_reset_flex(int unit); 538 539 extern int 540 soc_td2p_mmu_additional_buffer_reserve (int unit, int pipe, int flex, 541 _soc_mmu_rsvd_buffer_t *rsvd_buffer); 542 extern int 543 soc_td2p_port_asf_set (int unit, soc_port_t port, int enable); 544 extern int 545 soc_td2_port_asf_speed_set(int unit, soc_port_t port, int speed); 546 547 extern int 548 _soc_td2_default_lossless_pg_headroom(int unit, soc_port_t port); 549 extern int 550 _soc_td2_min_cell_rsvd_per_mcq(int unit, int port, int default_val); 551 extern void 552 _soc_td2_mmu_init_dev_config(int unit, _soc_mmu_device_info_t *devcfg, 553 int lossless); 554 extern void 555 _soc_td2_mmu_config_buf_default(int unit, _soc_mmu_cfg_buf_t *buf, 556 _soc_mmu_device_info_t *devcfg, int lossless); 557 extern void 558 _soc_td2_mmu_config_buf_default_global(int unit, _soc_mmu_cfg_buf_t *buf, 559 _soc_mmu_device_info_t *devcfg, int lossless); 560 extern void 561 _soc_td2_mmu_config_buf_default_port(int unit, int in_port, _soc_mmu_cfg_buf_t *buf, 562 _soc_mmu_device_info_t *devcfg, int lossless); 563 extern int 564 _soc_td2_mmu_config_buf_set_hw_port(int unit, int port, _soc_mmu_cfg_buf_t *buf, 565 _soc_mmu_device_info_t *devcfg, int lossless); 566 extern int 567 soc_td2p_mcq_entries_rsvd_port(int unit, int port); 568 extern int 569 soc_td2p_egr_buf_rsvd_port(int unit, int port, int default_mtu_cells); 570 571 572 /* 573 * FlexPort Functions 574 */ 575 576 extern int 577 soc_td2p_logic_ports_max_validate(int unit, portmod_pbmp_t phy_pbmp); 578 579 extern int 580 soc_td2p_num_hsp_reserved_per_pipe(int unit, int pipe, int *num_hsp); 581 582 extern void 583 soc_td2p_num_hsp_reserved_reset(int unit); 584 585 586 extern int 587 soc_td2p_port_macro_flex_enabled(int unit, int port_macro, int *flex_enabled); 588 589 extern int 590 soc_td2p_mmu_port_resource_set(int unit, soc_port_t port, int speed, int legacyFlex); 591 extern int 592 soc_td2p_mmu_port_resource_clear(int unit, soc_port_t port); 593 594 /* interfaces to reconfigure mmu data structures */ 595 extern int soc_td2p_mmu_flexport_map_validate(int unit, int nport, 596 soc_port_resource_t * flex_port_data); 597 extern int soc_td2p_mmu_flexport_map_set(int unit, int nport, 598 soc_port_resource_t * flexport_data); 599 600 /* called by interfaces to reconfigure mmu data structures */ 601 extern int soc_td2p_mmu_flexport_allocate_deallocate_ports(int unit, 602 int nport, soc_port_resource_t * flexport_data); 603 604 extern int soc_td2p_is_any_port_flex_enable(int unit); 605 extern int soc_td2p_is_port_flex_enable(int unit, int phy_port); 606 extern int soc_td2p_port_mode_get(int unit, int port, int *mode); 607 608 #ifdef PORTMOD_SUPPORT 609 extern int soc_td2p_portctrl_pm_portmod_init(int unit); 610 extern int soc_td2p_portctrl_pm_portmod_deinit(int unit); 611 extern int soc_td2p_portctrl_pm_port_config_get(int unit, soc_port_t port, void *port_config_info); 612 extern int soc_td2p_portctrl_pm_port_phyaddr_get(int unit, soc_port_t port); 613 extern int soc_td2p_portctrl_pm_type_get(int unit, soc_port_t phy_port, int* pm_type); 614 #endif 615 616 typedef int (*_soc_td2p_flexport_port_q_cb)(int unit, int nports, int * ports); 617 typedef int (*_soc_td2p_ets_mode_q_cb)(int unit, int port); 618 extern int soc_td2p_set_flexport_port_q_callback(int unit, 619 _soc_td2p_flexport_port_q_cb cb); 620 extern int soc_td2p_set_ets_mode_q_callback(int unit, 621 _soc_td2p_ets_mode_q_cb cb); 622 623 extern int soc_td2p_port_speed_set(int unit, soc_port_t port, int speed); 624 extern int soc_td2p_port_speed_get(int unit, soc_port_t port, int *speed); 625 626 extern int soc_td2p_port_sched_hsp_set(int unit, soc_port_t port, int sched_hsp); 627 extern int soc_td2p_port_sched_hsp_get(int unit, soc_port_t port, int *sched_hsp); 628 629 #ifdef BCM_WARM_BOOT_SUPPORT 630 extern int soc_td2p_flexport_scache_allocate(int unit); 631 extern int soc_td2p_flexport_scache_sync(int unit); 632 extern int soc_td2p_flexport_scache_recovery(int unit); 633 #endif /* BCM_WARM_BOOT_SUPPORT */ 634 #ifndef BCM_SW_STATE_DUMP_DISABLE 635 extern void soc_flexport_sw_dump(int unit); 636 #endif /* BCM_SW_STATE_DUMP_DISABLE */ 637 638 extern int soc_td2p_is_flex_enable(int unit); 639 640 #endif /* BCM_TRIDENT2PLUS_SUPPORT */ 641 642 #endif /* _td2_td2p_h */