shmoo_sjc16.h (10353B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * 16nm PHY Support 8 */ 9 10 #ifndef _SHMOO_SJC16_H 11 #define _SHMOO_SJC16_H 12 13 #include <sal/types.h> 14 #include <soc/defs.h> 15 #include <shared/types.h> 16 17 #define SHMOO_SJC16_CTL_TYPE_RSVP 0 18 #define SHMOO_SJC16_CTL_TYPE_RSVP_STR "t0" 19 #define SHMOO_SJC16_CTL_TYPE_1 1 20 #define SHMOO_SJC16_CTL_TYPE_1_STR "t1" 21 22 #define SHMOO_SJC16_DRAM_TYPE_RSVP 0 23 #define SHMOO_SJC16_DRAM_TYPE_DDR4 4 24 25 #define SHMOO_SJC16_PHY_REG_BASE_RSVP 0 26 #define SHMOO_SJC16_PHY_REG_BASE_HELIX5 0x00000000 27 28 #define SHMOO_SJC16_YDC_DDR_BIST_BIST_REG_BASE_RSVP 0 29 #define SHMOO_SJC16_YDC_DDR_BIST_BIST_REG_BASE_HELIX5 0x1023BC00 30 31 #define SHMOO_SJC16_CHIP_ID_RSVP 0 32 #define SHMOO_SJC16_CHIP_ID_HELIX5 0x85 33 34 #define CONFIG_HELIX5 1 35 36 #ifndef BCM_SJC16_SUPPORT 37 #define BCM_SJC16_SUPPORT 38 #endif 39 40 #if defined(CONFIG_HELIX5) 41 #define SOC_DDR4_SUPPORT 42 #define CHIP_IS_HELIX5 TRUE 43 #else 44 #define CHIP_IS_HELIX5 FALSE 45 #endif 46 47 #if(CHIP_IS_HELIX5) 48 #define SHMOO_SJC16_CHIP_ID SHMOO_SJC16_CHIP_ID_HELIX5 49 #define SHMOO_SJC16_PHY_REG_BASE SHMOO_SJC16_PHY_REG_BASE_HELIX5 50 #define SHMOO_SJC16_YDC_DDR_BIST_BIST_REG_BASE SHMOO_SJC16_YDC_DDR_BIST_BIST_REG_BASE_HELIX5 51 #define SHMOO_SJC16_PHY_BITWIDTH 32 52 #define SHMOO_SJC16_PHY_CONSTANT_CONFIG 0 53 #endif 54 55 #define SHMOO_SJC16_PHY_BITWIDTH_IS_32 (SHMOO_SJC16_PHY_BITWIDTH >> 5) 56 #define YDC_DDR_BIST_BIST_PHY_BITWIDTH_IS_32 SHMOO_SJC16_PHY_BITWIDTH_IS_32 57 #define YDC_DDR_BIST_BIST_REG_BASE SHMOO_SJC16_YDC_DDR_BIST_BIST_REG_BASE 58 59 #define SHMOO_SJC16_BIT 1 60 #define SHMOO_SJC16_BYTE (SHMOO_SJC16_BIT << 3) 61 #define SHMOO_SJC16_HALFWORD (SHMOO_SJC16_BYTE << 1) 62 #define SHMOO_SJC16_WORD (SHMOO_SJC16_HALFWORD << 1) 63 #define SHMOO_SJC16_DOUBLEWORD (SHMOO_SJC16_WORD << 1) 64 #define SHMOO_SJC16_QUADWORD (SHMOO_SJC16_DOUBLEWORD << 1) 65 66 #define SHMOO_SJC16_SHORT_SLEEP 10 67 #define SHMOO_SJC16_LONG_SLEEP 50 68 #define SHMOO_SJC16_DEEP_SLEEP 100 69 #define SHMOO_SJC16_HIBERNATION 1000 70 #define SHMOO_SJC16_STASIS 1000000 71 72 #define SHMOO_SJC16_SHMOO_RSVP -1 73 #define SHMOO_SJC16_RD_EN_FISH 24 74 #define SHMOO_SJC16_RD_EXTENDED 50 75 #define SHMOO_SJC16_WR_EXTENDED 60 76 #define SHMOO_SJC16_ADDR_CTRL_EXTENDED 70 77 #define SHMOO_SJC16_ADDR_EXTENDED 71 78 #define SHMOO_SJC16_CTRL_EXTENDED 72 79 #define SHMOO_SJC16_RD_EN_FISH_ECC 29 80 #define SHMOO_SJC16_RD_EXTENDED_ECC 59 81 #define SHMOO_SJC16_WR_EXTENDED_ECC 69 82 #define SHMOO_SJC16_DDR4_SEQUENCE_COUNT 4 83 #define SHMOO_SJC16_DDR4_ECC_32P4_SEQUENCE_COUNT 7 84 /* BEGIN: EXTRA */ 85 /* END: EXTRA */ 86 87 #define SHMOO_SJC16_QUICK_SHMOO_CTRL_EXTENDED 1 88 89 #define SHMOO_SJC16_REPEAT 9 90 #define SHMOO_SJC16_REPEAT_HALF (SHMOO_SJC16_REPEAT >> 1) 91 92 #define SHMOO_SJC16_SEQUENTIAL 0 93 #define SHMOO_SJC16_SINGLE 1 94 95 #define SHMOO_SJC16_ACTION_RSVP -1 96 #define SHMOO_SJC16_ACTION_RESTORE 0 97 #define SHMOO_SJC16_ACTION_RUN 1 98 #define SHMOO_SJC16_ACTION_SAVE 2 99 #define SHMOO_SJC16_ACTION_RUN_AND_SAVE 3 100 101 #define SHMOO_SJC16_CTL_FLAGS_STAT_BIT 0x1 102 #define SHMOO_SJC16_CTL_FLAGS_PLOT_BIT 0x2 103 #define SHMOO_SJC16_CTL_FLAGS_EXT_VREF_RANGE_BIT 0x4 104 #define SHMOO_SJC16_DEBUG_MODE_FLAG_BITS SHMOO_SJC16_CTL_FLAGS_EXT_VREF_RANGE_BIT 105 106 #define SHMOO_SJC16_MAX_INTERFACES 8 107 #define SHMOO_SJC16_INTERFACE_RSVP -1 108 #ifdef CONFIG_HELIX5 109 #define SHMOO_SJC16_BYTES_PER_INTERFACE 5 110 #else 111 #define SHMOO_SJC16_BYTES_PER_INTERFACE 4 112 #endif 113 114 #define SHMOO_SJC16_BIST_NOF_PATTERNS 8 115 #define SHMOO_SJC16_BIST_MPR_NOF_PATTERNS 4 116 117 /* Initial UI Shifts */ 118 #define SHMOO_SJC16_DDR4_INIT_CK_UI_SHIFT 2 119 #define SHMOO_SJC16_DDR4_INIT_ADDR_CTRL_UI_SHIFT 1 120 #define SHMOO_SJC16_DDR4_INIT_DQS_UI_SHIFT 2 121 #define SHMOO_SJC16_DDR4_INIT_DATA_UI_SHIFT 1 122 #define SHMOO_SJC16_GDDR5_INIT_CK_UI_SHIFT 1 123 #define SHMOO_SJC16_GDDR5_INIT_ADDR_CTRL_UI_SHIFT 3 124 #define SHMOO_SJC16_GDDR5_INIT_DQS_UI_SHIFT 1 125 #define SHMOO_SJC16_GDDR5_INIT_DATA_UI_SHIFT 0 126 127 /* Initial VDL Positions */ 128 #define SHMOO_SJC16_DDR4_INIT_WRITE_MIN_VDL_POS 0 129 #define SHMOO_SJC16_DDR4_INIT_READ_MIN_VDL_POS 30 130 131 /* Initial Configurations */ 132 #define SHMOO_SJC16_DDR4_INIT_REN_RD2_2G_DELAY 4 133 #define SHMOO_SJC16_DDR4_INIT_EDCEN_RD2_2G_DELAY 4 134 #define SHMOO_SJC16_GDDR5_INIT_REN_RD2_2G_DELAY 4 135 #define SHMOO_SJC16_GDDR5_INIT_EDCEN_RD2_2G_DELAY 9 136 137 #define SHMOO_SJC16_MAX_VISIBLE_UI_COUNT 9 138 #define SHMOO_SJC16_MAX_EFFECTIVE_UI_COUNT 8 139 #define SHMOO_SJC16_LAST_EFFECTIVE_UI (SHMOO_SJC16_MAX_EFFECTIVE_UI_COUNT - 1) 140 #define SHMOO_SJC16_MAX_VDL_LENGTH 512 141 #define SHMOO_SJC16_MAX_VREF_RANGE 32 142 #define SHMOO_SJC16_DDR4_VREF_RANGE_CROSSOVER 36 /* Must be between 23 - 50 */ 143 #define SHMOO_SJC16_MAX_ZQ_CAL_RANGE 32 144 145 #define SHMOO_SJC16_RESULT2D_X SHMOO_SJC16_MAX_VDL_LENGTH 146 #define SHMOO_SJC16_RESULT2D_Y SHMOO_SJC16_MAX_VREF_RANGE 147 148 #define SHMOO_SJC16_STRING_LENGTH ((SHMOO_SJC16_RESULT2D_X << 1) + 1) 149 #define SHMOO_SJC16_ERROR_ARRAY_LENGTH 4 150 151 #define SHMOO_SJC16_CALIB_CENTER_PASS 111 152 #define SHMOO_SJC16_CALIB_RISING_EDGE 011 153 #define SHMOO_SJC16_CALIB_FALLING_EDGE 100 154 #define SHMOO_SJC16_CALIB_PASS_START 001 155 #define SHMOO_SJC16_CALIB_FAIL_START 110 156 #define SHMOO_SJC16_CALIB_VDL_ZERO 000 157 #define SHMOO_SJC16_CALIB_XY_AVERAGE 010 158 159 #define SHMOO_SJC16_PHY_NOF_AD 16 160 #define SHMOO_SJC16_PHY_NOF_BA 3 161 #define SHMOO_SJC16_PHY_NOF_AUX 3 162 #define SHMOO_SJC16_PHY_NOF_CS 2 163 164 /* Config params */ 165 #define SHMOO_SJC16_DQ_CONFIG_NOF_BYTE SHMOO_SJC16_BYTES_PER_INTERFACE 166 167 typedef struct sjc16_shmoo_dram_info_s 168 { 169 uint32 ctl_type; 170 uint32 dram_type; 171 uint32 dram_bitmap; 172 uint32 interface_bitwidth; 173 uint32 ecc_32p4; 174 int num_columns; 175 int num_rows; 176 int num_banks; 177 int num_bank_groups; 178 int data_rate_mbps; 179 int ref_clk_mhz; 180 uint32 refi; 181 uint32 command_parity_latency; 182 int sim_system_mode; 183 } sjc16_shmoo_dram_info_t; 184 185 typedef struct sjc16_shmoo_config_param_s 186 { 187 uint8 dq_byte_wr_min_vdl_bit[SHMOO_SJC16_DQ_CONFIG_NOF_BYTE][SHMOO_SJC16_BYTE]; 188 uint8 dq_byte_wr_min_vdl_dbi[SHMOO_SJC16_DQ_CONFIG_NOF_BYTE]; 189 uint8 dq_byte_wr_min_vdl_edc[SHMOO_SJC16_DQ_CONFIG_NOF_BYTE]; 190 uint32 dq_byte_wr_max_vdl_data[SHMOO_SJC16_DQ_CONFIG_NOF_BYTE]; 191 uint32 dq_byte_wr_max_vdl_dqs[SHMOO_SJC16_DQ_CONFIG_NOF_BYTE]; 192 193 uint8 dq_byte_rd_min_vdl_bit[SHMOO_SJC16_DQ_CONFIG_NOF_BYTE][SHMOO_SJC16_BYTE]; 194 uint8 dq_byte_rd_min_vdl_dbi[SHMOO_SJC16_DQ_CONFIG_NOF_BYTE]; 195 uint8 dq_byte_rd_min_vdl_edc[SHMOO_SJC16_DQ_CONFIG_NOF_BYTE]; 196 uint32 dq_byte_rd_max_vdl_dqsp[SHMOO_SJC16_DQ_CONFIG_NOF_BYTE]; 197 uint32 dq_byte_rd_max_vdl_dqsn[SHMOO_SJC16_DQ_CONFIG_NOF_BYTE]; 198 199 uint32 dq_byte_ren_fifo_config[SHMOO_SJC16_DQ_CONFIG_NOF_BYTE]; 200 uint32 dq_byte_edcen_fifo_config[SHMOO_SJC16_DQ_CONFIG_NOF_BYTE]; 201 uint32 dq_byte_rd_max_vdl_fsm[SHMOO_SJC16_DQ_CONFIG_NOF_BYTE]; 202 uint32 dq_byte_vref_dac_config[SHMOO_SJC16_DQ_CONFIG_NOF_BYTE]; 203 uint32 dq_byte_macro_reserved_reg[SHMOO_SJC16_DQ_CONFIG_NOF_BYTE]; 204 205 uint32 aq_l_max_vdl_addr; 206 uint32 aq_l_max_vdl_ctrl; 207 uint32 aq_l_macro_reserved_reg; 208 uint32 aq_u_max_vdl_addr; 209 uint32 aq_u_max_vdl_ctrl; 210 uint32 aq_u_macro_reserved_reg; 211 212 uint32 common_macro_reserved_reg; 213 214 uint32 control_regs_read_clock_config; 215 uint32 control_regs_input_shift_ctrl; 216 uint32 control_regs_ren_fifo_central_init; 217 uint32 control_regs_edcen_fifo_central_init; 218 uint32 control_regs_shared_vref_dac_config; 219 uint32 control_regs_reserved_reg; 220 221 } sjc16_shmoo_config_param_t; 222 223 typedef struct sjc16_vendor_info_s { 224 uint32 dram_density; 225 uint32 fifo_depth; 226 uint32 revision_id; 227 uint32 manufacture_id; 228 } sjc16_vendor_info_t; 229 230 typedef struct sjc16_shmoo_container_s 231 { 232 uint32 sizeX; 233 uint32 sizeY; 234 uint32 yCapMin; 235 uint32 yCapMax; 236 uint32 yJump; 237 uint32 calibMode; 238 uint32 calibPos; 239 uint32 calibStart; 240 uint32 result2D[(SHMOO_SJC16_RESULT2D_X)*(SHMOO_SJC16_RESULT2D_Y)]; 241 uint32 resultData[SHMOO_SJC16_WORD]; 242 uint32 shmooType; 243 uint32 dramType; 244 uint32 ctlType; 245 uint32 trefi; 246 uint32 step1000; 247 uint32 size1000UI; 248 uint32 endUI[SHMOO_SJC16_MAX_VISIBLE_UI_COUNT]; 249 uint32 engageUIshift; 250 uint32 restore; 251 uint32 debugMode; 252 } sjc16_shmoo_container_t; 253 254 typedef struct sjc16_step_size_s 255 { 256 uint32 step1000; 257 uint32 size1000UI; 258 } sjc16_step_size_t; 259 260 typedef struct sjc16_ui_position_s 261 { 262 uint32 ui; 263 uint32 position; 264 } sjc16_ui_position_t; 265 266 typedef uint32 sjc16_shmoo_error_array_t[SHMOO_SJC16_ERROR_ARRAY_LENGTH]; 267 268 extern int soc_sjc16_shmoo_dram_info_set(int unit, sjc16_shmoo_dram_info_t *sdi); 269 extern int soc_sjc16_shmoo_phy_init(int unit, int phy_ndx); 270 extern int soc_sjc16_shmoo_ctl(int unit, int phy_ndx, int shmoo_type, int stat, int plot, int action, sjc16_shmoo_config_param_t *config_param); 271 272 #endif /* _SHMOO_SJC16_H */ 273