shmoo_ddr40.h (11105B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * DDR3 Memory support 8 */ 9 10 #ifndef _SHMOO_DDR40_H__ 11 #define _SHMOO_DDR40_H__ 12 13 #ifdef BCM_DDR3_SUPPORT 14 15 /** 16 * ddr40 register access 17 * m = memory, c = core, r = register, f = field, d = data. 18 */ 19 #define DDR40_REG_READ(_unit, _pc, flags, _reg_addr, _val) \ 20 soc_ddr40_phy_reg_ci_read((_unit), (_pc), (_reg_addr), (_val)) 21 #define DDR40_REG_WRITE(_unit, _pc, _flags, _reg_addr, _val) \ 22 soc_ddr40_phy_reg_ci_write((_unit), (_pc), (_reg_addr), (_val)) 23 #define DDR40_REG_MODIFY(_unit, _pc, _flags, _reg_addr, _val, _mask) \ 24 soc_ddr40_phy_reg_ci_modify((_unit), (_pc), (_reg_addr), (_val), (_mask)) 25 #define DDR40_GET_FIELD(m,c,r,f) \ 26 GET_FIELD(m,c,r,f) 27 #define DDR40_SET_FIELD(m,c,r,f,d) \ 28 SET_FIELD(m,c,r,f,d) 29 30 /* 31 enum drc_reg_set_e must be coordinate with drc_regs_table 32 */ 33 34 typedef enum drc_reg_set_e { 35 DRC_BIST_CONFIGURATIONSr, 36 DRC_BIST_END_ADDRESSr, 37 DRC_BIST_ERROR_OCCURREDr, 38 DRC_BIST_NUMBER_OF_ACTIONSr, 39 DRC_BIST_PATTERN_WORD_0r, 40 DRC_BIST_PATTERN_WORD_1r, 41 DRC_BIST_PATTERN_WORD_2r, 42 DRC_BIST_PATTERN_WORD_3r, 43 DRC_BIST_PATTERN_WORD_4r, 44 DRC_BIST_PATTERN_WORD_5r, 45 DRC_BIST_PATTERN_WORD_6r, 46 DRC_BIST_PATTERN_WORD_7r, 47 DRC_BIST_START_ADDRESSr, 48 DRC_BIST_STATUSESr, 49 DRC_DPI_STATUSr, 50 DRC_DRAM_INIT_FINISHEDr, 51 DRC_REG_COUNT 52 } drc_reg_set_t; 53 54 /* Convenience Macros - Arad Memory Controller - Recheck when MemC files change */ 55 /* 56 uint32 DRC_REG_READ(int unit, uint32 channel, drc_reg_set_t base, uint32 *rvp); 57 58 uint32 DRC_REG_WRITE(int unit, uint32 channel, drc_reg_set_t base, uint32 rv); 59 */ 60 61 #define DRCA DRCA_AC_OPERATING_CONDITIONS_1r 62 #define DRCB DRCB_AC_OPERATING_CONDITIONS_1r 63 #define DRCC DRCC_AC_OPERATING_CONDITIONS_1r 64 #define DRCD DRCD_AC_OPERATING_CONDITIONS_1r 65 #define DRCE DRCE_AC_OPERATING_CONDITIONS_1r 66 #define DRCF DRCF_AC_OPERATING_CONDITIONS_1r 67 #define DRCG DRCG_AC_OPERATING_CONDITIONS_1r 68 #define DRCH DRCH_AC_OPERATING_CONDITIONS_1r 69 #define DRCALL DRCBROADCAST_AC_OPERATING_CONDITIONS_1r 70 71 /* Conveniece Macros - recheck when ddr40.h changes */ 72 #define DDR40_PHY_ADDR_CTL_MIN (0x0) 73 #define DDR40_PHY_ADDR_CTL_MAX (0x00c0) 74 #define DDR40_PHY_BYTE_LANE0_ADDR_MIN (0x0200) 75 #define DDR40_PHY_BYTE_LANE0_ADDR_MAX (0x03ac) 76 #define DDR40_PHY_BYTE_LANE1_ADDR_MIN (0x0400) 77 #define DDR40_PHY_BYTE_LANE1_ADDR_MAX (0x05ac) 78 79 #define READ_DDR40_PHY_WORD_LANE_x_VDL_OVRIDE_BYTEy_BITz_R_Pr(_x, _y, _z, _unit, _pc, _val) \ 80 DDR40_REG_READ((_unit), (_pc), 0x00, (0x00000234+(_x*0x200)+(_y*0xa0)+(_z*8)), (_val)) 81 82 #define WRITE_DDR40_PHY_WORD_LANE_x_VDL_OVRIDE_BYTEy_BITz_R_Pr(_x, _y, _z, _unit, _pc, _val) \ 83 DDR40_REG_WRITE((_unit), (_pc), 0x00, (0x00000234+(_x*0x200)+(_y*0xa0)+(_z*8)), (_val)) 84 85 #define WRITE_DDR40_PHY_WORD_LANE_x_VDL_OVRIDE_BYTEy_BITz_R_Nr(_x, _y, _z, _unit, _pc, _val) \ 86 DDR40_REG_WRITE((_unit), (_pc), 0x00, (0x00000238+(_x*0x200)+(_y*0xa0)+(_z*8)), (_val)) 87 88 #define READ_DDR40_PHY_WORD_LANE_x_VDL_OVRIDE_BYTEy_BITz_Wr(_x, _y, _z, _unit,_pc,_val) \ 89 DDR40_REG_READ((_unit), (_pc), 0x00, (0x00000210+(_x*0x200)+(_y*0xa0)+(_z*4)), (_val)) 90 91 #define WRITE_DDR40_PHY_WORD_LANE_x_VDL_OVRIDE_BYTEy_BITz_Wr(_x, _y, _z, _unit,_pc,_val) \ 92 DDR40_REG_WRITE((_unit), (_pc), 0x00, (0x00000210+(_x*0x200)+(_y*0xa0)+(_z*4)), (_val)) 93 94 95 /* DDR Phy Registers Read/Write */ 96 extern int soc_ddr40_phy_reg_ci_read(int unit, int ci, uint32 reg_addr, uint32 *reg_data); 97 extern int soc_ddr40_phy_reg_ci_write(int unit, int ci, uint32 reg_addr, uint32 reg_data); 98 extern int soc_ddr40_phy_reg_ci_modify(int unit, uint32 ci, uint32 reg_addr, uint32 data, uint32 mask); 99 100 extern int soc_ddr40_katana_phy_reg_ci_read(int unit, int ci, uint32 reg_addr, uint32 *reg_data); 101 extern int soc_ddr40_katana_phy_reg_ci_write(int unit, int ci, uint32 reg_addr, uint32 reg_data); 102 extern int soc_ddr40_katana_phy_reg_ci_modify(int unit, uint32 ci, uint32 reg_addr, uint32 data, uint32 mask); 103 104 extern int soc_ddr40_arad_phy_reg_ci_read(int unit, int ci, uint32 reg_addr, uint32 *reg_data); 105 extern int soc_ddr40_arad_phy_reg_ci_write(int unit, int ci, uint32 reg_addr, uint32 reg_data); 106 extern int soc_ddr40_arad_phy_reg_ci_modify(int unit, uint32 ci, uint32 reg_addr, uint32 data, uint32 mask); 107 108 /* DDR Registers Read/Write */ 109 extern int soc_ddr40_read(int unit, int ci, uint32 addr, uint32 *pData0, 110 uint32 *pData1, uint32 *pData2, uint32 *pData3, 111 uint32 *pData4, uint32 *pData5, uint32 *pData6, 112 uint32 *pData7); 113 114 extern int soc_ddr40_write(int unit, int ci, uint32 addr, uint32 uData0, 115 uint32 uData1, uint32 uData2, uint32 uData3, 116 uint32 uData4, uint32 uData5, uint32 uData6, 117 uint32 uData7); 118 119 /* ------------------- */ 120 /* PRE-TUNE Parameters */ 121 /* ------------------- */ 122 #define SHMOO_USE_PRETUNE 0 123 #define SHMOO_CI0_WL0_PRETUNE_RD_EN 13 124 #define SHMOO_CI0_WL0_PRETUNE_RD_DQS 47 125 #define SHMOO_CI0_WL0_PRETUNE_RD_DQ 37 126 #define SHMOO_CI0_WL0_PRETUNE_WR_DQ 30 127 #define SHMOO_CI0_WL1_PRETUNE_RD_EN (SHMOO_CI0_WL0_PRETUNE_RD_EN+8) 128 #define SHMOO_CI0_WL1_PRETUNE_RD_DQS (SHMOO_CI0_WL0_PRETUNE_RD_DQS-4) 129 #define SHMOO_CI0_WL1_PRETUNE_RD_DQ (SHMOO_CI0_WL0_PRETUNE_RD_DQ+8) 130 #define SHMOO_CI0_WL1_PRETUNE_WR_DQ (SHMOO_CI0_WL0_PRETUNE_WR_DQ+16) 131 132 #define SHMOO_CI0_WL0_PRETUNE_ADDR 35 133 134 #define SHMOO_CI2_WL0_PRETUNE_RD_EN (SHMOO_CI0_WL0_PRETUNE_RD_EN+2) 135 #define SHMOO_CI2_WL0_PRETUNE_RD_DQS SHMOO_CI0_WL0_PRETUNE_RD_DQS 136 #define SHMOO_CI2_WL0_PRETUNE_RD_DQ SHMOO_CI0_WL0_PRETUNE_RD_DQ 137 #define SHMOO_CI2_WL0_PRETUNE_WR_DQ SHMOO_CI0_WL0_PRETUNE_WR_DQ 138 139 /* --------------------- */ 140 /* CI1 Offset Parameters */ 141 /* --------------------- */ 142 #define SHMOO_CI1_OFFSET_RD_EN 0 143 #define SHMOO_CI1_OFFSET_RD_DQS 0 144 #define SHMOO_CI1_OFFSET_RD_DQ 0 /* 15 */ /* 20 */ /* 10+5 */ 145 #define SHMOO_CI1_OFFSET_WR_DQ 10 /* 20 */ /* 10 */ 146 147 /* for the name consistency sake */ 148 #define SHMOO_CI0_WL1_OFFSET_RD_EN SHMOO_CI1_OFFSET_RD_EN 149 #define SHMOO_CI0_WL1_OFFSET_RD_DQS SHMOO_CI1_OFFSET_RD_DQS 150 #define SHMOO_CI0_WL1_OFFSET_RD_DQ SHMOO_CI1_OFFSET_RD_DQ 151 #define SHMOO_CI0_WL1_OFFSET_WR_DQ SHMOO_CI1_OFFSET_WR_DQ 152 153 #define SHMOO_CI02_WL0_OFFSET_RD_EN 0 154 #define SHMOO_CI02_WL0_OFFSET_RD_DQS 0 155 #define SHMOO_CI02_WL0_OFFSET_RD_DQ 0 /* 10 */ 156 #define SHMOO_CI02_WL0_OFFSET_WR_DQ 0 /* 10 */ 157 158 /* Shmoo Functions */ 159 #define SHMOO_INIT_VDL_RESULT 0 160 #define SHMOO_RD_EN 1 161 #define SHMOO_RD_DQ 2 162 #define SHMOO_WR_DQ 3 163 #define SHMOO_ADDRC 4 164 #define SHMOO_WR_DM 5 /* 13->9 */ 165 166 #define DDR_PHYTYPE_RSVP 0 167 #define DDR_PHYTYPE_RSVP_STR "rsvp" 168 #define DDR_PHYTYPE_NS 1 169 #define DDR_PHYTYPE_NS_STR "ns" 170 #define DDR_PHYTYPE_ENG 2 171 #define DDR_PHYTYPE_ENG_STR "eng" 172 #define DDR_PHYTYPE_CE 4 173 #define DDR_PHYTYPE_CE_STR "ce" 174 #define DDR_PHYTYPE_HR2 5 175 #define DDR_PHYTYPE_HR2_STR "hr2" 176 177 #define DDR_CTLR_TRSVP 0 178 #define DDR_CTLR_TRSVP_STR "trsvp" 179 #define DDR_CTLR_T0 1 180 #define DDR_CTLR_T0_STR "t0" 181 #define DDR_CTLR_T1 2 182 #define DDR_CTLR_T1_STR "t1" 183 #define DDR_CTLR_T2 3 184 #define DDR_CTLR_T2_STR "t2" 185 #define DDR_CTLR_T3 4 186 #define DDR_CTLR_T3_STR "t3" 187 188 #define DDR_FREQ_400 400 189 #define DDR_FREQ_500 500 190 #define DDR_FREQ_533 533 191 #define DDR_FREQ_667 667 192 #define DDR_FREQ_800 800 193 #define DDR_FREQ_914 914 194 #define DDR_FREQ_933 933 195 #define DDR_FREQ_1066 1066 196 197 #define MEM_GRADE_080808 0x080808 198 #define MEM_GRADE_090909 0x090909 199 #define MEM_GRADE_101010 0x101010 200 #define MEM_GRADE_111111 0x111111 201 #define MEM_GRADE_121212 0x121212 202 #define MEM_GRADE_131313 0x131313 203 #define MEM_GRADE_141414 0x141414 204 205 #define MEM_ROWS_16K 16384 206 #define MEM_ROWS_32K 32768 207 208 #define MEM_1GBITS_IN_MBYTES (128) /* 128Mbytes for 1 GBits */ 209 210 enum freq_set { 211 FREQ_400, 212 FREQ_500, 213 FREQ_533, 214 FREQ_667, 215 FREQ_800, 216 FREQ_914, 217 FREQ_933, 218 FREQ_1066, 219 FREQ_COUNT 220 }; 221 222 enum phy_set { 223 PHY_RSVP, 224 PHY_NS, 225 PHY_ENG, 226 PHY_AND, 227 PHY_CE, 228 PHY_COUNT 229 }; 230 231 enum ctlr_set { 232 CTLR_TRSVP, 233 CTLR_T0, 234 CTLR_T1, 235 CTLR_T2, 236 CTLR_T3, 237 CTLR_COUNT 238 }; 239 240 enum grade_set { 241 GRADE_DEFAULT, 242 GRADE_080808, 243 GRADE_090909, 244 GRADE_101010, 245 GRADE_111111, 246 GRADE_121212, 247 GRADE_131313, 248 GRADE_141414, 249 GRADE_COUNT 250 }; 251 252 enum mem_size_set { 253 MEM_4G, 254 MEM_2G, 255 MEM_1G, 256 MEM_COUNT 257 }; 258 259 typedef struct { 260 int ndiv; 261 int mdiv; 262 } phy_freq_div_set_t; 263 264 typedef struct { 265 int twl, twr, trc; /* CONFIG0 */ 266 int rfifo_afull, rfifo_full; /* CONFIG1 */ 267 int trtw, twtr, tfaw, tread_enb; /* CONFIG2 */ 268 int bank_unavail_rd, bank_unavail_wr, rr_read, rr_write; /* CONFIG3 */ 269 int refrate; /* CONFIG4 */ 270 int trp_read, trp_write, trfc[MEM_COUNT]; /* CONFIG6 */ 271 int tzq; /* CONFIG7 */ 272 int cl, cwl, wr; /* PHY_STRAP0 */ 273 int jedec, mhz; /* PHY_STRAP1 */ 274 uint32 mr0, mr2; /* MR0, MR2 */ 275 } KATANAfreq_grade_mem_set_set_t; 276 277 typedef struct { 278 int chip_siz; 279 int ad_width; 280 } size_mem_type_set_t; 281 282 typedef struct { 283 char result[129]; 284 } bit_shmoo; 285 286 typedef struct { 287 bit_shmoo bs[16]; 288 uint32 step[16]; 289 uint32 raw_result[132]; 290 uint32 uncapped_rd_en_step[2]; 291 bit_shmoo bytes[2]; 292 } word_shmoo; 293 typedef word_shmoo vref_word_shmoo[64]; 294 295 typedef struct soc_ddr_shmoo_param_s { 296 int type, wl; 297 uint32 result[132]; 298 uint32 init_step[16]; 299 uint32 new_step[16]; 300 vref_word_shmoo *vwsPtr; 301 } soc_ddr_shmoo_param_t; 302 303 extern void soc_ddr40_set_shmoo_dram_config(uint32 unit, uint32 dram_config); 304 extern int soc_ddr40_phy_pll_ctl (int u, int ci, uint32 freq, uint32 phyType, int stat); 305 extern int soc_ddr40_phy_calibrate(int u, int ci, uint32 phyType, int stat); 306 extern int soc_ddr40_ctlr_ctl (int u, int ci, uint32 ctlType, int stat); 307 extern int soc_ddr40_shmoo_ctl (int u, int ci, uint32 phyType, uint32 ctlType, int stat, int isplot); 308 extern int soc_ddr40_shmoo_savecfg(int unit, int ci); 309 extern int soc_ddr40_shmoo_restorecfg(int unit, int ci); 310 extern int soc_ddr40_phy_pll_rst (int u, int ci, uint32 phyType, int cnt); 311 extern int soc_ddr40_ctlr_reset (int u, int ci, uint32 ctlType, int stat); 312 extern int soc_ddr40_ctlr_zqcal_ctl(int u, int ci, uint32 ctlType, int stat); 313 314 #endif /* DDR3 Support */ 315 316 #endif /* _ESW_DDR40_H__ */