shmoo_and28.h (11850B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * 28nm PHY Support 8 */ 9 10 /* BEGIN: TEMPORARY */ 11 /* END: TEMPORARY */ 12 13 #ifndef _SHMOO_AND28_H 14 #define _SHMOO_AND28_H 15 16 #include <sal/types.h> 17 #include <soc/defs.h> 18 #include <shared/types.h> 19 20 /** 21 * ddr34 register access 22 * m = memory, c = core, r = register, f = field, d = data. 23 */ 24 25 #define DDR34_REG_READ(_unit, _pc, flags, _reg_addr, _val) \ 26 soc_and28_phy_reg_read((_unit), (_pc), (_reg_addr), (_val)) 27 #define DDR34_REG_WRITE(_unit, _pc, _flags, _reg_addr, _val) \ 28 soc_and28_phy_reg_write((_unit), (_pc), (_reg_addr), (_val)) 29 #define DDR34_REG_MODIFY(_unit, _pc, _flags, _reg_addr, _val, _mask) \ 30 soc_and28_phy_reg_modify((_unit), (_pc), (_reg_addr), (_val), (_mask)) 31 #define DDR34_GET_FIELD(m,c,r,f) \ 32 GET_FIELD(m,c,r,f) 33 #define DDR34_SET_FIELD(m,c,r,f,d) \ 34 SET_FIELD(m,c,r,f,d) 35 36 #define SET_ADDR_VDL_FORCE(v) ( 0x10000 | ( (v) & 0x011FF ) ) 37 #define SET_VREF_DAC_CONTROL(v) ( (v) & 0xFFFFF ) 38 #define SET_WR_VDL_FORCE(v) ( 0x10000 | ( (v) & 0x011FF ) ) 39 #define SET_WR_CHAN_DLY_CYC_FORCE(v) ( 0x10000 | ( (v) & 0x000F7 ) ) 40 #define SET_RD_VDL_FORCE(v) ( 0x10000 | ( (v) & 0x010FF ) ) 41 #define SET_RD_EN_DLY_CYC_FORCE(v) ( 0x10000 | ( (v) & 0x001FF ) ) 42 #define SET_RD_CONTROL(v) ( (v) & 0x0001F ) 43 44 #define SHMOO_AND28_PHY_TYPE_RSVP 0 45 #define SHMOO_AND28_PHY_TYPE_E0 0xE0 46 #define SHMOO_AND28_PHY_TYPE_F0 0xF0 47 48 #define SHMOO_AND28_CTL_TYPE_RSVP 0 49 #define SHMOO_AND28_CTL_TYPE_RSVP_STR "t0" 50 #define SHMOO_AND28_CTL_TYPE_1 1 51 #define SHMOO_AND28_CTL_TYPE_1_STR "t1" 52 53 #define SHMOO_AND28_DRAM_TYPE_RSVP 0 54 #define SHMOO_AND28_DRAM_TYPE_DDR3 3 55 #define SHMOO_AND28_DRAM_TYPE_DDR3L 31 56 #define SHMOO_AND28_DRAM_TYPE_DDR4 4 57 #define SHMOO_AND28_DRAM_TYPE_GDDR5 5 58 59 #define SHMOO_AND28_BIT 1 60 #define SHMOO_AND28_BYTE (SHMOO_AND28_BIT << 3) 61 #define SHMOO_AND28_HALFWORD (SHMOO_AND28_BYTE << 1) 62 #define SHMOO_AND28_WORD (SHMOO_AND28_HALFWORD << 1) 63 #define SHMOO_AND28_DOUBLEWORD (SHMOO_AND28_WORD << 1) 64 #define SHMOO_AND28_QUADWORD (SHMOO_AND28_DOUBLEWORD << 1) 65 66 #define SHMOO_AND28_SHORT_SLEEP 1 67 #define SHMOO_AND28_LONG_SLEEP 10 68 #define SHMOO_AND28_DEEP_SLEEP 100 69 #define SHMOO_AND28_HIBERNATION 1000 70 #define SHMOO_AND28_STASIS 1000000 71 72 #define SHMOO_AND28_SHMOO_RSVP -1 73 #define SHMOO_AND28_RD_EN 23 74 #define SHMOO_AND28_RD_EXTENDED 50 75 #define SHMOO_AND28_WR_EXTENDED 60 76 #define SHMOO_AND28_ADDR_EXTENDED 71 77 #define SHMOO_AND28_CTRL_EXTENDED 72 78 #define SHMOO_AND28_DDR3_SEQUENCE_COUNT 5 79 #define SHMOO_AND28_DDR3L_SEQUENCE_COUNT 5 80 #define SHMOO_AND28_DDR4_SEQUENCE_COUNT 5 81 /* BEGIN: EXTRA */ 82 /* END: EXTRA */ 83 84 #define SHMOO_AND28_QUICK_SHMOO_CTRL_EXTENDED 1 85 86 #define SHMOO_AND28_REPEAT 9 87 #define SHMOO_AND28_REPEAT_HALF (SHMOO_AND28_REPEAT >> 1) 88 89 #define SHMOO_AND28_SEQUENTIAL 0 90 #define SHMOO_AND28_SINGLE 1 91 92 #define SHMOO_AND28_ACTION_RSVP -1 93 #define SHMOO_AND28_ACTION_RESTORE 0 94 #define SHMOO_AND28_ACTION_RUN 1 95 #define SHMOO_AND28_ACTION_SAVE 2 96 #define SHMOO_AND28_ACTION_RUN_AND_SAVE 3 97 98 #define SHMOO_AND28_CTL_FLAGS_STAT_BIT 0x1 99 #define SHMOO_AND28_CTL_FLAGS_PLOT_BIT 0x2 100 #define SHMOO_AND28_CTL_FLAGS_EXT_VREF_RANGE_BIT 0x4 101 #define SHMOO_AND28_DEBUG_MODE_FLAG_BITS SHMOO_AND28_CTL_FLAGS_EXT_VREF_RANGE_BIT 102 103 #define SHMOO_AND28_MAX_INTERFACES 8 104 #define SHMOO_AND28_INTERFACE_RSVP -1 105 #define SHMOO_AND28_BYTES_PER_INTERFACE 4 106 107 #define SHMOO_AND28_BIST_NOF_PATTERNS 8 108 #define SHMOO_AND28_BIST_MPR_NOF_PATTERNS 4 109 110 #define SHMOO_AND28_MAX_VISIBLE_UI_COUNT 4 111 #define SHMOO_AND28_MAX_EFFECTIVE_UI_COUNT 4 112 #define SHMOO_AND28_LAST_EFFECTIVE_UI (SHMOO_AND28_MAX_EFFECTIVE_UI_COUNT - 1) 113 #define SHMOO_AND28_MAX_VDL_LENGTH 256 114 #define SHMOO_AND28_MAX_VREF_RANGE 64 115 #define SHMOO_AND28_MAX_ZQ_CAL_RANGE 32 116 117 #define SHMOO_AND28_RESULT2D_X SHMOO_AND28_MAX_VDL_LENGTH 118 #define SHMOO_AND28_RESULT2D_Y SHMOO_AND28_MAX_VREF_RANGE 119 120 #define SHMOO_AND28_STRING_LENGTH (SHMOO_AND28_RESULT2D_X + 1) 121 #define SHMOO_AND28_ERROR_ARRAY_LENGTH 4 122 123 #define SHMOO_AND28_CALIB_CENTER_PASS 111 124 #define SHMOO_AND28_CALIB_RISING_EDGE 011 125 #define SHMOO_AND28_CALIB_FALLING_EDGE 100 126 #define SHMOO_AND28_CALIB_PASS_START 001 127 #define SHMOO_AND28_CALIB_FAIL_START 110 128 #define SHMOO_AND28_CALIB_VDL_ZERO 000 129 130 #define SHMOO_AND28_VDL_TFIX 18 131 132 #define SHMOO_AND28_RD_DATA_DLY_INIT 7 133 134 #define SHMOO_AND28_RD_EN_CYC_INIT 2 135 136 #define SHMOO_AND28_RD_EN_VDL_INIT 0 137 138 #define SHMOO_AND28_RD_DQ_VDL_INIT 0 139 #define SHMOO_AND28_RD_DQ_FAIL_CAP 5 140 141 #define SHMOO_AND28_RD_DQS_VDL_OFFSET SHMOO_AND28_RD_DQ_VDL_INIT 142 143 #define SHMOO_AND28_WR_CYC_INIT 0 144 145 #define SHMOO_AND28_PHY_NOF_AD 16 146 #define SHMOO_AND28_PHY_NOF_BA 3 147 #define SHMOO_AND28_PHY_NOF_AUX 3 148 #define SHMOO_AND28_PHY_NOF_CS 2 149 150 typedef struct and28_shmoo_dram_info_s 151 { 152 uint32 ctl_type; 153 uint32 dram_type; 154 uint32 dram_bitmap; 155 uint32 interface_bitwidth; 156 uint32 split_bus; 157 int num_columns; 158 int num_rows; 159 int num_banks; 160 int num_bank_groups; 161 int data_rate_mbps; 162 int ref_clk_mhz; 163 uint32 refi; 164 uint32 command_parity_latency; 165 int sim_system_mode; 166 } and28_shmoo_dram_info_t; 167 168 typedef struct and28_shmoo_config_param_s 169 { 170 uint16 control_regs_ad[SHMOO_AND28_PHY_NOF_AD]; 171 uint16 control_regs_ba[SHMOO_AND28_PHY_NOF_BA]; 172 uint16 control_regs_aux[SHMOO_AND28_PHY_NOF_AUX]; 173 uint16 control_regs_cs[SHMOO_AND28_PHY_NOF_CS]; 174 uint16 control_regs_par; 175 uint16 control_regs_ras_n; 176 uint16 control_regs_cas_n; 177 uint16 control_regs_cke; 178 uint16 control_regs_rst_n; 179 uint16 control_regs_odt; 180 uint16 control_regs_we_n; 181 uint32 control_regs_vref_dac_control; 182 183 uint16 wr_vdl_dqsp[SHMOO_AND28_BYTES_PER_INTERFACE]; 184 uint16 wr_vdl_dqsn[SHMOO_AND28_BYTES_PER_INTERFACE]; 185 uint16 wr_vdl_dq[SHMOO_AND28_BYTES_PER_INTERFACE][SHMOO_AND28_BYTE]; 186 uint16 wr_vdl_dm[SHMOO_AND28_BYTES_PER_INTERFACE]; 187 uint16 wr_vdl_edc[SHMOO_AND28_BYTES_PER_INTERFACE]; 188 uint8 wr_chan_dly_cyc[SHMOO_AND28_BYTES_PER_INTERFACE]; 189 190 uint16 rd_vdl_dqsp[SHMOO_AND28_BYTES_PER_INTERFACE]; 191 uint16 rd_vdl_dqsn[SHMOO_AND28_BYTES_PER_INTERFACE]; 192 uint16 rd_vdl_dqp[SHMOO_AND28_BYTES_PER_INTERFACE][SHMOO_AND28_BYTE]; 193 uint16 rd_vdl_dqn[SHMOO_AND28_BYTES_PER_INTERFACE][SHMOO_AND28_BYTE]; 194 uint16 rd_vdl_dmp[SHMOO_AND28_BYTES_PER_INTERFACE]; 195 uint16 rd_vdl_dmn[SHMOO_AND28_BYTES_PER_INTERFACE]; 196 uint16 rd_en_vdl_cs[SHMOO_AND28_BYTES_PER_INTERFACE][SHMOO_AND28_PHY_NOF_CS]; 197 uint16 rd_en_dly_cyc[SHMOO_AND28_BYTES_PER_INTERFACE]; 198 uint8 rd_control[SHMOO_AND28_BYTES_PER_INTERFACE]; 199 } and28_shmoo_config_param_t; 200 201 typedef struct and28_bist_info_s 202 { 203 uint32 write_weight; 204 uint32 read_weight; 205 uint32 bist_timer_us; /* if bist_timer_us != 0, ignore bist_num_actions and wait bist_timer_us before stoping bist */ 206 uint32 bist_num_actions; 207 uint32 bist_start_address; 208 uint32 bist_end_address; 209 uint32 prbs_mode; 210 uint32 mpr_mode; 211 uint32 data_pattern[SHMOO_AND28_BIST_NOF_PATTERNS]; 212 uint8 mpr_pattern[SHMOO_AND28_BIST_MPR_NOF_PATTERNS]; 213 } and28_bist_info_t; 214 215 typedef struct and28_bist_err_cnt_s 216 { 217 uint32 bist_err_occur; 218 uint32 bist_full_err_cnt; 219 uint32 bist_single_err_cnt; 220 uint32 bist_global_err_cnt; 221 } and28_bist_err_cnt_t; 222 223 typedef struct and28_vendor_info_s { 224 uint32 dram_density; 225 uint32 fifo_depth; 226 uint32 revision_id; 227 uint32 manufacture_id; 228 } and28_vendor_info_t; 229 230 typedef struct and28_shmoo_container_s 231 { 232 uint32 sizeX; 233 uint32 sizeY; 234 uint32 yCapMin; 235 uint32 yCapMax; 236 uint32 yJump; 237 uint32 calibMode; 238 uint32 calibPos; 239 uint32 calibStart; 240 uint32 result2D[(SHMOO_AND28_RESULT2D_X)*(SHMOO_AND28_RESULT2D_Y)]; 241 uint32 resultData[SHMOO_AND28_DOUBLEWORD]; 242 uint32 shmooType; 243 uint32 dramType; 244 uint32 ctlType; 245 uint32 trefi; 246 uint32 step1000; 247 uint32 size1000UI; 248 uint32 endUI[SHMOO_AND28_MAX_VISIBLE_UI_COUNT]; 249 uint32 engageUIshift; 250 uint32 wckInv; 251 uint32 restore; 252 uint32 debugMode; 253 } and28_shmoo_container_t; 254 255 typedef struct and28_step_size_s 256 { 257 uint32 step1000; 258 uint32 size1000UI; 259 } and28_step_size_t; 260 261 typedef struct and28_ui_position_s 262 { 263 uint32 ui; 264 uint32 position; 265 } and28_ui_position_t; 266 267 typedef uint32 and28_shmoo_error_array_t[SHMOO_AND28_ERROR_ARRAY_LENGTH]; 268 269 typedef struct and28_shmoo_cbi_s { 270 /* PHY register Read */ 271 int (*and28_phy_reg_read)(int unit, int drc_ndx, uint32 addr, uint32 *data); 272 /* PHY register write */ 273 int (*and28_phy_reg_write)(int unit, int drc_ndx, uint32 addr, uint32 data); 274 /* PHY register Modify */ 275 int (*and28_phy_reg_modify)(int unit, int drc_ndx, uint32 addr, uint32 data, uint32 mask); 276 /* BIST Configuration */ 277 int (*and28_drc_bist_conf_set)(int unit, int drc_ndx, and28_bist_info_t info); 278 /* Get BIST error count */ 279 int (*and28_drc_bist_err_cnt)(int unit, int drc_ndx, and28_bist_err_cnt_t *info); 280 /* Set Dram Init Phase (First - 1/Second - 2) */ 281 int (*and28_drc_dram_init)(int unit, int drc_ndx, int phase); 282 } and28_shmoo_cbi_t; 283 284 typedef int (*soc_and28_phy_reg_read_t)(int unit, int drc_ndx, uint32 addr, uint32 *data); 285 typedef int (*soc_and28_phy_reg_write_t)(int unit, int drc_ndx, uint32 addr, uint32 data); 286 typedef int (*soc_and28_phy_reg_modify_t)(int unit, int drc_ndx, uint32 addr, uint32 data, uint32 mask); 287 typedef int (*_shmoo_and28_drc_bist_conf_set_t)(int unit, int drc_ndx, and28_bist_info_t info); 288 typedef int (*_shmoo_and28_drc_bist_err_cnt_t)(int unit, int drc_ndx, and28_bist_err_cnt_t *info); 289 typedef int (*_shmoo_and28_drc_dram_init_t)(int unit, int drc_ndx, int phase); 290 291 extern soc_and28_phy_reg_read_t soc_and28_phy_reg_read; 292 extern soc_and28_phy_reg_write_t soc_and28_phy_reg_write; 293 extern soc_and28_phy_reg_modify_t soc_and28_phy_reg_modify; 294 extern int soc_and28_shmoo_interface_cb_register(int unit, and28_shmoo_cbi_t shmoo_cbi); 295 extern int soc_and28_shmoo_dram_info_set(int unit, CONST and28_shmoo_dram_info_t *sdi); 296 extern int soc_and28_shmoo_phy_init(int unit, int drc_ndx); 297 extern int soc_and28_shmoo_ctl(int unit, int drc_ndx, int shmoo_type, uint32 flags, int action, and28_shmoo_config_param_t *config_param); 298 299 #endif /* _SHMOO_AND28_H */