saber2.h (31912B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * File: saber2.h 8 */ 9 10 #ifndef _SOC_SABER2_H_ 11 #define _SOC_SABER2_H_ 12 13 #include <soc/drv.h> 14 #include <soc/mem.h> 15 #include <soc/error.h> 16 #include <soc/katana2.h> 17 #include <soc/shmoo_and28.h> 18 typedef struct sb2_pbmp_s { 19 soc_pbmp_t *pbmp_gport_stack; 20 soc_pbmp_t *pbmp_mxq; 21 soc_pbmp_t *pbmp_mxq1g; 22 soc_pbmp_t *pbmp_mxq2p5g; 23 soc_pbmp_t *pbmp_mxq10g; 24 soc_pbmp_t *pbmp_xl; 25 soc_pbmp_t *pbmp_xl1g; 26 soc_pbmp_t *pbmp_xl2p5g; 27 soc_pbmp_t *pbmp_xl10g; 28 soc_pbmp_t *pbmp_xport_ge; 29 soc_pbmp_t *pbmp_xport_xe; 30 soc_pbmp_t *pbmp_valid; 31 soc_pbmp_t *pbmp_pp; 32 soc_pbmp_t *pbmp_linkphy; 33 }sb2_pbmp_t; 34 35 36 typedef struct sb2_tdm_pos_info_s { 37 uint16 total_slots; 38 int16 pos[180]; 39 } sb2_tdm_pos_info_t; 40 41 typedef struct bcm56260_tdm_info_s { 42 uint8 tdm_freq; 43 uint32 tdm_size; 44 45 /* Display purpose only */ 46 uint8 row; 47 uint8 col; 48 }bcm56260_tdm_info_t; 49 50 typedef enum bcmXlPhyPortMode_s { 51 bcmXlPhyPortModeQuad=0, 52 bcmXlPhyPortModeTri012=1, 53 bcmXlPhyPortModeTri023=2, 54 bcmXlPhyPortModeDual=3, 55 bcmXlPhyPortModeSingle=4, 56 bcmXlPhyPortModeTdmDisable=5 57 }bcmXlPhyPortMode_t; 58 59 typedef enum bcmXlCorePortMode_s { 60 bcmXlCorePortModeQuad=0, 61 bcmXlCorePortModeTri012=1, 62 bcmXlCorePortModeTri023=2, 63 bcmXlCorePortModeDual=3, 64 bcmXlCorePortModeSingle=4, 65 bcmXlCorePortModeTdmDisable=5 66 }bcmXlCorePortMode_t; 67 68 #define SB2_BIST_FLAGS_CONS_ADDR_8_BANKS (0x0001) 69 #define SB2_BIST_FLAGS_ADDRESS_SHIFT_MODE (0X0002) 70 #define SB2_BIST_FLAGS_INFINITE (0x0004) 71 #define SB2_BIST_FLAGS_ALL_ADDRESS (0x0008) 72 #define SB2_BIST_FLAGS_STOP (0x0010) 73 #define SB2_BIST_FLAGS_GET_DATA (0x0020) 74 #define SB2_BIST_FLAGS_TWO_ADDRESS_MODE (0x0040) 75 #define SB2_BIST_FLAGS_BG_INTERLEAVE (0x0080) 76 #define SB2_BIST_FLAGS_SINGLE_BANK_TEST (0x0100) 77 #define SB2_BIST_FLAGS_MPR_STAGGER_MODE (0x0200) 78 #define SB2_BIST_FLAGS_MPR_STAGGER_INCREMENT_MODE (0x0400) 79 #define SB2_BIST_FLAGS_MPR_READOUT_MODE (0x0800) 80 #define SB2_BIST_FLAGS_ADDRESS_PRBS_MODE (0x1000) 81 #define SB2_BIST_FLAGS_USE_RANDOM_DATA_SEED (0x2000) 82 #define SB2_BIST_FLAGS_USE_RANDOM_DBI_SEED (0x4000) 83 84 #define SB2_BIST_FLAGS_USE_RANDOM_SEED \ 85 (SB2_BIST_FLAGS_USE_RANDOM_DATA_SEED | SB2_BIST_FLAGS_USE_RANDOM_DBI_SEED) 86 87 88 #define SB2_BIST_NUM_PATTERNS 8 89 #define SB2_BIST_NUM_SEEDS 8 90 #define SB2_BIST_MPR_NUM_PATTERNS 4 91 92 typedef enum 93 { 94 SB2_BIST_MPR_MODE_SERIAL = 0, 95 SB2_BIST_MPR_MODE_PARALLEL = 1, 96 SB2_BIST_MPR_MODE_STAGARED = 2, 97 SB2_BIST_MPR_DISABLE = 3 98 } SB2_BIST_MPR_MODE; 99 100 typedef struct { 101 SB2_BIST_MPR_MODE mpr_mode; 102 uint32 mpr_readout_mpr_location; 103 uint8 mpr_pattern[SB2_BIST_MPR_NUM_PATTERNS]; 104 } sb2_bist_mpr_info; 105 106 typedef enum { 107 SB2_DRAM_BIST_DATA_PATTERN_CUSTOM = 0, 108 SB2_DRAM_BIST_DATA_PATTERN_RANDOM_PRBS = 1, 109 SB2_DRAM_BIST_DATA_PATTERN_DIFF = 2, 110 SB2_DRAM_BIST_DATA_PATTERN_ONE = 3, 111 SB2_DRAM_BIST_DATA_PATTERN_ZERO = 4, 112 SB2_DRAM_BIST_DATA_PATTERN_BIT_MODE = 5, 113 SB2_DRAM_BIST_DATA_PATTERN_SHIFT_MODE = 6, 114 SB2_DRAM_BIST_DATA_PATTERN_ADDR_MODE = 7, 115 SB2_DRAM_BIST_NOF_DATA_PATTERN_MODES = 8 116 }SB2_DRAM_BIST_DATA_PATTERN_MODE; 117 118 typedef struct { 119 uint32 write_weight; 120 uint32 read_weight; 121 uint32 bist_num_actions; 122 uint32 bist_start_address; 123 uint32 bist_end_address; 124 SB2_DRAM_BIST_DATA_PATTERN_MODE pattern_mode; 125 uint32 pattern[SB2_BIST_NUM_PATTERNS]; 126 uint32 data_seed[SB2_BIST_NUM_SEEDS]; 127 uint32 bist_flags; 128 }sb2_bist_info; 129 130 #define SB2_MEM_GRADE_080808 0x080808 131 #define SB2_MEM_GRADE_090909 0x090909 132 #define SB2_MEM_GRADE_101010 0x101010 133 #define SB2_MEM_GRADE_111111 0x111111 134 #define SB2_MEM_GRADE_121212 0x121212 135 #define SB2_MEM_GRADE_131313 0x131313 136 #define SB2_MEM_GRADE_141414 0x141414 137 138 #define SB2_MEM_ROWS_16K 16384 139 #define SB2_MEM_ROWS_32K 32768 140 141 #define SB2_DDR_FREQ_667 667 142 #define SB2_DDR_FREQ_800 800 143 144 /* Core PLL clock frequencies */ 145 #define CORE_PLL_CLOCK_130M 130 146 #define CORE_PLL_CLOCK_118M 118 147 #define CORE_PLL_CLOCK_75M 75 148 #define CORE_PLL_CLOCK_37M 37 149 #define CORE_PLL_CLOCK_24M 24 150 151 enum sb2_mem_size_set { 152 SB2_MEM_4G, 153 SB2_MEM_2G, 154 SB2_MEM_1G, 155 SB2_MEM_COUNT 156 }; 157 158 enum sb2_freq_set { 159 SB2_FREQ_667, 160 SB2_FREQ_800, 161 SB2_FREQ_CNT 162 }; 163 164 enum sb2_grade_set { 165 SB2_GRADE_DEFAULT, 166 SB2_GRADE_080808, 167 SB2_GRADE_090909, 168 SB2_GRADE_101010, 169 SB2_GRADE_111111, 170 SB2_GRADE_121212, 171 SB2_GRADE_131313, 172 SB2_GRADE_141414, 173 SB2_GRADE_CNT 174 }; 175 176 enum sb2_core_pll_clock { 177 SB2_CORE_PLL_CLOCK_130M, 178 SB2_CORE_PLL_CLOCK_118M, 179 SB2_CORE_PLL_CLOCK_75M, 180 SB2_CORE_PLL_CLOCK_37M, 181 SB2_CORE_PLL_CLOCK_24M, 182 SB2_CORE_PLL_CLOCK_CNT 183 }; 184 185 #define SOC_SB2_AND28_INTERFACES_NUM_MAX 8 186 #define SOC_SB2_AND28_NOF_PER_INTERFACE_BYTES 4 187 #define SOC_SB2_AND28_NOF_BITS_IN_BYTE 8 188 #define SOC_SB2_AND28_MRS_NUM_MAX 16 189 190 191 typedef struct { 192 int twl, twr, trc; /* CONFIG0 */ 193 int rfifo_afull, rfifo_full; /* CONFIG1 */ 194 int trtw, twtr, tfaw, tread_enb; /* CONFIG2 */ 195 int bank_unavail_rd, bank_unavail_wr, rr_read, rr_write; /* CONFIG3 */ 196 int refrate; /* CONFIG4 */ 197 int trp_read, trp_write, trfc[3]; /* CONFIG6 */ 198 int tzq; /* CONFIG7 */ 199 int cl, cwl, wr; /* PHY_STRAP0 */ 200 int jedec, mhz; /* PHY_STRAP1 */ 201 uint32 mr0, mr2; /* MR0, MR2 */ 202 } sb2_req_grade_mem_set_set_t; 203 204 typedef struct soc_sb2_and28_info_s { 205 uint32 device_core_freq; 206 uint32 device_dram_num_max; 207 uint8 enable; 208 uint32 dram_bitmap; 209 soc_pbmp_t ref_clk_bitmap; 210 int dram_num; 211 int dram_freq; 212 int data_rate_mbps; 213 int ref_clk_mhz; 214 uint32 dram_type; 215 uint32 nof_banks; 216 uint32 nof_columns; 217 uint32 nof_rows; 218 #if 0 219 soc_sb2_and28_info_dram_param_t dram_param; 220 soc_sb2_and28_info_dram_internal_param_t dram_int_param; 221 #endif 222 uint32 mr[ SOC_SB2_AND28_MRS_NUM_MAX]; 223 #if 0 224 DRC_AND28_DRAM_CLAM_SHELL_MODE 225 dram_clam_shell_mode[SOC_SB2_AND28_INTERFACES_NUM_MAX]; 226 #endif 227 uint32 228 dram_dq_swap[SOC_SB2_AND28_INTERFACES_NUM_MAX][SOC_SB2_AND28_NOF_PER_INTERFACE_BYTES][SOC_SB2_AND28_NOF_BITS_IN_BYTE]; 229 230 uint32 gear_down_mode; 231 uint32 alert_n_period_thrs; 232 uint32 abi; 233 uint32 write_dbi; 234 uint32 read_dbi; 235 uint32 write_crc; 236 uint32 read_crc; 237 uint32 cmd_par_latency; 238 int auto_tune; 239 and28_shmoo_config_param_t shmoo_config_param[SOC_SB2_AND28_INTERFACES_NUM_MAX]; 240 uint8 bist_enable; 241 int sim_system_mode; 242 }soc_sb2_and28_info_t; 243 244 typedef struct _sb2_cosq_counter_mem_map_s { 245 soc_mem_t mem; 246 soc_counter_non_dma_id_t non_dma_id; 247 char *cname_pkt; 248 char *cname_byte; 249 }_sb2_cosq_counter_mem_map_t; 250 251 /* *************************************************************** */ 252 /* SABER2 MMU HELPER --- START(As per Saber2_MMU_Settings-5.xls */ 253 /* *************************************************************** */ 254 /* Dynamic/SetLater Parameter */ 255 typedef struct _soc_sb2_mmu_params_s { 256 uint32 mmu_min_pkt_size; /*C5*/ 257 uint32 mmu_ethernet_mtu_bytes; /*C6*/ 258 uint32 mmu_max_pkt_size; /*C7*/ 259 uint32 mmu_jumbo_frame_size; /*C8*/ 260 uint32 mmu_int_buf_cell_size; /*C9*/ 261 /* mmu_ext_buf_cell_size = (mmu_int_buf_cell_size+2)*15; */ 262 uint32 mmu_ext_buf_cell_size; /*C10=2880*/ 263 uint32 mmu_pkt_header_size; /*C11*/ 264 uint32 packing_mode_d_c; /* C12:Dynamic */ 265 uint32 max_pkt_size_support_packing; /* C13:Dynamic */ 266 uint32 lossless_mode_d_c; /* C14:Dynamic */ 267 uint32 pfc_pause_mode_d_c; /* C15:Dynamic */ 268 uint32 mmu_lossless_pg_num; /*C16*/ 269 uint32 extbuf_used_d_c; /* C17:Dynamic */ 270 uint32 num_ge_ports_d; /* C19:Dynamic */ 271 uint32 mmu_line_rate_ge; /*C20*/ 272 uint32 num_ge_int_ports_d; /* c21:Dynamic */ 273 uint32 num_egr_queue_per_int_ge_port_d; /* C22:Dynamic */ 274 uint32 num_ge_ext_ports_d; /* C23:Dynamic */ 275 uint32 num_egr_queue_per_ext_ge_port_d; /* C24:Dynamic */ 276 uint32 num_hg_ports_d; /* C25:Dynamic */ 277 uint32 mmu_line_rate_hg; /*C26*/ 278 uint32 num_hg_int_ports_d; /* C27:Dynamic */ 279 uint32 num_egr_queue_per_int_hg_port_d; /* C28:Dynamic */ 280 uint32 num_hg_ext_ports_d; /* C29:Dynamic */ 281 uint32 num_egr_queue_per_ext_hg_port_d; /* C30:Dynamic */ 282 uint32 mmu_num_cpu_port; /*C31*/ 283 uint32 mmu_num_cpu_queue; /*C32*/ 284 uint32 cpu_port_int_ext_bounding_d_c; /* C33:Dynamic */ 285 uint32 mmu_num_loopback_port; /*C34*/ 286 uint32 mmu_num_loopback_queue; /*C35*/ 287 uint32 mmu_num_ep_redirection_queue; /*C36*/ 288 uint32 mmu_num_olp_port_d; /*C37*/ 289 uint32 mmu_num_olp_queue; /*C38*/ 290 uint32 olp_port_int_ext_bounding_d_c; /*C39:Dynamic*/ 291 uint32 mmu_total_egress_queue; /*C40*/ 292 uint32 mmu_pipeline_lat_cpap_admission; /*C41*/ 293 uint32 mmu_int_buf_size; /*C42:2048KB=2MB*/ 294 uint32 mmu_available_int_buf_size_d; /*C43:1434KB */ 295 uint32 mmu_reserved_int_buf_cells; /*C44:100 Cells */ 296 uint32 mmu_reserved_int_buf_ema_pool_size_d; /*C45:614KB */ 297 uint32 internal_buffer_reduction_d_c; /* C46:Dynamic */ 298 uint32 mmu_ext_buf_size; /*C47:737280KB=720MB*/ 299 uint32 mmu_reserved_ext_buf_space_cfap; /*C48:737280KB=720MB*/ 300 uint32 mmu_egress_queue_entries; /*C49*/ 301 uint32 mmu_ep_redirect_queue_entries; /*C50*/ 302 uint32 mmu_exp_num_of_repl_per_pkt; /*C51*/ 303 uint32 mmu_repl_engine_work_queue_entries; /*C52*/ 304 uint32 mmu_resv_repl_engine_work_queue_entries; /*C53*/ 305 uint32 mmu_repl_engine_work_queue_in_device;/*C54*/ 306 uint32 mmu_ema_queues; /*C55*/ 307 uint32 num_cells_rsrvd_ing_ext_buf; /* C56:Dynamic */ 308 uint32 per_cos_res_cells_for_int_buff_d; /* C58:Dynamic */ 309 uint32 per_cos_res_cells_for_ext_buff_d; /* C59:Dynamic */ 310 uint32 mmu_ing_port_dyn_thd_param; /*C60*/ 311 uint32 mmu_ing_pg_dyn_thd_param; /*C61*/ 312 uint32 mmu_egr_queue_dyn_thd_param_baf; /*C62*/ 313 uint32 mmu_egr_queue_dyn_thd_param_baf_profile_lossy; /*C63*/ 314 uint32 mmu_ing_cell_buf_reduction; /*C64 */ 315 uint32 mmu_ing_pkt_buf_reduction; /*C65 */ 316 } _soc_sb2_mmu_params_t; 317 extern _soc_sb2_mmu_params_t _soc_sb2_mmu_params; 318 319 320 typedef struct _sb2_general_info_s { 321 uint32 max_packet_size_in_cells; /* C72 */ 322 uint32 jumbo_frame_for_int_buff; /* C73 */ 323 uint32 jumbo_frame_for_ext_buff; /* C74 */ 324 uint32 ether_mtu_cells_for_int_buff; /* C76 */ 325 uint32 ether_mtu_cells_for_ext_buff; /* C77 */ 326 uint32 total_num_of_ports; /* C79 */ 327 uint32 total_num_of_ports_excl_lpbk; /* C80 */ 328 uint32 total_num_of_ports_excl_lpbk_olp; /* C81 */ 329 uint32 total_num_of_ports_excl_lpbk_olp_cpu; /* C82 */ 330 uint32 port_bw_bound_to_ext_buff; /* C83 */ 331 uint32 total_egr_queues_for_a_int_ge_ports; /* C84 */ 332 uint32 total_egr_queues_for_a_ext_ge_ports; /* C85 */ 333 uint32 total_egr_queues_for_a_int_hg_ports; /* C86 */ 334 uint32 total_egr_queues_for_a_ext_hg_ports; /* C87 */ 335 uint32 total_cpu_queues; /* C88 */ 336 uint32 total_base_queue_int_buff; /* C89 */ 337 uint32 total_base_queue_ext_buff; /* C90 */ 338 uint32 total_ema_queues; /* C91 */ 339 uint32 total_egr_base_queues_in_device; /* C93 */ 340 uint32 total_egr_queues_in_device; /* C94 */ 341 uint32 max_int_cell_buff_size; /* C95 */ 342 uint32 int_cell_buff_size_after_limitation; /* C96 */ 343 uint32 src_packing_fifo; /* C97 */ 344 uint32 int_buff_pool; /* C98 */ 345 uint32 ema_pool; /* C99 */ 346 uint32 max_ext_cell_buff_size; /* C100 */ 347 uint32 repl_engine_work_queue_entries; /* C101 */ 348 uint32 ratio_of_ext_buff_to_int_buff_size; /* C103 */ 349 uint32 int_buff_cells_per_avg_size_pkt; /* C104 */ 350 uint32 ext_buff_cells_per_avg_size_pkt; /* C105 */ 351 uint32 max_prop_of_buff_used_by_one_queue_port; /* C106 */ 352 }_sb2_general_info_t; 353 354 typedef struct _sb2_input_port_threshold_s { 355 uint32 global_hdrm_cells_for_int_buff_ingress_pool; /* C110 */ 356 uint32 global_hdrm_cells_for_int_buff_ema_pool; /* C111 */ 357 uint32 global_hdrm_cells_for_ext_buff_pool; /* C112 */ 358 uint32 global_hdrm_cells_for_RE_WQEs; /* C113 */ 359 uint32 global_hdrm_cells_for_EQEs; /* C114 */ 360 361 uint32 hdrm_int_buff_cells_for_10G_PG; /* C115 */ 362 uint32 hdrm_ema_buff_cells_for_10G_PG; /* C116 */ 363 uint32 hdrm_ext_buff_cells_for_10G_PG; /* C117 */ 364 uint32 hdrm_RE_WQEs_pkts_for_10G_PG; /* C118 */ 365 uint32 hdrm_EQEs_pkts_for_10G_PG; /* C119 */ 366 367 uint32 hdrm_int_buff_cells_for_10G_total_PG; /* C120 */ 368 uint32 hdrm_ema_buff_cells_for_10G_total_PG; /* C121 */ 369 uint32 hdrm_ext_buff_cells_for_10G_total_PG; /* C122 */ 370 uint32 hdrm_RE_WQEs_pkts_for_10G_total_PG; /* C123 */ 371 uint32 hdrm_EQEs_pkts_for_10G_total_PG; /* C124 */ 372 373 uint32 hdrm_int_buff_cells_for_1G_PG; /* C125 */ 374 uint32 hdrm_ema_buff_cells_for_1G_PG; /* C126 */ 375 uint32 hdrm_ext_buff_cells_for_1G_PG; /* C127 */ 376 uint32 hdrm_RE_WQEs_pkts_for_1G_PG; /* C128 */ 377 uint32 hdrm_EQEs_pkts_for_1G_PG; /* C129 */ 378 379 uint32 hdrm_int_buff_cells_for_1G_total_PG; /* C130 */ 380 uint32 hdrm_ema_buff_cells_for_1G_total_PG; /* C131 */ 381 uint32 hdrm_ext_buff_cells_for_1G_total_PG; /* C132 */ 382 uint32 hdrm_RE_WQEs_pkts_for_1G_total_PG; /* C133 */ 383 uint32 hdrm_EQEs_pkts_for_1G_total_PG; /* C134 */ 384 385 uint32 hdrm_int_buff_cells_for_olp_port; /* C135 */ 386 uint32 hdrm_ema_buff_cells_for_olp_port; /* C136 */ 387 uint32 hdrm_ext_buff_cells_for_olp_port; /* C137 */ 388 uint32 hdrm_RE_WQEs_pkts_for_olp_port; /* C138 */ 389 uint32 hdrm_EQEs_pkts_for_olp_port; /* C139 */ 390 391 uint32 hdrm_int_buff_cells_for_lpbk_port; /* C140 */ 392 uint32 hdrm_ema_buff_cells_for_lpbk_port; /* C141 */ 393 uint32 hdrm_ext_buff_cells_for_lpbk_port; /* C142 */ 394 uint32 hdrm_RE_WQEs_pkts_for_lpbk_port; /* C143 */ 395 uint32 hdrm_EQEs_pkts_for_lpbk_port; /* C144 */ 396 397 uint32 hdrm_int_buff_cells_for_cpu_port; /* C145 */ 398 uint32 hdrm_ema_buff_cells_for_cpu_port; /* C146 */ 399 uint32 hdrm_ext_buff_cells_for_cpu_port; /* C147 */ 400 uint32 hdrm_RE_WQEs_pkts_for_cpu_port; /* C148 */ 401 uint32 hdrm_EQEs_pkts_for_cpu_port; /* C149 */ 402 403 uint32 total_hdrm_int_buff_cells; /* C150 */ 404 uint32 total_hdrm_int_buff_ema_pool_cells; /* C151 */ 405 uint32 total_hdrm_ext_buff_cells; /* C152 */ 406 uint32 total_hdrm_RE_WQEs_pkts; /* C153 */ 407 uint32 total_hdrm_EQEs_pkts; /* C154 */ 408 409 uint32 min_int_buff_cells_per_PG; /* C156 */ 410 uint32 min_int_buff_ema_pool_cells_per_PG; /* C157 */ 411 uint32 min_ext_buff_cells_per_PG; /* C158 */ 412 uint32 min_RE_WQEs_pkt_per_PG; /* C159 */ 413 uint32 min_EQEs_pkt_per_PG; /* C160 */ 414 415 uint32 min_int_buff_cells_for_total_PG; /* C162 */ 416 uint32 min_int_buff_ema_pool_cells_for_total_PG; /* C163 */ 417 uint32 min_ext_buff_cells_for_total_PG; /* C164 */ 418 uint32 min_RE_WQEs_pkts_for_total_PG; /* C165 */ 419 uint32 min_EQEs_pkts_for_total_PG; /* C166 */ 420 421 uint32 min_int_buff_cells_for_a_port; /* C168 */ 422 uint32 min_int_buff_ema_pool_cells_for_a_port; /* C169 */ 423 uint32 min_ext_buff_cells_for_a_port; /* C170 */ 424 uint32 min_RE_WQEs_pkts_for_a_port; /* C171 */ 425 uint32 min_EQEs_pkts_for_a_port; /* C172 */ 426 427 uint32 min_int_buff_cells_for_total_port; /* C174 */ 428 uint32 min_int_buff_ema_pool_cells_for_total_port; /* C175 */ 429 uint32 min_ext_buff_cells_for_total_port; /* C176 */ 430 uint32 min_RE_WQEs_pkts_for_total_port; /* C177 */ 431 uint32 min_EQEs_pkts_for_total_port; /* C178 */ 432 433 uint32 total_min_int_buff_cells; /* C180 */ 434 uint32 total_min_int_buff_ema_pool_cells; /* C181 */ 435 uint32 total_min_ext_buff_cells; /* C182 */ 436 uint32 total_min_RE_WQEs_pkts; /* C183 */ 437 uint32 total_min_EQEs_pkts; /* C184 */ 438 439 uint32 total_shared_ing_buff_pool; /* C186 */ 440 uint32 total_shared_EMA_buff; /* C187 */ 441 uint32 total_shared_ext_buff; /* C188 */ 442 uint32 total_shared_RE_WQEs_buff; /* C189 */ 443 uint32 total_shared_EQEs_buff; /* C190 */ 444 445 uint32 ingress_burst_cells_size_for_one_port; /* C192 */ 446 uint32 ingress_burst_pkts_size_for_one_port; /* C193 */ 447 uint32 ingress_burst_cells_size_for_all_ports; /* C194 */ 448 uint32 ingress_total_shared_cells_use_for_all_port; /* C195 */ 449 uint32 ingress_burst_pkts_size_for_all_port; /* C196 */ 450 uint32 ingress_total_shared_pkts_use_for_all_port; /* C197 */ 451 uint32 ingress_total_shared_hdrm_cells_use_for_all_port; /* C198 */ 452 uint32 ingress_total_shared_hdrm_pkts_use_for_all_port; /* C199 */ 453 454 }_sb2_input_port_threshold_t; 455 456 typedef struct _sb2_output_port_threshold_s { 457 uint32 min_grntd_res_queue_cells_int_buff; /* C204 */ 458 uint32 min_grntd_res_queue_cells_ext_buff; /* C205 */ 459 uint32 min_grntd_res_queue_cells_EQEs; /* C206 */ 460 uint32 min_grntd_res_EMA_queue_cells; /* C207 */ 461 uint32 min_grntd_res_RE_WQs_cells; /* C208 */ 462 uint32 min_grntd_res_RE_WQs_queue_cells_for_int_buff; /* C209 */ 463 uint32 min_grntd_res_RE_WQs_queue_cells_for_ext_buff; /* C210 */ 464 uint32 min_grntd_res_EP_redirect_queue_entry_cells; /* C211 */ 465 466 uint32 min_grntd_tot_res_queue_cells_int_buff; /* C213 */ 467 uint32 min_grntd_tot_res_queue_cells_ext_buff; /* C214 */ 468 uint32 min_grntd_tot_res_queue_cells_EQEs; /* C215 */ 469 uint32 min_grntd_tot_res_EMA_queue_cells; /* C216 */ 470 uint32 min_grntd_tot_res_RE_WQs_cells; /* C217 */ 471 uint32 min_grntd_tot_res_RE_WQs_queue_cells_for_int_buff;/* C218 */ 472 uint32 min_grntd_tot_res_RE_WQs_queue_cells_for_ext_buff;/* C219 */ 473 uint32 min_grntd_tot_res_EP_redirect_queue_entry_cells; /* C220 */ 474 475 uint32 min_grntd_tot_shr_queue_cells_int_buff; /* C222 */ 476 uint32 min_grntd_tot_shr_queue_cells_ext_buff; /* C223 */ 477 uint32 min_grntd_tot_shr_queue_cells_EQEs; /* C224 */ 478 uint32 min_grntd_tot_shr_EMA_queue_cells; /* C225 */ 479 uint32 min_grntd_tot_shr_RE_WQs_cells; /* C226 */ 480 uint32 min_grntd_tot_shr_RE_WQs_queue_cells_for_int_buff;/* C227 */ 481 uint32 min_grntd_tot_shr_RE_WQs_queue_cells_for_ext_buff;/* C228 */ 482 uint32 min_grntd_tot_shr_EP_redirect_queue_entry_cells; /* C229 */ 483 484 uint32 egress_queue_dynamic_threshold_parameter; /* C230 */ 485 uint32 egress_burst_cells_size_for_one_queue; /* C231 */ 486 uint32 egress_burst_pkts_size_for_one_queue; /* C232 */ 487 uint32 egress_burst_cells_size_for_all_ports; /* C233 */ 488 uint32 egress_burst_pkts_size_for_all_ports; /* C234 */ 489 uint32 egress_burst_cells_size_for_all_queues; /* C235 */ 490 uint32 egress_burst_pkts_size_for_all_queues; /* C236 */ 491 uint32 egress_total_use_in_cells_for_all_queues; /* C237 */ 492 uint32 egress_total_use_in_pkts_for_all_queues; /* C238 */ 493 uint32 egress_remaining_cells_for_all_queues; /* C239 */ 494 uint32 egress_remaining_pkts_for_all_queues; /* C240 */ 495 496 }_sb2_output_port_threshold_t; 497 498 typedef struct _soc_sb2_mmu_intermediate_results_s { 499 _sb2_general_info_t general_info; 500 _sb2_input_port_threshold_t input_port_threshold; 501 _sb2_output_port_threshold_t output_port_threshold; 502 }_soc_sb2_mmu_intermediate_results_t; 503 extern _soc_sb2_mmu_intermediate_results_t _soc_sb2_mmu_intermediate_results; 504 505 extern int soc_sb2_linkphy_port_reg_blk_idx_get( 506 int unit, int port, int blktype, int *block, int *index); 507 extern int soc_sb2_linkphy_port_blk_idx_get( 508 int unit, int port, int *block, int *index); 509 extern int soc_sb2_linkphy_get_portid(int unit, int block, int index); 510 511 extern void _saber2_phy_addr_default(int unit, int port, 512 uint16 *phy_addr, uint16 *phy_addr_int); 513 extern soc_error_t soc_saber2_get_mxq_phy_port_mode( 514 int unit, soc_port_t port,int speed, bcmMxqPhyPortMode_t *mode); 515 extern soc_error_t soc_saber2_get_xl_phy_core_port_mode( 516 int unit, soc_port_t port, bcmXlPhyPortMode_t *phy_mode, 517 bcmXlCorePortMode_t *core_mode); 518 519 extern int soc_sb2_iecell_port_reg_blk_idx_get( 520 int unit, int port, int blktype, int *block, int *index); 521 extern int soc_sb2_iecell_port_blk_idx_get( 522 int unit, int port, int *block, int *index); 523 extern int soc_sb2_iecell_get_portid(int unit, int block, int index); 524 extern soc_error_t soc_saber2_port_enable_set( 525 int unit, soc_port_t port, int enable); 526 extern soc_error_t soc_saber2_get_port_block( 527 int unit, soc_port_t port,uint8 *block); 528 529 extern soc_functions_t soc_saber2_drv_funs; 530 extern int 531 soc_saber2_num_cosq_init(int unit); 532 extern int soc_sb2_dump_default_mmu(int unit); 533 extern int soc_sb2_mem_config(int unit, int dev_id); 534 extern int _soc_saber2_mmu_reconfigure(int unit, int port); 535 536 extern void soc_saber2_pbmp_init(int unit, sb2_pbmp_t sb2_pbmp); 537 extern void soc_saber2_subport_init(int unit); 538 extern void soc_saber2_block_reset(int unit, uint8 block,int active_low); 539 extern void soc_saber2_save_tdm_pos(int unit, uint32 new_tdm_size,uint32 *new_tdm); 540 extern soc_error_t soc_saber2_reconfigure_tdm(int unit,uint32 new_tdm_size,uint32 *new_tdm); 541 542 extern int _soc_saber2_flexio_scache_allocate(int unit); 543 extern int _soc_saber2_flexio_scache_retrieve(int unit); 544 extern int _soc_saber2_flexio_scache_sync(int unit); 545 546 extern int soc_sb2_temperature_monitor_get(int unit, 547 int temperature_max, 548 soc_switch_temperature_monitor_t *temperature_array, 549 int *temperature_count); 550 extern int soc_sb2_show_voltage(int unit); 551 extern int _soc_saber2_hw_reset_control_init(int unit); 552 553 #define SB2_TDM_MAX_SIZE 284 554 555 #define SB2_MAX_BLOCKS 7 556 #define SB2_MAX_PORTS_PER_BLOCK 4 557 558 #define SB2_MAX_LOGICAL_PORTS 30 559 #define SB2_MAX_PHYSICAL_PORTS 28 560 561 #define SB2_LPBK 29 562 #define SB2_CMIC 0 563 #define SB2_IDLE SB2_MAX_LOGICAL_PORTS 564 565 #define SB2_PORT_MAC_MAX 96 566 567 #define SB2_MAX_SERVICE_POOLS 4 568 #define SB2_MAX_PRIORITY_GROUPS 8 569 570 571 #define SOC_SB2_MIN_SUBPORT_INDEX 30 572 #define SOC_SB2_MAX_SUBPORTS 64 573 #define SOC_SB2_MAX_LINKPHY_SUBPORTS 32 574 #define SOC_SB2_SUBPORT_GROUP_MAX SOC_SB2_MAX_SUBPORTS 575 #define SOC_SB2_SUBPORT_PP_PORT_INDEX_MIN SOC_SB2_MIN_SUBPORT_INDEX 576 #define SOC_SB2_SUBPORT_PP_PORT_INDEX_MAX (\ 577 SOC_SB2_SUBPORT_PP_PORT_INDEX_MIN + SOC_SB2_MAX_SUBPORTS - 1) 578 579 #define SOC_SB2_LINKPHY_TX_DATA_BUF_START_ADDR_MAX 3392 580 #define SOC_SB2_LINKPHY_TX_DATA_BUF_END_ADDR_MIN 31 581 #define SOC_SB2_LINKPHY_TX_DATA_BUF_END_ADDR_MAX 3423 582 #define SOC_SB2_LINKPHY_TX_STREAM_START_ADDR_OFFSET 0x80 583 584 /* Max 32 streams per linkphy port. 585 * So we can support max of 16 subports per linkphy port. 586 */ 587 #define SOC_SB2_MAX_LINKPHY_SUBPORTS_PER_PORT 32 588 #define SOC_SB2_MAX_LINKPHY_STREAMS_PER_PORT 32 589 #define SOC_SB2_MAX_STREAMS_PER_SLICE 32 590 #define SOC_SB2_MAX_STREAMS_PER_SUBPORT BCM_SUBPORT_CONFIG_MAX_STREAMS 591 592 #define SOC_SB2_LINKPHY_BLOCK_MAX 1 593 #define SOC_SB2_MAX_LINKPHY_PORTS 4 594 595 /* Configs for BCM56460,461,465, 466 */ 596 #define BCM56460_DEVICE_ID_OFFSET_CFG 0 597 #define BCM56460_DEVICE_ID_DEFAULT_CFG 1 598 #define BCM56460_DEVICE_ID_MAX_CFG 6 599 600 /* Configs for BCM56462,467 */ 601 #define BCM56462_DEVICE_ID_OFFSET_CFG 6 602 #define BCM56462_DEVICE_ID_DEFAULT_CFG 7 603 #define BCM56462_DEVICE_ID_MAX_CFG 8 604 605 /* Configs for BCM56463,468 */ 606 #define BCM56463_DEVICE_ID_OFFSET_CFG 8 607 #define BCM56463_DEVICE_ID_DEFAULT_CFG 9 608 #define BCM56463_DEVICE_ID_MAX_CFG 11 609 610 /* Configs for BCM56260,261,265,266 */ 611 #define BCM56260_DEVICE_ID_OFFSET_CFG 11 612 #define BCM56260_DEVICE_ID_DEFAULT_CFG 12 613 #define BCM56260_DEVICE_ID_MAX_CFG 13 614 615 /* Configs for BCM56262,267 */ 616 #define BCM56262_DEVICE_ID_OFFSET_CFG 13 617 #define BCM56262_DEVICE_ID_DEFAULT_CFG 14 618 #define BCM56262_DEVICE_ID_MAX_CFG 14 619 620 /* Configs for BCM56263,268 */ 621 #define BCM56263_DEVICE_ID_OFFSET_CFG 14 622 #define BCM56263_DEVICE_ID_DEFAULT_CFG 15 623 #define BCM56263_DEVICE_ID_MAX_CFG 16 624 625 /* Configs for BCM56233 */ 626 #define BCM56233_DEVICE_ID_OFFSET_CFG 16 627 #define BCM56233_DEVICE_ID_DEFAULT_CFG 17 628 #define BCM56233_DEVICE_ID_MAX_CFG 17 629 630 /* SAT port for Saber2 */ 631 #define SOC_SB2_SAT_OAMP_PHY_PORT_NUMBER 5 632 633 /* Max CoE modules */ 634 #define SOC_SB2_MAX_COE_MODULES 3 635 636 typedef uint32 sb2_port_speeds_t[SB2_MAX_BLOCKS][SB2_MAX_PORTS_PER_BLOCK]; 637 typedef uint32 sb2_block_ports_t[SB2_MAX_BLOCKS][SB2_MAX_PORTS_PER_BLOCK]; 638 639 typedef uint32 sb2_speed_t[SB2_MAX_PHYSICAL_PORTS]; 640 typedef uint32 sb2_port_to_block_t[SB2_MAX_PHYSICAL_PORTS]; 641 typedef uint32 sb2_port_to_block_subports_t[SB2_MAX_PHYSICAL_PORTS]; 642 643 extern sb2_block_ports_t *sb2_block_ports[SOC_MAX_NUM_DEVICES]; 644 extern sb2_port_speeds_t *sb2_port_speeds[SOC_MAX_NUM_DEVICES]; 645 646 extern uint32 sb2_current_tdm[SB2_TDM_MAX_SIZE]; 647 extern uint32 sb2_current_tdm_size; 648 extern uint8 sb2_tdm_update_flag; 649 extern sb2_tdm_pos_info_t sb2_tdm_pos_info[SB2_MAX_BLOCKS]; 650 651 #ifdef INCLUDE_AVS 652 extern int soc_saber2_avs_init(int unit); 653 #endif /* INCLUDE_AVS */ 654 extern int soc_saber2_and28_info_config(int unit, soc_sb2_and28_info_t *drc_info, 655 and28_shmoo_dram_info_t *sdi); 656 extern int soc_sb2_and28_dram_init_reset(int unit); 657 extern int soc_sb2_and28_dram_init_config(int unit); 658 extern int soc_sb2_and28_dram_savecfg(int unit, and28_shmoo_config_param_t *config_param); 659 extern int soc_sb2_and28_dram_restorecfg(int unit, and28_shmoo_config_param_t *config_param); 660 extern int soc_saber2_hw_reset_control_init(int unit); 661 extern int soc_saber2_ser_init(int unit,int enable); 662 extern soc_error_t soc_saber2_mem_parity_control(int unit, soc_mem_t mem, int copyno, int enable); 663 extern soc_error_t soc_saber2_ser_mem_clear(int unit, soc_mem_t mem); 664 665 extern int soc_sb2_cosq_max_bucket_set(int unit, int port, 666 int index, uint32 level); 667 extern int 668 soc_sb2_cosq_min_bucket_get(int unit, int port, int index, int level, 669 uint32 *min_quantum, uint32 *mantissa, 670 uint32 *exp, uint32 *cycle); 671 extern int soc_sb2_cosq_min_clear (int unit, int port, 672 int index, uint32 level); 673 674 extern int 675 soc_katana_compute_shaper_rate(int unit, uint32 rate_mantissa, 676 uint32 rate_exponent, uint32 *rate); 677 678 extern int 679 _soc_ddr_sb2_phy_freqtoloc(uint32 freq); 680 extern int soc_saber2_xl_port_speed_get(int unit, int port, int *speed); 681 int 682 soc_sb2_mmu_config_shared_buf_recalc(int unit, int delta_size, bcm_kt2_cosq_recalc_type_t flags); 683 extern void soc_sb2_xport_type_update(int unit, soc_port_t port, int mode); 684 685 #define BCM_SB2_COSQ_FLEX_COUNT_SUPPORTED 3 686 #define BCM_SB2_COSQ_FLEX_COUNT_REGS 6 687 #define BCM_SB2_COSQ_WRED_DROP_MASK 0x037f 688 #define BCM_SB2_COSQ_TOTAL_DROP_MASK 0x0000 689 #define BCM_SB2_COSQ_DEFAULT_DROP_MASK 0x03ff 690 #define BCM_SB2_COSQ_CHECK_STAT_TYPE(drop_type,type) (drop_type ^ type) 691 692 extern void soc_sb2_cosq_counter_mem_map_get(int unit, int *num_elem, _sb2_cosq_counter_mem_map_t **mem_map); 693 extern int soc_saber2_perq_flex_counters_init(int unit, uint32 drop_mask); 694 695 #define SABER2_5626X_NGROUPS_FP 32 696 #define SABER2_5626X_NPORTS_FP 4 697 #define SABER2_5626X_NGROUPS_HG 4 698 #define SABER2_5626X_NPORTS_HG 4 699 700 extern int soc_sb2_5626x_devtype (int unit); 701 int 702 _soc_saber2_mdio_reg_read(int unit, uint32 phy_addr, 703 uint32 phy_reg, uint32 *phy_data); 704 int 705 _soc_saber2_tsce_firmware_set(int unit, int port, uint8 *array, int datalen); 706 int 707 _soc_saber2_mdio_reg_write(int unit, uint32 phy_addr, 708 uint32 phy_reg, uint32 phy_data); 709 int 710 soc_saber2_port_is_unused(int unit, int port_no); 711 extern int 712 soc_sb2_get_max_buffer_size(int unit, int external, int value); 713 extern void 714 soc_sb2_get_queue_min_size(int unit, int *internal_size, int *external_size); 715 #endif /* !_SOC_SABER2_H_ */