openbcm

property.h (497899B)

---

 /*
  * 
  * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file.
  * 
  * Copyright 2007-2019 Broadcom Inc. All rights reserved.
  * 
  * SOC Property Names (Autogenerated)
  * 
  * DO NOT EDIT THIS FILE. Your changes will be lost
  */
 #ifndef _SOC_PROPERTY_H
 #define _SOC_PROPERTY_H
 
 
 /*
  * Station MAC address used for management through the switch ports
  * itself. If using the CPU network interface, the NVRAM setting is used
  * for MAC address assignment.
  */
 #define spn_STATION_MAC_ADDRESS  "station_mac_address"
 /*
  * Enable polled IRQ mode (useful for board bringup and debugging).
  * IRQs will be polled from a dedicated thread and hardware interrupts
  * will remain disabled.
  */
 #define spn_POLLED_IRQ_MODE  "polled_irq_mode"
 /*
  * The priority of the IRQ poll thread as well as the minimum delay
  * between IRQ polls can be configured if needed.
  */
 #define spn_POLLED_IRQ_DELAY  "polled_irq_delay"
 /*
  * The priority of the IRQ poll thread as well as the minimum delay
  * between IRQ polls can be configured if needed.
  */
 #define spn_POLLED_IRQ_PRIORITY  "polled_irq_priority"
 /*
  * Allow filtering to be disabled in hardware if not being used.
  * Also, tables will not be cleared which can save time in simulation.
  */
 #define spn_FILTER_ENABLE  "filter_enable"
 
 /* Initial number of CoS queues bcm_init() configures the chip for. */
 #define spn_BCM_NUM_COS  "bcm_num_cos"
 
 /* Clear the filter table for 10/100Mb ports during initialization */
 #define spn_BCM_FILTER_CLEAR_FE  "bcm_filter_clear_fe"
 
 /* Clear the filter table for 1000Mb ports during initialization */
 #define spn_BCM_FILTER_CLEAR_GE  "bcm_filter_clear_ge"
 
 /* Clear the filter table for 10GE ports during initialization */
 #define spn_BCM_FILTER_CLEAR_XE  "bcm_filter_clear_xe"
 /*
  * Linkscan:
  * Specify ports on which bcm_init will run linkscan (default all).
  */
 #define spn_BCM_LINKSCAN_PBMP  "bcm_linkscan_pbmp"
 /*
  * Linkscan interval in microseconds.
  * If non-zero, bcm_init() will start linkscan
  */
 #define spn_BCM_LINKSCAN_INTERVAL  "bcm_linkscan_interval"
 /*
  * The number of port update errors which will cause the bcm_linkscan module
  * to suspend a port from update processing for the period of time set in
  * "bcm_linkscan_errdelay".
  */
 #define spn_BCM_LINKSCAN_MAXERR  "bcm_linkscan_maxerr"
 /*
  * The amount of time in microseconds for which the bcm_linkscan module
  * will suspend a port from further update processing after
  * "bcm_linkscan_maxerr" errors are detected.  After this delay, the
  * error state for the port is cleared and normal linkscan processing
  *  resumes on the port.
  */
 #define spn_BCM_LINKSCAN_ERRDELAY  "bcm_linkscan_errdelay"
 /*
  * BCM Statistics Collection:
  * Set bitmap of ports on which stat collection will be enabled.
  * Default is all ports.
  */
 #define spn_BCM_STAT_PBMP  "bcm_stat_pbmp"
 /*
  * INT per port metadata collection:
  * Set bitmap of ports for which link metadata collection will be enabled in the uKernel.
  */
 #define spn_INT_LINK_METADATA_PBMP  "int_link_metadata_pbmp"
 /*
  * Set stat collection interval in microseconds.
  * Setting this to 0 will prevent counters from being started.
  */
 #define spn_BCM_STAT_INTERVAL  "bcm_stat_interval"
 
 /* Timeout delay in microseconds before bcm_stat_sync returns BCM_E_TIMEOUT */
 #define spn_BCM_STAT_SYNC_TIMEOUT  "bcm_stat_sync_timeout"
 /*
  * Flag values to be ORd together:
  *    0x0 indicates that counter DMA should NOT be used
  *    0x1 indicates that counter DMA should be used (default).
  */
 #define spn_BCM_STAT_FLAGS  "bcm_stat_flags"
 /*
  * Threshold value for oversize (*OVR) frame size.
  * Values over 1518 affect the *OVR statistics computation
  */
 #define spn_BCM_STAT_JUMBO  "bcm_stat_jumbo"
 
 /* Selection of recovery clock lane for CAUI port. values: 0-3 */
 #define spn_CAUI_RX_CLOCK_RECOVERY_LANE  "caui_rx_clock_recovery_lane"
 
 /* Specified if port use 1 Byte preamble */
 #define spn_PREAMBLE_SOP_ONLY  "preamble_sop_only"
 
 /* Specifies the priority of the BCM TX thread */
 #define spn_BCM_TX_THREAD_PRI  "bcm_tx_thread_pri"
 
 /* Specifies the priority of the BCM RX thread */
 #define spn_BCM_RX_THREAD_PRI  "bcm_rx_thread_pri"
 /*
  * Specifies number of packets for BCM RX buffer allocation.
  * This is equal to number of channels x chains per channel x
  * descriptors per chain. For multi unit systems, the
  * resulting value needs to be multiplied by number of units.
  */
 #define spn_RX_POOL_NOF_PKTS  "rx_pool_nof_pkts"
 
 /* Specifies the priority of the BCM Linkscan thread */
 #define spn_LINKSCAN_THREAD_PRI  "linkscan_thread_pri"
 
 /* Specifies the priority of the BCM Portmon thread */
 #define spn_PORTMON_THREAD_PRI  "portmon_thread_pri"
 
 /* Specifies the priority of the bcm_bst_sync_thread */
 #define spn_BST_SYNC_THREAD_PRI  "bst_sync_thread_pri"
 
 /* Specifies the priority of the bcmBHH thread */
 #define spn_BHH_THREAD_PRI  "bhh_thread_pri"
 
 /* Specifies the priority of the bcmIbodSync thread */
 #define spn_IBOD_SYNC_THREAD_PRI  "ibod_sync_thread_pri"
 
 /* Specifies the priority of the bcmFtExportDma thread */
 #define spn_BCM_FT_REPORT_THREAD_PRI  "bcm_ft_report_thread_pri"
 
 /* Specifies the priority of the bcmBFD thread */
 #define spn_BFD_THREAD_PRI  "bfd_thread_pri"
 
 /* Specifies the priority of the dma monitor thread thread(bcmDmaIntrM) */
 #define spn_SOC_DMA_MONITOR_THREAD_PRI  "soc_dma_monitor_thread_pri"
 
 /* Specifies the priority of the SOC KNET RX thread */
 #define spn_SOC_KNET_RX_THREAD_PRI  "soc_knet_rx_thread_pri"
 
 /* Specifies the priority of the bcmPSCAN thread */
 #define spn_BCM_ESW_PSCAN_THREAD_PRI  "bcm_esw_pscan_thread_pri"
 
 /* Specifies the priority of the socdmadesc thread */
 #define spn_SBUS_DMA_DESC_THREAD_PRI  "sbus_dma_desc_thread_pri"
 
 /* Specifies the priority of the esm_recovery thread */
 #define spn_ESM_RECOVERY_THREAD_PRI  "esm_recovery_thread_pri"
 
 /* Packet DMA abort timeout */
 #define spn_PDMA_TIMEOUT_USEC  "pdma_timeout_usec"
 
 /* Counter DMA collection pass timeout in microseconds */
 #define spn_CDMA_TIMEOUT_USEC  "cdma_timeout_usec"
 /*
  * Manually collect the HOLD register in the counter DMA thread on
  * BCM568xx and BCM567xx devices.
  */
 #define spn_CDMA_PIO_HOLD_ENABLE  "cdma_pio_hold_enable"
 
 /* Table DMA operation timeout in microseconds */
 #define spn_TDMA_TIMEOUT_USEC  "tdma_timeout_usec"
 
 /* Table DMA operation should use interrupt rather than poll for completion */
 #define spn_TDMA_INTR_ENABLE  "tdma_intr_enable"
 
 /* Table SLAM DMA operation timeout in microseconds */
 #define spn_TSLAM_TIMEOUT_USEC  "tslam_timeout_usec"
 
 /* Table SLAM DMA operation should use interrupt rather than poll for completion */
 #define spn_TSLAM_INTR_ENABLE  "tslam_intr_enable"
 
 /* SCHAN FIFO operation timeout in microseconds */
 #define spn_SCHANFIFO_TIMEOUT_USEC  "schanfifo_timeout_usec"
 
 /* SCHAN FIFO operation should use interrupt rather than poll for completion */
 #define spn_SCHANFIFO_INTR_ENABLE  "schanfifo_intr_enable"
 
 /* CCM DMA operation timeout in microseconds */
 #define spn_CCMDMA_TIMEOUT_USEC  "ccmdma_timeout_usec"
 
 /* CCM DMA operation should use interrupt rather than poll for completion */
 #define spn_CCMDMA_INTR_ENABLE  "ccmdma_intr_enable"
 
 /* SBUSDMA descriptor mode operation timeout in microseconds */
 #define spn_DMA_DESC_TIMEOUT_USEC  "dma_desc_timeout_usec"
 
 /* timeout for DMA abort (of all DMA types) in microseconds */
 #define spn_DMA_ABORT_TIMEOUT_USEC  "dma_abort_timeout_usec"
 
 /* SBUSDMA descriptor mode operation should use interrupt rather than poll for completion */
 #define spn_DMA_DESC_INTR_ENABLE  "dma_desc_intr_enable"
 
 /* Packet DMA interrupts should be mitigated to improve performance */
 #define spn_DCB_INTR_MITIGATE_ENABLE  "dcb_intr_mitigate_enable"
 /*
  * Maximum number of consecutive S-channel errors the counter collection
  * code will tolerate before the counter thread gives up and exits.
  */
 #define spn_SOC_CTR_MAXERR  "soc_ctr_maxerr"
 /*
  * stat info will include the specific priotity and higher priorities
  * possible values: LOW_LEVEL, MEDIUM_LEVEL, HIGH_LEVEL.
  */
 #define spn_SOC_COUNTER_CONTROL_LEVEL  "soc_counter_control_level"
 /*
  * Skip hardware reset (CMIC_CONFIG.RESET_CPS) when calling soc_reset().
  * This means that e.g. 'init soc' will NOT perform a hard reset.
  */
 #define spn_SOC_SKIP_RESET  "soc_skip_reset"
 
 /* Miscellaneous thread priorities; 0 is highest and 255 is lowest */
 #define spn_COUNTER_THREAD_PRI  "counter_thread_pri"
 
 /* Miscellaneous thread priorities; 0 is highest and 255 is lowest */
 #define spn_COUNTER_EVICT_THREAD_PRI  "counter_evict_thread_pri"
 
 /* Number of entries in host buffer used for FIFO DMA in counter eviction */
 #define spn_COUNTER_EVICT_HOSTBUF_SIZE  "counter_evict_hostbuf_size"
 
 /* Number of entries in host buffer after which eviction thread should yield */
 #define spn_COUNTER_EVICT_ENTRIES_MAX  "counter_evict_entries_max"
 
 /* Check callback return code and abort on error. */
 #define spn_CB_ABORT_ON_ERR  "cb_abort_on_err"
 /*
  * When a link goes down for any reason, the driver waits for all packets
  * to that port to drain from the MMU before continuing.  There is a
  * timeout in case the packet count is non-zero AND non-decrementing.
  * This is only for devices with UniMAC and TriMAC.
  */
 #define spn_LCCDRAIN_TIMEOUT_USEC  "lccdrain_timeout_usec"
 #define spn_SOC_SCOREBOARD_ENABLE  "soc_scoreboard_enable"
 #define spn_SOC_SCOREBOARD_INTERVAL  "soc_scoreboard_interval"
 
 /* L3 switching enable */
 #define spn_L3_ENABLE  "l3_enable"
 
 /* IMPC switching enable */
 #define spn_IPMC_ENABLE  "ipmc_enable"
 
 /* Include the VLAN as part of the hash key for L3 IPMC */
 #define spn_IPMC_DO_VLAN  "ipmc_do_vlan"
 /*
  * Enable broadcast domain (VLAN/VPN) hash keys lookup for L2 IPMC
  * In absence of this config the device loopkup IPMC multicast table
  * based on L3 ingress interface.
  */
 #define spn_IPMC_L2_USE_VLAN_VPN  "ipmc_l2_use_vlan_vpn"
 
 /* EXTEND maximum number of front panel trunk groups  from 32 to 128 */
 #define spn_TRUNK_EXTEND  "trunk_extend"
 /*
  * Delay this long after an ARL message overrun before a lengthy ARL-
  * resync process.  Setting to 0 to disables resync, in peril of getting
  * an inconsistent ARL message stream and/or corrupt L2 shadow table.
  */
 #define spn_ARL_RESYNC_DELAY  "arl_resync_delay"
 
 /* Enable L2X shadowing into AVL tree. */
 #define spn_L2XMSG_AVL  "l2xmsg_avl"
 /*
  * Mode control to select L2 Table DMA mode aka L2MODE_POLL (0) or
  * L2MOD_FIFO mechanism aka L2MODE_FIFO (1) for L2 table change notification.
  */
 #define spn_L2XMSG_MODE  "l2xmsg_mode"
 /*
  * Priority of the _soc_l2x_thread, that is used to synchronize
  * shadow copy of the L2 entry with the HW table
  */
 #define spn_L2XMSG_THREAD_PRI  "l2xmsg_thread_pri"
 /*
  * Period between synchronizations of the software L2X shadow table
  * with the hardware (5690 only).  The thread actually runs every
  * l2xmsg_thread_usec/l2xmsg_chunks microseconds.
  */
 #define spn_L2XMSG_THREAD_USEC  "l2xmsg_thread_usec"
 /*
  * The l2xmsg thread will call back to the user any time an L2X address
  * is added, removed, or changed.  However, if only the hit bit changes,
  * it will not call back unless l2xmsg_shadow_hit_bits is set to 1.
  */
 #define spn_L2XMSG_SHADOW_HIT_BITS  "l2xmsg_shadow_hit_bits"
 /*
  * The l2xmsg thread will call back to the user any time an L2X address
  * is added, removed, or changed.  However, if only the source hit bit changes,
  * it will not call back unless l2xmsg_shadow_hit_bits is set to 0 and
  * l2xmsg_shadow_hit_src is set to 1.
  */
 #define spn_L2XMSG_SHADOW_HIT_SRC  "l2xmsg_shadow_hit_src"
 /*
  * The l2xmsg thread will call back to the user any time an L2X address
  * is added, removed, or changed.  However, if only the destination hit bit changes,
  * it will not call back unless l2xmsg_shadow_hit_bits is set to 0 and
  * l2xmsg_shadow_hit_dst is set to 1.
  */
 #define spn_L2XMSG_SHADOW_HIT_DST  "l2xmsg_shadow_hit_dst"
 /*
  * Synchronize the L2X table in chunks to spread out the work over
  * time and save memory on size of DMA buffer.  Must be power of 2.
  */
 #define spn_L2XMSG_CHUNKS  "l2xmsg_chunks"
 
 /* Size of the buffer that is used to drain L2 FIFO when working in the L2 FIFO mode */
 #define spn_L2XMSG_HOSTBUF_SIZE  "l2xmsg_hostbuf_size"
 /*
  * Timeout for hardware-accelerated ARL delete operations including:
  * delete by port, delete by port+modid, delete by VLAN, delete by trunk.
  */
 #define spn_ARL_CLEAN_TIMEOUT_USEC  "arl_clean_timeout_usec"
 
 /* Specifies the priority of the memory scanning and error correction thread */
 #define spn_MEM_SCAN_THREAD_PRI  "mem_scan_thread_pri"
 /*
  * Specifies the number of table entries to be retrieved at a time
  * during memory scanning.
  */
 #define spn_MEM_SCAN_CHUNK_SIZE  "mem_scan_chunk_size"
 
 /* Control to automatically run background memory scan. */
 #define spn_MEM_SCAN_ENABLE  "mem_scan_enable"
 
 /* Specifies the memory scan rate in terms of entries per pass. */
 #define spn_MEM_SCAN_RATE  "mem_scan_rate"
 
 /* Specifies the memory scan repeat interval. */
 #define spn_MEM_SCAN_INTERVAL  "mem_scan_interval"
 
 /* Specifies how many non-TCAM cycles to perform for every complete TCAM sweep in memscan. */
 #define spn_MEM_SCAN_NON_TCAM_ITERATIONS  "mem_scan_non_tcam_iterations"
 
 /* Specifies the priority of the sram scanning and error correction thread */
 #define spn_SRAM_SCAN_THREAD_PRI  "sram_scan_thread_pri"
 /*
  * Specifies the number of table entries to be retrieved at a time
  * during sram scanning.
  */
 #define spn_SRAM_SCAN_CHUNK_SIZE  "sram_scan_chunk_size"
 
 /* Control to automatically run background sram scan. */
 #define spn_SRAM_SCAN_ENABLE  "sram_scan_enable"
 
 /* Specifies the sram scan rate in terms of entries per pass. */
 #define spn_SRAM_SCAN_RATE  "sram_scan_rate"
 
 /* Specifies the sram scan repeat interval. */
 #define spn_SRAM_SCAN_INTERVAL  "sram_scan_interval"
 /*
  * S-Channel operation timeout in microseconds.  Note that ARL
  * insert/delete messages can take a while if the ARL is highly active.
  */
 #define spn_SCHAN_TIMEOUT_USEC  "schan_timeout_usec"
 
 /* MIIM operation timeout in microseconds */
 #define spn_MIIM_TIMEOUT_USEC  "miim_timeout_usec"
 
 /* Memory Built-In-Self-Test (BIST) timeout in milliseconds */
 #define spn_BIST_TIMEOUT_MSEC  "bist_timeout_msec"
 /*
  * Normally, the system will use polling for register/memory S-Channel
  * operations and interrupts for time-consuming operations such as ARL
  * insert/delete.  If this schan_intr_enable is set to 0, polling will be
  * used for ALL operations.
  */
 #define spn_SCHAN_INTR_ENABLE  "schan_intr_enable"
 /*
  * Length of time to block the S-Channel error interrupt after one occurs.
  * Prevents monopolizing the CPU (use 0 to disable any blocking).
  */
 #define spn_SCHAN_ERROR_BLOCK_USEC  "schan_error_block_usec"
 /*
  * If miim_intr_enable variable is set to 1, the system will use
  * interrupts for MII operations since they take a while (70 usec or so).
  * If this variable is set to 0, polling will be used for all MII
  * operations.
  */
 #define spn_MIIM_INTR_ENABLE  "miim_intr_enable"
 /*
  * Limit the number of ARL messages/sec the software will process, to
  * keep it from hogging the CPU.  Set to 0 to disable.
  * Does not apply to L2X shadow table (see l2xmsg_thread_usec instead).
  */
 #define spn_ARL_RATE_LIMIT  "arl_rate_limit"
 
 /* MMU SDRAM configuration */
 #define spn_MMU_SDRAM_ENABLE  "mmu_sdram_enable"
 /*
  * Diagnostics loopback (tr 17 through tr 24) timeout in seconds for
  * loopback packet reception
  */
 #define spn_DIAG_LB_PACKET_TIMEOUT  "diag_lb_packet_timeout"
 /*
  * Diagnostics loopback - if set to TRUE, all receive buffers are filled
  * with 0xdeadbeef before DMAing into them.  It is slow, but then you will
  * know if loopback miscompares are due to skipped PCI writes.
  */
 #define spn_DIAG_LB_FILL_RX  "diag_lb_fill_rx"
 
 /* Packet watcher thread priority */
 #define spn_DIAG_PW_THREAD_PRI  "diag_pw_thread_pri"
 /*
  * When set to >= 68, packet watcher will run in truncating mode,
  * allocating smaller Rx buffers and accepting oversized packets on
  * all Rx DMA channels.
  */
 #define spn_DIAG_PW_BUFFER_SIZE  "diag_pw_buffer_size"
 
 /* Select memory tests run by cfapinit (default MT_PAT_FIVES and MT_PAT_AS) */
 #define spn_CFAP_TESTS  "cfap_tests"
 /*
  * If phy_enable is set to 0, all ports will use the null PHY driver.
  * This is useful for simulations on Quickturn.
  */
 #define spn_PHY_ENABLE  "phy_enable"
 /*
  * If phy_null_<port> is set to 1, the port will use the null PHY driver.
  * This is useful for configuring direct-connect GMII links such as the
  * chip-to-chip links on a 48-port board (example shown for 48 port board).
  */
 #define spn_PHY_NULL  "phy_null"
 
 /* If phy_simul_<port> is set to 1, the port will use the simulation. */
 #define spn_PHY_SIMUL  "phy_simul"
 
 /* Fiber vs. copper autodetection enable. */
 #define spn_PHY_AUTOMEDIUM  "phy_automedium"
 /*
  * Fiber vs. copper preference
  * When automedium is enabled, phy_fiber_pref indicates which medium to
  * prefer if BOTH are active.  Selects fiber (1) or copper (0).
  * When automedium is disabled, phy_fiber_pref indicates which medium to
  * use.  Selects fiber (1) or copper (0).
  */
 #define spn_PHY_FIBER_PREF  "phy_fiber_pref"
 /*
  *  Fiber de-glitch: some GBICs may cause a brief fiber energy detect
  *  when inserted, even without a link.  This could cause the copper link
  *  to be dropped, so an energy detect de-glitch is provided.  The
  *  phy_fiber_deglitch_usecs is the de-glitch time in usec. This is
  *  only applied to BCM5421S PHY device.
  */
 #define spn_PHY_FIBER_DEGLITCH_USECS  "phy_fiber_deglitch_usecs"
 
 /* Per-port parameter on maximum time to wait for PHY autoneg busy condition. */
 #define spn_PHY_AUTONEG_TIMEOUT  "phy_autoneg_timeout"
 #define spn_PHY_SERDES  "phy_serdes"
 /*
  * Serdes Autonegotiation configuration
  * This per-port parameter specifies what will happen if autonegotiation is
  * on but the remote partner is not autonegotiating.  If the value is zero,
  * we will not link.  If the value is non-zero, we will link.
  */
 #define spn_PHY_SERDES_AUTOS  "phy_serdes_autos"
 
 /* This specifies the external PHY device is BCM5464S. */
 #define spn_PHY_5464S  "phy_5464S"
 
 /* This specifies the external PHY device is BCM5690. */
 #define spn_PHY_5690  "phy_5690"
 
 /* This specifies the external PHY device is BCM8706 and equivalent. */
 #define spn_PHY_8706  "phy_8706"
 
 /* This specifies the external PHY device is BCM8072 and equivalent. */
 #define spn_PHY_8072  "phy_8072"
 
 /* This specifies the external PHY device is BCM84740. */
 #define spn_PHY_84740  "phy_84740"
 
 /* This specifies the external PHY device is BCM84752. */
 #define spn_PHY_84752  "phy_84752"
 
 /* This specifies the external PHY device is BCM84753. */
 #define spn_PHY_84753  "phy_84753"
 
 /* This specifies the external PHY device is BCM84754. */
 #define spn_PHY_84754  "phy_84754"
 
 /* This specifies the external PHY device is BCM84064. */
 #define spn_PHY_84064  "phy_84064"
 
 /* This specifies the position of external phy in the phy chain. */
 #define spn_PHY_CHAIN_LENGTH  "phy_chain_length"
 
 /* This specifies the primary core number to which it belongs to. */
 #define spn_XPHY_PRIMARY_CORE_NUM  "xphy_primary_core_num"
 
 /* This specifies the position of external phy in the phy chain.
                         For Recent PHY devices, logical ports can  span across multiple cores
                         These cores could be connected to multi-core external PHYs or Single core multi-lane external PHYs
                         This presents complex topology options.
                         Here is the format of the new config variable:
                         Format1: phy_topology_pport_xphyId=mdio-addr:sys_lane:line_lane
                         Format2: phy_topology_pport_xphyId_mapX=mdio-addr:sys_lane:line_lane
                                  where:
                                   pport = physical port number
                                   xphyId = position of the external PHY in the chain
                                   mdio_addr = mdio address of the external phy
                                   sys_lane = system side physical lane number
                                   line_lane = line side physical lane number
                                   mapX = index of lane mapping for specific pport and xphyId
                         The above mentioned config would help in figuring out the physical lane numbers associated with the logical port
                         to enable programming where there is no logical to logical lane mapping
                         Here is an example for format1 case that show multiple cores connected to a external phy and it corresponding topology config
                                               ________          ________
                                              |        |________|        |
                                              |        |        |        |
                                              |        |________|        |
                                              | CORE0  |        | EXTPHY |
                                              |        |________|        |
                                              |        |        |        |
                                              |        |________|        |
                                              |________|        |        |
                                                                |        |
                                                       Sys side |        |
                                               ________         |        |
                                              |        |        |        | Line side
                                              |        |\       |        |__________
                                              |        | \      |        |
                                              | CORE0  |\ \    /|        |__________
                                              |        | \ \  / |        |
                                              |        |\ \ \/ /|        |__________
                                              |        | \ \/\/ |        |
                                              |________|\ \/\/\/|        |__________
                                                         \/\/\/\|        |
                                               ________  /\/\/\ |        |
                                              |        |/ /\/\ \|        |
                                              |        | / /\ \ |        |
                                              |        |/ /  \ \|        |
                                              | CORE0  | /    \ | EXTPHY |
                                              |        |/      \|        |
                                              |        |        |        |
                                              |        |________|        |
                                              |________|        |________|
 
                                In the above image the physical lane swap crossed the core boundary on core1&2 and
                                there is no logical to logical mapping for  lanes 4 to 11 on the system side of ExtPhy
                                with the internal PHY. If the user wants to run the PRBS on logical lane 4
                                (on internal PHY core1 logical lane 0), the driver can query the DB
                                and get the necessary physical lane information (physical lane 8 in this case).
                         Here is an example for format2 case that show the mux mode that one core connects to a external phy and it corresponding topology config
                                                               ________
                                                              |        |
                                             ________         |        |__________
                                            |        |________|        |__________\
                                            |        |        |        |__________ - PORT1
                                            |        |________|        |__________/
                                            |        |        |        |
                                            |  CORE  |        | EXTPHY |
                                            |        |________|        |__________
                                            |        |        |        |__________\
                                            |        |________|        |__________ - PORT2
                                            |________|        |        |__________/
                                                              |        |
                                                              |________|
                                                     Sys side           Line side
 
                         In the above image, port1 and port2 map 4 line lanes and 2 system lines. There is no logical to logical mapping
                         for lanes 0 to 7 on the system side of ExtPhy with the internal PHY. Here is an example to describe the relation.
                         The format just describes the lane bitmap related with the port.
                         Port1:  mdio-addr is supposed to 0x10 and the first physical port is supposed to 0x8
                               phy_topology_8_1_map1=0x10:0:0
                               phy_topology_8_1_map2=0x10:0:1
                               phy_topology_9_1_map1=0x10:1:2
                               phy_topology_9_1_map2=0x10:1:3
                         Port2:
                               phy_topology_10_1_map1=0x10:1:4
                               phy_topology_10_1_map2=0x10:1:5
                               phy_topology_11_1_map1=0x10:1:6
                               phy_topology_11_1_map2=0x10:1:7 */
 #define spn_PHY_TOPOLOGY  "phy_topology"
 
 /* Specify the physical lane number corresponding to the logical lane0 . */
 #define spn_PHY_LANE0_L2P_MAP  "phy_lane0_l2p_map"
 
 /* This controls the clause 72  enable(1), disable(0). */
 #define spn_PHY_AN_C72  "phy_an_c72"
 
 /* This controls the clause 91(FEC) enable(2), the clause 74(FEC) enable(1), disable(0). */
 #define spn_PHY_AN_FEC  "phy_an_fec"
 /*
  * Advertise Clause 74 (or) Clause 91 Forward Error Correction (FEC) as part of Auto-Negotiation ability for external PHYs
  * 0 - Do not advertise FEC as Auto-Negotiation ability.
  * 1 - Advertise FEC CL74 as Auto-Negotiation ability.
  * 2 - Advertise FEC CL91 as Auto-Negotiation ability.
  */
 #define spn_PHY_EXT_AN_FEC  "phy_ext_an_fec"
 /*
  * This controls the clause 73 auto-negotiation.
  *  Disable cl73(0),
  *  Enable cl73_and_c73bam(1),
  *  Enable cl73_wo_c73bam(2),
  *  Enable cl73_and_MSA(3),
  *  Enable MSA_ONLY(4).
  *  Enable CL73_CL37(5).
  */
 #define spn_PHY_AN_C73  "phy_an_c73"
 /*
  * This controls the clause 37 auto-negotiation.
  *  Disable cl37(0),
  *  Enable cl37_and_c37bam(1),
  *  Enable cl37_wo_c37bam(2).
  */
 #define spn_PHY_AN_C37  "phy_an_c37"
 
 /* This controls if pll change allowed during AN  enable(1), disable(0). */
 #define spn_PHY_AN_ALLOW_PLL_CHANGE  "phy_an_allow_pll_change"
 /*
  * This config enables  TX FIFO RESET routine in Warpcore
  * firmware. The routine performs a targeted reset of the
  * tx_os8_fifo whenever the CL73 arbitration FSM enters
  * either the TX_DISABLE or the AN_GOOD_CHECK states.
  * When enabled this config applies to independent
  * channel mode when CL73 AN is enabled.
  * The config is relevant to Warpcore B0/C0/..
  * By default, the routine is disabled in firmware.
  */
 #define spn_SERDES_AN_C73_TX_FIFO_RESET_ENABLE  "serdes_an_c73_tx_fifo_reset_enable"
 /*
  * This controls whether to load the external ROM microcode to the
  *  applicable PHY devices, load(1), not load(0).
  */
 #define spn_PHY_EXT_ROM_BOOT  "phy_ext_rom_boot"
 /*
  * This controls whether to force firmware load during PHY init of
  *  applicable PHY devices, auto load (2) force load (1), may skip load(0)
  *  This is also used for specifying download method. Along with force(1)
  *  2nd nibble is used to specify firmware download method. Below are the values for
  *  firmware download methods
  *  0x01 Do not download the firmware
  *  0x11 force download the FW through MDIO
  *  0x21 force download(Flash) FW to EEPROM
  *  0x12 auto download the FW throgh MDIO if the version is not same as current one.
  */
 #define spn_PHY_FORCE_FIRMWARE_LOAD  "phy_force_firmware_load"
 /*
  * This indicates whether the long cable is used on the external PHY device
  *  with XFI interface, By default XFI cannot drive long distance cables.
  *  TX preemphasis needs to be adjusted if long cables are used on the XFI side.
  */
 #define spn_PHY_LONG_XFI  "phy_long_xfi"
 
 /* this controls half power mode for applicable PHY devices, enable(1), disable(0). */
 #define spn_PHY_HALF_POWER  "phy_half_power"
 /*
  * set BCM5488 family PHY to operate in class A/B low power mode.
  *  Accept value 0(lowest power) to 7(highest power).
  */
 #define spn_PHY_LOW_POWER_MODE  "phy_low_power_mode"
 
 /* indicate which port is the first port of the octal PHY. */
 #define spn_PHY_OCTAL_PORT_FIRST  "phy_octal_port_first"
 /*
  * Set the given XGXS control mode in independent channel mode for
  *  Hyperlite/Hypercore/Warpcore serdes. Valid value 4,5, and 6
  */
 #define spn_PHY_HL65_1LANE_MODE  "phy_hl65_1lane_mode"
 /*
  * Specify switch port on BCM8040. The switch port is the port
  *  connecting to MAC side device.
  */
 #define spn_PHY_8040_SWITCH_PORT  "phy_8040_switch_port"
 
 /* Specify mux port0 on BCM8040. A mux port will connect to another PHY device. */
 #define spn_PHY_8040_MUX_PORT0  "phy_8040_mux_port0"
 
 /* Specify mux port1 on BCM8040. A mux port will connect to another PHY device. */
 #define spn_PHY_8040_MUX_PORT1  "phy_8040_mux_port1"
 /*
  * Specify mux port2 on BCM8040. A mux port will connect to another PHY device.
  * The port is treated as invalid if there is no PHY device connecting to
  */
 #define spn_PHY_8040_MUX_PORT2  "phy_8040_mux_port2"
 
 /* Specify 53314 PHY device operating frequency as 156.25MHz. */
 #define spn_PHY_53314_CLK156  "phy_53314_clk156"
 
 /* Specify the external PHY device uses I2C bus instead of MDIO bus */
 #define spn_PHY_BUS_I2C  "phy_bus_i2c"
 
 /* Specify the external PHY device is a copper SFP PHY */
 #define spn_PHY_COPPER_SFP  "phy_copper_sfp"
 
 /* The PHY has a fiber medium in addition to a copper medium */
 #define spn_PHY_FIBER_CAPABLE  "phy_fiber_capable"
 /*
  * Set phy operational mode (repeater/retimer/Gearbox/EBE).
  * Value 0 => Repeater (default)
  * Value 1 => Retimer
  * Value 2 => Gearbox
  * Value 3 => EBE
  */
 #define spn_PHY_OPERATIONAL_MODE  "phy_operational_mode"
 
 /* Initialize external phy with CL72 enabled */
 #define spn_PHY_INIT_CL72  "phy_init_cl72"
 /*
  * Set phy datapath mode (default/alternate).
  * Value 0 => Default Datapath (default)
  * Value 1 => Alternate DataPath
  */
 #define spn_PHY_ALT_DATAPATH_MODE  "phy_alt_datapath_mode"
 /*
  * Bypass the PCS retimer function to provide better latency.
  * However it requires a more clean input clock than in retimer mode
  */
 #define spn_PHY_PCS_REPEATER  "phy_pcs_repeater"
 
 /* Specify the sytem side interface to be configured for the PHY */
 #define spn_PHY_SYS_INTERFACE  "phy_sys_interface"
 
 /* Specify the data path mode to be configured for the PHY */
 #define spn_PHY_ULL_DATAPATH  "phy_ull_datapath"
 
 /* Specify tx disable to not be wired to LPMODE pin from the PHY to the cage */
 #define spn_PHY_TX_DISABLE_NO_LPMODE  "phy_tx_disable_no_lpmode"
 
 /* gig port i/o voltage control on BCM5615 and similar devices */
 #define spn_GIG_IOV  "gig_iov"
 
 /* Force the port into TBI(10-bit interface) mode */
 #define spn_IF_TBI  "if_tbi"
 
 /* Set 10G+ stack ports to default to B5632 encapsulation instead of Higig format */
 #define spn_BCM5632_MODE  "bcm5632_mode"
 
 /* Reset meters for 10/100Mb ports during initialization */
 #define spn_BCM_METER_CLEAR_FE  "bcm_meter_clear_fe"
 
 /* Reset meters for 1000Mb ports during initialization */
 #define spn_BCM_METER_CLEAR_GE  "bcm_meter_clear_ge"
 
 /* Reset meters for 10GE ports during initialization */
 #define spn_BCM_METER_CLEAR_XE  "bcm_meter_clear_xe"
 /*
  * Fusion/Uni core preemphasis, driver current and  pre-driver current
  * values 0-15 (can be changed per-port)
  */
 #define spn_XGXS_PREEMPHASIS  "xgxs_preemphasis"
 
 /* Configure the given driver current value for applicable XGXS serdes devices. */
 #define spn_XGXS_DRIVER_CURRENT  "xgxs_driver_current"
 
 /* Configure the given pre driver current value for applicable XGXS serdes devices. */
 #define spn_XGXS_PRE_DRIVER_CURRENT  "xgxs_pre_driver_current"
 
 /* Fusion PLL lock range value 0-15 (can be changed per-port) */
 #define spn_XGXS_PLLLOCK  "xgxs_plllock"
 
 /* Set the specific RX equalizer control value for applicable XGXS devices */
 #define spn_XGXS_EQUALIZER  "xgxs_equalizer"
 /*
  * Set the specific offset which is part of RX equalizer control value
  *  for applicable XGXS devices
  */
 #define spn_XGXS_OFFSET  "xgxs_offset"
 
 /* Use crystal input for LCPLL */
 #define spn_XGXS_LCPLL_XTAL_REFCLK  "xgxs_lcpll_xtal_refclk"
 
 /* Use crystal input for WCPLL */
 #define spn_XGXS_WCPLL_XTAL_REFCLK  "xgxs_wcpll_xtal_refclk"
 
 /* Use crystal input for QGPLL */
 #define spn_XGXS_QGPLL_XTAL_REFCLK  "xgxs_qgpll_xtal_refclk"
 
 /* phy pll divider */
 #define spn_XGXS_PHY_PLL_DIVIDER  "xgxs_phy_pll_divider"
 
 /* phy oversample mode */
 #define spn_XGXS_PHY_OVERSAMPLE_MODE  "xgxs_phy_oversample_mode"
 /*
  * Fusion core reference clock selection
  *  External Clock = 0, Internal LCPLL = 1
  */
 #define spn_XGXS_LCPLL  "xgxs_lcpll"
 /*
  * this property is for debug and diagnostic purpose.
  * byte0:
  * 0: not loading WC firmware
  * 1: load from MDIO. default method.
  * 2: load from parallel bus if applicable. Provide fast downloading time
  *  
  * byte1: bit 0
  * 0: inform uC not to perform checksum calculation(default). Save ~70ms for WC init time
  * 1: inform uC to perform checksum calculation. 
  * byte1: bit 4
  * 0: not to do the FW load verify
  * 1: do the FW load verify. 
  */
 #define spn_LOAD_FIRMWARE  "load_firmware"
 
 /* Fusion core LCPLL clock speed selection - 10Gbps = 0, 12Gbps = 1 */
 #define spn_XGXS_LCPLL_12GBPS  "xgxs_lcpll_12gbps"
 
 /* Unicore 10G parallel detect (10/12 Gbps legacy speed detection) */
 #define spn_XGXS_PDETECT_10G  "xgxs_pdetect_10g"
 
 /* Remap XGXS tx lanes to desired mapping. See xgxs_rx_lane_map */
 #define spn_XGXS_TX_LANE_MAP  "xgxs_tx_lane_map"
 /*
  * Remap XGXS rx lanes to desired mapping. Four bits were used for
  * specifying each lane in the format of Lane 0 (bit 15-12), Lane 1 (bit 11-8),
  * lane 2 (bit 7-4), and lane 3 (bit 3-0).
  * For example, to reverse the rx lane mapping in 3, 2, 1, 0 order,
  * set xgxs_rx_lane_map=0x3210.
  * However for Warpcore serdes device, the format is in reversed order, that is,  
  * Lane 3 (bit 15-12), Lane 2 (bit 11-8),lane 1 (bit 7-4), and lane 0 (bit 3-0),
  * The example above will be: set xgxs_rx_lane_map=0x0123.
  */
 #define spn_XGXS_RX_LANE_MAP  "xgxs_rx_lane_map"
 
 /* Remap tx lanes to desired mapping. See phy_rx_lane_map. */
 #define spn_PHY_TX_LANE_MAP  "phy_tx_lane_map"
 
 /* Remap tx lanes to desired mapping. See phy_chain_rx_lane_map_physical. */
 #define spn_PHY_CHAIN_TX_LANE_MAP_PHYSICAL  "phy_chain_tx_lane_map_physical"
 /*
  * Configure cross-switch lane mapping. Four bits are used for
  * specifying each lane in the format of lane 0 (bits 3-0), 
  * lane 1 (bits 7-4), lane 3 (bits 11-8), etc.
  */
 #define spn_PHY_XSW_LANE_MAP  "phy_xsw_lane_map"
 /*
  * Remap tx lanes to desired mapping. The format is in reversed order, that is,  
  * Lane 3 (bit 15-12), Lane 2 (bit 11-8),lane 1 (bit 7-4), and lane 0 (bit 3-0)
  */
 #define spn_PHY_RX_LANE_MAP  "phy_rx_lane_map"
 /*
  * Remap tx lanes to desired mapping on applicable PHY devices
  * Format: phy_chain_rx_lane_map_physical[{<phys_port>[<phy:num>]}] = VALUE
  * 	<phys_port>: Physical port number which is corresponding to a physical lane within a Serdes or an external phy.
  * 		     If ommitted, this applies to all PHYs in the chain.
  * 	<phy_num>:   Serdes or phy number.
  * 		     If ommitted, this applies to all PHYs in the chain (internal/external) where the <phys_port> belongs to.
  * 		     0 = internal Serdes
  * 		     1 = the external phy directly attached to Serdes
  * 		     2 = the external phy attached to phy1
  * 		     3 = the external phy attached to phy2
  * 		     etc.
  * 	VALUE: The format is in reversed order, that is,
  * 		     bit3-0:   lane 0 for physical port <phys_port>
  * 		     bit7-4:   lane 1 for physical port <phys_port>
  * 		     bit11-8:  lane 2 for physical port <phys_port>
  * 		     bit15-12: lane 3 for physical port <phys_port>
  * 		     etc.
  * 	For Example: phy_chain_rx_lane_map_physical{1.0} = 0x2103	Internal Serdes rx lane map on physical port 1
  * 		     phy_chain_rx_lane_map_physical{1.1} = 0x0123	rx lane swap  for the physical  physical port 1 in the innermost external phy
  */
 #define spn_PHY_CHAIN_RX_LANE_MAP_PHYSICAL  "phy_chain_rx_lane_map_physical"
 /*
  * BCM8806X Support
  * Bits [1:0] = 0b00 - log to UART, 0b01 - log to memory, 0b10 - turn off logging
  */
 #define spn_PHY_DIAG_BMP  "phy_diag_bmp"
 /*
  * BCM8806X Support
  * Host managed fiber channel transceiver. Is a Per-Port SOC property.
  * 0 -> Not Host managed (Default)
  * 1->Host Managed.
  */
 #define spn_FCMAP_TRANSCEIVER_HOST_MANAGED  "fcmap_transceiver_host_managed"
 /*
  * Remap ESM serdes tx lanes to desired mapping.
  * Four bits were used for specifying each lane in the 
  * format of Lane 3 (bit 15-12), Lane 2 (bit 11-8),
  * lane 1 (bit 7-4), and lane 0 (bit 3-0).
  * For ex: To reverse the rx lane mapping in 0-1-2-3 order,
  * set esm_serdes_tx_lane_map_core0=0x0123.
  * set esm_serdes_tx_lane_map_core1=0x0123, for core1 and so on
  */
 #define spn_ESM_SERDES_TX_LANE_MAP  "esm_serdes_tx_lane_map"
 /*
  * Remap ESM serdes rx lanes to desired mapping.
  * Four bits were used for specifying each lane in the 
  * format of Lane 3 (bit 15-12), Lane 2 (bit 11-8),
  * lane 1 (bit 7-4), and lane 0 (bit 3-0).
  * For ex: To reverse the rx lane mapping in 0-1-2-3 order,
  * set esm_serdes_rx_lane_map_core0=0x0123.
  * set esm_serdes_rx_lane_map_core1=0x0123, for core1 and so on
  */
 #define spn_ESM_SERDES_RX_LANE_MAP  "esm_serdes_rx_lane_map"
 /*
  * Select a serdes for master clock source among/for a group of
  * serdes devices
  * For ex: set esm_serdes_master_clk_src=2, to select 3rd serdes(0,1,->2<-)
  */
 #define spn_ESM_SERDES_MASTER_CLK_SRC  "esm_serdes_master_clk_src"
 /*
  * ESM serdes lane TX amplitude control,
  *  default value is 4
  */
 #define spn_ESM_SERDES_DRIVER_CURRENT  "esm_serdes_driver_current"
 /*
  * ESM serdes lane TX amplitude control,
  *  default value is 4
  */
 #define spn_ESM_SERDES_PRE_DRIVER_CURRENT  "esm_serdes_pre_driver_current"
 /*
  * ESM serdes lane TX fir control to AFE for ESM and PentaCore only,
  *  default value is 0
  */
 #define spn_ESM_SERDES_PRECURSOR_TAP  "esm_serdes_precursor_tap"
 /*
  * ESM serdes lane TX fir control to AFE for ESM and PentaCore only,
  *  default value is 40
  */
 #define spn_ESM_SERDES_MAIN_TAP  "esm_serdes_main_tap"
 /*
  * ESM serdes lane TX fir control to AFE for ESM and PentaCore only,
  *  default value is 7
  */
 #define spn_ESM_SERDES_POSTCURSOR_TAP  "esm_serdes_postcursor_tap"
 /*
  * Serdes reference clock selection External Clock = 0,
  *  Internal LCPLL = 1
  */
 #define spn_SERDES_LCPLL  "serdes_lcpll"
 
 /* Serdes core preemphasis. values 0-15 (can be changed per-port) */
 #define spn_SERDES_PREEMPHASIS  "serdes_preemphasis"
 
 /* Serdes core pre-driver current. values 0-15 (can be changed per-port) */
 #define spn_SERDES_PRE_DRIVER_CURRENT  "serdes_pre_driver_current"
 
 /* Serdes core driver current. values 0-15 (can be changed per-port) */
 #define spn_SERDES_DRIVER_CURRENT  "serdes_driver_current"
 
 /* Serdes core post 2 driver current. values 0-15 (can be changed per-port) */
 #define spn_SERDES_POST2_DRIVER_CURRENT  "serdes_post2_driver_current"
 
 /* Serdes micro controller firmware mode */
 #define spn_SERDES_FIRMWARE_MODE  "serdes_firmware_mode"
 
 /* Serdes scrambler enable */
 #define spn_SERDES_SCRAMBLER_ENABLE  "serdes_scrambler_enable"
 
 /* Serdes over sampling mode */
 #define spn_SERDES_OS_MODE  "serdes_os_mode"
 
 /* Serdes enocde mode */
 #define spn_SERDES_ENC_MODE  "serdes_enc_mode"
 
 /* Serdes PLL divider value */
 #define spn_SERDES_PLL_DIV  "serdes_pll_div"
 
 /* Serdes number of lanes per port */
 #define spn_SERDES_NUM_LANE  "serdes_num_lane"
 /*
  * Configure signal auto-detection between SGMII and fiber
  *  Note this only works when auto-negotiation is enabled.
  */
 #define spn_SERDES_AUTOMEDIUM  "serdes_automedium"
 
 /* This manually select the port interface type like SFI, XFI, GMII, SGMII, XAUI, XLAUI */
 #define spn_SERDES_IF_TYPE  "serdes_if_type"
 
 /* This manually selects either fiber or SGMII when auto-detection is off */
 #define spn_SERDES_FIBER_PREF  "serdes_fiber_pref"
 
 /* switch serdes SGMII master/slave mode configuration.  Default is slave. */
 #define spn_SERDES_SGMII_MASTER  "serdes_sgmii_master"
 /*
  * In QSGMII serdes, this overrides the SGMII/QSGMII mode
  *  0 = HW default (OTP/Strap Selected) , 1 = QSGMII, 2 = SGMII. 
  */
 #define spn_SERDES_QSGMII_SGMII_OVERRIDE  "serdes_qsgmii_sgmii_override"
 
 /* Enable/disable two lane XAUI interface on applicable serdes devices */
 #define spn_SERDES_2WIRE_XAUI  "serdes_2wire_xaui"
 
 /* Enable serdes Loss Of Signal(LOS) function. 0 disable, 1 enable */
 #define spn_SERDES_RX_LOS  "serdes_rx_los"
 
 /* Invert serdes LOS signal level. 0 not invert, 1 invert */
 #define spn_SERDES_RX_LOS_INVERT  "serdes_rx_los_invert"
 
 /* TX serdes LOS interval to reset the LP receiver */
 #define spn_SERDES_TX_LOS_USEC  "serdes_tx_los_usec"
 
 /* Enable Asymmetric fixed speed mode. 1 enable */
 #define spn_SERDES_ASYMMETRIC_SPEED_MODE  "serdes_asymmetric_speed_mode"
 
 /* Serdes pcs speed HTO pll_diviver */
 #define spn_SERDES_PCS_SPEED_HTO_PLL_DIVIDER  "serdes_pcs_speed_hto_pll_divider"
 
 /* Serdes pcs speed HTO pma over sample mode */
 #define spn_SERDES_PCS_SPEED_HTO_PMA_OS  "serdes_pcs_speed_hto_pma_os"
 
 /* Serdes pcs speed HTO scramble mode */
 #define spn_SERDES_PCS_SPEED_HTO_SCR_MODE  "serdes_pcs_speed_hto_scr_mode"
 
 /* Serdes pcs speed HTO encode mode */
 #define spn_SERDES_PCS_SPEED_HTO_ENCODE_MODE  "serdes_pcs_speed_hto_encode_mode"
 
 /* Serdes pcs speed HTO CL48 checkend mode */
 #define spn_SERDES_PCS_SPEED_HTO_CL48_CHECK_END  "serdes_pcs_speed_hto_cl48_check_end"
 
 /* Serdes pcs speed HTO block sync mode */
 #define spn_SERDES_PCS_SPEED_HTO_BLK_SYNC_END  "serdes_pcs_speed_hto_blk_sync_end"
 
 /* Serdes pcs speed HTO reorder mode */
 #define spn_SERDES_PCS_SPEED_HTO_REORDER_MODE  "serdes_pcs_speed_hto_reorder_mode"
 
 /* Serdes pcs speed HTO cl36 enable mode */
 #define spn_SERDES_PCS_SPEED_HTO_CL36_EN  "serdes_pcs_speed_hto_cl36_en"
 
 /* Serdes pcs speed HTO descramble reg1 mode */
 #define spn_SERDES_PCS_SPEED_HTO_DESCR1_MODE  "serdes_pcs_speed_hto_descr1_mode"
 
 /* Serdes pcs speed HTO decode reg1 mode */
 #define spn_SERDES_PCS_SPEED_HTO_DEC1_MODE  "serdes_pcs_speed_hto_dec1_mode"
 
 /* Serdes pcs speed HTO deskew mode */
 #define spn_SERDES_PCS_SPEED_HTO_DESKEW_MODE  "serdes_pcs_speed_hto_deskew_mode"
 
 /* Serdes pcs speed HTO descramble reg2 mode */
 #define spn_SERDES_PCS_SPEED_HTO_DESC2_MODE  "serdes_pcs_speed_hto_desc2_mode"
 
 /* Serdes pcs speed HTO descramble reg2 byte delete mode */
 #define spn_SERDES_PCS_SPEED_HTO_DESC2_BYTE_DEL  "serdes_pcs_speed_hto_desc2_byte_del"
 
 /* Serdes pcs speed HTO BRCM 64/66 descrmable mode */
 #define spn_SERDES_PCS_SPEED_HTO_BRCM64B66_DESCR  "serdes_pcs_speed_hto_brcm64b66_descr"
 
 /* Serdes pcs speed HTO SGMII mode */
 #define spn_SERDES_PCS_SPEED_HTO_SGMII_MODE  "serdes_pcs_speed_hto_sgmii_mode"
 
 /* Serdes pcs speed HTO clock counter0 value */
 #define spn_SERDES_PCS_SPEED_HTO_CLKCNT0  "serdes_pcs_speed_hto_clkcnt0"
 
 /* Serdes pcs speed HTO clock counter1 value */
 #define spn_SERDES_PCS_SPEED_HTO_CLKCNT1  "serdes_pcs_speed_hto_clkcnt1"
 
 /* Serdes pcs speed HTO loop counter0 value */
 #define spn_SERDES_PCS_SPEED_HTO_LPCNT0  "serdes_pcs_speed_hto_lpcnt0"
 
 /* Serdes pcs speed HTO loop counter1 value */
 #define spn_SERDES_PCS_SPEED_HTO_LPCNT1  "serdes_pcs_speed_hto_lpcnt1"
 
 /* Serdes pcs speed HTO MAC CGC value */
 #define spn_SERDES_PCS_SPEED_HTO_MAC_CGC  "serdes_pcs_speed_hto_mac_cgc"
 
 /* Serdes pcs speed HTO PCS repeat count */
 #define spn_SERDES_PCS_SPEED_HTO_PCS_REPCNT  "serdes_pcs_speed_hto_pcs_repcnt"
 
 /* Serdes pcs speed HTO PCS credit enable */
 #define spn_SERDES_PCS_SPEED_HTO_PCS_CRDTEN  "serdes_pcs_speed_hto_pcs_crdten"
 
 /* Serdes pcs speed HTO PCS clock count */
 #define spn_SERDES_PCS_SPEED_HTO_PCS_CLKCNT  "serdes_pcs_speed_hto_pcs_clkcnt"
 
 /* Serdes pcs speed HTO PCS CGC value */
 #define spn_SERDES_PCS_SPEED_HTO_PCS_CGC  "serdes_pcs_speed_hto_pcs_cgc"
 
 /* Serdes pcs speed HTO CL72 enable */
 #define spn_SERDES_PCS_SPEED_HTO_CL72_ENABLE  "serdes_pcs_speed_hto_cl72_enable"
 
 /* Enable different speed rates in the same serdes. 1 enable */
 #define spn_SERDES_MIXED_RATE_ENABLE  "serdes_mixed_rate_enable"
 
 /* Enable 1000X at 6.25G vco. default is running at 10.3125G  1 enable */
 #define spn_SERDES_1000X_AT_6250_VCO  "serdes_1000x_at_6250_vco"
 
 /* Enable 1000X at 25G vco. default is running at 20G vco  1 enable */
 #define spn_SERDES_1000X_AT_25G_VCO  "serdes_1000x_at_25g_vco"
 
 /* Enable 10GBase-R at 25G vco. default is running at 20G vco  1 enable */
 #define spn_SERDES_10G_AT_25G_VCO  "serdes_10g_at_25g_vco"
 
 /* Enable fec during serdes init 0 no fec, 1 cl74, 2 cl91 */
 #define spn_SERDES_FEC_ENABLE  "serdes_fec_enable"
 
 /* Enable 1000X at 12.5G vco. default is running at 10.3125G vco  1 enable */
 #define spn_SERDES_1000X_AT_12500_VCO  "serdes_1000x_at_12500_vco"
 /*
  * serdes PMD lane configurations.
  * suffixes and property values for each suffix:
  * - dfe: on|off|lp
  * - media_type: backplane|copper|optics
  * - unreliable_los: 0|1
  * - cl72_auto_polarity_en: 0|1
  * - cl72_restart_timeout_en: 0|1
  * - channel_mode: force_nr|force_er
  * for example,
  * for logical port ce0, you can specify
  * serdes_lane_config_dfe_ce0=on
  * this will be implying that for logical port ce0
  * DFE is on
  */
 #define spn_SERDES_LANE_CONFIG  "serdes_lane_config"
 /*
  * has the link partner enabled pre-coding on its TX side
  * in other words - enable the decoding on my RX side. 
  * the configuration is per logical port.
  * to enable the feature on my rx, the property value should be "enable".
  * to disable the feature on my rx, the property value should be "disable".
  * for example: port_lp_tx_precoder_ce0=enable
  * will imply that precoding is enabled on TX side of the link partner of logical port ce0
  * and so decoding is enabled on RX of logical port ce0.
  */
 #define spn_PORT_LP_TX_PRECODER  "port_lp_tx_precoder"
 /*
  * is the precoding enabled on TX side
  * the configuration is per logical port.
  * to enable precoding, the property value should be "enable".
  * to disable precoding, the property value should be "disable".
  * for example: port_tx_pam4_precoder_ce0=enable
  * will imply that precoding is enabled on TX side of logical port ce0
  */
 #define spn_PORT_TX_PAM4_PRECODER  "port_tx_pam4_precoder"
 /*
  * serdes_tx_taps to specify either 3 taps or 6 taps, in nrz or pam4 signalling mode.
  * this config is per logical port.
  * the taps are decimal numbers, positive or negative, separated by a colon ":".
  * the first parameter will specify whether the Tx params are suitable for nrz or pam4 signaling mode.
  * the order will be as follows:
  * For 3 taps mode:
  * serdes_tx_taps_<port>=signaling_mode:pre:main:post
  * For example, for ce3 in 3 taps mode, pre=8, main=50, post=12, that will be working in nrz mode,
  * The config will be serdes_tx_taps_ce3=nrz:8:50:12
  * For 6 taps mode:
  * serdes_tx_taps_<port>=signaling_mode:pre:main:post:pre2:post2:post3
  * For example, for ce9 that needs to config 6 taps mode, pre1=-10, main=60, post1=8, pre2=2, post2=-4, post3=3,
  * that will be working in pam4 mode,
  * serdes_tx_taps_ce9=pam4:-10:60:8:2:-4:3
  * if this config is not specified, then SDK will use its own default tx taps value.
  */
 #define spn_SERDES_TX_TAPS  "serdes_tx_taps"
 /*
  * this config is per PM Core
  * serdes_core_tx_polarity_flip_physical{phys_port}
  * phys_port will be the first physical port on that core
  * bit 0 represents the logical lane 0 tx flip
  * bit 1 represents the logical lane 1 tx flip,
  * etc...
  * for example
  * serdes_core_tx_polarity_flip_physical{5}=0xc5
  * the core which is used by physical port 5 have lane 0,2,6 and 7 tx flipped
  */
 #define spn_SERDES_CORE_TX_POLARITY_FLIP_PHYSICAL  "serdes_core_tx_polarity_flip_physical"
 /*
  * this config is per PM Core
  * serdes_core_rx_polarity_flip_physical{phys_port}
  * bit 0 represents the logical lane 0 rx flip
  * bit 1 represents the logical lane 1 rx flip,
  * etc...
  * serdes_core_rx_polarity_flip_physical{9}=0x38
  * the core which is used by physical port 5 have lane  lane 3,4 and 5 rx flipped
  */
 #define spn_SERDES_CORE_RX_POLARITY_FLIP_PHYSICAL  "serdes_core_rx_polarity_flip_physical"
 /*
  * Selects the primary L1 clock recovery port.
  * Choose a non-cpu port that does not have an external phy.
  */
 #define spn_L1_PRIMARY_CLK_RECOVERY_PORT  "L1_primary_clk_recovery_port"
 /*
  * Selects the backup L1 clock recovery port.
  * Choose a non-cpu port that does not have an external phy.
  */
 #define spn_L1_BACKUP_CLK_RECOVERY_PORT  "L1_backup_clk_recovery_port"
 /*
  * BCM5665L and BCM5666L support
  * The BCM5665L and BCM5666L device IDs are 0x5665, same as the BCM5665.
  * However, these devices do not support the upper 24 FE ports.
  * The following property must be used to invalidate them.
  */
 #define spn_PBMP_VALID  "pbmp_valid"
 /*
  * Configure the memory tests run during BCM5670 initialization
  * (using MT_PAT_* flags)
  */
 #define spn_LLA_TESTS  "lla_tests"
 #define spn_STACK_ENABLE  "stack_enable"
 #define spn_STACK_SIMPLEX  "stack_simplex"
 
 /* Stack master priority for stacking examples. */
 #define spn_STACK_CPU_PRIORITY  "stack_cpu_priority"
 /*
  * By default, 5670 will be configured to accept the maximum number of
  * packets per port, but may drop them if resources are oversubscribed due
  * to activity from other ports.  If lossless mode is enabled, 5670 will
  * instead be configured to accept packets only if sufficient processing
  * resources are guaranteed for all ports.  This may decrease overall
  * throughput, but no accepted packets will be dropped.
  */
 #define spn_LOSSLESS_MODE  "lossless_mode"
 /*
  * Allow a BCM5675 fabric device to mirror using the same method as
  * a BCM5670 fabric.
  */
 #define spn_MIRROR_5670_MODE  "mirror_5670_mode"
 
 /* Configure a BCM5675 fabric device to to operate with a 12G core clock. */
 #define spn_CORE_CLOCK_12G  "core_clock_12G"
 /*
  * BCM5675 HOL blocking avoidance mode (jitter and hysteresis)
  * Set this to 1 to enable jitter for comparing low cell/packet count thresholds
  */
 #define spn_MMU_HOL_JITTER  "mmu_hol_jitter"
 
 /* Set this to 1 to enable hysteresis with recommended default low thresholds */
 #define spn_MMU_HOL_HYSTERESIS  "mmu_hol_hysteresis"
 
 /* Specify IEEE MII reset timeout value for copper PHY devices */
 #define spn_PHY_RESET_TIMEOUT  "phy_reset_timeout"
 /*
  * 24c64 EEPROM and XFP share the same I2C slave address. Set this to
  * 1 to treat the device found at this slave address as XFP.
  */
 #define spn_I2C_NVRAM_SKIP  "i2c_nvram_skip"
 /*
  * PCF8574 lpt2 and LTC4258 poe3 share the same I2C slave address. Set
  * this to 1 to treat the device found at this slave address as POE.
  */
 #define spn_I2C_HCLK_SKIP  "i2c_hclk_skip"
 /*
  * PD63000 init power setting. Set this to 1 for 100W; otherwise
  * default of 37W is used.
  */
 #define spn_I2C_POE_POWER  "i2c_poe_power"
 /*
  * The maximum wait time for a I2C transaction to complete in
  * interrupt-driven mode.
  */
 #define spn_I2C_TIMEOUT_USEC  "i2c_timeout_usec"
 
 /* Swap XGXS device tx lane 0, 1, 2, 3 to lane 3, 2, 1, 0 on 10G PHYs */
 #define spn_PHY_XAUI_TX_LANE_SWAP  "phy_xaui_tx_lane_swap"
 
 /* Swap XGXS device rx lane 0, 1, 2, 3 to lane 3, 2, 1, 0 on 10G PHYs */
 #define spn_PHY_XAUI_RX_LANE_SWAP  "phy_xaui_rx_lane_swap"
 
 /* Swap MLD lane tx lane 0 through 23 */
 #define spn_MLD_LANE_SWAP  "mld_lane_swap"
 
 /* to specify 10 active lanes for 100G application */
 #define spn_PHY_XAUI_ACTIVE_LANE_MAP  "phy_xaui_active_lane_map"
 
 /* specify port ot run at pcs bypass or not */
 #define spn_PHY_PCS_BYPASS  "phy_pcs_bypass"
 
 /* specify rxaui mode */
 #define spn_SERDES_RXAUI_MODE  "serdes_rxaui_mode"
 
 /* To disable the logic of proxy removal */
 #define spn_SERDES_USE_PROXY_REMOVAL  "serdes_use_proxy_removal"
 
 /* To set customers specific alignment marker */
 #define spn_SERDES_PCS_20G_ALIGNMENT_MARKER_RESERVED  "serdes_pcs_20g_alignment_marker_reserved"
 /*
  * Flip PHY lane TX polarity on applicable serdes devices
  * Format: phy_xaui_tx_polarity_flip_logicalPort = VALUE
  * VALUE:  1 - Flip TX polarity.
  *         0 - Do not flip TX polarity.
  *         Each bit represents one lane.
  *         Logical lane 0 is the right most bit.
  * Example: phy_xaui_tx_polarity_flip_xe10 = 0x5  Flip TX polarity on logical lane 0 and logical lane 2 in internal serdes.
  *          phy_xaui_tx_polarity_flip_ce0 = 0x104 TX polarity flip lanes: Lane 2 of first quad, Lane 0 of the third quad.
  *          For TSCe12, which has three quads for a logical port, the right most nibble represents the first TSCe4 quad while middle nibble represents the second (middle) TSCe4 quad.
  */
 #define spn_PHY_XAUI_TX_POLARITY_FLIP  "phy_xaui_tx_polarity_flip"
 
 /* Flip PHY lane RX polarity. Detail see phy_xaui_tx_polarity_flip for values */
 #define spn_PHY_XAUI_RX_POLARITY_FLIP  "phy_xaui_rx_polarity_flip"
 /*
  * Flip PHY lane TX polarity on applicable ext PHY devices
  * Format: phy_tx_polarity_flip_logicalPort = VALUE
  * 	VALUE:       1 - Flip TX polarity.
  * 		     0 - Do not flip TX polarity.
  * 		     Each bit represents one lane.
  * 	For Example: phy_tx_polarity_flip_ce0 = 0x5	Flip TX polarity on the first and third lane of ce0 on external phy
  * The polarity info of one core needs to be given in a signle command.
  */
 #define spn_PHY_TX_POLARITY_FLIP  "phy_tx_polarity_flip"
 /*
  * Flip PHY lane RX polarity on applicable ext PHY devices
  * Detail see phy_tx_polarity_flip.
  */
 #define spn_PHY_RX_POLARITY_FLIP  "phy_rx_polarity_flip"
 /*
  * Flip PHY lane TX polarity on applicable PHY devices
  * Format: phy_chain_tx_polarity_flip_physical[{<phys_port>.<phy:num>}] = VALUE
  * 	<phys_port>: Physical port number which is corresponding to a physical lane within a Serdes or an external phy.
  * 	<phy_num>:   Serdes or phy number.
  * 		     0 = internal Serdes
  * 		     1 = the external phy directly attached to Serdes
  * 		     2 = the external phy attached to phy1
  * 		     3 = the external phy attached to phy2
  * 		     etc.
  * 	VALUE:       1 - Flip TX polarity.
  * 		     0 - Do not flip TX polarity.
  * 		     Should be a 1-bit VALUE
  * 	For Example: phy_chain_tx_polarity_flip_physical{1.0} = 1	Internal Serdes TX polarity flip is enabled on physical port 1
  * 		     phy_chain_tx_polarity_flip_physical{1.1} = 1	TX polarity flip is enabled for the physical port 1 in the innermost external phy
  * This format does not applicable for Gearbox mode and Reverse Gearbox mode external Phys. Use phy_tx/rx_polarity_flip instead.
  */
 #define spn_PHY_CHAIN_TX_POLARITY_FLIP_PHYSICAL  "phy_chain_tx_polarity_flip_physical"
 /*
  * Flip PHY lane RX polarity on applicable PHY devices
  * Detail see phy_chain_tx_polarity_flip_physical.
  */
 #define spn_PHY_CHAIN_RX_POLARITY_FLIP_PHYSICAL  "phy_chain_rx_polarity_flip_physical"
 
 /* Flip PCS lane TX polarity. See phy_xaui_tx_polarity_flip for values */
 #define spn_PHY_PCS_TX_POLARITY_FLIP  "phy_pcs_tx_polarity_flip"
 
 /* Flip PCS lane RX polarity. See phy_xaui_tx_polarity_flip for values */
 #define spn_PHY_PCS_RX_POLARITY_FLIP  "phy_pcs_rx_polarity_flip"
 /*
  * Flip ESM serdes lane TX polarity.
  * Each lane is represented by a single bit.
  * For ex: Bit0 represents Lane0, Bit1 represents Lane1
  * value of 0x0001 - Flip TX polarity on lane 0.
  * value of 0x0002 - Flip TX polarity on lane 1.
  * value of 0x0004 - Flip TX polarity on lane 2.
  * value of 0x0008 - Flip TX polarity on lane 3.
  * value of 0x000f - Flip TX polarity on lane 3,2,1,0.
  */
 #define spn_ESM_SERDES_TX_POLARITY_FLIP  "esm_serdes_tx_polarity_flip"
 /*
  * Flip ESM serdes lane RX polarity.
  * Each lane is represented by a single bit.
  * For ex: Bit0 represents Lane0, Bit1 represents Lane1
  * value of 0x0001 - Flip RX polarity on lane 0.
  * value of 0x0002 - Flip RX polarity on lane 1.
  * value of 0x0004 - Flip RX polarity on lane 2.
  * value of 0x0008 - Flip RX polarity on lane 3.
  * value of 0x000f - Flip TX polarity on lane 3,2,1,0.
  */
 #define spn_ESM_SERDES_RX_POLARITY_FLIP  "esm_serdes_rx_polarity_flip"
 
 /* Transform CX4 pinout to Higig pinout on 5650x/5660x */
 #define spn_CX4_TO_HIGIG  "cx4_to_higig"
 /*
  * Set serdes device CX4 mode or Higig mode for 10G speed. 
  * Value TRUE is CX4 mode, FALSE is Higig mode.
  */
 #define spn_10G_IS_CX4  "10g_is_cx4"
 
 /* Control Active Laser Loss of light level. */
 #define spn_FORCE_OPTRXLOSLVL  "force_optrxloslvl"
 /*
  * The following optical controls manage to force various PHY signal on
  * BCM8703/4/5
  * Control Active Optical Enable output level.
  */
 #define spn_FORCE_OPTTXENBLVL  "force_opttxenblvl"
 
 /* Control Active Optical Reset output level. */
 #define spn_FORCE_OPTTXRSTLVL  "force_opttxrstlvl"
 
 /* Control Active Laser Bias Fault level. */
 #define spn_FORCE_OPTBIASFLTLVL  "force_optbiasfltlvl"
 
 /* Control Active Temperature level. */
 #define spn_FORCE_OPTTEMPFLTLVL  "force_opttempfltlvl"
 
 /* Control Active Laser Power Fault level. */
 #define spn_FORCE_OPTPRFLTLVL  "force_optprfltlvl"
 
 /* Control Active TX fault level. */
 #define spn_FORCE_OPTTXFLLVL  "force_opttxfllvl"
 
 /* Control Active RX fault level. */
 #define spn_FORCE_OPTRXFLTLVL  "force_optrxfltlvl"
 
 /* Control Active TX on level. */
 #define spn_FORCE_OPTTXONLVL  "force_opttxonlvl"
 /*
  * BCM5665 family debug mode - bypass MCU, allows diagnostics such as
  * loopback to be run without initializing the MCU (but requires small
  * packet sizes and counts).
  */
 #define spn_BYPASS_MCU  "bypass_mcu"
 /*
  * Allow external MDIO master access.  Otherwise, the switch device
  * is the MDIO master.
  */
 #define spn_MDIO_EXTERNAL_MASTER  "mdio_external_master"
 /*
  * Per-port phy LED control values (currently only used by 546x phy driver)
  * see 546x phy data sheets:
  * ledN_mode are LED selector values from phy reg 0x1x[011101, 01110]
  * led_ctrl is phy reg 0x1x[01001]
  */
 #define spn_PHY_LED1_MODE  "phy_led1_mode"
 
 /* See description of phy_led1_mode */
 #define spn_PHY_LED2_MODE  "phy_led2_mode"
 
 /* See description of phy_led1_mode */
 #define spn_PHY_LED3_MODE  "phy_led3_mode"
 
 /* See description of phy_led1_mode */
 #define spn_PHY_LED4_MODE  "phy_led4_mode"
 
 /* Control the LED function on 546x phy device. */
 #define spn_PHY_LED_CTRL  "phy_led_ctrl"
 
 /* select the multi-color LED display pattern on 546x phy device. */
 #define spn_PHY_LED_SELECT  "phy_led_select"
 /*
  * Any LED programmed to linkspd(0) or linkspd(1) indicate 
  * the link and speed status of the copper interface. The 
  * phy has a feature that allows different interpretations 
  * of speed and link based on linkspd(0) and linkspd(1).
  * Use this config to select one of the following modes-
  * DEFAULT(0), LINK_LED_MODE(1) & LINK_SPEED_MODE(2)
  */
 #define spn_PHY_LED_LINK_SPEED_MODE  "phy_led_link_speed_mode"
 /*
  * Control the behavior of an LED in the phy to access 
  * the TOP_MISC_SPARE_REG_0 to set bit 1 for LOS signal.
  * Need to set bit 1 in this reg on the first port of the chip.
  */
 #define spn_PHY_LED3_OUTPUT_DISABLE  "phy_led3_output_disable"
 /*
  * Per-port control of fiber signal detection (for 546x phys)
  *     0    use the phy's default as signal detect
  *     1    use PECL SD as signal detect (default on 5461)
  *     4    use LED4 as signal detect (default on 5464)
  * 10    use EN_10B as signal detect
  * Negating value treats signal detect as loss of signal without
  * needing an external inverter on the board
  */
 #define spn_PHY_FIBER_DETECT  "phy_fiber_detect"
 /*
  * MCU properties are available to tune DDR memory interfaces on devices
  * with external packet buffers.  The device value controlled by each
  * property is indicated in that property.  Note that such devices
  * typically have multiple channels to the packet buffer memory, so these
  * properties may be configured with the base name to control all channels,
  * or with the suffix "_ch#" to configure a specific channel.
  * A channel-specific property value will override an existing non-channel
  * value for the appropriate channel.
  * Please refer to the device documentation for additional details.
  */
 
 /* BCM566x/5x: MCU_CHN#_MODE.DRV_STR_0 */
 #define spn_MCU_DRV_STR0  "mcu_drv_str0"
 
 /* BCM566x/5x: MCU_CHN#_MODE.DRV_STR_1 */
 #define spn_MCU_DRV_STR1  "mcu_drv_str1"
 
 /* BCM566x/5x: MCU_CHN#_PAD_CTL.DATA_CLASS_2 */
 #define spn_MCU_PAD_DATA_CLASS2  "mcu_pad_data_class2"
 
 /* BCM566x/5x: MCU_CHN#_PAD_CTL.DATA_PAD_DRIVE */
 #define spn_MCU_PAD_DATA_DRIVE  "mcu_pad_data_drive"
 
 /* BCM566x/5x: MCU_CHN#_PAD_CTL.DATA_PAD_SLEW */
 #define spn_MCU_PAD_DATA_SLEW  "mcu_pad_data_slew"
 
 /* BCM566x/5x: MCU_CHN#_PAD_CTL.ADDR_CLASS_2 */
 #define spn_MCU_PAD_ADDR_CLASS2  "mcu_pad_addr_class2"
 
 /* BCM566x/5x: MCU_CHN#_PAD_CTL.ADDR_PAD_DRIVE */
 #define spn_MCU_PAD_ADDR_DRIVE  "mcu_pad_addr_drive"
 
 /* BCM566x/5x: MCU_CHN#_PAD_CTL.ADDR_PAD_SLEW */
 #define spn_MCU_PAD_ADDR_SLEW  "mcu_pad_addr_slew"
 
 /* BCM566x/5x: MCU_CHN#_DELAY_CTL.DQI_ADJ_DIR */
 #define spn_MCU_DELAY_DQI_ADJ_DIR  "mcu_delay_dqi_adj_dir"
 
 /* BCM566x/5x: MCU_CHN#_DELAY_CTL.DQI_ADJ_VAL */
 #define spn_MCU_DELAY_DQI_ADJ_VAL  "mcu_delay_dqi_adj_val"
 
 /* BCM566x/5x: MCU_CHN#_DELAY_CTL.ADDR_ADJ_DIR */
 #define spn_MCU_DELAY_ADDR_ADJ_DIR  "mcu_delay_addr_adj_dir"
 
 /* BCM566x/5x: MCU_CHN#_DELAY_CTL.ADDR_ADJ_VAL */
 #define spn_MCU_DELAY_ADDR_ADJ_VAL  "mcu_delay_addr_adj_val"
 
 /* Default speed that the port will initialize with */
 #define spn_PORT_INIT_SPEED  "port_init_speed"
 
 /* overwrite the default port max speed */
 #define spn_PORT_MAX_SPEED  "port_max_speed"
 
 /* Default duplex mode the port will initialize with */
 #define spn_PORT_INIT_DUPLEX  "port_init_duplex"
 
 /* Default local advertisement settings for a port */
 #define spn_PORT_INIT_ADV  "port_init_adv"
 
 /* Default auto negotiation state of the port */
 #define spn_PORT_INIT_AUTONEG  "port_init_autoneg"
 /*
  * PHY address of a port.
  * Used also to specify the MDIO address of non-switching interfaces, such as external tcams in the format port_phy_addr_ext_tcam#.
  * Format: port_phy_addr_logicalPort = mdio_addr
  * For example: port_phy_addr_ce0 = 0x10
  */
 #define spn_PORT_PHY_ADDR  "port_phy_addr"
 
 /* First part of a uniqe PHY identifier, if not specified in register */
 #define spn_PORT_PHY_ID0  "port_phy_id0"
 
 /* Second part of a uniqe PHY identifier, if not specified in register */
 #define spn_PORT_PHY_ID1  "port_phy_id1"
 
 /* Configures 3 additional MDIO addresses for the mux port with 8040 type phy */
 #define spn_PORT_PHY_ADDR1  "port_phy_addr1"
 
 /* MDIO Bus Property to select the MDIO access mechanism (CLAUSE22 / CLAUSE45) */
 #define spn_PORT_PHY_CLAUSE  "port_phy_clause"
 /*
  * This controls whether to precondition this port 
  * before probing of PHY on this port for 
  * applicable PHY devices, precondition(1)/not(0).
  */
 #define spn_PORT_PHY_PRECONDITION_BEFORE_PROBE  "port_phy_precondition_before_probe"
 
 /* Enable MAC to check 802.3 frame length field */
 #define spn_MAC_LENGTH_CHECK_ENABLE  "mac_length_check_enable"
 /*
  * L2 table is DMAed into memory to search for entries to delete
  * when no hardware assists are available.  DMA is done in smaller
  * parts to minimize memory use.  Must be port of 2.
  */
 #define spn_L2DELETE_CHUNKS  "l2delete_chunks"
 
 /* Size of chunks to read at once while iterating over VLAN XLATE memory */
 #define spn_VLANDELETE_CHUNKS  "vlandelete_chunks"
 /*
  * BCM5665 family filter sizes
  * The FE port filters on 5665/50/55 may be configured for two mask/rule sizes
  * 256 rules and 16 masks (default)
  * 128 rules and 24 masks
  * Use this to select the 128/24 configuration for the chip.
  */
 #define spn_FILTER_RESIZE  "filter_resize"
 /*
  * Spread the XQs across all CoSqs as dictated by the weight properties.
  * This will allow use of all CoSqs. However, if some CoSqs are later
  * disabled, the XQs allocated here to those disabled CoSQs will be
  * unavailable for use.
  * This property configures all CoSq identically.  To specify the value
  * for a single CoSq, use the suffix "_cos#".  A CoSq-specific value
  * will override an generic property value.
  */
 #define spn_MMU_XQ_WEIGHT  "mmu_xq_weight"
 /*
  * Configure per-XQ packet aging for the various CoSQs. The shortest age
  * allowed by H/W is 250 microseconds. The longest age allowed is 7.162
  * seconds (7162 msec). The maximum ratio between the longest age and
  * the shortest(nonzero) age is 7:2.
  * This property configures all CoSq identically.  To specify the value
  * for a single CoSq, use the suffix "_cos#".  A CoSq-specific value
  * will override an generic property value.
  */
 #define spn_MMU_XQ_AGING  "mmu_xq_aging"
 /*
  * On 568xx devices, the XPORT block defaults to XE ports.  Uncomment the
  * following line to change all ports to HG ports.  A specific bitmap
  * may be provided to select some XE and some HG ports, with the set
  * bits initialized to HG ports.  Note that HG and XE ports may be
  * exchanged through the bcm_port_encap_set API.
  */
 #define spn_PBMP_XPORT_XE  "pbmp_xport_xe"
 /*
  * Some BCM56xxx devices, such as the BCM568xx series, allow the XPORTs
  * to be configured as XE, HG, and GE ports.  XPORTs set in this bitmap
  * will be GE ports.
  */
 #define spn_PBMP_XPORT_GE  "pbmp_xport_ge"
 /*
  * Some 56xxx device allow certain ports to be configured as
  * cpri radio ports at boot up depending on the hardware capability.
  */
 #define spn_PBMP_XPORT_CPRI  "pbmp_xport_cpri"
 /*
  * Some 56xxx device allow certain ports to be configured as
  * roe ports.This indicates whether such ports support compression .
  */
 #define spn_PBMP_ROE_COMPRESSION  "pbmp_roe_compression"
 /*
  * Some 56xxx device allow certain ports to be classified as
  * roe backplane ports at boot up . These ports connects to the
  *  back plane network in radio ethernet solution
  */
 #define spn_PBMP_XPORT_ROE_BACKPLANE  "pbmp_xport_roe_backplane"
 /*
  * Some 56xxx device allow certain ports to be classified as
  * roe mcu ports at boot up. These ports connect to the muti 
  *  protocol control unit in an radio ethernet solution.
  */
 #define spn_PBMP_XPORT_ROE_MCU  "pbmp_xport_roe_mcu"
 /*
  * Some 56xxx device allow certain ports to be classified as
  * roe bbu ports at boot up. These ports  connects to
  * the base band unit in a radio ethernet solution
  */
 #define spn_PBMP_XPORT_ROE_BBU  "pbmp_xport_roe_bbu"
 /*
  * Some 56xxx device allow certain ports to be classified as
  * fronthaul ports at boot up. These ports connects to the
  *  front haul network in an radio ethernet solution
  */
 #define spn_PBMP_XPORT_ROE_FRONTHAUL  "pbmp_xport_roe_fronthaul"
 /*
  * Uncomment the following line instead to set all GE ports as regular
  * front panel Ethernet ports.
  */
 #define spn_PBMP_GPORT_STACK  "pbmp_gport_stack"
 /*
  * pbmp_loopback is used to specify if a HIGIG/HIGIG-LITE port is
  * configured as loopback port
  * Uncomment the following line instead to set all HIGIG/HIGIG-LITE ports as regular
  * front panel Ethernet ports.
  */
 #define spn_PBMP_LOOPBACK  "pbmp_loopback"
 
 /* Port bitmap for ports in oversubscribe mode */
 #define spn_PBMP_OVERSUBSCRIBE  "pbmp_oversubscribe"
 /*
  * Config to describe the system Linerate or Oversubscribe mode.
  * 0: Linerate only (default).
  * 1: Oversubscribe mode (all ports will be oversub).
  * 2: Mixed mode. Check device specification for applicability. Port bitmap specified via pbmp_oversubscribe.
  */
 #define spn_OVERSUBSCRIBE_MODE  "oversubscribe_mode"
 /*
  * Config per Physical Port for oversubscription mode.
  * 0: Linerate only(default)
  * 1: Oversubscribe mode. 
  * Oversubscribe mode per Physical port takes priority
  * over logical port oversubscribe Port bitmap.
  * This property should be used together
  * with the oversubscribtion mode.
  */
 #define spn_PORT_OVERSUBSCRIBE  "port_oversubscribe"
 /*
  * Config per device can support 25/50G Mixed Sister Speed port config.
  * 0: 25/50G mixed-sister port config disable per device(default).
  * 1: 25/50G mixed-sister port config enable per device.
  * This property should be used together
  * with the oversubscribe mode.
  */
 #define spn_OVERSUBSCRIBE_MIXED_SISTER_25_50_ENABLE  "oversubscribe_mixed_sister_25_50_enable"
 /*
  * Config the capability of speed group consolidation.
  * 0: indicate to disable the capability of speed group consolidation in OS mode(default).
  * 1: indicate to enable capability of speed group consolidation in OS mode.
  * This property should be used together with the oversubscribe mode.
  */
 #define spn_OVERSUB_SPEED_GROUP_CONSOLIDATION_ENABLE  "oversub_speed_group_consolidation_enable"
 /*
  * Port bitmap for ports in LinkPHY channelization mode
  * For BCM56450 the ports in blocks [27,32,33,34] and
  * [28,29,30,31] can be member of this port bitmap.
  * For example, to set ports [27,32,33,34] in LinkPHY
  * channelization mode set pbmp_linkphy=0x708000000
  */
 #define spn_PBMP_LINKPHY  "pbmp_linkphy"
 /*
  * Port bitmap for ports in LinkPHY channelization mode
  * supporting only one stream per subport for all its subports
  * For BCM56260. For example, to configure port 1 such that
  * all its subports will support only one stream set
  * pbmp_linkphy_one_stream_per_subport=0x00000002
  */
 #define spn_PBMP_LINKPHY_ONE_STREAM_PER_SUBPORT  "pbmp_linkphy_one_stream_per_subport"
 /*
  * Port bitmap for skipping SDK default LLS tree creation mode.
  * In this mode, the application must create a LLS tree for each port.
  * Note:On BCM56850/BCM56860, the creation of default LLS trees will be skipped
  * when port bitmap spn_PBMP_SKIP_DEFAULT_LLS is non-zero. User should
  * enable MMU traffic for each port with bcmPortControlMmuTrafficEnable if use this mode.
  */
 #define spn_PBMP_SKIP_DEFAULT_LLS  "pbmp_skip_default_lls"
 
 /* Command memory controls */
 #define spn_MEMCMD_TIMEOUT_USEC  "memcmd_timeout_usec"
 #define spn_MEMCMD_INTR_ENABLE  "memcmd_intr_enable"
 #define spn_IPFIX_INTR_ENABLE  "ipfix_intr_enable"
 #define spn_FLOW_TRACKER_INTR_ENABLE  "flow_tracker_intr_enable"
 #define spn_L2MOD_DMA_INTR_ENABLE  "l2mod_dma_intr_enable"
 /*
  * ER_SEER_CFG_NO_EXT
  * ER_SEER_CFG_L2_512_EXT
  * ER_SEER_CFG_LPM_256_EXT
  * ER_SEER_CFG_L4_192_EXT
  * ER_SEER_CFG_L4_96_EXT
  * ER_SEER_CFG_LPM_256_L4_128_EXT
  * ER_SEER_CFG_LPM_384_L4_64_EXT
  * ER_SEER_CFG_LPM_128_L4_64_EXT
  * ER_SEER_CFG_LPM_192_L4_32_EXT
  * ER_SEER_CFG_LPM_448_EXT
  * ER_SEER_CFG_LPM_896_EXT
  */
 #define spn_SEER_EXT_TABLE_CFG  "seer_ext_table_cfg"
 
 /* External TCAM type */
 #define spn_SEER_EXT_TCAM_SELECT  "seer_ext_tcam_select"
 
 /* All V6 */
 #define spn_SEER_HOST_HASH_TABLE_CFG  "seer_host_hash_table_cfg"
 
 /* All MYSTATION */
 #define spn_SEER_MVL_HASH_TABLE_CFG  "seer_mvl_hash_table_cfg"
 
 /* HSE tuning parameters generated by extt command */
 #define spn_SEER_HSE_EM_LATENCY7  "seer_hse_em_latency7"
 
 /* CSE tuning parameters generated by extt command */
 #define spn_SEER_CSE_EM_LATENCY7  "seer_cse_em_latency7"
 /*
  * 8704 and 8705 XFP clock
  * 8704 and 8705 can provide the clock for the XFPs (thus eliminating the need
  * for an external clock. By default we enable it, but if you are not using it,
  * it should be disabled.
  */
 #define spn_PHY_XFP_CLOCK  "phy_xfp_clock"
 /*
  * Per-port parameter indicating the only PHY is 56XXX SERDES directly
  * connected to a fiber module.  This is needed on boards which have
  * resistors configuration to bypass external 5434/5464.
  * SERDES is used automatically if no PHY is detected on the MDIO.
  */
 #define spn_PHY_56XXX  "phy_56xxx"
 
 /* Enable Loss Of Signal(LOS) function. 0 disable, 1 enable */
 #define spn_PHY_RX_LOS  "phy_rx_los"
 
 /* Invert PHYs LOS signal level. 0 not invert, 1 invert */
 #define spn_PHY_RX_LOS_INVERT  "phy_rx_los_invert"
 
 /* Enable the module absent signalling function. 0 disable, 1 enable */
 #define spn_PHY_MOD_ABS  "phy_mod_abs"
 
 /* Invert PHYs MOD_ABS signal level. 0 not invert, 1 invert */
 #define spn_PHY_MOD_ABS_INVERT  "phy_mod_abs_invert"
 /*
  * Enable module auto detection for devices that are able to detect
  * when a module is inserted or removed. 0 disable, 1 enable
  */
 #define spn_PHY_MOD_AUTO_DETECT  "phy_mod_auto_detect"
 #define spn_TCAM_RESET_USEC  "tcam_reset_usec"
 /*
  * On BCM5660x devices, track end-to-end flow control on 64 modules of
  * 16 ports, instead of 32 modules of 32 ports.
  */
 #define spn_E2E_64_MODULES  "e2e_64_modules"
 
 /* Timeout value in microseconds for BCM5660x search engine initialization */
 #define spn_SEER_INIT_TIMEOUT_USEC  "seer_init_timeout_usec"
 
 /* Control to disable parity messages */
 #define spn_PARITY_ENABLE  "parity_enable"
 
 /* Control to disable parity correction */
 #define spn_PARITY_CORRECTION  "parity_correction"
 
 /* Control to clear or restore(last value accumulated in s/w) counter on parity error */
 #define spn_PARITY_COUNTER_CLEAR  "parity_counter_clear"
 
 /* Set BCM5660x external packet buffer to 500 MHz instead of 600 MHz */
 #define spn_PLL600_SLOWCLK  "pll600_slowclk"
 
 /* For MCU Channel 0 only (0x2 for Channel 1 only) */
 #define spn_MCU_CHANNEL_BITMAP  "mcu_channel_bitmap"
 
 /* BCM5660x: MCU_CHN#_TIMING_32.TCRD */
 #define spn_MCU_TCRD  "mcu_tcrd"
 
 /* BCM5660x: MCU_CHN#_TIMING_32.TCWD */
 #define spn_MCU_TCWD  "mcu_tcwd"
 
 /* BCM5660x: MCU_CHN#_TIMING_32.TWL */
 #define spn_MCU_TWL  "mcu_twl"
 
 /* MCU tuning parameters generated by extt command */
 #define spn_MCU_DLL90_OFFSET_TX  "mcu_dll90_offset_tx"
 
 /* MCU tuning parameters generated by extt command */
 #define spn_MCU_DLL90_OFFSET3  "mcu_dll90_offset3"
 
 /* MCU tuning parameters generated by extt command */
 #define spn_MCU_DLL90_OFFSET2  "mcu_dll90_offset2"
 
 /* MCU tuning parameters generated by extt command */
 #define spn_MCU_DLL90_OFFSET1  "mcu_dll90_offset1"
 
 /* MCU tuning parameters generated by extt command */
 #define spn_MCU_DLL90_OFFSET0_QK  "mcu_dll90_offset0_qk"
 
 /* MCU tuning parameters generated by extt command */
 #define spn_MCU_DLL90_OFFSET_QKB  "mcu_dll90_offset_qkb"
 
 /* MCU tuning parameters generated by extt command */
 #define spn_MCU_OVRD_SM_EN  "mcu_ovrd_sm_en"
 
 /* MCU tuning parameters generated by extt command */
 #define spn_MCU_PHASE_SEL  "mcu_phase_sel"
 
 /* MCU tuning parameters generated by extt command */
 #define spn_MCU_SEL_EARLY2_3  "mcu_sel_early2_3"
 
 /* MCU tuning parameters generated by extt command */
 #define spn_MCU_SEL_EARLY1_3  "mcu_sel_early1_3"
 
 /* MCU tuning parameters generated by extt command */
 #define spn_MCU_SEL_EARLY2_2  "mcu_sel_early2_2"
 
 /* MCU tuning parameters generated by extt command */
 #define spn_MCU_SEL_EARLY1_2  "mcu_sel_early1_2"
 
 /* MCU tuning parameters generated by extt command */
 #define spn_MCU_SEL_EARLY2_1  "mcu_sel_early2_1"
 
 /* MCU tuning parameters generated by extt command */
 #define spn_MCU_SEL_EARLY1_1  "mcu_sel_early1_1"
 
 /* MCU tuning parameters generated by extt command */
 #define spn_MCU_SEL_EARLY2_0  "mcu_sel_early2_0"
 
 /* MCU tuning parameters generated by extt command */
 #define spn_MCU_SEL_EARLY1_0  "mcu_sel_early1_0"
 /*
  * This setting may be used to change the number of LPM entries caches
  * when performing traversals of the tables.  Increasing this number
  * uses more memory for increased speed.
  */
 #define spn_SEER_LPM_TRAVERSE_ENTRIES  "seer_lpm_traverse_entries"
 /*
  * The maximum number of MMU/MCU initialization failures allowed before
  * aborting on XGS devices with external packet buffers.
  */
 #define spn_MMU_RESET_TRIES  "mmu_reset_tries"
 /*
  * The number of MMU DLL lock checks performed to insure that the interface
  * is stable on XGS devices with external packet buffers.
  */
 #define spn_MMU_PLL_LOCK_TESTS  "mmu_pll_lock_tests"
 #define spn_MCU_ODT_IMP_ENABLE  "mcu_odt_imp_enable"
 
 /* HSE tuning parameters generated by extt command */
 #define spn_DDR72_DLL90_OFFSET_TX  "ddr72_dll90_offset_tx"
 
 /* HSE tuning parameters generated by extt command */
 #define spn_DDR72_DLL90_OFFSET3  "ddr72_dll90_offset3"
 
 /* HSE tuning parameters generated by extt command */
 #define spn_DDR72_DLL90_OFFSET2  "ddr72_dll90_offset2"
 
 /* HSE tuning parameters generated by extt command */
 #define spn_DDR72_DLL90_OFFSET1  "ddr72_dll90_offset1"
 
 /* HSE tuning parameters generated by extt command */
 #define spn_DDR72_DLL90_OFFSET0_QK  "ddr72_dll90_offset0_qk"
 
 /* HSE tuning parameters generated by extt command */
 #define spn_DDR72_DLL90_OFFSET_QKB  "ddr72_dll90_offset_qkb"
 
 /* HSE tuning parameters generated by extt command */
 #define spn_DDR72_OVRD_SM_EN  "ddr72_ovrd_sm_en"
 
 /* HSE tuning parameters generated by extt command */
 #define spn_DDR72_PHASE_SEL  "ddr72_phase_sel"
 
 /* HSE tuning parameters generated by extt command */
 #define spn_DDR72_SEL_EARLY2_3  "ddr72_sel_early2_3"
 
 /* HSE tuning parameters generated by extt command */
 #define spn_DDR72_SEL_EARLY1_3  "ddr72_sel_early1_3"
 
 /* HSE tuning parameters generated by extt command */
 #define spn_DDR72_SEL_EARLY2_2  "ddr72_sel_early2_2"
 
 /* HSE tuning parameters generated by extt command */
 #define spn_DDR72_SEL_EARLY1_2  "ddr72_sel_early1_2"
 
 /* HSE tuning parameters generated by extt command */
 #define spn_DDR72_SEL_EARLY2_1  "ddr72_sel_early2_1"
 
 /* HSE tuning parameters generated by extt command */
 #define spn_DDR72_SEL_EARLY1_1  "ddr72_sel_early1_1"
 
 /* HSE tuning parameters generated by extt command */
 #define spn_DDR72_SEL_EARLY2_0  "ddr72_sel_early2_0"
 
 /* HSE tuning parameters generated by extt command */
 #define spn_DDR72_SEL_EARLY1_0  "ddr72_sel_early1_0"
 
 /* CSE tuning parameters generated by extt command */
 #define spn_QDR36_DLL90_OFFSET_TX  "qdr36_dll90_offset_tx"
 
 /* CSE tuning parameters generated by extt command */
 #define spn_QDR36_DLL90_OFFSET_QK  "qdr36_dll90_offset_qk"
 
 /* CSE tuning parameters generated by extt command */
 #define spn_QDR36_DLL90_OFFSET_QKB  "qdr36_dll90_offset_qkb"
 
 /* CSE tuning parameters generated by extt command */
 #define spn_QDR36_OVRD_SM_EN  "qdr36_ovrd_sm_en"
 
 /* CSE tuning parameters generated by extt command */
 #define spn_QDR36_PHASE_SEL  "qdr36_phase_sel"
 
 /* CSE tuning parameters generated by extt command */
 #define spn_QDR36_SEL_EARLY2_1  "qdr36_sel_early2_1"
 
 /* CSE tuning parameters generated by extt command */
 #define spn_QDR36_SEL_EARLY1_1  "qdr36_sel_early1_1"
 
 /* CSE tuning parameters generated by extt command */
 #define spn_QDR36_SEL_EARLY2_0  "qdr36_sel_early2_0"
 
 /* CSE tuning parameters generated by extt command */
 #define spn_QDR36_SEL_EARLY1_0  "qdr36_sel_early1_0"
 
 /* BCAM tuning */
 #define spn_SEER_TUNNEL_SAM  "seer_tunnel_sam"
 
 /* Master device of shared external TCAM */
 #define spn_EXT_TCAM_SHARING_MASTER  "ext_tcam_sharing_master"
 
 /* Slave device of shared external TCAM */
 #define spn_EXT_TCAM_SHARING_SLAVE  "ext_tcam_sharing_slave"
 /*
  * The size in bytes of memory to be used when clearing a table using bulk
  * table operations.  The number of table entries cleared in one operation
  * will vary by table entry width.
  */
 #define spn_MEM_CLEAR_CHUNK_SIZE  "mem_clear_chunk_size"
 
 /* Clear tables using the fastest method supported by the device. */
 #define spn_MEM_CLEAR_HW_ACCELERATION  "mem_clear_hw_acceleration"
 
 /* Check for mem max override properties and reconfigure memories. */
 #define spn_MEM_CHECK_MAX_OVERRIDE  "mem_check_max_override"
 
 /* Check for mem no-cache override properties and avoid caching. */
 #define spn_MEM_CHECK_NOCACHE_OVERRIDE  "mem_check_nocache_override"
 /*
  * For BCM5660x devices, determines whether the L2 multicast port bitmap
  * should be stored within the L2 table, rather than in a separate table.
  * May be helpful when external memory is used to increase L2 resources.
  */
 #define spn_L2MC_IN_L2ENTRY  "l2mc_in_l2entry"
 
 /* 8705 PHY supports both LAN and WAN mode. The default setting is LAN mode. */
 #define spn_PHY_WAN_MODE  "phy_wan_mode"
 
 /* 8705 PHY reference clock input selection. This should be set to TRUE in WAN mode. */
 #define spn_PHY_XCLKSEL_OVRD  "phy_xclksel_ovrd"
 
 /* Invert PCS TX output to PMD. Supported only on BCM8705 PHY. */
 #define spn_PHY_TX_INVERT  "phy_tx_invert"
 
 /* Invert PCS RX output to PMD. Supported only on BCM8705 PHY. */
 #define spn_PHY_RX_INVERT  "phy_rx_invert"
 /*
  * BCM5651x and BCM5632x devices allow the L2 table to be reduced to a
  * smaller size.  This value will be rounded up to provide the maximum
  * table index corresponding to a table size which is a power of 2.
  */
 #define spn_L2_TABLE_SIZE  "l2_table_size"
 /*
  * BCM5651x and BCM5632x devices allow the L3 table to be reduced to a
  * smaller size.  This value will be rounded up to provide the maximum
  * table index corresponding to a table size which is a power of 2.
  */
 #define spn_L3_TABLE_SIZE  "l3_table_size"
 /*
  * BCM5651x and BCM5632x devices allow the STG table to be reduced to a
  * smaller size.  This value will be rounded up to provide the maximum
  * table index corresponding to a table size which is a power of 2.
  */
 #define spn_STG_TABLE_SIZE  "stg_table_size"
 
 /* VLAN ID to be reserved for RCPU traffic */
 #define spn_RCPU_VLAN  "rcpu_vlan"
 
 /* Use OOB (out of band) channel for sending/receiving rcpu packets */
 #define spn_RCPU_USE_OOB  "rcpu_use_oob"
 
 /* Channel number to use during OOB (out of band) sending/receiving RCPU packets */
 #define spn_RCPU_OOB_CHANNEL  "rcpu_oob_channel"
 /*
  * MAC driver/unit to use
  * rcpu_oob_channel
  * Valid ports on which RCPU packets can be received by slave device.
  */
 #define spn_RCPU_RX_PBMP  "rcpu_rx_pbmp"
 
 /* switch port connected to slave RCPU device. */
 #define spn_RCPU_PORT  "rcpu_port"
 
 /* RCPU master unit. This is unit which is used to inject pkts to slave rcpu device. */
 #define spn_RCPU_MASTER_UNIT  "rcpu_master_unit"
 
 /* modid assigned to a slave RCPU unit in the system */
 #define spn_RCPU_SLAVE_MODID  "rcpu_slave_modid"
 
 /* modid assigned to a master RCPU unit in the system */
 #define spn_RCPU_MASTER_MODID  "rcpu_master_modid"
 #define spn_RCPU_HIGIG_PORT  "rcpu_higig_port"
 
 /* Indication that a switch can be control through RCPU mechanism only */
 #define spn_RCPU_ONLY  "rcpu_only"
 
 /* Indication that RCPU unit is present on a device */
 #define spn_PCI2EB_OVERRIDE  "pci2eb_override"
 
 /* Set global default maximum number of entry moves for all dual hash tables */
 #define spn_DUAL_HASH_RECURSE_DEPTH  "dual_hash_recurse_depth"
 
 /* Set default maximum number of entry moves for dual hash L2 table */
 #define spn_DUAL_HASH_RECURSE_DEPTH_L2X  "dual_hash_recurse_depth_l2x"
 
 /* Set default maximum number of entry moves for dual hash VLAN table */
 #define spn_DUAL_HASH_RECURSE_DEPTH_VLAN  "dual_hash_recurse_depth_vlan"
 
 /* Set default maximum number of entry moves for dual hash MPLS table */
 #define spn_DUAL_HASH_RECURSE_DEPTH_MPLS  "dual_hash_recurse_depth_mpls"
 
 /* Set default maximum number of entry moves for dual hash egress VLAN table */
 #define spn_DUAL_HASH_RECURSE_DEPTH_EGRESS_VLAN  "dual_hash_recurse_depth_egress_vlan"
 
 /* Set default maximum number of entry moves for all dual hash L3 tables */
 #define spn_DUAL_HASH_RECURSE_DEPTH_L3X  "dual_hash_recurse_depth_l3x"
 
 /* Set default maximum number of entry moves for dual hash DNAT Pool table */
 #define spn_DUAL_HASH_RECURSE_DEPTH_DNAT_POOL  "dual_hash_recurse_depth_dnat_pool"
 
 /* Set default maximum number of entry moves for dual hash ING_VLAN_VP_MEMBERSHIP table */
 #define spn_DUAL_HASH_RECURSE_DEPTH_ING_VP_VLAN_MEMBER  "dual_hash_recurse_depth_ing_vp_vlan_member"
 
 /* Set default maximum number of entry moves for dual hash EGR_VLAN_VP_MEMBERSHIP table */
 #define spn_DUAL_HASH_RECURSE_DEPTH_EGR_VP_VLAN_MEMBER  "dual_hash_recurse_depth_egr_vp_vlan_member"
 
 /* Set global default maximum number of entry moves for all dual hash tables */
 #define spn_MULTI_HASH_RECURSE_DEPTH  "multi_hash_recurse_depth"
 
 /* Set default maximum number of entry moves for multi hash L2 table */
 #define spn_MULTI_HASH_RECURSE_DEPTH_L2  "multi_hash_recurse_depth_l2"
 
 /* Set default maximum number of entry moves for multi hash VLAN table */
 #define spn_MULTI_HASH_RECURSE_DEPTH_VLAN  "multi_hash_recurse_depth_vlan"
 
 /* Set default maximum number of entry moves for multi hash MPLS table */
 #define spn_MULTI_HASH_RECURSE_DEPTH_MPLS  "multi_hash_recurse_depth_mpls"
 
 /* Set default maximum number of entry moves for multi hash egress VLAN table */
 #define spn_MULTI_HASH_RECURSE_DEPTH_EGRESS_VLAN  "multi_hash_recurse_depth_egress_vlan"
 
 /* Set default maximum number of entry moves for all multi hash L3 tables */
 #define spn_MULTI_HASH_RECURSE_DEPTH_L3  "multi_hash_recurse_depth_l3"
 
 /* Set default maximum number of entry moves for all multi hash FPEM tables */
 #define spn_MULTI_HASH_RECURSE_DEPTH_EXACT_MATCH  "multi_hash_recurse_depth_exact_match"
 
 /* Set default maximum number of entry moves for all multi hash Vlan Translate 1 tables */
 #define spn_MULTI_HASH_RECURSE_DEPTH_VLAN_1  "multi_hash_recurse_depth_vlan_1"
 
 /* Set default maximum number of entry moves for all multi hash Vlan Translate 2 tables */
 #define spn_MULTI_HASH_RECURSE_DEPTH_VLAN_2  "multi_hash_recurse_depth_vlan_2"
 
 /* Set default maximum number of entry moves for all multi hash Egress Vlan Translate 1 tables */
 #define spn_MULTI_HASH_RECURSE_DEPTH_EGRESS_VLAN_1  "multi_hash_recurse_depth_egress_vlan_1"
 
 /* Set default maximum number of entry moves for all multi hash Egress Vlan Translate 2 tables */
 #define spn_MULTI_HASH_RECURSE_DEPTH_EGRESS_VLAN_2  "multi_hash_recurse_depth_egress_vlan_2"
 
 /* Set default maximum number of entry moves for all multi hash MPLS tables */
 #define spn_MULTI_HASH_RECURSE_DEPTH_MPLS  "multi_hash_recurse_depth_mpls"
 /*
  * If ipv6_lpm_128b_enable is enabled,
  * set to 1 to reserve equal percentage(TCAM[v4]:TCAM[v6]) of ALPM buckets for IPv6.
  */
 #define spn_L3_ALPM_IPV6_128B_BKT_RSVD  "l3_alpm_ipv6_128b_bkt_rsvd"
 /*
  * Enable ALPM for L3 Prefix routes. Set to 1 for parallel search mode, 2 for combined search mode.
  *  3 for TCAM/ALPM mode.
  */
 #define spn_L3_ALPM_ENABLE  "l3_alpm_enable"
 
 /* Enable flex counter support for ALPM. */
 #define spn_ALPM_FLEX_STAT_SUPPORT  "alpm_flex_stat_support"
 
 /* Enable IPv6 128b prefix LPM routes. */
 #define spn_IPV6_LPM_128B_ENABLE  "ipv6_lpm_128b_enable"
 
 /* Configure the number of 128b prefix LPM routes. */
 #define spn_NUM_IPV6_LPM_128B_ENTRIES  "num_ipv6_lpm_128b_entries"
 
 /* Mode of operation of the route table. */
 #define spn_L3_LPM_MODE  "l3_lpm_mode"
 
 /* Control the scalability of ECMP groups */
 #define spn_L3_MAX_ECMP_MODE  "l3_max_ecmp_mode"
 
 /* Enables the routing into and out of tunnels. */
 #define spn_RIOT_ENABLE  "riot_enable"
 
 /* Configure size of l3 interface memory in overlay layer. */
 #define spn_RIOT_OVERLAY_L3_INTF_MEM_SIZE  "riot_overlay_l3_intf_mem_size"
 
 /* Configure size of l3 egress memory in overlay layer. */
 #define spn_RIOT_OVERLAY_L3_EGRESS_MEM_SIZE  "riot_overlay_l3_egress_mem_size"
 
 /* Configure size of resilient hashing ECMP in overlay layer. */
 #define spn_RIOT_OVERLAY_ECMP_RESILIENT_HASH_SIZE  "riot_overlay_ecmp_resilient_hash_size"
 
 /* Percentage of per-port cells usable before flow control starts */
 #define spn_MMU_FLOW_PERCENT  "mmu_flow_percent"
 
 /* Number of simultaneous senders to each port for flow control purposes */
 #define spn_MMU_FLOW_FANIN  "mmu_flow_fanin"
 /*
  * Percentage of per-port/per-cos packets used before
  * red packets will be dropped
  */
 #define spn_MMU_RED_DROP_PERCENT  "mmu_red_drop_percent"
 /*
  * Percentage of per-port/per-cos packets used before
  * yellow packets will be dropped
  */
 #define spn_MMU_YELLOW_DROP_PERCENT  "mmu_yellow_drop_percent"
 /*
  * Per-port/per-cos static reserved limit.
  * Rounded up from bytes to next cell size.
  * Remaining cells are put in dynamic pool.
  * If 0, then mmu_static_percent is used.
  */
 #define spn_MMU_STATIC_BYTES  "mmu_static_bytes"
 /*
  * Percentage of per-port/per-cos cells to
  * use as static reserved limit.
  * Remaining cells are put in dynamic pool.
  * Only used if mmu_static_bytes is 0.
  */
 #define spn_MMU_STATIC_PERCENT  "mmu_static_percent"
 /*
  * (1536 * 2)
  * offset from dynamic cell set limits for
  * reset (enable) limits.
  * Rounded up from bytes to next cell size.
  */
 #define spn_MMU_RESET_BYTES  "mmu_reset_bytes"
 
 /* Non-stack port overcommit factor for dynamic pool */
 #define spn_MMU_OVERCOMMIT  "mmu_overcommit"
 
 /* Stack port overcommit factor for dynamic pool */
 #define spn_MMU_OVERCOMMIT_STACK  "mmu_overcommit_stack"
 /*
  * On BCM56601 C0 devices, the valid bit of the L3 IPMC table may be used
  * instead as a hit bit.  In such a case, an invalid entry is judged by
  * empty L2 and L3 port bitmaps.
  */
 #define spn_L3_IPMC_VALID_AS_HIT  "l3_ipmc_valid_as_hit"
 
 /* ESM SRAM tuning result generated by extt command */
 #define spn_EXT_SRAM_TUNING  "ext_sram_tuning"
 
 /* ESM SRAM tuning statistics generated by extt command */
 #define spn_EXT_SRAM_TUNING_STATS  "ext_sram_tuning_stats"
 
 /* ESM SRAM tuning statistics generated by extt2 command */
 #define spn_EXT_SRAM_TUNING2_STATS  "ext_sram_tuning2_stats"
 
 /* ESM SRAM tuning result generated by extt command */
 #define spn_EXT_SRAM_PVT  "ext_sram_pvt"
 
 /* ESM TCAM tuning result generated by extt command */
 #define spn_EXT_TCAM_TUNING  "ext_tcam_tuning"
 
 /* ESM TCAM tuning statistics generated by extt command */
 #define spn_EXT_TCAM_TUNING_STATS  "ext_tcam_tuning_stats"
 
 /* ESM TCAM tuning result generated by extt command */
 #define spn_EXT_TCAM_PVT  "ext_tcam_pvt"
 
 /* For ESM based L2 memory, transition to using hardware based replace mechanism after this threshold for the number of entries to process is reached. */
 #define spn_EXT_L2_USE_HARDWARE_REPLACE_THRESHOLD  "ext_l2_use_hardware_replace_threshold"
 
 /* Disable copying External L2 table into shadow copy */
 #define spn_EXT_L2_SHADOW_DISABLE  "ext_l2_shadow_disable"
 
 /* 72-bit(tr2)/80-bit(tr3) external L2 forward table */
 #define spn_EXT_L2_FWD_TABLE_SIZE  "ext_l2_fwd_table_size"
 
 /* 80-bit external wide L2 forward table */
 #define spn_EXT_L2_WIDE_FWD_TABLE_SIZE  "ext_l2_wide_fwd_table_size"
 
 /* 72-bit(tr2)/80-bit(tr3)/var(Arad) external IPv4 forward table */
 #define spn_EXT_IP4_FWD_TABLE_SIZE  "ext_ip4_fwd_table_size"
 
 /* 80-bit external IPv4 host forward table */
 #define spn_EXT_IP4_HOST_FWD_TABLE_SIZE  "ext_ip4_host_fwd_table_size"
 
 /* 80-bit external IPv4 host wide forward table */
 #define spn_EXT_IP4_HOST_WIDE_FWD_TABLE_SIZE  "ext_ip4_host_wide_fwd_table_size"
 
 /* 72-bit(tr2)/80-bit(tr3) external IPv6 64-bit prefix length forward table */
 #define spn_EXT_IP6U_FWD_TABLE_SIZE  "ext_ip6u_fwd_table_size"
 
 /* 144-bit(tr2)/160-bit(tr3)/var(Arad) external IPv6 128-bit/var(Arad) prefix length forward table */
 #define spn_EXT_IP6_FWD_TABLE_SIZE  "ext_ip6_fwd_table_size"
 
 /* 160-bit(tr3) external IPv6 128-bit host forward table */
 #define spn_EXT_IP6_HOST_FWD_TABLE_SIZE  "ext_ip6_host_fwd_table_size"
 
 /* 160-bit(tr3) external IPv6 128-bit host wide forward table */
 #define spn_EXT_IP6_HOST_WIDE_FWD_TABLE_SIZE  "ext_ip6_host_wide_fwd_table_size"
 
 /* 288-bit external L2 ACL table */
 #define spn_EXT_L2_ACL_TABLE_SIZE  "ext_l2_acl_table_size"
 
 /* 288-bit external L2 ACL table policy width(multiples of 35 bits). Allowed values are 1, 2, 3, 4, 6 */
 #define spn_EXT_L2_ACL_TABLE_POLICY_WIDTH  "ext_l2_acl_table_policy_width"
 
 /* Number of entries in the 288-bit external L2 ACL table to reserve for use as warm-start scache.  If a value is not specified, no entries are reserved, and the regular external scache is used for level-2 warm start.  If a value is specified, that number of entries are reserved for use as the level-2 warm start scache.  If the value specified is 0, an optimal number of reserved entries is calculated such that the reserved space will hold all usable entries. */
 #define spn_EXT_L2_ACL_TABLE_SCACHE_SIZE  "ext_l2_acl_table_scache_size"
 
 /* 288-bit external IPv4 ACL table */
 #define spn_EXT_IP4_ACL_TABLE_SIZE  "ext_ip4_acl_table_size"
 
 /* 288-bit external IPv4 ACL table policy width(multiples of 35 bits).Allowed values are 1, 2, 3, 4, 6 */
 #define spn_EXT_IP4_ACL_TABLE_POLICY_WIDTH  "ext_ip4_acl_table_policy_width"
 
 /* Number of entries in the 288-bit external IPv4 ACL table to reserve for use as warm-start scache.  If a value is not specified, no entries are reserved, and the regular external scache is used for level-2 warm start.  If a value is specified, that number of entries are reserved for use as the level-2 warm start scache.  If the value specified is 0, an optimal number of reserved entries is calculated such that the reserved space will hold all usable entries. */
 #define spn_EXT_IP4_ACL_TABLE_SCACHE_SIZE  "ext_ip4_acl_table_scache_size"
 
 /* 360-bit external IPv6 ACL table */
 #define spn_EXT_IP6S_ACL_TABLE_SIZE  "ext_ip6s_acl_table_size"
 
 /* 360-bit external IPv6 ACL table policy width(multiples of 35 bits). Allowed values are 1, 2, 3, 4, 6 */
 #define spn_EXT_IP6S_ACL_TABLE_POLICY_WIDTH  "ext_ip6s_acl_table_policy_width"
 
 /* Number of entries in the 360-bit external IPv6 ACL table to reserve for use as warm-start scache.  If a value is not specified, no entries are reserved, and the regular external scache is used for level-2 warm start.  If a value is specified, that number of entries are reserved for use as the level-2 warm start scache.  If the value specified is 0, an optimal number of reserved entries is calculated such that the reserved space will hold all usable entries. */
 #define spn_EXT_IP6S_ACL_TABLE_SCACHE_SIZE  "ext_ip6s_acl_table_scache_size"
 
 /* 432-bit external IPv6 ACL table */
 #define spn_EXT_IP6F_ACL_TABLE_SIZE  "ext_ip6f_acl_table_size"
 
 /* 432-bit external IPv6 ACL table policy width(multiples of 35 bits). Allowed values are 1, 2, 3, 4, 6 */
 #define spn_EXT_IP6F_ACL_TABLE_POLICY_WIDTH  "ext_ip6f_acl_table_policy_width"
 
 /* Number of entries in the 432-bit external IPv6 ACL table to reserve for use as warm-start scache.  If a value is not specified, no entries are reserved, and the regular external scache is used for level-2 warm start.  If a value is specified, that number of entries are reserved for use as the level-2 warm start scache.  If the value specified is 0, an optimal number of reserved entries is calculated such that the reserved space will hold all usable entries. */
 #define spn_EXT_IP6F_ACL_TABLE_SCACHE_SIZE  "ext_ip6f_acl_table_scache_size"
 
 /* 144-bit external L2 ACL table */
 #define spn_EXT_L2C_ACL_TABLE_SIZE  "ext_l2c_acl_table_size"
 
 /* 144-bit external L2 ACL table policy width(multiples of 35 bits). Allowed values are 1, 2, 3, 4, 6 */
 #define spn_EXT_L2C_ACL_TABLE_POLICY_WIDTH  "ext_l2c_acl_table_policy_width"
 
 /* Number of entries in the 144-bit external L2 ACL table to reserve for use as warm-start scache.  If a value is not specified, no entries are reserved, and the regular external scache is used for level-2 warm start.  If a value is specified, that number of entries are reserved for use as the level-2 warm start scache.  If the value specified is 0, an optimal number of reserved entries is calculated such that the reserved space will hold all usable entries. */
 #define spn_EXT_L2C_ACL_TABLE_SCACHE_SIZE  "ext_l2c_acl_table_scache_size"
 
 /* 144-bit external IPv4 ACL table */
 #define spn_EXT_IP4C_ACL_TABLE_SIZE  "ext_ip4c_acl_table_size"
 
 /* 144-bit external IPv4 ACL table policy width(multiples of 35 bits). Allowed values are 1, 2, 3, 4, 6 */
 #define spn_EXT_IP4C_ACL_TABLE_POLICY_WIDTH  "ext_ip4c_acl_table_policy_width"
 
 /* Number of entries in the 144-bit external IPv4 ACL table to reserve for use as warm-start scache.  If a value is not specified, no entries are reserved, and the regular external scache is used for level-2 warm start.  If a value is specified, that number of entries are reserved for use as the level-2 warm start scache.  If the value specified is 0, an optimal number of reserved entries is calculated such that the reserved space will hold all usable entries. */
 #define spn_EXT_IP4C_ACL_TABLE_SCACHE_SIZE  "ext_ip4c_acl_table_scache_size"
 
 /* 144-bit external IPv6 ACL table */
 #define spn_EXT_IP6C_ACL_TABLE_SIZE  "ext_ip6c_acl_table_size"
 
 /* 144-bit external IPv6 ACL table policy width(multiples of 35 bits). Allowed values are 1, 2, 3, 4, 6 */
 #define spn_EXT_IP6C_ACL_TABLE_POLICY_WIDTH  "ext_ip6c_acl_table_policy_width"
 
 /* Number of entries in the 144-bit external IPv6 ACL table to reserve for use as warm-start scache.  If a value is not specified, no entries are reserved, and the regular external scache is used for level-2 warm start.  If a value is specified, that number of entries are reserved for use as the level-2 warm start scache.  If the value specified is 0, an optimal number of reserved entries is calculated such that the reserved space will hold all usable entries. */
 #define spn_EXT_IP6C_ACL_TABLE_SCACHE_SIZE  "ext_ip6c_acl_table_scache_size"
 
 /* 432-bit external L2 + IPv4 ACL table */
 #define spn_EXT_L2IP4_ACL_TABLE_SIZE  "ext_l2ip4_acl_table_size"
 
 /* 432-bit external L2 + IPv4 ACL table policy width(multiples of 35 bits). Allowed values are 1, 2, 3, 4, 6 */
 #define spn_EXT_L2IP4_ACL_TABLE_POLICY_WIDTH  "ext_l2ip4_acl_table_policy_width"
 
 /* Number of entries in the 432-bit external L2 + IPv4 ACL table to reserve for use as warm-start scache.  If a value is not specified, no entries are reserved, and the regular external scache is used for level-2 warm start.  If a value is specified, that number of entries are reserved for use as the level-2 warm start scache.  If the value specified is 0, an optimal number of reserved entries is calculated such that the reserved space will hold all usable entries. */
 #define spn_EXT_L2IP4_ACL_TABLE_SCACHE_SIZE  "ext_l2ip4_acl_table_scache_size"
 
 /* 432-bit external L2 + IPv6 ACL table */
 #define spn_EXT_L2IP6_ACL_TABLE_SIZE  "ext_l2ip6_acl_table_size"
 
 /* 432-bit external L2 + IPv6 ACL table policy width(multiples of 35 bits). Allowed values are 1, 2, 3, 4, 6 */
 #define spn_EXT_L2IP6_ACL_TABLE_POLICY_WIDTH  "ext_l2ip6_acl_table_policy_width"
 
 /* Number of entries in the 432-bit external L2 + IPv6 ACL table to reserve for use as warm-start scache.  If a value is not specified, no entries are reserved, and the regular external scache is used for level-2 warm start.  If a value is specified, that number of entries are reserved for use as the level-2 warm start scache.  If the value specified is 0, an optimal number of reserved entries is calculated such that the reserved space will hold all usable entries. */
 #define spn_EXT_L2IP6_ACL_TABLE_SCACHE_SIZE  "ext_l2ip6_acl_table_scache_size"
 
 /* 80-bit external ACL table */
 #define spn_EXT_ACL80_TABLE_SIZE  "ext_acl80_table_size"
 
 /* 160-bit external ACL table */
 #define spn_EXT_ACL160_TABLE_SIZE  "ext_acl160_table_size"
 
 /* 320-bit external ACL table */
 #define spn_EXT_ACL320_TABLE_SIZE  "ext_acl320_table_size"
 
 /* 480-bit external ACL table */
 #define spn_EXT_ACL480_TABLE_SIZE  "ext_acl480_table_size"
 
 /* External L2 forward table is duplicated */
 #define spn_EXT_L2_TABLE_DUPLICATED  "ext_l2_table_duplicated"
 
 /* External IPv4 forward table is duplicated */
 #define spn_EXT_IP4_TABLE_DUPLICATED  "ext_ip4_table_duplicated"
 
 /* External IPV6 64 bit prefix forward table is duplicated */
 #define spn_EXT_IP6U_TABLE_DUPLICATED  "ext_ip6u_table_duplicated"
 
 /* External IPV6 128 bit forward table is duplicated */
 #define spn_EXT_IP6_TABLE_DUPLICATED  "ext_ip6_table_duplicated"
 
 /* ESM TCAM operating frequency */
 #define spn_EXT_TCAM_FREQ  "ext_tcam_freq"
 
 /* ESM TCAM mode, 0 for 6 cycles per packet, 1 for 4 cycles per packet */
 #define spn_EXT_TCAM_MODE  "ext_tcam_mode"
 #define spn_EXT_TCAM_DEV_TYPE  "ext_tcam_dev_type"
 
 /* Number of TCAM banks in the ESM TCAM module */
 #define spn_EXT_TCAM_BANKS  "ext_tcam_banks"
 
 /* ESM SRAM operating frequency */
 #define spn_EXT_SRAM_FREQ  "ext_sram_freq"
 
 /* ESM SRAM mode, 0 for 1.5 clock latency, 1 for 2 clock latency */
 #define spn_EXT_SRAM_MODE  "ext_sram_mode"
 #define spn_EXT_SRAM_SPEED  "ext_sram_speed"
 #define spn_EXT_SRAM0_PRESENT  "ext_sram0_present"
 #define spn_EXT_SRAM1_PRESENT  "ext_sram1_present"
 /*
  * External associated data mode:
  * 1: 250 MHz, L2 table in ES0
  * 2: 250 MHz, L2 table in ES1
  * 3: 250 MHz, L3 table in ES0
  * 4: 250 MHz, L3 table in ES1
  * 5: 250 MHz, L2 and L3 table in ES0
  * 6: 250 MHz, L2 and L3 table in ES1
  * 7: 334 MHz, ACL table in ES0
  * 8: 334 MHz, ACL table in ES1
  * 9: 250 MHz, ACL table in both ES0 and ES1
  * 10: 250 MHz, L2 and ACL table in both ES0 and ES1
  * 11: 250 MHz, L3 and ACL table in both ES0 and ES1
  * 12: 334 MHz, L2 and L3 and ACL table in both ES0 and ES1
  */
 #define spn_EXT_AD_MODE  "ext_ad_mode"
 /*
  * External IPv6 forwarding search key selection
  * 0 for 72-bit, 1 for 144-bit
  */
 #define spn_EXT_IP6_FWD_KEY  "ext_ip6_fwd_key"
 /*
  * External ACL search key selection for L2 packet
  * 0 for disable, 1 for 288-bit, 2 for 144-bit
  */
 #define spn_EXT_L2_ACL_KEY  "ext_l2_acl_key"
 /*
  * External ACL search key selection for IPv4 packet
  * 0 for disable, 1 for 288-bit, 2 for 144-bit, 3 for using both L2 and IP4 key,
  * 4 for using L2 key
  */
 #define spn_EXT_IP4_ACL_KEY  "ext_ip4_acl_key"
 /*
  * External ACL search key selection for IPV6 packet
  * 0 for disable, 1 for 360-bit, 2 for 432-bit, 3 for 144-bit,
  * 4 for using both L2 and IP6 key, 5 for using L2 key
  */
 #define spn_EXT_IP6_ACL_KEY  "ext_ip6_acl_key"
 /*
  * On BCM5662x devices, enable external TCAM lookup on XPORT block
  * (back-panel ports) instead of XGPORT block (front-panel ports)
  */
 #define spn_EXT_LOOKUP_ON_XPORT  "ext_lookup_on_xport"
 
 /* External IPv4 Unicast with RPF forward table size */
 #define spn_EXT_IP4_UC_RPF_FWD_TABLE_SIZE  "ext_ip4_uc_rpf_fwd_table_size"
 
 /* External IPv4 Multicast forward table size */
 #define spn_EXT_IP4_MC_FWD_TABLE_SIZE  "ext_ip4_mc_fwd_table_size"
 
 /* External IPv6 Unicast with RPF forward table size */
 #define spn_EXT_IP6_UC_RPF_FWD_TABLE_SIZE  "ext_ip6_uc_rpf_fwd_table_size"
 
 /* External IPv6 Multicast forward table size */
 #define spn_EXT_IP6_MC_FWD_TABLE_SIZE  "ext_ip6_mc_fwd_table_size"
 
 /* External Trill Unicast forward table size */
 #define spn_EXT_TRILL_UC_FWD_TABLE_SIZE  "ext_trill_uc_fwd_table_size"
 
 /* External Trill Multicast forward table size */
 #define spn_EXT_TRILL_MC_FWD_TABLE_SIZE  "ext_trill_mc_fwd_table_size"
 /*
  * To enable/disable the SGMII Slave Autodetect function
  * 0x0 = Disable SGMII Slave Auto-detect function
  * 0x1 = Enable SGMII Slave Auto-detect function
  */
 #define spn_EXT_PHY_AUTODETECT_EN  "ext_phy_autodetect_en"
 /*
  * Select Fiber Interface when SGMII Slave Autodetect is disabled
  * 0x0 = 1000Base-X, 0x1 = 100Base-FX, 0x2 = SGMII-Slave.
  */
 #define spn_EXT_PHY_SERDES_FIBER_IFACE  "ext_phy_serdes_fiber_iface"
 
 /* External Mpls label forward table size */
 #define spn_EXT_MPLS_FWD_TABLE_SIZE  "ext_mpls_fwd_table_size"
 
 /* External coupling Mpls label forward table size */
 #define spn_EXT_COUP_MPLS_FWD_TABLE_SIZE  "ext_coup_mpls_fwd_table_size"
 
 /* External Transparent P2P mim (Mac in Mac) forward table size */
 #define spn_EXT_TP2P_MIM_FWD_TABLE_SIZE  "ext_tp2p_mim_fwd_table_size"
 
 /* External Transparent P2P mpls forward table size */
 #define spn_EXT_TP2P_MPLS_FWD_TABLE_SIZE  "ext_tp2p_mpls_fwd_table_size"
 
 /* External Transparent P2P vlan forward table size */
 #define spn_EXT_TP2P_VLAN_FWD_TABLE_SIZE  "ext_tp2p_vlan_fwd_table_size"
 /*
  * Enable SGMII autonegotiation between the serdes and PHY if the 
  * serdes supports SGMII autonegotiation.
  */
 #define spn_PHY_SGMII_AUTONEG  "phy_sgmii_autoneg"
 
 /* Priority assigned to CoS number 0 on a remote unit in RCPU system */
 #define spn_RCPU_DOT1PRI_COS0  "rcpu_dot1pri_cos0"
 
 /* Priority assigned to CoS number 1 on a remote unit in RCPU system */
 #define spn_RCPU_DOT1PRI_COS1  "rcpu_dot1pri_cos1"
 
 /* Priority assigned to CoS number 2 on a remote unit in RCPU system */
 #define spn_RCPU_DOT1PRI_COS2  "rcpu_dot1pri_cos2"
 
 /* Priority assigned to CoS number 3 on a remote unit in RCPU system */
 #define spn_RCPU_DOT1PRI_COS3  "rcpu_dot1pri_cos3"
 
 /* Priority assigned to CoS number 4 on a remote unit in RCPU system */
 #define spn_RCPU_DOT1PRI_COS4  "rcpu_dot1pri_cos4"
 
 /* Priority assigned to CoS number 5 on a remote unit in RCPU system */
 #define spn_RCPU_DOT1PRI_COS5  "rcpu_dot1pri_cos5"
 
 /* Priority assigned to CoS number 6 on a remote unit in RCPU system */
 #define spn_RCPU_DOT1PRI_COS6  "rcpu_dot1pri_cos6"
 
 /* Priority assigned to CoS number 7 on a remote unit in RCPU system */
 #define spn_RCPU_DOT1PRI_COS7  "rcpu_dot1pri_cos7"
 
 /* Module Header Traffic Class value for CoS number 0 */
 #define spn_RCPU_MH_TC_COS0  "rcpu_mh_tc_cos0"
 
 /* Module Header Traffic Class value for CoS number 1 */
 #define spn_RCPU_MH_TC_COS1  "rcpu_mh_tc_cos1"
 
 /* Module Header Traffic Class value for CoS number 2 */
 #define spn_RCPU_MH_TC_COS2  "rcpu_mh_tc_cos2"
 
 /* Module Header Traffic Class value for CoS number 3 */
 #define spn_RCPU_MH_TC_COS3  "rcpu_mh_tc_cos3"
 
 /* Module Header Traffic Class value for CoS number 4 */
 #define spn_RCPU_MH_TC_COS4  "rcpu_mh_tc_cos4"
 
 /* Module Header Traffic Class value for CoS number 5 */
 #define spn_RCPU_MH_TC_COS5  "rcpu_mh_tc_cos5"
 
 /* Module Header Traffic Class value for CoS number 6 */
 #define spn_RCPU_MH_TC_COS6  "rcpu_mh_tc_cos6"
 
 /* Module Header Traffic Class value for CoS number 7 */
 #define spn_RCPU_MH_TC_COS7  "rcpu_mh_tc_cos7"
 
 /* CPU Traffic Class to be added to the remote CPU packet for CoS number 0 */
 #define spn_RCPU_CPU_TC_COS0  "rcpu_cpu_tc_cos0"
 
 /* CPU Traffic Class to be added to the remote CPU packet for CoS number 1 */
 #define spn_RCPU_CPU_TC_COS1  "rcpu_cpu_tc_cos1"
 
 /* CPU Traffic Class to be added to the remote CPU packet for CoS number 2 */
 #define spn_RCPU_CPU_TC_COS2  "rcpu_cpu_tc_cos2"
 
 /* CPU Traffic Class to be added to the remote CPU packet for CoS number 3 */
 #define spn_RCPU_CPU_TC_COS3  "rcpu_cpu_tc_cos3"
 
 /* CPU Traffic Class to be added to the remote CPU packet for CoS number 4 */
 #define spn_RCPU_CPU_TC_COS4  "rcpu_cpu_tc_cos4"
 
 /* CPU Traffic Class to be added to the remote CPU packet for CoS number 5 */
 #define spn_RCPU_CPU_TC_COS5  "rcpu_cpu_tc_cos5"
 
 /* CPU Traffic Class to be added to the remote CPU packet for CoS number 6 */
 #define spn_RCPU_CPU_TC_COS6  "rcpu_cpu_tc_cos6"
 
 /* CPU Traffic Class to be added to the remote CPU packet for CoS number 7 */
 #define spn_RCPU_CPU_TC_COS7  "rcpu_cpu_tc_cos7"
 
 /* CPU queue ID to be used for RCPU packets */
 #define spn_RCPU_CPU_QUEUE  "rcpu_cpu_queue"
 
 /* Pick up the Module Header SRC_PID value from the PBE bus for RCPU packets */
 #define spn_RCPU_MH_SRC_PID_ENABLE  "rcpu_mh_src_pid_enable"
 
 /* Add CPU Traffic Class to the RCPU packet */
 #define spn_RCPU_MH_CPU_COS_ENABLE  "rcpu_mh_cpu_cos_enable"
 
 /* Add Module Header Traffic Class to the RCPU packet */
 #define spn_RCPU_MH_TC_MAP_ENABLE  "rcpu_mh_tc_map_enable"
 
 /* CoS Priority is enable on RCPU packet */
 #define spn_RCPU_DOT1PRI_MAP_ENABLE  "rcpu_dot1pri_map_enable"
 /*
  * On BCM5651x devices, select which of the 10G ports should be run in
  * single-lane serdes mode at 1/4 speed.  This bitmap consists of four
  * bits corresponding to the 10G ports.
  */
 #define spn_LMD_ENABLE_PBMP  "lmd_enable_pbmp"
 
 /* Number of IPFIX export entries allocated for the FIFO DMA host buffer */
 #define spn_IPFIX_HOSTBUF_SIZE  "ipfix_hostbuf_size"
 
 /* IPFIX export fifo thread priorities; 0 is highest and 255 is lowest */
 #define spn_IPFIX_THREAD_PRI  "ipfix_thread_pri"
 
 /* Set the Receive Status Vector (RSV) mask for the Unimac */
 #define spn_GPORT_RSV_MASK  "gport_rsv_mask"
 
 /* Enable post initialization for FE ports on BCM56024 and BCM56018 */
 #define spn_POST_INIT_ENABLE  "post_init_enable"
 
 /* Device that can support more than 32 ports per single modid will operate in configuration where all ports are mapped to the base modid */
 #define spn_MODULE_64PORTS  "module_64ports"
 
 /* Configure the number of module id used by the device */
 #define spn_MODULE_NUM_MODIDS  "module_num_modids"
 
 /* All API will return port numbers in GPORT encodings */
 #define spn_GPORT  "bcm_use_gport"
 /*
  * Multicast ranges
  * The Higig2 header format concatenates the broadcast, multicast, and
  * IP multicast indices into one generic multicast index.  The mapping
  * between the individual indices and the combined index is specified by
  * these.  The default values are indicated.
  * This value sets the allowed range of broadcast indices in the Higig2
  * header for stack ports.
  */
 #define spn_HIGIG2_MULTICAST_VLAN_RANGE  "higig2_multicast_vlan_range"
 /*
  * Multicast ranges
  * This value sets the allowed range of multicast indices in the Higig2
  * header for stack ports.
  */
 #define spn_HIGIG2_MULTICAST_L2_RANGE  "higig2_multicast_l2_range"
 /*
  * Multicast ranges
  * This value sets the allowed range of IP multicast indices in the Higig2
  * header for stack ports.
  */
 #define spn_HIGIG2_MULTICAST_L3_RANGE  "higig2_multicast_l3_range"
 
 /* Make all HG ports default to HiGig2. */
 #define spn_HIGIG2_HDR_MODE  "higig2_hdr_mode"
 /*
  * Used to select gport node or child of gport node for configuring burst for
  * minimum or maximum rate using bcm_cosq_control_set/bcm_cosq_control_get.
  * Set to 1, Burst will be configured for child of gport node.
  * Set to 0 (default),Burst will be configured for gport node.
  */
 #define spn_COSQ_CONTROL_BURST_NODE_SELECT  "cosq_control_burst_node_select"
 #define spn_BIST_ENABLE  "bist_enable"
 
 /* Define number of rows of external ram (ddr) devices used */
 #define spn_EXT_RAM_ROWS  "ext_ram_rows"
 
 /* Used by DNX devices only */
 #define spn_DISCARD_MTU_SIZE  "discard_mtu_size"
 /*
  * In BCM568xx and BCM567xx devices, some L2 and L3 multicast
  * information is stored in a shared resource.  This value describes
  * the number of resource entries devoted to L2 multicast.
  */
 #define spn_MULTICAST_L2_RANGE  "multicast_l2_range"
 /*
  * In BCM568xx and BCM567xx devices, some L2 and L3 multicast
  * information is stored in a shared resource.  This value describes
  * the number of resource entries devoted to IP multicast.
  */
 #define spn_MULTICAST_L3_RANGE  "multicast_l3_range"
 
 /* Destination (and CUD) encoding in the ingress Multicast table. */
 #define spn_MULTICAST_DESTINATION_ENCODING  "multicast_destination_encoding"
 
 /* Enable/Disable SLAM DMA */
 #define spn_TSLAM_DMA_ENABLE  "tslam_dma_enable"
 
 /* Enable/Disable TABLE DMA */
 #define spn_TABLE_DMA_ENABLE  "table_dma_enable"
 
 /* Enable/Disable CCM DMA */
 #define spn_CCM_DMA_ENABLE  "ccm_dma_enable"
 /*
  * The rate divisor/dividend properties allow a specific function clock
  * to be adjusted with respect to the device core clock.  If the core
  * clock speed is altered from the default, then use these settings to
  * tune the function clock to the required frequency range.
  * The calculation is (core clock) * dividend / divisor = (function clock).
  */
 
 /* I2C clock rate divisor */
 #define spn_RATE_I2C_DIVISOR  "rate_i2c_divisor"
 
 /* I2C clock rate dividend */
 #define spn_RATE_I2C_DIVIDEND  "rate_i2c_dividend"
 
 /* Statistics DMA clock rate divisor */
 #define spn_RATE_STDMA_DIVISOR  "rate_stdma_divisor"
 
 /* Statistics DMA clock rate dividend */
 #define spn_RATE_STDMA_DIVIDEND  "rate_stdma_dividend"
 
 /* External MDIO clock rate divisor */
 #define spn_RATE_EXT_MDIO_DIVISOR  "rate_ext_mdio_divisor"
 
 /* External MDIO clock rate dividend */
 #define spn_RATE_EXT_MDIO_DIVIDEND  "rate_ext_mdio_dividend"
 
 /* Internal MDIO clock rate divisor */
 #define spn_RATE_INT_MDIO_DIVISOR  "rate_int_mdio_divisor"
 
 /* Internal MDIO clock rate dividend */
 #define spn_RATE_INT_MDIO_DIVIDEND  "rate_int_mdio_dividend"
 
 /* External MDIO clock rate divisor during f/w download */
 #define spn_RATE_EXT_DOWNLOAD_MDIO_DIVISOR  "rate_ext_download_mdio_divisor"
 
 /* External MDIO clock rate dividend during f/w download */
 #define spn_RATE_EXT_DOWNLOAD_MDIO_DIVIDEND  "rate_ext_download_mdio_dividend"
 /*
  * Specifiers the priority
  * of the OAM thread
  */
 #define spn_BCM_OAM_THREAD_PRI  "bcm_oam_thread_pri"
 
 /* Specifies the port bitmap of the ports on which system snake should be skipped. */
 #define spn_SS_IGNORE_PBMP  "ss_ignore_pbmp"
 /*
  * On BCM5682x, BCM5672x and BCM56960 devices, some of the switching logic
  * may be skipped to decrease traffic latency.
  * On BCM5682x and BCM5672x, the three modes available are:
  * 0 - normal operation
  * 1 - Skip L3 switch logic
  * 2 - Skip L3 and FP switch logic
  * On BCM56960, the switch latency bypass modes availabe are:
  * 0 - normal operation
  * 1 - balanced latency L2 + L3
  * 2 - low latency L2
  * 3 - EFP Bypass
  */
 #define spn_SWITCH_BYPASS_MODE  "switch_bypass_mode"
 /*
  * Use a bulk memory operation when writing multiple table entries
  * in the CLI.
  */
 #define spn_DIAG_SHELL_USE_SLAM  "diag_shell_use_slam"
 #define spn_RLINK_L2_REMOTE_MAX  "rlink_l2_remote_max"
 #define spn_RLINK_L2_LOCAL_MAX  "rlink_l2_local_max"
 #define spn_RLINK_LINK_REMOTE_MAX  "rlink_link_remote_max"
 #define spn_RLINK_LINK_LOCAL_MAX  "rlink_link_local_max"
 #define spn_RLINK_AUTH_REMOTE_MAX  "rlink_auth_remote_max"
 #define spn_RLINK_AUTH_LOCAL_MAX  "rlink_auth_local_max"
 #define spn_RLINK_RX0_REMOTE_MAX  "rlink_rx0_remote_max"
 #define spn_RLINK_RX1_REMOTE_MAX  "rlink_rx1_remote_max"
 #define spn_RLINK_RX2_REMOTE_MAX  "rlink_rx2_remote_max"
 #define spn_RLINK_RX3_REMOTE_MAX  "rlink_rx3_remote_max"
 #define spn_RLINK_RX4_REMOTE_MAX  "rlink_rx4_remote_max"
 #define spn_RLINK_RX5_REMOTE_MAX  "rlink_rx5_remote_max"
 #define spn_RLINK_RX6_REMOTE_MAX  "rlink_rx6_remote_max"
 #define spn_RLINK_RX7_REMOTE_MAX  "rlink_rx7_remote_max"
 
 /* Specifies the max number of queued notifications in server side */
 #define spn_RLINK_OAM_REMOTE_MAX  "rlink_oam_remote_max"
 
 /* Specifies the max number of queued notifications in client side */
 #define spn_RLINK_OAM_LOCAL_MAX  "rlink_oam_local_max"
 /*
  * Enable diag shell port mapping. Port names will be assigned in
  * dport order, and the BCM shell will list multiple ports in
  * dport order regardless of the internal port numbering.
  */
 #define spn_DPORT_MAP_ENABLE  "dport_map_enable"
 /*
  * Port names for each port type (fe, ge, etc.) will increment
  * by one starting at zero, e.g. if a switch has four xe ports
  * with dport numbers 24, 25, 26, and 27, they will be named
  * xe0, xe1, xe2, and xe3. In non-indexed mode the ports would
  * be named xe24, xe25, xe26, and xe27.
  */
 #define spn_DPORT_MAP_INDEXED  "dport_map_indexed"
 /*
  * Traditionally, specifying a raw number instead of a port name
  * in the diag shell will be parsed as if port numbers are counted
  * from 1 up to the number of enabled ports. Typically this would
  * mean that for a gigabit switch, port 1 would correspond to ge0,
  * and so forth. Setting this flag causes raw port numbers to be
  * parsed as internal port numbers.
  */
 #define spn_DPORT_MAP_DIRECT  "dport_map_direct"
 
 /* Map dport number <dport> to internal port number <port>. dport_map_port_<port>=<dport> */
 #define spn_DPORT_MAP_PORT  "dport_map_port"
 /*
  * Interval (in usecs) at which the port monitor thread will run.
  * The port monitor can be used to handle workarounds which are
  * required only with specific equipment configurations.
  */
 #define spn_PORTMON_INTERVAL  "portmon_interval"
 /*
  * Select whether to always attach the corresponding Serdes shadow
  * driver for Raptor and Raven devices. Note that when deciding
  * which driver to attach, MDIO accesses are also verified independently
  * and checked for corruption. If corruption is detected, the
  * shadow driver is attached regardless of this property.
  * To always attach the shadow driver for a port:
  * serdes_shadow_driver_<port>=1
  */
 #define spn_SERDES_SHADOW_DRIVER  "serdes_shadow_driver"
 /*
  * Configure a BCM56725 device for 16-16G ports, instead of the default
  * 8-21G + 4-16G ports
  */
 #define spn_BCM56725_16X16  "bcm56725_16x16"
 /*
  * Configure a BCM56822 device for 8-16G + 12-10G + 4-1G ports, instead
  * of the default 4-21G + 2-16G + 12-10G + 4-1G ports
  */
 #define spn_BCM56822_8X16  "bcm56822_8x16"
 /*
  * Configure a BCM56821 device for 20-12G + 4-1G ports, instead
  * of the default 8-16G + 12-10G + 4-1G ports
  */
 #define spn_BCM56821_20X12  "bcm56821_20x12"
 
 /* L2 Caching of BPDU MAC addresses will be turned off */
 #define spn_SKIP_L2_USER_ENTRY  "skip_L2_USER_ENTRY"
 
 /* Enable Bigmac and Unimac on the XGPORT blocks of BCM56626 and BCM56628 */
 #define spn_FLEX_XGPORT  "flex_xgport"
 
 /* Enable the 40GE mode of BCM56629 */
 #define spn_BCM56629_40GE  "bcm56629_40ge"
 
 /* Enable the 28GE and 7x10G Higig mode of BCM56639 */
 #define spn_BCM56639_28G_7X10  "bcm56639_28g_7x10"
 
 /* Enable the 8x12G Higig mode (with loopback) of BCM56638 */
 #define spn_BCM56638_8X12  "bcm56638_8x12"
 
 /* Enable the 4x12G and 2x24G Higig mode (with loopback) of BCM56638 */
 #define spn_BCM56638_4X12_2X24  "bcm56638_4x12_2x24"
 
 /* Enable the 24GE and 6x12G Higig mode (with loopback) of BCM56636 */
 #define spn_BCM56636_24G_6X12  "bcm56636_24g_6x12"
 
 /* Enable the 24GE and 2x12G Higig and 2x24G Higig mode (with loopback) of BCM56636 */
 #define spn_BCM56636_2X12_2X24  "bcm56636_2x12_2x24"
 
 /* Enable the 48GE and 4x12G Higig mode (with loopback) of BCM56634 */
 #define spn_BCM56634_48G_4X12  "bcm56634_48g_4x12"
 
 /* Enable the 48GE and 2x24G Higig mode (with loopback) of BCM56634 */
 #define spn_BCM56634_48G_2X24  "bcm56634_48g_2x24"
 
 /* Enable the 48GE and 4x12G Higig mode (with loopback) of BCM56538 */
 #define spn_BCM56538_48G_4X12  "bcm56538_48g_4x12"
 
 /* Enable the 48GE and 2x24G Higig mode (with loopback) of BCM56538 */
 #define spn_BCM56538_48G_2X24  "bcm56538_48g_2x24"
 
 /* Enable the 24GE and 2x12G Higig and 2x24G Higig mode (with loopback) of BCM56630 */
 #define spn_BCM56630_2X12_2X24  "bcm56630_2x12_2x24"
 
 /* Enable the 24GE and 2x12G Higig and 2x24G Higig mode (with loopback) of BCM56521 */
 #define spn_BCM56521_2X12_2X24  "bcm56521_2x12_2x24"
 
 /* Enable the 24GE and 2x12G Higig and 2x24G Higig mode (with loopback) of BCM56524 */
 #define spn_BCM56524_2X12_2X24  "bcm56524_2x12_2x24"
 
 /* Enable the 24GE and 2x12G Higig and 2x24G Higig mode (with loopback) of BCM56534 */
 #define spn_BCM56534_2X12_2X24  "bcm56534_2x12_2x24"
 
 /* Enable the 28GE and 2x12G Higig and 4x16G Higig mode (with loopback) of BCM56526 */
 #define spn_BCM56526_2X12_4X16  "bcm56526_2x12_4x16"
 #define spn_BCM5614X_CONFIG  "bcm5614x_config"
 #define spn_BCM5615X_CONFIG  "bcm5615x_config"
 
 /* Enable mixed mode speed (10G+1G, 1G+10G) on XQPorts of hypercore in BCM5614x */
 #define spn_BCM5614X_HYPERCORE_MIXED_MODE  "bcm5614x_hypercore_mixed_mode"
 #define spn_BCM5644X_CONFIG  "bcm5644x_config"
 
 /* Enable the 12G Higig mode on BCM56630, BCM56521, BCM56522, BCM56524 or BCM56534 by setting the value to 12000 */
 #define spn_HIGIG_MAX_SPEED  "higig_max_speed"
 #define spn_FRONT_PANEL_ESM  "front_panel_esm"
 
 /* L2 and VLAN module initialization will be skipped */
 #define spn_SKIP_L2_VLAN_INIT  "skip_l2_vlan_init"
 /*
  * Convenience variable that can be used to turn off both physical
  * and system port mapping. This variable overrides the dedicated
  * variables described above.
  */
 #define spn_BCM_XLATE_PORT_ENABLE  "bcm_xlate_port_enable"
 /*
  * Enable translation of physical port numbers within the BCM layer.
  * This feature allows a new device to emulate an older similar
  * device even if the physical port map is different. Note that
  * translation support must be compiled in as well.
  */
 #define spn_BCM_XLATE_API_PORT_ENABLE  "bcm_xlate_api_port_enable"
 /*
  * Enable translation of system port numbers to physical port numbers
  * in hardware (if supported by the switch device). This feature may
  * be used to complement the BCM API translation feature, but can
  * also be used to limit the use of module IDs on devices with 32 or
  * fewer ports in case some physical port numbers reside beyond 31.
  */
 #define spn_BCM_XLATE_SYSPORT_ENABLE  "bcm_xlate_sysport_enable"
 
 /* String identification of port mapping function to be used. */
 #define spn_BCM_XLATE_PORT_MAP  "bcm_xlate_port_map"
 
 /* Indication if the port should be remapped given a mapping function */
 #define spn_BCM_XLATE_PORT  "bcm_xlate_port"
 
 /* Configure the PHY address(es) for the flex-ports */
 #define spn_FLEX_PORT_PHY_ADDR  "flex_port_phy_addr"
 /*
  * Display the usage information for a CLI command when "help <cmd>",
  * "? <cmd>", or "<cmd> {unrecognized parameters}" is entered.  To suppress
  * the usage message, set this property to 0.
  */
 #define spn_HELP_CLI_ENABLE  "help_cli_enable"
 /*
  * Display table information when the "listmem" CLI command is used.
  * To suppress the table listing, set this property to 0.
  */
 #define spn_MEMLIST_ENABLE  "memlist_enable"
 /*
  * Display register information when the "listreg" CLI command is used.
  * To suppress the register listing, set this property to 0.
  */
 #define spn_REGLIST_ENABLE  "reglist_enable"
 
 /* Enable lane0 IEEE MII reset on Hyperlite/Hypercore serdes. */
 #define spn_SERDES_LANE0_RESET  "serdes_lane0_reset"
 
 /* FE 100FX Selection */
 #define spn_PBMP_FE_100FX  "pbmp_fe_100fx"
 /*
  * Specifies the Logical to physical port mapping and bandwidth allocation.
  * portmap_<port>=<physical port number>:<bandwidth in Gb>
  * \[:<OSG.0xf - Oversub Speed Group>\]\[:<phy lane config or number of lanes per port or 
  * i - inactive port or m - management port>\]\[:<i - inactive port>\]
  * \[:<queue config>\]. Applicable to BCM56840, BCM56740, BCM56850 and BCM56960 device family.
  * portmap_<port>=<physical port number>:<bandwidth in Gb>
  * \[:<phy lane config>\]\[:<fallback phy for 100G auto-negotiation>\]
  * \[:<queue config>\]\[:i - inactive port or m - management port or l - lanes>\].
  * \[:<number of lanes for management or Front-panel and Higig port>\]
  * :l option applies only to BCM56860 and cannot be used for inactive ports i.e.
  * cannot be used with :i.
  *  Valid Phy lane configs: 442/244/343. Valid fallback phy options: 0/1/2. Applicable to BCM56860 device family.
  * Example: portmap_1 = 1:100:343
  *          portmap_1 = 1:40:2
  */
 #define spn_PORTMAP  "portmap"
 /*
  * Specifies the number of lanes used by each port in the flex port group.
  * portgroup_<port group>=<number of lanes>.
  * Applicable to BCM566xx and BCM565xx device family
  *  Example:
  *    portgroup_<port_group> = 1
  *      - Lane independent mode. Each lane is an independent port, for qsgmii the valid speeds are 10/100/1000M, 2.5G.
  *    portgroup_<port_group> = 4
  *      - For QSGMII, it means only lane 0 and lane 4 are valid ports that can operate at 10/100/1000M, 2.5G speeds. Lanes 1,2,3 and 5,6,7 are disabled for QSGMII.
  */
 #define spn_PORTGROUP  "portgroup"
 /*
  * backplane serdes encoding. Supported on DNX fabric only.
  * This property can be defined per port.
  * The following values supported for DFE:
  * 0: 8b9b Legacy FEC encoding
  * 1: 8b10b encoding
  * 2: 64b66b FEC encoding
  * 3: 64b66b BEC encoding.
  * 4: 64b66b encoding
  */
 #define spn_BACKPLANE_SERDES_ENCODING  "backplane_serdes_encoding"
 
 /* Used by DNX only */
 #define spn_TCAM_BIST_ENABLE  "tcam_bist_enable"
 
 /* Used by DNX only */
 #define spn_UCODE_PORT  "ucode_port"
 
 /* Used by DNX only */
 #define spn_TCAM_BANK_BLOCK_OWNER  "tcam_bank_block_owner"
 /*
  * L2 Aging Cycles
  * 
  * Indicates the number of cycles in an L2 aging interval.  This value
  * affects the number of L2 entries to be processed by the aging engine
  * during a run.
  * A value of 1 results in processing the entire L2 table during
  * an age run cycle.
  */
 #define spn_L2_AGE_CYCLES  "l2_age_cycles"
 
 /* L2 s/w aging cycle recurrence interval in seconds */
 #define spn_L2_SW_AGING_INTERVAL  "l2_sw_aging_interval"
 
 /* Priority of the s/w based L2 aging thread */
 #define spn_L2AGE_THREAD_PRI  "l2age_thread_pri"
 
 /* Run s/w based L2 aging thread by default */
 #define spn_RUN_L2_SW_AGING  "run_l2_sw_aging"
 
 /* Enable L2 overflow event processing by default */
 #define spn_L2_OVERFLOW_EVENT  "l2_overflow_event"
 
 /* Enable/Disable Memory table cache */
 #define spn_MEM_CACHE_ENABLE  "mem_cache_enable"
 
 /* Disable Memory table cache */
 #define spn_MEM_NOCACHE  "mem_nocache"
 
 /* Defines the maximum number of l2 cache entries */
 #define spn_L2CACHE_MAX  "l2cache_max_idx"
 #define spn_PORT_IS_SCI  "port_is_sci"
 #define spn_PORT_IS_SFI  "port_is_sfi"
 /*
  * Once enabled, it will allow sharing flex statid across accounting objects.
  * SDK will provide cumulative count for accounting objects sharing statid.
  * User has to take great precaution in not sharing statid across conflicting accounting objects.
  * Currently this config variable enables sharing statid for port module only.
  */
 #define spn_FLEX_STAT_SHARE_ENABLE  "flex_stat_share_enable"
 /*
  * Following properties are used by the diag shell only
  *     spn_DIAG_CHASSIS
  *        - defines the chassis type, 0 standalone
  *          1 fabric card + line cards
  *     spn_DIAG_COSQ_INIT
  *        - diag shell performs gport adds. Must be used with bcm_cosq_init=0
  */
 #define spn_DIAG_CHASSIS  "diag_chassis"
 #define spn_DIAG_SERDES_MASK  "diag_serdes_mask"
 #define spn_DIAG_NODES_MASK  "diag_nodes_mask"
 #define spn_DIAG_SLAVE_FC  "diag_slave_fc"
 #define spn_DIAG_SLOT  "diag_slot"
 #define spn_DIAG_COSQ_INIT  "diag_cosq_init"
 #define spn_DIAG_EASY_RELOAD  "diag_easy_reload"
 #define spn_DIAG_DISABLE_INTERRUPTS  "diag_disable_interrupts"
 /*
  *  Specifies to enable or disable MACSEC feature on the 
  *  specified port. MACSEC feature might be provided by a PHY device attached to 
  *  switch port. (Default is to disable MACSEC)
  */
 #define spn_MACSEC_ENABLE  "macsec_enable"
 
 /*  specifies the MDIO address for the MACSEC PHY device. */
 #define spn_MACSEC_DEV_ADDR  "macsec_dev_addr"
 
 /*  specifies Port index within the multi-port MACSEC PHY device. */
 #define spn_MACSEC_PORT_INDEX  "macsec_port_index"
 
 /*  Specifies to enable MACSEC fixed latency mode. */
 #define spn_MACSEC_FIXED_LATENCY_ENABLE  "macsec_fixed_latency_enable"
 /*
  *  Specifies the policy of line-side and switch-side MACs 
  *  0 : Follow-on mode, switch-side follows the setting of line-side
  *  1 : Fixed mode, switch-side settings are specified by user
  *  2 : Duplex Gateway mode, for working with half-duplex link partners
  */
 #define spn_MACSEC_SWITCH_SIDE_POLICY  "macsec_switch_side_policy"
 
 /* Tab width for diagnostics (especially 'show counters') */
 #define spn_DIAG_TABS  "diag_tabs"
 /*
  * ASCII comma character for show counters
  * Use 44 for comma, 46 for period, 0 for none
  */
 #define spn_DIAG_COMMA  "diag_comma"
 #define spn_SRP_ACK_AGING_ON  "SRP_ACK_AGING_ON"
 #define spn_EAV_SRP_INTERVAL  "EAV_SRP_INTERVAL"
 #define spn_EAV_DISCOVERY_SRC_MAC  "EAV_DISCOVERY_SRC_MAC"
 #define spn_EAV_TIMESYNC_MONITOR_PBMP  "EAV_TIMESYNC_MONITOR_PBMP"
 #define spn_EAV_DISCOVERY_MASTER  "EAV_DISCOVERY_MASTER"
 #define spn_EAV_TIMESYNC_INTERVAL  "EAV_TIMESYNC_INTERVAL"
 #define spn_EAV_TIMESYNC_SPECIAL_LOOP_PBMP  "EAV_TIMESYNC_SPECIAL_LOOP_PBMP"
 #define spn_EAV_TIMESYNC_DISABLE_PDELAY  "EAV_TIMESYNC_DISABLE_PDELAY"
 #define spn_DIAG_EMULATOR_PARTIAL_INIT  "diag_emulator_partial_init"
 /*
  * PCI device ID override allows you to pretend you are running
  * on a different chip (e.g. force 56504 driver to run on 56514)
  * NOTE: this one is actually in sysconf.c, not the driver.
  */
 #define spn_PCI_OVERRIDE_DEV  "pci_override_dev"
 /*
  * PCI revision ID override allows you to pretend you are running
  * on a different revision of a chip (e.g. force 56504 A0 driver to run on 56504 B0)
  * NOTE: this one is actually in sysconf.c, not the driver.
  */
 #define spn_PCI_OVERRIDE_REV  "pci_override_rev"
 #define spn_DIAG_ASSIGN_SYSPORT  "diag_assign_sysport"
 #define spn_DEFIP_CAM_TM  "defip_cam_tm"
 #define spn_FP_CAM_TM  "fp_cam_tm"
 #define spn_VFP_CAM_TM  "vfp_cam_tm"
 #define spn_EFP_CAM_TM  "efp_cam_tm"
 #define spn_EMULATION_REGS  "emulation_regs"
 #define spn_OTP_MEM_REPAIR_REG  "otp_mem_repair_reg"
 #define spn_OTP_MEM_REPAIR_VAL  "otp_mem_repair_val"
 #define spn_FIFO_DELAY_VALUE  "fifo_delay_value"
 #define spn_BCM5664X_WRR_GRANULARITY_1  "bcm5664x_wrr_granularity_1"
 #define spn_BCM56840_CONFIG  "bcm56840_config"
 #define spn_BCM56640_CONFIG  "bcm56640_config"
 
 /* Enable 1x100GE + 1xHG[127] mode for BCM56640 */
 #define spn_BCM56640_1X100_1X127  "bcm56640_1x100_1x127"
 
 /* Enable 1x100GE + 4xHG[32] mode for BCM56640 */
 #define spn_BCM56640_1X100_4X32  "bcm56640_1x100_4x32"
 
 /* Enable 1x100GE + 8xHGduo[16] mode for BCM56640 */
 #define spn_BCM56640_1X100_8X16  "bcm56640_1x100_8x16"
 
 /* Enable 1x100GE + 3xFlex.HG[42] mode for BCM56640 */
 #define spn_BCM56640_1X100_3X42  "bcm56640_1x100_3x42"
 
 /* Enable 3xFlex.HG[42] + 1xHG[127] mode for BCM56640 */
 #define spn_BCM56640_3X42_1X127  "bcm56640_3x42_1x127"
 
 /* Enable 3xFlex.HG[42] + 4xHG[32] mode for BCM56640 */
 #define spn_BCM56640_3X42_4X32  "bcm56640_3x42_4x32"
 
 /* Enable 3xFlex.HG[42] + 8xHGduo[16] mode for BCM56640 */
 #define spn_BCM56640_3X42_8X16  "bcm56640_3x42_8x16"
 
 /* Enable 3xFlex.40GE + 3xFlex.HG[42] mode for BCM56640, BCM56045 */
 #define spn_BCM56640_3X40_3X42  "bcm56640_3x40_3x42"
 
 /* Enable 3xFlex.HG[42] + 3xFlex.40GE mode for BCM56640, BCM56045 */
 #define spn_BCM56640_3X42_3X40  "bcm56640_3x42_3x40"
 
 /* Enable 3xFlex.40GE + 2Flex.HG[42] mode for BCM56046 */
 #define spn_BCM56640_3X40_2X42  "bcm56640_3x40_2x42"
 
 /* Enable 3xFlex.HG[42] + 2xFlex.40GE mode for BCM56046 */
 #define spn_BCM56640_3X42_2X40  "bcm56640_3x42_2x40"
 
 /* Enable 48xGE + 8xXFI mode */
 #define spn_BCM56640_8X10  "bcm56640_8x10"
 
 /* Enable 48xGE (or 28xGE) + 1x40GE + 4xHG[42] mode for BCM56643, BCM56648 (or BCM56649) */
 #define spn_BCM56640_1X40_4X42  "bcm56640_1x40_4x42"
 
 /* Enable 48xGE (or 28xGE) + 4xXFI + 1xHG[127] mode for BCM56643, BCM56648 (or BCM56649) */
 #define spn_BCM56640_4X10_1X127  "bcm56640_4x10_1x127"
 
 /* Enable 36xGE (or 28xGE) + 4xXFI + 2xHG[42] + 2xFlex.HG[42] mode for BCM56643, BCM56648 (or BCM56649) */
 #define spn_BCM56640_4X10_4X42  "bcm56640_4x10_4x42"
 
 /* Enable 36xGE (or 28xGE) + 4xXFI + 2xFlex.HG[42] + 2xHG[42] +  mode for BCM56643, BCM56648 (or BCM56649) */
 #define spn_BCM56643_4X10_4X42  "bcm56643_4x10_4x42"
 
 /* Enable 24GE(line rate encap) + 2xHG[25] + 2xHG[25] mode for BCM56644 */
 #define spn_BCM56644_24G  "bcm56644_24g"
 
 /* Enable 48xGE (or 28xGE) + 4xXFI + 2xHG[42] mode for BCM56540, BCM56545 (or BCM56541, BCM56546) */
 #define spn_BCM56540_4X10_2X42  "bcm56540_4x10_2x42"
 
 /* Enable 48xGE (or 28xGE) + 8xXFI mode for BCM56540, BCM56545 (or BCM56541, BCM56546) */
 #define spn_BCM56540_8X10  "bcm56540_8x10"
 
 /* Enable 24xGE + 4xXAUI + 2xXFI + 2xHG[12] mode for BCM56545 */
 #define spn_BCM56545_24G  "bcm56545_24g"
 
 /* Enable 28xGE + 2xF.XAUI/2x10GE + 2xF.HG[42] + 2xF.HG[21] mode for BCM56542 */
 #define spn_BCM56542_2X10_2X42_2X21  "bcm56542_2x10_2x42_2x21"
 
 /* Enable 10xFlex.XAUI + 4xXFI mode for BCM56544 */
 #define spn_BCM56544_10X10_4X10  "bcm56544_10x10_4x10"
 
 /* Enable 10xFlex.XAUI + 2xHG[42] mode for BCM56544 */
 #define spn_BCM56544_10X10_2X42  "bcm56544_10x10_2x42"
 
 /* Enable 4xXAUI + 12xXFI mode for BCM56544 */
 #define spn_BCM56544_4X10_12X10  "bcm56544_4x10_12x10"
 
 /* Enable 48xGE (or 28xGE) + 4xXFI + 2xHG[42] +  mode for BCM56545K */
 #define spn_BCM56545_4X11_2X42  "bcm56545_4x11_2x42"
 
 /* Enable 48xGE (or 28xGE) + 1x40 + 2xHG[42] +  mode for BCM56545K */
 #define spn_BCM56545_1X40_2X42  "bcm56545_1x40_2x42"
 
 /* Enable 48xGE (or 28xGE) + 4xXFI + 4xHG[42] +  mode for BCM56545K */
 #define spn_BCM56545_4X11_4X42  "bcm56545_4x11_4x42"
 
 /* Enable 10xF.QSGMII + 3xF.HG[42] + 1GE mode for BCM56547 */
 #define spn_BCM56547_3X42  "bcm56547_3x42"
 
 /* Enable 12xF.QSGMII + 2xF.HG[42] + 1GE mode for BCM56547 */
 #define spn_BCM56547_2X42  "bcm56547_2x42"
 
 /* Enable 12xF.QSGMII + 2xFlex[4x10] + 1GE mode for BCM56344 */
 #define spn_BCM56344_2X10  "bcm56344_2x10"
 
 /* Enable 7xF.QSGMII + Flex[4x10] + 2xHGd[21] mode for BCM56346 */
 #define spn_BCM56346_4X10_2X21  "bcm56346_4X10_2x21"
 
 /* Enable 12xF.QSGMII + Flex[4x10] + 2xHGd[21] mode for BCM56345 */
 #define spn_BCM56345_4X10_2X21  "bcm56345_4X10_2x21"
 
 /* Enable 12xF.QSGMII + 2xHGd[21] mode for BCM56345 */
 #define spn_BCM56345_2X21  "bcm56345_2x21"
 
 /* Enable 12xF.QSGMII + Flex[4x10] + 2xHG[21] + 1GE mode for BCM56340 */
 #define spn_BCM56340_4X10  "bcm56340_4x10"
 
 /* Enable 12xF.QSGMII + 2xFlex[4x10] + 1GE mode for BCM56340 */
 #define spn_BCM56340_2X10  "bcm56340_2x10"
 #define spn_BCM56340_CONFIG  "bcm56340_config"
 #define spn_BCM5645X_CONFIG  "bcm5645x_config"
 #define spn_TCAM_DAC_VALUE  "tcam_dac_value"
 #define spn_TCAM_PTR_DIST  "tcam_ptr_dist"
 #define spn_EXT_TCAM_USE_MIDL  "ext_tcam_use_midl"
 /*
  * Greyhound(bcm 53400) could support varities of port configurations
  * including SKU options and flexible port configuration in TSCx for some SKUs.
  * SKU options and flexible port configuration on TSCx could be configured 
  * via bcm53400_init_port_config=<sku option> and the extended suffix _tsc[x].
  * i.e. bcm53400_init_port_config_tsc<# of TSC 0-5> = <SINGLE/XAUI/RXAUI>
  * SINGLE: Initialize 4 GE/XE ports in TSCx.
  * XAUI: Initialize 1 XAUI port in TSCx.
  * RXAUI: Initialize 2 RXAUI ports in TSCx.
  * Note: The Value or String will be valid only when the 
  * configurations (sku options and port configurations in TSCx) 
  * are listed in the Data sheet.
  */
 #define spn_BCM53400_INIT_PORT_CONFIG  "bcm53400_init_port_config"
 
 /* Enable hardware cable diagnostic function on 546x PHY devices */
 #define spn_CABLE_DIAG_HW  "cable_diag_hw"
 #define spn_LRP_BYPASS  "lrp_bypass"
 #define spn_SPI_LOOPBACK  "spi_loopback"
 #define spn_DDR_TRAIN_NUM_ADDRS  "ddr_train_num_addrs"
 #define spn_SEED  "seed"
 #define spn_WIDE_SRAM0_X18  "wide_sram0_x18"
 #define spn_NP0_ADDR_WIDTH  "np0_addr_width"
 #define spn_NP0_DATA_WIDTH  "np0_data_width"
 #define spn_NP1_ADDR_WIDTH  "np1_addr_width"
 #define spn_NP1_DATA_WIDTH  "np1_data_width"
 #define spn_WP_ADDR_WIDTH  "wp_addr_width"
 #define spn_WP_DATA_WIDTH  "wp_data_width"
 #define spn_WIDE_SRAM1_X18  "wide_sram1_x18"
 /*
  * This configuration allows specification/override source queue config.
  * Valid only on BCM 8803x series.
  * The parameter is per queue so has to be used in conjunction with Queue id
  * The value is comma seperated set of following parameters in a single line
  *     {max_pages},{de1_threshold},{de2_threshold},
  *     {fc_treshold},{min_data_pages},{min_hdr_pages}
  * Example: config_queue100=100,80,75,60,10,10
  */
 #define spn_CONFIG_QUEUE  "config_queue"
 /*
  * This configuration applies universal PR buffer profile .
  * Valid only on BCM 8803x series.
  * Valid values are
  *     1 (Config uses CLPORT and XTPORT)
  *     2 (Config uses CLPORT only)
  * This config is required if Hotswap feature is used
  */
 #define spn_LINE_PR_BUFFER_PROFILE  "line_pr_buffer_profile"
 /*
  * This configuration allows override for PT Line side Client Calendar.
  * Valid only on BCM 8803x series.
  * The value is a comma seperated list of Client calendar entries
  * Each entry ranges from 0-6, 6 specifies that slot is to be skipped
  * Maximum number of entries is 255
  */
 #define spn_LINE_CLIENT_CALENDAR  "line_client_calendar"
 /*
  * This configuration allows override for PT Line side Port Calendar.
  * Valid only on BCM 8803x series.
  * The value is a comma seperated list of Port calendar entries
  * Each entry ranges from 0-51, -1 specifies that slot is to be skipped
  * Maximum number of entries is 255
  */
 #define spn_LINE_PORT_CALENDAR  "line_port_calendar"
 /*
  * This configuration allows override for PT Fabric side Client Calendar.
  * Valid only on BCM 8803x series.
  * The value is a comma seperated list of Client calendar entries
  * Each entry ranges from 0-5, -1 specifies that slot is to be skipped
  * Maximum number of entries is 255
  */
 #define spn_FABRIC_CLIENT_CALENDAR  "fabric_client_calendar"
 /*
  * This configuration allows override for PT Fabric side Port Calendar.
  * Valid only on BCM 8803x series.
  * The value is a comma seperated list of Port calendar entries
  * Each entry ranges from 0-11, -1 specifies that slot is to be skipped
  * Maximum number of entries is 255
  */
 #define spn_FABRIC_PORT_CALENDAR  "fabric_port_calendar"
 /*
  * This configuration allows override for PT Port Fifo Allocation.
  * Valid only on BCM 8803x series.
  * This is typically per port configuration, unless all the ports are the same type
  * Each entry is the number of 32B pages, There is a total of 102 such pages
  * These are typically allocated to each port according to the speed
  * SDK automatically allocates if this parameter is omitted
  */
 #define spn_TX_FIFO_SIZE  "tx_fifo_size"
 /*
  * This configuration allows override for WDRR weight assigned to queues
  * This config is per queue, if the given queue is source queue, the weight is applied to HPTE WDRR
  * If the given queue is destination queue, the weight is applied to IPTE WDRR
  * Valid only on BCM 8803x series.
  */
 #define spn_WDRR_WEIGHT_QUEUE  "wdrr_weight_queue"
 /*
  * This configuration allows override for Ingress Source Queues allocated to XLPORT.
  * Valid only on BCM 8803x series.
  */
 #define spn_XL_INGRESS_SQUEUE  "xl_ingress_squeue"
 /*
  * This configuration allows override for Ingress Destination Queues allocated to XLPORT.
  * Valid only on BCM 8803x series.
  */
 #define spn_XL_INGRESS_DQUEUE  "xl_ingress_dqueue"
 /*
  * This configuration allows override for Egress Source Queues allocated to XLPORT.
  * Valid only on BCM 8803x series.
  */
 #define spn_XL_EGRESS_SQUEUE  "xl_egress_squeue"
 /*
  * This configuration allows override for Egress Destination Queues allocated to XLPORT.
  * Valid only on BCM 8803x series.
  */
 #define spn_XL_EGRESS_DQUEUE  "xl_egress_dqueue"
 /*
  * This configuration allows override for Ingress Source Queues allocated to CMIC Port.
  * Valid only on BCM 8803x series.
  */
 #define spn_CMIC_INGRESS_SQUEUE  "cmic_ingress_squeue"
 /*
  * This configuration allows override for Ingress Destination Queues allocated to CMIC Port.
  * Valid only on BCM 8803x series.
  */
 #define spn_CMIC_INGRESS_DQUEUE  "cmic_ingress_dqueue"
 /*
  * This configuration allows override for Egress Source Queues allocated to CMIC Port.
  * Valid only on BCM 8803x series.
  */
 #define spn_CMIC_EGRESS_SQUEUE  "cmic_egress_squeue"
 /*
  * This configuration allows override for Egress Destination Queues allocated to CMIC Port.
  * Valid only on BCM 8803x series.
  */
 #define spn_CMIC_EGRESS_DQUEUE  "cmic_egress_dqueue"
 /*
  * This configuration allows override for Strict Priority Queue0
  * Max of 2 strict priority queues are allowed Queue0 and Queue1
  * Valid only on BCM 8803x series.
  */
 #define spn_SPRI0_QID  "spri0_qid"
 /*
  * This configuration allows override for Strict Priority Queue1
  * Max of 2 strict priority queues are allowed Queue0 and Queue1
  * Valid only on BCM 8803x series.
  */
 #define spn_SPRI1_QID  "spri1_qid"
 /*
  * This configuration allows override for ingress redirect queues
  * Max of 2 redirects are allowed Queue0 and Queue1
  * Valid only on BCM 8803x series.
  */
 #define spn_INGRESS_TO_EGRESS_REDIRECT_QID0  "ingress_to_egress_redirect_qid0"
 /*
  * This configuration allows override for ingress redirect queues
  * Max of 2 redirects are allowed Queue0 and Queue1
  * Valid only on BCM 8803x series.
  */
 #define spn_INGRESS_TO_EGRESS_REDIRECT_QID1  "ingress_to_egress_redirect_qid1"
 /*
  * This configuration allows override for egress redirect queues
  * Max of 2 redirects are allowed Queue0 and Queue1
  * Valid only on BCM 8803x series.
  */
 #define spn_EGRESS_TO_INGRESS_REDIRECT_QID0  "egress_to_ingress_redirect_qid0"
 /*
  * This configuration allows override for egress redirect queues
  * Max of 2 redirects are allowed Queue0 and Queue1
  * Valid only on BCM 8803x series.
  */
 #define spn_EGRESS_TO_INGRESS_REDIRECT_QID1  "egress_to_ingress_redirect_qid1"
 /*
  * This configuration allows override for ingress bubble queues
  * Valid only on BCM 8803x series.
  */
 #define spn_INGRESS_BUBBLE_QID  "ingress_bubble_qid"
 /*
  * This configuration allows override for egress bubble queues
  * Valid only on BCM 8803x series.
  */
 #define spn_EGRESS_BUBBLE_QID  "egress_bubble_qid"
 /*
  * This configuration allows allocation of application specific queues
  * Queue range is 0-255
  * Valid only on BCM 8803x series.
  */
 #define spn_APP_QUEUES_START  "app_queues_start"
 /*
  * This configuration specifies the number of application specific queues
  * Only usable with app_queue_start
  * Valid only on BCM 8803x series.
  */
 #define spn_APP_QUEUES_NUM  "app_queues_num"
 /*
  * This configuration allows override for NUM_PAGES_RESERVED global parameter.
  * Valid only on BCM 8803x series.
  */
 #define spn_NUM_PAGES_RESERVED  "num_pages_reserved"
 /*
  * This configuration allows override for TOTAL_BUFF_MAX_PAGES global parameter.
  * Valid only on BCM 8803x series.
  */
 #define spn_TOTAL_BUFF_MAX_PAGES  "total_buff_max_pages"
 /*
  * This configuration allows override for TOTAL_BUFF_HYSTERESIS_DELTA global parameter
  * Valid only on BCM 8803x series.
  */
 #define spn_TOTAL_BUFF_HYSTERESIS_DELTA  "total_buff_hysteresis_delta"
 /*
  * This configuration allows override for TOTAL_BUFF_DROP_THRES_DE1 global parameter
  * Valid only on BCM 8803x series.
  */
 #define spn_TOTAL_BUFF_DROP_THRES_DE1  "total_buff_drop_thres_de1"
 /*
  * This configuration allows override for TOTAL_BUFF_DROP_THRES_DE2 global parameter
  * Valid only on BCM 8803x series.
  */
 #define spn_TOTAL_BUFF_DROP_THRES_DE2  "total_buff_drop_thres_de2"
 /*
  * This configuration allows override for INGRESS_MAX_PAGES global parameter
  * Valid only on BCM 8803x series.
  */
 #define spn_INGRESS_MAX_PAGES  "ingress_max_pages"
 /*
  * This configuration allows override for INGRESS_HYSTERESIS_DELTA global parameter
  * Valid only on BCM 8803x series.
  */
 #define spn_INGRESS_HYSTERESIS_DELTA  "ingress_hysteresis_delta"
 /*
  * This configuration allows override for INGRESS_DROP_THRES_DE1 global parameter
  * Valid only on BCM 8803x series.
  */
 #define spn_INGRESS_DROP_THRES_DE1  "ingress_drop_thres_de1"
 /*
  * This configuration allows override for INGRESS_DROP_THRES_DE2 global parameter
  * Valid only on BCM 8803x series.
  */
 #define spn_INGRESS_DROP_THRES_DE2  "ingress_drop_thres_de2"
 /*
  * This configuration allows override for EGRESS_HYSTERESIS_DELTA global parameter
  * Valid only on BCM 8803x series.
  */
 #define spn_EGRESS_HYSTERESIS_DELTA  "egress_hysteresis_delta"
 /*
  * This configuration allows override for EGRESS_MAX_PAGES global parameter
  * Valid only on BCM 8803x series.
  */
 #define spn_EGRESS_MAX_PAGES  "egress_max_pages"
 /*
  * This configuration allows override for EGRESS_DROP_THRES_DE1 global parameter
  * Valid only on BCM 8803x series.
  */
 #define spn_EGRESS_DROP_THRES_DE1  "egress_drop_thres_de1"
 /*
  * This configuration allows override for EGRESS_DROP_THRES_DE2 global parameter
  * Valid only on BCM 8803x series.
  */
 #define spn_EGRESS_DROP_THRES_DE2  "egress_drop_thres_de2"
 /*
  * This configuration allows override for FC_TOTAL_BUFFER_XOFF_THRESH global parameter
  * Valid only on BCM 8803x series.
  */
 #define spn_FC_TOTAL_BUFFER_XOFF_THRESH  "fc_total_buffer_xoff_thresh"
 /*
  * This configuration allows override for FC_INGRESS_XOFF_THRESH global parameter
  * Valid only on BCM 8803x series.
  */
 #define spn_FC_INGRESS_XOFF_THRESH  "fc_ingress_xoff_thresh"
 /*
  * This configuration allows override for FC_EGRESS_XOFF_THRESH global parameter
  * Valid only on BCM 8803x series.
  */
 #define spn_FC_EGRESS_XOFF_THRESH  "fc_egress_xoff_thresh"
 /*
  * This configuration allows override for PER_QUEUE_DROP_HYSTERESIS_DELTA global parameter
  * Valid only on BCM 8803x series.
  */
 #define spn_PER_QUEUE_DROP_HYSTERESIS_DELTA  "per_queue_drop_hysteresis_delta"
 /*
  * This configuration allows enable/disable of Flow control global config
  * Valid only on BCM 8803x series.
  */
 #define spn_FC_ENABLE  "fc_enable"
 /*
  * This configuration enables IPv6 feature.
  * Requires microcode that supports IPv6
  * Cannot coexist with Mac-in-Mac feature
  */
 #define spn_IPV6_ENABLE  "ipv6_enable"
 
 /* Number of widest VLAN xlate mem entries. */
 #define spn_VLAN_XLATE_MEM_ENTRIES  "vlan_xlate_mem_entries"
 
 /* Number of widest l2 mem entries. */
 #define spn_L2_MEM_ENTRIES  "l2_mem_entries"
 
 /* Number of widest l3 mem entries. */
 #define spn_L3_MEM_ENTRIES  "l3_mem_entries"
 
 /* Number of widest egress VLAN xlate mem entries. */
 #define spn_EGR_VLAN_XLATE_MEM_ENTRIES  "egr_vlan_xlate_mem_entries"
 
 /* Number of widest MPLS mem entries. */
 #define spn_MPLS_MEM_ENTRIES  "mpls_mem_entries"
 
 /* Number of VLAN_XLATE_1 mem entries. */
 #define spn_VLAN_XLATE_1_MEM_ENTRIES  "vlan_xlate_1_mem_entries"
 
 /* Number of VLAN_XLATE_2 mem entries. */
 #define spn_VLAN_XLATE_2_MEM_ENTRIES  "vlan_xlate_2_mem_entries"
 
 /* Number of EGR_VLAN_XLATE_1 mem entries. */
 #define spn_EGR_VLAN_XLATE_1_MEM_ENTRIES  "egr_vlan_xlate_1_mem_entries"
 
 /* Number of EGR_VLAN_XLATE_2 mem entries. */
 #define spn_EGR_VLAN_XLATE_2_MEM_ENTRIES  "egr_vlan_xlate_2_mem_entries"
 
 /* Number of FPEM mem entries. */
 #define spn_FPEM_MEM_ENTRIES  "fpem_mem_entries"
 /*
  * Two modes of using OAM-PCP in ingress:
  * 0 - Do not take value from packet. PCP is taken from TC value, according to cos profile on the LIF 
  * 1 - Take value from packet. 
  */
 #define spn_OAM_PCP_VALUE_EXTRACT_FROM_PACKET  "oam_pcp_value_extract_from_packet"
 
 /* Enables fifo dma mode */
 #define spn_OAMP_FIFO_DMA_ENABLE  "oamp_fifo_dma_enable"
 /*
  * Size of the host memory allocated by the CPU.
  * Value 0 indicates that the size will be determined by the threshold
  */
 #define spn_OAMP_FIFO_DMA_BUFFER_SIZE  "oamp_fifo_dma_buffer_size"
 /*
  * The amount of time in microseconds that passes from the first write by the DMA until a timeout based interrupt is triggered.
  * Value 0 disables timeout based interrupts.
  */
 #define spn_OAMP_FIFO_DMA_TIMEOUT  "oamp_fifo_dma_timeout"
 
 /* The number of writes by the DMA until a threshold based interrupt is triggered. */
 #define spn_OAMP_FIFO_DMA_THRESHOLD  "oamp_fifo_dma_threshold"
 
 /* Enables fifo report interface dma mode */
 #define spn_OAMP_FIFO_DMA_REPORT_INTERFACE_ENABLE  "oamp_fifo_dma_report_interface_enable"
 /*
  * Size of the host memory allocated by the CPU.
  * Value 0 indicates that the size will be determined by the threshold
  */
 #define spn_OAMP_FIFO_DMA_REPORT_INTERFACE_BUFFER_SIZE  "oamp_fifo_dma_report_interface_buffer_size"
 /*
  * The amount of time in microseconds that passes from the first write by the DMA until a timeout based interrupt is triggered.
  * Value 0 disables timeout based interrupts.
  */
 #define spn_OAMP_FIFO_DMA_REPORT_INTERFACE_TIMEOUT  "oamp_fifo_dma_report_interface_timeout"
 
 /* The number of writes by the DMA until a threshold based interrupt is triggered. */
 #define spn_OAMP_FIFO_DMA_REPORT_INTERFACE_THRESHOLD  "oamp_fifo_dma_report_interface_threshold"
 
 /* Enables event interface fifo dma mode */
 #define spn_OAMP_FIFO_DMA_EVENT_INTERFACE_ENABLE  "oamp_fifo_dma_event_interface_enable"
 /*
  * Size of the host memory allocated by the CPU.
  * Value 0 indicates that the size will be determined by the threshold
  */
 #define spn_OAMP_FIFO_DMA_EVENT_INTERFACE_BUFFER_SIZE  "oamp_fifo_dma_event_interface_buffer_size"
 /*
  * The amount of time in microseconds that passes from the first write by the DMA until a timeout based interrupt is triggered.
  * Value 0 disables timeout based interrupts.
  */
 #define spn_OAMP_FIFO_DMA_EVENT_INTERFACE_TIMEOUT  "oamp_fifo_dma_event_interface_timeout"
 
 /* The number of writes by the DMA until a threshold based interrupt is triggered. */
 #define spn_OAMP_FIFO_DMA_EVENT_INTERFACE_THRESHOLD  "oamp_fifo_dma_event_interface_threshold"
 /*
  * Size of the host memory allocated by the CPU.
  * Value 0 indicates that the size will be determined by the threshold
  */
 #define spn_LEARNING_FIFO_DMA_BUFFER_SIZE  "learning_fifo_dma_buffer_size"
 /*
  * The amount of time in microseconds that passes from the first write by the DMA until a timeout based interrupt is triggered.
  * Value 0 disables timeout based interrupts.
  */
 #define spn_LEARNING_FIFO_DMA_TIMEOUT  "learning_fifo_dma_timeout"
 
 /* The number of writes by the DMA until a threshold based interrupt is triggered. */
 #define spn_LEARNING_FIFO_DMA_THRESHOLD  "learning_fifo_dma_threshold"
 
 /* Port used for L2 Reflector (swap DA with SA) */
 #define spn_RFC2544_REFLECTOR_MAC_SWAP_PORT  "RFC2544_reflector_mac_swap_port"
 
 /* Port used for L3 Reflector (swap DA with SA, SIP with DIP) */
 #define spn_RFC2544_REFLECTOR_MAC_AND_IP_SWAP_PORT  "RFC2544_reflector_mac_and_ip_swap_port"
 #define spn_V4MC_STR_SEL  "v4mc_str_sel"
 #define spn_V4UC_STR_SEL  "v4uc_str_sel"
 #define spn_SMAC_PYLD_PERCENT  "smac_pyld_percent"
 #define spn_DMAC_PYLD_PERCENT  "dmac_pyld_percent"
 #define spn_IPV4_SA_PYLD_PERCENT  "ipv4_sa_pyld_percent"
 #define spn_IPV4_DA_PYLD_PERCENT  "ipv4_da_pyld_percent"
 #define spn_IPV4MC_SG_PYLD_PERCENT  "ipv4mc_sg_pyld_percent"
 #define spn_IPV4MC_G_PYLD_PERCENT  "ipv4mc_g_pyld_percent"
 #define spn_IPV6_SA_PYLD_PERCENT  "ipv6_sa_pyld_percent"
 #define spn_IPV6_SA_LPM_PYLD_PERCENT  "ipv6_sa_lpm_pyld_percent"
 #define spn_IPV6_DA_PYLD_PERCENT  "ipv6_da_pyld_percent"
 #define spn_IPV6_DA_LPM_PYLD_PERCENT  "ipv6_da_lpm_pyld_percent"
 #define spn_IPV6_MC_PYLD_PERCENT  "ipv6_mc_pyld_percent"
 #define spn_IPV6_MC_EM_PERCENT  "ipv6_mc_em_percent"
 #define spn_INGR_COUNTER_PERCENT  "ingr_counter_percent"
 #define spn_EGR_COUNTER_PERCENT  "egr_counter_percent"
 #define spn_EXC_COUNTER_PERCENT  "exc_counter_percent"
 #define spn_IGMP_PROXY_MODE  "igmp_proxy_mode"
 #define spn_DIAG_HG_AS_GE  "diag_hg_as_ge"
 #define spn_DIAG_HG_AS_XE  "diag_hg_as_xe"
 /*
  * ThunderBolt flow ID size for user config
  * flow ID > tb_flow_id_size will be reserved
  * for internal use
  */
 #define spn_TB_FLOW_ID_SIZE  "tb_flow_id_size"
 
 /* Board driver name */
 #define spn_BOARD_NAME  "board_name"
 
 /* Board driver start flags */
 #define spn_BOARD_FLAGS  "board_flags"
 
 /* WAN ports select */
 #define spn_PBMP_WAN_PORT  "pbmp_wan_port"
 
 /* Dual IMP ports enable */
 #define spn_DUAL_IMP_ENABLE  "dual_imp_enable"
 
 /* Auto enable MAC Low Power mode */
 #define spn_AUTO_ENABLE_MAC_LOW_POWER  "auto_enable_mac_low_power"
 
 /* Configure field processor for atomic updates */
 #define spn_FIELD_ATOMIC_UPDATE  "field_atomic_update"
 
 /* Field Class ID size. Units: bits. */
 #define spn_FIELD_CLASS_ID_SIZE  "field_class_id_size"
 
 /* Define the bitmask for destination port data in the module/port info field */
 #define spn_HIGIG_DESTPORT_MASK  "higig_destport_mask"
 
 /* Specify the stable cache option for Warm Boot operations */
 #define spn_STABLE_LOCATION  "stable_location"
 
 /* Specify the stable cache flags to configure Warm Boot operations */
 #define spn_STABLE_FLAGS  "stable_flags"
 
 /* Specify the stable cache size in bytes used for Warm boot operations */
 #define spn_STABLE_SIZE  "stable_size"
 /*
  * If the stable cache location is BCM_SWITCH_STABLE_APPLICATION, the local
  * file system will be used to save the stable cache data with this filename
  */
 #define spn_STABLE_FILENAME  "stable_filename"
 
 /* This property determines the size of memory that is preallocated to the SDK SW state */
 #define spn_SW_STATE_MAX_SIZE  "sw_state_max_size"
 /*
  * This property determines the size of the HW WAL Journal used for storing the HW ops
  * for a single transaction in Crash Recovery mode
  */
 #define spn_HA_HW_JOURNAL_SIZE  "ha_hw_journal_size"
 /*
  * This property determines the size of the SW Roll Back Journal used for storing the SW ops
  * for a single transaction in Crash Recovery mode
  */
 #define spn_HA_SW_JOURNAL_SIZE  "ha_sw_journal_size"
 /*
  * This property determines the operation mode for crash recovery feature
  * Allowed values - 0:off 1:API 2:on-demand
  */
 #define spn_HA_CRASH_RECOVERY  "ha_crash_recovery"
 
 /* NSE SYNC_IN divider */
 #define spn_PHY_1588_TS_DIVIDER  "phy_1588_ts_divider"
 
 /* IEEE1588 DPLL coeff. K1 */
 #define spn_PHY_1588_DPLL_K1  "phy_1588_dpll_k1"
 
 /* IEEE1588 DPLL coeff. K2 */
 #define spn_PHY_1588_DPLL_K2  "phy_1588_dpll_k2"
 
 /* IEEE1588 DPLL coeff. K3 */
 #define spn_PHY_1588_DPLL_K3  "phy_1588_dpll_k3"
 
 /* Initial phase values for the IEEE1588 DPLL, lower 32 bits */
 #define spn_PHY_1588_DPLL_PHASE_INITIAL_LO  "phy_1588_dpll_phase_initial_lo"
 
 /* Initial phase values for the IEEE1588 DPLL, upper 32 bits */
 #define spn_PHY_1588_DPLL_PHASE_INITIAL_HI  "phy_1588_dpll_phase_initial_hi"
 
 /* IEEE1588 DPLL mode, 0 - phase lock, 1 - frequency lock */
 #define spn_PHY_1588_DPLL_FREQUENCY_LOCK  "phy_1588_dpll_frequency_lock"
 
 /* broadsync clock enable, 0 - disable, 1 - enable */
 #define spn_BROADSYNC_ENABLE_CLK  "broadsync_enable_clk"
 
 /* AR+ 20MHz bs pll out clock enable, 0 - disable, 1 - enable */
 #define spn_ARAD_20MHZ_BS  "arad_20mhz_bs"
 
 /* Serdes TX Phase Interpolator configure, 0 - disable (default), 1 - enable with external PD (Phase detector), 2 - enable with normal mode */
 #define spn_SERDES_TXPI_MODE  "serdes_txpi_mode"
 /*
  * TX Phase Interpolator SDM (Sigma-Delta Modulator) scheme type for Portmacro core:
  * 0 - 1st order scheme with floor. It follows the traditional TXPI SDM implementation.
  * 1 - 1st order scheme with rounding. It is a new implementation that supposed to solve frequent updates introduced by the 1st order floor implementation.
  * 2 - 2nd order scheme with rounding. It is a new implementation that supposed to solve the issue of low frequency phase nose introduced by the 1st order implementation.
  */
 #define spn_TXPI_SDM_SCHEME  "txpi_sdm_scheme"
 /*
  * Phy operating in the reverse direction.
  * To set reverse mode for phy84728 and phy8706
  * set port_phy_mode_reverse_phy84728 and 
  * set port_phy_mode_reverse_phy8706
  */
 #define spn_PORT_PHY_MODE_REVERSE  "port_phy_mode_reverse"
 /*
  * Device Interconnect Mode (PCI-EB3/VLI).
  * Currently used for BCM88732
  * 0 = PCI, 1 = EB3/VLI
  */
 #define spn_DEVICE_EB_VLI  "device_eb_vli"
 /*
  * BCM88732(Shadow) Flow Control Mode
  * 0 = InBand(IB), 1 = OutofBand(OOB)
  * Default is OOB for Shadow         
  */
 #define spn_BCM88732_USE_OOB  "bcm88732_use_oob"
 /*
  * BCM88732(Shadow) Device Mode
  * 0 = XGS, 1 = PETRAB
  */
 #define spn_BCM88732_DEVICE_MODE  "bcm88732_device_mode"
 /*
  * Shadow Port Configuration
  * Front Panel ports:2X40G Switch Panel ports(Interlaken):2X40
  */
 #define spn_BCM88732_2X40_2X40  "bcm88732_2x40_2x40"
 /*
  * Shadow Port Configuration
  * Front Panel ports:2x40G Switch Panel ports(Interlaken):1x40G
  */
 #define spn_BCM88732_2X40_1X40  "bcm88732_2x40_1x40"
 /*
  * Shadow Port Configuration
  * Front Panel ports:8x10G Switch Panel ports(Interlaken):1x40G
  */
 #define spn_BCM88732_8X10_1X40  "bcm88732_8x10_1x40"
 /*
  * Shadow Port Configuration
  * Front Panel ports:8x10G Switch Panel ports(Interlaken):2x40G
  */
 #define spn_BCM88732_8X10_2X40  "bcm88732_8x10_2x40"
 /*
  * Shadow Port Configuration
  * Front Panel ports:1X40G(XLAUI) Switch Panel(XAUI) ports:4X10G
  */
 #define spn_BCM88732_1X40_4X10  "bcm88732_1x40_4x10"
 /*
  * Shadow Port Configuration
  * Front Panel ports:4x10G(XFI/SFI) Switch Panel ports(XAUI):4x10G
  */
 #define spn_BCM88732_4X10_4X10  "bcm88732_4x10_4x10"
 /*
  * Shadow Port Configuration
  * Front Panel ports:2x40G Switch Panel ports(Interlaken):2x40G
  */
 #define spn_BCM88732_2X40_2X40E  "bcm88732_2x40_2x40E"
 /*
  * Shadow Port Configuration
  * Front Panel ports:2x40G Switch Panel ports:8x12G
  */
 #define spn_BCM88732_2X40_8X12  "bcm88732_2x40_8x12"
 /*
  * Shadow Port Configuration
  * Front Panel ports:8x10G Switch Panel ports:8x12G
  */
 #define spn_BCM88732_8X10_8X12  "bcm88732_8x10_8x12"
 /*
  * Shadow Port Configuration
  * Front Panel ports:1x40G,4x10G Switch Panel ports:8x12G
  */
 #define spn_BCM88732_1X40_4X10_8X12  "bcm88732_1x40_4x10_8x12"
 /*
  * Shadow Port Configuration
  * Front Panel ports:4x10G,1x40G Switch Panel ports:8x12G
  */
 #define spn_BCM88732_4X10_1X40_8X12  "bcm88732_4x10_1x40_8x12"
 /*
  * Shadow Port Configuration
  * Front Panel ports:1x40G Switch Panel ports:4x12G
  */
 #define spn_BCM88732_8X10_4X12  "bcm88732_8x10_4x12"
 /*
  * Shadow Port Configuration
  * Front Panel ports:8x10G Switch Panel ports:2x12G
  */
 #define spn_BCM88732_8X10_2X12  "bcm88732_8x10_2x12"
 /*
  * Shadow Port Configuration
  * Front Panel ports:6x10G Switch Panel ports:2x12G
  */
 #define spn_BCM88732_6X10_2X12  "bcm88732_6x10_2x12"
 /*
  * Shadow Port Configuration
  * Front Panel ports:2X40G Switch Panel ports(XFI):8x10
  */
 #define spn_BCM88732_2X40_8X10  "bcm88732_2x40_8x10"
 /*
  * Shadow Port Configuration
  * Front Panel ports:8X10G Switch Panel ports(XFI):8x10
  */
 #define spn_BCM88732_8X10_8X10  "bcm88732_8x10_8x10"
 /*
  * CMC in CMICm used by the microController
  * suffix with _pci _uc0 etc..
  */
 #define spn_CMC  "cmc"
 
 /* Number of CMC used by the PCI Host */
 #define spn_PCI_CMCS_NUM  "pci_cmcs_num"
 
 /* CMC in CMICm used by the PCI Host */
 #define spn_PCI_CMC  "pci_cmc"
 
 /* Enable Fast SCHAN present in CMICm */
 #define spn_FSCHAN_ENABLE  "fschan_enable"
 /*
  * On 5644x devices MMU, the ports can have its packet buffer either
  * the Internal memory or the External DRAM. Set the following pbmp to
  * configure specific ports for external memory.
  */
 #define spn_PBMP_EXT_MEM  "pbmp_ext_mem"
 /*
  *  Specifies to enable or disable FCMAP feature on the 
  *  specified port. FCMAP feature might be provided by a PHY device attached to 
  *  switch port. (Default is to disable FCMAP)
  */
 #define spn_FCMAP_ENABLE  "fcmap_enable"
 
 /*  specifies the MDIO address for the FCMAP PHY device. */
 #define spn_FCMAP_DEV_ADDR  "fcmap_dev_addr"
 
 /*  specifies Port index within the multi-port FCMAP PHY device. */
 #define spn_FCMAP_PORT_INDEX  "fcmap_port_index"
 /*
  * Specifies PFC class profile,
  * used in conjuction with profile id, e.g. mmu_pfc_class_profile_0
  */
 #define spn_MMU_PFC_CLASS_PROFILE  "mmu_pfc_class_profile"
 
 /* MMU config tool attribute */
 #define spn_PFC_PRIORITY  "pfc_priority"
 /*
  * MMU config tool attribute,
  * comma seperated values specifying the COS(s) controlled by other attributes
  * e.g. pfc_priority0.cos_list=0,1,2
  */
 #define spn_COS_LIST  "cos_list"
 /*
  * MMU config tool attribute,
  * comma seperated values specifying if PFC priorities are optimized
  * 0: non-optimized, 1: optimized.
  */
 #define spn_OPTIMIZED  "optimized"
 
 /* MMU config tool prefix */
 #define spn_BUF  "buf"
 
 /* MMU config tool prefix */
 #define spn_MAP  "map"
 
 /* MMU config tool object name */
 #define spn_PRI  "pri"
 
 /* MMU config tool object name */
 #define spn_DEVICE  "device"
 
 /* MMU config tool object name */
 #define spn_POOL  "pool"
 
 /* MMU config tool object name */
 #define spn_INGPORTPOOL  "ingportpool"
 
 /* MMU config tool object name */
 #define spn_PORT  "port"
 
 /* MMU config tool object name */
 #define spn_PRIGROUP  "prigroup"
 
 /* MMU config tool object name */
 #define spn_QUEUE  "queue"
 
 /* MMU config tool object name */
 #define spn_MQUEUE  "mqueue"
 
 /* MMU config tool object name */
 #define spn_RQEQUEUE  "rqequeue"
 
 /* MMU config tool attribute name */
 #define spn_QGROUP  "qgroup"
 
 /* MMU config tool object name */
 #define spn_EQUEUE  "equeue"
 
 /* MMU config tool attribute name */
 #define spn_SIZE  "size"
 
 /* MMU config tool attribute name */
 #define spn_NUMQ  "numq"
 
 /* MMU config tool attribute name */
 #define spn_YELLOW_SIZE  "yellow_size"
 
 /* MMU config tool attribute name */
 #define spn_RED_SIZE  "red_size"
 
 /* MMU config tool attribute name */
 #define spn_GUARANTEE  "guarantee"
 
 /* MMU config tool attribute name */
 #define spn_HEADROOM  "headroom"
 
 /* MMU config tool attribute name */
 #define spn_QGROUP_ID  "qgroup_id"
 
 /* MMU config tool attribute name */
 #define spn_QGROUP_GUARANTEE  "qgroup_guarantee"
 
 /* MMU config tool attribute name */
 #define spn_QGROUP_GUARANTEE_ENABLE  "qgroup_guarantee_enable"
 
 /* MMU config tool attribute name */
 #define spn_USER_DELAY  "user_delay"
 
 /* MMU config tool attribute name */
 #define spn_SWITCH_DELAY  "switch_delay"
 
 /* MMU config tool attribute name */
 #define spn_POOL_SCALE  "pool_scale"
 
 /* MMU config tool attribute name */
 #define spn_POOL_LIMIT  "pool_limit"
 
 /* MMU config tool attribute name */
 #define spn_POOL_RESUME  "pool_resume"
 
 /* MMU config tool attribute name */
 #define spn_POOL_FLOOR  "pool_floor"
 
 /* MMU config tool attribute name */
 #define spn_YELLOW_LIMIT  "yellow_limit"
 
 /* MMU config tool attribute name */
 #define spn_YELLOW_RESUME  "yellow_resume"
 
 /* MMU config tool attribute name */
 #define spn_RED_LIMIT  "red_limit"
 
 /* MMU config tool attribute name */
 #define spn_RED_RESUME  "red_resume"
 
 /* MMU config tool attribute name */
 #define spn_DEVICE_HEADROOM_ENABLE  "device_headroom_enable"
 
 /* MMU config tool attribute name */
 #define spn_PORT_GUARANTEE_ENABLE  "port_guarantee_enable"
 
 /* MMU config tool attribute name */
 #define spn_PORT_MAX_ENABLE  "port_max_enable"
 
 /* MMU config tool attribute name */
 #define spn_FLOW_CONTROL_ENABLE  "flow_control_enable"
 
 /* MMU config tool attribute name */
 #define spn_DISCARD_ENABLE  "discard_enable"
 
 /* MMU config tool attribute name */
 #define spn_COLOR_DISCARD_ENABLE  "color_discard_enable"
 
 /* MMU config tool attribute name */
 #define spn_PKT_SIZE  "pkt_size"
 
 /* MMU config tool attribute name, This is special case where the unit are considered as packets instead of cells */
 #define spn_PKT  "pkt"
 
 /* MMU config tool attribute name */
 #define spn_EXTMEM  "extmem"
 
 /* UC0 Messaging control */
 #define spn_UC_MSG_CTRL_0  "uc_msg_ctrl_0"
 
 /* UC1 Messaging control */
 #define spn_UC_MSG_CTRL_1  "uc_msg_ctrl_1"
 
 /* UC Messaging thread priority */
 #define spn_UC_MSG_THREAD_PRI  "uc_msg_thread_pri"
 
 /* UC Messaging ctl mutex timeout in microsecs */
 #define spn_UC_MSG_CTL_TIMEOUT  "uc_msg_ctl_timeout"
 
 /* UC Messaging send queue timeout in microsecs */
 #define spn_UC_MSG_QUEUE_TIMEOUT  "uc_msg_queue_timeout"
 
 /* UC Messaging send timeout in microsecs */
 #define spn_UC_MSG_SEND_TIMEOUT  "uc_msg_send_timeout"
 
 /* UC Messaging send retry delay in microseconds */
 #define spn_UC_MSG_SEND_RETRY_DELAY  "uc_msg_send_retry_delay"
 
 /* TX beacon messaging timeout in microsecs */
 #define spn_UC_MSG_TX_BEACON_TIMEOUT  "uc_msg_tx_beacon_timeout"
 /*
  * In 5644x, 48 queues will be shared across host CPU and
  * other micro controllers, this variable can be configured
  * suffix with _pci _uc0 etc..
  */
 #define spn_NUM_QUEUES  "num_queues"
 
 /* Valid Micro controllers bit map */
 #define spn_UC_VALID_BMP  "uc_valid_bmp"
 
 /* MMU configuration of maximum number of queues */
 #define spn_MMU_MAX_QUEUES  "mmu_max_queues"
 
 /* MMU configuration of maximum number of aggregate nodes */
 #define spn_MMU_MAX_NODES  "mmu_max_nodes"
 
 /* CoS levels per subscriber */
 #define spn_MMU_SUBSCRIBER_NUM_COS_LEVEL  "mmu_subscriber_num_cos_level"
 
 /* Enable Extended Queues */
 #define spn_MMU_EXT_QUEUES_ENABLED  "mmu_ext_queues_enabled"
 
 /* MMU configuration of maximum number of classic queues */
 #define spn_MMU_MAX_CLASSIC_QUEUES  "mmu_max_classic_queues"
 
 /* MMU configuration of number of dmvoq queues */
 #define spn_MMU_NUM_DMVOQ_QUEUES  "mmu_num_dmvoq_queues"
 
 /* MMU configuration of number of subscriber queues */
 #define spn_MMU_NUM_SUBSCRIBER_QUEUES  "mmu_num_subscriber_queues"
 
 /* BFD CoS queue */
 #define spn_BFD_COSQ  "bfd_cosq"
 
 /* PTP CoS queue */
 #define spn_PTP_COSQ  "ptp_cosq"
 
 /* Memory allocated for BFD encapsulation data (in bytes) */
 #define spn_BFD_ENCAP_MEMORY_SIZE  "bfd_encap_memory_size"
 
 /* Number of BFD simple password authentication keys */
 #define spn_BFD_SIMPLE_PASSWORD_KEYS  "bfd_simple_password_keys"
 
 /* Number of BFD SHA1 authentication keys */
 #define spn_BFD_SHA1_KEYS  "bfd_sha1_keys"
 
 /* Number of BFD sessions */
 #define spn_BFD_NUM_SESSIONS  "bfd_num_sessions"
 
 /* Enable BFD Feature with bit map fields, lower bits will take precedence,
                        1st LSB bit is Multi Hop as default, 2nd LSB bit is Micro/Trunk and
                        3rd LSB bit is Echo mode Feature.
                        Value 0 will disable all the features. */
 #define spn_BFD_FEATURE_ENABLE  "bfd_feature_enable"
 
 /* If this config property is enabled (set to 1),
                        there would be a state change event (State would
                        be down for the endpoint) received after the
                        session is created if we do not receive any packets
                        from the peer within detection_multiplier * 1 seconds.
                        Default value is 0 (disabled)  */
 #define spn_BFD_SESSION_DOWN_EVENT_ON_CREATE  "bfd_session_down_event_on_create"
 
 /* Enable/Disable the configuration of using endpoint index itself as local discriminator for BFD
                        endpoints.If the config property is enabled (set to 1), any value passed in local_discriminator
                        field in endpoint info will be ignored and endpoint index would be used instead. 
                        The default value of the config property is 0 (disabled) */
 #define spn_BFD_USE_ENDPOINT_ID_AS_DISCRIMINATOR  "bfd_use_endpoint_id_as_discriminator"
 
 /* If the config property is enabled (set to 1), configuring remote discriminator value is
                        always same, not overriding with the learned BFD My discriminator value.
                        The default value of the config property is 0 (disabled) */
 #define spn_BFD_REMOTE_DISCRIMINATOR  "bfd_remote_discriminator"
 
 /* If the config property is enabled by default (set to 1), if bfd_control_plane_independence is 0,
                        Fw transmit BFD packets with C bit 0, otherwise C bit 1.
                        The default value of the config property is 1 (enabled) */
 #define spn_BFD_CONTROL_PLANE_INDEPENDENCE  "bfd_control_plane_independence"
 
 /* When configured provides value for BFD IPV6 source CPU port used for transmission of packets.
                        The default value of the config property is 0 */
 #define spn_BFD_IPV6_SOURCE_CPU_PORT  "bfd_ipv6_source_cpu_port"
 
 /* PTP frequency synthesizer DFPLL value for state 1 and k1 filter parameter */
 #define spn_PTP_SYNTH_1_K1  "ptp_synth_1_k1"
 
 /* PTP frequency synthesizer DFPLL value for state 1 and k1k2 filter parameter */
 #define spn_PTP_SYNTH_1_K1K2  "ptp_synth_1_k1k2"
 
 /* PTP frequency synthesizer DFPLL value for state 1 and k1k3 filter parameter */
 #define spn_PTP_SYNTH_1_K1K3  "ptp_synth_1_k1k3"
 
 /* PTP frequency synthesizer DFPLL value for state 1 and k4 filter parameter */
 #define spn_PTP_SYNTH_1_K4  "ptp_synth_1_k4"
 
 /* PTP frequency synthesizer DFPLL value for state 1 and valid_thresh parameter */
 #define spn_PTP_SYNTH_1_VALID_THRESH  "ptp_synth_1_valid_thresh"
 
 /* PTP frequency synthesizer DFPLL value for state 1 and invalid_thresh parameter */
 #define spn_PTP_SYNTH_1_INVALID_THRESH  "ptp_synth_1_invalid_thresh"
 
 /* PTP frequency synthesizer DFPLL value for state 2 and k1 filter parameter */
 #define spn_PTP_SYNTH_2_K1  "ptp_synth_2_k1"
 
 /* PTP frequency synthesizer DFPLL value for state 2 and k1k2 filter parameter */
 #define spn_PTP_SYNTH_2_K1K2  "ptp_synth_2_k1k2"
 
 /* PTP frequency synthesizer DFPLL value for state 2 and k1k3 filter parameter */
 #define spn_PTP_SYNTH_2_K1K3  "ptp_synth_2_k1k3"
 
 /* PTP frequency synthesizer DFPLL value for state 2 and k4 filter parameter */
 #define spn_PTP_SYNTH_2_K4  "ptp_synth_2_k4"
 
 /* PTP frequency synthesizer DFPLL value for state 2 and valid_thresh parameter */
 #define spn_PTP_SYNTH_2_VALID_THRESH  "ptp_synth_2_valid_thresh"
 
 /* PTP frequency synthesizer DFPLL value for for state 2 and invalid_thresh parameter */
 #define spn_PTP_SYNTH_2_INVALID_THRESH  "ptp_synth_2_invalid_thresh"
 
 /* PTP frequency synthesizer DFPLL value for valid_input parameter */
 #define spn_PTP_SYNTH_VALID_INPUT_THRESH  "ptp_synth_valid_input_thresh"
 
 /* PTP frequency synthesizer DFPLL value for nominal_period parameter */
 #define spn_PTP_SYNTH_NOMINAL_PERIOD  "ptp_synth_nominal_period"
 
 /* PTP backplane DFPLL value for state 1 and k1 filter parameter */
 #define spn_PTP_BACKPLANE_1_K1  "ptp_backplane_1_k1"
 
 /* PTP backplane DFPLL value for state 1 and k1k2 filter parameter */
 #define spn_PTP_BACKPLANE_1_K1K2  "ptp_backplane_1_k1k2"
 
 /* PTP backplane DFPLL value for state 1 and k1k3 filter parameter */
 #define spn_PTP_BACKPLANE_1_K1K3  "ptp_backplane_1_k1k3"
 
 /* PTP backplane DFPLL value for state 1 and k4 filter parameter */
 #define spn_PTP_BACKPLANE_1_K4  "ptp_backplane_1_k4"
 
 /* PTP backplane DFPLL value for state 1 and valid_thresh parameter */
 #define spn_PTP_BACKPLANE_1_VALID_THRESH  "ptp_backplane_1_valid_thresh"
 
 /* PTP backplane DFPLL value for state 1 and invalid_thresh parameter */
 #define spn_PTP_BACKPLANE_1_INVALID_THRESH  "ptp_backplane_1_invalid_thresh"
 
 /* PTP backplane DFPLL value for state 2 and k1 filter parameter */
 #define spn_PTP_BACKPLANE_2_K1  "ptp_backplane_2_k1"
 
 /* PTP backplane DFPLL value for state 2 and k1k2 filter parameter */
 #define spn_PTP_BACKPLANE_2_K1K2  "ptp_backplane_2_k1k2"
 
 /* PTP backplane DFPLL value for state 2 and k1k3 filter parameter */
 #define spn_PTP_BACKPLANE_2_K1K3  "ptp_backplane_2_k1k3"
 
 /* PTP backplane DFPLL value for state 2 and k4 filter parameter */
 #define spn_PTP_BACKPLANE_2_K4  "ptp_backplane_2_k4"
 
 /* PTP backplane DFPLL value for state 2 and valid_thresh parameter */
 #define spn_PTP_BACKPLANE_2_VALID_THRESH  "ptp_backplane_2_valid_thresh"
 
 /* PTP backplane DFPLL value for state 2 and invalid_thresh parameter */
 #define spn_PTP_BACKPLANE_2_INVALID_THRESH  "ptp_backplane_2_invalid_thresh"
 
 /* PTP backplane DFPLL value for valid_input parameter */
 #define spn_PTP_BACKPLANE_VALID_INPUT_THRESH  "ptp_backplane_valid_input_thresh"
 
 /* PTP backplane DFPLL value for nominal_period parameter */
 #define spn_PTP_BACKPLANE_NOMINAL_PERIOD  "ptp_backplane_nominal_period"
 
 /* PTP Timestamping PLL value for fref parameter */
 #define spn_PTP_TS_PLL_FREF  "ptp_ts_pll_fref"
 
 /* PTP Timestamping PLL value for pdiv parameter */
 #define spn_PTP_TS_PLL_PDIV  "ptp_ts_pll_pdiv"
 
 /* PTP Timestamping PLL value for n parameter */
 #define spn_PTP_TS_PLL_N  "ptp_ts_pll_n"
 
 /* pPTP Timestamping PLL value for mndiv ch0 parameter */
 #define spn_PTP_TS_PLL_MNDIV  "ptp_ts_pll_mndiv"
 
 /* pPTP Timestamping PLL value for mndiv ch1 parameter */
 #define spn_PTP_TS_PLL_MNDIV1  "ptp_ts_pll_mndiv1"
 
 /* PTP Timestamping PLL value for ka parameter */
 #define spn_PTP_TS_KA  "ptp_ts_ka"
 
 /* PTP Timestamping PLL value for k1 parameter */
 #define spn_PTP_TS_KI  "ptp_ts_ki"
 
 /* PTP Timestamping PLL value for kp parameter */
 #define spn_PTP_TS_KP  "ptp_ts_kp"
 
 /* PTP Timestamping PLL value for vco_div2 parameter */
 #define spn_PTP_TS_VCO_DIV2  "ptp_ts_vco_div2"
 
 /* PTP BroadSync/10Mhz PLL value for fref parameter */
 #define spn_PTP_BS_FREF  "ptp_bs_fref"
 
 /* PTP BroadSync/10Mhz PLL value for pdiv parameter */
 #define spn_PTP_BS_PDIV  "ptp_bs_pdiv"
 
 /* PTP BroadSync/10Mhz PLL value for ndiv parameter */
 #define spn_PTP_BS_NDIV_INT  "ptp_bs_ndiv_int"
 
 /* PTP BroadSync/10Mhz PLL value for ndiv_frac parameter */
 #define spn_PTP_BS_NDIV_FRAC  "ptp_bs_ndiv_frac"
 
 /* PTP BroadSync/10Mhz PLL value for mndiv parameter */
 #define spn_PTP_BS_MNDIV  "ptp_bs_mndiv"
 
 /* PTP BroadSync/10Mhz PLL value for ka parameter */
 #define spn_PTP_BS_KA  "ptp_bs_ka"
 
 /* PTP BroadSync/10Mhz PLL value for k1 parameter */
 #define spn_PTP_BS_KI  "ptp_bs_ki"
 
 /* PTP BroadSync/10Mhz PLL value for kp parameter */
 #define spn_PTP_BS_KP  "ptp_bs_kp"
 
 /* PTP BroadSync/10Mhz PLL value for clk_dur_high parameter */
 #define spn_PTP_BS_CLK_DUR_HIGH  "ptp_bs_clk_dur_high"
 
 /* PTP BroadSync/10Mhz PLL value for clk_dur_low parameter */
 #define spn_PTP_BS_CLK_DUR_LOW  "ptp_bs_clk_dur_low"
 
 /* PTP BroadSync/10Mhz PLL value for hb_dur_high parameter */
 #define spn_PTP_BS_HB_DUR_HIGH  "ptp_bs_hb_dur_high"
 
 /* PTP BroadSync/10Mhz PLL value for hb_dur_low parameter */
 #define spn_PTP_BS_HB_DUR_LOW  "ptp_bs_hb_dur_low"
 
 /* PTP BroadSync/10Mhz PLL value for vco_div2 parameter */
 #define spn_PTP_BS_VCO_DIV2  "ptp_bs_vco_div2"
 
 /* PTP servo oscillator type */
 #define spn_PTP_SERVO_OSC_TYPE  "ptp_servo_osc_type"
 
 /* PTP servo transport type */
 #define spn_PTP_SERVO_TRANSPORT_TYPE  "ptp_servo_transport_type"
 
 /* PTP servo phase mode */
 #define spn_PTP_SERVO_PHASE_MODE  "ptp_servo_phase_mode"
 
 /* PTP servo bridge time */
 #define spn_PTP_SERVO_BRIDGE_TIME  "ptp_servo_bridge_time"
 
 /* Register Warm Boot event handler callback routine */
 #define spn_WARMBOOT_EVENT_HANDLER_ENABLE  "warmboot_event_handler_enable"
 
 /* Selects the TDM protocol to be used on all of the CES TDM ports. Valid protocols are either T1 or E1, the default is T1. */
 #define spn_CES_PORT_TDM_PROTO  "ces_port_tdm_proto"
 
 /* Sets the MAC address of the CES MII. If this is not specified then a default MAC of 00:F1:F2:F3:F4:F5 is used. */
 #define spn_CES_MII_MAC  "ces_mii_mac"
 
 /* Sets the CES MII port number. Default value is 0 */
 #define spn_CES_MII_PORT_NUMBER  "ces_mii_port_number"
 
 /* Sets the CES IPv4 address. Default value is 0 */
 #define spn_CES_IPV4_ADDRESS  "ces_ipv4_address"
 
 /* Sets the CES IPv6 address. Default value is 0 */
 #define spn_CES_IPV6_ADDRESS  "ces_ipv6_address"
 
 /* Specifies the CES system clock rate in Hz. Default value is 25000000 */
 #define spn_CES_SYSTEM_CLOCK_RATE  "ces_system_clock_rate"
 
 /* Specifies the CES PLL reference clock rate in Hz. Default value is 25000000 */
 #define spn_CES_PLL_REFERENCE_CLOCK_RATE  "ces_pll_reference_clock_rate"
 
 /* Specifies the CES common reference clock rate in Hz. Default value is 1544000 */
 #define spn_CES_COMMON_REF_CLOCK_RATE  "ces_common_ref_clock_rate"
 
 /* Memory Grade written in Hex Value. eg. 10-10-10 grade = 0x101010 */
 #define spn_DDR3_MEM_GRADE  "ddr3_mem_grade"
 
 /* Memory Speed in MHz */
 #define spn_DDR3_CLOCK_MHZ  "ddr3_clock_mhz"
 
 /* PLL Freq in MHz, For Underclocking */
 #define spn_DDR3_PLL_MHZ  "ddr3_pll_mhz"
 
 /* To Override the DDR Refresh Interval */
 #define spn_DDR3_REFRESH_INTVL_OVERRIDE  "ddr3_refresh_intvl_override"
 
 /* Autorun Shmoo Tuning on Init */
 #define spn_DDR3_AUTO_TUNE  "ddr3_auto_tune"
 /*
  * Following properties are used to store DDR3 Auto Tuning Values.
  * Restores these values only if Auto-Tune is Off
  */
 #define spn_DDR3_TUNE_RD_DATA_DLY  "ddr3_tune_rd_data_dly"
 #define spn_DDR3_TUNE_RD_EN  "ddr3_tune_rd_en"
 #define spn_DDR3_TUNE_RD_DQ_WL0_RP  "ddr3_tune_rd_dq_wl0_rp"
 #define spn_DDR3_TUNE_RD_DQ_WL1_RP  "ddr3_tune_rd_dq_wl1_rp"
 #define spn_DDR3_TUNE_RD_DQ_WL0_RN  "ddr3_tune_rd_dq_wl0_rn"
 #define spn_DDR3_TUNE_RD_DQ_WL1_RN  "ddr3_tune_rd_dq_wl1_rn"
 #define spn_DDR3_TUNE_RD_DQS  "ddr3_tune_rd_dqs"
 #define spn_DDR3_TUNE_VREF  "ddr3_tune_vref"
 #define spn_DDR3_TUNE_WR_DQ  "ddr3_tune_wr_dq"
 #define spn_DDR3_TUNE_WR_DQ_WL0  "ddr3_tune_wr_dq_wl0"
 #define spn_DDR3_TUNE_WR_DQ_WL1  "ddr3_tune_wr_dq_wl1"
 #define spn_DDR3_TUNE_ADDRC  "ddr3_tune_addrc"
 
 /* Following properties are for DDR3 Tuning Overrides */
 #define spn_DDR3_TREAD_ENB  "ddr3_tread_enb"
 #define spn_DDR3_BANK_UNAVAIL_RD  "ddr3_bank_unavail_rd"
 #define spn_DDR3_BANK_UNAVAIL_WR  "ddr3_bank_unavail_wr"
 #define spn_DDR3_TRP_READ  "ddr3_trp_read"
 #define spn_DDR3_TRP_WRITE  "ddr3_trp_write"
 #define spn_DDR3_ROUND_ROBIN_READ  "ddr3_round_robin_read"
 #define spn_DDR3_ROUND_ROBIN_WRITE  "ddr3_round_robin_write"
 /*
  * Following properties are used to store COMBO28 Auto Tuning Values.
  * Restores these values only if Auto-Tune is Off
  * 
  * Write data min delay - bit0 - bit 7
  */
 #define spn_COMBO28_TUNE_DQ_WR_MIN_VDL  "combo28_tune_dq_wr_min_vdl"
 
 /* Write data min delay - DBI Bit */
 #define spn_COMBO28_TUNE_DQ_WR_MIN_VDL_DBI  "combo28_tune_dq_wr_min_vdl_dbi"
 
 /* Write data min delay - EDC Bit */
 #define spn_COMBO28_TUNE_DQ_WR_MIN_VDL_EDC  "combo28_tune_dq_wr_min_vdl_edc"
 
 /* Write data max delay - Non-DQS Bits */
 #define spn_COMBO28_TUNE_DQ_WR_MAX_VDL_DATA  "combo28_tune_dq_wr_max_vdl_data"
 
 /* Write data max delay - DQS Bit */
 #define spn_COMBO28_TUNE_DQ_WR_MAX_VDL_DQS  "combo28_tune_dq_wr_max_vdl_dqs"
 
 /* Read data min delay - bit0 - bit 7 */
 #define spn_COMBO28_TUNE_DQ_RD_MIN_VDL  "combo28_tune_dq_rd_min_vdl"
 
 /* Read data min delay - DBI Bit */
 #define spn_COMBO28_TUNE_DQ_RD_MIN_VDL_DBI  "combo28_tune_dq_rd_min_vdl_dbi"
 
 /* Read data min delay - EDC Bit */
 #define spn_COMBO28_TUNE_DQ_RD_MIN_VDL_EDC  "combo28_tune_dq_rd_min_vdl_edc"
 
 /* Read data max delay - DQSP Bit */
 #define spn_COMBO28_TUNE_DQ_RD_MAX_VDL_DQSP  "combo28_tune_dq_rd_max_vdl_dqsp"
 
 /* Read data max delay - DQSN Bit */
 #define spn_COMBO28_TUNE_DQ_RD_MAX_VDL_DQSN  "combo28_tune_dq_rd_max_vdl_dqsn"
 
 /* REN FIFO configuration per DQ macro */
 #define spn_COMBO28_TUNE_DQ_REN_FIFO_CONFIG  "combo28_tune_dq_ren_fifo_config"
 
 /* EDCEN FIFO configuration per DQ macro */
 #define spn_COMBO28_TUNE_DQ_EDCEN_FIFO_CONFIG  "combo28_tune_dq_edcen_fifo_config"
 
 /* Read FSM max delay */
 #define spn_COMBO28_TUNE_DQ_READ_MAX_VDL_FSM  "combo28_tune_dq_read_max_vdl_fsm"
 
 /* Vref DAC configuration per DQ macro */
 #define spn_COMBO28_TUNE_DQ_VREF_DAC_CONFIG  "combo28_tune_dq_vref_dac_config"
 
 /* Reserved reg per DQ macro */
 #define spn_COMBO28_TUNE_DQ_MACRO_RESERVED_REG  "combo28_tune_dq_macro_reserved_reg"
 
 /* Address max delay - Address/Command Bits of Lower Macro */
 #define spn_COMBO28_TUNE_AQ_L_MAX_VDL_ADDR  "combo28_tune_aq_l_max_vdl_addr"
 
 /* Address max delay - Control Bits of Lower Macro */
 #define spn_COMBO28_TUNE_AQ_L_MAX_VDL_CTRL  "combo28_tune_aq_l_max_vdl_ctrl"
 
 /* Reserved reg - Control Bits of Lower Macro */
 #define spn_COMBO28_TUNE_AQ_L_MACRO_RESERVED_REG  "combo28_tune_aq_l_macro_reserved_reg"
 
 /* Address max delay - Address/Command Bits of Upper Macro */
 #define spn_COMBO28_TUNE_AQ_U_MAX_VDL_ADDR  "combo28_tune_aq_u_max_vdl_addr"
 
 /* Address max delay - Control Bits of Upper Macro */
 #define spn_COMBO28_TUNE_AQ_U_MAX_VDL_CTRL  "combo28_tune_aq_u_max_vdl_ctrl"
 
 /* Reserved reg - Control Bits of Upper Macro */
 #define spn_COMBO28_TUNE_AQ_U_MACRO_RESERVED_REG  "combo28_tune_aq_u_macro_reserved_reg"
 
 /* Reserved reg - common Macro */
 #define spn_COMBO28_TUNE_COMMON_MACRO_RESERVED_REG  "combo28_tune_common_macro_reserved_reg"
 
 /* Clock configuration for reads */
 #define spn_COMBO28_TUNE_CONTROL_REGS_READ_CLOCK_CONFIG  "combo28_tune_control_regs_read_clock_config"
 
 /* Shift register configuration for inputs */
 #define spn_COMBO28_TUNE_CONTROL_REGS_INPUT_SHIFT_CTRL  "combo28_tune_control_regs_input_shift_ctrl"
 
 /* REN FIFO configuration initializer */
 #define spn_COMBO28_TUNE_CONTROL_REGS_REN_FIFO_CENTRAL_INITIALIZER  "combo28_tune_control_regs_ren_fifo_central_initializer"
 
 /* EDCEN FIFO configuration initializer */
 #define spn_COMBO28_TUNE_CONTROL_REGS_EDCEN_FIFO_CENTRAL_INIT  "combo28_tune_control_regs_edcen_fifo_central_init"
 
 /* Shared Vref DAC configuration - AQ & Common macros */
 #define spn_COMBO28_TUNE_CONTROL_REGS_SHARED_VREF_DAC_CONFIG  "combo28_tune_control_regs_shared_vref_dac_config"
 
 /* Reserved reg - control macro */
 #define spn_COMBO28_TUNE_CONTROL_REGS_RESERVED_REG  "combo28_tune_control_regs_reserved_reg"
 
 /* Enable Service Meter */
 #define spn_GLOBAL_METER_CONTROL  "global_meter_control"
 /*
  * Sets the MAC address of RCPU master. If this is not specified then a
  * default MAC of 00:aa:bb:22:33:00 is used. Note local CPU MAC address
  * is used in case of OOB RCPU master even this property is specified.
  */
 #define spn_RCPU_SRC_MAC  "rcpu_src_mac"
 /*
  * Sets the MAC address used by RCPU slave units. If this is not specified
  * then a default MAC of 00:00:11:22:33:00 is used. And the last octet is
  * replaced with unit number.
  */
 #define spn_RCPU_LMAC  "rcpu_lmac"
 
 /* This controls whether to extract the recovered clock or not. (same as SyncE) */
 #define spn_PHY_CLOCK_ENABLE  "phy_clock_enable"
 /*
  * Number of clock delay between the rising edge of MDC
  * and the starting data of MDIO
  */
 #define spn_MDIO_OUTPUT_DELAY  "mdio_output_delay"
 
 /* MDIO IO voltage select. 0: 1.2 V, 1: 2.5 V, 2: 3.3 V */
 #define spn_MDIO_IO_VOLTAGE  "mdio_io_voltage"
 /*
  * Specifies the base port and phy index of a multi slice phy chip.
  * phy_port_primary_and_offset_<port>=0xPPOO 0xPP=primary port number 0xOO=offset of the slice
  * For example,for ports ge0-ge3 Primary Port number is 02 (base port)
  * phy_port_primary_and_offset_ge0=0x0200 primary port number=0x02 offset=00
  * phy_port_primary_and_offset_ge1=0x0201 primary port number=0x02 offset=01
  * phy_port_primary_and_offset_ge2=0x0202 primary port number=0x02 offset=02
  * phy_port_primary_and_offset_ge3=0x0203 primary port number=0x02 offset=03
  */
 #define spn_PHY_PORT_PRIMARY_AND_OFFSET  "phy_port_primary_and_offset"
 
 /* Specifies the mapping of physical pairs in an MDI interface. Value 0 means do not change pair mapping */
 #define spn_PHY_MDI_PAIR_MAP  "phy_mdi_pair_map"
 
 /* Enable VLAN queues */
 #define spn_VLAN_QUEUE_ENABLE  "vlan_queue_enable"
 
 /* Maximum levels for VLAN queues */
 #define spn_VLAN_QUEUE_LEVELS_MAX  "vlan_queue_levels_max"
 /*
  * cos mode. Supported on 88640 device
  * 
  * 0: Simple mode. Hierarchy setup by SDK
  * 1: Flexible mode. Hierarchy setup by application
  * 2: Hybrid mode. Hierarchy setup by SDK and application can add to it
  */
 #define spn_COS_MODE  "cos_mode"
 
 /* credit worth size. Configuration units are in bytes. Supported on 88640 and 88650 devices */
 #define spn_CREDIT_SIZE  "credit_size"
 
 /* If set, the link state sent to the scheduler is masked by the accessability of the local FAP and by the all-reachable vector  */
 #define spn_SCHEDULER_FABRIC_LINKS_ADAPTATION_ENABLE  "scheduler_fabric_links_adaptation_enable"
 /*
  * multicast fabric enhanced mode. Supported on 88640 device
  * 
  * 0: Traffic Class only mode
  * 1: {Traffic class, group} mode
  */
 #define spn_MULTICAST_SCHEDULER_MODE  "multicast_scheduler_mode"
 
 /* Number of multicast full Dbuffs. Supported on 88640 device */
 #define spn_MULTICAST_NBR_FULL_DBUFF  "multicast_nbr_full_dbuff"
 
 /* Number of multicast mini Dbuffs. Supported on 88640 device */
 #define spn_MULTICAST_NBR_MINI_DBUFF   "multicast_nbr_mini_dbuff "
 /*
  * port egress cos mode. Global configuration. Supported on 88640 device
  * 
  * 0: 2 unicast and 2 multicast queues per port.
  * 1: 8 unicast and 8 multicast queues per port. Not to be initially supported 
  */
 #define spn_PORT_EGRESS_COS_MODE  "port_egress_cos_mode"
 /*
  * port egress scheduler configuration. Supported on 88640 device
  * 
  * 0: OFFP port scheduler Configuration A.
  * 1: OFFP port scheduler Configuration B..
  */
 #define spn_PORT_EGRESS_SCHEDULER_CONFGURATION   "port_egress_scheduler_confguration "
 /*
  * Port egress recycling scheduler configuration. Supported on 88640 and 88650 device
  * 
  * 0: Strict Priority Scheduler.
  * 1: Round Robin Scheduler.
  */
 #define spn_PORT_EGRESS_RECYCLING_SCHEDULER_CONFIGURATION  "port_egress_recycling_scheduler_configuration"
 /*
  * this property is prefixed by the core (_core<id>) and region number ("_#"). The value that is assigned to this property configures the region mode
  * 
  * 0: queue connectors only (InterDigitated = FALSE, OddEven = TRUE)
  * 1: queue connectors, SE (InterDigitated =TRUE, OddEven = TRUE)
  * 2: queue connectors, SE (InterDigitated =TRUE, OddEven = FALSE)
  */
 #define spn_DTM_FLOW_MAPPING_MODE_REGION  "dtm_flow_mapping_mode_region"
 
 /* this property is prefixed by the core id  (_core#) and region number ("_#"). The value that is assigned to this property configures the number of symmetric connections in E2E scheme */
 #define spn_DTM_FLOW_NOF_REMOTE_CORES_REGION  "dtm_flow_nof_remote_cores_region"
 /*
  * this property is prefixed by the region number ("_#"). The value that is assigned to this property configures the queue region mode
  * 
  * 0: queue region corresponding to connector region with attribute InterDigitated = FALSE
  * 1: queue region corresponding to connector region with attribute InterDigitated = TRUE
  */
 #define spn_DTM_QUEUE_MAPPING_MODE_REGION  "dtm_queue_mapping_mode_region"
 
 /* Following properties are valid on Petra only */
 #define spn_PORT_NIF_TYPE  "port_nif_type"
 /*
  * SINGLE_STAGE_FE2, 
  * MULTI_STAGE_FE2, 
  * MULTI_STAGE_FE13, or
  * REPEATER
  */
 #define spn_FABRIC_DEVICE_MODE  "fabric_device_mode"
 
 /* Specify Single (0) or Dual (1) context mode */
 #define spn_IS_DUAL_MODE  "is_dual_mode"
 
 /* Specify number of fabric pipes */
 #define spn_FABRIC_NUM_PIPES  "fabric_num_pipes"
 
 /* Specify mapping of uc,mc and number of priortiy to fabric pipe */
 #define spn_FABRIC_PIPE_MAP  "fabric_pipe_map"
 
 /* Specify fabric FIFO depth in RX stage */
 #define spn_FABRIC_LINK_FIFO_SIZE_RX  "fabric_link_fifo_size_rx"
 
 /* Specify fabric FIFO depth in MIDDLE stage */
 #define spn_FABRIC_LINK_FIFO_SIZE_MID  "fabric_link_fifo_size_mid"
 
 /* Specify fabric FIFO depth in TX stage */
 #define spn_FABRIC_LINK_FIFO_SIZE_TX  "fabric_link_fifo_size_tx"
 /*
  * Whether local routing from FE1 to FE3 is enabled
  * For generations before Ramon, this SoC property is used without suffix and enables local routing for Unicast traffic only.
  * For Ramon:
  * - to enable local routing for Unicast traffic, use fabric_local_routing_enable_uc
  * - to enable local routing for Multicast traffic, use fabric_local_routing_enable_mc
  * - to enable local routing for both Unicast and Multicast traffic, use fabric_local_routing_enable
  */
 #define spn_FABRIC_LOCAL_ROUTING_ENABLE  "fabric_local_routing_enable"
 
 /* Whether there is a device in multi-pipe mode in system */
 #define spn_SYSTEM_CONTAINS_MULTIPLE_PIPE_DEVICE  "system_contains_multiple_pipe_device"
 
 /* Whether there is a device in VCS128 mode in system */
 #define spn_SYSTEM_IS_VCS_128_IN_SYSTEM  "system_is_vcs_128_in_system"
 
 /* Whether there is a device in the in dual mode system. */
 #define spn_SYSTEM_IS_DUAL_MODE_IN_SYSTEM  "system_is_dual_mode_in_system"
 
 /* Whether there is a device in the in single mode system. */
 #define spn_SYSTEM_IS_SINGLE_MODE_IN_SYSTEM  "system_is_single_mode_in_system"
 
 /* Whether there is an FE600 device in the system. */
 #define spn_SYSTEM_IS_FE600_IN_SYSTEM  "system_is_fe600_in_system"
 
 /* Whether there is a Petra B device in the system. */
 #define spn_SYSTEM_IS_PETRA_B_IN_SYSTEM  "system_is_petra_b_in_system"
 
 /* Whether there is a Arad or Arad Plus device in the system. */
 #define spn_SYSTEM_IS_ARAD_IN_SYSTEM  "system_is_arad_in_system"
 /*
  * 225 - 666 
  * System reference core clock. 
  * If there are FE600 devices in the system it must match their frequency. If  there are Peter-A devices in the system it must match their frequency or 2/3 of their frequency
  */
 #define spn_SYSTEM_REF_CORE_CLOCK  "system_ref_core_clock"
 /*
  * BCM88X4X has a mode to send successive 128B cell on the link. The BCM88X5X can merge this to a single 256B that is processed more efficiently.
  * This mode is set if all VSC128 link are sourced by BCM88X4X.  
  */
 #define spn_FABRIC_MERGE_CELLS  "fabric_merge_cells"
 /*
  * DIRECT or 
  *  INDIRECT. 
  * Indirect mode is used when the maximal FAP module ID is higher than 127. In this case the per-multicast destination IDs bitmap doesn't represent module IDs, rather FAP group IDs, or internal FAP IDs.
  */
 #define spn_FABRIC_MULTICAST_MODE  "fabric_multicast_mode"
 /*
  * The multicast table access can be configured to work at a round robin between all requestors
  * or to give priority to the secondary pipe when used for TDM.
  * 0 - use round robin mode between all requesting queries when accessing table.
  * 1  - use strict priority to secondary pipe, to be used in TDM/Non-TDM pipe splitting.
  */
 #define spn_MC_TABLE_ENABLE_TDM_PRIORITY  "mc_table_enable_TDM_priority"
 /*
  * Select load balancing mode: 
  * NORMAL_LOAD_BALANCE, 
  * DESTINATION_UNREACHABLE, or 
  * BALANCED_INPUT
  */
 #define spn_FABRIC_LOAD_BALANCING_MODE  "fabric_load_balancing_mode"
 
 /* Number of good cells that add a token to the bucket. Value is set to 2^fabric_mac_bucket_fill_rate. Range valid for BCM88750: 0-11 */
 #define spn_FABRIC_MAC_BUCKET_FILL_RATE  "fabric_mac_bucket_fill_rate"
 /*
  * Per port cell format
  * VSC128 or VSC256
  */
 #define spn_FABRIC_CELL_FORMAT  "fabric_cell_format"
 
 /* Enables fabric cell fifo dma mode */
 #define spn_FABRIC_CELL_FIFO_DMA_ENABLE  "fabric_cell_fifo_dma_enable"
 
 /* Size of the host memory stored allocated by the CPU */
 #define spn_FABRIC_CELL_FIFO_DMA_BUFFER_SIZE  "fabric_cell_fifo_dma_buffer_size"
 /*
  * The amount of time in microseconds that passes from the first write by the DMA until a timeout based interrupt is triggered. 
  * Value 0 disables timeout based interrupts. 
  */
 #define spn_FABRIC_CELL_FIFO_DMA_TIMEOUT  "fabric_cell_fifo_dma_timeout"
 
 /* The number of writes by the DMA until a threshold based interrupt is triggered. */
 #define spn_FABRIC_CELL_FIFO_DMA_THRESHOLD  "fabric_cell_fifo_dma_threshold"
 
 /* Drop multicast best effort according to Delete-FIFO available resources (number of packet descriptors which can be added to Delete-FIFO).  */
 #define spn_EGRESS_FABRIC_DROP_THRESHOLD_MULTICAST_LOW  "egress_fabric_drop_threshold_multicast_low"
 
 /* Drop multicast according to Delete-FIFO available resources (number of packet descriptors which can be added to Delete-FIFO). */
 #define spn_EGRESS_FABRIC_DROP_THRESHOLD_MULTICAST  "egress_fabric_drop_threshold_multicast"
 
 /* Drop all traffic except TDM according to Delete-FIFO available resources (number of packet descriptors which can be added to Delete-FIFO). */
 #define spn_EGRESS_FABRIC_DROP_THRESHOLD_ALL_EXCEPT_TDM  "egress_fabric_drop_threshold_all_except_tdm"
 
 /*   Drop all traffic according to Delete-FIFO available resources (number of packet descriptors which can be added to Delete-FIFO). */
 #define spn_EGRESS_FABRIC_DROP_THRESHOLD_ALL  "egress_fabric_drop_threshold_all"
 
 /* Initialize port with CL72 enabled */
 #define spn_PORT_INIT_CL72  "port_init_cl72"
 
 /* In repeater mode: set destination for link */
 #define spn_REPEATER_LINK_DEST  "repeater_link_dest"
 
 /* If set, the link is connected to a fabric in a repeater mode. */
 #define spn_REPEATER_LINK_ENABLE  "repeater_link_enable"
 
 /* Used to define the fragment number used for TDM identification */
 #define spn_FABRIC_TDM_FRAGMENT  "fabric_tdm_fragment"
 
 /* Allows single pipe device to send TDM traffic over the fabric primary pipe.  */
 #define spn_FABRIC_TDM_OVER_PRIMARY_PIPE  "fabric_tdm_over_primary_pipe"
 
 /* Configures a specific fabric priority (and all higher priorities) as TDM */
 #define spn_FABRIC_TDM_PRIORITY_MIN  "fabric_tdm_priority_min"
 
 /* Defines the priority for VCS128 unicast cells  */
 #define spn_VCS128_UNICAST_PRIORITY  "vcs128_unicast_priority"
 
 /* If the BCM88750 is connected with links 0 - 11, 16 - 27, 32 - 43, 48 - 59, 64 - 75, 80 - 91, 96 - 107, 112 - 123 (first 12 in every 16 links group), and the secondary switch is used, then its secondary TX FIFOs can use the memory of the unused links, thus increasing their capacity by 33 percent  to 144 entries.  */
 #define spn_FABRIC_OPTIMIZE_PARTIAL_LINKS  "fabric_optimize_partial_links"
 
 /* Set range of MC IDs */
 #define spn_FE_MC_ID_RANGE  "fe_mc_id_range"
 
 
 
 
 /* Map all incoming multicast traffic to the secondary switch  */
 #define spn_SECONDARY_IS_MULTICAST  "secondary_is_multicast"
 
 
 /* Enable mapping internal multicast priority from priority field. */
 #define spn_FE_MC_PRIORITY_MAP_ENABLE  "fe_mc_priority_map_enable"
 
 
 /* High voltage driver strap. If 0, connected to 1.4V supply; if 1, connected to 1V mode. */
 #define spn_SRD_TX_DRV_HV_DISABLE  "srd_tx_drv_hv_disable"
 /*
  * If True, then Packets coming from this TM Port have a
  * Statistic Tag header. The Statistic Header position is
  * defined globally according to the pb_itm_stag_set
  * API. Relevant only if the header type is TM.
  */
 #define spn_STAG_ENABLE  "stag_enable"
 /*
  * If True, then Packets coming from this TM Port have a
  * first header to strip before any processing. For
  * example, in the Fat Pipe processing a Sequence Number
  * header (2 Bytes) must be stripped.
  * For injected packets, the PTCH Header must be
  * removed (4 Bytes).
  * Units: Bytes. Range: 0 - 63.
  */
 #define spn_FIRST_HEADER_SIZE  "first_header_size"
 /*
  * If True, then ITMH packets arriving from this port have their header stripped
  * length according to the SOC property
  */
 #define spn_POST_HEADERS_SIZE  "post_headers_size"
 /*
  * Flow control type:
  * NONE
  * LL: Link-level.
  * CB2: Class-Based Flow Control (2 classes).
  * CB8: Class-Based Flow Control (8 classes).
  */
 #define spn_FLOW_CONTROL_TYPE  "flow_control_type"
 /*
  * If True, then Packets coming from this TM Port are snooped
  * according to the ITMH. Snoop action command
  */
 #define spn_SNOOP_ENABLE  "snoop_enable"
 /*
  * Inbound mirroring action command (i.e., its profile) for this
  * PP Port. Range: 0 - 15.
  * Relevant only if the header type is not Ethernet.
  */
 #define spn_MIRROR_PROFILE  "mirror_profile"
 /*
  * If True, then TM Packets can come with an Ingress Shaping header
  * before the ITMH. Relevant only if the header type is TM.
  */
 #define spn_TM_INGRESS_SHAPING_ENABLE  "tm_ingress_shaping_enable"
 /*
  * If True, then TM Packets can come with a PPH header
  * after the ITMH (the PPH-present bit in the ITMH can be set).
  * Relevant only if the header type is TM.
  */
 #define spn_TM_PPH_PPH_PRESENT_ENABLE  "tm_pph_pph_present_enable"
 
 /* bcm local port to BCM88X4X tm port mapping. */
 #define spn_LOCAL_TO_TM_PORT  "local_to_tm_port"
 
 /* bcm local port to BCM88X4X pp port mapping. */
 #define spn_LOCAL_TO_PP_PORT  "local_to_pp_port"
 /*
  * System cell format.
  * Allowed values:
  * FCS: Fixed cell size
  * VSC128: Variable cell size 128B
  */
 #define spn_SYSTEM_CELL_FORMAT  "system_cell_format"
 /*
  * If TRUE, fabric segmentation will be performed to
  * improve the fabric performance.
  */
 #define spn_FABRIC_SEGMENTATION_ENABLE  "fabric_segmentation_enable"
 /*
  * FTMH load balancing mode.
  * Valid values:
  * DISABLED
  * 8B_LB_KEY_8B_STACKING_ROUTE_HISTORY: load balancing
  * key and an 8-bit stacking route history bitmap.
  * 16B_STACKING_ROUTE_HISTORY: stacking route history.
  * STANDBY_MC_LB: supported in ARAD+.
  */
 #define spn_SYSTEM_FTMH_LOAD_BALANCING_EXT_MODE  "system_ftmh_load_balancing_ext_mode"
 /*
  * Fap device mode:
  * TM: only traffic management features are enabled.
  * PP: packet processing mode.
  * TDM_OPTIMIZED: TDM Cells traffic mode with an Optimized FTMH Header
  *    format. If set, all the devices this device can
  *    communicate with must be configured with the same mode.
  *    Invalid for ARAD.
  * TDM_STANDARD: TDM Cells traffic mode with a Standard FTMH Header
  *   format. In this mode, the device can communicate with
  *   devices (other devices should be configured in TM/PP/TDM_STANDARD mode).
  *   Invalid for ARAD.
  */
 #define spn_FAP_DEVICE_MODE  "fap_device_mode"
 /*
  * supported on ARAD device. If non 0 TDM packets bypass Queuing is enabled
  * operation when in hybrid mode (i.e both data packets and TDM packets).
  * TDM_OPTIMIZED: TDM Cells traffic mode with an Optimized FTMH Header
  *    format. If set, all the devices this device can
  *    communicate with must be configured with the same mode.
  * TDM_STANDARD: TDM Cells traffic mode with a Standard FTMH Header
  *   format. In this mode, the device can communicate with
  *   devices (other devices should be configured in TM/PP/TDM_STANDARD mode).
  */
 #define spn_FAP_TDM_BYPASS  "fap_tdm_bypass"
 
 /* if this soc property is 0, configuring ports to TDM packet mode traffic is not allowed. */
 #define spn_FAP_TDM_PACKET  "fap_tdm_packet"
 /*
  * Supported on ARAD devices.Used to support sending TDM (OTN/CBR) packets from multiple FAPs to a FAP
  * which supports a smaller size of such packets. Like when sending packets
  * from Arad to Petra. The packet source FAP ID will be set tothe ID of the
  * source FAP plus the offset specified here. The resulting value needs to be
  * different than all FAP IDs and different then all other source FAP IDs.
  */
 #define spn_TDM_SOURCE_FAP_ID_OFFSET  "tdm_source_fap_id_offset"
 /*
  * If TRUE, fap20 devices exist in the system. This imposes
  * certain limitations on the device behavior (e.g. fabric
  * cells must be fixed size, fap20-compatible fabric header
  * must be used etc.).
  */
 #define spn_SYSTEM_HAS_FAP20  "system_has_fap20"
 /*
  * If TRUE, fap21 devices exist in the system. This imposes certain
  * limitations on the device behavior (e.g. fabric cells must be fixed size etc.).
  */
 #define spn_SYSTEM_HAS_FAP21  "system_has_fap21"
 /*
  * If TRUE, Petra Rev-A devices exist in the system. This imposes
  * certain limitations on the device behavior (e.g. PPH is in
  * Petra-A compatible mode).
  */
 #define spn_SYSTEM_HAS_PETRA_REV_A  "system_has_petra_rev_a"
 
 /* Whether there is an FE1600 device in the system. */
 #define spn_SYSTEM_IS_FE1600_IN_SYSTEM  "system_is_fe1600_in_system"
 /*
  * Per DRAM interface, defines if exists and needs to be configured.
  * Note: The following number of DRAM interfaces can be configured: 2, 3, 4, 6
  */
 #define spn_EXT_RAM_PRESENT  "ext_ram_present"
 
 /* DRAM type. Values: DDR2/DDR3/GDDR3. */
 #define spn_EXT_RAM_TYPE  "ext_ram_type"
 /*
  * If set, a 16b CRC is appended to the end of the packet in the DRAM
  * (aligned to the last two bytes of a 32B word).
  */
 #define spn_EXT_RAM_PACKET_CRC_ENABLE  "ext_ram_packet_crc_enable"
 
 /* Number of Banks. */
 #define spn_EXT_RAM_BANKS  "ext_ram_banks"
 
 /* Number of DRAM columns. Possible values: 256/512/1024/2048/4096/8192      */
 #define spn_EXT_RAM_COLUMNS  "ext_ram_columns"
 
 /* Summarized DRAM size of all DRAM interfaces. Units: Mbytes. */
 #define spn_EXT_RAM_TOTAL_SIZE  "ext_ram_total_size"
 
 /* Autorun Shmoo Tuning on Init */
 #define spn_EXT_RAM_AUTO_TUNE  "ext_ram_auto_tune"
 
 /* Total buffer size allocated for User buffer. Units: Mbytes. */
 #define spn_USER_BUFFER_SIZE  "user_buffer_size"
 /*
  * The size of a single data buffer in the DRAM
  * Allowed values: 256/512/1024/2048
  */
 #define spn_EXT_RAM_DBUFF_SIZE  "ext_ram_dbuff_size"
 
 /* DRAM frequency */
 #define spn_EXT_RAM_FREQ  "ext_ram_freq"
 /*
  * Auto precharge bit position. Determines the position of the Auto
  * Precharge bit in the address going to the DRAM
  */
 #define spn_EXT_RAM_AP_BIT_POS  "ext_ram_ap_bit_pos"
 
 /* Dram burst size. May be 16 or 32 bytes. Must be set according to the dram's burst size */
 #define spn_EXT_RAM_BURST_SIZE  "ext_ram_burst_size"
 /*
  * Column Address Strobe latency. The period (clocks) between READ command and valid
  * read data presented on the data out pins of the dram.
  */
 #define spn_EXT_RAM_C_CAS_LATENCY  "ext_ram_c_cas_latency"
 
 /* The period (clocks) between WRITE command and write data set on the dram data in pins. */
 #define spn_EXT_RAM_C_WR_LATENCY  "ext_ram_c_wr_latency"
 /*
  * Refresh Cycle. Period (ps) between the active to the active/auto refresh commands.
  * By default this period is stated in terms of picoseconds. To state it in terms of
  * number of clocks add "c" suffix to the value (e.g. 1000 is 1000 ps, and 1000c is 1000 clocks)
  */
 #define spn_EXT_RAM_T_RC  "ext_ram_t_rc"
 /*
  * Row Refresh Cycle. Auto refresh command period. The minimal period (ps) between
  * the refresh command and the next active command. By default this period is stated
  * in terms of picoseconds. To state it in terms of number of clocks add "c" suffix to the value (e.g. 1000 is 1000 ps, and 1000c is 1000 clocks)
  */
 #define spn_EXT_RAM_T_RFC  "ext_ram_t_rfc"
 /*
  * Row Address Strobe. The minimal period (ps) needed to access a certain row of data
  * in RAM between the data request and the precharge command. By default this period is
  * stated in terms of picoseconds. To state it in terms of number of clocks add",
                      "c" suffix to the value (e.g. 1000 is 1000 ps, and 1000c is 1000 clocks)
  */
 #define spn_EXT_RAM_T_RAS  "ext_ram_t_ras"
 /*
  * The ext_ram_t_ras_enable is used to control if the value of t_ras config to hw, the default value sets to 0
  * if ext_ram_t_ras_enable is 1, the driver will use ext_ram_t_ras value, otherwise it will set to 0!
  */
 #define spn_EXT_RAM_T_RAS_ENABLE  "ext_ram_t_ras_enable"
 /*
  * Four Active Window. No more than four banks may be activated in a rolling window. By
  * default this period is stated in terms of picoseconds. To state it in terms of number
  * of clocks add "c" suffix to the value (e.g. 1000 is 1000 ps, and 1000c is 1000 clocks)
  */
 #define spn_EXT_RAM_T_FAW  "ext_ram_t_faw"
 /*
  * Row address to Column address Delay. The minimal period (ps) needed between
  * RAS and CAS. It is the time required between row activation and read access
  * to the column of the given memory block. By default this period is stated in
  * terms of picoseconds. To state it in terms of number of clocks add
  * "c" suffix to the value (e.g. 1000 is 1000 ps, and 1000c is 1000 clocks)
  */
 #define spn_EXT_RAM_T_RCD_RD  "ext_ram_t_rcd_rd"
 /*
  * Row address to Column address Delay. The minimal period (ps) needed between
  * RAS and CAS. It is the time required between row activation and write access
  * to the column of the given memory block. By default this period is stated in
  * terms of picoseconds. To state it in terms of number of clocks add
  * "c" suffix to the value (e.g. 1000 is 1000 ps, and 1000c is 1000 clocks)
  */
 #define spn_EXT_RAM_T_RCD_WR  "ext_ram_t_rcd_wr"
 /*
  * RAS To RAS delay. Active bank a to active bank command. By default this
  * period is stated in terms of picoseconds. To state it in terms of number
  * of clocks add "c" suffix to the value (e.g. 1000 is 1000 ps, and 1000c is 1000 clocks)
  */
 #define spn_EXT_RAM_T_RRD  "ext_ram_t_rrd"
 /*
  * Row Precharge. The minimal period between pre-charge action of a certain
  * Row and the next consecutive action to the same bank/row. By default this
  * period is stated in terms of picoseconds. To state it in terms of number
  * of clocks add "c" suffix to the value (e.g. 1000 is 1000 ps, and 1000c is 1000 clocks)
  */
 #define spn_EXT_RAM_T_RP  "ext_ram_t_rp"
 /*
  * Write Recovery Time. Specifies the period (ps) that must elapse after
  * the completion of a valid write operation, before a pre-charge command
  * can be issued. By default this period is stated in terms of picoseconds.
  * To state it in terms of number of clocks add "c" suffix to the value (e.g. 1000 is 1000 ps, and 1000c is 1000 clocks)
  */
 #define spn_EXT_RAM_T_WR  "ext_ram_t_wr"
 /*
  * Average periodic refresh interval.
  * By default this period is stated in terms of picoseconds. To state
  * The value 0 disables the auto refresh mechanism.
  * To state it in terms of number of clocks add "c" suffix to the value (e.g. 1000 is 1000 ps, and 1000c is 1000 clocks)
  */
 #define spn_EXT_RAM_T_REF  "ext_ram_t_ref"
 /*
  * Write To Read Delay. The minimal period (ps) that must elapse between the
  * last valid write operation and the next read command to the same internal
  * bank of the DDR device. By default this period is stated in terms of picoseconds.
  * To state it in terms of number of clocks add "c" suffix to the value (e.g. 1000 is 1000 ps, and 1000c is 1000 clocks)
  */
 #define spn_EXT_RAM_T_WTR  "ext_ram_t_wtr"
 /*
  * Read To Precharge Delay. By default this period is stated in terms of picoseconds.
  * To state it in terms of number of clocks add "c" suffix to the value (e.g. 1000 is 1000 ps, and 1000c is 1000 clocks)
  */
 #define spn_EXT_RAM_T_RTP  "ext_ram_t_rtp"
 
 /* Jedec - Joint Electron Devices Engineering Council. */
 #define spn_EXT_RAM_JEDEC  "ext_ram_jedec"
 /*
  * RAS To RAS delay (Same).
  * ACTIVATE to ACTIVATE Command delay to same bank group (tRRD_L).
  * By default this period is stated in terms of picoseconds.
  * To state it in terms of number of clocks add "c" suffix to the value (e.g. 1000 is 1000 ps, and 1000c is 1000 clocks).
  */
 #define spn_EXT_RAM_T_RRD_L  "ext_ram_t_rrd_l"
 /*
  * RAS To RAS delay (Diff).
  * ACTIVATE to ACTIVATE Command delay to different bank group (tRRD_S).
  * By default this period is stated in terms of picoseconds.
  * To state it in terms of number of clocks add "c" suffix to the value (e.g. 1000 is 1000 ps, and 1000c is 1000 clocks).
  */
 #define spn_EXT_RAM_T_RRD_S  "ext_ram_t_rrd_s"
 /*
  * Thirty two bank activate window.
  * No more than 32 banks may be activated in a rolling t32AW window. (t32AW).
  * By default this period is stated in terms of picoseconds.
  * To state it in terms of number of clocks add "c" suffix to the value (e.g. 1000 is 1000 ps, and 1000c is 1000 clocks).
  */
 #define spn_EXT_RAM_T_32AW  "ext_ram_t_32aw"
 /*
  * READ to PRECHARGE command delay same bank with bank groups enabled (tRTP_L).
  * By default this period is stated in terms of picoseconds.
  * To state it in terms of number of clocks add "c" suffix to the value (e.g. 1000 is 1000 ps, and 1000c is 1000 clocks).
  */
 #define spn_EXT_RAM_T_RTP_L  "ext_ram_t_rtp_l"
 /*
  * READ to PRECHARGE command delay different bank with bank groups enabled (tRTP_S).
  * By default this period is stated in terms of picoseconds.
  * To state it in terms of number of clocks add "c" suffix to the value (e.g. 1000 is 1000 ps, and 1000c is 1000 clocks).
  */
 #define spn_EXT_RAM_T_RTP_S  "ext_ram_t_rtp_s"
 /*
  * Write To Read Delay (Same).
  * The minimal period that must elapse between the last valid write operation and the next read command to the same internal bank of the DDR device (tWTR_L).
  * By default this period is stated in terms of picoseconds.
  * To state it in terms of number of clocks add "c" suffix to the value (e.g. 1000 is 1000 ps, and 1000c is 1000 clocks).
  */
 #define spn_EXT_RAM_T_WTR_L  "ext_ram_t_wtr_l"
 /*
  * Write To Read Delay (Diff).
  * The minimal period that must elapse between the last valid write operation and the next read command to the different internal bank of the DDR device (tWTR_S).
  * By default this period is stated in terms of picoseconds.
  * To state it in terms of number of clocks add "c" suffix to the value (e.g. 1000 is 1000 ps, and 1000c is 1000 clocks).
  */
 #define spn_EXT_RAM_T_WTR_S  "ext_ram_t_wtr_s"
 /*
  * RD/WR bank A to RD/WR bank B command delay same bank group (tCCD_L).
  * By default this period is stated in terms of picoseconds.
  * To state it in terms of number of clocks add "c" suffix to the value (e.g. 1000 is 1000 ps, and 1000c is 1000 clocks).
  */
 #define spn_EXT_RAM_T_CCD_L  "ext_ram_t_ccd_l"
 /*
  * RD/WR bank A to RD/WR bank B command delay different bank group (tCCD_S).
  * By default this period is stated in terms of picoseconds.
  * To state it in terms of number of clocks add "c" suffix to the value (e.g. 1000 is 1000 ps, and 1000c is 1000 clocks).
  */
 #define spn_EXT_RAM_T_CCD_S  "ext_ram_t_ccd_s"
 /*
  * Normal operation Short calibration time (tZQCS).
  * By default this period is stated in terms of picoseconds.
  * To state it in terms of number of clocks add "c" suffix to the value (e.g. 1000 is 1000 ps, and 1000c is 1000 clocks).
  */
 #define spn_EXT_RAM_T_ZQCS  "ext_ram_t_zqcs"
 /*
  * CRC error to ALERT_n latency (tCRC_ALERT.)
  * By default this period is stated in terms of picoseconds.
  * To state it in terms of number of clocks add "c" suffix to the value (e.g. 1000 is 1000 ps, and 1000c is 1000 clocks).
  */
 #define spn_EXT_RAM_T_CRC_ALERT  "ext_ram_t_crc_alert"
 /*
  * Number of clocks to wait after reset (tRST).
  * By default this period is stated in terms of picoseconds.
  * To state it in terms of number of clocks add "c" suffix to the value (e.g. 1000 is 1000 ps, and 1000c is 1000 clocks).
  */
 #define spn_EXT_RAM_T_RST  "ext_ram_t_rst"
 /*
  * Additive latency add to user (tAL).
  * By default this period is stated in terms of picoseconds.
  * To state it in terms of number of clocks add "c" suffix to the value (e.g. 1000 is 1000 ps, and 1000c is 1000 clocks).
  */
 #define spn_EXT_RAM_T_AL  "ext_ram_t_al"
 /*
  * CRC Read Latency (tCRCRL).
  * By default this period is stated in terms of picoseconds.
  * To state it in terms of number of clocks add "c" suffix to the value (e.g. 1000 is 1000 ps, and 1000c is 1000 clocks).
  */
 #define spn_EXT_RAM_T_CRC_RD_LATENCY  "ext_ram_t_crc_rd_latency"
 /*
  * CRC Write Latency (tCRCWL).
  * By default this period is stated in terms of picoseconds.
  * To state it in terms of number of clocks add "c" suffix to the value (e.g. 1000 is 1000 ps, and 1000c is 1000 clocks).
  */
 #define spn_EXT_RAM_T_CRC_WR_LATENCY  "ext_ram_t_crc_wr_latency"
 
 /* Wait period (Clocks) between commands during INIT sequence. Range: 0-0x3ff. Default: 0x3ff. */
 #define spn_EXT_RAM_INIT_WAIT_PERIOD  "ext_ram_init_wait_period"
 /*
  * Dram Gear down mode.
  * Valid values: 0 - Enable, 1 - Disable. Default: 0x0.
  */
 #define spn_EXT_RAM_GEAR_DOWN_MODE  "ext_ram_gear_down_mode"
 /*
  * Dram Address bus inversion.
  * Valid values: 0 - Enable, 1 - Disable. Default: 0x0.
  */
 #define spn_EXT_RAM_ABI  "ext_ram_abi"
 /*
  * Data bus inversion on write direction.
  * Valid values: 0 - Enable, 1 - Disable. Default: 0x0.
  */
 #define spn_EXT_RAM_WRITE_DBI  "ext_ram_write_dbi"
 /*
  * Data bus inversion on read direction.
  * Valid values: 0 - Enable, 1 - Disable. Default: 0x0.
  */
 #define spn_EXT_RAM_READ_DBI  "ext_ram_read_dbi"
 /*
  * Command parity latency.
  * Valid values: 0 - Enable, 1 - Disable. Default: 0x0.
  */
 #define spn_EXT_RAM_CMD_PAR_LATENCY  "ext_ram_cmd_par_latency"
 /*
  * Enable write CRC 
  * Valid values: 0 - Enable, 1 - Disable. Default: 0x0.
  */
 #define spn_EXT_RAM_WRITE_CRC  "ext_ram_write_crc"
 /*
  * Enable read CRC (DDR4 does not support read CRC)
  * Valid values: 0 - Enable, 1 - Disable. Default: 0x0.
  */
 #define spn_EXT_RAM_READ_CRC  "ext_ram_read_crc"
 /*
  * Dram Addr Bank Swap.
  * Format: ext_ram_addr_bank_swap_dramX_bitY=M. Means, In dram X, swap addr/bank bit Y and M.
  * Default: No swapping.
  */
 #define spn_EXT_RAM_ADDR_BANK_SWAP  "ext_ram_addr_bank_swap"
 /*
  * Dram DQ Swap.
  * Format: ext_ram_dq_swap_dramX_byteY_bitZ=M. Means, In dram X, Byte Y swap DQ Z and M.
  * Default: No swapping.
  */
 #define spn_EXT_RAM_DQ_SWAP  "ext_ram_dq_swap"
 
 /* DDR2 - MRS0 (1st write) */
 #define spn_EXT_RAM_DDR2_MRS0_WR1  "ext_ram_ddr2_mrs0_wr1"
 
 /* DDR2 - MRS0 (2nd write) */
 #define spn_EXT_RAM_DDR2_MRS0_WR2  "ext_ram_ddr2_mrs0_wr2"
 
 /* DDR2 - EMR0 (1st write) */
 #define spn_EXT_RAM_DDR2_EMR0_WR1  "ext_ram_ddr2_emr0_wr1"
 
 /* DDR2 - EMR0 (2nd write) */
 #define spn_EXT_RAM_DDR2_EMR0_WR2  "ext_ram_ddr2_emr0_wr2"
 
 /* DDR2 - EMR0 (3rd write) */
 #define spn_EXT_RAM_DDR2_EMR0_WR3  "ext_ram_ddr2_emr0_wr3"
 
 /* DDR2 - EMR1 (1st write) */
 #define spn_EXT_RAM_DDR2_EMR1_WR1  "ext_ram_ddr2_emr1_wr1"
 
 /* DDR2 - EMR2 (1st write) */
 #define spn_EXT_RAM_DDR2_EMR2_WR1  "ext_ram_ddr2_emr2_wr1"
 
 /* DDR3 - MRS0 (1st write) */
 #define spn_EXT_RAM_DDR3_MRS0_WR1  "ext_ram_ddr3_mrs0_wr1"
 
 /* DDR3 - MRS0 (2nd write) */
 #define spn_EXT_RAM_DDR3_MRS0_WR2  "ext_ram_ddr3_mrs0_wr2"
 
 /* DDR3 - MRS1 (1st write) */
 #define spn_EXT_RAM_DDR3_MRS1_WR1  "ext_ram_ddr3_mrs1_wr1"
 
 /* DDR3 - MRS2 (1st write) */
 #define spn_EXT_RAM_DDR3_MRS2_WR1  "ext_ram_ddr3_mrs2_wr1"
 
 /* DDR3 - MRS3 (1st write) */
 #define spn_EXT_RAM_DDR3_MRS3_WR1  "ext_ram_ddr3_mrs3_wr1"
 
 /* GDD3 - MRS0 (1st write) */
 #define spn_EXT_RAM_GDDR3_MRS0_WR1  "ext_ram_gddr3_mrs0_wr1"
 
 /* GDD3 - EMR0 (1st write) */
 #define spn_EXT_RAM_GDDR3_EMR0_WR1  "ext_ram_gddr3_emr0_wr1"
 /*
  * Petra-B DRAM PLL.
  * Must be set for Petra-B revision A1 and above.
  * In this case, the PETRA_HW_PLL_PARAMS structure of the dram HW_ADJUSTMENTS
  * configuration is ignored
  * The DRAM frequency is derived from the following formula:
  * F-out = F-Ref*(2*(f+1)/[(r+1)*2^q]), where F-out is twice the DRAM frequency.
  * Limitations:
  * 75MHz   <= F-ref    <= 175MHz
  * 25MHz   <= F-ref/r+1 <= 45MHz
  * 1600MHz <= F-vco    <= 3200MHz
  * 
  * Valid range for r: 0-7.
  */
 #define spn_EXT_RAM_PLL_R  "ext_ram_pll_r"
 
 /* Range: 17 - 63. */
 #define spn_EXT_RAM_PLL_F  "ext_ram_pll_f"
 
 /* Range: 1 - 4. */
 #define spn_EXT_RAM_PLL_Q  "ext_ram_pll_q"
 /*
  * Select Parity or ECC protection type.
  * Values: PARITY/ECC.
  */
 #define spn_EXT_QDR_PROTECTION_TYPE  "ext_qdr_protection_type"
 
 /* If TRUE, the 250Mhz Core clock is used as QDR reference clock. Otherwise (lower frequency) - QDR clock is used. In the later case, pll configuration must be set. */
 #define spn_EXT_QDR_USE_CORE_CLOCK_FREQ  "ext_qdr_use_core_clock_freq"
 /*
  * QDR type. Allowed values:
  * QDR: QDR type 2. This is the default QDR type
  *   and can typically be used also for QDR type 2-plus and
  *   QDR type 3
  * QDR2P: QDR type 2-plus. Choosing this value
  *   may be needed if using this QDR type
  * QDR3: QDR type 3. Choosing this value
  *   may be needed if using this QDR type
  * NONE: No QDR is used.
  */
 #define spn_EXT_QDR_TYPE  "ext_qdr_type"
 /*
  * QDR Pll configuration as derived from the QDR reference
  * clock. Note: this field is only relevant if
  * is_core_clock_freq is FALSE - ignored otherwise.
  * CAUTION: it is a misconfiguration to use QDR clock,
  * configured to the Core clock frequency (250Mhz) or above!
  */
 #define spn_EXT_QDR_PLL_M  "ext_qdr_pll_m"
 
 /* Pll-N */
 #define spn_EXT_QDR_PLL_N  "ext_qdr_pll_n"
 
 /* Pll-P */
 #define spn_EXT_QDR_PLL_P  "ext_qdr_pll_p"
 /*
  * Total QDR SRAM memory size
  * Units: Mbits.
  */
 #define spn_EXT_QDR_SIZE_MBIT  "ext_qdr_size_mbit"
 
 /* MPLS ELSP Minimum label range */
 #define spn_MPLS_ELSP_LABEL_RANGE_MIN  "mpls_elsp_label_range_min"
 
 /* MPLS ELSP Maximum label range */
 #define spn_MPLS_ELSP_LABEL_RANGE_MAX  "mpls_elsp_label_range_max"
 /*
  * The reference clock that feeds the Fabric CMU-s. Units: KHz.
  * If m/n are not forced to zero, only the below values
  * are valid:
  * 12500/156250/200000/212500/218750/312500
  */
 #define spn_FABRIC_REF_CLOCK  "fabric_ref_clock"
 /*
  * Force m/n divisors, when referring serdes rate from reference clock.
  * Add suffix _fabric0/_combo0/_nif0 to choose which clock domain to configure.
  */
 #define spn_FORCE_CLK_M_N_DIVISORS_ZERO  "force_clk_m_n_divisors_zero"
 /*
  * Number of ticks the 88640 and 88650 devices clock ticks per second (about a tick every
  * 4.00 nanoseconds).Default value 88640: 250. Default value 88650: 600. Units: MHz.
  * Range for 88640: 150 - 300. For 88650: 150-900
  */
 #define spn_CORE_CLOCK_SPEED  "core_clock_speed"
 
 /* Enable statistics interface */
 #define spn_STAT_IF_ENABLE  "stat_if_enable"
 /*
  * Statistics interface rate in Mbps
  * If Value is '0' the statistics port rate will be used. Default: 0.
  */
 #define spn_STAT_IF_RATE  "stat_if_rate"
 /*
  * Enable statistics reports on EnQueue.
  * Valid valued: 0/1.
  * Default: '1'.
  */
 #define spn_STAT_IF_REPORT_ENQUEUE_ENABLE  "stat_if_report_enqueue_enable"
 /*
  * Enable statistics reports on DeQueue.
  * Valid valued: 0/1.
  * Default: '1'.
  */
 #define spn_STAT_IF_REPORT_DEQUEUE_ENABLE  "stat_if_report_dequeue_enable"
 /*
  * Statistics interface phase.
  * Valid valued: 0/90/180/270.
  */
 #define spn_STAT_IF_PHASE  "stat_if_phase"
 /*
  * If False, no idle period and set to 0 (StBillNullPrd & StQszIdlePrd) otherwise, to the maximum value
  * Valid valued: TRUE/FALSE
  */
 #define spn_STAT_IF_IDLE_REPORTS_PRESENT  "stat_if_idle_reports_present"
 /*
  * If True, then only a single copy per multicast packet
  * (for ingress replication multicast packets) is reported.
  * Otherwise, all the packets are reported.
  */
 #define spn_STAT_IF_REPORT_MULTICAST_SINGLE_COPY  "stat_if_report_multicast_single_copy"
 /*
  * Statistics-Report (packet) size.
  * Valid valued: 65B/126B/248B/492B (Queue-Size), 64B/128B/256B/512B/1024B (Billing).
  */
 #define spn_STAT_IF_PKT_SIZE  "stat_if_pkt_size"
 /*
  * Selective report Queue range
  * Reports will be generated for traffic transferred through these queues
  * Valid valued: 0-96K-1
  */
 #define spn_STAT_IF_SELECTIVE_REPORT_QUEUE_MIN  "stat_if_selective_report_queue_min"
 /*
  * Selective report Queue range
  * Reports will be generated for traffic transferred through these queues
  * Valid valued: 0-96K-1
  */
 #define spn_STAT_IF_SELECTIVE_REPORT_QUEUE_MAX  "stat_if_selective_report_queue_max"
 /*
  * Scrubber Queue range
  * Valid valued: 0/96K-1
  */
 #define spn_STAT_IF_SCRUBBER_QUEUE_MIN  "stat_if_scrubber_queue_min"
 /*
  * Scrubber Queue range
  * Valid valued: 0/96K-1
  */
 #define spn_STAT_IF_SCRUBBER_QUEUE_MAX  "stat_if_scrubber_queue_max"
 /*
  * Scrubber Rate
  * Valid valued: more than 0
  */
 #define spn_STAT_IF_SCRUBBER_RATE_MIN  "stat_if_scrubber_rate_min"
 /*
  * Scrubber Rate
  * Valid valued: more than 0
  */
 #define spn_STAT_IF_SCRUBBER_RATE_MAX  "stat_if_scrubber_rate_max"
 /*
  * Buffer descriptor threshold
  * -1 - ignore threshold
  */
 #define spn_STAT_IF_SCRUBBER_BUFFER_DESCR_TH  "stat_if_scrubber_buffer_descr_th"
 /*
  * Buffer descriptor buffers (BDBs) threshold
  * -1 - ignore threshold
  */
 #define spn_STAT_IF_SCRUBBER_BDB_TH  "stat_if_scrubber_bdb_th"
 /*
  * unicast DRAM buffers threshold
  * -1 - ignore threshold
  */
 #define spn_STAT_IF_SCRUBBER_UC_DRAM_BUFFER_TH  "stat_if_scrubber_uc_dram_buffer_th"
 
 /* If set, enable Statistics interface Scrubber functionality. */
 #define spn_STAT_IF_SCRUBBER_ENABLE  "stat_if_scrubber_enable"
 
 /* Statistics report mode. Valid values: BILLING/FAP20V/QSIZE. */
 #define spn_STAT_IF_REPORT_MODE  "stat_if_report_mode"
 /*
  * Select between Packet-size and Queue-size formats.
  * Valid values: QUEUE/PACKET.
  */
 #define spn_STAT_IF_REPORT_FAP20V_MODE  "stat_if_report_fap20v_mode"
 /*
  * Multicast report format for the Fabric Multicast: report
  * of the copies with their Queue number or with their
  * Multicast-Ids. Valid only if the mode is PACKET.
  * Valid values: QUEUE_NUM/MC_ID.
  */
 #define spn_STAT_IF_REPORT_FAP20V_FABRIC_MC  "stat_if_report_fap20v_fabric_mc"
 /*
  * Multicast report format for the Ingress Replication
  * Multicast: report of the copies with their Queue number
  * or with their Multicast-Ids. Valid only if the mode is
  * PKT_SIZE.
  * Valid values: QUEUE_NUM/MC_ID.
  */
 #define spn_STAT_IF_REPORT_FAP20V_ING_MC  "stat_if_report_fap20v_ing_mc"
 /*
  * Applicable for Petra-B only. TRUE - snoop/mirror packets
  * are also counted in the Copy-Count
  */
 #define spn_STAT_IF_REPORT_FAP20V_COUNT_SNOOP  "stat_if_report_fap20v_count_snoop"
 /*
  * If True, then the reported packet size is the one at the
  * packet reception. Otherwise, the reported packet size is
  * the one after the header editing.
  */
 #define spn_STAT_IF_REPORT_ORIGINAL_PKT_SIZE  "stat_if_report_original_pkt_size"
 /*
  * If True, then only a single copy per multicast packet
  * (for ingress replication multicast packets) is reported.
  * Otherwise, all the packets are reported.
  */
 #define spn_STAT_IF_REPORT_FAP20V_ING_MC_REPORT_SINGLE  "stat_if_report_fap20v_ing_mc_report_single"
 /*
  * If True, then only a single copy per multicast packet
  * (for ingress replication multicast packets) is reported.
  * Otherwise, all the packets are reported.
  */
 #define spn_STAT_IF_REPORT_FAP20V_SINGLE_COPY_REPORTED  "stat_if_report_fap20v_single_copy_reported"
 /*
  * If TRUE, CNM (Congestion Notification Message) packet statistics
  * are reported. Valid only if the FAP20V mode is PACKET.
  */
 #define spn_STAT_IF_REPORT_FAP20V_CNM_REPORT  "stat_if_report_fap20v_cnm_report"
 /*
  * Billing mode for the egress report.
  * Valid values:
  * EGR_Q_NB: Egress queue number presentation in the egress report.
  * CUD: Copy-Unique-Data (Out-LIF) presentation in the egress report.
  * VSI_VLAN: Egress statistics according to the VSI (VLAN).
  * BOTH_LIFS: Both In-LIF and Out-LIF presentations in the egress
  */
 #define spn_STAT_IF_REPORT_BILLING_MODE  "stat_if_report_billing_mode"
 /*
  * Statistics interface sync period in nanoseconds. Defines maximal period
  * between consecutive sync patterns transmitted on the statistics interface.
  * Zero disables sync patterns transmission. Maximum value: 0xffffffff.
  */
 #define spn_STAT_IF_SYNC_RATE  "stat_if_sync_rate"
 /*
  * If TRUE, parity checking is enabled. Reports with
  * parity-errors are discarded. The parity indications
  * are on expense of some other fields, as described in
  * the statistics report format documentation.
  */
 #define spn_STAT_IF_PARITY_ENABLE  "stat_if_parity_enable"
 
 /* Traffic Class source in the Statistic-Reports */
 #define spn_STAT_IF_TC_SOURCE  "stat_if_tc_source"
 /*
  * If set to DEDICATED, then each core works with a seperate statistics interface
  * If set to UNIFIED, then both cores with the same statistics interface
  */
 #define spn_STAT_IF_CORE_MODE  "stat_if_core_mode"
 /*
  * Determines the report size when working in SIF queue size mode, can choose
  * between 61b, the arad format, or 64b, the jericho format
  */
 #define spn_STAT_IF_REPORT_SIZE  "stat_if_report_size"
 /*
  * Determines the number of statistics reports provided in each packet outputted
  * by the statistics interface, options are: 8/16/32/64/128
  */
 #define spn_STAT_IF_REPORTS_PER_PACKET  "stat_if_reports_per_packet"
 /*
  * Determines whether the ingress reports should be stamped with the queue number
  * Valid options are 0/1
  */
 #define spn_STAT_IF_BILLING_INGRESS_QUEUE_STAMP_ENABLE  "stat_if_billing_ingress_queue_stamp_enable"
 /*
  * Enables drop reason field in ingress reports
  * Valid options are 0/1
  */
 #define spn_STAT_IF_BILLING_INGRESS_DROP_REASON_ENABLE  "stat_if_billing_ingress_drop_reason_enable"
 /*
  * Enables filtering in reports generation in billing mode
  * must be used with egress/ingress suffix
  * Valid options are 0/1
  */
 #define spn_STAT_IF_BILLING_FILTER_REPORTS  "stat_if_billing_filter_reports"
 /*
  * If set, the CPU streaming IF is in Multi-Port Mode.
  * Otherwise, the CPU is in Single-Port Mode.
  */
 #define spn_STREAMING_IF_MULTI_PORT_MODE  "streaming_if_multi_port_mode"
 /*
  * If set, the CSI time-out counter is activated and
  * the CSI will send a read reply command back to
  * the CPU after timeout_prd cycles, if no read
  * reply was received from the Petra blocks.
  */
 #define spn_STREAMING_IF_ENABLE_TIMEOUTCNT  "streaming_if_enable_timeoutcnt"
 /*
  * Number of cycles the CSI waits for a read reply from
  * the Petra blocks before issuing a read reply command.
  */
 #define spn_STREAMING_IF_TIMEOUT_PRD  "streaming_if_timeout_prd"
 /*
  * If set, the CSI will not send a reply command for
  * write requests. As for read requests, the CSI will
  * send a 32b reply command containing the read data only.
  */
 #define spn_STREAMING_IF_QUIET_MODE  "streaming_if_quiet_mode"
 /*
  * If set, the CSI does not discard data received with a
  * parity error and treats it as valid data. Default is
  * to set this register to assist in the bring-up phase.
  * The application should clear this register after the
  * CPU interface is working.
  */
 #define spn_STREAMING_IF_DISCARD_BAD_PARITY  "streaming_if_discard_bad_parity"
 /*
  * If set, disables transmitting packets over the streaming
  * interface. These packets can be read through the
  * cpu_asynchronous_packet_data address.
  */
 #define spn_STREAMING_IF_DISCARD_PKT_STREAMING  "streaming_if_discard_pkt_streaming"
 /*
  * Out of total of 15 SerDes quartets, two (one per internal NIF Group
  * consisting of 4 MALs) may be assigned to either Network or Fabric interfaces.
  * If TRUE, combo is used towards the network. Else, it is used towards the fabric.
  * Use suffix 0 for combo-A or 1 for combo-B.
  */
 #define spn_COMBO_NIF  "combo_nif"
 /*
  * The reference clock that feeds the NIF CMU-s. Units: KHz.
  * If m/n are not forced to zero, only the below values
  * are valid:
  * 12500/156250/200000/212500/218750/312500
  */
 #define spn_NIF_REF_CLOCK  "nif_ref_clock"
 /*
  * The reference clock that feeds the Combo CMU-s. The combo CMU-s can be dedicated
  * to either NIF or fabric - refer to the `shared_quartet' configuration in the operation mode.
  * Units: KHz.
  * If m/n are not forced to zero, only the below values
  * are valid:
  * 12500/156250/200000/212500/218750/312500
  */
 #define spn_COMBO_REF_CLOCK  "combo_ref_clock"
 /*
  * Enable/Disable Rx/Tx lanes swap.
  * Note: This is applicable for XAUI/RXAUI interfaces only
  * Default: disabled. 
  */
 #define spn_LANES_SWAP  "lanes_swap"
 /*
  * If TRUE - the link partner`s bus size is 64 bits length. If FALSE - the
  * link partner`s bus size is 32 bits length. 
  */
 #define spn_SPAUI_LINK_PARTNER_DOUBLE_SIZE_BUS  "spaui_link_partner_double_size_bus"
 /*
  * Relevant only if link_partner_double_size_bus is set, ignored otherwise.
  * If TRUE - the SOP will be only in odd position.
  */
 #define spn_SPAUI_IS_DOUBLE_SIZE_SOP_ODD_ONLY  "spaui_is_double_size_sop_odd_only"
 /*
  * Relevant only if link_partner_double_size_bus is set, ignored otherwise.
  * If TRUE - the SOP will be only in even position.
  */
 #define spn_SPAUI_IS_DOUBLE_SIZE_SOP_EVEN_ONLY  "spaui_is_double_size_sop_even_only"
 
 /* Preamble size */
 #define spn_SPAUI_PREAMBLE_SIZE  "spaui_preamble_size"
 /*
  * If set, /S/ character will not be inserted at the
  * beginning of a packet.
  */
 #define spn_SPAUI_PREAMBLE_SKIP_SOP  "spaui_preamble_skip_sop"
 
 /* Deficit Idle Count mode. Valid values: AVERAGE/MIN. */
 #define spn_SPAUI_IPG_DIC_MODE  "spaui_ipg_dic_mode"
 
 /* Inter Packet Gap size in bytes. Range: 1 - 255. */
 #define spn_SPAUI_IPG_SIZE  "spaui_ipg_size"
 
 /* 24/32 Byte CRC mode configuration. Valid values: 32b/24b/NONE. */
 #define spn_SPAUI_CRC_MODE  "spaui_crc_mode"
 /*
  * Index of the byte containing the CH (Channel) field inside the first column
  * of the preamble. Possible values are 0 (if no SOP in preamble), 1, 2, 3.
  * Range: 0 - 3. 
  */
 #define spn_SPAUI_CHAN_BCT_CHANNEL_BYTE_NDX  "spaui_chan_bct_channel_byte_ndx"
 
 /* Burst Control Tag Size. Range: 0 - 2.      */
 #define spn_SPAUI_CHAN_BCT_SIZE  "spaui_chan_bct_size"
 
 /* If TRUE, the channelized interface will function in burst interleaving mode. Otherwise - in full packet mode. Note: if TRUE, the bct_size must be set to `2'  */
 #define spn_SPAUI_CHAN_IS_BURST_INTERLEAVING  "spaui_chan_is_burst_interleaving"
 
 /* Defines the response to local/remote fault indication. */
 #define spn_  ""
 /*
  * Response to local fault indication.
  * Valid values:
  * DATA_AND_IDLE: Continue sending data, send Idles
  * DATA_AND_RF: Continue sending data, send Remote Fault Indication.
  * DATA_AND_LF: Continue sending data, send Local Fault Indication.
  * NO_DATA_IDLE: Stop sending data, send Idles.
  * NO_DATA_RF: Stop sending data, send Remote Fault Indication.
  * NO_DATA_LF: Stop sending data, send Local Fault Indication.
  */
 #define spn_SPAUI_CHAN_FAULT_RESPONSE_LOCAL  "spaui_chan_fault_response_local"
 /*
  * Response to remote fault indication.
  * Valid values:
  * DATA_AND_IDLE: Continue sending data, send Idles
  * DATA_AND_RF: Continue sending data, send Remote Fault Indication.
  * DATA_AND_LF: Continue sending data, send Local Fault Indication.
  * NO_DATA_IDLE: Stop sending data, send Idles.
  * NO_DATA_RF: Stop sending data, send Remote Fault Indication.
  * NO_DATA_LF: Stop sending data, send Local Fault Indication.
  */
 #define spn_SPAUI_CHAN_FAULT_RESPONSE_REMOTE  "spaui_chan_fault_response_remote"
 
 /* If TRUE, the appropriate SGMII interface is enabled. */
 #define spn_GMII_ENABLE_RX  "gmii_enable_rx"
 
 /* If TRUE, the appropriate SGMII interface is enabled. */
 #define spn_GMII_ENABLE_TX  "gmii_enable_tx"
 
 /* 1000BASE-X or SGMII. */
 #define spn_GMII_MODE  "gmii_mode"
 /*
  * Used to indicate the mode port macro is operating in.
  * port_gmii_mode{physical port number}
  * The given physical port number has to be the
  * first physical port residing on the port macro.
  * Default value is 0.
  * For BCM56370 based devices following applies:
  * Value of 0 indicates PM4x10Q is in Ethernet mode
  * Value of 1 indicates PM4x10Q is in GMII mode
  */
 #define spn_PORT_GMII_MODE  "port_gmii_mode"
 
 /* SGMII link-rate - explicit, or auto-negotiation */
 #define spn_GMII_RATE  "gmii_rate"
 /*
  * Number of lanes in the Interlaken interface.
  * For ILKN-A; Range: 8 - 24.
  * For ILKN-B; Range: 4 - 12
  */
 #define spn_ILKN_NUM_LANES  "ilkn_num_lanes"
 
 /* When a bit is set, the equivalent lane (PHY) is used for the corresponding port. */
 #define spn_ILKN_LANES  "ilkn_lanes"
 /*
  *  ILKN lanes swap. This swap is logical and relates to ILKN protocol lane numbering (diffrent than phy_tx_lane_map\phy_rx_lane_map).
  *  Format: ilkn_lane_map_lane<num>_<logical_port>=<mapping>
  *  The default mapping mode is the straightforward mapping, i.e., 0 to 0, 1 to 1, etc. 
  *  To easily support reverse-order mapping the following convention can be used: ilkn_lane_map_1=reversed
  *  From Jericho2, the format of this property is: 
  *  ilkn_lane_map_<ilkn_id>_lane<num>=<ilkn lane id>, lane number is the Serdes logical lane number. 
  */
 #define spn_ILKN_LANE_MAP  "ilkn_lane_map"
 /*
  * Number of lanes in the caui interface.
  * For caui-A; Range: 10 - 12.
  * For caui; Range: 10 - 12
  */
 #define spn_CAUI_NUM_LANES  "caui_num_lanes"
 /*
  * If defined, identifies the invalid lane. Ignored otherwise.
  * For ILKN-A; Range: 0 - 23.
  * For ILKN-B; Range: 0 - 11
  */
 #define spn_ILKN_INVALID_LANE_ID  "ilkn_invalid_lane_id"
 /*
  * If TRUE, the channelized interface functions in burst interleaving mode. Otherwise - in full packet mode.
  * Note: when configuring FAT-PIPE over ILKN, ILKN must be configured to work as interleaved (is_burst_interleaving == TRUE)    
  */
 #define spn_ILKN_IS_BURST_INTERLEAVING  "ilkn_is_burst_interleaving"
 /*
  * ILKN interface statistics mecanism can count packets per port channel, burst per port channel or per physical port
  * Avaliable modes:
  * PACKET_PER_CHANNEL
  * BURST_PER_CHANNEL
  * STAT_PER_PHYSICAL_PORT
  */
 #define spn_ILKN_COUNTERS_MODE  "ilkn_counters_mode"
 /*
  * Allowed values:
  * DISABLED
  * 3x4: Fat-Pipe Enabled on (at maximum) 3 Fat-pipe interfaces
  *   A-C, (at maximum) 4 FAP ports per interface
  * 2x6: Fat-Pipe Enabled on (at maximum) 2 Fat-pipe interfaces
  *   A-B, (at maximum) 6 FAP ports per interface
  * 1x12: Fat-Pipe Enabled on 1 Fat-pipe interface A, (at maximum)
  *   12 FAP ports per interface
  */
 #define spn_FAT_PIPE_MODE  "fat_pipe_mode"
 /*
  * If the Fat-pipe is enabled, the FAP Port index of the base port of the Fat-pipe. Range: 1 - 12. 
  * If the Fat-pipe is disabled, this field is ignored.
  * Use suffix "_idN" to configure fat-pipe N (0-2)
  */
 #define spn_FAT_PIPE_BASE_PORT  "fat_pipe_base_port"
 /*
  * If the Fat-pipe is enabled, the number of Fat-pipe consecutive OFP ports, and accordingly Network Interfaces, that comprise the Fat-pipe.
  * If the Fat-pipe is enabled, the number of Fat-pipe consecutive OFP ports, and accordingly Network Interfaces, that comprise the Fat-pipe.
  * According to the NIF_FATP_MODE: 
  * For 3x4: Range: 1 - 4.
  * For 2x6: Range: 1 - 6.
  * For 1x12: Range: 1 - 12.
  * If the Fat-pipe is disabled, this field is ignored.
  * Use suffix "_idN" to configure fat-pipe N (0-2)
  */
 #define spn_FAT_PIPE_NUM_PORTS  "fat_pipe_num_ports"
 /*
  * If enabled, the MAL consumed by the ELK interface. The appropriate MAL cannot be used for NIF configuration.
  * Valid values: 0/12/14
  */
 #define spn_EXTERNAL_LOOKUP_MAL  "external_lookup_mal"
 
 /* If TRUE, the Synchronous Ethernet pins of MALG-B can be used (4 SYNCE signals in total). Otherwise, only 2 SYNCE signals can be used. Note: If TRUE, not fully compatible with Petra-A pinout (override VSS pins).  */
 #define spn_SYNC_ETH_IS_MALG_B_ENABLED  "sync_eth_is_malg_b_enabled"
 /*
  * Synchronous Ethernet Signal Mode.
  * Valid values:
  * TWO_DIFF_CLK: Synchronous Ethernet signal - differential (two signals
  *   per clock) recovered clock, two differential outputs
  * FOUR_CLK: Synchronous Ethernet signal - recovered clock, four
  *   outputs - two from each MAL group. Each clock may be
  *   connected to any NIF in the same MAL group.
  * TWO_CLK_AND_VALID: Synchronous Ethernet signal - recovered clock accompanied
  *   by a valid indication, two clk+valid outputs
  */
 #define spn_SYNC_ETH_MODE  "sync_eth_mode"
 /*
  * Note: the actual source is a single SerDes lane in the specified NIF port. 
  * Use suffix "_clkN" to configure click id N
  */
 #define spn_SYNC_ETH_CLK_TO_NIF_ID  "sync_eth_clk_to_nif_id"
 /*
  * Clock Divider for the selected recovered clock. Valid values: 20/40/80.
  * Use suffix "_clkN" to configure click id N
  */
 #define spn_SYNC_ETH_CLK_DIVIDER  "sync_eth_clk_divider"
 /*
  * If TRUE, automatic squelch function is enabled for the recovered clock. This
  * function powers down the clock output whenever the link is not synced, i.e. the
  * clock is invalid (even if the VALID indication is not present on the pin).
  * Use suffix "_clkN" to configure click id N
  */
 #define spn_SYNC_ETH_CLK_SQUELCH_ENABLE  "sync_eth_clk_squelch_enable"
 
 /* Specify the SerDes lane that will drive the recovered clock (master-0, slave-1) */
 #define spn_SYNC_ETH_CLK_TO_PORT_ID_CLK  "sync_eth_clk_to_port_id_clk"
 
 /* MDIO frequency. Units: KHz. */
 #define spn_MDIO_CLOCK_FREQ_KHZ  "mdio_clock_freq_khz"
 /*
  * If TRUE, the specified quartet CMU in the SerDes star is activated.
  * Notes:
  * 1. If any CMU is expected to be used at some stage in the future, it must be activated on init (the ACTIVE CMU structure).
  * 2. Not activating a CMU (if not expected to be used at any point) improves the device power consumption.
  * Suffix "_N" denots quartet N.
  */
 #define spn_PB_SERDES_QRTT_ACTIVE  "pb_serdes_qrtt_active"
 /*
  * If TRUE, the specified quartet in the SerDes is activated.
  * Notes:
  * 1. If any of the ports in the quartet are expected to be used at some stage in the future,
  *    it must be activated on init.
  * 2. Not activating a quartet (if not expected to be used at any point) improves the device power consumption.
  * Suffix "_N" denots quartet N.
  */
 #define spn_SERDES_QRTT_ACTIVE  "serdes_qrtt_active"
 /*
  * The maximal expected rate for any lane in the quartet.
  * Must be identical for all lanes per-quartet.
  * Suffix _N denots quartet N.
  * Range: 1000 - 6250. Units: Mbps.
  * If m/n divisors are forced to zero (see soc parameter
  * force_clk_m_n_divisors_zero), any value is allowed
  * If m/n are not forced to zero, only the below values
  * are valid:
  * 1000000/1041670/1171880/1250000/1302030/1333330/1562500/
  * 2343750/2500000/2604160/2666670/2083330/3000000/3125000/
  * 3750000/4000000/4166670/4687500/5000000/5208330/5333330/
  * 5833330/6000000/6250000/4375000/5468750/4250000
  */
 #define spn_PB_SERDES_QRTT_MAX_EXPECTED_RATE  "pb_serdes_qrtt_max_expected_rate"
 /*
  * Per-SerDes Lane rate configuration parameters.
  * Range: 1000 - 6250. Units: Mbps.
  * If m/n divisors are forced to zero (see soc parameter
  * force_clk_m_n_divisors_zero), any value is allowed
  * If m/n are not forced to zero, only the below values
  * are valid:
  * 1000000/1041670/1171880/1250000/1302030/1333330/1562500/
  * 2343750/2500000/2604160/2666670/2083330/3000000/3125000/
  * 3750000/4000000/4166670/4687500/5000000/5208330/5333330/
  * 5833330/6000000/6250000/4375000/5468750/4250000
  */
 #define spn_PB_SERDES_LANE_RATE  "pb_serdes_lane_rate"
 /*
  * Transmitter amplitude value- internal representation. An
  * amplification factor for the entire transmit waveform.
  * Range: 0 - 31.
  */
 #define spn_PB_SERDES_LANE_TX_PHYS_AMP  "pb_serdes_lane_tx_phys_amp"
 /*
  * Transmitter main value - internal representation. A
  * weight value for the non-emphasized bits. Range: 0 - 31.
  */
 #define spn_PB_SERDES_LANE_TX_PHYS_MAIN  "pb_serdes_lane_tx_phys_main"
 /*
  * Transmitter pre-emphasis value - internal
  * representation. A weight value for the Pre-Curser
  * emphasis. Range: 0 - 7.
  */
 #define spn_PB_SERDES_LANE_TX_PHYS_PRE  "pb_serdes_lane_tx_phys_pre"
 /*
  * Transmitter post-emphasis value - internal
  * representation. A weight value for the Post-Curser
  * emphasis. Range: 0 - 15.
  */
 #define spn_PB_SERDES_LANE_TX_PHYS_POST  "pb_serdes_lane_tx_phys_post"
 /*
  * 
  * TX physical parameters are derived from the selected
  * media type. Used only if the conf_mode is 'MEDIA_TYPE' -
  * ignored otherwise.
  * Allowed values:
  * CHIP2CHIP: The 2 communicating chips lay on the same board,
  *   therefore very minor Loss is expected.
  * SHORT_BACKPLANE: The 2 communicating chips lay on a short back-plane or
  *   connected through a connector.
  * LONG_BACKPLANE: The 2 communicating chips lay on a long back-plane, this
  *   derives a relatively high Loss.
  */
 #define spn_PB_SERDES_LANE_TX_PHYS_MEDIA_TYPE  "pb_serdes_lane_tx_phys_media_type"
 
 /* Receiver zcnt value- internal representation. */
 #define spn_PB_SERDES_LANE_RX_PHYS_ZCNT  "pb_serdes_lane_rx_phys_zcnt"
 
 /* Receiver z1cnt value- internal representation. */
 #define spn_PB_SERDES_LANE_RX_PHYS_Z1CNT  "pb_serdes_lane_rx_phys_z1cnt"
 
 /* Receiver dfelth value- internal representation. */
 #define spn_PB_SERDES_LANE_RX_PHYS_DFELTH  "pb_serdes_lane_rx_phys_dfelth"
 
 /* Receiver tlth value- internal representation. */
 #define spn_PB_SERDES_LANE_RX_PHYS_TLTH  "pb_serdes_lane_rx_phys_tlth"
 
 /* Receiver g1cnt value- internal representation. */
 #define spn_PB_SERDES_LANE_RX_PHYS_G1CNT  "pb_serdes_lane_rx_phys_g1cnt"
 /*
  * Per-SerDes Lane power state configuration parameters.
  * Note: if enabled, the configuration is set for both direction
  * (receive and transmit). To set different configuration
  * per-direction - either set FALSE here and configure using
  * dedicated API, or override one of the directions using dedicated API.
  * Allowed values:
  * DOWN
  * UP
  * UP_AND_RELOCK: SerDes is powered up. When setting this state, the
  *    SerDes is validated after power-up. If needed. a re-lock
  *    sequence is performed to verify SerDes is active. Note:
  *    this is the recommended value for powering-up the
  *    SerDes.
  */
 #define spn_PB_SERDES_LANE_POWER_STATE  "pb_serdes_lane_power_state"
 
 /* If TRUE, polarity is swapped (TX). */
 #define spn_PB_SERDES_LANE_SWAP_POLARITY_TX  "pb_serdes_lane_swap_polarity_tx"
 
 /* If TRUE, polarity is swapped (RX). */
 #define spn_PB_SERDES_LANE_SWAP_POLARITY_RX  "pb_serdes_lane_swap_polarity_rx"
 /*
  * This configuration affects the maximal number of Egress MC groups that can be opened.
  * Can only be enabled (TRUE) when working with FE600 (not FE200 or mesh).
  * If TRUE, up to 16K Egress MC groups can be opened. Otherwise - up to 8K.
  * The configuration must be consistant with the FE600 device configuration.
  * Note! If enabled, the FAP-IDs range in the system is limited to 0 - 511.
  */
 #define spn_EGR_MC_16K_GROUPS  "egr_mc_16k_groups"
 /*
  * The way the device is connected to fabric.
  * Valid values:
  * FE: Indicate FAP Fabric interface is connected to FE device.
  * BACK2BACK: Indicates FAP Fabric interface is connected to another
  *    FAP device. Total are 2 FAP devices in the system. No FE
  *    devices.
  * MESH: Indicate FAP Fabric interface is connected to another 2
  *    FAP. Total are 3, 4, ... FAP devices in the system. No FE devices.
  * MULT_STAGE_FE: Indicate FAP Fabric interface is connected to FE device,
  *    and that the system is multistage system.
  * SINGLE_FAP: Indicate single FAP in the system, without other FAPs
  *    or FEs.
  */
 #define spn_FABRIC_CONNECT_MODE  "fabric_connect_mode"
 /*
  * FTMH Header configuration: always allow, never allow, allow only when the packet is multicast.
  * Allowed values: ALWAYS/IF_MC/NEVER
  */
 #define spn_FABRIC_FTMH_OUTLIF_EXTENSION  "fabric_ftmh_outlif_extension"
 
 /* tacking is enabled in the system. */
 #define spn_STACKING_ENABLE  "stacking_enable"
 /*
  * Determine if FTMH Destination System Port Extension is added to all Ethernet packets.
  * Allowed values: TRUE/FALSE. Default: FALSE
  */
 #define spn_FTMH_DSP_EXTENSION_ADD  "ftmh_dsp_extension_add"
 /*
  * TM Domain of this device.
  * Default: 0
  */
 #define spn_DEVICE_TM_DOMAIN  "device_tm_domain"
 
 /* Per Port. Sets the TM Domin the port is connected to. */
 #define spn_PEER_TM_DOMAIN  "peer_tm_domain"
 
 /* External header size appended by external PP. This is used to calculate credit discount. */
 #define spn_EXTERNAL_HEADER_SIZE  "external_header_size"
 /*
  * Base queue for packets with explicit flow (does not affect packets with destination id in the header).
  * Default: 0.
  */
 #define spn_FLOW_MAPPING_QUEUE_BASE  "flow_mapping_queue_base"
 
 /* Explicit flow should be added or deleted from flow_mapping_queue_base value to get the final flow value. 1 => add, 2 => delete */
 #define spn_FLOW_MAPING_ADD_DELETE  "flow_maping_add_delete"
 /*
  * start of the ingress multicast group id range, from which
  * bcm_multicast_create allocates when the BCM_MULTICAST_WITH_ID flag not set.
  * Manually using legal multicast IDs not in the range may be less efficient.
  */
 #define spn_MULTICAST_INGRESS_GROUP_ID_RANGE_MIN  "multicast_ingress_group_id_range_min"
 /*
  * end of the ingress multicast group id range, from which
  * bcm_multicast_create allocates when the BCM_MULTICAST_WITH_ID flag not set.
  * Manually using legal multicast IDs not in the range may be less efficient.
  */
 #define spn_MULTICAST_INGRESS_GROUP_ID_RANGE_MAX  "multicast_ingress_group_id_range_max"
 /*
  * start of the egress multicast group id range, from which
  * bcm_multicast_create allocates when the BCM_MULTICAST_WITH_ID flag not set.
  * Manually using legal multicast IDs not in the range may be less efficient.
  */
 #define spn_MULTICAST_EGRESS_GROUP_ID_RANGE_MIN  "multicast_egress_group_id_range_min"
 /*
  * end of the egress multicast group id range, from which
  * bcm_multicast_create allocates when the BCM_MULTICAST_WITH_ID flag not set.
  * Manually using legal multicast IDs not in the range may be less efficient.
  */
 #define spn_MULTICAST_EGRESS_GROUP_ID_RANGE_MAX  "multicast_egress_group_id_range_max"
 
 /* If TRUE, egress bitmap reserved for multicast(4K) */
 #define spn_MULTICAST_EGRESS_BITMAP_RESERVE  "multicast_egress_bitmap_reserve"
 
 /* specifies the size of BFR entries available in the system for BIER */
 #define spn_BIER_NOF_BFR_ENTRIES  "bier_nof_bfr_entries"
 
 /* If TRUE, EEP extension is added to PPH header. This field is valid only when working in petra-B mode (is_petra_rev_a_in_system == FALSE), and PP is enabled. */
 #define spn_SYSTEM_PPH_EEP_EXT  "system_pph_eep_ext"
 /*
  * Statistics tag mode. 
  * Allowed values:
  * DISABLED
  * EN_NO_VSQ: The Statistics Tag is enabled with no use of the VSQ pointer.
  *   In the Statistics Interface, the dequeue information is not
  *   available. It still can be used in Billing mode.
  * EN_WITH_VSQ: The Statistics Tag is enabled and the use of the VSQ pointer
  *   is enabled. In the Statistics Interface, the dequeue information is not
  *   available. It still can be used in Billing mode.
  */
 #define spn_SYSTEM_STAG_ENCONDING_ENABLE_MODE  "system_stag_enconding_enable_mode"
 /*
  * Offset of the statistics tag header data from the base
  * header, in 4 bit (nibble) units. Range: 5 - 63.
  * The format of the Statistic-Tag is {VSQ-Pointer (8b, optional), Statistic-Tag(18b)}
  * Note: the offset points to the LSB of the Statistic-Tag
  */
 #define spn_SYSTEM_STAG_ENCONDING_OFFSET_4BIT  "system_stag_enconding_offset_4bit"
 /*
  * Port header type.
  * Allowed values:
  * ETH: Port header processing type: Ethernet. Supported
  *   direction: incoming / outgoing. Switching and TM
  *   functions are based on Ethernet packet
  *   processing. Incoming and outgoing outermost header is
  *   Ethernet.
  * RAW: Port header processing type: Raw. Supported direction:
  *   incoming / outgoing. Simple static switching; entire
  *   packet is payload. No header is assumed.
  * TM: Port header processing type: TM. Supported direction:
  *   incoming / outgoing. Designed to enable use of the TM
  *   features of the Incoming/Outgoing packets have an
  *   outermost Incoming/Outgoing-TM-Header (ITMH/OTMH).
  * PROG: Port header processing type: programmable. Supported
  *   direction: incoming. User programmable ingress
  *   prcessing. There are 4 programmable types that define
  *   the different starting program for classification of the
  *   packet.
  * CPU: Port header processing type: CPU. Supported direction:
  *   Outgoing. Designed to support CPU protocol
  *   processing. Outgoing packet has a Fabric-TM-Header (FTMH).
  * STACKING: Port header processing type: Stacking. Supported direction:
  *   Incoming / Outgoing. Designed to support use of stacking ports
  *   with a Fabric-TM-Header(FTMH) format.
  * TDM: Port header processing type: TDM. Supported direction:
  *   Incoming / Outgoing. Designed to support use of TDM processing
  *   with a regular Fabric-TM-Header(FTMH) format. 
  *   Defines port to be TDM Packet mode port
  * TDM_RAW: Port header processing type: TDM_RAW. Supported direction:
  *   Incoming. Designed to support use of TDM ports with
  *   simple static switching; entire packet is payload.
  *   No header is assumed. Defines port to be TDM Packet mode port.
  * INJECTED: Port header processing type: Both. Supported direction:
  *   Incoming only. Designed to support use of injected packets with
  *   PTCH Header as a first header.
  *   Output: FTMH (6B) + Out-LIF Extension (2B) + PPH.
  * XGS_HQoS: Port header processing type: Raw. Supported direction:
  *   incoming / outgoing. Designed to support higig headers for working
  *   with XGS devices and HQoS Queing model.
  * XGS_DiffServ: Port header processing type: Raw. Supported direction:
  *   incoming / outgoing. Designed to support higig headers for working
  *   with XGS devices and DiffServ Queing model.
  * XGS_MAC_EXT: Port header processing type: Raw. Supported direction:
  *   incoming / outgoing. Designed to support higig headers for working
  *   with XGS devices as MAC extension.
  * RCH_0: standardized recycle header type 0. Supported direction:
  *   incoming / outgoing. Defined on recycle port. When defined,
  *   a standardized recycle header (RCH) will be prepended on the packet.
  *   After recycle, RCH header is terminated, packet is L3 forwarded
  *   using first pass InRIF.
  * RCH_1: standardized recycle header type 1. Supported direction:
  *   incoming / outgoing. Defined on recycle port. When defined,
  *   a standardized recycle header (RCH) will be prepended on the packet.
  *   After recycle, RCH header is terminated, packet is L3 forwarded
  *   using first pass Out-RIF.
  */
 #define spn_TM_PORT_HEADER_TYPE  "tm_port_header_type"
 
 /* If TRUE, an extension added to its ITMH. */
 #define spn_TM_PORT_ITMH_EXT_ENABLE  "tm_port_itmh_ext_enable"
 
 /* If TRUE, source extension added to its OTMH. */
 #define spn_TM_PORT_OTMH_SRC_EXT_ENABLE  "tm_port_otmh_src_ext_enable"
 
 /* If TRUE, destination extension added to its OTMH. */
 #define spn_TM_PORT_OTMH_DEST_EXT_ENABLE  "tm_port_otmh_dest_ext_enable"
 
 /* TM Egress Replication port. Range: 0-1. */
 #define spn_NUM_ERP_TM_PORTS  "num_erp_tm_ports"
 
 /* Offload processor port. Range: 0-1. */
 #define spn_NUM_OLP_TM_PORTS  "num_olp_tm_ports"
 
 /* Recycle ports */
 #define spn_NUM_RECYCLE_TM_PORTS  "num_recycle_tm_ports"
 
 /* OAM processor port enable */
 #define spn_NUM_OAMP_PORTS  "num_oamp_ports"
 /*
  * If set driver reserve bcmPortClassFieldIngressPacketProcessing 2 bits to support OAM default profile.
  * In case feature is set then the number of bcmPortClassFieldIngressPacketProcessing is divided by 4. 
  */
 #define spn_BCM886XX_OAM_DEFAULT_PROFILE  "bcm886xx_oam_default_profile"
 /*
  * oam packet count per priority mode.
  * Mode: 0/1. 0 - disabled, 1 - enabled and reserves one bit from OutLIF profile.
  */
 #define spn_OAM_PCP_MODE  "oam_pcp_mode"
 /*
  * If set driver reserve bcmPortClassFieldEgressPacketProcessing 2 bits to support OAM default profile.
  * In case feature is set then the number of bcmPortClassFieldEgressPacketProcessing is divided by 4. 
  */
 #define spn_BCM886XX_OAM_DEFAULT_PROFILE_EGRESS  "bcm886xx_oam_default_profile_egress"
 /*
  * If set oam classifier of Arad+ works in advanced mode, otherwise classifier works in simple mode which is similar to Arad. 
  * Value 1 enables adding up to 2 meps with different direction on same lif. 
  * Value 2 enables adding multiple meps with different direction on same lif. 
  * (only Arad+)
  */
 #define spn_OAM_CLASSIFIER_ADVANCED_MODE  "oam_classifier_advanced_mode"
 
 /* setting bfd pwe (mode 0) or bfd cc mplstp mode (mode 1). */
 #define spn_BFD_ENCAPSULATION_MODE  "bfd_encapsulation_mode"
 /*
  *  The 6 bit value represent the flags supported:
  * Set to 1 for each Flag that should be supported in the order which they appear in the packet (P,F,C,A,D,M).
  */
 #define spn_BFD_SUPPORTED_FLAGS_BITFIELD  "bfd_supported_flags_bitfield"
 /*
  * BFD Flag masking - the 6 bit value represent the flags to be masked: 
  * Set to 1 for each flag in the order which they appear in the packet (P,F,C,A,D,M) 
  */
 #define spn_BFD_MASK_FLAGS_BITFIELD  "bfd_mask_flags_bitfield"
 
 /* User defined G-ACH for BFD-CC packets, oam */
 #define spn_MPLSTP_CC_CHANNEL_TYPE  "mplstp_cc_channel_type"
 
 /* User defined G-ACH for BFD-CV packets, oam */
 #define spn_MPLSTP_CV_CHANNEL_TYPE  "mplstp_cv_channel_type"
 
 /* User defined G-ACH for BFD control, oam */
 #define spn_MPLSTP_BFD_CONTROL_CHANNEL_TYPE  "mplstp_bfd_control_channel_type"
 
 /* User defined PW-ACH, oam */
 #define spn_MPLSTP_PW_ACH_CHANNEL_TYPE  "mplstp_pw_ach_channel_type"
 
 /* User defined G-ACH for DLM, oam */
 #define spn_MPLSTP_DLM_CHANNEL_TYPE  "mplstp_dlm_channel_type"
 
 /* User defined G-ACH for ILM, oam */
 #define spn_MPLSTP_ILM_CHANNEL_TYPE  "mplstp_ilm_channel_type"
 
 /* User defined G-ACH for DM, oam */
 #define spn_MPLSTP_DM_CHANNEL_TYPE  "mplstp_dm_channel_type"
 
 /* User defined G-ACH for MPLSTP-IPV4, oam */
 #define spn_MPLSTP_IPV4_CHANNEL_TYPE  "mplstp_ipv4_channel_type"
 
 /* User defined G-ACH for on demand CV control, oam */
 #define spn_MPLSTP_ON_DEMAND_CV_CHANNEL_TYPE  "mplstp_on_demand_cv_channel_type"
 
 /* User defined G-ACH PWE-OAM , oam */
 #define spn_MPLSTP_PWE_OAM_CHANNEL_TYPE  "mplstp_pwe_oam_channel_type"
 
 /* User defined G-ACH for MPLS-TP-IPV6, oam */
 #define spn_MPLSTP_IPV6_CHANNEL_TYPE  "mplstp_ipv6_channel_type"
 
 /* User defined G-ACH OAM fault, oam */
 #define spn_MPLSTP_FAULT_OAM_CHANNEL_TYPE  "mplstp_fault_oam_channel_type"
 
 /* User defined G-ACH for G8113, oam */
 #define spn_MPLSTP_G8113_CHANNEL_TYPE  "mplstp_g8113_channel_type"
 
 /* Recycling port to be used for OAM */
 #define spn_OAM_RCY_PORT  "oam_rcy_port"
 /*
  * Configures outlif extenstion on otmh.
  * Allowed values:
  * NEVER: Outlif extension is never added.
  * IF_MC: Outlif extension is added only for MC.
  * ALWAYS: Outlif extension is always added.
  * DOUBLE_TAG: Two hop scheduling. Change the PRGE program to Double-Tag(special mode for recycle ports) and not regular OTMH.
  * EXTENDED: Extended CUD. Change the PRGE program to Extended CUD(OTMH program with 24bit CUD extension) and not regular OTMH.
  */
 #define spn_TM_PORT_OTMH_OUTLIF_EXT_MODE  "tm_port_otmh_outlif_ext_mode"
 /*
  * Selects the source for counter engine commands on Dune Packet Processors.
  * Use port mode to differentiate between counter engines, not ports.
  * Possible extension _LSB or _MSB for: INGRESS_FIELD, EGRESS_VSI, EGRESS_OUT_LIF, EGRESS_TM
  * Allowed values:
  * INGRESS_FIELD: Ingress PP counter 0.
  * INGRESS_FIELD_0: Ingress PP counter 0.
  * INGRESS_FIELD_1: Ingress PP counter 1.
  * INGRESS_VOQ: IIngress VOQ.
  * INGRESS_STAG: Ingress Statistics tag.
  * INGRESS_VSQ: Ingress VSQ.
  * INGRESS_CNM: ngress CNM ID.
  * INGRESS_LATENCY: ingress latency.
  * EGRESS_FIELD: Egress PP.
  * EGRESS_VSI: Egress VSI - counter 0 (ARAD only).
  * EGRESS_VSI_0: Egress VSI - counter 0 (ARAD only).
  * EGRESS_VSI_1: Egress VSI - counter 1(ARAD only).
  * EGRESS_OUT_LIF: Egress OutLIF counter 0 (ARAD only).
  * EGRESS_OUT_LIF_0: Egress OutLIF counter 0 (ARAD only).
  * EGRESS_OUT_LIF_1: Egress OutLIF counter 1 (ARAD only).
  * EGRESS_TM: Egress TM counter 0(ARAD only).
  * EGRESS_TM_0: Egress TM counter 0(ARAD only).
  * EGRESS_TM_1: Egress TM counter 1(ARAD only).
  * INGRESS_OAM: Ingress OAM (ARAD only).
  * EGRESS_OAM: Egress OAM (ARAD only).
  */
 #define spn_COUNTER_ENGINE_SOURCE  "counter_engine_source"
 /*
  * Selects the counter engine statistics mode on Dune Packet Processors.
  * Various statistics can be kept according to source and statistics mode.
  * Certain statistics sets may only work with certain sources.
  * Uses port mode to differentiate between counter engines, not ports.
  * Allowed values:
  * FWD: forwarded.
  * FWD_COLOR: forwarded green, forwarded yellow.
  * FWD_DROP: forwarded, dropped.
  * GREEN_NOT_GREEN: fwd grn, fwd yel, drop grn, drop not grn.
  * FULL_COLOR: fwd grn, fwd yel, drop grn, drop yel, drop red.
  * NOTE: default for ingress sources = FWD_DROP, for egress sources = FWD
  */
 #define spn_COUNTER_ENGINE_STATISTICS  "counter_engine_statistics"
 /*
  * Least significant bit of statistics tag to use as counter index on
  * Dune Packet Processor counter engine, when source is statistics tag.
  * Uses port mode to differentiate between counter engines, not ports.
  * Default is bit zero.
  */
 #define spn_COUNTER_ENGINE_STAG_LOW_BIT  "counter_engine_stag_low_bit"
 /*
  * Selects first queue for inclusion in statistics on Dune Packet Processor
  * counter engine, when the engine source is VOQ.
  * Uses port mode to differentiate between counter engines, not ports.
  * First such counter engine defaults to min queue zero.
  * If more than one engine uses VOQ source, default is contiguous queues.
  */
 #define spn_COUNTER_ENGINE_VOQ_MIN_QUEUE  "counter_engine_voq_min_queue"
 /*
  * If set, the counter offsets inside the Counter-Set
  * (according to the color and the forwarded/drop indication)
  * is configurable, according to counter_engine_map.
  */
 #define spn_COUNTER_ENGINE_MAP_ENABLE  "counter_engine_map_enable"
 /*
  * If counter_engine_map_enable is set, this SOC property
  * indicates the Counter-Set size (number of counters).
  */
 #define spn_COUNTER_ENGINE_MAP_SIZE  "counter_engine_map_size"
 /*
  * Counter offset inside the Counter-Set for the forward green counter.
  * Applicable if counter_engine_map_enable is enabled.
  */
 #define spn_COUNTER_ENGINE_MAP_FWD_GREEN_OFFSET  "counter_engine_map_fwd_green_offset"
 /*
  * Counter offset inside the Counter-Set for the forward yellow counter.
  * Applicable if counter_engine_map_enable is enabled.
  */
 #define spn_COUNTER_ENGINE_MAP_FWD_YELLOW_OFFSET  "counter_engine_map_fwd_yellow_offset"
 /*
  * Counter offset inside the Counter-Set for the forward red counter.
  * Applicable if counter_engine_map_enable is enabled.
  */
 #define spn_COUNTER_ENGINE_MAP_FWD_RED_OFFSET  "counter_engine_map_fwd_red_offset"
 /*
  * Counter offset inside the Counter-Set for the forward black counter.
  * Applicable if counter_engine_map_enable is enabled.
  */
 #define spn_COUNTER_ENGINE_MAP_FWD_BLACK_OFFSET  "counter_engine_map_fwd_black_offset"
 /*
  * Counter offset inside the Counter-Set for the drop green counter.
  * Applicable if counter_engine_map_enable is enabled.
  */
 #define spn_COUNTER_ENGINE_MAP_DROP_GREEN_OFFSET  "counter_engine_map_drop_green_offset"
 /*
  * Counter offset inside the Counter-Set for the drop yellow counter.
  * Applicable if counter_engine_map_enable is enabled.
  */
 #define spn_COUNTER_ENGINE_MAP_DROP_YELLOW_OFFSET  "counter_engine_map_drop_yellow_offset"
 /*
  * Counter offset inside the Counter-Set for the drop red counter.
  * Applicable if counter_engine_map_enable is enabled.
  */
 #define spn_COUNTER_ENGINE_MAP_DROP_RED_OFFSET  "counter_engine_map_drop_red_offset"
 /*
  * Counter offset inside the Counter-Set for the drop black counter.
  * Applicable if counter_engine_map_enable is enabled.
  */
 #define spn_COUNTER_ENGINE_MAP_DROP_BLACK_OFFSET  "counter_engine_map_drop_black_offset"
 /*
  * Selects number of queues per counter set on Dune Packet Processor
  * counter engine, when the engine source is VOQ.
  * Uses port mode to differentiate between counter engines, not ports.
  * First such counter engine defaults to 1 queue per counter set.
  * If more than one processor uses VOQ source, later processors default
  * to same setting as the immediately previous one in VOQ mode.
  */
 #define spn_COUNTER_ENGINE_VOQ_QUEUE_SET_SIZE  "counter_engine_voq_queue_set_size"
 /*
  * Flow Control Out-Of-Band port type. Values: 0 => not used/unknown,
  * 1 => spi, 2 => Interlaken, 3 => HCFC, 4 => COE, 5 => E2E.
  * COE and E2E are supported by Jericho
  * For Dune devices the port range is [0-1]
  */
 #define spn_FC_OOB_TYPE  "fc_oob_type"
 /*
  * Flow Control Out-Of-Band port mode. Values:  0 => disable,
  * 0x1 => enable Rx flow control, 0x2 => enable Tx flow control.
  * Depending on h/w capability both enable Rx flow control and
  * enable TX flow control could be specified.
  * This is a bitwise definition. This allows the user to specify
  * the mode via a single entry.
  * For Dune devices the port range is [0-1]
  */
 #define spn_FC_OOB_MODE  "fc_oob_mode"
 /*
  * Flow Control Out-Of-Band calender length.
  * For Dune devices the port range is [0-1]
  */
 #define spn_FC_OOB_CALENDER_LENGTH  "fc_oob_calender_length"
 /*
  * Flow Control Out-Of-Band repeat count.
  * For Dune devices the port range is [0-1]
  */
 #define spn_FC_OOB_CALENDER_REP_COUNT  "fc_oob_calender_rep_count"
 /*
  * Flow Control InBand(interlaken) port type. Values: 0 => not used/unknown,
  * 1 => Interlaken, 2 => COE, 3 => HCFC.
  */
 #define spn_FC_INBAND_INTLKN_TYPE  "fc_inband_intlkn_type"
 /*
  * Flow Control InBand(interlaken) port mode. Values:  0 => disable,
  * 0x1 => enable Rx flow control, 0x2 => enable Tx flow control.
  * depending on h/w capability both enable Rx flow control and
  * enable TX flow control could be specified.
  * This is a bitwise definition. This allows the user to specify
  * the mode via a single entry.
  * For Dune devices the port range is [0-1]
  */
 #define spn_FC_INBAND_INTLKN_MODE  "fc_inband_intlkn_mode"
 /*
  * Flow Control InBand(interlaken) calender length.
  * For Dune devices the port range is [0-1]
  */
 #define spn_FC_INBAND_INTLKN_CALENDER_LENGTH  "fc_inband_intlkn_calender_length"
 /*
  * Flow Control InBand(interlaken) repeat count.
  * For Dune devices the port range is [0-1]
  */
 #define spn_FC_INBAND_INTLKN_CALENDER_REP_COUNT  "fc_inband_intlkn_calender_rep_count"
 /*
  * Flow Control InBand(interlaken) LLFC calender entries.
  * Values: 0 => disabled, , 1 => calender 0, 2 => calender 0, 16, ...
  * For Dune devices the port range is [0-1]
  */
 #define spn_FC_INBAND_INTLKN_CALENDER_LLFC_MODE  "fc_inband_intlkn_calender_llfc_mode"
 /*
  * Flow Control InBand(interlaken) LLFC multi use bits mask.
  * This is a 6 bit value. Values: 0 => disabled, non-zero => represents mask
  * For Dune devices the port range is [0-1]
  */
 #define spn_FC_INBAND_INTLKN_LLFC_MUB_ENABLE_MASK  "fc_inband_intlkn_llfc_mub_enable_mask"
 /*
  * Flow Control InBand(interlaken) Channel multi use bits mask.
  * This is a 6 bit value. Values: 0 => disabled, non-zero => represents mask
  * For Dune devices the port range is [0-1]
  */
 #define spn_FC_INBAND_INTLKN_CHANNEL_MUB_ENABLE_MASK  "fc_inband_intlkn_channel_mub_enable_mask"
 /*
  * PP E2E FC status size
  * Valid value: 8B/16B/32B/48B/64B
  */
 #define spn_FC_CALENDAR_E2E_STATUS_NOF_ENTRIES  "fc_calendar_e2e_status_nof_entries"
 
 /* PP COE Pause counter rate. Unit: usec. */
 #define spn_FC_CALENDAR_PAUSE_RESOLUTION  "fc_calendar_pause_resolution"
 
 /* PP E2E FC polarity. */
 #define spn_FC_CALENDAR_INDICATION_INVERT  "fc_calendar_indication_invert"
 /*
  * PP COE Mode
  * Valid value: PAUSE/PFC
  */
 #define spn_FC_CALENDAR_COE_MODE  "fc_calendar_coe_mode"
 
 /* Set the mac address of COE FC packet (48 bits) */
 #define spn_FC_COE_MAC_ADDRESS  "fc_coe_mac_address"
 
 /* set ethertype of COE FC packet.(16bits) */
 #define spn_FC_COE_ETHERTYPE  "fc_coe_ethertype"
 
 /* define offset in bytes from after Ethernet Frame for COE FC data. Valid range = [0-31] */
 #define spn_FC_COE_DATA_OFFSET  "fc_coe_data_offset"
 /*
  * Flow Control COE calender length.
  * Port range is [0-1]
  */
 #define spn_FC_COE_CALENDER_LENGTH  "fc_coe_calender_length"
 
 /* This controls whether to extract the recovered clock or not. (same as SyncE) */
 #define spn_PHY_CLOCK_ENABLE  "phy_clock_enable"
 /*
  * Enable Tunnel Termination for protocol types, compatible for all devices.
  * Setting the compatible mode ignores protocol match and sets protocol mask to zero.
  */
 #define spn_BCM_TUNNEL_TERM_COMPATIBLE_MODE  "bcm_tunnel_term_compatible_mode"
 /*
  * this property is prefixed by the range number ("_#"). The value that is assigned to this property configures the label range start
  * 
  * 0: First label in range number 0
  * 1: First label in range number 1
  * 2: First label in range number 2
  */
 #define spn_MPLS_TUNNEL_TERM_LABEL_RANGE_MIN  "mpls_tunnel_term_label_range_min"
 /*
  * this property is prefixed by the range number ("_#"). The value that is assigned to this property configures the label range end
  * 
  * 0: Last label in range number 0
  * 1: Last label in range number 1
  * 2: Last label in range number 2
  */
 #define spn_MPLS_TUNNEL_TERM_LABEL_RANGE_MAX  "mpls_tunnel_term_label_range_max"
 
 /* Set the start range of the egress encapsulation ip tunnel */
 #define spn_EGRESS_ENCAP_IP_TUNNEL_RANGE_MIN  "egress_encap_ip_tunnel_range_min"
 
 /* Set the end range of the egress encapsulation ip tunnel */
 #define spn_EGRESS_ENCAP_IP_TUNNEL_RANGE_MAX  "egress_encap_ip_tunnel_range_max"
 
 /* Set the start range of the egress multicast bitmap type */
 #define spn_EGRESS_MULTICAST_DIRECT_BITMAP_MIN  "egress_multicast_direct_bitmap_min"
 
 /* Set the end range of the egress multicast bitmap type */
 #define spn_EGRESS_MULTICAST_DIRECT_BITMAP_MAX  "egress_multicast_direct_bitmap_max"
 
 /* Set the nof ingress multicast bitmap ids */
 #define spn_MULTICAST_NOF_INGRESS_BITMAP  "multicast_nof_ingress_bitmap"
 
 /* Set the nof egress multicast bitmap ids */
 #define spn_MULTICAST_NOF_EGRESS_BITMAP  "multicast_nof_egress_bitmap"
 
 /* Set the number of Outgoing local port queue-pairs (1/2/8) per port */
 #define spn_PORT_PRIORITIES  "port_priorities"
 /*
  * Set the shared multicast resource mode
  * Strict
  * Discrete
  */
 #define spn_EGRESS_SHARED_RESOURCES_MODE  "egress_shared_resources_mode"
 /*
  * Mapping VOQs to Destination-Device and PP-DSP modes
  * DIRECT
  * INDIRECT
  */
 #define spn_VOQ_MAPPING_MODE  "voq_mapping_mode"
 /*
  * Define the 4 multicast ID offsets for the four incoming interfaces.
  * Add suffix _nif/_recycling/_cpu/_olp to choose which offset incoming interface to configure.
  */
 #define spn_MULTICAST_ID_OFFSET  "multicast_id_offset"
 /*
  * Define outgoing port rate mode in data rate or packet rate.
  * The configuration is per port. Valid values:
  * DATA
  * PACKET
  */
 #define spn_OTM_PORT_PACKET_RATE  "otm_port_packet_rate"
 
 /* Set the number of LAGs: 1024, 512, 256, 128 or 64 */
 #define spn_NUMBER_OF_TRUNKS  "number_of_trunks"
 
 /* Using the lb-key's MSB in stack trunk resolutions. To use the MSB, set the property to '1'. */
 #define spn_TRUNK_RESOLVE_USE_LB_KEY_MSB_STACK  "trunk_resolve_use_lb_key_msb_stack"
 
 /* Using the lb-key's MSB in smooth-division trunk resolutions. To use the MSB, set the property to '1'. */
 #define spn_TRUNK_RESOLVE_USE_LB_KEY_MSB_SMOOTH_DIVISION  "trunk_resolve_use_lb_key_msb_smooth_division"
 /*
  * Explicity control local port to OTM-queue base pair assignment.
  * Range: 0-255
  */
 #define spn_OTM_BASE_Q_PAIR  "otm_base_q_pair"
 /*
  * enable / disable queue level interface.
  * 0: disable
  * 1: enable
  */
 #define spn_QUEUE_LEVEL_INTERFACE  "queue_level_interface"
 
 
 /*
  * Specify the "Auxiliary table" mode (0/1/2).
  * Valid values:
  * 0: Private VLAN support
  * 1: Split horizon mode
  * 2: Mac-In-Mac support
  */
 #define spn_BCM886XX_AUXILIARY_TABLE_MODE  "bcm886xx_auxiliary_table_mode"
 /*
  * bcm886xx_port_extend_p2p_<port>.
  * 0/1 (Disable / Enable look up on this port).
  * Valid values:
  * 0
  * 1
  */
 #define spn_BCM886XX_PORT_EXTEND_P2P  "bcm886xx_port_extend_p2p"
 
 /* Initial settings. Not including the settings in CTRL/ADVA */
 #define spn_PHY_LR_INITIAL_MODE  "phy_lr_initial_mode"
 
 /* Initial speed, pairs, LDS(Autoneg), master/slave, unidirectional settings */
 #define spn_PHY_LR_INITIAL_CTRL  "phy_lr_initial_ctrl"
 
 /* Initial advertised ability */
 #define spn_PHY_LR_INITIAL_ADVA  "phy_lr_initial_adva"
 
 /* select wether to set memory/table DMA access to use low endianess in host memory */
 #define spn_SYSTEM_SET_DMA_LOW_ENDIANESS  "system_set_dma_low_endianess"
 
 /* Set the default MMU lossless behavior */
 #define spn_MMU_LOSSLESS  "mmu_lossless"
 /*
  * Select ports to apply MMU lossless configuration (valid only if
  * mmu_lossless=1).
  * This property is only required for specific chips that have limited MMU
  * lossless ports, such as BCM5354x.
  * For example, enable MMU lossless mode on port 4~7.
  * mmu_lossless=1
  * mmu_lossless_pbmp=0xf0
  */
 #define spn_MMU_LOSSLESS_PBMP  "mmu_lossless_pbmp"
 
 /* Select whether to enable/disable SA authentication on the device */
 #define spn_SA_AUTH_ENABLED  "sa_auth_enabled"
 
 /* Retransmission enable Tx */
 #define spn_ILKN_RETRANSMIT_ENABLE_TX  "ilkn_retransmit_enable_tx"
 
 /* Retransmission enable Rx */
 #define spn_ILKN_RETRANSMIT_ENABLE_RX  "ilkn_retransmit_enable_rx"
 /*
  * Retransmission Buffer size in entries of 128 Bytes.
  * Range: 1-255
  */
 #define spn_ILKN_RETRANSMIT_BUFFER_SIZE  "ilkn_retransmit_buffer_size"
 /*
  * Number of times a retransmit request is resent for a specific sequence number before indicating a fatal error.
  * Range: 0 - 14
  */
 #define spn_ILKN_RETRANSMIT_NUM_REQUESTS_RESENT  "ilkn_retransmit_num_requests_resent"
 /*
  * Number of Sequence Number repetitions Tx
  * If 1, then the sequence number is always increased by 1. If 2, each sequence number is put on 2 consecutive packets
  * Valid values: 1/2/4/8
  */
 #define spn_ILKN_RETRANSMIT_NUM_SN_REPETITIONS_TX  "ilkn_retransmit_num_sn_repetitions_tx"
 /*
  * Number of Sequence Number repetitions Rx.
  * If 1, then the sequence number is always increased by 1. If 2, each sequence number is put on 2 consecutive packets
  * Valid values: 1/2/4/8
  */
 #define spn_ILKN_RETRANSMIT_NUM_SN_REPETITIONS_RX  "ilkn_retransmit_num_sn_repetitions_rx"
 /*
  * Number of ILKN words to wait before considering the request as failed.
  * Range: 0 - 0xFFFF
  */
 #define spn_ILKN_RETRANSMIT_RX_TIMEOUT_WORDS  "ilkn_retransmit_rx_timeout_words"
 /*
  * Number of Sequence numbers to wait after a Retransmit request before considering the request as failed.
  * Range: 0 - 0xFF
  */
 #define spn_ILKN_RETRANSMIT_RX_TIMEOUT_SN  "ilkn_retransmit_rx_timeout_sn"
 /*
  * Number of ILKN words to ignore if consecutive errors are received.
  * Range: 0 - 0xFFFF
  */
 #define spn_ILKN_RETRANSMIT_RX_IGNORE  "ilkn_retransmit_rx_ignore"
 /*
  * Number of ILKN words received from the error event and before the packet is received again for the Watchdog on the retransmit logic.
  * Range: 0 - 0xFFFF
  */
 #define spn_ILKN_RETRANSMIT_RX_WATCHDOG  "ilkn_retransmit_rx_watchdog"
 
 /* If set enable reset of rx retransmit logic in case of error. */
 #define spn_ILKN_RETRANSMIT_RX_RESET_WHEN_ERROR_ENABLE  "ilkn_retransmit_rx_reset_when_error_enable"
 
 /* If set and ilkn_rx_retransmit_reset_when_error is set, the rx retransmit logic will be restarted in case that allignment is lost. */
 #define spn_ILKN_RETRANSMIT_RX_RESET_WHEN_ALLIGNED_ERROR_ENABLE  "ilkn_retransmit_rx_reset_when_alligned_error_enable"
 
 /* If set and ilkn_rx_retransmit_reset_when_error is set, the rx retransmit logic will be restarted in case that retry error occures. */
 #define spn_ILKN_RETRANSMIT_RX_RESET_WHEN_RETRY_ERROR_ENABLE  "ilkn_retransmit_rx_reset_when_retry_error_enable"
 
 /* If set and ilkn_rx_retransmit_reset_when_error is set, the rx retransmit logic will be restarted in case that too many bursts received after the discontinuity event. */
 #define spn_ILKN_RETRANSMIT_RX_RESET_WHEN_WRAP_AFTER_DISC_ERROR_ENABLE  "ilkn_retransmit_rx_reset_when_wrap_after_disc_error_enable"
 
 /* If set and ilkn_rx_retransmit_reset_when_error is set, the rx retransmit logic will be restarted in case the expected sequence number is received before the discontinuity event. */
 #define spn_ILKN_RETRANSMIT_RX_RESET_WHEN_WRAP_BEFORE_DISC_ERROR_ENABLE  "ilkn_retransmit_rx_reset_when_wrap_before_disc_error_enable"
 
 /* If set and ilkn_rx_retransmit_reset_when_error is set, the rx retransmit logic will be restarted in case that timout error occures. */
 #define spn_ILKN_RETRANSMIT_RX_RESET_WHEN_TIMOUT_ERROR_ENABLE  "ilkn_retransmit_rx_reset_when_timout_error_enable"
 
 /* If set, when retransmit starts, the TX  will wait to detect sequence number change in the data from the buffer before retransmitting. */
 #define spn_ILKN_RETRANSMIT_TX_WAIT_FOR_SEQ_NUM_CHANGE_ENABLE  "ilkn_retransmit_tx_wait_for_seq_num_change_enable"
 
 /* -If set, the TX will ignore incoming retransmit request when there are less bursts in the FIFO bursts than bursts per sequence number; */
 #define spn_ILKN_RETRANSMIT_TX_IGNORE_REQUESTS_WHEN_FIFO_ALMOST_EMPTY  "ilkn_retransmit_tx_ignore_requests_when_fifo_almost_empty"
 /*
  * If set, DRAM interface swap its HW PIN pairs during init. Note: Only one of DRAMs can have its PIN swapped.
  * Valid values: FALSE/TRUE
  */
 #define spn_DRAM0_CLAMSHELL_ENABLE  "dram0_clamshell_enable"
 /*
  * The Max number of crc error per DRAM buffer before that interrupt application delete this buffer.
  * Range: 0 - 0xFFFFFFFF
  */
 #define spn_DRAM_CRC_DEL_BUFFER_MAX_RECLAIMS  "dram_crc_del_buffer_max_reclaims"
 /*
  * If set, DRAM interface swap its HW PIN pairs during init. Note: Only one of DRAMs can have its PIN swapped.
  * Valid values: FALSE/TRUE
  */
 #define spn_DRAM1_CLAMSHELL_ENABLE  "dram1_clamshell_enable"
 
 /* Set System-Red functionality. Note: In BCM88650 device if Set, number of system ports is limited to 4K */
 #define spn_SYSTEM_RED_ENABLE  "system_red_enable"
 
 /* Number of BHH sessions */
 #define spn_BHH_NUM_SESSIONS  "bhh_num_sessions"
 /*
  * Total number of MPLS OAM sessions. This would be the total number of BHH and MPLS LM/DM sessions that can be run in both firmware and any other OLP
  * This property would also decide if we allocate 8 hardware indexes for each MPLS OAM session or one hardware index
  */
 #define spn_MPLS_OAM_NUM_SESSIONS  "mpls_oam_num_sessions"
 
 /* BHH cosq */
 #define spn_BHH_COSQ  "bhh_cosq"
 
 /* ITU-T Carrier Code (ICC) to use in BHH LB ICC-based MIP ID. Length is six bytes, must be specified using a mac address like format, e.g 00:11:22:33:44:55 */
 #define spn_BHH_CARRIER_CODE  "bhh_carrier_code"
 
 /* Node ID to use in BHH LB ICC-based MIP ID */
 #define spn_BHH_NODE_ID  "bhh_node_id"
 
 /* Number of LM enabled BHH section meps */
 #define spn_BHH_NUM_LM_ENABLED_SECTION_MEPS  "bhh_num_lm_enabled_section_meps"
 /*
  * Enable will set device to support only simple vlan translation
  * i.e.: lookup of port or portxvlan or portxvlanxvlan. In this mode, assume a minimal usage of the vlan translation,
  * for example,parallel lookups of portxvlan with portxvlanxvlan will be disabled. Set this mode for MPLS-core device
  */
 #define spn_SIMPLE_VLAN_TRANSLATION_ENABLE  "simple_vlan_translation_enable"
 /*
  * MPLS termination with known stack (e.g. adding 2nd label) enables termination of label only on the required location,
  * in the MPLS stack and not over all different,locations in the MPLS stack. In this mode, no need to duplicate MPLS entries
  */
 #define spn_MPLS_TERMINATION_LABEL_INDEX_ENABLE  "mpls_termination_label_index_enable"
 
 /* Enable indicates device supports fast reroute (FRR) labels. Disable this mode provides the ability to add up to 64K label entries (and not 32K). */
 #define spn_FAST_REROUTE_LABELS_ENABLE  "fast_reroute_labels_enable"
 /*
  * Enable flexibility of setting shaper refresh interval.The configuration is a mutiplier factor of 1.95usec.
  * The supported factors are 1, 2 and 4 based on number of queues.
  * i.e 1024 or fewer queues: 1.95 usec, 3.096 usec and 7.8125 usec
  *     1025 to 2048 queues: 3.096 usec and 7.8125 usec
  *     2048 to 4096 queues: 7.8125 usec.
  */
 #define spn_MMU_SHAPER_REFRESH_INTERVAL  "mmu_shaper_refresh_interval"
 
 /* Enable the OCB (On-Chip Buffer). Enabled by default. */
 #define spn_BCM886XX_OCB_ENABLE  "bcm886xx_ocb_enable"
 /*
  * The size of a single data buffer in the OCB.
  * Allowed values: 128/256/512/1024 Bytes. Default: 128 Bytes.
  */
 #define spn_BCM886XX_OCB_DATABUFFER_SIZE  "bcm886xx_ocb_databuffer_size"
 /*
  * Reference clock frequency for the Network Interface SerDeses.
  * Default: 125.
  */
 #define spn_SERDES_NIF_CLK_FREQ  "serdes_nif_clk_freq"
 /*
  * Reference clock frequency for the Fabric SerDeses .
  * 0=125MHz, 1=156.25MHz
  */
 #define spn_SERDES_FABRIC_CLK_FREQ  "serdes_fabric_clk_freq"
 /*
  * This option controls the meaning of '0'/'1' in the of Calendar FC indications per interface (2).
  * If unset (default), use the standard FC indication. If set, use an inverted FC indication. 
  */
 #define spn_FC_SPI_INDICATION_INVERT  "fc_spi_indication_invert"
 /*
  * This option controls the meaning of '0'/'1' in the of Calendar FC indications per interface (2).
  * If unset (default), use the standard FC indication. If set, use an inverted FC indication. 
  */
 #define spn_FC_INTLKN_INDICATION_INVERT  "fc_intlkn_indication_invert"
 
 /*
  * The maximal interval, in words, between meta-frame sync words (see section 5.4.3 of Interlaken spec 1.1).
  * Units: words (67-bit blocks). Default: 2K. Range: 64 - 16K.
  */
 #define spn_ILKN_METAFRAME_SYNC_PERIOD  "ilkn_metaframe_sync_period"
 
 /* Enable\Disable ILKN status message check. */
 #define spn_ILKN_INTERFACE_STATUS_IGNORE  "ilkn_interface_status_ignore"
 
 /* Enable\Disable ILKN status message sent through an out-of-band interface. */
 #define spn_ILKN_INTERFACE_STATUS_OOB_IGNORE  "ilkn_interface_status_oob_ignore"
 
 /* Trap strength used when drop / trap packets to CPU. */
 #define spn_DEFAULT_TRAP_STRENGTH  "default_trap_strength"
 
 /* Snoop strength used when snoop packets to CPU */
 #define spn_DEFAULT_SNOOP_STRENGTH  "default_snoop_strength"
 
 /* Specify the trap strength that should be used for passive OAM trap. If this is not specified, the strength from spn_DEFAULT_TRAP_STRENGTH would be used for passive traps. */
 #define spn_OAM_TRAP_STRENGTH_PASSIVE  "oam_trap_strength_passive"
 
 /* Specify the trap strength that should be used for level OAM trap. If this is not specified, the strength from spn_DEFAULT_TRAP_STRENGTH would be used for level traps. */
 #define spn_OAM_TRAP_STRENGTH_LEVEL  "oam_trap_strength_level"
 
 /* Specify the trap strength that should be used for injected OAM packets. If this is not specified, the strength from spn_DEFAULT_TRAP_STRENGTH would be used. */
 #define spn_OAM_TRAP_STRENGTH_INJECTED  "oam_trap_strength_injected"
 
 /* Specify the oam default trap strength that should be used for OAM trap. If this is not specified, the strength from spn_DEFAULT_TRAP_STRENGTH would be used for oam traps. */
 #define spn_OAM_DEFAULT_TRAP_STRENGTH  "oam_default_trap_strength"
 
 /* Specify the forward trap strength that should be used for forward OAM trap. If this is not specified, the strength from spn_DEFAULT_TRAP_STRENGTH would be used. */
 #define spn_OAM_FORWARD_TRAP_STRENGTH  "oam_forward_trap_strength"
 
 /* PDM Mode. 0: simple (default), 1: extended (mandatory for LLFC-VSQ, PFC-VSQ, or ST-VSQ)  */
 #define spn_BCM886XX_PDM_MODE  "bcm886xx_pdm_mode"
 /*
  * received external synthesizer clock frequency
  * default value: 25MHz
  */
 #define spn_SYNTH_DRAM_FREQ  "synth_dram_freq"
 /*
  * Repartition of the OCB memory pointers. 0: 800nicast and 20% Multicast, 1: Unicast-Only
  * default value: 0
  */
 #define spn_BCM886XX_OCB_REPARTITION  "bcm886xx_ocb_repartition"
 /*
  * choose GE port between guarantee line rate vs less than line rate
  * on 56333.
  */
 #define spn_BCM56333_PBMP_GE_LINERATE  "bcm56333_pbmp_ge_linerate"
 
 /* On 56640 devices bitmap of ports which participate in ESM searches */
 #define spn_PBMP_ESM_ELIGIBLE  "pbmp_esm_eligible"
 /*
  * use HSP scheduler for the port.
  * On TD2/TD2+ chip, only the lowest 16 MMU port numbers on each pipe
  * can be configured to reside in the HSP scheduler.
  * Port that enabled in the HSP scheduler, reserves an additional
  * MMU port with offset of 36.
  */
 #define spn_PORT_SCHED_HSP  "port_sched_hsp"
 
 /* Select BCM8823X TDM table for mode: 4*20G Xport, 1G CPU */
 #define spn_BCM8823X_4X20_1  "bcm8823x_4x20_1"
 
 /* Select BCM8823X TDM table for mode: 4*10G Xport, 2*20G Requeue, 1G CPU */
 #define spn_BCM8823X_4X10_2X20_1  "bcm8823x_4x10_2x20_1"
 
 /* Select BCM8823X TDM table for mode: 2*20G Xport, 2*20G Requeue, 1G CPU */
 #define spn_BCM8823X_2X20_2X20_1  "bcm8823x_2x20_2x20_1"
 
 /* Select BCM8823X TDM table for mode: 2*24G Xport, 1G CPU */
 #define spn_BCM8823X_2X24_1  "bcm8823x_2x24_1"
 /*
  * Select BCM8823X TDM table for mode: 2*24G and 2*20G Xport, 1G CPU
  * Below are the values to set based on the interface speeds
  * Value   IF0   IF1   IF2   IF3
  *   1:    24    24    20    20
  *   2:    24    20    24    20
  *   3:    24    20    20    24
  *   4:    20    24    24    20
  *   5:    20    24    20    24
  *   6:    20    20    24    24
  */
 #define spn_BCM8823X_2X24_2X20_1  "bcm8823x_2x24_2x20_1"
 
 /* Select BCM8823X TDM table for mode: 4x11G Xport + 25G Requeue0 + 11G Requeue1 */
 #define spn_BCM8823X_4X11_1X25_1X11  "bcm8823x_4x11_1x25_1x11"
 
 /* Select BCM8823X TDM table for mode: 4x11G Xport + 12G Requeue0 + 24G Requeue1 */
 #define spn_BCM8823X_4X11_1X12_1X24  "bcm8823x_4x11_1x12_1x24"
 
 /* Select BCM8823X TDM table for mode: 4x11G Xport + 11G Requeue0 + 25G Requeue1 */
 #define spn_BCM8823X_4X11_1X11_1X25  "bcm8823x_4x11_1x11_1x25"
 
 /* Select BCM8823X TDM table for mode: 4x11G Xport + 2x18G Requeue  */
 #define spn_BCM8823X_4X11_2X18  "bcm8823x_4x11_2x18"
 /*
  * L3 VRRP max VID. Support VRID configuration on VLANs: 0 - l3_vrrp_max_vid.
  * This affects maximal number of VRIDs to support on each VLAN.
  * Possible values are: 4K, 2K, 1K, 512 and 256.
  */
 #define spn_L3_VRRP_MAX_VID  "l3_vrrp_max_vid"
 
 /* L3 VRRP IPV6 distinct. Whether to to enable separate VRID configuration for IPv4 and IPv6. */
 #define spn_L3_VRRP_IPV6_DISTINCT  "l3_vrrp_ipv6_distinct"
 
 /* Option to enable dynamic update of scheduler mode */
 #define spn_MMU_DYNAMIC_SCHED_UPDATE  "mmu_dynamic_sched_update"
 
 /* Timeout delay in microseconds for queue flush complete */
 #define spn_MMU_QUEUE_FLUSH_TIMEOUT  "mmu_queue_flush_timeout"
 
 /* Number of policers to allocate for ingress processing. Valid values: 0, 32K, 64K, 128K */
 #define spn_POLICER_INGRESS_COUNT  "policer_ingress_count"
 
 /* Number of policers to allocate for egress processing. Valid values: 0, 32K, 64K */
 #define spn_POLICER_EGRESS_COUNT  "policer_egress_count"
 /*
  * Sharing mode to allocate meters for ingress processing.
  * Valid values:
  * 0 = NONE (No sharing. One meter may be applied per packet),
  * 1 = SERIAL (Policers are arranged in pairs. The result of the first meter is fed into the second meter),
  * 2 = PARALLEL (Policers are arranged in pairs. The final meter result is the worst-case result of the two meters)
  */
 #define spn_POLICER_INGRESS_SHARING_MODE  "policer_ingress_sharing_mode"
 /*
  * Sharing mode to allocate meters for egress processing.
  * Valid values:
  * 0 = NONE (No sharing. One meter may be applied per packet),
  * 1 = SERIAL (Policers are arranged in pairs. The result of the first meter is fed into the second meter),
  * 2 = PARALLEL (Policers are arranged in pairs. The final meter result is the worst-case result of the two meters)
  */
 #define spn_POLICER_EGRESS_SHARING_MODE  "policer_egress_sharing_mode"
 /*
  * Sets the Flow Control OOB TX Speed relatively to the Core Clock. Possible values:
  * 1 - Same as Core Clock
  * 2 - Core Clock / 2
  * 4 - Core Clock / 4
  * 8 - Core Clock / 8
  */
 #define spn_FC_OOB_TX_FREQ_RATIO  "fc_oob_tx_freq_ratio"
 /*
  * Number of Virtual Routing and Forwarding ID for the device.
  * Available VRF are 0,1,... ipv4_num_vrfs-1.
  * Set to 0 when routing is disabled.
  */
 #define spn_IPV4_NUM_VRFS  "ipv4_num_vrfs"
 /*
  * Number of IPv4 route entries to be supported in subnet database.
  * This is the total number for all VRFs in device.
  */
 #define spn_IPV4_NUM_ROUTES  "ipv4_num_routes"
 
 /* Number of bits to consider in first memory. */
 #define spn_BCM886XX_IPV4_SLICE1_SIZE  "bcm886xx_ipv4_slice1_size"
 
 /* Number of bits to consider in second memory. */
 #define spn_BCM886XX_IPV4_SLICE2_SIZE  "bcm886xx_ipv4_slice2_size"
 
 /* Number of bits to consider in third memory. */
 #define spn_BCM886XX_IPV4_SLICE3_SIZE  "bcm886xx_ipv4_slice3_size"
 
 /* Number of bits to consider in 4th memory. */
 #define spn_BCM886XX_IPV4_SLICE4_SIZE  "bcm886xx_ipv4_slice4_size"
 
 /* Number of bits to consider in 5th memory. */
 #define spn_BCM886XX_IPV4_SLICE5_SIZE  "bcm886xx_ipv4_slice5_size"
 
 /* Number of bits to consider in 6th memory. */
 #define spn_BCM886XX_IPV4_SLICE6_SIZE  "bcm886xx_ipv4_slice6_size"
 /*
  * default
  * pcp_lookup - PCP lookup: If set PCP is taking into account as part of Logical L2 interface, when set Mac termination is disabled
  * pon_pcp_ethertype - PCP and ETHERTYPE lookup: Whether to permit the use of PCP and Ethernet type in the AC matching lookup.
  */
 #define spn_VLAN_MATCH_CRITERIA_MODE  "vlan_match_criteria_mode"
 /*
  * default
  * full_db -  set db mode for Logical L2 interfaces lookups. Full DB: support up to 64K entries of vlan translation, when set Mac termination is disabled
  */
 #define spn_VLAN_MATCH_DB_MODE  "vlan_match_db_mode"
 /*
  * default
  * Enable Triumph3 synamic scheduler mode change
  */
 #define spn_PORT_SCHED_DYNAMIC  "port_sched_dynamic"
 /*
  * Possible values:
  * global
  * port
  * interface
  * port_and_interface
  */
 #define spn_MPLS_CONTEXT  "mpls_context"
 /*
  * Set default parameters for the DPLL command. Comma-Separated-Values.
  * DevSel, CPOL, CPHA, AddrBitOrder, DataBitOrder, AddrWidth, UseBrstBit, UseRwBit
  */
 #define spn_DPLL_PARAMS  "dpll_params"
 /*
  * Selects the format of the counter engine commands.
  * Uses port mode to differentiate between counter engines(not ports)
  * Allowed values:
  * PACKETS : Count only Packets 
  * BYTES : Count only bytes
  * PACKETS_AND_BYTES: Count Packets and bytes
  * LATENCY: Count ingress latency
  * MAX_QUEUE_SIZE
  */
 #define spn_COUNTER_ENGINE_FORMAT  "counter_engine_format"
 /*
  * Indicate which packets are counted:
  * Allowed values:
  * ALL_COPIES  : Count all packets, including replicated packets
  * FWD_COPIES : count only forwarded packets, including Multicast replicated packets , but not snooped-mirrored packets
  * ONE_COPY : only one replication per incoming packet
  */
 #define spn_COUNTER_ENGINE_REPLICATED_PACKETS  "counter_engine_replicated_packets"
 
 /* Define the sampling rate to read the near-to-overflow counters from a prefetch FIFO. interval in microseconds */
 #define spn_COUNTER_ENGINE_SAMPLING_INTERVAL  "counter_engine_sampling_interval"
 /*
  * Map the policer result. Allowed values:
  * INGR: Meter result affect ingress TM only, does not affect egress TM and remark.
  * EGR: Meter result affect egress TM and remark, does not affect ingress TM.
  * INGR_EGR: Meter result affect both ingress TM, egress TM and remark.
  * NONE: No affect for metering.
  */
 #define spn_POLICER_RESULT_MAP  "policer_result_map"
 /*
  * Set the color result function in policer parallel mode.
  * Possible values: BEST / WORST (default).
  */
 #define spn_POLICER_RESULT_PARALLEL_COLOR_MAP  "policer_result_parallel_color_map"
 /*
  * Indicate in policer parallel mode which bucket to update.
  * Possible values: CONSTANT, TRANSPARENT, DEFERRED.
  */
 #define spn_POLICER_RESULT_PARALLEL_BUCKET_UPDATE  "policer_result_parallel_bucket_update"
 
 /* If set, the Ethernet policer is blind (no influence of the input color). */
 #define spn_RATE_COLOR_BLIND  "rate_color_blind"
 /*
  * stamp the CUD in special location for HG packets. Allowed values:
  * True: stamp the CUD in PPD REP_ID field.
  * False: regular stamping of CUD to FTMH.
  */
 #define spn_XGS_COMPATABILITY_STAMP_CUD  "xgs_compatability_stamp_cud"
 /*
  * Trill mode:
  * 0: disabled
  * 1: fine-grained (single customer-tag)
  * 2: coarse-grained (double customer-tag)
  */
 #define spn_TRILL_MODE  "trill_mode"
 /*
  * Trill multicast prunning mod. Key for multicast database is tree-name,esadi-bit,<VSI>:
  * 0: no pruninig. Key is tree-name,esadi-bit.
  * 1: VSI pruning. Ket is tree-name,esadi-bit,VSI 
  */
 #define spn_TRILL_MC_PRUNE_MODE  "trill_mc_prune_mode"
 /*
  * QSGMII Alternative Serdes mapping.
  * Can be enabled per MAL, and will cause the following mapping:
  * MAL 5 --> Serdes Lane 1
  * MAL 6 --> Serdes Lane 7
  * MAL 7 --> Serdes Lane 3
  */
 #define spn_PB_QSGMII_ALT_MAPPING  "pb_qsgmii_alt_mapping"
 /*
  * Customer-specific features.
  * Is used with a propery name suffix per feature.
  * features will likely be specific to a certain device type.
  */
 #define spn_CUSTOM_FEATURE  "custom_feature"
 /*
  * maintenance default override.
  * Will be used for overrides as maintenance_default_override_<stream>_<override> with a suffix per feature.
  */
 #define spn_MAINTENANCE_DEFAULT_OVERRIDE  "maintenance_default_override"
 /*
  * Determines if the action signature is taken from the queue (QUEUE_SIGNATURE) or from the packet header (FORWARDING_ACTION)
  * possible values are: FORWARDING_ACTION, QUEUE_SIGNATURE
  */
 #define spn_ACTION_TYPE_SIGNATURE_STAMPING  "action_type_signature_stamping"
 
 /* Enable the IPv4 Host extension table */
 #define spn_IP4_HOST_EXTENSION_TABLE_ENABLE  "ip4_host_extension_table_enable"
 
 /* Select if a port is PON port and PON applications are loaded. */
 #define spn_PON_APPLICATION_SUPPORT_ENABLED  "pon_application_support_enabled"
 /*
  * The maximum number of virtual port trunk groups
  * (default is the maximum number supported by the device).
  */
 #define spn_MAX_VP_LAGS  "max_vp_lags"
 /*
  * If set, Initial-VID is supported. In that case BCM_VLAN_PORT_MATCH_PORT_INITIAL_VLAN can be used
  * and different between Untagged packets and tagged packet.
  */
 #define spn_VLAN_TRANSLATION_INITIAL_VLAN_ENABLE  "vlan_translation_initial_vlan_enable"
 
 /* Enable indicates device supports Upstream assignment label on MPLS packets */
 #define spn_MPLS_CONTEXT_SPECIFIC_LABEL_ENABLE  "mpls_context_specific_label_enable"
 /*
  * This property is prefixed by the bank number ("_#") 0-15. The value that is assigned to this property configures the bank phase access (1-4)
  * Supported values:
  * 0: Access phase is dynamic allocated.
  * 1: Access phase for MPLS Tunnel, Data.
  * 2: Access phase for MPLS tunnel, IP tunnel, I-SID, Out-RIF, Trill, Data.
  * 3: Access phase for Link Layer, Data.
  * 4: Access phase for Data.
  * 5: Access phase for PWE, MPLS Tunnel, Data. Access phase number same as 1. Egress encap bank must be synchronize with Ingress.
  * 6: Access phase for AC, Data. Access phase number same as 4. Egress encap bank must be synchronize with Ingress.
  */
 #define spn_EGRESS_ENCAP_BANK_PHASE  "egress_encap_bank_phase"
 /*
  * To Disable CES if it is enabled in Bond Optons.
  * Cant be used to Enable CES if it is not enabled in the Bond Option.
  */
 #define spn_CES_DISABLE  "ces_disable"
 /*
  * mapping Egress Queue to ILKN channel
  * e.g. egress_queue_2 = ILKN0.4 or egress_queue_core0_2 = ILKN0.4, Where "2" is egress queue 2,
  * and ILKN0.4 means ILKN interface #0, channel 4.
  */
 #define spn_EGRESS_QUEUE  "egress_queue"
 
 /* enable/disable ip-tunnel termination & encapsulation. Values: 0/1 */
 #define spn_BCM886XX_IPV6_TUNNEL_ENABLE  "bcm886xx_ipv6_tunnel_enable"
 
 /* enable/disable ERSPAN-tunnel encapsulation. Values: 0/1 */
 #define spn_BCM886XX_ERSPAN_TUNNEL_ENABLE  "bcm886xx_erspan_tunnel_enable"
 
 /* enable/disable RSPAN-tunnel encapsulation. Values: 0/1 */
 #define spn_BCM886XX_RSPAN_TUNNEL_ENABLE  "bcm886xx_rspan_tunnel_enable"
 /*
  * IPv4 tunnel lookup mode :0:none 1:dip_sip termination 2: dip_termination 3: both dip_sip and dip termination
  * 4: dip_sip_port_next_protocol termination 5: dip_sip_port_next_protocol and dip termination. In modes 4 and 5, 
  * port lookup is done by looking at the LSBs [0..3] of bcmPortClassFieldIngressVlanTranslation 6: dip sip vrf termination
  */
 #define spn_BCM886XX_IP4_TUNNEL_TERMINATION_MODE  "bcm886xx_ip4_tunnel_termination_mode"
 
 /* enable/disable etherIP (RFC 3378) support */
 #define spn_BCM886XX_ETHER_IP_ENABLE  "bcm886xx_ether_ip_enable"
 
 /* Result size of the External lookups. Unit: bytes. */
 #define spn_EXT_ACL_RESULT_SIZE  "ext_acl_result_size"
 /*
  * Set External LPM forwarding algorithem type
  * Value Options: 0/1. 0 - TCAM, 1 - Netroute, 2 - LPM. Default: 0.
  */
 #define spn_EXT_FWD_ALGORITHM_LPM  "ext_fwd_algorithm_lpm"
 /*
  * Set External lookup  interface mode.
  * Change External lookup interface configuration.
  * Value Options: 0/1. 0 - Normal mode, 1 - 2 CAUI (100 Gb) ports + External lookup mode (Arad). Default: 0.
  */
 #define spn_EXT_INTERFACE_MODE  "ext_interface_mode"
 /*
  * The number of entries in the resilient hash table used by ECMP.
  * The remaining entries are used by LAG resilient hashing.
  * By default, the table is split evenly between ECMP and LAG resilient hashing.
  * Valid values are 0, 32768, and 65536.
  */
 #define spn_ECMP_RESILIENT_HASH_SIZE  "ecmp_resilient_hash_size"
 
 /* Enable resilient hashing. */
 #define spn_RESILIENT_HASH_ENABLE  "resilient_hash_enable"
 
 /* The default number of unicast queues at L2 for LLS setup. */
 #define spn_LLS_NUM_L2UC  "lls_num_l2uc"
 /*
  * This controls whether to enable the auxiliary ouput voltage from the
  * applicable PHY devices. enable(1), disable(0).
  */
 #define spn_PHY_AUX_VOLTAGE_ENABLE  "phy_aux_voltage_enable"
 /*
  * A bitmap of ports eligible for packet replication.
  * The default value is a bitmap of valid ports.
  * This configuration property is applicable to devices on which
  * the hardware resource for packet replication needs to be statically
  * allocated to replication groups during initialization. On such
  * devices, decreasing the number of ports eligible for replication
  * would increase the number of replication groups supported.
  */
 #define spn_REPLICATION_ELIGIBLE_PBMP  "replication_eligible_pbmp"
 
 /* Option to enable/disable strict priority vector mode */
 #define spn_MMU_STRICT_PRI_VECTOR_MODE  "mmu_strict_pri_vector_mode"
 
 /* Number of writes by the DMA until a threshold based interrupt is triggered. */
 #define spn_L2_CPU_FIFO_DMA_THRESHOLD  "l2_cpu_fifo_dma_threshold"
 /*
  * Amount of time in microseconds that passes from the first write by the DMA until a timeout based interrupt is triggered.
  * Value 0 disables timeout based interrupts.
  */
 #define spn_L2_CPU_FIFO_DMA_TIMEOUT  "l2_cpu_fifo_dma_timeout"
 /*
  * Option to Set L2 learn limit mode.
  * Support modes: per VLAN - Default settings , per VLAN_PORT , per PON port and Tunnel-ID.
  */
 #define spn_L2_LEARN_LIMIT_MODE  "l2_learn_limit_mode"
 
 /* Disable l2 application configurations. */
 #define spn_DIAG_L2_DISABLE  "diag_l2_disable"
 
 /* In-LIF range base for L2 MACT limits. */
 #define spn_L2_LEARN_LIF_RANGE_BASE  "l2_learn_lif_range_base"
 
 /* This controls whether the FCMAP passthrough mode is enabled or not */
 #define spn_PHY_FCMAP_PASSTHROUGH  "phy_fcmap_passthrough"
 /*
  * Set PFC Deadlock event process sequence, only support on Tomahawk.
  * 0-SDK call user callback function after set PFC XOFF, 1-SDK call user callback function before set PFC XOFF
  */
 #define spn_PFC_DEADLOCK_SEQ_CONTROL  "pfc_deadlock_seq_control"
 /*
  * Set Flow Control mode per port per direction (RX / TX).
  * Supported modes are: 0=DISABLE (TX default), 1=LLFC (RX default), 2=PFC, 3=SAFC.
  */
 #define spn_FC_INBAND_MODE  "fc_inband_mode"
 
 /* enable/disable L2GRE support */
 #define spn_BCM886XX_L2GRE_ENABLE  "bcm886xx_l2gre_enable"
 
 /* enable/disable VXLAN support */
 #define spn_BCM886XX_VXLAN_ENABLE  "bcm886xx_vxlan_enable"
 /*
  * lookup modes for vxlan: 1: sip_dip_separated 2: sip_dip_joined
  *  3: Up to 3 lookups: first: dip lookup in ISEM returns my-vtep-index. Second: my-vtep-index, sip, vrf lookup in ISEM to terminate the tunnel.
  *  Third: An additional dip sip vrf joined in TCAM can be configured to terminate the tunnel in case the second lookup didn't hit
  *  Second and third lookup are performed only when DIP lookup hits
  */
 #define spn_BCM886XX_VXLAN_TUNNEL_LOOKUP_MODE  "bcm886xx_vxlan_tunnel_lookup_mode"
 
 /* lookup modes for l2gre: 1: sip_dip_separated 2: sip_dip_joined */
 #define spn_BCM886XX_L2GRE_TUNNEL_LOOKUP_MODE  "bcm886xx_l2gre_tunnel_lookup_mode"
 
 /* enable intra DC router */
 #define spn_BCM886XX_INTRA_DC_ROUTER_ENABLE  "bcm886xx_intra_dc_router_enable"
 /*
  *  bcm886xx_logical_interface_bridge_filter_enable.
  * If set, then Incoming logical interface can set or unset Same-interface filter.
  * In BCM88660, in case feature is set the number of bcmPortClassFieldIngressPacketProcessing is divided by 2.
  */
 #define spn_BCM886XX_LOGICAL_INTERFACE_BRIDGE_FILTER_ENABLE  "bcm886xx_logical_interface_bridge_filter_enable"
 /*
  * Set LIF ID for Simple Bridge default LIF settings. By default all ports are set with default_lif_simple.
  * Default settings set VSI = VLAN. Valid values : 0-64K
  */
 #define spn_LOGICAL_PORT_L2_BRIDGE  "logical_port_l2_bridge"
 /*
  * Set LIF ID for drop LIF settings. Drop LIF is used when user set bcmVlanTranslateIngressHitDrop for a specific port. 
  * Valid values: 0-64K. ID = -1 means do not allocate. 
  * In case LIF is not allocated bcmVlanTranslateIngressHitDrop is not supported .
  */
 #define spn_LOGICAL_PORT_DROP  "logical_port_drop"
 /*
  * Do not create default KNET Rx filter and preserve existing
  * KNET filters during BCM API initialization and shutdown.
  */
 #define spn_KNET_FILTER_PERSIST  "knet_filter_persist"
 /*
  * Set the retransmit calendar mode on the RX direction.
  * This property can be set for each ILKN channel by using a port suffix.
  * Optional values are: 
  * 0 - the calendar is disabled.
  * 1 - the calendar will handle re-transmit on the same interface.
  * 2 - the calendar will handle re-transmit on both interfaces. 
  */
 #define spn_ILKN_RETRANSMIT_CALENDAR_MODE_RX  "ilkn_retransmit_calendar_mode_rx"
 /*
  * Set the retransmit calendar mode on the TX direction.
  * This property can be set for each ILKN channel by using a port suffix.
  * Optional values are: 
  * 0 - the calendar is disabled.
  * 1 - the calendar will handle re-transmit on the same interface.
  * 2 - the calendar will handle re-transmit on both interfaces. 
  */
 #define spn_ILKN_RETRANSMIT_CALENDAR_MODE_TX  "ilkn_retransmit_calendar_mode_tx"
 /*
  * The operation mode of the CNM mechanism.
  * This property cannot be changed during run-time.
  * Optional values are: 
  * 0 - Dune PP
  * 1 - External PP
  * 2 - Sampling mode
  * 3 - HiGig
  */
 #define spn_CONGESTION_POINT_MODE  "congestion_point_mode"
 /*
  * The mapping mode between VOQs to Congestion Manages Queues.
  * This property also affects the number of ports that can be monitored by the CNM mechanism.
  * Optional values are: 
  * 0 - Each VOQ in the range of selected VOQs is mapped to a CMQ, which means supporting 8 TCs per port
  * 1 - Only odd VOQs are mapped to a CMQ, a total of 4 CMQs per port
  * 2 - Only even VOQs are mapped to a CMQ, a total of 4 CMQs per port
  */
 #define spn_VOQ_TO_CMQ_MAPPING_MODE  "voq_to_cmq_mapping_mode"
 
 /* values: 0 :NONE, 1:transit_switch 2: FCF */
 #define spn_BCM886XX_FCOE_SWITCH_MODE  "bcm886xx_fcoe_switch_mode"
 
 /* vrf-id to use for FCoE */
 #define spn_BCM886XX_FCOE_NUM_VRF  "bcm886xx_fcoe_num_vrf"
 
 /* max routes for FCoE */
 #define spn_BCM886XX_FCOE_MAX_ROUTES  "bcm886xx_fcoe_max_routes"
 
 /* 0: don't enable DF control in ipv4 tunne, 1: enable DF control, in 886xx this may affect number of qos-maps */
 #define spn_886XX_IPV4_TUNNEL_DONT_FRAGMENT  "886xx_ipv4_tunnel_dont_fragment"
 
 /* Enable EVB support */
 #define spn_EVB_ENABLE  "evb_enable"
 /*
  * DISABLE - Disable this function
  * IPV4 - Enable IPV4 source bind
  * IPV6 - Enable IPV6 source bind.
  * IP   - Enable IPV4 and IPV6 source bind.
  */
 #define spn_L3_SOURCE_BIND_MODE  "l3_source_bind_mode"
 /*
  * DISABLE - Disable IP anti-spoofing subnet function.
  * IPV4 - Enable IPv4 anti-spoofing subnet function.
  * IPV6 - Enable IPv6 anti-spoofing subnet function.
  * IP   - Enable IPV4 and IPV6 anti-spoofing subnet function.
  */
 #define spn_L3_SOURCE_BIND_SUBNET_MODE  "l3_source_bind_subnet_mode"
 
 /* Enable IPMC independent mode. */
 #define spn_IPMC_INDEPENDENT_MODE  "ipmc_independent_mode"
 
 /* Enable IPMC to operate at half of supported capacity. */
 #define spn_IPMC_REDUCED_TABLE_SIZE  "ipmc_reduced_table_size"
 /*
  * System port encoding in System that support XGS Diffserv, HQoS. Supported modes: 
  * 0 - 7_modid_8_port : System port is extracted from FRC.MODID 7b and FRC.PORT 8b
  * 1 - 8_modid_7_port : System port is extracted from FRC.MODID 8b and FRC.PORT 7b
  */
 #define spn_HIGIG_FRC_TM_SYSTEM_PORT_ENCODING  "higig_frc_tm_system_port_encoding"
 
 /* 0: don't enable DF control in ipv4 tunne, 1: enable DF control, in 886xx this may affect number of qos-maps */
 #define spn_8865X_IPV4_TUNNEL_DF_ENABLE  "8865x_ipv4_tunnel_df_enable"
 /*
  * ECN for MPLS is in disabled, 1-bit mode or 2-bits mode
  * 0 - ECN disabled
  * 1 - 1-bit mode
  * 2 - 2-bits mode.
  */
 #define spn_MPLS_ECN_MODE  "mpls_ecn_mode"
 /*
  * ECN mode for IP
  * 0 - Disabled
  * 1 - Enabled
  */
 #define spn_IP_ECN_MODE  "ip_ecn_mode"
 
 /* 16b value. Tpid of PON tunnel tag. */
 #define spn_PON_TPID_TUNNEL_ID  "pon_tpid_tunnel_id"
 /*
  * Maximal number of MAC-In-MAC VSIs. In case maximal number is 32768 then Ingress VLAN translate action is disabled. Supported values:
  * 4096 - 4K MAC-In-MAC VSIs
  * 32768 - 32K MAC-In-MAC VSIs. No ingress VLAN translate action.
  */
 #define spn_MIM_NUM_VSIS  "mim_num_vsis"
 /*
  * Set the credit worth resolution of the device.
  * Lower resolution will support wider range of port rates.
  * Higher resolution will offer better control of the exact port rate.
  * When using ILKN/CAUI interfaces, higher resolution will limit the max port rate
  * Supported values and corresponding max port rates:
  * low - up to 400G
  * medium - up to 200G
  * high - up to 50G
  * auto - will be set automatically during init according to interfaces in-use
  */
 #define spn_CREDIT_WORTH_RESOLUTION  "credit_worth_resolution"
 /*
  * In case set, Device will support My-MAC termination of reserved MC Ethernet 
  * for MPLS TP (01-00-5E-90-00-00). By default: It is enabled. For BCM 886XX default
  *  is disabled. In BCM 886xx Trill and MPLS TP mymac reserved address do not coexist
  */
 #define spn_MPLS_TP_MYMAC_RESERVED_ADDRESS  "mpls_tp_mymac_reserved_address"
 
 /* TLS database mode: 0: Default (SEM), 1: TCAM. */
 #define spn_PON_TLS_DATABASE  "pon_tls_database"
 /*
  * when set to 1, any frame received with an error is discarded in the core and not forwarded to the client interface.
  * when set to 0, error frames are forwarded to the client interface.
  * Receive MAC counters (GRPOK, GRPKT, GRBYT etc) will be incremented for CRC error packets irrespective of this setting.
  * Note:It is recommended to set this variable to 1 only when store and forward operation is enabled on the core
  */
 #define spn_PORT_RX_FCS_ERROR_EARLY_DISCARD  "port_rx_fcs_error_early_discard"
 
 /* If set, the device supports being a Control Bridge device. */
 #define spn_EXTENDER_CONTROL_BRIDGE_ENABLE  "extender_control_bridge_enable"
 
 /* If set, the device supports being a Transit-PE device. */
 #define spn_EXTENDER_TRANSIT_ENABLE  "extender_transit_enable"
 
 /* Prepend tag to be 4 bytes or 8 bytes. Default: 4B. */
 #define spn_PREPEND_TAG_BYTES  "prepend_tag_bytes"
 
 /* The Prepend Tag is located at (12 + 2*offset) bytes from the start of the packet. Default: 0 */
 #define spn_PREPEND_TAG_OFFSET  "prepend_tag_offset"
 /*
  * Port bitmap for ports that support subport feature.
  * This specifies subport feature to be enabled with any
  * mode of vlan tag based or LinkPHY channel/stream based.
  */
 #define spn_PBMP_SUBPORT  "pbmp_subport"
 /*
  * Maximum number of subports or packet processing ports per physical port.
  * This can be used to distribute the total number of available subports across
  * physical ports(cascaded port) suffix with .portX, .geX or _geX.
  */
 #define spn_NUM_SUBPORTS  "num_subports"
 /*
  * Maximum number of cos levels supported by subport or packet processing port.
  * This can be used to specify subport cos levels per physical port(cascaded port)
  * suffix with .portX, .geX or _geX.
  */
 #define spn_NUM_SUBPORT_COS  "num_subport_cos"
 
 /* packets less than this size are padded to get to this size. */
 #define spn_PACKET_PADDING_SIZE  "packet_padding_size"
 
 /* If set, the device supports being a Control Bridge device. */
 #define spn_EXTENDER_CONTROL_BRIDGE_ENABLE  "extender_control_bridge_enable"
 
 /* If set, the device supports being a Transit-PE device. */
 #define spn_EXTENDER_TRANSIT_ENABLE  "extender_transit_enable"
 
 /* Prepend tag to be 4 bytes or 8 bytes. Default: 4B. */
 #define spn_PREPEND_TAG_BYTES  "prepend_tag_bytes"
 
 /* The Prepend Tag is located at (12 + 2*offset) bytes from the start of the packet. Default: 0 */
 #define spn_PREPEND_TAG_OFFSET  "prepend_tag_offset"
 /*
  * Set OutLIF ID for NOP operation on Out-E-Channel. Must be set in case Extender application is set.
  * ID = -1 means do not allocate. Valid values: 0-64K.
  */
 #define spn_DEFAULT_LOGICAL_INTERFACE_OUT_ECH  "default_logical_interface_out_ech"
 
 /* Block trap strengths. */
 #define spn_BLOCK_TRAP_STRENGTH  "block_trap_strength"
 
 /*  Trunk hash format. Possible values: NORMAL (default) / INVERTED / DUPLICATED. */
 #define spn_TRUNK_HASH_FORMAT  "trunk_hash_format"
 /*
  * If set, the ARP table (next Hop MAC address) is extended. In BCM 886XX ARP table extend from 32K to 256K,
  * In BCM 88650 in case soc property is set System headers for PP packets always contain 5Bytes Learn extension header.
  * ARP table extension do not coexist with MIM application
  */
 #define spn_BCM886XX_NEXT_HOP_MAC_EXTENSION_ENABLE  "bcm886xx_next_hop_mac_extension_enable"
 /*
  * Enable buffer packing mode for storing multiple packets bound to the same queue in a single
  * external data buffer cell.
  */
 #define spn_MMU_MULTI_PACKETS_PER_CELL  "mmu_multi_packets_per_cell"
 
 /* 0x1: PIM-SM 0x2:PIM-BIDIR () 0x4:PIM-DS () */
 #define spn_IPMC_PIM_MODE  "ipmc_pim_mode"
 /*
  * 1: for IPMC packet with VRF !=0  (VPN) forwarding is according to VRF, G
  * 0: for IPMC packet forwarding is according to <RIF,G,SIP> regardless the VRF value
  */
 #define spn_IPMC_VPN_LOOKUP_ENABLE  "ipmc_vpn_lookup_enable"
 /*
  * in which Database to perform the PIM-BIDIR Group check
  * -    0: Exact-match
  * -    1: TCAM
  * -    2: both
  */
 #define spn_IPMC_PIM_BIDIR_CHECK_DB  "ipmc_pim_bidir_check_db"
 
 /* Enable Scheduler compensation */
 #define spn_SCHEDULER_COMPENSATION_ENABLE  "scheduler_compensation_enable"
 /*
  * Enable all of the low power modes that the device/sw combination supported.
  * 1 means enabling low power mode; 0 means disabling low power mode. 
  */
 #define spn_LOW_POWER  "low_power"
 /*
  * Set InLIF and OutLIF ID for default MIM-L2-LIF settings. By default all MacinMac ports are set with default logical_port_mim.
  * Default settings set B-VSI = B-VLAN. Valid values : 0-64K
  */
 #define spn_LOGICAL_PORT_MIM  "logical_port_mim"
 /*
  * Vlan translation mode.
  * 0: normal
  * 1: advanced mode. Enable vlan edit settings with enhanced user control
  */
 #define spn_BCM886XX_VLAN_TRANSLATE_MODE  "bcm886xx_vlan_translate_mode"
 
 /* Option to enable/disable vmac function */
 #define spn_VMAC_ENABLE  "vmac_enable"
 
 /* Set the VMAC address value (48 bits) */
 #define spn_VMAC_ENCODING_VALUE  "vmac_encoding_value"
 
 /* Set the mask of VMAC address */
 #define spn_VMAC_ENCODING_MASK  "vmac_encoding_mask"
 /*
  * If set driver reserve bcmPortClassFieldIngressPacketProcessing bit to support QOS L3 egress marking.
  * In case feature is set then the number of bcmPortClassFieldIngressPacketProcessing is divided by 2. Default value is 0 - disable the feature.
  */
 #define spn_BCM886XX_QOS_L3_L2_MARKING  "bcm886xx_qos_l3_l2_marking"
 /*
  * If set device can support Urpf mode per L3 ingress interface.
  * In BCM88660 in case feature is set the number of bcmPortClassFieldIngressPacketProcessing is divided by 2.
  */
 #define spn_BCM886XX_L3_INGRESS_URPF_ENABLE  "bcm886xx_l3_ingress_urpf_enable"
 /*
  * If set, indicate that external MAC is connected to the port.
  * when external MAC is connected to the port, 1588 CF stamping (adding residence time) is not done by the device,
  * the residence time addition is done by the external MAC.
  */
 #define spn_EXT_1588_MAC_ENABLE  "ext_1588_mac_enable"
 /*
  * If set, 48 bits stamping is used for 1588 packets. otherwise 32 bit stamping is used
  * (supported only for Arad+)
  */
 #define spn_BCM88660_1588_48B_STAMPING_ENABLE  "bcm88660_1588_48b_stamping_enable"
 /*
  * If set , device supports ELI special Entropy Label Indicator capabilities in MPLS networks.
  * In BCM 886xx it is supported by default.
  */
 #define spn_MPLS_ENTROPY_LABEL_INDICATOR_ENABLE  "mpls_entropy_label_indicator_enable"
 
 /* If set , device supports Adding ELI special Entropy Label Indicator when initiating a MPLS tunnel. */
 #define spn_MPLS_EGRESS_LABEL_ENTROPY_INDICATOR_ENABLE  "mpls_egress_label_entropy_indicator_enable"
 /*
  * 0: Separate port use-count, port limit and port resume for UC and MC.
  * 1: Combined port use-count, port limit and port resume for UC and MC.
  */
 #define spn_PORT_UC_MC_ACCOUNTING_COMBINE  "port_uc_mc_accounting_combine"
 /*
  * 0: A red result from both modules implies that DP=3.
  * 1: A red result from the policer implies that DP=2, while a red result from rate (Ethernet policer) implies DP=3.
  * This allows to distinguish between an Ethernet meter drop and a regular meter drop.
  */
 #define spn_POLICER_COLOR_RESOLUTION_MODE  "policer_color_resolution_mode"
 /*
  * If set then the MPLS BOS bit is not used as a key for MPLS tunnel termination.
  * 0: key is <label,Is-BOS>
  * 1: key is label only.
  */
 #define spn_BCM886XX_MPLS_TERMINATION_KEY_MODE  "bcm886xx_mpls_termination_key_mode"
 /*
  * 0: Global
  * 1: Local
  */
 #define spn_BCM88XXX_SYSTEM_RESOURCE_MANAGEMENT  "bcm88xxx_system_resource_management"
 
 /* Enable or disable local switching feature */
 #define spn_LOCAL_SWITCHING_ENABLE  "local_switching_enable"
 /*
  * Set voltage mode for oob interfaces
  * HSTL_1.5V
  * 3.3V
  * HSTL_1.5V_VDDO_DIV_2
  * HSTL_1.8V
  */
 #define spn_EXT_VOLTAGE_MODE  "ext_voltage_mode"
 /*
  * Map a chip to a family. This is used in order to map several chips
  * which require similar soc properties to a family, and than use the
  * family as the property suffix.
  * E.g, map chip X and Y to family Z, and than one can define property.Z
  * than will be recognized by both X and Y.
  */
 #define spn_SOC_FAMILY  "soc_family"
 /*
  * Enable/Disable ILKN reset when watchdog error occurs
  * 0: Disable
  * 1: Enable
  */
 #define spn_ILKN_RETRANSMIT_RX_RESET_UPON_WATCHDOG_ERROR_ENABLE  "ilkn_retransmit_rx_reset_upon_watchdog_error_enable"
 
 /* The channel ID reserved for retransmit request. */
 #define spn_ILKN_RETRANSMIT_RESERVED_CHANNEL_ID  "ilkn_retransmit_reserved_channel_id"
 /*
  * Nubmer of bits from MULTIPLE USE field that are used for re-transmit burst numbering
  * Valid range is 5/6/7/8
  */
 #define spn_ILKN_RETRANSMIT_SN_BITS  "ilkn_retransmit_sn_bits"
 /*
  * Time after ignore_crc24_delay time within which receiver should detect a Jump in sequence number
  * units in micro-secs (usec)
  */
 #define spn_ILKN_RETRANSMIT_RX_DISCONTINUITY_EVENT_TIMEOUT  "ilkn_retransmit_rx_discontinuity_event_timeout"
 
 /* Maximum number of Interlaken data words for which receiver waits for last good sequence detection after jump is detected */
 #define spn_ILKN_RETRANSMIT_PEER_TX_BUFFER_SIZE  "ilkn_retransmit_peer_tx_buffer_size"
 /*
  * MPLS termination databases mode. 
  * Default mode when mpls_termination_label_index_enable=0 is 0. 
  * Default mode when mpls_termiantino_label_index_enable=1 is 2. 
  * 0: MPLS_1 refers to label namespaces L1,L2. MPLS_1 is located in SEM-B. 
  * Valid only in case mpls_termination_label_index_enable=0. 
  * 1: MPLS_1 refers to label namespaces L1,L2. MPLS_1 is located in SEM-A. 
  * Valid only in case mpls_termination_label_index_enable=0. 
  * Note: In this mode MPLS and bcmVlanPortDoubleLookupEnable are supported on the same-port. 
  * 2: MPLS_x refers to label namespace Lx. MPLS_1,_3 is located in SEM-B, MPLS_2 is located in SEM-A. 
  * Valid only in case mpls_termination_label_index_enable=1. 
  * 3: MPLS_x refers to label namespace Lx. MPLS_1,_3 is located in SEM-A, MPLS_2 is located in SEM-B. 
  * Valid only in case mpls_termination_label_index_enable=1. 
  * Note: In this mode MPLS and bcmVlanPortDoubleLookupEnable are supported on the same-port. 
  * 4: MPLS_x refers to label namespace Lx. MPLS_1,_2 is located in SEM-B, MPLS_3 is located in SEM-A. 
  * Valid only in case mpls_termination_label_index_enable=1. 
  * 5: MPLS_x refers to label namespace Lx. MPLS_1,_2 is located in SEM-A, MPLS_3 is located in SEM-B. 
  * Valid only in case mpls_termination_label_index_enable=1. 
  * Note: In this mode MPLS and bcmVlanPortDoubleLookupEnable are supported on the same-port. 
  * 6: MPLS_1 refers to label namespace L1,L2 and located in SEM-A. MPLS_2 refers to label namespace L3 and located in SEM-B. 
  * Valid only in case mpls_termination_label_index_enable=1. 
  * Note: In this mode MPLS and bcmVlanPortDoubleLookupEnable are supported on the same-port. 
  * 7: MPLS_1 refers to label namespace L1,L2 and located in SEM-B. MPLS_2 refers to label namespace L3 and located in SEM-A. 
  * Valid only in case mpls_termination_label_index_enable=1. 
  * 8: MPLS_1 refers to label namespace L1,L3 and located in SEM-A. MPLS_2 refers to label namespace L2 and located in SEM-B. 
  * Valid only in case mpls_termination_label_index_enable=1. 
  * Note: In this mode MPLS and bcmVlanPortDoubleLookupEnable are supported on the same-port. 
  * 9: MPLS_1 refers to label namespace L1,L3 and located in SEM-B. MPLS_2 refers to label namespace L2 and located in SEM-A. 
  * Valid only in case mpls_termination_label_index_enable=1. 
  * 10: MPLS_1 refers to label namespace L1 and located in SEM-A. MPLS_2 refers to label namespace L2 and located in SEM-B. 
  * Tunnel termination lookups are done at the TT stage only. 
  * Valid only in case mpls_termination_label_index_enable=1 and BCM88x6x and above. 
  */
 #define spn_BCM886XX_MPLS_TERMINATION_DATABASE_MODE  "bcm886xx_mpls_termination_database_mode"
 
 /* Timeout delay in seconds before entering power down state */
 #define spn_POWER_DOWN_TIMEOUT  "power_down_timeout"
 /*
  * If set then device support multiple MyMAC termination. 
  * VRRP and multiple mymac termination do not co-exist on the same device. 
  * Therefore, when enabling this soc property, l3_vrrp_max_vid and
  * l3_vrrp_ipv6_distinct must be set to 0. 
  */
 #define spn_L3_MULTIPLE_MYMAC_TERMINATION_ENABLE  "l3_multiple_mymac_termination_enable"
 
 /* 0 - dont distinct between L3 protocols , 1 - distinct between IPV4 and other L3 packets  */
 #define spn_L3_MULTIPLE_MYMAC_TERMINATION_MODE  "l3_multiple_mymac_termination_mode"
 
 /* 0 - profile priority group with 1 shared profile and 8 headroom profiles, 1 - profile priority group with 8 shared profiles and 1 headroom profile */
 #define spn_PROFILE_PG_1HDRM_8SHARED  "profile_pg_1hdrm_8shared"
 
 /* Core clock frequency applied to switch chip, any unsupported frequency will be ignored */
 #define spn_CORE_CLOCK_FREQUENCY  "core_clock_frequency"
 
 /* Tdm frequency to be used for the  switch chip, any unsupported frequency will be ignored */
 #define spn_BCM_TDM_FREQUENCY  "bcm_tdm_frequency"
 
 /* Max io Bandwidth to be used for the  switch chip, any unsupported frequency will be ignored */
 #define spn_BCM_TDM_IO_BANDWIDTH  "bcm_tdm_io_bandwidth"
 
 /* Percentage of port LED intensity. Valid value 0~100 */
 #define spn_LED_INTENSITY  "led_intensity"
 
 /* Enable external TCAM lane swap for TX during ETU init */
 #define spn_EXT_TCAM_TX_LANE_SWAP  "ext_tcam_tx_lane_swap"
 
 /* Enable external TCAM lane swap for RX during ETU init */
 #define spn_EXT_TCAM_RX_LANE_SWAP  "ext_tcam_rx_lane_swap"
 
 /* External TCAM request response latency */
 #define spn_EXT_TCAM_REQUEST_RESPONSE_LATENCY  "ext_tcam_request_response_latency"
 /*
  * 1: Allow adding 64B IPV6 LPM entries in unreserved paired TCAM.
  * 0: Do not allow adding 64B IPV6 LPM entries in paired TCAM.
  */
 #define spn_LPM_SCALING_ENABLE  "lpm_scaling_enable"
 /*
  * 1: num_ipv6_lpm_128b_entries number of entries are reserved exclusively for 128B V6 LPM entries
  * 0: Do not reserve any entries for 128B V6 entries and use the whole of paired TCAMs for either 128B V6, 64B V6, V4 entries.
  * Ignored if lpm_scaling_enable is 0.
  */
 #define spn_LPM_IPV6_128B_RESERVED  "lpm_ipv6_128b_reserved"
 
 /* Enables accelerated linkscan mode on specified port. */
 #define spn_RX_FAST_LOS_LINK  "rx_fast_los_link"
 /*
  * Indicates the linkscan time interval in usecs 
  * during accelerated mode.
  */
 #define spn_RX_FAST_LOS_USEC  "rx_fast_los_usec"
 /*
  * Indicates the maximum number of times linkscan 
  * will poll in accelerated mode without a status 
  * change in any accelerated mode ports.
  */
 #define spn_RX_FAST_LOS_POLL_COUNT_MAX  "rx_fast_los_poll_count_max"
 
 /* Set the default MMU configuration  */
 #define spn_MMU_CONFIG_OVERRIDE  "mmu_config_override"
 /*
  * Sets TDM dedicated queuing mode for ILKN 
  * 0 - TDM dedicated queuing is disabled 
  * 1 - TDM dedicated queuing is enabled 
  */
 #define spn_ILKN_TDM_DEDICATED_QUEUING  "ilkn_tdm_dedicated_queuing"
 /*
  * Device Interconnect Mode (PCI-EB2).
  * 0 = PCI, 1 = EB2
  */
 #define spn_EB2_2BYTES_BIG_ENDIAN  "eb2_2bytes_big_endian"
 /*
  * Disable, enable designated VLAN check. In case of 
  * disable bcmPortControlTrillDesignatedVlan is not 
  * applicable. By default: feature is enabled
  */
 #define spn_TRILL_DESIGNATED_VLAN_CHECK_DISABLE  "trill_designated_vlan_check_disable"
 /*
  * Device Interconnect Mode (PCI-EB2).
  * 0 = PCI, 1 = EB2
  */
 #define spn_EB2_2BYTES_BIG_ENDIAN  "eb2_2bytes_big_endian"
 
 /* Enable/Disable vlan translation match for IPv4 frames based on 5-tuple information. */
 #define spn_VLAN_TRANSLATION_MATCH_IPV4  "vlan_translation_match_ipv4"
 /*
  * If set presel managemnet works in advanced mode, otherwise works in simple mode 
  * Advanced mode enables managing the program selectors insertion/deletion in PSL table in atomic operation.
  */
 #define spn_FIELD_PRESEL_MGMT_ADVANCED_MODE  "field_presel_mgmt_advanced_mode"
 
 /* If set ITMH proceesing works in programmable mode, otherwise works in simple mode  */
 #define spn_ITMH_PROGRAMMABLE_MODE_ENABLE  "itmh_programmable_mode_enable"
 
 /* If set ITMH processing works in ARAD mode, itmh_programmable_mode_enable needs to be set to 0 in order for this property to work  */
 #define spn_ITMH_ARAD_MODE_ENABLE  "itmh_arad_mode_enable"
 /*
  * Disable and restrict user to create l2 entry 
  * as part of l3 interface create
  */
 #define spn_L3_DISABLE_ADD_TO_ARL  "l3_disable_add_to_arl"
 
 /* Triumph3 external TCAM 0 Serdes Tx/Ctx driver current */
 #define spn_EXT_TCAM0_TX_DRIVER_CURRENT  "ext_tcam0_tx_driver_current"
 
 /* Triumph3 external TCAM 0 Serdes Tx/Ctx postcursor tap */
 #define spn_EXT_TCAM0_TX_POSTCURSOR_TAP  "ext_tcam0_tx_postcursor_tap"
 
 /* Triumph3 external TCAM 0 Serdes Tx/Ctx main tap */
 #define spn_EXT_TCAM0_TX_MAIN_TAP  "ext_tcam0_tx_main_tap"
 
 /* Triumph3 external TCAM 0 Serdes Rx/Crx gain */
 #define spn_EXT_TCAM0_RX_GAIN  "ext_tcam0_rx_gain"
 
 /* Triumph3 external TCAM 1 Serdes Tx/Ctx driver current */
 #define spn_EXT_TCAM1_TX_DRIVER_CURRENT  "ext_tcam1_tx_driver_current"
 
 /* Triumph3 external TCAM 1 Serdes Tx/Ctx postcursor tap */
 #define spn_EXT_TCAM1_TX_POSTCURSOR_TAP  "ext_tcam1_tx_postcursor_tap"
 
 /* Triumph3 external TCAM 1 Serdes Tx/Ctx main tap */
 #define spn_EXT_TCAM1_TX_MAIN_TAP  "ext_tcam1_tx_main_tap"
 
 /* Triumph3 external TCAM 1 Serdes Rx/Crx gain */
 #define spn_EXT_TCAM1_RX_GAIN  "ext_tcam1_rx_gain"
 
 /* Set 2 MSBs value of ARP-pointer in Host-table Routing over overlay format. */
 #define spn_BCM886XX_ROO_HOST_ARP_MSBS  "bcm886xx_roo_host_arp_msbs"
 
 /* If set, enable Native Routing over Overlay (ROO) in device */
 #define spn_BCM886XX_ROO_ENABLE  "bcm886xx_roo_enable"
 
 /* If set, enable processing of IPv6 extension headers */
 #define spn_BCM886XX_IPV6_EXT_HDR_ENABLE  "bcm886xx_ipv6_ext_hdr_enable"
 /*
  * 0 - Use 0-1 range for lif orientation
  *     No inlif profile and outlif profile bits are occupied
  * 1 - Use 0-1 range for lif orientation in AC lifs and 0-3 range for orientation in other lif types
  *     0/1bit is occupied in AC/OTHER inlif profile; 1/2bits are occupied in AC/OTHER outlif profile
  * 2 - Use 0-3 range for lif orientation
  *     1bits is occupied in inlif profile; 2bits are occupied in outlif profile
  * 3 - Use 0-1 range for lif orientation
  *     0bit is occupied in inlif profile; 1bit is occupied in outlif profile
  */
 #define spn_SPLIT_HORIZON_FORWARDING_GROUPS_MODE  "split_horizon_forwarding_groups_mode"
 /*
  * 1: Some of last entries of MMU_REPL_HEAD_TBL are reserved.
  *    The number of reserved entries equals to the number of ports
  *    in the valid PBMP.
  *    When there are not enough entries during deleting a port from
  *    a replication group, the reserved entries will be used as
  *    a swap space to configure the replication info of the group.
  *    After the port is deleted, there will be enough entries to
  *    configure the replication info of the group.
  *    Then, the reserved entires will be in free status again.
  * 0: The entires are not reserved.
  */
 #define spn_RESERVE_MULTICAST_RESOURCES  "reserve_multicast_resources"
 
 /* 32b value. In-LIF-ID of IP-LIF-dummy for termination of IP-Overlay bud multicast traffic. */
 #define spn_DEFAULT_LOGICAL_INTERFACE_IP_TUNNEL_OVERLAY_MC  "default_logical_interface_ip_tunnel_overlay_mc"
 
 /* 16b value. In-LIF-ID of MPLS-LIF-dummy for termination of MPLS 1 label bud multicast supporting DataoIPoMPLSoE packets. */
 #define spn_DEFAULT_LOGICAL_INTERFACE_MPLS_1_LABEL_BUD_MULTICAST  "default_logical_interface_mpls_1_label_bud_multicast"
 
 /* 16b value. In-LIF-ID of MPLS-LIF-dummy for termination of MPLS 2 labels bud multicast supporting DataoIPoMPLSoMPLSoE packets. */
 #define spn_DEFAULT_LOGICAL_INTERFACE_MPLS_2_LABELS_BUD_MULTICAST  "default_logical_interface_mpls_2_labels_bud_multicast"
 /*
  * 0 - Enable the 60x1GE/2.5GE and 2x40XE mode of BCM56849.
  * 1 - Enable the 56x1GE/2.5GE and 8x10XE mode of BCM56849.
  * By default 56x1GE/2.5GE and 8x10XE mode will be used.
  */
 #define spn_BCM56849_56X2POINT5_8X10  "bcm56849_56x2point5_8x10"
 
 /* If set, aging is done based on HITSA only, not considering HITDA. Config property valid only for BCM56640 and BCM56340 */
 #define spn_L2X_AGE_ONLY_ON_HITSA  "l2x_age_only_on_hitsa"
 /*
  * Specifies ingress objects sharing same pool or using exclusive pool.
  * Example:
  * ing_share_flex_counter_pool=split(vlan,vfi) make vlan, vfi use exclusive pool.
  * ing_share_flex_counter_pool=share(vlan,vfi) make vlan, vfi use same pool.
  * An object can appear in both share case and split case,
  * but in each case it can appear one time at most.
  * Use token between each groups and use comma between each objects.
  * eg: ing_share_flex_counter_pool=split(A,B,C);share(C,D);
  * Some objects may use the same HW table, so only the first one will take effect.
  * All valid object name: 
  * port, vlan, vlanxlate, vfi, l3intf, vrf, policy, mplsvclabel, mplsswitchlabel, mplsfrrlabel,
  * l3host, trill, mimlookupid, l2gre, extpolicy, vxlan, vsan, fcoe, l3route, niv, ipmc.
  */
 #define spn_ING_SHARE_FLEX_COUNTER_POOL  "ing_share_flex_counter_pool"
 
 /* Number of RPC Server Threads, RPC Server threads handle
                         the requests from RPC Clients concurrently. By default 
                         the number of threads are set to 1. */
 #define spn_RPC_SERVER_THREAD_COUNT  "rpc_server_thread_count"
 /*
  * Ingress Protection Coupling mode.
  * 0: Decoupled mode
  * 1: Coupled mode
  */
 #define spn_BCM886XX_INGRESS_PROTECTION_COUPLED_MODE  "bcm886xx_ingress_protection_coupled_mode"
 /*
  * Egress Protection Coupling mode.
  * 0: Decoupled mode
  * 1: Coupled mode
  */
 #define spn_BCM886XX_EGRESS_PROTECTION_COUPLED_MODE  "bcm886xx_egress_protection_coupled_mode"
 /*
  * FEC accelerated failover reroute mode.
  * 0: Standard path reroute mode
  * 1: Accelerated reroute mode
  */
 #define spn_BCM886XX_FEC_ACCELERATED_REROUTE_MODE  "bcm886xx_fec_accelerated_reroute_mode"
 /*
  * Packet Cell Packing (PCP) enable.
  * 0: Disable PCP
  * 1: Enable PCP
  */
 #define spn_FABRIC_PCP_ENABLE  "fabric_pcp_enable"
 /*
  * 1: Allow defining LPM prefix layout in unpaired TCAM during initialization stage.
  * 0: Do not defining LPM prefix layout in unpaired TCAM during initialization stage.
  */
 #define spn_LPM_LAYOUT_PREFIX_ENABLE  "lpm_layout_prefix_enable"
 /*
  * LPM could support LPM free space layout for different prefixes.
  * Specifies the IP version, VRF type, prefix length and prefix count.
  * via string lpm_layout_prefix<# of idx 0-64>=<IP ver>:<VRF type>:<prefix length>:<prefix count>.
  * i.e. lpm_layout_prefix<1-64> = <4/6>:<0/1/2>:<0~32/0~64/>:<number>
  * IP version: IPv4 or IPv6
  * VRF type: 0 for specific VRF, 1 for BCM_L3_VRF_OVERRIDE, 2 for BCM_L3_VRF_GLOBAL
  * Prefix length: for IPv4, its range is 0~32, for IPv6, its range is 0~64
  * Prefix count: total route number should not greater than L3_DEFIP memory capacity
  * This property does not support for Warmboot.
  */
 #define spn_LPM_LAYOUT  "lpm_layout"
 /*
  * Few devices(BCM56334_B0) can forward MIM missed look up
  * packets to a predefined default port. This property is
  * used to reserve that specific MIM port. At present it is
  * only valid for 56334_B0.
  */
 #define spn_RESERVE_MIM_DEFAULT_SVP  "reserve_mim_default_svp"
 /*
  * A mode representing if a devices cores are configured symmetrically, asymmetrically, or for single core only.
  * possiable values:
  * SYMMETRIC
  * ASYMMETRIC
  * SINGLE_CORE
  */
 #define spn_DEVICE_CORE_MODE  "device_core_mode"
 /*
  * A configuration of higher preference to addmitance tests or to resource reservation.
  * If admit tests have higher precedence, they will drop packets even if they are with in the guarenteed/reserved range.
  * The configuration is either for all drop precendences, or for a specific one when its number (0-3) is specified as a postfix.
  * possiable values:
  * ADMIT_OVER_GUARANTEE
  * GUARANTEE_OVER_ADMIT
  */
 #define spn_COSQ_ADMISSION_PREFERENCE  "cosq_admission_preference"
 /*
  * Trill transparent service enable the Trill campus to carry customer VLAN information for remote processing:
  * 0: disabled
  * 1: enabled
  */
 #define spn_TRILL_TRANSPARENT_SERVICE  "trill_transparent_service"
 /*
  * Fabric Receive Adapter supports two modes for mapping the fabric links to egress core:
  * Possible values:
  * SHARED - Both cores are reachable through all links.
  * DEDICATED - Each egress core receive data cells from a specific set of fabric links-
  * Egress core 0 is reachable only through links 0-17 and egress core 1  is reachable only through links 18-35.
  */
 #define spn_FABRIC_LINKS_TO_CORE_MAPPING_MODE  "fabric_links_to_core_mapping_mode"
 /*
  * This soc property signifies the first fabric logical port id.
  * All logical port ids of the fabric ports will be defined from this value up.
  */
 #define spn_FABRIC_LOGICAL_PORT_BASE  "fabric_logical_port_base"
 /*
  * The allocation of the total cores resources between source and queue based reservation depends on one of two guarantee modes: strict and loose.
  *  ingress_congestion_management_guarantee_mode={STRICT,LOOSE} default: STRICT
  * Each DP has its own thresholds for source based (dynamic) and for queue based (pools 0,1 and headroom).
  *  ingress_congestion_management_{source,queue,all}_threshold_percentage_color_[0-3]=[0-100] default: 100,85,75,0
  *  ingress_congestion_management_{ocb_only,dram_mix}_{pool_{0,1},headroom}=size default: 0
  *  ingress_congestion_management_min_resource_percentage_dynamic=[0-80] default: 20
  */
 #define spn_INGRESS_CONGESTION_MANAGEMENT  "ingress_congestion_management"
 
 /* The allowed maximum ID of ST-VSQs */
 #define spn_INGRESS_CONGESTION_MANAGEMENT_STAG_MAX_ID  "ingress_congestion_management_stag_max_id"
 
 /* Enable header-compansation */
 #define spn_INGRESS_CONGESTION_MANAGEMENT_PKT_HEADER_COMPENSATION_ENABLE  "ingress_congestion_management_pkt_header_compensation_enable"
 
 /* the maximal ID for TM-ports, if 0 then the any-value is legal. */
 #define spn_INGRESS_CONGESTION_MANAGEMENT_TM_PORT_MAX_ID  "ingress_congestion_management_tm_port_max_id"
 
 /* Select egress queue for TDM traffic. */
 #define spn_TDM_EGRESS_PRIORITY  "tdm_egress_priority"
 
 /* Select egress drop precedence TDM traffic. */
 #define spn_TDM_EGRESS_DP  "tdm_egress_dp"
 
 /* Enable or disable FEC. */
 #define spn_PHY_FEC_ENABLE  "phy_fec_enable"
 
 /* If set, PWE-GAL DB in MPLS termination stage is supported on device. */
 #define spn_MPLS_TERMINATION_PWE_VCCV_TYPE4_MODE  "mpls_termination_pwe_vccv_type4_mode"
 
 /* Enable fabric multicast in Mesh systems */
 #define spn_FABRIC_MESH_MULTICAST_ENABLE  "fabric_mesh_multicast_enable"
 /*
  * BCM56960/BCM56970 : MMU Cell Buffer Allocation Profile to support ASF (cut-thru) Forwarding
  * 0: No cut-through support
  * 1: Similar speed profile (Default)
  * 2: Extreme speed profile
  */
 #define spn_ASF_MEM_PROFILE  "asf_mem_profile"
 
 /* If set, device support Explicit NULL label TCAM lookup at the VT stage. */
 #define spn_MPLS_TERMINATION_EXPLICIT_NULL_LABEL_LOOKUP_MODE  "mpls_termination_explicit_null_label_lookup_mode"
 
 /* In-LIF-ID of MPLS-LIF-dummy for termination of Explicit NULL label. */
 #define spn_DEFAULT_LOGICAL_INTERFACE_MPLS_TERMINATION_EXPLICIT_NULL  "default_logical_interface_mpls_termination_explicit_null"
 /*
  * L3 routing disable mode on incoming logical port
  * 0: None
  * 1: Combinational mode
  * 2: Separate mode
  */
 #define spn_L3_DISABLED_ON_LIF_MODE  "l3_disabled_on_lif_mode"
 /*
  * L3 routing disable bits in profile of incoming logical port,valid when l3_disabled_on_lif_mode != 0
  * Bit 0:1 ---bit nmuber for IPv4 
  * Bit 2:3 ---bit nmuber for IPv6 
  */
 #define spn_L3_DISABLED_BIT_ON_LIF  "l3_disabled_bit_on_lif"
 
 /* enable bfd echo functionality. */
 #define spn_BFD_ECHO_ENABLED  "bfd_echo_enabled"
 /*
  * External lookup (elk) ILKN lanes swap. If set, reverse the lanes numbering order on elk device side.
  * This swap is logical and relates to ILKN protocol lane numbering.
  */
 #define spn_EXT_ILKN_REVERSE  "ext_ilkn_reverse"
 
 /* enable raw mpls port configuration on device */
 #define spn_PORT_RAW_MPLS_ENABLE  "port_raw_mpls_enable"
 
 /* Enable support for NTP format in OAM DM messages */
 #define spn_OAM_DM_NTP_ENABLE  "oam_dm_ntp_enable"
 
 /* Enable support for bfd ipv4 single hop extended mode */
 #define spn_BFD_IPV4_SINGLE_HOP_EXTENDED  "bfd_ipv4_single_hop_extended"
 /*
  * Enable support for micro bfd
  * May be set to NONE, IPv4, IPv6 or IPv4_AND_IPv6
  */
 #define spn_MICRO_BFD_SUPPORT_MODE  "micro_bfd_support_mode"
 /*
  * Specifies egress objects sharing same pool or using exclusive pool.
  * Example:
  * egr_share_flex_counter_pool=split(vlan,vfi) make egr_vlan, egr_vfi use exclusive pool.
  * egr_share_flex_counter_pool=share(vlan,vfi) make egr_vlan, egr_vfi use same pool.
  * An object can appear in both share case and split case,
  * but in each case it can appear one time at most.
  * Use token between each groups and use comma between each objects.
  * eg: egr_share_flex_counter_pool=split(A,B,C);share(C,D);
  * Some objects may use the same HW table, so only the first one will take effect.
  * All valid egress object name: 
  * port, vlan, vlanxlate, vfi, l3intf, mimlookupid, l2gre, vxlan, l3nat, niv, wlan, mim.
  */
 #define spn_EGR_SHARE_FLEX_COUNTER_POOL  "egr_share_flex_counter_pool"
 /*
  * Specifies egress objects can different egress properties.
  * Acceptable values:
  * 0 -- bcm_l3_intf_t objects with the same l3a_vid can NOT have different egress properties
  * (e.g. l3a_mtu, l3a_mac_addr). However, Strict Mode URPF and ICMP redirected to cpu are
  * guaranteed to work.
  * 1 -- bcm_l3_intf_t objects with the same l3a_vid can have different (split) egress
  * personalities, e.g. l3a_mtu, l3a_mac_addr. However, Strict Mode URPF and ICMP
  * redirected to cpu are not guaranteed to work.
  */
 #define spn_L3_INTF_VLAN_SPLIT_EGRESS  "l3_intf_vlan_split_egress"
 
 /* Enable the use of SW shadow for exact match tables. */
 #define spn_EXACT_MATCH_TABLES_SHADOW_ENABLE  "exact_match_tables_shadow_enable"
 
 /* Enable support for packet I/O continuous DMA mode */
 #define spn_PDMA_CONTINUOUS_MODE_ENABLE  "pdma_continuous_mode_enable"
 
 /* Enable ECN Delay Measurement */
 #define spn_ECN_DM_ENABLE  "ecn_dm_enable"
 
 /* Enable 48 bytes OAM MAID using external FPGA */
 #define spn_OAM_MAID_48_BYTES_EXTERNAL_ENABLE  "oam_maid_48_bytes_external_enable"
 
 /* Enable 11 bytes OAM MAID */
 #define spn_OAM_MAID_11_BYTES_ENABLE  "oam_maid_11_bytes_enable"
 
 /* Enable 1dm OAM packets handling */
 #define spn_OAM_ONE_DM_ENABLE  "oam_one_dm_enable"
 
 /* If set, enable L2_ENTRY and L2_USER_ENTRY my station hit. */
 #define spn_L2_ENTRY_USED_AS_MY_STATION  "l2_entry_used_as_my_station"
 
 /* Enable SDK to load the ARM core 0 image. */
 #define spn_MCS_LOAD_UC0  "mcs_load_uc0"
 
 /* Enable SDK to load the ARM core 1 image. */
 #define spn_MCS_LOAD_UC1  "mcs_load_uc1"
 
 /* Set random seed to configure remapping structures for robust hash vlan translate table. */
 #define spn_ROBUST_HASH_SEED_VLAN  "robust_hash_seed_vlan"
 
 /* Set random seed to configure remapping structures for robust hash vlan translate 1 table. */
 #define spn_ROBUST_HASH_SEED_VLAN_1  "robust_hash_seed_vlan_1"
 
 /* Set random seed to configure remapping structures for robust hash vlan translate 2 table. */
 #define spn_ROBUST_HASH_SEED_VLAN_2  "robust_hash_seed_vlan_2"
 
 /* Set random seed to configure remapping structures for robust hash egress vlan translate table. */
 #define spn_ROBUST_HASH_SEED_EGRESS_VLAN  "robust_hash_seed_egress_vlan"
 
 /* Set random seed to configure remapping structures for robust hash egress vlan translate table. */
 #define spn_ROBUST_HASH_SEED_EGRESS_VLAN_1  "robust_hash_seed_egress_vlan_1"
 
 /* Set random seed to configure remapping structures for robust hash egress vlan translate table. */
 #define spn_ROBUST_HASH_SEED_EGRESS_VLAN_2  "robust_hash_seed_egress_vlan_2"
 
 /* Set random seed to configure remapping structures for robust hash MPLS table. */
 #define spn_ROBUST_HASH_SEED_MPLS  "robust_hash_seed_mpls"
 
 /* Set random seed to configure remapping structures for robust hash L2 table. */
 #define spn_ROBUST_HASH_SEED_L2  "robust_hash_seed_l2"
 
 /* Set random seed to configure remapping structures for robust hash L3 table. */
 #define spn_ROBUST_HASH_SEED_L3  "robust_hash_seed_l3"
 
 /* Set random seed to configure remapping structures for robust hash Exact Match table. */
 #define spn_ROBUST_HASH_SEED_EXACT_MATCH  "robust_hash_seed_exact_match"
 
 /* Set random seed to configure remapping structures for robust hash subport id sgpp map table. */
 #define spn_ROBUST_HASH_SEED_SUBPORT_ID_TO_SGPP_MAP  "robust_hash_seed_subport_id_to_sgpp_map"
 
 /* Set random seed to configure remapping structures for robust hash L3 table. */
 #define spn_ROBUST_HASH_SEED_ING_DNAT_ADDRESS  "robust_hash_seed_ing_dnat_address"
 
 /* Set random seed to configure remapping structures for robust hash L3 Tunnel table. */
 #define spn_ROBUST_HASH_SEED_L3_TUNNEL  "robust_hash_seed_l3_tunnel"
 
 /* Exopose HW id in traps */
 #define spn_BCM886XX_RX_USE_HW_TRAP_ID  "bcm886xx_rx_use_hw_trap_id"
 /*
  * BCM5696x : VP support in embedded nexthop
  * 0 (FALSE): embedded nexthop (l3_egress) information in bcm_l3_host_t can only use BCM_GPORT_MODPORT
  * or BCM_GPORT_TRUNK (i.e. a DGLP) as the destination
  * 1 (TRUE): embedded nexthop (l3_egress) information in bcm_l3_host_t can use other types of GPORTs
  * (e.g. BCM_GPORT_NIV as the destinations (if supported by a given device; on the devices that do not
  * support this feature, the property will be silently ignored)). The tradeoff is that on some of the devices
  * the number of distinct destination MAC addresses or other parameters might be limited.
  */
 #define spn_EMBEDDED_NH_VP_SUPPORT  "embedded_nh_vp_support"
 
 /* Enable flex port on 20G oversub port. */
 #define spn_20G_OVERSUB_PORT_FLEXPORT_ENABLE  "20g_oversub_port_flexport_enable"
 
 /* Set random seed to configure remapping structures for robust hash Ingress VP VLAN Membership table. */
 #define spn_ROBUST_HASH_SEED_INGRESS_VP_VLAN  "robust_hash_seed_ingress_vp_vlan"
 
 /* Set random seed to configure remapping structures for robust hash Egress VP VLAN Membership table. */
 #define spn_ROBUST_HASH_SEED_EGRESS_VP_VLAN  "robust_hash_seed_egress_vp_vlan"
 
 /* The number of inrif mac termination combinations. Legal values 0 - 16 */
 #define spn_NUMBER_OF_INRIF_MAC_TERMINATION_COMBINATIONS  "number_of_inrif_mac_termination_combinations"
 
 /* Enable OAM statistics per mep ID. */
 #define spn_OAM_STATISTICS_PER_MEP_ENABLED  "oam_statistics_per_mep_enabled"
 /*
  * BCM56960: Set number of ECMP Levels/ECMP mode.
  * 1: One Level or Single Level Mode
  * 2: Two Levels or Hierarchical Mode
  */
 #define spn_L3_ECMP_LEVELS  "l3_ecmp_levels"
 
 /* The size of public forwarding table in number of entries. */
 #define spn_PUBLIC_IP_FRWRD_TABLE_SIZE  "public_ip_frwrd_table_size"
 
 /* The size of private forwarding table in number of entries. */
 #define spn_PRIVATE_IP_FRWRD_TABLE_SIZE  "private_ip_frwrd_table_size"
 
 /* The size of direct access DB in number of entries. */
 #define spn_PMF_KAPS_LARGE_DB_SIZE  "pmf_kaps_large_db_size"
 /*
  * Enable BFD over IPv6 support.
  * 0 : Disable
  * 1 : BFD IPV6 enabled with UC support
  * 2 : BFD IPV6 enabled without UC support
  */
 #define spn_BFD_IPV6_ENABLE  "bfd_ipv6_enable"
 
 /* BFD over IPv6 trap port. */
 #define spn_BFD_IPV6_TRAP_PORT  "bfd_ipv6_trap_port"
 /*
  * HW journal working mode. Allowed values: 0-2.
  * 0 : Disabled
  * 1 : Commit After Each Api
  * 2 : Commit Upon User Request
  */
 #define spn_HA_HW_JOURNAL_MODE  "ha_hw_journal_mode"
 
 /* HW Journal Size. */
 #define spn_HA_HW_JOURNAL_SIZE  "ha_hw_journal_size"
 
 /* Enable configuring of SIP for BFD over IPv4. */
 #define spn_BFD_EXTENDED_IPV4_SRC_IP  "bfd_extended_ipv4_src_ip"
 
 /* Configuring maximum slow rate level, options are LOW/NORMAL/HIGH  */
 #define spn_SLOW_MAX_RATE_LEVEL  "slow_max_rate_level"
 /*
  * Specifies the master keys for TCAM_PARTITION_ACL_L2IP4
  * Acceptable values:
  * 0 -- The default value, use the original master key
  * 1 -- Use the new master key, some qualifiers may be
  * different with the original master key(i.e. OuterVlan,
  * SGLP ,DGLP, EtherType and so on), more lookup status
  * are supported
  */
 #define spn_EXT_L2IP4_ACL_TABLE_MASTER_KEY_TYPE  "ext_l2ip4_acl_table_master_key_type"
 /*
  * Specifies the master keys for TCAM_PARTITION_ACL_L2IP6
  * Acceptable values:
  * 0 -- The default value, use the original master key
  * 1 -- Use the new master key, some qualifiers may be
  * different with the original master key(i.e. EtherType,
  * SGLP, DGLP, IP6FlowLable and so on), more lookup status
  * are supported
  */
 #define spn_EXT_L2IP6_ACL_TABLE_MASTER_KEY_TYPE  "ext_l2ip6_acl_table_master_key_type"
 /*
  * Indicates the maximum number of RIF ids can be allocated 
  * in the EEDB bank entries. 
  * valid range 0- 32*1024-1.
  */
 #define spn_RIF_ID_MAX  "rif_id_max"
 
 /* Indicates if defragment of Inlif table is enabled.  */
 #define spn_INLIF_TABLE_DEFRAG_ENABLE  "inlif_table_defrag_enable"
 
 /* Indicates if defragment of EEDB table is enabled.  */
 #define spn_EEDB_DEFRAG_ENABLE  "eedb_defrag_enable"
 
 /* Option to enable/disable VXLAN VDC support */
 #define spn_BCM886XX_VXLAN_VPN_LOOKUP_MODE  "bcm886xx_vxlan_vpn_lookup_mode"
 
 /* Option to enable/disable L2GRE VDC support */
 #define spn_BCM886XX_L2GRE_VPN_LOOKUP_MODE  "bcm886xx_l2gre_vpn_lookup_mode"
 
 
 /* Enable EVPN application */
 #define spn_EVPN_ENABLE  "evpn_enable"
 
 /* Enable three label encapsulation over ROO */
 #define spn_ROO_EXTENSION_LABEL_ENCAPSULATION  "roo_extension_label_encapsulation"
 
 /* If set, never add the PPH learn extension (unless explictly required in FP action).  */
 #define spn_BCM886XX_PPH_LEARN_EXTENSION_DISABLE  "bcm886xx_pph_learn_extension_disable"
 
 /* If True, the parsing indicates if it is the first fragment (if fragmented) of the IP packet. If False, the parsing indicates whether the IP packet is fragmented. */
 #define spn_FIELD_IP_FIRST_FRAGMENT_PARSED  "field_ip_first_fragment_parsed"
 
 /* Number of ETH_LM_DM sessions */
 #define spn_ETH_LM_DM_NUM_SESSIONS  "eth_lm_dm_num_sessions"
 
 /* ETH_LM_DM cosq */
 #define spn_ETH_LM_DM_COSQ  "eth_lm_dm_cosq"
 
 /* In FCoE, NPV switch, if true, packets that ingress from the N_PORT are treated as bridge and packets that ingress from the NP_PORT are treated as router */
 #define spn_FCOE_NPV_BRIDGE_MODE  "fcoe_npv_bridge_mode"
 
 /* Link delay for 10 MbE port (ns) */
 #define spn_LINK_DELAY_10MBE_NS  "link_delay_10mbe_ns"
 
 /* Link delay for 100 MbE port (ns) */
 #define spn_LINK_DELAY_100MBE_NS  "link_delay_100mbe_ns"
 
 /* Link delay for 1 GbE port (ns) */
 #define spn_LINK_DELAY_1GBE_NS  "link_delay_1gbe_ns"
 
 /* Link delay for 2.5 GbE port (ns) */
 #define spn_LINK_DELAY_2_5GBE_NS  "link_delay_2_5gbe_ns"
 
 /* Link delay for 10 GbE port (ns) */
 #define spn_LINK_DELAY_10GBE_NS  "link_delay_10gbe_ns"
 
 /* Link delay for 25 GbE port (ns) */
 #define spn_LINK_DELAY_25GBE_NS  "link_delay_25gbe_ns"
 
 /* Link delay for 40 GbE port (ns) */
 #define spn_LINK_DELAY_40GBE_NS  "link_delay_40gbe_ns"
 
 /* Link delay for 50 GbE port (ns) */
 #define spn_LINK_DELAY_50GBE_NS  "link_delay_50gbe_ns"
 
 /* Link delay for 100 GbE port (ns) */
 #define spn_LINK_DELAY_100GBE_NS  "link_delay_100gbe_ns"
 
 /* Link delay for otherwise unspecified speed (ns) */
 #define spn_LINK_DELAY_NS  "link_delay_ns"
 
 /* Timestamp osts adjust for 10 MbE port (ns) */
 #define spn_TIMESTAMP_ADJUST_10MBE_NS  "timestamp_adjust_10mbe_ns"
 
 /* Timestamp osts adjust for 100 MbE port (ns) */
 #define spn_TIMESTAMP_ADJUST_100MBE_NS  "timestamp_adjust_100mbe_ns"
 
 /* Timestamp osts adjust for 1 GbE port (ns) */
 #define spn_TIMESTAMP_ADJUST_1GBE_NS  "timestamp_adjust_1gbe_ns"
 
 /* Timestamp osts adjust for 2.5 GbE port (ns) */
 #define spn_TIMESTAMP_ADJUST_2_5GBE_NS  "timestamp_adjust_2_5gbe_ns"
 
 /* Timestamp osts adjust for 10 GbE port (ns) */
 #define spn_TIMESTAMP_ADJUST_10GBE_NS  "timestamp_adjust_10gbe_ns"
 
 /* Timestamp osts adjust for 25 GbE port (ns) */
 #define spn_TIMESTAMP_ADJUST_25GBE_NS  "timestamp_adjust_25gbe_ns"
 
 /* Timestamp osts adjust for 50 GbE port (ns) */
 #define spn_TIMESTAMP_ADJUST_50GBE_NS  "timestamp_adjust_50gbe_ns"
 
 /* Timestamp osts adjust for 40 GbE port (ns) */
 #define spn_TIMESTAMP_ADJUST_40GBE_NS  "timestamp_adjust_40gbe_ns"
 
 /* Timestamp osts adjust for 100 GbE port (ns) */
 #define spn_TIMESTAMP_ADJUST_100GBE_NS  "timestamp_adjust_100gbe_ns"
 
 /* Timestamp osts adjust for otherwise unspecified speed (ns) */
 #define spn_TIMESTAMP_ADJUST_NS  "timestamp_adjust_ns"
 
 /* Timestamp tsts adjust for 10 MbE port (ns) */
 #define spn_TIMESTAMP_TSTS_ADJUST_10MBE_NS  "timestamp_tsts_adjust_10mbe_ns"
 
 /* Timestamp tsts adjust osts for 100 MbE port (ns) */
 #define spn_TIMESTAMP_TSTS_ADJUST_100MBE_NS  "timestamp_tsts_adjust_100mbe_ns"
 
 /* Timestamp tsts adjust for 1 GbE port (ns) */
 #define spn_TIMESTAMP_TSTS_ADJUST_1GBE_NS  "timestamp_tsts_adjust_1gbe_ns"
 
 /* Timestamp tsts adjust for 2.5 GbE port (ns) */
 #define spn_TIMESTAMP_TSTS_ADJUST_2_5GBE_NS  "timestamp_tsts_adjust_2_5gbe_ns"
 
 /* Timestamp tsts adjust for 10 GbE port (ns) */
 #define spn_TIMESTAMP_TSTS_ADJUST_10GBE_NS  "timestamp_tsts_adjust_10gbe_ns"
 
 /* Timestamp tsts adjust for 25 GbE port (ns) */
 #define spn_TIMESTAMP_TSTS_ADJUST_25GBE_NS  "timestamp_tsts_adjust_25gbe_ns"
 
 /* Timestamp tsts adjust for 50 GbE port (ns) */
 #define spn_TIMESTAMP_TSTS_ADJUST_50GBE_NS  "timestamp_tsts_adjust_50gbe_ns"
 
 /* Timestamp tsts adjust for 40 GbE port (ns) */
 #define spn_TIMESTAMP_TSTS_ADJUST_40GBE_NS  "timestamp_tsts_adjust_40gbe_ns"
 
 /* Timestamp tsts adjust for 100 GbE port (ns) */
 #define spn_TIMESTAMP_TSTS_ADJUST_100GBE_NS  "timestamp_tsts_adjust_100gbe_ns"
 
 /* Timestamp tsts adjust for otherwise unspecified speed (ns) */
 #define spn_TIMESTAMP_TSTS_ADJUST_NS  "timestamp_tsts_adjust_ns"
 /*
  * Indicates the maximum speed that any port can be 
  * set to in a device. On TD2+ port_flex_speed_max_x 
  * and port_flex_speed_max_y may be used to specify 
  * per pipe. They default to -1 if undefined and 
  * port_flex_speed_max is used instead.
  */
 #define spn_PORT_FLEX_SPEED_MAX  "port_flex_speed_max"
 /*
  * IPMC source specific lookup for bridged packets 
  *  0 - disable 
  *  1 - enable using TCAM 
  *  2 - enable using KAPS 
  *  3 - enable using ELK 
  */
 #define spn_IPMC_L2_SSM_MODE  "ipmc_l2_ssm_mode"
 
 /* Enable SAT for Saber2 device. If SAT is enabled, Saber2 port 5 is reserved automatically. */
 #define spn_SAT_ENABLE  "sat_enable"
 
 /* Per trunk multicast replication mode */
 #define spn_MULTICAST_PER_TRUNK_REPLICATION  "multicast_per_trunk_replication"
 
 /* DDR interface signal AD VDL control register */
 #define spn_DDR3_TUNE_CTRL_VDL_AD00  "ddr3_tune_ctrl_vdl_ad00"
 
 /* DDR interface signal AD VDL control register */
 #define spn_DDR3_TUNE_CTRL_VDL_AD04  "ddr3_tune_ctrl_vdl_ad04"
 
 /* DDR interface signal AD VDL control register */
 #define spn_DDR3_TUNE_CTRL_VDL_AD08  "ddr3_tune_ctrl_vdl_ad08"
 
 /* DDR interface signal AD VDL control register */
 #define spn_DDR3_TUNE_CTRL_VDL_AD12  "ddr3_tune_ctrl_vdl_ad12"
 
 /* DDR interface signal BA VDL control register */
 #define spn_DDR3_TUNE_CTRL_VDL_BA  "ddr3_tune_ctrl_vdl_ba"
 
 /* DDR interface signal AUX VDL control register */
 #define spn_DDR3_TUNE_CTRL_VDL_AUX  "ddr3_tune_ctrl_vdl_aux"
 
 /* DDR interface signal CS VDL control register */
 #define spn_DDR3_TUNE_CTRL_VDL_CS  "ddr3_tune_ctrl_vdl_cs"
 
 /* DDR interface signal PAR VDL control register */
 #define spn_DDR3_TUNE_CTRL_VDL_PAR  "ddr3_tune_ctrl_vdl_par"
 
 /* DDR interface signal RAS_N VDL control register */
 #define spn_DDR3_TUNE_CTRL_VDL_RAS_N  "ddr3_tune_ctrl_vdl_ras_n"
 
 /* DDR interface signal CAS_N VDL control register */
 #define spn_DDR3_TUNE_CTRL_VDL_CAS_N  "ddr3_tune_ctrl_vdl_cas_n"
 
 /* DDR interface signal CKE0 VDL control register */
 #define spn_DDR3_TUNE_CTRL_VDL_CKE  "ddr3_tune_ctrl_vdl_cke"
 
 /* DDR interface signal RST_N VDL control register */
 #define spn_DDR3_TUNE_CTRL_VDL_RST_N  "ddr3_tune_ctrl_vdl_rst_n"
 
 /* DDR interface signal ODT0 VDL control register */
 #define spn_DDR3_TUNE_CTRL_VDL_ODT  "ddr3_tune_ctrl_vdl_odt"
 
 /* DDR interface signal WEN_N VDL control register */
 #define spn_DDR3_TUNE_CTRL_VDL_WE_N  "ddr3_tune_ctrl_vdl_we_n"
 
 /* VREF DAC Control register */
 #define spn_DDR3_TUNE_CTRL_VREF_DAC  "ddr3_tune_ctrl_vref_dac"
 
 /* Write channel DQS VDL control register */
 #define spn_DDR3_TUNE_WR_VDL_DQSP  "ddr3_tune_wr_vdl_dqsp"
 
 /* Write channel DQS VDL control register */
 #define spn_DDR3_TUNE_WR_VDL_DQSN  "ddr3_tune_wr_vdl_dqsn"
 
 /* Write channel DQ VDL control register */
 #define spn_DDR3_TUNE_WR_VDL_DQ0_BL0  "ddr3_tune_wr_vdl_dq0_bl0"
 
 /* Write channel DQ VDL control register */
 #define spn_DDR3_TUNE_WR_VDL_DQ4_BL0  "ddr3_tune_wr_vdl_dq4_bl0"
 
 /* Write channel DQ VDL control register */
 #define spn_DDR3_TUNE_WR_VDL_DQ0_BL1  "ddr3_tune_wr_vdl_dq0_bl1"
 
 /* Write channel DQ VDL control register */
 #define spn_DDR3_TUNE_WR_VDL_DQ4_BL1  "ddr3_tune_wr_vdl_dq4_bl1"
 
 /* Write channel DQ VDL control register */
 #define spn_DDR3_TUNE_WR_VDL_DQ0_BL2  "ddr3_tune_wr_vdl_dq0_bl2"
 
 /* Write channel DQ VDL control register */
 #define spn_DDR3_TUNE_WR_VDL_DQ4_BL2  "ddr3_tune_wr_vdl_dq4_bl2"
 
 /* Write channel DQ VDL control register */
 #define spn_DDR3_TUNE_WR_VDL_DQ0_BL3  "ddr3_tune_wr_vdl_dq0_bl3"
 
 /* Write channel DQ VDL control register */
 #define spn_DDR3_TUNE_WR_VDL_DQ4_BL3  "ddr3_tune_wr_vdl_dq4_bl3"
 
 /* Write channel DM VDL control register */
 #define spn_DDR3_TUNE_WR_VDL_DM  "ddr3_tune_wr_vdl_dm"
 
 /* Write channel EDC VDL control register */
 #define spn_DDR3_TUNE_WR_VDL_EDC  "ddr3_tune_wr_vdl_edc"
 
 /* Write leveling bit-clock cycle delay control register */
 #define spn_DDR3_TUNE_WR_CHAN_DLY_CYC  "ddr3_tune_wr_chan_dly_cyc"
 
 /* Read channel DQSP VDL control register */
 #define spn_DDR3_TUNE_RD_VDL_DQSP  "ddr3_tune_rd_vdl_dqsp"
 
 /* Read channel DQSN VDL control register */
 #define spn_DDR3_TUNE_RD_VDL_DQSN  "ddr3_tune_rd_vdl_dqsn"
 
 /* Read channel DQ0-P VDL control register */
 #define spn_DDR3_TUNE_RD_VDL_DQP0_BL0  "ddr3_tune_rd_vdl_dqp0_bl0"
 
 /* Read channel DQ0-P VDL control register */
 #define spn_DDR3_TUNE_RD_VDL_DQP4_BL0  "ddr3_tune_rd_vdl_dqp4_bl0"
 
 /* Read channel DQ0-P VDL control register */
 #define spn_DDR3_TUNE_RD_VDL_DQP0_BL1  "ddr3_tune_rd_vdl_dqp0_bl1"
 
 /* Read channel DQ0-P VDL control register */
 #define spn_DDR3_TUNE_RD_VDL_DQP4_BL1  "ddr3_tune_rd_vdl_dqp4_bl1"
 
 /* Read channel DQ0-P VDL control register */
 #define spn_DDR3_TUNE_RD_VDL_DQP0_BL2  "ddr3_tune_rd_vdl_dqp0_bl2"
 
 /* Read channel DQ0-P VDL control register */
 #define spn_DDR3_TUNE_RD_VDL_DQP4_BL2  "ddr3_tune_rd_vdl_dqp4_bl2"
 
 /* Read channel DQ0-P VDL control register */
 #define spn_DDR3_TUNE_RD_VDL_DQP0_BL3  "ddr3_tune_rd_vdl_dqp0_bl3"
 
 /* Read channel DQ0-P VDL control register */
 #define spn_DDR3_TUNE_RD_VDL_DQP4_BL3  "ddr3_tune_rd_vdl_dqp4_bl3"
 
 /* Read channel DQ0-N VDL control register */
 #define spn_DDR3_TUNE_RD_VDL_DQN0_BL0  "ddr3_tune_rd_vdl_dqn0_bl0"
 
 /* Read channel DQ0-N VDL control register */
 #define spn_DDR3_TUNE_RD_VDL_DQN4_BL0  "ddr3_tune_rd_vdl_dqn4_bl0"
 
 /* Read channel DQ0-N VDL control register */
 #define spn_DDR3_TUNE_RD_VDL_DQN0_BL1  "ddr3_tune_rd_vdl_dqn0_bl1"
 
 /* Read channel DQ0-N VDL control register */
 #define spn_DDR3_TUNE_RD_VDL_DQN4_BL1  "ddr3_tune_rd_vdl_dqn4_bl1"
 
 /* Read channel DQ0-N VDL control register */
 #define spn_DDR3_TUNE_RD_VDL_DQN0_BL2  "ddr3_tune_rd_vdl_dqn0_bl2"
 
 /* Read channel DQ0-N VDL control register */
 #define spn_DDR3_TUNE_RD_VDL_DQN4_BL2  "ddr3_tune_rd_vdl_dqn4_bl2"
 
 /* Read channel DQ0-N VDL control register */
 #define spn_DDR3_TUNE_RD_VDL_DQN0_BL3  "ddr3_tune_rd_vdl_dqn0_bl3"
 
 /* Read channel DQ0-N VDL control register */
 #define spn_DDR3_TUNE_RD_VDL_DQN4_BL3  "ddr3_tune_rd_vdl_dqn4_bl3"
 
 /* Read channel DM-P VDL control register */
 #define spn_DDR3_TUNE_RD_VDL_DMP  "ddr3_tune_rd_vdl_dmp"
 
 /* Read channel DM-N VDL control register */
 #define spn_DDR3_TUNE_RD_VDL_DMN  "ddr3_tune_rd_vdl_dmn"
 
 /* Read channel CS_N[0] read enable VDL control register */
 #define spn_DDR3_TUNE_RD_EN_VDL_CS0  "ddr3_tune_rd_en_vdl_cs0"
 
 /* Read channel CS_N[1] read enable VDL control register (used for reads when only cs1_n is active) */
 #define spn_DDR3_TUNE_RD_EN_VDL_CS1  "ddr3_tune_rd_en_vdl_cs1"
 
 /* Read enable bit-clock cycle delay control register */
 #define spn_DDR3_TUNE_RD_EN_DLY_CYC  "ddr3_tune_rd_en_dly_cyc"
 
 /* Read channel datapath control register */
 #define spn_DDR3_TUNE_RD_CONTROL  "ddr3_tune_rd_control"
 /*
  * If set, For ingress-MC, trunk-id should be specified as destination.
  * If unset, when a trunk MC destinations is wanted for ingress-MC, The destinations are specified by listing all trunk member-ports as MC destinations.
  * In this case, pruning is applied by the HW to ensure that a single replica is egressed for a trunk destination.
  * for BCM88650 seting this feature will in effect disable using egress MC with trunk destinations
  * for BCM88660 and above seting this feature will NOT cause such an effect
  * Default value for BCM88650 is 0 (unset), for BCM88660 and higher is 1 (set)
  */
 #define spn_USE_TRUNK_AS_INGRESS_MC_DESTINATION  "use_trunk_as_ingress_mc_destination"
 /*
  * Indicate Raw data collection or Processed Stats collection mode for BHH LM/DM
  * Set to 1 for Processed stats collection
  * Set to 2 for Raw data collection
  */
 #define spn_BHH_DATA_COLLECTION_MODE  "bhh_data_collection_mode"
 /*
  * Indicate Raw data collection or Processed Stats collection mode for MPLS LM/DM
  * Set to 1 for Processed stats collection
  * Set to 2 for Raw data collection
  */
 #define spn_MPLS_LMDM_DATA_COLLECTION_MODE  "mpls_lmdm_data_collection_mode"
 /*
  * Indicate Raw data collection or Processed Stats collection mode for Ethernet LM/DM
  * Set to 1 for Processed stats collection
  * Set to 2 for Raw data collection
  */
 #define spn_ETH_LMDM_DATA_COLLECTION_MODE  "eth_lmdm_data_collection_mode"
 /*
  * Indicate the number of buffers allocated for collecting the BHH Raw samples in SDK
  * Range is 2 to 8. Default is 4
  */
 #define spn_BHH_PM_RAW_DATA_BUFFERS  "bhh_pm_raw_data_buffers"
 /*
  * Indicate the number of buffers allocated for collecting the MPLS LM/DM Raw samples in SDK
  * Range is 2 to 8. Default is 4
  */
 #define spn_MPLS_LMDM_PM_RAW_DATA_BUFFERS  "mpls_lmdm_pm_raw_data_buffers"
 /*
  * Indicate the number of buffers allocated for collecting the Ethernet LM/DM Raw samples in SDK
  * Range is 2 to 8. Default is 4
  */
 #define spn_ETH_LMDM_PM_RAW_DATA_BUFFERS  "eth_lmdm_pm_raw_data_buffers"
 /*
  * Soc property to control optimization. The specific optimization is
  * indicated by suffix: runtime_performance_optimize_enable<_suffix>
  * and is set to either 1 or 0.
  * List of suffixes (currently only one):
  *   sched_allocation
  *     Soc property to control time optimization of execution time of
  *     port setup operations (e.g., bcm_cosq_gport_sched_set()).
  *     Activation of this option results in requiring about 58 Mbytes of
  *     memory per unit.
  * Example:
  *   runtime_performance_optimize_enable_sched_allocation.BCM88675=1
  */
 #define spn_RUNTIME_PERFORMANCE_OPTIMIZE_ENABLE  "runtime_performance_optimize_enable"
 /*
  * Indicates that the port module(macro) on which this physical port resides
  * is flex enable or not.
  * For BCM56860 based devices, the following applies:
  * This property is per port macro. For port macros consisting of multiple
  * smaller port macros, enabling flex on that port macro also enables
  * flex on the smaller port macros.
  * port_flex_enable{physical port number}=1 or 0
  *  Valid values are 0 or 1. Default value is 0.
  * The given physical port number has to be the first physical port residing
  * on the port macro.
  */
 #define spn_PORT_FLEX_ENABLE  "port_flex_enable"
 /*
  * Indicates the maximum number of ports that the core could flex to.
  * port_flex_max_ports{core number or physical port number}=1, 2 or 4
  * Valid values are 1, 2 or 4. Default value is 4.
  * The given physical port number has to be the first physical port residing
  * on the port macro.
  */
 #define spn_PORT_FLEX_MAX_PORTS  "port_flex_max_ports"
 /*
  * BCM5696X :
  * 0 => Disable support for Ethernet to HiGig2 transformation
  * 1 => Enable support for Ethernet to HiGig2 transformation
  * Ethernet to HiGig2 transformation involves two steps
  * - Encapsulation change from IEEE to HiGig2 and
  * - Port speed change from Ethernet port speeds to HiGig2 port speeds
  * When fabric_port_enable=0, encapsulation changes are still permitted,
  * but Ethernet to HiGig2 speed change is disallowed.
  * If the initial portmap contains HiGig2 ports then fabric_port_enable config is ignored
  */
 #define spn_FABRIC_PORT_ENABLE  "fabric_port_enable"
 /*
  * This SOC property is used to map any lanes of a PHY to any physical port of a switch. This SOC property is per port
  * This should be set to 0x0 (default) if user does not want to specify any lane mask for a switch port.
  * This should be set to 0xF if user wants to map 4 lanes from lane 0 (0 - 3) of a PHY to a switch port.
  * This should be set to 0xF0 if user wants to map 4 lanes from lane 4 (4 - 7) of a PHY to a switch port.
  * This should be set to 0xF00 if user wants to map 4 lanes from lane 8 (8 - 11) of a PHY to a switch port.
  * This should be set to 0x33 if user wants to map 4 different lanes (0, 1, 4 and 5) of a PHY to a switch port.
  * This should be set to 0x590 if user wants to map 4 different lanes (4, 7, 8 and 10) of a PHY to a switch port.
  */
 #define spn_PORT_PHY_LANE_MASK  "port_phy_lane_mask"
 
 /* Setting this property to 1 enables the gearbox data path mode on select PHY devices. */
 #define spn_PHY_GEARBOX_ENABLE  "phy_gearbox_enable"
 
 /* Setting this property to 1 enables backward pin-compatibility on select PHY devices. */
 #define spn_PHY_PIN_COMPATIBILITY_ENABLE  "phy_pin_compatibility_enable"
 /*
  * This SOC property is used to select the auto-negotiation master lane for a port.
  * The auto-negotiation master lane selection should be done by the user prior to enabling auto-negotiation.
  */
 #define spn_PHY_AUTONEG_MASTER_LANE  "phy_autoneg_master_lane"
 /*
  * There are various Hurricane3 SKU options defined in the datasheet.
  * These SKU options determine initial port configurations.
  * This SOC property is used to specify the SKU option.
  * i.e. bcm5616x_init_port_config = <sku option>.
  * Default value is 1. 
  * The value will be valid when the SKU option is defined in the datasheet.
  * Furthermore, Serdes interface of QTC blocks in Hurricane3 can be selected as QSGMII or SGMII mode
  * via bcm5616x_init_port_config_qtc<# of QTC, 0-1> = <QSGMII/SGMII> 
  * Default string is QSGMII.
  * Valid strings are QSGMII and SGMII. 
  * The TSC configuration also can be configured of SKUs, 56163 and 53443,
  * via bcm5616x_init_port_config_tsc<# of TSC, 0-1> = <SINGLE/XAUI>
  * SINGLE: Initialize 4 GE/XE ports in TSCx.
  * XAUI: Initialize 1 XAUI port in TSCx.
  */
 #define spn_BCM5616X_INIT_PORT_CONFIG  "bcm5616x_init_port_config"
 /*
  * External TCAM result size, allows to modify each external tcam result size. The total size of the external result should not be changed.
  * The size of each segment updates the corresponding qualifier bcmFieldQualifyExternalValue#. Default values according to the device property.
  */
 #define spn_EXT_TCAM_RESULT_SIZE_SEGMENT  "ext_tcam_result_size_segment"
 /*
  * BCM56450 :
  * 0 => LinkPHY is disabled at init time for the ports in port bitmap represented by existing SOC property "pbmp_linkphy".
  * 1 => LinkPHY is enabled at init time for the ports in port bitmap represented by existing SOC property "pbmp_linkphy".
  */
 #define spn_LINKPHY_ENABLE  "linkphy_enable"
 /*
  * This soc property is used to direct ILKN interface to fabric links (only relevant for ILKN in PML1).
  * When enabled, all 16 dedicated fabric links cannot be used for fabric connection.
  * 0 => Disable. ILKN PML1 will be directed to NIF serdes
  * 1 => Enable. ILKN PML1 will be directed to fabric serdes
  */
 #define spn_USE_FABRIC_LINKS_FOR_ILKN_NIF  "use_fabric_links_for_ilkn_nif"
 /*
  * This soc property is used to enable enhanced SER correction event report mechanism
  * (i.e. parity correction/ECC 1-bit correction/ECC 2-bit correction event are identified).
  * 0 => Use the traditional SER correction event report mechanism:
  * Report event with SOC_SWITCH_EVENT_DATA_ERROR_CORRECTED type for both parity and ECC error correction(including 1-bit and 2-bit).
  * 1 => Use enhanced SER correction event report mechanism:
  * Report event with SOC_SWITCH_EVENT_DATA_ERROR_ECC_1BIT_CORRECTED type for ECC 1-bit error correction.
  * Report event with SOC_SWITCH_EVENT_DATA_ERROR_ECC_2BIT_CORRECTED type for ECC 2-bit error correction.
  * Report event with SOC_SWITCH_EVENT_DATA_ERROR_PARITY_CORRECTED type for parity error correction.
  */
 #define spn_ENHANCED_SER_CORRECTION_EVENT_REPORT  "enhanced_ser_correction_event_report"
 
 /* DPP clock ratio applied to switch chip, any unsupported ratio will be ignored */
 #define spn_DPP_CLOCK_RATIO  "dpp_clock_ratio"
 /*
  * Select either trunk or higig trunk that supports DLB
  * 0: higig trunk
  * 1: trunk
  */
 #define spn_DLB_HGT_LAG_SELECTION  "dlb_hgt_lag_selection"
 /*
  * This soc property is used to enable whether overwrite the speed when the new speed/interface is same as current
  * 0 => Overwrite the speed no matter the new spseed and interface
  * 1 => Do not overwrite the speed if the new speed/interface is same as current
  */
 #define spn_SAME_SPEED_INTF_DO_NOT_OVERWRITE  "same_speed_intf_do_not_overwrite"
 /*
  * TRUE => Support
  *   a. Changing service queue configuration with traffic.
  *   b. Allows multiple SERVICE_QUEUE_MAP table entries can share same egress
  *      Service Queue Group.
  * 
  * FALSE => Default Setting
  * 
  * Note: Hw limites number of port profile indexes to be 8. i.e. Max 8 unique
  *       combination of PORT_OFFSETS can be mapped. However, due to software
  *       use of memory profile indexing, one of these profile is used as a work
  *       entry. Thus we are limite to maximum of 7 unique port profiles.
  */
 #define spn_SERVICE_QUEUE_DYNAMIC_CONFIG  "service_queue_dynamic_config"
 /*
  * Soc property to skip enabling of parity/ecc per memory. The specific memory 
  * to be skipped is indicated by table name: mem_parity_enable_skip_table_name
  * Example: mem_parity_enable_skip_VLAN_TAB=1
  */
 #define spn_MEM_PARITY_ENABLE_SKIP  "mem_parity_enable_skip"
 /*
  * Enable/Disable BHH LM/DM processing on 5664x.
  * If 0, BHH LM/DM feature is disabled.
  * If 1,  BHH LM/DM feature is enabled, reserves UDF objects for internal use.
  */
 #define spn_BHH_LM_DM_ENABLE  "bhh_lm_dm_enable"
 /*
  * Use udf/field API for BHH LM/DM UDF reservation on 5664x.
  * If 0, use bcm_field_xxx to reserve UDF for BHH LM/DM.
  * If 1, use bcm_udf_xxx to reserve UDF for BHH LM/DM.
  */
 #define spn_BHH_UDF_MODE  "bhh_udf_mode"
 /*
  * This soc property is used to set ILKN burst max value
  * supported values are 128 and 256
  */
 #define spn_ILKN_BURST_MAX  "ilkn_burst_max"
 /*
  * This soc property is used to set ILKN burst short value
  * value should be a multiplier of 32 and not bigger than ilkn_burst_max /2
  */
 #define spn_ILKN_BURST_SHORT  "ilkn_burst_short"
 /*
  * This soc property is used to enable mapping of many system ports to a single destination (modport)
  * Relevant only in DIRECT mapping mode
  * value should be 0 or 1
  */
 #define spn_HQOS_MAPPING_ENABLE  "hqos_mapping_enable"
 /*
  * Set the debug buffer polling interval in uSec for Broadsync.
  * Default being 1000 uSec.
  */
 #define spn_BS_POLL_INTERVAL  "bs_poll_interval"
 /*
  * Get 1588 timestamps from HW register or SW FIFO.
  * If 1(default), timestamps are controlled by
  * soc_feature_timestamp_counter and timestamps
  * are obtained from SW FIFO.
  * If 0, get timestamps directly from HW register.
  */
 #define spn_SW_TIMESTAMP_FIFO_ENABLE  "sw_timestamp_fifo_enable"
 /*
  * Specifies the boot master and chip master ports of a MT2 quad if the defaults are unacceptable.
  * If the defaults are valid this config should not be set. The default boot master ports are 0 and 4
  * of a MT2 chip and the default chip master port is 0.
  * To indicate that a ports is only a boot master use phy_boot_master_<p>=1 .
  * To indicate that a ports is a boot master and a chip master use phy_boot_master_<p>=1:c .
  * There should be only one boot master per quad and one chip master per chip which should also be a 
  * bootmaster.
  */
 #define spn_PHY_BOOT_MASTER  "phy_boot_master"
 /*
  * Specifies the Logical Port that corresponds to the MT2 PHY that does the,
  * public to provate MDIO transaction copying. Setting this config variable is mandatory
  * for the proper operation of a MT2 system. A value of -1 means download to every chip.
  * A value of -2 means download once per every bus. The first chip on each bus should be wired for 
  * copying from pbulic to private bus and all the chips on that bus should be chained via the private bus.
  */
 #define spn_MDIO_FIRMWARE_DOWNLOAD_MASTER  "mdio_firmware_download_master"
 /*
  * Enable support for packet DMA descriptor prefetch mode.
  * This feature enables descriptors contiguous in memory
  * to be prefetched and thus increase packet dma throughput.
  * This feature is specific to cmicx based devices.
  */
 #define spn_PDMA_DESCRIPTOR_PREFETCH_ENABLE  "pdma_descriptor_prefetch_enable"
 
 /* Configure the given preemphasis value for applicable external phy devices. */
 #define spn_PHY_PREEMPHASIS  "phy_preemphasis"
 
 /* Configure the given driver current value for applicable external phy devices. */
 #define spn_PHY_DRIVER_CURRENT  "phy_driver_current"
 /*
  * Set the Extra Ancillary Bandwidth mode (bcm56850)
  * Valid values:
  * 0 = Regular mode(default)
  * 1 = Extra-CPU-Bandwidth mode
  * 1 = Extra-LOOPBACK-Bandwidth mode(reserved)
  * 3 = Extra-CPU-LOOPBACK-Bandwidth mode(reserved)
  */
 #define spn_ANCILLARY_BANDWIDTH_MODE  "ancillary_bandwidth_mode"
 /*
  * Configure allocation mode of overlay egress L3 interface.
  * Valid values:
  * 0 = allocate from low portion (default)
  * 1 = allocate from high portion
  */
 #define spn_RIOT_OVERLAY_L3_INTF_MEM_ALLOC_MODE  "riot_overlay_l3_intf_mem_alloc_mode"
 /*
  * Configure allocation mode of overlay egress object.
  * Valid values:
  * 0 = allocate from low portion (default)
  * 1 = allocate from high portion
  */
 #define spn_RIOT_OVERLAY_L3_EGRESS_MEM_ALLOC_MODE  "riot_overlay_l3_egress_mem_alloc_mode"
 /*
  * The config property used to override default reservation of split horizon groups.
  * By default the access side ports of L2 tunneling applications are part of split horizon group 0.
  * Starting from BCM5656x family of devices by default the network side ports of L2 tunneling
  * applications are part of split horizon group 1.
  * The valid values for the config variable are 0 and 1.
  * 0 => Indicates the default behaviour;
  * Application cannot configure prune properties on reserved split horizon groups
  * 1 => Indicates that no split horizon groups will be reserved by default.
  * Application can configure the prune properties of all the groups.
  * Also in this mode, the application must specify a valid split-horizon group
  * while adding ports to various virtual port applications.
  */
 #define spn_USE_ALL_SPLITHORIZON_GROUPS  "use_all_splithorizon_groups"
 /*
  * This will be used to specify starting endpoint ID for BHH protocol on FP based OAM devices
  * Default is 512
  */
 #define spn_BHH_BASE_ENDPOINT_ID  "bhh_base_endpoint_id"
 /*
  * This will be used to specify starting OAM group ID for BHH protocol on FP based OAM devices
  * Default is 256
  */
 #define spn_BHH_BASE_GROUP_ID  "bhh_base_group_id"
 /*
  * This per-physical port property is used to specify the mode-lane configuration.
  * For BCM56860 based devices,
  * Each nibble-index is the TSC lane number (0..11) and
  * the nibble value is the 100GE port lane number(0..9).
  * A nibble value of "f" indicates the TSC lane is not used.
  * Supported 100GE lane distributions:
  * - TSC 100g 4-4-2 mode:  phy_mld_map{x} = 0xff9876543210
  * - TSC 100g 3-4-3 mode:  phy_mld_map{x} = 0xf9876543f210
  * - TSC 100g 2-4-4 mode:  phy_mld_map{x} = 0x98765432ff10
  */
 #define spn_PHY_MLD_MAP  "phy_mld_map"
 /*
  * This per-physical port property specifies the master core number
  * that is used for autonegotiation.
  *  Valid values are 0, 1, 2.
  */
 #define spn_PHY_AN_CORE_NUM  "phy_an_core_num"
 /*
  * This will be used to specify warmboot scache size needed for field module
  * Default value is 0
  */
 #define spn_FIELD_SCACHE_SIZE  "field_scache_size"
 /*
  * This will be used to specify compression feature enable/disable for Tomahawk IFP
  * Default value is 1 which means enabled.
  */
 #define spn_FP_COMPRESSION_ENABLE  "fp_compression_enable"
 /*
  * The max length in bytes of a BHH PDU's encapsulation
  * Default value is 76 which includes OLP Tx header(34) + L2 header(22) + 4 MPLS labels (16) + ACH header(4).
  */
 #define spn_BHH_ENCAP_MAX_LENGTH  "bhh_encap_max_length"
 /*
  * Configure the default invalid value for egress mpls labels
  * Valid values:
  * 0 - 1048575
  */
 #define spn_MPLS_ENCAP_INVALID_VALUE  "mpls_encap_invalid_value"
 
 /* Enable MPLS egress encapsulation switch and push actions on same OutLif */
 #define spn_MPLS_ENCAPSULATION_ACTION_SWAP_OR_PUSH_ENABLE  "mpls_encapsulation_action_swap_or_push_enable"
 
 /* Enable VPWS tagged mode termination */
 #define spn_VPWS_TAGGED_MODE  "vpws_tagged_mode"
 /*
  * In case of an IPv4 MC packet with IPMC disable allows a per RIF program selection
  * instead of global RIF setting using the bcmSwitchL3McastL2 switch control.
  * 0 = Disable
  * 1 = Enable
  */
 #define spn_IPMC_L3MCASTL2_MODE  "ipmc_l3mcastl2_mode"
 /*
  * Egress Membership mode.
  * 0: VSI
  * 1: VLAN
  */
 #define spn_EGRESS_MEMBERSHIP_MODE  "egress_membership_mode"
 /*
  * This soc property is used in vxlan termination according to DIP SIP VRF, using my-vtep-index, 
  * enabled using bcm886xx_vxlan_tunnel_lookup_mode = 3.
  * It defines the number of bits available for VRF 
  * in IP tunnel termination lookup: my-vtep-index, SIP, VRF lookup.
  * Max value is number of VRF in the device.
  * Note that  number of bits for VRFs + number of bits for my-vtep-index must be <= 15.
  */
 #define spn_VXLAN_TUNNEL_TERM_IN_SEM_VRF_NOF_BITS  "vxlan_tunnel_term_in_sem_vrf_nof_bits"
 /*
  * This soc property is used in vxlan termination according to DIP SIP VRF, using my-vtep-index, 
  * enabled using bcm886xx_vxlan_tunnel_lookup_mode = 3.
  * It defines the number of bits available for my-vtep-index 
  * in IP tunnel termination lookup: my-vtep-index, SIP, VRF lookup.
  * Max value is 4.
  * Note that number of bits for VRFs + number of bits for my-vtep-index must be <= 15.
  */
 #define spn_VXLAN_TUNNEL_TERM_IN_SEM_MY_VTEP_INDEX_NOF_BITS  "vxlan_tunnel_term_in_sem_my_vtep_index_nof_bits"
 /*
  * This soc property is used to enable stamping of the DSP-Ext field 
  * in mirror/snooped packets with the system port DSP.
  * FTMH Extension must be enabled.
  * Default value is 0 which means disabled.
  */
 #define spn_MIRROR_STAMP_SYS_ON_DSP_EXT  "mirror_stamp_sys_on_dsp_ext"
 /*
  * This soc property is used to Enable/Disable truncate (IRPP editing) for counter processor
  * Default value is 0 which means disabled.
  */
 #define spn_TRUNCATE_DELTA_IN_PP_COUNTER  "truncate_delta_in_pp_counter"
 /*
  * This soc property is used to enable allocating seperate recycling termination context (in pp port) 
  * for each channel on a channelized interface which should be recycled
  */
 #define spn_RCY_CHANNELIZED_SHARED_CONTEXT_ENABLE  "rcy_channelized_shared_context_enable"
 
 /* Enable MPLS extended encapsulation. */
 #define spn_MPLS_EGRESS_LABEL_EXTENDED_ENCAPSULATION_MODE  "mpls_egress_label_extended_encapsulation_mode"
 /*
  * This soc property defines the number of free DMA Vectors
  * the SOC DMA driver will cache to avoid calling alloc/free routines
  * The value can vary between 32 to 512.
  */
 #define spn_PDMA_DV_FREE_COUNT  "pdma_dv_free_count"
 /*
  * This soc property defines the number of DCBs(dma control blocks)
  * in the DMA vector. the value can vary between 160 to 640.
  * This value has to be greater than pdma_dv_free_count property
  * User has to make sure that enough memory is available to allocate
  * these DCBs.
  */
 #define spn_PDMA_DV_FREE_SIZE  "pdma_dv_free_size"
 
 /* link bonding enable */
 #define spn_LINK_BONDING_ENABLE  "link_bonding_enable"
 /*
  * The size of total ingress data buffer in the OCB for link bonding.
  * Allowed values: 0/2/4/6/8 MB. Default: 8 MBytes.
  */
 #define spn_LB_BUFFER_SIZE  "lb_buffer_size"
 /*
  * The size of one ingress data buffer in the OCB for link bonding.
  * Allowed values: 128/256. Default: 256 Bytes.
  */
 #define spn_LB_INGRESS_BUFFER_SIZE_SINGLE  "lb_ingress_buffer_size_single"
 
 /* Number of FIFO per Modem */
 #define spn_LB_MODEM_FIFO_SIZE  "lb_modem_fifo_size"
 
 /* Number of FIFO per Link Bonding Group */
 #define spn_LB_LBG_FIFO_SIZE  "lb_lbg_fifo_size"
 /*
  * This soc_property is used to enable/disable NIV feature at init time.
  * Example:
  * niv_enable = 1 - NIV will be enabled at init time if the device supports NIV.
  * This is the default value of the config property.
  * niv_enable = 0 - NIV will be disabled at init time if the device supports NIV.
  */
 #define spn_NIV_ENABLE  "niv_enable"
 /*
  * This soc property is used to specify number of Max Groups for CCM EApp
  * Default value is 256.
  */
 #define spn_OAM_CCM_MAX_GROUPS  "oam_ccm_max_groups"
 /*
  * This soc property is used to specify number of Max MEPs for CCM EApp
  * Default value is 256.
  */
 #define spn_OAM_CCM_MAX_MEPS  "oam_ccm_max_meps"
 
 /* External IPv4 double capacity forward table size */
 #define spn_EXT_IP4_DOUBLE_CAPACITY_FWD_TABLE_SIZE  "ext_ip4_double_capacity_fwd_table_size"
 /*
  * This soc_property is used to select a specific route prefix length that can be stored in the LEM.
  * Possible values: 0(disabled)/4/8/12/16/20/24/28.
  */
 #define spn_ENHANCED_FIB_SCALE_PREFIX_LENGTH  "enhanced_fib_scale_prefix_length"
 
 /* Enable OAM features CFM,Y1731 and Y1711  */
 #define spn_OAM_ENABLE  "oam_enable"
 
 /* Enable BFD features */
 #define spn_BFD_ENABLE  "bfd_enable"
 
 /* This soc property is the max number of descriptors in a single chain. */
 #define spn_DMA_DESC_AGGREGATOR_CHAIN_LENGTH_MAX  "dma_desc_aggregator_chain_length_max"
 
 /* This soc property is the total size of the DMA memory double-buffer. */
 #define spn_DMA_DESC_AGGREGATOR_BUFF_SIZE_KB  "dma_desc_aggregator_buff_size_kb"
 
 /* This soc property is the timeout between the creation of a new descriptor chain and its commit to HW. */
 #define spn_DMA_DESC_AGGREGATOR_TIMEOUT_USEC  "dma_desc_aggregator_timeout_usec"
 
 /* This soc property enables descriptor DMA for a specific memory, _MEM suffix. */
 #define spn_DMA_DESC_AGGREGATOR_ENABLE_SPECIFIC  "dma_desc_aggregator_enable_specific"
 
 /* During occurrence of conflicting events - TimeOut and State change, only final event(Either TimeOut (or) State change) will be communicated to SDK. Other events will not be affected by this. */
 #define spn_BHH_CONSOLIDATED_FINAL_EVENT  "bhh_consolidated_final_event"
 
 /* Specify starting endpoint id for MPLS LM/DM endpoint in FP based OAM devices. */
 #define spn_MPLS_LM_DM_BASE_ENDPOINT_ID  "mpls_lm_dm_base_endpoint_id"
 
 /* Specify if ETPP LIF MTU feature is enabled. When enabled allows to create bcmRxTrapEgTxMtuFilter trap which allows to map LIF to specific MTU filter value */
 #define spn_TRAP_LIF_MTU_ENABLE  "trap_lif_mtu_enable"
 
 /* If set, enables per LIF control of preserve DSCP remark after routing. If enabled, reserves one bit each from InLIF profile and OutLIF profile. DSCP is preserved if both InLIF and OutLIF decides to preserve it */
 #define spn_LOGICAL_PORT_ROUTING_PRESERVE_DSCP  "logical_port_routing_preserve_dscp"
 
 /* This soc property will be used to define the rcy port which will be used in LBM up-mep. In case of dual cored device (Jericho) the soc property should be used with suffix: oam_rcy_port_up_0 for core 0, oam_rcy_port_up_1 for core 1 */
 #define spn_OAM_RCY_PORT_UP  "oam_rcy_port_up"
 
 /* tdm_queuing_force_<port> = 0 | 1, if set TDM queuing is on for this port, which mean this port will be handled like a TDM interlave port with high priority */
 #define spn_TDM_QUEUING_FORCE  "tdm_queuing_force"
 
 /* Each port can have its' own namespace for PWE label termination(termination lookup key is <port+label>) */
 #define spn_PWE_TERMINATION_PORT_MODE_ENABLE  "pwe_termination_port_mode_enable"
 
 /* Indicate the mode for PWE binded with MPLS EEDB entry creation (one call or more) */
 #define spn_MPLS_BIND_PWE_WITH_MPLS_ONE_CALL  "mpls_bind_pwe_with_mpls_one_call"
 
 /* Number of linkscan intervals to wait before applying the AN restart while switching between SGMII-CL37 vice versa */
 #define spn_SERDES_CL37_SGMII_RESTART_COUNT  "serdes_cl37_sgmii_restart_count"
 
 /* stat_if_etpp_counter_mode_<counterNumber> = EGRESS_VSI/EGRESS_OUT_LIF/EGRESS_PORT. <counterNumber> = be 0 or 1 for two stat_if counters. */
 #define spn_STAT_IF_ETPP_COUNTER_MODE  "stat_if_etpp_counter_mode"
 /*
  * SRAM packet descriptor buffers (PDBs) threshold
  * -1 - ignore threshold
  */
 #define spn_STAT_IF_SCRUBBER_SRAM_PDBS_TH  "stat_if_scrubber_sram_pdbs_th"
 /*
  * SRAM buffers threshold
  * -1 - ignore threshold
  */
 #define spn_STAT_IF_SCRUBBER_SRAM_BUFFERS_TH  "stat_if_scrubber_sram_buffers_th"
 /*
  * This soc_property is used to select a specific IPv6 route long prefix length that can be stored in the LEM.
  * Possible values: 0(disabled)/8/12/../56/60/64.
  */
 #define spn_ENHANCED_FIB_SCALE_PREFIX_LENGTH_IPV6_LONG  "enhanced_fib_scale_prefix_length_ipv6_long"
 /*
  * This soc_property is used to select a specific IPv6 route short prefix length that can be stored in the LEM.
  * Its value must be 12/8/4 bits shorter than enhanced_fib_scale_prefix_length_ipv6_long.
  */
 #define spn_ENHANCED_FIB_SCALE_PREFIX_LENGTH_IPV6_SHORT  "enhanced_fib_scale_prefix_length_ipv6_short"
 /*
  * If set driver reserve bcmPortClassFieldEgressPacketProcessing 2 bits to support DP profile.
  * In case feature is set then the number of bcmPortClassFieldEgressPacketProcessing is divided by 4. 
  */
 #define spn_QOS_POLICER_COLOR_MAPPING_PCP  "qos_policer_color_mapping_pcp"
 /*
  * When set, the Ingress PMF key allocation algorithm, performs a balanced distrubution between LSB and MSB instructions.
  * When disabled the allocation performs the old method.
  */
 #define spn_FIELD_KEY_ALLOCATION_MSB_BALANCE_ENABLE  "field_key_allocation_msb_balance_enable"
 /*
  * When set, all 4 bits of the VSI profile are used for the pmf, also disables L2CP traps.
  * When disabled 2 LSB bits are used for the L2CP vsi profile and 2 MSB bits are used for the pmf vsi profile.
  */
 #define spn_PMF_VSI_PROFILE_FULL_RANGE  "pmf_vsi_profile_full_range"
 /*
  * If set and when MPLS egress object is replaced/converted to L3 object using BCM_L3_REPLACE flag,
  * MAC DA in the L3 object will be configred with new value instead of using MAC DA from MPLS egress object.
  * If is not set and when MPLS egress object is replaced/converted to L3 object using BCM_L3_REPLACE flag,
  * MAC DA in the L3 object will be configred with MAC DA from MPLS egress object (default).
  */
 #define spn_EGRESS_OBJECT_MAC_DA_REPLACE  "egress_object_mac_da_replace"
 /*
  * 1: Provide LPM atomicity during entry update operations for IPv4 routes.
  * 0: IPv4 entries gets overwritten during entry udpate (add or delete) operations.
  */
 #define spn_LPM_ATOMIC_WRITE  "lpm_atomic_write"
 /*
  * BRCM MGBASE-T or IEEE 802.3bz Mode selection for speeds 2.5G/5G
  * 1: IEEE 802.3bz 5GBase-T & 2.5GBase-T.
  * 0: MGBASE-T, Broadcom 5GBase-T & 2.5GBase-T.
  */
 #define spn_PHY_MGBASET_802P3BZ_PRIORITY  "phy_mgbaset_802p3bz_priority"
 /*
  * 1: Enable KBP broadcast at transport layer.
  * 0: Disable KBP broadcast at transport layer.
  */
 #define spn_KBP_MESSAGE_BROADCAST_ENABLE  "kbp_message_broadcast_enable"
 /*
  * This soc property is used to set ILKN burst min value,
  * value must be greater than or equal to BURSTSHORT and less than or equal to half of the BURSTMAX (in bytes).
  */
 #define spn_ILKN_BURST_MIN  "ilkn_burst_min"
 /*
  * This soc property is used to enable UDPoIP tunnel support.
  * 0: UDPoIP tunnel support disabled.
  * 1: Enable UDPoIP tunnel initiation, Egress PRGE support and Parsing.
  */
 #define spn_UDP_TUNNEL_ENABLE  "udp_tunnel_enable"
 /*
  * This soc property is used to set the ETPP counter generation mode
  * 0 - Arad compatible mode. Take 16 lsb from lifs
  * 1 - JerichoModeA - pointers = lifs, no additional data on msb
  */
 #define spn_STAT_IF_ETPP_MODE  "stat_if_etpp_mode"
 /*
  * This soc property is used to decide which pin carries the OOB ILKN SYNC signal.
  * 0: Use pin FC_x_SYNC.
  * 1: Use pin FC_x_STAT[1]
  */
 #define spn_FC_OOB_ILKN_PAD_SYNC_ON_DATA_PIN  "fc_oob_ilkn_pad_sync_on_data_pin"
 /*
  * This soc property is used to turn on/off vlan auto stack.
  * Note:
  * It will override the preprocessor macro BCM_VLAN_NO_AUTO_STACK.
  * vlan_auto_stack = 1: turn on  vlan auto stack.
  * vlan_auto_stack = 2: turn off vlan atuo stack.
  * vlan_auto_stack = 0: the soc property does not take effect.
  */
 #define spn_VLAN_AUTO_STACK  "vlan_auto_stack"
 /*
  * Max number of egress l2cp profiles available, legal values are 1/2/4.
  * An unexpected value will be translated to one of the three values.
  * It is available on the devices of BCM88470 and above only.
  */
 #define spn_NOF_L2CP_EGRESS_PROFILES_MAX  "nof_l2cp_egress_profiles_max"
 /*
  * Number of minimum VLAN xlate mem banks.
  * Applicable for devices supporting ISM.
  */
 #define spn_VLAN_XLATE_MEM_BANKS  "vlan_xlate_mem_banks"
 /*
  * Number of minimum l2 mem banks.
  * Applicable for devices supporting ISM.
  */
 #define spn_L2_MEM_BANKS  "l2_mem_banks"
 /*
  * Number of minimum l3 mem banks.
  * Applicable for devices supporting ISM.
  */
 #define spn_L3_MEM_BANKS  "l3_mem_banks"
 /*
  * Number of minimum egress VLAN xlate mem banks.
  * Applicable for devices supporting ISM.
  */
 #define spn_EGR_VLAN_XLATE_MEM_BANKS  "egr_vlan_xlate_mem_banks"
 /*
  * Number of minimum MPLS mem banks.
  * Applicable for devices supporting ISM.
  */
 #define spn_MPLS_MEM_BANKS  "mpls_mem_banks"
 
 /* Enable large swing on the receiver input voltage. 0 disable, 1 enable */
 #define spn_SERDES_RX_LARGE_SWING  "serdes_rx_large_swing"
 /*
  * This soc property is used to skip hit bits maintenance in ALPM mode.
  * 1: Do not maintain the HIT bits to achieve performance gain.
  */
 #define spn_L3_ALPM_HIT_SKIP  "l3_alpm_hit_skip"
 
 /* Enable Ingress inheritance of TTL per Outgoing Logical interface. 0 disaable, 1 enable */
 #define spn_LOGICAL_INTERFACE_OUT_TTL_INHERITANCE  "logical_interface_out_ttl_inheritance"
 
 /* Enable Ingress inheritance of DSCP-EXP per Outgoing Logical interface. 0 disaable, 1 enable */
 #define spn_LOGICAL_INTERFACE_OUT_QOS_INHERITANCE  "logical_interface_out_qos_inheritance"
 /*
  * Flags to enable pstats or oob stats.
  * only one can be enabled at a time.
  * TH only supports 0 and 1.
  * 0x0 None: disable both oob stats and pstats
  * 0x1 OOB STATS: only enable out-of-band stats
  * 0x2 PSTATS: only enable packetized statistic
  */
 #define spn_BUFFER_STATS_COLLECT_TYPE  "buffer_stats_collect_type"
 /*
  * Flags to denote pstats and oob stats mode.
  * TH only supports 0.
  * 0x0 Instantaneous mode
  * 0x1 Max use count mode with HW clear on Read
  */
 #define spn_BUFFER_STATS_COLLECT_MODE  "buffer_stats_collect_mode"
 
 /* Set default maximum number of entry moves for all multi hash FPEM tables */
 #define spn_MULTI_HASH_RECURSE_DEPTH_EXACT_MATCH  "multi_hash_recurse_depth_exact_match"
 /*
  * Enable OAM hierarchical loss measurement by MDL (level).
  * Supports counting for two endpoints with different levels on the same LIF.
  * 0 = Disabled (default). 1 = Enabled.
  * O-EM1 table will be logically split while keys with your-disc-valid == 1
  * will be used to store the counter of the higher level MEP.
  * CAUTION: OEM1 BFD entries (classified by your-discriminator)
  *          could collide with CFM entries.
  */
 #define spn_OAM_HIERARCHICAL_LOSS_MEASUREMENT_BY_MDL_ENABLE  "oam_hierarchical_loss_measurement_by_mdl_enable"
 
 /* enable/disable Lawful Interception. */
 #define spn_LAWFUL_INTERCEPTION_ENABLE  "lawful_interception_enable"
 /*
  * Enable/Disable Flex flows Vs Legacy VXLAN module.
  * flow_init_mode = 0 loads Legacy VXLAN module on sdk initialization.
  * flow_init_mode = 1 loads flex flow module on sdk initialization.
  */
 #define spn_FLOW_INIT_MODE  "flow_init_mode"
 
 /* Default speed that the external PHY will initialize with */
 #define spn_PHY_INIT_SPEED  "phy_init_speed"
 
 /* Enable stacking FTMH extension of 2 bytes. */
 #define spn_STACKING_EXTENSION_ENABLE  "stacking_extension_enable"
 
 /* Enable double pointer pwe injection */
 #define spn_OAM_USE_DOUBLE_OUTLIF_INJECTION  "oam_use_double_outlif_injection"
 
 /* Software Autoneg Polling Interval in msec */
 #define spn_SW_AUTONEG_POLLING_INTERVAL  "sw_autoneg_polling_interval"
 /*
  * Time Aware Scheduling (TAS) calendar entries auto adjustment to avoid
  * TX overrun.
  * 1: enable the auto adjustment.
  * 0: disable the auto adjustment.
  * Available suffix: _port<#>
  *   Optional to specify the designated port(zero-based BCM API port number).
  */
 #define spn_TAS_CALENDAR_AUTO_ADJUST_FOR_TXOVERRUN  "tas_calendar_auto_adjust_for_txoverrun"
 /*
  * Time Aware Scheduling (TAS) calendar entries auto adjustment to reflect
  * holdAdvance parameter defined in 802.1Qbu.
  * 1: enable the auto adjustment.
  * 0: disable the auto adjustment.
  * Available suffix: _port<#>
  *   Optional to specify the designated port(zero-based BCM API port number).
  */
 #define spn_TAS_CALENDAR_AUTO_ADJUST_FOR_HOLDADVANCE  "tas_calendar_auto_adjust_for_holdadvance"
 /*
  * Select which flow type applies per-flow cut-through control (force store and forward).
  * 1 : Seamless Redundancy flow
  * 2 : Time-Sensitive Networking flow
  * By default, Seamless Redundancy flow is selected.
  * Note that this property only selects the flow type that supports per-flow cut through control.
  * Per-flow cut through control is achieved using the corresponding flow configuration API.
  */
 #define spn_FLOW_TYPE_FOR_CUT_THROUGH_CONTROL  "flow_type_for_cut_through_control"
 /*
  * Time Aware Scheduling (TAS): Specify the queueMaxSDU value to compute the
  * delay parameters (gate close response time) when
  * spn_TAS_CALENDAR_AUTO_ADJUST_FOR_TXOVERRUN is enabled.
  * Value: SDU size in bytes
  * Available suffix: _port<#>_cos<#>
  *   Optional to specify the designated port(zero-based BCM API port number)
  *   and the traffic class associated with the port by suffix.
  * If below properties are configured,
  *   tas_calendar_auto_adjust_ref_maxsdu = 512
  *   tas_calendar_auto_adjust_ref_maxsdu_port2 = 256
  *   tas_calendar_auto_adjust_ref_maxsdu_port2_cos0 = 128
  *   tas_calendar_auto_adjust_ref_maxsdu_port2_cos2 = 128
  *   Other traffic class which is not specified like cos1,cos3-7 on port 2
  *   will deploy the value=256
  *   The queueMaxDSU value of the ports other than port 2 will take 512.
  * NOTE: If tas_calendar_auto_adjust_ref_maxsdu is not specified when
  * tas_calendar_auto_adjust_for_txoverrun = 1, default value will be 1522.
  */
 #define spn_TAS_CALENDAR_AUTO_ADJUST_REF_MAXSDU  "tas_calendar_auto_adjust_ref_maxsdu"
 /*
  * Seamless Redundancy: Enable PRP support with selected loopback port.
  * To enable PRP, specify an appropriate logical port ID (excluding CPU port and
  * reserved ports) as the loopback port for the PRP feature.
  * Default value is 0 (PRP disabled).
  */
 #define spn_SR_PRP_ENABLE  "sr_prp_enable"
 
 /* Decrpt packet parsing will be turned off  */
 #define spn_XFLOW_MACSEC_SKIP_DECRYPT_PKT_PARSER  "xflow_macsec_skip_decrypt_pkt_parser"
 /*
  * This config property describes the number of Secure Associations 
  * associated with a Secure Channel. Default would be 1. This can be 
  * set to 4 to have 4 SA belonging to 1 SC. Any other value other 
  * than 1 or 4 will result in error.
  */
 #define spn_XFLOW_MACSEC_SECURE_CHAN_TO_NUM_SECURE_ASSOC  "xflow_macsec_secure_chan_to_num_secure_assoc"
 /*
  * Packets smaller than the threshold value are padded to this size. 
  * This must be set to a value >= 60. The CRC bytes are not included. 
  * The value is in bytes.
  */
 #define spn_XFLOW_MACSEC_DECRYPT_PAD_THRESHOLD  "xflow_macsec_decrypt_pad_threshold"
 /*
  * Treat the macsec packet having the C bit of the Sectag (or clear 
  * bit) set and the E bit of Sectag (or encrypt bit) unset as an error 
  * packet. The default is to treat such packets the same as the macsec 
  * packet having both the C bit of the Sectag and the E bit of the Sectag 
  * unset.
  */
 #define spn_XFLOW_MACSEC_DECRYPT_SECTAG_C1E0_ERROR  "xflow_macsec_decrypt_sectag_c1e0_error"
 /*
  * Packets are switched to CPU. Default is all decrypt SOP error 
  * packets will be dropped inside Macsec engine.
  */
 #define spn_XFLOW_MACSEC_DECRYPT_FAIL_SWITCH_TO_CPU  "xflow_macsec_decrypt_fail_switch_to_cpu"
 /*
  * Packets are switched to CPU. Default is all encrypt SOP error 
  * packets will be dropped inside Macsec engine.
  */
 #define spn_XFLOW_MACSEC_ENCRYPT_FAIL_SWITCH_TO_CPU  "xflow_macsec_encrypt_fail_switch_to_cpu"
 /*
  * Added support to config MPLS oam egress label ttl field
  * To avoid change in existing behavior, a new config
  * property mpls_oam_egress_label_ttl is added 
  */
 #define spn_MPLS_OAM_EGRESS_LABEL_TTL  "mpls_oam_egress_label_ttl"
 /*
  * Enable binding NBIs PLLs.
  * When this feature is enabled, the input to PML0 and/or PML1 PLLs will be taken from PMH PLL output.
  * This feature is relevant for QAX when using ILKN port on more than one NBI block.
  * Note: if both Soc Properties serdes_nif_clk_freq_in0/1 and serdes_nif_clk_binding_in0/1 are used, an error will be returned.
  */
 #define spn_SERDES_NIF_CLK_BINDING  "serdes_nif_clk_binding"
 /*
  * SW bypass for ILKN first packet issue.
  * To activate the SW bypass, set ilkn_first_packet_sw_bypass to 1.
  * NOTES:
  *   1. SW linkscan must be activated with this SOC property!
  *   2. This SOC property is not required for ILKN KBP ports as the KBP apps will bypass the first packet issue.
  */
 #define spn_ILKN_FIRST_PACKET_SW_BYPASS  "ilkn_first_packet_sw_bypass"
 /*
  * Disable tunnel ID, PON port to PON PP port mapping.
  * 1 - tunnel ID, PON port to PON PP port mapping is disabled.
  * 0 - tunnel ID, PON port to PON PP port mapping is enabled.
  */
 #define spn_PON_PP_PORT_MAPPING_BYPASS  "pon_pp_port_mapping_bypass"
 /*
  * Specifies initial port configuration based on SKU option ID.
  *     init_port_config_option=<SKU option ID>
  * This property is valid only when the SKU option ID is defined in the device
  * datasheet.
  */
 #define spn_INIT_PORT_CONFIG_OPTION  "init_port_config_option"
 /*
  * This soc property is used to enable/disable the reservation of NextHop tables.
  * The number of entries it reserves is equal to the number of ECMP Groups.
  * NOTES:
  *    1. It is a WAR for H/W bug.
  *    2. When it is enabled, Black Hole(0) and L2CPU(1) entries will also be moved after
  *       reserved entries.
  *    3. Interaction with spn_RIOT_OVERLAY_L3_EGRESS_MEM_ALLOC_MODE and
  *       spn_RIOT_OVERLAY_L3_EGRESS_MEM_SIZE:
  *       No matter spn_RIOT_OVERLAY_L3_EGRESS_MEM_ALLOC_MODE is enabled or
  *       disabled, spn_RIOT_OVERLAY_L3_EGRESS_MEM_SIZE which define the size of
  *       overlay can be ensured. Only underlay entries (equal the number of ECMP Groups)
  *       will be wasted. spn_RIOT_OVERLAY_L3_EGRESS_MEM_SIZE should be less than the
  *       actual size after reservation.
  *    4. On BCM56960, when it is enabled, no need to call bcm_l3_egress_create with
  *       BCM_L3_FLAGS2_NO_ECMP_OVERLAP flag.
  */
 #define spn_RESERVE_NH_FOR_ECMP  "reserve_nh_for_ecmp"
 /*
  * 0=disable 1=enable.
  * This SOC property will allocate the existing prge program ARAD_EGR_PROG_EDITOR_PROG_MIM_PTCH2.
  * This program does not remove the network headers and adds PTCH to packet.
  */
 #define spn_ADD_PTCH2_HEADER  "add_ptch2_header"
 /*
  * 0=disable 1=enable.
  * This SOC property will allocate the existing TT program PROG_TT_BRIDGE_STAR_2ND_PROG with program selection- ptc_tt_profile = RPF port.
  */
 #define spn_FORCE_BRIDGE_FORWARDING  "force_bridge_forwarding"
 /*
  * 0=basic 1=advanced optimized scheme.
  * When advanced optimized scheme is used then:
  * a. The amount of resources in parser are controlled via soc-properties.
  * b. The field HeaderFormat (Packet format code) is changed in regards to MPLS flows and HeaderFormatExtension (Parser leaf context) is introduced for better pre-selector and qualifiers in Field Processor APIs.
  * c. Introduce the capability of load-balancing for MPLS flows cases (non-terminated, partial-terminated and full-terminated) speculative and non speculative which are not supported in basic parser mode. 
  */
 #define spn_PARSER_MODE  "parser_mode"
 /*
  * This SOC property will enable ITPP network headers termination.
  * This mode can not support when UDH exist.
  * Support only on QAX and above.
  * 0=disable 1=enable.
  */
 #define spn_ITPP_NETWORK_HEADERS_TERMINATION  "itpp_network_headers_termination"
 /*
  * Enable 2-pass egress ACL processing. When enabled, packets routed to egress ACL recycle port 
  * will have network header terminated, a new Ethernet header is built, origin system header 
  * is kept and zero-padded to 48 bytes, then recycled for 2nd pass processing
  * 0=disable 1=enable.
  */
 #define spn_EGRESS_ACL_TWO_PASS_ENABLE  "egress_acl_two_pass_enable"
 /*
  * 0=disable 1=enable.
  * By default, IPv4 and IPv6 packets are enabled for MPLS tunnels. This config variable provides option to override the default values.
  */
 #define spn_MPLS_SWITCH_IPV4_IPV6_INDEPENDENT_CONTROL  "mpls_switch_ipv4_ipv6_independent_control"
 /*
  * Configure a BCM56972 device for 32-100G ports with RIOT, instead of the default
  * 36-100G ports
  */
 #define spn_BCM56972_RIOT_32X100  "bcm56972_riot_32x100"
 
 /* DPR clock frequency applied to switch chip, any unsupported frequency will be ignored. */
 #define spn_DPR_CLOCK_FREQUENCY  "dpr_clock_frequency"
 /*
  * Number of unicast and multicast queues per port
  * mmu_port_num_mc_queue = 0 (12 unicast, 0 multicast)
  * mmu_port_num_mc_queue = 1 (10 unicast, 2 multicast)
  * mmu_port_num_mc_queue = 2 (8 unicast, 4 multicast)
  * mmu_port_num_mc_queue = 3 (6 unicast, 6 multicast)
  */
 #define spn_MMU_PORT_NUM_MC_QUEUE  "mmu_port_num_mc_queue"
 /*
  * MMU Config Tool attribute name
  * Profile index(per port) to indicate which profile to use for input priority to priority group mapping
  */
 #define spn_INPUT_PRI_TO_PRIORITY_GROUP_PROFILE_IDX  "input_pri_to_priority_group_profile_idx"
 /*
  * MMU Config Tool attribute name
  * Profile index(per port) to indicate which profile to use for priority group to pool mapping
  */
 #define spn_PRIORITY_GROUP_PROFILE_IDX  "priority_group_profile_idx"
 /*
  * MMU Config Tool object name
  * Profile mapping structure
  */
 #define spn_MAPPROFILE  "mapprofile"
 /*
  * MMU Config Tool attribute name
  * Indicates if a profile is valid not not. 0=Not valid, 1=Valid
  */
 #define spn_PROFILE_VALID  "profile_valid"
 /*
  * MMU Config Tool attribute name
  * Specify input priority(0-15) to priority group mapping (0-7) for Unicast
  */
 #define spn_INPUT_PRI_TO_PRIORITY_GROUP_UC  "input_pri_to_priority_group_uc"
 /*
  * MMU Config Tool attribute name
  * Specify input priority(0-15) to priority group mapping (0-7) for Multicast
  */
 #define spn_INPUT_PRI_TO_PRIORITY_GROUP_MC  "input_pri_to_priority_group_mc"
 /*
  * MMU Config Tool attribute name
  * Specify priority group (0-7) to service pool mapping (0-3)
  */
 #define spn_PRIORITY_GROUP_TO_SERVICE_POOL  "priority_group_to_service_pool"
 /*
  * MMU Config Tool attribute name
  * Specify priority group (0-7) to headroom pool mapping (0-3)
  */
 #define spn_PRIORITY_GROUP_TO_HEADROOM_POOL  "priority_group_to_headroom_pool"
 /*
  * MMU Config Tool attribute name
  * Specify PFC class (0-7) to priority group mapping(0-7)
  */
 #define spn_PFCCLASS_TO_PRIORITY_GROUP  "pfcclass_to_priority_group"
 /*
  * MMU Config Tool attribute name
  * Specify if a priority group(per port) is lossless. 0=lossy 1=lossless 
  */
 #define spn_PRIORITY_GROUP_LOSSLESS  "priority_group_lossless"
 /*
  * MMU Config Tool attribute name
  * Specify min guarantee for multicast
  */
 #define spn_GUARANTEE_MC  "guarantee_mc"
 
 /* Scheduler profile attribute name */
 #define spn_SCHEDULER_PROFILE_MAP  "scheduler_profile_map"
 
 /* Scheduler profile attribute name */
 #define spn_SCHEDULER_PROFILE  "scheduler_profile"
 
 /* Cos to queue mapping. number of unicast queues */
 #define spn_NUM_UNICAST_QUEUE  "num_unicast_queue"
 
 /* Cos to queue mapping. number of multicast queues */
 #define spn_NUM_MULTICAST_QUEUE  "num_multicast_queue"
 
 /* Cos to queue mapping. Strict priority scheduling */
 #define spn_SCHED_STRICT_PRIORITY  "sched_strict_priority"
 
 /* Cos to queue mapping. Only unicast is flow controlled */
 #define spn_FLOW_CONTROL_ONLY_UNICAST  "flow_control_only_unicast"
 /*
  * Configures size of L3 ECMP_GROUP memory in fist lookup.
  * It is used to decide the size of L3_ECMP_GROUP memories that are available for first ECMP lookup. Internally, the size rounds up to multiple of 512.
  */
 #define spn_L3_ECMP_GROUP_FIRST_LKUP_MEM_SIZE  "l3_ecmp_group_first_lkup_mem_size"
 /*
  * Configures size of L3 ECMP memory in first lookup.
  * It is used to decide the size of L3_ECMP memories that are available for first ECMP lookup.
  * Internally, the size rounds up to multiple of 4096 in BCM5687x class of devices and 1024 in BCM5637x/BCM5657x.
  * On BCM5687x this value defaults to half the ECMP member table size.
  * On BCM5637x/BCM5657x, since only 3 out of 4 banks can be used when ECMP works in 2 levels, this defaults to size of one bank (1024).
  */
 #define spn_L3_ECMP_MEMBER_FIRST_LKUP_MEM_SIZE  "l3_ecmp_member_first_lkup_mem_size"
 
 /* Enable or Disable allocating even based meter indexes for flow mode metering for stage ingress. 0=Disable, 1=Enable. */
 #define spn_FP_EVEN_INDEX_FOR_INGRESS_FLOW_METER  "fp_even_index_for_ingress_flow_meter"
 /*
  * This config property describes the number of Secure Associations 
  * associated with a Secure Channel. Default would be 1. This can be 
  * set to 4 to have 4 SA belonging to 1 SC. Any other value other 
  * than 1 or 4 will result in error.
  */
 #define spn_XFLOW_MACSEC_SECURE_CHAN_TO_NUM_SECURE_ASSOC  "xflow_macsec_secure_chan_to_num_secure_assoc"
 /*
  * This soc property is used to set dram auto calibration update to enable - relevant only for GDDR5
  * 0 - disable dram auto calibration update
  * 1 - enable dram auto calibration update
  * this is enabled by default
  */
 #define spn_DRAM_AUTO_CALIBRATION_UPDATE_ENABLE  "dram_auto_calibration_update_enable"
 /*
  * Sets the CDR to work in an extended-threshold, i.e. reduced jitter mode:
  * Default value: 1 (enabled)
  * Backward compatible value, against BRCM recommendation: 0 (disabled)
  */
 #define spn_EXT_RAM_PHY_CDR_TH_EXTENDED_EN  "ext_ram_phy_cdr_th_extended_en"
 /*
  * Defines the DDR Chip Select (CS) and DDR Clock Enable (CKE) delay mode to reduced delay and extended setup margins:
  * Default value: 1 (enabled)
  * Backward compatible value, against BRCM recommendation: 0 (disabled)
  */
 #define spn_EXT_RAM_CMD_REDUCED_DELAY_EN  "ext_ram_cmd_reduced_delay_en"
 /*
  * Pair serdes rx and tx with a lane number. Usage:
  * lane_to_serdes_map_<nif\fabric>_lane<lane_id>=rx<srd_rx_id>:tx<srd_tx_id>
  * lane_to_serdes_map_<nif\fabric>_lane<lane_id>=rx<srd_rx_id>:tx<srd_tx_id>
  */
 #define spn_LANE_TO_SERDES_MAP  "lane_to_serdes_map"
 /*
  * Reference application enable property.
  * This is not a standard soc property, used to enable or disable reference applications.
  * Default value: 1 (enabled)
  * appl_enable_<appl_name>=0/1
  */
 #define spn_APPL_ENABLE  "appl_enable"
 /*
  * Reference application parametrs.
  * This is not a standard soc property, used to pass arguments to reference application.
  * appl_param_<param_name>=value
  */
 #define spn_APPL_PARAM  "appl_param"
 /*
  * This soc property indicates a channel bitmap which uses packet dma poll mode.
  * Bit n is for channel n. The bit value 1 means poll mode, 0 means interrupt mode.
  * Default value is 0x0.
  * Example:
  * pktdma_poll_mode_channel_bitmap=0x02 means channel 1 uses poll mode.
  */
 #define spn_PKTDMA_POLL_MODE_CHANNEL_BITMAP  "pktdma_poll_mode_channel_bitmap"
 /*
  * Define the connection mode which connecting with BCM52311 and beyond
  * Valid values:
  * Single: Single Host Dual Port mode
  * Dual: Dual Host Quad Port mode - In this mode the even unit is
  * responsible for the initializing work.
  */
 #define spn_EXT_TCAM_CONNECT_MODE  "ext_tcam_connect_mode"
 /*
  * Define the start lane number on Optimus Prime side for each OP port.
  * Also define the switch core to Optimus Port port mapping.
  * Use suffix "_portN" to configure each port.
  * In Single Host Dual Port mode, only port1 and port2 is acceptable.
  * In Dual Host Quad Port mode, four ports are all acceptable.
  * Example:
  * ext_tcam_start_lane_port1=18:core1 means the start lane number of Optimus
  * Prime port 1 is 18, connecting with switch core 1
  */
 #define spn_EXT_TCAM_START_LANE  "ext_tcam_start_lane"
 /*
  * ext_tcam_serdes_tx_taps to specify either 3 taps or 6 taps, in nrz or pam4 signalling mode per lane on KBP side.
  * this config is per lane id.
  * the taps are decimal numbers, positive or negative, separated by a colon ":".
  * the first parameter will specify whether the Tx params are suitable for nrz or pam4 signaling mode.
  * the order will be as follows:
  * For 3 taps mode:
  * ext_tcam_serdes_tx_taps_lane<id>=signaling_mode:pre:main:post
  * For example, for lane 0 taps mode, pre=8, main=50, post=12, that will be working in nrz mode,
  * The config will be ext_tcam_serdes_tx_taps_lane0=nrz:8:50:12
  * For 6 taps mode:
  * ext_tcam_serdes_tx_taps_lane<id>=signaling_mode:pre:main:post:pre2:post2:post3
  * For example, for lane 8 that needs to config 6 taps mode, pre1=-10, main=60, post1=8, pre2=2, post2=-4, post3=3,
  * that will be working in pam4 mode,
  * ext_tcam_serdes_tx_taps_lane8=pam4:-10:60:8:2:-4:3
  * if this config is not specified, then SDK will use its own default tx taps value.
  */
 #define spn_EXT_TCAM_SERDES_TX_TAPS  "ext_tcam_serdes_tx_taps"
 /*
  * The correction factor for the PVT MON SW WA. The unit is degrees Celsius.
  * The value can be positive or negative. Default value is 0
  */
 #define spn_PVT_MON_CORRECTION_FACTOR  "pvt_mon_correction_factor"
 /*
  * This soc property indicates if the dummy VP for VLAN_XLATE action feature is enabled.
  * Value 1 means enable mode, 0 means disable mode. Default value is 0
  */
 #define spn_VLAN_ACTION_DUMMY_VP_RESERVED  "vlan_action_dummy_vp_reserved"
 /*
  * Temperature threshold to trigger the high temperature interrupt. 
  * Should be no more than 110C.
  */
 #define spn_SW_TEMP_THRESHOLD  "sw_temp_threshold"
 
 /* Ipfix observation domain Id for an observation domain (usually a switch) */
 #define spn_FLOWTRACKER_IPFIX_OBSERVATION_DOMAIN_ID  "flowtracker_ipfix_observation_domain_id"
 
 /* Interrupt vs polled mode for flowtracker fifo dma export */
 #define spn_FLOWTRACKER_EXPORT_FIFO_INTR_ENABLE  "flowtracker_export_fifo_intr_enable"
 
 /* flowtracker export fifo thread priority; 0 is highest and 255 is lowest */
 #define spn_FLOWTRACKER_EXPORT_FIFO_THREAD_PRI  "flowtracker_export_fifo_thread_pri"
 
 /* Number of flowtracker export entries allocated for the FIFO DMA host buffer */
 #define spn_FLOWTRACKER_EXPORT_FIFO_HOSTBUF_SIZE  "flowtracker_export_fifo_hostbuf_size"
 
 /* Number of unique flowtracker user entry keys. */
 #define spn_FLOWTRACKER_NUM_UNIQUE_USER_ENTRY_KEYS  "flowtracker_num_unique_user_entry_keys"
 /*
  * Specifies S-Channel method/engine used for SOC memory bulk operations
  * soc_mem_bulk_XXX().
  * FIFO - S-Channel FIFO engine is SBUS master.
  * PIO - S-Channel PIO engine is SBUS master.
  * FIFO engine is the recommended as default SBUS master for better performance.
  * PIO mode is useful for debugging and performance comparison.
  */
 #define spn_SOC_MEM_BULK_SCHAN_OP_MODE  "soc_mem_bulk_schan_op_mode"
 /*
  * 1 - enable flow tracker(FTv1) embedded app
  * 2 - enable flow tracker(FTv2) embedded app
  * default value: 0 (disabled)
  */
 #define spn_FLOWTRACKER_ENABLE  "flowtracker_enable"
 /*
  * Maximum number of flow groups monitored by flowtracker embedded app
  * default value: 255
  */
 #define spn_FLOWTRACKER_MAX_FLOW_GROUPS  "flowtracker_max_flow_groups"
 /*
  * Maximum number of flows that can be learnt. In multi-pipe devices, the flow limit
  * is equally distributed among all the pipes, per pipe flow limit can be imposed by
  * suffixing with _pipe<pipe_num>
  * default value: 16K
  */
 #define spn_FLOWTRACKER_MAX_FLOWS  "flowtracker_max_flows"
 /*
  * Maximum number of counters that can be assigned to a single flow.
  * Valid values currently supported are 1, 2 and 4.
  * default value: 1
  */
 #define spn_FLOWTRACKER_MAX_COUNTERS_PER_FLOW  "flowtracker_max_counters_per_flow"
 /*
  * Maximum length of an export packet in bytes that will be sent by Flowtracker embedded app
  * default value: 1500
  */
 #define spn_FLOWTRACKER_MAX_EXPORT_PKT_LENGTH  "flowtracker_max_export_pkt_length"
 
 /* Enable elephant monitoring, 0 - Disable, 1 - Enable */
 #define spn_FLOWTRACKER_ELEPHANT_ENABLE  "flowtracker_elephant_enable"
 
 /* Interval at which the flow table is scanned to detect elephant flows. */
 #define spn_FLOWTRACKER_ELEPHANT_SCAN_INTERVAL_USECS  "flowtracker_elephant_scan_interval_usecs"
 
 /* Enables the tracking the flow start timestamp information element, 0 - Disable, 1 - Enable. */
 #define spn_FLOWTRACKER_FLOW_START_TIMESTAMP_IE_ENABLE  "flowtracker_flow_start_timestamp_ie_enable"
 
 /* Export interval of the active flows in usecs */
 #define spn_FLOWTRACKER_EXPORT_INTERVAL_USECS  "flowtracker_export_interval_usecs"
 /*
  * Expected time required to drain the egress COS queues. Used to
  * prevent re-ordering when demoting elephant flows to mice
  */
 #define spn_FLOWTRACKER_ELEPHANT_EXPECTED_QUEUE_DRAIN_TIME_USECS  "flowtracker_elephant_expected_queue_drain_time_usecs"
 
 /* Enterprise number to be used when exporting template sets containing enterprise specific information elements */
 #define spn_FLOWTRACKER_ENTERPRISE_NUMBER  "flowtracker_enterprise_number"
 
 /* Drop monitoring, 0 - Disable, 1 - Enable */
 #define spn_FLOWTRACKER_DROP_MONITOR_ENABLE  "flowtracker_drop_monitor_enable"
 
 /* Maximum length of the reinjected FSP packet. Packets larger than this number are truncated prior to re-injection */
 #define spn_FLOWTRACKER_FSP_REINJECT_MAX_LENGTH  "flowtracker_fsp_reinject_max_length"
 
 /* Interval at which the flow table is scanned to collect counter information in micro seconds. Minimum value allowed is 100000 micro seconds */
 #define spn_FLOWTRACKER_SCAN_INTERVAL_USECS  "flowtracker_scan_interval_usecs"
 
 /* Maximum number of ports that can be monitored simultaneously by ST app */
 #define spn_TELEMETRY_MAX_PORTS_MONITOR  "telemetry_max_ports_monitor"
 /*
  * PCIE host interface timeout in microseconds
  * timeout value is based on 250 Mhz clock
  * 1 usc = 0x100, Default is 50 msec
  */
 #define spn_PCIE_HOST_INTF_TIMEOUT_USEC  "pcie_host_intf_timeout_usec"
 
 /* Enable Purge operation as soon as PCIE timeout is detected. */
 #define spn_PCIE_HOST_INTF_TIMEOUT_PURGE_ENABLE  "pcie_host_intf_timeout_purge_enable"
 
 /* If set, then incoming logical interface can set or unset Same-interface filtering according to logical-interface ID while incoming and outgoing port-ID will be ignored. */
 #define spn_BCM886XX_LOGICAL_INTERFACE_SAME_FILTER_ENABLE  "bcm886xx_logical_interface_same_filter_enable"
 /*
  * Disables OTM-Port restriction on LAG creation.
  * Allows TM-Port to be a member of multiple LAGs
  * Should never be used.
  */
 #define spn_DISABLE_LAG_OTM_CHECK  "disable_lag_otm_check"
 /*
  * IPv6 tunnel encapsulation mode:
  * 0: Disable.
  * 1: Legacy mode.
  * Limited number tunnels (depends on the PRGE-data size), allocates EEDB and PRGE-data entries per Tunnel.
  * 2: Normal mode.
  * Scalable solution, allocates 2xEEDB entries per Tunnel, Limited number of SIP supported (according to PRGE-data).
  * 3: Large mode.
  * Large solution (depends on the KAPs large-direct table size), allocates EEDB and PRGE-data entries per Tunnel.
  */
 #define spn_BCM886XX_IP6_TUNNEL_ENCAPSULATION_MODE  "bcm886xx_ip6_tunnel_encapsulation_mode"
 /*
  * IPv6 tunnel termination mode:
  * 0: Disable.
  * 1: Legacy mode.
  * DIP lookup only.
  * 2: Normal mode.
  * (DIP, VRF, Next-protocol, Port-property) or (DIP, SIP, VRF, Next-protocol, Port-property) lookup.
  * Note: including DIP, SIP in the lookup key require cascading lookup and occupy VT TCAM resource.
  */
 #define spn_BCM886XX_IP6_TUNNEL_TERMINATION_MODE  "bcm886xx_ip6_tunnel_termination_mode"
 /*
  * This soc property is used in IPv6 tunnel termination according to (DIP, VRF, Next-protocol, Port-property)
  * enabled using bcm886xx_ip6_tunnel_termination_mode = 2.
  * It defines the number of bits available for VRF in IPv6 tunnel termination.
  */
 #define spn_IP6_TUNNEL_TERM_IN_TCAM_VRF_NOF_BITS  "ip6_tunnel_term_in_tcam_vrf_nof_bits"
 /*
  * The storm control meter index to be used for broadcast packets.
  * Valid range 0 to 3. If out of range value is provided, will fallback to default value
  */
 #define spn_BCM_RATE_BCAST_INDEX  "bcm_rate_bcast_index"
 /*
  * The storm control meter index to be used for multicast packets
  * Valid range 0 to 3. If out of range value is provided, will fallback to default value
  */
 #define spn_BCM_RATE_MCAST_INDEX  "bcm_rate_mcast_index"
 /*
  * The storm control meter index to be used for unknown multicast packets
  * Valid range 0 to 3. If out of range value is provided, will fallback to default value
  */
 #define spn_BCM_RATE_UNKNOWN_MCAST_INDEX  "bcm_rate_unknown_mcast_index"
 /*
  * The storm control meter index to be used for destination lookup failure packets
  * Valid range 0 to 3. If out of range value is provided, will fallback to default value
  */
 #define spn_BCM_RATE_DLF_INDEX  "bcm_rate_dlf_index"
 /*
  * This soc property is relevant only for Jericho.
  * It sets the distribution of Mini MC buffers between cores to be optimized -
  * meaning equal distribution as possible between cores
  */
 #define spn_EXT_RAM_DBUFF_MMC_OPTIMIZED_DISTRIBUTION_ENABLE  "ext_ram_dbuff_mmc_optimized_distribution_enable"
 /*
  * To set the couple mode in bcm_port_untagged_vlan_set.
  * mode = 0 is legacy couple mode.
  * Port-based VLAN and protocol-based VLAN can be used at the same time and work right.
  * But port-based vlan supports at max 127 ports with different default vlan.
  * mode = 1 is decouple mode, it supports all ports(>128) based default vlan.
  * But protocol-based vlan is suggested to abandon or use VFP instead.
  */
 #define spn_PROTOCOL_VLAN_COUPLED_MODE  "protocol_vlan_coupled_mode"
 /*
  * This soc property is to indicate if shutdown KNET during doing warmboot.
  * 0-shutdown by default
  * 1-no shutdown
  */
 #define spn_WARMBOOT_KNET_SHUTDOWN_MODE  "warmboot_knet_shutdown_mode"
 /*
  * This soc property is used to specify max mtu size for the device.
  * If this is not specified, the defalut mtu size supported
  * by the device is used as max mtu
  */
 #define spn_MAX_MTU_SIZE  "max_mtu_size"
 /*
  * IPv4 tunnel encapsulation mode:
  * 0: Disable.
  * 1: Legacy mode.
  * Limited number tunnels (depends on the EEDB table size), allocates EEDB entries per Tunnel.
  * 2: Large mode.
  * Scalable solution, allocates KAPS large direct entries per Tunnel.
  */
 #define spn_BCM886XX_IP4_TUNNEL_ENCAPSULATION_MODE  "bcm886xx_ip4_tunnel_encapsulation_mode"
 /*
  * PPPoE mode:
  * 0: disabled
  * 1: enable PPPoE termination and encapsulation
  */
 #define spn_PPPOE_MODE  "PPPoE_mode"
 /*
  * Specifices the number of entries to be reserved in flowset table for
  * resilient hashing load balancing mode front panel trunk groups.
  * The remaining entries in this table are used by resilient hashing load
  * balancing mode HiGig trunk groups.If this property is not configured,
  * then the table entries are split evenly between resilient hashing load
  * balancing mode front panel trunk groups and HiGig trunk groups.
  * Valid values for this property are: 0, 32K, 64K. Default: 32K.
  */
 #define spn_TRUNK_RESILIENT_HASH_TABLE_SIZE  "trunk_resilient_hash_table_size"
 /*
  * Initial speed for CPRI port
  * Speeds 0: 1228.8
  *        1: 2457.6
  *        2: 3072.0
  *        3: 4915.2
  *        4: 6144.0
  *        5: 9830.4
  *        6: 10137.6
  *        7: 12165.12
  *        8: 24330.24
  */
 #define spn_CPRI_PORT_INIT_SPEED_ID  "cpri_port_init_speed_id"
 /*
  * Initial speed for rsvd4 port
  * Speeds 4: 3072.0
  *        8: 6144.0
  */
 #define spn_RSVD4_PORT_INIT_SPEED_ID  "rsvd4_port_init_speed_id"
 
 /* 1bit value for Stuffing bit */
 #define spn_ROE_STUFFING_BIT  "roe_stuffing_bit"
 
 /* 1bit value for Reserved bit */
 #define spn_ROE_RESERVED_BIT  "roe_reserved_bit"
 
 /* scramblar seed for CPRI and RSVD4 mode */
 #define spn_SERDES_SCRAMBLER_SEED  "serdes_scrambler_seed"
 /*
  * Configure the mep db full entry threshold.
  * MEP IDs up to and including the theshold will be utilized by 1/4 entries
  * MEP IDs above the theshold will be utilized by full entries
  */
 #define spn_OAMP_MEP_DB_FULL_ENTRY_THRESHOLD  "oamp_mep_db_full_entry_threshold"
 /*
  * Configure the rmep db full entry threshold.
  * RMEP IDs up to and including the theshold will be utilized by 1/2 entries
  * RMEP IDs above the theshold will be utilized by full entries
  */
 #define spn_OAMP_RMEP_DB_FULL_ENTRY_THRESHOLD  "oamp_rmep_db_full_entry_threshold"
 
 /* Enable graceful lag modification. */
 #define spn_GRACEFUL_LAG_MODIFICATION_ENABLE  "graceful_lag_modification_enable"
 /*
  * This soc property indicates which ipmc lookup model is used.
  * 0=legacy private and public model
  *   legacy model LPM lookup key: <[VRF], Group, SIP, InRIF>
  * 1=new model.
  *   new model LPM lookup key: <[InRIF], VRF, Group, SIP>
  */
 #define spn_IPMC_LOOKUP_MODEL  "ipmc_lookup_model"
 /*
  * Enable FEC and set FEC type.
  * This config is per logical port.
  * Each FEC type is encoded by a number. The options are:
  * 0  - no fec.
  * 1  - cl-74/Base-R. 64/66b KR FEC for DNX fabric.
  * 2  - cl-91/RS-FEC
  * 3  - rs-544. Use 1xN RS FEC architecture.
  * 4  - rs-272. Use 1xN RS FEC architecture.
  * 5  - rs-206. 64/66b 5T RS FEC for DNX fabric.
  * 6  - rs-108. 64/66b 5T low latency RS FEC for DNX fabric.
  * 7  - rs-545. 64/66b 15T RS FEC for DNX fabric
  * 8  - rs-304. 64/66b 15T low latency RS FEC for DNX fabric.
  * 9  - rs-544-2xN. Use 2xN RS FEC architecture.
  * 10 - rs-272-2xN. Use 2xN RS FEC architecture.
  */
 #define spn_PORT_FEC  "port_fec"
 /*
  * When flex_stat_compression_share config property is set
  * user is allowed to share flex counter compression tables
  * across different flex counter group mode ids
  * whose packet attribute types and values are same or subset.
  * Valid Values:
  * 0 (Disable) - compression table sharing is disabled (default)
  * 1 (Enable)  - compression table sharing is enabled
  */
 #define spn_FLEX_STAT_COMPRESSION_SHARE  "flex_stat_compression_share"
 
 /* Enable/disable counting of CCM packets, excluding CCMs with dual ended LM for BCM88270 devices */
 #define spn_OAM_CCM_COUNTING_ENABLE  "oam_ccm_counting_enable"
 
 /* Enable LM or SLM mode for BCM88270 devices. 0 for LM and 1 for SLM. */
 #define spn_OAM_SLM_LM_MODE  "oam_slm_lm_mode"
 /*
  * System headers mode the device supports, possible values:
  * 0x0 - Jericho-mode - used for Jericho/QMX/QAX/QUX mode
  * 0x1 - Jericho2-mode - used for Jericho 2 mode
  */
 #define spn_SYSTEM_HEADERS_MODE  "system_headers_mode"
 /*
  * Field class ID size 0 is used to determine UDH_0
  * size in J1 mode and also the udh_egress_offset.
  * Default: 0x0.
  */
 #define spn_FIELD_CLASS_ID_SIZE_0  "field_class_id_size_0"
 /*
  * Field class ID size 0 is used to determine UDH_0
  * size in J1 mode and also the udh_egress_offset_0/1.
  * Default: 0x0.
  */
 #define spn_FIELD_CLASS_ID_SIZE_0  "field_class_id_size_0"
 /*
  * Field class ID size 1 is used to determine UDH_1
  * size in J1 mode.
  * Default: 0x0.
  */
 #define spn_FIELD_CLASS_ID_SIZE_1  "field_class_id_size_1"
 /*
  * Field class ID size 2 is used to determine UDH_0
  * size in J1 mode.
  * Default: 0x0.
  */
 #define spn_FIELD_CLASS_ID_SIZE_2  "field_class_id_size_2"
 /*
  * Field class ID size 3 is used to determine UDH_1
  * size in J1 mode.
  * Default: 0x0.
  */
 #define spn_FIELD_CLASS_ID_SIZE_3  "field_class_id_size_3"
 #define spn_BCM5626X_CONFIG  "bcm5626x_config"
 #define spn_BCM5627X_CONFIG  "bcm5627x_config"
 
 /* External IPv4 Unicast public forward table size. */
 #define spn_EXT_IP4_PUBLIC_FWD_TABLE_SIZE  "ext_ip4_public_fwd_table_size"
 
 /* External IPv4 Unicast with RPF public forward table size. */
 #define spn_EXT_IP4_UC_RPF_PUBLIC_FWD_TABLE_SIZE  "ext_ip4_uc_rpf_public_fwd_table_size"
 
 /* External IPv6 Unicast public forward table size. */
 #define spn_EXT_IP6_PUBLIC_FWD_TABLE_SIZE  "ext_ip6_public_fwd_table_size"
 
 /* External IPv6 Unicast with RPF public forward table size. */
 #define spn_EXT_IP6_UC_RPF_PUBLIC_FWD_TABLE_SIZE  "ext_ip6_uc_rpf_public_fwd_table_size"
 /*
  * Port bitmap for 25G ports use 50G TDM calendar during initialization.
  * It refers to logical port number. This SOC property only apply to TH2
  * and other devices which use new type flex port
  * API(bcm_port_resource_multi_set).
  */
 #define spn_PBMP_OVERSUBSCRIBE_MIXED_SISTER_25_50_INIT  "pbmp_oversubscribe_mixed_sister_25_50_init"
 
 /* Property to explicitly enable InPorts Qualifier support in Ingress Field Module. */
 #define spn_IFP_INPORTS_SUPPORT_ENABLE  "ifp_inports_support_enable"
 
 /* Large direct lookup advanced mode. */
 #define spn_PMF_KAPS_MGMT_ADVANCED_MODE  "pmf_kaps_mgmt_advanced_mode"
 /*
  * When global_meter_compression_share config property is set, SDK allows
  * sharing of global meter compression tables across different policer
  * group mode ids. Valid values are:
  * 0 (Disable) - compression table sharing is disabled (default)
  * 1 (Enable)  - compression table sharing is enabled for policer group
  *     mode ids whose packet attribute types and values are same or subset.
  */
 #define spn_GLOBAL_METER_COMPRESSION_SHARE  "global_meter_compression_share"
 /*
  * The  config property need to be set to be able to use the new APIs that help in
  * association of counter pool id with accounting object and help in compaction.
  * After the config property is set the Customer can use API bcm_stat_custom_group_id_create()
  * to map any,accounting object to any pool and use API bcm_stat_flex_counter_id_move() to move.
  * counters within and across pools to help in compaction . In this mode SDK will not maintain any static
  * allocation of pools to accounting objects.
  * Valid Values:
  * 0 (Disable) - flexible pool allocation and compaction is disabled (default)
  * 1 (Enable)  - flexible pool allocation and compaction is enabled
  */
 #define spn_FLEX_STAT_COMPACTION_SUPPORT  "flex_stat_compaction_support"
 /*
  * Property to allow flexible allocation of pools to policer groups and
  * movement of policer group within or across pool (for the purpose of
  * compaction). Valid values are
  * 0 (Disable) - flexible pool allocation and compaction are disabled (default)
  * 1 (Enable)  - flexible pool allocation and compaction are enabled.
  */
 #define spn_GLOBAL_METER_COMPACTION_SUPPORT  "global_meter_compaction_support"
 
 /* User can configure a non-default (non-IETF 4789) VXLAN UDP destination port. */
 #define spn_VXLAN_UDP_DEST_PORT  "vxlan_udp_dest_port"
 
 /* Specifies number of ACL qualify ranges in ELK. */
 #define spn_KBP_MAX_NUM_RANGES  "kbp_max_num_ranges"
 /*
  * Enable/Disable egress multiple split horizon group check enhancement for IPv6 VxLAN.
  * ip6_vxlan_mshg_enable = 0 disable ipv6 vxlan egress MSHG check enhancement.
  * ip6_vxlan_mshg_enable = 1 enable ipv6 vxlan egress MSHG check enhancement.
  */
 #define spn_IP6_VXLAN_MSHG_ENABLE  "ip6_vxlan_mshg_enable"
 /*
  * Define how to configure LUT entry while connecting with BCM52311 and beyond
  * Valid values:
  * MDIO: Configure LUT entry via MDIO registers, this is the default value
  * ROP: Configure LUT entry via ROP packets
  */
 #define spn_EXT_TCAM_LUT_WRITE_MODE  "ext_tcam_lut_write_mode"
 /*
  * Defines which entries in the remap table per cmc is reserved (for Arm) and cannot be used by SDK.
  * value is a bitmap, each bit represent an entry of the table
  * example: host_memory_address_remap_entries_cmc_<cmc_index>=0x12
  */
 #define spn_HOST_MEMORY_ADDRESS_REMAP_ENTRIES_RESERVED_CMC  "host_memory_address_remap_entries_reserved_cmc"
 
 /* This property determines if warmboot is supported */
 #define spn_WARMBOOT_SUPPORT  "warmboot_support"
 
 /* External IPv4 Multicase source specific lookup for bridged packets forward table size. */
 #define spn_EXT_IP4_MC_BRIDGE_FWD_TABLE_SIZE  "ext_ip4_mc_bridge_fwd_table_size"
 
 /* Enable IP ACL on bridged packets for egress PMF */
 #define spn_FIELD_EGRESS_ENABLE_IP_ACL_ON_BRIDGE  "field_egress_enable_ip_acl_on_bridge"
 /*
  * This property will be used to enable interrupts for learn cache mechanism.
  * When interrupts are enabled, the CPU will be interrupted based on the
  * threshold valuep rogrammed in the learn cache control register.
  * Valid values: 0 (polled mode) or 1 (interrupt mode)
  */
 #define spn_L2XLRN_INTR_EN  "l2xlrn_intr_en"
 /*
  * Priority of learn thread on BCM5698x. This thread is used for L2 learning
  * This thread should always run, otherwise L2 learning will stop
  * Range 0(highest) - 255(lowest)
  */
 #define spn_L2XLRN_THREAD_PRI  "l2xlrn_thread_pri"
 
 /* Interval in microseconds for L2 learn thread in polled mode. */
 #define spn_L2XLRN_THREAD_INTERVAL  "l2xlrn_thread_interval"
 /*
  * Generate an interrupt for learning, depending on the fill level of the cache.
  * Valid only in interrupt mode (that is, when interrupts are enabled).
  * In polled mode, this value will be ignored. Range: 1 to 15
  */
 #define spn_L2XLRN_INTR_THRESHOLD  "l2xlrn_intr_threshold"
 /*
  * When enabled, entries are removed from learn cache immediately following a
  * read operation.
  * Valid values: 0 (disable) or 1 (enable)
  */
 #define spn_L2XLRN_CLEAR_ON_READ  "l2xlrn_clear_on_read"
 /*
  * This soc property is used to enable/disable HOST AS ROUTE feature
  * which allows the entry to be automatically added to the route table
  * if the host table is either full or there is a hash collision by calling
  * bcm_l3_host_add API with BCM_L3_HOST_AS_ROUTE flag.
  * 0 = Enable HOST AS ROUTE(default). 1 = Disable HOST AS ROUTE.
  */
 #define spn_HOST_AS_ROUTE_DISABLE  "host_as_route_disable"
 /*
  * When enabled, all free subports are added in general pp port pbm and
  * can be used for special purpose like OAM application.
  * Valid values: 0 (disable) or 1 (enable)
  */
 #define spn_GENERAL_CASCADE_MODE  "general_cascade_mode"
 /*
  * Default ALPM route data mode: 1 (default) for full data mode
  * and 0 for reduced data mode.
  */
 #define spn_L3_ALPM2_DEFAULT_ROUTE_DATA_MODE  "l3_alpm2_default_route_data_mode"
 /*
  * This soc property is used to control vplag vp allocation
  * Set to 0(default) to control vplag vp allocation from low end
  * Set to 1 to control vplag vp allocation from high end.
  */
 #define spn_VPLAG_VP_ALLOC_MODE  "vplag_vp_alloc_mode"
 /*
  * This soc property is used to bring up KBP serdes via PCIe.
  * This feature is only relevant for BCM52311 and beyond.
  * Set to 0(default) to bring up KBP serdes via MDIO.
  * Set to 1 to bring up KBP serdes via PCIe.
  */
 #define spn_EXT_TCAM_SERDES_PCIE_INIT  "ext_tcam_serdes_pcie_init"
 /*
  * This soc property defines whether SOBMH packets sent to
  * loopback ports use unicast or multicast queues.
  * The value is 0 to use multicast queues and 1 to use unicast queues.
  */
 #define spn_LB_PORT_USE_UC_QUEUES  "lb_port_use_uc_queues"
 /*
  * Disable loading of ingress field default programs.
  * Used with following suffixes:
  * _raw
  *     Program is used when tm_port_header_type is RAW/DSA_RAW/RAW_DSA/TDM_RAW
  * _xgs
  *     Program is used when tm_port_header_type is XGS_HQoS/XGS_DiffServ
  * _stack
  *     Program is used when tm_port_header_type is TDM/STACKING
  * _prog
  *     Program is used when tm_port_header_type is PROG
  * _mirror_raw
  *     Program is used when tm_port_header_type is MIRROR_RAW
  */
 #define spn_FIELD_INGRESS_DEFAULT_PGM_LOAD_DISABLE  "field_ingress_default_pgm_load_disable"
 /*
  * enable In-band Flow Analyzer embedded app
  * default value: 0 (disabled)
  */
 #define spn_IFA_ENABLE  "ifa_enable"
 /*
  * Turn on/off DLB flow monitoring. When set to a non-zero value, DLB flow
  * monitoring feature is enabled. DLB id of 0 is not available when DLB
  * monitoring is enabled.
  * Currently supported on BCM5698x only.
  * Valid values are: 0 (disabled) or non-zero (enabled).
  * Default value is 0 (disabled)
  */
 #define spn_DLB_FLOW_MONITOR_EN  "dlb_flow_monitor_en"
 
 /* VLAN reserved for MACSEC OLP use only.  */
 #define spn_XFLOW_MACSEC_OLP_VLAN  "xflow_macsec_olp_vlan"
 
 /*  Enable/Disable seamless BFD feature support (RFC7880).By default, it is disabled  */
 #define spn_SEAMLESS_BFD_ENABLE  "seamless_bfd_enable"
 
 /*  This soc property will be used to define the rcy port which will be used in SBFD reflector. In case of dual cored device (Jericho) the soc property should be used with suffix: sbfd_rcy_port_0 for core 0, sbfd_rcy_port_1 for core 1  */
 #define spn_SBFD_RCY_PORT  "sbfd_rcy_port"
 /*
  * Maximum size of the packet sent by telemetry application.
  * default value: 1500 bytes
  */
 #define spn_TELEMETRY_EXPORT_MAX_PACKET_SIZE  "telemetry_export_max_packet_size"
 /*
  * enable Telemetry embedded app
  * default value: 0 (disabled)
  */
 #define spn_TELEMETRY_ENABLE  "telemetry_enable"
 /*
  * Enable Tomahawk3-like L3/MPLS failover (protection switching)
  * with fixed next hop offset from primary NH on EGR_L3_NEXT_HOP table.
  * Set value 1 to enabled the feature and half of EGR_L3_NEXT_HOP is
  * reserved for possible failover usage.
  * Default value is 0 which disable the fixed next hop offset failover.
  */
 #define spn_FAILOVER_FIXED_NH_OFFSET_ENABLE  "failover_fixed_nh_offset_enable"
 /*
  * Enable grouping of different flex stat attributes together as a class
  * Default value is 0 which disables this feature.
  */
 #define spn_FLEX_STAT_ATTRIBUTES_CLASS  "flex_stat_attributes_class"
 /*
  * Enable INT Turnaround embedded app
  * default value: 0 (disabled)
  */
 #define spn_INT_TURNAROUND_ENABLE  "int_turnaround_enable"
 /*
  * enable Chip debug functionality. The counters for multiple
                similar objects will be counted together across the chip.
  * default value: 0 (disabled)
  */
 #define spn_FLOWTRACKER_CHIP_DEBUG_ENABLE  "flowtracker_chip_debug_enable"
 /*
  * Indicates whether VRRP scaling is enabled/disabled
  * default value: 0 (disabled)
  */
 #define spn_VRRP_SCALING_TCAM  "vrrp_scaling_tcam"
 /*
  * Indicates what size of TCAM banks is allocated for VRRP (0 = any, 1 = small, 2 = big)
  * default value: 0 (disabled)
  */
 #define spn_USE_SMALL_BANKS_MODE_VRRP  "use_small_banks_mode_vrrp"
 /*
  * This soc property is used to disable the mirror copy counting on all pool nums
  * To disable a specific pool num, use the suffix "_poolx". x represents the pool num
  * default value is 0 (mirror copy counting is enabled).
  */
 #define spn_MIRROR_COPY_COUNTING_DISABLE  "mirror_copy_counting_disable"
 /*
  * Enable SUM embedded app
  * default value: 0 (disabled)
  */
 #define spn_SUM_ENABLE  "sum_enable"
 
 /* Export interval of the active flows in seconds */
 #define spn_FLOWTRACKER_EXPORT_INTERVAL_SECS  "flowtracker_export_interval_secs"
 /*
  * ALPM Level3 bank usage threshold when bucket defragmentation or expansion
  * is required during insert. Return FULL if exceeds this threshold.
  * Default value is 95 percent.
  */
 #define spn_L3_ALPM2_BNK_THRESHOLD  "l3_alpm2_bnk_threshold"
 /*
  * This soc property is used to disable IP-EP clock gating for BCM5677x devices
  * This needs to be set if visibility feature is being used
  * Example:
  * ipep_clock_gating_disable=0 -> Default, enables clock gating during init for power saving
  * ipep_clock_gating_disable=1 -> Disables IPEP clock gating during init, MUST for visibility feature.
  */
 #define spn_IPEP_CLOCK_GATING_DISABLE  "ipep_clock_gating_disable"
 /*
  * LC_PLL clock source selection.
  * Usage : lc_pll_ext_clock.X=Y
  * X is the index number of LC_PLL pin. For LC_PLL0, X is ignored.
  * Y is the property value. Default value 0 means the source is from internal.
  * Nonzero value means the source is from external and specifies the frequency
  * in MHz. The supported external clock source frequency depends on chip design.
  */
 #define spn_LC_PLL_EXT_CLOCK  "lc_pll_ext_clock"
 /*
  * This property is used to enable or disable a special mode that will pause L2
  * hardware learning when tables are being written, and resume learning after
  * table write operation completes.
  * This is only applicable when OAM is enabled.
  * 0 (Disable) - Do not pause L2 hardware learning when any tables are being written.
  * 1 (Enable) - To pause L2 hardware learning when tables are being written.
  */
 #define spn_OAM_PAUSE_L2_LEARN_ON_TABLE_WRITE  "oam_pause_l2_learn_on_table_write"
 /*
  * Enable INT Turnaround embedded app
  * default value: 0 (disabled)
  */
 #define spn_INT_TURNAROUND_ENABLE  "int_turnaround_enable"
 /*
  * enable Chip debug functionality. The counters for multiple
                similar objects will be counted together across the chip.
  * default value: 0 (disabled)
  */
 #define spn_FLOWTRACKER_CHIP_DEBUG_ENABLE  "flowtracker_chip_debug_enable"
 /*
  * Map outlif logical phase to physical phase.
  * The suffix for this property is the logical phase, and the value is the physical phase.
  * Every logical phase and every physical phase must be configured.
  */
 #define spn_OUTLIF_LOGICAL_TO_PHYSICAL_PHASE_MAP  "outlif_logical_to_physical_phase_map"
 
 /* Dram tuning mode during init */
 #define spn_DRAM_PHY_TUNE_MODE_ON_INIT  "dram_phy_tune_mode_on_init"
 
 /* command address parity */
 #define spn_EXT_RAM_COMMAND_ADDRESS_PARITY  "ext_ram_command_address_parity"
 
 /* dq write parity */
 #define spn_EXT_RAM_DQ_WRITE_PARITY  "ext_ram_dq_write_parity"
 
 /* dq read parity */
 #define spn_EXT_RAM_DQ_READ_PARITY  "ext_ram_dq_read_parity"
 
 /* read latency */
 #define spn_EXT_RAM_READ_LATENCY  "ext_ram_read_latency"
 
 /* bitmap that represents enabled Drams */
 #define spn_EXT_RAM_ENABLED_BITMAP  "ext_ram_enabled_bitmap"
 
 /* Read To Write command delay */
 #define spn_EXT_RAM_T_RTW  "ext_ram_t_rtw"
 
 /* RD SID A to RD SID B command delay */
 #define spn_EXT_RAM_T_CCD_R  "ext_ram_t_ccd_r"
 
 /* write latency */
 #define spn_EXT_RAM_WRITE_LATENCY  "ext_ram_write_latency"
 
 /* parity latency */
 #define spn_EXT_RAM_PARITY_LATENCY  "ext_ram_parity_latency"
 
 /* path to file containing deleted buffers */
 #define spn_DELETED_BUFFERS_FILE_PATH  "deleted_buffers_file_path"
 /*
  * max number of members in trunk group
  * possible suffix is pool nubmer
  */
 #define spn_TRUNK_GROUP_MAX_MEMBERS  "trunk_group_max_members"
 /*
  * The MDB profile controls the allocation of HW resources to different tables.
  * Supported profiles: Default, Default-Per, MAX L2, MAX L3, L2L3 VPN, ROO, Transport.
  */
 #define spn_MDB_PROFILE  "mdb_profile"
 /*
  * The KAPS A size.
  * The ratio between this value and mdb_kaps_b_size determines the allocation of dynamic resources available to the KAPS in MDB.
  */
 #define spn_MDB_KAPS_A_SIZE  "mdb_kaps_a_size"
 /*
  * The KAPS B size.
  * The ratio between this value and mdb_kaps_a_size determines the allocation of dynamic resources available to the KAPS in MDB.
  */
 #define spn_MDB_KAPS_B_SIZE  "mdb_kaps_b_size"
 /*
  * Set of values defined by the suffix, which gather the HBM tuning data
  * Used to restore Hbm Tuning Values
  */
 #define spn_HBM_TUNE  "hbm_tune"
 /*
  * The number of allowed errors a single buffer can have before being deleted by the Quarantine Mechanism
  * Value of 0 means that a buffer will never be deleted - the Quarantine Mechanism is deactivated
  */
 #define spn_QUARANTINE_MECHANISM_ALLOWED_ERRORS  "quarantine_mechanism_allowed_errors"
 
 /* Number of values to allocate for egress in_lif_profile attribute */
 #define spn_IN_LIF_PROFILE_EGRESS_ALLOCATE  "in_lif_profile_egress_allocate"
 /*
  * The way the protocol traps are doing the indexing in the protocol prifle table.
  * Valid values:
  * IN_LIF:  Use IN_LIF as the indexing for the protocol trap table.
  * IN_PORT: Use IN_PORT as the indexing for the protocol trap table.
  */
 #define spn_PROTOCOL_TRAPS_MODE  "protocol_traps_mode"
 
 /* Enable/disable SDK DRAM temperature monitor */
 #define spn_DRAM_TEMPERATURE_MONITOR_ENABLE  "dram_temperature_monitor_enable"
 
 /* Dram temperature restore traffic threshold. When going below this temperature, the traffic redirect to the DRAM */
 #define spn_DRAM_TEMPERATURE_THRESHOLD_RESTORE_TRAFFIC  "dram_temperature_threshold_restore_traffic"
 
 /* Dram temperature stop traffic threshold. When going beyond this temperature, SDK stop redirect traffic to the DRAM */
 #define spn_DRAM_TEMPERATURE_THRESHOLD_STOP_TRAFFIC  "dram_temperature_threshold_stop_traffic"
 
 /* Dram temperature power down threshold. When going beyond this temperature, DRAM is shut down */
 #define spn_DRAM_TEMPERATURE_THRESHOLD_POWER_DOWN  "dram_temperature_threshold_power_down"
 
 /* Enable external IPv4 forwarding appl. */
 #define spn_EXT_IPV4_FWD_ENABLE  "ext_ipv4_fwd_enable"
 
 /* Enable external IPv6 forwarding appl. */
 #define spn_EXT_IPV6_FWD_ENABLE  "ext_ipv6_fwd_enable"
 /*
  * Decide which PMF stage will have access to SEXEM3.
  * Valid values:
  * IPMF2:  Ingress PMF 2 will be able to perform a lookup in EXEM3.
  * IPMF3:  Ingress PMF 3 will be able to perform a lookup in EXEM3.
  */
 #define spn_PMF_SEXEM3_STAGE  "pmf_sexem3_stage"
 
 /* This soc property is used to determine how many bits in the In-Lif profile will be used by PMF */
 #define spn_PMF_IN_LIF_PROFILE_NOF_BITS  "pmf_in_lif_profile_nof_bits"
 
 /* This soc property is used to determine how many bits in the In-Rif profile will be used by PMF */
 #define spn_PMF_IN_RIF_PROFILE_NOF_BITS  "pmf_in_rif_profile_nof_bits"
 /*
  * Assign a data granularity to each outlif physical phase.
  * The suffix for this property is the physical phase, and the value is the data granularity.
  * Valid data granularity values are 30/60/120.
  * Every physical phase must be configured.
  * See related soc property outlif_logical_to_physical_phase_map.
  */
 #define spn_OUTLIF_PHYSICAL_PHASE_DATA_GRANULARITY  "outlif_physical_phase_data_granularity"
 
 /* Do nothing when exit diag shell without "clean" option */
 #define spn_DIAG_SHELL_EXIT_DO_NOTHING  "diag_shell_exit_do_nothing"
 
 /* Maximal bandwidh in Mbits-per-second a single port can have */
 #define spn_MAXIMAL_PORT_BANDWIDTH  "maximal_port_bandwidth"
 
 /* Enable L4 protocols participation in Load Balancing hashing */
 #define spn_L4_PROTOCOLS_LOAD_BALANCING_ENABLE  "l4_protocols_load_balancing_enable"
 /*
  * Select a KAPS database configuration based on the MDB profile.
  * This configuration controls the resource allocation between the two KAPS databases.
  * The minimum value is 1, the maximum value depends on the number of possible allocations based on the MDB profile.
  * See related soc property mdb_profile.
  */
 #define spn_MDB_PROFILE_KAPS_CFG  "mdb_profile_kaps_cfg"
 
 /* Enable/Disable the configuration of using local discriminator  as session ID for BFD
                    endpoints.If the config property is enabled (set to 1), value passed in local_discriminator
                    field in endpoint info will be used as BFD session ID in the FW.
                    The default value of the config property is 0 (disabled). */
 #define spn_BFD_USE_LOCAL_DISCRIMINATOR_AS_SESSION_ID  "bfd_use_local_discriminator_as_session_id"
 
 /* Define the relative path to the ucode txt file, relative to bcm.user executable. default value is the standard_1 ucode */
 #define spn_PROGRAMMABILITY_UCODE_RELATIVE_PATH  "programmability_ucode_relative_path"
 
 /* Define the device image, default value is standard_1 */
 #define spn_PROGRAMMABILITY_IMAGE_NAME  "programmability_image_name"
 /*
  * supported on J2C device.
  * TDM_NONE: no TDM traffic is allowed
  * TDM_OPTIMIZED: TDM BYPASS only traffic mode with an Optimized FTMH Header
  *    format. If set, all the devices this device can
  *    communicate with must be configured with the same mode.
  * TDM_STANDARD: TDM BYPASS only traffic mode with a Standard FTMH Header format.
  *   In this mode, the device can communicate with
  *   devices (other devices should be configured in either TDM_STANDARD or TDM_PACKET mode).
  * TDM_PACKET: TDM PACKET only traffic mode with a Standard FTMH Header format.
  *   In this mode, the device can communicate with
  *   devices (other devices should be configured in either TDM_STANDARD or TDM_PACKET mode).
  */
 #define spn_TDM_MODE  "tdm_mode"
 
 /* PCIE hot swap timeout in microseconds for IDLE/READY condition */
 #define spn_PCIE_HOT_SWAP_TIMEOUT_USEC  "pcie_hot_swap_timeout_usec"
 
 /* Specify the maximum MTU size for PFC optimized groups. */
 #define spn_MMU_PFC_GROUP_OPTIMIZED_MTU_SIZE  "mmu_pfc_group_optimized_mtu_size"
 
 #define BCM_SOC_PROP_NAMES_INITIALIZER \
 { \
   "10g_is_cx4", \
   "20g_oversub_port_flexport_enable", \
   "8865x_ipv4_tunnel_df_enable", \
   "886xx_ipv4_tunnel_dont_fragment", \
   "EAV_DISCOVERY_MASTER", \
   "EAV_DISCOVERY_SRC_MAC", \
   "EAV_SRP_INTERVAL", \
   "EAV_TIMESYNC_DISABLE_PDELAY", \
   "EAV_TIMESYNC_INTERVAL", \
   "EAV_TIMESYNC_MONITOR_PBMP", \
   "EAV_TIMESYNC_SPECIAL_LOOP_PBMP", \
   "L1_backup_clk_recovery_port", \
   "L1_primary_clk_recovery_port", \
   "PPPoE_mode", \
   "RFC2544_reflector_mac_and_ip_swap_port", \
   "RFC2544_reflector_mac_swap_port", \
   "SRP_ACK_AGING_ON", \
   "action_type_signature_stamping", \
   "add_ptch2_header", \
   "alpm_flex_stat_support", \
   "ancillary_bandwidth_mode", \
   "app_queues_num", \
   "app_queues_start", \
   "appl_enable", \
   "appl_param", \
   "arad_20mhz_bs", \
   "arl_clean_timeout_usec", \
   "arl_rate_limit", \
   "arl_resync_delay", \
   "asf_mem_profile", \
   "auto_enable_mac_low_power", \
   "backplane_serdes_encoding", \
   "bcm53400_init_port_config", \
   "bcm5614x_config", \
   "bcm5614x_hypercore_mixed_mode", \
   "bcm5615x_config", \
   "bcm5616x_init_port_config", \
   "bcm5626x_config", \
   "bcm5627x_config", \
   "bcm5632_mode", \
   "bcm56333_pbmp_ge_linerate", \
   "bcm56340_2x10", \
   "bcm56340_4x10", \
   "bcm56340_config", \
   "bcm56344_2x10", \
   "bcm56345_2x21", \
   "bcm56345_4X10_2x21", \
   "bcm56346_4X10_2x21", \
   "bcm5644x_config", \
   "bcm5645x_config", \
   "bcm56521_2x12_2x24", \
   "bcm56524_2x12_2x24", \
   "bcm56526_2x12_4x16", \
   "bcm56534_2x12_2x24", \
   "bcm56538_48g_2x24", \
   "bcm56538_48g_4x12", \
   "bcm56540_4x10_2x42", \
   "bcm56540_8x10", \
   "bcm56542_2x10_2x42_2x21", \
   "bcm56544_10x10_2x42", \
   "bcm56544_10x10_4x10", \
   "bcm56544_4x10_12x10", \
   "bcm56545_1x40_2x42", \
   "bcm56545_24g", \
   "bcm56545_4x11_2x42", \
   "bcm56545_4x11_4x42", \
   "bcm56547_2x42", \
   "bcm56547_3x42", \
   "bcm56629_40ge", \
   "bcm56630_2x12_2x24", \
   "bcm56634_48g_2x24", \
   "bcm56634_48g_4x12", \
   "bcm56636_24g_6x12", \
   "bcm56636_2x12_2x24", \
   "bcm56638_4x12_2x24", \
   "bcm56638_8x12", \
   "bcm56639_28g_7x10", \
   "bcm56640_1x100_1x127", \
   "bcm56640_1x100_3x42", \
   "bcm56640_1x100_4x32", \
   "bcm56640_1x100_8x16", \
   "bcm56640_1x40_4x42", \
   "bcm56640_3x40_2x42", \
   "bcm56640_3x40_3x42", \
   "bcm56640_3x42_1x127", \
   "bcm56640_3x42_2x40", \
   "bcm56640_3x42_3x40", \
   "bcm56640_3x42_4x32", \
   "bcm56640_3x42_8x16", \
   "bcm56640_4x10_1x127", \
   "bcm56640_4x10_4x42", \
   "bcm56640_8x10", \
   "bcm56640_config", \
   "bcm56643_4x10_4x42", \
   "bcm56644_24g", \
   "bcm5664x_wrr_granularity_1", \
   "bcm56725_16x16", \
   "bcm56821_20x12", \
   "bcm56822_8x16", \
   "bcm56840_config", \
   "bcm56849_56x2point5_8x10", \
   "bcm56972_riot_32x100", \
   "bcm8823x_2x20_2x20_1", \
   "bcm8823x_2x24_1", \
   "bcm8823x_2x24_2x20_1", \
   "bcm8823x_4x10_2x20_1", \
   "bcm8823x_4x11_1x11_1x25", \
   "bcm8823x_4x11_1x12_1x24", \
   "bcm8823x_4x11_1x25_1x11", \
   "bcm8823x_4x11_2x18", \
   "bcm8823x_4x20_1", \
   "bcm88660_1588_48b_stamping_enable", \
   "bcm886xx_auxiliary_table_mode", \
   "bcm886xx_egress_protection_coupled_mode", \
   "bcm886xx_erspan_tunnel_enable", \
   "bcm886xx_ether_ip_enable", \
   "bcm886xx_fcoe_max_routes", \
   "bcm886xx_fcoe_num_vrf", \
   "bcm886xx_fcoe_switch_mode", \
   "bcm886xx_fec_accelerated_reroute_mode", \
   "bcm886xx_ingress_protection_coupled_mode", \
   "bcm886xx_intra_dc_router_enable", \
   "bcm886xx_ip4_tunnel_encapsulation_mode", \
   "bcm886xx_ip4_tunnel_termination_mode", \
   "bcm886xx_ip6_tunnel_encapsulation_mode", \
   "bcm886xx_ip6_tunnel_termination_mode", \
   "bcm886xx_ipv4_slice1_size", \
   "bcm886xx_ipv4_slice2_size", \
   "bcm886xx_ipv4_slice3_size", \
   "bcm886xx_ipv4_slice4_size", \
   "bcm886xx_ipv4_slice5_size", \
   "bcm886xx_ipv4_slice6_size", \
   "bcm886xx_ipv6_ext_hdr_enable", \
   "bcm886xx_ipv6_tunnel_enable", \
   "bcm886xx_l2gre_enable", \
   "bcm886xx_l2gre_tunnel_lookup_mode", \
   "bcm886xx_l2gre_vpn_lookup_mode", \
   "bcm886xx_l3_ingress_urpf_enable", \
   "bcm886xx_logical_interface_bridge_filter_enable", \
   "bcm886xx_logical_interface_same_filter_enable", \
   "bcm886xx_mpls_termination_database_mode", \
   "bcm886xx_mpls_termination_key_mode", \
   "bcm886xx_next_hop_mac_extension_enable", \
   "bcm886xx_oam_default_profile", \
   "bcm886xx_oam_default_profile_egress", \
   "bcm886xx_ocb_databuffer_size", \
   "bcm886xx_ocb_enable", \
   "bcm886xx_ocb_repartition", \
   "bcm886xx_pdm_mode", \
   "bcm886xx_port_extend_p2p", \
   "bcm886xx_pph_learn_extension_disable", \
   "bcm886xx_qos_l3_l2_marking", \
   "bcm886xx_roo_enable", \
   "bcm886xx_roo_host_arp_msbs", \
   "bcm886xx_rspan_tunnel_enable", \
   "bcm886xx_rx_use_hw_trap_id", \
   "bcm886xx_vlan_translate_mode", \
   "bcm886xx_vxlan_enable", \
   "bcm886xx_vxlan_tunnel_lookup_mode", \
   "bcm886xx_vxlan_vpn_lookup_mode", \
   "bcm88732_1x40_4x10", \
   "bcm88732_1x40_4x10_8x12", \
   "bcm88732_2x40_1x40", \
   "bcm88732_2x40_2x40", \
   "bcm88732_2x40_2x40E", \
   "bcm88732_2x40_8x10", \
   "bcm88732_2x40_8x12", \
   "bcm88732_4x10_1x40_8x12", \
   "bcm88732_4x10_4x10", \
   "bcm88732_6x10_2x12", \
   "bcm88732_8x10_1x40", \
   "bcm88732_8x10_2x12", \
   "bcm88732_8x10_2x40", \
   "bcm88732_8x10_4x12", \
   "bcm88732_8x10_8x10", \
   "bcm88732_8x10_8x12", \
   "bcm88732_device_mode", \
   "bcm88732_use_oob", \
   "bcm88xxx_system_resource_management", \
   "bcm_esw_pscan_thread_pri", \
   "bcm_filter_clear_fe", \
   "bcm_filter_clear_ge", \
   "bcm_filter_clear_xe", \
   "bcm_ft_report_thread_pri", \
   "bcm_linkscan_errdelay", \
   "bcm_linkscan_interval", \
   "bcm_linkscan_maxerr", \
   "bcm_linkscan_pbmp", \
   "bcm_meter_clear_fe", \
   "bcm_meter_clear_ge", \
   "bcm_meter_clear_xe", \
   "bcm_num_cos", \
   "bcm_oam_thread_pri", \
   "bcm_rate_bcast_index", \
   "bcm_rate_dlf_index", \
   "bcm_rate_mcast_index", \
   "bcm_rate_unknown_mcast_index", \
   "bcm_rx_thread_pri", \
   "bcm_stat_flags", \
   "bcm_stat_interval", \
   "bcm_stat_jumbo", \
   "bcm_stat_pbmp", \
   "bcm_stat_sync_timeout", \
   "bcm_tdm_frequency", \
   "bcm_tdm_io_bandwidth", \
   "bcm_tunnel_term_compatible_mode", \
   "bcm_tx_thread_pri", \
   "bcm_xlate_api_port_enable", \
   "bcm_xlate_port", \
   "bcm_xlate_port_enable", \
   "bcm_xlate_port_map", \
   "bcm_xlate_sysport_enable", \
   "bfd_control_plane_independence", \
   "bfd_cosq", \
   "bfd_echo_enabled", \
   "bfd_enable", \
   "bfd_encap_memory_size", \
   "bfd_encapsulation_mode", \
   "bfd_extended_ipv4_src_ip", \
   "bfd_feature_enable", \
   "bfd_ipv4_single_hop_extended", \
   "bfd_ipv6_enable", \
   "bfd_ipv6_source_cpu_port", \
   "bfd_ipv6_trap_port", \
   "bfd_mask_flags_bitfield", \
   "bfd_num_sessions", \
   "bfd_remote_discriminator", \
   "bfd_session_down_event_on_create", \
   "bfd_sha1_keys", \
   "bfd_simple_password_keys", \
   "bfd_supported_flags_bitfield", \
   "bfd_thread_pri", \
   "bfd_use_endpoint_id_as_discriminator", \
   "bfd_use_local_discriminator_as_session_id", \
   "bhh_base_endpoint_id", \
   "bhh_base_group_id", \
   "bhh_carrier_code", \
   "bhh_consolidated_final_event", \
   "bhh_cosq", \
   "bhh_data_collection_mode", \
   "bhh_encap_max_length", \
   "bhh_lm_dm_enable", \
   "bhh_node_id", \
   "bhh_num_lm_enabled_section_meps", \
   "bhh_num_sessions", \
   "bhh_pm_raw_data_buffers", \
   "bhh_thread_pri", \
   "bhh_udf_mode", \
   "bier_nof_bfr_entries", \
   "bist_enable", \
   "bist_timeout_msec", \
   "block_trap_strength", \
   "board_flags", \
   "board_name", \
   "broadsync_enable_clk", \
   "bs_poll_interval", \
   "bst_sync_thread_pri", \
   "buf", \
   "buffer_stats_collect_mode", \
   "buffer_stats_collect_type", \
   "bypass_mcu", \
   "cable_diag_hw", \
   "caui_num_lanes", \
   "caui_rx_clock_recovery_lane", \
   "cb_abort_on_err", \
   "ccm_dma_enable", \
   "ccmdma_intr_enable", \
   "ccmdma_timeout_usec", \
   "cdma_pio_hold_enable", \
   "cdma_timeout_usec", \
   "ces_common_ref_clock_rate", \
   "ces_disable", \
   "ces_ipv4_address", \
   "ces_ipv6_address", \
   "ces_mii_mac", \
   "ces_mii_port_number", \
   "ces_pll_reference_clock_rate", \
   "ces_port_tdm_proto", \
   "ces_system_clock_rate", \
   "cfap_tests", \
   "cmc", \
   "cmic_egress_dqueue", \
   "cmic_egress_squeue", \
   "cmic_ingress_dqueue", \
   "cmic_ingress_squeue", \
   "color_discard_enable", \
   "combo28_tune_aq_l_macro_reserved_reg", \
   "combo28_tune_aq_l_max_vdl_addr", \
   "combo28_tune_aq_l_max_vdl_ctrl", \
   "combo28_tune_aq_u_macro_reserved_reg", \
   "combo28_tune_aq_u_max_vdl_addr", \
   "combo28_tune_aq_u_max_vdl_ctrl", \
   "combo28_tune_common_macro_reserved_reg", \
   "combo28_tune_control_regs_edcen_fifo_central_init", \
   "combo28_tune_control_regs_input_shift_ctrl", \
   "combo28_tune_control_regs_read_clock_config", \
   "combo28_tune_control_regs_ren_fifo_central_initializer", \
   "combo28_tune_control_regs_reserved_reg", \
   "combo28_tune_control_regs_shared_vref_dac_config", \
   "combo28_tune_dq_edcen_fifo_config", \
   "combo28_tune_dq_macro_reserved_reg", \
   "combo28_tune_dq_rd_max_vdl_dqsn", \
   "combo28_tune_dq_rd_max_vdl_dqsp", \
   "combo28_tune_dq_rd_min_vdl", \
   "combo28_tune_dq_rd_min_vdl_dbi", \
   "combo28_tune_dq_rd_min_vdl_edc", \
   "combo28_tune_dq_read_max_vdl_fsm", \
   "combo28_tune_dq_ren_fifo_config", \
   "combo28_tune_dq_vref_dac_config", \
   "combo28_tune_dq_wr_max_vdl_data", \
   "combo28_tune_dq_wr_max_vdl_dqs", \
   "combo28_tune_dq_wr_min_vdl", \
   "combo28_tune_dq_wr_min_vdl_dbi", \
   "combo28_tune_dq_wr_min_vdl_edc", \
   "combo_nif", \
   "combo_ref_clock", \
   "config_queue", \
   "congestion_point_mode", \
   "core_clock_12G", \
   "core_clock_frequency", \
   "core_clock_speed", \
   "cos_list", \
   "cos_mode", \
   "cosq_admission_preference", \
   "cosq_control_burst_node_select", \
   "counter_engine_format", \
   "counter_engine_map_drop_black_offset", \
   "counter_engine_map_drop_green_offset", \
   "counter_engine_map_drop_red_offset", \
   "counter_engine_map_drop_yellow_offset", \
   "counter_engine_map_enable", \
   "counter_engine_map_fwd_black_offset", \
   "counter_engine_map_fwd_green_offset", \
   "counter_engine_map_fwd_red_offset", \
   "counter_engine_map_fwd_yellow_offset", \
   "counter_engine_map_size", \
   "counter_engine_replicated_packets", \
   "counter_engine_sampling_interval", \
   "counter_engine_source", \
   "counter_engine_stag_low_bit", \
   "counter_engine_statistics", \
   "counter_engine_voq_min_queue", \
   "counter_engine_voq_queue_set_size", \
   "counter_evict_entries_max", \
   "counter_evict_hostbuf_size", \
   "counter_evict_thread_pri", \
   "counter_thread_pri", \
   "cpri_port_init_speed_id", \
   "credit_size", \
   "credit_worth_resolution", \
   "custom_feature", \
   "cx4_to_higig", \
   "dcb_intr_mitigate_enable", \
   "ddr3_auto_tune", \
   "ddr3_bank_unavail_rd", \
   "ddr3_bank_unavail_wr", \
   "ddr3_clock_mhz", \
   "ddr3_mem_grade", \
   "ddr3_pll_mhz", \
   "ddr3_refresh_intvl_override", \
   "ddr3_round_robin_read", \
   "ddr3_round_robin_write", \
   "ddr3_tread_enb", \
   "ddr3_trp_read", \
   "ddr3_trp_write", \
   "ddr3_tune_addrc", \
   "ddr3_tune_ctrl_vdl_ad00", \
   "ddr3_tune_ctrl_vdl_ad04", \
   "ddr3_tune_ctrl_vdl_ad08", \
   "ddr3_tune_ctrl_vdl_ad12", \
   "ddr3_tune_ctrl_vdl_aux", \
   "ddr3_tune_ctrl_vdl_ba", \
   "ddr3_tune_ctrl_vdl_cas_n", \
   "ddr3_tune_ctrl_vdl_cke", \
   "ddr3_tune_ctrl_vdl_cs", \
   "ddr3_tune_ctrl_vdl_odt", \
   "ddr3_tune_ctrl_vdl_par", \
   "ddr3_tune_ctrl_vdl_ras_n", \
   "ddr3_tune_ctrl_vdl_rst_n", \
   "ddr3_tune_ctrl_vdl_we_n", \
   "ddr3_tune_ctrl_vref_dac", \
   "ddr3_tune_rd_control", \
   "ddr3_tune_rd_data_dly", \
   "ddr3_tune_rd_dq_wl0_rn", \
   "ddr3_tune_rd_dq_wl0_rp", \
   "ddr3_tune_rd_dq_wl1_rn", \
   "ddr3_tune_rd_dq_wl1_rp", \
   "ddr3_tune_rd_dqs", \
   "ddr3_tune_rd_en", \
   "ddr3_tune_rd_en_dly_cyc", \
   "ddr3_tune_rd_en_vdl_cs0", \
   "ddr3_tune_rd_en_vdl_cs1", \
   "ddr3_tune_rd_vdl_dmn", \
   "ddr3_tune_rd_vdl_dmp", \
   "ddr3_tune_rd_vdl_dqn0_bl0", \
   "ddr3_tune_rd_vdl_dqn0_bl1", \
   "ddr3_tune_rd_vdl_dqn0_bl2", \
   "ddr3_tune_rd_vdl_dqn0_bl3", \
   "ddr3_tune_rd_vdl_dqn4_bl0", \
   "ddr3_tune_rd_vdl_dqn4_bl1", \
   "ddr3_tune_rd_vdl_dqn4_bl2", \
   "ddr3_tune_rd_vdl_dqn4_bl3", \
   "ddr3_tune_rd_vdl_dqp0_bl0", \
   "ddr3_tune_rd_vdl_dqp0_bl1", \
   "ddr3_tune_rd_vdl_dqp0_bl2", \
   "ddr3_tune_rd_vdl_dqp0_bl3", \
   "ddr3_tune_rd_vdl_dqp4_bl0", \
   "ddr3_tune_rd_vdl_dqp4_bl1", \
   "ddr3_tune_rd_vdl_dqp4_bl2", \
   "ddr3_tune_rd_vdl_dqp4_bl3", \
   "ddr3_tune_rd_vdl_dqsn", \
   "ddr3_tune_rd_vdl_dqsp", \
   "ddr3_tune_vref", \
   "ddr3_tune_wr_chan_dly_cyc", \
   "ddr3_tune_wr_dq", \
   "ddr3_tune_wr_dq_wl0", \
   "ddr3_tune_wr_dq_wl1", \
   "ddr3_tune_wr_vdl_dm", \
   "ddr3_tune_wr_vdl_dq0_bl0", \
   "ddr3_tune_wr_vdl_dq0_bl1", \
   "ddr3_tune_wr_vdl_dq0_bl2", \
   "ddr3_tune_wr_vdl_dq0_bl3", \
   "ddr3_tune_wr_vdl_dq4_bl0", \
   "ddr3_tune_wr_vdl_dq4_bl1", \
   "ddr3_tune_wr_vdl_dq4_bl2", \
   "ddr3_tune_wr_vdl_dq4_bl3", \
   "ddr3_tune_wr_vdl_dqsn", \
   "ddr3_tune_wr_vdl_dqsp", \
   "ddr3_tune_wr_vdl_edc", \
   "ddr72_dll90_offset0_qk", \
   "ddr72_dll90_offset1", \
   "ddr72_dll90_offset2", \
   "ddr72_dll90_offset3", \
   "ddr72_dll90_offset_qkb", \
   "ddr72_dll90_offset_tx", \
   "ddr72_ovrd_sm_en", \
   "ddr72_phase_sel", \
   "ddr72_sel_early1_0", \
   "ddr72_sel_early1_1", \
   "ddr72_sel_early1_2", \
   "ddr72_sel_early1_3", \
   "ddr72_sel_early2_0", \
   "ddr72_sel_early2_1", \
   "ddr72_sel_early2_2", \
   "ddr72_sel_early2_3", \
   "ddr_train_num_addrs", \
   "default_logical_interface_ip_tunnel_overlay_mc", \
   "default_logical_interface_mpls_1_label_bud_multicast", \
   "default_logical_interface_mpls_2_labels_bud_multicast", \
   "default_logical_interface_mpls_termination_explicit_null", \
   "default_logical_interface_out_ech", \
   "default_snoop_strength", \
   "default_trap_strength", \
   "defip_cam_tm", \
   "deleted_buffers_file_path", \
   "device", \
   "device_core_mode", \
   "device_eb_vli", \
   "device_headroom_enable", \
   "device_tm_domain", \
   "diag_assign_sysport", \
   "diag_chassis", \
   "diag_comma", \
   "diag_cosq_init", \
   "diag_disable_interrupts", \
   "diag_easy_reload", \
   "diag_emulator_partial_init", \
   "diag_hg_as_ge", \
   "diag_hg_as_xe", \
   "diag_l2_disable", \
   "diag_lb_fill_rx", \
   "diag_lb_packet_timeout", \
   "diag_nodes_mask", \
   "diag_pw_buffer_size", \
   "diag_pw_thread_pri", \
   "diag_serdes_mask", \
   "diag_shell_exit_do_nothing", \
   "diag_shell_use_slam", \
   "diag_slave_fc", \
   "diag_slot", \
   "diag_tabs", \
   "disable_lag_otm_check", \
   "discard_enable", \
   "discard_mtu_size", \
   "dlb_flow_monitor_en", \
   "dlb_hgt_lag_selection", \
   "dma_abort_timeout_usec", \
   "dma_desc_aggregator_buff_size_kb", \
   "dma_desc_aggregator_chain_length_max", \
   "dma_desc_aggregator_enable_specific", \
   "dma_desc_aggregator_timeout_usec", \
   "dma_desc_intr_enable", \
   "dma_desc_timeout_usec", \
   "dmac_pyld_percent", \
   "dpll_params", \
   "dport_map_direct", \
   "dport_map_enable", \
   "dport_map_indexed", \
   "dport_map_port", \
   "dpp_clock_ratio", \
   "dpr_clock_frequency", \
   "dram0_clamshell_enable", \
   "dram1_clamshell_enable", \
   "dram_auto_calibration_update_enable", \
   "dram_crc_del_buffer_max_reclaims", \
   "dram_phy_tune_mode_on_init", \
   "dram_temperature_monitor_enable", \
   "dram_temperature_threshold_power_down", \
   "dram_temperature_threshold_restore_traffic", \
   "dram_temperature_threshold_stop_traffic", \
   "dtm_flow_mapping_mode_region", \
   "dtm_flow_nof_remote_cores_region", \
   "dtm_queue_mapping_mode_region", \
   "dual_hash_recurse_depth", \
   "dual_hash_recurse_depth_dnat_pool", \
   "dual_hash_recurse_depth_egr_vp_vlan_member", \
   "dual_hash_recurse_depth_egress_vlan", \
   "dual_hash_recurse_depth_ing_vp_vlan_member", \
   "dual_hash_recurse_depth_l2x", \
   "dual_hash_recurse_depth_l3x", \
   "dual_hash_recurse_depth_mpls", \
   "dual_hash_recurse_depth_vlan", \
   "dual_imp_enable", \
   "e2e_64_modules", \
   "eb2_2bytes_big_endian", \
   "eb2_2bytes_big_endian", \
   "ecmp_resilient_hash_size", \
   "ecn_dm_enable", \
   "eedb_defrag_enable", \
   "efp_cam_tm", \
   "egr_counter_percent", \
   "egr_mc_16k_groups", \
   "egr_share_flex_counter_pool", \
   "egr_vlan_xlate_1_mem_entries", \
   "egr_vlan_xlate_2_mem_entries", \
   "egr_vlan_xlate_mem_banks", \
   "egr_vlan_xlate_mem_entries", \
   "egress_acl_two_pass_enable", \
   "egress_bubble_qid", \
   "egress_drop_thres_de1", \
   "egress_drop_thres_de2", \
   "egress_encap_bank_phase", \
   "egress_encap_ip_tunnel_range_max", \
   "egress_encap_ip_tunnel_range_min", \
   "egress_fabric_drop_threshold_all", \
   "egress_fabric_drop_threshold_all_except_tdm", \
   "egress_fabric_drop_threshold_multicast", \
   "egress_fabric_drop_threshold_multicast_low", \
   "egress_hysteresis_delta", \
   "egress_max_pages", \
   "egress_membership_mode", \
   "egress_multicast_direct_bitmap_max", \
   "egress_multicast_direct_bitmap_min", \
   "egress_object_mac_da_replace", \
   "egress_queue", \
   "egress_shared_resources_mode", \
   "egress_to_ingress_redirect_qid0", \
   "egress_to_ingress_redirect_qid1", \
   "embedded_nh_vp_support", \
   "emulation_regs", \
   "enhanced_fib_scale_prefix_length", \
   "enhanced_fib_scale_prefix_length_ipv6_long", \
   "enhanced_fib_scale_prefix_length_ipv6_short", \
   "enhanced_ser_correction_event_report", \
   "equeue", \
   "esm_recovery_thread_pri", \
   "esm_serdes_driver_current", \
   "esm_serdes_main_tap", \
   "esm_serdes_master_clk_src", \
   "esm_serdes_postcursor_tap", \
   "esm_serdes_pre_driver_current", \
   "esm_serdes_precursor_tap", \
   "esm_serdes_rx_lane_map", \
   "esm_serdes_rx_polarity_flip", \
   "esm_serdes_tx_lane_map", \
   "esm_serdes_tx_polarity_flip", \
   "eth_lm_dm_cosq", \
   "eth_lm_dm_num_sessions", \
   "eth_lmdm_data_collection_mode", \
   "eth_lmdm_pm_raw_data_buffers", \
   "evb_enable", \
   "evpn_enable", \
   "exact_match_tables_shadow_enable", \
   "exc_counter_percent", \
   "ext_1588_mac_enable", \
   "ext_acl160_table_size", \
   "ext_acl320_table_size", \
   "ext_acl480_table_size", \
   "ext_acl80_table_size", \
   "ext_acl_result_size", \
   "ext_ad_mode", \
   "ext_coup_mpls_fwd_table_size", \
   "ext_fwd_algorithm_lpm", \
   "ext_ilkn_reverse", \
   "ext_interface_mode", \
   "ext_ip4_acl_key", \
   "ext_ip4_acl_table_policy_width", \
   "ext_ip4_acl_table_scache_size", \
   "ext_ip4_acl_table_size", \
   "ext_ip4_double_capacity_fwd_table_size", \
   "ext_ip4_fwd_table_size", \
   "ext_ip4_host_fwd_table_size", \
   "ext_ip4_host_wide_fwd_table_size", \
   "ext_ip4_mc_bridge_fwd_table_size", \
   "ext_ip4_mc_fwd_table_size", \
   "ext_ip4_public_fwd_table_size", \
   "ext_ip4_table_duplicated", \
   "ext_ip4_uc_rpf_fwd_table_size", \
   "ext_ip4_uc_rpf_public_fwd_table_size", \
   "ext_ip4c_acl_table_policy_width", \
   "ext_ip4c_acl_table_scache_size", \
   "ext_ip4c_acl_table_size", \
   "ext_ip6_acl_key", \
   "ext_ip6_fwd_key", \
   "ext_ip6_fwd_table_size", \
   "ext_ip6_host_fwd_table_size", \
   "ext_ip6_host_wide_fwd_table_size", \
   "ext_ip6_mc_fwd_table_size", \
   "ext_ip6_public_fwd_table_size", \
   "ext_ip6_table_duplicated", \
   "ext_ip6_uc_rpf_fwd_table_size", \
   "ext_ip6_uc_rpf_public_fwd_table_size", \
   "ext_ip6c_acl_table_policy_width", \
   "ext_ip6c_acl_table_scache_size", \
   "ext_ip6c_acl_table_size", \
   "ext_ip6f_acl_table_policy_width", \
   "ext_ip6f_acl_table_scache_size", \
   "ext_ip6f_acl_table_size", \
   "ext_ip6s_acl_table_policy_width", \
   "ext_ip6s_acl_table_scache_size", \
   "ext_ip6s_acl_table_size", \
   "ext_ip6u_fwd_table_size", \
   "ext_ip6u_table_duplicated", \
   "ext_ipv4_fwd_enable", \
   "ext_ipv6_fwd_enable", \
   "ext_l2_acl_key", \
   "ext_l2_acl_table_policy_width", \
   "ext_l2_acl_table_scache_size", \
   "ext_l2_acl_table_size", \
   "ext_l2_fwd_table_size", \
   "ext_l2_shadow_disable", \
   "ext_l2_table_duplicated", \
   "ext_l2_use_hardware_replace_threshold", \
   "ext_l2_wide_fwd_table_size", \
   "ext_l2c_acl_table_policy_width", \
   "ext_l2c_acl_table_scache_size", \
   "ext_l2c_acl_table_size", \
   "ext_l2ip4_acl_table_master_key_type", \
   "ext_l2ip4_acl_table_policy_width", \
   "ext_l2ip4_acl_table_scache_size", \
   "ext_l2ip4_acl_table_size", \
   "ext_l2ip6_acl_table_master_key_type", \
   "ext_l2ip6_acl_table_policy_width", \
   "ext_l2ip6_acl_table_scache_size", \
   "ext_l2ip6_acl_table_size", \
   "ext_lookup_on_xport", \
   "ext_mpls_fwd_table_size", \
   "ext_phy_autodetect_en", \
   "ext_phy_serdes_fiber_iface", \
   "ext_qdr_pll_m", \
   "ext_qdr_pll_n", \
   "ext_qdr_pll_p", \
   "ext_qdr_protection_type", \
   "ext_qdr_size_mbit", \
   "ext_qdr_type", \
   "ext_qdr_use_core_clock_freq", \
   "ext_ram_abi", \
   "ext_ram_addr_bank_swap", \
   "ext_ram_ap_bit_pos", \
   "ext_ram_auto_tune", \
   "ext_ram_banks", \
   "ext_ram_burst_size", \
   "ext_ram_c_cas_latency", \
   "ext_ram_c_wr_latency", \
   "ext_ram_cmd_par_latency", \
   "ext_ram_cmd_reduced_delay_en", \
   "ext_ram_columns", \
   "ext_ram_command_address_parity", \
   "ext_ram_dbuff_mmc_optimized_distribution_enable", \
   "ext_ram_dbuff_size", \
   "ext_ram_ddr2_emr0_wr1", \
   "ext_ram_ddr2_emr0_wr2", \
   "ext_ram_ddr2_emr0_wr3", \
   "ext_ram_ddr2_emr1_wr1", \
   "ext_ram_ddr2_emr2_wr1", \
   "ext_ram_ddr2_mrs0_wr1", \
   "ext_ram_ddr2_mrs0_wr2", \
   "ext_ram_ddr3_mrs0_wr1", \
   "ext_ram_ddr3_mrs0_wr2", \
   "ext_ram_ddr3_mrs1_wr1", \
   "ext_ram_ddr3_mrs2_wr1", \
   "ext_ram_ddr3_mrs3_wr1", \
   "ext_ram_dq_read_parity", \
   "ext_ram_dq_swap", \
   "ext_ram_dq_write_parity", \
   "ext_ram_enabled_bitmap", \
   "ext_ram_freq", \
   "ext_ram_gddr3_emr0_wr1", \
   "ext_ram_gddr3_mrs0_wr1", \
   "ext_ram_gear_down_mode", \
   "ext_ram_init_wait_period", \
   "ext_ram_jedec", \
   "ext_ram_packet_crc_enable", \
   "ext_ram_parity_latency", \
   "ext_ram_phy_cdr_th_extended_en", \
   "ext_ram_pll_f", \
   "ext_ram_pll_q", \
   "ext_ram_pll_r", \
   "ext_ram_present", \
   "ext_ram_read_crc", \
   "ext_ram_read_dbi", \
   "ext_ram_read_latency", \
   "ext_ram_rows", \
   "ext_ram_t_32aw", \
   "ext_ram_t_al", \
   "ext_ram_t_ccd_l", \
   "ext_ram_t_ccd_r", \
   "ext_ram_t_ccd_s", \
   "ext_ram_t_crc_alert", \
   "ext_ram_t_crc_rd_latency", \
   "ext_ram_t_crc_wr_latency", \
   "ext_ram_t_faw", \
   "ext_ram_t_ras", \
   "ext_ram_t_ras_enable", \
   "ext_ram_t_rc", \
   "ext_ram_t_rcd_rd", \
   "ext_ram_t_rcd_wr", \
   "ext_ram_t_ref", \
   "ext_ram_t_rfc", \
   "ext_ram_t_rp", \
   "ext_ram_t_rrd", \
   "ext_ram_t_rrd_l", \
   "ext_ram_t_rrd_s", \
   "ext_ram_t_rst", \
   "ext_ram_t_rtp", \
   "ext_ram_t_rtp_l", \
   "ext_ram_t_rtp_s", \
   "ext_ram_t_rtw", \
   "ext_ram_t_wr", \
   "ext_ram_t_wtr", \
   "ext_ram_t_wtr_l", \
   "ext_ram_t_wtr_s", \
   "ext_ram_t_zqcs", \
   "ext_ram_total_size", \
   "ext_ram_type", \
   "ext_ram_write_crc", \
   "ext_ram_write_dbi", \
   "ext_ram_write_latency", \
   "ext_sram0_present", \
   "ext_sram1_present", \
   "ext_sram_freq", \
   "ext_sram_mode", \
   "ext_sram_pvt", \
   "ext_sram_speed", \
   "ext_sram_tuning", \
   "ext_sram_tuning2_stats", \
   "ext_sram_tuning_stats", \
   "ext_tcam0_rx_gain", \
   "ext_tcam0_tx_driver_current", \
   "ext_tcam0_tx_main_tap", \
   "ext_tcam0_tx_postcursor_tap", \
   "ext_tcam1_rx_gain", \
   "ext_tcam1_tx_driver_current", \
   "ext_tcam1_tx_main_tap", \
   "ext_tcam1_tx_postcursor_tap", \
   "ext_tcam_banks", \
   "ext_tcam_connect_mode", \
   "ext_tcam_dev_type", \
   "ext_tcam_freq", \
   "ext_tcam_lut_write_mode", \
   "ext_tcam_mode", \
   "ext_tcam_pvt", \
   "ext_tcam_request_response_latency", \
   "ext_tcam_result_size_segment", \
   "ext_tcam_rx_lane_swap", \
   "ext_tcam_serdes_pcie_init", \
   "ext_tcam_serdes_tx_taps", \
   "ext_tcam_sharing_master", \
   "ext_tcam_sharing_slave", \
   "ext_tcam_start_lane", \
   "ext_tcam_tuning", \
   "ext_tcam_tuning_stats", \
   "ext_tcam_tx_lane_swap", \
   "ext_tcam_use_midl", \
   "ext_tp2p_mim_fwd_table_size", \
   "ext_tp2p_mpls_fwd_table_size", \
   "ext_tp2p_vlan_fwd_table_size", \
   "ext_trill_mc_fwd_table_size", \
   "ext_trill_uc_fwd_table_size", \
   "ext_voltage_mode", \
   "extender_control_bridge_enable", \
   "extender_control_bridge_enable", \
   "extender_transit_enable", \
   "extender_transit_enable", \
   "external_header_size", \
   "external_lookup_mal", \
   "extmem", \
   "fabric_cell_fifo_dma_buffer_size", \
   "fabric_cell_fifo_dma_enable", \
   "fabric_cell_fifo_dma_threshold", \
   "fabric_cell_fifo_dma_timeout", \
   "fabric_cell_format", \
   "fabric_client_calendar", \
   "fabric_connect_mode", \
   "fabric_device_mode", \
   "fabric_ftmh_outlif_extension", \
   "fabric_link_fifo_size_mid", \
   "fabric_link_fifo_size_rx", \
   "fabric_link_fifo_size_tx", \
   "fabric_links_to_core_mapping_mode", \
   "fabric_load_balancing_mode", \
   "fabric_local_routing_enable", \
   "fabric_logical_port_base", \
   "fabric_mac_bucket_fill_rate", \
   "fabric_merge_cells", \
   "fabric_mesh_multicast_enable", \
   "fabric_multicast_mode", \
   "fabric_num_pipes", \
   "fabric_optimize_partial_links", \
   "fabric_pcp_enable", \
   "fabric_pipe_map", \
   "fabric_port_calendar", \
   "fabric_port_enable", \
   "fabric_ref_clock", \
   "fabric_segmentation_enable", \
   "fabric_tdm_fragment", \
   "fabric_tdm_over_primary_pipe", \
   "fabric_tdm_priority_min", \
   "failover_fixed_nh_offset_enable", \
   "fap_device_mode", \
   "fap_tdm_bypass", \
   "fap_tdm_packet", \
   "fast_reroute_labels_enable", \
   "fat_pipe_base_port", \
   "fat_pipe_mode", \
   "fat_pipe_num_ports", \
   "fc_calendar_coe_mode", \
   "fc_calendar_e2e_status_nof_entries", \
   "fc_calendar_indication_invert", \
   "fc_calendar_pause_resolution", \
   "fc_coe_calender_length", \
   "fc_coe_data_offset", \
   "fc_coe_ethertype", \
   "fc_coe_mac_address", \
   "fc_egress_xoff_thresh", \
   "fc_enable", \
   "fc_inband_intlkn_calender_length", \
   "fc_inband_intlkn_calender_llfc_mode", \
   "fc_inband_intlkn_calender_rep_count", \
   "fc_inband_intlkn_channel_mub_enable_mask", \
   "fc_inband_intlkn_llfc_mub_enable_mask", \
   "fc_inband_intlkn_mode", \
   "fc_inband_intlkn_type", \
   "fc_inband_mode", \
   "fc_ingress_xoff_thresh", \
   "fc_intlkn_indication_invert", \
   "fc_oob_calender_length", \
   "fc_oob_calender_rep_count", \
   "fc_oob_ilkn_pad_sync_on_data_pin", \
   "fc_oob_mode", \
   "fc_oob_tx_freq_ratio", \
   "fc_oob_type", \
   "fc_spi_indication_invert", \
   "fc_total_buffer_xoff_thresh", \
   "fcmap_dev_addr", \
   "fcmap_enable", \
   "fcmap_port_index", \
   "fcmap_transceiver_host_managed", \
   "fcoe_npv_bridge_mode", \
   "fe_mc_id_range", \
   "fe_mc_priority_map_enable", \
   "field_atomic_update", \
   "field_class_id_size", \
   "field_class_id_size_0", \
   "field_class_id_size_0", \
   "field_class_id_size_1", \
   "field_class_id_size_2", \
   "field_class_id_size_3", \
   "field_egress_enable_ip_acl_on_bridge", \
   "field_ingress_default_pgm_load_disable", \
   "field_ip_first_fragment_parsed", \
   "field_key_allocation_msb_balance_enable", \
   "field_presel_mgmt_advanced_mode", \
   "field_scache_size", \
   "fifo_delay_value", \
   "filter_enable", \
   "filter_resize", \
   "first_header_size", \
   "flex_port_phy_addr", \
   "flex_stat_attributes_class", \
   "flex_stat_compaction_support", \
   "flex_stat_compression_share", \
   "flex_stat_share_enable", \
   "flex_xgport", \
   "flow_control_enable", \
   "flow_control_only_unicast", \
   "flow_control_type", \
   "flow_init_mode", \
   "flow_maping_add_delete", \
   "flow_mapping_queue_base", \
   "flow_tracker_intr_enable", \
   "flow_type_for_cut_through_control", \
   "flowtracker_chip_debug_enable", \
   "flowtracker_chip_debug_enable", \
   "flowtracker_drop_monitor_enable", \
   "flowtracker_elephant_enable", \
   "flowtracker_elephant_expected_queue_drain_time_usecs", \
   "flowtracker_elephant_scan_interval_usecs", \
   "flowtracker_enable", \
   "flowtracker_enterprise_number", \
   "flowtracker_export_fifo_hostbuf_size", \
   "flowtracker_export_fifo_intr_enable", \
   "flowtracker_export_fifo_thread_pri", \
   "flowtracker_export_interval_secs", \
   "flowtracker_export_interval_usecs", \
   "flowtracker_flow_start_timestamp_ie_enable", \
   "flowtracker_fsp_reinject_max_length", \
   "flowtracker_ipfix_observation_domain_id", \
   "flowtracker_max_counters_per_flow", \
   "flowtracker_max_export_pkt_length", \
   "flowtracker_max_flow_groups", \
   "flowtracker_max_flows", \
   "flowtracker_num_unique_user_entry_keys", \
   "flowtracker_scan_interval_usecs", \
   "force_bridge_forwarding", \
   "force_clk_m_n_divisors_zero", \
   "force_optbiasfltlvl", \
   "force_optprfltlvl", \
   "force_optrxfltlvl", \
   "force_optrxloslvl", \
   "force_opttempfltlvl", \
   "force_opttxenblvl", \
   "force_opttxfllvl", \
   "force_opttxonlvl", \
   "force_opttxrstlvl", \
   "fp_cam_tm", \
   "fp_compression_enable", \
   "fp_even_index_for_ingress_flow_meter", \
   "fpem_mem_entries", \
   "front_panel_esm", \
   "fschan_enable", \
   "ftmh_dsp_extension_add", \
   "general_cascade_mode", \
   "gig_iov", \
   "global_meter_compaction_support", \
   "global_meter_compression_share", \
   "global_meter_control", \
   "gmii_enable_rx", \
   "gmii_enable_tx", \
   "gmii_mode", \
   "gmii_rate", \
   "bcm_use_gport", \
   "gport_rsv_mask", \
   "graceful_lag_modification_enable", \
   "guarantee", \
   "guarantee_mc", \
   "ha_crash_recovery", \
   "ha_hw_journal_mode", \
   "ha_hw_journal_size", \
   "ha_hw_journal_size", \
   "ha_sw_journal_size", \
   "hbm_tune", \
   "headroom", \
   "help_cli_enable", \
   "higig2_hdr_mode", \
   "higig2_multicast_l2_range", \
   "higig2_multicast_l3_range", \
   "higig2_multicast_vlan_range", \
   "higig_destport_mask", \
   "higig_frc_tm_system_port_encoding", \
   "higig_max_speed", \
   "host_as_route_disable", \
   "host_memory_address_remap_entries_reserved_cmc", \
   "hqos_mapping_enable", \
   "i2c_hclk_skip", \
   "i2c_nvram_skip", \
   "i2c_poe_power", \
   "i2c_timeout_usec", \
   "ibod_sync_thread_pri", \
   "if_tbi", \
   "ifa_enable", \
   "ifp_inports_support_enable", \
   "igmp_proxy_mode", \
   "ilkn_burst_max", \
   "ilkn_burst_min", \
   "ilkn_burst_short", \
   "ilkn_counters_mode", \
   "ilkn_first_packet_sw_bypass", \
   "ilkn_interface_status_ignore", \
   "ilkn_interface_status_oob_ignore", \
   "ilkn_invalid_lane_id", \
   "ilkn_is_burst_interleaving", \
   "ilkn_lane_map", \
   "ilkn_lanes", \
   "ilkn_metaframe_sync_period", \
   "ilkn_num_lanes", \
   "ilkn_retransmit_buffer_size", \
   "ilkn_retransmit_calendar_mode_rx", \
   "ilkn_retransmit_calendar_mode_tx", \
   "ilkn_retransmit_enable_rx", \
   "ilkn_retransmit_enable_tx", \
   "ilkn_retransmit_num_requests_resent", \
   "ilkn_retransmit_num_sn_repetitions_rx", \
   "ilkn_retransmit_num_sn_repetitions_tx", \
   "ilkn_retransmit_peer_tx_buffer_size", \
   "ilkn_retransmit_reserved_channel_id", \
   "ilkn_retransmit_rx_discontinuity_event_timeout", \
   "ilkn_retransmit_rx_ignore", \
   "ilkn_retransmit_rx_reset_upon_watchdog_error_enable", \
   "ilkn_retransmit_rx_reset_when_alligned_error_enable", \
   "ilkn_retransmit_rx_reset_when_error_enable", \
   "ilkn_retransmit_rx_reset_when_retry_error_enable", \
   "ilkn_retransmit_rx_reset_when_timout_error_enable", \
   "ilkn_retransmit_rx_reset_when_wrap_after_disc_error_enable", \
   "ilkn_retransmit_rx_reset_when_wrap_before_disc_error_enable", \
   "ilkn_retransmit_rx_timeout_sn", \
   "ilkn_retransmit_rx_timeout_words", \
   "ilkn_retransmit_rx_watchdog", \
   "ilkn_retransmit_sn_bits", \
   "ilkn_retransmit_tx_ignore_requests_when_fifo_almost_empty", \
   "ilkn_retransmit_tx_wait_for_seq_num_change_enable", \
   "ilkn_tdm_dedicated_queuing", \
   "in_lif_profile_egress_allocate", \
   "ing_share_flex_counter_pool", \
   "ingportpool", \
   "ingr_counter_percent", \
   "ingress_bubble_qid", \
   "ingress_congestion_management", \
   "ingress_congestion_management_pkt_header_compensation_enable", \
   "ingress_congestion_management_stag_max_id", \
   "ingress_congestion_management_tm_port_max_id", \
   "ingress_drop_thres_de1", \
   "ingress_drop_thres_de2", \
   "ingress_hysteresis_delta", \
   "ingress_max_pages", \
   "ingress_to_egress_redirect_qid0", \
   "ingress_to_egress_redirect_qid1", \
   "init_port_config_option", \
   "inlif_table_defrag_enable", \
   "input_pri_to_priority_group_mc", \
   "input_pri_to_priority_group_profile_idx", \
   "input_pri_to_priority_group_uc", \
   "int_link_metadata_pbmp", \
   "int_turnaround_enable", \
   "int_turnaround_enable", \
   "ip4_host_extension_table_enable", \
   "ip6_tunnel_term_in_tcam_vrf_nof_bits", \
   "ip6_vxlan_mshg_enable", \
   "ip_ecn_mode", \
   "ipep_clock_gating_disable", \
   "ipfix_hostbuf_size", \
   "ipfix_intr_enable", \
   "ipfix_thread_pri", \
   "ipmc_do_vlan", \
   "ipmc_enable", \
   "ipmc_independent_mode", \
   "ipmc_l2_ssm_mode", \
   "ipmc_l2_use_vlan_vpn", \
   "ipmc_l3mcastl2_mode", \
   "ipmc_lookup_model", \
   "ipmc_pim_bidir_check_db", \
   "ipmc_pim_mode", \
   "ipmc_reduced_table_size", \
   "ipmc_vpn_lookup_enable", \
   "ipv4_da_pyld_percent", \
   "ipv4_num_routes", \
   "ipv4_num_vrfs", \
   "ipv4_sa_pyld_percent", \
   "ipv4mc_g_pyld_percent", \
   "ipv4mc_sg_pyld_percent", \
   "ipv6_da_lpm_pyld_percent", \
   "ipv6_da_pyld_percent", \
   "ipv6_enable", \
   "ipv6_lpm_128b_enable", \
   "ipv6_mc_em_percent", \
   "ipv6_mc_pyld_percent", \
   "ipv6_sa_lpm_pyld_percent", \
   "ipv6_sa_pyld_percent", \
   "is_dual_mode", \
   "itmh_arad_mode_enable", \
   "itmh_programmable_mode_enable", \
   "itpp_network_headers_termination", \
   "kbp_max_num_ranges", \
   "kbp_message_broadcast_enable", \
   "knet_filter_persist", \
   "l2_age_cycles", \
   "l2_cpu_fifo_dma_threshold", \
   "l2_cpu_fifo_dma_timeout", \
   "l2_entry_used_as_my_station", \
   "l2_learn_lif_range_base", \
   "l2_learn_limit_mode", \
   "l2_mem_banks", \
   "l2_mem_entries", \
   "l2_overflow_event", \
   "l2_sw_aging_interval", \
   "l2_table_size", \
   "l2age_thread_pri", \
   "l2cache_max_idx", \
   "l2delete_chunks", \
   "l2mc_in_l2entry", \
   "l2mod_dma_intr_enable", \
   "l2x_age_only_on_hitsa", \
   "l2xlrn_clear_on_read", \
   "l2xlrn_intr_en", \
   "l2xlrn_intr_threshold", \
   "l2xlrn_thread_interval", \
   "l2xlrn_thread_pri", \
   "l2xmsg_avl", \
   "l2xmsg_chunks", \
   "l2xmsg_hostbuf_size", \
   "l2xmsg_mode", \
   "l2xmsg_shadow_hit_bits", \
   "l2xmsg_shadow_hit_dst", \
   "l2xmsg_shadow_hit_src", \
   "l2xmsg_thread_pri", \
   "l2xmsg_thread_usec", \
   "l3_alpm2_bnk_threshold", \
   "l3_alpm2_default_route_data_mode", \
   "l3_alpm_enable", \
   "l3_alpm_hit_skip", \
   "l3_alpm_ipv6_128b_bkt_rsvd", \
   "l3_disable_add_to_arl", \
   "l3_disabled_bit_on_lif", \
   "l3_disabled_on_lif_mode", \
   "l3_ecmp_group_first_lkup_mem_size", \
   "l3_ecmp_levels", \
   "l3_ecmp_member_first_lkup_mem_size", \
   "l3_enable", \
   "l3_intf_vlan_split_egress", \
   "l3_ipmc_valid_as_hit", \
   "l3_lpm_mode", \
   "l3_max_ecmp_mode", \
   "l3_mem_banks", \
   "l3_mem_entries", \
   "l3_multiple_mymac_termination_enable", \
   "l3_multiple_mymac_termination_mode", \
   "l3_source_bind_mode", \
   "l3_source_bind_subnet_mode", \
   "l3_table_size", \
   "l3_vrrp_ipv6_distinct", \
   "l3_vrrp_max_vid", \
   "l4_protocols_load_balancing_enable", \
   "lane_to_serdes_map", \
   "lanes_swap", \
   "lawful_interception_enable", \
   "lb_buffer_size", \
   "lb_ingress_buffer_size_single", \
   "lb_lbg_fifo_size", \
   "lb_modem_fifo_size", \
   "lb_port_use_uc_queues", \
   "lc_pll_ext_clock", \
   "lccdrain_timeout_usec", \
   "learning_fifo_dma_buffer_size", \
   "learning_fifo_dma_threshold", \
   "learning_fifo_dma_timeout", \
   "led_intensity", \
   "line_client_calendar", \
   "line_port_calendar", \
   "line_pr_buffer_profile", \
   "link_bonding_enable", \
   "link_delay_100gbe_ns", \
   "link_delay_100mbe_ns", \
   "link_delay_10gbe_ns", \
   "link_delay_10mbe_ns", \
   "link_delay_1gbe_ns", \
   "link_delay_25gbe_ns", \
   "link_delay_2_5gbe_ns", \
   "link_delay_40gbe_ns", \
   "link_delay_50gbe_ns", \
   "link_delay_ns", \
   "linkphy_enable", \
   "linkscan_thread_pri", \
   "lla_tests", \
   "lls_num_l2uc", \
   "lmd_enable_pbmp", \
   "load_firmware", \
   "local_switching_enable", \
   "local_to_pp_port", \
   "local_to_tm_port", \
   "logical_interface_out_qos_inheritance", \
   "logical_interface_out_ttl_inheritance", \
   "logical_port_drop", \
   "logical_port_l2_bridge", \
   "logical_port_mim", \
   "logical_port_routing_preserve_dscp", \
   "lossless_mode", \
   "low_power", \
   "lpm_atomic_write", \
   "lpm_ipv6_128b_reserved", \
   "lpm_layout", \
   "lpm_layout_prefix_enable", \
   "lpm_scaling_enable", \
   "lrp_bypass", \
   "mac_length_check_enable", \
   "macsec_dev_addr", \
   "macsec_enable", \
   "macsec_fixed_latency_enable", \
   "macsec_port_index", \
   "macsec_switch_side_policy", \
   "maintenance_default_override", \
   "map", \
   "mapprofile", \
   "max_mtu_size", \
   "max_vp_lags", \
   "maximal_port_bandwidth", \
   "mc_table_enable_TDM_priority", \
   "mcs_load_uc0", \
   "mcs_load_uc1", \
   "mcu_channel_bitmap", \
   "mcu_delay_addr_adj_dir", \
   "mcu_delay_addr_adj_val", \
   "mcu_delay_dqi_adj_dir", \
   "mcu_delay_dqi_adj_val", \
   "mcu_dll90_offset0_qk", \
   "mcu_dll90_offset1", \
   "mcu_dll90_offset2", \
   "mcu_dll90_offset3", \
   "mcu_dll90_offset_qkb", \
   "mcu_dll90_offset_tx", \
   "mcu_drv_str0", \
   "mcu_drv_str1", \
   "mcu_odt_imp_enable", \
   "mcu_ovrd_sm_en", \
   "mcu_pad_addr_class2", \
   "mcu_pad_addr_drive", \
   "mcu_pad_addr_slew", \
   "mcu_pad_data_class2", \
   "mcu_pad_data_drive", \
   "mcu_pad_data_slew", \
   "mcu_phase_sel", \
   "mcu_sel_early1_0", \
   "mcu_sel_early1_1", \
   "mcu_sel_early1_2", \
   "mcu_sel_early1_3", \
   "mcu_sel_early2_0", \
   "mcu_sel_early2_1", \
   "mcu_sel_early2_2", \
   "mcu_sel_early2_3", \
   "mcu_tcrd", \
   "mcu_tcwd", \
   "mcu_twl", \
   "mdb_kaps_a_size", \
   "mdb_kaps_b_size", \
   "mdb_profile", \
   "mdb_profile_kaps_cfg", \
   "mdio_clock_freq_khz", \
   "mdio_external_master", \
   "mdio_firmware_download_master", \
   "mdio_io_voltage", \
   "mdio_output_delay", \
   "mem_cache_enable", \
   "mem_check_max_override", \
   "mem_check_nocache_override", \
   "mem_clear_chunk_size", \
   "mem_clear_hw_acceleration", \
   "mem_nocache", \
   "mem_parity_enable_skip", \
   "mem_scan_chunk_size", \
   "mem_scan_enable", \
   "mem_scan_interval", \
   "mem_scan_non_tcam_iterations", \
   "mem_scan_rate", \
   "mem_scan_thread_pri", \
   "memcmd_intr_enable", \
   "memcmd_timeout_usec", \
   "memlist_enable", \
   "micro_bfd_support_mode", \
   "miim_intr_enable", \
   "miim_timeout_usec", \
   "mim_num_vsis", \
   "mirror_5670_mode", \
   "mirror_copy_counting_disable", \
   "mirror_profile", \
   "mirror_stamp_sys_on_dsp_ext", \
   "mld_lane_swap", \
   "mmu_config_override", \
   "mmu_dynamic_sched_update", \
   "mmu_ext_queues_enabled", \
   "mmu_flow_fanin", \
   "mmu_flow_percent", \
   "mmu_hol_hysteresis", \
   "mmu_hol_jitter", \
   "mmu_lossless", \
   "mmu_lossless_pbmp", \
   "mmu_max_classic_queues", \
   "mmu_max_nodes", \
   "mmu_max_queues", \
   "mmu_multi_packets_per_cell", \
   "mmu_num_dmvoq_queues", \
   "mmu_num_subscriber_queues", \
   "mmu_overcommit", \
   "mmu_overcommit_stack", \
   "mmu_pfc_class_profile", \
   "mmu_pfc_group_optimized_mtu_size", \
   "mmu_pll_lock_tests", \
   "mmu_port_num_mc_queue", \
   "mmu_queue_flush_timeout", \
   "mmu_red_drop_percent", \
   "mmu_reset_bytes", \
   "mmu_reset_tries", \
   "mmu_sdram_enable", \
   "mmu_shaper_refresh_interval", \
   "mmu_static_bytes", \
   "mmu_static_percent", \
   "mmu_strict_pri_vector_mode", \
   "mmu_subscriber_num_cos_level", \
   "mmu_xq_aging", \
   "mmu_xq_weight", \
   "mmu_yellow_drop_percent", \
   "module_64ports", \
   "module_num_modids", \
   "mpls_bind_pwe_with_mpls_one_call", \
   "mpls_context", \
   "mpls_context_specific_label_enable", \
   "mpls_ecn_mode", \
   "mpls_egress_label_entropy_indicator_enable", \
   "mpls_egress_label_extended_encapsulation_mode", \
   "mpls_elsp_label_range_max", \
   "mpls_elsp_label_range_min", \
   "mpls_encap_invalid_value", \
   "mpls_encapsulation_action_swap_or_push_enable", \
   "mpls_entropy_label_indicator_enable", \
   "mpls_lm_dm_base_endpoint_id", \
   "mpls_lmdm_data_collection_mode", \
   "mpls_lmdm_pm_raw_data_buffers", \
   "mpls_mem_banks", \
   "mpls_mem_entries", \
   "mpls_oam_egress_label_ttl", \
   "mpls_oam_num_sessions", \
   "mpls_switch_ipv4_ipv6_independent_control", \
   "mpls_termination_explicit_null_label_lookup_mode", \
   "mpls_termination_label_index_enable", \
   "mpls_termination_pwe_vccv_type4_mode", \
   "mpls_tp_mymac_reserved_address", \
   "mpls_tunnel_term_label_range_max", \
   "mpls_tunnel_term_label_range_min", \
   "mplstp_bfd_control_channel_type", \
   "mplstp_cc_channel_type", \
   "mplstp_cv_channel_type", \
   "mplstp_dlm_channel_type", \
   "mplstp_dm_channel_type", \
   "mplstp_fault_oam_channel_type", \
   "mplstp_g8113_channel_type", \
   "mplstp_ilm_channel_type", \
   "mplstp_ipv4_channel_type", \
   "mplstp_ipv6_channel_type", \
   "mplstp_on_demand_cv_channel_type", \
   "mplstp_pw_ach_channel_type", \
   "mplstp_pwe_oam_channel_type", \
   "mqueue", \
   "multi_hash_recurse_depth", \
   "multi_hash_recurse_depth_egress_vlan", \
   "multi_hash_recurse_depth_egress_vlan_1", \
   "multi_hash_recurse_depth_egress_vlan_2", \
   "multi_hash_recurse_depth_exact_match", \
   "multi_hash_recurse_depth_exact_match", \
   "multi_hash_recurse_depth_l2", \
   "multi_hash_recurse_depth_l3", \
   "multi_hash_recurse_depth_mpls", \
   "multi_hash_recurse_depth_mpls", \
   "multi_hash_recurse_depth_vlan", \
   "multi_hash_recurse_depth_vlan_1", \
   "multi_hash_recurse_depth_vlan_2", \
   "multicast_destination_encoding", \
   "multicast_egress_bitmap_reserve", \
   "multicast_egress_group_id_range_max", \
   "multicast_egress_group_id_range_min", \
   "multicast_id_offset", \
   "multicast_ingress_group_id_range_max", \
   "multicast_ingress_group_id_range_min", \
   "multicast_l2_range", \
   "multicast_l3_range", \
   "multicast_nbr_full_dbuff", \
   "multicast_nbr_mini_dbuff ", \
   "multicast_nof_egress_bitmap", \
   "multicast_nof_ingress_bitmap", \
   "multicast_per_trunk_replication", \
   "multicast_scheduler_mode", \
   "nif_ref_clock", \
   "niv_enable", \
   "nof_l2cp_egress_profiles_max", \
   "np0_addr_width", \
   "np0_data_width", \
   "np1_addr_width", \
   "np1_data_width", \
   "num_erp_tm_ports", \
   "num_ipv6_lpm_128b_entries", \
   "num_multicast_queue", \
   "num_oamp_ports", \
   "num_olp_tm_ports", \
   "num_pages_reserved", \
   "num_queues", \
   "num_recycle_tm_ports", \
   "num_subport_cos", \
   "num_subports", \
   "num_unicast_queue", \
   "number_of_inrif_mac_termination_combinations", \
   "number_of_trunks", \
   "numq", \
   "oam_ccm_counting_enable", \
   "oam_ccm_max_groups", \
   "oam_ccm_max_meps", \
   "oam_classifier_advanced_mode", \
   "oam_default_trap_strength", \
   "oam_dm_ntp_enable", \
   "oam_enable", \
   "oam_forward_trap_strength", \
   "oam_hierarchical_loss_measurement_by_mdl_enable", \
   "oam_maid_11_bytes_enable", \
   "oam_maid_48_bytes_external_enable", \
   "oam_one_dm_enable", \
   "oam_pause_l2_learn_on_table_write", \
   "oam_pcp_mode", \
   "oam_pcp_value_extract_from_packet", \
   "oam_rcy_port", \
   "oam_rcy_port_up", \
   "oam_slm_lm_mode", \
   "oam_statistics_per_mep_enabled", \
   "oam_trap_strength_injected", \
   "oam_trap_strength_level", \
   "oam_trap_strength_passive", \
   "oam_use_double_outlif_injection", \
   "oamp_fifo_dma_buffer_size", \
   "oamp_fifo_dma_enable", \
   "oamp_fifo_dma_event_interface_buffer_size", \
   "oamp_fifo_dma_event_interface_enable", \
   "oamp_fifo_dma_event_interface_threshold", \
   "oamp_fifo_dma_event_interface_timeout", \
   "oamp_fifo_dma_report_interface_buffer_size", \
   "oamp_fifo_dma_report_interface_enable", \
   "oamp_fifo_dma_report_interface_threshold", \
   "oamp_fifo_dma_report_interface_timeout", \
   "oamp_fifo_dma_threshold", \
   "oamp_fifo_dma_timeout", \
   "oamp_mep_db_full_entry_threshold", \
   "oamp_rmep_db_full_entry_threshold", \
   "optimized", \
   "otm_base_q_pair", \
   "otm_port_packet_rate", \
   "otp_mem_repair_reg", \
   "otp_mem_repair_val", \
   "outlif_logical_to_physical_phase_map", \
   "outlif_physical_phase_data_granularity", \
   "oversub_speed_group_consolidation_enable", \
   "oversubscribe_mixed_sister_25_50_enable", \
   "oversubscribe_mode", \
   "packet_padding_size", \
   "parity_correction", \
   "parity_counter_clear", \
   "parity_enable", \
   "parser_mode", \
   "pb_qsgmii_alt_mapping", \
   "pb_serdes_lane_power_state", \
   "pb_serdes_lane_rate", \
   "pb_serdes_lane_rx_phys_dfelth", \
   "pb_serdes_lane_rx_phys_g1cnt", \
   "pb_serdes_lane_rx_phys_tlth", \
   "pb_serdes_lane_rx_phys_z1cnt", \
   "pb_serdes_lane_rx_phys_zcnt", \
   "pb_serdes_lane_swap_polarity_rx", \
   "pb_serdes_lane_swap_polarity_tx", \
   "pb_serdes_lane_tx_phys_amp", \
   "pb_serdes_lane_tx_phys_main", \
   "pb_serdes_lane_tx_phys_media_type", \
   "pb_serdes_lane_tx_phys_post", \
   "pb_serdes_lane_tx_phys_pre", \
   "pb_serdes_qrtt_active", \
   "pb_serdes_qrtt_max_expected_rate", \
   "pbmp_esm_eligible", \
   "pbmp_ext_mem", \
   "pbmp_fe_100fx", \
   "pbmp_gport_stack", \
   "pbmp_linkphy", \
   "pbmp_linkphy_one_stream_per_subport", \
   "pbmp_loopback", \
   "pbmp_oversubscribe", \
   "pbmp_oversubscribe_mixed_sister_25_50_init", \
   "pbmp_roe_compression", \
   "pbmp_skip_default_lls", \
   "pbmp_subport", \
   "pbmp_valid", \
   "pbmp_wan_port", \
   "pbmp_xport_cpri", \
   "pbmp_xport_ge", \
   "pbmp_xport_roe_backplane", \
   "pbmp_xport_roe_bbu", \
   "pbmp_xport_roe_fronthaul", \
   "pbmp_xport_roe_mcu", \
   "pbmp_xport_xe", \
   "pci2eb_override", \
   "pci_cmc", \
   "pci_cmcs_num", \
   "pci_override_dev", \
   "pci_override_rev", \
   "pcie_host_intf_timeout_purge_enable", \
   "pcie_host_intf_timeout_usec", \
   "pcie_hot_swap_timeout_usec", \
   "pdma_continuous_mode_enable", \
   "pdma_descriptor_prefetch_enable", \
   "pdma_dv_free_count", \
   "pdma_dv_free_size", \
   "pdma_timeout_usec", \
   "peer_tm_domain", \
   "per_queue_drop_hysteresis_delta", \
   "pfc_deadlock_seq_control", \
   "pfc_priority", \
   "pfcclass_to_priority_group", \
   "phy_1588_dpll_frequency_lock", \
   "phy_1588_dpll_k1", \
   "phy_1588_dpll_k2", \
   "phy_1588_dpll_k3", \
   "phy_1588_dpll_phase_initial_hi", \
   "phy_1588_dpll_phase_initial_lo", \
   "phy_1588_ts_divider", \
   "phy_53314_clk156", \
   "phy_5464S", \
   "phy_5690", \
   "phy_56xxx", \
   "phy_8040_mux_port0", \
   "phy_8040_mux_port1", \
   "phy_8040_mux_port2", \
   "phy_8040_switch_port", \
   "phy_8072", \
   "phy_84064", \
   "phy_84740", \
   "phy_84752", \
   "phy_84753", \
   "phy_84754", \
   "phy_8706", \
   "phy_alt_datapath_mode", \
   "phy_an_allow_pll_change", \
   "phy_an_c37", \
   "phy_an_c72", \
   "phy_an_c73", \
   "phy_an_core_num", \
   "phy_an_fec", \
   "phy_automedium", \
   "phy_autoneg_master_lane", \
   "phy_autoneg_timeout", \
   "phy_aux_voltage_enable", \
   "phy_boot_master", \
   "phy_bus_i2c", \
   "phy_chain_length", \
   "phy_chain_rx_lane_map_physical", \
   "phy_chain_rx_polarity_flip_physical", \
   "phy_chain_tx_lane_map_physical", \
   "phy_chain_tx_polarity_flip_physical", \
   "phy_clock_enable", \
   "phy_clock_enable", \
   "phy_copper_sfp", \
   "phy_diag_bmp", \
   "phy_driver_current", \
   "phy_enable", \
   "phy_ext_an_fec", \
   "phy_ext_rom_boot", \
   "phy_fcmap_passthrough", \
   "phy_fec_enable", \
   "phy_fiber_capable", \
   "phy_fiber_deglitch_usecs", \
   "phy_fiber_detect", \
   "phy_fiber_pref", \
   "phy_force_firmware_load", \
   "phy_gearbox_enable", \
   "phy_half_power", \
   "phy_hl65_1lane_mode", \
   "phy_init_cl72", \
   "phy_init_speed", \
   "phy_lane0_l2p_map", \
   "phy_led1_mode", \
   "phy_led2_mode", \
   "phy_led3_mode", \
   "phy_led3_output_disable", \
   "phy_led4_mode", \
   "phy_led_ctrl", \
   "phy_led_link_speed_mode", \
   "phy_led_select", \
   "phy_long_xfi", \
   "phy_low_power_mode", \
   "phy_lr_initial_adva", \
   "phy_lr_initial_ctrl", \
   "phy_lr_initial_mode", \
   "phy_mdi_pair_map", \
   "phy_mgbaset_802p3bz_priority", \
   "phy_mld_map", \
   "phy_mod_abs", \
   "phy_mod_abs_invert", \
   "phy_mod_auto_detect", \
   "phy_null", \
   "phy_octal_port_first", \
   "phy_operational_mode", \
   "phy_pcs_bypass", \
   "phy_pcs_repeater", \
   "phy_pcs_rx_polarity_flip", \
   "phy_pcs_tx_polarity_flip", \
   "phy_pin_compatibility_enable", \
   "phy_port_primary_and_offset", \
   "phy_preemphasis", \
   "phy_reset_timeout", \
   "phy_rx_invert", \
   "phy_rx_lane_map", \
   "phy_rx_los", \
   "phy_rx_los_invert", \
   "phy_rx_polarity_flip", \
   "phy_serdes", \
   "phy_serdes_autos", \
   "phy_sgmii_autoneg", \
   "phy_simul", \
   "phy_sys_interface", \
   "phy_topology", \
   "phy_tx_disable_no_lpmode", \
   "phy_tx_invert", \
   "phy_tx_lane_map", \
   "phy_tx_polarity_flip", \
   "phy_ull_datapath", \
   "phy_wan_mode", \
   "phy_xaui_active_lane_map", \
   "phy_xaui_rx_lane_swap", \
   "phy_xaui_rx_polarity_flip", \
   "phy_xaui_tx_lane_swap", \
   "phy_xaui_tx_polarity_flip", \
   "phy_xclksel_ovrd", \
   "phy_xfp_clock", \
   "phy_xsw_lane_map", \
   "pkt", \
   "pkt_size", \
   "pktdma_poll_mode_channel_bitmap", \
   "pll600_slowclk", \
   "pmf_in_lif_profile_nof_bits", \
   "pmf_in_rif_profile_nof_bits", \
   "pmf_kaps_large_db_size", \
   "pmf_kaps_mgmt_advanced_mode", \
   "pmf_sexem3_stage", \
   "pmf_vsi_profile_full_range", \
   "policer_color_resolution_mode", \
   "policer_egress_count", \
   "policer_egress_sharing_mode", \
   "policer_ingress_count", \
   "policer_ingress_sharing_mode", \
   "policer_result_map", \
   "policer_result_parallel_bucket_update", \
   "policer_result_parallel_color_map", \
   "polled_irq_delay", \
   "polled_irq_mode", \
   "polled_irq_priority", \
   "pon_application_support_enabled", \
   "pon_pp_port_mapping_bypass", \
   "pon_tls_database", \
   "pon_tpid_tunnel_id", \
   "pool", \
   "pool_floor", \
   "pool_limit", \
   "pool_resume", \
   "pool_scale", \
   "port", \
   "port_egress_cos_mode", \
   "port_egress_recycling_scheduler_configuration", \
   "port_egress_scheduler_confguration ", \
   "port_fec", \
   "port_flex_enable", \
   "port_flex_max_ports", \
   "port_flex_speed_max", \
   "port_gmii_mode", \
   "port_guarantee_enable", \
   "port_init_adv", \
   "port_init_autoneg", \
   "port_init_cl72", \
   "port_init_duplex", \
   "port_init_speed", \
   "port_is_sci", \
   "port_is_sfi", \
   "port_lp_tx_precoder", \
   "port_max_enable", \
   "port_max_speed", \
   "port_nif_type", \
   "port_oversubscribe", \
   "port_phy_addr", \
   "port_phy_addr1", \
   "port_phy_clause", \
   "port_phy_id0", \
   "port_phy_id1", \
   "port_phy_lane_mask", \
   "port_phy_mode_reverse", \
   "port_phy_precondition_before_probe", \
   "port_priorities", \
   "port_raw_mpls_enable", \
   "port_rx_fcs_error_early_discard", \
   "port_sched_dynamic", \
   "port_sched_hsp", \
   "port_tx_pam4_precoder", \
   "port_uc_mc_accounting_combine", \
   "portgroup", \
   "portmap", \
   "portmon_interval", \
   "portmon_thread_pri", \
   "post_headers_size", \
   "post_init_enable", \
   "power_down_timeout", \
   "preamble_sop_only", \
   "prepend_tag_bytes", \
   "prepend_tag_bytes", \
   "prepend_tag_offset", \
   "prepend_tag_offset", \
   "pri", \
   "prigroup", \
   "priority_group_lossless", \
   "priority_group_profile_idx", \
   "priority_group_to_headroom_pool", \
   "priority_group_to_service_pool", \
   "private_ip_frwrd_table_size", \
   "profile_pg_1hdrm_8shared", \
   "profile_valid", \
   "programmability_image_name", \
   "programmability_ucode_relative_path", \
   "protocol_traps_mode", \
   "protocol_vlan_coupled_mode", \
   "ptp_backplane_1_invalid_thresh", \
   "ptp_backplane_1_k1", \
   "ptp_backplane_1_k1k2", \
   "ptp_backplane_1_k1k3", \
   "ptp_backplane_1_k4", \
   "ptp_backplane_1_valid_thresh", \
   "ptp_backplane_2_invalid_thresh", \
   "ptp_backplane_2_k1", \
   "ptp_backplane_2_k1k2", \
   "ptp_backplane_2_k1k3", \
   "ptp_backplane_2_k4", \
   "ptp_backplane_2_valid_thresh", \
   "ptp_backplane_nominal_period", \
   "ptp_backplane_valid_input_thresh", \
   "ptp_bs_clk_dur_high", \
   "ptp_bs_clk_dur_low", \
   "ptp_bs_fref", \
   "ptp_bs_hb_dur_high", \
   "ptp_bs_hb_dur_low", \
   "ptp_bs_ka", \
   "ptp_bs_ki", \
   "ptp_bs_kp", \
   "ptp_bs_mndiv", \
   "ptp_bs_ndiv_frac", \
   "ptp_bs_ndiv_int", \
   "ptp_bs_pdiv", \
   "ptp_bs_vco_div2", \
   "ptp_cosq", \
   "ptp_servo_bridge_time", \
   "ptp_servo_osc_type", \
   "ptp_servo_phase_mode", \
   "ptp_servo_transport_type", \
   "ptp_synth_1_invalid_thresh", \
   "ptp_synth_1_k1", \
   "ptp_synth_1_k1k2", \
   "ptp_synth_1_k1k3", \
   "ptp_synth_1_k4", \
   "ptp_synth_1_valid_thresh", \
   "ptp_synth_2_invalid_thresh", \
   "ptp_synth_2_k1", \
   "ptp_synth_2_k1k2", \
   "ptp_synth_2_k1k3", \
   "ptp_synth_2_k4", \
   "ptp_synth_2_valid_thresh", \
   "ptp_synth_nominal_period", \
   "ptp_synth_valid_input_thresh", \
   "ptp_ts_ka", \
   "ptp_ts_ki", \
   "ptp_ts_kp", \
   "ptp_ts_pll_fref", \
   "ptp_ts_pll_mndiv", \
   "ptp_ts_pll_mndiv1", \
   "ptp_ts_pll_n", \
   "ptp_ts_pll_pdiv", \
   "ptp_ts_vco_div2", \
   "public_ip_frwrd_table_size", \
   "pvt_mon_correction_factor", \
   "pwe_termination_port_mode_enable", \
   "qdr36_dll90_offset_qk", \
   "qdr36_dll90_offset_qkb", \
   "qdr36_dll90_offset_tx", \
   "qdr36_ovrd_sm_en", \
   "qdr36_phase_sel", \
   "qdr36_sel_early1_0", \
   "qdr36_sel_early1_1", \
   "qdr36_sel_early2_0", \
   "qdr36_sel_early2_1", \
   "qgroup", \
   "qgroup_guarantee", \
   "qgroup_guarantee_enable", \
   "qgroup_id", \
   "qos_policer_color_mapping_pcp", \
   "quarantine_mechanism_allowed_errors", \
   "queue", \
   "queue_level_interface", \
   "rate_color_blind", \
   "rate_ext_download_mdio_dividend", \
   "rate_ext_download_mdio_divisor", \
   "rate_ext_mdio_dividend", \
   "rate_ext_mdio_divisor", \
   "rate_i2c_dividend", \
   "rate_i2c_divisor", \
   "rate_int_mdio_dividend", \
   "rate_int_mdio_divisor", \
   "rate_stdma_dividend", \
   "rate_stdma_divisor", \
   "rcpu_cpu_queue", \
   "rcpu_cpu_tc_cos0", \
   "rcpu_cpu_tc_cos1", \
   "rcpu_cpu_tc_cos2", \
   "rcpu_cpu_tc_cos3", \
   "rcpu_cpu_tc_cos4", \
   "rcpu_cpu_tc_cos5", \
   "rcpu_cpu_tc_cos6", \
   "rcpu_cpu_tc_cos7", \
   "rcpu_dot1pri_cos0", \
   "rcpu_dot1pri_cos1", \
   "rcpu_dot1pri_cos2", \
   "rcpu_dot1pri_cos3", \
   "rcpu_dot1pri_cos4", \
   "rcpu_dot1pri_cos5", \
   "rcpu_dot1pri_cos6", \
   "rcpu_dot1pri_cos7", \
   "rcpu_dot1pri_map_enable", \
   "rcpu_higig_port", \
   "rcpu_lmac", \
   "rcpu_master_modid", \
   "rcpu_master_unit", \
   "rcpu_mh_cpu_cos_enable", \
   "rcpu_mh_src_pid_enable", \
   "rcpu_mh_tc_cos0", \
   "rcpu_mh_tc_cos1", \
   "rcpu_mh_tc_cos2", \
   "rcpu_mh_tc_cos3", \
   "rcpu_mh_tc_cos4", \
   "rcpu_mh_tc_cos5", \
   "rcpu_mh_tc_cos6", \
   "rcpu_mh_tc_cos7", \
   "rcpu_mh_tc_map_enable", \
   "rcpu_only", \
   "rcpu_oob_channel", \
   "rcpu_port", \
   "rcpu_rx_pbmp", \
   "rcpu_slave_modid", \
   "rcpu_src_mac", \
   "rcpu_use_oob", \
   "rcpu_vlan", \
   "rcy_channelized_shared_context_enable", \
   "red_limit", \
   "red_resume", \
   "red_size", \
   "reglist_enable", \
   "repeater_link_dest", \
   "repeater_link_enable", \
   "replication_eligible_pbmp", \
   "reserve_mim_default_svp", \
   "reserve_multicast_resources", \
   "reserve_nh_for_ecmp", \
   "resilient_hash_enable", \
   "rif_id_max", \
   "riot_enable", \
   "riot_overlay_ecmp_resilient_hash_size", \
   "riot_overlay_l3_egress_mem_alloc_mode", \
   "riot_overlay_l3_egress_mem_size", \
   "riot_overlay_l3_intf_mem_alloc_mode", \
   "riot_overlay_l3_intf_mem_size", \
   "rlink_auth_local_max", \
   "rlink_auth_remote_max", \
   "rlink_l2_local_max", \
   "rlink_l2_remote_max", \
   "rlink_link_local_max", \
   "rlink_link_remote_max", \
   "rlink_oam_local_max", \
   "rlink_oam_remote_max", \
   "rlink_rx0_remote_max", \
   "rlink_rx1_remote_max", \
   "rlink_rx2_remote_max", \
   "rlink_rx3_remote_max", \
   "rlink_rx4_remote_max", \
   "rlink_rx5_remote_max", \
   "rlink_rx6_remote_max", \
   "rlink_rx7_remote_max", \
   "robust_hash_seed_egress_vlan", \
   "robust_hash_seed_egress_vlan_1", \
   "robust_hash_seed_egress_vlan_2", \
   "robust_hash_seed_egress_vp_vlan", \
   "robust_hash_seed_exact_match", \
   "robust_hash_seed_ing_dnat_address", \
   "robust_hash_seed_ingress_vp_vlan", \
   "robust_hash_seed_l2", \
   "robust_hash_seed_l3", \
   "robust_hash_seed_l3_tunnel", \
   "robust_hash_seed_mpls", \
   "robust_hash_seed_subport_id_to_sgpp_map", \
   "robust_hash_seed_vlan", \
   "robust_hash_seed_vlan_1", \
   "robust_hash_seed_vlan_2", \
   "roe_reserved_bit", \
   "roe_stuffing_bit", \
   "roo_extension_label_encapsulation", \
   "rpc_server_thread_count", \
   "rqequeue", \
   "rsvd4_port_init_speed_id", \
   "run_l2_sw_aging", \
   "runtime_performance_optimize_enable", \
   "rx_fast_los_link", \
   "rx_fast_los_poll_count_max", \
   "rx_fast_los_usec", \
   "rx_pool_nof_pkts", \
   "sa_auth_enabled", \
   "same_speed_intf_do_not_overwrite", \
   "sat_enable", \
   "sbfd_rcy_port", \
   "sbus_dma_desc_thread_pri", \
   "schan_error_block_usec", \
   "schan_intr_enable", \
   "schan_timeout_usec", \
   "schanfifo_intr_enable", \
   "schanfifo_timeout_usec", \
   "sched_strict_priority", \
   "scheduler_compensation_enable", \
   "scheduler_fabric_links_adaptation_enable", \
   "scheduler_profile", \
   "scheduler_profile_map", \
   "seamless_bfd_enable", \
   "secondary_is_multicast", \
   "seed", \
   "seer_cse_em_latency7", \
   "seer_ext_table_cfg", \
   "seer_ext_tcam_select", \
   "seer_host_hash_table_cfg", \
   "seer_hse_em_latency7", \
   "seer_init_timeout_usec", \
   "seer_lpm_traverse_entries", \
   "seer_mvl_hash_table_cfg", \
   "seer_tunnel_sam", \
   "serdes_1000x_at_12500_vco", \
   "serdes_1000x_at_25g_vco", \
   "serdes_1000x_at_6250_vco", \
   "serdes_10g_at_25g_vco", \
   "serdes_2wire_xaui", \
   "serdes_an_c73_tx_fifo_reset_enable", \
   "serdes_asymmetric_speed_mode", \
   "serdes_automedium", \
   "serdes_cl37_sgmii_restart_count", \
   "serdes_core_rx_polarity_flip_physical", \
   "serdes_core_tx_polarity_flip_physical", \
   "serdes_driver_current", \
   "serdes_enc_mode", \
   "serdes_fabric_clk_freq", \
   "serdes_fec_enable", \
   "serdes_fiber_pref", \
   "serdes_firmware_mode", \
   "serdes_if_type", \
   "serdes_lane0_reset", \
   "serdes_lane_config", \
   "serdes_lcpll", \
   "serdes_mixed_rate_enable", \
   "serdes_nif_clk_binding", \
   "serdes_nif_clk_freq", \
   "serdes_num_lane", \
   "serdes_os_mode", \
   "serdes_pcs_20g_alignment_marker_reserved", \
   "serdes_pcs_speed_hto_blk_sync_end", \
   "serdes_pcs_speed_hto_brcm64b66_descr", \
   "serdes_pcs_speed_hto_cl36_en", \
   "serdes_pcs_speed_hto_cl48_check_end", \
   "serdes_pcs_speed_hto_cl72_enable", \
   "serdes_pcs_speed_hto_clkcnt0", \
   "serdes_pcs_speed_hto_clkcnt1", \
   "serdes_pcs_speed_hto_dec1_mode", \
   "serdes_pcs_speed_hto_desc2_byte_del", \
   "serdes_pcs_speed_hto_desc2_mode", \
   "serdes_pcs_speed_hto_descr1_mode", \
   "serdes_pcs_speed_hto_deskew_mode", \
   "serdes_pcs_speed_hto_encode_mode", \
   "serdes_pcs_speed_hto_lpcnt0", \
   "serdes_pcs_speed_hto_lpcnt1", \
   "serdes_pcs_speed_hto_mac_cgc", \
   "serdes_pcs_speed_hto_pcs_cgc", \
   "serdes_pcs_speed_hto_pcs_clkcnt", \
   "serdes_pcs_speed_hto_pcs_crdten", \
   "serdes_pcs_speed_hto_pcs_repcnt", \
   "serdes_pcs_speed_hto_pll_divider", \
   "serdes_pcs_speed_hto_pma_os", \
   "serdes_pcs_speed_hto_reorder_mode", \
   "serdes_pcs_speed_hto_scr_mode", \
   "serdes_pcs_speed_hto_sgmii_mode", \
   "serdes_pll_div", \
   "serdes_post2_driver_current", \
   "serdes_pre_driver_current", \
   "serdes_preemphasis", \
   "serdes_qrtt_active", \
   "serdes_qsgmii_sgmii_override", \
   "serdes_rx_large_swing", \
   "serdes_rx_los", \
   "serdes_rx_los_invert", \
   "serdes_rxaui_mode", \
   "serdes_scrambler_enable", \
   "serdes_scrambler_seed", \
   "serdes_sgmii_master", \
   "serdes_shadow_driver", \
   "serdes_tx_los_usec", \
   "serdes_tx_taps", \
   "serdes_txpi_mode", \
   "serdes_use_proxy_removal", \
   "service_queue_dynamic_config", \
   "simple_vlan_translation_enable", \
   "size", \
   "skip_L2_USER_ENTRY", \
   "skip_l2_vlan_init", \
   "slow_max_rate_level", \
   "smac_pyld_percent", \
   "snoop_enable", \
   "soc_counter_control_level", \
   "soc_ctr_maxerr", \
   "soc_dma_monitor_thread_pri", \
   "soc_family", \
   "soc_knet_rx_thread_pri", \
   "soc_mem_bulk_schan_op_mode", \
   "soc_scoreboard_enable", \
   "soc_scoreboard_interval", \
   "soc_skip_reset", \
   "spaui_chan_bct_channel_byte_ndx", \
   "spaui_chan_bct_size", \
   "spaui_chan_fault_response_local", \
   "spaui_chan_fault_response_remote", \
   "spaui_chan_is_burst_interleaving", \
   "spaui_crc_mode", \
   "spaui_ipg_dic_mode", \
   "spaui_ipg_size", \
   "spaui_is_double_size_sop_even_only", \
   "spaui_is_double_size_sop_odd_only", \
   "spaui_link_partner_double_size_bus", \
   "spaui_preamble_size", \
   "spaui_preamble_skip_sop", \
   "spi_loopback", \
   "split_horizon_forwarding_groups_mode", \
   "spri0_qid", \
   "spri1_qid", \
   "sr_prp_enable", \
   "sram_scan_chunk_size", \
   "sram_scan_enable", \
   "sram_scan_interval", \
   "sram_scan_rate", \
   "sram_scan_thread_pri", \
   "srd_tx_drv_hv_disable", \
   "ss_ignore_pbmp", \
   "stable_filename", \
   "stable_flags", \
   "stable_location", \
   "stable_size", \
   "stack_cpu_priority", \
   "stack_enable", \
   "stack_simplex", \
   "stacking_enable", \
   "stacking_extension_enable", \
   "stag_enable", \
   "stat_if_billing_filter_reports", \
   "stat_if_billing_ingress_drop_reason_enable", \
   "stat_if_billing_ingress_queue_stamp_enable", \
   "stat_if_core_mode", \
   "stat_if_enable", \
   "stat_if_etpp_counter_mode", \
   "stat_if_etpp_mode", \
   "stat_if_idle_reports_present", \
   "stat_if_parity_enable", \
   "stat_if_phase", \
   "stat_if_pkt_size", \
   "stat_if_rate", \
   "stat_if_report_billing_mode", \
   "stat_if_report_dequeue_enable", \
   "stat_if_report_enqueue_enable", \
   "stat_if_report_fap20v_cnm_report", \
   "stat_if_report_fap20v_count_snoop", \
   "stat_if_report_fap20v_fabric_mc", \
   "stat_if_report_fap20v_ing_mc", \
   "stat_if_report_fap20v_ing_mc_report_single", \
   "stat_if_report_fap20v_mode", \
   "stat_if_report_fap20v_single_copy_reported", \
   "stat_if_report_mode", \
   "stat_if_report_multicast_single_copy", \
   "stat_if_report_original_pkt_size", \
   "stat_if_report_size", \
   "stat_if_reports_per_packet", \
   "stat_if_scrubber_bdb_th", \
   "stat_if_scrubber_buffer_descr_th", \
   "stat_if_scrubber_enable", \
   "stat_if_scrubber_queue_max", \
   "stat_if_scrubber_queue_min", \
   "stat_if_scrubber_rate_max", \
   "stat_if_scrubber_rate_min", \
   "stat_if_scrubber_sram_buffers_th", \
   "stat_if_scrubber_sram_pdbs_th", \
   "stat_if_scrubber_uc_dram_buffer_th", \
   "stat_if_selective_report_queue_max", \
   "stat_if_selective_report_queue_min", \
   "stat_if_sync_rate", \
   "stat_if_tc_source", \
   "station_mac_address", \
   "stg_table_size", \
   "streaming_if_discard_bad_parity", \
   "streaming_if_discard_pkt_streaming", \
   "streaming_if_enable_timeoutcnt", \
   "streaming_if_multi_port_mode", \
   "streaming_if_quiet_mode", \
   "streaming_if_timeout_prd", \
   "sum_enable", \
   "sw_autoneg_polling_interval", \
   "sw_state_max_size", \
   "sw_temp_threshold", \
   "sw_timestamp_fifo_enable", \
   "switch_bypass_mode", \
   "switch_delay", \
   "sync_eth_clk_divider", \
   "sync_eth_clk_squelch_enable", \
   "sync_eth_clk_to_nif_id", \
   "sync_eth_clk_to_port_id_clk", \
   "sync_eth_is_malg_b_enabled", \
   "sync_eth_mode", \
   "synth_dram_freq", \
   "system_cell_format", \
   "system_contains_multiple_pipe_device", \
   "system_ftmh_load_balancing_ext_mode", \
   "system_has_fap20", \
   "system_has_fap21", \
   "system_has_petra_rev_a", \
   "system_headers_mode", \
   "system_is_arad_in_system", \
   "system_is_dual_mode_in_system", \
   "system_is_fe1600_in_system", \
   "system_is_fe600_in_system", \
   "system_is_petra_b_in_system", \
   "system_is_single_mode_in_system", \
   "system_is_vcs_128_in_system", \
   "system_pph_eep_ext", \
   "system_red_enable", \
   "system_ref_core_clock", \
   "system_set_dma_low_endianess", \
   "system_stag_enconding_enable_mode", \
   "system_stag_enconding_offset_4bit", \
   "table_dma_enable", \
   "tas_calendar_auto_adjust_for_holdadvance", \
   "tas_calendar_auto_adjust_for_txoverrun", \
   "tas_calendar_auto_adjust_ref_maxsdu", \
   "tb_flow_id_size", \
   "tcam_bank_block_owner", \
   "tcam_bist_enable", \
   "tcam_dac_value", \
   "tcam_ptr_dist", \
   "tcam_reset_usec", \
   "tdm_egress_dp", \
   "tdm_egress_priority", \
   "tdm_mode", \
   "tdm_queuing_force", \
   "tdm_source_fap_id_offset", \
   "tdma_intr_enable", \
   "tdma_timeout_usec", \
   "telemetry_enable", \
   "telemetry_export_max_packet_size", \
   "telemetry_max_ports_monitor", \
   "timestamp_adjust_100gbe_ns", \
   "timestamp_adjust_100mbe_ns", \
   "timestamp_adjust_10gbe_ns", \
   "timestamp_adjust_10mbe_ns", \
   "timestamp_adjust_1gbe_ns", \
   "timestamp_adjust_25gbe_ns", \
   "timestamp_adjust_2_5gbe_ns", \
   "timestamp_adjust_40gbe_ns", \
   "timestamp_adjust_50gbe_ns", \
   "timestamp_adjust_ns", \
   "timestamp_tsts_adjust_100gbe_ns", \
   "timestamp_tsts_adjust_100mbe_ns", \
   "timestamp_tsts_adjust_10gbe_ns", \
   "timestamp_tsts_adjust_10mbe_ns", \
   "timestamp_tsts_adjust_1gbe_ns", \
   "timestamp_tsts_adjust_25gbe_ns", \
   "timestamp_tsts_adjust_2_5gbe_ns", \
   "timestamp_tsts_adjust_40gbe_ns", \
   "timestamp_tsts_adjust_50gbe_ns", \
   "timestamp_tsts_adjust_ns", \
   "tm_ingress_shaping_enable", \
   "tm_port_header_type", \
   "tm_port_itmh_ext_enable", \
   "tm_port_otmh_dest_ext_enable", \
   "tm_port_otmh_outlif_ext_mode", \
   "tm_port_otmh_src_ext_enable", \
   "tm_pph_pph_present_enable", \
   "total_buff_drop_thres_de1", \
   "total_buff_drop_thres_de2", \
   "total_buff_hysteresis_delta", \
   "total_buff_max_pages", \
   "trap_lif_mtu_enable", \
   "trill_designated_vlan_check_disable", \
   "trill_mc_prune_mode", \
   "trill_mode", \
   "trill_transparent_service", \
   "truncate_delta_in_pp_counter", \
   "trunk_extend", \
   "trunk_group_max_members", \
   "trunk_hash_format", \
   "trunk_resilient_hash_table_size", \
   "trunk_resolve_use_lb_key_msb_smooth_division", \
   "trunk_resolve_use_lb_key_msb_stack", \
   "tslam_dma_enable", \
   "tslam_intr_enable", \
   "tslam_timeout_usec", \
   "tx_fifo_size", \
   "txpi_sdm_scheme", \
   "uc_msg_ctl_timeout", \
   "uc_msg_ctrl_0", \
   "uc_msg_ctrl_1", \
   "uc_msg_queue_timeout", \
   "uc_msg_send_retry_delay", \
   "uc_msg_send_timeout", \
   "uc_msg_thread_pri", \
   "uc_msg_tx_beacon_timeout", \
   "uc_valid_bmp", \
   "ucode_port", \
   "udp_tunnel_enable", \
   "use_all_splithorizon_groups", \
   "use_fabric_links_for_ilkn_nif", \
   "use_small_banks_mode_vrrp", \
   "use_trunk_as_ingress_mc_destination", \
   "user_buffer_size", \
   "user_delay", \
   "v4mc_str_sel", \
   "v4uc_str_sel", \
   "vcs128_unicast_priority", \
   "vfp_cam_tm", \
   "vlan_action_dummy_vp_reserved", \
   "vlan_auto_stack", \
   "vlan_match_criteria_mode", \
   "vlan_match_db_mode", \
   "vlan_queue_enable", \
   "vlan_queue_levels_max", \
   "vlan_translation_initial_vlan_enable", \
   "vlan_translation_match_ipv4", \
   "vlan_xlate_1_mem_entries", \
   "vlan_xlate_2_mem_entries", \
   "vlan_xlate_mem_banks", \
   "vlan_xlate_mem_entries", \
   "vlandelete_chunks", \
   "vmac_enable", \
   "vmac_encoding_mask", \
   "vmac_encoding_value", \
   "voq_mapping_mode", \
   "voq_to_cmq_mapping_mode", \
   "vplag_vp_alloc_mode", \
   "vpws_tagged_mode", \
   "vrrp_scaling_tcam", \
   "vxlan_tunnel_term_in_sem_my_vtep_index_nof_bits", \
   "vxlan_tunnel_term_in_sem_vrf_nof_bits", \
   "vxlan_udp_dest_port", \
   "warmboot_event_handler_enable", \
   "warmboot_knet_shutdown_mode", \
   "warmboot_support", \
   "wdrr_weight_queue", \
   "wide_sram0_x18", \
   "wide_sram1_x18", \
   "wp_addr_width", \
   "wp_data_width", \
   "xflow_macsec_decrypt_fail_switch_to_cpu", \
   "xflow_macsec_decrypt_pad_threshold", \
   "xflow_macsec_decrypt_sectag_c1e0_error", \
   "xflow_macsec_encrypt_fail_switch_to_cpu", \
   "xflow_macsec_olp_vlan", \
   "xflow_macsec_secure_chan_to_num_secure_assoc", \
   "xflow_macsec_secure_chan_to_num_secure_assoc", \
   "xflow_macsec_skip_decrypt_pkt_parser", \
   "xgs_compatability_stamp_cud", \
   "xgxs_driver_current", \
   "xgxs_equalizer", \
   "xgxs_lcpll", \
   "xgxs_lcpll_12gbps", \
   "xgxs_lcpll_xtal_refclk", \
   "xgxs_offset", \
   "xgxs_pdetect_10g", \
   "xgxs_phy_oversample_mode", \
   "xgxs_phy_pll_divider", \
   "xgxs_plllock", \
   "xgxs_pre_driver_current", \
   "xgxs_preemphasis", \
   "xgxs_qgpll_xtal_refclk", \
   "xgxs_rx_lane_map", \
   "xgxs_tx_lane_map", \
   "xgxs_wcpll_xtal_refclk", \
   "xl_egress_dqueue", \
   "xl_egress_squeue", \
   "xl_ingress_dqueue", \
   "xl_ingress_squeue", \
   "xphy_primary_core_num", \
   "yellow_limit", \
   "yellow_resume", \
   "yellow_size", \
   "", \
 }
 #endif /* __SOC_PROPERTY_H */