portmode.h (11103B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 */ 7 8 #ifndef _SOC_PORTMODE_H 9 #define _SOC_PORTMODE_H 10 11 #include <shared/portmode.h> 12 #include <shared/phyconfig.h> 13 14 #include <soc/defs.h> 15 16 /* 17 * Defines: 18 * SOC_PM_* 19 * Purpose: 20 * Defines for port modes. 21 */ 22 /* Port Speeds */ 23 #define SOC_PM_10MB_HD _SHR_PM_10MB_HD 24 #define SOC_PM_10MB_FD _SHR_PM_10MB_FD 25 #define SOC_PM_100MB_HD _SHR_PM_100MB_HD 26 #define SOC_PM_100MB_FD _SHR_PM_100MB_FD 27 #define SOC_PM_1000MB_HD _SHR_PM_1000MB_HD 28 #define SOC_PM_1000MB_FD _SHR_PM_1000MB_FD 29 #define SOC_PM_2500MB_HD _SHR_PM_2500MB_HD 30 #define SOC_PM_2500MB_FD _SHR_PM_2500MB_FD 31 #define SOC_PM_3000MB_HD _SHR_PM_3000MB_HD 32 #define SOC_PM_3000MB_FD _SHR_PM_3000MB_FD 33 #define SOC_PM_10GB_HD _SHR_PM_10GB_HD 34 #define SOC_PM_10GB_FD _SHR_PM_10GB_FD 35 #define SOC_PM_12GB_HD _SHR_PM_12GB_HD 36 #define SOC_PM_12GB_FD _SHR_PM_12GB_FD 37 #define SOC_PM_13GB_HD _SHR_PM_13GB_HD 38 #define SOC_PM_13GB_FD _SHR_PM_13GB_FD 39 #define SOC_PM_16GB_HD _SHR_PM_16GB_HD 40 #define SOC_PM_16GB_FD _SHR_PM_16GB_FD 41 #define SOC_PM_SPEED_ALL _SHR_PM_SPEED_ALL 42 43 /* Pause Modes */ 44 #define SOC_PM_PAUSE_TX _SHR_PM_PAUSE_TX 45 #define SOC_PM_PAUSE_RX _SHR_PM_PAUSE_RX 46 #define SOC_PM_PAUSE_ASYMM _SHR_PM_PAUSE_ASYMM 47 48 /* Interface Types */ 49 #define SOC_PM_TBI _SHR_PM_TBI 50 #define SOC_PM_MII _SHR_PM_MII 51 #define SOC_PM_GMII _SHR_PM_GMII 52 #define SOC_PM_SGMII _SHR_PM_SGMII 53 #define SOC_PM_XGMII _SHR_PM_XGMII 54 55 /* Loopback Mode */ 56 #define SOC_PM_LB_MAC _SHR_PM_LB_MAC 57 #define SOC_PM_LB_PHY _SHR_PM_LB_PHY 58 #define SOC_PM_LB_NONE _SHR_PM_LB_NONE 59 60 /* Autonegotiation */ 61 #define SOC_PM_AN _SHR_PM_AN 62 63 /* Combo port */ 64 #define SOC_PM_COMBO _SHR_PM_COMBO 65 66 #define SOC_PM_PAUSE _SHR_PM_PAUSE 67 68 #define SOC_PM_10MB _SHR_PM_10MB 69 #define SOC_PM_100MB _SHR_PM_100MB 70 #define SOC_PM_1000MB _SHR_PM_1000MB 71 #define SOC_PM_2500MB _SHR_PM_2500MB 72 #define SOC_PM_3000MB _SHR_PM_3000MB 73 #define SOC_PM_10GB _SHR_PM_10GB 74 #define SOC_PM_12GB _SHR_PM_12GB 75 #define SOC_PM_13GB _SHR_PM_13GB 76 #define SOC_PM_16GB _SHR_PM_16GB 77 78 #define SOC_PM_SPEED_MAX(m) _SHR_PM_SPEED_MAX(m) 79 #define SOC_PM_SPEED(s) _SHR_PM_SPEED(s) 80 81 #define SOC_PM_FD _SHR_PM_FD 82 #define SOC_PM_HD _SHR_PM_HD 83 84 /* 85 * Defines: 86 * SOC_PM_ABILITY_[MAC/PHY] 87 * Purpose: 88 * Defines a mask of modes that are exclusive to the MAC or 89 * PHY drivers. To determine the ability of a port, the 90 * ability masks for the MAC and PHY are ANDed together, and then 91 * ORed with the MAC/PHY ability bits selected by these masks. 92 */ 93 94 #define SOC_PM_ABILITY_PHY (SOC_PM_LB_PHY|SOC_PM_AN|SOC_PM_COMBO) 95 #define SOC_PM_ABILITY_MAC (SOC_PM_LB_MAC) 96 97 typedef _shr_port_mode_t soc_port_mode_t; 98 99 typedef _shr_phy_config_t soc_phy_config_t; 100 101 /* 102 * Typedef: 103 * soc_port_if_t, soc_port_ms_t, soc_port_duplex_t 104 * Purpose: 105 * Defines interface type between MAC and PHY. 106 * Defines master/slave mode of a port (PHY). 107 * Defines duplexity of a port 108 * Notes: 109 * Must be kept in sync with _SHR_PORT_IF_xxx and BCM_PORT_IF_xxx. 110 */ 111 112 typedef _shr_port_if_t soc_port_if_t; 113 #define SOC_PORT_IF_NOCXN _SHR_PORT_IF_NOCXN 114 #define SOC_PORT_IF_NULL _SHR_PORT_IF_NULL 115 #define SOC_PORT_IF_MII _SHR_PORT_IF_MII 116 #define SOC_PORT_IF_GMII _SHR_PORT_IF_GMII 117 #define SOC_PORT_IF_SGMII _SHR_PORT_IF_SGMII 118 #define SOC_PORT_IF_TBI _SHR_PORT_IF_TBI 119 #define SOC_PORT_IF_XGMII _SHR_PORT_IF_XGMII 120 #define SOC_PORT_IF_XAUI _SHR_PORT_IF_XGMII 121 /*Special XAUI IF for DNX since the legacy directed to XGMII*/ 122 #define SOC_PORT_IF_DNX_XAUI _SHR_PORT_IF_XAUI 123 #define SOC_PORT_IF_RGMII _SHR_PORT_IF_RGMII 124 #define SOC_PORT_IF_RvMII _SHR_PORT_IF_RvMII 125 #define SOC_PORT_IF_SFI _SHR_PORT_IF_SFI 126 #define SOC_PORT_IF_XFI _SHR_PORT_IF_XFI 127 #define SOC_PORT_IF_KR _SHR_PORT_IF_KR 128 #define SOC_PORT_IF_KR4 _SHR_PORT_IF_KR4 129 #define SOC_PORT_IF_CR _SHR_PORT_IF_CR 130 #define SOC_PORT_IF_CR4 _SHR_PORT_IF_CR4 131 #define SOC_PORT_IF_XLAUI _SHR_PORT_IF_XLAUI 132 #define SOC_PORT_IF_SR _SHR_PORT_IF_SR 133 #define SOC_PORT_IF_RXAUI _SHR_PORT_IF_RXAUI 134 #define SOC_PORT_IF_SPAUI _SHR_PORT_IF_SPAUI 135 #define SOC_PORT_IF_QSGMII _SHR_PORT_IF_QSGMII 136 #define SOC_PORT_IF_ILKN _SHR_PORT_IF_ILKN 137 #define SOC_PORT_IF_RCY _SHR_PORT_IF_RCY 138 #define SOC_PORT_IF_FAT_PIPE _SHR_PORT_IF_FAT_PIPE 139 #define SOC_PORT_IF_CGMII _SHR_PORT_IF_CGMII 140 #define SOC_PORT_IF_CAUI _SHR_PORT_IF_CAUI 141 #define SOC_PORT_IF_LR _SHR_PORT_IF_LR 142 #define SOC_PORT_IF_LR4 _SHR_PORT_IF_LR4 143 #define SOC_PORT_IF_SR4 _SHR_PORT_IF_SR4 144 #define SOC_PORT_IF_KX _SHR_PORT_IF_KX 145 #define SOC_PORT_IF_ZR _SHR_PORT_IF_ZR 146 #define SOC_PORT_IF_SR10 _SHR_PORT_IF_SR10 147 #define SOC_PORT_IF_OTL _SHR_PORT_IF_OTL 148 #define SOC_PORT_IF_CPU _SHR_PORT_IF_CPU 149 #define SOC_PORT_IF_OLP _SHR_PORT_IF_OLP 150 #define SOC_PORT_IF_OAMP _SHR_PORT_IF_OAMP 151 #define SOC_PORT_IF_ERP _SHR_PORT_IF_ERP 152 #define SOC_PORT_IF_TM_INTERNAL_PKT _SHR_PORT_IF_TM_INTERNAL_PKT 153 #define SOC_PORT_IF_SR2 _SHR_PORT_IF_SR2 154 #define SOC_PORT_IF_KR2 _SHR_PORT_IF_KR2 155 #define SOC_PORT_IF_CR2 _SHR_PORT_IF_CR2 156 #define SOC_PORT_IF_XFI2 _SHR_PORT_IF_XFI2 157 #define SOC_PORT_IF_XLAUI2 _SHR_PORT_IF_XLAUI2 158 #define SOC_PORT_IF_CR10 _SHR_PORT_IF_CR10 159 #define SOC_PORT_IF_KR10 _SHR_PORT_IF_KR10 160 #define SOC_PORT_IF_LR10 _SHR_PORT_IF_LR10 161 #define SOC_PORT_IF_ER _SHR_PORT_IF_ER 162 #define SOC_PORT_IF_ER2 _SHR_PORT_IF_ER2 163 #define SOC_PORT_IF_ER4 _SHR_PORT_IF_ER4 164 #define SOC_PORT_IF_CX _SHR_PORT_IF_CX 165 #define SOC_PORT_IF_CX2 _SHR_PORT_IF_CX2 166 #define SOC_PORT_IF_CX4 _SHR_PORT_IF_CX4 167 #define SOC_PORT_IF_CAUI_C2C _SHR_PORT_IF_CAUI_C2C 168 #define SOC_PORT_IF_CAUI_C2M _SHR_PORT_IF_CAUI_C2M 169 #define SOC_PORT_IF_VSR _SHR_PORT_IF_VSR 170 #define SOC_PORT_IF_LR2 _SHR_PORT_IF_LR2 171 #define SOC_PORT_IF_LRM _SHR_PORT_IF_LRM 172 #define SOC_PORT_IF_XLPPI _SHR_PORT_IF_XLPPI 173 #define SOC_PORT_IF_2500X _SHR_PORT_IF_2500X 174 #define SOC_PORT_IF_5000X _SHR_PORT_IF_5000X 175 #define SOC_PORT_IF_SAT _SHR_PORT_IF_SAT 176 #define SOC_PORT_IF_IPSEC _SHR_PORT_IF_IPSEC 177 #define SOC_PORT_IF_EVENTOR _SHR_PORT_IF_EVENTOR 178 #define SOC_PORT_IF_LBG _SHR_PORT_IF_LBG 179 #define SOC_PORT_IF_CAUI4 _SHR_PORT_IF_CAUI4 180 #define SOC_PORT_IF_CPRI _SHR_PORT_IF_CPRI 181 #define SOC_PORT_IF_RSVD4 _SHR_PORT_IF_RSVD4 182 #define SOC_PORT_IF_NIF_ETH _SHR_PORT_IF_NIF_ETH 183 #define SOC_PORT_IF_COUNT _SHR_PORT_IF_COUNT 184 185 #define SOC_PORT_IF_NAMES_INITIALIZER { \ 186 "None", \ 187 "Null", \ 188 "MII", \ 189 "GMII", \ 190 "SGMII", \ 191 "TBI", \ 192 "XGMII", \ 193 "RGMII", \ 194 "RvMII", \ 195 "SFI", \ 196 "XFI", \ 197 "KR", \ 198 "KR4", \ 199 "CR", \ 200 "CR4", \ 201 "XLAUI", \ 202 "SR", \ 203 "RXAUI", \ 204 "XAUI", \ 205 "SPAUI", \ 206 "QSGMII", \ 207 "ILKN", \ 208 "RCY", \ 209 "FAT_PIPE", \ 210 "CGMII", \ 211 "CAUI", \ 212 "LR", \ 213 "LR4", \ 214 "SR4", \ 215 "KX", \ 216 "ZR", \ 217 "SR10", \ 218 "OTL", \ 219 "CPU", \ 220 "OLP", \ 221 "OAMP", \ 222 "ERP", \ 223 "SYNC_PACKET", \ 224 "SR2", \ 225 "KR2", \ 226 "CR2", \ 227 "XFI2",\ 228 "XLAUI2",\ 229 "CR10",\ 230 "KR10",\ 231 "LR10",\ 232 "ER",\ 233 "ER2",\ 234 "ER4",\ 235 "CX",\ 236 "CX2",\ 237 "CX4",\ 238 "CAC2C",\ 239 "CAC2M",\ 240 "VSR",\ 241 "LR2",\ 242 "LRM",\ 243 "XLPPI",\ 244 "2500X",\ 245 "SAT",\ 246 "IPSEC",\ 247 "LBG",\ 248 "CAUI4",\ 249 "5000X",\ 250 "EVENTOR",\ 251 "RCY_MIRROR",\ 252 "CPRI",\ 253 "RSVD4",\ 254 "ETH",\ 255 } 256 257 #define SOC_PORT_ENCODING_NAMES_INITIALIZER { \ 258 "8B9BLFEC", \ 259 "8B10B", \ 260 "64B66BFEC", \ 261 "64B66BBEC", \ 262 "64B66B", \ 263 "64B66BRSFEC", \ 264 "64B66BLLRSFEC", \ 265 "64B66B15TRSFEC", \ 266 "64B66B15TLLRSFEC", \ 267 } 268 269 typedef _shr_port_ms_t soc_port_ms_t; 270 #define SOC_PORT_MS_SLAVE _SHR_PORT_MS_SLAVE 271 #define SOC_PORT_MS_MASTER _SHR_PORT_MS_MASTER 272 #define SOC_PORT_MS_AUTO _SHR_PORT_MS_AUTO 273 #define SOC_PORT_MS_NONE _SHR_PORT_MS_NONE 274 #define SOC_PORT_MS_COUNT _SHR_PORT_MS_COUNT 275 276 typedef _shr_port_duplex_t soc_port_duplex_t; 277 #define SOC_PORT_DUPLEX_HALF _SHR_PORT_DUPLEX_HALF 278 #define SOC_PORT_DUPLEX_FULL _SHR_PORT_DUPLEX_FULL 279 #define SOC_PORT_DUPLEX_COUNT _SHR_PORT_DUPLEX_COUNT 280 281 typedef _shr_port_mdix_t soc_port_mdix_t; 282 #define SOC_PORT_MDIX_AUTO _SHR_PORT_MDIX_AUTO 283 #define SOC_PORT_MDIX_FORCE_AUTO _SHR_PORT_MDIX_FORCE_AUTO 284 #define SOC_PORT_MDIX_NORMAL _SHR_PORT_MDIX_NORMAL 285 #define SOC_PORT_MDIX_XOVER _SHR_PORT_MDIX_XOVER 286 #define SOC_PORT_MDIX_COUNT _SHR_PORT_MDIX_COUNT 287 288 typedef _shr_port_mdix_status_t soc_port_mdix_status_t; 289 #define SOC_PORT_MDIX_STATUS_NORMAL _SHR_PORT_MDIX_STATUS_NORMAL 290 #define SOC_PORT_MDIX_STATUS_XOVER _SHR_PORT_MDIX_STATUS_XOVER 291 #define SOC_PORT_MDIX_STATUS_COUNT _SHR_PORT_MDIX_STATUS_COUNT 292 293 typedef _shr_port_medium_t soc_port_medium_t; 294 #define SOC_PORT_MEDIUM_NONE _SHR_PORT_MEDIUM_NONE 295 #define SOC_PORT_MEDIUM_COPPER _SHR_PORT_MEDIUM_COPPER 296 #define SOC_PORT_MEDIUM_FIBER _SHR_PORT_MEDIUM_FIBER 297 #define SOC_PORT_MEDIUM_COUNT _SHR_PORT_MEDIUM_COUNT 298 299 typedef _shr_port_mcast_flood_t soc_port_mcast_flood_t; 300 #define SOC_PORT_MCAST_FLOOD_ALL _SHR_PORT_MCAST_FLOOD_ALL 301 #define SOC_PORT_MCAST_FLOOD_UNKNOWN _SHR_PORT_MCAST_FLOOD_UNKNOWN 302 #define SOC_PORT_MCAST_FLOOD_NONE _SHR_PORT_MCAST_FLOOD_NONE 303 #define SOC_PORT_MCAST_FLOOD_COUNT _SHR_PORT_MCAST_FLOOD_COUNT 304 305 typedef _shr_port_cable_state_t soc_port_cable_state_t; 306 #define SOC_PORT_CABLE_STATE_OK _SHR_PORT_CABLE_STATE_OK 307 #define SOC_PORT_CABLE_STATE_OPEN _SHR_PORT_CABLE_STATE_OPEN 308 #define SOC_PORT_CABLE_STATE_SHORT _SHR_PORT_CABLE_STATE_SHORT 309 #define SOC_PORT_CABLE_STATE_OPENSHORT _SHR_PORT_CABLE_STATE_OPENSHORT 310 #define SOC_PORT_CABLE_STATE_CROSSTALK _SHR_PORT_CABLE_STATE_CROSSTALK 311 #define SOC_PORT_CABLE_STATE_UNKNOWN _SHR_PORT_CABLE_STATE_UNKNOWN 312 #define SOC_PORT_CABLE_STATE_COUNT _SHR_PORT_CABLE_STATE_COUNT 313 314 /* Port link fault signalling. */ 315 #define SOC_PORT_FAULT_LOCAL _SHR_PORT_FAULT_LOCAL 316 #define SOC_PORT_FAULT_REMOTE _SHR_PORT_FAULT_REMOTE 317 318 typedef _shr_port_cable_diag_t soc_port_cable_diag_t; 319 320 extern int 321 soc_port_phy_pll_os_set(int unit, int port, uint32 vco_freq, uint32 oversample_mode, uint32 pll_divider); 322 323 typedef _shr_port_timestamp_adjust_t soc_port_timestamp_adjust_t; 324 325 #endif /* !_SOC_PORTMODE_H */