portmod_internal.h (23778B)
1 /* 2 * 3 * 4 * 5 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 6 * 7 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 8 */ 9 10 #ifndef _PORTMOD_INTERNAL_H_ 11 #define _PORTMOD_INTERNAL_H_ 12 13 #include <soc/portmod/portmod.h> 14 #include <appl/diag/diag.h> 15 16 #define MAX_PMS_PER_PHY (3) 17 #define MAX_VARS_PER_BUFFER (64) 18 #define VERSION(_ver) (_ver) 19 20 #define PORTMOD_PORT_IS_DEFAULT_TX_PARAMS_UPDATED(port_dynamic_state) (port_dynamic_state & 0x1) 21 #define PORTMOD_PORT_DEFAULT_TX_PARAMS_UPDATED_SET(port_dynamic_state) (port_dynamic_state |= 0x1) 22 #define PORTMOD_PORT_DEFAULT_TX_PARAMS_UPDATED_CLR(port_dynamic_state) (port_dynamic_state &= 0xfffe) 23 24 #define PORTMOD_PORT_IS_AUTONEG_MODE_UPDATED(port_dynamic_state) (port_dynamic_state & 0x2) 25 #define PORTMOD_PORT_AUTONEG_MODE_UPDATED_SET(port_dynamic_state) (port_dynamic_state |= 0x2) 26 #define PORTMOD_PORT_AUTONEG_MODE_UPDATED_CLR(port_dynamic_state) (port_dynamic_state &= 0xfffd) 27 28 #define PORTMOD_PORT_IS_DEFAULT_EXT_PHY_TX_PARAMS_UPDATED(port_dynamic_state) (port_dynamic_state & 0x4) 29 #define PORTMOD_PORT_DEFAULT_EXT_PHY_TX_PARAMS_UPDATED_SET(port_dynamic_state) (port_dynamic_state |= 0x4) 30 #define PORTMOD_PORT_DEFAULT_EXT_PHY_TX_PARAMS_UPDATED_CLR(port_dynamic_state) (port_dynamic_state &= 0xfffb) 31 32 #define PORTMOD_PORT_IS_DEFAULT_TIMESTAMP_ADJUSTMENT_UPDATED(port_dynamic_state) (port_dynamic_state & 0x8) 33 #define PORTMOD_PORT_DEFAULT_TIMESTAMP_ADJUSTMENT_UPDATED_SET(port_dynamic_state) (port_dynamic_state |= 0x8) 34 #define PORTMOD_PORT_DEFAULT_TIMESTAMP_ADJUSTMENT_UPDATED_CLR(port_dynamic_state) (port_dynamic_state &= 0xfff7) 35 36 /* following defines is for FEC init value */ 37 #define PORTMOD_PORT_FEC_OFF 0x0 38 #define PORTMOD_PORT_FEC_CL74 0x1 39 #define PORTMOD_PORT_FEC_CL91 0x2 40 #define PORTMOD_PORT_FEC_CL108 0x3 41 42 /* RS FEC frame size in bits */ 43 #define PORTMOD_PORT_FEC_FRAME_SIZE_INVALID 0 44 #define PORTMOD_PORT_FEC_FRAME_SIZE_RS_544 5440 45 46 /* 47 * Macros is to indicate RX Fragment types 48 * used by portmod_preemption_control_set/get() Api's 49 * to configure the RX fragment size 50 */ 51 #define PORTMOD_PREEMPTION_NON_FINAL_FRAG 0x0 52 #define PORTMOD_PREEMPTION_FINAL_FRAG 0x1 53 54 /* 55 * Macros for IEEE, HIGIG, HIGIG2 mode, matching BCM marcos 56 * such as BCM_PORT_ENCAP_IEEE 57 */ 58 #define PORTMOD_ENCAP_IEEE_MODE 0 59 #define PORTMOD_ENCAP_HIGIG_MODE 1 60 #define PORTMOD_ENCAP_HIGIG2_MODE 3 61 62 /* 63 * Define Portmacro Version 64 */ 65 typedef enum pm_type_e { 66 PM_TYPE_INVALID, 67 PM_TYPE_PM4X10, 68 PM_TYPE_PM4X25, 69 PM_TYPE_PM12X10, 70 PM_TYPE_PM4X10Q, 71 PM_TYPE_FCPM, 72 PM_TYPE_CPM4X25, 73 PM_TYPE_PM8X50, 74 PM_TYPE_COUNT 75 }pm_type_t; 76 77 typedef enum pm_gen_e { 78 PM_GEN_INVALID, 79 PM_GEN1, 80 PM_GEN2, 81 PM_GEN3, 82 PM_GEN4, 83 PM_GEN_COUNT 84 }pm_gen_t; 85 86 typedef enum pm_tech_process_e { 87 PM_TECH_INVALID, 88 PM_TECH_28NM, /* Technology process. 28nm */ 89 PM_TECH_16NM, /* Technology process. 16nm */ 90 PM_TECH_COUNT 91 }pm_tech_process_t; 92 93 typedef enum pm_rev_num_e { 94 PM_REVISION_NUM_INVALID, 95 PM_REVISION_0, 96 PM_REVISION_1, 97 PM_REVISION_2, 98 PM_REVISION_3, 99 PM_REVISION_4, 100 PM_REVISION_5, 101 PM_REVISION_6, 102 PM_REVISION_7, 103 PM_REVISION_NUM_COUNT 104 }pm_rev_num_t; 105 106 typedef enum pm_rev_letter_e { 107 PM_REVISION_LETTER_INVALID, 108 PM_REVISION_A, 109 PM_REVISION_B, 110 PM_REVISION_C, 111 PM_REVISION_D, 112 PM_REVISION_LETTER_COUNT 113 }pm_rev_letter_t; 114 115 typedef struct pm_version_s{ 116 pm_type_t type; 117 pm_gen_t gen; 118 pm_tech_process_t tech_process; 119 pm_rev_num_t revision_number; 120 pm_rev_letter_t revision_letter; 121 }pm_version_t; 122 123 typedef struct pm4x10_s *pm4x10_t; 124 typedef struct pm4x10q_s *pm4x10q_t; 125 typedef struct pm4x25_s *pm4x25_t; 126 typedef struct pm12x10_s *pm12x10_t; 127 typedef struct dnx_fabric_s *dnx_fabric_t; 128 typedef struct pm8x50_fabric_s *pm8x50_fabric_t; 129 typedef struct pmOsIlkn_s *pmOsIlkn_t; 130 typedef struct pm_qtc_s *pm_qtc_t; 131 typedef struct pm4x2p5_s *pm4x2p5_t; 132 typedef struct pm8x50_s *pm8x50_t; 133 typedef struct pm4x10_qtc_s *pm4x10_qtc_t; 134 135 typedef union pm_db_u{ 136 pm4x10_t pm4x10_db; 137 pm4x10q_t pm4x10q_db; 138 dnx_fabric_t dnx_fabric; 139 pm8x50_fabric_t pm8x50_fabric; 140 pm4x25_t pm4x25_db; 141 pm12x10_t pm12x10_db; 142 pmOsIlkn_t pmOsIlkn_db; 143 pm_qtc_t pm_qtc_db; 144 pm4x2p5_t pm4x2p5_db; 145 pm8x50_t pm8x50_db; 146 pm4x10_qtc_t pm4x10_qtc_db; 147 }pm_db_t; 148 149 150 /* This structure cntain specific PM state. 151 it's pointed from pms array in portmod.c */ 152 struct pm_info_s{ 153 portmod_dispatch_type_t type; /* PM type (used manly for dispatching)*/ 154 int unit; /* PM unit ID */ 155 int wb_buffer_id; /* Buffer id is given for each PM (see warmboot description in portmod.c) */ 156 int wb_vars_ids[MAX_VARS_PER_BUFFER]; /* Allotcaed WB variables for this PM */ 157 pm_db_t pm_data; /* PM internal state. This information is internal, and mainted in the speicifc PM c code*/ 158 }; 159 160 typedef struct pm_info_s *pm_info_t; 161 162 /* When port macro is added to the PMM the user passing in specific PM required information. 163 In some cases the PMM rebuild another structure before sending the information to the PM 164 the *_internal_t strucutres represents the internal information as the PMM send to the PM 165 (translation code can be found in portmod.c */ 166 167 /* PM4x25: no translation is required */ 168 typedef portmod_pm4x25_create_info_t portmod_pm4x25_create_info_internal_t; 169 170 /* PM4x10: no translation is required */ 171 typedef portmod_pm4x10_create_info_t portmod_pm4x10_create_info_internal_t; 172 173 /* QTC: no translation is required */ 174 typedef portmod_pm_qtc_create_info_t portmod_pm_qtc_create_info_internal_t; 175 176 /* DNX fabric internal create structure*/ 177 typedef struct portmod_dnx_fabric_create_info_internal_s{ 178 phymod_ref_clk_t ref_clk; /**< SerDes quad ref clock */ 179 phymod_ref_clk_t com_clk; /**< SerDes commmon ref clock */ 180 phymod_access_t access; /**< phymod access structure; defines the register access for the SerDes Core */ 181 phymod_lane_map_t lane_map; 182 phymod_firmware_load_method_t fw_load_method; 183 phymod_firmware_loader_f external_fw_loader; /**< firmware loader that will be used in case that fw_load_method=phymodFirmwareLoadMethodExternal */ 184 phymod_polarity_t polarity; /**< Lanes Polarity */ 185 int fmac_schan_id; /**< FMAC schan id */ 186 int fsrd_schan_id; /**< FSRD schan id */ 187 int fsrd_internal_quad; /**< Core instance in FSRD */ 188 int first_phy_offset; 189 int core_index; 190 int is_over_nif; 191 pm_info_t *pms; /**< PM used for fabric over nif */ 192 }portmod_dnx_fabric_create_info_internal_t; 193 194 /* PM8x50_fabric internal create structure*/ 195 typedef struct portmod_pm8x50_fabric_create_info_internal_s{ 196 phymod_ref_clk_t ref_clk; /**< SerDes quad ref clock */ 197 phymod_access_t access; /**< phymod access structure; defines the register access for the SerDes Core */ 198 phymod_firmware_load_method_t fw_load_method; 199 phymod_firmware_loader_f external_fw_loader; /**< firmware loader that will be used in case that fw_load_method=phymodFirmwareLoadMethodExternal */ 200 phymod_polarity_t polarity; /**< Lanes Polarity */ 201 int fmac_schan_id[PORTMOD_NOF_FMACS_PER_PM8X50_FABRIC]; /**< FMACs schan ids */ 202 int fsrd_schan_id; /**< FSRD schan id */ 203 int first_phy_offset; 204 int core_index; 205 uint32 force_single_pll; /**< only one PLL can be used in this core */ 206 uint32 bypass_lanes_bitmap[PORTMOD_NOF_WORDS_PER_PM8X50_FABRIC_LANES_BITMAP]; 207 int is_rx_ctrl_bypass_supported; 208 }portmod_pm8x50_fabric_create_info_internal_t; 209 210 /* PM4x10Q internal create structure*/ 211 typedef struct portmod_pm4x10q_create_info_internal_s{ 212 pm_info_t pm4x10; 213 uint32 blk_id; 214 void* qsgmii_user_acc; 215 void* pm4x10_user_acc; 216 uint32 core_clock_khz; 217 }portmod_pm4x10q_create_info_internal_t; 218 219 /* PM12x10 internal create structure*/ 220 typedef struct portmod_pm12x10_create_info_internal_s{ 221 pm_info_t pm4x25; 222 pm_info_t pm4x10[3]; 223 uint32 flags; 224 int blk_id; 225 int refclk_source; 226 }portmod_pm12x10_create_info_internal_t; 227 228 /* PM4x2p5: no translation is required */ 229 typedef portmod_pm4x2p5_create_info_t portmod_pm4x2p5_create_info_internal_t; 230 231 /* OS ILKN internal create structure*/ 232 typedef struct portmod_os_ilkn_create_info_internal_s{ 233 int nof_aggregated_pms; 234 pm_info_t *pms; 235 int *pm_ids; 236 int wm_high[PORTMOD_MAX_ILKN_PORTS_PER_ILKN_PM]; /**< watermark high value */ 237 int wm_low[PORTMOD_MAX_ILKN_PORTS_PER_ILKN_PM]; /**< watermark low value */ 238 uint8 is_over_fabric; 239 uint32 core_clock_khz; 240 portmod_ilkn_core_lane_map_callback_get_f ilkn_core_lane_map_get; 241 portmod_ilkn_pm_lane_map_callback_get_f ilkn_pm_lane_map_get; 242 uint32 ilkn_block_index; 243 }portmod_os_ilkn_create_info_internal_t; 244 245 /* PM8x50: no translation is required??? */ 246 typedef portmod_pm8x50_create_info_t portmod_pm8x50_create_info_internal_t; 247 248 /* PM4x10_qtc: no translation is required */ 249 typedef portmod_pm4x10_qtc_create_info_t portmod_pm4x10_qtc_create_info_internal_t; 250 251 /* Union for internal create structures*/ 252 typedef union portmod_pm_specific_create_info_internal_u{ 253 portmod_dnx_fabric_create_info_internal_t dnx_fabric; 254 portmod_pm8x50_fabric_create_info_internal_t pm8x50_fabric; 255 portmod_pm4x25_create_info_internal_t pm4x25; 256 portmod_pm4x10_create_info_internal_t pm4x10; 257 portmod_pm4x10q_create_info_internal_t pm4x10q; 258 portmod_pm_qtc_create_info_internal_t pm_qtc; 259 portmod_pm12x10_create_info_internal_t pm12x10; 260 portmod_os_ilkn_create_info_internal_t os_ilkn; 261 portmod_pm4x2p5_create_info_internal_t pm4x2p5; 262 portmod_pm8x50_create_info_internal_t pm8x50; 263 portmod_pm4x10_qtc_create_info_internal_t pm4x10_qtc; 264 }portmod_pm_specific_create_info_internal_t; 265 266 /* the structure which is used as input to portmod_port_macro_add function*/ 267 typedef struct portmod_pm_create_info_internal_s { 268 portmod_dispatch_type_t type; /**< PM type */ 269 portmod_pbmp_t phys; /**< which PHYs belongs to the PM */ 270 portmod_pm_specific_create_info_internal_t pm_specific_info; 271 } portmod_pm_create_info_internal_t; 272 273 /* PMs can implement xxx_default_bus_update() internal API to update phymod bus 274 When this API is implemented the below struct is used as input*/ 275 typedef struct portmod_bus_update_s { 276 phymod_firmware_loader_f external_fw_loader; 277 phymod_bus_t* default_bus; 278 void* user_acc; 279 int blk_id; 280 } portmod_bus_update_t; 281 282 /* External Phy information */ 283 typedef struct portmod_ext_phy_core_info_s 284 { 285 phymod_core_access_t core_access; /**< core access */ 286 int is_initialized; /**< Phy is Initialized - need to convert to WB */ 287 } portmod_ext_phy_core_info_t; 288 289 #define PM_DRIVER(pm_info) (__portmod__dispatch__[(pm_info)->type]) 290 291 #define XPHY_PBMP_IDX_MAX PORTMOD_MAX_NUM_XPHY_SUPPORTED 292 #define XPHY_PBMP_WORD_WIDTH 32 293 294 #define XPHY_PBMP_WORD_MAX \ 295 ((XPHY_PBMP_IDX_MAX+XPHY_PBMP_WORD_WIDTH-1)/XPHY_PBMP_WORD_WIDTH) 296 297 #define XPHY_PBMP_WORD_GET(bm,word) ((bm).pbits[(word)]) 298 #define XPHY_PBMP_WENT(idx) ((idx)/XPHY_PBMP_WORD_WIDTH) 299 300 #define XPHY_PBMP_WBIT(idx) \ 301 (1U << ((idx) % XPHY_PBMP_WORD_WIDTH)) 302 303 #define XPHY_PBMP_ENTRY(bm, idx) \ 304 (XPHY_PBMP_WORD_GET(bm,XPHY_PBMP_WENT(idx))) 305 306 #define XPHY_PBMP_MEMBER(bm, idx) \ 307 ((XPHY_PBMP_ENTRY(bm, idx) & XPHY_PBMP_WBIT(idx)) != 0) 308 309 #define XPHY_PBMP_CLEAR(pbm) do { \ 310 int _w; \ 311 for (_w = 0; _w < XPHY_PBMP_WORD_MAX; _w++) { \ 312 XPHY_PBMP_WORD_GET(bm, _w) = 0; \ 313 } \ 314 } while (0) 315 316 #define XPHY_PBMP_IDX_ADD(bm, idx) \ 317 ( XPHY_PBMP_ENTRY(bm, idx) |= XPHY_PBMP_WBIT(idx)) 318 319 #define XPHY_PBMP_IDX_REMOVE(bm, idx) \ 320 ( XPHY_PBMP_ENTRY(bm, idx) &= ~XPHY_PBMP_WBIT(idx)) 321 322 #define XPHY_PBMP_ITER(bmp, idx) \ 323 for ((idx) = 0; (idx) < XPHY_PBMP_IDX_MAX; (idx)++) \ 324 if (XPHY_PBMP_MEMBER((bmp), (idx))) 325 326 typedef struct xphy_pbmp { 327 uint32 pbits[XPHY_PBMP_WORD_MAX]; 328 } xphy_pbmp_t; 329 330 #define PORTMOD_DIV_ROUND_UP(x,y) ( ((x)+((y)-1)) / (y) ) 331 332 #define PORTMOD_BIT_COUNT(pbm, count) (count = _shr_popcount(pbm)) 333 334 typedef enum portmod_txpi_sdm_type_e { 335 FRIST_ORDER_WITH_FLOOR, /* 1st order scheme with floor follows the traditional TXPI SDM implementation. */ 336 FRIST_ORDER_WITH_ROUNDING, /* 1st order scheme with rounding is a new implementation that supposed to solve frequent updates introduced by the 1st order floor implementation. */ 337 SECOND_ORDER_WITH_ROUNDING, /* 2nd order scheme with rounding is a new implementation that supposed to solve the low frequency phase nose introduced by the 1st order implementation. */ 338 TXPI_SDM_SCHEME_COUNT 339 } portmod_txpi_sdm_type_t; 340 341 /* Flags to indicate the interrupt status and clear mechanism. */ 342 /******************************************************* 343 *************** Start of Flags ************************ 344 */ 345 346 /* NO ECC error */ 347 #define PORTMOD_PM_ECC_ERR_NONE PORTMOD_PM_ECC_NO_ERR 348 349 /* 1-bit ECC error */ 350 #define PORTMOD_INTR_ECC_1B_ERR PORTMOD_PM_ECC_1B_ERR 351 352 /* 2-bit ECC error */ 353 #define PORTMOD_INTR_ECC_2B_ERR PORTMOD_PM_ECC_2B_ERR 354 355 /* Multi-bit ECC error */ 356 #define PORTMOD_INTR_ECC_MULTIB_ERR PORTMOD_PM_ECC_MULTIB_ERR 357 358 /* Write 1 to hardware to clear the interrupt status */ 359 #define PORTMOD_INTR_STATUS_W1TC 0x8 360 361 /* Interrupt status is clear-on-read */ 362 #define PORTMOD_INTR_STATUS_COR 0x10 363 364 /* Indicates that each bit indicates an interrupt status */ 365 #define PORTMOD_INTR_STATUS_BIT_FLDS 0x20 366 367 /* 368 * indicates an ECC error interrupt along with 369 * memory address information. 370 */ 371 #define PORTMOD_INTR_READ_ECC_ADDR 0x40 372 373 /* 374 * Indicates an ECC error interrupt with no 375 * memory address information. 376 * 1-bit ECC error. 377 */ 378 #define PORTMOD_INTR_NO_READ_ECC_ADDR 0x80 379 380 /* 381 * Indicates that the clear mechanism is per block 382 * and not per port. 383 */ 384 #define PORTMOD_INTR_BLOCK_CLEAR_REG 0x100 385 386 /******************************************************* 387 *************** End of Flags ************************** 388 */ 389 390 typedef struct portmod_intr_reg_info_s { 391 uint32 flags; 392 portmod_intr_type_t intr_type; 393 soc_reg_t en_reg; 394 soc_field_t en_fld; 395 soc_reg_t st_reg; 396 soc_field_t st_fld; 397 soc_reg_t clr_reg; 398 soc_field_t clr_fld; 399 char *str; 400 soc_reg_t addr_reg; 401 soc_field_t addr_fld; 402 }portmod_intr_reg_info_t; 403 404 405 typedef struct portmod_pm_intr_info_s { 406 /* 407 * Interrupt type here means the highest level of 408 * interrupt exposed an the PortMacro port block 409 * level. Typically it could be one of below types 410 * MAC error, TSC error, PMD error, Link intr, 411 * MIB intr, Flow control intr. 412 * Each port Macro could expose different interrupts 413 */ 414 portmod_intr_type_t intr_type; 415 soc_reg_t en_reg; 416 soc_field_t en_fld; 417 int is_intr_enable_group; 418 portmod_intr_reg_info_t *intr_list_enable_reg; 419 soc_reg_t st_reg; 420 soc_field_t st_fld; 421 int is_intr_status_group; 422 portmod_intr_reg_info_t *intr_list_status_reg; 423 soc_reg_t clr_reg; 424 soc_field_t clr_fld; 425 int is_intr_clear_group; 426 portmod_intr_reg_info_t *intr_list_clear_reg; 427 soc_mem_t mem; 428 char *mem_str; 429 }portmod_pm_intr_info_t; 430 431 /* Initialize portmod_pm_create_info_internal_t structure */ 432 int portmod_pm_create_info_internal_t_init(int unit, portmod_pm_create_info_internal_t *create_info_internal); 433 434 /* Translate PM id to PM type */ 435 int portmod_pm_id_pm_type_get(int unit, int pm_id, portmod_dispatch_type_t *type); 436 437 /* Get internal PM info from a port */ 438 int portmod_pm_info_get(int unit, int port, pm_info_t *pm_info); 439 /* Get list of PMs attached to a phy */ 440 int portmod_phy_pms_info_get(int unit, int phy, int max_pms, pm_info_t *pms_info, int *nof_pms, int *pms_ids); 441 442 int portmod_pm_info_type_get(int unit, int port, portmod_dispatch_type_t type, pm_info_t* pm_info); 443 int portmod_pm_info_from_pm_id_get(int unit, int pm_id, pm_info_t* pm_info); 444 445 int portmod_port_interface_type_get(int unit, int port, soc_port_if_t *interface); 446 int portmod_port_main_core_access_get(int unit, int port, int phyn, 447 phymod_core_access_t *core_access, 448 int *nof_cores); 449 450 /*is interface type supported by PM should be supported by all PMs types*/ 451 int portmod_pm_interface_type_is_supported(int unit, pm_info_t pm_info, soc_port_if_t interface, int* is_supported); 452 453 int portmod_pm_init(int unit, const portmod_pm_create_info_internal_t* pm_add_info, int wb_buffer_index, pm_info_t pm_info); 454 int portmod_pm_destroy(int unit, pm_info_t pm_info); 455 int portmod_pm_core_info_get(int unit, pm_info_t pm_info, int phyn, portmod_pm_core_info_t* core_info); 456 int portmod_port_attach(int unit, int port, const portmod_port_add_info_t* add_info); 457 int portmod_port_detach(int unit, int port); 458 int portmod_port_replace(int unit, int port, int new_port); 459 int portmod_pm_aggregated_update(int unit, pm_info_t pm_info, int core_id, int nof_aggregated_pms, const pm_info_t* pms, const int* pm_ids); 460 int portmod_next_wb_var_id_get(int unit, int *var_id); 461 int portmod_ext_phy_lane_attach_to_pm(int unit, pm_info_t pm_info, int iphy, int phyn, const portmod_lane_connection_t* lane_connection); 462 int portmod_ext_phy_lane_detach_from_pm(int unit, pm_info_t pm_info, int iphy, int phyn, portmod_lane_connection_t* lane_connection); 463 464 /*! 465 * portmod_port_mac_rsv_mask_set 466 * 467 * @brief portmod port rsv mask set 468 * 469 * @param [in] unit - unit id 470 * @param [in] port - logical port 471 * @param [in] rsv_mask - rsv mask 472 */ 473 int portmod_port_mac_rsv_mask_set(int unit, int port, uint32 rsv_mask); 474 475 /*! 476 * portmod_port_mib_reset_toggle 477 * 478 * @brief portmod port mib reset toggle 479 * 480 * @param [in] unit - unit id 481 * @param [in] port - logical port 482 * @param [in] port_index - internal port 483 */ 484 int portmod_port_mib_reset_toggle(int unit, int port, int port_index); 485 486 int portmod_xphy_lane_attach_to_pm(int unit, pm_info_t pm_info, int iphy, int phyn, const portmod_xphy_lane_connection_t* lane_connection); 487 int portmod_xphy_lane_detach_from_pm(int unit, pm_info_t pm_info, int iphy, int phyn, portmod_xphy_lane_connection_t* lane_connection); 488 int portmod_max_pms_get(int unit, int* max_pms); 489 int portmod_eyescan_diag_dispatch(int unit, soc_port_t port, args_t *a); 490 int portmod_phy_pm_type_get(int unit, int phy, portmod_dispatch_type_t *type); 491 int portmod_xphy_addr_set(int unit, int idx, int xphy_addr); 492 int portmod_xphy_db_addr_set(int unit, int idx, int xphy_addr); 493 int portmod_xphy_all_valid_phys_get(int unit, xphy_pbmp_t *active_phys); 494 int portmod_xphy_valid_phy_set (int unit, int xphy_idx, int valid); 495 int portmod_xphy_valid_phy_get (int unit, int xphy_idx, int *valid); 496 int portmod_xphy_db_addr_get(int unit, int xphy_idx, int* xphy_addr); 497 498 499 /*! 500 * portmod_pm_is_in_pm12x10 501 * 502 * @brief Get whether the Port Macro is part of PM12x10 503 * 504 * @param [in] unit - unit id 505 * @param [in] pm_info - 506 * @param [out] in_pm12x10 - 507 */ 508 int portmod_pm_is_in_pm12x10(int unit, pm_info_t pm_info, int* in_pm12x10); 509 510 /*! 511 * portmod_port_lane_count_get 512 * 513 * @brief Get the number of lanes belong to a logical port. 514 * 515 * @param [in] unit - unit id 516 * @param [in] port - logical port 517 * @param [in] line_side - line side 1, sys_side 0 518 * @param [out] num_lanes - num of line side lanes 519 */ 520 int portmod_port_lane_count_get(int unit, int port, int line_side, int* num_lanes); 521 522 523 #ifdef FW_BCAST_DOWNLOAD 524 int portmod_fw_bcast(int unit, pm_info_t pm_info, const portmod_sbus_bcast_config_t* sbus_bcast_cfg); 525 #endif 526 527 /*! 528 * portmod_pm_capability_get 529 * 530 * @brief Get PortMacro specific capabilites 531 * 532 * @param [in] unit - unit id 533 * @param [out] pm_cap - PM specific capabilities 534 */ 535 int portmod_pm_specific_capability_get(int unit, 536 portmod_pm_capability_t* pm_cap); 537 538 539 /*******************************************************************/ 540 /** PMs Periodic events **/ 541 /*******************************************************************/ 542 /* 543 The below functions enable the PMs to regitser per-port periodic events. 544 545 When PM decided periodic operation is required it can register it using 546 portmod_port_periodic_callback_register API. 547 548 When the operation is no longer required call 549 portmod_port_periodic_callback_unregister API 550 551 Note that callback should be re-registered upon WB. 552 553 */ 554 555 /*! 556 * Callback for per port periodic event 557 */ 558 typedef int (*portmod_periodic_event_f)(int unit, int port); 559 560 /*! 561 * 562 * portmod_port_periodic_callback_unregister 563 * 564 * @brief - unregister port periodic event 565 * 566 * @param unit - unit # 567 * @param port - port to unregister callback 568 * 569 * @note This API has protection between callback context and main thread. 570 * Except of callback context usage - it doesn't allow other multithreading. 571 */ 572 int portmod_port_periodic_callback_unregister(int unit, int port); 573 574 575 /*! 576 * portmod_port_periodic_callback_register 577 * 578 * @brief - register port periodic event 579 * 580 * @param unit - unit # 581 * @param port - port to register callback 582 * @param callback - callback to be called periodically 583 * @param interval - expected period (actual period will be 584 * equal or smaller from given value). 585 * 586 * @note 587 * 1. Callback must be re-registers after WB 588 * 2. This API has protection between callback context and main thread. 589 * Except of callback context usage - it doesn't allow other multithreading. 590 */ 591 int portmod_port_periodic_callback_register(int unit, int port, portmod_periodic_event_f callback, int interval); 592 593 594 /*! 595 * portmod_port_periodic_handler_get 596 * 597 * @brief - get handler to periodic event object 598 * the purpose of it is unit testing only 599 * 600 * @param unit - unit # 601 * @param pe_handler - periodic event current interval 602 */ 603 int portmod_port_periodic_interval_get(int unit, int* interval); 604 605 /*******************************************************************/ 606 607 int portmod_core_pm_id_get(int unit, int core_num, int *pm_id); 608 int portmod_pm_core_num_get(int unit, pm_info_t pm_info, int* core_num); 609 610 611 612 /*! 613 * portmod_ilkn_block_phys_set 614 * 615 * @brief - set the phys used by a specific ilkn block id in SW-state 616 * 617 * @param unit - unit # 618 * @param ilkn_block_id - ilkn block id 619 * @param phys - bitmap of phys usded for the specific ilkn block 620 * @param enable - 0 | 1 set ore remove the phys to the ilkn block 621 */ 622 int portmod_ilkn_block_phys_set(int unit, int ilkn_block_id, portmod_pbmp_t phys, int enable); 623 624 #endif /*_PORTMOD_INTERNAL_H_*/ 625 626 #ifdef CPRIMOD_SUPPORT 627 /*! 628 * portmod_cpri_port_interrupt_link_status_get 629 * 630 * @brief Get the CPRI Port interrupt status. 631 * 632 * @param [in] unit - unit id 633 * @param [in] port - logical port 634 * @param [in] is_link_intr_status - 635 */ 636 int portmod_cpri_port_interrupt_link_status_get(int unit, int port, const int* is_link_intr_status); 637 #endif