portmod.h (329395B)
1 /* 2 * 3 * 4 * 5 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 6 * 7 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 8 * 9 * 10 * DO NOT EDIT THIS FILE! 11 */ 12 13 #ifndef _PORTMOD_H__H_ 14 #define _PORTMOD_H__H_ 15 16 #include <phymod/phymod.h> 17 #include <phymod/phymod_diagnostics.h> 18 #include <phymod/phymod_reg.h> 19 #include <soc/cprimod/cprimod.h> 20 #include <soc/portmod/portmod_defs.h> 21 22 /*! 23 * @enum portmod_dispatch_type_e 24 * @brief Supported Drivers 25 */ 26 typedef enum portmod_dispatch_type_e { 27 #ifdef PORTMOD_PM4X25_SUPPORT 28 portmodDispatchTypePm4x25, 29 #endif /*PORTMOD_PM4X25_SUPPORT */ 30 #ifdef PORTMOD_PM4X10_SUPPORT 31 portmodDispatchTypePm4x10, 32 #endif /*PORTMOD_PM4X10_SUPPORT */ 33 #ifdef PORTMOD_PM4X10TD_SUPPORT 34 portmodDispatchTypePm4x10td, 35 #endif /*PORTMOD_PM4X10TD_SUPPORT */ 36 #ifdef PORTMOD_PM12X10_SUPPORT 37 portmodDispatchTypePm12x10, 38 #endif /*PORTMOD_PM12X10_SUPPORT */ 39 #ifdef PORTMOD_PM4x10Q_SUPPORT 40 portmodDispatchTypePm4x10Q, 41 #endif /*PORTMOD_PM4x10Q_SUPPORT */ 42 #ifdef PORTMOD_PM_QTC_SUPPORT 43 portmodDispatchTypePm_qtc, 44 #endif /*PORTMOD_PM_QTC_SUPPORT */ 45 #ifdef PORTMOD_PM_OS_ILKN_SUPPORT 46 portmodDispatchTypePmOsILKN, 47 #endif /*PORTMOD_PM_OS_ILKN_SUPPORT */ 48 #ifdef PORTMOD_PM_OS_ILKN_50G_SUPPORT 49 portmodDispatchTypePmOsILKN_50G, 50 #endif /*PORTMOD_PM_OS_ILKN_50G_SUPPORT */ 51 #ifdef PORTMOD_DNX_FABRIC_SUPPORT 52 portmodDispatchTypeDnx_fabric, 53 #endif /*PORTMOD_DNX_FABRIC_SUPPORT */ 54 #ifdef PORTMOD_DNX_FABRIC_O_NIF_SUPPORT 55 portmodDispatchTypeDnx_fabric_o_nif, 56 #endif /*PORTMOD_DNX_FABRIC_O_NIF_SUPPORT */ 57 #ifdef PORTMOD_PM8X50_FABRIC_SUPPORT 58 portmodDispatchTypePm8x50_fabric, 59 #endif /*PORTMOD_PM8X50_FABRIC_SUPPORT */ 60 #ifdef PORTMOD_PM4X25TD_SUPPORT 61 portmodDispatchTypePm4x25td, 62 #endif /*PORTMOD_PM4X25TD_SUPPORT */ 63 #ifdef PORTMOD_PM12X10_XGS_SUPPORT 64 portmodDispatchTypePm12x10_xgs, 65 #endif /*PORTMOD_PM12X10_XGS_SUPPORT */ 66 #ifdef PORTMOD_PM4X2P5_SUPPORT 67 portmodDispatchTypePm4x2p5, 68 #endif /*PORTMOD_PM4X2P5_SUPPORT */ 69 #ifdef PORTMOD_CPM4X25_SUPPORT 70 portmodDispatchTypeCpm4x25, 71 #endif /*PORTMOD_CPM4X25_SUPPORT */ 72 #ifdef PORTMOD_PM8X50_SUPPORT 73 portmodDispatchTypePm8x50, 74 #endif /*PORTMOD_PM8X50_SUPPORT */ 75 #ifdef PORTMOD_PM4X10_QTC_SUPPORT 76 portmodDispatchTypePm4x10_qtc, 77 #endif /*PORTMOD_PM4X10_QTC_SUPPORT */ 78 #ifdef PORTMOD_PMNULL_SUPPORT 79 portmodDispatchTypePmNull, 80 #endif /*PORTMOD_PMNULL_SUPPORT */ 81 portmodDispatchTypeCount 82 } portmod_dispatch_type_t; 83 84 #ifdef PORTMOD_DIAG 85 extern enum_mapping_t portmod_dispatch_type_t_mapping[]; 86 #endif /*PORTMOD_DIAG*/ 87 88 /* portmod_dispatch_type_t validation */ 89 int portmod_dispatch_type_t_validate(int unit, portmod_dispatch_type_t portmod_dispatch_type); 90 /*! 91 * @brief Flags for user access struct 92 */ 93 #define PORTMOD_USER_ACCESS_FW_LOAD_REVERSE 0x1 /**< Load FW in reverse mode */ 94 #define PORTMOD_USER_ACCESS_REG_VAL_OFFSET_ZERO 0x2 /**< When reading register using UCMEM the data is in offset 0 */ 95 #define PORTMOD_USER_ACCESS_FW_LOAD_BROADCAST 0x4 /**< Load FW in broadcast mode */ 96 97 #define PORTMOD_USER_ACCESS_FW_LOAD_REVERSE_SET(user_data) ((user_data->flags) |= PORTMOD_USER_ACCESS_FW_LOAD_REVERSE) 98 #define PORTMOD_USER_ACCESS_REG_VAL_OFFSET_ZERO_SET(user_data) ((user_data->flags) |= PORTMOD_USER_ACCESS_REG_VAL_OFFSET_ZERO) 99 #define PORTMOD_USER_ACCESS_FW_LOAD_BROADCAST_SET(user_data) ((user_data->flags) |= PORTMOD_USER_ACCESS_FW_LOAD_BROADCAST) 100 101 #define PORTMOD_USER_ACCESS_FW_LOAD_REVERSE_CLR(user_data) ((user_data->flags) &= ~PORTMOD_USER_ACCESS_FW_LOAD_REVERSE) 102 #define PORTMOD_USER_ACCESS_REG_VAL_OFFSET_ZERO_CLR(user_data) ((user_data->flags) &= ~PORTMOD_USER_ACCESS_REG_VAL_OFFSET_ZERO) 103 #define PORTMOD_USER_ACCESS_FW_LOAD_BROADCAST_CLR(user_data) ((user_data->flags) &= ~PORTMOD_USER_ACCESS_FW_LOAD_BROADCAST) 104 105 #define PORTMOD_USER_ACCESS_FW_LOAD_REVERSE_GET(user_data) ((user_data->flags) & PORTMOD_USER_ACCESS_FW_LOAD_REVERSE ? 1 : 0) 106 #define PORTMOD_USER_ACCESS_REG_VAL_OFFSET_ZERO_GET(user_data) ((user_data->flags) & PORTMOD_USER_ACCESS_REG_VAL_OFFSET_ZERO ? 1 : 0) 107 #define PORTMOD_USER_ACCESS_FW_LOAD_BROADCAST_GET(user_data) ((user_data->flags) & PORTMOD_USER_ACCESS_FW_LOAD_BROADCAST ? 1 : 0) 108 109 110 /*! 111 * @struct portmod_default_user_access_s 112 * @brief Expected user access structure when using PM default bus 113 */ 114 typedef struct portmod_default_user_access_s { 115 int unit; /**< Unit that will be used for phy access */ 116 int blk_id; /**< block id */ 117 sal_mutex_t mutex; /**< Mutex operation for phy access */ 118 uint32 flags; /**< user access flags */ 119 } portmod_default_user_access_t; 120 121 /* portmod_default_user_access_t initialization and validation */ 122 int portmod_default_user_access_t_validate(int unit, const portmod_default_user_access_t* portmod_default_user_access); 123 int portmod_default_user_access_t_init(int unit, portmod_default_user_access_t* portmod_default_user_access); 124 125 126 /*! 127 * @struct portmod_pm4x10q_user_data_s 128 * @brief Expected qsgmii user access structure when using PMQ default bus 129 */ 130 typedef struct portmod_pm4x10q_user_data_s { 131 phymod_access_t pm4x10_access; /**< Unit that will be used for phy access */ 132 portmod_default_user_access_t qsgmiie_user_data; /**< qsgmii_access */ 133 } portmod_pm4x10q_user_data_t; 134 135 /* portmod_pm4x10q_user_data_t initialization and validation */ 136 int portmod_pm4x10q_user_data_t_validate(int unit, const portmod_pm4x10q_user_data_t* portmod_pm4x10q_user_data); 137 int portmod_pm4x10q_user_data_t_init(int unit, portmod_pm4x10q_user_data_t* portmod_pm4x10q_user_data); 138 139 140 /*! 141 * @struct portmod_fifo_status_s 142 * @brief In Fifo Time stamp and sequence id value. 143 */ 144 typedef struct portmod_fifo_status_s { 145 uint32 timestamps_in_fifo; /**< low 32bit of Timestamp in Fifo */ 146 uint32 timestamps_in_fifo_hi; /**< high 32 bit of timestamp in Fifo */ 147 uint32 sequence_id; /**< sequence id of sent ptp packet */ 148 uint32 timestamp_sub_nanosec; /**< sub-nanosecond of 1588 transmit packet */ 149 } portmod_fifo_status_t; 150 151 /* portmod_fifo_status_t initialization and validation */ 152 int portmod_fifo_status_t_validate(int unit, const portmod_fifo_status_t* portmod_fifo_status); 153 int portmod_fifo_status_t_init(int unit, portmod_fifo_status_t* portmod_fifo_status); 154 155 156 /*! 157 * @struct portmod_pfc_config_s 158 * @brief PFC Config Information. 159 */ 160 typedef struct portmod_pfc_config_s { 161 uint32 type; /**< PFC Ether Type */ 162 uint32 opcode; /**< PFC Message Opcode */ 163 uint32 classes; /**< PFC Classes */ 164 uint32 da_oui; /**< PFC OUI Msg OUI Dest Addr */ 165 uint32 da_nonoui; /**< PFC Non OUI Dest Addr */ 166 uint32 rxpass; /**< PFC rxpass */ 167 } portmod_pfc_config_t; 168 169 /* portmod_pfc_config_t initialization and validation */ 170 int portmod_pfc_config_t_validate(int unit, const portmod_pfc_config_t* portmod_pfc_config); 171 int portmod_pfc_config_t_init(int unit, portmod_pfc_config_t* portmod_pfc_config); 172 173 174 /*! 175 * @struct portmod_eee_s 176 * @brief EEE Timer Information. 177 */ 178 typedef struct portmod_eee_s { 179 uint32 enable; /**< EEE Enable */ 180 uint32 tx_idle_time; /**< EEE tx idle time */ 181 uint32 tx_wake_time; /**< EEE tx wake time */ 182 } portmod_eee_t; 183 184 /* portmod_eee_t initialization and validation */ 185 int portmod_eee_t_validate(int unit, const portmod_eee_t* portmod_eee); 186 int portmod_eee_t_init(int unit, portmod_eee_t* portmod_eee); 187 188 189 /*! 190 * @struct portmod_eee_clock_s 191 * @brief EEE clock gate Information. 192 */ 193 typedef struct portmod_eee_clock_s { 194 uint32 clock_gate; /**< EEE Clock Gate */ 195 uint32 clock_count; /**< EEE clock counter */ 196 uint32 timer_pulse; /**< EEE timer pulse */ 197 } portmod_eee_clock_t; 198 199 /* portmod_eee_clock_t initialization and validation */ 200 int portmod_eee_clock_t_validate(int unit, const portmod_eee_clock_t* portmod_eee_clock); 201 int portmod_eee_clock_t_init(int unit, portmod_eee_clock_t* portmod_eee_clock); 202 203 204 /*! 205 * @struct portmod_vlan_tag_s 206 * @brief Vlan Tag Inner/Outer Values. 207 */ 208 typedef struct portmod_vlan_tag_s { 209 int inner_vlan_tag; /**< Inner Vlan Tag */ 210 int outer_vlan_tag; /**< Outer Vlan Tag */ 211 } portmod_vlan_tag_t; 212 213 /* portmod_vlan_tag_t initialization and validation */ 214 int portmod_vlan_tag_t_validate(int unit, const portmod_vlan_tag_t* portmod_vlan_tag); 215 int portmod_vlan_tag_t_init(int unit, portmod_vlan_tag_t* portmod_vlan_tag); 216 217 #define PORTMOD_MAC_PASS_CONTROL_FRAME 0x1 /**< pass control frame to system side */ 218 #define PORTMOD_MAC_PASS_PFC_FRAME 0x2 /**< pass pfc frame to system side */ 219 #define PORTMOD_MAC_PASS_PAUSE_FRAME 0x4 /**< pass pause frame to system side */ 220 221 222 /*! 223 * @struct portmod_rx_control_s 224 * @brief Rx Control Pass control frames. 225 */ 226 typedef struct portmod_rx_control_s { 227 uint32 flags; /**< bitmap for rx Frames */ 228 uint32 pass_control_frames; /**< Pass Control Frames */ 229 uint32 pass_pfc_frames; /**< Pass PFC Frames */ 230 uint32 pass_pause_frames; /**< Pass pause Frames */ 231 } portmod_rx_control_t; 232 233 /* portmod_rx_control_t initialization and validation */ 234 int portmod_rx_control_t_validate(int unit, const portmod_rx_control_t* portmod_rx_control); 235 int portmod_rx_control_t_init(int unit, portmod_rx_control_t* portmod_rx_control); 236 237 typedef struct portmod_multi_get_s { 238 uint32 flags; 239 uint32 dev_addr; 240 uint32 offset; 241 uint32 max_size; 242 unsigned char* data; 243 uint32* actual_size; 244 } portmod_multi_get_t; 245 246 /* portmod_multi_get_t initialization and validation */ 247 int portmod_multi_get_t_validate(int unit, const portmod_multi_get_t* portmod_multi_get); 248 int portmod_multi_get_t_init(int unit, portmod_multi_get_t* portmod_multi_get); 249 250 #define PORTMOD_NUM_PATTERN_DATA_INTS (8) 251 #define PORTMOD_TSCE_LANE_NAME_LEN (30) 252 253 #define PORTMOD_PCS_8B9B_LFEC _SHR_PORT_PCS_8B9BLFEC 254 #define PORTMOD_PCS_8B10B _SHR_PORT_PCS_8B10B 255 #define PORTMOD_PCS_64B66B_FEC _SHR_PORT_PCS_64B66BFEC /**< 64/66b FEC */ 256 #define PORTMOD_PCS_64B66B_BEC _SHR_PORT_PCS_64B66BBEC /**< 64/66b BEC */ 257 #define PORTMOD_PCS_64B66B _SHR_PORT_PCS_64B66B /**< 64/66b without FEC */ 258 #define PORTMOD_PCS_64B66B_RS_FEC _SHR_PORT_PCS_64B66B_RS_FEC /**< 64/66b reed solomon FEC */ 259 #define PORTMOD_PCS_64B66B_LOW_LATENCY_RS_FEC _SHR_PORT_PCS_64B66B_LOW_LATENCY_RS_FEC /**< 64/66b low latency reed solomon FEC */ 260 #define PORTMOD_PCS_64B66B_15T_RS_FEC _SHR_PORT_PCS_64B66B_15T_RS_FEC /**< 64/66b 15T reed solomon FEC */ 261 #define PORTMOD_PCS_64B66B_15T_LOW_LATENCY_RS_FEC _SHR_PORT_PCS_64B66B_15T_LOW_LATENCY_RS_FEC /**< 64/66b 15T low latency reed solomon FEC */ 262 #define PORTMOD_PCS_UNKNOWN _SHR_PORT_PCS_UNKNOWN /**< unknown pcs */ 263 264 #define PORTMOD_CL37_DISABLE (0x0) 265 #define PORTMOD_CL37_W_BAM (0x1) 266 #define PORTMOD_CL37_WO_BAM (0x2) 267 #define PORTMOD_CL37_W_10G (0x3) 268 #define PORTMOD_CL37_HR2SPM (0x4) 269 #define PORTMOD_CL37_HR2SPM_W_10G (0x5) 270 #define PORTMOD_CL37_W_BAM_HG (0x6) 271 #define PORTMOD_CL37_SGMII_COMBO (0x7) 272 273 #define PORTMOD_CL73_DISABLE (0x0) 274 #define PORTMOD_CL73_WO_BAM (0x2) 275 #define PORTMOD_CL73_W_BAM (0x1) 276 #define PORTMOD_CL73_MSA (0x3) 277 #define PORTMOD_MSA (0x4) 278 #define PORTMOD_CL73_CL37 (0x5) 279 #define PORTMOD_CL73_HG (0x6) 280 #define PORTMOD_CL73_HPAM (0x7) 281 #define PORTMOD_CL73_HPAM_VS_SW (0x8) 282 283 typedef _shr_port_pcs_t portmod_port_pcs_t; 284 285 /*! 286 * @brief Flags for port enable set. no flags means RX+TX for MAC and PHY 287 */ 288 #define PORTMOD_PORT_ENABLE_MAC 0x1 /**< enable/disable the MAC(RX/TX according to the flags) */ 289 #define PORTMOD_PORT_ENABLE_PHY 0x2 /**< enable/disable the Serdes (RX/TX according to the flags) */ 290 #define PORTMOD_PORT_ENABLE_TX 0x4 /**< enable/disable TX */ 291 #define PORTMOD_PORT_ENABLE_RX 0x8 /**< enable/disable RX */ 292 #define PORTMOD_PORT_ENABLE_INTERNAL_PHY_ONLY 0x10 /**< enable/disable only the internal phy */ 293 294 #define PORTMOD_PORT_ENABLE_MAC_SET(flags) ((flags) |= PORTMOD_PORT_ENABLE_MAC) 295 #define PORTMOD_PORT_ENABLE_PHY_SET(flags) ((flags) |= PORTMOD_PORT_ENABLE_PHY) 296 #define PORTMOD_PORT_ENABLE_TX_SET(flags) ((flags) |= PORTMOD_PORT_ENABLE_TX) 297 #define PORTMOD_PORT_ENABLE_RX_SET(flags) ((flags) |= PORTMOD_PORT_ENABLE_RX) 298 #define PORTMOD_PORT_ENABLE_INTERNAL_PHY_ONLY_SET(flags) ((flags) |= PORTMOD_PORT_ENABLE_INTERNAL_PHY_ONLY) 299 300 #define PORTMOD_PORT_ENABLE_MAC_CLR(flags) ((flags) &= ~PORTMOD_PORT_ENABLE_MAC) 301 #define PORTMOD_PORT_ENABLE_PHY_CLR(flags) ((flags) &= ~PORTMOD_PORT_ENABLE_PHY) 302 #define PORTMOD_PORT_ENABLE_TX_CLR(flags) ((flags) &= ~PORTMOD_PORT_ENABLE_TX) 303 #define PORTMOD_PORT_ENABLE_RX_CLR(flags) ((flags) &= ~PORTMOD_PORT_ENABLE_RX) 304 #define PORTMOD_PORT_ENABLE_INTERNAL_PHY_ONLY_CLR(flags) ((flags) &= ~PORTMOD_PORT_ENABLE_INTERNAL_PHY_ONLY) 305 306 #define PORTMOD_PORT_ENABLE_MAC_GET(flags) ((flags) & PORTMOD_PORT_ENABLE_MAC ? 1 : 0) 307 #define PORTMOD_PORT_ENABLE_PHY_GET(flags) ((flags) & PORTMOD_PORT_ENABLE_PHY ? 1 : 0) 308 #define PORTMOD_PORT_ENABLE_TX_GET(flags) ((flags) & PORTMOD_PORT_ENABLE_TX ? 1 : 0) 309 #define PORTMOD_PORT_ENABLE_RX_GET(flags) ((flags) & PORTMOD_PORT_ENABLE_RX ? 1 : 0) 310 #define PORTMOD_PORT_ENABLE_INTERNAL_PHY_ONLY_GET(flags) ((flags) & PORTMOD_PORT_ENABLE_INTERNAL_PHY_ONLY ? 1 : 0) 311 312 /*! 313 * @brief Flags for TX paramas setting method 314 */ 315 #define PORTMOD_USER_SET_TX_PREEMPHASIS_BY_CONFIG 0x1 /**< preemphasis by configuration setting */ 316 #define PORTMOD_USER_SET_TX_AMP_BY_CONFIG 0x2 /**< preemphasis by configuration setting */ 317 #define PORTMOD_USER_SET_TX_PREEMPHASIS_BY_API 0x4 /**< by api call */ 318 #define PORTMOD_USER_SET_TX_AMP_BY_API 0x8 /**< by api call */ 319 320 #define PORTMOD_USER_SET_TX_PREEMPHASIS_BY_CONFIG_SET(flags) ((flags) |= PORTMOD_USER_SET_TX_PREEMPHASIS_BY_CONFIG) 321 #define PORTMOD_USER_SET_TX_AMP_BY_CONFIG_SET(flags) ((flags) |= PORTMOD_USER_SET_TX_AMP_BY_CONFIG) 322 #define PORTMOD_USER_SET_TX_PREEMPHASIS_BY_API_SET(flags) ((flags) |= PORTMOD_USER_SET_TX_PREEMPHASIS_BY_API) 323 #define PORTMOD_USER_SET_TX_AMP_BY_API_SET(flags) ((flags) |= PORTMOD_USER_SET_TX_AMP_BY_API) 324 325 #define PORTMOD_USER_SET_TX_PREEMPHASIS_BY_CONFIG_CLR(flags) ((flags) &= ~PORTMOD_USER_SET_TX_PREEMPHASIS_BY_CONFIG) 326 #define PORTMOD_USER_SET_TX_AMP_BY_CONFIG_CLR(flags) ((flags) &= ~PORTMOD_USER_SET_TX_AMP_BY_CONFIG) 327 #define PORTMOD_USER_SET_TX_PREEMPHASIS_BY_API_CLR(flags) ((flags) &= ~PORTMOD_USER_SET_TX_PREEMPHASIS_BY_API) 328 #define PORTMOD_USER_SET_TX_AMP_BY_API_CLR(flags) ((flags) &= ~PORTMOD_USER_SET_TX_AMP_BY_API) 329 330 #define PORTMOD_USER_SET_TX_PREEMPHASIS_BY_CONFIG_GET(flags) ((flags) & PORTMOD_USER_SET_TX_PREEMPHASIS_BY_CONFIG ? 1 : 0) 331 #define PORTMOD_USER_SET_TX_AMP_BY_CONFIG_GET(flags) ((flags) & PORTMOD_USER_SET_TX_AMP_BY_CONFIG ? 1 : 0) 332 #define PORTMOD_USER_SET_TX_PREEMPHASIS_BY_API_GET(flags) ((flags) & PORTMOD_USER_SET_TX_PREEMPHASIS_BY_API ? 1 : 0) 333 #define PORTMOD_USER_SET_TX_AMP_BY_API_GET(flags) ((flags) & PORTMOD_USER_SET_TX_AMP_BY_API ? 1 : 0) 334 335 /*! 336 * @brief properties for portmod_port_encoding_set, portmod_port_encoding_get 337 */ 338 #define PORTMOD_ENCODING_LOW_LATENCY_LLFC 0x1 /**< 0: flow control indications sent on cell header / 1: flow control indications sent on FEC frames */ 339 #define PORTMOD_ENCODING_FEC_ERROR_DETECT 0x2 /**< enable/disable error marking (add/remove error indications on the frame) */ 340 #define PORTMOD_ENCODING_EXTRCT_CIG_FROM_LLFC 0x4 /**< enable/disable extracting CIG information from LLFC cells */ 341 #define PORTMOD_ENCODING_LLFC_AFTER_FEC 0x8 /**< enable/disable FEC on LLFC and congestion indication */ 342 #define PORTMOD_ENCODING_CONTROL_CELLS_FEC_BYPASS 0x10 /**< enable/disable FEC bypass on flow status and credit control cells */ 343 344 #define PORTMOD_ENCODING_LOW_LATENCY_LLFC_SET(properties) ((properties) |= PORTMOD_ENCODING_LOW_LATENCY_LLFC) 345 #define PORTMOD_ENCODING_FEC_ERROR_DETECT_SET(properties) ((properties) |= PORTMOD_ENCODING_FEC_ERROR_DETECT) 346 #define PORTMOD_ENCODING_EXTRCT_CIG_FROM_LLFC_SET(properties) ((properties) |= PORTMOD_ENCODING_EXTRCT_CIG_FROM_LLFC) 347 #define PORTMOD_ENCODING_LLFC_AFTER_FEC_SET(properties) ((properties) |= PORTMOD_ENCODING_LLFC_AFTER_FEC) 348 #define PORTMOD_ENCODING_CONTROL_CELLS_FEC_BYPASS_SET(properties) ((properties) |= PORTMOD_ENCODING_CONTROL_CELLS_FEC_BYPASS) 349 350 #define PORTMOD_ENCODING_LOW_LATENCY_LLFC_CLR(properties) ((properties) &= ~PORTMOD_ENCODING_LOW_LATENCY_LLFC) 351 #define PORTMOD_ENCODING_FEC_ERROR_DETECT_CLR(properties) ((properties) &= ~PORTMOD_ENCODING_FEC_ERROR_DETECT) 352 #define PORTMOD_ENCODING_EXTRCT_CIG_FROM_LLFC_CLR(properties) ((properties) &= ~PORTMOD_ENCODING_EXTRCT_CIG_FROM_LLFC) 353 #define PORTMOD_ENCODING_LLFC_AFTER_FEC_CLR(properties) ((properties) &= ~PORTMOD_ENCODING_LLFC_AFTER_FEC) 354 #define PORTMOD_ENCODING_CONTROL_CELLS_FEC_BYPASS_CLR(properties) ((properties) &= ~PORTMOD_ENCODING_CONTROL_CELLS_FEC_BYPASS) 355 356 #define PORTMOD_ENCODING_LOW_LATENCY_LLFC_GET(properties) ((properties) & PORTMOD_ENCODING_LOW_LATENCY_LLFC ? 1 : 0) 357 #define PORTMOD_ENCODING_FEC_ERROR_DETECT_GET(properties) ((properties) & PORTMOD_ENCODING_FEC_ERROR_DETECT ? 1 : 0) 358 #define PORTMOD_ENCODING_EXTRCT_CIG_FROM_LLFC_GET(properties) ((properties) & PORTMOD_ENCODING_EXTRCT_CIG_FROM_LLFC ? 1 : 0) 359 #define PORTMOD_ENCODING_LLFC_AFTER_FEC_GET(properties) ((properties) & PORTMOD_ENCODING_LLFC_AFTER_FEC ? 1 : 0) 360 #define PORTMOD_ENCODING_CONTROL_CELLS_FEC_BYPASS_GET(properties) ((properties) & PORTMOD_ENCODING_CONTROL_CELLS_FEC_BYPASS ? 1 : 0) 361 362 #define PORTMOD_MAX_CORES_PER_PORT (3) 363 364 #define PORTMOD_TS_ADJUST_NUM_OLD (8) 365 #define PORTMOD_TS_ADJUST_NUM (16) 366 367 368 /*! 369 * @enum portmod_loopback_mode_e 370 * @brief looopback modes for portmod_port_loopback_set, portmod_port_loopback_get 371 */ 372 typedef enum portmod_loopback_mode_e { 373 portmodLoopbackMacOuter = 0, 374 portmodLoopbackMacCore = 1, 375 portmodLoopbackMacPCS = 2, 376 portmodLoopbackMacAsyncFifo = 3, 377 portmodLoopbackPhyGloopPCS = 4, 378 portmodLoopbackPhyGloopPMD = 5, 379 portmodLoopbackPhyRloopPCS = 6, /**< remote PHY loopback in the PCS layer */ 380 portmodLoopbackPhyRloopPMD = 7, /**< remote PHY loopback in the PMD layer */ 381 portmodLoopbackMacRloop = 8, /**< remote MAC loopback */ 382 portmodLoopbackCount 383 } portmod_loopback_mode_t; 384 385 #ifdef PORTMOD_DIAG 386 extern enum_mapping_t portmod_loopback_mode_t_mapping[]; 387 #endif /*PORTMOD_DIAG*/ 388 389 /* portmod_loopback_mode_t validation */ 390 int portmod_loopback_mode_t_validate(int unit, portmod_loopback_mode_t portmod_loopback_mode); 391 392 /*! 393 * @enum portmod_core_port_mode_e 394 * @brief Port Modes for MAC 395 */ 396 typedef enum portmod_core_port_mode_e { 397 portmodPortModeQuad = 0, 398 portmodPortModeTri012 = 1, 399 portmodPortModeTri023 = 2, 400 portmodPortModeDual = 3, 401 portmodPortModeSingle = 4, 402 portmodPortModeCount 403 } portmod_core_port_mode_t; 404 405 #ifdef PORTMOD_DIAG 406 extern enum_mapping_t portmod_core_port_mode_t_mapping[]; 407 #endif /*PORTMOD_DIAG*/ 408 409 /* portmod_core_port_mode_t validation */ 410 int portmod_core_port_mode_t_validate(int unit, portmod_core_port_mode_t portmod_core_port_mode); 411 412 /*! 413 * @enum portmod_port_mode_aux_info_e 414 * @brief auxiliary info for assigning port mode 415 */ 416 typedef enum portmod_port_mode_aux_info_e { 417 portmodModeInfoNone = 0, 418 portmodModeInfoThreePorts = 1, /**< there are three ports in a core */ 419 portmodModeInfoTwoDualModePorts = 2, /**< there are two ports in a core and each lane is in dual port mode */ 420 portmodModeInfoCount 421 } portmod_port_mode_aux_info_t; 422 423 #ifdef PORTMOD_DIAG 424 extern enum_mapping_t portmod_port_mode_aux_info_t_mapping[]; 425 #endif /*PORTMOD_DIAG*/ 426 427 /* portmod_port_mode_aux_info_t validation */ 428 int portmod_port_mode_aux_info_t_validate(int unit, portmod_port_mode_aux_info_t portmod_port_mode_aux_info); 429 430 /*! 431 * @enum portmod_prbs_mode_e 432 * @brief Psuedo Random Bit Stream (PRBS) modes 433 */ 434 typedef enum portmod_prbs_mode_e { 435 portmodPrbsModePhy = 0, 436 portmodPrbsModeMac = 1, 437 portmodPrbsModeCount 438 } portmod_prbs_mode_t; 439 440 #ifdef PORTMOD_DIAG 441 extern enum_mapping_t portmod_prbs_mode_t_mapping[]; 442 #endif /*PORTMOD_DIAG*/ 443 444 /* portmod_prbs_mode_t validation */ 445 int portmod_prbs_mode_t_validate(int unit, portmod_prbs_mode_t portmod_prbs_mode); 446 447 /*! 448 * @enum portmod_ext_to_int_phy_ctrlcode_e 449 * @brief Control Codes to Call Internal Phy PortMod functions from legacy External Phy 450 */ 451 typedef enum portmod_ext_to_int_phy_ctrlcode_e { 452 portmodExtToInt_CtrlCode_Init = 0, 453 portmodExtToInt_CtrlCode_Reset = 1, 454 portmodExtToInt_CtrlCode_Link = 2, 455 portmodExtToInt_CtrlCode_Enable = 3, 456 portmodExtToInt_CtrlCode_Duplex = 4, 457 portmodExtToInt_CtrlCode_Speed = 5, 458 portmodExtToInt_CtrlCode_Master = 6, 459 portmodExtToInt_CtrlCode_AN = 7, 460 portmodExtToInt_CtrlCode_AdvLocal = 8, 461 portmodExtToInt_CtrlCode_AdvRemote = 9, 462 portmodExtToInt_CtrlCode_LB = 10, 463 portmodExtToInt_CtrlCode_Interface = 11, 464 portmodExtToInt_CtrlCode_Ability = 12, 465 portmodExtToInt_CtrlCode_AbilityAdvert = 13, 466 portmodExtToInt_CtrlCode_AbilityRemote = 14, 467 portmodExtToInt_CtrlCode_AbilityLocal = 15, 468 portmodExtToInt_CtrlCode_LinkupEvt = 16, 469 portmodExtToInt_CtrlCode_LinkdnEvt = 17, 470 portmodExtToInt_CtrlCode_MDIX = 18, 471 portmodExtToInt_CtrlCode_MDIXStatus = 19, 472 portmodExtToInt_CtrlCode_MediumConfig = 20, 473 portmodExtToInt_CtrlCode_Medium = 21, 474 portmodExtToInt_CtrlCode_CableDiag = 22, 475 portmodExtToInt_CtrlCode_Control = 23, 476 portmodExtToInt_CtrlCode_Firmware = 24, 477 portmodExtToInt_CtrlCode_TimesyncConfig = 25, 478 portmodExtToInt_CtrlCode_TimesyncControl = 26, 479 portmodExtToInt_CtrlCode_TimesyncEnhancedCapture = 27, 480 portmodExtToInt_CtrlCode_DiagCtrl = 28, 481 portmodExtToInt_CtrlCode_LaneControl = 29, 482 portmodExtToInt_CtrlCode_OAMConfig = 30, 483 portmodExtToInt_CtrlCode_OAMControl = 31, 484 portmodExtToInt_CtrlCode_Multi = 32, 485 portmodExtToInt_CtrlCode_Probe = 33, 486 portmodExtToInt_CtrlCode_PreconditionBeforeProbe = 34, 487 portmodExtToInt_CtrlCode_LinkfaultGet = 35, 488 portmodExtToInt_CtrlCode_SpeedLine = 36, 489 portmodExtToInt_CtrlCode_Count 490 } portmod_ext_to_int_phy_ctrlcode_t; 491 492 #ifdef PORTMOD_DIAG 493 extern enum_mapping_t portmod_ext_to_int_phy_ctrlcode_t_mapping[]; 494 #endif /*PORTMOD_DIAG*/ 495 496 /* portmod_ext_to_int_phy_ctrlcode_t validation */ 497 int portmod_ext_to_int_phy_ctrlcode_t_validate(int unit, portmod_ext_to_int_phy_ctrlcode_t portmod_ext_to_int_phy_ctrlcode); 498 499 /*! 500 * @enum portmod_cpm_core_mode_e 501 * @brief cpm core modes 502 */ 503 typedef enum portmod_cpm_core_mode_e { 504 portmodCpmAllCpri = 0, 505 portmodCpmAllIEEE = 1, 506 portmodCpmAllHIGIG = 2, 507 portmodCpmMixEthCpri = 3, 508 portmodCpmCount 509 } portmod_cpm_core_mode_t; 510 511 #ifdef PORTMOD_DIAG 512 extern enum_mapping_t portmod_cpm_core_mode_t_mapping[]; 513 #endif /*PORTMOD_DIAG*/ 514 515 /* portmod_cpm_core_mode_t validation */ 516 int portmod_cpm_core_mode_t_validate(int unit, portmod_cpm_core_mode_t portmod_cpm_core_mode); 517 518 /*! 519 * @enum portmod_core_port_enet_cpri_type_e 520 * @brief Different ports cpri/ethernet 521 */ 522 typedef enum portmod_core_port_enet_cpri_type_e { 523 portmodCpmPrtEthMode = 0, 524 portmodCpmPrtEthOfMixedMode = 1, 525 portmodCpmPrtCpriMode = 2, 526 portmodCpmPrtCpriOfMixedMode = 3, 527 portmodCpmPrtRsvd4Mode = 4, 528 portmodCpmPrtRsvd4OfMixedMode = 5, 529 portmodCpmPrtCount 530 } portmod_core_port_enet_cpri_type_t; 531 532 #ifdef PORTMOD_DIAG 533 extern enum_mapping_t portmod_core_port_enet_cpri_type_t_mapping[]; 534 #endif /*PORTMOD_DIAG*/ 535 536 /* portmod_core_port_enet_cpri_type_t validation */ 537 int portmod_core_port_enet_cpri_type_t_validate(int unit, portmod_core_port_enet_cpri_type_t portmod_core_port_enet_cpri_type); 538 539 /*! 540 * @struct portmod_portphy_ability_s 541 * @brief portmod version of port's ability mapping. 542 */ 543 typedef struct portmod_portphy_ability_s { 544 portmod_port_mode_t cur_mode; 545 portmod_port_mode_t speed_half_duplex; 546 portmod_port_mode_t speed_full_duplex; 547 portmod_port_mode_t pause; 548 portmod_port_mode_t interface; 549 portmod_port_mode_t medium; 550 portmod_port_mode_t loopback; 551 portmod_port_mode_t flags; 552 portmod_port_mode_t eee; 553 portmod_port_mode_t fcmap; 554 portmod_pa_encap_t encap; 555 } portmod_portphy_ability_t; 556 557 /* portmod_portphy_ability_t initialization and validation */ 558 int portmod_portphy_ability_t_validate(int unit, const portmod_portphy_ability_t* portmod_portphy_ability); 559 int portmod_portphy_ability_t_init(int unit, portmod_portphy_ability_t* portmod_portphy_ability); 560 561 562 /*! 563 * @struct portmod_pdata_s 564 * @brief portmod version of port's pdata to transger data. 565 */ 566 typedef struct portmod_pdata_s { 567 uint32_t data; 568 uint32_t enable; 569 portmod_port_if_t pif; 570 portmod_port_ability_t* ability; 571 } portmod_pdata_t; 572 573 /* portmod_pdata_t initialization and validation */ 574 int portmod_pdata_t_validate(int unit, const portmod_pdata_t* portmod_pdata); 575 int portmod_pdata_t_init(int unit, portmod_pdata_t* portmod_pdata); 576 577 578 /*! 579 * @struct portmod_port_mode_info_s 580 * @brief port mode info. 581 */ 582 typedef struct portmod_port_mode_info_s { 583 portmod_core_port_mode_t cur_mode; 584 int lanes; 585 int port_index; 586 } portmod_port_mode_info_t; 587 588 /* portmod_port_mode_info_t initialization and validation */ 589 int portmod_port_mode_info_t_validate(int unit, const portmod_port_mode_info_t* portmod_port_mode_info); 590 int portmod_port_mode_info_t_init(int unit, portmod_port_mode_info_t* portmod_port_mode_info); 591 592 typedef _shr_port_phy_fec_t portmod_fec_t; 593 594 595 /*! 596 * @struct portmod_port_diag_info_s 597 * @brief This structure return port diagnostics information from the PMM 598 */ 599 typedef struct portmod_port_diag_info_s { 600 int original_port; /**< in case of alias this field will be the original port */ 601 soc_port_if_t interface; /**< interface type */ 602 int pm_id; /**< pm id which the port belongs */ 603 portmod_pbmp_t phys; /**< The PHYs that assemble the port */ 604 int sub_phy; /**< qsgmii only; Sub PHY index */ 605 int medium; /**< Fiber or Copper; */ 606 portmod_port_mode_info_t core_mode; /**< core port mode */ 607 phymod_polarity_t polarity; /**< phy polority */ 608 portmod_fec_t fec; /**< FEC type */ 609 } portmod_port_diag_info_t; 610 611 /* portmod_port_diag_info_t initialization and validation */ 612 int portmod_port_diag_info_t_validate(int unit, const portmod_port_diag_info_t* portmod_port_diag_info); 613 int portmod_port_diag_info_t_init(int unit, portmod_port_diag_info_t* portmod_port_diag_info); 614 615 616 /*! 617 * @struct portmod_pm_core_info_s 618 * @brief This structure return port diagnostics information from the PMM 619 */ 620 typedef struct portmod_pm_core_info_s { 621 phymod_ref_clk_t ref_clk; /**< reference clock */ 622 phymod_lane_map_t lane_map; /**< lane map */ 623 int nof_phys; /**< internal + external phys */ 624 } portmod_pm_core_info_t; 625 626 /* portmod_pm_core_info_t initialization and validation */ 627 int portmod_pm_core_info_t_validate(int unit, const portmod_pm_core_info_t* portmod_pm_core_info); 628 int portmod_pm_core_info_t_init(int unit, portmod_pm_core_info_t* portmod_pm_core_info); 629 630 631 /*! 632 * @struct portmod_pm_diag_info_s 633 * @brief PM diagnostics information 634 */ 635 typedef struct portmod_pm_diag_info_s { 636 portmod_dispatch_type_t type; /**< PM type */ 637 portmod_pm_core_info_t core_info; /**< PM core information */ 638 portmod_pbmp_t phys; /**< Which PHYs are connected to the PM */ 639 soc_pbmp_t ports; /**< Which ports are connected to the PM */ 640 uint16 serdes_id0; /**< Serdes ID */ 641 uint16 phy_id0; /**< Phy ID0 */ 642 uint16 phy_id1; /**< Phy ID1 */ 643 char name[PORTMOD_TSCE_LANE_NAME_LEN]; 644 } portmod_pm_diag_info_t; 645 646 /* portmod_pm_diag_info_t initialization and validation */ 647 int portmod_pm_diag_info_t_validate(int unit, const portmod_pm_diag_info_t* portmod_pm_diag_info); 648 int portmod_pm_diag_info_t_init(int unit, portmod_pm_diag_info_t* portmod_pm_diag_info); 649 650 651 /*! 652 * @struct portmod_port_ts_adjust_s 653 * @brief Store time stamp adjust from configuration for MAC 654 */ 655 typedef struct portmod_port_ts_adjust_s { 656 int speed; 657 uint32 osts_adjust; /**< MAC pipeline delay in OSTS */ 658 uint32 tsts_adjust; /**< Delay of TS timer from TS clk to TSC_Clk domain */ 659 } portmod_port_ts_adjust_t; 660 661 /* portmod_port_ts_adjust_t initialization and validation */ 662 int portmod_port_ts_adjust_t_validate(int unit, const portmod_port_ts_adjust_t* portmod_port_ts_adjust); 663 int portmod_port_ts_adjust_t_init(int unit, portmod_port_ts_adjust_t* portmod_port_ts_adjust); 664 665 typedef enum portmod_qtc_mode_e { 666 portmodQtcModeInvalid = 0, /**< Invalid mode. */ 667 portmodQtcModeEthernet = 1, /**< PM core in Ethernet mode. */ 668 portmodQtcModeQsgmii = 2, /**< PM core in QSGMII mode. */ 669 portmodQtcModeUsxgmii = 3, /**< PM core in USXGMII mode. */ 670 portmodQtcModeCount 671 } portmod_qtc_mode_t; 672 673 #ifdef PORTMOD_DIAG 674 extern enum_mapping_t portmod_qtc_mode_t_mapping[]; 675 #endif /*PORTMOD_DIAG*/ 676 677 /* portmod_qtc_mode_t validation */ 678 int portmod_qtc_mode_t_validate(int unit, portmod_qtc_mode_t portmod_qtc_mode); 679 680 /*! 681 * @struct portmod_port_init_config_s 682 * @brief port config information. 683 */ 684 typedef struct portmod_port_init_config_s { 685 phymod_phy_reset_t phy_reset_config; 686 phymod_pattern_t pattern; 687 int cx4_10g; 688 int pdetect1000x; 689 phymod_an_mode_type_t an_mode; /**< spn_PHY_AN_MODE - Specify the AN mode */ 690 int an_master_lane; /**< spn_PHY_AUTONEG_MASTER_LANE - Specify the AN master lane */ 691 int an_cl72; /**< spn_PHY_AN_C72 - Specify if the link training should be enabled */ 692 int fs_cl72; /**< spn_FORCED_INIT_CL72 - if trainig should be enabled in Forced speed mode */ 693 int an_fec; /**< spn_FORCED_INIT_FEC specify if FEC should be enabled in AN mode */ 694 int serdes_fec_enable; /**< spn_SERDES_FEC_ENABLE, 0 - no FEC(default), 1 - CL74, 2 - CL91 */ 695 int sgmii_mstr; 696 int serdes_driver_current; 697 int serdes_1000x_at_6250_vco; /**< run 1G at 6.25 VCO */ 698 int serdes_1000x_at_12500_vco; /**< run 1G at 12.5 VCO */ 699 int serdes_1000x_at_25g_vco; /**< run 1G at 25 VCO */ 700 int serdes_10g_at_25g_vco; /**< run 10GBase-R at 25 VCO */ 701 int pll_divider_req; /**< specify the PLL divider value to use for the speed */ 702 int rxaui_mode; 703 int port_fallback_lane; 704 int tx_params_user_flag[PHYMOD_MAX_LANES_PER_PORT]; 705 phymod_tx_t tx_params[PHYMOD_MAX_LANES_PER_PORT]; /**< tx params from config */ 706 int an_cl37; /**< AN CL37 */ 707 int cl37_sgmii_war; 708 int cl37_sgmii_cnt; 709 int cl37_sgmii_RESTART_CNT; /**< threshold for cl37_sgmii_cnt */ 710 int an_cl73; /**< AN_CL73 */ 711 int is_hg; /**< is higig port */ 712 int ext_phy_tx_params_user_flag[PHYMOD_MAX_LANES_PER_PORT]; 713 phymod_tx_t ext_phy_tx_params[PHYMOD_MAX_LANES_PER_PORT]; /**< external phy tx params from config */ 714 phymod_polarity_t polarity[PORTMOD_MAX_CORES_PER_PORT]; 715 uint8 polarity_overwrite; /**< Get polarity form config to overwrite PM's polarity when port probe */ 716 phymod_lane_map_t lane_map[PORTMOD_MAX_CORES_PER_PORT]; 717 uint8 lane_map_overwrite; /**< Get lane map form config to overwrite PM's lane map when port probe */ 718 phymod_firmware_load_method_t fw_load_method[PORTMOD_MAX_CORES_PER_PORT]; 719 uint8 fw_load_method_overwrite; /**< Get fw load method form config to overwrite PM's fw load method when port probe */ 720 phymod_ref_clk_t ref_clk; 721 uint8 ref_clk_overwrite; /**< Get ref clk form config to overwrite PM's ref clk when port probe */ 722 portmod_port_mode_aux_info_t port_mode_aux_info; /**< auxiliary info for assigning the core port mode */ 723 portmod_port_ts_adjust_t port_ts_adjust[PORTMOD_TS_ADJUST_NUM]; /**< Configure time stamp adjust for mac */ 724 uint32 txpi_mode; /**< PMD TXPI mode. 0 - disable, 1- Enable with external PD (Phase detector) */ 725 uint32 txpi_sdm_scheme; /**< TXPI SDM scheme type. 0 - 1st order scheme with floor, 1 - 1st order scheme with rounding, 2 - 2nd order scheme with rounding */ 726 int roe_stuffing_bit; /**< 1bit value for Stuffing bit */ 727 int roe_reserved_bit; /**< 1bit value for Reserved bit */ 728 portmod_cpm_core_mode_t cpm_core_mode; 729 portmod_qtc_mode_t qtc_mode; 730 int parity_enable; /**< parity enable */ 731 } portmod_port_init_config_t; 732 733 /* portmod_port_init_config_t initialization and validation */ 734 int portmod_port_init_config_t_validate(int unit, const portmod_port_init_config_t* portmod_port_init_config); 735 int portmod_port_init_config_t_init(int unit, portmod_port_init_config_t* portmod_port_init_config); 736 737 typedef _shr_port_encap_t portmod_encap_t; 738 739 740 /*! 741 * @struct portmod_port_interface_config_s 742 * @brief This structure contains the rate, settings as medium, scrambler en, etc. and flags which allow/forbid the change of PLL/TX parameters/FW configuration/etc. 743 */ 744 typedef struct portmod_port_interface_config_s { 745 soc_port_if_t interface; 746 soc_port_if_t line_interface; 747 soc_port_if_t serdes_interface; 748 uint32 interface_modes; /**< see PHYMOD_INTF_MODES_ */ 749 uint32 flags; /**< see PHYMOD_INTF_F_ */ 750 uint32 port_refclk_int; 751 int port_num_lanes; 752 int speed; /**< speed at which the port should be initialized */ 753 int max_speed; /**< Max Port Speed Supported */ 754 portmod_encap_t encap_mode; /**< Encap Mode */ 755 int pll_divider_req; 756 int port_op_mode; /**< mainly used by ext phy for repeater/retimer */ 757 uint32 serdes_scrambler_seed; /**< scramblar seed for CPRI and RSVD4 mode */ 758 uint32 serdes_scrambler_enable; /**< 1bit value for scramblar enable for CPRI and RSVD4 mode */ 759 } portmod_port_interface_config_t; 760 761 /* portmod_port_interface_config_t initialization and validation */ 762 int portmod_port_interface_config_t_validate(int unit, const portmod_port_interface_config_t* portmod_port_interface_config); 763 int portmod_port_interface_config_t_init(int unit, portmod_port_interface_config_t* portmod_port_interface_config); 764 765 /*! 766 * @brief Port Add Flags 767 */ 768 #define PORTMOD_PORT_ADD_F_INIT_PASS1 0x1 /**< phymod init PASS1:do some initializations before FW load.If broadcast is not supported, download FW unicast */ 769 #define PORTMOD_PORT_ADD_F_INIT_PASS2 0x2 /**< phymod init PASS2:do some initializations after FW load */ 770 #define PORTMOD_PORT_ADD_F_FIRMWARE_LOAD_VERIFY 0x4 /**< Verify FW loaded correctly */ 771 #define PORTMOD_PORT_ADD_F_RX_SRIP_CRC 0x8 /**< Set port RX to strip CRC mode */ 772 #define PORTMOD_PORT_ADD_F_TX_APPEND_CRC 0x10 /**< Set port TX to append CRC before sending the packet */ 773 #define PORTMOD_PORT_ADD_F_TX_REPLACE_CRC 0x20 /**< Set port TX to replace CRC before sending the packet */ 774 #define PORTMOD_PORT_ADD_F_TX_PASS_THROUGH_CRC 0x40 /**< Set port TX to pass through CRC */ 775 #define PORTMOD_PORT_ADD_F_EGR_1588_TIMESTAMP_MODE_48BIT 0x80 /**< Enable 48-bit time stamping */ 776 #define PORTMOD_PORT_ADD_F_INIT_CORE_PROBE 0x100 /**< Do Core Probe. This is stage 1 of 3 stage init. INIT_UNTIL, RESUME AFTER are other 2 stages. If no flag is set - all 3 will be performed. */ 777 #define PORTMOD_PORT_ADD_F_PORT_ATTACH_EXT_PHY_SKIP 0x200 /**< Skip external phy port attach */ 778 #define PORTMOD_PORT_ADD_F_ELK 0x400 /**< flag for ELK */ 779 #define PORTMOD_PORT_ADD_F_SYS_16B_INTF_MODE 0x800 /**< flag for CLMAC 16B Mode */ 780 #define PORTMOD_PORT_ADD_F_AUTONEG_CONFIG_SKIP 0x1000 /**< Skip autoneg configuration in port attach */ 781 #define PORTMOD_PORT_ADD_F_FIRMWARE_DOWNLOAD_BCAST 0x2000 /**< FW download broadcast */ 782 #define PORTMOD_PORT_ADD_F_SKIP_SPEED_INIT 0x4000 /**< Flag used by DNX to skip speed set duirng init */ 783 #define PORTMOD_PORT_ADD_F_IS_ENHANCED_PM4X25_GEN2 0x8000 /**< enhanced pm 4x25 gen2 */ 784 #define PORTMOD_PORT_ADD_F_DEFAULT_OSR2P5 0x10000 /**< Set OSR2P5 by default */ 785 #define PORTMOD_PORT_ADD_F_PCS_BYPASSED 0x20000 /**< Bypass the PCS logic in PM */ 786 #define PORTMOD_PORT_ADD_F_BYPASS_FW_CRC_CHECK 0x40000 /**< Bypass the FW CRC check */ 787 788 #define PORTMOD_PORT_ADD_F_INIT_PASS1_SET(info) ((info)->flags |= PORTMOD_PORT_ADD_F_INIT_PASS1) 789 #define PORTMOD_PORT_ADD_F_INIT_PASS2_SET(info) ((info)->flags |= PORTMOD_PORT_ADD_F_INIT_PASS2) 790 #define PORTMOD_PORT_ADD_F_FIRMWARE_LOAD_VERIFY_SET(info) ((info)->flags |= PORTMOD_PORT_ADD_F_FIRMWARE_LOAD_VERIFY) 791 #define PORTMOD_PORT_ADD_F_RX_SRIP_CRC_SET(info) ((info)->flags |= PORTMOD_PORT_ADD_F_RX_SRIP_CRC) 792 #define PORTMOD_PORT_ADD_F_TX_APPEND_CRC_SET(info) ((info)->flags |= PORTMOD_PORT_ADD_F_TX_APPEND_CRC) 793 #define PORTMOD_PORT_ADD_F_TX_REPLACE_CRC_SET(info) ((info)->flags |= PORTMOD_PORT_ADD_F_TX_REPLACE_CRC) 794 #define PORTMOD_PORT_ADD_F_TX_PASS_THROUGH_CRC_SET(info) ((info)->flags |= PORTMOD_PORT_ADD_F_TX_PASS_THROUGH_CRC) 795 #define PORTMOD_PORT_ADD_F_EGR_1588_TIMESTAMP_MODE_48BIT_SET(info) ((info)->flags |= PORTMOD_PORT_ADD_F_EGR_1588_TIMESTAMP_MODE_48BIT) 796 #define PORTMOD_PORT_ADD_F_INIT_CORE_PROBE_SET(info) ((info)->flags |= PORTMOD_PORT_ADD_F_INIT_CORE_PROBE) 797 #define PORTMOD_PORT_ADD_F_PORT_ATTACH_EXT_PHY_SKIP_SET(info) ((info)->flags |= PORTMOD_PORT_ADD_F_PORT_ATTACH_EXT_PHY_SKIP) 798 #define PORTMOD_PORT_ADD_F_ELK_SET(info) ((info)->flags |= PORTMOD_PORT_ADD_F_ELK) 799 #define PORTMOD_PORT_ADD_F_SYS_16B_INTF_MODE_SET(info) ((info)->flags |= PORTMOD_PORT_ADD_F_SYS_16B_INTF_MODE) 800 #define PORTMOD_PORT_ADD_F_AUTONEG_CONFIG_SKIP_SET(info) ((info)->flags |= PORTMOD_PORT_ADD_F_AUTONEG_CONFIG_SKIP) 801 #define PORTMOD_PORT_ADD_F_FIRMWARE_DOWNLOAD_BCAST_SET(info) ((info)->flags |= PORTMOD_PORT_ADD_F_FIRMWARE_DOWNLOAD_BCAST) 802 #define PORTMOD_PORT_ADD_F_SKIP_SPEED_INIT_SET(info) ((info)->flags |= PORTMOD_PORT_ADD_F_SKIP_SPEED_INIT) 803 #define PORTMOD_PORT_ADD_F_IS_ENHANCED_PM4X25_GEN2_SET(info) ((info)->flags |= PORTMOD_PORT_ADD_F_IS_ENHANCED_PM4X25_GEN2) 804 #define PORTMOD_PORT_ADD_F_DEFAULT_OSR2P5_SET(info) ((info)->flags |= PORTMOD_PORT_ADD_F_DEFAULT_OSR2P5) 805 #define PORTMOD_PORT_ADD_F_PCS_BYPASSED_SET(info) ((info)->flags |= PORTMOD_PORT_ADD_F_PCS_BYPASSED) 806 #define PORTMOD_PORT_ADD_F_BYPASS_FW_CRC_CHECK_SET(info) ((info)->flags |= PORTMOD_PORT_ADD_F_BYPASS_FW_CRC_CHECK) 807 808 #define PORTMOD_PORT_ADD_F_INIT_PASS1_CLR(info) ((info)->flags &= ~PORTMOD_PORT_ADD_F_INIT_PASS1) 809 #define PORTMOD_PORT_ADD_F_INIT_PASS2_CLR(info) ((info)->flags &= ~PORTMOD_PORT_ADD_F_INIT_PASS2) 810 #define PORTMOD_PORT_ADD_F_FIRMWARE_LOAD_VERIFY_CLR(info) ((info)->flags &= ~PORTMOD_PORT_ADD_F_FIRMWARE_LOAD_VERIFY) 811 #define PORTMOD_PORT_ADD_F_RX_SRIP_CRC_CLR(info) ((info)->flags &= ~PORTMOD_PORT_ADD_F_RX_SRIP_CRC) 812 #define PORTMOD_PORT_ADD_F_TX_APPEND_CRC_CLR(info) ((info)->flags &= ~PORTMOD_PORT_ADD_F_TX_APPEND_CRC) 813 #define PORTMOD_PORT_ADD_F_TX_REPLACE_CRC_CLR(info) ((info)->flags &= ~PORTMOD_PORT_ADD_F_TX_REPLACE_CRC) 814 #define PORTMOD_PORT_ADD_F_TX_PASS_THROUGH_CRC_CLR(info) ((info)->flags &= ~PORTMOD_PORT_ADD_F_TX_PASS_THROUGH_CRC) 815 #define PORTMOD_PORT_ADD_F_EGR_1588_TIMESTAMP_MODE_48BIT_CLR(info) ((info)->flags &= ~PORTMOD_PORT_ADD_F_EGR_1588_TIMESTAMP_MODE_48BIT) 816 #define PORTMOD_PORT_ADD_F_INIT_CORE_PROBE_CLR(info) ((info)->flags &= ~PORTMOD_PORT_ADD_F_INIT_CORE_PROBE) 817 #define PORTMOD_PORT_ADD_F_PORT_ATTACH_EXT_PHY_SKIP_CLR(info) ((info)->flags &= ~PORTMOD_PORT_ADD_F_PORT_ATTACH_EXT_PHY_SKIP) 818 #define PORTMOD_PORT_ADD_F_ELK_CLR(info) ((info)->flags &= ~PORTMOD_PORT_ADD_F_ELK) 819 #define PORTMOD_PORT_ADD_F_SYS_16B_INTF_MODE_CLR(info) ((info)->flags &= ~PORTMOD_PORT_ADD_F_SYS_16B_INTF_MODE) 820 #define PORTMOD_PORT_ADD_F_AUTONEG_CONFIG_SKIP_CLR(info) ((info)->flags &= ~PORTMOD_PORT_ADD_F_AUTONEG_CONFIG_SKIP) 821 #define PORTMOD_PORT_ADD_F_FIRMWARE_DOWNLOAD_BCAST_CLR(info) ((info)->flags &= ~PORTMOD_PORT_ADD_F_FIRMWARE_DOWNLOAD_BCAST) 822 #define PORTMOD_PORT_ADD_F_SKIP_SPEED_INIT_CLR(info) ((info)->flags &= ~PORTMOD_PORT_ADD_F_SKIP_SPEED_INIT) 823 #define PORTMOD_PORT_ADD_F_IS_ENHANCED_PM4X25_GEN2_CLR(info) ((info)->flags &= ~PORTMOD_PORT_ADD_F_IS_ENHANCED_PM4X25_GEN2) 824 #define PORTMOD_PORT_ADD_F_DEFAULT_OSR2P5_CLR(info) ((info)->flags &= ~PORTMOD_PORT_ADD_F_DEFAULT_OSR2P5) 825 #define PORTMOD_PORT_ADD_F_PCS_BYPASSED_CLR(info) ((info)->flags &= ~PORTMOD_PORT_ADD_F_PCS_BYPASSED) 826 #define PORTMOD_PORT_ADD_F_BYPASS_FW_CRC_CHECK_CLR(info) ((info)->flags &= ~PORTMOD_PORT_ADD_F_BYPASS_FW_CRC_CHECK) 827 828 #define PORTMOD_PORT_ADD_F_INIT_PASS1_GET(info) ((info)->flags & PORTMOD_PORT_ADD_F_INIT_PASS1 ? 1 : 0) 829 #define PORTMOD_PORT_ADD_F_INIT_PASS2_GET(info) ((info)->flags & PORTMOD_PORT_ADD_F_INIT_PASS2 ? 1 : 0) 830 #define PORTMOD_PORT_ADD_F_FIRMWARE_LOAD_VERIFY_GET(info) ((info)->flags & PORTMOD_PORT_ADD_F_FIRMWARE_LOAD_VERIFY ? 1 : 0) 831 #define PORTMOD_PORT_ADD_F_RX_SRIP_CRC_GET(info) ((info)->flags & PORTMOD_PORT_ADD_F_RX_SRIP_CRC ? 1 : 0) 832 #define PORTMOD_PORT_ADD_F_TX_APPEND_CRC_GET(info) ((info)->flags & PORTMOD_PORT_ADD_F_TX_APPEND_CRC ? 1 : 0) 833 #define PORTMOD_PORT_ADD_F_TX_REPLACE_CRC_GET(info) ((info)->flags & PORTMOD_PORT_ADD_F_TX_REPLACE_CRC ? 1 : 0) 834 #define PORTMOD_PORT_ADD_F_TX_PASS_THROUGH_CRC_GET(info) ((info)->flags & PORTMOD_PORT_ADD_F_TX_PASS_THROUGH_CRC ? 1 : 0) 835 #define PORTMOD_PORT_ADD_F_EGR_1588_TIMESTAMP_MODE_48BIT_GET(info) ((info)->flags & PORTMOD_PORT_ADD_F_EGR_1588_TIMESTAMP_MODE_48BIT ? 1 : 0) 836 #define PORTMOD_PORT_ADD_F_INIT_CORE_PROBE_GET(info) ((info)->flags & PORTMOD_PORT_ADD_F_INIT_CORE_PROBE ? 1 : 0) 837 #define PORTMOD_PORT_ADD_F_PORT_ATTACH_EXT_PHY_SKIP_GET(info) ((info)->flags & PORTMOD_PORT_ADD_F_PORT_ATTACH_EXT_PHY_SKIP ? 1 : 0) 838 #define PORTMOD_PORT_ADD_F_ELK_GET(info) ((info)->flags & PORTMOD_PORT_ADD_F_ELK ? 1 : 0) 839 #define PORTMOD_PORT_ADD_F_SYS_16B_INTF_MODE_GET(info) ((info)->flags & PORTMOD_PORT_ADD_F_SYS_16B_INTF_MODE ? 1 : 0) 840 #define PORTMOD_PORT_ADD_F_AUTONEG_CONFIG_SKIP_GET(info) ((info)->flags & PORTMOD_PORT_ADD_F_AUTONEG_CONFIG_SKIP ? 1 : 0) 841 #define PORTMOD_PORT_ADD_F_FIRMWARE_DOWNLOAD_BCAST_GET(info) ((info)->flags & PORTMOD_PORT_ADD_F_FIRMWARE_DOWNLOAD_BCAST ? 1 : 0) 842 #define PORTMOD_PORT_ADD_F_SKIP_SPEED_INIT_GET(info) ((info)->flags & PORTMOD_PORT_ADD_F_SKIP_SPEED_INIT ? 1 : 0) 843 #define PORTMOD_PORT_ADD_F_IS_ENHANCED_PM4X25_GEN2_GET(info) ((info)->flags & PORTMOD_PORT_ADD_F_IS_ENHANCED_PM4X25_GEN2 ? 1 : 0) 844 #define PORTMOD_PORT_ADD_F_DEFAULT_OSR2P5_GET(info) ((info)->flags & PORTMOD_PORT_ADD_F_DEFAULT_OSR2P5 ? 1 : 0) 845 #define PORTMOD_PORT_ADD_F_PCS_BYPASSED_GET(info) ((info)->flags & PORTMOD_PORT_ADD_F_PCS_BYPASSED ? 1 : 0) 846 #define PORTMOD_PORT_ADD_F_BYPASS_FW_CRC_CHECK_GET(info) ((info)->flags & PORTMOD_PORT_ADD_F_BYPASS_FW_CRC_CHECK ? 1 : 0) 847 848 /*! 849 * @brief flag defines for the core init 850 */ 851 #define PORTMOD_CORE_INIT_FLAG_INITIALZIED 0x1 852 #define PORTMOD_CORE_INIT_FLAG_FIRMWARE_LOADED 0x2 /**< enable/disable the MAC(RX/TX according to the flags) */ 853 #define PORTMOD_CORE_INIT_FLAG_CPRI_CORE_INITIALZIED 0x4 /**< CPRI core is initialized */ 854 855 #define PORTMOD_CORE_INIT_FLAG_INITIALZIED_SET(flag) ((flag) |= PORTMOD_CORE_INIT_FLAG_INITIALZIED) 856 #define PORTMOD_CORE_INIT_FLAG_FIRMWARE_LOADED_SET(flag) ((flag) |= PORTMOD_CORE_INIT_FLAG_FIRMWARE_LOADED) 857 #define PORTMOD_CORE_INIT_FLAG_CPRI_CORE_INITIALZIED_SET(flag) ((flag) |= PORTMOD_CORE_INIT_FLAG_CPRI_CORE_INITIALZIED) 858 859 #define PORTMOD_CORE_INIT_FLAG_INITIALZIED_CLR(flag) ((flag) &= ~PORTMOD_CORE_INIT_FLAG_INITIALZIED) 860 #define PORTMOD_CORE_INIT_FLAG_FIRMWARE_LOADED_CLR(flag) ((flag) &= ~PORTMOD_CORE_INIT_FLAG_FIRMWARE_LOADED) 861 #define PORTMOD_CORE_INIT_FLAG_CPRI_CORE_INITIALZIED_CLR(flag) ((flag) &= ~PORTMOD_CORE_INIT_FLAG_CPRI_CORE_INITIALZIED) 862 863 #define PORTMOD_CORE_INIT_FLAG_INITIALZIED_GET(flag) ((flag) & PORTMOD_CORE_INIT_FLAG_INITIALZIED ? 1 : 0) 864 #define PORTMOD_CORE_INIT_FLAG_FIRMWARE_LOADED_GET(flag) ((flag) & PORTMOD_CORE_INIT_FLAG_FIRMWARE_LOADED ? 1 : 0) 865 #define PORTMOD_CORE_INIT_FLAG_CPRI_CORE_INITIALZIED_GET(flag) ((flag) & PORTMOD_CORE_INIT_FLAG_CPRI_CORE_INITIALZIED ? 1 : 0) 866 867 #define PORTMOD_PORT_PHY_FEC_INVALID _SHR_PORT_PHY_FEC_INVALID 868 #define PORTMOD_PORT_PHY_FEC_NONE _SHR_PORT_PHY_FEC_NONE /**< no FEC */ 869 #define PORTMOD_PORT_PHY_FEC_BASE_R _SHR_PORT_PHY_FEC_BASE_R /**< CL74/Base-R. 64/66b KR FEC for fabric */ 870 #define PORTMOD_PORT_PHY_FEC_RS_FEC _SHR_PORT_PHY_FEC_RS_FEC /**< CL91/RS-FEC */ 871 #define PORTMOD_PORT_PHY_FEC_RS_544 _SHR_PORT_PHY_FEC_RS_544 /**< Rs544, using 1xN RS FEC architecture */ 872 #define PORTMOD_PORT_PHY_FEC_RS_272 _SHR_PORT_PHY_FEC_RS_272 /**< Rs272, using 1xN RS FEC architecture */ 873 #define PORTMOD_PORT_PHY_FEC_RS_206 _SHR_PORT_PHY_FEC_RS_206 /**< Rs206. 64/66b 5T RS FEC for fabric */ 874 #define PORTMOD_PORT_PHY_FEC_RS_108 _SHR_PORT_PHY_FEC_RS_108 /**< Rs108. 64/66b 5T low latency RS FEC for fabric */ 875 #define PORTMOD_PORT_PHY_FEC_RS_545 _SHR_PORT_PHY_FEC_RS_545 /**< Rs545. 64/66b 15T RS FEC for fabric */ 876 #define PORTMOD_PORT_PHY_FEC_RS_304 _SHR_PORT_PHY_FEC_RS_304 /**< Rs304. 64/66b 15T low latency RS FEC for fabric */ 877 #define PORTMOD_PORT_PHY_FEC_RS_544_2XN _SHR_PORT_PHY_FEC_RS_544_2XN /**< Rs544, using 2xN RS FEC architecture */ 878 #define PORTMOD_PORT_PHY_FEC_RS_272_2XN _SHR_PORT_PHY_FEC_RS_272_2XN /**< Rs272, using 2xN RS FEC architecture */ 879 #define PORTMOD_PORT_PHY_FEC_FEC_COUNT _SHR_PORT_PHY_FEC_COUNT /**< Fec type count */ 880 881 #define PORTMOD_PORT_PHY_MEDIUM_COPPER _SHR_PORT_MEDIUM_COPPER 882 #define PORTMOD_PORT_PHY_MEDIUM_BACKPLANE _SHR_PORT_MEDIUM_BACKPLANE 883 #define PORTMOD_PORT_PHY_MEDIUM_ALL _SHR_PORT_MEDIUM_ALL 884 885 typedef _shr_port_medium_t portmod_port_medium_t; 886 887 #define PORTMOD_PORT_PHY_PAUSE_NONE _SHR_PORT_PHY_PAUSE_NONE 888 #define PORTMOD_PORT_PHY_PAUSE_TX _SHR_PORT_PHY_PAUSE_TX 889 #define PORTMOD_PORT_PHY_PAUSE_RX _SHR_PORT_PHY_PAUSE_RX 890 #define PORTMOD_PORT_PHY_PAUSE_SYMM _SHR_PORT_PHY_PAUSE_SYMM 891 #define PORTMOD_PORT_PHY_PAUSE_ALL _SHR_PORT_PHY_PAUSE_ALL 892 893 typedef _shr_port_phy_pause_t portmod_port_phy_pause_t; 894 895 #define PORTMOD_PORT_PHY_CHANNEL_SHORT _SHR_PORT_PHY_CHANNEL_SHORT 896 #define PORTMOD_PORT_PHY_CHANNEL_LONG _SHR_PORT_PHY_CHANNEL_LONG 897 #define PORTMOD_PORT_PHY_CHANNEL_ALL _SHR_PORT_PHY_CHANNEL_ALL 898 899 typedef _shr_port_phy_channel_t portmod_port_phy_channel_t; 900 901 #define PORTMOD_PORT_PHY_CONTROL_AUTONEG_MODE_CL73 _SHR_PORT_PHY_CONTROL_AUTONEG_MODE_CL73 902 #define PORTMOD_PORT_PHY_CONTROL_AUTONEG_MODE_CL73_BAM _SHR_PORT_PHY_CONTROL_AUTONEG_MODE_CL73_BAM 903 #define PORTMOD_PORT_PHY_CONTROL_AUTONEG_MODE_CL73_MSA _SHR_PORT_PHY_CONTROL_AUTONEG_MODE_CL73_MSA 904 #define PORTMOD_PORT_PHY_CONTROL_AUTONEG_MODE_NONE _SHR_PORT_PHY_CONTROL_AUTONEG_MODE_NONE 905 906 typedef _shr_port_phy_control_autoneg_mode_t portmod_port_phy_control_autoneg_mode_t; 907 908 909 /*! 910 * @struct portmod_port_speed_ability_s 911 * @brief This is the PORTMOD version of bcm_port_speed_ability_t 912 */ 913 typedef struct portmod_port_speed_ability_s { 914 uint32 speed; /**< port speed in Mbps */ 915 uint32 num_lanes; /**< number of lanes */ 916 portmod_fec_t fec_type; /**< FEC type */ 917 portmod_port_medium_t medium; /**< medium */ 918 portmod_port_phy_pause_t pause; /**< pause ability */ 919 portmod_port_phy_channel_t channel; /**< channel type */ 920 portmod_port_phy_control_autoneg_mode_t an_mode; /**< autoneg mode such as cl73, bam or msa */ 921 } portmod_port_speed_ability_t; 922 923 /* portmod_port_speed_ability_t initialization and validation */ 924 int portmod_port_speed_ability_t_validate(int unit, const portmod_port_speed_ability_t* portmod_port_speed_ability); 925 int portmod_port_speed_ability_t_init(int unit, portmod_port_speed_ability_t* portmod_port_speed_ability); 926 927 /*! 928 * portmod_port_speed_ability_local_get 929 * 930 * 931 * @param [in] unit - unit id 932 * @param [in] port - logical port 933 * @param [in] max_num_abilities - 934 * @param [out] abilities - 935 * @param [out] num_abilities - 936 */ 937 int portmod_port_speed_ability_local_get(int unit, int port, int max_num_abilities, portmod_port_speed_ability_t* abilities, int* num_abilities); 938 939 /*! 940 * @brief Speed Config Flags 941 */ 942 #define PORTMOD_SPEED_CONFIG_F_SKIP_FEC_CONFIGURATION 0x1 /**< don't set FEC configuration */ 943 944 #define PORTMOD_SPEED_CONFIG_F_SKIP_FEC_CONFIGURATION_SET(speed_config) ((speed_config)->flags |= PORTMOD_SPEED_CONFIG_F_SKIP_FEC_CONFIGURATION) 945 946 #define PORTMOD_SPEED_CONFIG_F_SKIP_FEC_CONFIGURATION_CLR(speed_config) ((speed_config)->flags &= ~PORTMOD_SPEED_CONFIG_F_SKIP_FEC_CONFIGURATION) 947 948 #define PORTMOD_SPEED_CONFIG_F_SKIP_FEC_CONFIGURATION_GET(speed_config) ((speed_config)->flags & PORTMOD_SPEED_CONFIG_F_SKIP_FEC_CONFIGURATION ? 1 : 0) 949 950 typedef struct portmod_speed_config_s { 951 int speed; /**< Port speed */ 952 int num_lane; /**< Number of lanes of the port */ 953 portmod_fec_t fec; /**< Fec type */ 954 int link_training; /**< Link training */ 955 int lane_config; /**< PMD lane configuration */ 956 uint32 flags; /**< Flags */ 957 } portmod_speed_config_t; 958 959 /* portmod_speed_config_t initialization and validation */ 960 int portmod_speed_config_t_validate(int unit, const portmod_speed_config_t* portmod_speed_config); 961 int portmod_speed_config_t_init(int unit, portmod_speed_config_t* portmod_speed_config); 962 963 964 /*! 965 * @enum portmod_vco_type_e 966 * @brief List of available VCOs for PM 967 */ 968 typedef enum portmod_vco_type_e { 969 portmodVCOInvalid = 0, 970 portmodVCO20G = 1, 971 portmodVCO21G = 2, 972 portmodVCO25G = 3, 973 portmodVCO26G = 4, 974 portmodVCO27G = 5, 975 portmodVCO20P625G = 6, 976 portmodVCO20P937G = 7, 977 portmodVCO22P5G = 8, 978 portmodVCO23G = 9, 979 portmodVCO25P781G = 11, 980 portmodVCO26P562G = 12, 981 portmodVCO6P25G = 13, 982 portmodVCO6P5625G = 14, 983 portmodVCO8P125G = 15, 984 portmodVCO9P735G = 16, 985 portmodVCO10G = 17, 986 portmodVCO10P3125G = 18, 987 portmodVCO10P9375G = 19, 988 portmodVCO12P5G = 20, 989 portmodVCO27P343G = 21, 990 portmodVCO28P125G = 22, 991 portmodVCOCount 992 } portmod_vco_type_t; 993 994 #ifdef PORTMOD_DIAG 995 extern enum_mapping_t portmod_vco_type_t_mapping[]; 996 #endif /*PORTMOD_DIAG*/ 997 998 /* portmod_vco_type_t validation */ 999 int portmod_vco_type_t_validate(int unit, portmod_vco_type_t portmod_vco_type); 1000 /*! 1001 * portmod_ilkn_core_lane_map_callback_get_f 1002 * 1003 * @brief Callback function to get the ILKN core lane map info 1004 * 1005 * @param [in] unit - unit id 1006 * @param [in] port - logical port 1007 * @param [in] nof_lanes - Max lanes for this ILKN core 1008 * @param [out] rx_lane_map - Rx logical to physical mapping info 1009 * @param [out] tx_lane_map - Tx logcial to physical mapping info 1010 */ 1011 typedef int (*portmod_ilkn_core_lane_map_callback_get_f)(int unit, int port, int nof_lanes, int* rx_lane_map, int* tx_lane_map); 1012 1013 /*! 1014 * portmod_ilkn_pm_lane_map_callback_get_f 1015 * 1016 * @brief Callback function to get the ILKN PM lane map info 1017 * 1018 * @param [in] unit - unit id 1019 * @param [in] port - logical port 1020 * @param [in] nof_lanes - Number of lanes for this ILKN PM 1021 * @param [in] first_phy - lower phy in the pm 1022 * @param [out] lane_map - physical mapping info 1023 */ 1024 typedef int (*portmod_ilkn_pm_lane_map_callback_get_f)(int unit, int port, int nof_lanes, int first_phy, phymod_lane_map_t* lane_map); 1025 1026 1027 /*! 1028 * @struct portmod_pm_identifier_s 1029 * @brief This struct defines specific PM 1030 */ 1031 typedef struct portmod_pm_identifier_s { 1032 portmod_dispatch_type_t type; /**< PM type */ 1033 int phy; /**< First PHY of the PM */ 1034 } portmod_pm_identifier_t; 1035 1036 /* portmod_pm_identifier_t initialization and validation */ 1037 int portmod_pm_identifier_t_validate(int unit, const portmod_pm_identifier_t* portmod_pm_identifier); 1038 int portmod_pm_identifier_t_init(int unit, portmod_pm_identifier_t* portmod_pm_identifier); 1039 1040 typedef struct portmod_port_add_info_s { 1041 portmod_port_interface_config_t interface_config; 1042 portmod_port_init_config_t init_config; 1043 portmod_speed_config_t speed_config; /**< used for TSCBH */ 1044 portmod_vco_type_t tvco; 1045 portmod_vco_type_t ovco; 1046 portmod_pbmp_t phys; 1047 portmod_pbmp_t phy_ports; /**< phys with qsgmii offsets. to be removed */ 1048 int sub_phy; /**< qsgmii only; Sub PHY index */ 1049 uint8 autoneg_en; 1050 uint8 link_training_en; 1051 uint32 flags; /**< port add flags */ 1052 uint32 is_fabric_o_nif; /**< dnx fabric over nif. fabric port is over nif serdes */ 1053 uint32 ilkn_core_id; /**< ilkn only. core id (0-1) */ 1054 uint32 ilkn_port_is_over_fabric; /**< ilkn only. port is over fabric serdes or nif */ 1055 int ilkn_burst_max; /**< ilkn only. burst_max value. */ 1056 int ilkn_burst_min; /**< ilkn only. burst_min value. */ 1057 int ilkn_burst_short; /**< ilkn only. burst_short value. */ 1058 int ilkn_nof_segments; /**< ilkn only. nof_segmnets value. */ 1059 int ilkn_metaframe_period; /**< ilkn only. metaframe sync period value. */ 1060 uint32 rx_retransmit; /**< rx retransmit enable */ 1061 uint32 tx_retransmit; /**< tx retransmit enable */ 1062 phymod_operation_mode_t phy_op_mode; /**< ext phy operation mode. */ 1063 phymod_datapath_t phy_op_datapath; /**< ext phy data path mode (e.g. ULL ultra low latency. */ 1064 int ilkn_inb_cal_len_rx; /**< calendar length for ILKN INB */ 1065 int ilkn_inb_cal_len_tx; /**< calendar length for ILKN INB */ 1066 int ilkn_oob_cal_len_rx; /**< calendar length for ILKN OOB */ 1067 int ilkn_oob_cal_len_tx; /**< calendar length for ILKN OOB */ 1068 uint32 reserved_channel_rx; /**< reserved channel id for rx retransmit */ 1069 uint32 reserved_channel_tx; /**< reserved channel id for tx retransmit */ 1070 portmod_pbmp_t ilkn_lanes; 1071 int nof_aggregated_pms; /**< Number of PMs controlled by this ILKN PM */ 1072 portmod_pm_identifier_t controlled_pms[PORTMOD_MAX_ILKN_AGGREGATED_PMS]; /**< Array of PMs controlled by this ILKN PM */ 1073 } portmod_port_add_info_t; 1074 1075 /* portmod_port_add_info_t initialization and validation */ 1076 int portmod_port_add_info_t_validate(int unit, const portmod_port_add_info_t* portmod_port_add_info); 1077 int portmod_port_add_info_t_init(int unit, portmod_port_add_info_t* portmod_port_add_info); 1078 1079 1080 /*! 1081 * @struct portmod_dnx_fabric_create_info_s 1082 * @brief Dune Fabric PM specific information required for PM add API. 1083 */ 1084 typedef struct portmod_dnx_fabric_create_info_s { 1085 phymod_ref_clk_t ref_clk; /**< SerDes quad ref clock */ 1086 phymod_ref_clk_t com_clk; /**< SerDes quad common clock */ 1087 phymod_access_t access; /**< phymod access structure; defines the register access for the SerDes Core */ 1088 phymod_lane_map_t lane_map; 1089 phymod_firmware_load_method_t fw_load_method; 1090 phymod_firmware_loader_f external_fw_loader; /**< firmware loader that will be used in case that fw_load_method=phymodFirmwareLoadMethodExternal */ 1091 phymod_polarity_t polarity; /**< Lanes Polarity */ 1092 int fmac_schan_id; /**< FMAC schan id */ 1093 int fsrd_schan_id; /**< FSRD schan id */ 1094 int fsrd_internal_quad; /**< Core instance in FSRD */ 1095 int first_phy_offset; /**< offset for phy index get */ 1096 int core_index; /**< core index */ 1097 int is_over_nif; /**< is fabric pm over nif */ 1098 portmod_pm_identifier_t fabric_o_nif_pm; /**< PM used for fabric over nif */ 1099 } portmod_dnx_fabric_create_info_t; 1100 1101 /* portmod_dnx_fabric_create_info_t initialization and validation */ 1102 int portmod_dnx_fabric_create_info_t_validate(int unit, const portmod_dnx_fabric_create_info_t* portmod_dnx_fabric_create_info); 1103 int portmod_dnx_fabric_create_info_t_init(int unit, portmod_dnx_fabric_create_info_t* portmod_dnx_fabric_create_info); 1104 1105 #define PORTMOD_NOF_FMACS_PER_PM8X50_FABRIC (2) 1106 1107 #define PORTMOD_NOF_WORDS_PER_PM8X50_FABRIC_LANES_BITMAP (1) 1108 1109 1110 /*! 1111 * @struct portmod_pm8x50_fabric_create_info_s 1112 * @brief Dune Fabric PM specific information required for PM add API. 1113 */ 1114 typedef struct portmod_pm8x50_fabric_create_info_s { 1115 phymod_ref_clk_t ref_clk; /**< SerDes quad ref clock */ 1116 phymod_access_t access; /**< phymod access structure; defines the register access for the SerDes Core */ 1117 phymod_firmware_load_method_t fw_load_method; 1118 phymod_firmware_loader_f external_fw_loader; /**< firmware loader that will be used in case that fw_load_method=phymodFirmwareLoadMethodExternal */ 1119 phymod_polarity_t polarity; /**< Lanes Polarity */ 1120 int fmac_schan_id[PORTMOD_NOF_FMACS_PER_PM8X50_FABRIC]; /**< FMACs schan ids */ 1121 int fsrd_schan_id; /**< FSRD schan id */ 1122 int first_phy_offset; /**< offset for phy index get */ 1123 int core_index; /**< core index */ 1124 uint32 force_single_pll; /**< only one PLL can be used in this core */ 1125 uint32 bypass_lanes_bitmap[PORTMOD_NOF_WORDS_PER_PM8X50_FABRIC_LANES_BITMAP]; /**< bitmap containing the bypass lanes of the pm */ 1126 int is_rx_ctrl_bypass_supported; /**< Is rx control bypass supported */ 1127 } portmod_pm8x50_fabric_create_info_t; 1128 1129 /* portmod_pm8x50_fabric_create_info_t initialization and validation */ 1130 int portmod_pm8x50_fabric_create_info_t_validate(int unit, const portmod_pm8x50_fabric_create_info_t* portmod_pm8x50_fabric_create_info); 1131 int portmod_pm8x50_fabric_create_info_t_init(int unit, portmod_pm8x50_fabric_create_info_t* portmod_pm8x50_fabric_create_info); 1132 1133 1134 /*! 1135 * @enum portmod_call_back_action_type_e 1136 * @brief Psuedo Random Bit Stream (PRBS) modes 1137 */ 1138 typedef enum portmod_call_back_action_type_e { 1139 portmodCallBackActionTypePre = 0, 1140 portmodCallBackActionTypeDuring = 1, 1141 portmodCallBackActionTypePost = 2, 1142 portmodCallBackActionTypeCount 1143 } portmod_call_back_action_type_t; 1144 1145 #ifdef PORTMOD_DIAG 1146 extern enum_mapping_t portmod_call_back_action_type_t_mapping[]; 1147 #endif /*PORTMOD_DIAG*/ 1148 1149 /* portmod_call_back_action_type_t validation */ 1150 int portmod_call_back_action_type_t_validate(int unit, portmod_call_back_action_type_t portmod_call_back_action_type); 1151 1152 /*! 1153 * @enum portmod_intr_type_e 1154 * @brief Interrupt types 1155 */ 1156 typedef enum portmod_intr_type_e { 1157 portmodIntrTypeMibTxMemErr = 0, /**< clmac/xlmac mib Tx err */ 1158 portmodIntrTypeMibRxMemErr = 1, /**< clmac/xlmac mib Rx err */ 1159 portmodIntrTypeMacTxCdcMemErr = 2, /**< clmac/xlmac tx CDC */ 1160 portmodIntrTypeMacRxCdcMemErr = 3, /**< clmac/xlmac Rx CDC */ 1161 portmodIntrTypeMacRxTsCdcMemErr = 4, /**< clmac/xlmac Rx TS CDC err */ 1162 portmodIntrTypeTscErr = 5, /**< clmac TSC err */ 1163 portmodIntrTypePmdErr = 6, /**< clmac PMD err */ 1164 portmodIntrTypeRxFcReqFull = 7, /**< 100G CXX Flow Control Req */ 1165 portmodIntrTypeCore0Intr = 8, /**< 100G core-0 irq */ 1166 portmodIntrTypeCore1Intr = 9, /**< 100G core-1 irq */ 1167 portmodIntrTypeCore2Intr = 10, /**< 100G core-2 irq */ 1168 portmodIntrTypeCore3Intr = 11, /**< 100G core-3 irq */ 1169 portmodIntrTypeTsc0Intr = 12, /**< 100G Tsc-0 irq */ 1170 portmodIntrTypeTsc1Intr = 13, /**< 100G Tsc-1 irq */ 1171 portmodIntrTypeTsc2Intr = 14, /**< 100G Tsc-2 irq */ 1172 portmodIntrTypeLinkdown = 15, /**< Link down */ 1173 portmodIntrTypeMacErr = 16, /**< MAC error */ 1174 portmodIntrTypeTxPktUnderflow = 17, /**< MAC tx packet fifo underflow */ 1175 portmodIntrTypeTxPktOverflow = 18, /**< MAC tx packet fifo overflow */ 1176 portmodIntrTypeTxLlfcMsgOverflow = 19, /**< MAC TX LLFC message fifo overflow */ 1177 portmodIntrTypeTxTSFifoOverflow = 20, /**< Overflow in TX two-step Time Stamp FIFO */ 1178 portmodIntrTypeRxPktOverflow = 21, /**< MAC RX packet fifo overflow */ 1179 portmodIntrTypeRxMsgOverflow = 22, /**< MAC RX message fifo overflow */ 1180 portmodIntrTypeTxCdcSingleBitErr = 23, /**< Single bit error in the MAC Tx CDC memory */ 1181 portmodIntrTypeTxCdcDoubleBitErr = 24, /**< Double bit error in the MAC Tx CDC memory */ 1182 portmodIntrTypeRxCdcSingleBitErr = 25, /**< Single bit error in the MAC Rx CDC memory */ 1183 portmodIntrTypeRxCdcDoubleBitErr = 26, /**< Double bit error in the MAC Rx CDC memory */ 1184 portmodIntrTypeRxTsMemSingleBitErr = 27, /**< Single bit error in the MAC Rx Timestamp memory */ 1185 portmodIntrTypeRxTsMemDoubleBitErr = 28, /**< Double bit error in the MAC Rx Timestamp memory */ 1186 portmodIntrTypeLocalFaultStatus = 29, /**< Local fault by RS layer */ 1187 portmodIntrTypeRemoteFaultStatus = 30, /**< Remote fault by RS layer */ 1188 portmodIntrTypeLinkInterruptionStatus = 31, /**< Link interruption by RS layer */ 1189 portmodIntrTypeTsEntryValid = 32, /**< TimeStamp */ 1190 portmodIntrTypeMibMemSingleBitErr = 33, /**< single-bit error in the MIB statistics counter memory in CDMAC */ 1191 portmodIntrTypeMibMemDoubleBitErr = 34, /**< double-bit error in the MIB statistics counter memory in CDMAC */ 1192 portmodIntrTypeMibMemMultipleBitErr = 35, /**< multiple-bit error in the MIB statistics counter memory in CDMAC */ 1193 portmodIntrTypeTscCore0Err = 36, /**< Error occurred on TSC core (also called MPP) 0 of CDPORT */ 1194 portmodIntrTypeTscCore1Err = 37, /**< Error occurred on TSC core (also called MPP) 1 of CDPORT */ 1195 portmodIntrTypeFcReqFull = 38, /**< When set per subport 7:0, PM8x50 accumulates more than 2 Rx pfc outstanding requests from MAC or 2 Tx outstanding pfc requests. */ 1196 portmodIntrTypeCount 1197 } portmod_intr_type_t; 1198 1199 #ifdef PORTMOD_DIAG 1200 extern enum_mapping_t portmod_intr_type_t_mapping[]; 1201 #endif /*PORTMOD_DIAG*/ 1202 1203 /* portmod_intr_type_t validation */ 1204 int portmod_intr_type_t_validate(int unit, portmod_intr_type_t portmod_intr_type); 1205 /*! 1206 * portmod_mac_soft_reset_f 1207 * 1208 * @brief external reset function 1209 * 1210 * @param [in] unit - unit id 1211 * @param [in] port - logical port 1212 * @param [in] action - when is this callback called 1213 */ 1214 typedef int (*portmod_mac_soft_reset_f)(int unit, int port, portmod_call_back_action_type_t action); 1215 1216 1217 /*! 1218 * @struct portmod_pm4x25_create_info_s 1219 * @brief PM4X25 specific information required for PM add API. 1220 */ 1221 typedef struct portmod_pm4x25_create_info_s { 1222 phymod_ref_clk_t ref_clk; /**< SerDes quad ref clock */ 1223 phymod_access_t access; /**< phymod access structure; defines the register access for the SerDes Core */ 1224 phymod_lane_map_t lane_map; 1225 phymod_firmware_load_method_t fw_load_method; 1226 phymod_firmware_loader_f external_fw_loader; /**< firmware loader that will be used in case that fw_load_method=phymodFirmwareLoadMethodExternal */ 1227 phymod_polarity_t polarity; /**< Lanes Polarity */ 1228 uint8 in_pm_12x10; /**< is the PM part of a PM12x10 block */ 1229 int core_num; 1230 int core_num_int; 1231 portmod_mac_soft_reset_f portmod_mac_soft_reset; /**< used when soft reset require external method. */ 1232 phymod_afe_pll_t afe_pll; /**< override default value of AFE/PLL reg. */ 1233 int rescal; 1234 portmod_port_mode_aux_info_t port_mode_aux_info; /**< auxiliary info for assigning the core port mode */ 1235 } portmod_pm4x25_create_info_t; 1236 1237 /* portmod_pm4x25_create_info_t initialization and validation */ 1238 int portmod_pm4x25_create_info_t_validate(int unit, const portmod_pm4x25_create_info_t* portmod_pm4x25_create_info); 1239 int portmod_pm4x25_create_info_t_init(int unit, portmod_pm4x25_create_info_t* portmod_pm4x25_create_info); 1240 1241 /*! 1242 * portmod_phy_external_reset_f 1243 * 1244 * @brief external reset function 1245 * 1246 * @param [in] unit - unit id 1247 * @param [in] port - logical port 1248 * @param [in] in_reset - whether to put phy in\out reset 1249 */ 1250 typedef int (*portmod_phy_external_reset_f)(int unit, int port, uint32 in_reset); 1251 1252 1253 /*! 1254 * @struct portmod_pm4x10_create_info_s 1255 * @brief PM4X10 specific information required for PM add API. 1256 */ 1257 typedef struct portmod_pm4x10_create_info_s { 1258 portmod_pbmp_t phy_ports; /**< phys with qsgmii offsets. to be removed */ 1259 phymod_ref_clk_t ref_clk; /**< SerDes quad ref clock */ 1260 phymod_access_t access; /**< phymod access structure; defines the register access for the SerDes Core */ 1261 phymod_lane_map_t lane_map; 1262 phymod_firmware_load_method_t fw_load_method; 1263 phymod_firmware_loader_f external_fw_loader; /**< firmware loader that will be used in case that fw_load_method=phymodFirmwareLoadMethodExternal */ 1264 phymod_polarity_t polarity; /**< Lanes Polarity */ 1265 uint8 in_pm_12x10; /**< is the PM part of a PM12x10 block */ 1266 portmod_phy_external_reset_f portmod_phy_external_reset; /**< used when phy required external method to be taken oor */ 1267 portmod_mac_soft_reset_f portmod_mac_soft_reset; /**< used when soft reset require external method. */ 1268 int core_num; 1269 int core_num_int; 1270 portmod_port_mode_aux_info_t port_mode_aux_info; /**< auxiliary info for assigning the core port mode */ 1271 int rescal; 1272 int is_pm4x10q; 1273 } portmod_pm4x10_create_info_t; 1274 1275 /* portmod_pm4x10_create_info_t initialization and validation */ 1276 int portmod_pm4x10_create_info_t_validate(int unit, const portmod_pm4x10_create_info_t* portmod_pm4x10_create_info); 1277 int portmod_pm4x10_create_info_t_init(int unit, portmod_pm4x10_create_info_t* portmod_pm4x10_create_info); 1278 1279 1280 /*! 1281 * @struct portmod_pm_qtc_create_info_s 1282 * @brief PM_QTC specific information required for PM add API. 1283 */ 1284 typedef struct portmod_pm_qtc_create_info_s { 1285 phymod_ref_clk_t ref_clk; /**< SerDes quad ref clock */ 1286 phymod_access_t access; /**< phymod access structure; defines the register access for the SerDes Core */ 1287 phymod_lane_map_t lane_map; 1288 phymod_firmware_load_method_t fw_load_method; 1289 phymod_firmware_loader_f external_fw_loader; /**< firmware loader that will be used in case that fw_load_method=phymodFirmwareLoadMethodExternal */ 1290 phymod_polarity_t polarity; /**< Lanes Polarity */ 1291 portmod_phy_external_reset_f portmod_phy_external_reset; /**< used when phy required external method to be taken oor */ 1292 portmod_mac_soft_reset_f portmod_mac_soft_reset; /**< used when soft reset require external method. */ 1293 int core_num; 1294 uint32 core_clock_khz; /**< core clock Khz */ 1295 } portmod_pm_qtc_create_info_t; 1296 1297 /* portmod_pm_qtc_create_info_t initialization and validation */ 1298 int portmod_pm_qtc_create_info_t_validate(int unit, const portmod_pm_qtc_create_info_t* portmod_pm_qtc_create_info); 1299 int portmod_pm_qtc_create_info_t_init(int unit, portmod_pm_qtc_create_info_t* portmod_pm_qtc_create_info); 1300 1301 1302 /*! 1303 * @struct portmod_pm_gphy_create_info_s 1304 * @brief PM4X10 specific information required for PM add API. 1305 */ 1306 typedef struct portmod_pm_gphy_create_info_s { 1307 phymod_ref_clk_t ref_clk; /**< SerDes quad ref clock */ 1308 phymod_access_t access; /**< phymod access structure; defines the register access for the SerDes Core */ 1309 phymod_lane_map_t lane_map; 1310 phymod_firmware_load_method_t fw_load_method; 1311 phymod_firmware_loader_f external_fw_loader; /**< firmware loader that will be used in case that fw_load_method=phymodFirmwareLoadMethodExternal */ 1312 phymod_polarity_t polarity; /**< Lanes Polarity */ 1313 portmod_phy_external_reset_f portmod_phy_external_reset; /**< used when phy required external method to be taken oor */ 1314 portmod_mac_soft_reset_f portmod_mac_soft_reset; /**< used when soft reset require external method. */ 1315 int core_num; 1316 } portmod_pm_gphy_create_info_t; 1317 1318 /* portmod_pm_gphy_create_info_t initialization and validation */ 1319 int portmod_pm_gphy_create_info_t_validate(int unit, const portmod_pm_gphy_create_info_t* portmod_pm_gphy_create_info); 1320 int portmod_pm_gphy_create_info_t_init(int unit, portmod_pm_gphy_create_info_t* portmod_pm_gphy_create_info); 1321 1322 /*! 1323 * @brief Flags for adding PM12x10 1324 */ 1325 #define PORTMOD_PM12x10_F_EXTERNAL_TOP_MODE 0x1 /**< Each PM4x10 handles its own access (use for default access/fw load functions) */ 1326 #define PORTMOD_PM12x10_F_USE_PM_TD 0x2 /**< Use TD version of PM4x25, PM4x10 */ 1327 #define PORTMOD_PM12x10_F_USE_PM_XGS 0x4 /**< Use XGS version PM12x10 */ 1328 1329 #define PORTMOD_PM12x10_F_EXTERNAL_TOP_MODE_SET(flags) ((flags) |= PORTMOD_PM12x10_F_EXTERNAL_TOP_MODE) 1330 #define PORTMOD_PM12x10_F_USE_PM_TD_SET(flags) ((flags) |= PORTMOD_PM12x10_F_USE_PM_TD) 1331 #define PORTMOD_PM12x10_F_USE_PM_XGS_SET(flags) ((flags) |= PORTMOD_PM12x10_F_USE_PM_XGS) 1332 1333 #define PORTMOD_PM12x10_F_EXTERNAL_TOP_MODE_CLR(flags) ((flags) &= ~PORTMOD_PM12x10_F_EXTERNAL_TOP_MODE) 1334 #define PORTMOD_PM12x10_F_USE_PM_TD_CLR(flags) ((flags) &= ~PORTMOD_PM12x10_F_USE_PM_TD) 1335 #define PORTMOD_PM12x10_F_USE_PM_XGS_CLR(flags) ((flags) &= ~PORTMOD_PM12x10_F_USE_PM_XGS) 1336 1337 #define PORTMOD_PM12x10_F_EXTERNAL_TOP_MODE_GET(flags) ((flags) & PORTMOD_PM12x10_F_EXTERNAL_TOP_MODE ? 1 : 0) 1338 #define PORTMOD_PM12x10_F_USE_PM_TD_GET(flags) ((flags) & PORTMOD_PM12x10_F_USE_PM_TD ? 1 : 0) 1339 #define PORTMOD_PM12x10_F_USE_PM_XGS_GET(flags) ((flags) & PORTMOD_PM12x10_F_USE_PM_XGS ? 1 : 0) 1340 1341 1342 /*! 1343 * @struct portmod_pm12x10_create_info_s 1344 * @brief PM12X10 specific information required for PM add API. 1345 */ 1346 typedef struct portmod_pm12x10_create_info_s { 1347 portmod_pm4x10_create_info_t pm4x10_infos[3]; /**< initialization information for the three pm4x10 in the pm12x10 */ 1348 portmod_pm4x25_create_info_t pm4x25_info; 1349 uint32 flags; /**< see PORTMOD_PM12x10_F_ */ 1350 int blk_id; /**< block id of PM12x10 */ 1351 int refclk_source; /**< select which quad in pm12x10 is refclk source for other 2 quads */ 1352 } portmod_pm12x10_create_info_t; 1353 1354 /* portmod_pm12x10_create_info_t initialization and validation */ 1355 int portmod_pm12x10_create_info_t_validate(int unit, const portmod_pm12x10_create_info_t* portmod_pm12x10_create_info); 1356 int portmod_pm12x10_create_info_t_init(int unit, portmod_pm12x10_create_info_t* portmod_pm12x10_create_info); 1357 1358 1359 /*! 1360 * @struct portmod_pm4x10q_create_info_s 1361 * @brief PM4X10Q specific information required for PM add API. 1362 */ 1363 typedef struct portmod_pm4x10q_create_info_s { 1364 portmod_pm4x10_create_info_t pm4x10_info; /**< initialization information for the pm4x10 in the pm4x10Q */ 1365 uint32 blk_id; /**< PMQ block id */ 1366 void* qsgmii_user_acc; /**< qsgmii_access */ 1367 uint32 core_clock_khz; /**< core clock Khz */ 1368 } portmod_pm4x10q_create_info_t; 1369 1370 /* portmod_pm4x10q_create_info_t initialization and validation */ 1371 int portmod_pm4x10q_create_info_t_validate(int unit, const portmod_pm4x10q_create_info_t* portmod_pm4x10q_create_info); 1372 int portmod_pm4x10q_create_info_t_init(int unit, portmod_pm4x10q_create_info_t* portmod_pm4x10q_create_info); 1373 1374 #define PORTMOD_MAX_ILKN_PORTS_PER_ILKN_PM (2) 1375 1376 1377 /*! 1378 * @struct portmod_ilkn_os_create_info_s 1379 * @brief Open Silicon ILKN information required for PM add API. 1380 */ 1381 typedef struct portmod_ilkn_os_create_info_s { 1382 int nof_aggregated_pms; /**< Number of PMs controlled by this ILKN PM */ 1383 portmod_pm_identifier_t* controlled_pms; /**< Array of PMs controlled by this ILKN PM */ 1384 int wm_high[PORTMOD_MAX_ILKN_PORTS_PER_ILKN_PM]; /**< Tx fifo watermark high value for each port in the ILKN core */ 1385 int wm_low[PORTMOD_MAX_ILKN_PORTS_PER_ILKN_PM]; /**< Tx fifo watermark low value for each port in the ILKN core */ 1386 uint32 is_over_fabric; /**< dnx specific feature */ 1387 uint32 core_clock_khz; /**< core clock Khz */ 1388 portmod_ilkn_core_lane_map_callback_get_f ilkn_core_lane_map_get; /**< ilkn core lane map get function */ 1389 portmod_ilkn_pm_lane_map_callback_get_f ilkn_pm_lane_map_get; /**< ilkn pm lane map get function */ 1390 uint32 ilkn_block_index; /**< ilkn interface block Index */ 1391 } portmod_ilkn_os_create_info_t; 1392 1393 /* portmod_ilkn_os_create_info_t initialization and validation */ 1394 int portmod_ilkn_os_create_info_t_validate(int unit, const portmod_ilkn_os_create_info_t* portmod_ilkn_os_create_info); 1395 int portmod_ilkn_os_create_info_t_init(int unit, portmod_ilkn_os_create_info_t* portmod_ilkn_os_create_info); 1396 1397 1398 /*! 1399 * @struct portmod_pm4x2p5_create_info_s 1400 * @brief PM4X2P5 specific information required for PM add API. 1401 */ 1402 typedef struct portmod_pm4x2p5_create_info_s { 1403 soc_pbmp_t phy_ports; /**< phys with qsgmii offsets. to be removed */ 1404 phymod_ref_clk_t ref_clk; /**< SerDes quad ref clock */ 1405 phymod_access_t access; /**< phymod access structure; defines the register access for the SerDes Core */ 1406 phymod_lane_map_t lane_map; 1407 phymod_firmware_load_method_t fw_load_method; 1408 phymod_firmware_loader_f external_fw_loader; /**< firmware loader that will be used in case that fw_load_method=phymodFirmwareLoadMethodExternal */ 1409 phymod_polarity_t polarity; /**< Lanes Polarity */ 1410 portmod_phy_external_reset_f portmod_phy_external_reset; /**< used when phy required external method to be taken oor */ 1411 portmod_mac_soft_reset_f portmod_mac_soft_reset; /**< used when soft reset require external method. */ 1412 } portmod_pm4x2p5_create_info_t; 1413 1414 /* portmod_pm4x2p5_create_info_t initialization and validation */ 1415 int portmod_pm4x2p5_create_info_t_validate(int unit, const portmod_pm4x2p5_create_info_t* portmod_pm4x2p5_create_info); 1416 int portmod_pm4x2p5_create_info_t_init(int unit, portmod_pm4x2p5_create_info_t* portmod_pm4x2p5_create_info); 1417 1418 /*! 1419 * portmod_egress_buffer_reset_f 1420 * 1421 * @brief external egress reset function 1422 * 1423 * @param [in] unit - unit id 1424 * @param [in] port - logical port 1425 */ 1426 typedef int (*portmod_egress_buffer_reset_f)(int unit, int port); 1427 1428 1429 /*! 1430 * @struct portmod_pm8x50_create_info_s 1431 * @brief PM8X50 specific information required for PM add API. 1432 */ 1433 typedef struct portmod_pm8x50_create_info_s { 1434 soc_pbmp_t phy_ports; /**< list of physical ports in PM */ 1435 phymod_ref_clk_t ref_clk; /**< Ref clock 156Mhz etc */ 1436 portmod_vco_type_t tvco; /**< VCO value to be used by PLL1 */ 1437 portmod_vco_type_t ovco; /**< VCO value to be used by PLL0 */ 1438 phymod_phy_access_t access; /**< phymod phy access structure; defines the register access for the SerDes Core */ 1439 phymod_lane_map_t lane_map; 1440 phymod_firmware_load_method_t fw_load_method; 1441 phymod_firmware_loader_f external_fw_loader; /**< firmware loader that will be used in case that fw_load_method=phymodFirmwareLoadMethodExternal */ 1442 phymod_polarity_t polarity; /**< Lanes Polarity */ 1443 portmod_phy_external_reset_f portmod_phy_external_reset; /**< used when phy required external method to be taken oor */ 1444 portmod_mac_soft_reset_f portmod_mac_soft_reset; /**< used when soft reset require external method. */ 1445 int core_num; 1446 phymod_afe_pll_t afe_pll; /**< override default value of AFE/PLL reg. */ 1447 int rescal; 1448 int is_master_pm; 1449 portmod_egress_buffer_reset_f portmod_egress_buffer_reset; /**< for 400G AN WAR */ 1450 int allow_20p625g_tvco; 1451 } portmod_pm8x50_create_info_t; 1452 1453 /* portmod_pm8x50_create_info_t initialization and validation */ 1454 int portmod_pm8x50_create_info_t_validate(int unit, const portmod_pm8x50_create_info_t* portmod_pm8x50_create_info); 1455 int portmod_pm8x50_create_info_t_init(int unit, portmod_pm8x50_create_info_t* portmod_pm8x50_create_info); 1456 1457 1458 /*! 1459 * @struct portmod_pm4x10_qtc_create_info_s 1460 * @brief PM4x10_qtc specific information required for PM add API. 1461 */ 1462 typedef struct portmod_pm4x10_qtc_create_info_s { 1463 portmod_pm4x10_create_info_t pm4x10_info; /**< initialization information for pm4x10 in the pm4x10_qtc */ 1464 portmod_pm_qtc_create_info_t pm_qtc_info; /**< initialization information for pm_qtc in the pm4x10_qtc */ 1465 } portmod_pm4x10_qtc_create_info_t; 1466 1467 /* portmod_pm4x10_qtc_create_info_t initialization and validation */ 1468 int portmod_pm4x10_qtc_create_info_t_validate(int unit, const portmod_pm4x10_qtc_create_info_t* portmod_pm4x10_qtc_create_info); 1469 int portmod_pm4x10_qtc_create_info_t_init(int unit, portmod_pm4x10_qtc_create_info_t* portmod_pm4x10_qtc_create_info); 1470 1471 typedef union portmod_pm_specific_create_info_u { 1472 portmod_pm4x10_create_info_t pm4x10; 1473 portmod_pm4x10q_create_info_t pm4x10q; 1474 portmod_pm_qtc_create_info_t pm_qtc; 1475 portmod_pm_gphy_create_info_t pm_gphy; 1476 portmod_pm4x25_create_info_t pm4x25; 1477 portmod_pm12x10_create_info_t pm12x10; 1478 portmod_ilkn_os_create_info_t os_ilkn; 1479 portmod_dnx_fabric_create_info_t dnx_fabric; 1480 portmod_pm8x50_fabric_create_info_t pm8x50_fabric; 1481 portmod_pm4x2p5_create_info_t pm4x2p5; 1482 portmod_pm8x50_create_info_t pm8x50; 1483 portmod_pm4x10_qtc_create_info_t pm4x10_qtc; 1484 } portmod_pm_specific_create_info_t; 1485 1486 1487 /*! 1488 * @struct portmod_remote_fault_control_s 1489 * @brief This struct contains the parameters that 1490 */ 1491 typedef struct portmod_remote_fault_control_s { 1492 uint8 enable; /**< enable/disable processing of local fault messages */ 1493 uint8 drop_tx_on_fault; /**< drop tx data in case of fault */ 1494 } portmod_remote_fault_control_t; 1495 1496 /* portmod_remote_fault_control_t initialization and validation */ 1497 int portmod_remote_fault_control_t_validate(int unit, const portmod_remote_fault_control_t* portmod_remote_fault_control); 1498 int portmod_remote_fault_control_t_init(int unit, portmod_remote_fault_control_t* portmod_remote_fault_control); 1499 1500 typedef struct portmod_local_fault_control_s { 1501 uint8 enable; /**< enable/disable processing of remote fault messages */ 1502 uint8 drop_tx_on_fault; /**< drop tx data in case of fault */ 1503 } portmod_local_fault_control_t; 1504 1505 /* portmod_local_fault_control_t initialization and validation */ 1506 int portmod_local_fault_control_t_validate(int unit, const portmod_local_fault_control_t* portmod_local_fault_control); 1507 int portmod_local_fault_control_t_init(int unit, portmod_local_fault_control_t* portmod_local_fault_control); 1508 1509 1510 /*! 1511 * @struct portmod_llfc_control_s 1512 * @brief link level flow control configuration 1513 */ 1514 typedef struct portmod_llfc_control_s { 1515 uint8 rx_enable; /**< enable LLFX in RX path */ 1516 uint8 tx_enable; /**< enable LLFX in TX path */ 1517 uint8 crc_ignore; 1518 uint8 in_ipg_only; /**< llfc messages will be inserted only during IPG */ 1519 } portmod_llfc_control_t; 1520 1521 /* portmod_llfc_control_t initialization and validation */ 1522 int portmod_llfc_control_t_validate(int unit, const portmod_llfc_control_t* portmod_llfc_control); 1523 int portmod_llfc_control_t_init(int unit, portmod_llfc_control_t* portmod_llfc_control); 1524 1525 1526 /*! 1527 * @struct portmod_pfc_control_s 1528 * @brief priority flow control configuration 1529 */ 1530 typedef struct portmod_pfc_control_s { 1531 uint8 rx_enable; 1532 uint8 tx_enable; 1533 uint8 stats_en; /**< enable PFC counters */ 1534 uint8 force_xon; /**< Instructs MAC to send Xon message to all classes of service */ 1535 int refresh_timer; /**< use 0 for disable this feature; Threshold for pause timer to cause XOFF to be resent */ 1536 int xoff_timer; /**< Time value sent in the Timer Field for classes in XOFF state */ 1537 } portmod_pfc_control_t; 1538 1539 /* portmod_pfc_control_t initialization and validation */ 1540 int portmod_pfc_control_t_validate(int unit, const portmod_pfc_control_t* portmod_pfc_control); 1541 int portmod_pfc_control_t_init(int unit, portmod_pfc_control_t* portmod_pfc_control); 1542 1543 1544 /*! 1545 * @struct portmod_pause_control_s 1546 * @brief pause flow control configuration 1547 */ 1548 typedef struct portmod_pause_control_s { 1549 uint8 rx_enable; 1550 uint8 tx_enable; 1551 int refresh_timer; /**< use -1 for disable this feature; Threshold for pause timer to cause XOFF to be resent */ 1552 int xoff_timer; /**< Time value sent in the Timer Field for classes in XOFF state */ 1553 } portmod_pause_control_t; 1554 1555 /* portmod_pause_control_t initialization and validation */ 1556 int portmod_pause_control_t_validate(int unit, const portmod_pause_control_t* portmod_pause_control); 1557 int portmod_pause_control_t_init(int unit, portmod_pause_control_t* portmod_pause_control); 1558 1559 1560 /*! 1561 * @struct portmod_drain_cells_s 1562 * @brief Information needed to restore after drain cells 1563 */ 1564 typedef struct portmod_drain_cells_s { 1565 int rx_pfc_en; 1566 int llfc_en; 1567 int rx_pause; 1568 int tx_pause; 1569 } portmod_drain_cells_t; 1570 1571 /* portmod_drain_cells_t initialization and validation */ 1572 int portmod_drain_cells_t_validate(int unit, const portmod_drain_cells_t* portmod_drain_cells); 1573 int portmod_drain_cells_t_init(int unit, portmod_drain_cells_t* portmod_drain_cells); 1574 1575 1576 /*! 1577 * @struct portmod_pm_create_info_s 1578 * @brief This struct contains the required information in order to add new PM to the PMM and create PM DB. 1579 */ 1580 typedef struct portmod_pm_create_info_s { 1581 portmod_dispatch_type_t type; /**< PM type */ 1582 portmod_pbmp_t phys; /**< which PHYs belongs to the PM */ 1583 portmod_pm_specific_create_info_t pm_specific_info; 1584 } portmod_pm_create_info_t; 1585 1586 /* portmod_pm_create_info_t initialization and validation */ 1587 int portmod_pm_create_info_t_validate(int unit, const portmod_pm_create_info_t* portmod_pm_create_info); 1588 int portmod_pm_create_info_t_init(int unit, portmod_pm_create_info_t* portmod_pm_create_info); 1589 1590 #define PORTMOD_SIDE_SYSTEM (0) 1591 #define PORTMOD_SIDE_LINE (1) 1592 1593 #define PORTMOD_PHYN_LAST_ONE (-1) 1594 1595 1596 /*! 1597 * @struct portmod_access_get_params_s 1598 * @brief This struct used to select the access structure that will return from port_phy_lane_access_get 1599 */ 1600 typedef struct portmod_access_get_params_s { 1601 int phyn; /**< hop number. 0-internal phy. 1 and up- external phys. -1 means the last one */ 1602 int sys_side; /**< sys/line side.values: PORTMOD_SIDE_LINE, PORTMOD_SIDE_SYSTEM */ 1603 int lane; /**< specific lane index. -1 (PORTMOD_ALL_LANES_ARE_ACTIVE) means return all lanes. -2 (PORTMOD_NO_LANE_IS_ACTIVE) means return no lane */ 1604 int apply_lane_mask; /**< do lane masked for int core pm12x10 */ 1605 } portmod_access_get_params_t; 1606 1607 /* portmod_access_get_params_t initialization and validation */ 1608 int portmod_access_get_params_t_validate(int unit, const portmod_access_get_params_t* portmod_access_get_params); 1609 int portmod_access_get_params_t_init(int unit, portmod_access_get_params_t* portmod_access_get_params); 1610 1611 #define PORTMOD_ALL_LANES_ARE_ACTIVE (-1) 1612 #define PORTMOD_NO_LANE_IS_ACTIVE (-2) 1613 1614 1615 /*! 1616 * @struct portmod_pm_instances_s 1617 * @brief This struct contains information about number of instances for PM type 1618 */ 1619 typedef struct portmod_pm_instances_s { 1620 portmod_dispatch_type_t type; /**< Port Macro type */ 1621 int instances; /**< the number of instances of the specified Port Macro type */ 1622 } portmod_pm_instances_t; 1623 1624 /* portmod_pm_instances_t initialization and validation */ 1625 int portmod_pm_instances_t_validate(int unit, const portmod_pm_instances_t* portmod_pm_instances); 1626 int portmod_pm_instances_t_init(int unit, portmod_pm_instances_t* portmod_pm_instances); 1627 1628 /*! 1629 * @brief Portmod Create Flags 1630 */ 1631 #define PORTMOD_CREATE_F_PM_NULL 0x1 /**< Add PortmodNull */ 1632 1633 #define PORTMOD_CREATE_F_PM_NULL_SET(flags) (flags |= PORTMOD_CREATE_F_PM_NULL) 1634 1635 #define PORTMOD_CREATE_F_PM_NULL_CLR(flags) (flags &= ~PORTMOD_CREATE_F_PM_NULL) 1636 1637 #define PORTMOD_CREATE_F_PM_NULL_GET(flags) (flags & PORTMOD_CREATE_F_PM_NULL ? 1 : 0) 1638 1639 #define PORTMOD_EEE_ENABLE_LPI_BYPASS PHYMOD_LPI_BYPASS /**< enable/disable LPI bypass */ 1640 1641 #define PORTMOD_EEE_ENABLE_LPI_BYPASS_SET(flags) ((flags) |= PORTMOD_EEE_ENABLE_LPI_BYPASS) 1642 1643 #define PORTMOD_EEE_ENABLE_LPI_BYPASS_CLR(flags) ((flags) &= ~PORTMOD_EEE_ENABLE_LPI_BYPASS) 1644 1645 #define PORTMOD_EEE_ENABLE_LPI_BYPASS_GET(flags) ((flags) & PORTMOD_EEE_ENABLE_LPI_BYPASS ? 1 : 0) 1646 1647 /*! 1648 * portmod_create 1649 * 1650 * @brief Allocate PMM memory for the specified unit. 1651 Should be recalled in case of Warm Boot 1652 * 1653 * @param [in] unit - unit id 1654 * @param [in] flags - flags to indicate pmnull 1655 * @param [in] max_ports - Max ports that should be supported in portmod for the specified unit 1656 * @param [in] max_phys - Max PHYs that should be supported in portmod for the specified unit 1657 * @param [in] nof_pm_instances - Number of elements of the pm_instances array 1658 * @param [in] pm_instances - 1659 */ 1660 int portmod_create(int unit, int flags, int max_ports, int max_phys, int nof_pm_instances, const portmod_pm_instances_t* pm_instances); 1661 1662 /*! 1663 * portmod_destroy 1664 * 1665 * @brief Release unit PMM resources. 1666 * 1667 * @param [in] unit - unit id 1668 */ 1669 int portmod_destroy(int unit); 1670 1671 /*! 1672 * portmod_port_macro_add 1673 * 1674 * @brief Add new port macro to the unit PMM; <br> In case of warm boot should be re called in the same order as called in cold boot 1675 * 1676 * @param [in] unit - unit id 1677 * @param [in] pm_info - 1678 */ 1679 int portmod_port_macro_add(int unit, const portmod_pm_create_info_t* pm_info); 1680 1681 1682 1683 1684 /*! 1685 * portmod_port_add 1686 * 1687 * @brief Add new port. Add the port to the PM DB. 1688 * 1689 * @param [in] unit - unit id 1690 * @param [in] port - logical port 1691 * @param [in] add_info - 1692 */ 1693 int portmod_port_add(int unit, int port, const portmod_port_add_info_t* add_info); 1694 1695 1696 1697 1698 1699 1700 1701 /*! 1702 * portmod_port_remove 1703 * 1704 * @brief Remove the port from the PM and PMM. 1705 portmod_port_enable_set(unit, port, 0); should be called before 1706 * 1707 * @param [in] unit - unit id 1708 * @param [in] port - logical port 1709 */ 1710 int portmod_port_remove(int unit, int port); 1711 1712 1713 1714 /*! 1715 * portmod_port_first_phy_get 1716 * 1717 * @brief get the first phy of the specified port 1718 * 1719 * @param [in] unit - unit id 1720 * @param [in] port - logical port 1721 * @param [out] phy - 1722 * @param [out] sub_phy - 1723 */ 1724 int portmod_port_first_phy_get(int unit, int port, int* phy, int* sub_phy); 1725 1726 /*! 1727 * portmod_port_phys_get 1728 * 1729 * @brief get the phys bitmap of the specified port 1730 * 1731 * @param [in] unit - unit id 1732 * @param [in] port - logical port 1733 * @param [out] phys - phys bitmap 1734 */ 1735 int portmod_port_phys_get(int unit, int port, portmod_pbmp_t* phys); 1736 1737 /*! 1738 * portmod_port_is_valid 1739 * 1740 * @brief Get the specific port has valid pm. 1741 * 1742 * @param [in] unit - unit id 1743 * @param [in] port - logical port 1744 * @param [out] valid - TRUE if port has valid pm_id 1745 */ 1746 int portmod_port_is_valid(int unit, int port, int* valid); 1747 1748 /*! 1749 * portmod_port_pm_type_get 1750 * 1751 * @brief Get the pm type of a port. 1752 * 1753 * @param [in] unit - unit id 1754 * @param [in] port - logical port 1755 * @param [out] real_port - real port num 1756 * @param [out] pm_type - dispatch type 1757 */ 1758 int portmod_port_pm_type_get(int unit, int port, int* real_port, portmod_dispatch_type_t* pm_type); 1759 1760 /*! 1761 * portmod_port_enable_set 1762 * 1763 * @brief Port enable 1764 * 1765 * @param [in] unit - unit id 1766 * @param [in] port - logical port 1767 * @param [out] flags - see PORTMOD_PORT_ENABLE_... 1768 * @param [in] enable - 1769 */ 1770 int portmod_port_enable_set(int unit, int port, int flags, int enable); 1771 /*! 1772 * portmod_port_enable_get 1773 * 1774 * @brief Port enable 1775 * 1776 * @param [in] unit - unit id 1777 * @param [in] port - logical port 1778 * @param [out] flags - see PORTMOD_PORT_ENABLE_... 1779 * @param [out] enable - 1780 */ 1781 int portmod_port_enable_get(int unit, int port, int flags, int* enable); 1782 1783 /*! 1784 * portmod_port_cdr_lock_get 1785 * 1786 * @brief Get if CDR is locked 1787 * 1788 * @param [in] unit - unit id 1789 * @param [in] port - logical port 1790 * @param [out] is_locked - is cdr locked 1791 */ 1792 int portmod_port_cdr_lock_get(int unit, int port, int* is_locked); 1793 1794 /*! 1795 * portmod_port_interface_config_set 1796 * 1797 * @brief set/get the interface, speed and encapsulation for the specified port. 1798 For the First port within core this function initialize the PM, MAC and PHY before configure the port. 1799 * 1800 * @param [in] unit - unit id 1801 * @param [in] port - logical port 1802 * @param [in] config - 1803 * @param [in] phy_init_flags - see PORTMOD_INIT_F_... 1804 */ 1805 int portmod_port_interface_config_set(int unit, int port, const portmod_port_interface_config_t* config, int phy_init_flags); 1806 /*! 1807 * portmod_port_interface_config_get 1808 * 1809 * @brief set/get the interface, speed and encapsulation for the specified port. 1810 For the First port within core this function initialize the PM, MAC and PHY before configure the port. 1811 * 1812 * @param [in] unit - unit id 1813 * @param [in] port - logical port 1814 * @param [out] config - 1815 * @param [in] phy_init_flags - see PORTMOD_INIT_F_... 1816 */ 1817 int portmod_port_interface_config_get(int unit, int port, portmod_port_interface_config_t* config, int phy_init_flags); 1818 1819 /*! 1820 * portmod_port_default_interface_get 1821 * 1822 * @brief get the default line-side (outmost) interface type of a port based on its speed, encap, number of lanes, etc, when there is or there is not an ext PHY 1823 * 1824 * @param [in] unit - unit id 1825 * @param [in] port - logical port 1826 * @param [in] config - 1827 * @param [out] interface - 1828 */ 1829 int portmod_port_default_interface_get(int unit, int port, const portmod_port_interface_config_t* config, soc_port_if_t* interface); 1830 1831 /*! 1832 * portmod_port_interface_check 1833 * 1834 * @brief check whether the interface type is valid based on the port speed, #lanes, etc 1835 * 1836 * @param [in] unit - unit id 1837 * @param [in] port - logical port 1838 * @param [in] config - 1839 * @param [in] is_ext_phy - 1840 * @param [in] interface - 1841 * @param [out] is_valid - 1842 */ 1843 int portmod_port_interface_check(int unit, int port, const portmod_port_interface_config_t* config, int is_ext_phy, soc_port_if_t interface, int* is_valid); 1844 1845 /*! 1846 * portmod_port_encoding_set 1847 * 1848 * @brief chage port PCS encoding 1849 * 1850 * @param [in] unit - unit id 1851 * @param [in] port - logical port 1852 * @param [in] properties - 1853 * @param [in] encoding - 1854 */ 1855 int portmod_port_encoding_set(int unit, int port, uint32 properties, portmod_port_pcs_t encoding); 1856 /*! 1857 * portmod_port_encoding_get 1858 * 1859 * @brief chage port PCS encoding 1860 * 1861 * @param [in] unit - unit id 1862 * @param [in] port - logical port 1863 * @param [out] properties - 1864 * @param [out] encoding - 1865 */ 1866 int portmod_port_encoding_get(int unit, int port, uint32* properties, portmod_port_pcs_t* encoding); 1867 1868 /*! 1869 * portmod_port_cl72_set 1870 * 1871 * @brief Port cl72 set/get 1872 * 1873 * @param [in] unit - unit id 1874 * @param [in] port - logical port 1875 * @param [in] enable - 1876 */ 1877 int portmod_port_cl72_set(int unit, int port, uint32 enable); 1878 /*! 1879 * portmod_port_cl72_get 1880 * 1881 * @brief Port cl72 set/get 1882 * 1883 * @param [in] unit - unit id 1884 * @param [in] port - logical port 1885 * @param [out] enable - 1886 */ 1887 int portmod_port_cl72_get(int unit, int port, uint32* enable); 1888 1889 /*! 1890 * portmod_port_cl72_status_get 1891 * 1892 * @brief Get port cl72 status 1893 * 1894 * @param [in] unit - unit id 1895 * @param [in] port - logical port 1896 * @param [out] status - 1897 */ 1898 int portmod_port_cl72_status_get(int unit, int port, phymod_cl72_status_t* status); 1899 1900 /*! 1901 * portmod_port_loopback_set 1902 * 1903 * @brief Port speed set/get 1904 * 1905 * @param [in] unit - unit id 1906 * @param [in] port - logical port 1907 * @param [in] loopback_type - 1908 * @param [in] enable - 1909 */ 1910 int portmod_port_loopback_set(int unit, int port, portmod_loopback_mode_t loopback_type, int enable); 1911 /*! 1912 * portmod_port_loopback_get 1913 * 1914 * @brief Port speed set/get 1915 * 1916 * @param [in] unit - unit id 1917 * @param [in] port - logical port 1918 * @param [in] loopback_type - 1919 * @param [out] enable - 1920 */ 1921 int portmod_port_loopback_get(int unit, int port, portmod_loopback_mode_t loopback_type, int* enable); 1922 1923 /*! 1924 * portmod_port_pass_through_set 1925 * 1926 * @brief Port pass through set/get 1927 * 1928 * @param [in] unit - unit id 1929 * @param [in] port - logical port 1930 * @param [in] loopback_en - 1931 * @param [in] enable - 1932 */ 1933 int portmod_port_pass_through_set(int unit, int port, int loopback_en, int enable); 1934 /*! 1935 * portmod_port_pass_through_get 1936 * 1937 * @brief Port pass through set/get 1938 * 1939 * @param [in] unit - unit id 1940 * @param [in] port - logical port 1941 * @param [out] loopback_en - 1942 * @param [out] enable - 1943 */ 1944 int portmod_port_pass_through_get(int unit, int port, int* loopback_en, int* enable); 1945 1946 /*! 1947 * portmod_port_pass_through_calibrate 1948 * 1949 * @brief Port pass through calibration 1950 * 1951 * @param [in] unit - unit id 1952 * @param [in] port - logical port 1953 */ 1954 int portmod_port_pass_through_calibrate(int unit, int port); 1955 1956 /*! 1957 * portmod_port_pass_through_fec_enable_set 1958 * 1959 * @brief Port pass through fec enable set/get 1960 * 1961 * @param [in] unit - unit id 1962 * @param [in] port - logical port 1963 * @param [in] enable - 1964 */ 1965 int portmod_port_pass_through_fec_enable_set(int unit, int port, int enable); 1966 /*! 1967 * portmod_port_pass_through_fec_enable_get 1968 * 1969 * @brief Port pass through fec enable set/get 1970 * 1971 * @param [in] unit - unit id 1972 * @param [in] port - logical port 1973 * @param [out] enable - 1974 */ 1975 int portmod_port_pass_through_fec_enable_get(int unit, int port, int* enable); 1976 1977 /*! 1978 * portmod_port_rx_mac_enable_set 1979 * 1980 * @brief Port RX MAC ENABLE set/get 1981 * 1982 * @param [in] unit - unit id 1983 * @param [in] port - logical port 1984 * @param [in] enable - 1985 */ 1986 int portmod_port_rx_mac_enable_set(int unit, int port, int enable); 1987 /*! 1988 * portmod_port_rx_mac_enable_get 1989 * 1990 * @brief Port RX MAC ENABLE set/get 1991 * 1992 * @param [in] unit - unit id 1993 * @param [in] port - logical port 1994 * @param [out] enable - 1995 */ 1996 int portmod_port_rx_mac_enable_get(int unit, int port, int* enable); 1997 1998 /*! 1999 * portmod_port_tx_mac_enable_set 2000 * 2001 * @brief Port TX MAC ENABLE set/get 2002 * 2003 * @param [in] unit - unit id 2004 * @param [in] port - logical port 2005 * @param [in] enable - 2006 */ 2007 int portmod_port_tx_mac_enable_set(int unit, int port, int enable); 2008 /*! 2009 * portmod_port_tx_mac_enable_get 2010 * 2011 * @brief Port TX MAC ENABLE set/get 2012 * 2013 * @param [in] unit - unit id 2014 * @param [in] port - logical port 2015 * @param [out] enable - 2016 */ 2017 int portmod_port_tx_mac_enable_get(int unit, int port, int* enable); 2018 2019 /*! 2020 * portmod_port_ability_local_get 2021 * 2022 * @brief get port auto negotiation local ability 2023 * 2024 * @param [in] unit - unit id 2025 * @param [in] port - logical port 2026 * @param [in] phy_flags - which phy in the chain should be affected. see PORTMOD_INIT_F... 2027 * @param [out] ability - 2028 */ 2029 int portmod_port_ability_local_get(int unit, int port, uint32 phy_flags, portmod_port_ability_t* ability); 2030 2031 /*! 2032 * portmod_port_autoneg_set 2033 * 2034 * @brief Set/Get autoneg 2035 * 2036 * @param [in] unit - unit id 2037 * @param [in] port - logical port 2038 * @param [in] phy_flags - which phy in the chain should be affected. see PORTMOD_INIT_F... 2039 * @param [in] an - 2040 */ 2041 int portmod_port_autoneg_set(int unit, int port, uint32 phy_flags, const phymod_autoneg_control_t* an); 2042 /*! 2043 * portmod_port_autoneg_get 2044 * 2045 * @brief Set/Get autoneg 2046 * 2047 * @param [in] unit - unit id 2048 * @param [in] port - logical port 2049 * @param [in] phy_flags - which phy in the chain should be affected. see PORTMOD_INIT_F... 2050 * @param [out] an - 2051 */ 2052 int portmod_port_autoneg_get(int unit, int port, uint32 phy_flags, phymod_autoneg_control_t* an); 2053 2054 /*! 2055 * portmod_port_autoneg_status_get 2056 * 2057 * @brief Get autoneg status 2058 * 2059 * @param [in] unit - unit id 2060 * @param [in] port - logical port 2061 * @param [out] an_status - 2062 */ 2063 int portmod_port_autoneg_status_get(int unit, int port, phymod_autoneg_status_t* an_status); 2064 2065 /*! 2066 * portmod_port_link_get 2067 * 2068 * @brief get link status 2069 * 2070 * @param [in] unit - unit id 2071 * @param [in] port - logical port 2072 * @param [in] flags - option flag to indicate where cmd coming from. 2073 * @param [out] link - link indication up/down 2074 */ 2075 int portmod_port_link_get(int unit, int port, int flags, int* link); 2076 2077 /*! 2078 * @brief Port link latch down flags 2079 */ 2080 #define PORTMOD_PORT_LINK_LATCH_DOWN_F_CLEAR 0x1 /**< clear the latch down indication */ 2081 2082 2083 /*! 2084 * portmod_port_link_latch_down_get 2085 * 2086 * @brief get latch down link status (whether link was ever down since last clear) 2087 * 2088 * @param [in] unit - unit id 2089 * @param [in] port - logical port 2090 * @param [in] flags - see PORT_LINK_LATCH_DOWN_F 2091 * @param [out] link - link latch down indication 2092 */ 2093 int portmod_port_link_latch_down_get(int unit, int port, uint32 flags, int* link); 2094 2095 /*! 2096 * portmod_port_phy_link_up_event 2097 * 2098 * @brief link up event 2099 * 2100 * @param [in] unit - unit id 2101 * @param [in] port - logical port 2102 */ 2103 int portmod_port_phy_link_up_event(int unit, int port); 2104 2105 /*! 2106 * portmod_port_phy_link_down_event 2107 * 2108 * @brief link down event 2109 * 2110 * @param [in] unit - unit id 2111 * @param [in] port - logical port 2112 */ 2113 int portmod_port_phy_link_down_event(int unit, int port); 2114 2115 /*! 2116 * portmod_port_prbs_config_set 2117 * 2118 * @brief PRBS configuration set/get 2119 * 2120 * @param [in] unit - unit id 2121 * @param [in] port - logical port 2122 * @param [in] mode - 0- PHY PRBS, 1- MAC PRBS 2123 * @param [in] flags - 2124 * @param [in] config - PRBS configuration 2125 */ 2126 int portmod_port_prbs_config_set(int unit, int port, portmod_prbs_mode_t mode, int flags, const phymod_prbs_t* config); 2127 /*! 2128 * portmod_port_prbs_config_get 2129 * 2130 * @brief PRBS configuration set/get 2131 * 2132 * @param [in] unit - unit id 2133 * @param [in] port - logical port 2134 * @param [in] mode - 0- PHY PRBS, 1- MAC PRBS 2135 * @param [in] flags - 2136 * @param [out] config - PRBS configuration 2137 */ 2138 int portmod_port_prbs_config_get(int unit, int port, portmod_prbs_mode_t mode, int flags, phymod_prbs_t* config); 2139 2140 /*! 2141 * portmod_port_prbs_enable_set 2142 * 2143 * @brief PRBS enable set/get 2144 * 2145 * @param [in] unit - unit id 2146 * @param [in] port - logical port 2147 * @param [in] mode - 0- PHY PRBS, 1- MAC PRBS 2148 * @param [in] flags - 2149 * @param [in] enable - 2150 */ 2151 int portmod_port_prbs_enable_set(int unit, int port, portmod_prbs_mode_t mode, int flags, int enable); 2152 /*! 2153 * portmod_port_prbs_enable_get 2154 * 2155 * @brief PRBS enable set/get 2156 * 2157 * @param [in] unit - unit id 2158 * @param [in] port - logical port 2159 * @param [in] mode - 0- PHY PRBS, 1- MAC PRBS 2160 * @param [in] flags - 2161 * @param [out] enable - 2162 */ 2163 int portmod_port_prbs_enable_get(int unit, int port, portmod_prbs_mode_t mode, int flags, int* enable); 2164 2165 /*! 2166 * portmod_port_prbs_status_get 2167 * 2168 * @brief PRBS status get 2169 * 2170 * @param [in] unit - unit id 2171 * @param [in] port - logical port 2172 * @param [in] mode - 0- PHY PRBS, 1- MAC PRBS 2173 * @param [in] flags - see PHYMOD_PRBS_STATUS_FLAGS_ 2174 * @param [out] status - 2175 */ 2176 int portmod_port_prbs_status_get(int unit, int port, portmod_prbs_mode_t mode, int flags, phymod_prbs_status_t* status); 2177 2178 /*! 2179 * portmod_port_nof_lanes_get 2180 * 2181 * @brief Number of lanes get 2182 * 2183 * @param [in] unit - unit id 2184 * @param [in] port - logical port 2185 * @param [out] nof_lanes - 2186 */ 2187 int portmod_port_nof_lanes_get(int unit, int port, int* nof_lanes); 2188 2189 /*! 2190 * portmod_port_ilkn_nof_segments_set 2191 * 2192 * @brief ILKN Number of segments set/get 2193 * 2194 * @param [in] unit - unit id 2195 * @param [in] port - logical port 2196 * @param [in] nof_segments - Segemnts are a resource of the ILKN core, should be shared between the two ports on the same core. 2197 */ 2198 int portmod_port_ilkn_nof_segments_set(int unit, int port, uint32 nof_segments); 2199 /*! 2200 * portmod_port_ilkn_nof_segments_get 2201 * 2202 * @brief ILKN Number of segments set/get 2203 * 2204 * @param [in] unit - unit id 2205 * @param [in] port - logical port 2206 * @param [out] nof_segments - Segemnts are a resource of the ILKN core, should be shared between the two ports on the same core. 2207 */ 2208 int portmod_port_ilkn_nof_segments_get(int unit, int port, uint32* nof_segments); 2209 2210 /*! 2211 * portmod_ilkn_retranstmit_config_set 2212 * 2213 * @brief ILKN retransmit configuration set/get 2214 * 2215 * @param [in] unit - unit id 2216 * @param [in] port - logical port 2217 * @param [in] retransmit_config - 2218 */ 2219 int portmod_ilkn_retranstmit_config_set(int unit, int port, const ilkn_retransmit_config_t* retransmit_config); 2220 /*! 2221 * portmod_ilkn_retranstmit_config_get 2222 * 2223 * @brief ILKN retransmit configuration set/get 2224 * 2225 * @param [in] unit - unit id 2226 * @param [in] port - logical port 2227 * @param [out] retransmit_config - 2228 */ 2229 int portmod_ilkn_retranstmit_config_get(int unit, int port, ilkn_retransmit_config_t* retransmit_config); 2230 2231 /*! 2232 * portmod_port_lanes_assign 2233 * 2234 * @brief assign lane map to specific port 2235 * 2236 * @param [in] unit - unit id 2237 * @param [in] port - logical port 2238 * @param [in] assign_map - 2239 */ 2240 int portmod_port_lanes_assign(int unit, int port, const portmod_lanes_assign_info_t* assign_map); 2241 2242 /*! 2243 * portmod_port_lanes_retrieve 2244 * 2245 * @brief retrieve lane map of specific port 2246 * 2247 * @param [in] unit - unit id 2248 * @param [in] port - logical port 2249 * @param [out] assign_map - 2250 */ 2251 int portmod_port_lanes_retrieve(int unit, int port, portmod_lanes_assign_info_t* assign_map); 2252 2253 /*! 2254 * portmod_port_firmware_mode_set 2255 * 2256 * @brief Set port PHYs' firmware mode 2257 * 2258 * @param [in] unit - unit id 2259 * @param [in] port - logical port 2260 * @param [in] fw_mode - 2261 */ 2262 int portmod_port_firmware_mode_set(int unit, int port, phymod_firmware_mode_t fw_mode); 2263 /*! 2264 * portmod_port_firmware_mode_get 2265 * 2266 * @brief Set port PHYs' firmware mode 2267 * 2268 * @param [in] unit - unit id 2269 * @param [in] port - logical port 2270 * @param [out] fw_mode - 2271 */ 2272 int portmod_port_firmware_mode_get(int unit, int port, phymod_firmware_mode_t* fw_mode); 2273 2274 /*! 2275 * portmod_port_runt_threshold_set 2276 * 2277 * @brief Filter packets smaller than the specified threshold 2278 * 2279 * @param [in] unit - unit id 2280 * @param [in] port - logical port 2281 * @param [in] value - packets smaller than the specified values will be filtered 2282 */ 2283 int portmod_port_runt_threshold_set(int unit, int port, int value); 2284 /*! 2285 * portmod_port_runt_threshold_get 2286 * 2287 * @brief Filter packets smaller than the specified threshold 2288 * 2289 * @param [in] unit - unit id 2290 * @param [in] port - logical port 2291 * @param [out] value - packets smaller than this value are filtered 2292 */ 2293 int portmod_port_runt_threshold_get(int unit, int port, int* value); 2294 2295 /*! 2296 * portmod_port_max_packet_size_set 2297 * 2298 * @brief Filter packets bigger than the specified value 2299 * 2300 * @param [in] unit - unit id 2301 * @param [in] port - logical port 2302 * @param [in] value - the max packet size 2303 */ 2304 int portmod_port_max_packet_size_set(int unit, int port, int value); 2305 /*! 2306 * portmod_port_max_packet_size_get 2307 * 2308 * @brief Filter packets bigger than the specified value 2309 * 2310 * @param [in] unit - unit id 2311 * @param [in] port - logical port 2312 * @param [out] value - the max packet size 2313 */ 2314 int portmod_port_max_packet_size_get(int unit, int port, int* value); 2315 2316 /*! 2317 * portmod_port_pad_size_set 2318 * 2319 * @brief TX pad packets to the specified size. values smaller than 17 means pad is disabled. 2320 * 2321 * @param [in] unit - unit id 2322 * @param [in] port - logical port 2323 * @param [in] value - 2324 */ 2325 int portmod_port_pad_size_set(int unit, int port, int value); 2326 /*! 2327 * portmod_port_pad_size_get 2328 * 2329 * @brief TX pad packets to the specified size. values smaller than 17 means pad is disabled. 2330 * 2331 * @param [in] unit - unit id 2332 * @param [in] port - logical port 2333 * @param [out] value - 2334 */ 2335 int portmod_port_pad_size_get(int unit, int port, int* value); 2336 2337 /*! 2338 * portmod_port_tx_mac_sa_set 2339 * 2340 * @brief set/get the MAC source address that will be sent in case of Pause/LLFC 2341 * 2342 * @param [in] unit - unit id 2343 * @param [in] port - logical port 2344 * @param [in] mac_sa - 2345 */ 2346 int portmod_port_tx_mac_sa_set(int unit, int port, sal_mac_addr_t mac_sa); 2347 /*! 2348 * portmod_port_tx_mac_sa_get 2349 * 2350 * @brief set/get the MAC source address that will be sent in case of Pause/LLFC 2351 * 2352 * @param [in] unit - unit id 2353 * @param [in] port - logical port 2354 * @param [out] mac_sa - 2355 */ 2356 int portmod_port_tx_mac_sa_get(int unit, int port, sal_mac_addr_t mac_sa); 2357 2358 /*! 2359 * portmod_port_rx_mac_sa_set 2360 * 2361 * @brief set/get SA recognized for MAC control packets in addition to the standard 0x0180C2000001 2362 * 2363 * @param [in] unit - unit id 2364 * @param [in] port - logical port 2365 * @param [in] mac_sa - 2366 */ 2367 int portmod_port_rx_mac_sa_set(int unit, int port, sal_mac_addr_t mac_sa); 2368 /*! 2369 * portmod_port_rx_mac_sa_get 2370 * 2371 * @brief set/get SA recognized for MAC control packets in addition to the standard 0x0180C2000001 2372 * 2373 * @param [in] unit - unit id 2374 * @param [in] port - logical port 2375 * @param [out] mac_sa - 2376 */ 2377 int portmod_port_rx_mac_sa_get(int unit, int port, sal_mac_addr_t mac_sa); 2378 2379 /*! 2380 * portmod_port_tx_average_ipg_set 2381 * 2382 * @brief set/get Average inter-packet gap 2383 * 2384 * @param [in] unit - unit id 2385 * @param [in] port - logical port 2386 * @param [in] value - 2387 */ 2388 int portmod_port_tx_average_ipg_set(int unit, int port, int value); 2389 /*! 2390 * portmod_port_tx_average_ipg_get 2391 * 2392 * @brief set/get Average inter-packet gap 2393 * 2394 * @param [in] unit - unit id 2395 * @param [in] port - logical port 2396 * @param [out] value - 2397 */ 2398 int portmod_port_tx_average_ipg_get(int unit, int port, int* value); 2399 2400 /*! 2401 * portmod_port_tx_preamble_length_set 2402 * 2403 * @brief set/get Number of preamble bytes for transmit IEEE packets; this value should include the K.SOP and SFD character as well 2404 * 2405 * @param [in] unit - unit id 2406 * @param [in] port - logical port 2407 * @param [in] value - 2408 */ 2409 int portmod_port_tx_preamble_length_set(int unit, int port, int value); 2410 /*! 2411 * portmod_port_tx_preamble_length_get 2412 * 2413 * @brief set/get Number of preamble bytes for transmit IEEE packets; this value should include the K.SOP and SFD character as well 2414 * 2415 * @param [in] unit - unit id 2416 * @param [in] port - logical port 2417 * @param [out] value - 2418 */ 2419 int portmod_port_tx_preamble_length_get(int unit, int port, int* value); 2420 2421 /*! 2422 * portmod_port_local_fault_control_set 2423 * 2424 * @brief local fault set/get 2425 * 2426 * @param [in] unit - unit id 2427 * @param [in] port - logical port 2428 * @param [in] control - 2429 */ 2430 int portmod_port_local_fault_control_set(int unit, int port, const portmod_local_fault_control_t* control); 2431 /*! 2432 * portmod_port_local_fault_control_get 2433 * 2434 * @brief local fault set/get 2435 * 2436 * @param [in] unit - unit id 2437 * @param [in] port - logical port 2438 * @param [out] control - 2439 */ 2440 int portmod_port_local_fault_control_get(int unit, int port, portmod_local_fault_control_t* control); 2441 2442 /*! 2443 * portmod_port_remote_fault_control_set 2444 * 2445 * @brief remote fault set/get 2446 * 2447 * @param [in] unit - unit id 2448 * @param [in] port - logical port 2449 * @param [in] control - 2450 */ 2451 int portmod_port_remote_fault_control_set(int unit, int port, const portmod_remote_fault_control_t* control); 2452 /*! 2453 * portmod_port_remote_fault_control_get 2454 * 2455 * @brief remote fault set/get 2456 * 2457 * @param [in] unit - unit id 2458 * @param [in] port - logical port 2459 * @param [out] control - 2460 */ 2461 int portmod_port_remote_fault_control_get(int unit, int port, portmod_remote_fault_control_t* control); 2462 2463 /*! 2464 * portmod_port_local_fault_status_get 2465 * 2466 * @brief local fault steatus get 2467 * 2468 * @param [in] unit - unit id 2469 * @param [in] port - logical port 2470 * @param [out] value - 2471 */ 2472 int portmod_port_local_fault_status_get(int unit, int port, int* value); 2473 2474 /*! 2475 * portmod_port_remote_fault_status_get 2476 * 2477 * @brief remote fault status get 2478 * 2479 * @param [in] unit - unit id 2480 * @param [in] port - logical port 2481 * @param [out] value - 2482 */ 2483 int portmod_port_remote_fault_status_get(int unit, int port, int* value); 2484 2485 /*! 2486 * portmod_port_local_fault_status_clear 2487 * 2488 * @brief local fault steatus clear 2489 * 2490 * @param [in] unit - unit id 2491 * @param [in] port - logical port 2492 */ 2493 int portmod_port_local_fault_status_clear(int unit, int port); 2494 2495 /*! 2496 * portmod_port_remote_fault_status_clear 2497 * 2498 * @brief remote fault status clear 2499 * 2500 * @param [in] unit - unit id 2501 * @param [in] port - logical port 2502 */ 2503 int portmod_port_remote_fault_status_clear(int unit, int port); 2504 2505 /*! 2506 * portmod_port_pause_control_set 2507 * 2508 * @brief set/get Pause FC configuration 2509 * 2510 * @param [in] unit - unit id 2511 * @param [in] port - logical port 2512 * @param [in] control - 2513 */ 2514 int portmod_port_pause_control_set(int unit, int port, const portmod_pause_control_t* control); 2515 /*! 2516 * portmod_port_pause_control_get 2517 * 2518 * @brief set/get Pause FC configuration 2519 * 2520 * @param [in] unit - unit id 2521 * @param [in] port - logical port 2522 * @param [out] control - 2523 */ 2524 int portmod_port_pause_control_get(int unit, int port, portmod_pause_control_t* control); 2525 2526 /*! 2527 * portmod_port_pfc_control_set 2528 * 2529 * @brief set/get PFC FC configuration 2530 * 2531 * @param [in] unit - unit id 2532 * @param [in] port - logical port 2533 * @param [in] control - 2534 */ 2535 int portmod_port_pfc_control_set(int unit, int port, const portmod_pfc_control_t* control); 2536 /*! 2537 * portmod_port_pfc_control_get 2538 * 2539 * @brief set/get PFC FC configuration 2540 * 2541 * @param [in] unit - unit id 2542 * @param [in] port - logical port 2543 * @param [out] control - 2544 */ 2545 int portmod_port_pfc_control_get(int unit, int port, portmod_pfc_control_t* control); 2546 2547 /*! 2548 * portmod_port_llfc_control_set 2549 * 2550 * @brief set/get LLFC FC configuration 2551 * 2552 * @param [in] unit - unit id 2553 * @param [in] port - logical port 2554 * @param [in] control - 2555 */ 2556 int portmod_port_llfc_control_set(int unit, int port, const portmod_llfc_control_t* control); 2557 /*! 2558 * portmod_port_llfc_control_get 2559 * 2560 * @brief set/get LLFC FC configuration 2561 * 2562 * @param [in] unit - unit id 2563 * @param [in] port - logical port 2564 * @param [out] control - 2565 */ 2566 int portmod_port_llfc_control_get(int unit, int port, portmod_llfc_control_t* control); 2567 2568 /*! 2569 * @brief Port Update Flags 2570 */ 2571 #define PORTMOD_PORT_UPDATE_F_DISABLE_MAC 0x1 /**< disable MAC when phy link status is down */ 2572 #define PORTMOD_PORT_UPDATE_F_UPDATE_SERDES_LINK 0x2 /**< Force Serdes Link Status */ 2573 2574 #define PORTMOD_PORT_UPDATE_F_DISABLE_MAC_SET(control) ((control)->flags |= PORTMOD_PORT_UPDATE_F_DISABLE_MAC) 2575 #define PORTMOD_PORT_UPDATE_F_UPDATE_SERDES_LINK_SET(control) ((control)->flags |= PORTMOD_PORT_UPDATE_F_UPDATE_SERDES_LINK) 2576 2577 #define PORTMOD_PORT_UPDATE_F_DISABLE_MAC_CLR(control) ((control)->flags &= ~PORTMOD_PORT_UPDATE_F_DISABLE_MAC) 2578 #define PORTMOD_PORT_UPDATE_F_UPDATE_SERDES_LINK_CLR(control) ((control)->flags &= ~PORTMOD_PORT_UPDATE_F_UPDATE_SERDES_LINK) 2579 2580 #define PORTMOD_PORT_UPDATE_F_DISABLE_MAC_GET(control) ((control)->flags & PORTMOD_PORT_UPDATE_F_DISABLE_MAC ? 1 : 0) 2581 #define PORTMOD_PORT_UPDATE_F_UPDATE_SERDES_LINK_GET(control) ((control)->flags & PORTMOD_PORT_UPDATE_F_UPDATE_SERDES_LINK ? 1 : 0) 2582 2583 2584 /*! 2585 * @struct portmod_port_update_control_s 2586 * @brief Expected user access structure when using PM default bus 2587 */ 2588 typedef struct portmod_port_update_control_s { 2589 int link_status; /**< Current link status, use -1 to retrive the status inside the function */ 2590 uint32 flags; 2591 } portmod_port_update_control_t; 2592 2593 /* portmod_port_update_control_t initialization and validation */ 2594 int portmod_port_update_control_t_validate(int unit, const portmod_port_update_control_t* portmod_port_update_control); 2595 int portmod_port_update_control_t_init(int unit, portmod_port_update_control_t* portmod_port_update_control); 2596 2597 /*! 2598 * portmod_port_update 2599 * 2600 * @brief Routine for MAC/PHY sync. 2601 * 2602 * @param [in] unit - unit id 2603 * @param [in] port - logical port 2604 * @param [in] update_control - inputs for update operation 2605 */ 2606 int portmod_port_update(int unit, int port, const portmod_port_update_control_t* update_control); 2607 2608 /*! 2609 * portmod_port_core_access_get 2610 * 2611 * @brief get port cores' phymod access 2612 * 2613 * @param [in] unit - unit id 2614 * @param [in] port - logical port 2615 * @param [in] phyn - the number of hops from the internal phy. 0 - internal, 1- first external PHY, etc. 2616 * @param [in] max_cores - the output array number of elements 2617 * @param [out] core_access_arr - port phymod cores array 2618 * @param [out] nof_cores - number of core access structutres filled by the function 2619 * @param [out] is_most_ext - Whether this phy is the most external, can be passed as NULL 2620 */ 2621 int portmod_port_core_access_get(int unit, int port, int phyn, int max_cores, phymod_core_access_t* core_access_arr, int* nof_cores, int* is_most_ext); 2622 2623 /*! 2624 * portmod_port_phy_lane_access_get 2625 * 2626 * @brief Get lane phymod access structure. can be used for per lane operations 2627 * 2628 * @param [in] unit - unit id 2629 * @param [in] port - logical port 2630 * @param [in] params - 2631 * @param [in] max_phys - the output array number of elements 2632 * @param [out] access - 2633 * @param [out] nof_phys - number of phy access structutres filled by the function 2634 * @param [out] is_most_ext - Whether this phy is the most external, can be passed as NULL 2635 */ 2636 int portmod_port_phy_lane_access_get(int unit, int port, const portmod_access_get_params_t* params, int max_phys, phymod_phy_access_t* access, int* nof_phys, int* is_most_ext); 2637 2638 /*! 2639 * portmod_pm_phy_lane_access_get 2640 * 2641 * @brief Get lane phymod access structure via pm id. can be used for per lane operations 2642 * 2643 * @param [in] unit - unit id 2644 * @param [in] pm_id - port macro id 2645 * @param [in] params - 2646 * @param [in] max_phys - the output array number of elements 2647 * @param [out] access - 2648 * @param [out] nof_phys - number of phy access structutres filled by the function 2649 * @param [out] is_most_ext - Whether this phy is the most external, can be passed as NULL 2650 */ 2651 int portmod_pm_phy_lane_access_get(int unit, int pm_id, const portmod_access_get_params_t* params, int max_phys, phymod_phy_access_t* access, int* nof_phys, int* is_most_ext); 2652 2653 /*! 2654 * portmod_pm_diag_info_get 2655 * 2656 * @brief get PM diag info 2657 * 2658 * @param [in] unit - unit id 2659 * @param [in] pm_id - pm id 2660 * @param [out] diag_info - 2661 */ 2662 int portmod_pm_diag_info_get(int unit, int pm_id, portmod_pm_diag_info_t* diag_info); 2663 2664 /*! 2665 * portmod_port_diag_info_get 2666 * 2667 * @brief get port diag info 2668 * 2669 * @param [in] unit - unit id 2670 * @param [in] port - logical port 2671 * @param [out] diag_info - 2672 */ 2673 int portmod_port_diag_info_get(int unit, int port, portmod_port_diag_info_t* diag_info); 2674 2675 /*! 2676 * portmod_port_duplex_set 2677 * 2678 * @brief Port duplex set/get 2679 * 2680 * @param [in] unit - unit id 2681 * @param [in] port - logical port 2682 * @param [in] enable - 2683 */ 2684 int portmod_port_duplex_set(int unit, int port, int enable); 2685 /*! 2686 * portmod_port_duplex_get 2687 * 2688 * @brief Port duplex set/get 2689 * 2690 * @param [in] unit - unit id 2691 * @param [in] port - logical port 2692 * @param [out] enable - 2693 */ 2694 int portmod_port_duplex_get(int unit, int port, int* enable); 2695 2696 /*! 2697 * portmod_port_phy_reg_read 2698 * 2699 * @brief Port PHY Control register read 2700 * 2701 * @param [in] unit - unit id 2702 * @param [in] port - logical port 2703 * @param [in] lane - logic lane 2704 * @param [in] flags - flags 2705 * @param [in] reg_addr - register address 2706 * @param [out] value - read data 2707 */ 2708 int portmod_port_phy_reg_read(int unit, int port, int lane, int flags, int reg_addr, uint32* value); 2709 2710 /*! 2711 * portmod_port_phy_reg_write 2712 * 2713 * @brief Port PHY Control register write 2714 * 2715 * @param [in] unit - unit id 2716 * @param [in] port - logical port 2717 * @param [in] lane - logic lane 2718 * @param [in] flags - see PORTMOD_PORT_PHY_CONTROL_ 2719 * @param [in] reg_addr - register address 2720 * @param [in] value - 2721 */ 2722 int portmod_port_phy_reg_write(int unit, int port, int lane, int flags, int reg_addr, uint32 value); 2723 2724 /*! 2725 * portmod_port_reset_set 2726 * 2727 * @brief Port Reset set/get 2728 * 2729 * @param [in] unit - unit id 2730 * @param [in] port - logical port 2731 * @param [in] mode - 2732 * @param [in] opcode - 2733 * @param [in] value - 2734 */ 2735 int portmod_port_reset_set(int unit, int port, int mode, int opcode, int value); 2736 /*! 2737 * portmod_port_reset_get 2738 * 2739 * @brief Port Reset set/get 2740 * 2741 * @param [in] unit - unit id 2742 * @param [in] port - logical port 2743 * @param [in] mode - 2744 * @param [in] opcode - 2745 * @param [out] value - 2746 */ 2747 int portmod_port_reset_get(int unit, int port, int mode, int opcode, int* value); 2748 2749 /*! 2750 * portmod_port_adv_remote_get 2751 * 2752 * @brief Port remote Adv get 2753 * 2754 * @param [in] unit - unit id 2755 * @param [in] port - logical port 2756 * @param [out] value - 2757 */ 2758 int portmod_port_adv_remote_get(int unit, int port, int* value); 2759 2760 /*! 2761 * portmod_port_drv_name 2762 * 2763 * @brief Port get drv name 2764 * 2765 * @param [in] unit - unit id 2766 * @param [in] port - logical port 2767 */ 2768 int portmod_port_drv_name(int unit, int port); 2769 2770 /*! 2771 * portmod_port_drv_name_get 2772 * 2773 * @brief Drv Name Get 2774 * 2775 * @param [in] unit - unit id 2776 * @param [in] port - logical port 2777 * @param [out] name - 2778 * @param [in] len - 2779 */ 2780 int portmod_port_drv_name_get(int unit, int port, char* name, int len); 2781 2782 /*! 2783 * portmod_port_fec_enable_set 2784 * 2785 * @brief set/get port fec enable according to local/remote FEC ability 2786 * 2787 * @param [in] unit - unit id 2788 * @param [in] port - logical port 2789 * @param [in] phy_flags - which phy in the chain should be affected. see PORTMOD_INIT_F... 2790 * @param [in] enable - 2791 */ 2792 int portmod_port_fec_enable_set(int unit, int port, uint32 phy_flags, uint32_t enable); 2793 /*! 2794 * portmod_port_fec_enable_get 2795 * 2796 * @brief set/get port fec enable according to local/remote FEC ability 2797 * 2798 * @param [in] unit - unit id 2799 * @param [in] port - logical port 2800 * @param [in] phy_flags - which phy in the chain should be affected. see PORTMOD_INIT_F... 2801 * @param [out] enable - 2802 */ 2803 int portmod_port_fec_enable_get(int unit, int port, uint32 phy_flags, uint32_t* enable); 2804 2805 /*! 2806 * portmod_port_ability_advert_set 2807 * 2808 * @brief get port auto negotiation local ability 2809 * 2810 * @param [in] unit - unit id 2811 * @param [in] port - logical port 2812 * @param [in] phy_flags - which phy in the chain should be affected. see PORTMOD_INIT_F... 2813 * @param [out] ability - 2814 */ 2815 int portmod_port_ability_advert_set(int unit, int port, uint32 phy_flags, portmod_port_ability_t* ability); 2816 /*! 2817 * portmod_port_ability_advert_get 2818 * 2819 * @brief get port auto negotiation local ability 2820 * 2821 * @param [in] unit - unit id 2822 * @param [in] port - logical port 2823 * @param [in] phy_flags - which phy in the chain should be affected. see PORTMOD_INIT_F... 2824 * @param [out] ability - 2825 */ 2826 int portmod_port_ability_advert_get(int unit, int port, uint32 phy_flags, portmod_port_ability_t* ability); 2827 2828 /*! 2829 * portmod_port_ability_remote_get 2830 * 2831 * @brief Port ability remote Adv get 2832 * 2833 * @param [in] unit - unit id 2834 * @param [in] port - logical port 2835 * @param [in] phy_flags - which phy in the chain should be affected. see PORTMOD_INIT_F... 2836 * @param [out] ability - 2837 */ 2838 int portmod_port_ability_remote_get(int unit, int port, uint32 phy_flags, portmod_port_ability_t* ability); 2839 2840 /*! 2841 * portmod_port_frame_spacing_stretch_set 2842 * 2843 * @brief Port Mac Control Spacing Stretch 2844 * 2845 * @param [in] unit - unit id 2846 * @param [in] port - logical port 2847 * @param [in] spacing - 2848 */ 2849 int portmod_port_frame_spacing_stretch_set(int unit, int port, int spacing); 2850 /*! 2851 * portmod_port_frame_spacing_stretch_get 2852 * 2853 * @brief Port Mac Control Spacing Stretch 2854 * 2855 * @param [in] unit - unit id 2856 * @param [in] port - logical port 2857 * @param [in] spacing - 2858 */ 2859 int portmod_port_frame_spacing_stretch_get(int unit, int port, const int* spacing); 2860 2861 /*! 2862 * portmod_port_diag_fifo_status_get 2863 * 2864 * @brief get port timestamps in fifo 2865 * 2866 * @param [in] unit - unit id 2867 * @param [in] port - logical port 2868 * @param [in] diag_info - 2869 */ 2870 int portmod_port_diag_fifo_status_get(int unit, int port, const portmod_fifo_status_t* diag_info); 2871 2872 /*! 2873 * portmod_port_rx_control_set 2874 * 2875 * @brief set/get pass control frames. 2876 * 2877 * @param [in] unit - unit id 2878 * @param [in] port - logical port 2879 * @param [in] rx_ctrl - 2880 */ 2881 int portmod_port_rx_control_set(int unit, int port, const portmod_rx_control_t* rx_ctrl); 2882 /*! 2883 * portmod_port_rx_control_get 2884 * 2885 * @brief set/get pass control frames. 2886 * 2887 * @param [in] unit - unit id 2888 * @param [in] port - logical port 2889 * @param [out] rx_ctrl - 2890 */ 2891 int portmod_port_rx_control_get(int unit, int port, portmod_rx_control_t* rx_ctrl); 2892 2893 /*! 2894 * portmod_port_pfc_config_set 2895 * 2896 * @brief set PFC config registers. 2897 * 2898 * @param [in] unit - unit id 2899 * @param [in] port - logical port 2900 * @param [in] pfc_cfg - 2901 */ 2902 int portmod_port_pfc_config_set(int unit, int port, const portmod_pfc_config_t* pfc_cfg); 2903 /*! 2904 * portmod_port_pfc_config_get 2905 * 2906 * @brief set PFC config registers. 2907 * 2908 * @param [in] unit - unit id 2909 * @param [in] port - logical port 2910 * @param [out] pfc_cfg - 2911 */ 2912 int portmod_port_pfc_config_get(int unit, int port, portmod_pfc_config_t* pfc_cfg); 2913 2914 /*! 2915 * portmod_port_eee_set 2916 * 2917 * @brief set EEE Config. 2918 * 2919 * @param [in] unit - unit id 2920 * @param [in] port - logical port 2921 * @param [in] eee - 2922 */ 2923 int portmod_port_eee_set(int unit, int port, const portmod_eee_t* eee); 2924 /*! 2925 * portmod_port_eee_get 2926 * 2927 * @brief set EEE Config. 2928 * 2929 * @param [in] unit - unit id 2930 * @param [in] port - logical port 2931 * @param [out] eee - 2932 */ 2933 int portmod_port_eee_get(int unit, int port, portmod_eee_t* eee); 2934 2935 /*! 2936 * portmod_port_eee_clock_set 2937 * 2938 * @brief set EEE Config. 2939 * 2940 * @param [in] unit - unit id 2941 * @param [in] port - logical port 2942 * @param [in] eee_clk - 2943 */ 2944 int portmod_port_eee_clock_set(int unit, int port, const portmod_eee_clock_t* eee_clk); 2945 /*! 2946 * portmod_port_eee_clock_get 2947 * 2948 * @brief set EEE Config. 2949 * 2950 * @param [in] unit - unit id 2951 * @param [in] port - logical port 2952 * @param [out] eee_clk - 2953 */ 2954 int portmod_port_eee_clock_get(int unit, int port, portmod_eee_clock_t* eee_clk); 2955 2956 /*! 2957 * portmod_port_vlan_tag_set 2958 * 2959 * @brief set Vlan Inner/Outer tag. 2960 * 2961 * @param [in] unit - unit id 2962 * @param [in] port - logical port 2963 * @param [in] vlan_tag - 2964 */ 2965 int portmod_port_vlan_tag_set(int unit, int port, const portmod_vlan_tag_t* vlan_tag); 2966 /*! 2967 * portmod_port_vlan_tag_get 2968 * 2969 * @brief set Vlan Inner/Outer tag. 2970 * 2971 * @param [in] unit - unit id 2972 * @param [in] port - logical port 2973 * @param [out] vlan_tag - 2974 */ 2975 int portmod_port_vlan_tag_get(int unit, int port, portmod_vlan_tag_t* vlan_tag); 2976 2977 /*! 2978 * portmod_port_to_phyaddr 2979 * 2980 * @brief Get Phy addr for a given port. 2981 * 2982 * @param [in] unit - unit id 2983 * @param [in] port - logical port 2984 */ 2985 int portmod_port_to_phyaddr(int unit, int port); 2986 2987 /*! 2988 * portmod_port_to_phyaddr_int 2989 * 2990 * @brief Get internal Phy addr for a given port. 2991 * 2992 * @param [in] unit - unit id 2993 * @param [in] port - logical port 2994 */ 2995 int portmod_port_to_phyaddr_int(int unit, int port); 2996 2997 /*! 2998 * portmod_port_modid_set 2999 * 3000 * @brief set modid field. 3001 * 3002 * @param [in] unit - unit id 3003 * @param [in] port - logical port 3004 * @param [in] value - 3005 */ 3006 int portmod_port_modid_set(int unit, int port, int value); 3007 3008 /*! 3009 * portmod_port_led_chain_config 3010 * 3011 * @brief set modid field. 3012 * 3013 * @param [in] unit - unit id 3014 * @param [in] port - logical port 3015 * @param [in] value - 3016 */ 3017 int portmod_port_led_chain_config(int unit, int port, int value); 3018 3019 /*! 3020 * portmod_port_clear_rx_lss_status_set 3021 * 3022 * @brief set modid field. 3023 * 3024 * @param [in] unit - unit id 3025 * @param [in] port - logical port 3026 * @param [in] lcl_fault - 3027 * @param [in] rmt_fault - 3028 */ 3029 int portmod_port_clear_rx_lss_status_set(int unit, int port, int lcl_fault, int rmt_fault); 3030 /*! 3031 * portmod_port_clear_rx_lss_status_get 3032 * 3033 * @brief set modid field. 3034 * 3035 * @param [in] unit - unit id 3036 * @param [in] port - logical port 3037 * @param [out] lcl_fault - 3038 * @param [out] rmt_fault - 3039 */ 3040 int portmod_port_clear_rx_lss_status_get(int unit, int port, int* lcl_fault, int* rmt_fault); 3041 3042 #define PORTMOD_PRIMARY_PORT_INVALID (-1) 3043 #define PORTMOD_PORT_OFFSET_INVALID (-1) 3044 #define PORTMOD_CORE_INDEX_INVALID (-1) 3045 #define PORTMOD_LANE_INDEX_INVALID (-1) 3046 #define PORTMOD_XPHY_ID_INVALID (0xFFFF) 3047 #define PORTMOD_MAX_NUM_XPHY_SUPPORTED (512) 3048 #define PORTMOD_XPHY_EXISTING_IDX (-2) 3049 3050 3051 /*! 3052 * @struct portmod_lane_connection_s 3053 * @brief lane connection structture between internal and external phy 3054 */ 3055 typedef struct portmod_lane_connection_s { 3056 int core_index; /**< the connected core in the external phy */ 3057 int lane_index; /**< the connected lane in the external phy */ 3058 } portmod_lane_connection_t; 3059 3060 /* portmod_lane_connection_t initialization and validation */ 3061 int portmod_lane_connection_t_validate(int unit, const portmod_lane_connection_t* portmod_lane_connection); 3062 int portmod_lane_connection_t_init(int unit, portmod_lane_connection_t* portmod_lane_connection); 3063 3064 3065 /*! 3066 * @struct portmod_phy_core_info_s 3067 * @brief Core information structure for external phy db 3068 */ 3069 typedef struct portmod_phy_core_info_s { 3070 phymod_core_access_t core_access; /**< core access */ 3071 } portmod_phy_core_info_t; 3072 3073 /* portmod_phy_core_info_t initialization and validation */ 3074 int portmod_phy_core_info_t_validate(int unit, const portmod_phy_core_info_t* portmod_phy_core_info); 3075 int portmod_phy_core_info_t_init(int unit, portmod_phy_core_info_t* portmod_phy_core_info); 3076 3077 3078 /*! 3079 * @struct portmod_xphy_lane_connection_s 3080 * @brief lane connection structture between internal and external phy 3081 */ 3082 typedef struct portmod_xphy_lane_connection_s { 3083 uint32 xphy_id; /**< connected xphy id */ 3084 int ss_lane_mask; /**< connected xphy system side lane mask */ 3085 int ls_lane_mask; /**< connected xphy line side lane mask */ 3086 int rsvd1; /**< connected xphy line side lane mask */ 3087 int rsvd2; /**< connected xphy line side lane mask */ 3088 } portmod_xphy_lane_connection_t; 3089 3090 /* portmod_xphy_lane_connection_t initialization and validation */ 3091 int portmod_xphy_lane_connection_t_validate(int unit, const portmod_xphy_lane_connection_t* portmod_xphy_lane_connection); 3092 int portmod_xphy_lane_connection_t_init(int unit, portmod_xphy_lane_connection_t* portmod_xphy_lane_connection); 3093 3094 /*! 3095 * portmod_xphy_lane_attach 3096 * 3097 * @brief Attaches an external phy lane to a phy chain 3098 * 3099 * @param [in] unit - unit id 3100 * @param [in] iphy - internal phy index representing the starting point of a phy chain 3101 * @param [in] phyn - indicate the external phy layer in the phy chain 3102 * @param [in] lane_conn - lane connection between internal and external phy 3103 */ 3104 int portmod_xphy_lane_attach(int unit, int iphy, int phyn, const portmod_xphy_lane_connection_t* lane_conn); 3105 3106 /*! 3107 * portmod_xphy_lane_detach 3108 * 3109 * @brief Detaches an external phy lane from a phy chain 3110 * 3111 * @param [in] unit - unit id 3112 * @param [in] iphy - internal phy index representing the starting point of a phy chain 3113 * @param [in] phyn - indicate the external phy layer in the phy chain 3114 */ 3115 int portmod_xphy_lane_detach(int unit, int iphy, int phyn); 3116 3117 3118 3119 /*! 3120 * portmod_xphy_add 3121 * 3122 * @brief Add External Phy to DB. 3123 * 3124 * @param [in] unit - unit id 3125 * @param [in] xphy_addr - External Phy Address. Usually MDIO address. 3126 * @param [in] core_access - External Phy Access information 3127 * @param [out] xphy_idx - Indicate location of new entry. 3128 */ 3129 int portmod_xphy_add(int unit, int xphy_addr, const phymod_core_access_t* core_access, int* xphy_idx); 3130 3131 /*! 3132 * portmod_xphy_delete 3133 * 3134 * @brief Remove External Phy from DB. 3135 * 3136 * @param [in] unit - unit id 3137 * @param [in] xphy_addr - External Phy Address. Usually MDIO address. 3138 */ 3139 int portmod_xphy_delete(int unit, int xphy_addr); 3140 3141 /*! 3142 * portmod_xphy_wb_db_restore 3143 * 3144 * @brief Restore External Phy DB from WB buffer. 3145 * 3146 * @param [in] unit - unit id 3147 * @param [in] xphy_idx - index to the xphy db 3148 * @param [in] xphy_addr - external phy address 3149 * @param [in] core_access - the core_access to be used for external phys restored from WB database. external phy address , external phy type and external phy device_op_mode will be override with values restored from WB DB. 3150 */ 3151 int portmod_xphy_wb_db_restore(int unit, int xphy_idx, int xphy_addr, const phymod_core_access_t* core_access); 3152 3153 3154 3155 3156 /*! 3157 * portmod_ext_phy_lane_attach 3158 * 3159 * @brief Attaches an external phy lane to a phy chain 3160 * 3161 * @param [in] unit - unit id 3162 * @param [in] iphy - internal phy index representing the starting point of a phy chain 3163 * @param [in] phyn - indicate the external phy layer in the phy chain 3164 * @param [in] lane_connection - lane connection between internal and external phy 3165 */ 3166 int portmod_ext_phy_lane_attach(int unit, int iphy, int phyn, const portmod_lane_connection_t* lane_connection); 3167 3168 /*! 3169 * portmod_ext_phy_lane_detach 3170 * 3171 * @brief Detaches an external phy lane from a phy chain 3172 * 3173 * @param [in] unit - unit id 3174 * @param [in] iphy - internal phy index representing the starting point of a phy chain 3175 * @param [in] phyn - indicate the external phy layer in the phy chain 3176 */ 3177 int portmod_ext_phy_lane_detach(int unit, int iphy, int phyn); 3178 3179 3180 3181 /*! 3182 * portmod_port_lag_failover_status_toggle 3183 * 3184 * @brief Toggle Lag Failover Status. 3185 * 3186 * @param [in] unit - unit id 3187 * @param [in] port - logical port 3188 */ 3189 int portmod_port_lag_failover_status_toggle(int unit, int port); 3190 3191 /*! 3192 * portmod_port_lag_failover_loopback_set 3193 * 3194 * @brief Toggle Lag Failover loopback set / get. 3195 * 3196 * @param [in] unit - unit id 3197 * @param [in] port - logical port 3198 * @param [in] value - 3199 */ 3200 int portmod_port_lag_failover_loopback_set(int unit, int port, int value); 3201 /*! 3202 * portmod_port_lag_failover_loopback_get 3203 * 3204 * @brief Toggle Lag Failover loopback set / get. 3205 * 3206 * @param [in] unit - unit id 3207 * @param [in] port - logical port 3208 * @param [out] value - 3209 */ 3210 int portmod_port_lag_failover_loopback_get(int unit, int port, int* value); 3211 3212 /*! 3213 * portmod_port_mode_set 3214 * 3215 * @brief set port mode. 3216 * 3217 * @param [in] unit - unit id 3218 * @param [in] port - logical port 3219 * @param [in] mode - 3220 */ 3221 int portmod_port_mode_set(int unit, int port, const portmod_port_mode_info_t* mode); 3222 /*! 3223 * portmod_port_mode_get 3224 * 3225 * @brief set port mode. 3226 * 3227 * @param [in] unit - unit id 3228 * @param [in] port - logical port 3229 * @param [out] mode - 3230 */ 3231 int portmod_port_mode_get(int unit, int port, portmod_port_mode_info_t* mode); 3232 3233 /*! 3234 * portmod_port_encap_set 3235 * 3236 * @brief set port encap. 3237 * 3238 * @param [in] unit - unit id 3239 * @param [in] port - logical port 3240 * @param [in] flags - 3241 * @param [in] encap - 3242 */ 3243 int portmod_port_encap_set(int unit, int port, int flags, portmod_encap_t encap); 3244 /*! 3245 * portmod_port_encap_get 3246 * 3247 * @brief set port encap. 3248 * 3249 * @param [in] unit - unit id 3250 * @param [in] port - logical port 3251 * @param [out] flags - 3252 * @param [out] encap - 3253 */ 3254 int portmod_port_encap_get(int unit, int port, int* flags, portmod_encap_t* encap); 3255 3256 /*! 3257 * portmod_port_higig_mode_set 3258 * 3259 * @brief set port register higig field. 3260 * 3261 * @param [in] unit - unit id 3262 * @param [in] port - logical port 3263 * @param [in] mode - 3264 */ 3265 int portmod_port_higig_mode_set(int unit, int port, int mode); 3266 /*! 3267 * portmod_port_higig_mode_get 3268 * 3269 * @brief set port register higig field. 3270 * 3271 * @param [in] unit - unit id 3272 * @param [in] port - logical port 3273 * @param [out] mode - 3274 */ 3275 int portmod_port_higig_mode_get(int unit, int port, int* mode); 3276 3277 /*! 3278 * portmod_port_higig2_mode_set 3279 * 3280 * @brief set port register higig field. 3281 * 3282 * @param [in] unit - unit id 3283 * @param [in] port - logical port 3284 * @param [in] mode - 3285 */ 3286 int portmod_port_higig2_mode_set(int unit, int port, int mode); 3287 /*! 3288 * portmod_port_higig2_mode_get 3289 * 3290 * @brief set port register higig field. 3291 * 3292 * @param [in] unit - unit id 3293 * @param [in] port - logical port 3294 * @param [out] mode - 3295 */ 3296 int portmod_port_higig2_mode_get(int unit, int port, int* mode); 3297 3298 /*! 3299 * portmod_port_config_port_type_set 3300 * 3301 * @brief set port register port type field. 3302 * 3303 * @param [in] unit - unit id 3304 * @param [in] port - logical port 3305 * @param [in] type - 3306 */ 3307 int portmod_port_config_port_type_set(int unit, int port, int type); 3308 /*! 3309 * portmod_port_config_port_type_get 3310 * 3311 * @brief set port register port type field. 3312 * 3313 * @param [in] unit - unit id 3314 * @param [in] port - logical port 3315 * @param [out] type - 3316 */ 3317 int portmod_port_config_port_type_get(int unit, int port, int* type); 3318 3319 /*! 3320 * portmod_port_trunk_hwfailover_config_set 3321 * 3322 * @brief set/get hwfailover for trident. 3323 * 3324 * @param [in] unit - unit id 3325 * @param [in] port - logical port 3326 * @param [in] hw_count - 3327 */ 3328 int portmod_port_trunk_hwfailover_config_set(int unit, int port, int hw_count); 3329 /*! 3330 * portmod_port_trunk_hwfailover_config_get 3331 * 3332 * @brief set/get hwfailover for trident. 3333 * 3334 * @param [in] unit - unit id 3335 * @param [in] port - logical port 3336 * @param [out] enable - 3337 */ 3338 int portmod_port_trunk_hwfailover_config_get(int unit, int port, int* enable); 3339 3340 /*! 3341 * portmod_port_trunk_hwfailover_status_get 3342 * 3343 * @brief set/get hwfailover for trident. 3344 * 3345 * @param [in] unit - unit id 3346 * @param [in] port - logical port 3347 * @param [out] loopback - 3348 */ 3349 int portmod_port_trunk_hwfailover_status_get(int unit, int port, int* loopback); 3350 3351 /*! 3352 * portmod_port_diag_ctrl 3353 * 3354 * @brief port diagnostics control. 3355 * 3356 * @param [in] unit - unit id 3357 * @param [in] port - logical port 3358 * @param [in] inst - 3359 * @param [in] op_type - 3360 * @param [in] op_cmd - 3361 * @param [in] arg - 3362 */ 3363 int portmod_port_diag_ctrl(int unit, int port, uint32 inst, int op_type, int op_cmd, const void* arg); 3364 3365 /*! 3366 * portmod_port_ref_clk_get 3367 * 3368 * @brief Get the reference clock value 156 or 125. 3369 * 3370 * @param [in] unit - unit id 3371 * @param [in] port - logical port 3372 * @param [out] ref_clk - 3373 */ 3374 int portmod_port_ref_clk_get(int unit, int port, int* ref_clk); 3375 3376 /*! 3377 * portmod_port_lag_failover_disable 3378 * 3379 * @brief Disable lag failover. 3380 * 3381 * @param [in] unit - unit id 3382 * @param [in] port - logical port 3383 */ 3384 int portmod_port_lag_failover_disable(int unit, int port); 3385 3386 /*! 3387 * portmod_port_lag_remove_failover_lpbk_set 3388 * 3389 * @brief Disable lag failover. 3390 * 3391 * @param [in] unit - unit id 3392 * @param [in] port - logical port 3393 * @param [in] val - 3394 */ 3395 int portmod_port_lag_remove_failover_lpbk_set(int unit, int port, int val); 3396 /*! 3397 * portmod_port_lag_remove_failover_lpbk_get 3398 * 3399 * @brief Disable lag failover. 3400 * 3401 * @param [in] unit - unit id 3402 * @param [in] port - logical port 3403 * @param [out] val - 3404 */ 3405 int portmod_port_lag_remove_failover_lpbk_get(int unit, int port, int* val); 3406 3407 /*! 3408 * portmod_port_cntmaxsize_set 3409 * 3410 * @brief Disable lag failover. 3411 * 3412 * @param [in] unit - unit id 3413 * @param [in] port - logical port 3414 * @param [in] val - 3415 */ 3416 int portmod_port_cntmaxsize_set(int unit, int port, int val); 3417 /*! 3418 * portmod_port_cntmaxsize_get 3419 * 3420 * @brief Disable lag failover. 3421 * 3422 * @param [in] unit - unit id 3423 * @param [in] port - logical port 3424 * @param [out] val - 3425 */ 3426 int portmod_port_cntmaxsize_get(int unit, int port, int* val); 3427 3428 /*! 3429 * portmod_port_multi_get 3430 * 3431 * @brief Read multiple bytes get. 3432 * 3433 * @param [in] unit - unit id 3434 * @param [in] port - logical port 3435 * @param [inout] multi_get - 3436 */ 3437 int portmod_port_multi_get(int unit, int port, portmod_multi_get_t* multi_get); 3438 3439 /*! 3440 * portmod_port_drain_cell_get 3441 * 3442 * @brief Get Info needed to restore after drain cells. 3443 * 3444 * @param [in] unit - unit id 3445 * @param [in] port - logical port 3446 * @param [out] drain_cells - 3447 */ 3448 int portmod_port_drain_cell_get(int unit, int port, portmod_drain_cells_t* drain_cells); 3449 3450 /*! 3451 * portmod_port_drain_cell_stop 3452 * 3453 * @brief Restore informaation after drain cells. 3454 * 3455 * @param [in] unit - unit id 3456 * @param [in] port - logical port 3457 * @param [in] drain_cells - 3458 */ 3459 int portmod_port_drain_cell_stop(int unit, int port, const portmod_drain_cells_t* drain_cells); 3460 3461 /*! 3462 * portmod_port_drain_cell_start 3463 * 3464 * @brief Restore informaation after drain cells. 3465 * 3466 * @param [in] unit - unit id 3467 * @param [in] port - logical port 3468 */ 3469 int portmod_port_drain_cell_start(int unit, int port); 3470 3471 /*! 3472 * portmod_port_drain_cells_rx_enable 3473 * 3474 * 3475 * @param [in] unit - unit id 3476 * @param [in] port - logical port 3477 * @param [out] rx_en - 3478 */ 3479 int portmod_port_drain_cells_rx_enable(int unit, int port, int rx_en); 3480 3481 /*! 3482 * portmod_port_egress_queue_drain_rx_en 3483 * 3484 * 3485 * @param [in] unit - unit id 3486 * @param [in] port - logical port 3487 * @param [out] rx_en - 3488 */ 3489 int portmod_port_egress_queue_drain_rx_en(int unit, int port, int rx_en); 3490 3491 /*! 3492 * portmod_port_mac_ctrl_set 3493 * 3494 * 3495 * @param [in] unit - unit id 3496 * @param [in] port - logical port 3497 * @param [out] ctrl - 3498 */ 3499 int portmod_port_mac_ctrl_set(int unit, int port, uint64 ctrl); 3500 3501 /*! 3502 * portmod_port_txfifo_cell_cnt_get 3503 * 3504 * 3505 * @param [in] unit - unit id 3506 * @param [in] port - logical port 3507 * @param [out] cnt - 3508 */ 3509 int portmod_port_txfifo_cell_cnt_get(int unit, int port, uint32* cnt); 3510 3511 /*! 3512 * portmod_port_egress_queue_drain_get 3513 * 3514 * 3515 * @param [in] unit - unit id 3516 * @param [in] port - logical port 3517 * @param [out] ctrl - 3518 * @param [out] rxen - 3519 */ 3520 int portmod_port_egress_queue_drain_get(int unit, int port, uint64* ctrl, int* rxen); 3521 3522 /*! 3523 * portmod_port_mac_reset_set 3524 * 3525 * @brief Set/get port mac reset 3526 * 3527 * @param [in] unit - unit id 3528 * @param [in] port - logical port 3529 * @param [in] val - 3530 */ 3531 int portmod_port_mac_reset_set(int unit, int port, int val); 3532 /*! 3533 * portmod_port_mac_reset_get 3534 * 3535 * @brief Set/get port mac reset 3536 * 3537 * @param [in] unit - unit id 3538 * @param [in] port - logical port 3539 * @param [out] val - 3540 */ 3541 int portmod_port_mac_reset_get(int unit, int port, int* val); 3542 3543 /*! 3544 * portmod_port_soft_reset_toggle 3545 * 3546 * 3547 * @param [in] unit - unit id 3548 * @param [in] port - logical port 3549 * @param [out] idx - 3550 */ 3551 int portmod_port_soft_reset_toggle(int unit, int port, int idx); 3552 3553 /*! 3554 * portmod_port_mac_reset_check 3555 * 3556 * @brief Check if MAC needs to be reset. 3557 * 3558 * @param [in] unit - unit id 3559 * @param [in] port - logical port 3560 * @param [out] enable - Check for enable or disable MAC 3561 * @param [out] reset - TRUE if MAC needs to be reset 3562 */ 3563 int portmod_port_mac_reset_check(int unit, int port, int enable, int* reset); 3564 3565 /*! 3566 * portmod_port_core_num_get 3567 * 3568 * 3569 * @param [in] unit - unit id 3570 * @param [in] port - logical port 3571 * @param [out] core_num - 3572 */ 3573 int portmod_port_core_num_get(int unit, int port, int* core_num); 3574 3575 3576 /*! 3577 * @struct portmod_port_higig_e2ecc_hdr_s 3578 * @brief PM E2ECC header . 3579 */ 3580 typedef struct portmod_port_higig_e2ecc_hdr_s { 3581 uint32 words[8]; 3582 } portmod_port_higig_e2ecc_hdr_t; 3583 3584 /* portmod_port_higig_e2ecc_hdr_t initialization and validation */ 3585 int portmod_port_higig_e2ecc_hdr_t_validate(int unit, const portmod_port_higig_e2ecc_hdr_t* portmod_port_higig_e2ecc_hdr); 3586 int portmod_port_higig_e2ecc_hdr_t_init(int unit, portmod_port_higig_e2ecc_hdr_t* portmod_port_higig_e2ecc_hdr); 3587 3588 /*! 3589 * portmod_port_e2ecc_hdr_set 3590 * 3591 * 3592 * @param [in] unit - unit id 3593 * @param [in] port - logical port 3594 * @param [in] e2ecc_hdr - 3595 */ 3596 int portmod_port_e2ecc_hdr_set(int unit, int port, const portmod_port_higig_e2ecc_hdr_t* e2ecc_hdr); 3597 /*! 3598 * portmod_port_e2ecc_hdr_get 3599 * 3600 * 3601 * @param [in] unit - unit id 3602 * @param [in] port - logical port 3603 * @param [out] e2ecc_hdr - 3604 */ 3605 int portmod_port_e2ecc_hdr_get(int unit, int port, portmod_port_higig_e2ecc_hdr_t* e2ecc_hdr); 3606 3607 /*! 3608 * portmod_port_e2e_enable_set 3609 * 3610 * 3611 * @param [in] unit - unit id 3612 * @param [in] port - logical port 3613 * @param [in] enable - 3614 */ 3615 int portmod_port_e2e_enable_set(int unit, int port, int enable); 3616 /*! 3617 * portmod_port_e2e_enable_get 3618 * 3619 * 3620 * @param [in] unit - unit id 3621 * @param [in] port - logical port 3622 * @param [out] enable - 3623 */ 3624 int portmod_port_e2e_enable_get(int unit, int port, int* enable); 3625 3626 /*! 3627 * portmod_port_fallback_lane_get 3628 * 3629 * 3630 * @param [in] unit - unit id 3631 * @param [in] port - logical port 3632 * @param [out] fallback_lane - 3633 */ 3634 int portmod_port_fallback_lane_get(int unit, int port, int* fallback_lane); 3635 3636 /*! 3637 * portmod_port_speed_get 3638 * 3639 * @brief get the speed for the specified port 3640 * 3641 * @param [in] unit - unit id 3642 * @param [in] port - logical port 3643 * @param [out] speed - 3644 */ 3645 int portmod_port_speed_get(int unit, int port, int* speed); 3646 3647 /*! 3648 * portmod_port_tsc_refclock_set 3649 * 3650 * @brief TSC refere clock input and output set/get 3651 * 3652 * @param [in] unit - unit id 3653 * @param [in] port - logical port 3654 * @param [in] ref_in - Selects between pad and LCREF as source of refclk into this TSC PLL. 0 -- pad, 1 -- LCREF 3655 * @param [in] ref_out - Enables LCREFOUT to be driven by this TSC. 0 -- disable, 1 -- enable 3656 */ 3657 int portmod_port_tsc_refclock_set(int unit, int port, int ref_in, int ref_out); 3658 /*! 3659 * portmod_port_tsc_refclock_get 3660 * 3661 * @brief TSC refere clock input and output set/get 3662 * 3663 * @param [in] unit - unit id 3664 * @param [in] port - logical port 3665 * @param [out] ref_in - 3666 * @param [out] ref_out - 3667 */ 3668 int portmod_port_tsc_refclock_get(int unit, int port, int* ref_in, int* ref_out); 3669 3670 /*! 3671 * portmod_port_discard_set 3672 * 3673 * @brief Port discard set 3674 * 3675 * @param [in] unit - unit id 3676 * @param [in] port - logical port 3677 * @param [in] discard - Set Discardf and EP_Discard 3678 */ 3679 int portmod_port_discard_set(int unit, int port, int discard); 3680 3681 /*! 3682 * portmod_port_soft_reset_set 3683 * 3684 * @brief Port soft reset set set 3685 * 3686 * @param [in] unit - unit id 3687 * @param [in] port - logical port 3688 * @param [in] idx - index 3689 * @param [in] val - value 0/1 3690 * @param [in] flags - 3691 */ 3692 int portmod_port_soft_reset_set(int unit, int port, int idx, int val, int flags); 3693 3694 /*! 3695 * portmod_port_tx_down 3696 * 3697 * @brief Port tx_en=0 and softreset mac 3698 * 3699 * @param [in] unit - unit id 3700 * @param [in] port - logical port 3701 */ 3702 int portmod_port_tx_down(int unit, int port); 3703 3704 /*! 3705 * portmod_port_logical_lane_order_set 3706 * 3707 * @brief "logical lane order" 3708 * 3709 * @param [in] unit - unit id 3710 * @param [in] port - logical port 3711 * @param [in] lane_order - ILKN Logical lane order. For pmOsILKN_50G, lane_order[N] is represent for the Nth lane; otherwise it is represent for logical lane N 3712 * @param [in] lane_order_size - Nof lanes of the ILKN port 3713 */ 3714 int portmod_port_logical_lane_order_set(int unit, int port, const int* lane_order, int lane_order_size); 3715 /*! 3716 * portmod_port_logical_lane_order_get 3717 * 3718 * @brief "logical lane order" 3719 * 3720 * @param [in] unit - unit id 3721 * @param [in] port - logical port 3722 * @param [in] lane_order_max_size - Max lane numbers when get ILKN lane order 3723 * @param [out] lane_order - Logical lane order, lane_order[N] is represent for the Nth lane 3724 * @param [out] lane_order_actual_size - The actual lane numbers when get ILKN lane order 3725 */ 3726 int portmod_port_logical_lane_order_get(int unit, int port, int lane_order_max_size, int* lane_order, int* lane_order_actual_size); 3727 3728 /*! 3729 * portmod_port_pgw_reconfig 3730 * 3731 * @brief reconfig pgw. 3732 * 3733 * @param [in] unit - unit id 3734 * @param [in] port - logical port 3735 * @param [in] pmode - 3736 * @param [in] phy_port - 3737 * @param [in] flags - 3738 */ 3739 int portmod_port_pgw_reconfig(int unit, int port, const portmod_port_mode_info_t* pmode, int phy_port, int flags); 3740 3741 /*! 3742 * portmod_port_notify 3743 * 3744 * @brief Routine to notify internal phy of external phy link state. 3745 * 3746 * @param [in] unit - unit id 3747 * @param [in] port - logical port 3748 * @param [in] link - link status 3749 */ 3750 int portmod_port_notify(int unit, int port, int link); 3751 3752 typedef soc_port_phy_timesync_config_t portmod_phy_timesync_config_t; 3753 3754 typedef _shr_port_control_phy_timesync_t portmod_port_control_phy_timesync_t; 3755 3756 /*! 3757 * portmod_port_control_phy_timesync_set 3758 * 3759 * @brief "port control phy timesync config set/get" 3760 * 3761 * @param [in] unit - unit id 3762 * @param [in] port - logical port 3763 * @param [in] config - 3764 * @param [in] value - 3765 */ 3766 int portmod_port_control_phy_timesync_set(int unit, int port, portmod_port_control_phy_timesync_t config, uint64 value); 3767 /*! 3768 * portmod_port_control_phy_timesync_get 3769 * 3770 * @brief "port control phy timesync config set/get" 3771 * 3772 * @param [in] unit - unit id 3773 * @param [in] port - logical port 3774 * @param [in] config - 3775 * @param [out] value - 3776 */ 3777 int portmod_port_control_phy_timesync_get(int unit, int port, portmod_port_control_phy_timesync_t config, uint64* value); 3778 3779 /*! 3780 * portmod_port_timesync_config_set 3781 * 3782 * @brief "port timesync config set/get" 3783 * 3784 * @param [in] unit - unit id 3785 * @param [in] port - logical port 3786 * @param [in] config - 3787 */ 3788 int portmod_port_timesync_config_set(int unit, int port, const portmod_phy_timesync_config_t* config); 3789 /*! 3790 * portmod_port_timesync_config_get 3791 * 3792 * @brief "port timesync config set/get" 3793 * 3794 * @param [in] unit - unit id 3795 * @param [in] port - logical port 3796 * @param [out] config - 3797 */ 3798 int portmod_port_timesync_config_get(int unit, int port, portmod_phy_timesync_config_t* config); 3799 3800 /*! 3801 * portmod_port_timesync_enable_set 3802 * 3803 * @brief "port timesync enable set/get" 3804 * 3805 * @param [in] unit - unit id 3806 * @param [in] port - logical port 3807 * @param [in] enable - 3808 */ 3809 int portmod_port_timesync_enable_set(int unit, int port, uint32 enable); 3810 /*! 3811 * portmod_port_timesync_enable_get 3812 * 3813 * @brief "port timesync enable set/get" 3814 * 3815 * @param [in] unit - unit id 3816 * @param [in] port - logical port 3817 * @param [out] enable - 3818 */ 3819 int portmod_port_timesync_enable_get(int unit, int port, uint32* enable); 3820 3821 /*! 3822 * portmod_port_timesync_nco_addend_set 3823 * 3824 * @brief "port timesync nco addend set/get" 3825 * 3826 * @param [in] unit - unit id 3827 * @param [in] port - logical port 3828 * @param [in] freq_step - NCO Frequency Step. 3829 */ 3830 int portmod_port_timesync_nco_addend_set(int unit, int port, uint32 freq_step); 3831 /*! 3832 * portmod_port_timesync_nco_addend_get 3833 * 3834 * @brief "port timesync nco addend set/get" 3835 * 3836 * @param [in] unit - unit id 3837 * @param [in] port - logical port 3838 * @param [out] freq_step - NCO Frequency Step. 3839 */ 3840 int portmod_port_timesync_nco_addend_get(int unit, int port, uint32* freq_step); 3841 3842 typedef phymod_timesync_framesync_t portmod_timesync_framesync_t; 3843 3844 /*! 3845 * portmod_port_timesync_framesync_mode_set 3846 * 3847 * @brief "port timesync framesync info set/get" 3848 * 3849 * @param [in] unit - unit id 3850 * @param [in] port - logical port 3851 * @param [in] framesync - Framesync Info. 3852 */ 3853 int portmod_port_timesync_framesync_mode_set(int unit, int port, const portmod_timesync_framesync_t* framesync); 3854 /*! 3855 * portmod_port_timesync_framesync_mode_get 3856 * 3857 * @brief "port timesync framesync info set/get" 3858 * 3859 * @param [in] unit - unit id 3860 * @param [in] port - logical port 3861 * @param [out] framesync - Framesync Info. 3862 */ 3863 int portmod_port_timesync_framesync_mode_get(int unit, int port, portmod_timesync_framesync_t* framesync); 3864 3865 /*! 3866 * portmod_port_timesync_local_time_set 3867 * 3868 * @brief "port timesync local time set/get" 3869 * 3870 * @param [in] unit - unit id 3871 * @param [in] port - logical port 3872 * @param [in] local_time - Local Time. 3873 */ 3874 int portmod_port_timesync_local_time_set(int unit, int port, uint64 local_time); 3875 /*! 3876 * portmod_port_timesync_local_time_get 3877 * 3878 * @brief "port timesync local time set/get" 3879 * 3880 * @param [in] unit - unit id 3881 * @param [in] port - logical port 3882 * @param [out] local_time - Local Time. 3883 */ 3884 int portmod_port_timesync_local_time_get(int unit, int port, uint64* local_time); 3885 3886 /*! 3887 * portmod_port_timesync_load_ctrl_set 3888 * 3889 * @brief "port timesync framesync info set/get" 3890 * 3891 * @param [in] unit - unit id 3892 * @param [in] port - logical port 3893 * @param [in] load_once - Load Once. 3894 * @param [in] load_always - Load Always. 3895 */ 3896 int portmod_port_timesync_load_ctrl_set(int unit, int port, uint32 load_once, uint32 load_always); 3897 /*! 3898 * portmod_port_timesync_load_ctrl_get 3899 * 3900 * @brief "port timesync framesync info set/get" 3901 * 3902 * @param [in] unit - unit id 3903 * @param [in] port - logical port 3904 * @param [out] load_once - Load Once. 3905 * @param [out] load_always - Load Always. 3906 */ 3907 int portmod_port_timesync_load_ctrl_get(int unit, int port, uint32* load_once, uint32* load_always); 3908 3909 /*! 3910 * portmod_port_timesync_tx_timestamp_offset_set 3911 * 3912 * @brief "port timesync tx timestamp offset set/get" 3913 * 3914 * @param [in] unit - unit id 3915 * @param [in] port - logical port 3916 * @param [in] ts_offset - TX AFE Delay in ns. 3917 */ 3918 int portmod_port_timesync_tx_timestamp_offset_set(int unit, int port, uint32 ts_offset); 3919 /*! 3920 * portmod_port_timesync_tx_timestamp_offset_get 3921 * 3922 * @brief "port timesync tx timestamp offset set/get" 3923 * 3924 * @param [in] unit - unit id 3925 * @param [in] port - logical port 3926 * @param [out] ts_offset - TX AFE Delay in ns. 3927 */ 3928 int portmod_port_timesync_tx_timestamp_offset_get(int unit, int port, uint32* ts_offset); 3929 3930 /*! 3931 * portmod_port_timesync_rx_timestamp_offset_set 3932 * 3933 * @brief "port timesync rx timestamp offset set/get" 3934 * 3935 * @param [in] unit - unit id 3936 * @param [in] port - logical port 3937 * @param [in] ts_offset - RX AFE Delay in ns. 3938 */ 3939 int portmod_port_timesync_rx_timestamp_offset_set(int unit, int port, uint32 ts_offset); 3940 /*! 3941 * portmod_port_timesync_rx_timestamp_offset_get 3942 * 3943 * @brief "port timesync rx timestamp offset set/get" 3944 * 3945 * @param [in] unit - unit id 3946 * @param [in] port - logical port 3947 * @param [out] ts_offset - RX AFE Delay in ns. 3948 */ 3949 int portmod_port_timesync_rx_timestamp_offset_get(int unit, int port, uint32* ts_offset); 3950 3951 /*! 3952 * portmod_port_timestamp_adjust_set 3953 * 3954 * @brief "port timestamp adjust set/get" 3955 * 3956 * @param [in] unit - unit id 3957 * @param [in] port - logical port 3958 * @param [in] ts_adjust - TSTS,OSTS adjust. 3959 */ 3960 int portmod_port_timestamp_adjust_set(int unit, int port, const soc_port_timestamp_adjust_t* ts_adjust); 3961 /*! 3962 * portmod_port_timestamp_adjust_get 3963 * 3964 * @brief "port timestamp adjust set/get" 3965 * 3966 * @param [in] unit - unit id 3967 * @param [in] port - logical port 3968 * @param [out] ts_adjust - TSTS,OSTS adjust. 3969 */ 3970 int portmod_port_timestamp_adjust_get(int unit, int port, soc_port_timestamp_adjust_t* ts_adjust); 3971 3972 /*! 3973 * portmod_port_phy_intr_enable_set 3974 * 3975 * @brief "port timesync interrupt mask set/get" 3976 * 3977 * @param [in] unit - unit id 3978 * @param [in] port - logical port 3979 * @param [in] intr_enable - Interrupt Eanble. 3980 */ 3981 int portmod_port_phy_intr_enable_set(int unit, int port, uint32 intr_enable); 3982 /*! 3983 * portmod_port_phy_intr_enable_get 3984 * 3985 * @brief "port timesync interrupt mask set/get" 3986 * 3987 * @param [in] unit - unit id 3988 * @param [in] port - logical port 3989 * @param [out] intr_enable - Interrupt Eanble. 3990 */ 3991 int portmod_port_phy_intr_enable_get(int unit, int port, uint32* intr_enable); 3992 3993 /*! 3994 * portmod_port_phy_intr_status_get 3995 * 3996 * @brief "port phy interrupt status get" 3997 * 3998 * @param [in] unit - unit id 3999 * @param [in] port - logical port 4000 * @param [out] intr_status - Interrupt Status. 4001 */ 4002 int portmod_port_phy_intr_status_get(int unit, int port, uint32* intr_status); 4003 4004 /*! 4005 * portmod_port_phy_intr_status_clear 4006 * 4007 * @brief "port phy interrupt status clear" 4008 * 4009 * @param [in] unit - unit id 4010 * @param [in] port - logical port 4011 */ 4012 int portmod_port_phy_intr_status_clear(int unit, int port); 4013 4014 /*! 4015 * portmod_port_phy_timesync_do_sync 4016 * 4017 * @brief "port timesync force frame sync." 4018 * 4019 * @param [in] unit - unit id 4020 * @param [in] port - logical port 4021 */ 4022 int portmod_port_phy_timesync_do_sync(int unit, int port); 4023 4024 /*! 4025 * portmod_port_timesync_capture_timestamp_get 4026 * 4027 * @brief "port timesync capture timestamp get" 4028 * 4029 * @param [in] unit - unit id 4030 * @param [in] port - logical port 4031 * @param [out] cap_ts - Capture Timestamp. 4032 */ 4033 int portmod_port_timesync_capture_timestamp_get(int unit, int port, uint64* cap_ts); 4034 4035 /*! 4036 * portmod_port_timesync_heartbeat_timestamp_get 4037 * 4038 * @brief "port timesync heartbeat timestamp get" 4039 * 4040 * @param [in] unit - unit id 4041 * @param [in] port - logical port 4042 * @param [out] hb_ts - Heartbeat Timestamp. 4043 */ 4044 int portmod_port_timesync_heartbeat_timestamp_get(int unit, int port, uint64* hb_ts); 4045 4046 typedef phymod_edc_config_t portmod_edc_config_t; 4047 4048 /*! 4049 * portmod_port_edc_config_set 4050 * 4051 * @brief "port timesync tx timestamp offset set/get" 4052 * 4053 * @param [in] unit - unit id 4054 * @param [in] port - logical port 4055 * @param [in] config - Electronic Dispersion Compensation config. 4056 */ 4057 int portmod_port_edc_config_set(int unit, int port, const portmod_edc_config_t* config); 4058 /*! 4059 * portmod_port_edc_config_get 4060 * 4061 * @brief "port timesync tx timestamp offset set/get" 4062 * 4063 * @param [in] unit - unit id 4064 * @param [in] port - logical port 4065 * @param [out] config - Electronic Dispersion Compensation config.. 4066 */ 4067 int portmod_port_edc_config_get(int unit, int port, portmod_edc_config_t* config); 4068 4069 /*! 4070 * portmod_port_interrupt_enable_set 4071 * 4072 * @brief set/get interrupt enable value. 4073 * 4074 * @param [in] unit - unit id 4075 * @param [in] port - logical port 4076 * @param [in] intr_type - portmod_intr_type_t enum 4077 * @param [out] val - value write 4078 */ 4079 int portmod_port_interrupt_enable_set(int unit, int port, int intr_type, uint32 val); 4080 /*! 4081 * portmod_port_interrupt_enable_get 4082 * 4083 * @brief set/get interrupt enable value. 4084 * 4085 * @param [in] unit - unit id 4086 * @param [in] port - logical port 4087 * @param [in] intr_type - portmod_intr_type_t enum 4088 * @param [out] val - value read 4089 */ 4090 int portmod_port_interrupt_enable_get(int unit, int port, int intr_type, uint32* val); 4091 4092 /*! 4093 * portmod_port_interrupt_get 4094 * 4095 * @brief get interrupt status value. 4096 * 4097 * @param [in] unit - unit id 4098 * @param [in] port - logical port 4099 * @param [in] intr_type - portmod_intr_type_t enum 4100 * @param [out] val - value read 4101 */ 4102 int portmod_port_interrupt_get(int unit, int port, int intr_type, uint32* val); 4103 4104 /*! 4105 * portmod_port_interrupts_get 4106 * 4107 * @brief get interrupt value array. 4108 * 4109 * @param [in] unit - unit id 4110 * @param [in] port - logical port 4111 * @param [in] arr_max_size - maximum size of output array 4112 * @param [out] intr_arr - array of intr status 4113 * @param [out] size - actual siz of output array 4114 */ 4115 int portmod_port_interrupts_get(int unit, int port, int arr_max_size, uint32* intr_arr, uint32* size); 4116 4117 #define PORTMOD_PORT_REG_ACCESS_DEFAULT (0) 4118 #define PORTMOD_PORT_REG_ACCESS_DIRECT (1) 4119 4120 #define PORTMOD_PORT_PGW_CONFIGURE (0) 4121 #define PORTMOD_PORT_PGW_MAC_RESET (1) 4122 #define PORTMOD_PORT_PGW_POWER_SAVE (2) 4123 #define PORTMOD_PORT_PGW_MAC_UNRESET (3) 4124 4125 4126 /*! 4127 * @enum portmod_stat_val_e 4128 * @brief portmod statistics 4129 */ 4130 typedef enum portmod_stat_val_e { 4131 portmodIfInOctets = 0, 4132 portmodIfInUcastPkts = 1, 4133 portmodIfInNUcastPkts = 2, 4134 portmodIfInBroadcastPkts = 3, 4135 portmodIfInMulticastPkts = 4, 4136 portmodIfInDiscards = 5, 4137 portmodIfInErrors = 6, 4138 portmodIfOutOctets = 7, 4139 portmodIfOutUcastPkts = 8, 4140 portmodIfOutNUcastPkts = 9, 4141 portmodIfOutBroadcastPkts = 10, 4142 portmodIfOutMulticastPkts = 11, 4143 portmodIfOutDiscards = 12, 4144 portmodIfOutErrors = 13, 4145 portmodIpInReceives = 14, 4146 portmodIpInHdrErrors = 15, 4147 portmodIpForwDatagrams = 16, 4148 portmodIpInDiscards = 17, 4149 portmodDot1dBasePortMtuExceededDiscards = 18, 4150 portmodDot1dTpPortInFrames = 19, 4151 portmodDot1dTpPortOutFrames = 20, 4152 portmodDot1dPortInDiscards = 21, 4153 portmodEtherStatsDropEvents = 22, 4154 portmodEtherStatsOctets = 23, 4155 portmodEtherStatsPkts = 24, 4156 portmodEtherStatsBroadcastPkts = 25, 4157 portmodEtherStatsMulticastPkts = 26, 4158 portmodEtherStatsCRCAlignErrors = 27, 4159 portmodEtherStatsUndersizePkts = 28, 4160 portmodEtherStatsOversizePkts = 29, 4161 portmodEtherRxOversizePkts = 30, 4162 portmodEtherTxOversizePkts = 31, 4163 portmodEtherStatsFragments = 32, 4164 portmodEtherStatsJabbers = 33, 4165 portmodEtherStatsPkts64Octets = 34, 4166 portmodEtherStatsPkts65to127Octets = 35, 4167 portmodEtherStatsPkts128to255Octets = 36, 4168 portmodEtherStatsPkts256to511Octets = 37, 4169 portmodEtherStatsPkts512to1023Octets = 38, 4170 portmodEtherStatsPkts1024to1518Octets = 39, 4171 portmodBcmEtherStatsPkts1519to1522Octets = 40, 4172 portmodBcmEtherStatsPkts1522to2047Octets = 41, 4173 portmodBcmEtherStatsPkts2048to4095Octets = 42, 4174 portmodBcmEtherStatsPkts4095to9216Octets = 43, 4175 portmodBcmEtherStatsPkts9217to16383Octets = 44, 4176 portmodBcmReceivedPkts64Octets = 45, 4177 portmodBcmReceivedPkts65to127Octets = 46, 4178 portmodBcmReceivedPkts128to255Octets = 47, 4179 portmodBcmReceivedPkts256to511Octets = 48, 4180 portmodBcmReceivedPkts512to1023Octets = 49, 4181 portmodBcmReceivedPkts1024to1518Octets = 50, 4182 portmodBcmReceivedPkts1519to2047Octets = 51, 4183 portmodBcmReceivedPkts2048to4095Octets = 52, 4184 portmodBcmReceivedPkts4095to9216Octets = 53, 4185 portmodBcmReceivedPkts9217to16383Octets = 54, 4186 portmodBcmTransmittedPkts64Octets = 55, 4187 portmodBcmTransmittedPkts65to127Octets = 56, 4188 portmodBcmTransmittedPkts128to255Octets = 57, 4189 portmodBcmTransmittedPkts256to511Octets = 58, 4190 portmodBcmTransmittedPkts512to1023Octets = 59, 4191 portmodBcmTransmittedPkts1024to1518Octets = 60, 4192 portmodBcmTransmittedPkts1519to2047Octets = 61, 4193 portmodBcmTransmittedPkts2048to4095Octets = 62, 4194 portmodBcmTransmittedPkts4095to9216Octets = 63, 4195 portmodBcmTransmittedPkts9217to16383Octets = 64, 4196 portmodEtherStatsTXNoErrors = 65, 4197 portmodEtherStatsRXNoErrors = 66, 4198 portmodDot3StatsFCSErrors = 67, 4199 portmodDot3StatsInternalMacTransmitErrors = 68, 4200 portmodDot3StatsFrameTooLongs = 69, 4201 portmodDot3StatsSymbolErrors = 70, 4202 portmodDot3ControlInUnknownOpcodes = 71, 4203 portmodDot3InPauseFrames = 72, 4204 portmodDot3OutPauseFrames = 73, 4205 portmodIfHCInOctets = 74, 4206 portmodIfHCInUcastPkts = 75, 4207 portmodIfHCInMulticastPkts = 76, 4208 portmodIfHCInBroadcastPkts = 77, 4209 portmodIfHCOutOctets = 78, 4210 portmodIfHCOutUcastPkts = 79, 4211 portmodIfHCOutMulticastPkts = 80, 4212 portmodIfHCOutBroadcastPckts = 81, 4213 portmodIpv6IfStatsInReceives = 82, 4214 portmodIpv6IfStatsInHdrErrors = 83, 4215 portmodIpv6IfStatsInAddrErrors = 84, 4216 portmodIpv6IfStatsInDiscards = 85, 4217 portmodIpv6IfStatsOutForwDatagrams = 86, 4218 portmodIpv6IfStatsOutDiscards = 87, 4219 portmodIpv6IfStatsInMcastPkts = 88, 4220 portmodIpv6IfStatsOutMcastPkts = 89, 4221 portmodIeee8021PfcRequests = 90, 4222 portmodIeee8021PfcIndications = 91, 4223 portmodBcmIPMCBridgedPckts = 92, 4224 portmodBcmIPMCRoutedPckts = 93, 4225 portmodBcmIPMCInDroppedPckts = 94, 4226 portmodBcmIPMCOutDroppedPckts = 95, 4227 portmodBcmRxVlanTagFrame = 96, 4228 portmodBcmRxDoubleVlanTagFrame = 97, 4229 portmodBcmTxVlanTagFrame = 98, 4230 portmodBcmTxDoubleVlanTagFrame = 99, 4231 portmodBcmRxPFCControlFrame = 100, 4232 portmodBcmTxPFCControlFrame = 101, 4233 portmodBcmRxPFCFramePriority0 = 102, 4234 portmodBcmRxPFCFramePriority1 = 103, 4235 portmodBcmRxPFCFramePriority2 = 104, 4236 portmodBcmRxPFCFramePriority3 = 105, 4237 portmodBcmRxPFCFramePriority4 = 106, 4238 portmodBcmRxPFCFramePriority5 = 107, 4239 portmodBcmRxPFCFramePriority6 = 108, 4240 portmodBcmRxPFCFramePriority7 = 109, 4241 portmodBcmTxPFCFramePriority0 = 110, 4242 portmodBcmTxPFCFramePriority1 = 111, 4243 portmodBcmTxPFCFramePriority2 = 112, 4244 portmodBcmTxPFCFramePriority3 = 113, 4245 portmodBcmTxPFCFramePriority4 = 114, 4246 portmodBcmTxPFCFramePriority5 = 115, 4247 portmodBcmTxPFCFramePriority6 = 116, 4248 portmodBcmTxPFCFramePriority7 = 117, 4249 portmodCount 4250 } portmod_stat_val_t; 4251 4252 #ifdef PORTMOD_DIAG 4253 extern enum_mapping_t portmod_stat_val_t_mapping[]; 4254 #endif /*PORTMOD_DIAG*/ 4255 4256 /* portmod_stat_val_t validation */ 4257 int portmod_stat_val_t_validate(int unit, portmod_stat_val_t portmod_stat_val); 4258 /*! 4259 * portmod_port_stats_read 4260 * 4261 * @brief portmod stats read 4262 * 4263 * @param [in] unit - unit id 4264 * @param [in] port - logical port 4265 * @param [in] cntr_type - counter type 4266 * @param [out] value - read value 4267 */ 4268 int portmod_port_stats_read(int unit, int port, portmod_stat_val_t cntr_type, uint64* value); 4269 4270 /*! 4271 * portmod_port_stats_clear 4272 * 4273 * @brief portmod stats clear 4274 * 4275 * @param [in] unit - unit id 4276 * @param [in] port - logical port 4277 * @param [in] cntr_type - counter type 4278 */ 4279 int portmod_port_stats_clear(int unit, int port, portmod_stat_val_t cntr_type); 4280 4281 /*! 4282 * portmod_port_check_legacy_phy 4283 * 4284 * @brief portmod check if external phy is legacy 4285 * 4286 * @param [in] unit - unit id 4287 * @param [in] port - logical port 4288 * @param [out] legacy_phy - check if phy is legacy 4289 */ 4290 int portmod_port_check_legacy_phy(int unit, int port, int* legacy_phy); 4291 4292 /*! 4293 * portmod_port_failover_mode_set 4294 * 4295 * @brief portmod phy failover mode 4296 * 4297 * @param [in] unit - unit id 4298 * @param [in] port - logical port 4299 * @param [in] failover - Failover Mode set 4300 */ 4301 int portmod_port_failover_mode_set(int unit, int port, phymod_failover_mode_t failover); 4302 /*! 4303 * portmod_port_failover_mode_get 4304 * 4305 * @brief portmod phy failover mode 4306 * 4307 * @param [in] unit - unit id 4308 * @param [in] port - logical port 4309 * @param [out] failover - Failover Mode get 4310 */ 4311 int portmod_port_failover_mode_get(int unit, int port, phymod_failover_mode_t* failover); 4312 4313 4314 4315 /*! 4316 * portmod_port_warmboot_db_restore 4317 * 4318 * @brief portmod restore information after warmboot 4319 * 4320 * @param [in] unit - unit id 4321 * @param [in] port - logical port 4322 * @param [in] intf_config - 4323 * @param [in] init_config - 4324 * @param [in] phy_op_mode - 4325 */ 4326 int portmod_port_warmboot_db_restore(int unit, int port, const portmod_port_interface_config_t* intf_config, const portmod_port_init_config_t* init_config, phymod_operation_mode_t phy_op_mode); 4327 4328 /*! 4329 * portmod_port_flow_control_set 4330 * 4331 * @brief portmod port flow control config 4332 * 4333 * @param [in] unit - unit id 4334 * @param [in] port - logical port 4335 * @param [in] merge_mode_en - merge_mode 4336 * @param [in] parallel_fc_en - Parallel Flow control enable 4337 */ 4338 int portmod_port_flow_control_set(int unit, int port, int merge_mode_en, int parallel_fc_en); 4339 4340 4341 /*! 4342 * @brief Flags for phy init 4343 */ 4344 #define PORTMOD_INIT_F_EXTERNAL_MOST_ONLY 0 /**< init external most phy */ 4345 #define PORTMOD_INIT_F_ALL_PHYS 1 /**< init all phys */ 4346 #define PORTMOD_INIT_F_INTERNAL_SERDES_ONLY 2 /**< init internal serdes */ 4347 #define PORTMOD_INIT_F_EXTERNAL_PHYS_ONLY 3 /**< init external phys */ 4348 #define PORTMOD_INIT_F_TX_ONLY 4 /**< init Tx side only */ 4349 #define PORTMOD_INIT_F_RX_ONLY 5 /**< init Rx side only */ 4350 4351 4352 /*! 4353 * portmod_port_update_dynamic_state 4354 * 4355 * @brief Portmod state for any logical port dynamixc settings 4356 * 4357 * @param [in] unit - unit id 4358 * @param [in] port - logical port 4359 * @param [in] port_dynamic_state - flag to specify if the user updated any HW params from its defauklt value 4360 */ 4361 int portmod_port_update_dynamic_state(int unit, int port, uint32_t port_dynamic_state); 4362 4363 /*! 4364 * portmod_port_phy_op_mode_get 4365 * 4366 * @brief get phy operation mode. 4367 * 4368 * @param [in] unit - unit id 4369 * @param [in] port - logical port 4370 * @param [out] val - value read 4371 */ 4372 int portmod_port_phy_op_mode_get(int unit, int port, phymod_operation_mode_t* val); 4373 4374 /*! 4375 * @brief Flags for port lane map 4376 */ 4377 #define PORTMOD_LANE_MAP_MAC_ONLY 0x1 /**< mac only lane map */ 4378 4379 #define PORTMOD_LANE_MAP_MAC_ONLY_SET(flags) ((flags) |= PORTMOD_LANE_MAP_MAC_ONLY) 4380 4381 #define PORTMOD_LANE_MAP_MAC_ONLY_CLR(flags) ((flags) &= ~PORTMOD_LANE_MAP_MAC_ONLY) 4382 4383 #define PORTMOD_LANE_MAP_MAC_ONLY_GET(flags) ((flags) & PORTMOD_LANE_MAP_MAC_ONLY ? 1 : 0) 4384 4385 /*! 4386 * portmod_port_lane_map_set 4387 * 4388 * @brief override function for board lane swap. 4389 * 4390 * @param [in] unit - unit id 4391 * @param [in] port - logical port 4392 * @param [in] flags - configuration flags 4393 * @param [in] lane_map - lane map 4394 */ 4395 int portmod_port_lane_map_set(int unit, int port, uint32 flags, const phymod_lane_map_t* lane_map); 4396 /*! 4397 * portmod_port_lane_map_get 4398 * 4399 * @brief override function for board lane swap. 4400 * 4401 * @param [in] unit - unit id 4402 * @param [in] port - logical port 4403 * @param [in] flags - configuration flags 4404 * @param [out] lane_map - lane map 4405 */ 4406 int portmod_port_lane_map_get(int unit, int port, uint32 flags, phymod_lane_map_t* lane_map); 4407 4408 /*! 4409 * portmod_port_polarity_set 4410 * 4411 * @brief override function for board lane swap. 4412 * 4413 * @param [in] unit - unit id 4414 * @param [in] port - logical port 4415 * @param [in] polarity - polarity 4416 */ 4417 int portmod_port_polarity_set(int unit, int port, const phymod_polarity_t* polarity); 4418 /*! 4419 * portmod_port_polarity_get 4420 * 4421 * @brief override function for board lane swap. 4422 * 4423 * @param [in] unit - unit id 4424 * @param [in] port - logical port 4425 * @param [out] polarity - polarity 4426 */ 4427 int portmod_port_polarity_get(int unit, int port, phymod_polarity_t* polarity); 4428 4429 /*! 4430 * portmod_port_medium_config_set 4431 * 4432 * @brief set/get port medium type config. 4433 * 4434 * @param [in] unit - unit id 4435 * @param [in] port - logical port 4436 * @param [in] medium - port medium 4437 * @param [out] config - phy config 4438 */ 4439 int portmod_port_medium_config_set(int unit, int port, soc_port_medium_t medium, soc_phy_config_t* config); 4440 /*! 4441 * portmod_port_medium_config_get 4442 * 4443 * @brief set/get port medium type config. 4444 * 4445 * @param [in] unit - unit id 4446 * @param [in] port - logical port 4447 * @param [in] medium - port medium 4448 * @param [out] config - phy config 4449 */ 4450 int portmod_port_medium_config_get(int unit, int port, soc_port_medium_t medium, soc_phy_config_t* config); 4451 4452 /*! 4453 * portmod_port_medium_get 4454 * 4455 * @brief get port medium type. 4456 * 4457 * @param [in] unit - unit id 4458 * @param [in] port - logical port 4459 * @param [out] medium - port medium 4460 */ 4461 int portmod_port_medium_get(int unit, int port, soc_port_medium_t* medium); 4462 4463 4464 4465 /*! 4466 * @brief Flags for user access struct 4467 */ 4468 #define PORTMOD_SERDES_1000X_AT_6250 0x1 /**< 1000x working at 6.25g */ 4469 #define PORTMOD_SERDES_1000X_AT_12500 0x2 /**< 1000x working at 12.5g */ 4470 #define PORTMOD_SERDES_1000X_AT_25G 0x4 /**< 1000x working at 25g */ 4471 #define PORTMOD_SERDES_10G_AT_25G 0x8 /**< 10g working at 25g */ 4472 4473 #define PORTMOD_SERDES_1000X_AT_6250_SET(flag) ((flag) |= PORTMOD_SERDES_1000X_AT_6250) 4474 #define PORTMOD_SERDES_1000X_AT_12500_SET(flag) ((flag) |= PORTMOD_SERDES_1000X_AT_12500) 4475 #define PORTMOD_SERDES_1000X_AT_25G_SET(flag) ((flag) |= PORTMOD_SERDES_1000X_AT_25G) 4476 #define PORTMOD_SERDES_10G_AT_25G_SET(flag) ((flag) |= PORTMOD_SERDES_10G_AT_25G) 4477 4478 #define PORTMOD_SERDES_1000X_AT_6250_CLR(flag) ((flag) &= ~PORTMOD_SERDES_1000X_AT_6250) 4479 #define PORTMOD_SERDES_1000X_AT_12500_CLR(flag) ((flag) &= ~PORTMOD_SERDES_1000X_AT_12500) 4480 #define PORTMOD_SERDES_1000X_AT_25G_CLR(flag) ((flag) &= ~PORTMOD_SERDES_1000X_AT_25G) 4481 #define PORTMOD_SERDES_10G_AT_25G_CLR(flag) ((flag) &= ~PORTMOD_SERDES_10G_AT_25G) 4482 4483 #define PORTMOD_SERDES_1000X_AT_6250_GET(flag) ((flag) & PORTMOD_SERDES_1000X_AT_6250 ? 1 : 0) 4484 #define PORTMOD_SERDES_1000X_AT_12500_GET(flag) ((flag) & PORTMOD_SERDES_1000X_AT_12500 ? 1 : 0) 4485 #define PORTMOD_SERDES_1000X_AT_25G_GET(flag) ((flag) & PORTMOD_SERDES_1000X_AT_25G ? 1 : 0) 4486 #define PORTMOD_SERDES_10G_AT_25G_GET(flag) ((flag) & PORTMOD_SERDES_10G_AT_25G ? 1 : 0) 4487 4488 4489 /*! 4490 * @struct portmod_port_resources_s 4491 * @brief portmod port resources for flex port 4492 */ 4493 typedef struct portmod_port_resources_s { 4494 portmod_dispatch_type_t pm_type; /**< portmod dispatch type */ 4495 int speed; /**< speed at which port will be flexed */ 4496 int num_lane; /**< lanes of flex port */ 4497 portmod_encap_t encap_mode; /**< flex port encap mode */ 4498 uint32_t flag; /**< same speed working at different VCO */ 4499 } portmod_port_resources_t; 4500 4501 /* portmod_port_resources_t initialization and validation */ 4502 int portmod_port_resources_t_validate(int unit, const portmod_port_resources_t* portmod_port_resources); 4503 int portmod_port_resources_t_init(int unit, portmod_port_resources_t* portmod_port_resources); 4504 4505 /*! 4506 * portmod_pm_port_pll_div_get 4507 * 4508 * @brief dispatch [portmacro]_pll_div_get based on the pm_type in portmod_port_resources_t 4509 * 4510 * @param [in] unit - unit id 4511 * @param [in] port - port 4512 * @param [in] phy_port - physical port 4513 * @param [in] port_resource - port resource 4514 * @param [out] pll_div - pll div 4515 */ 4516 int portmod_pm_port_pll_div_get(int unit, int port, int phy_port, const portmod_port_resources_t* port_resource, uint32_t* pll_div); 4517 4518 4519 /*! 4520 * portmod_port_master_set 4521 * 4522 * @brief set/get the port master mode if the port is running SGMII AN 4523 * 4524 * @param [in] unit - unit id 4525 * @param [in] port - logical port 4526 * @param [in] master_mode - set port master mode 4527 */ 4528 int portmod_port_master_set(int unit, int port, int master_mode); 4529 /*! 4530 * portmod_port_master_get 4531 * 4532 * @brief set/get the port master mode if the port is running SGMII AN 4533 * 4534 * @param [in] unit - unit id 4535 * @param [in] port - logical port 4536 * @param [out] master_mode - get port master mode 4537 */ 4538 int portmod_port_master_get(int unit, int port, int* master_mode); 4539 4540 4541 /*! 4542 * @enum portmod_preemption_control_e 4543 * @brief Preemption controls for portmod_preemption_control_set, portmod_preemption_control_get 4544 */ 4545 typedef enum portmod_preemption_control_e { 4546 portmodPreemptionControlInvalid = 0, /**< Invalid Control */ 4547 portmodPreemptionControlPreemptionSupport = 1, /**< Support preemption operation. */ 4548 portmodPreemptionControlEnableTx = 2, /**< Enable preemption in transmit direction. */ 4549 portmodPreemptionControlVerifyEnable = 3, /**< Enable preemption verify operation. */ 4550 portmodPreemptionControlVerifyTime = 4, /**< The wait time in ms between verification attempts. */ 4551 portmodPreemptionControlVerifyAttempts = 5, /**< The number of verification attempts. */ 4552 portmodPreemptionControlNonFinalFragSizeRx = 6, /**< The minimum size of non-final fragment of a packet in receive direction. */ 4553 portmodPreemptionControlFinalFragSizeRx = 7, /**< The minimum size of final fragment of a packet in receive direction. */ 4554 portmodPreemptionControlCount 4555 } portmod_preemption_control_t; 4556 4557 #ifdef PORTMOD_DIAG 4558 extern enum_mapping_t portmod_preemption_control_t_mapping[]; 4559 #endif /*PORTMOD_DIAG*/ 4560 4561 /* portmod_preemption_control_t validation */ 4562 int portmod_preemption_control_t_validate(int unit, portmod_preemption_control_t portmod_preemption_control); 4563 /*! 4564 * portmod_preemption_control_set 4565 * 4566 * @brief Port preemption configuration set/get 4567 * 4568 * @param [in] unit - unit id 4569 * @param [in] port - logical port 4570 * @param [in] type - preemption parameter of type portmod_preemption_control_t 4571 * @param [in] value - configured value 4572 */ 4573 int portmod_preemption_control_set(int unit, int port, portmod_preemption_control_t type, uint32 value); 4574 /*! 4575 * portmod_preemption_control_get 4576 * 4577 * @brief Port preemption configuration set/get 4578 * 4579 * @param [in] unit - unit id 4580 * @param [in] port - logical port 4581 * @param [in] type - preemption parameter of type portmod_preemption_control_t 4582 * @param [out] value - returns configured value 4583 */ 4584 int portmod_preemption_control_get(int unit, int port, portmod_preemption_control_t type, uint32* value); 4585 4586 4587 /*! 4588 * @enum portmod_preemption_tx_status_e 4589 * @brief Preemption status in the transmit direction, used by portmod_preemption_tx_status_get 4590 */ 4591 typedef enum portmod_preemption_tx_status_e { 4592 portmodPreemptionTxStatusInactive = 0, /**< Verify is enabled but its status is either failed or not initiated. Or Preemption is not enabled. */ 4593 portmodPreemptionTxStatusVerifying = 1, /**< Preemption is enabled and proceeding the verify operation. */ 4594 portmodPreemptionTxStatusActive = 2, /**< Preemption is activated. */ 4595 portmodPreemptionTxStatusCount 4596 } portmod_preemption_tx_status_t; 4597 4598 #ifdef PORTMOD_DIAG 4599 extern enum_mapping_t portmod_preemption_tx_status_t_mapping[]; 4600 #endif /*PORTMOD_DIAG*/ 4601 4602 /* portmod_preemption_tx_status_t validation */ 4603 int portmod_preemption_tx_status_t_validate(int unit, portmod_preemption_tx_status_t portmod_preemption_tx_status); 4604 /*! 4605 * portmod_preemption_tx_status_get 4606 * 4607 * @brief Get the preemption status on the transmit side 4608 * 4609 * @param [in] unit - unit id 4610 * @param [in] port - logical port 4611 * @param [out] value - returns preemption status of type portmod_preemption_tx_status_t 4612 */ 4613 int portmod_preemption_tx_status_get(int unit, int port, uint32* value); 4614 4615 typedef enum portmod_preemption_verify_status_type_e { 4616 portmodPreemptionVerifyStatus = 0, /**< Verify operation status. */ 4617 portmodPreemptionVerifyCountStatus = 1, /**< Verify operation status of number of attempts. */ 4618 portmodPreemptionVerifyCount 4619 } portmod_preemption_verify_status_type_t; 4620 4621 #ifdef PORTMOD_DIAG 4622 extern enum_mapping_t portmod_preemption_verify_status_type_t_mapping[]; 4623 #endif /*PORTMOD_DIAG*/ 4624 4625 /* portmod_preemption_verify_status_type_t validation */ 4626 int portmod_preemption_verify_status_type_t_validate(int unit, portmod_preemption_verify_status_type_t portmod_preemption_verify_status_type); 4627 typedef enum portmod_preemption_verify_status_e { 4628 portmodPreemptionVerifyStatusDisabled = 0, /**< Verify operation is not enabled. */ 4629 portmodPreemptionVerifyStatusInitial = 1, /**< Verify operation is enabled but the not started yet. */ 4630 portmodPreemptionVerifyStatusInProgress = 2, /**< Verify operation is in progress. */ 4631 portmodPreemptionVerifyStatusSucceeded = 3, /**< Verify operation is succeeded. */ 4632 portmodPreemptionVerifyStatusFailed = 4, /**< Verify operation is failed. */ 4633 portmodPreemptionVerifyStatusCount 4634 } portmod_preemption_verify_status_t; 4635 4636 #ifdef PORTMOD_DIAG 4637 extern enum_mapping_t portmod_preemption_verify_status_t_mapping[]; 4638 #endif /*PORTMOD_DIAG*/ 4639 4640 /* portmod_preemption_verify_status_t validation */ 4641 int portmod_preemption_verify_status_t_validate(int unit, portmod_preemption_verify_status_t portmod_preemption_verify_status); 4642 /*! 4643 * portmod_preemption_verify_status_get 4644 * 4645 * @brief Get the preemption verification status or status on number of verify attempts/messages if verification is not complete(failed/succeed) 4646 * 4647 * @param [in] unit - unit id 4648 * @param [in] port - logical port 4649 * @param [in] type - preemption verify operaton status of type portmod_preemption_verify_status_type_t 4650 * @param [out] value - returns verify operation status of type portmod_preemption_verify_status_t 4651 */ 4652 int portmod_preemption_verify_status_get(int unit, int port, portmod_preemption_verify_status_type_t type, uint32* value); 4653 4654 typedef enum portmod_preemption_force_rx_eop_mode_e { 4655 portmodPreemptionForceSwRxEop = 0, /**< Forced SW Rx lost EOP sequence */ 4656 portmodPreemptionForceAutoHwEop = 1, /**< Forced Auto HW Rx lost EOP sequence */ 4657 portmodPreemptionForceCount 4658 } portmod_preemption_force_rx_eop_mode_t; 4659 4660 #ifdef PORTMOD_DIAG 4661 extern enum_mapping_t portmod_preemption_force_rx_eop_mode_t_mapping[]; 4662 #endif /*PORTMOD_DIAG*/ 4663 4664 /* portmod_preemption_force_rx_eop_mode_t validation */ 4665 int portmod_preemption_force_rx_eop_mode_t_validate(int unit, portmod_preemption_force_rx_eop_mode_t portmod_preemption_force_rx_eop_mode); 4666 /*! 4667 * portmod_preemption_force_rx_eop_mode_set 4668 * 4669 * @brief Set/Get preemption forced rx lost eop sequence mode setting. The rx lost eop sequence can be either software or hardware enforced. If Hw based auto rx lost eop is enabled, the rx eop sequence is initiated based on link events. 4670 * 4671 * @param [in] unit - unit id 4672 * @param [in] port - logical port 4673 * @param [in] type - indicates SW or HW enforced EOP of type portmod_preemption_force_rx_eop_mode_t 4674 * @param [in] value - 0 - disable, 1 - enable 4675 */ 4676 int portmod_preemption_force_rx_eop_mode_set(int unit, int port, portmod_preemption_force_rx_eop_mode_t type, uint32 value); 4677 /*! 4678 * portmod_preemption_force_rx_eop_mode_get 4679 * 4680 * @brief Set/Get preemption forced rx lost eop sequence mode setting. The rx lost eop sequence can be either software or hardware enforced. If Hw based auto rx lost eop is enabled, the rx eop sequence is initiated based on link events. 4681 * 4682 * @param [in] unit - unit id 4683 * @param [in] port - logical port 4684 * @param [in] type - indicates SW or HW enforced EOP of type portmod_preemption_force_rx_eop_mode_t 4685 * @param [out] value - returns enabled(1)/disabled(0) 4686 */ 4687 int portmod_preemption_force_rx_eop_mode_get(int unit, int port, portmod_preemption_force_rx_eop_mode_t type, uint32* value); 4688 4689 /*! 4690 * portmod_preemption_rx_timeout_set 4691 * 4692 * @brief Set/Get specified preemption rx timeout and timeout count. This API is not exposed to end user, and needs to be called only during device init. 4693 * 4694 * @param [in] unit - unit id 4695 * @param [in] port - logical port 4696 * @param [in] enable - enables timeout for rx preempt traffic 4697 * @param [in] timeout_cnt - timeout in microsecs 4698 */ 4699 int portmod_preemption_rx_timeout_set(int unit, int port, uint32 enable, uint32 timeout_cnt); 4700 /*! 4701 * portmod_preemption_rx_timeout_get 4702 * 4703 * @brief Set/Get specified preemption rx timeout and timeout count. This API is not exposed to end user, and needs to be called only during device init. 4704 * 4705 * @param [in] unit - unit id 4706 * @param [in] port - logical port 4707 * @param [out] enable - returns status of timeout for rx preempt traffic 4708 * @param [out] timeout_cnt - timeout in microsecs 4709 */ 4710 int portmod_preemption_rx_timeout_get(int unit, int port, uint32* enable, uint32* timeout_cnt); 4711 4712 4713 /*! 4714 * portmod_port_timesync_tx_info_get 4715 * 4716 * @brief Get timestamp and sequence id of tx 1588 packet. 4717 * 4718 * @param [in] unit - unit id 4719 * @param [in] port - logical port 4720 * @param [out] tx_info - tx information of 1588 packet 4721 */ 4722 int portmod_port_timesync_tx_info_get(int unit, int port, portmod_fifo_status_t* tx_info); 4723 4724 4725 #define PORTMOD_LINK_RECOVERY_STATE_LINK_GOOD 0x1 /**< link good state */ 4726 #define PORTMOD_LINK_RECOVERY_STATE_WAIT_FOR_LINK 0x2 /**< wait for link up state */ 4727 #define PORTMOD_LINK_RECOVERY_STATE_RESET_RX 0x3 /**< reset rx state */ 4728 #define PORTMOD_LINK_RECOVERY_LINK_WAIT_CNT_LIMIT 0x6 /**< timeout count before reset rx */ 4729 4730 4731 /*! 4732 * @struct portmod_link_recovery_s 4733 * @brief link recovery for optics. 4734 */ 4735 typedef struct portmod_link_recovery_s { 4736 uint32 state; /**< state of the link recovery */ 4737 uint32 enabled; /**< feature enabled or not */ 4738 uint32 tick_cnt; /**< timeout counter */ 4739 } portmod_link_recovery_t; 4740 4741 /* portmod_link_recovery_t initialization and validation */ 4742 int portmod_link_recovery_t_validate(int unit, const portmod_link_recovery_t* portmod_link_recovery); 4743 int portmod_link_recovery_t_init(int unit, portmod_link_recovery_t* portmod_link_recovery); 4744 4745 /*! 4746 * portmod_core_add 4747 * 4748 * @brief PM Core init routine for DNX devices; XGS does not call this API but calls portmod_pm_serdes_core_init() directly 4749 * 4750 * @param [in] unit - unit id 4751 * @param [in] pm_id - port macro id 4752 * @param [in] add_info - 4753 */ 4754 int portmod_core_add(int unit, int pm_id, const portmod_port_add_info_t* add_info); 4755 4756 /*! 4757 * portmod_pm_serdes_core_init 4758 * 4759 * @brief PM Core init routine 4760 * 4761 * @param [in] unit - unit id 4762 * @param [in] pm_id - port macro id 4763 * @param [in] add_info - 4764 */ 4765 int portmod_pm_serdes_core_init(int unit, int pm_id, const portmod_port_add_info_t* add_info); 4766 4767 /*! 4768 * portmod_pm_is_initialized 4769 * 4770 * @brief Returns if the PortMacro associated with the port is initialized or not 4771 * 4772 * @param [in] unit - unit id 4773 * @param [in] pm_id - port macro id 4774 * @param [out] is_initialized - indicates if PM is initialized 4775 */ 4776 int portmod_pm_is_initialized(int unit, int pm_id, int* is_initialized); 4777 4778 typedef struct portmod_pmd_lane_config_s { 4779 phymod_firmware_lane_config_t pmd_firmware_lane_config; /**< pmd firmware_lane config info */ 4780 uint32_t pam4_channel_loss; /**< pam4 channel loss in DB */ 4781 } portmod_pmd_lane_config_t; 4782 4783 /* portmod_pmd_lane_config_t initialization and validation */ 4784 int portmod_pmd_lane_config_t_validate(int unit, const portmod_pmd_lane_config_t* portmod_pmd_lane_config); 4785 int portmod_pmd_lane_config_t_init(int unit, portmod_pmd_lane_config_t* portmod_pmd_lane_config); 4786 4787 /*! 4788 * portmod_port_speed_config_validate 4789 * 4790 * @brief Port speed validation. 4791 * 4792 * @param [in] unit - unit id 4793 * @param [in] port - logical port 4794 * @param [in] speed_config - port speed config 4795 * @param [out] affected_pbmp - Port bit map for affected ports 4796 */ 4797 int portmod_port_speed_config_validate(int unit, int port, const portmod_speed_config_t* speed_config, portmod_pbmp_t* affected_pbmp); 4798 4799 /*! 4800 * portmod_pm_enable 4801 * 4802 * @brief Enable port macro. 4803 * 4804 * @param [in] unit - unit id 4805 * @param [in] pm_id - port macro id 4806 * @param [in] enable - enable or disable 4807 */ 4808 int portmod_pm_enable(int unit, int pm_id, int enable); 4809 4810 /*! 4811 * portmod_phy_pm_id_get 4812 * 4813 * @brief Geven the physical port ID, return the associated PM ID 4814 * 4815 * @param [in] unit - unit id 4816 * @param [in] pport - physical port 4817 * @param [out] pm_id - the associated PM ID of the physical port 4818 */ 4819 int portmod_phy_pm_id_get(int unit, int pport, int* pm_id); 4820 4821 /*! 4822 * portmod_pm_logical_pbmp_get 4823 * 4824 * @brief Get the logical port bitmap based on the input PM ID 4825 * 4826 * @param [in] unit - unit id 4827 * @param [in] pm_id - port macro id 4828 * @param [out] logical_pbmp - logical port bitmap of the PM 4829 */ 4830 int portmod_pm_logical_pbmp_get(int unit, int pm_id, portmod_pbmp_t* logical_pbmp); 4831 4832 /*! 4833 * portmod_pm_vco_reconfig 4834 * 4835 * @brief Reconfigure the vco rate for pm core. 4836 * 4837 * @param [in] unit - unit id 4838 * @param [in] pm_id - port macro id 4839 * @param [in] vco - vco rates; vco[0] is TVCO and vco[1] is OVCO; two VCO rates always have to present 4840 */ 4841 int portmod_pm_vco_reconfig(int unit, int pm_id, const portmod_vco_type_t* vco); 4842 4843 /*! 4844 * portmod_port_speed_config_set 4845 * 4846 * @brief set/get the speed config for the specified port. 4847 * 4848 * @param [in] unit - unit id 4849 * @param [in] port - logical port 4850 * @param [in] speed_config - port speed config 4851 */ 4852 int portmod_port_speed_config_set(int unit, int port, const portmod_speed_config_t* speed_config); 4853 /*! 4854 * portmod_port_speed_config_get 4855 * 4856 * @brief set/get the speed config for the specified port. 4857 * 4858 * @param [in] unit - unit id 4859 * @param [in] port - logical port 4860 * @param [out] speed_config - port speed config 4861 */ 4862 int portmod_port_speed_config_get(int unit, int port, portmod_speed_config_t* speed_config); 4863 4864 /*! 4865 * @brief Flags for pm_speed_validate. 4866 */ 4867 #define PORTMOD_PM_SPEED_VALIDATE_F_PLL_SWITCH_DEFAULT 0x1 /**< TVCO change is allowed if the entire PM's speed config is provided; otherwise only OVCO change is allowed */ 4868 #define PORTMOD_PM_SPEED_VALIDATE_F_PLL_SWITCH_NOT_ALLOWED 0x2 /**< do not allow PLL change */ 4869 #define PORTMOD_PM_SPEED_VALIDATE_F_ONE_PLL_SWITCH_ALLOWED 0x4 /**< only allow one PLL (OVCO) change */ 4870 #define PORTMOD_PM_SPEED_VALIDATE_F_TWO_PLL_SWITCH_ALLOWED 0x8 /**< allow two PLL (TVCO and OVCO) change */ 4871 4872 4873 4874 /*! 4875 * @struct portmod_sbus_bcast_config_s 4876 * @brief SBUS broadcast configuration 4877 */ 4878 typedef struct portmod_sbus_bcast_config_s { 4879 int flag; /**< broadcast phase */ 4880 int bcast_id; /**< SBUS broadcast ID */ 4881 int chain_last; /**< the last instance in SBUS ring */ 4882 } portmod_sbus_bcast_config_t; 4883 4884 /* portmod_sbus_bcast_config_t initialization and validation */ 4885 int portmod_sbus_bcast_config_t_validate(int unit, const portmod_sbus_bcast_config_t* portmod_sbus_bcast_config); 4886 int portmod_sbus_bcast_config_t_init(int unit, portmod_sbus_bcast_config_t* portmod_sbus_bcast_config); 4887 4888 4889 /*! 4890 * portmod_port_credits_enable_set 4891 * 4892 * @brief Enable credits for the port. 4893 * 4894 * @param [in] unit - unit id 4895 * @param [in] port - logical port 4896 * @param [in] enable - 4897 */ 4898 int portmod_port_credits_enable_set(int unit, int port, int enable); 4899 4900 #ifdef CPRIMOD_SUPPORT 4901 typedef enum portmod_cpri_stage_e { 4902 portmodCpriStageRx = 0, /**< Rx Basic Frame Parser */ 4903 portmodCpriStageTx = 1, /**< Tx Basic Frame Assembly */ 4904 portmodCpriStageCount 4905 } portmod_cpri_stage_t; 4906 4907 #ifdef PORTMOD_DIAG 4908 extern enum_mapping_t portmod_cpri_stage_t_mapping[]; 4909 #endif /*PORTMOD_DIAG*/ 4910 4911 /* portmod_cpri_stage_t validation */ 4912 int portmod_cpri_stage_t_validate(int unit, portmod_cpri_stage_t portmod_cpri_stage); 4913 #endif /* CPRIMOD_SUPPORT */ 4914 /*! 4915 * portmod_cpri_port_stage_activate 4916 * 4917 * @brief Activate the basic framer standby table. 4918 * 4919 * @param [in] unit - unit id 4920 * @param [in] port - logical port 4921 * @param [in] stage - 4922 */ 4923 #ifdef CPRIMOD_SUPPORT 4924 int portmod_cpri_port_stage_activate(int unit, int port, portmod_cpri_stage_t stage); 4925 #endif /* CPRIMOD_SUPPORT */ 4926 4927 4928 /*! 4929 * @struct portmod_cpri_axc_frame_info_s 4930 * @brief CPRI Rx AxC Frame information. 4931 */ 4932 #ifdef CPRIMOD_SUPPORT 4933 typedef struct portmod_cpri_axc_frame_info_s { 4934 uint32 start_bit; /**< Start Bit */ 4935 uint32 num_bits; /**< Number of Bit */ 4936 cprimod_cpri_container_config_t container_info; /**< Container Information. */ 4937 cprimod_payload_size_info_t roe_payload_info; /**< Payload Information. */ 4938 cprimod_encap_decap_data_config_t encap_data_info; /**< Encap Data Information. */ 4939 } portmod_cpri_axc_frame_info_t; 4940 4941 /* portmod_cpri_axc_frame_info_t initialization and validation */ 4942 int portmod_cpri_axc_frame_info_t_validate(int unit, const portmod_cpri_axc_frame_info_t* portmod_cpri_axc_frame_info); 4943 int portmod_cpri_axc_frame_info_t_init(int unit, portmod_cpri_axc_frame_info_t* portmod_cpri_axc_frame_info); 4944 4945 #endif /* CPRIMOD_SUPPORT */ 4946 /*! 4947 * portmod_cpri_port_rsvd4_tx_fsm_state_set 4948 * 4949 * @brief Set rsvd4 fsm state 4950 * 4951 * @param [in] unit - unit id 4952 * @param [in] port - logical port 4953 * @param [in] state - State to set. 4954 */ 4955 #ifdef CPRIMOD_SUPPORT 4956 int portmod_cpri_port_rsvd4_tx_fsm_state_set(int unit, int port, cprimod_rsvd4_tx_fsm_state_t state); 4957 #endif /* CPRIMOD_SUPPORT */ 4958 4959 /*! 4960 * portmod_cpri_port_rsvd4_tx_override_set 4961 * 4962 * @brief Set rsvd4 tx override 4963 * 4964 * @param [in] unit - unit id 4965 * @param [in] port - logical port 4966 * @param [in] parameter - override parameter. 4967 * @param [in] enable - enable override. 4968 * @param [in] value - value override. 4969 */ 4970 #ifdef CPRIMOD_SUPPORT 4971 int portmod_cpri_port_rsvd4_tx_override_set(int unit, int port, cprimod_rsvd4_tx_overide_t parameter, int enable, int value); 4972 #endif /* CPRIMOD_SUPPORT */ 4973 4974 /*! 4975 * portmod_cpri_port_rsvd4_rx_override_set 4976 * 4977 * @brief Set rsvd4 rx override 4978 * 4979 * @param [in] unit - unit id 4980 * @param [in] port - logical port 4981 * @param [in] parameter - override parameter. 4982 * @param [in] enable - enable override. 4983 * @param [in] value - value override. 4984 */ 4985 #ifdef CPRIMOD_SUPPORT 4986 int portmod_cpri_port_rsvd4_rx_override_set(int unit, int port, cprimod_rsvd4_rx_overide_t parameter, int enable, int value); 4987 #endif /* CPRIMOD_SUPPORT */ 4988 4989 /*! 4990 * portmod_cpri_port_rx_axc_frame_add 4991 * 4992 * @brief Add Rx AxC to the framer. 4993 * 4994 * @param [in] unit - unit id 4995 * @param [in] port - logical port 4996 * @param [in] axc_id - AxC ID. 4997 * @param [in] frame_info - frame configuration information. 4998 */ 4999 #ifdef CPRIMOD_SUPPORT 5000 int portmod_cpri_port_rx_axc_frame_add(int unit, int port, uint32 axc_id, const portmod_cpri_axc_frame_info_t* frame_info); 5001 #endif /* CPRIMOD_SUPPORT */ 5002 5003 /*! 5004 * portmod_cpri_port_rx_frame_optional_config_set 5005 * 5006 * @brief Set/Get Rx required field. 5007 * 5008 * @param [in] unit - unit id 5009 * @param [in] port - logical port 5010 * @param [in] field - Fild to set/get. 5011 * @param [in] value - value going to Field 5012 */ 5013 #ifdef CPRIMOD_SUPPORT 5014 int portmod_cpri_port_rx_frame_optional_config_set(int unit, int port, cprimod_rx_config_field_t field, int value); 5015 #endif /* CPRIMOD_SUPPORT */ 5016 /*! 5017 * portmod_cpri_port_rx_frame_optional_config_get 5018 * 5019 * @brief Set/Get Rx required field. 5020 * 5021 * @param [in] unit - unit id 5022 * @param [in] port - logical port 5023 * @param [in] field - Fild to set/get. 5024 * @param [out] value - value going to Field 5025 */ 5026 #ifdef CPRIMOD_SUPPORT 5027 int portmod_cpri_port_rx_frame_optional_config_get(int unit, int port, cprimod_rx_config_field_t field, int* value); 5028 #endif /* CPRIMOD_SUPPORT */ 5029 5030 /*! 5031 * portmod_cpri_port_tx_frame_optional_config_set 5032 * 5033 * @brief Set/Get Tx required field. 5034 * 5035 * @param [in] unit - unit id 5036 * @param [in] port - logical port 5037 * @param [in] field - Fild to set/get. 5038 * @param [in] value - value going to Field 5039 */ 5040 #ifdef CPRIMOD_SUPPORT 5041 int portmod_cpri_port_tx_frame_optional_config_set(int unit, int port, cprimod_tx_config_field_t field, uint32 value); 5042 #endif /* CPRIMOD_SUPPORT */ 5043 /*! 5044 * portmod_cpri_port_tx_frame_optional_config_get 5045 * 5046 * @brief Set/Get Tx required field. 5047 * 5048 * @param [in] unit - unit id 5049 * @param [in] port - logical port 5050 * @param [in] field - Fild to set/get. 5051 * @param [out] value - value going to Field 5052 */ 5053 #ifdef CPRIMOD_SUPPORT 5054 int portmod_cpri_port_tx_frame_optional_config_get(int unit, int port, cprimod_tx_config_field_t field, uint32* value); 5055 #endif /* CPRIMOD_SUPPORT */ 5056 5057 /*! 5058 * portmod_port_rsvd4_rx_frame_optional_config_set 5059 * 5060 * @brief Set/Get Rx required field. 5061 * 5062 * @param [in] unit - unit id 5063 * @param [in] port - logical port 5064 * @param [in] field - Fild to set/get. 5065 * @param [in] value - value going to Field 5066 */ 5067 #ifdef CPRIMOD_SUPPORT 5068 int portmod_port_rsvd4_rx_frame_optional_config_set(int unit, int port, cprimod_rsvd4_rx_config_field_t field, int value); 5069 #endif /* CPRIMOD_SUPPORT */ 5070 /*! 5071 * portmod_port_rsvd4_rx_frame_optional_config_get 5072 * 5073 * @brief Set/Get Rx required field. 5074 * 5075 * @param [in] unit - unit id 5076 * @param [in] port - logical port 5077 * @param [in] field - Fild to set/get. 5078 * @param [out] value - value going to Field 5079 */ 5080 #ifdef CPRIMOD_SUPPORT 5081 int portmod_port_rsvd4_rx_frame_optional_config_get(int unit, int port, cprimod_rsvd4_rx_config_field_t field, int* value); 5082 #endif /* CPRIMOD_SUPPORT */ 5083 5084 /*! 5085 * portmod_port_rsvd4_tx_frame_optional_config_set 5086 * 5087 * @brief Set/Get Tx required field. 5088 * 5089 * @param [in] unit - unit id 5090 * @param [in] port - logical port 5091 * @param [in] field - Fild to set/get. 5092 * @param [in] value - value going to Field 5093 */ 5094 #ifdef CPRIMOD_SUPPORT 5095 int portmod_port_rsvd4_tx_frame_optional_config_set(int unit, int port, cprimod_rsvd4_tx_config_field_t field, int value); 5096 #endif /* CPRIMOD_SUPPORT */ 5097 /*! 5098 * portmod_port_rsvd4_tx_frame_optional_config_get 5099 * 5100 * @brief Set/Get Tx required field. 5101 * 5102 * @param [in] unit - unit id 5103 * @param [in] port - logical port 5104 * @param [in] field - Fild to set/get. 5105 * @param [out] value - value going to Field 5106 */ 5107 #ifdef CPRIMOD_SUPPORT 5108 int portmod_port_rsvd4_tx_frame_optional_config_get(int unit, int port, cprimod_rsvd4_tx_config_field_t field, int* value); 5109 #endif /* CPRIMOD_SUPPORT */ 5110 5111 /*! 5112 * portmod_port_rsvd4_rx_speed_set 5113 * 5114 * @brief Set/Get Tx required field. 5115 * 5116 * @param [in] unit - unit id 5117 * @param [in] port - logical port 5118 * @param [in] speed - value going to Field 5119 */ 5120 #ifdef CPRIMOD_SUPPORT 5121 int portmod_port_rsvd4_rx_speed_set(int unit, int port, cprimod_port_rsvd4_speed_mult_t speed); 5122 #endif /* CPRIMOD_SUPPORT */ 5123 /*! 5124 * portmod_port_rsvd4_rx_speed_get 5125 * 5126 * @brief Set/Get Tx required field. 5127 * 5128 * @param [in] unit - unit id 5129 * @param [in] port - logical port 5130 * @param [out] speed - value going to Field 5131 */ 5132 #ifdef CPRIMOD_SUPPORT 5133 int portmod_port_rsvd4_rx_speed_get(int unit, int port, cprimod_port_rsvd4_speed_mult_t* speed); 5134 #endif /* CPRIMOD_SUPPORT */ 5135 5136 /*! 5137 * portmod_port_rsvd4_tx_speed_set 5138 * 5139 * @brief Set/Get Tx required field. 5140 * 5141 * @param [in] unit - unit id 5142 * @param [in] port - logical port 5143 * @param [in] speed - value going to Field 5144 */ 5145 #ifdef CPRIMOD_SUPPORT 5146 int portmod_port_rsvd4_tx_speed_set(int unit, int port, cprimod_port_rsvd4_speed_mult_t speed); 5147 #endif /* CPRIMOD_SUPPORT */ 5148 /*! 5149 * portmod_port_rsvd4_tx_speed_get 5150 * 5151 * @brief Set/Get Tx required field. 5152 * 5153 * @param [in] unit - unit id 5154 * @param [in] port - logical port 5155 * @param [out] speed - value going to Field 5156 */ 5157 #ifdef CPRIMOD_SUPPORT 5158 int portmod_port_rsvd4_tx_speed_get(int unit, int port, cprimod_port_rsvd4_speed_mult_t* speed); 5159 #endif /* CPRIMOD_SUPPORT */ 5160 5161 /*! 5162 * portmod_cpri_port_rx_axc_frame_delete 5163 * 5164 * @brief Delete Rx AxC to the framer. 5165 * 5166 * @param [in] unit - unit id 5167 * @param [in] port - logical port 5168 * @param [in] axc_id - AxC ID. 5169 */ 5170 #ifdef CPRIMOD_SUPPORT 5171 int portmod_cpri_port_rx_axc_frame_delete(int unit, int port, uint32 axc_id); 5172 #endif /* CPRIMOD_SUPPORT */ 5173 5174 /*! 5175 * portmod_cpri_port_rx_axc_frame_get 5176 * 5177 * @brief Get Rx AxC to the framer. 5178 * 5179 * @param [in] unit - unit id 5180 * @param [in] port - logical port 5181 * @param [in] axc_id - AxC ID. 5182 * @param [in] from_get_all - from get_all or get 5183 * @param [out] frame_info - frame configuration information. 5184 */ 5185 #ifdef CPRIMOD_SUPPORT 5186 int portmod_cpri_port_rx_axc_frame_get(int unit, int port, uint32 axc_id, uint32 from_get_all, portmod_cpri_axc_frame_info_t* frame_info); 5187 #endif /* CPRIMOD_SUPPORT */ 5188 5189 /*! 5190 * portmod_cpri_port_rsvd4_rx_fsm_state_set 5191 * 5192 * @brief Set rsvd4 fsm state 5193 * 5194 * @param [in] unit - unit id 5195 * @param [in] port - logical port 5196 * @param [in] state - State to set. 5197 */ 5198 #ifdef CPRIMOD_SUPPORT 5199 int portmod_cpri_port_rsvd4_rx_fsm_state_set(int unit, int port, cprimod_rsvd4_rx_fsm_state_t state); 5200 #endif /* CPRIMOD_SUPPORT */ 5201 5202 /*! 5203 * portmod_cpri_port_tx_axc_frame_add 5204 * 5205 * @brief Add Tx AxC to the framer. 5206 * 5207 * @param [in] unit - unit id 5208 * @param [in] port - logical port 5209 * @param [in] axc_id - AxC ID. 5210 * @param [in] frame_info - frame configuration information. 5211 */ 5212 #ifdef CPRIMOD_SUPPORT 5213 int portmod_cpri_port_tx_axc_frame_add(int unit, int port, uint32 axc_id, const portmod_cpri_axc_frame_info_t* frame_info); 5214 #endif /* CPRIMOD_SUPPORT */ 5215 5216 /*! 5217 * portmod_cpri_port_tx_axc_frame_delete 5218 * 5219 * @brief Delete Tx AxC to the framer. 5220 * 5221 * @param [in] unit - unit id 5222 * @param [in] port - logical port 5223 * @param [in] axc_id - AxC ID. 5224 */ 5225 #ifdef CPRIMOD_SUPPORT 5226 int portmod_cpri_port_tx_axc_frame_delete(int unit, int port, uint32 axc_id); 5227 #endif /* CPRIMOD_SUPPORT */ 5228 5229 /*! 5230 * portmod_cpri_port_tx_axc_frame_get 5231 * 5232 * @brief Get Tx AxC to the framer. 5233 * 5234 * @param [in] unit - unit id 5235 * @param [in] port - logical port 5236 * @param [in] axc_id - AxC ID. 5237 * @param [in] from_get_all - from get_all or get 5238 * @param [out] frame_info - frame configuration information. 5239 */ 5240 #ifdef CPRIMOD_SUPPORT 5241 int portmod_cpri_port_tx_axc_frame_get(int unit, int port, uint32 axc_id, uint32 from_get_all, portmod_cpri_axc_frame_info_t* frame_info); 5242 #endif /* CPRIMOD_SUPPORT */ 5243 5244 /*! 5245 * portmod_cpri_port_encap_set 5246 * 5247 * @brief Encap Header Configuration. 5248 * 5249 * @param [in] unit - unit id 5250 * @param [in] port - logical port 5251 * @param [in] queue_num - Queue Number. 5252 * @param [in] config - Encapsulate Header Configuration. 5253 */ 5254 #ifdef CPRIMOD_SUPPORT 5255 int portmod_cpri_port_encap_set(int unit, int port, uint32 queue_num, const cprimod_encap_header_config_t* config); 5256 #endif /* CPRIMOD_SUPPORT */ 5257 /*! 5258 * portmod_cpri_port_encap_get 5259 * 5260 * @brief Encap Header Configuration. 5261 * 5262 * @param [in] unit - unit id 5263 * @param [in] port - logical port 5264 * @param [in] queue_num - Queue Number. 5265 * @param [out] config - Encapsulate Header Configuration. 5266 */ 5267 #ifdef CPRIMOD_SUPPORT 5268 int portmod_cpri_port_encap_get(int unit, int port, uint32 queue_num, cprimod_encap_header_config_t* config); 5269 #endif /* CPRIMOD_SUPPORT */ 5270 5271 /*! 5272 * portmod_cpri_port_encap_roe_ordering_info_set 5273 * 5274 * @brief Encap Ordering info. 5275 * 5276 * @param [in] unit - unit id 5277 * @param [in] port - logical port 5278 * @param [in] index - Index to ROE ordering info table. 5279 * @param [in] config - Encap Ordering info. 5280 */ 5281 #ifdef CPRIMOD_SUPPORT 5282 int portmod_cpri_port_encap_roe_ordering_info_set(int unit, int port, uint32 index, const cprimod_encap_ordering_info_entry_t* config); 5283 #endif /* CPRIMOD_SUPPORT */ 5284 /*! 5285 * portmod_cpri_port_encap_roe_ordering_info_get 5286 * 5287 * @brief Encap Ordering info. 5288 * 5289 * @param [in] unit - unit id 5290 * @param [in] port - logical port 5291 * @param [in] index - Index to ROE ordering info table. 5292 * @param [out] config - Encap Ordering info. 5293 */ 5294 #ifdef CPRIMOD_SUPPORT 5295 int portmod_cpri_port_encap_roe_ordering_info_get(int unit, int port, uint32 index, cprimod_encap_ordering_info_entry_t* config); 5296 #endif /* CPRIMOD_SUPPORT */ 5297 5298 /*! 5299 * portmod_cpri_port_encap_roe_ordering_sequence_offset_set 5300 * 5301 * @brief Encap Ordering info Offset. 5302 * 5303 * @param [in] unit - unit id 5304 * @param [in] port - logical port 5305 * @param [in] queue_num - Queue number. 5306 * @param [in] control - 1 Control 0 Data. 5307 * @param [in] config - Encap Ordering info Offset for Queue. 5308 */ 5309 #ifdef CPRIMOD_SUPPORT 5310 int portmod_cpri_port_encap_roe_ordering_sequence_offset_set(int unit, int port, uint32 queue_num, uint32 control, const cprimod_cpri_ordering_info_offset_t* config); 5311 #endif /* CPRIMOD_SUPPORT */ 5312 /*! 5313 * portmod_cpri_port_encap_roe_ordering_sequence_offset_get 5314 * 5315 * @brief Encap Ordering info Offset. 5316 * 5317 * @param [in] unit - unit id 5318 * @param [in] port - logical port 5319 * @param [in] queue_num - Queue number. 5320 * @param [in] control - 1 Control 0 Data. 5321 * @param [out] config - Encap Ordering info Offset for Queue. 5322 */ 5323 #ifdef CPRIMOD_SUPPORT 5324 int portmod_cpri_port_encap_roe_ordering_sequence_offset_get(int unit, int port, uint32 queue_num, uint32 control, cprimod_cpri_ordering_info_offset_t* config); 5325 #endif /* CPRIMOD_SUPPORT */ 5326 5327 /*! 5328 * portmod_cpri_port_roe_encap_macda_entry_set 5329 * 5330 * @brief Encap Mac Da. 5331 * 5332 * @param [in] unit - unit id 5333 * @param [in] port - logical port 5334 * @param [in] index - Index to MAC DA table. 5335 * @param [in] mac_addr - Mac Addr. 5336 */ 5337 #ifdef CPRIMOD_SUPPORT 5338 int portmod_cpri_port_roe_encap_macda_entry_set(int unit, int port, uint32 index, cprimod_mac_addr_t mac_addr); 5339 #endif /* CPRIMOD_SUPPORT */ 5340 /*! 5341 * portmod_cpri_port_roe_encap_macda_entry_get 5342 * 5343 * @brief Encap Mac Da. 5344 * 5345 * @param [in] unit - unit id 5346 * @param [in] port - logical port 5347 * @param [in] index - Index to MAC DA table. 5348 * @param [out] mac_addr - Mac Addr. 5349 */ 5350 #ifdef CPRIMOD_SUPPORT 5351 int portmod_cpri_port_roe_encap_macda_entry_get(int unit, int port, uint32 index, cprimod_mac_addr_t mac_addr); 5352 #endif /* CPRIMOD_SUPPORT */ 5353 5354 /*! 5355 * portmod_cpri_port_roe_encap_macsa_entry_set 5356 * 5357 * @brief Encap Mac Sa. 5358 * 5359 * @param [in] unit - unit id 5360 * @param [in] port - logical port 5361 * @param [in] index - Index to MAC DA table. 5362 * @param [in] mac_addr - Mac Addr. 5363 */ 5364 #ifdef CPRIMOD_SUPPORT 5365 int portmod_cpri_port_roe_encap_macsa_entry_set(int unit, int port, uint32 index, cprimod_mac_addr_t mac_addr); 5366 #endif /* CPRIMOD_SUPPORT */ 5367 /*! 5368 * portmod_cpri_port_roe_encap_macsa_entry_get 5369 * 5370 * @brief Encap Mac Sa. 5371 * 5372 * @param [in] unit - unit id 5373 * @param [in] port - logical port 5374 * @param [in] index - Index to MAC DA table. 5375 * @param [out] mac_addr - Mac Addr. 5376 */ 5377 #ifdef CPRIMOD_SUPPORT 5378 int portmod_cpri_port_roe_encap_macsa_entry_get(int unit, int port, uint32 index, cprimod_mac_addr_t mac_addr); 5379 #endif /* CPRIMOD_SUPPORT */ 5380 5381 /*! 5382 * portmod_cpri_port_roe_encap_vlan_entry_set 5383 * 5384 * @brief Encap VLAN. 5385 * 5386 * @param [in] unit - unit id 5387 * @param [in] port - logical port 5388 * @param [in] index - Index to VLAN table. 5389 * @param [in] table_id - VLAN0 or VLAN1 table. 5390 * @param [in] vlan_id - VLAN ID. 5391 */ 5392 #ifdef CPRIMOD_SUPPORT 5393 int portmod_cpri_port_roe_encap_vlan_entry_set(int unit, int port, uint32 index, cprimod_vlan_table_id_t table_id, uint32 vlan_id); 5394 #endif /* CPRIMOD_SUPPORT */ 5395 /*! 5396 * portmod_cpri_port_roe_encap_vlan_entry_get 5397 * 5398 * @brief Encap VLAN. 5399 * 5400 * @param [in] unit - unit id 5401 * @param [in] port - logical port 5402 * @param [in] index - Index to VLAN table. 5403 * @param [in] table_id - VLAN0 or VLAN1 table. 5404 * @param [out] vlan_id - VLAN ID. 5405 */ 5406 #ifdef CPRIMOD_SUPPORT 5407 int portmod_cpri_port_roe_encap_vlan_entry_get(int unit, int port, uint32 index, cprimod_vlan_table_id_t table_id, uint32* vlan_id); 5408 #endif /* CPRIMOD_SUPPORT */ 5409 5410 /*! 5411 * portmod_cpri_port_decap_ethertype_config_set 5412 * 5413 * @brief Set Decap ethtype for a packet type. 5414 * 5415 * @param [in] unit - unit id 5416 * @param [in] port - logical port 5417 * @param [in] pkt_type - Packet Type. 5418 * @param [in] ethtype - ETHTYPE. 5419 */ 5420 #ifdef CPRIMOD_SUPPORT 5421 int portmod_cpri_port_decap_ethertype_config_set(int unit, int port, cprimod_ethertype_t pkt_type, uint16 ethtype); 5422 #endif /* CPRIMOD_SUPPORT */ 5423 /*! 5424 * portmod_cpri_port_decap_ethertype_config_get 5425 * 5426 * @brief Set Decap ethtype for a packet type. 5427 * 5428 * @param [in] unit - unit id 5429 * @param [in] port - logical port 5430 * @param [in] pkt_type - Packet Type. 5431 * @param [out] ethtype - ETHTYPE. 5432 */ 5433 #ifdef CPRIMOD_SUPPORT 5434 int portmod_cpri_port_decap_ethertype_config_get(int unit, int port, cprimod_ethertype_t pkt_type, uint16* ethtype); 5435 #endif /* CPRIMOD_SUPPORT */ 5436 5437 /*! 5438 * portmod_cpri_port_encap_ethertype_config_set 5439 * 5440 * @brief Set Encap ethtype for a packet type. 5441 * 5442 * @param [in] unit - unit id 5443 * @param [in] port - logical port 5444 * @param [in] pkt_type - Packet Type. 5445 * @param [in] ethtype - ETHTYPE. 5446 */ 5447 #ifdef CPRIMOD_SUPPORT 5448 int portmod_cpri_port_encap_ethertype_config_set(int unit, int port, cprimod_ethertype_t pkt_type, uint16 ethtype); 5449 #endif /* CPRIMOD_SUPPORT */ 5450 /*! 5451 * portmod_cpri_port_encap_ethertype_config_get 5452 * 5453 * @brief Set Encap ethtype for a packet type. 5454 * 5455 * @param [in] unit - unit id 5456 * @param [in] port - logical port 5457 * @param [in] pkt_type - Packet Type. 5458 * @param [out] ethtype - ETHTYPE. 5459 */ 5460 #ifdef CPRIMOD_SUPPORT 5461 int portmod_cpri_port_encap_ethertype_config_get(int unit, int port, cprimod_ethertype_t pkt_type, uint16* ethtype); 5462 #endif /* CPRIMOD_SUPPORT */ 5463 5464 /*! 5465 * portmod_cpri_port_decap_flow_config_set 5466 * 5467 * @brief Flow Classification. 5468 * 5469 * @param [in] unit - unit id 5470 * @param [in] port - logical port 5471 * @param [in] roe_subtype - ROE SubType. 5472 * @param [in] queue_num - Queue Number. 5473 * @param [in] cls_option - Option. 5474 * @param [in] flow_type - Flow Type. 5475 */ 5476 #ifdef CPRIMOD_SUPPORT 5477 int portmod_cpri_port_decap_flow_config_set(int unit, int port, uint8 roe_subtype, uint32 queue_num, cprimod_cls_option_t cls_option, cprimod_cls_flow_type_t flow_type); 5478 #endif /* CPRIMOD_SUPPORT */ 5479 /*! 5480 * portmod_cpri_port_decap_flow_config_get 5481 * 5482 * @brief Flow Classification. 5483 * 5484 * @param [in] unit - unit id 5485 * @param [in] port - logical port 5486 * @param [in] roe_subtype - ROE SubType. 5487 * @param [out] queue_num - Queue Number. 5488 * @param [out] cls_option - Option. 5489 * @param [out] flow_type - Flow Type. 5490 */ 5491 #ifdef CPRIMOD_SUPPORT 5492 int portmod_cpri_port_decap_flow_config_get(int unit, int port, uint8 roe_subtype, uint32* queue_num, cprimod_cls_option_t* cls_option, cprimod_cls_flow_type_t* flow_type); 5493 #endif /* CPRIMOD_SUPPORT */ 5494 5495 /*! 5496 * portmod_cpri_port_decap_queue_to_ordering_info_index_set 5497 * 5498 * @brief Queue to Ordering info Index. 5499 * 5500 * @param [in] unit - unit id 5501 * @param [in] port - logical port 5502 * @param [in] queue_num - Queue Number. 5503 * @param [in] ordering_info_index - Index to decap ordering info table. 5504 */ 5505 #ifdef CPRIMOD_SUPPORT 5506 int portmod_cpri_port_decap_queue_to_ordering_info_index_set(int unit, int port, uint32 queue_num, uint32 ordering_info_index); 5507 #endif /* CPRIMOD_SUPPORT */ 5508 /*! 5509 * portmod_cpri_port_decap_queue_to_ordering_info_index_get 5510 * 5511 * @brief Queue to Ordering info Index. 5512 * 5513 * @param [in] unit - unit id 5514 * @param [in] port - logical port 5515 * @param [in] queue_num - Queue Number. 5516 * @param [out] ordering_info_index - Index to decap ordering info table. 5517 */ 5518 #ifdef CPRIMOD_SUPPORT 5519 int portmod_cpri_port_decap_queue_to_ordering_info_index_get(int unit, int port, uint32 queue_num, uint32* ordering_info_index); 5520 #endif /* CPRIMOD_SUPPORT */ 5521 5522 /*! 5523 * portmod_cpri_port_decap_flow_to_queue_mapping_set 5524 * 5525 * @brief Queue to Ordering info Index. 5526 * 5527 * @param [in] unit - unit id 5528 * @param [in] port - logical port 5529 * @param [in] flow_id - Flow Id. 5530 * @param [in] queue_num - Queue Number. 5531 */ 5532 #ifdef CPRIMOD_SUPPORT 5533 int portmod_cpri_port_decap_flow_to_queue_mapping_set(int unit, int port, uint32 flow_id, uint32 queue_num); 5534 #endif /* CPRIMOD_SUPPORT */ 5535 /*! 5536 * portmod_cpri_port_decap_flow_to_queue_mapping_get 5537 * 5538 * @brief Queue to Ordering info Index. 5539 * 5540 * @param [in] unit - unit id 5541 * @param [in] port - logical port 5542 * @param [in] flow_id - Flow Id. 5543 * @param [out] queue_num - Queue Number. 5544 */ 5545 #ifdef CPRIMOD_SUPPORT 5546 int portmod_cpri_port_decap_flow_to_queue_mapping_get(int unit, int port, uint32 flow_id, uint32* queue_num); 5547 #endif /* CPRIMOD_SUPPORT */ 5548 5549 /*! 5550 * portmod_cpri_port_decap_roe_ordering_info_set 5551 * 5552 * @brief Decap Ordering info. 5553 * 5554 * @param [in] unit - unit id 5555 * @param [in] port - logical port 5556 * @param [in] index - Index to ROE ordering info table. 5557 * @param [in] config - Decap Ordering info. 5558 */ 5559 #ifdef CPRIMOD_SUPPORT 5560 int portmod_cpri_port_decap_roe_ordering_info_set(int unit, int port, uint32 index, const cprimod_decap_ordering_info_entry_t* config); 5561 #endif /* CPRIMOD_SUPPORT */ 5562 /*! 5563 * portmod_cpri_port_decap_roe_ordering_info_get 5564 * 5565 * @brief Decap Ordering info. 5566 * 5567 * @param [in] unit - unit id 5568 * @param [in] port - logical port 5569 * @param [in] index - Index to ROE ordering info table. 5570 * @param [out] config - Decap Ordering info. 5571 */ 5572 #ifdef CPRIMOD_SUPPORT 5573 int portmod_cpri_port_decap_roe_ordering_info_get(int unit, int port, uint32 index, cprimod_decap_ordering_info_entry_t* config); 5574 #endif /* CPRIMOD_SUPPORT */ 5575 5576 /*! 5577 * portmod_cpri_port_decap_roe_ordering_sequence_offset_set 5578 * 5579 * @brief Encap Ordering info Offset. 5580 * 5581 * @param [in] unit - unit id 5582 * @param [in] port - logical port 5583 * @param [in] queue_num - Queue number. 5584 * @param [in] config - Encap Ordering info Offset for Queue. 5585 */ 5586 #ifdef CPRIMOD_SUPPORT 5587 int portmod_cpri_port_decap_roe_ordering_sequence_offset_set(int unit, int port, uint32 queue_num, const cprimod_cpri_ordering_info_offset_t* config); 5588 #endif /* CPRIMOD_SUPPORT */ 5589 /*! 5590 * portmod_cpri_port_decap_roe_ordering_sequence_offset_get 5591 * 5592 * @brief Encap Ordering info Offset. 5593 * 5594 * @param [in] unit - unit id 5595 * @param [in] port - logical port 5596 * @param [in] queue_num - Queue number. 5597 * @param [out] config - Encap Ordering info Offset for Queue. 5598 */ 5599 #ifdef CPRIMOD_SUPPORT 5600 int portmod_cpri_port_decap_roe_ordering_sequence_offset_get(int unit, int port, uint32 queue_num, cprimod_cpri_ordering_info_offset_t* config); 5601 #endif /* CPRIMOD_SUPPORT */ 5602 5603 5604 /*! 5605 * @struct portmod_tx_frame_tgen_config_s 5606 * @brief TGEN Configuration. 5607 */ 5608 #ifdef CPRIMOD_SUPPORT 5609 typedef struct portmod_tx_frame_tgen_config_s { 5610 uint32 tx_tgen_hfn; /**< Hyper Frame Number */ 5611 uint32 tx_tgen_bfn; /**< Radio Frame Number */ 5612 cprimod_tgen_counter_select_t tx_gen_bfn_hfn_sel; /**< 1 select bfn, 0 select hfn. */ 5613 uint64 tx_tgen_ts_offset; /**< timeout counter */ 5614 } portmod_tx_frame_tgen_config_t; 5615 5616 /* portmod_tx_frame_tgen_config_t initialization and validation */ 5617 int portmod_tx_frame_tgen_config_t_validate(int unit, const portmod_tx_frame_tgen_config_t* portmod_tx_frame_tgen_config); 5618 int portmod_tx_frame_tgen_config_t_init(int unit, portmod_tx_frame_tgen_config_t* portmod_tx_frame_tgen_config); 5619 5620 #endif /* CPRIMOD_SUPPORT */ 5621 /*! 5622 * portmod_cpri_port_tx_frame_tgen_config_set 5623 * 5624 * @brief TGEN configuration. 5625 * 5626 * @param [in] unit - unit id 5627 * @param [in] port - logical port 5628 * @param [in] config - TGEN Configuration. 5629 */ 5630 #ifdef CPRIMOD_SUPPORT 5631 int portmod_cpri_port_tx_frame_tgen_config_set(int unit, int port, const portmod_tx_frame_tgen_config_t* config); 5632 #endif /* CPRIMOD_SUPPORT */ 5633 /*! 5634 * portmod_cpri_port_tx_frame_tgen_config_get 5635 * 5636 * @brief TGEN configuration. 5637 * 5638 * @param [in] unit - unit id 5639 * @param [in] port - logical port 5640 * @param [out] config - TGEN Configuration. 5641 */ 5642 #ifdef CPRIMOD_SUPPORT 5643 int portmod_cpri_port_tx_frame_tgen_config_get(int unit, int port, portmod_tx_frame_tgen_config_t* config); 5644 #endif /* CPRIMOD_SUPPORT */ 5645 5646 /*! 5647 * portmod_cpri_port_tx_frame_tgen_enable 5648 * 5649 * @brief TGEN configuration. 5650 * 5651 * @param [in] unit - unit id 5652 * @param [in] port - logical port 5653 * @param [out] enable - Enable/Disable. 5654 */ 5655 #ifdef CPRIMOD_SUPPORT 5656 int portmod_cpri_port_tx_frame_tgen_enable(int unit, int port, uint32 enable); 5657 #endif /* CPRIMOD_SUPPORT */ 5658 5659 /*! 5660 * portmod_cpri_port_tx_frame_tgen_ts_offset_set 5661 * 5662 * @brief TGEN Offset. 5663 * 5664 * @param [in] unit - unit id 5665 * @param [in] port - logical port 5666 * @param [in] offset - Enable/Disable. 5667 */ 5668 #ifdef CPRIMOD_SUPPORT 5669 int portmod_cpri_port_tx_frame_tgen_ts_offset_set(int unit, int port, uint64 offset); 5670 #endif /* CPRIMOD_SUPPORT */ 5671 /*! 5672 * portmod_cpri_port_tx_frame_tgen_ts_offset_get 5673 * 5674 * @brief TGEN Offset. 5675 * 5676 * @param [in] unit - unit id 5677 * @param [in] port - logical port 5678 * @param [out] offset - Enable/Disable. 5679 */ 5680 #ifdef CPRIMOD_SUPPORT 5681 int portmod_cpri_port_tx_frame_tgen_ts_offset_get(int unit, int port, uint64* offset); 5682 #endif /* CPRIMOD_SUPPORT */ 5683 5684 /*! 5685 * portmod_cpri_port_tx_frame_next_hfn_get 5686 * 5687 * @brief Get next hyper frame number. 5688 * 5689 * @param [in] unit - unit id 5690 * @param [in] port - logical port 5691 * @param [out] hfn - HFN number. 5692 */ 5693 #ifdef CPRIMOD_SUPPORT 5694 int portmod_cpri_port_tx_frame_next_hfn_get(int unit, int port, uint32* hfn); 5695 #endif /* CPRIMOD_SUPPORT */ 5696 5697 /*! 5698 * portmod_cpri_port_tx_frame_next_bfn_get 5699 * 5700 * @brief Get next radio frame/master frame number. 5701 * 5702 * @param [in] unit - unit id 5703 * @param [in] port - logical port 5704 * @param [out] bfn - BFN number. 5705 */ 5706 #ifdef CPRIMOD_SUPPORT 5707 int portmod_cpri_port_tx_frame_next_bfn_get(int unit, int port, uint32* bfn); 5708 #endif /* CPRIMOD_SUPPORT */ 5709 5710 5711 /*! 5712 * @struct portmod_rsvd4_rx_flow_info_s 5713 * @brief Rx Flow Information. 5714 */ 5715 #ifdef CPRIMOD_SUPPORT 5716 typedef struct portmod_rsvd4_rx_flow_info_s { 5717 uint32 axc_id; /**< AxC/Queue ID. */ 5718 uint32 mask; /**< Msg Header Mask */ 5719 uint32 match_data; /**< Msg Header Match Data */ 5720 uint32 packet_size; /**< ROE Packet Payload size in Bits */ 5721 uint32 last_packet_size; /**< ROE last packet Payload size in Bits */ 5722 uint32 last_packet_num; /**< ROE last packet number if different size. */ 5723 uint32 stuffing_cnt; /**< stuffing count */ 5724 cprimod_rsvd4_msg_ts_mode_t msg_ts_mode; /**< msg ts mode */ 5725 uint32 msg_ts_count; /**< Msg timeslot count */ 5726 cprimod_rsvd4_frame_sync_mode_t frame_sync_mode; /**< frame sync mode. */ 5727 uint32 master_frame_offset; /**< Master Frame Offset (bfn_offset) */ 5728 uint32 message_number_offset; /**< Message Number Offset (rfrm_offset) */ 5729 uint32 container_block_count; /**< Container Block Count (number of bits in 10ms frame). */ 5730 uint32 queue_size; /**< Queue Size in bytes. */ 5731 uint32 priority; /**< WorkQueue Prioirty.Rx Only */ 5732 uint32 pad_size; /**< Pad Size. */ 5733 uint32 extra_pad_size; /**< Extra Pad Size. */ 5734 uint32 pad_enable; /**< Pad Enable. */ 5735 uint32 control_location; /**< Control TSN location. */ 5736 uint32 tsn_bitmap; /**< TSN bitmap. Rx only. */ 5737 } portmod_rsvd4_rx_flow_info_t; 5738 5739 /* portmod_rsvd4_rx_flow_info_t initialization and validation */ 5740 int portmod_rsvd4_rx_flow_info_t_validate(int unit, const portmod_rsvd4_rx_flow_info_t* portmod_rsvd4_rx_flow_info); 5741 int portmod_rsvd4_rx_flow_info_t_init(int unit, portmod_rsvd4_rx_flow_info_t* portmod_rsvd4_rx_flow_info); 5742 5743 #endif /* CPRIMOD_SUPPORT */ 5744 5745 /*! 5746 * @struct portmod_rsvd4_tx_flow_info_s 5747 * @brief Tx Flow Information. 5748 */ 5749 #ifdef CPRIMOD_SUPPORT 5750 typedef struct portmod_rsvd4_tx_flow_info_s { 5751 uint32 axc_id; /**< AxC/Queue ID. */ 5752 uint32 packet_size; /**< ROE Packet Payload size in Bits */ 5753 uint32 last_packet_size; /**< ROE last packet Payload size in Bits */ 5754 uint32 last_packet_num; /**< ROE last packet number if different size. */ 5755 uint32 stuffing_cnt; /**< stuffing count */ 5756 cprimod_rsvd4_msg_ts_mode_t msg_ts_mode; /**< msg ts mode */ 5757 uint32 msg_ts_count; /**< Msg timeslot count */ 5758 cprimod_rsvd4_frame_sync_mode_t frame_sync_mode; /**< frame sync mode. */ 5759 uint32 master_frame_offset; /**< Master Frame Offset (bfn_offset) */ 5760 uint32 message_number_offset; /**< Message Number Offset (rfrm_offset) */ 5761 uint32 container_block_count; /**< Container Block Size (number of bits in 10ms frame). */ 5762 uint32 buffer_size; /**< Buffer Size in bytes. */ 5763 uint32 cycle_size; /**< Number of Packet in Queue. */ 5764 uint32 use_ts_dbm; /**< Use ts dbm (secondary dbm) Tx Only. */ 5765 uint32 ts_dbm_profile_num; /**< ts dbm (secondary dbm) Profile Number. Tx Only */ 5766 uint32 num_active_slot; /**< ts dbm (secondary dbm) number of slots. Tx Only */ 5767 uint32 msg_addr; /**< msg addr. Tx Only. */ 5768 uint32 msg_type; /**< msg type.Tx Only */ 5769 uint32 msg_ts_offset; /**< msg type.Tx Only */ 5770 uint32 pad_size; /**< Pad Size. */ 5771 uint32 extra_pad_size; /**< Extra Pad Size. */ 5772 uint32 pad_enable; /**< Pad Enable. */ 5773 uint32 control_location; /**< Control TSN location. */ 5774 } portmod_rsvd4_tx_flow_info_t; 5775 5776 /* portmod_rsvd4_tx_flow_info_t initialization and validation */ 5777 int portmod_rsvd4_tx_flow_info_t_validate(int unit, const portmod_rsvd4_tx_flow_info_t* portmod_rsvd4_tx_flow_info); 5778 int portmod_rsvd4_tx_flow_info_t_init(int unit, portmod_rsvd4_tx_flow_info_t* portmod_rsvd4_tx_flow_info); 5779 5780 #endif /* CPRIMOD_SUPPORT */ 5781 /*! 5782 * portmod_cpri_port_rsvd4_rx_flow_add 5783 * 5784 * @brief RSVD4 rx data flow add. 5785 * 5786 * @param [in] unit - unit id 5787 * @param [in] port - logical port 5788 * @param [in] flow_id - Flow ID. 5789 * @param [in] info - Flow Information. 5790 */ 5791 #ifdef CPRIMOD_SUPPORT 5792 int portmod_cpri_port_rsvd4_rx_flow_add(int unit, int port, uint32 flow_id, const portmod_rsvd4_rx_flow_info_t* info); 5793 #endif /* CPRIMOD_SUPPORT */ 5794 5795 /*! 5796 * portmod_cpri_port_rsvd4_rx_flow_delete 5797 * 5798 * @brief RSVD4 rx data flow delete. 5799 * 5800 * @param [in] unit - unit id 5801 * @param [in] port - logical port 5802 * @param [in] flow_id - Flow ID. 5803 */ 5804 #ifdef CPRIMOD_SUPPORT 5805 int portmod_cpri_port_rsvd4_rx_flow_delete(int unit, int port, uint32 flow_id); 5806 #endif /* CPRIMOD_SUPPORT */ 5807 5808 /*! 5809 * portmod_cpri_port_rsvd4_tx_flow_add 5810 * 5811 * @brief RSVD4 Tx Flow add. 5812 * 5813 * @param [in] unit - unit id 5814 * @param [in] port - logical port 5815 * @param [in] flow_id - Flow ID. 5816 * @param [in] info - Flow Information. 5817 */ 5818 #ifdef CPRIMOD_SUPPORT 5819 int portmod_cpri_port_rsvd4_tx_flow_add(int unit, int port, uint32 flow_id, const portmod_rsvd4_tx_flow_info_t* info); 5820 #endif /* CPRIMOD_SUPPORT */ 5821 5822 /*! 5823 * portmod_cpri_port_rsvd4_tx_flow_delete 5824 * 5825 * @brief RSVD4 tx data flow delete. 5826 * 5827 * @param [in] unit - unit id 5828 * @param [in] port - logical port 5829 * @param [in] flow_id - Flow ID. 5830 */ 5831 #ifdef CPRIMOD_SUPPORT 5832 int portmod_cpri_port_rsvd4_tx_flow_delete(int unit, int port, uint32 flow_id); 5833 #endif /* CPRIMOD_SUPPORT */ 5834 5835 /*! 5836 * portmod_cpri_port_rsvd4_dbm_entry_set 5837 * 5838 * @brief RSVD4 Set/Get DBM Profile. 5839 * 5840 * @param [in] unit - unit id 5841 * @param [in] port - logical port 5842 * @param [in] profile_id - DBM Profile ID. 5843 * @param [in] profile - DBM Profile Information. 5844 */ 5845 #ifdef CPRIMOD_SUPPORT 5846 int portmod_cpri_port_rsvd4_dbm_entry_set(int unit, int port, uint32 profile_id, const cprimod_dbm_rule_entry_t* profile); 5847 #endif /* CPRIMOD_SUPPORT */ 5848 /*! 5849 * portmod_cpri_port_rsvd4_dbm_entry_get 5850 * 5851 * @brief RSVD4 Set/Get DBM Profile. 5852 * 5853 * @param [in] unit - unit id 5854 * @param [in] port - logical port 5855 * @param [in] profile_id - DBM Profile ID. 5856 * @param [out] profile - DBM Profile Information. 5857 */ 5858 #ifdef CPRIMOD_SUPPORT 5859 int portmod_cpri_port_rsvd4_dbm_entry_get(int unit, int port, uint32 profile_id, cprimod_dbm_rule_entry_t* profile); 5860 #endif /* CPRIMOD_SUPPORT */ 5861 5862 /*! 5863 * portmod_cpri_port_rsvd4_secondary_dbm_entry_set 5864 * 5865 * @brief RSVD4 Set/Get Secondary DBM Profile. 5866 * 5867 * @param [in] unit - unit id 5868 * @param [in] port - logical port 5869 * @param [in] profile_id - DBM Profile ID. 5870 * @param [in] profile - Secondary DBM Profile Information. 5871 */ 5872 #ifdef CPRIMOD_SUPPORT 5873 int portmod_cpri_port_rsvd4_secondary_dbm_entry_set(int unit, int port, uint32 profile_id, const cprimod_secondary_dbm_rule_entry_t* profile); 5874 #endif /* CPRIMOD_SUPPORT */ 5875 /*! 5876 * portmod_cpri_port_rsvd4_secondary_dbm_entry_get 5877 * 5878 * @brief RSVD4 Set/Get Secondary DBM Profile. 5879 * 5880 * @param [in] unit - unit id 5881 * @param [in] port - logical port 5882 * @param [in] profile_id - DBM Profile ID. 5883 * @param [out] profile - Secondary DBM Profile Information. 5884 */ 5885 #ifdef CPRIMOD_SUPPORT 5886 int portmod_cpri_port_rsvd4_secondary_dbm_entry_get(int unit, int port, uint32 profile_id, cprimod_secondary_dbm_rule_entry_t* profile); 5887 #endif /* CPRIMOD_SUPPORT */ 5888 5889 /*! 5890 * portmod_cpri_port_rsvd4_modulo_rule_entry_set 5891 * 5892 * @brief Modulo Rule Entry Set/Get. 5893 * 5894 * @param [in] unit - unit id 5895 * @param [in] port - logical port 5896 * @param [in] modulo_rule_num - Modulo Rule Number 0-71 for data 0-15 for control. 5897 * @param [in] modulo_rule_type - Modulo Rule Type, Data or Ctrl. 5898 * @param [in] modulo_rule - Modulo Rule Entry. 5899 */ 5900 #ifdef CPRIMOD_SUPPORT 5901 int portmod_cpri_port_rsvd4_modulo_rule_entry_set(int unit, int port, uint32 modulo_rule_num, cprimod_transmission_rule_type_t modulo_rule_type, const cprimod_modulo_rule_entry_t* modulo_rule); 5902 #endif /* CPRIMOD_SUPPORT */ 5903 /*! 5904 * portmod_cpri_port_rsvd4_modulo_rule_entry_get 5905 * 5906 * @brief Modulo Rule Entry Set/Get. 5907 * 5908 * @param [in] unit - unit id 5909 * @param [in] port - logical port 5910 * @param [in] modulo_rule_num - Modulo Rule Number 0-71 for data 0-15 for control. 5911 * @param [in] modulo_rule_type - Modulo Rule Type, Data or Ctrl. 5912 * @param [out] modulo_rule - Modulo Rule Entry. 5913 */ 5914 #ifdef CPRIMOD_SUPPORT 5915 int portmod_cpri_port_rsvd4_modulo_rule_entry_get(int unit, int port, uint32 modulo_rule_num, cprimod_transmission_rule_type_t modulo_rule_type, cprimod_modulo_rule_entry_t* modulo_rule); 5916 #endif /* CPRIMOD_SUPPORT */ 5917 5918 /*! 5919 * portmod_cpri_port_rsvd4_dbm_position_entry_set 5920 * 5921 * @brief Dual Bitmap Position Table Entry Set/Get. 5922 * 5923 * @param [in] unit - unit id 5924 * @param [in] port - logical port 5925 * @param [in] index - Index to Position Table Entry. 5926 * @param [in] pos_entry - DBM Position Table Entry. 5927 */ 5928 #ifdef CPRIMOD_SUPPORT 5929 int portmod_cpri_port_rsvd4_dbm_position_entry_set(int unit, int port, uint32 index, const cprimod_dbm_pos_table_entry_t* pos_entry); 5930 #endif /* CPRIMOD_SUPPORT */ 5931 /*! 5932 * portmod_cpri_port_rsvd4_dbm_position_entry_get 5933 * 5934 * @brief Dual Bitmap Position Table Entry Set/Get. 5935 * 5936 * @param [in] unit - unit id 5937 * @param [in] port - logical port 5938 * @param [in] index - Index to Position Table Entry. 5939 * @param [out] pos_entry - DBM Position Table Entry. 5940 */ 5941 #ifdef CPRIMOD_SUPPORT 5942 int portmod_cpri_port_rsvd4_dbm_position_entry_get(int unit, int port, uint32 index, cprimod_dbm_pos_table_entry_t* pos_entry); 5943 #endif /* CPRIMOD_SUPPORT */ 5944 5945 /*! 5946 * portmod_cpri_port_rsvd4_rx_master_frame_sync_config_set 5947 * 5948 * @brief Set/Get Rx Master Frame Synchronizaiton 5949 * 5950 * @param [in] unit - unit id 5951 * @param [in] port - logical port 5952 * @param [in] master_frame_number - Master Frame Number when start countng. 5953 * @param [in] master_frame_start_time - Maser Frame Time to start count. 5954 */ 5955 #ifdef CPRIMOD_SUPPORT 5956 int portmod_cpri_port_rsvd4_rx_master_frame_sync_config_set(int unit, int port, uint32 master_frame_number, uint64 master_frame_start_time); 5957 #endif /* CPRIMOD_SUPPORT */ 5958 /*! 5959 * portmod_cpri_port_rsvd4_rx_master_frame_sync_config_get 5960 * 5961 * @brief Set/Get Rx Master Frame Synchronizaiton 5962 * 5963 * @param [in] unit - unit id 5964 * @param [in] port - logical port 5965 * @param [out] master_frame_number - Master Frame Number when start countng. 5966 * @param [out] master_frame_start_time - Master Frame Time to start count. 5967 */ 5968 #ifdef CPRIMOD_SUPPORT 5969 int portmod_cpri_port_rsvd4_rx_master_frame_sync_config_get(int unit, int port, uint32* master_frame_number, uint64* master_frame_start_time); 5970 #endif /* CPRIMOD_SUPPORT */ 5971 5972 5973 /*! 5974 * @struct portmod_vcos_speed_config_s 5975 * @brief Speed configuration 5976 */ 5977 typedef struct portmod_vcos_speed_config_s { 5978 uint32 speed; /**< speed */ 5979 uint8 num_lanes; /**< number of lanes */ 5980 uint8 ieee_mode; /**< IEEE mode */ 5981 uint8 higig_mode; /**< HIGIG mode */ 5982 uint8 txpi_mode; /**< TXPI mode */ 5983 uint8 eth_of_mixed_mode; /**< ETH port of mixed mode */ 5984 portmod_core_port_enet_cpri_type_t port_type; /**< port type */ 5985 } portmod_vcos_speed_config_t; 5986 5987 /* portmod_vcos_speed_config_t initialization and validation */ 5988 int portmod_vcos_speed_config_t_validate(int unit, const portmod_vcos_speed_config_t* portmod_vcos_speed_config); 5989 int portmod_vcos_speed_config_t_init(int unit, portmod_vcos_speed_config_t* portmod_vcos_speed_config); 5990 5991 5992 /*! 5993 * @struct portmod_dual_vcos_s 5994 * @brief Dual VCOs 5995 */ 5996 typedef struct portmod_dual_vcos_s { 5997 uint32 vco_0; /**< VCO_0 */ 5998 uint32 vco_1; /**< VCO_1 */ 5999 } portmod_dual_vcos_t; 6000 6001 /* portmod_dual_vcos_t initialization and validation */ 6002 int portmod_dual_vcos_t_validate(int unit, const portmod_dual_vcos_t* portmod_dual_vcos); 6003 int portmod_dual_vcos_t_init(int unit, portmod_dual_vcos_t* portmod_dual_vcos); 6004 6005 /*! 6006 * portmod_pm_supported_vcos_get 6007 * 6008 * @brief Get Supported VCOs 6009 * 6010 * @param [in] unit - unit id 6011 * @param [in] port - logical port 6012 * @param [in] pm_type - PM type 6013 * @param [in] speed_config_list - port speed config param 6014 * @param [in] size - size of speed config list 6015 * @param [out] dual_vco - supported VCOs 6016 */ 6017 int portmod_pm_supported_vcos_get(int unit, int port, portmod_dispatch_type_t pm_type, const portmod_vcos_speed_config_t* speed_config_list, int size, portmod_dual_vcos_t* dual_vco); 6018 6019 /*! 6020 * portmod_port_vcos_get 6021 * 6022 * @brief Get supported VCOs 6023 * 6024 * @param [in] unit - unit id 6025 * @param [in] port - logical port 6026 * @param [in] speed_config_list - port speed config param 6027 * @param [in] size - size of speed config list 6028 * @param [out] dual_vco - supported VCOs 6029 */ 6030 int portmod_port_vcos_get(int unit, int port, const portmod_vcos_speed_config_t* speed_config_list, int size, portmod_dual_vcos_t* dual_vco); 6031 6032 /*! 6033 * portmod_port_mac_timestamp_enable_set 6034 * 6035 * @brief Port mac timestamp enable set/get 6036 * 6037 * @param [in] unit - unit id 6038 * @param [in] port - logical port 6039 * @param [in] enable - set port mac timestamp enable 6040 */ 6041 int portmod_port_mac_timestamp_enable_set(int unit, int port, int enable); 6042 /*! 6043 * portmod_port_mac_timestamp_enable_get 6044 * 6045 * @brief Port mac timestamp enable set/get 6046 * 6047 * @param [in] unit - unit id 6048 * @param [in] port - logical port 6049 * @param [out] enable - get port mac timestamp enable 6050 */ 6051 int portmod_port_mac_timestamp_enable_get(int unit, int port, int* enable); 6052 6053 /*! 6054 * portmod_cpri_port_rx_cw_sync_info_get 6055 * 6056 * @brief CPRI Sync information. 6057 * 6058 * @param [in] unit - unit id 6059 * @param [in] port - logical port 6060 * @param [out] hyper_frame_num - Hyper Frame Number. 6061 * @param [out] radio_frame_num - Radio Frame Number. 6062 */ 6063 #ifdef CPRIMOD_SUPPORT 6064 int portmod_cpri_port_rx_cw_sync_info_get(int unit, int port, uint32* hyper_frame_num, uint32* radio_frame_num); 6065 #endif /* CPRIMOD_SUPPORT */ 6066 6067 #ifdef CPRIMOD_SUPPORT 6068 typedef _shr_cpri_cw_l1_protocol_info_t portmod_cpri_cw_l1_protocol_info_t; 6069 6070 #endif /* CPRIMOD_SUPPORT */ 6071 /*! 6072 * portmod_cpri_port_rx_cw_l1_signal_info_get 6073 * 6074 * @brief Get L1 portocol information. 6075 * 6076 * @param [in] unit - unit id 6077 * @param [in] port - logical port 6078 * @param [out] l1_info - L1 information 6079 */ 6080 #ifdef CPRIMOD_SUPPORT 6081 int portmod_cpri_port_rx_cw_l1_signal_info_get(int unit, int port, portmod_cpri_cw_l1_protocol_info_t* l1_info); 6082 #endif /* CPRIMOD_SUPPORT */ 6083 6084 /*! 6085 * portmod_cpri_port_rx_cw_l1_signal_signal_protection_set 6086 * 6087 * @brief Set/Get L1 Protection. 6088 * 6089 * @param [in] unit - unit id 6090 * @param [in] port - logical port 6091 * @param [in] signal_map - Signal List - Bit Map 6092 * @param [in] enable - 0 - Disable 1- Enable 6093 */ 6094 #ifdef CPRIMOD_SUPPORT 6095 int portmod_cpri_port_rx_cw_l1_signal_signal_protection_set(int unit, int port, uint32 signal_map, uint32 enable); 6096 #endif /* CPRIMOD_SUPPORT */ 6097 /*! 6098 * portmod_cpri_port_rx_cw_l1_signal_signal_protection_get 6099 * 6100 * @brief Set/Get L1 Protection. 6101 * 6102 * @param [in] unit - unit id 6103 * @param [in] port - logical port 6104 * @param [in] signal_map - Signal List - Bit Map 6105 * @param [out] enable - Bit Map - Corresponding Bit will have either enable 1 or disable 0 6106 */ 6107 #ifdef CPRIMOD_SUPPORT 6108 int portmod_cpri_port_rx_cw_l1_signal_signal_protection_get(int unit, int port, uint32 signal_map, uint32* enable); 6109 #endif /* CPRIMOD_SUPPORT */ 6110 6111 #ifdef CPRIMOD_SUPPORT 6112 typedef _shr_cpri_hdlc_fcs_size_t portmod_cpri_hdlc_fcs_size_t; 6113 6114 #endif /* CPRIMOD_SUPPORT */ 6115 #ifdef CPRIMOD_SUPPORT 6116 #define PORTMOD_CPRI_HDLC_FCS_SIZE_8_BITS _shrCpriHdlcFcsSize8Bits 6117 #define PORTMOD_CPRI_HDLC_FCS_SIZE_16_BITS _shrCpriHdlcFcsSize16Bits 6118 #define PORTMOD_CPRI_HDLC_FCS_SIZE_32_BITS _shrCpriHdlcFcsSize32Bits 6119 #endif /* CPRIMOD_SUPPORT */ 6120 6121 #ifdef CPRIMOD_SUPPORT 6122 typedef _shr_cpri_hdlc_filling_flag_pattern_t portmod_cpri_hdlc_filling_flag_pattern_t; 6123 6124 #endif /* CPRIMOD_SUPPORT */ 6125 #ifdef CPRIMOD_SUPPORT 6126 #define PORTMOD_CPRI_HDLC_FILLING_FLAG_PATTERN_7E _shrCpriHdlcFillingFlagPattern7E 6127 #define PORTMOD_CPRI_HDLC_FILLING_FLAG_PATTERN_7F _shrCpriHdlcFillingFlagPattern7F 6128 #define PORTMOD_CPRI_HDLC_FILLING_FLAG_PATTERN_FF _shrCpriHdlcFillingFlagPatternFF 6129 #endif /* CPRIMOD_SUPPORT */ 6130 6131 #ifdef CPRIMOD_SUPPORT 6132 typedef _shr_cpri_hdlc_flag_size_t portmod_cpri_hdlc_num_flag_bytes_t; 6133 6134 #endif /* CPRIMOD_SUPPORT */ 6135 #ifdef CPRIMOD_SUPPORT 6136 #define PORTMOD_HDLC_FLAG_SIZE_1_BYTE _shrCpriHdlcNumFlagSizeOneByte 6137 #define PORTMOD_HDLC_FLAG_SIZE_2_BYTE _shrCpriHdlcNumFlagSizeTwoByte 6138 #endif /* CPRIMOD_SUPPORT */ 6139 6140 #ifdef CPRIMOD_SUPPORT 6141 typedef _shr_cpri_hdlc_crc_mode_t portmod_cpri_crc_mode_t; 6142 6143 #endif /* CPRIMOD_SUPPORT */ 6144 #ifdef CPRIMOD_SUPPORT 6145 #define PORTMOD_CPRI_HDLC_CRC_MODE_APPEND _shrCpriHdlcCrcAppend 6146 #define PORTMOD_CPRI_HDLC_CRC_MODE_REPLACE _shrCpriHdlcCrcReplace 6147 #define PORTMOD_CPRI_HDLC_CRC_MODE_NO_UPDATE _shrCpriHdlcCrcNoUpdate 6148 #endif /* CPRIMOD_SUPPORT */ 6149 6150 #ifdef CPRIMOD_SUPPORT 6151 typedef _shr_cpri_hdlc_crc_init_val_t portmod_cpri_hdlc_crc_init_val_t; 6152 6153 #endif /* CPRIMOD_SUPPORT */ 6154 #ifdef CPRIMOD_SUPPORT 6155 #define PORTMOD_CPRI_HDLC_CRC_INIT_VAL_ALL_0 _shrCpriHdlcCrcInitValAll0 6156 #define PORTMOD_CPRI_HDLC_CRC_INIT_VAL_ALL_1 _shrCpriHdlcCrcInitValAll1 6157 #endif /* CPRIMOD_SUPPORT */ 6158 6159 6160 /*! 6161 * @struct portmod_cpri_slow_hdlc_config_info_s 6162 * @brief CPRI Slow HDLC configuration information. 6163 */ 6164 #ifdef CPRIMOD_SUPPORT 6165 typedef struct portmod_cpri_slow_hdlc_config_info_s { 6166 portmod_cpri_crc_mode_t tx_crc_mode; /**< Tx CRC Mode. Append/Replace/NoUpdate. */ 6167 portmod_cpri_hdlc_num_flag_bytes_t tx_flag_size; /**< Tx Num of Flag Bytes 1 or 2. */ 6168 portmod_cpri_hdlc_filling_flag_pattern_t tx_filling_flag_pattern; /**< Tx Filling Flag Pattern. */ 6169 portmod_cpri_hdlc_crc_init_val_t crc_init_val; /**< CRC init Value, all 0s or 1s. */ 6170 int use_fe_mac; /**< Use FE Mac instead of HDLC. */ 6171 int crc_byte_swap; /**< 0 - 15..0 1- [7:0][15:8] */ 6172 int no_fcs_err_check; /**< Turn off FCS error check. */ 6173 uint32 cw_sel; /**< control word subchannel Xs */ 6174 uint32 cw_size; /**< control word size */ 6175 portmod_cpri_hdlc_fcs_size_t fcs_size; /**< 8,16 or 16 bits FCS. */ 6176 int runt_frame_drop; /**< Indicate frame smaller than 16 bits (runt) be dropped. */ 6177 int long_frame_drop; /**< Indicate frame longer than max frame size be dropped. */ 6178 uint32 min_frame_size; /**< Min HDLC Frame Size in Bits (including FCS). */ 6179 uint32 max_frame_size; /**< Max HDLC Frame Size in Bits (including FCS). */ 6180 uint32 queue_num; /**< Queue Number */ 6181 uint32 priority; /**< Priority */ 6182 uint32 queue_size; /**< Queue Size in Bytes */ 6183 uint32 cycle_size; /**< Cycle Size */ 6184 uint32 buffer_size; /**< Buffer Size */ 6185 } portmod_cpri_slow_hdlc_config_info_t; 6186 6187 /* portmod_cpri_slow_hdlc_config_info_t initialization and validation */ 6188 int portmod_cpri_slow_hdlc_config_info_t_validate(int unit, const portmod_cpri_slow_hdlc_config_info_t* portmod_cpri_slow_hdlc_config_info); 6189 int portmod_cpri_slow_hdlc_config_info_t_init(int unit, portmod_cpri_slow_hdlc_config_info_t* portmod_cpri_slow_hdlc_config_info); 6190 6191 #endif /* CPRIMOD_SUPPORT */ 6192 /*! 6193 * portmod_cpri_port_cw_slow_hdlc_config_set 6194 * 6195 * @brief HDLC Config Set/Get. 6196 * 6197 * @param [in] unit - unit id 6198 * @param [in] port - logical port 6199 * @param [in] config_info - Config info. 6200 */ 6201 #ifdef CPRIMOD_SUPPORT 6202 int portmod_cpri_port_cw_slow_hdlc_config_set(int unit, int port, const portmod_cpri_slow_hdlc_config_info_t* config_info); 6203 #endif /* CPRIMOD_SUPPORT */ 6204 /*! 6205 * portmod_cpri_port_cw_slow_hdlc_config_get 6206 * 6207 * @brief HDLC Config Set/Get. 6208 * 6209 * @param [in] unit - unit id 6210 * @param [in] port - logical port 6211 * @param [out] config_info - Config info. 6212 */ 6213 #ifdef CPRIMOD_SUPPORT 6214 int portmod_cpri_port_cw_slow_hdlc_config_get(int unit, int port, portmod_cpri_slow_hdlc_config_info_t* config_info); 6215 #endif /* CPRIMOD_SUPPORT */ 6216 6217 6218 /*! 6219 * @struct portmod_cpri_fast_eth_config_info_s 6220 * @brief CPRI Fast Eth configuration information. 6221 */ 6222 #ifdef CPRIMOD_SUPPORT 6223 typedef struct portmod_cpri_fast_eth_config_info_s { 6224 portmod_cpri_crc_mode_t tx_crc_mode; /**< Tx CRC Mode. Append/Replace/NoUpdate. */ 6225 uint32 schan_start; /**< sub channel start location */ 6226 uint32 schan_size; /**< sub channel size. */ 6227 uint32 cw_sel; /**< control word subchannel Xs */ 6228 uint32 cw_size; /**< control word size */ 6229 uint32 min_packet_size; /**< Min Packet Size in Bytes. */ 6230 uint32 max_packet_size; /**< Max Packet Size in Bytes. */ 6231 int min_packet_drop; /**< Indicate frame smaller than min_packet_size be dropped. */ 6232 int max_packet_drop; /**< Indicate frame larger than max packet size be dropped. */ 6233 int strip_crc; /**< CRC bytes are drop and not forwarded to encap. */ 6234 uint32 min_ipg; /**< Min IPG Size in Bytes. */ 6235 uint32 queue_num; /**< Queue Number */ 6236 uint32 priority; /**< Priority */ 6237 uint32 queue_size; /**< Queue Size in Bytes */ 6238 uint32 cycle_size; /**< Cycle Size */ 6239 uint32 buffer_size; /**< Buffer Size */ 6240 int no_fcs_err_check; /**< Turn off FCS error check. */ 6241 } portmod_cpri_fast_eth_config_info_t; 6242 6243 /* portmod_cpri_fast_eth_config_info_t initialization and validation */ 6244 int portmod_cpri_fast_eth_config_info_t_validate(int unit, const portmod_cpri_fast_eth_config_info_t* portmod_cpri_fast_eth_config_info); 6245 int portmod_cpri_fast_eth_config_info_t_init(int unit, portmod_cpri_fast_eth_config_info_t* portmod_cpri_fast_eth_config_info); 6246 6247 #endif /* CPRIMOD_SUPPORT */ 6248 /*! 6249 * portmod_cpri_port_cw_fast_eth_config_set 6250 * 6251 * @brief Fast ETH Config Set/Get. 6252 * 6253 * @param [in] unit - unit id 6254 * @param [in] port - logical port 6255 * @param [in] config_info - Config info. 6256 */ 6257 #ifdef CPRIMOD_SUPPORT 6258 int portmod_cpri_port_cw_fast_eth_config_set(int unit, int port, const portmod_cpri_fast_eth_config_info_t* config_info); 6259 #endif /* CPRIMOD_SUPPORT */ 6260 /*! 6261 * portmod_cpri_port_cw_fast_eth_config_get 6262 * 6263 * @brief Fast ETH Config Set/Get. 6264 * 6265 * @param [in] unit - unit id 6266 * @param [in] port - logical port 6267 * @param [out] config_info - Config info. 6268 */ 6269 #ifdef CPRIMOD_SUPPORT 6270 int portmod_cpri_port_cw_fast_eth_config_get(int unit, int port, portmod_cpri_fast_eth_config_info_t* config_info); 6271 #endif /* CPRIMOD_SUPPORT */ 6272 6273 typedef _shr_cpri_vsd_control_subchan_num_bytes_t portmod_cpri_vsd_control_subchan_num_bytes_t; 6274 6275 #define PORTMOD_CPRI_VSD_CONTROL_SUBCHAN_NUM_BYTES_1 _shrVsdCtrlSubchanNumBytes1 6276 #define PORTMOD_CPRI_VSD_CONTROL_SUBCHAN_NUM_BYTES_2 _shrVsdCtrlSubchanNumBytes2 6277 #define PORTMOD_CPRI_VSD_CONTROL_SUBCHAN_NUM_BYTES_4 _shrVsdCtrlSubchanNumBytes4 6278 6279 typedef _shr_cpri_vsd_control_subchan_size_t portmod_cpri_vsd_control_subchan_size_t; 6280 6281 #define PORTMOD_CPRI_VSD_CONTROL_SUBCHAN_SIZE_2 _shrVsdCtrlSubchanSize2 6282 #define PORTMOD_CPRI_VSD_CONTROL_SUBCHAN_SIZE_4 _shrVsdCtrlSubchanSize4 6283 6284 typedef _shr_cpri_vsd_control_flow_num_bytes_t portmod_cpri_vsd_control_flow_num_bytes_t; 6285 6286 #define PORTMOD_CPRI_CONTROL_FLOW_NUM_BYTES_2 _shrVsdCtrlFlowNumBytes2 6287 #define PORTMOD_CPRI_CONTROL_FLOW_NUM_BYTES_4 _shrVsdCtrlFlowNumBytes2 6288 6289 6290 /*! 6291 * @struct portmod_cpri_rx_vsd_config_info_s 6292 * @brief CPRI Rx VSD configuration information. 6293 */ 6294 #ifdef CPRIMOD_SUPPORT 6295 typedef struct portmod_cpri_rx_vsd_config_info_s { 6296 uint32 subchan_start; /**< sub channel start location */ 6297 portmod_cpri_vsd_control_subchan_size_t subchan_size; /**< sub channel size. */ 6298 portmod_cpri_vsd_control_subchan_num_bytes_t subchan_bytes; /**< Number of bytes */ 6299 uint32 subchan_steps; /**< control word steps */ 6300 portmod_cpri_vsd_control_flow_num_bytes_t flow_bytes; /**< Number of Bytes per flow. */ 6301 uint32 queue_num; /**< Queue Number */ 6302 uint32 rsvd_sector_mask[4]; /**< Reserved Sector Mask up to 128 bits total. */ 6303 uint32 priority; /**< Priority */ 6304 uint32 queue_size; /**< Queue Size in Bytes */ 6305 } portmod_cpri_rx_vsd_config_info_t; 6306 6307 /* portmod_cpri_rx_vsd_config_info_t initialization and validation */ 6308 int portmod_cpri_rx_vsd_config_info_t_validate(int unit, const portmod_cpri_rx_vsd_config_info_t* portmod_cpri_rx_vsd_config_info); 6309 int portmod_cpri_rx_vsd_config_info_t_init(int unit, portmod_cpri_rx_vsd_config_info_t* portmod_cpri_rx_vsd_config_info); 6310 6311 #endif /* CPRIMOD_SUPPORT */ 6312 /*! 6313 * portmod_cpri_port_rx_vsd_config_set 6314 * 6315 * @brief CPRI Rx VSD Config Set/Get. 6316 * 6317 * @param [in] unit - unit id 6318 * @param [in] port - logical port 6319 * @param [in] config_info - Config info. 6320 */ 6321 #ifdef CPRIMOD_SUPPORT 6322 int portmod_cpri_port_rx_vsd_config_set(int unit, int port, const portmod_cpri_rx_vsd_config_info_t* config_info); 6323 #endif /* CPRIMOD_SUPPORT */ 6324 /*! 6325 * portmod_cpri_port_rx_vsd_config_get 6326 * 6327 * @brief CPRI Rx VSD Config Set/Get. 6328 * 6329 * @param [in] unit - unit id 6330 * @param [in] port - logical port 6331 * @param [out] config_info - Config info. 6332 */ 6333 #ifdef CPRIMOD_SUPPORT 6334 int portmod_cpri_port_rx_vsd_config_get(int unit, int port, portmod_cpri_rx_vsd_config_info_t* config_info); 6335 #endif /* CPRIMOD_SUPPORT */ 6336 6337 6338 /*! 6339 * @struct portmod_cpri_tx_vsd_config_info_s 6340 * @brief CPRI Tx VSD configuration information. 6341 */ 6342 #ifdef CPRIMOD_SUPPORT 6343 typedef struct portmod_cpri_tx_vsd_config_info_s { 6344 uint32 subchan_start; /**< sub channel start location */ 6345 portmod_cpri_vsd_control_subchan_size_t subchan_size; /**< sub channel size. */ 6346 portmod_cpri_vsd_control_subchan_num_bytes_t subchan_bytes; /**< Number of bytes */ 6347 uint32 subchan_steps; /**< control word steps */ 6348 portmod_cpri_vsd_control_flow_num_bytes_t flow_bytes; /**< Number of Bytes per flow. */ 6349 uint32 queue_num; /**< Queue Number */ 6350 uint32 rsvd_sector_mask[4]; /**< Reserved Sector Mask up to 128 bits total. */ 6351 uint32 buffer_size; /**< Buffer Size in Bytes */ 6352 uint32 cycle_size; /**< Cycle Size */ 6353 int byte_order_swap; /**< Byte Order Swap. */ 6354 } portmod_cpri_tx_vsd_config_info_t; 6355 6356 /* portmod_cpri_tx_vsd_config_info_t initialization and validation */ 6357 int portmod_cpri_tx_vsd_config_info_t_validate(int unit, const portmod_cpri_tx_vsd_config_info_t* portmod_cpri_tx_vsd_config_info); 6358 int portmod_cpri_tx_vsd_config_info_t_init(int unit, portmod_cpri_tx_vsd_config_info_t* portmod_cpri_tx_vsd_config_info); 6359 6360 #endif /* CPRIMOD_SUPPORT */ 6361 /*! 6362 * portmod_cpri_port_tx_vsd_config_set 6363 * 6364 * @brief CPRI Tx VSD Config Set/Get. 6365 * 6366 * @param [in] unit - unit id 6367 * @param [in] port - logical port 6368 * @param [in] config_info - Config info. 6369 */ 6370 #ifdef CPRIMOD_SUPPORT 6371 int portmod_cpri_port_tx_vsd_config_set(int unit, int port, const portmod_cpri_tx_vsd_config_info_t* config_info); 6372 #endif /* CPRIMOD_SUPPORT */ 6373 /*! 6374 * portmod_cpri_port_tx_vsd_config_get 6375 * 6376 * @brief CPRI Tx VSD Config Set/Get. 6377 * 6378 * @param [in] unit - unit id 6379 * @param [in] port - logical port 6380 * @param [out] config_info - Config info. 6381 */ 6382 #ifdef CPRIMOD_SUPPORT 6383 int portmod_cpri_port_tx_vsd_config_get(int unit, int port, portmod_cpri_tx_vsd_config_info_t* config_info); 6384 #endif /* CPRIMOD_SUPPORT */ 6385 6386 #ifdef CPRIMOD_SUPPORT 6387 typedef _shr_cpri_rx_vsd_flow_info_t portmod_cpri_rx_vsd_flow_info_t; 6388 6389 #endif /* CPRIMOD_SUPPORT */ 6390 /*! 6391 * portmod_cpri_port_rx_vsd_flow_add 6392 * 6393 * @brief CPRI Rx VSD Config Flow Add. 6394 * 6395 * @param [in] unit - unit id 6396 * @param [in] port - logical port 6397 * @param [in] group_id - group id 6398 * @param [in] flow_info - Flow info. 6399 */ 6400 #ifdef CPRIMOD_SUPPORT 6401 int portmod_cpri_port_rx_vsd_flow_add(int unit, int port, uint32 group_id, const portmod_cpri_rx_vsd_flow_info_t* flow_info); 6402 #endif /* CPRIMOD_SUPPORT */ 6403 6404 /*! 6405 * portmod_cpri_port_rx_vsd_flow_get 6406 * 6407 * @brief CPRI Rx VSD Config Flow Get. 6408 * 6409 * @param [in] unit - unit id 6410 * @param [in] port - logical port 6411 * @param [in] group_id - group id 6412 * @param [out] flow_info - Flow info. 6413 */ 6414 #ifdef CPRIMOD_SUPPORT 6415 int portmod_cpri_port_rx_vsd_flow_get(int unit, int port, uint32 group_id, portmod_cpri_rx_vsd_flow_info_t* flow_info); 6416 #endif /* CPRIMOD_SUPPORT */ 6417 6418 /*! 6419 * portmod_cpri_port_rx_vsd_flow_delete 6420 * 6421 * @brief Delete CPRI Rx VSD Group Flow. 6422 * 6423 * @param [in] unit - unit id 6424 * @param [in] port - logical port 6425 * @param [in] group_id - group id 6426 */ 6427 #ifdef CPRIMOD_SUPPORT 6428 int portmod_cpri_port_rx_vsd_flow_delete(int unit, int port, uint32 group_id); 6429 #endif /* CPRIMOD_SUPPORT */ 6430 6431 typedef _shr_cpri_tx_vsd_flow_info_t portmod_cpri_tx_vsd_flow_info_t; 6432 6433 /*! 6434 * portmod_cpri_port_tx_vsd_flow_add 6435 * 6436 * @brief CPRI Rx VSD Config Flow Add. 6437 * 6438 * @param [in] unit - unit id 6439 * @param [in] port - logical port 6440 * @param [in] group_id - group id 6441 * @param [in] flow_info - Flow info. 6442 */ 6443 #ifdef CPRIMOD_SUPPORT 6444 int portmod_cpri_port_tx_vsd_flow_add(int unit, int port, uint32 group_id, const portmod_cpri_tx_vsd_flow_info_t* flow_info); 6445 #endif /* CPRIMOD_SUPPORT */ 6446 6447 /*! 6448 * portmod_cpri_port_tx_vsd_flow_delete 6449 * 6450 * @brief Delete CPRI Rx VSD Group Flow. 6451 * 6452 * @param [in] unit - unit id 6453 * @param [in] port - logical port 6454 * @param [in] group_id - group id 6455 */ 6456 #ifdef CPRIMOD_SUPPORT 6457 int portmod_cpri_port_tx_vsd_flow_delete(int unit, int port, uint32 group_id); 6458 #endif /* CPRIMOD_SUPPORT */ 6459 6460 /*! 6461 * portmod_cpri_port_tx_vsd_flow_get 6462 * 6463 * @brief CPRI Rx VSD Config Flow Get. 6464 * 6465 * @param [in] unit - unit id 6466 * @param [in] port - logical port 6467 * @param [in] group_id - group id 6468 * @param [out] flow_info - Flow info. 6469 */ 6470 #ifdef CPRIMOD_SUPPORT 6471 int portmod_cpri_port_tx_vsd_flow_get(int unit, int port, uint32 group_id, portmod_cpri_tx_vsd_flow_info_t* flow_info); 6472 #endif /* CPRIMOD_SUPPORT */ 6473 6474 /*! 6475 * portmod_cpri_port_encap_queue_control_tag_to_flow_map_set 6476 * 6477 * @brief CPRI Rx VSD Config Set/Get. 6478 * 6479 * @param [in] unit - unit id 6480 * @param [in] port - logical port 6481 * @param [in] tag_id - Tag Id. 6482 * @param [in] flow_id - Flow ID. 6483 */ 6484 #ifdef CPRIMOD_SUPPORT 6485 int portmod_cpri_port_encap_queue_control_tag_to_flow_map_set(int unit, int port, uint32 tag_id, uint32 flow_id); 6486 #endif /* CPRIMOD_SUPPORT */ 6487 /*! 6488 * portmod_cpri_port_encap_queue_control_tag_to_flow_map_get 6489 * 6490 * @brief CPRI Rx VSD Config Set/Get. 6491 * 6492 * @param [in] unit - unit id 6493 * @param [in] port - logical port 6494 * @param [in] tag_id - Tag Id. 6495 * @param [out] flow_id - FLow ID. 6496 */ 6497 #ifdef CPRIMOD_SUPPORT 6498 int portmod_cpri_port_encap_queue_control_tag_to_flow_map_get(int unit, int port, uint32 tag_id, uint32* flow_id); 6499 #endif /* CPRIMOD_SUPPORT */ 6500 6501 #ifdef CPRIMOD_SUPPORT 6502 typedef _shr_cpri_cw_filter_mode_t portmod_cpri_cw_filter_mode_t; 6503 6504 #endif /* CPRIMOD_SUPPORT */ 6505 #ifdef CPRIMOD_SUPPORT 6506 #define PORTMOD_CPRI_CW_FILTER_DISABLE _shrCpriFilterDisable 6507 #define PORTMOD_CPRI_CW_FILTER_NON_ZERO _shrCpriFilterNonZero 6508 #define PORTMOD_CPRI_CW_FILTER_PERIODIC _shrCpriFilterPeriodic 6509 #define PORTMOD_CPRI_CW_FILTER_CHANGE _shrCpriFilterChange 6510 #define PORTMOD_CPRI_CW_FILTER_PATTERN_MATCH _shrCpriFilterPatternMatch 6511 #endif /* CPRIMOD_SUPPORT */ 6512 6513 6514 /*! 6515 * @struct portmod_cpri_rx_vsd_raw_config_s 6516 * @brief CPRI Rx VSD Raw Configuration Information. 6517 */ 6518 #ifdef CPRIMOD_SUPPORT 6519 typedef struct portmod_cpri_rx_vsd_raw_config_s { 6520 uint32 schan_start; /**< Sub Channel Start */ 6521 uint32 schan_size; /**< Sub Channel Size */ 6522 uint32 cw_sel; /**< Control Word Select Bit Map */ 6523 uint32 cw_size; /**< Control Word Size, number of bytes */ 6524 portmod_cpri_cw_filter_mode_t filter_mode; /**< Filter Mode */ 6525 uint32 hyper_frame_index; /**< Hyper Frame Index */ 6526 uint32 hyper_frame_modulo; /**< Hyper Frame Modulo */ 6527 uint32 match_offset; /**< Match Offset */ 6528 uint32 match_value; /**< Match Value */ 6529 uint32 match_mask; /**< Match Mask */ 6530 uint32 queue_num; /**< Queue Number. */ 6531 uint32 priority; /**< Priority */ 6532 uint32 queue_size; /**< Queue Size in Bytes */ 6533 } portmod_cpri_rx_vsd_raw_config_t; 6534 6535 /* portmod_cpri_rx_vsd_raw_config_t initialization and validation */ 6536 int portmod_cpri_rx_vsd_raw_config_t_validate(int unit, const portmod_cpri_rx_vsd_raw_config_t* portmod_cpri_rx_vsd_raw_config); 6537 int portmod_cpri_rx_vsd_raw_config_t_init(int unit, portmod_cpri_rx_vsd_raw_config_t* portmod_cpri_rx_vsd_raw_config); 6538 6539 #endif /* CPRIMOD_SUPPORT */ 6540 /*! 6541 * portmod_cpri_port_rx_vsd_raw_config_set 6542 * 6543 * @brief Get/Set VSD Raw Configuration. 6544 * 6545 * @param [in] unit - unit id 6546 * @param [in] port - logical port 6547 * @param [in] index - VSD Raw Group Index. 0-7 6548 * @param [in] config_info - VSD Raw Configuration info. 6549 */ 6550 #ifdef CPRIMOD_SUPPORT 6551 int portmod_cpri_port_rx_vsd_raw_config_set(int unit, int port, uint32 index, const portmod_cpri_rx_vsd_raw_config_t* config_info); 6552 #endif /* CPRIMOD_SUPPORT */ 6553 /*! 6554 * portmod_cpri_port_rx_vsd_raw_config_get 6555 * 6556 * @brief Get/Set VSD Raw Configuration. 6557 * 6558 * @param [in] unit - unit id 6559 * @param [in] port - logical port 6560 * @param [in] index - VSD Raw Group Index. 0-7 6561 * @param [out] config_info - VSD Raw Configuration info. 6562 */ 6563 #ifdef CPRIMOD_SUPPORT 6564 int portmod_cpri_port_rx_vsd_raw_config_get(int unit, int port, uint32 index, portmod_cpri_rx_vsd_raw_config_t* config_info); 6565 #endif /* CPRIMOD_SUPPORT */ 6566 6567 #ifdef CPRIMOD_SUPPORT 6568 typedef _shr_vsd_raw_map_mode_t portmod_cpri_vsd_raw_map_mode_t; 6569 6570 #endif /* CPRIMOD_SUPPORT */ 6571 #ifdef CPRIMOD_SUPPORT 6572 #define PORTMOD_CPRI_CW_MAP_MODE_PERIODIC _shrVsdRawMapModePeriodic 6573 #define PORTMOD_CPRI_CW_MAP_MODE_ROE_FRAME _shrVsdRawMapModeRoeFrame 6574 #endif /* CPRIMOD_SUPPORT */ 6575 6576 6577 /*! 6578 * @struct portmod_cpri_tx_vsd_raw_config_s 6579 * @brief CPRI Tx VSD Raw Configuration Information. 6580 */ 6581 #ifdef CPRIMOD_SUPPORT 6582 typedef struct portmod_cpri_tx_vsd_raw_config_s { 6583 uint32 schan_start; /**< Sub Channel Start */ 6584 uint32 schan_size; /**< Sub Channel Size */ 6585 uint32 cw_sel; /**< Control Word Select Bit Map */ 6586 uint32 cw_size; /**< Control Word Size, number of bytes */ 6587 uint32 hyper_frame_index; /**< Hyper Frame Index */ 6588 uint32 hyper_frame_modulo; /**< Hyper Frame Modulo */ 6589 uint32 queue_num; /**< Queue Number. */ 6590 portmod_cpri_vsd_raw_map_mode_t map_mode; /**< Map Mode. */ 6591 int repeat_enable; /**< Repeat until new data.. */ 6592 int bfn0_filter_enable; /**< Enable Filter BFN0. */ 6593 int bfn1_filter_enable; /**< Enable Filter BFN1. */ 6594 uint32 idle_value; /**< Value to be insert when data is not available. */ 6595 uint32 buffer_size; /**< Buffer Size in Bytes */ 6596 uint32 cycle_size; /**< Cycle Size */ 6597 } portmod_cpri_tx_vsd_raw_config_t; 6598 6599 /* portmod_cpri_tx_vsd_raw_config_t initialization and validation */ 6600 int portmod_cpri_tx_vsd_raw_config_t_validate(int unit, const portmod_cpri_tx_vsd_raw_config_t* portmod_cpri_tx_vsd_raw_config); 6601 int portmod_cpri_tx_vsd_raw_config_t_init(int unit, portmod_cpri_tx_vsd_raw_config_t* portmod_cpri_tx_vsd_raw_config); 6602 6603 #endif /* CPRIMOD_SUPPORT */ 6604 /*! 6605 * portmod_cpri_port_tx_vsd_raw_config_set 6606 * 6607 * @brief Get/Set Tx VSD Raw Configuration. 6608 * 6609 * @param [in] unit - unit id 6610 * @param [in] port - logical port 6611 * @param [in] index - VSD Raw Group Index. 0-7 6612 * @param [in] config_info - VSD Raw Configuration info. 6613 */ 6614 #ifdef CPRIMOD_SUPPORT 6615 int portmod_cpri_port_tx_vsd_raw_config_set(int unit, int port, uint32 index, const portmod_cpri_tx_vsd_raw_config_t* config_info); 6616 #endif /* CPRIMOD_SUPPORT */ 6617 /*! 6618 * portmod_cpri_port_tx_vsd_raw_config_get 6619 * 6620 * @brief Get/Set Tx VSD Raw Configuration. 6621 * 6622 * @param [in] unit - unit id 6623 * @param [in] port - logical port 6624 * @param [in] index - VSD Raw Group Index. 0-7 6625 * @param [out] config_info - VSD Raw Configuration info. 6626 */ 6627 #ifdef CPRIMOD_SUPPORT 6628 int portmod_cpri_port_tx_vsd_raw_config_get(int unit, int port, uint32 index, portmod_cpri_tx_vsd_raw_config_t* config_info); 6629 #endif /* CPRIMOD_SUPPORT */ 6630 6631 /*! 6632 * portmod_cpri_port_tx_vsd_raw_filter_set 6633 * 6634 * @brief VSD Raw Radio Frame Filter Set/Get. 6635 * 6636 * @param [in] unit - unit id 6637 * @param [in] port - logical port 6638 * @param [in] bfn0_value - BFN0 Radio Frame Number. 6639 * @param [in] bfn0_mask - BFN0 Radio Frame Mask. 6640 * @param [in] bfn1_value - BFN1 Radio Frame Number. 6641 * @param [in] bfn1_mask - BFN1 Radio Frame Mask. 6642 */ 6643 #ifdef CPRIMOD_SUPPORT 6644 int portmod_cpri_port_tx_vsd_raw_filter_set(int unit, int port, uint32 bfn0_value, uint32 bfn0_mask, uint32 bfn1_value, uint32 bfn1_mask); 6645 #endif /* CPRIMOD_SUPPORT */ 6646 /*! 6647 * portmod_cpri_port_tx_vsd_raw_filter_get 6648 * 6649 * @brief VSD Raw Radio Frame Filter Set/Get. 6650 * 6651 * @param [in] unit - unit id 6652 * @param [in] port - logical port 6653 * @param [out] bfn0_value - BFN0 Radio Frame Number. 6654 * @param [out] bfn0_mask - BFN0 Radio Frame Mask. 6655 * @param [out] bfn1_value - BFN1 Radio Frame Number. 6656 * @param [out] bfn1_mask - BFN1 Radio Frame Mask. 6657 */ 6658 #ifdef CPRIMOD_SUPPORT 6659 int portmod_cpri_port_tx_vsd_raw_filter_get(int unit, int port, uint32* bfn0_value, uint32* bfn0_mask, uint32* bfn1_value, uint32* bfn1_mask); 6660 #endif /* CPRIMOD_SUPPORT */ 6661 6662 6663 /*! 6664 * @struct portmod_cpri_rx_brcm_rsvd5_config_s 6665 * @brief CPRI Rx RSVD5 Configuration Information. 6666 */ 6667 #ifdef CPRIMOD_SUPPORT 6668 typedef struct portmod_cpri_rx_brcm_rsvd5_config_s { 6669 uint32 schan_start; /**< Sub Channel Start */ 6670 uint32 schan_size; /**< Sub Channel Size */ 6671 int parity_disable; /**< Parity Disable. */ 6672 uint32 queue_num; /**< Queue Number. */ 6673 uint32 priority; /**< Priority */ 6674 uint32 queue_size; /**< Queue Size in Bytes */ 6675 } portmod_cpri_rx_brcm_rsvd5_config_t; 6676 6677 /* portmod_cpri_rx_brcm_rsvd5_config_t initialization and validation */ 6678 int portmod_cpri_rx_brcm_rsvd5_config_t_validate(int unit, const portmod_cpri_rx_brcm_rsvd5_config_t* portmod_cpri_rx_brcm_rsvd5_config); 6679 int portmod_cpri_rx_brcm_rsvd5_config_t_init(int unit, portmod_cpri_rx_brcm_rsvd5_config_t* portmod_cpri_rx_brcm_rsvd5_config); 6680 6681 #endif /* CPRIMOD_SUPPORT */ 6682 /*! 6683 * portmod_cpri_port_rx_brcm_rsvd5_config_set 6684 * 6685 * @brief Get/Set Rx RSVD5 Configuration. 6686 * 6687 * @param [in] unit - unit id 6688 * @param [in] port - logical port 6689 * @param [in] config_info - RSVD5 Configuration info. 6690 */ 6691 #ifdef CPRIMOD_SUPPORT 6692 int portmod_cpri_port_rx_brcm_rsvd5_config_set(int unit, int port, const portmod_cpri_rx_brcm_rsvd5_config_t* config_info); 6693 #endif /* CPRIMOD_SUPPORT */ 6694 /*! 6695 * portmod_cpri_port_rx_brcm_rsvd5_config_get 6696 * 6697 * @brief Get/Set Rx RSVD5 Configuration. 6698 * 6699 * @param [in] unit - unit id 6700 * @param [in] port - logical port 6701 * @param [out] config_info - RSVD5 Configuration info. 6702 */ 6703 #ifdef CPRIMOD_SUPPORT 6704 int portmod_cpri_port_rx_brcm_rsvd5_config_get(int unit, int port, portmod_cpri_rx_brcm_rsvd5_config_t* config_info); 6705 #endif /* CPRIMOD_SUPPORT */ 6706 6707 6708 /*! 6709 * @struct portmod_cpri_tx_brcm_rsvd5_config_s 6710 * @brief CPRI Rx RSVD5 Configuration Information. 6711 */ 6712 #ifdef CPRIMOD_SUPPORT 6713 typedef struct portmod_cpri_tx_brcm_rsvd5_config_s { 6714 uint32 schan_start; /**< Sub Channel Start */ 6715 uint32 schan_size; /**< Sub Channel Size */ 6716 int crc_enable; /**< Parity Disable. */ 6717 uint32 queue_num; /**< Queue Number. */ 6718 uint32 buffer_size; /**< Buffer Size in Bytes */ 6719 uint32 cycle_size; /**< Cycle Size */ 6720 } portmod_cpri_tx_brcm_rsvd5_config_t; 6721 6722 /* portmod_cpri_tx_brcm_rsvd5_config_t initialization and validation */ 6723 int portmod_cpri_tx_brcm_rsvd5_config_t_validate(int unit, const portmod_cpri_tx_brcm_rsvd5_config_t* portmod_cpri_tx_brcm_rsvd5_config); 6724 int portmod_cpri_tx_brcm_rsvd5_config_t_init(int unit, portmod_cpri_tx_brcm_rsvd5_config_t* portmod_cpri_tx_brcm_rsvd5_config); 6725 6726 #endif /* CPRIMOD_SUPPORT */ 6727 /*! 6728 * portmod_cpri_port_tx_brcm_rsvd5_config_set 6729 * 6730 * @brief Get/Set Tx RSVD5 Configuration. 6731 * 6732 * @param [in] unit - unit id 6733 * @param [in] port - logical port 6734 * @param [in] config_info - RSVD5 Configuration info. 6735 */ 6736 #ifdef CPRIMOD_SUPPORT 6737 int portmod_cpri_port_tx_brcm_rsvd5_config_set(int unit, int port, const portmod_cpri_tx_brcm_rsvd5_config_t* config_info); 6738 #endif /* CPRIMOD_SUPPORT */ 6739 /*! 6740 * portmod_cpri_port_tx_brcm_rsvd5_config_get 6741 * 6742 * @brief Get/Set Tx RSVD5 Configuration. 6743 * 6744 * @param [in] unit - unit id 6745 * @param [in] port - logical port 6746 * @param [out] config_info - RSVD5 Configuration info. 6747 */ 6748 #ifdef CPRIMOD_SUPPORT 6749 int portmod_cpri_port_tx_brcm_rsvd5_config_get(int unit, int port, portmod_cpri_tx_brcm_rsvd5_config_t* config_info); 6750 #endif /* CPRIMOD_SUPPORT */ 6751 6752 #ifdef CPRIMOD_SUPPORT 6753 typedef _shr_cpri_gcw_mask_t portmod_cpri_gcw_mask_t; 6754 6755 #endif /* CPRIMOD_SUPPORT */ 6756 #ifdef CPRIMOD_SUPPORT 6757 #define PORTMOD_CPRI_GCW_MASK_NONE _shrCpriGcwMaskNone 6758 #define PORTMOD_CPRI_GCW_MASK_LSB _shrCpriGcwMaskLSB 6759 #define PORTMOD_CPRI_GCW_MASK_MSB _shrCpriGcwMaskMSB 6760 #define PORTMOD_CPRI_GCW_MASK_BOTH _shrCpriGcwMaskBOTH 6761 #endif /* CPRIMOD_SUPPORT */ 6762 6763 6764 /*! 6765 * @struct portmod_cpri_rx_gcw_config_s 6766 * @brief CPRI Rx GCW Configuration Information. 6767 */ 6768 #ifdef CPRIMOD_SUPPORT 6769 typedef struct portmod_cpri_rx_gcw_config_s { 6770 uint32 Ns; /**< Sub Channel Number 0-63 */ 6771 uint32 Xs; /**< Sub Channel Word 0-3. */ 6772 uint32 Y; /**< Sub Channel First Byte Location . */ 6773 portmod_cpri_gcw_mask_t mask; /**< Mask */ 6774 portmod_cpri_cw_filter_mode_t filter_mode; /**< Filter Mode */ 6775 uint32 hyper_frame_index; /**< Hyper Frame Index */ 6776 uint32 hyper_frame_modulo; /**< Hyper Frame Modulo */ 6777 uint32 match_mask; /**< Match Mask */ 6778 uint32 match_value; /**< Match Value */ 6779 } portmod_cpri_rx_gcw_config_t; 6780 6781 /* portmod_cpri_rx_gcw_config_t initialization and validation */ 6782 int portmod_cpri_rx_gcw_config_t_validate(int unit, const portmod_cpri_rx_gcw_config_t* portmod_cpri_rx_gcw_config); 6783 int portmod_cpri_rx_gcw_config_t_init(int unit, portmod_cpri_rx_gcw_config_t* portmod_cpri_rx_gcw_config); 6784 6785 #endif /* CPRIMOD_SUPPORT */ 6786 6787 /*! 6788 * @struct portmod_cpri_tx_gcw_config_s 6789 * @brief CPRI Tx GCW Configuration Information. 6790 */ 6791 #ifdef CPRIMOD_SUPPORT 6792 typedef struct portmod_cpri_tx_gcw_config_s { 6793 uint32 Ns; /**< Sub Channel Number 0-63 */ 6794 uint32 Xs; /**< Sub Channel Word 0-3. */ 6795 uint32 Y; /**< Sub Channel First Byte Location . */ 6796 portmod_cpri_gcw_mask_t mask; /**< Mask */ 6797 uint32 hyper_frame_index; /**< Hyper Frame Index */ 6798 uint32 hyper_frame_modulo; /**< Hyper Frame Modulo */ 6799 int repeat_enable; /**< Repeat until new data.. */ 6800 int bfn0_filter_enable; /**< Enable Filter BFN0. */ 6801 int bfn1_filter_enable; /**< Enable Filter BFN1. */ 6802 } portmod_cpri_tx_gcw_config_t; 6803 6804 /* portmod_cpri_tx_gcw_config_t initialization and validation */ 6805 int portmod_cpri_tx_gcw_config_t_validate(int unit, const portmod_cpri_tx_gcw_config_t* portmod_cpri_tx_gcw_config); 6806 int portmod_cpri_tx_gcw_config_t_init(int unit, portmod_cpri_tx_gcw_config_t* portmod_cpri_tx_gcw_config); 6807 6808 #endif /* CPRIMOD_SUPPORT */ 6809 /*! 6810 * portmod_cpri_port_rx_gcw_config_set 6811 * 6812 * @brief Get/Set Rx GCW Configuration. 6813 * 6814 * @param [in] unit - unit id 6815 * @param [in] port - logical port 6816 * @param [in] index - GCW Index. 0-15 6817 * @param [in] config_info - GCW Configuration info. 6818 */ 6819 #ifdef CPRIMOD_SUPPORT 6820 int portmod_cpri_port_rx_gcw_config_set(int unit, int port, uint32 index, const portmod_cpri_rx_gcw_config_t* config_info); 6821 #endif /* CPRIMOD_SUPPORT */ 6822 /*! 6823 * portmod_cpri_port_rx_gcw_config_get 6824 * 6825 * @brief Get/Set Rx GCW Configuration. 6826 * 6827 * @param [in] unit - unit id 6828 * @param [in] port - logical port 6829 * @param [in] index - GCW Index. 0-15 6830 * @param [out] config_info - GCW Configuration info. 6831 */ 6832 #ifdef CPRIMOD_SUPPORT 6833 int portmod_cpri_port_rx_gcw_config_get(int unit, int port, uint32 index, portmod_cpri_rx_gcw_config_t* config_info); 6834 #endif /* CPRIMOD_SUPPORT */ 6835 6836 /*! 6837 * portmod_cpri_port_tx_gcw_config_set 6838 * 6839 * @brief Get/Set Tx GCW Configuration. 6840 * 6841 * @param [in] unit - unit id 6842 * @param [in] port - logical port 6843 * @param [in] index - GCW Index. 0-15 6844 * @param [in] config_info - GCW Configuration info. 6845 */ 6846 #ifdef CPRIMOD_SUPPORT 6847 int portmod_cpri_port_tx_gcw_config_set(int unit, int port, uint32 index, const portmod_cpri_tx_gcw_config_t* config_info); 6848 #endif /* CPRIMOD_SUPPORT */ 6849 /*! 6850 * portmod_cpri_port_tx_gcw_config_get 6851 * 6852 * @brief Get/Set Tx GCW Configuration. 6853 * 6854 * @param [in] unit - unit id 6855 * @param [in] port - logical port 6856 * @param [in] index - GCW Index. 0-15 6857 * @param [out] config_info - GCW Configuration info. 6858 */ 6859 #ifdef CPRIMOD_SUPPORT 6860 int portmod_cpri_port_tx_gcw_config_get(int unit, int port, uint32 index, portmod_cpri_tx_gcw_config_t* config_info); 6861 #endif /* CPRIMOD_SUPPORT */ 6862 6863 /*! 6864 * portmod_cpri_port_tx_gcw_filter_set 6865 * 6866 * @brief GCW Radio Frame Filter Set/Get. 6867 * 6868 * @param [in] unit - unit id 6869 * @param [in] port - logical port 6870 * @param [in] bfn0_value - BFN0 Radio Frame Number. 6871 * @param [in] bfn0_mask - BFN0 Radio Frame Mask. 6872 * @param [in] bfn1_value - BFN1 Radio Frame Number. 6873 * @param [in] bfn1_mask - BFN1 Radio Frame Mask. 6874 */ 6875 #ifdef CPRIMOD_SUPPORT 6876 int portmod_cpri_port_tx_gcw_filter_set(int unit, int port, uint32 bfn0_value, uint32 bfn0_mask, uint32 bfn1_value, uint32 bfn1_mask); 6877 #endif /* CPRIMOD_SUPPORT */ 6878 /*! 6879 * portmod_cpri_port_tx_gcw_filter_get 6880 * 6881 * @brief GCW Radio Frame Filter Set/Get. 6882 * 6883 * @param [in] unit - unit id 6884 * @param [in] port - logical port 6885 * @param [out] bfn0_value - BFN0 Radio Frame Number. 6886 * @param [out] bfn0_mask - BFN0 Radio Frame Mask. 6887 * @param [out] bfn1_value - BFN1 Radio Frame Number. 6888 * @param [out] bfn1_mask - BFN1 Radio Frame Mask. 6889 */ 6890 #ifdef CPRIMOD_SUPPORT 6891 int portmod_cpri_port_tx_gcw_filter_get(int unit, int port, uint32* bfn0_value, uint32* bfn0_mask, uint32* bfn1_value, uint32* bfn1_mask); 6892 #endif /* CPRIMOD_SUPPORT */ 6893 6894 /*! 6895 * portmod_cpri_port_tx_cw_sync_info_set 6896 * 6897 * @brief CPRI Sync information. 6898 * 6899 * @param [in] unit - unit id 6900 * @param [in] port - logical port 6901 * @param [in] hyper_frame_num - Hyper Frame Number. 6902 * @param [in] radio_frame_num - Radio Frame Number. 6903 */ 6904 #ifdef CPRIMOD_SUPPORT 6905 int portmod_cpri_port_tx_cw_sync_info_set(int unit, int port, uint32 hyper_frame_num, uint32 radio_frame_num); 6906 #endif /* CPRIMOD_SUPPORT */ 6907 /*! 6908 * portmod_cpri_port_tx_cw_sync_info_get 6909 * 6910 * @brief CPRI Sync information. 6911 * 6912 * @param [in] unit - unit id 6913 * @param [in] port - logical port 6914 * @param [out] hyper_frame_num - Hyper Frame Number. 6915 * @param [out] radio_frame_num - Radio Frame Number. 6916 */ 6917 #ifdef CPRIMOD_SUPPORT 6918 int portmod_cpri_port_tx_cw_sync_info_get(int unit, int port, uint32* hyper_frame_num, uint32* radio_frame_num); 6919 #endif /* CPRIMOD_SUPPORT */ 6920 6921 #ifdef CPRIMOD_SUPPORT 6922 typedef _shr_cpri_cw_l1_config_info_t portmod_cpri_cw_l1_config_info_t; 6923 6924 #endif /* CPRIMOD_SUPPORT */ 6925 /*! 6926 * portmod_cpri_port_tx_cw_l1_config_set 6927 * 6928 * @brief CPRI Tx Control Word information. 6929 * 6930 * @param [in] unit - unit id 6931 * @param [in] port - logical port 6932 * @param [in] control_info - Control Word info.. 6933 */ 6934 #ifdef CPRIMOD_SUPPORT 6935 int portmod_cpri_port_tx_cw_l1_config_set(int unit, int port, const portmod_cpri_cw_l1_config_info_t* control_info); 6936 #endif /* CPRIMOD_SUPPORT */ 6937 6938 typedef _shr_rsvd4_control_msg_proc_type_t portmod_control_msg_proc_type_t; 6939 6940 #define PORTMOD_CONTROL_MSG_PROC_TYPE_FE _shrRsvd4CtrlMsgProcFE 6941 #define PORTMOD_CONTROL_MSG_PROC_TYPE_FCB _shrRsvd4CtrlMsgProcFCB 6942 #define PORTMOD_CONTROL_MSG_PROC_TYPE_PAYLOAD _shrRsvd4CtrlMsgProcPayload 6943 #define PORTMOD_CONTROL_MSG_PROC_TYPE_FULL_MESSAGE _shrRsvd4CtrlMsgProcFull 6944 #define PORTMOD_CONTROL_MSG_PROC_TYPE_FULL_MESSAGE_W_TAG _shrRsvd4CtrlMsgProcFullWithTag 6945 6946 6947 /*! 6948 * @struct portmod_control_flow_config_s 6949 * @brief Control Flow Configuration Information. 6950 */ 6951 typedef struct portmod_control_flow_config_s { 6952 uint32 match_mask; /**< Match Mask */ 6953 uint32 match_data; /**< Match data */ 6954 portmod_control_msg_proc_type_t proc_type; /**< . */ 6955 uint32 queue_num; /**< Queue Number . */ 6956 uint32 sync_profile; /**< Sync Profile Number */ 6957 int sync_enable; /**< Sync Profile Enable. */ 6958 uint32 priority; /**< Priority */ 6959 uint32 queue_size; /**< Queue Size in Bytes */ 6960 } portmod_control_flow_config_t; 6961 6962 /* portmod_control_flow_config_t initialization and validation */ 6963 int portmod_control_flow_config_t_validate(int unit, const portmod_control_flow_config_t* portmod_control_flow_config); 6964 int portmod_control_flow_config_t_init(int unit, portmod_control_flow_config_t* portmod_control_flow_config); 6965 6966 /*! 6967 * portmod_rsvd4_rx_control_flow_add 6968 * 6969 * @brief Set Control Message Configuration.. 6970 * 6971 * @param [in] unit - unit id 6972 * @param [in] port - logical port 6973 * @param [in] flow_id - Control Flow ID. 6974 * @param [in] config - Control Flow Configuration. 6975 */ 6976 #ifdef CPRIMOD_SUPPORT 6977 int portmod_rsvd4_rx_control_flow_add(int unit, int port, uint32 flow_id, const portmod_control_flow_config_t* config); 6978 #endif /* CPRIMOD_SUPPORT */ 6979 6980 /*! 6981 * portmod_rsvd4_rx_control_flow_delete 6982 * 6983 * @brief Set Control Message Configuration.. 6984 * 6985 * @param [in] unit - unit id 6986 * @param [in] port - logical port 6987 * @param [in] flow_id - Control Flow ID. 6988 * @param [in] config - Control Flow Configuration. 6989 */ 6990 #ifdef CPRIMOD_SUPPORT 6991 int portmod_rsvd4_rx_control_flow_delete(int unit, int port, uint32 flow_id, const portmod_control_flow_config_t* config); 6992 #endif /* CPRIMOD_SUPPORT */ 6993 6994 #ifdef CPRIMOD_SUPPORT 6995 typedef _shr_cpri_fast_eth_config_t portmod_cpri_fast_eth_config_t; 6996 6997 #endif /* CPRIMOD_SUPPORT */ 6998 /*! 6999 * portmod_rsvd4_fast_eth_config_set 7000 * 7001 * @brief Set Fast Ethernet configuration.. 7002 * 7003 * @param [in] unit - unit id 7004 * @param [in] port - logical port 7005 * @param [in] config_info - Fast Eth Configuration. 7006 */ 7007 #ifdef CPRIMOD_SUPPORT 7008 int portmod_rsvd4_fast_eth_config_set(int unit, int port, const portmod_cpri_fast_eth_config_t* config_info); 7009 #endif /* CPRIMOD_SUPPORT */ 7010 7011 typedef _shr_rsvd4_sync_count_cycle_t portmod_sync_count_cycle_t; 7012 7013 #define PORTMOD_SYNC_COUNT_CYCLE_EVERY_MF _shrRsvd4SyncCountCycleEveryMF 7014 #define PORTMOD_SYNC_COUNT_CYCLE_UP_TO_6MF _shrRsvd4SyncCountCycleUpToSixMF 7015 7016 7017 /*! 7018 * @struct portmod_sync_profile_entry_s 7019 * @brief Control Flow Configuration Information. 7020 */ 7021 typedef struct portmod_sync_profile_entry_s { 7022 portmod_sync_count_cycle_t count_cycle; /**< Count Cycle */ 7023 uint32 message_offset; /**< Message offset within Master Frame . */ 7024 uint32 master_frame_offset; /**< Master Frame Offset. bfn_offset */ 7025 } portmod_sync_profile_entry_t; 7026 7027 /* portmod_sync_profile_entry_t initialization and validation */ 7028 int portmod_sync_profile_entry_t_validate(int unit, const portmod_sync_profile_entry_t* portmod_sync_profile_entry); 7029 int portmod_sync_profile_entry_t_init(int unit, portmod_sync_profile_entry_t* portmod_sync_profile_entry); 7030 7031 /*! 7032 * portmod_rsvd4_rx_sync_profile_entry_set 7033 * 7034 * @brief Sync Profile Entry.. 7035 * 7036 * @param [in] unit - unit id 7037 * @param [in] port - logical port 7038 * @param [in] profile_id - Control Flow ID. 7039 * @param [in] entry - Sync Profile Entry. 7040 */ 7041 #ifdef CPRIMOD_SUPPORT 7042 int portmod_rsvd4_rx_sync_profile_entry_set(int unit, int port, uint32 profile_id, const portmod_sync_profile_entry_t* entry); 7043 #endif /* CPRIMOD_SUPPORT */ 7044 /*! 7045 * portmod_rsvd4_rx_sync_profile_entry_get 7046 * 7047 * @brief Sync Profile Entry.. 7048 * 7049 * @param [in] unit - unit id 7050 * @param [in] port - logical port 7051 * @param [in] profile_id - Control Flow ID. 7052 * @param [out] entry - Sync Profile Entry. 7053 */ 7054 #ifdef CPRIMOD_SUPPORT 7055 int portmod_rsvd4_rx_sync_profile_entry_get(int unit, int port, uint32 profile_id, portmod_sync_profile_entry_t* entry); 7056 #endif /* CPRIMOD_SUPPORT */ 7057 7058 /*! 7059 * portmod_rx_tag_config_set 7060 * 7061 * @brief Tag Generation Entry.. 7062 * 7063 * @param [in] unit - unit id 7064 * @param [in] port - logical port 7065 * @param [in] default_tag - Default Tag . 7066 * @param [in] no_match_tag - No Match Tag . 7067 */ 7068 int portmod_rx_tag_config_set(int unit, int port, uint32 default_tag, uint32 no_match_tag); 7069 7070 typedef _shr_cpri_tag_gen_entry_t portmod_tag_gen_entry_t; 7071 7072 /*! 7073 * portmod_rx_tag_gen_entry_add 7074 * 7075 * @brief Tag Generation Entry.. 7076 * 7077 * @param [in] unit - unit id 7078 * @param [in] port - logical port 7079 * @param [in] entry - Tag Generation Entry Info. 7080 */ 7081 int portmod_rx_tag_gen_entry_add(int unit, int port, const portmod_tag_gen_entry_t* entry); 7082 7083 /*! 7084 * portmod_rx_tag_gen_entry_delete 7085 * 7086 * @brief Tag Generation Entry.. 7087 * 7088 * @param [in] unit - unit id 7089 * @param [in] port - logical port 7090 * @param [in] entry - Tag Generation Entry Info. 7091 */ 7092 int portmod_rx_tag_gen_entry_delete(int unit, int port, const portmod_tag_gen_entry_t* entry); 7093 7094 /*! 7095 * portmod_rsvd4_tx_control_flow_group_member_add 7096 * 7097 * @brief Add member to the Tx Control Flow Group.. 7098 * 7099 * @param [in] unit - unit id 7100 * @param [in] port - logical port 7101 * @param [in] group_id - Group Number 0 or 1. 7102 * @param [in] priority - Prioirty within the group 0-3. 7103 * @param [in] queue_num - Queue Numer. 7104 * @param [in] proc_type - Processing Type. 7105 */ 7106 #ifdef CPRIMOD_SUPPORT 7107 int portmod_rsvd4_tx_control_flow_group_member_add(int unit, int port, uint32 group_id, uint32 priority, uint32 queue_num, portmod_control_msg_proc_type_t proc_type); 7108 #endif /* CPRIMOD_SUPPORT */ 7109 7110 /*! 7111 * portmod_rsvd4_tx_control_flow_group_member_delete 7112 * 7113 * @brief Delete member to the Tx Control Flow Group.. 7114 * 7115 * @param [in] unit - unit id 7116 * @param [in] port - logical port 7117 * @param [in] group_id - Group Number 0 or 1. 7118 * @param [in] priority - Prioirty within the group 0-3. 7119 */ 7120 #ifdef CPRIMOD_SUPPORT 7121 int portmod_rsvd4_tx_control_flow_group_member_delete(int unit, int port, uint32 group_id, uint32 priority); 7122 #endif /* CPRIMOD_SUPPORT */ 7123 7124 /*! 7125 * portmod_rsvd4_tx_eth_message_config_set 7126 * 7127 * @brief Setting RSVD4 Fast Ethernet Control Message Configuration.. 7128 * 7129 * @param [in] unit - unit id 7130 * @param [in] port - logical port 7131 * @param [in] msg_node - Message Node. 7132 * @param [in] msg_subnode - Message SubNode. 7133 * @param [in] msg_type - Message Type. 7134 * @param [in] msg_padding - Padding Bit 0 or 1. 7135 */ 7136 #ifdef CPRIMOD_SUPPORT 7137 int portmod_rsvd4_tx_eth_message_config_set(int unit, int port, uint32 msg_node, uint32 msg_subnode, uint32 msg_type, uint32 msg_padding); 7138 #endif /* CPRIMOD_SUPPORT */ 7139 7140 /*! 7141 * portmod_rsvd4_tx_single_raw_message_config_set 7142 * 7143 * @brief Setting RSVD4 Single Raw Control Message Configuration.. 7144 * 7145 * @param [in] unit - unit id 7146 * @param [in] port - logical port 7147 * @param [in] msg_id - Message ID. 7148 * @param [in] msg_type - Message Type. 7149 */ 7150 #ifdef CPRIMOD_SUPPORT 7151 int portmod_rsvd4_tx_single_raw_message_config_set(int unit, int port, uint32 msg_id, uint32 msg_type); 7152 #endif /* CPRIMOD_SUPPORT */ 7153 7154 7155 /*! 7156 * @struct portmod_rsvd4_tx_config_info_s 7157 * @brief Control Flow Configuration Information. 7158 */ 7159 #ifdef CPRIMOD_SUPPORT 7160 typedef struct portmod_rsvd4_tx_config_info_s { 7161 portmod_control_msg_proc_type_t proc_type; /**< Controm message process type */ 7162 uint8 queue_num; /**< queue number */ 7163 uint32 queue_size; /**< queue size */ 7164 uint32 cycle_size; /**< cycle size */ 7165 uint8 crc_mode; /**< crc mode */ 7166 } portmod_rsvd4_tx_config_info_t; 7167 7168 /* portmod_rsvd4_tx_config_info_t initialization and validation */ 7169 int portmod_rsvd4_tx_config_info_t_validate(int unit, const portmod_rsvd4_tx_config_info_t* portmod_rsvd4_tx_config_info); 7170 int portmod_rsvd4_tx_config_info_t_init(int unit, portmod_rsvd4_tx_config_info_t* portmod_rsvd4_tx_config_info); 7171 7172 #endif /* CPRIMOD_SUPPORT */ 7173 /*! 7174 * portmod_rsvd4_tx_control_flow_config_set 7175 * 7176 * @brief Set Control Message Configuration.. 7177 * 7178 * @param [in] unit - unit id 7179 * @param [in] port - logical port 7180 * @param [in] flow_id - Control Flow ID. 7181 * @param [in] config_info - control config info. 7182 */ 7183 #ifdef CPRIMOD_SUPPORT 7184 int portmod_rsvd4_tx_control_flow_config_set(int unit, int port, uint32 flow_id, const portmod_rsvd4_tx_config_info_t* config_info); 7185 #endif /* CPRIMOD_SUPPORT */ 7186 /*! 7187 * portmod_rsvd4_tx_control_flow_config_get 7188 * 7189 * @brief Set Control Message Configuration.. 7190 * 7191 * @param [in] unit - unit id 7192 * @param [in] port - logical port 7193 * @param [in] flow_id - Control Flow ID. 7194 * @param [out] config_info - control config info. 7195 */ 7196 #ifdef CPRIMOD_SUPPORT 7197 int portmod_rsvd4_tx_control_flow_config_get(int unit, int port, uint32 flow_id, portmod_rsvd4_tx_config_info_t* config_info); 7198 #endif /* CPRIMOD_SUPPORT */ 7199 7200 /*! 7201 * portmod_rsvd4_tx_control_flow_header_index_set 7202 * 7203 * @brief Set Index to header config table for a particular flow.. 7204 * 7205 * @param [in] unit - unit id 7206 * @param [in] port - logical port 7207 * @param [in] roe_flow_id - Flow ID from ROE header. 7208 * @param [in] index - Index to header config table. 7209 */ 7210 #ifdef CPRIMOD_SUPPORT 7211 int portmod_rsvd4_tx_control_flow_header_index_set(int unit, int port, uint32 roe_flow_id, uint32 index); 7212 #endif /* CPRIMOD_SUPPORT */ 7213 /*! 7214 * portmod_rsvd4_tx_control_flow_header_index_get 7215 * 7216 * @brief Set Index to header config table for a particular flow.. 7217 * 7218 * @param [in] unit - unit id 7219 * @param [in] port - logical port 7220 * @param [in] roe_flow_id - Flow ID from ROE header. 7221 * @param [out] index - Index to header config table. 7222 */ 7223 #ifdef CPRIMOD_SUPPORT 7224 int portmod_rsvd4_tx_control_flow_header_index_get(int unit, int port, uint32 roe_flow_id, uint32* index); 7225 #endif /* CPRIMOD_SUPPORT */ 7226 7227 /*! 7228 * portmod_rsvd4_tx_control_header_entry_set 7229 * 7230 * @brief Header Look up Entry.. 7231 * 7232 * @param [in] unit - unit id 7233 * @param [in] port - logical port 7234 * @param [in] index - Index to the table. 7235 * @param [in] header_node - rsvd4 header node. 7236 * @param [in] header_subnode - rsvd4 header subnode. 7237 * @param [in] payload_node - rsvd4 payload node. 7238 */ 7239 #ifdef CPRIMOD_SUPPORT 7240 int portmod_rsvd4_tx_control_header_entry_set(int unit, int port, uint32 index, uint32 header_node, uint32 header_subnode, uint32 payload_node); 7241 #endif /* CPRIMOD_SUPPORT */ 7242 /*! 7243 * portmod_rsvd4_tx_control_header_entry_get 7244 * 7245 * @brief Header Look up Entry.. 7246 * 7247 * @param [in] unit - unit id 7248 * @param [in] port - logical port 7249 * @param [in] index - Index to the table. 7250 * @param [out] header_node - rsvd4 header node. 7251 * @param [out] header_subnode - rsvd4 header subnode. 7252 * @param [out] payload_node - rsvd4 payload node. 7253 */ 7254 #ifdef CPRIMOD_SUPPORT 7255 int portmod_rsvd4_tx_control_header_entry_get(int unit, int port, uint32 index, uint32* header_node, uint32* header_subnode, uint32* payload_node); 7256 #endif /* CPRIMOD_SUPPORT */ 7257 7258 #ifdef CPRIMOD_SUPPORT 7259 typedef _shr_rsvd4_crc_option_t portmod_cpri_crc_option_t; 7260 7261 #endif /* CPRIMOD_SUPPORT */ 7262 #ifdef CPRIMOD_SUPPORT 7263 #define PORTMOD_CPRI_CRC_USE_ROE _shrRsvd4CrcOptionUseRoe 7264 #define PORTMOD_CPRI_CRC_REGENERATE _shrRsvd4CrcOptionRegenerate 7265 #endif /* CPRIMOD_SUPPORT */ 7266 7267 /*! 7268 * portmod_rsvd4_tx_single_tunnel_message_config_set 7269 * 7270 * @brief Setting RSVD4 Single Raw Control Message Configuration.. 7271 * 7272 * @param [in] unit - unit id 7273 * @param [in] port - logical port 7274 * @param [in] crc_option - CRC option. 7275 */ 7276 #ifdef CPRIMOD_SUPPORT 7277 int portmod_rsvd4_tx_single_tunnel_message_config_set(int unit, int port, portmod_cpri_crc_option_t crc_option); 7278 #endif /* CPRIMOD_SUPPORT */ 7279 7280 7281 /*! 7282 * @struct portmod_txpi_override_s 7283 * @brief TX phase interpolator DSM override configuration 7284 */ 7285 typedef struct portmod_txpi_override_s { 7286 uint32 enable; /**< Enable/disable TXPI override */ 7287 int value; /**< TXPI override value */ 7288 } portmod_txpi_override_t; 7289 7290 /* portmod_txpi_override_t initialization and validation */ 7291 int portmod_txpi_override_t_validate(int unit, const portmod_txpi_override_t* portmod_txpi_override); 7292 int portmod_txpi_override_t_init(int unit, portmod_txpi_override_t* portmod_txpi_override); 7293 7294 /*! 7295 * portmod_port_txpi_override_set 7296 * 7297 * @brief "Set/get Portmacro TXPI SDM override configuration. This function is for debug." 7298 * 7299 * @param [in] unit - unit id 7300 * @param [in] port - logical port 7301 * @param [in] override - Enable TXPI DSM override with value 7302 */ 7303 int portmod_port_txpi_override_set(int unit, int port, const portmod_txpi_override_t* override); 7304 /*! 7305 * portmod_port_txpi_override_get 7306 * 7307 * @brief "Set/get Portmacro TXPI SDM override configuration. This function is for debug." 7308 * 7309 * @param [in] unit - unit id 7310 * @param [in] port - logical port 7311 * @param [out] override - Get TXPI DSM override status 7312 */ 7313 int portmod_port_txpi_override_get(int unit, int port, portmod_txpi_override_t* override); 7314 7315 /*! 7316 * portmod_port_txpi_sdm_data_get 7317 * 7318 * @brief "Get Portmacro TXPI SDM value. This funciont is for debug" 7319 * 7320 * @param [in] unit - unit id 7321 * @param [in] port - logical port 7322 * @param [out] value - The value for TXPI SDM, which is the final resolution. 7323 */ 7324 int portmod_port_txpi_sdm_data_get(int unit, int port, int* value); 7325 7326 /*! 7327 * @brief PM8x50 Specific capabilities 7328 */ 7329 #define PORTMOD_PM8x50_MAX_VCOS (3) 7330 #define PORTMOD_PM8x50_NUM_PLLS (2) 7331 #define PORTMOD_PM8x50_NUM_CORES (1) 7332 #define PORTMOD_PM8x50_NUM_LANES (8) 7333 7334 typedef struct portmod_pm8x50_capability_s { 7335 uint8 num_lanes; /**< number of physical lanes(ports) supported by the PM */ 7336 uint8 num_cores; /**< Number of Cores in the PM */ 7337 uint8 num_plls; /**< Number of PLLs supported by the PM */ 7338 uint8 num_vcos; /**< Number of VCOs available in the PM */ 7339 uint8 vcos[PORTMOD_PM8x50_MAX_VCOS]; /**< Available VCO range values for the PM */ 7340 } portmod_pm8x50_capability_t; 7341 7342 /* portmod_pm8x50_capability_t initialization and validation */ 7343 int portmod_pm8x50_capability_t_validate(int unit, const portmod_pm8x50_capability_t* portmod_pm8x50_capability); 7344 int portmod_pm8x50_capability_t_init(int unit, portmod_pm8x50_capability_t* portmod_pm8x50_capability); 7345 7346 typedef union portmod_pm_specific_capability_u { 7347 portmod_pm8x50_capability_t pm8x50_cap; 7348 } portmod_pm_specific_capability_t; 7349 7350 typedef struct portmod_pm_capability_s { 7351 portmod_dispatch_type_t type; /**< PM type */ 7352 portmod_pm_specific_capability_t pm_capability; /**< PM capability */ 7353 } portmod_pm_capability_t; 7354 7355 /* portmod_pm_capability_t initialization and validation */ 7356 int portmod_pm_capability_t_validate(int unit, const portmod_pm_capability_t* portmod_pm_capability); 7357 int portmod_pm_capability_t_init(int unit, portmod_pm_capability_t* portmod_pm_capability); 7358 7359 typedef struct portmod_pm_vco_setting_s { 7360 int num_speeds; /**< number of speed ids that need to be supported */ 7361 portmod_speed_config_t* speed_config_list; /**< list of speed configs */ 7362 int* port_starting_lane_list; /**< list of starting_lanes correspond to speed configs in speed_config_list */ 7363 int* speed_for_pcs_bypass_port; /**< if speed is for PCS bypass port */ 7364 portmod_vco_type_t tvco; /**< Higher VCO value */ 7365 portmod_vco_type_t ovco; /**< Lower VCO value */ 7366 int is_tvco_new; /**< tvco change is needed */ 7367 int is_ovco_new; /**< ovco change is needed */ 7368 } portmod_pm_vco_setting_t; 7369 7370 /* portmod_pm_vco_setting_t initialization and validation */ 7371 int portmod_pm_vco_setting_t_validate(int unit, const portmod_pm_vco_setting_t* portmod_pm_vco_setting); 7372 int portmod_pm_vco_setting_t_init(int unit, portmod_pm_vco_setting_t* portmod_pm_vco_setting); 7373 7374 /*! 7375 * portmod_pm_speed_config_validate 7376 * 7377 * @brief Validate a set of speed config within a port macro. 7378 * 7379 * @param [in] unit - unit id 7380 * @param [in] pm_id - port macro id 7381 * @param [in] ports - logical ports being validated 7382 * @param [in] flag - flag 7383 * @param [inout] vco_setting - suggested vco setting 7384 */ 7385 int portmod_pm_speed_config_validate(int unit, int pm_id, const portmod_pbmp_t* ports, int flag, portmod_pm_vco_setting_t* vco_setting); 7386 7387 /*! 7388 * portmod_pm_vcos_get 7389 * 7390 * @brief Get the suggested VCO values based on the speed config list of a PM 7391 * 7392 * @param [in] unit - unit id 7393 * @param [in] pm_type - PM type 7394 * @param [in] flags - Flags, see PM_VERSION_F_ 7395 * @param [inout] vco_select - speed config list as the input and suggested VCO rates as the output 7396 */ 7397 int portmod_pm_vcos_get(int unit, portmod_dispatch_type_t pm_type, uint32 flags, portmod_pm_vco_setting_t* vco_select); 7398 7399 /*! 7400 * @brief Flags for portmod_vcos_get function. 7401 */ 7402 #define PORTMOD_PM8X50_REV0_16NM 0x1 /**< The target PM version is PM8x50 16nm revision0. */ 7403 #define PORTMOD_ALLOW_20P625G_TVCO 0x1000 /**< Allow TVCO to be 20.625G. */ 7404 7405 #define PORTMOD_PM8X50_REV0_16NM_SET(flags) ((flags) |= PORTMOD_PM8X50_REV0_16NM) 7406 #define PORTMOD_ALLOW_20P625G_TVCO_SET(flags) ((flags) |= PORTMOD_ALLOW_20P625G_TVCO) 7407 7408 #define PORTMOD_PM8X50_REV0_16NM_CLR(flags) ((flags) &= ~PORTMOD_PM8X50_REV0_16NM) 7409 #define PORTMOD_ALLOW_20P625G_TVCO_CLR(flags) ((flags) &= ~PORTMOD_ALLOW_20P625G_TVCO) 7410 7411 #define PORTMOD_PM8X50_REV0_16NM_GET(flags) ((flags) & PORTMOD_PM8X50_REV0_16NM ? 1 : 0) 7412 #define PORTMOD_ALLOW_20P625G_TVCO_GET(flags) ((flags) & PORTMOD_ALLOW_20P625G_TVCO ? 1 : 0) 7413 7414 7415 /*! 7416 * portmod_port_autoneg_ability_advert_set 7417 * 7418 * @brief Set/get port auto negotiation ability 7419 * 7420 * @param [in] unit - unit id 7421 * @param [in] port - logical port 7422 * @param [in] num_abilities - Number of AN abilities to be set 7423 * @param [in] abilities - AN abilities array 7424 */ 7425 int portmod_port_autoneg_ability_advert_set(int unit, int port, int num_abilities, const portmod_port_speed_ability_t* abilities); 7426 /*! 7427 * portmod_port_autoneg_ability_advert_get 7428 * 7429 * @brief Set/get port auto negotiation ability 7430 * 7431 * @param [in] unit - unit id 7432 * @param [in] port - logical port 7433 * @param [in] max_num_abilities - Maximum abilities that can return in the ability array 7434 * @param [out] abilities - AN abilities array 7435 * @param [out] actual_num_abilities - Number of AN abilities to be set 7436 */ 7437 int portmod_port_autoneg_ability_advert_get(int unit, int port, int max_num_abilities, portmod_port_speed_ability_t* abilities, int* actual_num_abilities); 7438 7439 /*! 7440 * portmod_port_autoneg_ability_remote_get 7441 * 7442 * @brief Port ability remote Adv get 7443 * 7444 * @param [in] unit - unit id 7445 * @param [in] port - logical port 7446 * @param [in] max_num_abilities - Maximum abilities that can return in the ability array 7447 * @param [out] abilities - AN abilities array 7448 * @param [out] actual_num_abilities - Number of AN abilities to be set 7449 */ 7450 int portmod_port_autoneg_ability_remote_get(int unit, int port, int max_num_abilities, portmod_port_speed_ability_t* abilities, int* actual_num_abilities); 7451 7452 7453 typedef _shr_cpri_interrupt_type_t portmod_cpri_port_intr_type_t; 7454 7455 typedef struct portmod_cpri_port_intr_info_s { 7456 portmod_cpri_port_intr_type_t cpri_intr_type; /**< cpri interrupt type */ 7457 int axc_id; /**< AxC Id */ 7458 int queue_num; /**< queu num */ 7459 int data; /**< reserved */ 7460 uint64 data64; /**< reserved */ 7461 } portmod_cpri_port_intr_info_t; 7462 7463 /* portmod_cpri_port_intr_info_t initialization and validation */ 7464 int portmod_cpri_port_intr_info_t_validate(int unit, const portmod_cpri_port_intr_info_t* portmod_cpri_port_intr_info); 7465 int portmod_cpri_port_intr_info_t_init(int unit, portmod_cpri_port_intr_info_t* portmod_cpri_port_intr_info); 7466 7467 typedef _shr_cpri_port_interrupt_callback_t portmod_cpri_port_interrupt_callback_t; 7468 7469 /*! 7470 * portmod_cpri_port_interrupt_callback_register 7471 * 7472 * @brief Register callback for CPRI Interrupts 7473 * 7474 * @param [in] unit - unit id 7475 * @param [in] cpri_intr_type - 7476 * @param [in] callback - 7477 * @param [out] cb_data - 7478 */ 7479 #ifdef CPRIMOD_SUPPORT 7480 int portmod_cpri_port_interrupt_callback_register(int unit, portmod_cpri_port_intr_type_t cpri_intr_type, portmod_cpri_port_interrupt_callback_t callback, void* cb_data); 7481 #endif /* CPRIMOD_SUPPORT */ 7482 7483 /*! 7484 * portmod_cpri_port_interrupt_callback_unregister 7485 * 7486 * @brief Unregister callback for CPRI Interrupts 7487 * 7488 * @param [in] unit - unit id 7489 * @param [in] cpri_intr_type - 7490 * @param [in] callback - 7491 */ 7492 #ifdef CPRIMOD_SUPPORT 7493 int portmod_cpri_port_interrupt_callback_unregister(int unit, portmod_cpri_port_intr_type_t cpri_intr_type, cprimod_cpri_port_interrupt_callback_t callback); 7494 #endif /* CPRIMOD_SUPPORT */ 7495 7496 /*! 7497 * portmod_phy_pms_ids_get 7498 * 7499 * @brief get all the PMS info of specific phy 7500 * 7501 * @param [in] unit - unit id 7502 * @param [in] phy - phy number 7503 * @param [in] max_pms - max number of returned pms 7504 * @param [out] nof_pms - retrieved number of pms 7505 * @param [out] pms_types - retrieved pms type 7506 * @param [out] pms_ids - retrieved pms ids 7507 */ 7508 int portmod_phy_pms_ids_get(int unit, int phy, int max_pms, int* nof_pms, portmod_dispatch_type_t* pms_types, int* pms_ids); 7509 7510 /*! 7511 * portmod_port_pm_id_get 7512 * 7513 * @brief get PM id of specific port 7514 * 7515 * @param [in] unit - unit id 7516 * @param [in] port - logical port 7517 * @param [out] pm_id - retrieved pm id 7518 */ 7519 int portmod_port_pm_id_get(int unit, int port, int* pm_id); 7520 7521 /*! 7522 * portmod_cpri_port_interrupt_enable_set 7523 * 7524 * @brief Get the CPRI Port interrupt status. 7525 * 7526 * @param [in] unit - unit id 7527 * @param [in] port - logical port 7528 * @param [in] cpri_intr_type - 7529 * @param [in] data - 7530 * @param [in] enable - 7531 */ 7532 #ifdef CPRIMOD_SUPPORT 7533 int portmod_cpri_port_interrupt_enable_set(int unit, int port, portmod_cpri_port_intr_type_t cpri_intr_type, int data, int enable); 7534 #endif /* CPRIMOD_SUPPORT */ 7535 7536 /*! 7537 * portmod_cpri_port_interrupt_process 7538 * 7539 * @brief Get the CPRI Port interrupt status. 7540 * 7541 * @param [in] unit - unit id 7542 * @param [in] port - logical port 7543 */ 7544 #ifdef CPRIMOD_SUPPORT 7545 int portmod_cpri_port_interrupt_process(int unit, int port); 7546 #endif /* CPRIMOD_SUPPORT */ 7547 7548 /*! 7549 * portmod_fast_clk_bit_time_period_set 7550 * 7551 * @brief set/get fast clk bit period 7552 * 7553 * @param [in] unit - unit id 7554 * @param [in] port - logical port 7555 * @param [in] bit_time_period - bit time 2 bit ns 12 bit sub ns 7556 */ 7557 #ifdef CPRIMOD_SUPPORT 7558 int portmod_fast_clk_bit_time_period_set(int unit, int port, uint32 bit_time_period); 7559 #endif /* CPRIMOD_SUPPORT */ 7560 /*! 7561 * portmod_fast_clk_bit_time_period_get 7562 * 7563 * @brief set/get fast clk bit period 7564 * 7565 * @param [in] unit - unit id 7566 * @param [in] port - logical port 7567 * @param [out] bit_time_period - bit time 2 bit ns 12 bit sub ns 7568 */ 7569 #ifdef CPRIMOD_SUPPORT 7570 int portmod_fast_clk_bit_time_period_get(int unit, int port, uint32* bit_time_period); 7571 #endif /* CPRIMOD_SUPPORT */ 7572 7573 typedef _shr_cpri_dir_t portmod_direction_t; 7574 7575 #define PORTMOD_DIR_TX _shrCpriDirTx 7576 #define PORTMOD_DIR_RX _shrCpriDirRx 7577 7578 /*! 7579 * portmod_1588_bit_time_period_set 7580 * 7581 * @brief set/get time stamp bit period 7582 * 7583 * @param [in] unit - unit id 7584 * @param [in] port - logical port 7585 * @param [in] direction - TX/RX 7586 * @param [in] speed - speed 7587 */ 7588 #ifdef CPRIMOD_SUPPORT 7589 int portmod_1588_bit_time_period_set(int unit, int port, portmod_direction_t direction, cprimod_port_speed_t speed); 7590 #endif /* CPRIMOD_SUPPORT */ 7591 /*! 7592 * portmod_1588_bit_time_period_get 7593 * 7594 * @brief set/get time stamp bit period 7595 * 7596 * @param [in] unit - unit id 7597 * @param [in] port - logical port 7598 * @param [in] direction - TX/RX 7599 * @param [out] bit_time_period - bit time 7600 */ 7601 #ifdef CPRIMOD_SUPPORT 7602 int portmod_1588_bit_time_period_get(int unit, int port, portmod_direction_t direction, uint32* bit_time_period); 7603 #endif /* CPRIMOD_SUPPORT */ 7604 7605 /*! 7606 * portmod_1588_timestamp_capture_config_set 7607 * 7608 * @brief set/get time stamp config 7609 * 7610 * @param [in] unit - unit id 7611 * @param [in] port - logical port 7612 * @param [in] direction - TX/RX 7613 * @param [in] config - Config 7614 */ 7615 #ifdef CPRIMOD_SUPPORT 7616 int portmod_1588_timestamp_capture_config_set(int unit, int port, portmod_direction_t direction, const cprimod_1588_capture_config_t* config); 7617 #endif /* CPRIMOD_SUPPORT */ 7618 /*! 7619 * portmod_1588_timestamp_capture_config_get 7620 * 7621 * @brief set/get time stamp config 7622 * 7623 * @param [in] unit - unit id 7624 * @param [in] port - logical port 7625 * @param [in] direction - TX/RX 7626 * @param [out] config - Config 7627 */ 7628 #ifdef CPRIMOD_SUPPORT 7629 int portmod_1588_timestamp_capture_config_get(int unit, int port, portmod_direction_t direction, cprimod_1588_capture_config_t* config); 7630 #endif /* CPRIMOD_SUPPORT */ 7631 7632 typedef _shr_cpri_1588_ts_type_t portmod_1588_ts_type_t; 7633 7634 #define PORTMOD_1588_TS_TYPE_FIFO _shrCpri1588TsTypeFifo 7635 #define PORTMOD_1588_TS_TYPE_CMIC _shrCpri1588TsTypeCMIC 7636 #define PORTMOD_1588_TS_TYPE_SW_CAP _shrCpri1588TsTypeSw 7637 7638 /*! 7639 * portmod_1588_captured_timestamp_get 7640 * 7641 * @brief Get timestemp 7642 * 7643 * @param [in] unit - unit id 7644 * @param [in] port - logical port 7645 * @param [in] direction - TX/RX 7646 * @param [in] ts_type - Fifo or capture timestamp 7647 * @param [in] mx_cnt - 7648 * @param [out] count - 7649 * @param [out] captured_time - captured time 7650 */ 7651 #ifdef CPRIMOD_SUPPORT 7652 int portmod_1588_captured_timestamp_get(int unit, int port, portmod_direction_t direction, portmod_1588_ts_type_t ts_type, uint8 mx_cnt, uint8* count, uint64* captured_time); 7653 #endif /* CPRIMOD_SUPPORT */ 7654 7655 /*! 7656 * portmod_1588_timestamp_adjust_set 7657 * 7658 * @brief set/get time stamp config 7659 * 7660 * @param [in] unit - unit id 7661 * @param [in] port - logical port 7662 * @param [in] direction - TX/RX 7663 * @param [in] adjust_time - adjest time 7664 */ 7665 #ifdef CPRIMOD_SUPPORT 7666 int portmod_1588_timestamp_adjust_set(int unit, int port, portmod_direction_t direction, const cprimod_1588_time_t* adjust_time); 7667 #endif /* CPRIMOD_SUPPORT */ 7668 /*! 7669 * portmod_1588_timestamp_adjust_get 7670 * 7671 * @brief set/get time stamp config 7672 * 7673 * @param [in] unit - unit id 7674 * @param [in] port - logical port 7675 * @param [in] direction - TX/RX 7676 * @param [out] adjust_time - adjest time 7677 */ 7678 #ifdef CPRIMOD_SUPPORT 7679 int portmod_1588_timestamp_adjust_get(int unit, int port, portmod_direction_t direction, cprimod_1588_time_t* adjust_time); 7680 #endif /* CPRIMOD_SUPPORT */ 7681 7682 /*! 7683 * portmod_1588_timestamp_fifo_config_set 7684 * 7685 * @brief set/get time stamp modulo for fifo 7686 * 7687 * @param [in] unit - unit id 7688 * @param [in] port - logical port 7689 * @param [in] direction - TX/RX 7690 * @param [in] modulo - modulo 7691 */ 7692 #ifdef CPRIMOD_SUPPORT 7693 int portmod_1588_timestamp_fifo_config_set(int unit, int port, portmod_direction_t direction, uint16 modulo); 7694 #endif /* CPRIMOD_SUPPORT */ 7695 /*! 7696 * portmod_1588_timestamp_fifo_config_get 7697 * 7698 * @brief set/get time stamp modulo for fifo 7699 * 7700 * @param [in] unit - unit id 7701 * @param [in] port - logical port 7702 * @param [in] direction - TX/RX 7703 * @param [out] modulo - modulo 7704 */ 7705 #ifdef CPRIMOD_SUPPORT 7706 int portmod_1588_timestamp_fifo_config_get(int unit, int port, portmod_direction_t direction, uint16* modulo); 7707 #endif /* CPRIMOD_SUPPORT */ 7708 7709 /*! 7710 * portmod_1588_timestamp_cmic_config_set 7711 * 7712 * @brief set/get time stamp modulo for cmic 7713 * 7714 * @param [in] unit - unit id 7715 * @param [in] port - logical port 7716 * @param [in] direction - TX/RX 7717 * @param [in] modulo - modulo 7718 */ 7719 #ifdef CPRIMOD_SUPPORT 7720 int portmod_1588_timestamp_cmic_config_set(int unit, int port, portmod_direction_t direction, uint16 modulo); 7721 #endif /* CPRIMOD_SUPPORT */ 7722 /*! 7723 * portmod_1588_timestamp_cmic_config_get 7724 * 7725 * @brief set/get time stamp modulo for cmic 7726 * 7727 * @param [in] unit - unit id 7728 * @param [in] port - logical port 7729 * @param [in] direction - TX/RX 7730 * @param [out] modulo - modulo 7731 */ 7732 #ifdef CPRIMOD_SUPPORT 7733 int portmod_1588_timestamp_cmic_config_get(int unit, int port, portmod_direction_t direction, uint16* modulo); 7734 #endif /* CPRIMOD_SUPPORT */ 7735 7736 /*! 7737 * portmod_port_tx_set 7738 * 7739 * @brief Port tx taps set/get 7740 * 7741 * @param [in] unit - unit id 7742 * @param [in] port - logical port 7743 * @param [in] tx - 7744 */ 7745 int portmod_port_tx_set(int unit, int port, const phymod_tx_t* tx); 7746 /*! 7747 * portmod_port_tx_get 7748 * 7749 * @brief Port tx taps set/get 7750 * 7751 * @param [in] unit - unit id 7752 * @param [in] port - logical port 7753 * @param [out] tx - 7754 */ 7755 int portmod_port_tx_get(int unit, int port, phymod_tx_t* tx); 7756 7757 7758 /*! 7759 * @struct portmod_port_synce_clk_ctrl_s 7760 * @brief Port SyncE configuration info 7761 */ 7762 typedef struct portmod_port_synce_clk_ctrl_s { 7763 int stg0_mode; /**< stage 0 divider value */ 7764 int stg1_mode; /**< stage 1 divider value */ 7765 uint32 sdm_val; /**< modulator value */ 7766 } portmod_port_synce_clk_ctrl_t; 7767 7768 /* portmod_port_synce_clk_ctrl_t initialization and validation */ 7769 int portmod_port_synce_clk_ctrl_t_validate(int unit, const portmod_port_synce_clk_ctrl_t* portmod_port_synce_clk_ctrl); 7770 int portmod_port_synce_clk_ctrl_t_init(int unit, portmod_port_synce_clk_ctrl_t* portmod_port_synce_clk_ctrl); 7771 7772 /*! 7773 * portmod_port_synce_clk_ctrl_set 7774 * 7775 * @brief Port SyncE clock control config 7776 * 7777 * @param [in] unit - unit id 7778 * @param [in] port - logical port 7779 * @param [in] cfg - synce clock divisor config 7780 */ 7781 int portmod_port_synce_clk_ctrl_set(int unit, int port, const portmod_port_synce_clk_ctrl_t* cfg); 7782 /*! 7783 * portmod_port_synce_clk_ctrl_get 7784 * 7785 * @brief Port SyncE clock control config 7786 * 7787 * @param [in] unit - unit id 7788 * @param [in] port - logical port 7789 * @param [out] cfg - synce clock divisor config 7790 */ 7791 int portmod_port_synce_clk_ctrl_get(int unit, int port, portmod_port_synce_clk_ctrl_t* cfg); 7792 7793 typedef _shr_cpri_frame_sync_mode_t portmod_cpri_frame_sync_mode_t; 7794 7795 #define PORTMOD_CPRI_FRAME_SYNC_MODE_HYPER _shrCpriFrameSyncModeHyper 7796 #define PORTMOD_CPRI_FRAME_SYNC_MODE_RADIO _shrCpriFrameSyncModeRadio 7797 #define PORTMOD_CPRI_FRAME_SYNC_MODE_BASIC _shrCpriFrameSyncModeBasic 7798 #define PORTMOD_CPRI_FRAME_SYNC_MODE_TUNNEL _shrCpriFrameSyncModeTunnel 7799 7800 typedef _shr_cpri_roe_payload_multiple_t portmod_cpri_roe_payload_multiple_t; 7801 7802 #define PORTMOD_CPRI_PAYLOAD_MULTIPLE_1X _shrCpriPayloadMultiple1X 7803 #define PORTMOD_CPRI_PAYLOAD_MULTIPLE_1P5X _shrCpriPayloadMultiple1p5X 7804 #define PORTMOD_CPRI_PAYLOAD_MULTIPLE_2X _shrCpriPayloadMultiple2X 7805 #define PORTMOD_CPRI_PAYLOAD_MULTIPLE_4X _shrCpriPayloadMultiple4X 7806 7807 typedef _shr_cpri_roe_ordering_info_option_t portmod_cpri_roe_ordering_info_option_t; 7808 7809 #define PORTMOD_CPRI_ROE_ORDERING_INFO_OPTION_SEQ_NUM _shrCpriRoeOrderingInfoOptionSeqNum 7810 #define PORTMOD_CPRI_ROE_ORDERING_INFO_OPTION_TIMESTAMP _shrCpriRoeOrderingInfoOptionTimestamp 7811 7812 7813 /*! 7814 * @struct portmod_cpri_rx_agnostic_config_info_s 7815 * @brief CPRI Rx Agnostic Configuration information. 7816 */ 7817 #ifdef CPRIMOD_SUPPORT 7818 typedef struct portmod_cpri_rx_agnostic_config_info_s { 7819 portmod_cpri_frame_sync_mode_t sync_mode; /**< Frame Sync Mode */ 7820 uint32 basic_frame_offset; /**< Basic Frame Offset */ 7821 uint32 hyper_frame_offset; /**< Hyper Frame Offset */ 7822 uint32 radio_frame_offset; /**< Radio Frame Offset */ 7823 portmod_cpri_roe_payload_multiple_t payload_multiple; /**< RoE Payload size multiple of Basic Frame Length. */ 7824 uint32 pres_mod_count; /**< Presentation Mod Count. */ 7825 portmod_cpri_roe_ordering_info_option_t ordering_info_option; /**< Ordering Info Option. */ 7826 } portmod_cpri_rx_agnostic_config_info_t; 7827 7828 /* portmod_cpri_rx_agnostic_config_info_t initialization and validation */ 7829 int portmod_cpri_rx_agnostic_config_info_t_validate(int unit, const portmod_cpri_rx_agnostic_config_info_t* portmod_cpri_rx_agnostic_config_info); 7830 int portmod_cpri_rx_agnostic_config_info_t_init(int unit, portmod_cpri_rx_agnostic_config_info_t* portmod_cpri_rx_agnostic_config_info); 7831 7832 #endif /* CPRIMOD_SUPPORT */ 7833 /*! 7834 * portmod_cpri_port_rx_agnostic_config_set 7835 * 7836 * @brief Setup Rx framer for agnostic mode. 7837 * 7838 * @param [in] unit - unit id 7839 * @param [in] port - logical port 7840 * @param [in] enable - enable 7841 * @param [in] config_info - Agnostic configuration information. 7842 */ 7843 #ifdef CPRIMOD_SUPPORT 7844 int portmod_cpri_port_rx_agnostic_config_set(int unit, int port, int enable, const portmod_cpri_rx_agnostic_config_info_t* config_info); 7845 #endif /* CPRIMOD_SUPPORT */ 7846 /*! 7847 * portmod_cpri_port_rx_agnostic_config_get 7848 * 7849 * @brief Setup Rx framer for agnostic mode. 7850 * 7851 * @param [in] unit - unit id 7852 * @param [in] port - logical port 7853 * @param [out] enable - enable 7854 * @param [out] config_info - Agnostic configuration information. 7855 */ 7856 #ifdef CPRIMOD_SUPPORT 7857 int portmod_cpri_port_rx_agnostic_config_get(int unit, int port, int* enable, portmod_cpri_rx_agnostic_config_info_t* config_info); 7858 #endif /* CPRIMOD_SUPPORT */ 7859 7860 7861 /*! 7862 * @struct portmod_cpri_tx_agnostic_config_info_s 7863 * @brief CPRI Rx Agnostic Configuration information. 7864 */ 7865 #ifdef CPRIMOD_SUPPORT 7866 typedef struct portmod_cpri_tx_agnostic_config_info_s { 7867 portmod_cpri_frame_sync_mode_t sync_mode; /**< Frame Sync Mode */ 7868 uint32 basic_frame_offset; /**< Basic Frame Offset */ 7869 uint32 hyper_frame_offset; /**< Hyper Frame Offset */ 7870 uint32 radio_frame_offset; /**< Radio Frame Offset */ 7871 portmod_cpri_roe_payload_multiple_t payload_multiple; /**< RoE Payload size multiple of Basic Frame Length. */ 7872 uint32 queue_mod_count; /**< Queue Mod Count for Jitter Buffer. */ 7873 uint32 pres_mod_count; /**< Presentation Mod Count for Filtering. */ 7874 uint32 pres_mod_offset; /**< Presentation Mod Offset. */ 7875 portmod_cpri_roe_ordering_info_option_t ordering_info_option; /**< Ordering Info Option. */ 7876 } portmod_cpri_tx_agnostic_config_info_t; 7877 7878 /* portmod_cpri_tx_agnostic_config_info_t initialization and validation */ 7879 int portmod_cpri_tx_agnostic_config_info_t_validate(int unit, const portmod_cpri_tx_agnostic_config_info_t* portmod_cpri_tx_agnostic_config_info); 7880 int portmod_cpri_tx_agnostic_config_info_t_init(int unit, portmod_cpri_tx_agnostic_config_info_t* portmod_cpri_tx_agnostic_config_info); 7881 7882 #endif /* CPRIMOD_SUPPORT */ 7883 /*! 7884 * portmod_cpri_port_tx_agnostic_config_set 7885 * 7886 * @brief Setup Tx framer for agnostic mode. 7887 * 7888 * @param [in] unit - unit id 7889 * @param [in] port - logical port 7890 * @param [in] enable - enable 7891 * @param [in] config_info - Agnostic configuration information. 7892 */ 7893 #ifdef CPRIMOD_SUPPORT 7894 int portmod_cpri_port_tx_agnostic_config_set(int unit, int port, int enable, const portmod_cpri_tx_agnostic_config_info_t* config_info); 7895 #endif /* CPRIMOD_SUPPORT */ 7896 /*! 7897 * portmod_cpri_port_tx_agnostic_config_get 7898 * 7899 * @brief Setup Tx framer for agnostic mode. 7900 * 7901 * @param [in] unit - unit id 7902 * @param [in] port - logical port 7903 * @param [out] enable - enable 7904 * @param [out] config_info - Agnostic configuration information. 7905 */ 7906 #ifdef CPRIMOD_SUPPORT 7907 int portmod_cpri_port_tx_agnostic_config_get(int unit, int port, int* enable, portmod_cpri_tx_agnostic_config_info_t* config_info); 7908 #endif /* CPRIMOD_SUPPORT */ 7909 7910 typedef _shr_cpri_presentation_ts_attribute_t portmod_presentation_time_attribute_t; 7911 7912 #define PORTMOD_ENCAP_PRESENTATION_TIME_ADJUST _shrCpriEncapPresentationTsAdjust 7913 #define PORTMOD_ENCAP_PRESENTATION_APPRIOX_INC _shrCpriEncapPresentationApproxInc 7914 7915 typedef _shr_cpri_presentation_time_t portmod_presentation_time_t; 7916 7917 /*! 7918 * portmod_cpri_port_encap_presentation_time_config_set 7919 * 7920 * @brief Set/Get Encap Presentation time configuration. 7921 * 7922 * @param [in] unit - unit id 7923 * @param [in] port - logical port 7924 * @param [in] attribute - Attribute to configure. 7925 * @param [in] time - Time 7926 */ 7927 #ifdef CPRIMOD_SUPPORT 7928 int portmod_cpri_port_encap_presentation_time_config_set(int unit, int port, portmod_presentation_time_attribute_t attribute, const portmod_presentation_time_t* time); 7929 #endif /* CPRIMOD_SUPPORT */ 7930 /*! 7931 * portmod_cpri_port_encap_presentation_time_config_get 7932 * 7933 * @brief Set/Get Encap Presentation time configuration. 7934 * 7935 * @param [in] unit - unit id 7936 * @param [in] port - logical port 7937 * @param [in] attribute - Attribute to configure. 7938 * @param [out] time - Time 7939 */ 7940 #ifdef CPRIMOD_SUPPORT 7941 int portmod_cpri_port_encap_presentation_time_config_get(int unit, int port, portmod_presentation_time_attribute_t attribute, portmod_presentation_time_t* time); 7942 #endif /* CPRIMOD_SUPPORT */ 7943 7944 typedef _shr_cpri_decap_presentation_config_t portmod_decap_presentation_time_config_t; 7945 7946 /*! 7947 * portmod_cpri_port_decap_presentation_time_config_set 7948 * 7949 * @brief Set/Get Decap Presentation time configuration. 7950 * 7951 * @param [in] unit - unit id 7952 * @param [in] port - logical port 7953 * @param [in] config - Decap Config 7954 */ 7955 #ifdef CPRIMOD_SUPPORT 7956 int portmod_cpri_port_decap_presentation_time_config_set(int unit, int port, const portmod_decap_presentation_time_config_t* config); 7957 #endif /* CPRIMOD_SUPPORT */ 7958 /*! 7959 * portmod_cpri_port_decap_presentation_time_config_get 7960 * 7961 * @brief Set/Get Decap Presentation time configuration. 7962 * 7963 * @param [in] unit - unit id 7964 * @param [in] port - logical port 7965 * @param [out] config - Decap Config 7966 */ 7967 #ifdef CPRIMOD_SUPPORT 7968 int portmod_cpri_port_decap_presentation_time_config_get(int unit, int port, portmod_decap_presentation_time_config_t* config); 7969 #endif /* CPRIMOD_SUPPORT */ 7970 7971 /*! 7972 * portmod_cpri_port_compression_lookup_table_set 7973 * 7974 * @brief Set/Get Compression Lookup Table. 7975 * 7976 * @param [in] unit - unit id 7977 * @param [in] port - logical port 7978 * @param [in] table_depth - Input Table Depth 7979 * @param [in] table - Table array of 1024 entries, 23 bits 7980 */ 7981 #ifdef CPRIMOD_SUPPORT 7982 int portmod_cpri_port_compression_lookup_table_set(int unit, int port, int table_depth, const uint32* table); 7983 #endif /* CPRIMOD_SUPPORT */ 7984 /*! 7985 * portmod_cpri_port_compression_lookup_table_get 7986 * 7987 * @brief Set/Get Compression Lookup Table. 7988 * 7989 * @param [in] unit - unit id 7990 * @param [in] port - logical port 7991 * @param [in] max_depth - Buffer Size. 7992 * @param [out] table_depth - Num of Table entries populated. 7993 * @param [out] table - Table array of 1024 entries, 23 bits 7994 */ 7995 #ifdef CPRIMOD_SUPPORT 7996 int portmod_cpri_port_compression_lookup_table_get(int unit, int port, int max_depth, int* table_depth, uint32* table); 7997 #endif /* CPRIMOD_SUPPORT */ 7998 7999 /*! 8000 * portmod_cpri_port_decompression_lookup_table_set 8001 * 8002 * @brief Set/Get DeCompression Lookup Table. 8003 * 8004 * @param [in] unit - unit id 8005 * @param [in] port - logical port 8006 * @param [in] table_depth - Input Table Depth 8007 * @param [in] table - Table array of 256 entries, 14 bits 8008 */ 8009 #ifdef CPRIMOD_SUPPORT 8010 int portmod_cpri_port_decompression_lookup_table_set(int unit, int port, int table_depth, const uint32* table); 8011 #endif /* CPRIMOD_SUPPORT */ 8012 /*! 8013 * portmod_cpri_port_decompression_lookup_table_get 8014 * 8015 * @brief Set/Get DeCompression Lookup Table. 8016 * 8017 * @param [in] unit - unit id 8018 * @param [in] port - logical port 8019 * @param [in] max_depth - Buffer Size. 8020 * @param [out] table_depth - Num of Table entries populated. 8021 * @param [out] table - Table array of 256 entries, 14 bits 8022 */ 8023 #ifdef CPRIMOD_SUPPORT 8024 int portmod_cpri_port_decompression_lookup_table_get(int unit, int port, int max_depth, int* table_depth, uint32* table); 8025 #endif /* CPRIMOD_SUPPORT */ 8026 8027 /*! 8028 * portmod_cpri_port_decap_queue_flow_control_set 8029 * 8030 * @brief Set/Get control queue flow control. 8031 * 8032 * @param [in] unit - unit id 8033 * @param [in] port - logical port 8034 * @param [in] queue_num - Queue Number 8035 * @param [in] enable - Enable . 8036 * @param [in] xon_threshold - Threshold to turn OFF back-pressure. 8037 * @param [in] xoff_threshold - Threshold to turn ON back-pressure. 8038 */ 8039 #ifdef CPRIMOD_SUPPORT 8040 int portmod_cpri_port_decap_queue_flow_control_set(int unit, int port, uint32 queue_num, int enable, uint32_t xon_threshold, uint32_t xoff_threshold); 8041 #endif /* CPRIMOD_SUPPORT */ 8042 /*! 8043 * portmod_cpri_port_decap_queue_flow_control_get 8044 * 8045 * @brief Set/Get control queue flow control. 8046 * 8047 * @param [in] unit - unit id 8048 * @param [in] port - logical port 8049 * @param [in] queue_num - Queue Number 8050 * @param [out] enable - Enable . 8051 * @param [out] xon_threshold - Threshold to turn OFF back-pressure. 8052 * @param [out] xoff_threshold - Threshold to turn ON back-pressure. 8053 */ 8054 #ifdef CPRIMOD_SUPPORT 8055 int portmod_cpri_port_decap_queue_flow_control_get(int unit, int port, uint32 queue_num, int* enable, uint32_t* xon_threshold, uint32_t* xoff_threshold); 8056 #endif /* CPRIMOD_SUPPORT */ 8057 8058 typedef _shr_cpri_fec_ts_source_t portmod_fec_ts_source_t; 8059 8060 #define PORTMOD_CPRI_FEC_TS_SOURCE_66B _shrCpriFecTsSource66b 8061 #define PORTMOD_CPRI_FEC_TS_SOURCE_257B _shrCpriFecTsSource257b 8062 8063 typedef _shr_cpri_fec_aux_config_t portmod_fec_aux_config_para_t; 8064 8065 #define PORTMOD_CPRI_FEC_AUX_CONFIG_SCRAMBLE_BYPASS_TX _shrCpriFecAuxConfigScrambleBypassTx 8066 #define PORTMOD_CPRI_FEC_AUX_CONFIG_DESCRAMBLE_BYPASS_RX _shrCpriFecAuxConfigDescrambleBypassRx 8067 #define PORTMOD_CPRI_FEC_AUX_CONFIG_BYPASS_INDICATION_ENABLE _shrCpriFecAuxConfigBypassIndicationEnable 8068 #define PORTMOD_CPRI_FEC_AUX_CONFIG_BYPASS_CORRECTION_ENABLE _shrCpriFecAuxConfigBypassCorrectionEnable 8069 #define PORTMOD_CPRI_FEC_AUX_CONFIG_CORRUPT_ALTERNATE_BLOCK_ENABLE _shrCpriFecAuxConfigCorruptAlternateBlocksEnable 8070 #define PORTMOD_CPRI_FEC_AUX_CONFIG_SYMBOL_ERROR_CORRUPT_ENABLE _shrCpriFecAuxConfigSymbolErrorCorruptEnable 8071 #define PORTMOD_CPRI_FEC_AUX_CONFIG_SYMBOL_ERROR_TIMER_PERIOD _shrCpriFecAuxConfigSymbolErrorTmrPeriod 8072 #define PORTMOD_CPRI_FEC_AUX_CONFIG_SYMBOL_ERROR_COUNT_THRESHOLD _shrCpriFecAuxConfigSymbolErrCntThreshold 8073 #define PORTMOD_CPRI_FEC_AUX_CONFIG_SYMBOL_ERROR_WINDOW _shrCpriFecAuxConfigSetSymbErrWindow128 8074 #define PORTMOD_CPRI_FEC_AUX_CONFIG_TICK_DENOMINATOR _shrCpriFecAuxConfigGboxTickDenominator 8075 #define PORTMOD_CPRI_FEC_AUX_CONFIG_TICK_NUMERATOR _shrCpriFecAuxConfigGboxTickNumerator 8076 #define PORTMOD_CPRI_FEC_AUX_CONFIG_SOFT_RESET _shrCpriFecAuxConfigSoftReset 8077 8078 8079 /*! 8080 * @struct portmod_fec_timestamp_config_s 8081 * @brief CPRI timestamp with FEC 8082 */ 8083 #ifdef CPRIMOD_SUPPORT 8084 typedef struct portmod_fec_timestamp_config_s { 8085 int enable; /**< Enable time stamp */ 8086 portmod_fec_ts_source_t fec_fifo_ts_source_select; /**< src for time to fifo */ 8087 portmod_fec_ts_source_t fec_cmic_ts_source_select; /**< src for time to dpll */ 8088 uint32 control_bit_offset_0; /**< Ctrl wd in 1st 66b in 257b. */ 8089 uint32 control_bit_offset_1; /**< Ctrl wd in 2nd 66b in 257b. */ 8090 uint32 control_bit_offset_2; /**< Ctrl wd in 3rd 66b in 257b. */ 8091 uint32 control_bit_offset_3; /**< Ctrl wd in 4th 66b in 257b. */ 8092 } portmod_fec_timestamp_config_t; 8093 8094 /* portmod_fec_timestamp_config_t initialization and validation */ 8095 int portmod_fec_timestamp_config_t_validate(int unit, const portmod_fec_timestamp_config_t* portmod_fec_timestamp_config); 8096 int portmod_fec_timestamp_config_t_init(int unit, portmod_fec_timestamp_config_t* portmod_fec_timestamp_config); 8097 8098 #endif /* CPRIMOD_SUPPORT */ 8099 /*! 8100 * portmod_cpri_port_fec_enable_set 8101 * 8102 * @brief Set/Get FEC enable. 8103 * 8104 * @param [in] unit - unit id 8105 * @param [in] port - logical port 8106 * @param [in] dir - TX/RX 8107 * @param [in] enable - Fec enable. 8108 */ 8109 #ifdef CPRIMOD_SUPPORT 8110 int portmod_cpri_port_fec_enable_set(int unit, int port, portmod_direction_t dir, int enable); 8111 #endif /* CPRIMOD_SUPPORT */ 8112 /*! 8113 * portmod_cpri_port_fec_enable_get 8114 * 8115 * @brief Set/Get FEC enable. 8116 * 8117 * @param [in] unit - unit id 8118 * @param [in] port - logical port 8119 * @param [in] dir - TX/RX 8120 * @param [out] enable - Fec enable. 8121 */ 8122 #ifdef CPRIMOD_SUPPORT 8123 int portmod_cpri_port_fec_enable_get(int unit, int port, portmod_direction_t dir, int* enable); 8124 #endif /* CPRIMOD_SUPPORT */ 8125 8126 /*! 8127 * portmod_cpri_port_fec_timestamp_config_set 8128 * 8129 * @brief Set/Get Fec timestamp config. 8130 * 8131 * @param [in] unit - unit id 8132 * @param [in] port - logical port 8133 * @param [in] dir - TX/RX 8134 * @param [in] config - Fec timestamp config. 8135 */ 8136 #ifdef CPRIMOD_SUPPORT 8137 int portmod_cpri_port_fec_timestamp_config_set(int unit, int port, portmod_direction_t dir, const portmod_fec_timestamp_config_t* config); 8138 #endif /* CPRIMOD_SUPPORT */ 8139 /*! 8140 * portmod_cpri_port_fec_timestamp_config_get 8141 * 8142 * @brief Set/Get Fec timestamp config. 8143 * 8144 * @param [in] unit - unit id 8145 * @param [in] port - logical port 8146 * @param [in] dir - TX/RX 8147 * @param [out] config - Fec timestamp config. 8148 */ 8149 #ifdef CPRIMOD_SUPPORT 8150 int portmod_cpri_port_fec_timestamp_config_get(int unit, int port, portmod_direction_t dir, portmod_fec_timestamp_config_t* config); 8151 #endif /* CPRIMOD_SUPPORT */ 8152 8153 /*! 8154 * portmod_cpri_port_fec_aux_config_set 8155 * 8156 * @brief Set/Get Fec Auxiliry config. 8157 * 8158 * @param [in] unit - unit id 8159 * @param [in] port - logical port 8160 * @param [in] parameter_id - Auxiliry config type 8161 * @param [in] value - Auxiliry config value. 8162 */ 8163 #ifdef CPRIMOD_SUPPORT 8164 int portmod_cpri_port_fec_aux_config_set(int unit, int port, portmod_fec_aux_config_para_t parameter_id, uint32 value); 8165 #endif /* CPRIMOD_SUPPORT */ 8166 /*! 8167 * portmod_cpri_port_fec_aux_config_get 8168 * 8169 * @brief Set/Get Fec Auxiliry config. 8170 * 8171 * @param [in] unit - unit id 8172 * @param [in] port - logical port 8173 * @param [in] parameter_id - Auxiliry config type 8174 * @param [out] value - Auxiliry config value. 8175 */ 8176 #ifdef CPRIMOD_SUPPORT 8177 int portmod_cpri_port_fec_aux_config_get(int unit, int port, portmod_fec_aux_config_para_t parameter_id, uint32* value); 8178 #endif /* CPRIMOD_SUPPORT */ 8179 8180 #ifdef CPRIMOD_SUPPORT 8181 #define PORTMOD_PM_CPRI_ECC_ERR_NONE _shrCpriEccErrTypeNone 8182 #define PORTMOD_PM_CPRI_ECC_ERR_1_BIT _shrCpriEccErrType1Bit 8183 #define PORTMOD_PM_CPRI_ECC_ERR_2_BIT _shrCpriEccErrType2Bit 8184 #define PORTMOD_PM_CPRI_ECC_ERR_MULTI_BIT _shrCpriEccErrTypeMultiBit 8185 #endif /* CPRIMOD_SUPPORT */ 8186 8187 8188 /*! 8189 * @struct portmod_ecc_intr_info_s 8190 * @brief ECC error interrupt information report 8191 */ 8192 typedef struct portmod_ecc_intr_info_s { 8193 int port; /**< port */ 8194 soc_mem_t err_mem_info; /**< ecc error memory */ 8195 soc_reg_t ecc_reg_info; /**< ecc error register */ 8196 int ecc_num_bits_err; /**< num bits ecc error */ 8197 uint32 err_addr; /**< error address */ 8198 char* mem_str; /**< error address */ 8199 } portmod_ecc_intr_info_t; 8200 8201 /* portmod_ecc_intr_info_t initialization and validation */ 8202 int portmod_ecc_intr_info_t_validate(int unit, const portmod_ecc_intr_info_t* portmod_ecc_intr_info); 8203 int portmod_ecc_intr_info_t_init(int unit, portmod_ecc_intr_info_t* portmod_ecc_intr_info); 8204 8205 #ifdef CPRIMOD_SUPPORT 8206 typedef portmod_ecc_intr_info_t portmod_cpri_ecc_intr_info_t; 8207 8208 #endif /* CPRIMOD_SUPPORT */ 8209 /*! 8210 * portmod_cpri_port_ecc_interrupt_enable_set 8211 * 8212 * @brief Enable/Disable ECC interrupts. 8213 * 8214 * @param [in] unit - unit id 8215 * @param [in] port - logical port 8216 * @param [in] enable - enable/disable ECC interrupts 8217 */ 8218 #ifdef CPRIMOD_SUPPORT 8219 int portmod_cpri_port_ecc_interrupt_enable_set(int unit, int port, int enable); 8220 #endif /* CPRIMOD_SUPPORT */ 8221 8222 /*! 8223 * portmod_cpri_port_ecc_interrupt_status_get 8224 * 8225 * @brief ECC interrupt status and information get. 8226 * 8227 * @param [in] unit - unit id 8228 * @param [in] port - logical port 8229 * @param [in] ecc_err_info - ecc error info 8230 */ 8231 #ifdef CPRIMOD_SUPPORT 8232 int portmod_cpri_port_ecc_interrupt_status_get(int unit, int port, const portmod_cpri_ecc_intr_info_t* ecc_err_info); 8233 #endif /* CPRIMOD_SUPPORT */ 8234 8235 /*! 8236 * portmod_cpri_init 8237 * 8238 * @brief Reset cpri port 8239 * 8240 * @param [in] unit - unit id 8241 * @param [in] port - logical port 8242 */ 8243 #ifdef CPRIMOD_SUPPORT 8244 int portmod_cpri_init(int unit, int port); 8245 #endif /* CPRIMOD_SUPPORT */ 8246 8247 /*! 8248 * portmod_cpri_port_rx_gcw_word_get 8249 * 8250 * @brief Get Rx GCW word 8251 * 8252 * @param [in] unit - unit id 8253 * @param [in] port - logical port 8254 * @param [in] group_index - GCW group index 8255 * @param [out] gcw_word - GCW word. 8256 */ 8257 #ifdef CPRIMOD_SUPPORT 8258 int portmod_cpri_port_rx_gcw_word_get(int unit, int port, int group_index, uint16* gcw_word); 8259 #endif /* CPRIMOD_SUPPORT */ 8260 8261 /*! 8262 * portmod_cpri_port_tx_gcw_word_set 8263 * 8264 * @brief Get Tx GCW word 8265 * 8266 * @param [in] unit - unit id 8267 * @param [in] port - logical port 8268 * @param [in] group_index - GCW group index 8269 * @param [in] gcw_word - GCW word. 8270 */ 8271 #ifdef CPRIMOD_SUPPORT 8272 int portmod_cpri_port_tx_gcw_word_set(int unit, int port, int group_index, uint16 gcw_word); 8273 #endif /* CPRIMOD_SUPPORT */ 8274 8275 #define PORTMOD_PM_ECC_NO_ERR 0x0 8276 #define PORTMOD_PM_ECC_1B_ERR 0x1 8277 #define PORTMOD_PM_ECC_2B_ERR 0x2 8278 #define PORTMOD_PM_ECC_MULTIB_ERR 0x4 8279 8280 /*! 8281 * portmod_pm_interrupt_process 8282 * 8283 * @brief Process PM interrupts. 8284 * 8285 * @param [in] unit - unit id 8286 * @param [in] pm_id - port macro id 8287 * @param [out] ecc_err_info - ecc error info 8288 */ 8289 int portmod_pm_interrupt_process(int unit, int pm_id, portmod_ecc_intr_info_t* ecc_err_info); 8290 8291 8292 8293 /*! 8294 * @struct portmod_port_rlm_config_s 8295 * @brief RLM config 8296 */ 8297 typedef struct portmod_port_rlm_config_s { 8298 int is_initiator; /**< is initiator */ 8299 uint32 active_lane_bit_map; /**< rlm active bit map */ 8300 } portmod_port_rlm_config_t; 8301 8302 /* portmod_port_rlm_config_t initialization and validation */ 8303 int portmod_port_rlm_config_t_validate(int unit, const portmod_port_rlm_config_t* portmod_port_rlm_config); 8304 int portmod_port_rlm_config_t_init(int unit, portmod_port_rlm_config_t* portmod_port_rlm_config); 8305 8306 /*! 8307 * portmod_port_rlm_config_set 8308 * 8309 * @brief RLM config set 8310 * 8311 * @param [in] unit - unit id 8312 * @param [in] port - logical port 8313 * @param [in] enable - RLM enable 8314 * @param [in] rlm_config - RLM config set 8315 */ 8316 int portmod_port_rlm_config_set(int unit, int port, int enable, const portmod_port_rlm_config_t* rlm_config); 8317 8318 /*! 8319 * portmod_port_rlm_config_get 8320 * 8321 * @brief RLM status get 8322 * 8323 * @param [in] unit - unit id 8324 * @param [in] port - logical port 8325 * @param [out] enable - RLM enable 8326 * @param [out] rlm_status - RLM config get 8327 */ 8328 int portmod_port_rlm_config_get(int unit, int port, int* enable, portmod_port_rlm_config_t* rlm_status); 8329 8330 8331 /*! 8332 * @struct portmod_port_rlm_status_s 8333 * @brief RLM status 8334 */ 8335 typedef struct portmod_port_rlm_status_s { 8336 int rlm_disabled; /**< rlm is not enabled */ 8337 int rlm_busy; /**< rlm is not enabled */ 8338 int rlm_done; /**< rlm is complete */ 8339 int rlm_failed; /**< rlm failed */ 8340 int rlm_status_count; /**< rlm status count */ 8341 } portmod_port_rlm_status_t; 8342 8343 /* portmod_port_rlm_status_t initialization and validation */ 8344 int portmod_port_rlm_status_t_validate(int unit, const portmod_port_rlm_status_t* portmod_port_rlm_status); 8345 int portmod_port_rlm_status_t_init(int unit, portmod_port_rlm_status_t* portmod_port_rlm_status); 8346 8347 /*! 8348 * portmod_port_rlm_status_get 8349 * 8350 * @brief RLM status get 8351 * 8352 * @param [in] unit - unit id 8353 * @param [in] port - logical port 8354 * @param [out] rlm_status - RLM status 8355 */ 8356 int portmod_port_rlm_status_get(int unit, int port, portmod_port_rlm_status_t* rlm_status); 8357 8358 8359 /*! 8360 * @struct portmod_cpri_rx_tunnel_mode_config_s 8361 * @brief CPRI Rx Tunnel Configuration information. 8362 */ 8363 #ifdef CPRIMOD_SUPPORT 8364 typedef struct portmod_cpri_rx_tunnel_mode_config_s { 8365 uint32 payload_size; /**< RoE Payload size in bytes. */ 8366 uint32 pres_mod_count; /**< Presentation Mod Count. */ 8367 portmod_cpri_roe_ordering_info_option_t ordering_info_option; /**< Ordering Info Option. */ 8368 } portmod_cpri_rx_tunnel_mode_config_t; 8369 8370 /* portmod_cpri_rx_tunnel_mode_config_t initialization and validation */ 8371 int portmod_cpri_rx_tunnel_mode_config_t_validate(int unit, const portmod_cpri_rx_tunnel_mode_config_t* portmod_cpri_rx_tunnel_mode_config); 8372 int portmod_cpri_rx_tunnel_mode_config_t_init(int unit, portmod_cpri_rx_tunnel_mode_config_t* portmod_cpri_rx_tunnel_mode_config); 8373 8374 #endif /* CPRIMOD_SUPPORT */ 8375 /*! 8376 * portmod_cpri_port_rx_tunnel_mode_config_set 8377 * 8378 * @brief Setup Rx framer for Tunnel mode. 8379 * 8380 * @param [in] unit - unit id 8381 * @param [in] port - logical port 8382 * @param [in] enable - enable 8383 * @param [in] config_info - Tunnel Mode configuration information. 8384 */ 8385 #ifdef CPRIMOD_SUPPORT 8386 int portmod_cpri_port_rx_tunnel_mode_config_set(int unit, int port, int enable, const portmod_cpri_rx_tunnel_mode_config_t* config_info); 8387 #endif /* CPRIMOD_SUPPORT */ 8388 /*! 8389 * portmod_cpri_port_rx_tunnel_mode_config_get 8390 * 8391 * @brief Setup Rx framer for Tunnel mode. 8392 * 8393 * @param [in] unit - unit id 8394 * @param [in] port - logical port 8395 * @param [out] enable - enable 8396 * @param [out] config_info - Tunnel Mode configuration information. 8397 */ 8398 #ifdef CPRIMOD_SUPPORT 8399 int portmod_cpri_port_rx_tunnel_mode_config_get(int unit, int port, int* enable, portmod_cpri_rx_tunnel_mode_config_t* config_info); 8400 #endif /* CPRIMOD_SUPPORT */ 8401 8402 8403 /*! 8404 * @struct portmod_cpri_tx_tunnel_mode_config_s 8405 * @brief CPRI Rx Tunnel Configuration information. 8406 */ 8407 #ifdef CPRIMOD_SUPPORT 8408 typedef struct portmod_cpri_tx_tunnel_mode_config_s { 8409 uint32 payload_size; /**< RoE Payload size in bytes. */ 8410 uint32 queue_mod_count; /**< Mod Count for Jitter Buffer. */ 8411 uint32 pres_mod_count; /**< Presentation Mod Count. */ 8412 uint32 pres_mod_offset; /**< Presentation Mod Offset. */ 8413 portmod_cpri_roe_ordering_info_option_t ordering_info_option; /**< Ordering Info Option. */ 8414 } portmod_cpri_tx_tunnel_mode_config_t; 8415 8416 /* portmod_cpri_tx_tunnel_mode_config_t initialization and validation */ 8417 int portmod_cpri_tx_tunnel_mode_config_t_validate(int unit, const portmod_cpri_tx_tunnel_mode_config_t* portmod_cpri_tx_tunnel_mode_config); 8418 int portmod_cpri_tx_tunnel_mode_config_t_init(int unit, portmod_cpri_tx_tunnel_mode_config_t* portmod_cpri_tx_tunnel_mode_config); 8419 8420 #endif /* CPRIMOD_SUPPORT */ 8421 /*! 8422 * portmod_cpri_port_tx_tunnel_mode_config_set 8423 * 8424 * @brief Setup Tx framer for Tunnel mode. 8425 * 8426 * @param [in] unit - unit id 8427 * @param [in] port - logical port 8428 * @param [in] enable - enable 8429 * @param [in] config_info - Tunnel Mode configuration information. 8430 */ 8431 #ifdef CPRIMOD_SUPPORT 8432 int portmod_cpri_port_tx_tunnel_mode_config_set(int unit, int port, int enable, const portmod_cpri_tx_tunnel_mode_config_t* config_info); 8433 #endif /* CPRIMOD_SUPPORT */ 8434 /*! 8435 * portmod_cpri_port_tx_tunnel_mode_config_get 8436 * 8437 * @brief Setup Tx framer for Tunnel mode. 8438 * 8439 * @param [in] unit - unit id 8440 * @param [in] port - logical port 8441 * @param [out] enable - enable 8442 * @param [out] config_info - Tunnel Mode configuration information. 8443 */ 8444 #ifdef CPRIMOD_SUPPORT 8445 int portmod_cpri_port_tx_tunnel_mode_config_get(int unit, int port, int* enable, portmod_cpri_tx_tunnel_mode_config_t* config_info); 8446 #endif /* CPRIMOD_SUPPORT */ 8447 8448 8449 /*! 8450 * @struct portmod_rsvd4_rx_agnostic_config_s 8451 * @brief CPRI Rx RSVD4 Configuration information. 8452 */ 8453 #ifdef CPRIMOD_SUPPORT 8454 typedef struct portmod_rsvd4_rx_agnostic_config_s { 8455 cprimod_rsvd4_frame_sync_mode_t frame_sync_mode; /**< frame sync mode. */ 8456 uint32 master_frame_offset; /**< Master Frame Offset (bfn_offset) */ 8457 uint32 message_group_number; /**< Message Group Number (rfrm_offset) */ 8458 uint32 payload_multiple; /**< RoE Payload size in multiple of Message Group 1-3. */ 8459 uint32 pres_mod_count; /**< Presentation Mod Count. */ 8460 portmod_cpri_roe_ordering_info_option_t ordering_info_option; /**< Ordering Info Option. */ 8461 } portmod_rsvd4_rx_agnostic_config_t; 8462 8463 /* portmod_rsvd4_rx_agnostic_config_t initialization and validation */ 8464 int portmod_rsvd4_rx_agnostic_config_t_validate(int unit, const portmod_rsvd4_rx_agnostic_config_t* portmod_rsvd4_rx_agnostic_config); 8465 int portmod_rsvd4_rx_agnostic_config_t_init(int unit, portmod_rsvd4_rx_agnostic_config_t* portmod_rsvd4_rx_agnostic_config); 8466 8467 #endif /* CPRIMOD_SUPPORT */ 8468 /*! 8469 * portmod_rsvd4_port_rx_agnostic_config_set 8470 * 8471 * @brief Setup Rx framer for RSVD4 Agnostic. 8472 * 8473 * @param [in] unit - unit id 8474 * @param [in] port - logical port 8475 * @param [in] enable - enable 8476 * @param [in] config_info - RSVD4 Agnostic configuration information. 8477 */ 8478 #ifdef CPRIMOD_SUPPORT 8479 int portmod_rsvd4_port_rx_agnostic_config_set(int unit, int port, int enable, const portmod_rsvd4_rx_agnostic_config_t* config_info); 8480 #endif /* CPRIMOD_SUPPORT */ 8481 /*! 8482 * portmod_rsvd4_port_rx_agnostic_config_get 8483 * 8484 * @brief Setup Rx framer for RSVD4 Agnostic. 8485 * 8486 * @param [in] unit - unit id 8487 * @param [in] port - logical port 8488 * @param [out] enable - enable 8489 * @param [out] config_info - RSVD4 Agnostic configuration information. 8490 */ 8491 #ifdef CPRIMOD_SUPPORT 8492 int portmod_rsvd4_port_rx_agnostic_config_get(int unit, int port, int* enable, portmod_rsvd4_rx_agnostic_config_t* config_info); 8493 #endif /* CPRIMOD_SUPPORT */ 8494 8495 8496 /*! 8497 * @struct portmod_rsvd4_tx_agnostic_config_s 8498 * @brief CPRI Tx RSVD4 Agnstic Configuration information. 8499 */ 8500 #ifdef CPRIMOD_SUPPORT 8501 typedef struct portmod_rsvd4_tx_agnostic_config_s { 8502 cprimod_rsvd4_frame_sync_mode_t frame_sync_mode; /**< frame sync mode. */ 8503 uint32 master_frame_offset; /**< Master Frame Offset (bfn_offset) */ 8504 uint32 message_group_number; /**< Message Group Number (rfrm_offset) */ 8505 uint32 payload_multiple; /**< RoE Payload size in Multiple of Message Group 1-3. */ 8506 uint32 queue_mod_count; /**< Mod Count for Jitter Buffer. */ 8507 uint32 pres_mod_count; /**< Presentation Mod Count. */ 8508 uint32 pres_mod_offset; /**< Presentation Mod Offset. */ 8509 portmod_cpri_roe_ordering_info_option_t ordering_info_option; /**< Ordering Info Option. */ 8510 } portmod_rsvd4_tx_agnostic_config_t; 8511 8512 /* portmod_rsvd4_tx_agnostic_config_t initialization and validation */ 8513 int portmod_rsvd4_tx_agnostic_config_t_validate(int unit, const portmod_rsvd4_tx_agnostic_config_t* portmod_rsvd4_tx_agnostic_config); 8514 int portmod_rsvd4_tx_agnostic_config_t_init(int unit, portmod_rsvd4_tx_agnostic_config_t* portmod_rsvd4_tx_agnostic_config); 8515 8516 #endif /* CPRIMOD_SUPPORT */ 8517 /*! 8518 * portmod_rsvd4_port_tx_agnostic_config_set 8519 * 8520 * @brief Setup Tx framer for RSVD4 Agnstic. 8521 * 8522 * @param [in] unit - unit id 8523 * @param [in] port - logical port 8524 * @param [in] enable - enable 8525 * @param [in] config_info - RSVD4 Agnostic configuration information. 8526 */ 8527 #ifdef CPRIMOD_SUPPORT 8528 int portmod_rsvd4_port_tx_agnostic_config_set(int unit, int port, int enable, const portmod_rsvd4_tx_agnostic_config_t* config_info); 8529 #endif /* CPRIMOD_SUPPORT */ 8530 /*! 8531 * portmod_rsvd4_port_tx_agnostic_config_get 8532 * 8533 * @brief Setup Tx framer for RSVD4 Agnstic. 8534 * 8535 * @param [in] unit - unit id 8536 * @param [in] port - logical port 8537 * @param [out] enable - enable 8538 * @param [out] config_info - RSVD4 Agnostic configuration information. 8539 */ 8540 #ifdef CPRIMOD_SUPPORT 8541 int portmod_rsvd4_port_tx_agnostic_config_get(int unit, int port, int* enable, portmod_rsvd4_tx_agnostic_config_t* config_info); 8542 #endif /* CPRIMOD_SUPPORT */ 8543 8544 typedef _shr_cpri_ecpri_header_field_t portmod_cpri_ecpri_header_field_t; 8545 8546 #ifdef CPRIMOD_SUPPORT 8547 #define PORTMOD_CPRI_ECPRI_HEADER_FIELD_BYTE_0 _shrCpriEcpriHeaderFieldByte0 8548 #define PORTMOD_CPRI_ECPRI_HEADER_FIELD_BYTE_1 _shrCpriEcpriHeaderFieldByte1 8549 #define PORTMOD_CPRI_ECPRI_HEADER_FIELD_BYTE_2 _shrCpriEcpriHeaderFieldByte2 8550 #define PORTMOD_CPRI_ECPRI_HEADER_FIELD_BYTE_3 _shrCpriEcpriHeaderFieldByte3 8551 #define PORTMOD_CPRI_ECPRI_HEADER_FIELD_BYTE_4 _shrCpriEcpriHeaderFieldByte4 8552 #define PORTMOD_CPRI_ECPRI_HEADER_FIELD_BYTE_5 _shrCpriEcpriHeaderFieldByte5 8553 #define PORTMOD_CPRI_ECPRI_HEADER_FIELD_BYTE_6 _shrCpriEcpriHeaderFieldByte6 8554 #define PORTMOD_CPRI_ECPRI_HEADER_FIELD_BYTE_7 _shrCpriEcpriHeaderFieldByte7 8555 #define PORTMOD_CPRI_ECPRI_HEADER_FIELD_BYTE_8 _shrCpriEcpriHeaderFieldByte8 8556 #define PORTMOD_CPRI_ECPRI_HEADER_FIELD_BYTE_9 _shrCpriEcpriHeaderFieldByte9 8557 #define PORTMOD_CPRI_ECPRI_HEADER_FIELD_BYTE_10 _shrCpriEcpriHeaderFieldByte10 8558 #define PORTMOD_CPRI_ECPRI_HEADER_FIELD_BYTE_11 _shrCpriEcpriHeaderFieldByte11 8559 #define PORTMOD_CPRI_ECPRI_HEADER_FIELD_VLAN_0_BYTE_0 _shrCpriEcpriHeaderFieldVlan0Byte0 8560 #define PORTMOD_CPRI_ECPRI_HEADER_FIELD_VLAN_0_BYTE_1 _shrCpriEcpriHeaderFieldVlan0Byte1 8561 #define PORTMOD_CPRI_ECPRI_HEADER_FIELD_VLAN_1_BYTE_0 _shrCpriEcpriHeaderFieldVlan1Byte0 8562 #define PORTMOD_CPRI_ECPRI_HEADER_FIELD_VLAN_1_BYTE_1 _shrCpriEcpriHeaderFieldVlan1Byte1 8563 #endif /* CPRIMOD_SUPPORT */ 8564 8565 typedef _shr_cpri_roe_frame_format_t portmod_cpri_roe_frame_format_t; 8566 8567 #ifdef CPRIMOD_SUPPORT 8568 #define PORTMOD_CPRI_ROE_FRAME_FORMAT_IEEE1914 _shrCpriRoeFrameFormatIEEE1914 8569 #define PORTMOD_CPRI_ROE_FRAME_FORMAT_RSVD3 _shrCpriRoeFrameFormatRsvd3 8570 #define PORTMOD_CPRI_ROE_FRAME_FORMAT_ECPRI8 _shrCpriRoeFrameFormatEcpri8 8571 #define PORTMOD_CPRI_ROE_FRAME_FORMAT_ECPRI12 _shrCpriRoeFrameFormatEcpri12 8572 #endif /* CPRIMOD_SUPPORT */ 8573 8574 8575 /*! 8576 * @struct portmod_cpri_port_frame_config_s 8577 * @brief CPRI RoE frame configuration.. 8578 */ 8579 #ifdef CPRIMOD_SUPPORT 8580 typedef struct portmod_cpri_port_frame_config_s { 8581 portmod_cpri_roe_frame_format_t frame_type; /**< frame sync mode. */ 8582 portmod_cpri_ecpri_header_field_t decap_primary_key; /**< Primary Key */ 8583 portmod_cpri_ecpri_header_field_t decap_secondary_key; /**< Secondary Key */ 8584 } portmod_cpri_port_frame_config_t; 8585 8586 /* portmod_cpri_port_frame_config_t initialization and validation */ 8587 int portmod_cpri_port_frame_config_t_validate(int unit, const portmod_cpri_port_frame_config_t* portmod_cpri_port_frame_config); 8588 int portmod_cpri_port_frame_config_t_init(int unit, portmod_cpri_port_frame_config_t* portmod_cpri_port_frame_config); 8589 8590 #endif /* CPRIMOD_SUPPORT */ 8591 /*! 8592 * portmod_cpri_port_frame_config_set 8593 * 8594 * @brief Set CPRI port RoE frame formation configuration. 8595 * 8596 * @param [in] unit - unit id 8597 * @param [in] port - logical port 8598 * @param [in] config - Configuration 8599 */ 8600 #ifdef CPRIMOD_SUPPORT 8601 int portmod_cpri_port_frame_config_set(int unit, int port, const portmod_cpri_port_frame_config_t* config); 8602 #endif /* CPRIMOD_SUPPORT */ 8603 8604 /*! 8605 * portmod_cpri_port_compression_saturation_config_set 8606 * 8607 * @brief Setting the compression saturation threshold. 8608 * 8609 * @param [in] unit - unit id 8610 * @param [in] port - logical port 8611 * @param [in] threshold_value - Threshold Value 8612 */ 8613 #ifdef CPRIMOD_SUPPORT 8614 int portmod_cpri_port_compression_saturation_config_set(int unit, int port, uint32 threshold_value); 8615 #endif /* CPRIMOD_SUPPORT */ 8616 /*! 8617 * portmod_cpri_port_compression_saturation_config_get 8618 * 8619 * @brief Setting the compression saturation threshold. 8620 * 8621 * @param [in] unit - unit id 8622 * @param [in] port - logical port 8623 * @param [out] threshold_value - Threshold Value 8624 */ 8625 #ifdef CPRIMOD_SUPPORT 8626 int portmod_cpri_port_compression_saturation_config_get(int unit, int port, uint32* threshold_value); 8627 #endif /* CPRIMOD_SUPPORT */ 8628 8629 /*! 8630 * portmod_cpri_port_decompression_saturation_config_set 8631 * 8632 * @brief Setting the decompression saturation value. 8633 * 8634 * @param [in] unit - unit id 8635 * @param [in] port - logical port 8636 * @param [in] sat_value - Saturation Value 8637 */ 8638 #ifdef CPRIMOD_SUPPORT 8639 int portmod_cpri_port_decompression_saturation_config_set(int unit, int port, uint32 sat_value); 8640 #endif /* CPRIMOD_SUPPORT */ 8641 /*! 8642 * portmod_cpri_port_decompression_saturation_config_get 8643 * 8644 * @brief Setting the decompression saturation value. 8645 * 8646 * @param [in] unit - unit id 8647 * @param [in] port - logical port 8648 * @param [out] sat_value - Saturation Value 8649 */ 8650 #ifdef CPRIMOD_SUPPORT 8651 int portmod_cpri_port_decompression_saturation_config_get(int unit, int port, uint32* sat_value); 8652 #endif /* CPRIMOD_SUPPORT */ 8653 8654 #endif /*_PORTMOD_H_*/