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pm8x50_private.h (15473B)

      1 /*
      2  *
      3  * 
      4  *
      5  * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file.
      6  * 
      7  * Copyright 2007-2019 Broadcom Inc. All rights reserved.
      8  *
      9  *
     10  * Note: DO NOT INCLUDE THIS FILE IN ANY OTHER FILE OTHER THAN
     11  *       pm8x50.c
     12  */
     13 
     14 #ifndef _PM8X50_PRIVATE_H_
     15 #define _PM8X50_PRIVATE_H_
     16 
     17 /* portmod tsc interrupts type */
     18 typedef enum pm8x50_tsc_intr_type_e {
     19     pm8x50TscIntrEccNone,
     20     pm8x50TscIntrEcc1bErr,
     21     pm8x50TscIntrEcc1bErrRx1588400g = pm8x50TscIntrEcc1bErr,
     22     pm8x50TscIntrEcc1bErrRx1588Mpp1,
     23     pm8x50TscIntrEcc1bErrRx1588Mpp0,
     24     pm8x50TscIntrEcc1bErrTx1588400g,
     25     pm8x50TscIntrEcc1bErrTx1588Mpp1,
     26     pm8x50TscIntrEcc1bErrTx1588Mpp0,
     27     pm8x50TscIntrEcc1bErrUmTable,
     28     pm8x50TscIntrEcc1bErrAmTable,
     29     pm8x50TscIntrEcc1bErrSpeedTable,
     30     pm8x50TscIntrEcc1bErrDeskew,
     31     pm8x50TscIntrEcc1bErrRsfecRs400gMpp1,
     32     pm8x50TscIntrEcc1bErrRsfecRs400gMpp0,
     33     pm8x50TscIntrEcc1bErrRsfecRbufMpp1,
     34     pm8x50TscIntrEcc1bErrRsfecRbufMpp0,
     35     pm8x50TscIntrEcc1bErrBaseRFec,
     36     pm8x50TscIntrEcc1bErrCount = pm8x50TscIntrEcc1bErrBaseRFec,
     37     pm8x50TscIntrEcc2bErr,
     38     pm8x50TscIntrEcc2bErrRx1588400g = pm8x50TscIntrEcc2bErr,
     39     pm8x50TscIntrEcc2bErrRx1588Mpp1,
     40     pm8x50TscIntrEcc2bErrRx1588Mpp0,
     41     pm8x50TscIntrEcc2bErrTx1588400g,
     42     pm8x50TscIntrEcc2bErrTx1588Mpp1,
     43     pm8x50TscIntrEcc2bErrTx1588Mpp0,
     44     pm8x50TscIntrEcc2bErrUmTable,
     45     pm8x50TscIntrEcc2bErrAmTable,
     46     pm8x50TscIntrEcc2bErrSpdTable,
     47     pm8x50TscIntrEcc2bErrDeskew,
     48     pm8x50TscIntrEcc2bErrRsfecRs400gMpp1,
     49     pm8x50TscIntrEcc2bErrRsfecRs400gMpp0,
     50     pm8x50TscIntrEcc2bErrRsfecRbufMpp1,
     51     pm8x50TscIntrEcc2bErrRsfecRbufMpp0,
     52     pm8x50TscIntrEcc2bErrBaseRFec,
     53     pm8x50TscIntrEcc2bErrCount = pm8x50TscIntrEcc2bErrBaseRFec,
     54     pm8x50TscIntrEccCount
     55 }pm8x50_tsc_intr_type_t;
     56 
     57 
     58 /*
     59  * Macros to indicate the interrupt types(1-bit or 2-bit)
     60  * based on the register fields of the Portmacro.
     61  * CDPORT_TSC_INTR_STATUS,
     62  * TSC_ECC_1b_ERR - 15-bit field.
     63  * TSC_ECC_2b_ERR - 15-bit field.
     64  */
     65 #define PM8x50_TSC_ECC_1B_INTR     0x1
     66 #define PM8x50_TSC_ECC_2B_INTR     0x2
     67 
     68 
     69 /*
     70  * Each bit position in the register fields
     71  * TSC_ECC_2b_ERR, TSC_ECC_2b_ERR indicate
     72  * a TSC memory as under.
     73  * TSC_ECC_1b_ERR - 15-bit field.
     74  * TSC_ECC_2b_ERR - 15-bit field.
     75  *
     76  * bit 14: err_intr_en_rx_1588_400g
     77  * bit 13: err_intr_en_rx_1588_mpp1
     78  * bit 12: err_intr_en_rx_1588_mpp0
     79  * bit 11: err_intr_en_tx_1588_400g
     80  * bit 10: err_intr_en_tx_1588_mpp1
     81  * bit  9: err_intr_en_tx_1588_mpp0
     82  * bit  8: err_intr_en_um_tbl
     83  * bit  7: err_intr_en_am_tbl
     84  * bit  6: err_intr_en_spd_tbl
     85  * bit  5: err_intr_en_deskew
     86  * bit  4: err_intr_en_rsfec_rs400g_mpp1
     87  * bit  3: err_intr_en_rsfec_rs400g_mpp0
     88  * bit  2: err_intr_en_rsfec_rbuf_mpp1
     89  * bit  1: err_intr_en_rsfec_rbuf_mpp0
     90  * bit  0: err_intr_en_base_r_fec
     91  */
     92 /* Macros for 1-bit errors. */
     93 #define PM8x50_TSC_ECC_INTR_NONE                   0x0
     94 #define PM8x50_TSC_ECC_1B_INTR_RX_1588_400G        (1 << 14)
     95 #define PM8x50_TSC_ECC_1B_INTR_RX_1588_MPP1        (1 << 13)
     96 #define PM8x50_TSC_ECC_1B_INTR_RX_1588_MPP0        (1 << 12)
     97 #define PM8x50_TSC_ECC_1B_INTR_TX_1588_400G        (1 << 11)
     98 #define PM8x50_TSC_ECC_1B_INTR_TX_1588_MPP1        (1 << 10)
     99 #define PM8x50_TSC_ECC_1B_INTR_TX_1588_MPP0        (1 << 9)
    100 #define PM8x50_TSC_ECC_1B_INTR_UM_TABLE            (1 << 8)
    101 #define PM8x50_TSC_ECC_1B_INTR_AM_TABLE            (1 << 7)
    102 #define PM8x50_TSC_ECC_1B_INTR_SPEED_TABLE         (1 << 6)
    103 #define PM8x50_TSC_ECC_1B_INTR_DESKEW              (1 << 5)
    104 #define PM8x50_TSC_ECC_1B_INTR_RSFEC_400G_MPP1     (1 << 4)
    105 #define PM8x50_TSC_ECC_1B_INTR_RSFEC_400G_MPP0     (1 << 3)
    106 #define PM8x50_TSC_ECC_1B_INTR_RSFEC_RBUF_MPP1     (1 << 2)
    107 #define PM8x50_TSC_ECC_1B_INTR_RSFEC_RBUF_MPP0     (1 << 1)
    108 #define PM8x50_TSC_ECC_1B_INTR_BASE_R_FEC          (1 << 0)
    109 
    110 /* Macros for 2-bit errors. */
    111 #define PM8x50_TSC_ECC_2B_INTR_RX_1588_400G        (1 << 14)
    112 #define PM8x50_TSC_ECC_2B_INTR_RX_1588_MPP1        (1 << 13)
    113 #define PM8x50_TSC_ECC_2B_INTR_RX_1588_MPP0        (1 << 12)
    114 #define PM8x50_TSC_ECC_2B_INTR_TX_1588_400G        (1 << 11)
    115 #define PM8x50_TSC_ECC_2B_INTR_TX_1588_MPP1        (1 << 10)
    116 #define PM8x50_TSC_ECC_2B_INTR_TX_1588_MPP0        (1 << 9)
    117 #define PM8x50_TSC_ECC_2B_INTR_UM_TABLE            (1 << 8)
    118 #define PM8x50_TSC_ECC_2B_INTR_AM_TABLE            (1 << 7)
    119 #define PM8x50_TSC_ECC_2B_INTR_SPEED_TABLE         (1 << 6)
    120 #define PM8x50_TSC_ECC_2B_INTR_DESKEW              (1 << 5)
    121 #define PM8x50_TSC_ECC_2B_INTR_RSFEC_400G_MPP1     (1 << 4)
    122 #define PM8x50_TSC_ECC_2B_INTR_RSFEC_400G_MPP0     (1 << 3)
    123 #define PM8x50_TSC_ECC_2B_INTR_RSFEC_RBUF_MPP1     (1 << 2)
    124 #define PM8x50_TSC_ECC_2B_INTR_RSFEC_RBUF_MPP0     (1 << 1)
    125 #define PM8x50_TSC_ECC_2B_INTR_BASE_R_FEC          (1 << 0)
    126 
    127 #if 0
    128 /*!
    129  * PM8x50 TSC to phymod_phy_interrupt_type map.
    130  */
    131 typedef enum pm8x50_phymod_phy_interrupt_type_e {
    132      pm8x50PhymodIntrNone = 0x0,
    133      /**< RX 1588 400G ecc error */
    134      pm8x50PhymodIntrEccRx1588400g = phymodIntrEccRx1588400g,
    135      /**< RX 1588 Mpp1 ecc error */
    136      pm8x50PhymodIntrEccRx1588Mpp1 = phymodIntrEccRx1588Mpp1,
    137      /**< RX 1588 Mpp0 ecc error */
    138      pm8x50PhymodIntrEccRx1588Mpp0 = phymodIntrEccRx1588Mpp0,
    139      /**< TX 1588 400G ecc error */
    140      pm8x50PhymodIntrEccTx1588400g = phymodIntrEccTx1588400g,
    141      /**< TX 1588 Mpp1 ecc error */
    142      pm8x50PhymodIntrEccTx1588Mpp1 = phymodIntrEccTx1588Mpp1,
    143      /**< TX 1588 Mpp0 ecc error */
    144      pm8x50PhymodIntrEccTx1588Mpp0 = phymodIntrEccTx1588Mpp0,
    145      /**< UM table ecc error */
    146      pm8x50PhymodIntrEccUMTable = phymodIntrEccUMTable,
    147      /**< AM table ecc error */
    148      pm8x50PhymodIntrEccAMTable = phymodIntrEccAMTable,
    149      /**< Speed table ecc error */
    150      pm8x50PhymodIntrEccSpeedTable = phymodIntrEccSpeedTable,
    151      /**< Deskew ecc error */
    152      pm8x50PhymodIntrEccDeskew = phymodIntrEccDeskew,
    153      /**< Rsfec_Rs400g Mpp1 ecc error */
    154      pm8x50PhymodIntrEccRsfecRs400gMpp1 = phymodIntrEccRsFECRs400gMpp1,
    155      /**< Rsfec_Rs400g Mpp0 ecc error */
    156      pm8x50PhymodIntrEccRsfecRs400gMpp0 = phymodIntrEccRsFECRs400gMpp0,
    157      /**< RSFEC_RSBUF MPP1 ecc error */
    158      pm8x50PhymodIntrEccRsfecRbufMpp1 = phymodIntrEccRsFECRbufMpp1,
    159      /**< RSFEC_RSBUF MPP0 ecc error */
    160      pm8x50PhymodIntrEccRsfecRbufMpp0 = phymodIntrEccRsFECRbufMpp0,
    161      /**< BaseR FEC ecc error */
    162      pm8x50PhymodIntrEccBaseRFec = phymodIntrEccBaseRFEC,
    163      pm8x50PhymodIntrCount = phymodIntrCount
    164 } pm8x50_phymod_phy_interrupt_type_t;
    165 #endif
    166 
    167 typedef struct pm8x50_tsc_err_intr_phymod_map_e{
    168     uint32  flags;
    169     phymod_interrupt_type_t phymod_intr_map;
    170     char    *str;
    171 }pm8x50_tsc_err_intr_phymod_map_t;
    172 
    173 pm8x50_tsc_err_intr_phymod_map_t
    174          pm8x50_tsc_ecc_intr_info [pm8x50TscIntrEccCount] = {
    175     {
    176         PM8x50_TSC_ECC_INTR_NONE,
    177         phymodIntrNone,
    178         "Interrupt none" 
    179     },
    180     {
    181         PM8x50_TSC_ECC_1B_INTR_RX_1588_400G,
    182         phymodIntrEccRx1588400g,
    183         "1-bit RX 1588 400G ecc error"
    184     },
    185     {
    186         PM8x50_TSC_ECC_1B_INTR_RX_1588_MPP1,
    187         phymodIntrEccRx1588Mpp1,
    188         "1-bit RX 1588 Mpp1 ecc error"
    189     },
    190     {
    191         PM8x50_TSC_ECC_1B_INTR_RX_1588_MPP0,
    192         phymodIntrEccRx1588Mpp0,
    193         "1-bit RX 1588 Mpp0 ecc error"
    194     },
    195     {
    196         PM8x50_TSC_ECC_1B_INTR_TX_1588_400G,
    197         phymodIntrEccTx1588400g,
    198         "1-bit TX 1588 400G ecc error"
    199     },
    200     {
    201         PM8x50_TSC_ECC_1B_INTR_TX_1588_MPP1,
    202         phymodIntrEccTx1588Mpp1,
    203         "1-bit TX 1588 Mpp1 ecc error"
    204     },
    205     {
    206         PM8x50_TSC_ECC_1B_INTR_TX_1588_MPP0,
    207         phymodIntrEccTx1588Mpp0,
    208         "1-bit TX 1588 Mpp0 ecc error"
    209     },
    210     {
    211         PM8x50_TSC_ECC_1B_INTR_UM_TABLE,
    212         phymodIntrEccUMTable,
    213         "1-bit Unique Marker table ecc error"
    214     },
    215     {
    216         PM8x50_TSC_ECC_1B_INTR_AM_TABLE,
    217         phymodIntrEccAMTable,
    218         "1-bit Alignment Marker table ecc error"
    219     },
    220     {
    221         PM8x50_TSC_ECC_1B_INTR_SPEED_TABLE,
    222         phymodIntrEccSpeedTable,
    223         "1-bit Speed table ecc error"
    224     },
    225     {
    226         PM8x50_TSC_ECC_1B_INTR_DESKEW,
    227         phymodIntrEccDeskew,
    228         "1-bit Deskew ecc error"
    229     },
    230     {
    231         PM8x50_TSC_ECC_1B_INTR_RSFEC_400G_MPP1,
    232         phymodIntrEccRsFECRs400gMpp1,
    233         "1-bit RsFEC_Rs400g Mpp1 ecc error"
    234     },
    235     {
    236         PM8x50_TSC_ECC_1B_INTR_RSFEC_400G_MPP0,
    237         phymodIntrEccRsFECRs400gMpp0,
    238         "1-bit RsFEC_Rs400g Mpp1 ecc error"
    239     },
    240     {
    241         PM8x50_TSC_ECC_1B_INTR_RSFEC_RBUF_MPP1,
    242         phymodIntrEccRsFECRbufMpp1,
    243         "1-bit RsFEC_RBUF MPP1 ecc error"
    244     },
    245     {
    246         PM8x50_TSC_ECC_1B_INTR_RSFEC_RBUF_MPP0,
    247         phymodIntrEccRsFECRbufMpp0,
    248         "1-bit RsFEC_RBUF MPP0 ecc error"
    249     },
    250     {
    251         PM8x50_TSC_ECC_1B_INTR_BASE_R_FEC,
    252         phymodIntrEccBaseRFEC,
    253         "1-bit BaseR FEC ecc error"
    254     },
    255     {
    256         PM8x50_TSC_ECC_2B_INTR_RX_1588_400G,
    257         phymodIntrEccRx1588400g,
    258         "2-bit RX 1588 400G ecc error"
    259     },
    260     {
    261         PM8x50_TSC_ECC_2B_INTR_RX_1588_MPP1,
    262         phymodIntrEccRx1588Mpp1,
    263         "2-bit RX 1588 Mpp1 ecc error"
    264     },
    265     {
    266         PM8x50_TSC_ECC_2B_INTR_RX_1588_MPP0,
    267         phymodIntrEccRx1588Mpp0,
    268         "2-bit RX 1588 Mpp0 ecc error"
    269     },
    270     {
    271         PM8x50_TSC_ECC_2B_INTR_TX_1588_400G,
    272         phymodIntrEccTx1588400g,
    273         "2-bit TX 1588 400G ecc error"
    274     },
    275     {
    276         PM8x50_TSC_ECC_2B_INTR_TX_1588_MPP1,
    277         phymodIntrEccTx1588Mpp1,
    278         "2-bit TX 1588 Mpp1 ecc error"
    279     },
    280     {
    281         PM8x50_TSC_ECC_2B_INTR_TX_1588_MPP0,
    282         phymodIntrEccTx1588Mpp0,
    283         "2-bit TX 1588 Mpp0 ecc error"
    284     },
    285     {
    286         PM8x50_TSC_ECC_2B_INTR_UM_TABLE,
    287         phymodIntrEccUMTable,
    288         "2-bit Unique Marker table ecc error"
    289     },
    290     {
    291         PM8x50_TSC_ECC_2B_INTR_AM_TABLE,
    292         phymodIntrEccAMTable,
    293         "2-bit Alignment Marker table ecc error"
    294     },
    295     {
    296         PM8x50_TSC_ECC_2B_INTR_SPEED_TABLE,
    297         phymodIntrEccSpeedTable,
    298         "2-bit Speed table ecc error"
    299     },
    300     {
    301         PM8x50_TSC_ECC_2B_INTR_DESKEW,
    302         phymodIntrEccDeskew,
    303         "2-bit Deskew ecc error"
    304     },
    305     {
    306         PM8x50_TSC_ECC_2B_INTR_RSFEC_400G_MPP1,
    307         phymodIntrEccRsFECRs400gMpp1,
    308         "2-bit RsFEC_Rs400g Mpp1 ecc error"
    309     },
    310     {
    311         PM8x50_TSC_ECC_2B_INTR_RSFEC_400G_MPP0,
    312         phymodIntrEccRsFECRs400gMpp0,
    313         "2-bit RsFEC_Rs400g Mpp1 ecc error"
    314     },
    315     {
    316         PM8x50_TSC_ECC_2B_INTR_RSFEC_RBUF_MPP1,
    317         phymodIntrEccRsFECRbufMpp1,
    318         "2-bit RsFEC_RBUF MPP1 ecc error"
    319     },
    320     {
    321         PM8x50_TSC_ECC_2B_INTR_RSFEC_RBUF_MPP0,
    322         phymodIntrEccRsFECRbufMpp0,
    323         "2-bit RsFEC_RBUF MPP0 ecc error"
    324     },
    325     {
    326         PM8x50_TSC_ECC_2B_INTR_BASE_R_FEC,
    327         phymodIntrEccBaseRFEC,
    328         "2-bit BaseR FEC ecc error"
    329      }
    330 };
    331 
    332 portmod_intr_reg_info_t pm8x50_mac_intr_info[] = {
    333     {
    334         PORTMOD_INTR_STATUS_COR | PORTMOD_INTR_BLOCK_CLEAR_REG |
    335         PORTMOD_INTR_ECC_1B_ERR,
    336         portmodIntrTypeMibMemSingleBitErr,
    337         CDMAC_INTR_ENABLEr, MIB_COUNTER_SINGLE_BIT_ERRf,
    338         CDMAC_INTR_STATUSr, MIB_COUNTER_SINGLE_BIT_ERRf,
    339         CDMAC_ECC_STATUSr, MIB_COUNTER_SINGLE_BIT_ERRf,
    340         "CDMAC MIB single bit error"
    341     },
    342     {
    343         PORTMOD_INTR_STATUS_COR | PORTMOD_INTR_BLOCK_CLEAR_REG |
    344         PORTMOD_INTR_ECC_2B_ERR,
    345         portmodIntrTypeMibMemDoubleBitErr,
    346         CDMAC_INTR_ENABLEr, MIB_COUNTER_DOUBLE_BIT_ERRf,
    347         CDMAC_INTR_STATUSr, MIB_COUNTER_DOUBLE_BIT_ERRf,
    348         CDMAC_ECC_STATUSr, MIB_COUNTER_DOUBLE_BIT_ERRf,
    349         "CDMAC MIB double bit error"
    350     },
    351     {
    352         PORTMOD_INTR_STATUS_COR | PORTMOD_INTR_BLOCK_CLEAR_REG |
    353         PORTMOD_INTR_ECC_MULTIB_ERR,
    354         portmodIntrTypeMibMemMultipleBitErr,
    355         CDMAC_INTR_ENABLEr, MIB_COUNTER_MULTIPLE_ERRf,
    356         CDMAC_INTR_STATUSr, MIB_COUNTER_MULTIPLE_ERRf,
    357         CDMAC_ECC_STATUSr, MIB_COUNTER_MULTIPLE_ERRf,
    358         "CDMAC MIB Multiple bit error"
    359     },
    360     {
    361         PORTMOD_INTR_STATUS_COR | PORTMOD_INTR_BLOCK_CLEAR_REG |
    362         PORTMOD_INTR_ECC_1B_ERR,
    363         portmodIntrTypeTxCdcSingleBitErr,
    364         CDMAC_INTR_ENABLEr, TX_CDC_SINGLE_BIT_ERRf,
    365         CDMAC_INTR_STATUSr, TX_CDC_SINGLE_BIT_ERRf,
    366         CDMAC_ECC_STATUSr, TX_CDC_SINGLE_BIT_ERRf,
    367         "CDMAC TX CDC single bit error"
    368     },
    369     {
    370         PORTMOD_INTR_STATUS_COR | PORTMOD_INTR_BLOCK_CLEAR_REG |
    371         PORTMOD_INTR_ECC_1B_ERR,
    372         portmodIntrTypeTxCdcDoubleBitErr,
    373         CDMAC_INTR_ENABLEr, TX_CDC_DOUBLE_BIT_ERRf,
    374         CDMAC_INTR_STATUSr, TX_CDC_DOUBLE_BIT_ERRf,
    375         CDMAC_ECC_STATUSr, TX_CDC_DOUBLE_BIT_ERRf,
    376         "CDMAC TX CDC double bit error"
    377     },
    378     {
    379         PORTMOD_INTR_STATUS_COR | PORTMOD_INTR_BLOCK_CLEAR_REG,
    380         portmodIntrTypeTxPktUnderflow,
    381         CDMAC_INTR_ENABLEr, TX_PKT_UNDERFLOWf,
    382         CDMAC_INTR_STATUSr, TX_PKT_UNDERFLOWf,
    383         CDMAC_INTR_STATUSr, TX_PKT_UNDERFLOWf,
    384         "CDMAC TX packet underflow interrupt"
    385     },
    386     {
    387         PORTMOD_INTR_STATUS_COR | PORTMOD_INTR_BLOCK_CLEAR_REG,
    388         portmodIntrTypeTxPktOverflow,
    389         CDMAC_INTR_ENABLEr, TX_PKT_OVERFLOWf,
    390         CDMAC_INTR_STATUSr, TX_PKT_OVERFLOWf,
    391         CDMAC_INTR_STATUSr, TX_PKT_OVERFLOWf,
    392         "CDMAC TX packet overflow interrupt"
    393     },
    394     {
    395         0x0, /* No flags */
    396         portmodIntrTypeCount,
    397         INVALIDr, INVALIDf,
    398         INVALIDr, INVALIDf,
    399         INVALIDr, INVALIDf,
    400         " "
    401     }
    402 };
    403 
    404 portmod_intr_reg_info_t pm8x50_tsc_core_intr_info[] = {
    405     {
    406         PORTMOD_INTR_STATUS_W1TC | PORTMOD_INTR_STATUS_BIT_FLDS |
    407         PORTMOD_INTR_ECC_2B_ERR,
    408         portmodIntrTypeTscCore0Err,
    409         INVALIDr, INVALIDf,
    410         CDPORT_TSC_INTR_STATUSr, TSC_ECC_2B_ERRf,
    411         INVALIDr, INVALIDf,
    412         " "
    413     },
    414     {
    415         PORTMOD_INTR_STATUS_W1TC | PORTMOD_INTR_STATUS_BIT_FLDS |
    416         PORTMOD_INTR_ECC_1B_ERR,
    417         portmodIntrTypeTscCore0Err,
    418         INVALIDr, INVALIDf,
    419         CDPORT_TSC_INTR_STATUSr, TSC_ECC_1B_ERRf,
    420         INVALIDr, INVALIDf,
    421         " "
    422     }
    423 };
    424 
    425 portmod_pm_intr_info_t pm8x50_pm_intr_info[] = {
    426     {
    427         portmodIntrTypeMacErr, CDPORT_INTR_ENABLEr, MAC_ERRf,
    428         1, pm8x50_mac_intr_info,
    429         CDPORT_INTR_STATUSr, MAC_ERRf,
    430         1, pm8x50_mac_intr_info,
    431         INVALIDr, INVALIDf,
    432         0, NULL,
    433         INVALIDm, "PM MAC error interrupt"
    434     },
    435     {
    436         portmodIntrTypeTscCore0Err, CDPORT_INTR_ENABLEr, TSC_CORE0_ERRf,
    437         1, pm8x50_tsc_core_intr_info,
    438         CDPORT_INTR_STATUSr, TSC_CORE0_ERRf,
    439         1, pm8x50_tsc_core_intr_info,
    440         INVALIDr, INVALIDf,
    441         0, NULL,
    442         INVALIDm, "PM TSC Core0 error interrupt"
    443     },
    444     {
    445         portmodIntrTypeTscCore1Err, CDPORT_INTR_ENABLEr, TSC_CORE1_ERRf,
    446         1, pm8x50_tsc_core_intr_info,
    447         CDPORT_INTR_STATUSr, TSC_CORE1_ERRf,
    448         1, pm8x50_tsc_core_intr_info,
    449         INVALIDr, INVALIDf,
    450         0, NULL,
    451         INVALIDm, "PM TSC Core1 error interrupt"
    452     },
    453     {
    454         portmodIntrTypeFcReqFull, CDPORT_INTR_ENABLEr, FLOWCONTROL_REQ_FULLf,
    455         0, NULL,
    456         CDPORT_INTR_STATUSr, FLOWCONTROL_REQ_FULLf,
    457         0, NULL,
    458         INVALIDr, INVALIDf,
    459         0, NULL,
    460         INVALIDm, "PM Flow cotrol request interrupt"
    461     },
    462     {
    463         portmodIntrTypePmdErr, CDPORT_INTR_ENABLEr, PMD_ERRf,
    464         0, NULL,
    465         CDPORT_INTR_STATUSr, PMD_ERRf,
    466         0, NULL,
    467         INVALIDr, INVALIDf,
    468         0, NULL,
    469         INVALIDm, "PM PMD error interrupt"
    470     }
    471 };
    472 
    473 #endif /*_PM8X50_PRIVATE_H_*/