port_ability.h (7440B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * This file defines common network port modes. 8 * 9 * Its contents are not used directly by applications; it is used only 10 * by header files of parent APIs which need to define port modes. 11 */ 12 13 #ifndef _SOC_PORTABILITY_H 14 #define _SOC_PORTABILITY_H 15 16 #include <shared/port_ability.h> 17 18 typedef _shr_port_ability_t soc_port_ability_t; 19 20 #define SOC_PA_ABILITY_ALL _SHR_PA_ABILITY_ALL 21 #define SOC_PA_ABILITY_NONE _SHR_PA_ABILITY_NONE 22 23 24 typedef _shr_pa_encap_t soc_pa_encap_t; 25 26 #define SOC_PA_ENCAP_IEEE _SHR_PA_ENCAP_IEEE 27 #define SOC_PA_ENCAP_HIGIG _SHR_PA_ENCAP_HIGIG 28 #define SOC_PA_ENCAP_B5632 _SHR_PA_ENCAP_B5632 29 #define SOC_PA_ENCAP_HIGIG2 _SHR_PA_ENCAP_HIGIG2 30 #define SOC_PA_ENCAP_HIGIG2_LITE _SHR_PA_ENCAP_HIGIG2_LITE 31 #define SOC_PA_ENCAP_HIGIG2_L2 _SHR_PA_ENCAP_HIGIG2_L2 32 #define SOC_PA_ENCAP_HIGIG2_IP_GRE _SHR_PA_ENCAP_HIGIG2_IP_GRE 33 #define SOC_PA_ENCAP_OBSOLETE _SHR_PA_ENCAP_OBSOLETE 34 #define SOC_PA_ENCAP_HIGIG_OVER_ETHERNET _SHR_PA_ENCAP_HIGIG_OVER_ETHERNET 35 36 #define SOC_PA_ENCAP_STRING _SHR_PA_ENCAP_STRING 37 38 39 /* 40 * Defines: 41 * SOC_PA_SPEED_* 42 * Purpose: 43 * Defines for port speeds. 44 */ 45 #define SOC_PA_SPEED_10MB _SHR_PA_SPEED_10MB 46 #define SOC_PA_SPEED_100MB _SHR_PA_SPEED_100MB 47 #define SOC_PA_SPEED_1000MB _SHR_PA_SPEED_1000MB 48 #define SOC_PA_SPEED_2500MB _SHR_PA_SPEED_2500MB 49 #define SOC_PA_SPEED_3000MB _SHR_PA_SPEED_3000MB 50 #define SOC_PA_SPEED_5000MB _SHR_PA_SPEED_5000MB 51 #define SOC_PA_SPEED_6000MB _SHR_PA_SPEED_6000MB 52 #define SOC_PA_SPEED_10GB _SHR_PA_SPEED_10GB 53 #define SOC_PA_SPEED_11GB _SHR_PA_SPEED_11GB 54 #define SOC_PA_SPEED_12GB _SHR_PA_SPEED_12GB 55 #define SOC_PA_SPEED_12P5GB _SHR_PA_SPEED_12P5GB 56 #define SOC_PA_SPEED_13GB _SHR_PA_SPEED_13GB 57 #define SOC_PA_SPEED_15GB _SHR_PA_SPEED_15GB 58 #define SOC_PA_SPEED_16GB _SHR_PA_SPEED_16GB 59 #define SOC_PA_SPEED_20GB _SHR_PA_SPEED_20GB 60 #define SOC_PA_SPEED_21GB _SHR_PA_SPEED_21GB 61 #define SOC_PA_SPEED_23GB _SHR_PA_SPEED_23GB 62 #define SOC_PA_SPEED_24GB _SHR_PA_SPEED_24GB 63 #define SOC_PA_SPEED_25GB _SHR_PA_SPEED_25GB 64 #define SOC_PA_SPEED_27GB _SHR_PA_SPEED_27GB 65 #define SOC_PA_SPEED_30GB _SHR_PA_SPEED_30GB 66 #define SOC_PA_SPEED_32GB _SHR_PA_SPEED_32GB 67 #define SOC_PA_SPEED_40GB _SHR_PA_SPEED_40GB 68 #define SOC_PA_SPEED_42GB _SHR_PA_SPEED_42GB 69 #define SOC_PA_SPEED_48GB _SHR_PA_SPEED_48GB 70 #define SOC_PA_SPEED_50GB _SHR_PA_SPEED_50GB 71 #define SOC_PA_SPEED_53GB _SHR_PA_SPEED_53GB 72 #define SOC_PA_SPEED_100GB _SHR_PA_SPEED_100GB 73 #define SOC_PA_SPEED_106GB _SHR_PA_SPEED_106GB 74 #define SOC_PA_SPEED_120GB _SHR_PA_SPEED_120GB 75 #define SOC_PA_SPEED_127GB _SHR_PA_SPEED_127GB 76 #define SOC_PA_SPEED_EXTENDED _SHR_PA_SPEED_EXTENDED 77 78 /* NOTE: these speeds are overlayed with 10MB and EXTENDED */ 79 #define SOC_PA_SPEED_200GB _SHR_PA_SPEED_200GB 80 #define SOC_PA_SPEED_400GB _SHR_PA_SPEED_400GB 81 82 #define SOC_PA_SPEED_STRING _SHR_PA_SPEED_STRING 83 84 /* 85 * Defines: 86 * SOC_PA_PAUSE_* 87 * Purpose: 88 * Defines for flow control abilities. 89 */ 90 #define SOC_PA_PAUSE_TX _SHR_PA_PAUSE_TX 91 #define SOC_PA_PAUSE_RX _SHR_PA_PAUSE_RX 92 #define SOC_PA_PAUSE_ASYMM _SHR_PA_PAUSE_ASYMM 93 94 #define SOC_PA_PAUSE_STRING _SHR_PA_PAUSE_STRING 95 96 97 /* 98 * Defines: 99 * SOC_PA_FEC_* 100 * Purpose: 101 * Defines for FEC abilities. 102 */ 103 #define SOC_PA_FEC_NONE _SHR_PA_FEC_NONE 104 #define SOC_PA_FEC_CL74 _SHR_PA_FEC_CL74 105 #define SOC_PA_FEC_CL91 _SHR_PA_FEC_CL91 106 #define SOC_PA_FEC_STRING _SHR_PA_FEC_STRING 107 108 /* 109 * Defines: 110 * SOC_PA_CHANNEL_* 111 * Purpose: 112 * Defines for CHANNEL abilities. 113 */ 114 #define SOC_PA_CHANNEL_LONG _SHR_PA_CHANNEL_LONG 115 #define SOC_PA_CHANNEL_SHORT _SHR_PA_CHANNEL_SHORT 116 117 /* 118 * Defines: 119 * SOC_PA_INTF_* 120 * Purpose: 121 * Defines for port interfaces supported. 122 */ 123 #define SOC_PA_INTF_TBI _SHR_PA_INTF_TBI 124 #define SOC_PA_INTF_MII _SHR_PA_INTF_MII 125 #define SOC_PA_INTF_GMII _SHR_PA_INTF_GMII 126 #define SOC_PA_INTF_RGMII _SHR_PA_INTF_RGMII 127 #define SOC_PA_INTF_SGMII _SHR_PA_INTF_SGMII 128 #define SOC_PA_INTF_XGMII _SHR_PA_INTF_XGMII 129 #define SOC_PA_INTF_QSGMII _SHR_PA_INTF_QSGMII 130 #define SOC_PA_INTF_CGMII _SHR_PA_INTF_CGMII 131 132 #define SOC_PA_INTF_STRING _SHR_PA_INTF_STRING 133 134 /* 135 * Defines: 136 * SOC_PA_MEDIUM_* 137 * Purpose: 138 * Defines for port medium modes. 139 */ 140 #define SOC_PA_MEDIUM_COPPER _SHR_PA_MEDIUM_COPPER 141 #define SOC_PA_MEDIUM_FIBER _SHR_PA_MEDIUM_FIBER 142 #define SOC_PA_MEDIUM_BACKPLANE _SHR_PA_MEDIUM_BACKPLANE 143 144 #define SOC_PA_MEDIUM_STRING _SHR_PA_MEDIUM_STRING 145 146 /* 147 * Defines: 148 * SOC_PA_LOOPBACK_* 149 * Purpose: 150 * Defines for port loopback modes. 151 */ 152 #define SOC_PA_LB_NONE _SHR_PA_LB_NONE 153 #define SOC_PA_LB_MAC _SHR_PA_LB_MAC 154 #define SOC_PA_LB_PHY _SHR_PA_LB_PHY 155 #define SOC_PA_LB_LINE _SHR_PA_LB_LINE 156 157 #define SOC_PA_LB_STRING _SHR_PA_LB_STRING 158 159 /* 160 * Defines: 161 * SOC_PA_FLAGS_* 162 * Purpose: 163 * Defines for the reest of port ability flags. 164 */ 165 #define SOC_PA_AUTONEG _SHR_PA_AUTONEG 166 #define SOC_PA_COMBO _SHR_PA_COMBO 167 168 169 #define SOC_PA_FLAGS_STRING _SHR_PA_FLAGS_STRING 170 171 /* Ability filters */ 172 173 #define SOC_PA_PAUSE _SHR_PA_PAUSE 174 175 #define SOC_PA_SPEED_ALL _SHR_PA_SPEED_ALL 176 177 #define SOC_PA_SPEED_MAX(m) _SHR_PA_SPEED_MAX(m) 178 179 #define SOC_PA_SPEED_MAX_EXTENDED(m) _SHR_PA_SPEED_MAX_EXTENDED(m) 180 181 #define SOC_PA_SPEED(s) _SHR_PA_SPEED(s) 182 183 #define SOC_PA_IS_HG_SPEED(m) _SHR_PA_IS_HG_SPEED(m) 184 185 #define SOC_PORT_ABILITY_SFI _SHR_PORT_ABILITY_SFI 186 #define SOC_PORT_ABILITY_DUAL_SFI _SHR_PORT_ABILITY_DUAL_SFI 187 #define SOC_PORT_ABILITY_SCI _SHR_PORT_ABILITY_SCI 188 #define SOC_PORT_ABILITY_SFI_SCI _SHR_PORT_ABILITY_SFI_SCI 189 190 191 /* EEE Abilities */ 192 #define SOC_PA_EEE_100MB_BASETX _SHR_PA_EEE_100MB_BASETX 193 #define SOC_PA_EEE_1GB_BASET _SHR_PA_EEE_1GB_BASET 194 #define SOC_PA_EEE_10GB_BASET _SHR_PA_EEE_10GB_BASET 195 #define SOC_PA_EEE_10GB_KX _SHR_PA_EEE_10GB_KX 196 #define SOC_PA_EEE_10GB_KX4 _SHR_PA_EEE_10GB_KX4 197 #define SOC_PA_EEE_10GB_KR _SHR_PA_EEE_10GB_KR 198 199 #define SOC_PA_EEE_STRING _SHR_PA_EEE_STRING 200 201 /* FCMAP Abilities */ 202 203 #define SOC_PA_FCMAP _SHR_PA_FCMAP 204 #define SOC_PA_FCMAP_FCMAC_LOOPBACK _SHR_PA_FCMAP_FCMAC_LOOPBACK 205 #define SOC_PA_FCMAP_AUTONEG _SHR_PA_FCMAP_AUTONEG 206 #define SOC_PA_FCMAP_2GB _SHR_PA_FCMAP_2GB 207 #define SOC_PA_FCMAP_4GB _SHR_PA_FCMAP_4GB 208 #define SOC_PA_FCMAP_8GB _SHR_PA_FCMAP_8GB 209 #define SOC_PA_FCMAP_16GB _SHR_PA_FCMAP_16GB 210 211 #define SOC_PA_FCMAP_STRING _SHR_PA_FCMAP_STRING 212 /* Port ability functions */ 213 extern int 214 soc_port_mode_to_ability(soc_port_mode_t mode, soc_port_ability_t *ability); 215 216 extern int 217 soc_port_ability_to_mode(soc_port_ability_t *ability, soc_port_mode_t *mode); 218 219 extern int 220 soc_port_ability_mask(soc_port_ability_t *ability, soc_port_ability_t *mask); 221 222 #endif /* !_SOC_PORTABILITY_H */