phyctrl.h (78635B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * File: phyctrl.h 8 * 9 * Data structures and function prototypes for PHY register access. 10 */ 11 12 #ifndef _SOC_PHYCTRL_H_ 13 #define _SOC_PHYCTRL_H_ 14 #include <shared/port.h> 15 #include <sal/core/time.h> 16 #include <soc/portmode.h> 17 #include <soc/port_ability.h> 18 #include <soc/types.h> 19 20 /* PHY specific control settings */ 21 typedef enum soc_phy_control_e { 22 SOC_PHY_CONTROL_WAN = _SHR_PORT_PHY_CONTROL_WAN, 23 SOC_PHY_CONTROL_PREEMPHASIS = _SHR_PORT_PHY_CONTROL_PREEMPHASIS, 24 SOC_PHY_CONTROL_DRIVER_CURRENT = _SHR_PORT_PHY_CONTROL_DRIVER_CURRENT, 25 SOC_PHY_CONTROL_PRE_DRIVER_CURRENT = 26 _SHR_PORT_PHY_CONTROL_PRE_DRIVER_CURRENT, 27 SOC_PHY_CONTROL_EQUALIZER_BOOST = 28 _SHR_PORT_PHY_CONTROL_EQUALIZER_BOOST, 29 SOC_PHY_CONTROL_INTERFACE = _SHR_PORT_PHY_CONTROL_INTERFACE, 30 SOC_PHY_CONTROL_INTERFACE_MAX = _SHR_PORT_PHY_CONTROL_INTERFACE_MAX, 31 SOC_PHY_CONTROL_MACSEC_SWITCH_FIXED = 32 _SHR_PORT_PHY_CONTROL_MACSEC_SWITCH_FIXED, 33 SOC_PHY_CONTROL_MACSEC_SWITCH_FIXED_SPEED = 34 _SHR_PORT_PHY_CONTROL_MACSEC_SWITCH_FIXED_SPEED, 35 SOC_PHY_CONTROL_MACSEC_SWITCH_FIXED_DUPLEX = 36 _SHR_PORT_PHY_CONTROL_MACSEC_SWITCH_FIXED_DUPLEX, 37 SOC_PHY_CONTROL_MACSEC_SWITCH_FIXED_PAUSE = 38 _SHR_PORT_PHY_CONTROL_MACSEC_SWITCH_FIXED_PAUSE, 39 SOC_PHY_CONTROL_MACSEC_PAUSE_RX_FORWARD = 40 _SHR_PORT_PHY_CONTROL_MACSEC_PAUSE_RX_FORWARD, 41 SOC_PHY_CONTROL_MACSEC_PAUSE_TX_FORWARD = 42 _SHR_PORT_PHY_CONTROL_MACSEC_PAUSE_TX_FORWARD, 43 SOC_PHY_CONTROL_MACSEC_LINE_IPG = 44 _SHR_PORT_PHY_CONTROL_MACSEC_LINE_IPG, 45 SOC_PHY_CONTROL_MACSEC_SWITCH_IPG = 46 _SHR_PORT_PHY_CONTROL_MACSEC_SWITCH_IPG, 47 SOC_PHY_CONTROL_LONGREACH_SPEED = 48 _SHR_PORT_PHY_CONTROL_LONGREACH_SPEED, 49 SOC_PHY_CONTROL_LONGREACH_PAIRS = 50 _SHR_PORT_PHY_CONTROL_LONGREACH_PAIRS, 51 SOC_PHY_CONTROL_LONGREACH_GAIN = 52 _SHR_PORT_PHY_CONTROL_LONGREACH_GAIN, 53 SOC_PHY_CONTROL_LONGREACH_AUTONEG = 54 _SHR_PORT_PHY_CONTROL_LONGREACH_AUTONEG, 55 SOC_PHY_CONTROL_LONGREACH_LOCAL_ABILITY = 56 _SHR_PORT_PHY_CONTROL_LONGREACH_LOCAL_ABILITY, 57 SOC_PHY_CONTROL_LONGREACH_REMOTE_ABILITY = 58 _SHR_PORT_PHY_CONTROL_LONGREACH_REMOTE_ABILITY, 59 SOC_PHY_CONTROL_LONGREACH_CURRENT_ABILITY = 60 _SHR_PORT_PHY_CONTROL_LONGREACH_CURRENT_ABILITY, 61 SOC_PHY_CONTROL_LONGREACH_MASTER = 62 _SHR_PORT_PHY_CONTROL_LONGREACH_MASTER, 63 SOC_PHY_CONTROL_LONGREACH_ACTIVE = 64 _SHR_PORT_PHY_CONTROL_LONGREACH_ACTIVE, 65 SOC_PHY_CONTROL_LONGREACH_ENABLE = 66 _SHR_PORT_PHY_CONTROL_LONGREACH_ENABLE, 67 SOC_PHY_CONTROL_LOOPBACK_EXTERNAL = 68 _SHR_PORT_PHY_CONTROL_LOOPBACK_EXTERNAL, 69 SOC_PHY_CONTROL_CLOCK_ENABLE = 70 _SHR_PORT_PHY_CONTROL_CLOCK_ENABLE, 71 SOC_PHY_CONTROL_CLOCK_SECONDARY_ENABLE = 72 _SHR_PORT_PHY_CONTROL_CLOCK_SECONDARY_ENABLE, 73 SOC_PHY_CONTROL_CLOCK_FREQUENCY = 74 _SHR_PORT_PHY_CONTROL_CLOCK_FREQUENCY, 75 SOC_PHY_CONTROL_CLOCK_MODE_AUTO = 76 _SHR_PORT_PHY_CONTROL_CLOCK_MODE_AUTO, 77 SOC_PHY_CONTROL_CLOCK_AUTO_SECONDARY = 78 _SHR_PORT_PHY_CONTROL_CLOCK_AUTO_SECONDARY, 79 SOC_PHY_CONTROL_CLOCK_SOURCE = 80 _SHR_PORT_PHY_CONTROL_CLOCK_SOURCE, 81 SOC_PHY_CONTROL_PORT_PRIMARY = 82 _SHR_PORT_PHY_CONTROL_PORT_PRIMARY, 83 SOC_PHY_CONTROL_PORT_OFFSET = 84 _SHR_PORT_PHY_CONTROL_PORT_OFFSET, 85 SOC_PHY_CONTROL_PRE_PREEMPHASIS= _SHR_PORT_PHY_CONTROL_PRE_PREEMPHASIS, 86 SOC_PHY_CONTROL_ENCODING = _SHR_PORT_PHY_CONTROL_ENCODING, 87 SOC_PHY_CONTROL_SCRAMBLER = _SHR_PORT_PHY_CONTROL_SCRAMBLER, 88 SOC_PHY_CONTROL_PRBS_POLYNOMIAL= _SHR_PORT_PHY_CONTROL_PRBS_POLYNOMIAL, 89 SOC_PHY_CONTROL_PRBS_TX_INVERT_DATA = 90 _SHR_PORT_PHY_CONTROL_PRBS_TX_INVERT_DATA, 91 SOC_PHY_CONTROL_PRBS_TX_ENABLE = _SHR_PORT_PHY_CONTROL_PRBS_TX_ENABLE, 92 SOC_PHY_CONTROL_PRBS_RX_ENABLE = _SHR_PORT_PHY_CONTROL_PRBS_RX_ENABLE, 93 SOC_PHY_CONTROL_PRBS_RX_STATUS = _SHR_PORT_PHY_CONTROL_PRBS_RX_STATUS, 94 SOC_PHY_CONTROL_SERDES_DRIVER_TUNE = 95 _SHR_PORT_PHY_CONTROL_SERDES_DRIVER_TUNE, 96 SOC_PHY_CONTROL_SERDES_DRIVER_EQUALIZATION_TUNE_STATUS_FAR_END = 97 _SHR_PORT_PHY_CONTROL_SERDES_DRIVER_EQUALIZATION_TUNE_STATUS_FAR_END, 98 SOC_PHY_CONTROL_8B10B = _SHR_PORT_PHY_CONTROL_8B10B, 99 SOC_PHY_CONTROL_64B66B = _SHR_PORT_PHY_CONTROL_64B66B, 100 SOC_PHY_CONTROL_POWER = _SHR_PORT_PHY_CONTROL_POWER, 101 SOC_PHY_CONTROL_POWER_AUTO_SLEEP_TIME = 102 _SHR_PORT_PHY_CONTROL_POWER_AUTO_SLEEP_TIME, 103 SOC_PHY_CONTROL_POWER_AUTO_WAKE_TIME = 104 _SHR_PORT_PHY_CONTROL_POWER_AUTO_WAKE_TIME, 105 SOC_PHY_CONTROL_LINKDOWN_TRANSMIT = 106 _SHR_PORT_PHY_CONTROL_LINKDOWN_TRANSMIT, 107 SOC_PHY_CONTROL_EDC_CONFIG = _SHR_PORT_PHY_CONTROL_EDC_CONFIG, 108 SOC_PHY_CONTROL_EDC_MODE = _SHR_PORT_PHY_CONTROL_EDC_MODE, 109 SOC_PHY_CONTROL_EEE = _SHR_PORT_PHY_CONTROL_EEE, 110 SOC_PHY_CONTROL_EEE_AUTO = _SHR_PORT_PHY_CONTROL_EEE_AUTO, 111 SOC_PHY_CONTROL_EEE_AUTO_IDLE_THRESHOLD = 112 _SHR_PORT_PHY_CONTROL_EEE_AUTO_IDLE_THRESHOLD, 113 SOC_PHY_CONTROL_EEE_AUTO_BUFFER_LIMIT = 114 _SHR_PORT_PHY_CONTROL_EEE_AUTO_BUFFER_LIMIT, 115 SOC_PHY_CONTROL_EEE_AUTO_FIXED_LATENCY = 116 _SHR_PORT_PHY_CONTROL_EEE_AUTO_FIXED_LATENCY, 117 SOC_PHY_CONTROL_EEE_TRANSMIT_WAKE_TIME = 118 _SHR_PORT_PHY_CONTROL_EEE_TRANSMIT_WAKE_TIME, 119 SOC_PHY_CONTROL_EEE_RECEIVE_WAKE_TIME = 120 _SHR_PORT_PHY_CONTROL_EEE_RECEIVE_WAKE_TIME, 121 SOC_PHY_CONTROL_EEE_TRANSMIT_SLEEP_TIME = 122 _SHR_PORT_PHY_CONTROL_EEE_TRANSMIT_SLEEP_TIME, 123 SOC_PHY_CONTROL_EEE_RECEIVE_SLEEP_TIME= 124 _SHR_PORT_PHY_CONTROL_EEE_RECEIVE_SLEEP_TIME, 125 SOC_PHY_CONTROL_EEE_TRANSMIT_QUIET_TIME = 126 _SHR_PORT_PHY_CONTROL_EEE_TRANSMIT_QUIET_TIME, 127 SOC_PHY_CONTROL_EEE_RECEIVE_QUIET_TIME = 128 _SHR_PORT_PHY_CONTROL_EEE_RECEIVE_QUIET_TIME, 129 SOC_PHY_CONTROL_EEE_TRANSMIT_REFRESH_TIME = 130 _SHR_PORT_PHY_CONTROL_EEE_TRANSMIT_REFRESH_TIME, 131 SOC_PHY_CONTROL_EEE_TRANSMIT_EVENTS = 132 _SHR_PORT_PHY_CONTROL_EEE_TRANSMIT_EVENTS, 133 SOC_PHY_CONTROL_EEE_TRANSMIT_DURATION = 134 _SHR_PORT_PHY_CONTROL_EEE_TRANSMIT_DURATION, 135 SOC_PHY_CONTROL_EEE_RECEIVE_EVENTS = 136 _SHR_PORT_PHY_CONTROL_EEE_RECEIVE_EVENTS, 137 SOC_PHY_CONTROL_EEE_RECEIVE_DURATION = 138 _SHR_PORT_PHY_CONTROL_EEE_RECEIVE_DURATION, 139 SOC_PHY_CONTROL_EEE_STATISTICS_CLEAR = 140 _SHR_PORT_PHY_CONTROL_EEE_STATISTICS_CLEAR, 141 SOC_PHY_CONTROL_SERDES_TUNE_MARGIN_MAX = 142 _SHR_PORT_PHY_CONTROL_SERDES_TUNE_MARGIN_MAX, 143 SOC_PHY_CONTROL_SERDES_TUNE_MARGIN_MODE = 144 _SHR_PORT_PHY_CONTROL_SERDES_TUNE_MARGIN_MODE, 145 SOC_PHY_CONTROL_SERDES_TUNE_MARGIN_VALUE = 146 _SHR_PORT_PHY_CONTROL_SERDES_TUNE_MARGIN_VALUE, 147 SOC_PHY_CONTROL_PARALLEL_DETECTION = 148 _SHR_PORT_PHY_CONTROL_PARALLEL_DETECTION, 149 SOC_PHY_CONTROL_PARALLEL_DETECTION_10G = 150 _SHR_PORT_PHY_CONTROL_PARALLEL_DETECTION_10G, 151 SOC_PHY_CONTROL_LOOPBACK_INTERNAL = 152 _SHR_PORT_PHY_CONTROL_LOOPBACK_INTERNAL, 153 SOC_PHY_CONTROL_LOOPBACK_REMOTE = 154 _SHR_PORT_PHY_CONTROL_LOOPBACK_REMOTE, 155 SOC_PHY_CONTROL_LOOPBACK_REMOTE_PCS_BYPASS = 156 _SHR_PORT_PHY_CONTROL_LOOPBACK_REMOTE_PCS_BYPASS, 157 SOC_PHY_CONTROL_FORWARD_ERROR_CORRECTION = 158 _SHR_PORT_PHY_CONTROL_FORWARD_ERROR_CORRECTION, /* this is mainly used cl74 */ 159 SOC_PHY_CONTROL_CUSTOM1 = 160 _SHR_PORT_PHY_CONTROL_CUSTOM1, 161 SOC_PHY_CONTROL_BERT_PATTERN = _SHR_PORT_PHY_CONTROL_BERT_PATTERN, 162 SOC_PHY_CONTROL_BERT_RUN = _SHR_PORT_PHY_CONTROL_BERT_RUN, 163 SOC_PHY_CONTROL_BERT_PACKET_SIZE = _SHR_PORT_PHY_CONTROL_BERT_PACKET_SIZE, 164 SOC_PHY_CONTROL_BERT_IPG = _SHR_PORT_PHY_CONTROL_BERT_IPG, 165 SOC_PHY_CONTROL_BERT_TX_PACKETS = _SHR_PORT_PHY_CONTROL_BERT_TX_PACKETS, 166 SOC_PHY_CONTROL_BERT_RX_PACKETS = _SHR_PORT_PHY_CONTROL_BERT_RX_PACKETS, 167 SOC_PHY_CONTROL_BERT_RX_ERROR_BITS = 168 _SHR_PORT_PHY_CONTROL_BERT_RX_ERROR_BITS, 169 SOC_PHY_CONTROL_BERT_RX_ERROR_BYTES = 170 _SHR_PORT_PHY_CONTROL_BERT_RX_ERROR_BYTES, 171 SOC_PHY_CONTROL_BERT_RX_ERROR_PACKETS = 172 _SHR_PORT_PHY_CONTROL_BERT_RX_ERROR_PACKETS, 173 SOC_PHY_CONTROL_PREEMPHASIS_LANE0 = _SHR_PORT_PHY_CONTROL_PREEMPHASIS_LANE0, 174 SOC_PHY_CONTROL_PREEMPHASIS_LANE1 = _SHR_PORT_PHY_CONTROL_PREEMPHASIS_LANE1, 175 SOC_PHY_CONTROL_PREEMPHASIS_LANE2 = _SHR_PORT_PHY_CONTROL_PREEMPHASIS_LANE2, 176 SOC_PHY_CONTROL_PREEMPHASIS_LANE3 = _SHR_PORT_PHY_CONTROL_PREEMPHASIS_LANE3, 177 SOC_PHY_CONTROL_DRIVER_CURRENT_LANE0 = _SHR_PORT_PHY_CONTROL_DRIVER_CURRENT_LANE0, 178 SOC_PHY_CONTROL_DRIVER_CURRENT_LANE1 = _SHR_PORT_PHY_CONTROL_DRIVER_CURRENT_LANE1, 179 SOC_PHY_CONTROL_DRIVER_CURRENT_LANE2 = _SHR_PORT_PHY_CONTROL_DRIVER_CURRENT_LANE2, 180 SOC_PHY_CONTROL_DRIVER_CURRENT_LANE3 = _SHR_PORT_PHY_CONTROL_DRIVER_CURRENT_LANE3, 181 SOC_PHY_CONTROL_PRE_DRIVER_CURRENT_LANE0 = 182 _SHR_PORT_PHY_CONTROL_PRE_DRIVER_CURRENT_LANE0, 183 SOC_PHY_CONTROL_PRE_DRIVER_CURRENT_LANE1 = 184 _SHR_PORT_PHY_CONTROL_PRE_DRIVER_CURRENT_LANE1, 185 SOC_PHY_CONTROL_PRE_DRIVER_CURRENT_LANE2 = 186 _SHR_PORT_PHY_CONTROL_PRE_DRIVER_CURRENT_LANE2, 187 SOC_PHY_CONTROL_PRE_DRIVER_CURRENT_LANE3 = 188 _SHR_PORT_PHY_CONTROL_PRE_DRIVER_CURRENT_LANE3, 189 SOC_PHY_CONTROL_TX_LANE_SQUELCH = 190 _SHR_PORT_PHY_CONTROL_TX_LANE_SQUELCH, 191 SOC_PHY_CONTROL_DRIVER_POST2_CURRENT = 192 _SHR_PORT_PHY_CONTROL_DRIVER_POST2_CURRENT, 193 SOC_PHY_CONTROL_RX_PPM = 194 _SHR_PORT_PHY_CONTROL_RX_PPM, 195 SOC_PHY_CONTROL_RX_PEAK_FILTER = 196 _SHR_PORT_PHY_CONTROL_RX_PEAK_FILTER, 197 SOC_PHY_CONTROL_RX_LOW_FREQ_PEAK_FILTER = 198 _SHR_PORT_PHY_CONTROL_RX_LOW_FREQ_PEAK_FILTER, 199 SOC_PHY_CONTROL_RX_VGA = 200 _SHR_PORT_PHY_CONTROL_RX_VGA, 201 SOC_PHY_CONTROL_RX_TAP1 = 202 _SHR_PORT_PHY_CONTROL_RX_TAP1, 203 SOC_PHY_CONTROL_RX_TAP2 = 204 _SHR_PORT_PHY_CONTROL_RX_TAP2, 205 SOC_PHY_CONTROL_RX_TAP3 = 206 _SHR_PORT_PHY_CONTROL_RX_TAP3, 207 SOC_PHY_CONTROL_RX_TAP4 = 208 _SHR_PORT_PHY_CONTROL_RX_TAP4, 209 SOC_PHY_CONTROL_RX_TAP5 = 210 _SHR_PORT_PHY_CONTROL_RX_TAP5, 211 SOC_PHY_CONTROL_RX_TAP6 = 212 _SHR_PORT_PHY_CONTROL_RX_TAP6, 213 SOC_PHY_CONTROL_RX_VGA_RELEASE = 214 _SHR_PORT_PHY_CONTROL_RX_VGA_RELEASE, 215 SOC_PHY_CONTROL_RX_TAP1_RELEASE = 216 _SHR_PORT_PHY_CONTROL_RX_TAP1_RELEASE, 217 SOC_PHY_CONTROL_RX_TAP2_RELEASE = 218 _SHR_PORT_PHY_CONTROL_RX_TAP2_RELEASE, 219 SOC_PHY_CONTROL_RX_TAP3_RELEASE = 220 _SHR_PORT_PHY_CONTROL_RX_TAP3_RELEASE, 221 SOC_PHY_CONTROL_RX_TAP4_RELEASE = 222 _SHR_PORT_PHY_CONTROL_RX_TAP4_RELEASE, 223 SOC_PHY_CONTROL_RX_TAP5_RELEASE = 224 _SHR_PORT_PHY_CONTROL_RX_TAP5_RELEASE, 225 SOC_PHY_CONTROL_RX_TAP6_RELEASE = 226 _SHR_PORT_PHY_CONTROL_RX_TAP6_RELEASE, 227 SOC_PHY_CONTROL_RX_PLUS1_SLICER = 228 _SHR_PORT_PHY_CONTROL_RX_PLUS1_SLICER, 229 SOC_PHY_CONTROL_RX_MINUS1_SLICER = 230 _SHR_PORT_PHY_CONTROL_RX_MINUS1_SLICER, 231 SOC_PHY_CONTROL_RX_D_SLICER = 232 _SHR_PORT_PHY_CONTROL_RX_D_SLICER, 233 SOC_PHY_CONTROL_RX_SIGNAL_DETECT = 234 _SHR_PORT_PHY_CONTROL_RX_SIGNAL_DETECT, 235 SOC_PHY_CONTROL_RX_SEQ_DONE = 236 _SHR_PORT_PHY_CONTROL_RX_SEQ_DONE, 237 SOC_PHY_CONTROL_RX_POLARITY = 238 _SHR_PORT_PHY_CONTROL_RX_POLARITY, 239 SOC_PHY_CONTROL_TX_POLARITY = 240 _SHR_PORT_PHY_CONTROL_TX_POLARITY, 241 SOC_PHY_CONTROL_RX_RESET = 242 _SHR_PORT_PHY_CONTROL_RX_RESET, 243 SOC_PHY_CONTROL_TX_RESET = 244 _SHR_PORT_PHY_CONTROL_TX_RESET, 245 SOC_PHY_CONTROL_CL72 = 246 _SHR_PORT_PHY_CONTROL_CL72, 247 SOC_PHY_CONTROL_CL72_STATUS = 248 _SHR_PORT_PHY_CONTROL_CL72_STATUS, 249 SOC_PHY_CONTROL_LANE_SWAP = 250 _SHR_PORT_PHY_CONTROL_LANE_SWAP, 251 SOC_PHY_CONTROL_DUMP = 252 _SHR_PORT_PHY_CONTROL_DUMP, 253 SOC_PHY_CONTROL_TX_PATTERN_20BIT = 254 _SHR_PORT_PHY_CONTROL_TX_PATTERN_20BIT, 255 SOC_PHY_CONTROL_TX_PATTERN_256BIT = 256 _SHR_PORT_PHY_CONTROL_TX_PATTERN_256BIT, 257 SOC_PHY_CONTROL_TX_PATTERN_DATA0 = 258 _SHR_PORT_PHY_CONTROL_TX_PATTERN_DATA0, 259 SOC_PHY_CONTROL_TX_PATTERN_DATA1 = 260 _SHR_PORT_PHY_CONTROL_TX_PATTERN_DATA1, 261 SOC_PHY_CONTROL_TX_PATTERN_DATA2 = 262 _SHR_PORT_PHY_CONTROL_TX_PATTERN_DATA2, 263 SOC_PHY_CONTROL_TX_PATTERN_DATA3 = 264 _SHR_PORT_PHY_CONTROL_TX_PATTERN_DATA3, 265 SOC_PHY_CONTROL_TX_PATTERN_DATA4 = 266 _SHR_PORT_PHY_CONTROL_TX_PATTERN_DATA4, 267 SOC_PHY_CONTROL_TX_PATTERN_DATA5 = 268 _SHR_PORT_PHY_CONTROL_TX_PATTERN_DATA5, 269 SOC_PHY_CONTROL_TX_PATTERN_DATA6 = 270 _SHR_PORT_PHY_CONTROL_TX_PATTERN_DATA6, 271 SOC_PHY_CONTROL_TX_PATTERN_DATA7 = 272 _SHR_PORT_PHY_CONTROL_TX_PATTERN_DATA7, 273 SOC_PHY_CONTROL_PHASE_INTERP = 274 _SHR_PORT_PHY_CONTROL_PHASE_INTERP, 275 SOC_PHY_CONTROL_PON_LASER_TX_POWER_TIME = 276 _SHR_PORT_PHY_CONTROL_PON_LASER_TX_POWER_TIME, 277 SOC_PHY_CONTROL_PON_LASER_TX_POWER_MODE = 278 _SHR_PORT_PHY_CONTROL_PON_LASER_TX_POWER_MODE, 279 SOC_PHY_CONTROL_PON_LASER_TX_STATUS = 280 _SHR_PORT_PHY_CONTROL_PON_LASER_TX_STATUS, 281 SOC_PHY_CONTROL_PON_LASER_RX_STATE = 282 _SHR_PORT_PHY_CONTROL_PON_LASER_RX_STATE, 283 SOC_PHY_CONTROL_PON_LASER_TRANCEIVER_TEMP = 284 _SHR_PORT_PHY_CONTROL_PON_LASER_TRANCEIVER_TEMP, 285 SOC_PHY_CONTROL_PON_LASER_SUPPLY_VOLTAGE = 286 _SHR_PORT_PHY_CONTROL_PON_LASER_SUPPLY_VOLTAGE, 287 SOC_PHY_CONTROL_PON_LASER_TX_BIAS = 288 _SHR_PORT_PHY_CONTROL_PON_LASER_TX_BIAS, 289 SOC_PHY_CONTROL_PON_LASER_TX_POWER = 290 _SHR_PORT_PHY_CONTROL_PON_LASER_TX_POWER, 291 SOC_PHY_CONTROL_PON_LASER_RX_POWER = 292 _SHR_PORT_PHY_CONTROL_PON_LASER_RX_POWER, 293 SOC_PHY_CONTROL_PON_RX_POWER_HIGH_ALARM_STATE = 294 _SHR_PORT_PHY_CONTROL_PON_RX_POWER_HIGH_ALARM_STATE, 295 SOC_PHY_CONTROL_PON_RX_POWER_HIGH_ALARM_REPORT_THRESHOLD = 296 _SHR_PORT_PHY_CONTROL_PON_RX_POWER_HIGH_ALARM_REPORT_THRESHOLD, 297 SOC_PHY_CONTROL_PON_RX_POWER_HIGH_ALARM_CLEAR_THRESHOLD = 298 _SHR_PORT_PHY_CONTROL_PON_RX_POWER_HIGH_ALARM_CLEAR_THRESHOLD, 299 SOC_PHY_CONTROL_PON_RX_POWER_LOW_ALARM_STATE = 300 _SHR_PORT_PHY_CONTROL_PON_RX_POWER_LOW_ALARM_STATE, 301 SOC_PHY_CONTROL_PON_RX_POWER_LOW_ALARM_REPORT_THRESHOLD = 302 _SHR_PORT_PHY_CONTROL_PON_RX_POWER_LOW_ALARM_REPORT_THRESHOLD, 303 SOC_PHY_CONTROL_PON_RX_POWER_LOW_ALARM_CLEAR_THRESHOLD = 304 _SHR_PORT_PHY_CONTROL_PON_RX_POWER_LOW_ALARM_CLEAR_THRESHOLD, 305 SOC_PHY_CONTROL_PON_TX_POWER_HIGH_ALARM_STATE = 306 _SHR_PORT_PHY_CONTROL_PON_TX_POWER_HIGH_ALARM_STATE, 307 SOC_PHY_CONTROL_PON_TX_POWER_HIGH_ALARM_REPORT_THRESHOLD = 308 _SHR_PORT_PHY_CONTROL_PON_TX_POWER_HIGH_ALARM_REPORT_THRESHOLD, 309 SOC_PHY_CONTROL_PON_TX_POWER_HIGH_ALARM_CLEAR_THRESHOLD = 310 _SHR_PORT_PHY_CONTROL_PON_TX_POWER_HIGH_ALARM_CLEAR_THRESHOLD, 311 SOC_PHY_CONTROL_PON_TX_POWER_LOW_ALARM_STATE = 312 _SHR_PORT_PHY_CONTROL_PON_TX_POWER_LOW_ALARM_STATE, 313 SOC_PHY_CONTROL_PON_TX_POWER_LOW_ALARM_REPORT_THRESHOLD = 314 _SHR_PORT_PHY_CONTROL_PON_TX_POWER_LOW_ALARM_REPORT_THRESHOLD, 315 SOC_PHY_CONTROL_PON_TX_POWER_LOW_ALARM_CLEAR_THRESHOLD = 316 _SHR_PORT_PHY_CONTROL_PON_TX_POWER_LOW_ALARM_CLEAR_THRESHOLD, 317 SOC_PHY_CONTROL_PON_TX_BIAS_HIGH_ALARM_STATE = 318 _SHR_PORT_PHY_CONTROL_PON_TX_BIAS_HIGH_ALARM_STATE, 319 SOC_PHY_CONTROL_PON_TX_BIAS_HIGH_ALARM_REPORT_THRESHOLD = 320 _SHR_PORT_PHY_CONTROL_PON_TX_BIAS_HIGH_ALARM_REPORT_THRESHOLD, 321 SOC_PHY_CONTROL_PON_TX_BIAS_HIGH_ALARM_CLEAR_THRESHOLD = 322 _SHR_PORT_PHY_CONTROL_PON_TX_BIAS_HIGH_ALARM_CLEAR_THRESHOLD, 323 SOC_PHY_CONTROL_PON_TX_BIAS_LOW_ALARM_STATE = 324 _SHR_PORT_PHY_CONTROL_PON_TX_BIAS_LOW_ALARM_STATE, 325 SOC_PHY_CONTROL_PON_TX_BIAS_LOW_ALARM_REPORT_THRESHOLD = 326 _SHR_PORT_PHY_CONTROL_PON_TX_BIAS_LOW_ALARM_REPORT_THRESHOLD, 327 SOC_PHY_CONTROL_PON_TX_BIAS_LOW_ALARM_CLEAR_THRESHOLD = 328 _SHR_PORT_PHY_CONTROL_PON_TX_BIAS_LOW_ALARM_CLEAR_THRESHOLD, 329 SOC_PHY_CONTROL_PON_VCC_HIGH_ALARM_STATE = 330 _SHR_PORT_PHY_CONTROL_PON_VCC_HIGH_ALARM_STATE, 331 SOC_PHY_CONTROL_PON_VCC_HIGH_ALARM_REPORT_THRESHOLD = 332 _SHR_PORT_PHY_CONTROL_PON_VCC_HIGH_ALARM_REPORT_THRESHOLD, 333 SOC_PHY_CONTROL_PON_VCC_HIGH_ALARM_CLEAR_THRESHOLD = 334 _SHR_PORT_PHY_CONTROL_PON_VCC_HIGH_ALARM_CLEAR_THRESHOLD, 335 SOC_PHY_CONTROL_PON_VCC_LOW_ALARM_STATE = 336 _SHR_PORT_PHY_CONTROL_PON_VCC_LOW_ALARM_STATE, 337 SOC_PHY_CONTROL_PON_VCC_LOW_ALARM_REPORT_THRESHOLD = 338 _SHR_PORT_PHY_CONTROL_PON_VCC_LOW_ALARM_REPORT_THRESHOLD, 339 SOC_PHY_CONTROL_PON_VCC_LOW_ALARM_CLEAR_THRESHOLD = 340 _SHR_PORT_PHY_CONTROL_PON_VCC_LOW_ALARM_CLEAR_THRESHOLD, 341 SOC_PHY_CONTROL_PON_TEMP_HIGH_ALARM_STATE = 342 _SHR_PORT_PHY_CONTROL_PON_TEMP_HIGH_ALARM_STATE, 343 SOC_PHY_CONTROL_PON_TEMP_HIGH_ALARM_REPORT_THRESHOLD = 344 _SHR_PORT_PHY_CONTROL_PON_TEMP_HIGH_ALARM_REPORT_THRESHOLD, 345 SOC_PHY_CONTROL_PON_TEMP_HIGH_ALARM_CLEAR_THRESHOLD = 346 _SHR_PORT_PHY_CONTROL_PON_TEMP_HIGH_ALARM_CLEAR_THRESHOLD, 347 SOC_PHY_CONTROL_PON_TEMP_LOW_ALARM_STATE = 348 _SHR_PORT_PHY_CONTROL_PON_TEMP_LOW_ALARM_STATE, 349 SOC_PHY_CONTROL_PON_TEMP_LOW_ALARM_REPORT_THRESHOLD = 350 _SHR_PORT_PHY_CONTROL_PON_TEMP_LOW_ALARM_REPORT_THRESHOLD, 351 SOC_PHY_CONTROL_PON_TEMP_LOW_ALARM_CLEAR_THRESHOLD = 352 _SHR_PORT_PHY_CONTROL_PON_TEMP_LOW_ALARM_CLEAR_THRESHOLD, 353 SOC_PHY_CONTROL_PON_RX_POWER_HIGH_WARNING_STATE = 354 _SHR_PORT_PHY_CONTROL_PON_RX_POWER_HIGH_WARNING_STATE, 355 SOC_PHY_CONTROL_PON_RX_POWER_HIGH_WARNING_REPORT_THRESHOLD = 356 _SHR_PORT_PHY_CONTROL_PON_RX_POWER_HIGH_WARNING_REPORT_THRESHOLD, 357 SOC_PHY_CONTROL_PON_RX_POWER_HIGH_WARNING_CLEAR_THRESHOLD = 358 _SHR_PORT_PHY_CONTROL_PON_RX_POWER_HIGH_WARNING_CLEAR_THRESHOLD, 359 SOC_PHY_CONTROL_PON_RX_POWER_LOW_WARNING_STATE = 360 _SHR_PORT_PHY_CONTROL_PON_RX_POWER_LOW_WARNING_STATE, 361 SOC_PHY_CONTROL_PON_RX_POWER_LOW_WARNING_REPORT_THRESHOLD = 362 _SHR_PORT_PHY_CONTROL_PON_RX_POWER_LOW_WARNING_REPORT_THRESHOLD, 363 SOC_PHY_CONTROL_PON_RX_POWER_LOW_WARNING_CLEAR_THRESHOLD = 364 _SHR_PORT_PHY_CONTROL_PON_RX_POWER_LOW_WARNING_CLEAR_THRESHOLD, 365 SOC_PHY_CONTROL_PON_TX_POWER_HIGH_WARNING_STATE = 366 _SHR_PORT_PHY_CONTROL_PON_TX_POWER_HIGH_WARNING_STATE, 367 SOC_PHY_CONTROL_PON_TX_POWER_HIGH_WARNING_REPORT_THRESHOLD = 368 _SHR_PORT_PHY_CONTROL_PON_TX_POWER_HIGH_WARNING_REPORT_THRESHOLD, 369 SOC_PHY_CONTROL_PON_TX_POWER_HIGH_WARNING_CLEAR_THRESHOLD = 370 _SHR_PORT_PHY_CONTROL_PON_TX_POWER_HIGH_WARNING_CLEAR_THRESHOLD, 371 SOC_PHY_CONTROL_PON_TX_POWER_LOW_WARNING_STATE = 372 _SHR_PORT_PHY_CONTROL_PON_TX_POWER_LOW_WARNING_STATE, 373 SOC_PHY_CONTROL_PON_TX_POWER_LOW_WARNING_REPORT_THRESHOLD = 374 _SHR_PORT_PHY_CONTROL_PON_TX_POWER_LOW_WARNING_REPORT_THRESHOLD, 375 SOC_PHY_CONTROL_PON_TX_POWER_LOW_WARNING_CLEAR_THRESHOLD = 376 _SHR_PORT_PHY_CONTROL_PON_TX_POWER_LOW_WARNING_CLEAR_THRESHOLD, 377 SOC_PHY_CONTROL_PON_TX_BIAS_HIGH_WARNING_STATE = 378 _SHR_PORT_PHY_CONTROL_PON_TX_BIAS_HIGH_WARNING_STATE, 379 SOC_PHY_CONTROL_PON_TX_BIAS_HIGH_WARNING_REPORT_THRESHOLD = 380 _SHR_PORT_PHY_CONTROL_PON_TX_BIAS_HIGH_WARNING_REPORT_THRESHOLD, 381 SOC_PHY_CONTROL_PON_TX_BIAS_HIGH_WARNING_CLEAR_THRESHOLD = 382 _SHR_PORT_PHY_CONTROL_PON_TX_BIAS_HIGH_WARNING_CLEAR_THRESHOLD, 383 SOC_PHY_CONTROL_PON_TX_BIAS_LOW_WARNING_STATE = 384 _SHR_PORT_PHY_CONTROL_PON_TX_BIAS_LOW_WARNING_STATE, 385 SOC_PHY_CONTROL_PON_TX_BIAS_LOW_WARNING_REPORT_THRESHOLD = 386 _SHR_PORT_PHY_CONTROL_PON_TX_BIAS_LOW_WARNING_REPORT_THRESHOLD, 387 SOC_PHY_CONTROL_PON_TX_BIAS_LOW_WARNING_CLEAR_THRESHOLD = 388 _SHR_PORT_PHY_CONTROL_PON_TX_BIAS_LOW_WARNING_CLEAR_THRESHOLD, 389 SOC_PHY_CONTROL_PON_VCC_HIGH_WARNING_STATE = 390 _SHR_PORT_PHY_CONTROL_PON_VCC_HIGH_WARNING_STATE, 391 SOC_PHY_CONTROL_PON_VCC_HIGH_WARNING_REPORT_THRESHOLD = 392 _SHR_PORT_PHY_CONTROL_PON_VCC_HIGH_WARNING_REPORT_THRESHOLD, 393 SOC_PHY_CONTROL_PON_VCC_HIGH_WARNING_CLEAR_THRESHOLD = 394 _SHR_PORT_PHY_CONTROL_PON_VCC_HIGH_WARNING_CLEAR_THRESHOLD, 395 SOC_PHY_CONTROL_PON_VCC_LOW_WARNING_STATE = 396 _SHR_PORT_PHY_CONTROL_PON_VCC_LOW_WARNING_STATE, 397 SOC_PHY_CONTROL_PON_VCC_LOW_WARNING_REPORT_THRESHOLD = 398 _SHR_PORT_PHY_CONTROL_PON_VCC_LOW_WARNING_REPORT_THRESHOLD, 399 SOC_PHY_CONTROL_PON_VCC_LOW_WARNING_CLEAR_THRESHOLD = 400 _SHR_PORT_PHY_CONTROL_PON_VCC_LOW_WARNING_CLEAR_THRESHOLD, 401 SOC_PHY_CONTROL_PON_TEMP_HIGH_WARNING_STATE = 402 _SHR_PORT_PHY_CONTROL_PON_TEMP_HIGH_WARNING_STATE, 403 SOC_PHY_CONTROL_PON_TEMP_HIGH_WARNING_REPORT_THRESHOLD = 404 _SHR_PORT_PHY_CONTROL_PON_TEMP_HIGH_WARNING_REPORT_THRESHOLD, 405 SOC_PHY_CONTROL_PON_TEMP_HIGH_WARNING_CLEAR_THRESHOLD = 406 _SHR_PORT_PHY_CONTROL_PON_TEMP_HIGH_WARNING_CLEAR_THRESHOLD, 407 SOC_PHY_CONTROL_PON_TEMP_LOW_WARNING_STATE = 408 _SHR_PORT_PHY_CONTROL_PON_TEMP_LOW_WARNING_STATE, 409 SOC_PHY_CONTROL_PON_TEMP_LOW_WARNING_REPORT_THRESHOLD = 410 _SHR_PORT_PHY_CONTROL_PON_TEMP_LOW_WARNING_REPORT_THRESHOLD, 411 SOC_PHY_CONTROL_PON_TEMP_LOW_WARNING_CLEAR_THRESHOLD = 412 _SHR_PORT_PHY_CONTROL_PON_TEMP_LOW_WARNING_CLEAR_THRESHOLD, 413 SOC_PHY_CONTROL_DLL_POWER_AUTO = _SHR_PORT_PHY_CONTROL_DLL_POWER_AUTO, 414 SOC_PHY_CONTROL_TX_PPM_ADJUST = _SHR_PORT_PHY_CONTROL_TX_PPM_ADJUST, 415 SOC_PHY_CONTROL_FIRMWARE_MODE = 416 _SHR_PORT_PHY_CONTROL_FIRMWARE_MODE, 417 SOC_PHY_CONTROL_DFE = _SHR_PORT_PHY_CONTROL_DFE, 418 SOC_PHY_CONTROL_VCO_FREQ = _SHR_PORT_PHY_CONTROL_VCO_FREQ , 419 SOC_PHY_CONTROL_VCO_DISTURBED = _SHR_PORT_PHY_CONTROL_VCO_DISTURBED , 420 SOC_PHY_CONTROL_PLL_DIVIDER = _SHR_PORT_PHY_CONTROL_PLL_DIVIDER , 421 SOC_PHY_CONTROL_OVERSAMPLE_MODE = _SHR_PORT_PHY_CONTROL_OVERSAMPLE_MODE, 422 SOC_PHY_CONTROL_REF_CLK = _SHR_PORT_PHY_CONTROL_REF_CLK, 423 SOC_PHY_CONTROL_SOFTWARE_RX_LOS = _SHR_PORT_PHY_CONTROL_SOFTWARE_RX_LOS, 424 SOC_PHY_CONTROL_PRBS_DECOUPLED_TX_ENABLE = 425 _SHR_PORT_PHY_CONTROL_PRBS_DECOUPLED_TX_ENABLE, 426 SOC_PHY_CONTROL_PRBS_DECOUPLED_TX_INVERT_DATA = 427 _SHR_PORT_PHY_CONTROL_PRBS_DECOUPLED_TX_INVERT_DATA, 428 SOC_PHY_CONTROL_PRBS_DECOUPLED_TX_POLYNOMIAL = 429 _SHR_PORT_PHY_CONTROL_PRBS_DECOUPLED_TX_POLYNOMIAL, 430 SOC_PHY_CONTROL_PRBS_DECOUPLED_RX_ENABLE = 431 _SHR_PORT_PHY_CONTROL_PRBS_DECOUPLED_RX_ENABLE, 432 SOC_PHY_CONTROL_PRBS_DECOUPLED_RX_INVERT_DATA = 433 _SHR_PORT_PHY_CONTROL_PRBS_DECOUPLED_RX_INVERT_DATA, 434 SOC_PHY_CONTROL_PRBS_DECOUPLED_RX_POLYNOMIAL = 435 _SHR_PORT_PHY_CONTROL_PRBS_DECOUPLED_RX_POLYNOMIAL, 436 SOC_PHY_CONTROL_RX_PEAK_FILTER_TEMP_COMP = _SHR_PORT_PHY_CONTROL_RX_PEAK_FILTER_TEMP_COMP, 437 SOC_PHY_CONTROL_CL73_FSM_AUTO_RECOVER = _SHR_PORT_PHY_CONTROL_CL73_FSM_AUTO_RECOVER, 438 SOC_PHY_CONTROL_RX_SEQ_TOGGLE = _SHR_PORT_PHY_CONTROL_RX_SEQ_TOGGLE, 439 SOC_PHY_CONTROL_DRIVER_SUPPLY = _SHR_PORT_PHY_CONTROL_DRIVER_SUPPLY, 440 SOC_PHY_CONTROL_AUTONEG_MODE = _SHR_PORT_PHY_CONTROL_AUTONEG_MODE, 441 SOC_PHY_CONTROL_HG2_BCM_CODEC_ENABLE = _SHR_PORT_PHY_CONTROL_HG2_BCM_CODEC_ENABLE, 442 SOC_PHY_CONTROL_PRBS_RX_INVERT_DATA = _SHR_PORT_PHY_CONTROL_PRBS_RX_INVERT_DATA , 443 SOC_PHY_CONTROL_PRBS_CHECK_MODE = _SHR_PORT_PHY_CONTROL_PRBS_CHECK_MODE, 444 SOC_PHY_CONTROL_MOD_AUTO_DETECT_ENABLE = _SHR_PORT_PHY_CONTROL_MOD_AUTO_DETECT_ENABLE, 445 SOC_PHY_CONTROL_DIGITAL_TEMP = _SHR_PORT_PHY_CONTROL_DIGITAL_TEMP, 446 SOC_PHY_CONTROL_ANALOG_TEMP = _SHR_PORT_PHY_CONTROL_ANALOG_TEMP, 447 SOC_PHY_CONTROL_TX_FIR_PRE = _SHR_PORT_PHY_CONTROL_TX_FIR_PRE, 448 SOC_PHY_CONTROL_TX_FIR_MAIN = _SHR_PORT_PHY_CONTROL_TX_FIR_MAIN, 449 SOC_PHY_CONTROL_TX_FIR_POST = _SHR_PORT_PHY_CONTROL_TX_FIR_POST, 450 SOC_PHY_CONTROL_TX_FIR_POST2 = _SHR_PORT_PHY_CONTROL_TX_FIR_POST2, 451 SOC_PHY_CONTROL_TX_FIR_POST3 = _SHR_PORT_PHY_CONTROL_TX_FIR_POST3, 452 SOC_PHY_CONTROL_PCS_SPEED_HTO_PMA_OS = _SHR_PORT_PHY_CONTROL_PCS_SPEED_HTO_PMA_OS, 453 SOC_PHY_CONTROL_PCS_SPEED_HTO_SCR_MODE = _SHR_PORT_PHY_CONTROL_PCS_SPEED_HTO_SCR_MODE, 454 SOC_PHY_CONTROL_PCS_SPEED_HTO_ENCODE_MODE = _SHR_PORT_PHY_CONTROL_PCS_SPEED_HTO_ENCODE_MODE, 455 SOC_PHY_CONTROL_PCS_SPEED_HTO_CL48_CHECK_END = _SHR_PORT_PHY_CONTROL_PCS_SPEED_HTO_CL48_CHECK_END, 456 SOC_PHY_CONTROL_PCS_SPEED_HTO_BLK_SYNC_MODE = _SHR_PORT_PHY_CONTROL_PCS_SPEED_HTO_BLK_SYNC_MODE, 457 SOC_PHY_CONTROL_PCS_SPEED_HTO_REORDER_MODE = _SHR_PORT_PHY_CONTROL_PCS_SPEED_HTO_REORDER_MODE, 458 SOC_PHY_CONTROL_PCS_SPEED_HTO_CL36_EN = _SHR_PORT_PHY_CONTROL_PCS_SPEED_HTO_CL36_EN, 459 SOC_PHY_CONTROL_PCS_SPEED_HTO_DESCR1_MODE = _SHR_PORT_PHY_CONTROL_PCS_SPEED_HTO_DESCR1_MODE, 460 SOC_PHY_CONTROL_PCS_SPEED_HTO_DEC1_MODE = _SHR_PORT_PHY_CONTROL_PCS_SPEED_HTO_DEC1_MODE, 461 SOC_PHY_CONTROL_PCS_SPEED_HTO_DESKEW_MODE = _SHR_PORT_PHY_CONTROL_PCS_SPEED_HTO_DESKEW_MODE, 462 SOC_PHY_CONTROL_PCS_SPEED_HTO_DESC2_MODE = _SHR_PORT_PHY_CONTROL_PCS_SPEED_HTO_DESC2_MODE, 463 SOC_PHY_CONTROL_PCS_SPEED_HTO_DESC2_BYTE_DEL = _SHR_PORT_PHY_CONTROL_PCS_SPEED_HTO_DESC2_BYTE_DEL, 464 SOC_PHY_CONTROL_PCS_SPEED_HTO_BRCM64B66_DESCR = _SHR_PORT_PHY_CONTROL_PCS_SPEED_HTO_BRCM64B66_DESCR, 465 SOC_PHY_CONTROL_PCS_SPEED_HTO_SGMII_MODE = _SHR_PORT_PHY_CONTROL_PCS_SPEED_HTO_SGMII_MODE, 466 SOC_PHY_CONTROL_PCS_SPEED_HTO_CLKCNT0 = _SHR_PORT_PHY_CONTROL_PCS_SPEED_HTO_CLKCNT0, 467 SOC_PHY_CONTROL_PCS_SPEED_HTO_CLKCNT1 = _SHR_PORT_PHY_CONTROL_PCS_SPEED_HTO_CLKCNT1, 468 SOC_PHY_CONTROL_PCS_SPEED_HTO_LPCNT0 = _SHR_PORT_PHY_CONTROL_PCS_SPEED_HTO_LPCNT0, 469 SOC_PHY_CONTROL_PCS_SPEED_HTO_LPCNT1 = _SHR_PORT_PHY_CONTROL_PCS_SPEED_HTO_LPCNT1, 470 SOC_PHY_CONTROL_PCS_SPEED_HTO_MAC_CGC = _SHR_PORT_PHY_CONTROL_PCS_SPEED_HTO_MAC_CGC, 471 SOC_PHY_CONTROL_PCS_SPEED_HTO_PCS_REPCNT = _SHR_PORT_PHY_CONTROL_PCS_SPEED_HTO_PCS_REPCNT, 472 SOC_PHY_CONTROL_PCS_SPEED_HTO_PCS_CREDTEN = _SHR_PORT_PHY_CONTROL_PCS_SPEED_HTO_PCS_CREDTEN, 473 SOC_PHY_CONTROL_PCS_SPEED_HTO_PCS_CLKCNT = _SHR_PORT_PHY_CONTROL_PCS_SPEED_HTO_PCS_CLKCNT, 474 SOC_PHY_CONTROL_PCS_SPEED_HTO_PCS_CGC = _SHR_PORT_PHY_CONTROL_PCS_SPEED_HTO_PCS_CGC, 475 SOC_PHY_CONTROL_PCS_SPEED_HTO_CL72_EN = _SHR_PORT_PHY_CONTROL_PCS_SPEED_HTO_CL72_EN, 476 SOC_PHY_CONTROL_PCS_SPEED_ST_ENTRY = _SHR_PORT_PHY_CONTROL_PCS_SPEED_ST_ENTRY, 477 SOC_PHY_CONTROL_PCS_SPEED_ST_HCD = _SHR_PORT_PHY_CONTROL_PCS_SPEED_ST_HCD, 478 SOC_PHY_CONTROL_PCS_SPEED_ST_PMA_OS = _SHR_PORT_PHY_CONTROL_PCS_SPEED_ST_PMA_OS, 479 SOC_PHY_CONTROL_PCS_SPEED_ST_SCR_MODE = _SHR_PORT_PHY_CONTROL_PCS_SPEED_ST_SCR_MODE, 480 SOC_PHY_CONTROL_PCS_SPEED_ST_ENCODE_MODE = _SHR_PORT_PHY_CONTROL_PCS_SPEED_ST_ENCODE_MODE, 481 SOC_PHY_CONTROL_PCS_SPEED_ST_CL48_CHECK_END = _SHR_PORT_PHY_CONTROL_PCS_SPEED_ST_CL48_CHECK_END, 482 SOC_PHY_CONTROL_PCS_SPEED_ST_BLK_SYNC_MODE = _SHR_PORT_PHY_CONTROL_PCS_SPEED_ST_BLK_SYNC_MODE, 483 SOC_PHY_CONTROL_PCS_SPEED_ST_REORDER_MODE = _SHR_PORT_PHY_CONTROL_PCS_SPEED_ST_REORDER_MODE, 484 SOC_PHY_CONTROL_PCS_SPEED_ST_CL36_EN = _SHR_PORT_PHY_CONTROL_PCS_SPEED_ST_CL36_EN, 485 SOC_PHY_CONTROL_PCS_SPEED_ST_DESCR1_MODE = _SHR_PORT_PHY_CONTROL_PCS_SPEED_ST_DESCR1_MODE, 486 SOC_PHY_CONTROL_PCS_SPEED_ST_DEC1_MODE = _SHR_PORT_PHY_CONTROL_PCS_SPEED_ST_DEC1_MODE, 487 SOC_PHY_CONTROL_PCS_SPEED_ST_DESKEW_MODE = _SHR_PORT_PHY_CONTROL_PCS_SPEED_ST_DESKEW_MODE, 488 SOC_PHY_CONTROL_PCS_SPEED_ST_DESC2_MODE = _SHR_PORT_PHY_CONTROL_PCS_SPEED_ST_DESC2_MODE, 489 SOC_PHY_CONTROL_PCS_SPEED_ST_DESC2_BYTE_DEL = _SHR_PORT_PHY_CONTROL_PCS_SPEED_ST_DESC2_BYTE_DEL, 490 SOC_PHY_CONTROL_PCS_SPEED_ST_BRCM64B66_DESCR = _SHR_PORT_PHY_CONTROL_PCS_SPEED_ST_BRCM64B66_DESCR, 491 SOC_PHY_CONTROL_PCS_SPEED_ST_SGMII_MODE = _SHR_PORT_PHY_CONTROL_PCS_SPEED_ST_SGMII_MODE, 492 SOC_PHY_CONTROL_PCS_SPEED_ST_CLKCNT0 = _SHR_PORT_PHY_CONTROL_PCS_SPEED_ST_CLKCNT0, 493 SOC_PHY_CONTROL_PCS_SPEED_ST_CLKCNT1 = _SHR_PORT_PHY_CONTROL_PCS_SPEED_ST_CLKCNT1, 494 SOC_PHY_CONTROL_PCS_SPEED_ST_LPCNT0 = _SHR_PORT_PHY_CONTROL_PCS_SPEED_ST_LPCNT0, 495 SOC_PHY_CONTROL_PCS_SPEED_ST_LPCNT1 = _SHR_PORT_PHY_CONTROL_PCS_SPEED_ST_LPCNT1, 496 SOC_PHY_CONTROL_PCS_SPEED_ST_MAC_CGC = _SHR_PORT_PHY_CONTROL_PCS_SPEED_ST_MAC_CGC, 497 SOC_PHY_CONTROL_PCS_SPEED_ST_PCS_REPCNT = _SHR_PORT_PHY_CONTROL_PCS_SPEED_ST_PCS_REPCNT, 498 SOC_PHY_CONTROL_PCS_SPEED_ST_PCS_CREDTEN = _SHR_PORT_PHY_CONTROL_PCS_SPEED_ST_PCS_CREDTEN, 499 SOC_PHY_CONTROL_PCS_SPEED_ST_PCS_CLKCNT = _SHR_PORT_PHY_CONTROL_PCS_SPEED_ST_PCS_CLKCNT, 500 SOC_PHY_CONTROL_PCS_SPEED_ST_PCS_CGC = _SHR_PORT_PHY_CONTROL_PCS_SPEED_ST_PCS_CGC, 501 SOC_PHY_CONTROL_PCS_SPEED_ST_CL72_EN = _SHR_PORT_PHY_CONTROL_PCS_SPEED_ST_CL72_EN, 502 SOC_PHY_CONTROL_LOOPBACK_PMD = _SHR_PORT_PHY_CONTROL_LOOPBACK_PMD, 503 SOC_PHY_CONTROL_TX_PATTERN_GEN_ENABLE = _SHR_PORT_PHY_CONTROL_TX_PATTERN_GEN_ENABLE, 504 SOC_PHY_CONTROL_TX_PATTERN_LENGTH = _SHR_PORT_PHY_CONTROL_TX_PATTERN_LENGTH, 505 SOC_PHY_CONTROL_PCS_SPEED_HTO_PLL_DIVIDER = _SHR_PORT_PHY_CONTROL_PCS_SPEED_HTO_PLL_DIVIDER, 506 SOC_PHY_CONTROL_PCS_SPEED_HTO_CLEAR = _SHR_PORT_PHY_CONTROL_PCS_SPEED_HTO_CLEAR, 507 SOC_PHY_CONTROL_PCS_SPEED_ST_PLL_DIVIDER = _SHR_PORT_PHY_CONTROL_PCS_SPEED_ST_PLL_DIVIDER, 508 SOC_PHY_CONTROL_PCS_SPEED_ST_NUM_OF_LANES = _SHR_PORT_PHY_CONTROL_PCS_SPEED_ST_NUM_OF_LANES, 509 SOC_PHY_CONTROL_INTR_MASK = _SHR_PORT_PHY_CONTROL_INTR_MASK, 510 SOC_PHY_CONTROL_INTR_STATUS = _SHR_PORT_PHY_CONTROL_INTR_STATUS, 511 SOC_PHY_CONTROL_XSW_LANE_MAP = _SHR_PORT_PHY_CONTROL_XSW_LANE_MAP, 512 SOC_PHY_CONTROL_FIRMWARE_DFE_ENABLE = _SHR_PORT_PHY_CONTROL_FIRMWARE_DFE_ENABLE, 513 SOC_PHY_CONTROL_FIRMWARE_LP_DFE_ENABLE = _SHR_PORT_PHY_CONTROL_FIRMWARE_LP_DFE_ENABLE, 514 SOC_PHY_CONTROL_FIRMWARE_BR_DFE_ENABLE = _SHR_PORT_PHY_CONTROL_FIRMWARE_BR_DFE_ENABLE, 515 SOC_PHY_CONTROL_GPIO_CONFIG = _SHR_PORT_PHY_CONTROL_GPIO_CONFIG, 516 SOC_PHY_CONTROL_GPIO_VALUE = _SHR_PORT_PHY_CONTROL_GPIO_VALUE, 517 SOC_PHY_CONTROL_PCS_MODE = _SHR_PORT_PHY_CONTROL_PCS_MODE, 518 SOC_PHY_CONTROL_SUPER_ISOLATE = _SHR_PORT_PHY_CONTROL_SUPER_ISOLATE, 519 SOC_PHY_CONTROL_SOFT_RESET = _SHR_PORT_PHY_CONTROL_SOFT_RESET, 520 SOC_PHY_CONTROL_AUTONEG_ALLOW_PLL_CHANGE = _SHR_PORT_PHY_CONTROL_AUTONEG_ALLOW_PLL_CHANGE, 521 SOC_PHY_CONTROL_FAIL_OVER_MODE = _SHR_PORT_PHY_CONTROL_FAIL_OVER_MODE, 522 SOC_PHY_CONTROL_SHORT_CHANNEL_MODE = _SHR_PORT_PHY_SHORT_CHANNEL_MODE, 523 SOC_PHY_CONTROL_EYE_VAL_HZ_L = _SHR_PORT_PHY_CONTROL_EYE_VAL_HZ_L, 524 SOC_PHY_CONTROL_EYE_VAL_HZ_R = _SHR_PORT_PHY_CONTROL_EYE_VAL_HZ_R, 525 SOC_PHY_CONTROL_EYE_VAL_VT_U = _SHR_PORT_PHY_CONTROL_EYE_VAL_VT_U, 526 SOC_PHY_CONTROL_EYE_VAL_VT_D = _SHR_PORT_PHY_CONTROL_EYE_VAL_VT_D, 527 SOC_PHY_CONTROL_MEDIUM_TYPE = _SHR_PORT_PHY_CONTROL_MEDIUM_TYPE, 528 SOC_PHY_CONTROL_FORCED_SPEED_LINE_SIDE = _SHR_PORT_PHY_CONTROL_FORCED_SPEED_LINE_SIDE, 529 SOC_PHY_CONTROL_FORWARD_ERROR_CORRECTION_CL91 = _SHR_PORT_PHY_CONTROL_FORWARD_ERROR_CORRECTION_CL91, 530 SOC_PHY_CONTROL_SHORT_CHANNEL_MODE_STATUS = _SHR_PORT_PHY_CONTROL_SHORT_CHANNEL_MODE_STATUS, 531 SOC_PHY_CONTROL_EGRESS_FLOW_CONTROL_MODE = _SHR_PORT_PHY_EGRESS_FLOW_CONTROL_MODE, 532 SOC_PHY_CONTROL_INGRESS_FLOW_CONTROL_MODE = _SHR_PORT_PHY_INGRESS_FLOW_CONTROL_MODE, 533 SOC_PHY_CONTROL_UNRELIABLE_LOS = _SHR_PORT_PHY_CONTROL_UNRELIABLE_LOS, 534 SOC_PHY_CONTROL_PSM_COS_BMP = _SHR_PORT_PHY_CONTROL_PSM_COS_BMP, 535 SOC_PHY_CONTROL_RX_LANE_SQUELCH = 536 _SHR_PORT_PHY_CONTROL_RX_LANE_SQUELCH, 537 SOC_PHY_CONTROL_FIRMWARE_CL72_RESTART_TIMEOUT_ENABLE = 538 _SHR_PORT_PHY_CONTROL_FIRMWARE_CL72_RESTART_TIMEOUT_ENABLE, 539 SOC_PHY_CONTROL_FIRMWARE_CL72_AUTO_POLARITY_ENABLE = 540 _SHR_PORT_PHY_CONTROL_FIRMWARE_CL72_AUTO_POLARITY_ENABLE, 541 SOC_PHY_CONTROL_SOFTWARE_RX_LOS_LINK_WAIT_TIMER_US = 542 _SHR_PORT_PHY_CONTROL_SOFTWARE_RX_LOS_LINK_WAIT_TIMER_US, 543 SOC_PHY_CONTROL_SOFTWARE_RX_LOS_RESTART_TIMER_US = 544 _SHR_PORT_PHY_CONTROL_SOFTWARE_RX_LOS_RESTART_TIMER_US, 545 SOC_PHY_CONTROL_MGBASET_802P3BZ_PRIORITY = _SHR_PORT_PHY_CONTROL_MGBASET_802P3BZ_PRIORITY, 546 SOC_PHY_CONTROL_TX_FIR_DRIVERMODE = _SHR_PORT_PHY_CONTROL_TX_FIR_DRIVERMODE, 547 SOC_PHY_CONTROL_AUTONEG_OUI = _SHR_PORT_PHY_CONTROL_AUTONEG_OUI, 548 SOC_PHY_CONTROL_AUTONEG_LINE_SIDE = _SHR_PORT_PHY_CONTROL_AUTONEG_LINE_SIDE, 549 SOC_PHY_CONTROL_PAM4_TX_PATTERN_ENABLE = _SHR_PORT_PHY_CONTROL_PAM4_TX_PATTERN_ENABLE, 550 SOC_PHY_CONTROL_FEC_SYMBOL_ERROR_COUNT = _SHR_PORT_PHY_CONTROL_FEC_SYMBOL_ERROR_COUNT, 551 SOC_PHY_CONTROL_TX_FIR_MODE = _SHR_PORT_PHY_CONTROL_TX_FIR_MODE, 552 SOC_PHY_CONTROL_TX_FIR_PRE2 = _SHR_PORT_PHY_CONTROL_TX_FIR_PRE2, 553 SOC_PHY_CONTROL_FEC_CORRECTED_BLOCK_COUNT = _SHR_PORT_PHY_CONTROL_FEC_CORRECTED_BLOCK_COUNT, 554 SOC_PHY_CONTROL_FEC_UNCORRECTED_BLOCK_COUNT = _SHR_PORT_PHY_CONTROL_FEC_UNCORRECTED_BLOCK_COUNT, 555 SOC_PHY_CONTROL_FEC_CORRECTED_CODEWORD_COUNT = _SHR_PORT_PHY_CONTROL_FEC_CORRECTED_CODEWORD_COUNT, 556 SOC_PHY_CONTROL_FEC_UNCORRECTED_CODEWORD_COUNT = _SHR_PORT_PHY_CONTROL_FEC_UNCORRECTED_CODEWORD_COUNT, 557 SOC_PHY_CONTROL_RX_ADAPTATION_RESUME = _SHR_PORT_PHY_CONTROL_RX_ADAPTATION_RESUME, 558 SOC_PHY_CONTROL_BOND_IN_PWRDN_OVERRIDE = _SHR_PORT_PHY_CONTROL_BOND_IN_PWRDN_OVERRIDE, 559 SOC_PHY_CONTROL_TX_PAM4_PRECODER_ENABLE = _SHR_PORT_PHY_CONTROL_TX_PAM4_PRECODER_ENABLE, 560 SOC_PHY_CONTROL_LP_TX_PRECODER_ENABLE = _SHR_PORT_PHY_CONTROL_LP_TX_PRECODER_ENABLE, 561 SOC_PHY_CONTROL_RX_HIGH_FREQ_PEAK_FILTER = _SHR_PORT_PHY_CONTROL_RX_HIGH_FREQ_PEAK_FILTER, 562 SOC_PHY_CONTROL_FIRMWARE_RX_FORCE_EXTENDED_REACH_ENABLE = _SHR_PORT_PHY_CONTROL_FIRMWARE_RX_FORCE_EXTENDED_REACH_ENABLE, 563 SOC_PHY_CONTROL_FIRMWARE_RX_FORCE_NORMAL_REACH_ENABLE = _SHR_PORT_PHY_CONTROL_FIRMWARE_RX_FORCE_NORMAL_REACH_ENABLE, 564 SOC_PHY_CONTROL_FAST_BER_PROJ = _SHR_PORT_PHY_CONTROL_FAST_BER_PROJ, 565 SOC_PHY_CONTROL_AUTONEG_FEC_OVERRIDE = _SHR_PORT_PHY_CONTROL_AUTONEG_FEC_OVERRIDE, 566 SOC_PHY_CONTROL_FORWARD_ERROR_CORRECTION_CL108 = _SHR_PORT_PHY_CONTROL_FORWARD_ERROR_CORRECTION_CL108, 567 SOC_PHY_CONTROL_CHANNEL_LOSS_HINT = _SHR_PORT_PHY_CONTROL_CHANNEL_LOSS_HINT, 568 SOC_PHY_CONTROL_LINK_TRAINING_INIT_TX_FIR_POST = _SHR_PORT_PHY_CONTROL_LINK_TRAINING_INIT_TX_FIR_POST, 569 SOC_PHY_CONTROL_MACSEC_ENABLE = _SHR_PORT_PHY_CONTROL_MACSEC_ENABLE, 570 SOC_PHY_CONTROL_FEC_BYPASS_INDICATION_ENABLE = _SHR_PORT_PHY_CONTROL_FEC_BYPASS_INDICATION_ENABLE, 571 SOC_PHY_CONTROL_PFC_USE_IP_COS = _SHR_PORT_PHY_CONTROL_PFC_USE_IP_COS, 572 SOC_PHY_CONTROL_COUNT = _SHR_PORT_PHY_CONTROL_NUM /* always last */ 573 } soc_phy_control_t; 574 575 /* 576 * SyncE recovered clock source 577 * status to indicate primary recovered clock has switched to secondary source 578 * when link failure 579 */ 580 typedef enum soc_port_phy_clock_source_e { 581 /* Recovery clock is being derived from primary port's recovered clock */ 582 SOC_PORT_PHY_CLOCK_SOURCE_PRIMARY = _SHR_PORT_PHY_CLOCK_SOURCE_PRIMARY, 583 /* Recovery clock is being derived from secondary port's recovered clock */ 584 SOC_PORT_PHY_CLOCK_SOURCE_SECONDARY = _SHR_PORT_PHY_CLOCK_SOURCE_SECONDARY 585 } soc_port_phy_clock_source_t; 586 587 typedef enum soc_phy_control_longreach_ability_e { 588 SOC_PHY_CONTROL_LONGREACH_ABILITY_NONE = 589 _SHR_PORT_PHY_CONTROL_LONGREACH_ABILITY_NONE, 590 SOC_PHY_CONTROL_LONGREACH_ABILITY_10M_1PAIR = 591 _SHR_PORT_PHY_CONTROL_LONGREACH_ABILITY_10M_1PAIR, 592 SOC_PHY_CONTROL_LONGREACH_ABILITY_10M_2PAIR = 593 _SHR_PORT_PHY_CONTROL_LONGREACH_ABILITY_10M_2PAIR, 594 SOC_PHY_CONTROL_LONGREACH_ABILITY_20M_1PAIR = 595 _SHR_PORT_PHY_CONTROL_LONGREACH_ABILITY_20M_1PAIR, 596 SOC_PHY_CONTROL_LONGREACH_ABILITY_20M_2PAIR = 597 _SHR_PORT_PHY_CONTROL_LONGREACH_ABILITY_20M_2PAIR, 598 SOC_PHY_CONTROL_LONGREACH_ABILITY_25M_1PAIR = 599 _SHR_PORT_PHY_CONTROL_LONGREACH_ABILITY_25M_1PAIR, 600 SOC_PHY_CONTROL_LONGREACH_ABILITY_25M_2PAIR = 601 _SHR_PORT_PHY_CONTROL_LONGREACH_ABILITY_25M_2PAIR, 602 SOC_PHY_CONTROL_LONGREACH_ABILITY_33M_1PAIR = 603 _SHR_PORT_PHY_CONTROL_LONGREACH_ABILITY_33M_1PAIR, 604 SOC_PHY_CONTROL_LONGREACH_ABILITY_33M_2PAIR = 605 _SHR_PORT_PHY_CONTROL_LONGREACH_ABILITY_33M_2PAIR, 606 SOC_PHY_CONTROL_LONGREACH_ABILITY_50M_1PAIR = 607 _SHR_PORT_PHY_CONTROL_LONGREACH_ABILITY_50M_1PAIR, 608 SOC_PHY_CONTROL_LONGREACH_ABILITY_50M_2PAIR = 609 _SHR_PORT_PHY_CONTROL_LONGREACH_ABILITY_50M_2PAIR, 610 SOC_PHY_CONTROL_LONGREACH_ABILITY_100M_1PAIR = 611 _SHR_PORT_PHY_CONTROL_LONGREACH_ABILITY_100M_1PAIR, 612 SOC_PHY_CONTROL_LONGREACH_ABILITY_100M_2PAIR = 613 _SHR_PORT_PHY_CONTROL_LONGREACH_ABILITY_100M_2PAIR, 614 SOC_PHY_CONTROL_LONGREACH_ABILITY_100M_4PAIR = 615 _SHR_PORT_PHY_CONTROL_LONGREACH_ABILITY_100M_4PAIR, 616 SOC_PHY_CONTROL_LONGREACH_ABILITY_PAUSE_RX = 617 _SHR_PORT_PHY_CONTROL_LONGREACH_ABILITY_PAUSE_RX, 618 SOC_PHY_CONTROL_LONGREACH_ABILITY_PAUSE_TX = 619 _SHR_PORT_PHY_CONTROL_LONGREACH_ABILITY_PAUSE_TX 620 } soc_phy_control_longreach_ability_t; 621 622 typedef enum soc_phy_control_power_e { 623 SOC_PHY_CONTROL_POWER_FULL = _SHR_PORT_PHY_CONTROL_POWER_FULL, 624 SOC_PHY_CONTROL_POWER_LOW = _SHR_PORT_PHY_CONTROL_POWER_LOW, 625 SOC_PHY_CONTROL_POWER_AUTO = _SHR_PORT_PHY_CONTROL_POWER_AUTO, 626 /* 627 Power mode added(SDK-30895). Requirement is to disable Auto Power Down 628 without changing Tx bias current 629 */ 630 SOC_PHY_CONTROL_POWER_AUTO_DISABLE= _SHR_PORT_PHY_CONTROL_POWER_AUTO_DISABLE, 631 SOC_PHY_CONTROL_POWER_AUTO_FULL= _SHR_PORT_PHY_CONTROL_POWER_AUTO_FULL, 632 SOC_PHY_CONTROL_POWER_AUTO_LOW= _SHR_PORT_PHY_CONTROL_POWER_AUTO_LOW 633 634 } soc_phy_control_power_t; 635 636 typedef enum soc_phy_control_edc_config_e { 637 SOC_PHY_CONTROL_EDC_CONFIG_NONE = _SHR_PORT_PHY_CONTROL_EDC_CONFIG_NONE, 638 SOC_PHY_CONTROL_EDC_CONFIG_HARDWARE = 639 _SHR_PORT_PHY_CONTROL_EDC_CONFIG_HARDWARE, 640 SOC_PHY_CONTROL_EDC_CONFIG_SOFTWARE = 641 _SHR_PORT_PHY_CONTROL_EDC_CONFIG_SOFTWARE 642 } soc_phy_control_edc_config_t; 643 644 typedef enum soc_phy_control_fec_e { 645 SOC_PHY_CONTROL_FEC_OFF = _SHR_PORT_PHY_CONTROL_FEC_OFF, 646 SOC_PHY_CONTROL_FEC_ON = _SHR_PORT_PHY_CONTROL_FEC_ON, 647 SOC_PHY_CONTROL_FEC_AUTO = _SHR_PORT_PHY_CONTROL_FEC_AUTO 648 } soc_phy_control_fec_t; 649 650 typedef enum soc_phy_control_bert_pattern_e { 651 SOC_PHY_CONTROL_BERT_CRPAT = _SHR_PORT_PHY_CONTROL_BERT_CRPAT, 652 SOC_PHY_CONTROL_BERT_CJPAT = _SHR_PORT_PHY_CONTROL_BERT_CJPAT 653 } soc_phy_control_bert_pattern_t; 654 655 656 typedef enum soc_phy_control_pam4_tx_pattern_e { 657 SOC_PHY_PAM4_TX_PATTERN_INVALID = _SHR_PORT_PHY_PAM4_TX_PATTERN_INVALID, 658 SOC_PHY_PAM4_TX_PATTERN_OFF = _SHR_PORT_PHY_PAM4_TX_PATTERN_OFF, 659 SOC_PHY_PAM4_TX_PATTERN_JP03B = _SHR_PORT_PHY_PAM4_TX_PATTERN_JP03B, 660 SOC_PHY_PAM4_TX_PATTERN_LINEAR = _SHR_PORT_PHY_PAM4_TX_PATTERN_LINEAR 661 } soc_phy_control_pam4_tx_pattern_t; 662 663 664 typedef enum soc_phy_control_driver_supply_e { 665 SOC_PHY_CONTROL_DRIVER_SUPPLY_1_5V_1_0V = _SHR_PORT_PHY_CONTROL_DRIVER_SUPPLY_1_5V_1_0V, 666 SOC_PHY_CONTROL_DRIVER_SUPPLY_1_0V_700MV = _SHR_PORT_PHY_CONTROL_DRIVER_SUPPLY_1_0V_700MV, 667 SOC_PHY_CONTROL_DRIVER_SUPPLY_1_5V_700MV = _SHR_PORT_PHY_CONTROL_DRIVER_SUPPLY_1_5V_700MV 668 } soc_port_phy_control_driver_supply_t; 669 670 typedef enum soc_phy_control_rx_los_e { 671 SOC_PHY_CONTROL_RX_LOS_NONE = _SHR_PORT_PHY_CONTROL_RX_LOS_NONE, 672 SOC_PHY_CONTROL_RX_LOS_SOFTWARE = _SHR_PORT_PHY_CONTROL_RX_LOS_SOFTWARE, 673 SOC_PHY_CONTROL_RX_LOS_FIRMWARE = _SHR_PORT_PHY_CONTROL_RX_LOS_FIRMWARE 674 } soc_phy_control_rx_los_t; 675 676 typedef enum soc_phy_control_gpio_config_e { 677 SOC_PHY_CONTROL_GPIO_CONFIG_DISABLED = _SHR_PORT_PHY_CONTROL_GPIO_CONFIG_DISABLED, 678 SOC_PHY_CONTROL_GPIO_CONFIG_OUTPUT = _SHR_PORT_PHY_CONTROL_GPIO_CONFIG_OUTPUT, 679 SOC_PHY_CONTROL_GPIO_CONFIG_INPUT = _SHR_PORT_PHY_CONTROL_GPIO_CONFIG_INPUT 680 } soc_phy_control_gpio_config_t; 681 682 683 typedef enum soc_phy_control_encoding_e { 684 phyControlEncoding8b10b, 685 phyControlEncoding64b66b 686 } soc_phy_control_encoding_t; 687 688 typedef enum soc_phy_control_firmware_mode_e { 689 SOC_PHY_FIRMWARE_DEFAULT = _SHR_PORT_PHY_FIRMWARE_DEFAULT, 690 SOC_PHY_FIRMWARE_SFP_OPT_SR4 = _SHR_PORT_PHY_FIRMWARE_SFP_OPT_SR4, 691 SOC_PHY_FIRMWARE_SFP_DAC = _SHR_PORT_PHY_FIRMWARE_SFP_DAC, 692 SOC_PHY_FIRMWARE_XLAUI = _SHR_PORT_PHY_FIRMWARE_XLAUI, 693 SOC_PHY_FIRMWARE_FORCE_OSDFE = _SHR_PORT_PHY_FIRMWARE_FORCE_OSDFE, 694 SOC_PHY_FIRMWARE_FORCE_BRDFE = _SHR_PORT_PHY_FIRMWARE_FORCE_BRDFE, 695 SOC_PHY_FIRMWARE_SW_CL72 = _SHR_PORT_PHY_FIRMWARE_SW_CL72, 696 SOC_PHY_FIRMWARE_CL72_WITHOUT_AN= _SHR_PORT_PHY_FIRMWARE_CL72_WITHOUT_AN, 697 SOC_PHY_FIRMWARE_DFE_ENABLE = _SHR_PORT_PHY_FIRMWARE_DFE_ENABLE, 698 SOC_PHY_FIRMWARE_LP_DFE_ENABLE = _SHR_PORT_PHY_FIRMWARE_LP_DFE_ENABLE 699 } soc_phy_control_firmware_mode_t; 700 701 typedef enum soc_phy_control_dfe_e { 702 SOC_PHY_DFE_AUTO = _SHR_PORT_PHY_DFE_AUTO, 703 SOC_PHY_DFE_FREEZE = _SHR_PORT_PHY_DFE_FREEZE 704 } soc_phy_control_dfe_t; 705 706 typedef enum soc_phy_control_tx_fir_drivermode_e { 707 SOC_PHY_CONTROL_TX_FIR_DRIVERMODE_DEFAULT = _SHR_PORT_PHY_CONTROL_TX_FIR_DRIVERMODE_DEFAULT, 708 SOC_PHY_CONTROL_TX_FIR_DRIVERMODE_NOT_SUPPORTED = _SHR_PORT_PHY_CONTROL_TX_FIR_DRIVERMODE_NOT_SUPPORTED, 709 SOC_PHY_CONTROL_TX_FIR_DRIVERMODE_HALF_AMP = _SHR_PORT_PHY_CONTROL_TX_FIR_DRIVERMODE_HALF_AMP, 710 SOC_PHY_CONTROL_TX_FIR_DRIVERMODE_HALF_AMP_HI_IMPED = _SHR_PORT_PHY_CONTROL_TX_FIR_DRIVERMODE_HALF_AMP_HI_IMPED 711 } soc_phy_control_tx_fir_drivermode_t ; 712 713 typedef enum soc_phy_control_hg2_bcm_codec_enable_e { 714 SOC_PHY_CONTROL_HG2_BCM_CODEC_ENABLE_OFF = _SHR_PORT_PHY_CONTROL_HG2_BCM_CODEC_ENABLE_OFF, 715 SOC_PHY_CONTROL_HG2_BCM_CODEC_ENABLE_ON_WITH_8BYTE_IPG = _SHR_PORT_PHY_CONTROL_HG2_BCM_CODEC_ENABLE_ON_WITH_8BYTE_IPG, 716 SOC_PHY_CONTROL_HG2_BCM_CODEC_ENABLE_ON_WITH_9BYTE_IPG = _SHR_PORT_PHY_CONTROL_HG2_BCM_CODEC_ENABLE_ON_WITH_9BYTE_IPG 717 } soc_phy_control_hg2_bcm_codec_enable_t ; 718 719 720 typedef enum soc_phy_control_tx_fir_mode_e { 721 SOC_PHY_TX_FIR_MODE_INVALID = _SHR_PORT_PHY_TX_FIR_MODE_INVALID, 722 SOC_PHY_TX_FIR_3TAP_MODE = _SHR_PORT_PHY_TX_FIR_3TAP_MODE, 723 SOC_PHY_TX_FIR_6TAP_MODE = _SHR_PORT_PHY_TX_FIR_6TAP_MODE 724 } soc_phy_control_tx_fir_mode_t; 725 726 727 typedef enum soc_phy_control_autoneg_mode_e { 728 SOC_PHY_CONTROL_AUTONEG_MODE_CL37 = _SHR_PORT_PHY_CONTROL_AUTONEG_MODE_CL37, 729 SOC_PHY_CONTROL_AUTONEG_MODE_CL37_BAM = _SHR_PORT_PHY_CONTROL_AUTONEG_MODE_CL37_BAM, 730 SOC_PHY_CONTROL_AUTONEG_MODE_CL73 = _SHR_PORT_PHY_CONTROL_AUTONEG_MODE_CL73, 731 SOC_PHY_CONTROL_AUTONEG_MODE_CL73_BAM = _SHR_PORT_PHY_CONTROL_AUTONEG_MODE_CL73_BAM, 732 SOC_PHY_CONTROL_AUTONEG_MODE_CL37_CL73 = _SHR_PORT_PHY_CONTROL_AUTONEG_MODE_CL37_CL73, 733 SOC_PHY_CONTROL_AUTONEG_MODE_CL37_CL73_BAM = _SHR_PORT_PHY_CONTROL_AUTONEG_MODE_CL37_CL73_BAM, 734 SOC_PHY_CONTROL_AUTONEG_MODE_CL37_BAM_CL73 = _SHR_PORT_PHY_CONTROL_AUTONEG_MODE_CL37_BAM_CL73, 735 SOC_PHY_CONTROL_AUTONEG_MODE_CL37_BAM_CL73_BAM = _SHR_PORT_PHY_CONTROL_AUTONEG_MODE_CL37_BAM_CL73_BAM 736 } soc_phy_control_autoneg_mode_t; 737 738 typedef enum soc_phy_control_autoneg_oui_value_e { 739 SOC_PHY_CONTROL_AUTONEG_OUI_DEFAULT = _SHR_PORT_PHY_CONTROL_AUTONEG_OUI_DEFAULT 740 } soc_phy_control_autoneg_oui_value_t; 741 742 typedef enum soc_phy_control_polynomial_e { 743 SOC_PHY_PRBS_POLYNOMIAL_X7_X6_1 = _SHR_PORT_PRBS_POLYNOMIAL_X7_X6_1, 744 SOC_PHY_PRBS_POLYNOMIAL_X15_X14_1 = _SHR_PORT_PRBS_POLYNOMIAL_X15_X14_1, 745 SOC_PHY_PRBS_POLYNOMIAL_X23_X18_1 = _SHR_PORT_PRBS_POLYNOMIAL_X23_X18_1, 746 SOC_PHY_PRBS_POLYNOMIAL_X31_X28_1 = _SHR_PORT_PRBS_POLYNOMIAL_X31_X28_1, 747 SOC_PHY_PRBS_POLYNOMIAL_X9_X5_1 = _SHR_PORT_PRBS_POLYNOMIAL_X9_X5_1, 748 SOC_PHY_PRBS_POLYNOMIAL_X11_X9_1 = _SHR_PORT_PRBS_POLYNOMIAL_X11_X9_1, 749 SOC_PHY_PRBS_POLYNOMIAL_X58_X31_1 = _SHR_PORT_PRBS_POLYNOMIAL_X58_X31_1, 750 SOC_PHY_PRBS_POLYNOMIAL_X49_X40_1 = _SHR_PORT_PRBS_POLYNOMIAL_X49_X40_1, 751 SOC_PHY_PRBS_POLYNOMIAL_X20_X3_1 = _SHR_PORT_PRBS_POLYNOMIAL_X20_X3_1, 752 SOC_PHY_PRBS_POLYNOMIAL_X13_X12_X2_1 = _SHR_PORT_PRBS_POLYNOMIAL_X13_X12_X2_1, 753 SOC_PHY_PRBS_POLYNOMIAL_X10_X7_1 = _SHR_PORT_PRBS_POLYNOMIAL_X10_X7_1, 754 SOC_PHY_PRBS_POLYNOMIAL_PAM4_13Q = _SHR_PORT_PRBS_POLYNOMIAL_PAM4_13Q 755 } soc_phy_control_polynomial_t; 756 757 typedef enum soc_phy_control_flow_control_mode_e { 758 SOC_PHY_CONTROL_FLOW_CTRL_MODE_NONE = _SHR_PORT_PHY_CONTROL_FLOW_CTRL_MODE_NONE, 759 SOC_PHY_CONTROL_FLOW_CTRL_LEGACY_PAUSE_EN = _SHR_PORT_PHY_CONTROL_FLOW_CTRL_LEGACY_PAUSE_EN, 760 SOC_PHY_CONTROL_FLOW_CTRL_PFC_PAUSE = _SHR_PORT_PHY_CONTROL_FLOW_CTRL_PFC_PAUSE, 761 SOC_PHY_CONTROL_FLOW_CTRL_LLFC = _SHR_PORT_PHY_CONTROL_FLOW_CTRL_LLFC 762 } soc_phy_control_flow_control_mode_t; 763 764 typedef enum soc_phy_event_e { 765 phyEventInterface, 766 phyEventDuplex, 767 phyEventSpeed, 768 phyEventStop, 769 phyEventResume, 770 phyEventAutoneg, 771 phyEventTxFifoReset, 772 phyEventMacLoopback, 773 phyEventTxSquelch, 774 phyEventLpiBypass, 775 phyEventLinkWait, 776 phyEventSpeedLine, 777 phyEventCount /* Always last */ 778 } soc_phy_event_t; 779 780 #define PHY_EVENT_STRING {"Interface", \ 781 "Duplex", \ 782 "Speed", \ 783 "Stop", \ 784 "Resume", \ 785 "Autoneg", \ 786 "TxFifoReset", \ 787 "MacLoopback", \ 788 "TxSquelch", \ 789 "LpiBypass", \ 790 "LinkWait", \ 791 "SpeedLine" } 792 793 typedef enum soc_phy_control_pcs_mode_e { 794 SOC_PHY_CONTROL_PCS_MODE_IEEE = _SHR_PORT_PHY_CONTROL_PCS_MODE_IEEE, 795 SOC_PHY_CONTROL_PCS_MODE_BRCM = _SHR_PORT_PHY_CONTROL_PCS_MODE_BRCM 796 } soc_phy_control_pcs_mode_t; 797 798 799 /* PHY_STOP flag to use with phyEventStop and phyEventResume */ 800 #define PHY_STOP_MAC_DIS (0x01) 801 #define PHY_STOP_PHY_DIS (0x02) 802 #define PHY_STOP_DRAIN (0x04) 803 #define PHY_STOP_DUPLEX_CHG (0x08) 804 #define PHY_STOP_SPEED_CHG (0x10) 805 #define PHY_STOP_COPPER (0x20) 806 807 /*for pcs bypass non-canned speed */ 808 #define SOC_PHY_NON_CANNED_SPEED 9999 809 810 /* device specific PHYCTRL flags */ 811 #define PHYCTRL_MDIO_ADDR_SHARE (1 << 0) /*use base address of phy to access lanes */ 812 #define PHYCTRL_MDIO_CL45 (1 << 1) /*use MDIO CL45 to access device */ 813 #define PHYCTRL_INIT_DONE (1 << 2) /*lane initialization is done */ 814 #define PHYCTRL_MDIO_BCST (1 << 3) /* capable of MDIO ucode broadcast */ 815 #define PHYCTRL_UCODE_BCST_DONE (1 << 4) /* ucode broadcast done */ 816 #define PHYCTRL_ANEG_INIT_DONE (1 << 5) /* autoneg initialization is done */ 817 #define PHYCTRL_SYS_SIDE_CTRL (1 << 6) /* Select system side for control set/get operations */ 818 #define PHYCTRL_CHAINED_PHY_CTRL (1 << 7) /* Select the chained phy for control set/get operations */ 819 #define PHYCTRL_IS_PORT0 (1 << 8) /* Indicates is 1st port of chip */ 820 #define PHYCTRL_MDIO_BCST2 (1 << 9) /* capable of 2nd MDIO ucode broadcast */ 821 #define ARDON_FABRIC_INIT_START (1 << 10) 822 #define ARDON_FABRIC_INIT_STG_1 (1 << 11) 823 #define ARDON_FABRIC_INIT_STG_2 (1 << 12) 824 #define PHYCTRL_LINE_SIDE_CTRL (1 << 13) /* Explicitly select line side for control set/get operations */ 825 826 827 /* bit 31:29 used for init state */ 828 #define PHYCTRL_INIT_STATE_DEFAULT 0 829 #define PHYCTRL_INIT_STATE_PASS1 1 830 #define PHYCTRL_INIT_STATE_PASS2 2 831 #define PHYCTRL_INIT_STATE_PASS3 3 832 #define PHYCTRL_INIT_STATE_PASS4 4 833 #define PHYCTRL_INIT_STATE_PASS5 5 834 #define PHYCTRL_INIT_STATE_PASS6 6 835 #define PHYCTRL_INIT_STATE_PASS7 7 836 #define PHYCTRL_INIT_MASK 0x7 837 #define PHYCTRL_INIT_SHFT 29 838 #define PHYCTRL_INIT_STATE(_pc) ((((_pc)->flags) >> PHYCTRL_INIT_SHFT) & PHYCTRL_INIT_MASK) 839 #define PHYCTRL_INIT_STATE_SET(_pc,_st) ((_pc)->flags = ((_pc)->flags & \ 840 (~(PHYCTRL_INIT_MASK << PHYCTRL_INIT_SHFT))) | \ 841 (((_st) & PHYCTRL_INIT_MASK) << PHYCTRL_INIT_SHFT)) 842 843 /* control commands used by firmware_set for ucode broadcast. Internal use only */ 844 /* Command should be executed once. Assume all devices in bcst mode */ 845 #define PHYCTRL_UCODE_BCST_ONEDEV 0x10000 846 847 /* Command is executed on each device. Assume all devices in non-bcst mode */ 848 #define PHYCTRL_UCODE_BCST_ALLDEV 0x20000 849 850 /* setup the broadcast mode for firmware download */ 851 #define PHYCTRL_UCODE_BCST_SETUP (0 | PHYCTRL_UCODE_BCST_ALLDEV) 852 853 /* Prepare micro-controller ready for firmware broadcast */ 854 #define PHYCTRL_UCODE_BCST_uC_SETUP (1 | PHYCTRL_UCODE_BCST_ONEDEV) 855 856 /* Re-Enable MDIO broadcast mode */ 857 #define PHYCTRL_UCODE_BCST_ENABLE (2 | PHYCTRL_UCODE_BCST_ALLDEV) 858 859 /* Load firmware */ 860 #define PHYCTRL_UCODE_BCST_LOAD (3 | PHYCTRL_UCODE_BCST_ONEDEV) 861 862 /* Load FC firmware */ 863 #define PHYCTRL_UCODE_BCST_LOAD2 (4 | PHYCTRL_UCODE_BCST_ONEDEV) 864 865 /* Verify firmware download */ 866 #define PHYCTRL_UCODE_BCST_END (5 | PHYCTRL_UCODE_BCST_ALLDEV) 867 868 /* device specific phy_mode values */ 869 #define PHYCTRL_SINGLE_LANE_IN_DUAL_PORT_MODE 9 870 #define PHYCTRL_QSGMII_CORE_PORT 8 871 #define PHYCTRL_MULTI_CORE_PORT 7 872 #define PHYCTRL_LANE_MODE_CUSTOM_3p125MHZ 6 873 #define PHYCTRL_LANE_MODE_CUSTOM1 5 874 #define PHYCTRL_LANE_MODE_CUSTOM 4 875 #define PHYCTRL_ONE_LANE_PORT 3 876 #define PHYCTRL_DUAL_LANE_PORT 2 877 #define PHYCTRL_QUAD_LANE_PORT 1 878 879 #define SOC_MAX_NUM_PHYS_PER_CHIP 8 880 881 #define PHY_OFFSET_VALID(x) (((x) >= 0) && ((x) < SOC_MAX_NUM_PHYS_PER_CHIP)) 882 883 #define SOC_PHYCTRL_PHYN_MAX_LIMIT (_SHR_PHY_GPORT_PHYN_PORT_PHYN_MASK) 884 885 /* Put PHY chip information here. */ 886 typedef struct soc_phy_chip_info_s { 887 int primary; 888 int offset; 889 int offset_to_port[SOC_MAX_NUM_PHYS_PER_CHIP]; 890 } soc_phy_chip_info_t; 891 892 /* Put extra PHY information for each port here. */ 893 typedef struct soc_phy_info_s { 894 uint16 phy_id0; /* PHY ID0 Register */ 895 uint16 phy_id1; /* PHY ID1 Register */ 896 uint16 phy_addr; /* PHY address to use for MII ops */ 897 uint16 phy_addr_int; /* Internal PHY address if applicable */ 898 char *phy_name; /* Short name of PHY */ 899 uint32 phy_flags; /* Logical OR among PHY_FLAGS_xxx */ 900 sal_usecs_t an_timeout; /* Autoneg timeout (from property) */ 901 soc_phy_chip_info_t *chip_info; 902 } soc_phy_info_t; 903 904 /* Data structure used for PHY BER projection */ 905 #define SOC_PORT_PHY_BER_PROJ_P_PRE (1 << 0) /* Pre-config stage for optimezed errcnt threshold*/ 906 #define SOC_PORT_PHY_BER_PROJ_P_CONFIG (1 << 1) /* Conig Analyzer per port */ 907 #define SOC_PORT_PHY_BER_PROJ_P_START (1 << 2) /* Start error accumulation per port */ 908 #define SOC_PORT_PHY_BER_PROJ_P_COLLECT (1 << 3) /* Called n times per port where n=sample_time/m (m==subsample time 5s) */ 909 #define SOC_PORT_PHY_BER_PROJ_P_CALC (1 << 4) /* Calculate BER per port */ 910 911 typedef struct soc_phy_prbs_errcnt_s{ 912 uint32 prbs_errcnt[9]; 913 } soc_phy_prbs_errcnt_t; 914 915 typedef struct soc_stat_ber_proj_s{ 916 int ber_proj_phase; 917 _shr_port_phy_fec_t ber_proj_fec_type; 918 int ber_proj_hist_errcnt_thresh; 919 int ber_proj_timeout_s; 920 soc_phy_prbs_errcnt_t* ber_proj_prbs_errcnt; 921 } soc_port_phy_ber_proj_params_t; 922 923 typedef struct soc_phy_rsfec_symb_errcnt_s { 924 int max_count; 925 int actual_count; 926 uint32* symbol_errcnt; 927 } soc_port_phy_rsfec_symb_errcnt_t; 928 929 /* phy diag function parameters */ 930 #define PHY_DIAG_INSTANCE(_dev,_intf, _lane) (((_dev) << 8) | \ 931 ((_intf) << 4) | (_lane)) 932 #define PHY_DIAG_INST_DEV(_inst) (((_inst) >> 8) & 0xf) 933 #define PHY_DIAG_INST_INTF(_inst) (((_inst) >> 4) & 0xf) 934 #define PHY_DIAG_INST_LN(_inst) ((_inst) & 0xf) 935 #define PHY_DIAG_INST_INTF_LN(_inst) ((_inst) & 0xff) 936 #define PHY_DIAG_INTF_DFLT 0 /* line side interface, default */ 937 #define PHY_DIAG_INTF_LINE 1 /* line side interface, default */ 938 #define PHY_DIAG_INTF_SYS 2 /* system side interface */ 939 #define PHY_DIAG_DEV_DFLT 0 /* internal PHY device, default */ 940 #define PHY_DIAG_DEV_INT 1 /* internal PHY device, default */ 941 #define PHY_DIAG_DEV_EXT 2 /* external PHY device, default */ 942 #define PHY_DIAG_LN_DFLT 0 /* default lane */ 943 #define PHY_DIAG_LN_ALL 0xf /* apply to all lanes */ 944 945 #define PHY_DIAG_INT PHY_DIAG_INSTANCE(PHY_DIAG_DEV_INT, \ 946 PHY_DIAG_INTF_LINE,PHY_DIAG_LN_DFLT) 947 #define PHY_DIAG_EXT PHY_DIAG_INSTANCE(PHY_DIAG_DEV_EXT, \ 948 PHY_DIAG_INTF_LINE,PHY_DIAG_LN_DFLT) 949 #define PHY_DIAG_EXT_SYS PHY_DIAG_INSTANCE(PHY_DIAG_DEV_EXT, \ 950 PHY_DIAG_INTF_SYS,PHY_DIAG_LN_DFLT) 951 #define PHY_DIAG_INST_DEFAULT PHY_DIAG_INSTANCE(PHY_DIAG_DEV_DFLT, \ 952 PHY_DIAG_INTF_DFLT,PHY_DIAG_LN_DFLT) 953 #define PHY_DIAG_INT_LANE(_ln) PHY_DIAG_INSTANCE(PHY_DIAG_DEV_INT, \ 954 PHY_DIAG_INTF_LINE,(_ln)) 955 #define PHY_DIAG_EXT_LANE(_ln) PHY_DIAG_INSTANCE(PHY_DIAG_DEV_EXT, \ 956 PHY_DIAG_INTF_LINE,(_ln)) 957 #define PHY_DIAG_EXT_SYS_LANE(_ln) PHY_DIAG_INSTANCE(PHY_DIAG_DEV_EXT, \ 958 PHY_DIAG_INTF_SYS,(_ln)) 959 960 /* Parameter op_type */ 961 #define PHY_DIAG_CTRL_GET 0 /* a get action */ 962 #define PHY_DIAG_CTRL_SET 1 /* a set action */ 963 #define PHY_DIAG_CTRL_CMD 2 /* a seqeunce of command actions, */ 964 965 /* Parameter op_cmd */ 966 typedef enum phy_diag_ctrl_e { 967 PHY_DIAG_CTRL_START = 0x08000000, 968 PHY_DIAG_CTRL_EYE_MARGIN_VEYE = PHY_DIAG_CTRL_START, 969 PHY_DIAG_CTRL_EYE_MARGIN_VEYE_UP, 970 PHY_DIAG_CTRL_EYE_MARGIN_VEYE_DOWN, 971 PHY_DIAG_CTRL_EYE_MARGIN_HEYE_LEFT, 972 PHY_DIAG_CTRL_EYE_MARGIN_HEYE_RIGHT, 973 PHY_DIAG_CTRL_DSC, 974 PHY_DIAG_CTRL_PROG_DATA, 975 PHY_DIAG_CTRL_EYE_MARGIN_LIVE_LINK, 976 PHY_DIAG_CTRL_EYE_MARGIN_PRBS, 977 PHY_DIAG_CTRL_EYE_MARGIN_PROJ, 978 PHY_DIAG_CTRL_EYE_ENABLE_LIVELINK, 979 PHY_DIAG_CTRL_EYE_DISABLE_LIVELINK, 980 PHY_DIAG_CTRL_EYE_ENABLE_DEADLINK, 981 PHY_DIAG_CTRL_EYE_DISABLE_DEADLINK, 982 PHY_DIAG_CTRL_EYE_SET_VOFFSET, 983 PHY_DIAG_CTRL_EYE_SET_HOFFSET, 984 PHY_DIAG_CTRL_EYE_GET_MAX_VOFFSET, 985 PHY_DIAG_CTRL_EYE_GET_MIN_VOFFSET, 986 PHY_DIAG_CTRL_EYE_GET_INIT_VOFFSET, 987 PHY_DIAG_CTRL_EYE_GET_MAX_LEFT_HOFFSET, 988 PHY_DIAG_CTRL_EYE_GET_MAX_RIGHT_HOFFSET, 989 PHY_DIAG_CTRL_EYE_START_LIVELINK, 990 PHY_DIAG_CTRL_EYE_START_DEADLINK, 991 PHY_DIAG_CTRL_EYE_STOP_LIVELINK, 992 PHY_DIAG_CTRL_EYE_CLEAR_LIVELINK, 993 PHY_DIAG_CTRL_EYE_READ_LIVELINK, 994 PHY_DIAG_CTRL_EYE_READ_DEADLINK, 995 PHY_DIAG_CTRL_MFG_HYB_CANC, 996 PHY_DIAG_CTRL_MFG_DENC, 997 PHY_DIAG_CTRL_MFG_TX_ON, 998 PHY_DIAG_CTRL_MFG_EXIT, 999 PHY_DIAG_CTRL_STATE_TRACE1, 1000 PHY_DIAG_CTRL_STATE_TRACE2, 1001 PHY_DIAG_CTRL_STATE_WHEREAMI, 1002 PHY_DIAG_CTRL_STATE_TEMP, 1003 PHY_DIAG_CTRL_STATE_GENERIC, 1004 PHY_DIAG_CTRL_PEEK, 1005 PHY_DIAG_CTRL_POKE, 1006 PHY_DIAG_CTRL_LOAD_UC, 1007 PHY_DIAG_CTRL_START_FAST_EYESCAN, 1008 PHY_DIAG_CTRL_REG_READ, 1009 PHY_DIAG_CTRL_REG_WRITE, 1010 PHY_DIAG_CTRL_PCS, 1011 PHY_DIAG_CTRL_LINKMON_MODE, 1012 PHY_DIAG_CTRL_LINKMON_STATUS, 1013 PHY_DIAG_CTRL_BER, 1014 PHY_DIAG_CTRL_BER_PROJ, 1015 PHY_DIAG_CTRL_RSFEC_SYMB_ERR, 1016 PHY_DIAG_CTRL_LAST 1017 } phy_diag_ctrl_t; 1018 1019 /* Link monitor modes for PHY_DIAG_CTRL_LINKMON_MODE */ 1020 #define PHY_DIAG_LMM_OFF 0 1021 #define PHY_DIAG_LMM_PCS49_1X10G 1 1022 #define PHY_DIAG_LMM_PCS82_4X10G 2 1023 #define PHY_DIAG_LMM_PCS82_2X25G 3 1024 #define PHY_DIAG_LMM_PCS82_4X25G 4 1025 #define PHY_DIAG_LMM_FC4 5 1026 #define PHY_DIAG_LMM_FC8 6 1027 #define PHY_DIAG_LMM_FC16 7 1028 #define PHY_DIAG_LMM_FC32 8 1029 1030 extern soc_phy_info_t *phy_port_info[SOC_MAX_NUM_DEVICES]; 1031 extern soc_port_t *phy_rmap[SOC_MAX_NUM_DEVICES]; 1032 extern int (*soc_phy_cb_xlate_port_func)(int, int *); 1033 1034 #define PHY_MIN_REG 0 1035 #define PHY_MAX_REG 0x1f 1036 1037 /* PHY address per MDIO Bus */ 1038 #define PHY_ADDR_MIN 0 1039 #define PHY_ADDR_MAX 31 1040 1041 /* 1042 * phy_addr encoding 1043 * bit7, 1: internal MDIO bus, 0: external MDIO bus 1044 * bit9,8,6,5, mdio bus number 1045 * bit4-0, mdio addresses 1046 */ 1047 #define PHY_ID_BUS_UPPER_MASK 0x300 1048 #define PHY_ID_BUS_UPPER_SHIFT 0x6 1049 #define PHY_ID_BUS_LOWER_MASK 0x60 1050 #define PHY_ID_BUS_LOWER_SHIFT 5 1051 #define PHY_ID_BUS_NUM(_id) ((((_id) & PHY_ID_BUS_UPPER_MASK) >> \ 1052 PHY_ID_BUS_UPPER_SHIFT) | (((_id) & PHY_ID_BUS_LOWER_MASK) >> \ 1053 PHY_ID_BUS_LOWER_SHIFT)) 1054 1055 /* phy address now uses bit9,8 and bit6,5 as bus number */ 1056 #define EXT_PHY_ADDR_MAX (256*4) /* value in 2's order */ 1057 1058 #define PHY_ADDR_TO_PORT(unit, phy_addr) (phy_rmap[unit][phy_addr & (EXT_PHY_ADDR_MAX -1)]) 1059 #define SOC_PHY_INFO(unit, port) (phy_port_info[unit][port]) 1060 #define PHY_ID0_REG(unit, port) (SOC_PHY_INFO(unit, port).phy_id0) 1061 #define PHY_ID1_REG(unit, port) (SOC_PHY_INFO(unit, port).phy_id1) 1062 #define PHY_ADDR(unit, port) (SOC_PHY_INFO(unit, port).phy_addr) 1063 #define PHY_ADDR_INT(unit, port) (SOC_PHY_INFO(unit, port).phy_addr_int) 1064 #define PHY_NAME(unit, port) (SOC_PHY_INFO(unit, port).phy_name) 1065 #define PHY_FLAGS(unit, port) (SOC_PHY_INFO(unit, port).phy_flags) 1066 #define PHY_AN_TIMEOUT(unit, port) (SOC_PHY_INFO(unit, port).an_timeout) 1067 1068 #define PHY_FLAGS_COPPER (1 << 0) /* copper medium */ 1069 #define PHY_FLAGS_FIBER (1 << 1) /* fiber medium */ 1070 #define PHY_FLAGS_PASSTHRU (1 << 2) /* serdes passthru (5690) */ 1071 #define PHY_FLAGS_10B (1 << 3) /* ten bit interface (TBI) */ 1072 #define PHY_FLAGS_5421S (1 << 4) /* True if PHY is a 5421S */ 1073 #define PHY_FLAGS_DISABLE (1 << 5) /* True if PHY is disabled */ 1074 #define PHY_FLAGS_C45 (1 << 6) /* True if PHY uses clause 45 1075 * MIIM */ 1076 #define PHY_FLAGS_100FX (1 << 7) /* True if PHY at 100FX 1077 * (for 5482S) */ 1078 #define PHY_FLAGS_MEDIUM_CHANGE (1 << 8) /* True if PHY medium changed 1079 * between copper and fiber */ 1080 #define PHY_FLAGS_SERDES_FIBER (1 << 9) /* True if use internal serdes 1081 * phy */ 1082 #define PHY_FLAGS_WAN (1 << 10) /* WAN mode */ 1083 #define PHY_FLAGS_SGMII_AUTONEG (1 << 11) /* Use SGMII autoneg between 1084 * internal SerDes and external 1085 * PHY */ 1086 #define PHY_FLAGS_EXTERNAL_PHY (1 << 12) /* Port has external PHY */ 1087 #define PHY_FLAGS_FORCED_SGMII (1 << 13) /* Interface between internal and 1088 * external PHY is always SGMII */ 1089 #define PHY_FLAGS_FORCED_COPPER (1 << 14) /* Forced media to copper */ 1090 #define PHY_FLAGS_C73 (1 << 15) /* Auto-negotiation for Backplane 1091 * Ethernet (clause 73) */ 1092 #define PHY_FLAGS_INDEPENDENT_LANE (1 << 16) /* Treat each XGXS lane as 1093 * independent lane. */ 1094 #define PHY_FLAGS_SINGLE_LANE (1 << 17) /* Use only lane 0 of XGXS core. */ 1095 1096 #define PHY_FLAGS_PRIMARY_SERDES (1<<18) 1097 1098 #define PHY_FLAGS_SECONDARY_SERDES (1<<19) 1099 1100 #define PHY_FLAGS_INIT_DONE (1<<20) 1101 1102 #define PHY_FLAGS_HC65_FABRIC (1<<21) /* True if PHY used for SBX */ 1103 /* fabric links */ 1104 #define PHY_FLAGS_EEE_CAPABLE (1<<22) 1105 1106 #define PHY_FLAGS_EEE_ENABLED (1<<23) 1107 1108 #define PHY_FLAGS_EEE_MODE (1<<24) 1109 1110 #define PHY_FLAGS_BR (1<<25) 1111 1112 #define PHY_FLAGS_HS_CAPABLE (1<<26) 1113 1114 #define PHY_FLAGS_CHAINED (1<<27) 1115 1116 #define PHY_FLAGS_REPEATER (1<<28) /* PHY is a repeater */ 1117 1118 #define PHY_FLAGS_SUPPORT_DUAL_RATE (1<<29) 1119 1120 #define PHY_FLAGS_SERVICE_INT_PHY_LINK_GET (1<<30) 1121 #define PHY_FLAGS_NO_SYS_LINE_SPD_SYNC (1<<31) 1122 1123 #define PHY_FLAGS_SET(unit, port, flags) \ 1124 (PHY_FLAGS(unit, port) |= (flags)) 1125 #define PHY_FLAGS_CLR(unit, port, flags) \ 1126 (PHY_FLAGS(unit, port) &= ~(flags)) 1127 #define PHY_FLAGS_TST(unit, port, flags) \ 1128 ((PHY_FLAGS(unit, port) & (flags)) == (flags)) 1129 #define PHY_FLAGS_CLR_ALL(unit, port) \ 1130 (PHY_FLAGS(unit, port) = 0) 1131 #define PHY_COPPER_MODE(unit, port) PHY_FLAGS_TST(unit, port, \ 1132 PHY_FLAGS_COPPER) 1133 #define PHY_FIBER_MODE(unit, port) PHY_FLAGS_TST(unit, port, \ 1134 PHY_FLAGS_FIBER) 1135 #define PHY_PASSTHRU_MODE(unit, port) PHY_FLAGS_TST(unit, port, \ 1136 PHY_FLAGS_PASSTHRU) 1137 #define PHY_TBI_MODE(unit, port) PHY_FLAGS_TST(unit, port, \ 1138 PHY_FLAGS_10B) 1139 #define PHY_5421S_MODE(unit, port) PHY_FLAGS_TST(unit, port, \ 1140 PHY_FLAGS_5421S) 1141 #define PHY_DISABLED_MODE(unit, port) PHY_FLAGS_TST(unit, port, \ 1142 PHY_FLAGS_DISABLE) 1143 #define PHY_CLAUSE45_MODE(unit, port) PHY_FLAGS_TST(unit, port, \ 1144 PHY_FLAGS_C45) 1145 #define PHY_FIBER_100FX_MODE(unit, port) PHY_FLAGS_TST(unit, port, \ 1146 PHY_FLAGS_100FX) 1147 #define PHY_MEDIUM_CHANGED(unit, port) PHY_FLAGS_TST(unit, port, \ 1148 PHY_FLAGS_MEDIUM_CHANGE) 1149 #define PHY_SERDES_FIBER_MODE(unit, port) PHY_FLAGS_TST(unit, port, \ 1150 PHY_FLAGS_SERDES_FIBER) 1151 #define PHY_WAN_MODE(unit, port) PHY_FLAGS_TST(unit, port, \ 1152 PHY_FLAGS_WAN) 1153 #define PHY_SGMII_AUTONEG_MODE(unit, port) PHY_FLAGS_TST(unit, port, \ 1154 PHY_FLAGS_SGMII_AUTONEG) 1155 #define PHY_EXTERNAL_MODE(unit, port) PHY_FLAGS_TST(unit, port, \ 1156 PHY_FLAGS_EXTERNAL_PHY) 1157 #define PHY_FORCED_SGMII_MODE(unit, port) PHY_FLAGS_TST(unit, port, \ 1158 PHY_FLAGS_FORCED_SGMII) 1159 #define PHY_FORCED_COPPER_MODE(unit, port) PHY_FLAGS_TST(unit, port, \ 1160 PHY_FLAGS_FORCED_COPPER) 1161 #define PHY_CLAUSE73_MODE(unit, port) PHY_FLAGS_TST(unit, port, \ 1162 PHY_FLAGS_C73) 1163 #define PHY_INDEPENDENT_LANE_MODE(unit, port) PHY_FLAGS_TST(unit, port, \ 1164 PHY_FLAGS_INDEPENDENT_LANE) 1165 #define PHY_SINGLE_LANE_MODE(unit, port) PHY_FLAGS_TST(unit, port, \ 1166 PHY_FLAGS_SINGLE_LANE) 1167 #define PHY_PRIMARY_SERDES_MODE(unit, port) PHY_FLAGS_TST(unit, port, \ 1168 PHY_FLAGS_PRIMARY_SERDES) 1169 #define PHY_SECONDARY_SERDES_MODE(unit, port) PHY_FLAGS_TST(unit, port, \ 1170 PHY_FLAGS_SECONDARY_SERDES) 1171 #define PHY_HC65_FABRIC_MODE(unit, port) PHY_FLAGS_TST(unit, port, \ 1172 PHY_FLAGS_HC65_FABRIC) 1173 #define PHY_EEE_CAPABLE(unit, port) PHY_FLAGS_TST(unit, port, \ 1174 PHY_FLAGS_EEE_CAPABLE) 1175 #define PHY_BR_MODE(unit, port) (PHY_FLAGS_TST(unit, port, PHY_FLAGS_COPPER) && \ 1176 PHY_FLAGS_TST(unit, port, PHY_FLAGS_BR)) 1177 #define PHY_HS_CAPABLE(unit, port) PHY_FLAGS_TST(unit, port, \ 1178 PHY_FLAGS_HS_CAPABLE) 1179 #define PHY_IS_CHAINED(unit, port) PHY_FLAGS_TST(unit, port, \ 1180 PHY_FLAGS_CHAINED) 1181 #define PHY_REPEATER(unit, port) PHY_FLAGS_TST(unit, port, \ 1182 PHY_FLAGS_REPEATER) 1183 #define PHY_IS_SUPPORT_DUAL_RATE(unit, port) PHY_FLAGS_TST(unit, port, \ 1184 PHY_FLAGS_SUPPORT_DUAL_RATE) 1185 1186 1187 /* PHY 100FX support 1188 * - Currently, the driver supports phy5482s only. Early chip like phy5461, 1189 * phy5464 or other should be very different on 100FX specification. 1190 * - PHY5482s 100FX in bcm95324_a1 board : 1191 * a. 100FX(SFP)-to-fiber wire, means wired at SGOUT+/- and SGIN+/-. 1192 * b. This driver is designed for the 100FX/1000X fiber auto-detect mode. 1193 * c. both 100FX/1000X use the same signal detecting for awaring fiber 1194 * link. 1195 * - Extern definition for explain the 100FX property, PHY_100FX_PROPERTY. 1196 * a. Fiber 100FX 0x1 1197 * b. Copper 100FX 0x2 1198 * c. 100FX only 0x10 1199 * d. 100FX/1000X auto-detect 0x20 1200 */ 1201 #define PHY_100FX_SUPPORT 1 1202 #if PHY_100FX_SUPPORT 1203 #define PROP_100FX_FIBER 0x1 1204 #define PROP_100FX_COPPER 0x2 1205 #define PROP_100FX_ONLY 0x10 1206 #define PROP_100FX_1000X_BOTH 0x20 1207 1208 /* above property-bit mask */ 1209 #define PHY_100FX_PROPERTY (PROP_100FX_FIBER |PROP_100FX_1000X_BOTH) 1210 #else 1211 #undef PHY_100FX_SUPPORT 1212 #endif 1213 1214 1215 #define PHY_DIAG_FULL_SNR_SUPPORT 0x1 1216 1217 typedef struct { 1218 int flags; 1219 uint32 serr; 1220 uint32 cerr; 1221 uint16 block_lock; 1222 uint16 block_point_id; 1223 uint16 digital_temp; 1224 uint16 analog_temp; 1225 uint8 snr_block[48]; 1226 } XGPHY_DIAG_DATA_t; 1227 1228 extern int 1229 soc_phyctrl_software_init(int unit); 1230 1231 extern int 1232 soc_phyctrl_software_port_init(int unit, soc_port_t port); 1233 1234 extern int 1235 soc_phyctrl_software_deinit(int unit); 1236 1237 extern int 1238 soc_phyctrl_init(int unit, soc_port_t port); 1239 1240 extern int 1241 soc_phyctrl_probe(int unit, soc_port_t port); 1242 1243 extern int 1244 soc_phyctrl_drv_name_get(int unit, soc_port_t port, char *name, int len); 1245 1246 extern char * 1247 soc_phyctrl_drv_name(int unit, soc_port_t port); 1248 1249 extern int 1250 soc_phyctrl_reset(int unit, soc_port_t port, void *user_arg); 1251 1252 extern int 1253 soc_phyctrl_link_get(int unit, soc_port_t port, int *link); 1254 1255 extern int 1256 soc_phyctrl_linkfault_get(int unit, soc_port_t port, int *fault); 1257 1258 extern int 1259 soc_phyctrl_enable_set(int unit, soc_port_t port, int enable); 1260 1261 extern int 1262 soc_phyctrl_enable_get(int unit, soc_port_t port, int *enable); 1263 1264 extern int 1265 soc_phyctrl_duplex_set(int unit, soc_port_t port, int duplex); 1266 1267 extern int 1268 soc_phyctrl_duplex_get(int unit, soc_port_t port, int *duplex); 1269 1270 extern int 1271 soc_phyctrl_speed_set(int unit, soc_port_t port, int speed); 1272 1273 extern int 1274 soc_phyctrl_speed_get(int unit, soc_port_t port, int *speed); 1275 1276 extern int 1277 soc_phyctrl_master_set(int unit, soc_port_t port, int master); 1278 1279 extern int 1280 soc_phyctrl_master_get(int unit, soc_port_t port, int *master); 1281 1282 extern int 1283 soc_phyctrl_auto_negotiate_set(int unit, soc_port_t port, int an); 1284 1285 extern int 1286 soc_phyctrl_redirect_auto_negotiate_set(int unit, soc_port_t port, int phyn, 1287 int phy_lane, int sys_side, int an); 1288 1289 extern int 1290 soc_phyctrl_auto_negotiate_get(int unit, soc_port_t port, int *an, 1291 int *an_done); 1292 1293 extern int 1294 soc_phyctrl_redirect_auto_negotiate_get(int unit, soc_port_t port, int phyn, 1295 int phy_lane, int sys_side, int *an, 1296 int *an_done); 1297 1298 extern int 1299 soc_phyctrl_adv_local_set(int unit, soc_port_t port, soc_port_mode_t mode); 1300 1301 extern int 1302 soc_phyctrl_adv_local_get(int unit, soc_port_t port, soc_port_mode_t *mode); 1303 1304 extern int 1305 soc_phyctrl_adv_remote_get(int unit, soc_port_t port, soc_port_mode_t *mode); 1306 1307 extern int 1308 soc_phyctrl_loopback_set(int unit, soc_port_t port, int enable, int serdes_linkup_wait); 1309 1310 extern int 1311 soc_phyctrl_loopback_extended_set(int unit, soc_port_t port, int enable, 1312 int serdes_linkup_wait, uint32 en_int_phy); 1313 1314 extern int 1315 soc_phyctrl_redirect_loopback_set(int unit, soc_port_t port, int phyn, 1316 int phy_lane, int sys_side, int enable, 1317 int serdes_linkup_wait); 1318 1319 extern int 1320 soc_phyctrl_loopback_get(int unit, soc_port_t port, int *enable); 1321 1322 extern int 1323 soc_phyctrl_redirect_loopback_get(int unit, soc_port_t port, int phyn, 1324 int phy_lane, int sys_side, int *enable); 1325 1326 extern int 1327 soc_phyctrl_interface_set(int unit, soc_port_t port, soc_port_if_t pif); 1328 1329 extern int 1330 soc_phyctrl_interface_get(int unit, soc_port_t port, soc_port_if_t *pif); 1331 1332 extern int 1333 soc_phyctrl_ability_get(int unit, soc_port_t port, soc_port_mode_t *mode); 1334 1335 extern int 1336 soc_phyctrl_linkup_evt(int unit, soc_port_t port); 1337 1338 extern int 1339 soc_phyctrl_linkdn_evt(int unit, soc_port_t port); 1340 1341 extern int 1342 soc_phyctrl_mdix_set(int unit, soc_port_t port, soc_port_mdix_t mdix); 1343 1344 #if defined(BCM_WARM_BOOT_SUPPORT) 1345 extern int 1346 soc_phyctrl_mdix_wb_update(int unit, soc_port_t port, soc_port_mdix_t *mdix); 1347 #endif /* defined(BCM_WARM_BOOT_SUPPORT) */ 1348 1349 extern int 1350 soc_phyctrl_mdix_get(int unit, soc_port_t port, soc_port_mdix_t *mdix); 1351 1352 extern int 1353 soc_phyctrl_mdix_status_get(int unit, soc_port_t port, 1354 soc_port_mdix_status_t *status); 1355 1356 extern int 1357 soc_phyctrl_medium_config_set(int unit, soc_port_t port, 1358 soc_port_medium_t medium, 1359 soc_phy_config_t *cfg); 1360 1361 extern int 1362 soc_phyctrl_medium_config_get(int unit, soc_port_t port, 1363 soc_port_medium_t medium, 1364 soc_phy_config_t *cfg); 1365 1366 extern int 1367 soc_phyctrl_medium_get(int unit, soc_port_t port, soc_port_medium_t *medium); 1368 1369 extern int 1370 soc_phyctrl_cable_diag(int unit, soc_port_t port, 1371 soc_port_cable_diag_t *status); 1372 1373 extern int 1374 soc_phyctrl_link_change(int unit, soc_port_t port, int *link); 1375 1376 extern int 1377 soc_phyctrl_control_set(int unit, soc_port_t port, 1378 soc_phy_control_t ctrl_type, uint32 value); 1379 1380 extern int 1381 soc_phyctrl_control_get(int unit, soc_port_t port, 1382 soc_phy_control_t ctrl_type, uint32 *value); 1383 1384 extern int 1385 soc_phyctrl_redirect_control_set(int unit, soc_port_t port, 1386 int phyn, int phy_lane, int sys_side, 1387 soc_phy_control_t ctrl_type, uint32 value); 1388 1389 extern int 1390 soc_phyctrl_redirect_control_get(int unit, soc_port_t port, 1391 int phyn, int phy_lane, int sys_side, 1392 soc_phy_control_t ctrl_type, uint32 *value); 1393 1394 extern int 1395 soc_phyctrl_reg_read(int unit, soc_port_t port, uint32 flags, 1396 uint32 addr, uint32 *data); 1397 1398 extern int 1399 soc_phyctrl_reg_write(int unit, soc_port_t port, uint32 flags, 1400 uint32 addr, uint32 data); 1401 1402 extern int 1403 soc_phyctrl_lane_control_set(int unit, soc_port_t port, int lane, 1404 soc_phy_control_t ctrl_type, uint32 value); 1405 1406 extern int 1407 soc_phyctrl_lane_control_get(int unit, soc_port_t port, int lane, 1408 soc_phy_control_t ctrl_type, uint32 *value); 1409 1410 extern int 1411 soc_phyctrl_synce_clock_set(int unit, soc_port_t port, uint32 mode0, 1412 uint32 mode1, uint32 sdm_value); 1413 1414 extern int 1415 soc_phyctrl_synce_clock_get(int unit, soc_port_t port, uint32 *mode0, 1416 uint32 *mode1, uint32 *sdm_value); 1417 1418 extern int 1419 soc_phyctrl_lane_reg_read(int unit, soc_port_t port, int lane, uint32 flags, 1420 uint32 addr, uint32 *data); 1421 1422 extern int 1423 soc_phyctrl_lane_reg_write(int unit, soc_port_t port, int lane, uint32 flags, 1424 uint32 addr, uint32 data); 1425 1426 extern int 1427 soc_phyctrl_reg_modify(int unit, soc_port_t port, uint32 flags, 1428 uint32 addr, uint32 data, uint32 mask); 1429 1430 extern int 1431 soc_phyctrl_ability_advert_get(int unit, soc_port_t port, 1432 soc_port_ability_t * ability); 1433 1434 extern int 1435 soc_phyctrl_ability_advert_set(int unit, soc_port_t port, 1436 soc_port_ability_t * ability); 1437 1438 extern int 1439 soc_phyctrl_ability_remote_get(int unit, soc_port_t port, 1440 soc_port_ability_t * ability); 1441 1442 extern int 1443 soc_phyctrl_ability_local_get(int unit, soc_port_t port, 1444 soc_port_ability_t * ability); 1445 1446 extern int 1447 soc_phyctrl_firmware_set(int unit, soc_port_t port, uint32 flags, 1448 int offset, uint8 *array, int len); 1449 1450 extern int 1451 soc_phyctrl_primary_set(int unit, soc_port_t port, soc_port_t primary); 1452 1453 extern int 1454 soc_phyctrl_primary_get(int unit, soc_port_t port, soc_port_t *primary); 1455 1456 extern int 1457 soc_phyctrl_offset_set(int unit, soc_port_t port, int offset); 1458 1459 extern int 1460 soc_phyctrl_offset_get(int unit, soc_port_t port, soc_port_t *offset); 1461 1462 extern int 1463 soc_phy_primary_and_offset_get(int unit, soc_port_t port, soc_port_t *primary_port, int *offset); 1464 1465 extern int 1466 soc_phy_boot_master_get(int unit, soc_port_t port, int *bm, int *cm); 1467 1468 extern int 1469 soc_phyctrl_toplvl_reg_read(int unit, soc_port_t port, soc_port_t primary_port, 1470 uint8 reg_offset, uint16 *data); 1471 extern int 1472 soc_phyctrl_toplvl_reg_write(int unit, soc_port_t port, soc_port_t primary_port, 1473 uint8 reg_offset, uint16 data); 1474 1475 extern int 1476 soc_phyctrl_port_phy_multi_get(int unit, soc_port_t port, uint32 flags, 1477 uint32 dev_addr, uint32 offset, int max_size, uint8 *data, int *actual_size); 1478 1479 extern int 1480 soc_phyctrl_detach(int unit, soc_port_t port); 1481 1482 extern int 1483 soc_phyctrl_notify(int unit, soc_port_t port, 1484 soc_phy_event_t event, uint32 data); 1485 1486 extern int 1487 soc_phy_init(int unit); 1488 1489 extern int 1490 soc_phy_port_init(int unit, soc_port_t port); 1491 1492 extern int 1493 soc_phy_deinit(int unit); 1494 1495 extern int 1496 soc_phy_info_get(int unit, soc_port_t port, soc_phy_info_t *pi); 1497 1498 extern uint16 1499 soc_phy_addr_of_port(int unit, soc_port_t port); 1500 1501 extern uint16 1502 soc_phy_addr_int_of_port(int unit, soc_port_t port); 1503 #define PORT_TO_PHY_ADDR_INT(_u, _p) PHY_ADDR_INT((_u), (_p)) 1504 1505 extern soc_port_t 1506 soc_phy_addr_to_port(int unit, uint16 phy_id); 1507 #define PORT_TO_PHY_ADDR(_u, _p) PHY_ADDR((_u), (_p)) 1508 1509 extern uint16 1510 soc_phy_id0reg_get(int unit, soc_port_t port); 1511 1512 extern uint16 1513 soc_phy_id1reg_get(int unit, soc_port_t port); 1514 1515 extern int 1516 soc_phy_is_c45_miim(int unit, soc_port_t port); 1517 1518 extern int 1519 soc_phy_port_offset_get(int unit, soc_port_t port); 1520 1521 extern char* 1522 soc_phy_name_get(int unit, soc_port_t port); 1523 1524 extern sal_usecs_t 1525 soc_phy_an_timeout_get(int unit, soc_port_t port); 1526 1527 extern int 1528 soc_phy_cfg_addr_get(int unit, soc_port_t port, int flags,uint16 *addr_ptr); 1529 1530 extern int 1531 soc_phy_cfg_addr_set(int unit, soc_port_t port, int flags, uint16 addr); 1532 1533 extern int 1534 soc_phyctrl_pbm_probe_init(int unit, pbmp_t pbmp, pbmp_t *okay_pbmp); 1535 1536 extern int 1537 soc_phyctrl_set_speed_max(int unit, soc_port_t port, int speed_max); 1538 /* 1539 * Phy reset method overloading support 1540 */ 1541 typedef _shr_port_phy_reset_cb_t soc_port_phy_reset_cb_t; 1542 1543 extern int 1544 soc_phy_reset_register(int unit, 1545 soc_port_t port, 1546 soc_port_phy_reset_cb_t callback, 1547 void *user_data, 1548 int reg_default); 1549 1550 extern int 1551 soc_phy_reset_unregister(int unit, 1552 soc_port_t port, 1553 soc_port_phy_reset_cb_t callback, 1554 void *user_data); 1555 1556 extern int 1557 soc_phy_reset(int unit, soc_port_t port); 1558 1559 /* 1560 * Medium configuration and control 1561 */ 1562 typedef _shr_port_medium_status_cb_t soc_port_medium_status_cb_t; 1563 1564 1565 extern int 1566 soc_phy_medium_status_register(int unit, 1567 soc_port_t port, 1568 soc_port_medium_status_cb_t cb, 1569 void *user_data); 1570 1571 extern int 1572 soc_phy_medium_status_unregister(int unit, 1573 soc_port_t port, 1574 soc_port_medium_status_cb_t cb, 1575 void *user_data); 1576 1577 extern void 1578 soc_phy_medium_status_notify(int unit, soc_port_t port, 1579 soc_port_medium_t medium); 1580 1581 extern int 1582 soc_phyctrl_diag_ctrl(int, soc_port_t, uint32, int, int, void *); 1583 1584 extern int 1585 soc_cmic_rate_param_get(int unit, int *dividend, int *divisor); 1586 1587 extern int 1588 soc_cmic_rate_param_set(int unit, int dividend, int divisor); 1589 1590 /* 1591 * Initialization of the features above 1592 */ 1593 extern int 1594 soc_phy_common_init(int unit); 1595 extern int 1596 soc_phy_common_detach(int unit); 1597 1598 #endif /* _PHYCTRL_H_ */