ydc_ddr_bist.h (193547B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 */ 7 8 #ifndef YDC_DDR_BIST_BIST_H__ 9 #define YDC_DDR_BIST_BIST_H__ 10 11 #ifndef YDC_DDR_BIST_BIST_REG_BASE 12 #define YDC_DDR_BIST_BIST_REG_BASE 0x1023BC00 13 #endif 14 15 #ifndef YDC_DDR_BIST_BIST_PHY_BITWITDH_IS_32 16 #define YDC_DDR_BIST_BIST_PHY_BITWITDH_IS_32 1 17 #endif 18 19 #define YDC_DDR_BIST_BIST_POLL_INTERVAL_US 10 20 #define YDC_DDR_BIST_BIST_POLL_COUNT_LIMIT 100000 21 22 typedef struct ydc_ddr_bist_info_s 23 { 24 uint32 write_weight; 25 uint32 read_weight; 26 uint32 bist_timer_us; /* if bist_timer_us != 0, ignore bist_num_actions and wait bist_timer_us before stopping bist */ 27 uint32 bist_num_actions; 28 uint32 bist_start_address; 29 uint32 bist_end_address; 30 uint32 prbs_mode; 31 uint32 mpr_mode; 32 uint32 addr_prbs_mode; 33 } ydc_ddr_bist_info_t; 34 35 typedef struct ydc_ddr_bist_err_cnt_s 36 { 37 uint32 bist_err_occur; 38 uint32 bist_full_err_cnt; 39 uint32 bist_single_err_cnt; 40 uint32 bist_global_err_cnt; 41 } ydc_ddr_bist_err_cnt_t; 42 43 extern int soc_ydc_ddr_bist_config_set(int unit, int phy_ndx, ydc_ddr_bist_info_t *bist_info); 44 extern int soc_ydc_ddr_bist_run(int unit, int phy_ndx, ydc_ddr_bist_err_cnt_t *error_count); 45 46 /** 47 * m = memory, c = core, r = register, f = field, d = data. 48 */ 49 #if !defined(GET_FIELD) && !defined(SET_FIELD) 50 #define BRCM_ALIGN(c,r,f) c##_##r##_##f##_ALIGN 51 #define BRCM_BITS(c,r,f) c##_##r##_##f##_BITS 52 #define BRCM_MASK(c,r,f) c##_##r##_##f##_MASK 53 #define BRCM_SHIFT(c,r,f) c##_##r##_##f##_SHIFT 54 55 #define GET_FIELD(m,c,r,f) \ 56 ((((m) & BRCM_MASK(c,r,f)) >> BRCM_SHIFT(c,r,f)) << BRCM_ALIGN(c,r,f)) 57 58 #define SET_FIELD(m,c,r,f,d) \ 59 ((m) = (((m) & ~BRCM_MASK(c,r,f)) | ((((d) >> BRCM_ALIGN(c,r,f)) << \ 60 BRCM_SHIFT(c,r,f)) & BRCM_MASK(c,r,f))) \ 61 ) 62 63 #define SET_TYPE_FIELD(m,c,r,f,d) SET_FIELD(m,c,r,f,c##_##d) 64 #define SET_NAME_FIELD(m,c,r,f,d) SET_FIELD(m,c,r,f,c##_##r##_##f##_##d) 65 #define SET_VALUE_FIELD(m,c,r,f,d) SET_FIELD(m,c,r,f,d) 66 67 #endif /* GET & SET */ 68 69 #define YDC_DDR_BIST_BIST_REG_READ(_unit, _pc, flags, _reg_addr, _val) \ 70 *(uint32 *)_val = REGRD((_pc) + (_reg_addr)) 71 /* soc_ddr40_phy_reg_ci_read((_unit), (_pc), (_reg_addr), (_val)) */ 72 #define YDC_DDR_BIST_BIST_REG_WRITE(_unit, _pc, _flags, _reg_addr, _val) \ 73 REGWR((_pc) + (_reg_addr), (_val)) 74 /* soc_ddr40_phy_reg_ci_write((_unit), (_pc), (_reg_addr), (_val)) */ 75 #define YDC_DDR_BIST_BIST_REG_MODIFY(_unit, _pc, _flags, _reg_addr, _val, _mask) \ 76 REGWR((_pc) + (_reg_addr), (REGRD((_pc) + (_reg_addr)) & ~(_mask)) | ((_val) & (_mask))) 77 /* soc_ddr40_phy_reg_ci_modify((_unit), (_pc), (_reg_addr), (_val), (_mask)) */ 78 #define YDC_DDR_BIST_BIST_GET_FIELD(m,c,r,f) \ 79 GET_FIELD(m,c,r,f) 80 #define YDC_DDR_BIST_BIST_SET_FIELD(m,c,r,f,d) \ 81 SET_FIELD(m,c,r,f,d) 82 83 /**************************************************************************** 84 * Core Enums. 85 */ 86 #define YDC_DDR_BIST_BIST_CONFIG 0x00000000 87 #define YDC_DDR_BIST_BIST_CONFIG_2 0x00000004 88 #define YDC_DDR_BIST_BIST_GENERAL_CONFIGURATIONS 0x00000008 89 #define YDC_DDR_BIST_DRAM_SPECIAL_FEATURES 0x0000000C 90 #define YDC_DDR_BIST_BIST_CONFIGURATIONS_0 0x00000010 91 #define YDC_DDR_BIST_BIST_CONFIGURATIONS_1 0x00000014 92 #define YDC_DDR_BIST_BIST_PRBS_DATA_SEED_MSB_31_TO_0 0x00000018 93 #define YDC_DDR_BIST_BIST_PRBS_DATA_SEED_MSB_63_TO_32 0x0000001C 94 #define YDC_DDR_BIST_BIST_PRBS_DATA_SEED_MSB_95_TO_64 0x00000020 95 #define YDC_DDR_BIST_BIST_PRBS_DATA_SEED_MSB_127_TO_96 0x00000024 96 #define YDC_DDR_BIST_BIST_PRBS_DATA_SEED_LSB_31_TO_0 0x00000028 97 #define YDC_DDR_BIST_BIST_PRBS_DATA_SEED_LSB_63_TO_32 0x0000002C 98 #define YDC_DDR_BIST_BIST_PRBS_DATA_SEED_LSB_95_TO_64 0x00000030 99 #define YDC_DDR_BIST_BIST_PRBS_DATA_SEED_LSB_127_TO_96 0x00000034 100 #define YDC_DDR_BIST_BIST_PRBS_ADDR_SEED 0x00000038 101 #define YDC_DDR_BIST_BIST_MPR_STAGGER_WEIGHTS 0x0000003C 102 #define YDC_DDR_BIST_BIST_MPR_STAGGER_PATTERNS 0x00000040 103 #define YDC_DDR_BIST_BIST_PATTERN_REPETITION_0 0x00000044 104 #define YDC_DDR_BIST_BIST_PATTERN_REPETITION_1 0x00000048 105 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_1_MSB_31_TO_0 0x0000004C 106 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_1_MSB_63_TO_32 0x00000050 107 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_1_MSB_95_TO_64 0x00000054 108 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_1_MSB_127_TO_96 0x00000058 109 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_1_LSB_31_TO_0 0x0000005C 110 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_1_LSB_63_TO_32 0x00000060 111 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_1_LSB_95_TO_64 0x00000064 112 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_1_LSB_127_TO_96 0x00000068 113 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_2_MSB_31_TO_0 0x0000006C 114 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_2_MSB_63_TO_32 0x00000070 115 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_2_MSB_95_TO_64 0x00000074 116 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_2_MSB_127_TO_96 0x00000078 117 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_2_LSB_31_TO_0 0x0000007C 118 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_2_LSB_63_TO_32 0x00000080 119 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_2_LSB_95_TO_64 0x00000084 120 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_2_LSB_127_TO_96 0x00000088 121 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_3_MSB_31_TO_0 0x0000008C 122 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_3_MSB_63_TO_32 0x00000090 123 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_3_MSB_95_TO_64 0x00000094 124 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_3_MSB_127_TO_96 0x00000098 125 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_3_LSB_31_TO_0 0x0000009C 126 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_3_LSB_63_TO_32 0x000000A0 127 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_3_LSB_95_TO_64 0x000000A4 128 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_3_LSB_127_TO_96 0x000000A8 129 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_4_MSB_31_TO_0 0x000000AC 130 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_4_MSB_63_TO_32 0x000000B0 131 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_4_MSB_95_TO_64 0x000000B4 132 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_4_MSB_127_TO_96 0x000000B8 133 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_4_LSB_31_TO_0 0x000000BC 134 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_4_LSB_63_TO_32 0x000000C0 135 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_4_LSB_95_TO_64 0x000000C4 136 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_4_LSB_127_TO_96 0x000000C8 137 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_5_MSB_31_TO_0 0x000000CC 138 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_5_MSB_63_TO_32 0x000000D0 139 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_5_MSB_95_TO_64 0x000000D4 140 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_5_MSB_127_TO_96 0x000000D8 141 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_5_LSB_31_TO_0 0x000000DC 142 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_5_LSB_63_TO_32 0x000000E0 143 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_5_LSB_95_TO_64 0x000000E4 144 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_5_LSB_127_TO_96 0x000000E8 145 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_6_MSB_31_TO_0 0x000000EC 146 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_6_MSB_63_TO_32 0x000000F0 147 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_6_MSB_95_TO_64 0x000000F4 148 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_6_MSB_127_TO_96 0x000000F8 149 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_6_LSB_31_TO_0 0x000000FC 150 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_6_LSB_63_TO_32 0x00000100 151 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_6_LSB_95_TO_64 0x00000104 152 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_6_LSB_127_TO_96 0x00000108 153 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_7_MSB_31_TO_0 0x0000010C 154 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_7_MSB_63_TO_32 0x00000110 155 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_7_MSB_95_TO_64 0x00000114 156 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_7_MSB_127_TO_96 0x00000118 157 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_7_LSB_31_TO_0 0x0000011C 158 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_7_LSB_63_TO_32 0x00000120 159 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_7_LSB_95_TO_64 0x00000124 160 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_7_LSB_127_TO_96 0x00000128 161 #define YDC_DDR_BIST_BIST_RATE_LIMITER 0x0000012C 162 #define YDC_DDR_BIST_BIST_NUMBER_OF_ACTIONS 0x00000130 163 #define YDC_DDR_BIST_BIST_START_ADDRESS 0x00000134 164 #define YDC_DDR_BIST_BIST_END_ADDRESS 0x00000138 165 #define YDC_DDR_BIST_BIST_SINGLE_BIT_MASK 0x0000013C 166 #define YDC_DDR_BIST_BIST_PATTERN_WORD_7 0x00000140 167 #define YDC_DDR_BIST_BIST_PATTERN_WORD_6 0x00000144 168 #define YDC_DDR_BIST_BIST_PATTERN_WORD_5 0x00000148 169 #define YDC_DDR_BIST_BIST_PATTERN_WORD_4 0x0000014C 170 #define YDC_DDR_BIST_BIST_PATTERN_WORD_3 0x00000150 171 #define YDC_DDR_BIST_BIST_PATTERN_WORD_2 0x00000154 172 #define YDC_DDR_BIST_BIST_PATTERN_WORD_1 0x00000158 173 #define YDC_DDR_BIST_BIST_PATTERN_WORD_0 0x0000015C 174 #define YDC_DDR_BIST_BIST_FULL_MASK_WORD_7 0x00000160 175 #define YDC_DDR_BIST_BIST_FULL_MASK_WORD_6 0x00000164 176 #define YDC_DDR_BIST_BIST_FULL_MASK_WORD_5 0x00000168 177 #define YDC_DDR_BIST_BIST_FULL_MASK_WORD_4 0x0000016C 178 #define YDC_DDR_BIST_BIST_FULL_MASK_WORD_3 0x00000170 179 #define YDC_DDR_BIST_BIST_FULL_MASK_WORD_2 0x00000174 180 #define YDC_DDR_BIST_BIST_FULL_MASK_WORD_1 0x00000178 181 #define YDC_DDR_BIST_BIST_FULL_MASK_WORD_0 0x0000017C 182 #define YDC_DDR_BIST_BIST_STATUSES 0x00000180 183 #define YDC_DDR_BIST_BIST_FULL_MASK_ERROR_COUNTER 0x00000184 184 #define YDC_DDR_BIST_BIST_SINGLE_BIT_MASK_ERROR_COUNTER 0x00000188 185 #define YDC_DDR_BIST_BIST_ERROR_OCCURRED 0x0000018C 186 #define YDC_DDR_BIST_BIST_GLOBAL_ERROR_COUNTER 0x00000190 187 #define YDC_DDR_BIST_CNT_BIST_DBI_ERR_GLOBAL 0x00000194 188 #define YDC_DDR_BIST_BIST_DBI_ERR_OCCURED 0x00000198 189 #define YDC_DDR_BIST_CNT_BIST_EDC_ERR_GLOBAL 0x0000019C 190 #define YDC_DDR_BIST_BIST_EDC_ERR_OCCURED 0x000001A0 191 #define YDC_DDR_BIST_BIST_LAST_ADDR_ERR 0x000001A4 192 #define YDC_DDR_BIST_BIST_LAST_DATA_ERR_MSB_31_TO_0 0x000001A8 193 #define YDC_DDR_BIST_BIST_LAST_DATA_ERR_MSB_63_TO_32 0x000001AC 194 #define YDC_DDR_BIST_BIST_LAST_DATA_ERR_MSB_95_TO_64 0x000001B0 195 #define YDC_DDR_BIST_BIST_LAST_DATA_ERR_MSB_127_TO_96 0x000001B4 196 #define YDC_DDR_BIST_BIST_LAST_DATA_ERR_LSB_31_TO_0 0x000001B8 197 #define YDC_DDR_BIST_BIST_LAST_DATA_ERR_LSB_63_TO_32 0x000001BC 198 #define YDC_DDR_BIST_BIST_LAST_DATA_ERR_LSB_95_TO_64 0x000001C0 199 #define YDC_DDR_BIST_BIST_LAST_DATA_ERR_LSB_127_TO_96 0x000001C4 200 #define YDC_DDR_BIST_BIST_LAST_READ_DATA_MSB_31_TO_0 0x000001C8 201 #define YDC_DDR_BIST_BIST_LAST_READ_DATA_MSB_63_TO_32 0x000001CC 202 #define YDC_DDR_BIST_BIST_LAST_READ_DATA_MSB_95_TO_64 0x000001D0 203 #define YDC_DDR_BIST_BIST_LAST_READ_DATA_MSB_127_TO_96 0x000001D4 204 #define YDC_DDR_BIST_BIST_LAST_READ_DATA_LSB_31_TO_0 0x000001D8 205 #define YDC_DDR_BIST_BIST_LAST_READ_DATA_LSB_63_TO_32 0x000001DC 206 #define YDC_DDR_BIST_BIST_LAST_READ_DATA_LSB_95_TO_64 0x000001E0 207 #define YDC_DDR_BIST_BIST_LAST_READ_DATA_LSB_127_TO_96 0x000001E4 208 #define YDC_DDR_BIST_GDDR5_BIST_FINISH_PRD 0x000001E8 209 #define YDC_DDR_BIST_INTIAL_CALIB_USE_MPR 0x000001EC 210 211 /**************************************************************************** 212 * YDC_DDR_BIST_BIST_YDC_DDR_BIST 213 */ 214 215 /* BIST Configuration Register */ 216 #define READ_YDC_DDR_BIST_BIST_CONFIGr(_unit, _pc, _val) \ 217 YDC_DDR_BIST_BIST_REG_READ((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_CONFIG, (_val)) 218 #define WRITE_YDC_DDR_BIST_BIST_CONFIGr(_unit, _pc, _val) \ 219 YDC_DDR_BIST_BIST_REG_WRITE((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_CONFIG, (_val)) 220 #define MODIFY_YDC_DDR_BIST_BIST_CONFIGr(_unit, _pc, _val, _mask) \ 221 YDC_DDR_BIST_BIST_REG_MODIFY((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_CONFIG, (_val), (_mask)) 222 223 /* BIST Configuration Register 2 */ 224 #define READ_YDC_DDR_BIST_BIST_CONFIG_2r(_unit, _pc, _val) \ 225 YDC_DDR_BIST_BIST_REG_READ((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_CONFIG_2, (_val)) 226 #define WRITE_YDC_DDR_BIST_BIST_CONFIG_2r(_unit, _pc, _val) \ 227 YDC_DDR_BIST_BIST_REG_WRITE((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_CONFIG_2, (_val)) 228 #define MODIFY_YDC_DDR_BIST_BIST_CONFIG_2r(_unit, _pc, _val, _mask) \ 229 YDC_DDR_BIST_BIST_REG_MODIFY((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_CONFIG_2, (_val), (_mask)) 230 231 /* BIST General Configurations Register */ 232 #define READ_YDC_DDR_BIST_BIST_GENERAL_CONFIGURATIONSr(_unit, _pc, _val) \ 233 YDC_DDR_BIST_BIST_REG_READ((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_GENERAL_CONFIGURATIONS, (_val)) 234 #define WRITE_YDC_DDR_BIST_BIST_GENERAL_CONFIGURATIONSr(_unit, _pc, _val) \ 235 YDC_DDR_BIST_BIST_REG_WRITE((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_GENERAL_CONFIGURATIONS, (_val)) 236 #define MODIFY_YDC_DDR_BIST_BIST_GENERAL_CONFIGURATIONSr(_unit, _pc, _val, _mask) \ 237 YDC_DDR_BIST_BIST_REG_MODIFY((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_GENERAL_CONFIGURATIONS, (_val), (_mask)) 238 239 /* DRAM Special Features Register */ 240 #define READ_YDC_DDR_BIST_DRAM_SPECIAL_FEATURESr(_unit, _pc, _val) \ 241 YDC_DDR_BIST_BIST_REG_READ((_unit), (_pc), 0x00, YDC_DDR_BIST_DRAM_SPECIAL_FEATURES, (_val)) 242 #define WRITE_YDC_DDR_BIST_DRAM_SPECIAL_FEATURESr(_unit, _pc, _val) \ 243 YDC_DDR_BIST_BIST_REG_WRITE((_unit), (_pc), 0x00, YDC_DDR_BIST_DRAM_SPECIAL_FEATURES, (_val)) 244 #define MODIFY_YDC_DDR_BIST_DRAM_SPECIAL_FEATURESr(_unit, _pc, _val, _mask) \ 245 YDC_DDR_BIST_BIST_REG_MODIFY((_unit), (_pc), 0x00, YDC_DDR_BIST_DRAM_SPECIAL_FEATURES, (_val), (_mask)) 246 247 /* BIST Configurations 0 Register */ 248 #define READ_YDC_DDR_BIST_BIST_CONFIGURATIONS_0r(_unit, _pc, _val) \ 249 YDC_DDR_BIST_BIST_REG_READ((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_CONFIGURATIONS_0, (_val)) 250 #define WRITE_YDC_DDR_BIST_BIST_CONFIGURATIONS_0r(_unit, _pc, _val) \ 251 YDC_DDR_BIST_BIST_REG_WRITE((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_CONFIGURATIONS_0, (_val)) 252 #define MODIFY_YDC_DDR_BIST_BIST_CONFIGURATIONS_0r(_unit, _pc, _val, _mask) \ 253 YDC_DDR_BIST_BIST_REG_MODIFY((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_CONFIGURATIONS_0, (_val), (_mask)) 254 255 /* BIST Configurations 1 Register */ 256 #define READ_YDC_DDR_BIST_BIST_CONFIGURATIONS_1r(_unit, _pc, _val) \ 257 YDC_DDR_BIST_BIST_REG_READ((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_CONFIGURATIONS_1, (_val)) 258 #define WRITE_YDC_DDR_BIST_BIST_CONFIGURATIONS_1r(_unit, _pc, _val) \ 259 YDC_DDR_BIST_BIST_REG_WRITE((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_CONFIGURATIONS_1, (_val)) 260 #define MODIFY_YDC_DDR_BIST_BIST_CONFIGURATIONS_1r(_unit, _pc, _val, _mask) \ 261 YDC_DDR_BIST_BIST_REG_MODIFY((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_CONFIGURATIONS_1, (_val), (_mask)) 262 263 /* BIST PRBS Data Seed MSB 31 to 0 Register */ 264 #define READ_YDC_DDR_BIST_BIST_PRBS_DATA_SEED_MSB_31_TO_0r(_unit, _pc, _val) \ 265 YDC_DDR_BIST_BIST_REG_READ((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_PRBS_DATA_SEED_MSB_31_TO_0, (_val)) 266 #define WRITE_YDC_DDR_BIST_BIST_PRBS_DATA_SEED_MSB_31_TO_0r(_unit, _pc, _val) \ 267 YDC_DDR_BIST_BIST_REG_WRITE((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_PRBS_DATA_SEED_MSB_31_TO_0, (_val)) 268 #define MODIFY_YDC_DDR_BIST_BIST_PRBS_DATA_SEED_MSB_31_TO_0r(_unit, _pc, _val, _mask) \ 269 YDC_DDR_BIST_BIST_REG_MODIFY((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_PRBS_DATA_SEED_MSB_31_TO_0, (_val), (_mask)) 270 271 /* BIST PRBS Data Seed MSB 63 to 32 Register */ 272 #define READ_YDC_DDR_BIST_BIST_PRBS_DATA_SEED_MSB_63_TO_32r(_unit, _pc, _val) \ 273 YDC_DDR_BIST_BIST_REG_READ((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_PRBS_DATA_SEED_MSB_63_TO_32, (_val)) 274 #define WRITE_YDC_DDR_BIST_BIST_PRBS_DATA_SEED_MSB_63_TO_32r(_unit, _pc, _val) \ 275 YDC_DDR_BIST_BIST_REG_WRITE((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_PRBS_DATA_SEED_MSB_63_TO_32, (_val)) 276 #define MODIFY_YDC_DDR_BIST_BIST_PRBS_DATA_SEED_MSB_63_TO_32r(_unit, _pc, _val, _mask) \ 277 YDC_DDR_BIST_BIST_REG_MODIFY((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_PRBS_DATA_SEED_MSB_63_TO_32, (_val), (_mask)) 278 279 /* BIST PRBS Data Seed MSB 95 to 64 Register */ 280 #define READ_YDC_DDR_BIST_BIST_PRBS_DATA_SEED_MSB_95_TO_64r(_unit, _pc, _val) \ 281 YDC_DDR_BIST_BIST_REG_READ((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_PRBS_DATA_SEED_MSB_95_TO_64, (_val)) 282 #define WRITE_YDC_DDR_BIST_BIST_PRBS_DATA_SEED_MSB_95_TO_64r(_unit, _pc, _val) \ 283 YDC_DDR_BIST_BIST_REG_WRITE((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_PRBS_DATA_SEED_MSB_95_TO_64, (_val)) 284 #define MODIFY_YDC_DDR_BIST_BIST_PRBS_DATA_SEED_MSB_95_TO_64r(_unit, _pc, _val, _mask) \ 285 YDC_DDR_BIST_BIST_REG_MODIFY((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_PRBS_DATA_SEED_MSB_95_TO_64, (_val), (_mask)) 286 287 /* BIST PRBS Data Seed MSB 127 to 96 Register */ 288 #define READ_YDC_DDR_BIST_BIST_PRBS_DATA_SEED_MSB_127_TO_96r(_unit, _pc, _val) \ 289 YDC_DDR_BIST_BIST_REG_READ((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_PRBS_DATA_SEED_MSB_127_TO_96, (_val)) 290 #define WRITE_YDC_DDR_BIST_BIST_PRBS_DATA_SEED_MSB_127_TO_96r(_unit, _pc, _val) \ 291 YDC_DDR_BIST_BIST_REG_WRITE((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_PRBS_DATA_SEED_MSB_127_TO_96, (_val)) 292 #define MODIFY_YDC_DDR_BIST_BIST_PRBS_DATA_SEED_MSB_127_TO_96r(_unit, _pc, _val, _mask) \ 293 YDC_DDR_BIST_BIST_REG_MODIFY((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_PRBS_DATA_SEED_MSB_127_TO_96, (_val), (_mask)) 294 295 /* BIST PRBS Data Seed LSB 31 to 0 Register */ 296 #define READ_YDC_DDR_BIST_BIST_PRBS_DATA_SEED_LSB_31_TO_0r(_unit, _pc, _val) \ 297 YDC_DDR_BIST_BIST_REG_READ((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_PRBS_DATA_SEED_LSB_31_TO_0, (_val)) 298 #define WRITE_YDC_DDR_BIST_BIST_PRBS_DATA_SEED_LSB_31_TO_0r(_unit, _pc, _val) \ 299 YDC_DDR_BIST_BIST_REG_WRITE((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_PRBS_DATA_SEED_LSB_31_TO_0, (_val)) 300 #define MODIFY_YDC_DDR_BIST_BIST_PRBS_DATA_SEED_LSB_31_TO_0r(_unit, _pc, _val, _mask) \ 301 YDC_DDR_BIST_BIST_REG_MODIFY((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_PRBS_DATA_SEED_LSB_31_TO_0, (_val), (_mask)) 302 303 /* BIST PRBS Data Seed LSB 63 to 32 Register */ 304 #define READ_YDC_DDR_BIST_BIST_PRBS_DATA_SEED_LSB_63_TO_32r(_unit, _pc, _val) \ 305 YDC_DDR_BIST_BIST_REG_READ((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_PRBS_DATA_SEED_LSB_63_TO_32, (_val)) 306 #define WRITE_YDC_DDR_BIST_BIST_PRBS_DATA_SEED_LSB_63_TO_32r(_unit, _pc, _val) \ 307 YDC_DDR_BIST_BIST_REG_WRITE((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_PRBS_DATA_SEED_LSB_63_TO_32, (_val)) 308 #define MODIFY_YDC_DDR_BIST_BIST_PRBS_DATA_SEED_LSB_63_TO_32r(_unit, _pc, _val, _mask) \ 309 YDC_DDR_BIST_BIST_REG_MODIFY((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_PRBS_DATA_SEED_LSB_63_TO_32, (_val), (_mask)) 310 311 /* BIST PRBS Data Seed LSB 95 to 64 Register */ 312 #define READ_YDC_DDR_BIST_BIST_PRBS_DATA_SEED_LSB_95_TO_64r(_unit, _pc, _val) \ 313 YDC_DDR_BIST_BIST_REG_READ((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_PRBS_DATA_SEED_LSB_95_TO_64, (_val)) 314 #define WRITE_YDC_DDR_BIST_BIST_PRBS_DATA_SEED_LSB_95_TO_64r(_unit, _pc, _val) \ 315 YDC_DDR_BIST_BIST_REG_WRITE((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_PRBS_DATA_SEED_LSB_95_TO_64, (_val)) 316 #define MODIFY_YDC_DDR_BIST_BIST_PRBS_DATA_SEED_LSB_95_TO_64r(_unit, _pc, _val, _mask) \ 317 YDC_DDR_BIST_BIST_REG_MODIFY((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_PRBS_DATA_SEED_LSB_95_TO_64, (_val), (_mask)) 318 319 /* BIST PRBS Data Seed LSB 127 to 96 Register */ 320 #define READ_YDC_DDR_BIST_BIST_PRBS_DATA_SEED_LSB_127_TO_96r(_unit, _pc, _val) \ 321 YDC_DDR_BIST_BIST_REG_READ((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_PRBS_DATA_SEED_LSB_127_TO_96, (_val)) 322 #define WRITE_YDC_DDR_BIST_BIST_PRBS_DATA_SEED_LSB_127_TO_96r(_unit, _pc, _val) \ 323 YDC_DDR_BIST_BIST_REG_WRITE((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_PRBS_DATA_SEED_LSB_127_TO_96, (_val)) 324 #define MODIFY_YDC_DDR_BIST_BIST_PRBS_DATA_SEED_LSB_127_TO_96r(_unit, _pc, _val, _mask) \ 325 YDC_DDR_BIST_BIST_REG_MODIFY((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_PRBS_DATA_SEED_LSB_127_TO_96, (_val), (_mask)) 326 327 /* BIST PRBS Address Seed Register */ 328 #define READ_YDC_DDR_BIST_BIST_PRBS_ADDR_SEEDr(_unit, _pc, _val) \ 329 YDC_DDR_BIST_BIST_REG_READ((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_PRBS_ADDR_SEED, (_val)) 330 #define WRITE_YDC_DDR_BIST_BIST_PRBS_ADDR_SEEDr(_unit, _pc, _val) \ 331 YDC_DDR_BIST_BIST_REG_WRITE((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_PRBS_ADDR_SEED, (_val)) 332 #define MODIFY_YDC_DDR_BIST_BIST_PRBS_ADDR_SEEDr(_unit, _pc, _val, _mask) \ 333 YDC_DDR_BIST_BIST_REG_MODIFY((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_PRBS_ADDR_SEED, (_val), (_mask)) 334 335 /* BIST MPR Stagger Weights Register */ 336 #define READ_YDC_DDR_BIST_BIST_MPR_STAGGER_WEIGHTSr(_unit, _pc, _val) \ 337 YDC_DDR_BIST_BIST_REG_READ((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_MPR_STAGGER_WEIGHTS, (_val)) 338 #define WRITE_YDC_DDR_BIST_BIST_MPR_STAGGER_WEIGHTSr(_unit, _pc, _val) \ 339 YDC_DDR_BIST_BIST_REG_WRITE((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_MPR_STAGGER_WEIGHTS, (_val)) 340 #define MODIFY_YDC_DDR_BIST_BIST_MPR_STAGGER_WEIGHTSr(_unit, _pc, _val, _mask) \ 341 YDC_DDR_BIST_BIST_REG_MODIFY((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_MPR_STAGGER_WEIGHTS, (_val), (_mask)) 342 343 /* BIST MPR Stagger Patterns Register */ 344 #define READ_YDC_DDR_BIST_BIST_MPR_STAGGER_PATTERNSr(_unit, _pc, _val) \ 345 YDC_DDR_BIST_BIST_REG_READ((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_MPR_STAGGER_PATTERNS, (_val)) 346 #define WRITE_YDC_DDR_BIST_BIST_MPR_STAGGER_PATTERNSr(_unit, _pc, _val) \ 347 YDC_DDR_BIST_BIST_REG_WRITE((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_MPR_STAGGER_PATTERNS, (_val)) 348 #define MODIFY_YDC_DDR_BIST_BIST_MPR_STAGGER_PATTERNSr(_unit, _pc, _val, _mask) \ 349 YDC_DDR_BIST_BIST_REG_MODIFY((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_MPR_STAGGER_PATTERNS, (_val), (_mask)) 350 351 /* BIST Pattern Repetition 0 Register */ 352 #define READ_YDC_DDR_BIST_BIST_PATTERN_REPETITION_0r(_unit, _pc, _val) \ 353 YDC_DDR_BIST_BIST_REG_READ((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_PATTERN_REPETITION_0, (_val)) 354 #define WRITE_YDC_DDR_BIST_BIST_PATTERN_REPETITION_0r(_unit, _pc, _val) \ 355 YDC_DDR_BIST_BIST_REG_WRITE((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_PATTERN_REPETITION_0, (_val)) 356 #define MODIFY_YDC_DDR_BIST_BIST_PATTERN_REPETITION_0r(_unit, _pc, _val, _mask) \ 357 YDC_DDR_BIST_BIST_REG_MODIFY((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_PATTERN_REPETITION_0, (_val), (_mask)) 358 359 /* BIST Pattern Repetition 1 Register */ 360 #define READ_YDC_DDR_BIST_BIST_PATTERN_REPETITION_1r(_unit, _pc, _val) \ 361 YDC_DDR_BIST_BIST_REG_READ((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_PATTERN_REPETITION_1, (_val)) 362 #define WRITE_YDC_DDR_BIST_BIST_PATTERN_REPETITION_1r(_unit, _pc, _val) \ 363 YDC_DDR_BIST_BIST_REG_WRITE((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_PATTERN_REPETITION_1, (_val)) 364 #define MODIFY_YDC_DDR_BIST_BIST_PATTERN_REPETITION_1r(_unit, _pc, _val, _mask) \ 365 YDC_DDR_BIST_BIST_REG_MODIFY((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_PATTERN_REPETITION_1, (_val), (_mask)) 366 367 /* BIST Repeat Pattern 1 MSB 31 to 0 Register */ 368 #define READ_YDC_DDR_BIST_BIST_REPEAT_PATTERN_1_MSB_31_TO_0r(_unit, _pc, _val) \ 369 YDC_DDR_BIST_BIST_REG_READ((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_1_MSB_31_TO_0, (_val)) 370 #define WRITE_YDC_DDR_BIST_BIST_REPEAT_PATTERN_1_MSB_31_TO_0r(_unit, _pc, _val) \ 371 YDC_DDR_BIST_BIST_REG_WRITE((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_1_MSB_31_TO_0, (_val)) 372 #define MODIFY_YDC_DDR_BIST_BIST_REPEAT_PATTERN_1_MSB_31_TO_0r(_unit, _pc, _val, _mask) \ 373 YDC_DDR_BIST_BIST_REG_MODIFY((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_1_MSB_31_TO_0, (_val), (_mask)) 374 375 /* BIST Repeat Pattern 1 MSB 63 to 32 Register */ 376 #define READ_YDC_DDR_BIST_BIST_REPEAT_PATTERN_1_MSB_63_TO_32r(_unit, _pc, _val) \ 377 YDC_DDR_BIST_BIST_REG_READ((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_1_MSB_63_TO_32, (_val)) 378 #define WRITE_YDC_DDR_BIST_BIST_REPEAT_PATTERN_1_MSB_63_TO_32r(_unit, _pc, _val) \ 379 YDC_DDR_BIST_BIST_REG_WRITE((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_1_MSB_63_TO_32, (_val)) 380 #define MODIFY_YDC_DDR_BIST_BIST_REPEAT_PATTERN_1_MSB_63_TO_32r(_unit, _pc, _val, _mask) \ 381 YDC_DDR_BIST_BIST_REG_MODIFY((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_1_MSB_63_TO_32, (_val), (_mask)) 382 383 /* BIST Repeat Pattern 1 MSB 95 to 64 Register */ 384 #define READ_YDC_DDR_BIST_BIST_REPEAT_PATTERN_1_MSB_95_TO_64r(_unit, _pc, _val) \ 385 YDC_DDR_BIST_BIST_REG_READ((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_1_MSB_95_TO_64, (_val)) 386 #define WRITE_YDC_DDR_BIST_BIST_REPEAT_PATTERN_1_MSB_95_TO_64r(_unit, _pc, _val) \ 387 YDC_DDR_BIST_BIST_REG_WRITE((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_1_MSB_95_TO_64, (_val)) 388 #define MODIFY_YDC_DDR_BIST_BIST_REPEAT_PATTERN_1_MSB_95_TO_64r(_unit, _pc, _val, _mask) \ 389 YDC_DDR_BIST_BIST_REG_MODIFY((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_1_MSB_95_TO_64, (_val), (_mask)) 390 391 /* BIST Repeat Pattern 1 MSB 127 to 96 Register */ 392 #define READ_YDC_DDR_BIST_BIST_REPEAT_PATTERN_1_MSB_127_TO_96r(_unit, _pc, _val) \ 393 YDC_DDR_BIST_BIST_REG_READ((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_1_MSB_127_TO_96, (_val)) 394 #define WRITE_YDC_DDR_BIST_BIST_REPEAT_PATTERN_1_MSB_127_TO_96r(_unit, _pc, _val) \ 395 YDC_DDR_BIST_BIST_REG_WRITE((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_1_MSB_127_TO_96, (_val)) 396 #define MODIFY_YDC_DDR_BIST_BIST_REPEAT_PATTERN_1_MSB_127_TO_96r(_unit, _pc, _val, _mask) \ 397 YDC_DDR_BIST_BIST_REG_MODIFY((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_1_MSB_127_TO_96, (_val), (_mask)) 398 399 /* BIST Repeat Pattern 1 LSB 31 to 0 Register */ 400 #define READ_YDC_DDR_BIST_BIST_REPEAT_PATTERN_1_LSB_31_TO_0r(_unit, _pc, _val) \ 401 YDC_DDR_BIST_BIST_REG_READ((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_1_LSB_31_TO_0, (_val)) 402 #define WRITE_YDC_DDR_BIST_BIST_REPEAT_PATTERN_1_LSB_31_TO_0r(_unit, _pc, _val) \ 403 YDC_DDR_BIST_BIST_REG_WRITE((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_1_LSB_31_TO_0, (_val)) 404 #define MODIFY_YDC_DDR_BIST_BIST_REPEAT_PATTERN_1_LSB_31_TO_0r(_unit, _pc, _val, _mask) \ 405 YDC_DDR_BIST_BIST_REG_MODIFY((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_1_LSB_31_TO_0, (_val), (_mask)) 406 407 /* BIST Repeat Pattern 1 LSB 63 to 32 Register */ 408 #define READ_YDC_DDR_BIST_BIST_REPEAT_PATTERN_1_LSB_63_TO_32r(_unit, _pc, _val) \ 409 YDC_DDR_BIST_BIST_REG_READ((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_1_LSB_63_TO_32, (_val)) 410 #define WRITE_YDC_DDR_BIST_BIST_REPEAT_PATTERN_1_LSB_63_TO_32r(_unit, _pc, _val) \ 411 YDC_DDR_BIST_BIST_REG_WRITE((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_1_LSB_63_TO_32, (_val)) 412 #define MODIFY_YDC_DDR_BIST_BIST_REPEAT_PATTERN_1_LSB_63_TO_32r(_unit, _pc, _val, _mask) \ 413 YDC_DDR_BIST_BIST_REG_MODIFY((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_1_LSB_63_TO_32, (_val), (_mask)) 414 415 /* BIST Repeat Pattern 1 LSB 95 to 64 Register */ 416 #define READ_YDC_DDR_BIST_BIST_REPEAT_PATTERN_1_LSB_95_TO_64r(_unit, _pc, _val) \ 417 YDC_DDR_BIST_BIST_REG_READ((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_1_LSB_95_TO_64, (_val)) 418 #define WRITE_YDC_DDR_BIST_BIST_REPEAT_PATTERN_1_LSB_95_TO_64r(_unit, _pc, _val) \ 419 YDC_DDR_BIST_BIST_REG_WRITE((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_1_LSB_95_TO_64, (_val)) 420 #define MODIFY_YDC_DDR_BIST_BIST_REPEAT_PATTERN_1_LSB_95_TO_64r(_unit, _pc, _val, _mask) \ 421 YDC_DDR_BIST_BIST_REG_MODIFY((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_1_LSB_95_TO_64, (_val), (_mask)) 422 423 /* BIST Repeat Pattern 1 LSB 127 to 96 Register */ 424 #define READ_YDC_DDR_BIST_BIST_REPEAT_PATTERN_1_LSB_127_TO_96r(_unit, _pc, _val) \ 425 YDC_DDR_BIST_BIST_REG_READ((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_1_LSB_127_TO_96, (_val)) 426 #define WRITE_YDC_DDR_BIST_BIST_REPEAT_PATTERN_1_LSB_127_TO_96r(_unit, _pc, _val) \ 427 YDC_DDR_BIST_BIST_REG_WRITE((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_1_LSB_127_TO_96, (_val)) 428 #define MODIFY_YDC_DDR_BIST_BIST_REPEAT_PATTERN_1_LSB_127_TO_96r(_unit, _pc, _val, _mask) \ 429 YDC_DDR_BIST_BIST_REG_MODIFY((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_1_LSB_127_TO_96, (_val), (_mask)) 430 431 /* BIST Repeat Pattern 2 MSB 31 to 0 Register */ 432 #define READ_YDC_DDR_BIST_BIST_REPEAT_PATTERN_2_MSB_31_TO_0r(_unit, _pc, _val) \ 433 YDC_DDR_BIST_BIST_REG_READ((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_2_MSB_31_TO_0, (_val)) 434 #define WRITE_YDC_DDR_BIST_BIST_REPEAT_PATTERN_2_MSB_31_TO_0r(_unit, _pc, _val) \ 435 YDC_DDR_BIST_BIST_REG_WRITE((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_2_MSB_31_TO_0, (_val)) 436 #define MODIFY_YDC_DDR_BIST_BIST_REPEAT_PATTERN_2_MSB_31_TO_0r(_unit, _pc, _val, _mask) \ 437 YDC_DDR_BIST_BIST_REG_MODIFY((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_2_MSB_31_TO_0, (_val), (_mask)) 438 439 /* BIST Repeat Pattern 2 MSB 63 to 32 Register */ 440 #define READ_YDC_DDR_BIST_BIST_REPEAT_PATTERN_2_MSB_63_TO_32r(_unit, _pc, _val) \ 441 YDC_DDR_BIST_BIST_REG_READ((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_2_MSB_63_TO_32, (_val)) 442 #define WRITE_YDC_DDR_BIST_BIST_REPEAT_PATTERN_2_MSB_63_TO_32r(_unit, _pc, _val) \ 443 YDC_DDR_BIST_BIST_REG_WRITE((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_2_MSB_63_TO_32, (_val)) 444 #define MODIFY_YDC_DDR_BIST_BIST_REPEAT_PATTERN_2_MSB_63_TO_32r(_unit, _pc, _val, _mask) \ 445 YDC_DDR_BIST_BIST_REG_MODIFY((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_2_MSB_63_TO_32, (_val), (_mask)) 446 447 /* BIST Repeat Pattern 2 MSB 95 to 64 Register */ 448 #define READ_YDC_DDR_BIST_BIST_REPEAT_PATTERN_2_MSB_95_TO_64r(_unit, _pc, _val) \ 449 YDC_DDR_BIST_BIST_REG_READ((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_2_MSB_95_TO_64, (_val)) 450 #define WRITE_YDC_DDR_BIST_BIST_REPEAT_PATTERN_2_MSB_95_TO_64r(_unit, _pc, _val) \ 451 YDC_DDR_BIST_BIST_REG_WRITE((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_2_MSB_95_TO_64, (_val)) 452 #define MODIFY_YDC_DDR_BIST_BIST_REPEAT_PATTERN_2_MSB_95_TO_64r(_unit, _pc, _val, _mask) \ 453 YDC_DDR_BIST_BIST_REG_MODIFY((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_2_MSB_95_TO_64, (_val), (_mask)) 454 455 /* BIST Repeat Pattern 2 MSB 127 to 96 Register */ 456 #define READ_YDC_DDR_BIST_BIST_REPEAT_PATTERN_2_MSB_127_TO_96r(_unit, _pc, _val) \ 457 YDC_DDR_BIST_BIST_REG_READ((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_2_MSB_127_TO_96, (_val)) 458 #define WRITE_YDC_DDR_BIST_BIST_REPEAT_PATTERN_2_MSB_127_TO_96r(_unit, _pc, _val) \ 459 YDC_DDR_BIST_BIST_REG_WRITE((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_2_MSB_127_TO_96, (_val)) 460 #define MODIFY_YDC_DDR_BIST_BIST_REPEAT_PATTERN_2_MSB_127_TO_96r(_unit, _pc, _val, _mask) \ 461 YDC_DDR_BIST_BIST_REG_MODIFY((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_2_MSB_127_TO_96, (_val), (_mask)) 462 463 /* BIST Repeat Pattern 2 LSB 31 to 0 Register */ 464 #define READ_YDC_DDR_BIST_BIST_REPEAT_PATTERN_2_LSB_31_TO_0r(_unit, _pc, _val) \ 465 YDC_DDR_BIST_BIST_REG_READ((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_2_LSB_31_TO_0, (_val)) 466 #define WRITE_YDC_DDR_BIST_BIST_REPEAT_PATTERN_2_LSB_31_TO_0r(_unit, _pc, _val) \ 467 YDC_DDR_BIST_BIST_REG_WRITE((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_2_LSB_31_TO_0, (_val)) 468 #define MODIFY_YDC_DDR_BIST_BIST_REPEAT_PATTERN_2_LSB_31_TO_0r(_unit, _pc, _val, _mask) \ 469 YDC_DDR_BIST_BIST_REG_MODIFY((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_2_LSB_31_TO_0, (_val), (_mask)) 470 471 /* BIST Repeat Pattern 2 LSB 63 to 32 Register */ 472 #define READ_YDC_DDR_BIST_BIST_REPEAT_PATTERN_2_LSB_63_TO_32r(_unit, _pc, _val) \ 473 YDC_DDR_BIST_BIST_REG_READ((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_2_LSB_63_TO_32, (_val)) 474 #define WRITE_YDC_DDR_BIST_BIST_REPEAT_PATTERN_2_LSB_63_TO_32r(_unit, _pc, _val) \ 475 YDC_DDR_BIST_BIST_REG_WRITE((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_2_LSB_63_TO_32, (_val)) 476 #define MODIFY_YDC_DDR_BIST_BIST_REPEAT_PATTERN_2_LSB_63_TO_32r(_unit, _pc, _val, _mask) \ 477 YDC_DDR_BIST_BIST_REG_MODIFY((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_2_LSB_63_TO_32, (_val), (_mask)) 478 479 /* BIST Repeat Pattern 2 LSB 95 to 64 Register */ 480 #define READ_YDC_DDR_BIST_BIST_REPEAT_PATTERN_2_LSB_95_TO_64r(_unit, _pc, _val) \ 481 YDC_DDR_BIST_BIST_REG_READ((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_2_LSB_95_TO_64, (_val)) 482 #define WRITE_YDC_DDR_BIST_BIST_REPEAT_PATTERN_2_LSB_95_TO_64r(_unit, _pc, _val) \ 483 YDC_DDR_BIST_BIST_REG_WRITE((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_2_LSB_95_TO_64, (_val)) 484 #define MODIFY_YDC_DDR_BIST_BIST_REPEAT_PATTERN_2_LSB_95_TO_64r(_unit, _pc, _val, _mask) \ 485 YDC_DDR_BIST_BIST_REG_MODIFY((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_2_LSB_95_TO_64, (_val), (_mask)) 486 487 /* BIST Repeat Pattern 2 LSB 127 to 96 Register */ 488 #define READ_YDC_DDR_BIST_BIST_REPEAT_PATTERN_2_LSB_127_TO_96r(_unit, _pc, _val) \ 489 YDC_DDR_BIST_BIST_REG_READ((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_2_LSB_127_TO_96, (_val)) 490 #define WRITE_YDC_DDR_BIST_BIST_REPEAT_PATTERN_2_LSB_127_TO_96r(_unit, _pc, _val) \ 491 YDC_DDR_BIST_BIST_REG_WRITE((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_2_LSB_127_TO_96, (_val)) 492 #define MODIFY_YDC_DDR_BIST_BIST_REPEAT_PATTERN_2_LSB_127_TO_96r(_unit, _pc, _val, _mask) \ 493 YDC_DDR_BIST_BIST_REG_MODIFY((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_2_LSB_127_TO_96, (_val), (_mask)) 494 495 /* BIST Repeat Pattern 3 MSB 31 to 0 Register */ 496 #define READ_YDC_DDR_BIST_BIST_REPEAT_PATTERN_3_MSB_31_TO_0r(_unit, _pc, _val) \ 497 YDC_DDR_BIST_BIST_REG_READ((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_3_MSB_31_TO_0, (_val)) 498 #define WRITE_YDC_DDR_BIST_BIST_REPEAT_PATTERN_3_MSB_31_TO_0r(_unit, _pc, _val) \ 499 YDC_DDR_BIST_BIST_REG_WRITE((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_3_MSB_31_TO_0, (_val)) 500 #define MODIFY_YDC_DDR_BIST_BIST_REPEAT_PATTERN_3_MSB_31_TO_0r(_unit, _pc, _val, _mask) \ 501 YDC_DDR_BIST_BIST_REG_MODIFY((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_3_MSB_31_TO_0, (_val), (_mask)) 502 503 /* BIST Repeat Pattern 3 MSB 63 to 32 Register */ 504 #define READ_YDC_DDR_BIST_BIST_REPEAT_PATTERN_3_MSB_63_TO_32r(_unit, _pc, _val) \ 505 YDC_DDR_BIST_BIST_REG_READ((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_3_MSB_63_TO_32, (_val)) 506 #define WRITE_YDC_DDR_BIST_BIST_REPEAT_PATTERN_3_MSB_63_TO_32r(_unit, _pc, _val) \ 507 YDC_DDR_BIST_BIST_REG_WRITE((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_3_MSB_63_TO_32, (_val)) 508 #define MODIFY_YDC_DDR_BIST_BIST_REPEAT_PATTERN_3_MSB_63_TO_32r(_unit, _pc, _val, _mask) \ 509 YDC_DDR_BIST_BIST_REG_MODIFY((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_3_MSB_63_TO_32, (_val), (_mask)) 510 511 /* BIST Repeat Pattern 3 MSB 95 to 64 Register */ 512 #define READ_YDC_DDR_BIST_BIST_REPEAT_PATTERN_3_MSB_95_TO_64r(_unit, _pc, _val) \ 513 YDC_DDR_BIST_BIST_REG_READ((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_3_MSB_95_TO_64, (_val)) 514 #define WRITE_YDC_DDR_BIST_BIST_REPEAT_PATTERN_3_MSB_95_TO_64r(_unit, _pc, _val) \ 515 YDC_DDR_BIST_BIST_REG_WRITE((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_3_MSB_95_TO_64, (_val)) 516 #define MODIFY_YDC_DDR_BIST_BIST_REPEAT_PATTERN_3_MSB_95_TO_64r(_unit, _pc, _val, _mask) \ 517 YDC_DDR_BIST_BIST_REG_MODIFY((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_3_MSB_95_TO_64, (_val), (_mask)) 518 519 /* BIST Repeat Pattern 3 MSB 127 to 96 Register */ 520 #define READ_YDC_DDR_BIST_BIST_REPEAT_PATTERN_3_MSB_127_TO_96r(_unit, _pc, _val) \ 521 YDC_DDR_BIST_BIST_REG_READ((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_3_MSB_127_TO_96, (_val)) 522 #define WRITE_YDC_DDR_BIST_BIST_REPEAT_PATTERN_3_MSB_127_TO_96r(_unit, _pc, _val) \ 523 YDC_DDR_BIST_BIST_REG_WRITE((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_3_MSB_127_TO_96, (_val)) 524 #define MODIFY_YDC_DDR_BIST_BIST_REPEAT_PATTERN_3_MSB_127_TO_96r(_unit, _pc, _val, _mask) \ 525 YDC_DDR_BIST_BIST_REG_MODIFY((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_3_MSB_127_TO_96, (_val), (_mask)) 526 527 /* BIST Repeat Pattern 3 LSB 31 to 0 Register */ 528 #define READ_YDC_DDR_BIST_BIST_REPEAT_PATTERN_3_LSB_31_TO_0r(_unit, _pc, _val) \ 529 YDC_DDR_BIST_BIST_REG_READ((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_3_LSB_31_TO_0, (_val)) 530 #define WRITE_YDC_DDR_BIST_BIST_REPEAT_PATTERN_3_LSB_31_TO_0r(_unit, _pc, _val) \ 531 YDC_DDR_BIST_BIST_REG_WRITE((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_3_LSB_31_TO_0, (_val)) 532 #define MODIFY_YDC_DDR_BIST_BIST_REPEAT_PATTERN_3_LSB_31_TO_0r(_unit, _pc, _val, _mask) \ 533 YDC_DDR_BIST_BIST_REG_MODIFY((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_3_LSB_31_TO_0, (_val), (_mask)) 534 535 /* BIST Repeat Pattern 3 LSB 63 to 32 Register */ 536 #define READ_YDC_DDR_BIST_BIST_REPEAT_PATTERN_3_LSB_63_TO_32r(_unit, _pc, _val) \ 537 YDC_DDR_BIST_BIST_REG_READ((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_3_LSB_63_TO_32, (_val)) 538 #define WRITE_YDC_DDR_BIST_BIST_REPEAT_PATTERN_3_LSB_63_TO_32r(_unit, _pc, _val) \ 539 YDC_DDR_BIST_BIST_REG_WRITE((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_3_LSB_63_TO_32, (_val)) 540 #define MODIFY_YDC_DDR_BIST_BIST_REPEAT_PATTERN_3_LSB_63_TO_32r(_unit, _pc, _val, _mask) \ 541 YDC_DDR_BIST_BIST_REG_MODIFY((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_3_LSB_63_TO_32, (_val), (_mask)) 542 543 /* BIST Repeat Pattern 3 LSB 95 to 64 Register */ 544 #define READ_YDC_DDR_BIST_BIST_REPEAT_PATTERN_3_LSB_95_TO_64r(_unit, _pc, _val) \ 545 YDC_DDR_BIST_BIST_REG_READ((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_3_LSB_95_TO_64, (_val)) 546 #define WRITE_YDC_DDR_BIST_BIST_REPEAT_PATTERN_3_LSB_95_TO_64r(_unit, _pc, _val) \ 547 YDC_DDR_BIST_BIST_REG_WRITE((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_3_LSB_95_TO_64, (_val)) 548 #define MODIFY_YDC_DDR_BIST_BIST_REPEAT_PATTERN_3_LSB_95_TO_64r(_unit, _pc, _val, _mask) \ 549 YDC_DDR_BIST_BIST_REG_MODIFY((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_3_LSB_95_TO_64, (_val), (_mask)) 550 551 /* BIST Repeat Pattern 3 LSB 127 to 96 Register */ 552 #define READ_YDC_DDR_BIST_BIST_REPEAT_PATTERN_3_LSB_127_TO_96r(_unit, _pc, _val) \ 553 YDC_DDR_BIST_BIST_REG_READ((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_3_LSB_127_TO_96, (_val)) 554 #define WRITE_YDC_DDR_BIST_BIST_REPEAT_PATTERN_3_LSB_127_TO_96r(_unit, _pc, _val) \ 555 YDC_DDR_BIST_BIST_REG_WRITE((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_3_LSB_127_TO_96, (_val)) 556 #define MODIFY_YDC_DDR_BIST_BIST_REPEAT_PATTERN_3_LSB_127_TO_96r(_unit, _pc, _val, _mask) \ 557 YDC_DDR_BIST_BIST_REG_MODIFY((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_3_LSB_127_TO_96, (_val), (_mask)) 558 559 /* BIST Repeat Pattern 4 MSB 31 to 0 Register */ 560 #define READ_YDC_DDR_BIST_BIST_REPEAT_PATTERN_4_MSB_31_TO_0r(_unit, _pc, _val) \ 561 YDC_DDR_BIST_BIST_REG_READ((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_4_MSB_31_TO_0, (_val)) 562 #define WRITE_YDC_DDR_BIST_BIST_REPEAT_PATTERN_4_MSB_31_TO_0r(_unit, _pc, _val) \ 563 YDC_DDR_BIST_BIST_REG_WRITE((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_4_MSB_31_TO_0, (_val)) 564 #define MODIFY_YDC_DDR_BIST_BIST_REPEAT_PATTERN_4_MSB_31_TO_0r(_unit, _pc, _val, _mask) \ 565 YDC_DDR_BIST_BIST_REG_MODIFY((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_4_MSB_31_TO_0, (_val), (_mask)) 566 567 /* BIST Repeat Pattern 4 MSB 63 to 32 Register */ 568 #define READ_YDC_DDR_BIST_BIST_REPEAT_PATTERN_4_MSB_63_TO_32r(_unit, _pc, _val) \ 569 YDC_DDR_BIST_BIST_REG_READ((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_4_MSB_63_TO_32, (_val)) 570 #define WRITE_YDC_DDR_BIST_BIST_REPEAT_PATTERN_4_MSB_63_TO_32r(_unit, _pc, _val) \ 571 YDC_DDR_BIST_BIST_REG_WRITE((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_4_MSB_63_TO_32, (_val)) 572 #define MODIFY_YDC_DDR_BIST_BIST_REPEAT_PATTERN_4_MSB_63_TO_32r(_unit, _pc, _val, _mask) \ 573 YDC_DDR_BIST_BIST_REG_MODIFY((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_4_MSB_63_TO_32, (_val), (_mask)) 574 575 /* BIST Repeat Pattern 4 MSB 95 to 64 Register */ 576 #define READ_YDC_DDR_BIST_BIST_REPEAT_PATTERN_4_MSB_95_TO_64r(_unit, _pc, _val) \ 577 YDC_DDR_BIST_BIST_REG_READ((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_4_MSB_95_TO_64, (_val)) 578 #define WRITE_YDC_DDR_BIST_BIST_REPEAT_PATTERN_4_MSB_95_TO_64r(_unit, _pc, _val) \ 579 YDC_DDR_BIST_BIST_REG_WRITE((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_4_MSB_95_TO_64, (_val)) 580 #define MODIFY_YDC_DDR_BIST_BIST_REPEAT_PATTERN_4_MSB_95_TO_64r(_unit, _pc, _val, _mask) \ 581 YDC_DDR_BIST_BIST_REG_MODIFY((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_4_MSB_95_TO_64, (_val), (_mask)) 582 583 /* BIST Repeat Pattern 4 MSB 127 to 96 Register */ 584 #define READ_YDC_DDR_BIST_BIST_REPEAT_PATTERN_4_MSB_127_TO_96r(_unit, _pc, _val) \ 585 YDC_DDR_BIST_BIST_REG_READ((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_4_MSB_127_TO_96, (_val)) 586 #define WRITE_YDC_DDR_BIST_BIST_REPEAT_PATTERN_4_MSB_127_TO_96r(_unit, _pc, _val) \ 587 YDC_DDR_BIST_BIST_REG_WRITE((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_4_MSB_127_TO_96, (_val)) 588 #define MODIFY_YDC_DDR_BIST_BIST_REPEAT_PATTERN_4_MSB_127_TO_96r(_unit, _pc, _val, _mask) \ 589 YDC_DDR_BIST_BIST_REG_MODIFY((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_4_MSB_127_TO_96, (_val), (_mask)) 590 591 /* BIST Repeat Pattern 4 LSB 31 to 0 Register */ 592 #define READ_YDC_DDR_BIST_BIST_REPEAT_PATTERN_4_LSB_31_TO_0r(_unit, _pc, _val) \ 593 YDC_DDR_BIST_BIST_REG_READ((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_4_LSB_31_TO_0, (_val)) 594 #define WRITE_YDC_DDR_BIST_BIST_REPEAT_PATTERN_4_LSB_31_TO_0r(_unit, _pc, _val) \ 595 YDC_DDR_BIST_BIST_REG_WRITE((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_4_LSB_31_TO_0, (_val)) 596 #define MODIFY_YDC_DDR_BIST_BIST_REPEAT_PATTERN_4_LSB_31_TO_0r(_unit, _pc, _val, _mask) \ 597 YDC_DDR_BIST_BIST_REG_MODIFY((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_4_LSB_31_TO_0, (_val), (_mask)) 598 599 /* BIST Repeat Pattern 4 LSB 63 to 32 Register */ 600 #define READ_YDC_DDR_BIST_BIST_REPEAT_PATTERN_4_LSB_63_TO_32r(_unit, _pc, _val) \ 601 YDC_DDR_BIST_BIST_REG_READ((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_4_LSB_63_TO_32, (_val)) 602 #define WRITE_YDC_DDR_BIST_BIST_REPEAT_PATTERN_4_LSB_63_TO_32r(_unit, _pc, _val) \ 603 YDC_DDR_BIST_BIST_REG_WRITE((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_4_LSB_63_TO_32, (_val)) 604 #define MODIFY_YDC_DDR_BIST_BIST_REPEAT_PATTERN_4_LSB_63_TO_32r(_unit, _pc, _val, _mask) \ 605 YDC_DDR_BIST_BIST_REG_MODIFY((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_4_LSB_63_TO_32, (_val), (_mask)) 606 607 /* BIST Repeat Pattern 4 LSB 95 to 64 Register */ 608 #define READ_YDC_DDR_BIST_BIST_REPEAT_PATTERN_4_LSB_95_TO_64r(_unit, _pc, _val) \ 609 YDC_DDR_BIST_BIST_REG_READ((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_4_LSB_95_TO_64, (_val)) 610 #define WRITE_YDC_DDR_BIST_BIST_REPEAT_PATTERN_4_LSB_95_TO_64r(_unit, _pc, _val) \ 611 YDC_DDR_BIST_BIST_REG_WRITE((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_4_LSB_95_TO_64, (_val)) 612 #define MODIFY_YDC_DDR_BIST_BIST_REPEAT_PATTERN_4_LSB_95_TO_64r(_unit, _pc, _val, _mask) \ 613 YDC_DDR_BIST_BIST_REG_MODIFY((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_4_LSB_95_TO_64, (_val), (_mask)) 614 615 /* BIST Repeat Pattern 4 LSB 127 to 96 Register */ 616 #define READ_YDC_DDR_BIST_BIST_REPEAT_PATTERN_4_LSB_127_TO_96r(_unit, _pc, _val) \ 617 YDC_DDR_BIST_BIST_REG_READ((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_4_LSB_127_TO_96, (_val)) 618 #define WRITE_YDC_DDR_BIST_BIST_REPEAT_PATTERN_4_LSB_127_TO_96r(_unit, _pc, _val) \ 619 YDC_DDR_BIST_BIST_REG_WRITE((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_4_LSB_127_TO_96, (_val)) 620 #define MODIFY_YDC_DDR_BIST_BIST_REPEAT_PATTERN_4_LSB_127_TO_96r(_unit, _pc, _val, _mask) \ 621 YDC_DDR_BIST_BIST_REG_MODIFY((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_4_LSB_127_TO_96, (_val), (_mask)) 622 623 /* BIST Repeat Pattern 5 MSB 31 to 0 Register */ 624 #define READ_YDC_DDR_BIST_BIST_REPEAT_PATTERN_5_MSB_31_TO_0r(_unit, _pc, _val) \ 625 YDC_DDR_BIST_BIST_REG_READ((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_5_MSB_31_TO_0, (_val)) 626 #define WRITE_YDC_DDR_BIST_BIST_REPEAT_PATTERN_5_MSB_31_TO_0r(_unit, _pc, _val) \ 627 YDC_DDR_BIST_BIST_REG_WRITE((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_5_MSB_31_TO_0, (_val)) 628 #define MODIFY_YDC_DDR_BIST_BIST_REPEAT_PATTERN_5_MSB_31_TO_0r(_unit, _pc, _val, _mask) \ 629 YDC_DDR_BIST_BIST_REG_MODIFY((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_5_MSB_31_TO_0, (_val), (_mask)) 630 631 /* BIST Repeat Pattern 5 MSB 63 to 32 Register */ 632 #define READ_YDC_DDR_BIST_BIST_REPEAT_PATTERN_5_MSB_63_TO_32r(_unit, _pc, _val) \ 633 YDC_DDR_BIST_BIST_REG_READ((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_5_MSB_63_TO_32, (_val)) 634 #define WRITE_YDC_DDR_BIST_BIST_REPEAT_PATTERN_5_MSB_63_TO_32r(_unit, _pc, _val) \ 635 YDC_DDR_BIST_BIST_REG_WRITE((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_5_MSB_63_TO_32, (_val)) 636 #define MODIFY_YDC_DDR_BIST_BIST_REPEAT_PATTERN_5_MSB_63_TO_32r(_unit, _pc, _val, _mask) \ 637 YDC_DDR_BIST_BIST_REG_MODIFY((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_5_MSB_63_TO_32, (_val), (_mask)) 638 639 /* BIST Repeat Pattern 5 MSB 95 to 64 Register */ 640 #define READ_YDC_DDR_BIST_BIST_REPEAT_PATTERN_5_MSB_95_TO_64r(_unit, _pc, _val) \ 641 YDC_DDR_BIST_BIST_REG_READ((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_5_MSB_95_TO_64, (_val)) 642 #define WRITE_YDC_DDR_BIST_BIST_REPEAT_PATTERN_5_MSB_95_TO_64r(_unit, _pc, _val) \ 643 YDC_DDR_BIST_BIST_REG_WRITE((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_5_MSB_95_TO_64, (_val)) 644 #define MODIFY_YDC_DDR_BIST_BIST_REPEAT_PATTERN_5_MSB_95_TO_64r(_unit, _pc, _val, _mask) \ 645 YDC_DDR_BIST_BIST_REG_MODIFY((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_5_MSB_95_TO_64, (_val), (_mask)) 646 647 /* BIST Repeat Pattern 5 MSB 127 to 96 Register */ 648 #define READ_YDC_DDR_BIST_BIST_REPEAT_PATTERN_5_MSB_127_TO_96r(_unit, _pc, _val) \ 649 YDC_DDR_BIST_BIST_REG_READ((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_5_MSB_127_TO_96, (_val)) 650 #define WRITE_YDC_DDR_BIST_BIST_REPEAT_PATTERN_5_MSB_127_TO_96r(_unit, _pc, _val) \ 651 YDC_DDR_BIST_BIST_REG_WRITE((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_5_MSB_127_TO_96, (_val)) 652 #define MODIFY_YDC_DDR_BIST_BIST_REPEAT_PATTERN_5_MSB_127_TO_96r(_unit, _pc, _val, _mask) \ 653 YDC_DDR_BIST_BIST_REG_MODIFY((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_5_MSB_127_TO_96, (_val), (_mask)) 654 655 /* BIST Repeat Pattern 5 LSB 31 to 0 Register */ 656 #define READ_YDC_DDR_BIST_BIST_REPEAT_PATTERN_5_LSB_31_TO_0r(_unit, _pc, _val) \ 657 YDC_DDR_BIST_BIST_REG_READ((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_5_LSB_31_TO_0, (_val)) 658 #define WRITE_YDC_DDR_BIST_BIST_REPEAT_PATTERN_5_LSB_31_TO_0r(_unit, _pc, _val) \ 659 YDC_DDR_BIST_BIST_REG_WRITE((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_5_LSB_31_TO_0, (_val)) 660 #define MODIFY_YDC_DDR_BIST_BIST_REPEAT_PATTERN_5_LSB_31_TO_0r(_unit, _pc, _val, _mask) \ 661 YDC_DDR_BIST_BIST_REG_MODIFY((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_5_LSB_31_TO_0, (_val), (_mask)) 662 663 /* BIST Repeat Pattern 5 LSB 63 to 32 Register */ 664 #define READ_YDC_DDR_BIST_BIST_REPEAT_PATTERN_5_LSB_63_TO_32r(_unit, _pc, _val) \ 665 YDC_DDR_BIST_BIST_REG_READ((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_5_LSB_63_TO_32, (_val)) 666 #define WRITE_YDC_DDR_BIST_BIST_REPEAT_PATTERN_5_LSB_63_TO_32r(_unit, _pc, _val) \ 667 YDC_DDR_BIST_BIST_REG_WRITE((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_5_LSB_63_TO_32, (_val)) 668 #define MODIFY_YDC_DDR_BIST_BIST_REPEAT_PATTERN_5_LSB_63_TO_32r(_unit, _pc, _val, _mask) \ 669 YDC_DDR_BIST_BIST_REG_MODIFY((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_5_LSB_63_TO_32, (_val), (_mask)) 670 671 /* BIST Repeat Pattern 5 LSB 95 to 64 Register */ 672 #define READ_YDC_DDR_BIST_BIST_REPEAT_PATTERN_5_LSB_95_TO_64r(_unit, _pc, _val) \ 673 YDC_DDR_BIST_BIST_REG_READ((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_5_LSB_95_TO_64, (_val)) 674 #define WRITE_YDC_DDR_BIST_BIST_REPEAT_PATTERN_5_LSB_95_TO_64r(_unit, _pc, _val) \ 675 YDC_DDR_BIST_BIST_REG_WRITE((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_5_LSB_95_TO_64, (_val)) 676 #define MODIFY_YDC_DDR_BIST_BIST_REPEAT_PATTERN_5_LSB_95_TO_64r(_unit, _pc, _val, _mask) \ 677 YDC_DDR_BIST_BIST_REG_MODIFY((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_5_LSB_95_TO_64, (_val), (_mask)) 678 679 /* BIST Repeat Pattern 5 LSB 127 to 96 Register */ 680 #define READ_YDC_DDR_BIST_BIST_REPEAT_PATTERN_5_LSB_127_TO_96r(_unit, _pc, _val) \ 681 YDC_DDR_BIST_BIST_REG_READ((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_5_LSB_127_TO_96, (_val)) 682 #define WRITE_YDC_DDR_BIST_BIST_REPEAT_PATTERN_5_LSB_127_TO_96r(_unit, _pc, _val) \ 683 YDC_DDR_BIST_BIST_REG_WRITE((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_5_LSB_127_TO_96, (_val)) 684 #define MODIFY_YDC_DDR_BIST_BIST_REPEAT_PATTERN_5_LSB_127_TO_96r(_unit, _pc, _val, _mask) \ 685 YDC_DDR_BIST_BIST_REG_MODIFY((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_5_LSB_127_TO_96, (_val), (_mask)) 686 687 /* BIST Repeat Pattern 6 MSB 31 to 0 Register */ 688 #define READ_YDC_DDR_BIST_BIST_REPEAT_PATTERN_6_MSB_31_TO_0r(_unit, _pc, _val) \ 689 YDC_DDR_BIST_BIST_REG_READ((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_6_MSB_31_TO_0, (_val)) 690 #define WRITE_YDC_DDR_BIST_BIST_REPEAT_PATTERN_6_MSB_31_TO_0r(_unit, _pc, _val) \ 691 YDC_DDR_BIST_BIST_REG_WRITE((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_6_MSB_31_TO_0, (_val)) 692 #define MODIFY_YDC_DDR_BIST_BIST_REPEAT_PATTERN_6_MSB_31_TO_0r(_unit, _pc, _val, _mask) \ 693 YDC_DDR_BIST_BIST_REG_MODIFY((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_6_MSB_31_TO_0, (_val), (_mask)) 694 695 /* BIST Repeat Pattern 6 MSB 63 to 32 Register */ 696 #define READ_YDC_DDR_BIST_BIST_REPEAT_PATTERN_6_MSB_63_TO_32r(_unit, _pc, _val) \ 697 YDC_DDR_BIST_BIST_REG_READ((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_6_MSB_63_TO_32, (_val)) 698 #define WRITE_YDC_DDR_BIST_BIST_REPEAT_PATTERN_6_MSB_63_TO_32r(_unit, _pc, _val) \ 699 YDC_DDR_BIST_BIST_REG_WRITE((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_6_MSB_63_TO_32, (_val)) 700 #define MODIFY_YDC_DDR_BIST_BIST_REPEAT_PATTERN_6_MSB_63_TO_32r(_unit, _pc, _val, _mask) \ 701 YDC_DDR_BIST_BIST_REG_MODIFY((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_6_MSB_63_TO_32, (_val), (_mask)) 702 703 /* BIST Repeat Pattern 6 MSB 95 to 64 Register */ 704 #define READ_YDC_DDR_BIST_BIST_REPEAT_PATTERN_6_MSB_95_TO_64r(_unit, _pc, _val) \ 705 YDC_DDR_BIST_BIST_REG_READ((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_6_MSB_95_TO_64, (_val)) 706 #define WRITE_YDC_DDR_BIST_BIST_REPEAT_PATTERN_6_MSB_95_TO_64r(_unit, _pc, _val) \ 707 YDC_DDR_BIST_BIST_REG_WRITE((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_6_MSB_95_TO_64, (_val)) 708 #define MODIFY_YDC_DDR_BIST_BIST_REPEAT_PATTERN_6_MSB_95_TO_64r(_unit, _pc, _val, _mask) \ 709 YDC_DDR_BIST_BIST_REG_MODIFY((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_6_MSB_95_TO_64, (_val), (_mask)) 710 711 /* BIST Repeat Pattern 6 MSB 127 to 96 Register */ 712 #define READ_YDC_DDR_BIST_BIST_REPEAT_PATTERN_6_MSB_127_TO_96r(_unit, _pc, _val) \ 713 YDC_DDR_BIST_BIST_REG_READ((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_6_MSB_127_TO_96, (_val)) 714 #define WRITE_YDC_DDR_BIST_BIST_REPEAT_PATTERN_6_MSB_127_TO_96r(_unit, _pc, _val) \ 715 YDC_DDR_BIST_BIST_REG_WRITE((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_6_MSB_127_TO_96, (_val)) 716 #define MODIFY_YDC_DDR_BIST_BIST_REPEAT_PATTERN_6_MSB_127_TO_96r(_unit, _pc, _val, _mask) \ 717 YDC_DDR_BIST_BIST_REG_MODIFY((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_6_MSB_127_TO_96, (_val), (_mask)) 718 719 /* BIST Repeat Pattern 6 LSB 31 to 0 Register */ 720 #define READ_YDC_DDR_BIST_BIST_REPEAT_PATTERN_6_LSB_31_TO_0r(_unit, _pc, _val) \ 721 YDC_DDR_BIST_BIST_REG_READ((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_6_LSB_31_TO_0, (_val)) 722 #define WRITE_YDC_DDR_BIST_BIST_REPEAT_PATTERN_6_LSB_31_TO_0r(_unit, _pc, _val) \ 723 YDC_DDR_BIST_BIST_REG_WRITE((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_6_LSB_31_TO_0, (_val)) 724 #define MODIFY_YDC_DDR_BIST_BIST_REPEAT_PATTERN_6_LSB_31_TO_0r(_unit, _pc, _val, _mask) \ 725 YDC_DDR_BIST_BIST_REG_MODIFY((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_6_LSB_31_TO_0, (_val), (_mask)) 726 727 /* BIST Repeat Pattern 6 LSB 63 to 32 Register */ 728 #define READ_YDC_DDR_BIST_BIST_REPEAT_PATTERN_6_LSB_63_TO_32r(_unit, _pc, _val) \ 729 YDC_DDR_BIST_BIST_REG_READ((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_6_LSB_63_TO_32, (_val)) 730 #define WRITE_YDC_DDR_BIST_BIST_REPEAT_PATTERN_6_LSB_63_TO_32r(_unit, _pc, _val) \ 731 YDC_DDR_BIST_BIST_REG_WRITE((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_6_LSB_63_TO_32, (_val)) 732 #define MODIFY_YDC_DDR_BIST_BIST_REPEAT_PATTERN_6_LSB_63_TO_32r(_unit, _pc, _val, _mask) \ 733 YDC_DDR_BIST_BIST_REG_MODIFY((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_6_LSB_63_TO_32, (_val), (_mask)) 734 735 /* BIST Repeat Pattern 6 LSB 95 to 64 Register */ 736 #define READ_YDC_DDR_BIST_BIST_REPEAT_PATTERN_6_LSB_95_TO_64r(_unit, _pc, _val) \ 737 YDC_DDR_BIST_BIST_REG_READ((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_6_LSB_95_TO_64, (_val)) 738 #define WRITE_YDC_DDR_BIST_BIST_REPEAT_PATTERN_6_LSB_95_TO_64r(_unit, _pc, _val) \ 739 YDC_DDR_BIST_BIST_REG_WRITE((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_6_LSB_95_TO_64, (_val)) 740 #define MODIFY_YDC_DDR_BIST_BIST_REPEAT_PATTERN_6_LSB_95_TO_64r(_unit, _pc, _val, _mask) \ 741 YDC_DDR_BIST_BIST_REG_MODIFY((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_6_LSB_95_TO_64, (_val), (_mask)) 742 743 /* BIST Repeat Pattern 6 LSB 127 to 96 Register */ 744 #define READ_YDC_DDR_BIST_BIST_REPEAT_PATTERN_6_LSB_127_TO_96r(_unit, _pc, _val) \ 745 YDC_DDR_BIST_BIST_REG_READ((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_6_LSB_127_TO_96, (_val)) 746 #define WRITE_YDC_DDR_BIST_BIST_REPEAT_PATTERN_6_LSB_127_TO_96r(_unit, _pc, _val) \ 747 YDC_DDR_BIST_BIST_REG_WRITE((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_6_LSB_127_TO_96, (_val)) 748 #define MODIFY_YDC_DDR_BIST_BIST_REPEAT_PATTERN_6_LSB_127_TO_96r(_unit, _pc, _val, _mask) \ 749 YDC_DDR_BIST_BIST_REG_MODIFY((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_6_LSB_127_TO_96, (_val), (_mask)) 750 751 /* BIST Repeat Pattern 7 MSB 31 to 0 Register */ 752 #define READ_YDC_DDR_BIST_BIST_REPEAT_PATTERN_7_MSB_31_TO_0r(_unit, _pc, _val) \ 753 YDC_DDR_BIST_BIST_REG_READ((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_7_MSB_31_TO_0, (_val)) 754 #define WRITE_YDC_DDR_BIST_BIST_REPEAT_PATTERN_7_MSB_31_TO_0r(_unit, _pc, _val) \ 755 YDC_DDR_BIST_BIST_REG_WRITE((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_7_MSB_31_TO_0, (_val)) 756 #define MODIFY_YDC_DDR_BIST_BIST_REPEAT_PATTERN_7_MSB_31_TO_0r(_unit, _pc, _val, _mask) \ 757 YDC_DDR_BIST_BIST_REG_MODIFY((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_7_MSB_31_TO_0, (_val), (_mask)) 758 759 /* BIST Repeat Pattern 7 MSB 63 to 32 Register */ 760 #define READ_YDC_DDR_BIST_BIST_REPEAT_PATTERN_7_MSB_63_TO_32r(_unit, _pc, _val) \ 761 YDC_DDR_BIST_BIST_REG_READ((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_7_MSB_63_TO_32, (_val)) 762 #define WRITE_YDC_DDR_BIST_BIST_REPEAT_PATTERN_7_MSB_63_TO_32r(_unit, _pc, _val) \ 763 YDC_DDR_BIST_BIST_REG_WRITE((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_7_MSB_63_TO_32, (_val)) 764 #define MODIFY_YDC_DDR_BIST_BIST_REPEAT_PATTERN_7_MSB_63_TO_32r(_unit, _pc, _val, _mask) \ 765 YDC_DDR_BIST_BIST_REG_MODIFY((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_7_MSB_63_TO_32, (_val), (_mask)) 766 767 /* BIST Repeat Pattern 7 MSB 95 to 64 Register */ 768 #define READ_YDC_DDR_BIST_BIST_REPEAT_PATTERN_7_MSB_95_TO_64r(_unit, _pc, _val) \ 769 YDC_DDR_BIST_BIST_REG_READ((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_7_MSB_95_TO_64, (_val)) 770 #define WRITE_YDC_DDR_BIST_BIST_REPEAT_PATTERN_7_MSB_95_TO_64r(_unit, _pc, _val) \ 771 YDC_DDR_BIST_BIST_REG_WRITE((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_7_MSB_95_TO_64, (_val)) 772 #define MODIFY_YDC_DDR_BIST_BIST_REPEAT_PATTERN_7_MSB_95_TO_64r(_unit, _pc, _val, _mask) \ 773 YDC_DDR_BIST_BIST_REG_MODIFY((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_7_MSB_95_TO_64, (_val), (_mask)) 774 775 /* BIST Repeat Pattern 7 MSB 127 to 96 Register */ 776 #define READ_YDC_DDR_BIST_BIST_REPEAT_PATTERN_7_MSB_127_TO_96r(_unit, _pc, _val) \ 777 YDC_DDR_BIST_BIST_REG_READ((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_7_MSB_127_TO_96, (_val)) 778 #define WRITE_YDC_DDR_BIST_BIST_REPEAT_PATTERN_7_MSB_127_TO_96r(_unit, _pc, _val) \ 779 YDC_DDR_BIST_BIST_REG_WRITE((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_7_MSB_127_TO_96, (_val)) 780 #define MODIFY_YDC_DDR_BIST_BIST_REPEAT_PATTERN_7_MSB_127_TO_96r(_unit, _pc, _val, _mask) \ 781 YDC_DDR_BIST_BIST_REG_MODIFY((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_7_MSB_127_TO_96, (_val), (_mask)) 782 783 /* BIST Repeat Pattern 7 LSB 31 to 0 Register */ 784 #define READ_YDC_DDR_BIST_BIST_REPEAT_PATTERN_7_LSB_31_TO_0r(_unit, _pc, _val) \ 785 YDC_DDR_BIST_BIST_REG_READ((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_7_LSB_31_TO_0, (_val)) 786 #define WRITE_YDC_DDR_BIST_BIST_REPEAT_PATTERN_7_LSB_31_TO_0r(_unit, _pc, _val) \ 787 YDC_DDR_BIST_BIST_REG_WRITE((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_7_LSB_31_TO_0, (_val)) 788 #define MODIFY_YDC_DDR_BIST_BIST_REPEAT_PATTERN_7_LSB_31_TO_0r(_unit, _pc, _val, _mask) \ 789 YDC_DDR_BIST_BIST_REG_MODIFY((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_7_LSB_31_TO_0, (_val), (_mask)) 790 791 /* BIST Repeat Pattern 7 LSB 63 to 32 Register */ 792 #define READ_YDC_DDR_BIST_BIST_REPEAT_PATTERN_7_LSB_63_TO_32r(_unit, _pc, _val) \ 793 YDC_DDR_BIST_BIST_REG_READ((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_7_LSB_63_TO_32, (_val)) 794 #define WRITE_YDC_DDR_BIST_BIST_REPEAT_PATTERN_7_LSB_63_TO_32r(_unit, _pc, _val) \ 795 YDC_DDR_BIST_BIST_REG_WRITE((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_7_LSB_63_TO_32, (_val)) 796 #define MODIFY_YDC_DDR_BIST_BIST_REPEAT_PATTERN_7_LSB_63_TO_32r(_unit, _pc, _val, _mask) \ 797 YDC_DDR_BIST_BIST_REG_MODIFY((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_7_LSB_63_TO_32, (_val), (_mask)) 798 799 /* BIST Repeat Pattern 7 LSB 95 to 64 Register */ 800 #define READ_YDC_DDR_BIST_BIST_REPEAT_PATTERN_7_LSB_95_TO_64r(_unit, _pc, _val) \ 801 YDC_DDR_BIST_BIST_REG_READ((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_7_LSB_95_TO_64, (_val)) 802 #define WRITE_YDC_DDR_BIST_BIST_REPEAT_PATTERN_7_LSB_95_TO_64r(_unit, _pc, _val) \ 803 YDC_DDR_BIST_BIST_REG_WRITE((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_7_LSB_95_TO_64, (_val)) 804 #define MODIFY_YDC_DDR_BIST_BIST_REPEAT_PATTERN_7_LSB_95_TO_64r(_unit, _pc, _val, _mask) \ 805 YDC_DDR_BIST_BIST_REG_MODIFY((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_7_LSB_95_TO_64, (_val), (_mask)) 806 807 /* BIST Repeat Pattern 7 LSB 127 to 96 Register */ 808 #define READ_YDC_DDR_BIST_BIST_REPEAT_PATTERN_7_LSB_127_TO_96r(_unit, _pc, _val) \ 809 YDC_DDR_BIST_BIST_REG_READ((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_7_LSB_127_TO_96, (_val)) 810 #define WRITE_YDC_DDR_BIST_BIST_REPEAT_PATTERN_7_LSB_127_TO_96r(_unit, _pc, _val) \ 811 YDC_DDR_BIST_BIST_REG_WRITE((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_7_LSB_127_TO_96, (_val)) 812 #define MODIFY_YDC_DDR_BIST_BIST_REPEAT_PATTERN_7_LSB_127_TO_96r(_unit, _pc, _val, _mask) \ 813 YDC_DDR_BIST_BIST_REG_MODIFY((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_REPEAT_PATTERN_7_LSB_127_TO_96, (_val), (_mask)) 814 815 /* BIST Rate Limiter Register */ 816 #define READ_YDC_DDR_BIST_BIST_RATE_LIMITERr(_unit, _pc, _val) \ 817 YDC_DDR_BIST_BIST_REG_READ((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_RATE_LIMITER, (_val)) 818 #define WRITE_YDC_DDR_BIST_BIST_RATE_LIMITERr(_unit, _pc, _val) \ 819 YDC_DDR_BIST_BIST_REG_WRITE((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_RATE_LIMITER, (_val)) 820 #define MODIFY_YDC_DDR_BIST_BIST_RATE_LIMITERr(_unit, _pc, _val, _mask) \ 821 YDC_DDR_BIST_BIST_REG_MODIFY((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_RATE_LIMITER, (_val), (_mask)) 822 823 /* BIST Number of Actions Register */ 824 #define READ_YDC_DDR_BIST_BIST_NUMBER_OF_ACTIONSr(_unit, _pc, _val) \ 825 YDC_DDR_BIST_BIST_REG_READ((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_NUMBER_OF_ACTIONS, (_val)) 826 #define WRITE_YDC_DDR_BIST_BIST_NUMBER_OF_ACTIONSr(_unit, _pc, _val) \ 827 YDC_DDR_BIST_BIST_REG_WRITE((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_NUMBER_OF_ACTIONS, (_val)) 828 #define MODIFY_YDC_DDR_BIST_BIST_NUMBER_OF_ACTIONSr(_unit, _pc, _val, _mask) \ 829 YDC_DDR_BIST_BIST_REG_MODIFY((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_NUMBER_OF_ACTIONS, (_val), (_mask)) 830 831 /* BIST Start Address Register */ 832 #define READ_YDC_DDR_BIST_BIST_START_ADDRESSr(_unit, _pc, _val) \ 833 YDC_DDR_BIST_BIST_REG_READ((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_START_ADDRESS, (_val)) 834 #define WRITE_YDC_DDR_BIST_BIST_START_ADDRESSr(_unit, _pc, _val) \ 835 YDC_DDR_BIST_BIST_REG_WRITE((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_START_ADDRESS, (_val)) 836 #define MODIFY_YDC_DDR_BIST_BIST_START_ADDRESSr(_unit, _pc, _val, _mask) \ 837 YDC_DDR_BIST_BIST_REG_MODIFY((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_START_ADDRESS, (_val), (_mask)) 838 839 /* BIST End Address Register */ 840 #define READ_YDC_DDR_BIST_BIST_END_ADDRESSr(_unit, _pc, _val) \ 841 YDC_DDR_BIST_BIST_REG_READ((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_END_ADDRESS, (_val)) 842 #define WRITE_YDC_DDR_BIST_BIST_END_ADDRESSr(_unit, _pc, _val) \ 843 YDC_DDR_BIST_BIST_REG_WRITE((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_END_ADDRESS, (_val)) 844 #define MODIFY_YDC_DDR_BIST_BIST_END_ADDRESSr(_unit, _pc, _val, _mask) \ 845 YDC_DDR_BIST_BIST_REG_MODIFY((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_END_ADDRESS, (_val), (_mask)) 846 847 /* BIST Single Bit Mask Register */ 848 #define READ_YDC_DDR_BIST_BIST_SINGLE_BIT_MASKr(_unit, _pc, _val) \ 849 YDC_DDR_BIST_BIST_REG_READ((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_SINGLE_BIT_MASK, (_val)) 850 #define WRITE_YDC_DDR_BIST_BIST_SINGLE_BIT_MASKr(_unit, _pc, _val) \ 851 YDC_DDR_BIST_BIST_REG_WRITE((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_SINGLE_BIT_MASK, (_val)) 852 #define MODIFY_YDC_DDR_BIST_BIST_SINGLE_BIT_MASKr(_unit, _pc, _val, _mask) \ 853 YDC_DDR_BIST_BIST_REG_MODIFY((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_SINGLE_BIT_MASK, (_val), (_mask)) 854 855 /* BIST Pattern Word 7 Register */ 856 #define READ_YDC_DDR_BIST_BIST_PATTERN_WORD_7r(_unit, _pc, _val) \ 857 YDC_DDR_BIST_BIST_REG_READ((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_PATTERN_WORD_7, (_val)) 858 #define WRITE_YDC_DDR_BIST_BIST_PATTERN_WORD_7r(_unit, _pc, _val) \ 859 YDC_DDR_BIST_BIST_REG_WRITE((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_PATTERN_WORD_7, (_val)) 860 #define MODIFY_YDC_DDR_BIST_BIST_PATTERN_WORD_7r(_unit, _pc, _val, _mask) \ 861 YDC_DDR_BIST_BIST_REG_MODIFY((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_PATTERN_WORD_7, (_val), (_mask)) 862 863 /* BIST Pattern Word 6 Register */ 864 #define READ_YDC_DDR_BIST_BIST_PATTERN_WORD_6r(_unit, _pc, _val) \ 865 YDC_DDR_BIST_BIST_REG_READ((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_PATTERN_WORD_6, (_val)) 866 #define WRITE_YDC_DDR_BIST_BIST_PATTERN_WORD_6r(_unit, _pc, _val) \ 867 YDC_DDR_BIST_BIST_REG_WRITE((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_PATTERN_WORD_6, (_val)) 868 #define MODIFY_YDC_DDR_BIST_BIST_PATTERN_WORD_6r(_unit, _pc, _val, _mask) \ 869 YDC_DDR_BIST_BIST_REG_MODIFY((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_PATTERN_WORD_6, (_val), (_mask)) 870 871 /* BIST Pattern Word 5 Register */ 872 #define READ_YDC_DDR_BIST_BIST_PATTERN_WORD_5r(_unit, _pc, _val) \ 873 YDC_DDR_BIST_BIST_REG_READ((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_PATTERN_WORD_5, (_val)) 874 #define WRITE_YDC_DDR_BIST_BIST_PATTERN_WORD_5r(_unit, _pc, _val) \ 875 YDC_DDR_BIST_BIST_REG_WRITE((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_PATTERN_WORD_5, (_val)) 876 #define MODIFY_YDC_DDR_BIST_BIST_PATTERN_WORD_5r(_unit, _pc, _val, _mask) \ 877 YDC_DDR_BIST_BIST_REG_MODIFY((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_PATTERN_WORD_5, (_val), (_mask)) 878 879 /* BIST Pattern Word 4 Register */ 880 #define READ_YDC_DDR_BIST_BIST_PATTERN_WORD_4r(_unit, _pc, _val) \ 881 YDC_DDR_BIST_BIST_REG_READ((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_PATTERN_WORD_4, (_val)) 882 #define WRITE_YDC_DDR_BIST_BIST_PATTERN_WORD_4r(_unit, _pc, _val) \ 883 YDC_DDR_BIST_BIST_REG_WRITE((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_PATTERN_WORD_4, (_val)) 884 #define MODIFY_YDC_DDR_BIST_BIST_PATTERN_WORD_4r(_unit, _pc, _val, _mask) \ 885 YDC_DDR_BIST_BIST_REG_MODIFY((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_PATTERN_WORD_4, (_val), (_mask)) 886 887 /* BIST Pattern Word 3 Register */ 888 #define READ_YDC_DDR_BIST_BIST_PATTERN_WORD_3r(_unit, _pc, _val) \ 889 YDC_DDR_BIST_BIST_REG_READ((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_PATTERN_WORD_3, (_val)) 890 #define WRITE_YDC_DDR_BIST_BIST_PATTERN_WORD_3r(_unit, _pc, _val) \ 891 YDC_DDR_BIST_BIST_REG_WRITE((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_PATTERN_WORD_3, (_val)) 892 #define MODIFY_YDC_DDR_BIST_BIST_PATTERN_WORD_3r(_unit, _pc, _val, _mask) \ 893 YDC_DDR_BIST_BIST_REG_MODIFY((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_PATTERN_WORD_3, (_val), (_mask)) 894 895 /* BIST Pattern Word 2 Register */ 896 #define READ_YDC_DDR_BIST_BIST_PATTERN_WORD_2r(_unit, _pc, _val) \ 897 YDC_DDR_BIST_BIST_REG_READ((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_PATTERN_WORD_2, (_val)) 898 #define WRITE_YDC_DDR_BIST_BIST_PATTERN_WORD_2r(_unit, _pc, _val) \ 899 YDC_DDR_BIST_BIST_REG_WRITE((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_PATTERN_WORD_2, (_val)) 900 #define MODIFY_YDC_DDR_BIST_BIST_PATTERN_WORD_2r(_unit, _pc, _val, _mask) \ 901 YDC_DDR_BIST_BIST_REG_MODIFY((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_PATTERN_WORD_2, (_val), (_mask)) 902 903 /* BIST Pattern Word 1 Register */ 904 #define READ_YDC_DDR_BIST_BIST_PATTERN_WORD_1r(_unit, _pc, _val) \ 905 YDC_DDR_BIST_BIST_REG_READ((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_PATTERN_WORD_1, (_val)) 906 #define WRITE_YDC_DDR_BIST_BIST_PATTERN_WORD_1r(_unit, _pc, _val) \ 907 YDC_DDR_BIST_BIST_REG_WRITE((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_PATTERN_WORD_1, (_val)) 908 #define MODIFY_YDC_DDR_BIST_BIST_PATTERN_WORD_1r(_unit, _pc, _val, _mask) \ 909 YDC_DDR_BIST_BIST_REG_MODIFY((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_PATTERN_WORD_1, (_val), (_mask)) 910 911 /* BIST Pattern Word 0 Register */ 912 #define READ_YDC_DDR_BIST_BIST_PATTERN_WORD_0r(_unit, _pc, _val) \ 913 YDC_DDR_BIST_BIST_REG_READ((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_PATTERN_WORD_0, (_val)) 914 #define WRITE_YDC_DDR_BIST_BIST_PATTERN_WORD_0r(_unit, _pc, _val) \ 915 YDC_DDR_BIST_BIST_REG_WRITE((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_PATTERN_WORD_0, (_val)) 916 #define MODIFY_YDC_DDR_BIST_BIST_PATTERN_WORD_0r(_unit, _pc, _val, _mask) \ 917 YDC_DDR_BIST_BIST_REG_MODIFY((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_PATTERN_WORD_0, (_val), (_mask)) 918 919 /* BIST Full Mask Word 7 Register */ 920 #define READ_YDC_DDR_BIST_BIST_FULL_MASK_WORD_7r(_unit, _pc, _val) \ 921 YDC_DDR_BIST_BIST_REG_READ((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_FULL_MASK_WORD_7, (_val)) 922 #define WRITE_YDC_DDR_BIST_BIST_FULL_MASK_WORD_7r(_unit, _pc, _val) \ 923 YDC_DDR_BIST_BIST_REG_WRITE((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_FULL_MASK_WORD_7, (_val)) 924 #define MODIFY_YDC_DDR_BIST_BIST_FULL_MASK_WORD_7r(_unit, _pc, _val, _mask) \ 925 YDC_DDR_BIST_BIST_REG_MODIFY((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_FULL_MASK_WORD_7, (_val), (_mask)) 926 927 /* BIST Full Mask Word 6 Register */ 928 #define READ_YDC_DDR_BIST_BIST_FULL_MASK_WORD_6r(_unit, _pc, _val) \ 929 YDC_DDR_BIST_BIST_REG_READ((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_FULL_MASK_WORD_6, (_val)) 930 #define WRITE_YDC_DDR_BIST_BIST_FULL_MASK_WORD_6r(_unit, _pc, _val) \ 931 YDC_DDR_BIST_BIST_REG_WRITE((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_FULL_MASK_WORD_6, (_val)) 932 #define MODIFY_YDC_DDR_BIST_BIST_FULL_MASK_WORD_6r(_unit, _pc, _val, _mask) \ 933 YDC_DDR_BIST_BIST_REG_MODIFY((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_FULL_MASK_WORD_6, (_val), (_mask)) 934 935 /* BIST Full Mask Word 5 Register */ 936 #define READ_YDC_DDR_BIST_BIST_FULL_MASK_WORD_5r(_unit, _pc, _val) \ 937 YDC_DDR_BIST_BIST_REG_READ((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_FULL_MASK_WORD_5, (_val)) 938 #define WRITE_YDC_DDR_BIST_BIST_FULL_MASK_WORD_5r(_unit, _pc, _val) \ 939 YDC_DDR_BIST_BIST_REG_WRITE((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_FULL_MASK_WORD_5, (_val)) 940 #define MODIFY_YDC_DDR_BIST_BIST_FULL_MASK_WORD_5r(_unit, _pc, _val, _mask) \ 941 YDC_DDR_BIST_BIST_REG_MODIFY((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_FULL_MASK_WORD_5, (_val), (_mask)) 942 943 /* BIST Full Mask Word 4 Register */ 944 #define READ_YDC_DDR_BIST_BIST_FULL_MASK_WORD_4r(_unit, _pc, _val) \ 945 YDC_DDR_BIST_BIST_REG_READ((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_FULL_MASK_WORD_4, (_val)) 946 #define WRITE_YDC_DDR_BIST_BIST_FULL_MASK_WORD_4r(_unit, _pc, _val) \ 947 YDC_DDR_BIST_BIST_REG_WRITE((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_FULL_MASK_WORD_4, (_val)) 948 #define MODIFY_YDC_DDR_BIST_BIST_FULL_MASK_WORD_4r(_unit, _pc, _val, _mask) \ 949 YDC_DDR_BIST_BIST_REG_MODIFY((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_FULL_MASK_WORD_4, (_val), (_mask)) 950 951 /* BIST Full Mask Word 3 Register */ 952 #define READ_YDC_DDR_BIST_BIST_FULL_MASK_WORD_3r(_unit, _pc, _val) \ 953 YDC_DDR_BIST_BIST_REG_READ((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_FULL_MASK_WORD_3, (_val)) 954 #define WRITE_YDC_DDR_BIST_BIST_FULL_MASK_WORD_3r(_unit, _pc, _val) \ 955 YDC_DDR_BIST_BIST_REG_WRITE((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_FULL_MASK_WORD_3, (_val)) 956 #define MODIFY_YDC_DDR_BIST_BIST_FULL_MASK_WORD_3r(_unit, _pc, _val, _mask) \ 957 YDC_DDR_BIST_BIST_REG_MODIFY((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_FULL_MASK_WORD_3, (_val), (_mask)) 958 959 /* BIST Full Mask Word 2 Register */ 960 #define READ_YDC_DDR_BIST_BIST_FULL_MASK_WORD_2r(_unit, _pc, _val) \ 961 YDC_DDR_BIST_BIST_REG_READ((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_FULL_MASK_WORD_2, (_val)) 962 #define WRITE_YDC_DDR_BIST_BIST_FULL_MASK_WORD_2r(_unit, _pc, _val) \ 963 YDC_DDR_BIST_BIST_REG_WRITE((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_FULL_MASK_WORD_2, (_val)) 964 #define MODIFY_YDC_DDR_BIST_BIST_FULL_MASK_WORD_2r(_unit, _pc, _val, _mask) \ 965 YDC_DDR_BIST_BIST_REG_MODIFY((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_FULL_MASK_WORD_2, (_val), (_mask)) 966 967 /* BIST Full Mask Word 1 Register */ 968 #define READ_YDC_DDR_BIST_BIST_FULL_MASK_WORD_1r(_unit, _pc, _val) \ 969 YDC_DDR_BIST_BIST_REG_READ((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_FULL_MASK_WORD_1, (_val)) 970 #define WRITE_YDC_DDR_BIST_BIST_FULL_MASK_WORD_1r(_unit, _pc, _val) \ 971 YDC_DDR_BIST_BIST_REG_WRITE((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_FULL_MASK_WORD_1, (_val)) 972 #define MODIFY_YDC_DDR_BIST_BIST_FULL_MASK_WORD_1r(_unit, _pc, _val, _mask) \ 973 YDC_DDR_BIST_BIST_REG_MODIFY((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_FULL_MASK_WORD_1, (_val), (_mask)) 974 975 /* BIST Full Mask Word 0 Register */ 976 #define READ_YDC_DDR_BIST_BIST_FULL_MASK_WORD_0r(_unit, _pc, _val) \ 977 YDC_DDR_BIST_BIST_REG_READ((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_FULL_MASK_WORD_0, (_val)) 978 #define WRITE_YDC_DDR_BIST_BIST_FULL_MASK_WORD_0r(_unit, _pc, _val) \ 979 YDC_DDR_BIST_BIST_REG_WRITE((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_FULL_MASK_WORD_0, (_val)) 980 #define MODIFY_YDC_DDR_BIST_BIST_FULL_MASK_WORD_0r(_unit, _pc, _val, _mask) \ 981 YDC_DDR_BIST_BIST_REG_MODIFY((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_FULL_MASK_WORD_0, (_val), (_mask)) 982 983 /* BIST Status Register */ 984 #define READ_YDC_DDR_BIST_BIST_STATUSESr(_unit, _pc, _val) \ 985 YDC_DDR_BIST_BIST_REG_READ((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_STATUSES, (_val)) 986 #define WRITE_YDC_DDR_BIST_BIST_STATUSESr(_unit, _pc, _val) \ 987 YDC_DDR_BIST_BIST_REG_WRITE((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_STATUSES, (_val)) 988 #define MODIFY_YDC_DDR_BIST_BIST_STATUSESr(_unit, _pc, _val, _mask) \ 989 YDC_DDR_BIST_BIST_REG_MODIFY((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_STATUSES, (_val), (_mask)) 990 991 /* BIST Full Mask Error Counter Register */ 992 #define READ_YDC_DDR_BIST_BIST_FULL_MASK_ERROR_COUNTERr(_unit, _pc, _val) \ 993 YDC_DDR_BIST_BIST_REG_READ((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_FULL_MASK_ERROR_COUNTER, (_val)) 994 #define WRITE_YDC_DDR_BIST_BIST_FULL_MASK_ERROR_COUNTERr(_unit, _pc, _val) \ 995 YDC_DDR_BIST_BIST_REG_WRITE((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_FULL_MASK_ERROR_COUNTER, (_val)) 996 #define MODIFY_YDC_DDR_BIST_BIST_FULL_MASK_ERROR_COUNTERr(_unit, _pc, _val, _mask) \ 997 YDC_DDR_BIST_BIST_REG_MODIFY((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_FULL_MASK_ERROR_COUNTER, (_val), (_mask)) 998 999 /* BIST Single Bit Mask Error Counter Register */ 1000 #define READ_YDC_DDR_BIST_BIST_SINGLE_BIT_MASK_ERROR_COUNTERr(_unit, _pc, _val) \ 1001 YDC_DDR_BIST_BIST_REG_READ((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_SINGLE_BIT_MASK_ERROR_COUNTER, (_val)) 1002 #define WRITE_YDC_DDR_BIST_BIST_SINGLE_BIT_MASK_ERROR_COUNTERr(_unit, _pc, _val) \ 1003 YDC_DDR_BIST_BIST_REG_WRITE((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_SINGLE_BIT_MASK_ERROR_COUNTER, (_val)) 1004 #define MODIFY_YDC_DDR_BIST_BIST_SINGLE_BIT_MASK_ERROR_COUNTERr(_unit, _pc, _val, _mask) \ 1005 YDC_DDR_BIST_BIST_REG_MODIFY((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_SINGLE_BIT_MASK_ERROR_COUNTER, (_val), (_mask)) 1006 1007 /* BIST Error Occurred Register */ 1008 #define READ_YDC_DDR_BIST_BIST_ERROR_OCCURREDr(_unit, _pc, _val) \ 1009 YDC_DDR_BIST_BIST_REG_READ((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_ERROR_OCCURRED, (_val)) 1010 #define WRITE_YDC_DDR_BIST_BIST_ERROR_OCCURREDr(_unit, _pc, _val) \ 1011 YDC_DDR_BIST_BIST_REG_WRITE((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_ERROR_OCCURRED, (_val)) 1012 #define MODIFY_YDC_DDR_BIST_BIST_ERROR_OCCURREDr(_unit, _pc, _val, _mask) \ 1013 YDC_DDR_BIST_BIST_REG_MODIFY((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_ERROR_OCCURRED, (_val), (_mask)) 1014 1015 /* BIST Global Error Counter Register */ 1016 #define READ_YDC_DDR_BIST_BIST_GLOBAL_ERROR_COUNTERr(_unit, _pc, _val) \ 1017 YDC_DDR_BIST_BIST_REG_READ((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_GLOBAL_ERROR_COUNTER, (_val)) 1018 #define WRITE_YDC_DDR_BIST_BIST_GLOBAL_ERROR_COUNTERr(_unit, _pc, _val) \ 1019 YDC_DDR_BIST_BIST_REG_WRITE((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_GLOBAL_ERROR_COUNTER, (_val)) 1020 #define MODIFY_YDC_DDR_BIST_BIST_GLOBAL_ERROR_COUNTERr(_unit, _pc, _val, _mask) \ 1021 YDC_DDR_BIST_BIST_REG_MODIFY((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_GLOBAL_ERROR_COUNTER, (_val), (_mask)) 1022 1023 /* Count BIST DBI Error Global Register */ 1024 #define READ_YDC_DDR_BIST_CNT_BIST_DBI_ERR_GLOBALr(_unit, _pc, _val) \ 1025 YDC_DDR_BIST_BIST_REG_READ((_unit), (_pc), 0x00, YDC_DDR_BIST_CNT_BIST_DBI_ERR_GLOBAL, (_val)) 1026 #define WRITE_YDC_DDR_BIST_CNT_BIST_DBI_ERR_GLOBALr(_unit, _pc, _val) \ 1027 YDC_DDR_BIST_BIST_REG_WRITE((_unit), (_pc), 0x00, YDC_DDR_BIST_CNT_BIST_DBI_ERR_GLOBAL, (_val)) 1028 #define MODIFY_YDC_DDR_BIST_CNT_BIST_DBI_ERR_GLOBALr(_unit, _pc, _val, _mask) \ 1029 YDC_DDR_BIST_BIST_REG_MODIFY((_unit), (_pc), 0x00, YDC_DDR_BIST_CNT_BIST_DBI_ERR_GLOBAL, (_val), (_mask)) 1030 1031 /* BIST DBI Error Occurred Register */ 1032 #define READ_YDC_DDR_BIST_BIST_DBI_ERR_OCCUREDr(_unit, _pc, _val) \ 1033 YDC_DDR_BIST_BIST_REG_READ((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_DBI_ERR_OCCURED, (_val)) 1034 #define WRITE_YDC_DDR_BIST_BIST_DBI_ERR_OCCUREDr(_unit, _pc, _val) \ 1035 YDC_DDR_BIST_BIST_REG_WRITE((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_DBI_ERR_OCCURED, (_val)) 1036 #define MODIFY_YDC_DDR_BIST_BIST_DBI_ERR_OCCUREDr(_unit, _pc, _val, _mask) \ 1037 YDC_DDR_BIST_BIST_REG_MODIFY((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_DBI_ERR_OCCURED, (_val), (_mask)) 1038 1039 /* Count BIST EDC Error Global Register */ 1040 #define READ_YDC_DDR_BIST_CNT_BIST_EDC_ERR_GLOBALr(_unit, _pc, _val) \ 1041 YDC_DDR_BIST_BIST_REG_READ((_unit), (_pc), 0x00, YDC_DDR_BIST_CNT_BIST_EDC_ERR_GLOBAL, (_val)) 1042 #define WRITE_YDC_DDR_BIST_CNT_BIST_EDC_ERR_GLOBALr(_unit, _pc, _val) \ 1043 YDC_DDR_BIST_BIST_REG_WRITE((_unit), (_pc), 0x00, YDC_DDR_BIST_CNT_BIST_EDC_ERR_GLOBAL, (_val)) 1044 #define MODIFY_YDC_DDR_BIST_CNT_BIST_EDC_ERR_GLOBALr(_unit, _pc, _val, _mask) \ 1045 YDC_DDR_BIST_BIST_REG_MODIFY((_unit), (_pc), 0x00, YDC_DDR_BIST_CNT_BIST_EDC_ERR_GLOBAL, (_val), (_mask)) 1046 1047 /* BIST EDC Error Occurred Register */ 1048 #define READ_YDC_DDR_BIST_BIST_EDC_ERR_OCCUREDr(_unit, _pc, _val) \ 1049 YDC_DDR_BIST_BIST_REG_READ((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_EDC_ERR_OCCURED, (_val)) 1050 #define WRITE_YDC_DDR_BIST_BIST_EDC_ERR_OCCUREDr(_unit, _pc, _val) \ 1051 YDC_DDR_BIST_BIST_REG_WRITE((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_EDC_ERR_OCCURED, (_val)) 1052 #define MODIFY_YDC_DDR_BIST_BIST_EDC_ERR_OCCUREDr(_unit, _pc, _val, _mask) \ 1053 YDC_DDR_BIST_BIST_REG_MODIFY((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_EDC_ERR_OCCURED, (_val), (_mask)) 1054 1055 /* BIST Last Error Address Register */ 1056 #define READ_YDC_DDR_BIST_BIST_LAST_ADDR_ERRr(_unit, _pc, _val) \ 1057 YDC_DDR_BIST_BIST_REG_READ((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_LAST_ADDR_ERR, (_val)) 1058 #define WRITE_YDC_DDR_BIST_BIST_LAST_ADDR_ERRr(_unit, _pc, _val) \ 1059 YDC_DDR_BIST_BIST_REG_WRITE((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_LAST_ADDR_ERR, (_val)) 1060 #define MODIFY_YDC_DDR_BIST_BIST_LAST_ADDR_ERRr(_unit, _pc, _val, _mask) \ 1061 YDC_DDR_BIST_BIST_REG_MODIFY((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_LAST_ADDR_ERR, (_val), (_mask)) 1062 1063 /* BIST Last Data Error MSB 31 to 0 Register */ 1064 #define READ_YDC_DDR_BIST_BIST_LAST_DATA_ERR_MSB_31_TO_0r(_unit, _pc, _val) \ 1065 YDC_DDR_BIST_BIST_REG_READ((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_LAST_DATA_ERR_MSB_31_TO_0, (_val)) 1066 #define WRITE_YDC_DDR_BIST_BIST_LAST_DATA_ERR_MSB_31_TO_0r(_unit, _pc, _val) \ 1067 YDC_DDR_BIST_BIST_REG_WRITE((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_LAST_DATA_ERR_MSB_31_TO_0, (_val)) 1068 #define MODIFY_YDC_DDR_BIST_BIST_LAST_DATA_ERR_MSB_31_TO_0r(_unit, _pc, _val, _mask) \ 1069 YDC_DDR_BIST_BIST_REG_MODIFY((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_LAST_DATA_ERR_MSB_31_TO_0, (_val), (_mask)) 1070 1071 /* BIST Last Data Error MSB 63 to 32 Register */ 1072 #define READ_YDC_DDR_BIST_BIST_LAST_DATA_ERR_MSB_63_TO_32r(_unit, _pc, _val) \ 1073 YDC_DDR_BIST_BIST_REG_READ((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_LAST_DATA_ERR_MSB_63_TO_32, (_val)) 1074 #define WRITE_YDC_DDR_BIST_BIST_LAST_DATA_ERR_MSB_63_TO_32r(_unit, _pc, _val) \ 1075 YDC_DDR_BIST_BIST_REG_WRITE((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_LAST_DATA_ERR_MSB_63_TO_32, (_val)) 1076 #define MODIFY_YDC_DDR_BIST_BIST_LAST_DATA_ERR_MSB_63_TO_32r(_unit, _pc, _val, _mask) \ 1077 YDC_DDR_BIST_BIST_REG_MODIFY((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_LAST_DATA_ERR_MSB_63_TO_32, (_val), (_mask)) 1078 1079 /* BIST Last Data Error MSB 95 to 64 Register */ 1080 #define READ_YDC_DDR_BIST_BIST_LAST_DATA_ERR_MSB_95_TO_64r(_unit, _pc, _val) \ 1081 YDC_DDR_BIST_BIST_REG_READ((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_LAST_DATA_ERR_MSB_95_TO_64, (_val)) 1082 #define WRITE_YDC_DDR_BIST_BIST_LAST_DATA_ERR_MSB_95_TO_64r(_unit, _pc, _val) \ 1083 YDC_DDR_BIST_BIST_REG_WRITE((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_LAST_DATA_ERR_MSB_95_TO_64, (_val)) 1084 #define MODIFY_YDC_DDR_BIST_BIST_LAST_DATA_ERR_MSB_95_TO_64r(_unit, _pc, _val, _mask) \ 1085 YDC_DDR_BIST_BIST_REG_MODIFY((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_LAST_DATA_ERR_MSB_95_TO_64, (_val), (_mask)) 1086 1087 /* BIST Last Data Error MSB 127 to 96 Register */ 1088 #define READ_YDC_DDR_BIST_BIST_LAST_DATA_ERR_MSB_127_TO_96r(_unit, _pc, _val) \ 1089 YDC_DDR_BIST_BIST_REG_READ((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_LAST_DATA_ERR_MSB_127_TO_96, (_val)) 1090 #define WRITE_YDC_DDR_BIST_BIST_LAST_DATA_ERR_MSB_127_TO_96r(_unit, _pc, _val) \ 1091 YDC_DDR_BIST_BIST_REG_WRITE((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_LAST_DATA_ERR_MSB_127_TO_96, (_val)) 1092 #define MODIFY_YDC_DDR_BIST_BIST_LAST_DATA_ERR_MSB_127_TO_96r(_unit, _pc, _val, _mask) \ 1093 YDC_DDR_BIST_BIST_REG_MODIFY((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_LAST_DATA_ERR_MSB_127_TO_96, (_val), (_mask)) 1094 1095 /* BIST Last Data Error LSB 31 to 0 Register */ 1096 #define READ_YDC_DDR_BIST_BIST_LAST_DATA_ERR_LSB_31_TO_0r(_unit, _pc, _val) \ 1097 YDC_DDR_BIST_BIST_REG_READ((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_LAST_DATA_ERR_LSB_31_TO_0, (_val)) 1098 #define WRITE_YDC_DDR_BIST_BIST_LAST_DATA_ERR_LSB_31_TO_0r(_unit, _pc, _val) \ 1099 YDC_DDR_BIST_BIST_REG_WRITE((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_LAST_DATA_ERR_LSB_31_TO_0, (_val)) 1100 #define MODIFY_YDC_DDR_BIST_BIST_LAST_DATA_ERR_LSB_31_TO_0r(_unit, _pc, _val, _mask) \ 1101 YDC_DDR_BIST_BIST_REG_MODIFY((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_LAST_DATA_ERR_LSB_31_TO_0, (_val), (_mask)) 1102 1103 /* BIST Last Data Error LSB 63 to 32 Register */ 1104 #define READ_YDC_DDR_BIST_BIST_LAST_DATA_ERR_LSB_63_TO_32r(_unit, _pc, _val) \ 1105 YDC_DDR_BIST_BIST_REG_READ((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_LAST_DATA_ERR_LSB_63_TO_32, (_val)) 1106 #define WRITE_YDC_DDR_BIST_BIST_LAST_DATA_ERR_LSB_63_TO_32r(_unit, _pc, _val) \ 1107 YDC_DDR_BIST_BIST_REG_WRITE((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_LAST_DATA_ERR_LSB_63_TO_32, (_val)) 1108 #define MODIFY_YDC_DDR_BIST_BIST_LAST_DATA_ERR_LSB_63_TO_32r(_unit, _pc, _val, _mask) \ 1109 YDC_DDR_BIST_BIST_REG_MODIFY((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_LAST_DATA_ERR_LSB_63_TO_32, (_val), (_mask)) 1110 1111 /* BIST Last Data Error LSB 95 to 64 Register */ 1112 #define READ_YDC_DDR_BIST_BIST_LAST_DATA_ERR_LSB_95_TO_64r(_unit, _pc, _val) \ 1113 YDC_DDR_BIST_BIST_REG_READ((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_LAST_DATA_ERR_LSB_95_TO_64, (_val)) 1114 #define WRITE_YDC_DDR_BIST_BIST_LAST_DATA_ERR_LSB_95_TO_64r(_unit, _pc, _val) \ 1115 YDC_DDR_BIST_BIST_REG_WRITE((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_LAST_DATA_ERR_LSB_95_TO_64, (_val)) 1116 #define MODIFY_YDC_DDR_BIST_BIST_LAST_DATA_ERR_LSB_95_TO_64r(_unit, _pc, _val, _mask) \ 1117 YDC_DDR_BIST_BIST_REG_MODIFY((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_LAST_DATA_ERR_LSB_95_TO_64, (_val), (_mask)) 1118 1119 /* BIST Last Data Error LSB 127 to 96 Register */ 1120 #define READ_YDC_DDR_BIST_BIST_LAST_DATA_ERR_LSB_127_TO_96r(_unit, _pc, _val) \ 1121 YDC_DDR_BIST_BIST_REG_READ((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_LAST_DATA_ERR_LSB_127_TO_96, (_val)) 1122 #define WRITE_YDC_DDR_BIST_BIST_LAST_DATA_ERR_LSB_127_TO_96r(_unit, _pc, _val) \ 1123 YDC_DDR_BIST_BIST_REG_WRITE((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_LAST_DATA_ERR_LSB_127_TO_96, (_val)) 1124 #define MODIFY_YDC_DDR_BIST_BIST_LAST_DATA_ERR_LSB_127_TO_96r(_unit, _pc, _val, _mask) \ 1125 YDC_DDR_BIST_BIST_REG_MODIFY((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_LAST_DATA_ERR_LSB_127_TO_96, (_val), (_mask)) 1126 1127 /* BIST Last Read Data MSB 31 to 0 Register */ 1128 #define READ_YDC_DDR_BIST_BIST_LAST_READ_DATA_MSB_31_TO_0r(_unit, _pc, _val) \ 1129 YDC_DDR_BIST_BIST_REG_READ((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_LAST_READ_DATA_MSB_31_TO_0, (_val)) 1130 #define WRITE_YDC_DDR_BIST_BIST_LAST_READ_DATA_MSB_31_TO_0r(_unit, _pc, _val) \ 1131 YDC_DDR_BIST_BIST_REG_WRITE((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_LAST_READ_DATA_MSB_31_TO_0, (_val)) 1132 #define MODIFY_YDC_DDR_BIST_BIST_LAST_READ_DATA_MSB_31_TO_0r(_unit, _pc, _val, _mask) \ 1133 YDC_DDR_BIST_BIST_REG_MODIFY((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_LAST_READ_DATA_MSB_31_TO_0, (_val), (_mask)) 1134 1135 /* BIST Last Read Data MSB 63 to 32 Register */ 1136 #define READ_YDC_DDR_BIST_BIST_LAST_READ_DATA_MSB_63_TO_32r(_unit, _pc, _val) \ 1137 YDC_DDR_BIST_BIST_REG_READ((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_LAST_READ_DATA_MSB_63_TO_32, (_val)) 1138 #define WRITE_YDC_DDR_BIST_BIST_LAST_READ_DATA_MSB_63_TO_32r(_unit, _pc, _val) \ 1139 YDC_DDR_BIST_BIST_REG_WRITE((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_LAST_READ_DATA_MSB_63_TO_32, (_val)) 1140 #define MODIFY_YDC_DDR_BIST_BIST_LAST_READ_DATA_MSB_63_TO_32r(_unit, _pc, _val, _mask) \ 1141 YDC_DDR_BIST_BIST_REG_MODIFY((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_LAST_READ_DATA_MSB_63_TO_32, (_val), (_mask)) 1142 1143 /* BIST Last Read Data MSB 95 to 64 Register */ 1144 #define READ_YDC_DDR_BIST_BIST_LAST_READ_DATA_MSB_95_TO_64r(_unit, _pc, _val) \ 1145 YDC_DDR_BIST_BIST_REG_READ((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_LAST_READ_DATA_MSB_95_TO_64, (_val)) 1146 #define WRITE_YDC_DDR_BIST_BIST_LAST_READ_DATA_MSB_95_TO_64r(_unit, _pc, _val) \ 1147 YDC_DDR_BIST_BIST_REG_WRITE((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_LAST_READ_DATA_MSB_95_TO_64, (_val)) 1148 #define MODIFY_YDC_DDR_BIST_BIST_LAST_READ_DATA_MSB_95_TO_64r(_unit, _pc, _val, _mask) \ 1149 YDC_DDR_BIST_BIST_REG_MODIFY((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_LAST_READ_DATA_MSB_95_TO_64, (_val), (_mask)) 1150 1151 /* BIST Last Read Data MSB 127 to 96 Register */ 1152 #define READ_YDC_DDR_BIST_BIST_LAST_READ_DATA_MSB_127_TO_96r(_unit, _pc, _val) \ 1153 YDC_DDR_BIST_BIST_REG_READ((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_LAST_READ_DATA_MSB_127_TO_96, (_val)) 1154 #define WRITE_YDC_DDR_BIST_BIST_LAST_READ_DATA_MSB_127_TO_96r(_unit, _pc, _val) \ 1155 YDC_DDR_BIST_BIST_REG_WRITE((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_LAST_READ_DATA_MSB_127_TO_96, (_val)) 1156 #define MODIFY_YDC_DDR_BIST_BIST_LAST_READ_DATA_MSB_127_TO_96r(_unit, _pc, _val, _mask) \ 1157 YDC_DDR_BIST_BIST_REG_MODIFY((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_LAST_READ_DATA_MSB_127_TO_96, (_val), (_mask)) 1158 1159 /* BIST Last Read Data LSB 31 to 0 Register */ 1160 #define READ_YDC_DDR_BIST_BIST_LAST_READ_DATA_LSB_31_TO_0r(_unit, _pc, _val) \ 1161 YDC_DDR_BIST_BIST_REG_READ((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_LAST_READ_DATA_LSB_31_TO_0, (_val)) 1162 #define WRITE_YDC_DDR_BIST_BIST_LAST_READ_DATA_LSB_31_TO_0r(_unit, _pc, _val) \ 1163 YDC_DDR_BIST_BIST_REG_WRITE((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_LAST_READ_DATA_LSB_31_TO_0, (_val)) 1164 #define MODIFY_YDC_DDR_BIST_BIST_LAST_READ_DATA_LSB_31_TO_0r(_unit, _pc, _val, _mask) \ 1165 YDC_DDR_BIST_BIST_REG_MODIFY((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_LAST_READ_DATA_LSB_31_TO_0, (_val), (_mask)) 1166 1167 /* BIST Last Read Data LSB 63 to 32 Register */ 1168 #define READ_YDC_DDR_BIST_BIST_LAST_READ_DATA_LSB_63_TO_32r(_unit, _pc, _val) \ 1169 YDC_DDR_BIST_BIST_REG_READ((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_LAST_READ_DATA_LSB_63_TO_32, (_val)) 1170 #define WRITE_YDC_DDR_BIST_BIST_LAST_READ_DATA_LSB_63_TO_32r(_unit, _pc, _val) \ 1171 YDC_DDR_BIST_BIST_REG_WRITE((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_LAST_READ_DATA_LSB_63_TO_32, (_val)) 1172 #define MODIFY_YDC_DDR_BIST_BIST_LAST_READ_DATA_LSB_63_TO_32r(_unit, _pc, _val, _mask) \ 1173 YDC_DDR_BIST_BIST_REG_MODIFY((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_LAST_READ_DATA_LSB_63_TO_32, (_val), (_mask)) 1174 1175 /* BIST Last Read Data LSB 95 to 64 Register */ 1176 #define READ_YDC_DDR_BIST_BIST_LAST_READ_DATA_LSB_95_TO_64r(_unit, _pc, _val) \ 1177 YDC_DDR_BIST_BIST_REG_READ((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_LAST_READ_DATA_LSB_95_TO_64, (_val)) 1178 #define WRITE_YDC_DDR_BIST_BIST_LAST_READ_DATA_LSB_95_TO_64r(_unit, _pc, _val) \ 1179 YDC_DDR_BIST_BIST_REG_WRITE((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_LAST_READ_DATA_LSB_95_TO_64, (_val)) 1180 #define MODIFY_YDC_DDR_BIST_BIST_LAST_READ_DATA_LSB_95_TO_64r(_unit, _pc, _val, _mask) \ 1181 YDC_DDR_BIST_BIST_REG_MODIFY((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_LAST_READ_DATA_LSB_95_TO_64, (_val), (_mask)) 1182 1183 /* BIST Last Read Data LSB 127 to 96 Register */ 1184 #define READ_YDC_DDR_BIST_BIST_LAST_READ_DATA_LSB_127_TO_96r(_unit, _pc, _val) \ 1185 YDC_DDR_BIST_BIST_REG_READ((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_LAST_READ_DATA_LSB_127_TO_96, (_val)) 1186 #define WRITE_YDC_DDR_BIST_BIST_LAST_READ_DATA_LSB_127_TO_96r(_unit, _pc, _val) \ 1187 YDC_DDR_BIST_BIST_REG_WRITE((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_LAST_READ_DATA_LSB_127_TO_96, (_val)) 1188 #define MODIFY_YDC_DDR_BIST_BIST_LAST_READ_DATA_LSB_127_TO_96r(_unit, _pc, _val, _mask) \ 1189 YDC_DDR_BIST_BIST_REG_MODIFY((_unit), (_pc), 0x00, YDC_DDR_BIST_BIST_LAST_READ_DATA_LSB_127_TO_96, (_val), (_mask)) 1190 1191 /* GDDR5 BIST Finish Period Register */ 1192 #define READ_YDC_DDR_BIST_GDDR5_BIST_FINISH_PRDr(_unit, _pc, _val) \ 1193 YDC_DDR_BIST_BIST_REG_READ((_unit), (_pc), 0x00, YDC_DDR_BIST_GDDR5_BIST_FINISH_PRD, (_val)) 1194 #define WRITE_YDC_DDR_BIST_GDDR5_BIST_FINISH_PRDr(_unit, _pc, _val) \ 1195 YDC_DDR_BIST_BIST_REG_WRITE((_unit), (_pc), 0x00, YDC_DDR_BIST_GDDR5_BIST_FINISH_PRD, (_val)) 1196 #define MODIFY_YDC_DDR_BIST_GDDR5_BIST_FINISH_PRDr(_unit, _pc, _val, _mask) \ 1197 YDC_DDR_BIST_BIST_REG_MODIFY((_unit), (_pc), 0x00, YDC_DDR_BIST_GDDR5_BIST_FINISH_PRD, (_val), (_mask)) 1198 1199 /* Initial Calibration Use MPR Register */ 1200 #define READ_YDC_DDR_BIST_INTIAL_CALIB_USE_MPRr(_unit, _pc, _val) \ 1201 YDC_DDR_BIST_BIST_REG_READ((_unit), (_pc), 0x00, YDC_DDR_BIST_INTIAL_CALIB_USE_MPR, (_val)) 1202 #define WRITE_YDC_DDR_BIST_INTIAL_CALIB_USE_MPRr(_unit, _pc, _val) \ 1203 YDC_DDR_BIST_BIST_REG_WRITE((_unit), (_pc), 0x00, YDC_DDR_BIST_INTIAL_CALIB_USE_MPR, (_val)) 1204 #define MODIFY_YDC_DDR_BIST_INTIAL_CALIB_USE_MPRr(_unit, _pc, _val, _mask) \ 1205 YDC_DDR_BIST_BIST_REG_MODIFY((_unit), (_pc), 0x00, YDC_DDR_BIST_INTIAL_CALIB_USE_MPR, (_val), (_mask)) 1206 1207 1208 /**************************************************************************** 1209 * YDC_DDR_BIST_BIST_YDC_DDR_BIST 1210 */ 1211 /**************************************************************************** 1212 * YDC_DDR_BIST :: BIST_CONFIG 1213 */ 1214 /* YDC_DDR_BIST :: BIST_CONFIG :: reserved0 [31:16] */ 1215 #define YDC_DDR_BIST_BIST_CONFIG_RESERVED0_MASK 0xffff0000 1216 #define YDC_DDR_BIST_BIST_CONFIG_RESERVED0_ALIGN 0 1217 #define YDC_DDR_BIST_BIST_CONFIG_RESERVED0_BITS 16 1218 #define YDC_DDR_BIST_BIST_CONFIG_RESERVED0_SHIFT 16 1219 #define YDC_DDR_BIST_BIST_CONFIG_RESERVED0_DEFAULT 0x00000000 1220 1221 /* YDC_DDR_BIST :: BIST_CONFIG :: BUS16_MODE [15:15] */ 1222 #define YDC_DDR_BIST_BIST_CONFIG_BUS16_MODE_MASK 0x00008000 1223 #define YDC_DDR_BIST_BIST_CONFIG_BUS16_MODE_ALIGN 0 1224 #define YDC_DDR_BIST_BIST_CONFIG_BUS16_MODE_BITS 1 1225 #define YDC_DDR_BIST_BIST_CONFIG_BUS16_MODE_SHIFT 15 1226 #define YDC_DDR_BIST_BIST_CONFIG_BUS16_MODE_DEFAULT 0x00000000 1227 1228 /* YDC_DDR_BIST :: BIST_CONFIG :: ENABLE_8_BANKS_MODE [14:14] */ 1229 #define YDC_DDR_BIST_BIST_CONFIG_ENABLE_8_BANKS_MODE_MASK 0x00004000 1230 #define YDC_DDR_BIST_BIST_CONFIG_ENABLE_8_BANKS_MODE_ALIGN 0 1231 #define YDC_DDR_BIST_BIST_CONFIG_ENABLE_8_BANKS_MODE_BITS 1 1232 #define YDC_DDR_BIST_BIST_CONFIG_ENABLE_8_BANKS_MODE_SHIFT 14 1233 #define YDC_DDR_BIST_BIST_CONFIG_ENABLE_8_BANKS_MODE_DEFAULT 0x00000000 1234 1235 /* YDC_DDR_BIST :: BIST_CONFIG :: DISABLE_COL_BANK_SWAPPING [13:13] */ 1236 #define YDC_DDR_BIST_BIST_CONFIG_DISABLE_COL_BANK_SWAPPING_MASK 0x00002000 1237 #define YDC_DDR_BIST_BIST_CONFIG_DISABLE_COL_BANK_SWAPPING_ALIGN 0 1238 #define YDC_DDR_BIST_BIST_CONFIG_DISABLE_COL_BANK_SWAPPING_BITS 1 1239 #define YDC_DDR_BIST_BIST_CONFIG_DISABLE_COL_BANK_SWAPPING_SHIFT 13 1240 #define YDC_DDR_BIST_BIST_CONFIG_DISABLE_COL_BANK_SWAPPING_DEFAULT 0x00000000 1241 1242 /* YDC_DDR_BIST :: BIST_CONFIG :: BIST_ARPRIORITY [12:10] */ 1243 #define YDC_DDR_BIST_BIST_CONFIG_BIST_ARPRIORITY_MASK 0x00001c00 1244 #define YDC_DDR_BIST_BIST_CONFIG_BIST_ARPRIORITY_ALIGN 0 1245 #define YDC_DDR_BIST_BIST_CONFIG_BIST_ARPRIORITY_BITS 3 1246 #define YDC_DDR_BIST_BIST_CONFIG_BIST_ARPRIORITY_SHIFT 10 1247 #define YDC_DDR_BIST_BIST_CONFIG_BIST_ARPRIORITY_DEFAULT 0x00000000 1248 1249 /* YDC_DDR_BIST :: BIST_CONFIG :: BIST_ARAPCMD [09:09] */ 1250 #define YDC_DDR_BIST_BIST_CONFIG_BIST_ARAPCMD_MASK 0x00000200 1251 #define YDC_DDR_BIST_BIST_CONFIG_BIST_ARAPCMD_ALIGN 0 1252 #define YDC_DDR_BIST_BIST_CONFIG_BIST_ARAPCMD_BITS 1 1253 #define YDC_DDR_BIST_BIST_CONFIG_BIST_ARAPCMD_SHIFT 9 1254 #define YDC_DDR_BIST_BIST_CONFIG_BIST_ARAPCMD_DEFAULT 0x00000000 1255 1256 /* YDC_DDR_BIST :: BIST_CONFIG :: BIST_AWUSER [08:08] */ 1257 #define YDC_DDR_BIST_BIST_CONFIG_BIST_AWUSER_MASK 0x00000100 1258 #define YDC_DDR_BIST_BIST_CONFIG_BIST_AWUSER_ALIGN 0 1259 #define YDC_DDR_BIST_BIST_CONFIG_BIST_AWUSER_BITS 1 1260 #define YDC_DDR_BIST_BIST_CONFIG_BIST_AWUSER_SHIFT 8 1261 #define YDC_DDR_BIST_BIST_CONFIG_BIST_AWUSER_DEFAULT 0x00000000 1262 1263 /* YDC_DDR_BIST :: BIST_CONFIG :: BIST_AWPRIORITY [07:05] */ 1264 #define YDC_DDR_BIST_BIST_CONFIG_BIST_AWPRIORITY_MASK 0x000000e0 1265 #define YDC_DDR_BIST_BIST_CONFIG_BIST_AWPRIORITY_ALIGN 0 1266 #define YDC_DDR_BIST_BIST_CONFIG_BIST_AWPRIORITY_BITS 3 1267 #define YDC_DDR_BIST_BIST_CONFIG_BIST_AWPRIORITY_SHIFT 5 1268 #define YDC_DDR_BIST_BIST_CONFIG_BIST_AWPRIORITY_DEFAULT 0x00000000 1269 1270 /* YDC_DDR_BIST :: BIST_CONFIG :: BIST_AWCOBUF [04:04] */ 1271 #define YDC_DDR_BIST_BIST_CONFIG_BIST_AWCOBUF_MASK 0x00000010 1272 #define YDC_DDR_BIST_BIST_CONFIG_BIST_AWCOBUF_ALIGN 0 1273 #define YDC_DDR_BIST_BIST_CONFIG_BIST_AWCOBUF_BITS 1 1274 #define YDC_DDR_BIST_BIST_CONFIG_BIST_AWCOBUF_SHIFT 4 1275 #define YDC_DDR_BIST_BIST_CONFIG_BIST_AWCOBUF_DEFAULT 0x00000000 1276 1277 /* YDC_DDR_BIST :: BIST_CONFIG :: BIST_AWAPCMD [03:03] */ 1278 #define YDC_DDR_BIST_BIST_CONFIG_BIST_AWAPCMD_MASK 0x00000008 1279 #define YDC_DDR_BIST_BIST_CONFIG_BIST_AWAPCMD_ALIGN 0 1280 #define YDC_DDR_BIST_BIST_CONFIG_BIST_AWAPCMD_BITS 1 1281 #define YDC_DDR_BIST_BIST_CONFIG_BIST_AWAPCMD_SHIFT 3 1282 #define YDC_DDR_BIST_BIST_CONFIG_BIST_AWAPCMD_DEFAULT 0x00000000 1283 1284 /* YDC_DDR_BIST :: BIST_CONFIG :: BIST_AWCACHE_0 [02:02] */ 1285 #define YDC_DDR_BIST_BIST_CONFIG_BIST_AWCACHE_0_MASK 0x00000004 1286 #define YDC_DDR_BIST_BIST_CONFIG_BIST_AWCACHE_0_ALIGN 0 1287 #define YDC_DDR_BIST_BIST_CONFIG_BIST_AWCACHE_0_BITS 1 1288 #define YDC_DDR_BIST_BIST_CONFIG_BIST_AWCACHE_0_SHIFT 2 1289 #define YDC_DDR_BIST_BIST_CONFIG_BIST_AWCACHE_0_DEFAULT 0x00000000 1290 1291 /* YDC_DDR_BIST :: BIST_CONFIG :: AXI_PORT_SEL [01:01] */ 1292 #define YDC_DDR_BIST_BIST_CONFIG_AXI_PORT_SEL_MASK 0x00000002 1293 #define YDC_DDR_BIST_BIST_CONFIG_AXI_PORT_SEL_ALIGN 0 1294 #define YDC_DDR_BIST_BIST_CONFIG_AXI_PORT_SEL_BITS 1 1295 #define YDC_DDR_BIST_BIST_CONFIG_AXI_PORT_SEL_SHIFT 1 1296 #define YDC_DDR_BIST_BIST_CONFIG_AXI_PORT_SEL_DEFAULT 0x00000000 1297 1298 /* YDC_DDR_BIST :: BIST_CONFIG :: BIST_RESETB [00:00] */ 1299 #define YDC_DDR_BIST_BIST_CONFIG_BIST_RESETB_MASK 0x00000001 1300 #define YDC_DDR_BIST_BIST_CONFIG_BIST_RESETB_ALIGN 0 1301 #define YDC_DDR_BIST_BIST_CONFIG_BIST_RESETB_BITS 1 1302 #define YDC_DDR_BIST_BIST_CONFIG_BIST_RESETB_SHIFT 0 1303 #define YDC_DDR_BIST_BIST_CONFIG_BIST_RESETB_DEFAULT 0x00000000 1304 1305 1306 /**************************************************************************** 1307 * YDC_DDR_BIST :: BIST_CONFIG_2 1308 */ 1309 /* YDC_DDR_BIST :: BIST_CONFIG_2 :: reserved0 [31:19] */ 1310 #define YDC_DDR_BIST_BIST_CONFIG_2_RESERVED0_MASK 0xfff80000 1311 #define YDC_DDR_BIST_BIST_CONFIG_2_RESERVED0_ALIGN 0 1312 #define YDC_DDR_BIST_BIST_CONFIG_2_RESERVED0_BITS 13 1313 #define YDC_DDR_BIST_BIST_CONFIG_2_RESERVED0_SHIFT 19 1314 #define YDC_DDR_BIST_BIST_CONFIG_2_RESERVED0_DEFAULT 0x00000000 1315 1316 /* YDC_DDR_BIST :: BIST_CONFIG_2 :: FIFO_RADDR_ALMOST_FULL_LEVEL [18:16] */ 1317 #define YDC_DDR_BIST_BIST_CONFIG_2_FIFO_RADDR_ALMOST_FULL_LEVEL_MASK 0x00070000 1318 #define YDC_DDR_BIST_BIST_CONFIG_2_FIFO_RADDR_ALMOST_FULL_LEVEL_ALIGN 0 1319 #define YDC_DDR_BIST_BIST_CONFIG_2_FIFO_RADDR_ALMOST_FULL_LEVEL_BITS 3 1320 #define YDC_DDR_BIST_BIST_CONFIG_2_FIFO_RADDR_ALMOST_FULL_LEVEL_SHIFT 16 1321 #define YDC_DDR_BIST_BIST_CONFIG_2_FIFO_RADDR_ALMOST_FULL_LEVEL_DEFAULT 0x00000004 1322 1323 /* YDC_DDR_BIST :: BIST_CONFIG_2 :: reserved1 [15:11] */ 1324 #define YDC_DDR_BIST_BIST_CONFIG_2_RESERVED1_MASK 0x0000f800 1325 #define YDC_DDR_BIST_BIST_CONFIG_2_RESERVED1_ALIGN 0 1326 #define YDC_DDR_BIST_BIST_CONFIG_2_RESERVED1_BITS 5 1327 #define YDC_DDR_BIST_BIST_CONFIG_2_RESERVED1_SHIFT 11 1328 #define YDC_DDR_BIST_BIST_CONFIG_2_RESERVED1_DEFAULT 0x00000000 1329 1330 /* YDC_DDR_BIST :: BIST_CONFIG_2 :: FIFO_CMD_ALMOST_FULL_LEVEL [10:08] */ 1331 #define YDC_DDR_BIST_BIST_CONFIG_2_FIFO_CMD_ALMOST_FULL_LEVEL_MASK 0x00000700 1332 #define YDC_DDR_BIST_BIST_CONFIG_2_FIFO_CMD_ALMOST_FULL_LEVEL_ALIGN 0 1333 #define YDC_DDR_BIST_BIST_CONFIG_2_FIFO_CMD_ALMOST_FULL_LEVEL_BITS 3 1334 #define YDC_DDR_BIST_BIST_CONFIG_2_FIFO_CMD_ALMOST_FULL_LEVEL_SHIFT 8 1335 #define YDC_DDR_BIST_BIST_CONFIG_2_FIFO_CMD_ALMOST_FULL_LEVEL_DEFAULT 0x00000002 1336 1337 /* YDC_DDR_BIST :: BIST_CONFIG_2 :: reserved2 [07:03] */ 1338 #define YDC_DDR_BIST_BIST_CONFIG_2_RESERVED2_MASK 0x000000f8 1339 #define YDC_DDR_BIST_BIST_CONFIG_2_RESERVED2_ALIGN 0 1340 #define YDC_DDR_BIST_BIST_CONFIG_2_RESERVED2_BITS 5 1341 #define YDC_DDR_BIST_BIST_CONFIG_2_RESERVED2_SHIFT 3 1342 #define YDC_DDR_BIST_BIST_CONFIG_2_RESERVED2_DEFAULT 0x00000000 1343 1344 /* YDC_DDR_BIST :: BIST_CONFIG_2 :: FIFO_WDATA_ALMOST_FULL_LEVEL [02:00] */ 1345 #define YDC_DDR_BIST_BIST_CONFIG_2_FIFO_WDATA_ALMOST_FULL_LEVEL_MASK 0x00000007 1346 #define YDC_DDR_BIST_BIST_CONFIG_2_FIFO_WDATA_ALMOST_FULL_LEVEL_ALIGN 0 1347 #define YDC_DDR_BIST_BIST_CONFIG_2_FIFO_WDATA_ALMOST_FULL_LEVEL_BITS 3 1348 #define YDC_DDR_BIST_BIST_CONFIG_2_FIFO_WDATA_ALMOST_FULL_LEVEL_SHIFT 0 1349 #define YDC_DDR_BIST_BIST_CONFIG_2_FIFO_WDATA_ALMOST_FULL_LEVEL_DEFAULT 0x00000002 1350 1351 1352 /**************************************************************************** 1353 * YDC_DDR_BIST :: BIST_GENERAL_CONFIGURATIONS 1354 */ 1355 /* YDC_DDR_BIST :: BIST_GENERAL_CONFIGURATIONS :: reserved0 [31:16] */ 1356 #define YDC_DDR_BIST_BIST_GENERAL_CONFIGURATIONS_RESERVED0_MASK 0xffff0000 1357 #define YDC_DDR_BIST_BIST_GENERAL_CONFIGURATIONS_RESERVED0_ALIGN 0 1358 #define YDC_DDR_BIST_BIST_GENERAL_CONFIGURATIONS_RESERVED0_BITS 16 1359 #define YDC_DDR_BIST_BIST_GENERAL_CONFIGURATIONS_RESERVED0_SHIFT 16 1360 #define YDC_DDR_BIST_BIST_GENERAL_CONFIGURATIONS_RESERVED0_DEFAULT 0x00000000 1361 1362 /* YDC_DDR_BIST :: BIST_GENERAL_CONFIGURATIONS :: BANK_GROUP_TOPO [15:14] */ 1363 #define YDC_DDR_BIST_BIST_GENERAL_CONFIGURATIONS_BANK_GROUP_TOPO_MASK 0x0000c000 1364 #define YDC_DDR_BIST_BIST_GENERAL_CONFIGURATIONS_BANK_GROUP_TOPO_ALIGN 0 1365 #define YDC_DDR_BIST_BIST_GENERAL_CONFIGURATIONS_BANK_GROUP_TOPO_BITS 2 1366 #define YDC_DDR_BIST_BIST_GENERAL_CONFIGURATIONS_BANK_GROUP_TOPO_SHIFT 14 1367 #define YDC_DDR_BIST_BIST_GENERAL_CONFIGURATIONS_BANK_GROUP_TOPO_DEFAULT 0x00000000 1368 1369 /* YDC_DDR_BIST :: BIST_GENERAL_CONFIGURATIONS :: reserved1 [13:07] */ 1370 #define YDC_DDR_BIST_BIST_GENERAL_CONFIGURATIONS_RESERVED1_MASK 0x00003f80 1371 #define YDC_DDR_BIST_BIST_GENERAL_CONFIGURATIONS_RESERVED1_ALIGN 0 1372 #define YDC_DDR_BIST_BIST_GENERAL_CONFIGURATIONS_RESERVED1_BITS 7 1373 #define YDC_DDR_BIST_BIST_GENERAL_CONFIGURATIONS_RESERVED1_SHIFT 7 1374 #define YDC_DDR_BIST_BIST_GENERAL_CONFIGURATIONS_RESERVED1_DEFAULT 0x00000000 1375 1376 /* YDC_DDR_BIST :: BIST_GENERAL_CONFIGURATIONS :: NUM_COLS [06:04] */ 1377 #define YDC_DDR_BIST_BIST_GENERAL_CONFIGURATIONS_NUM_COLS_MASK 0x00000070 1378 #define YDC_DDR_BIST_BIST_GENERAL_CONFIGURATIONS_NUM_COLS_ALIGN 0 1379 #define YDC_DDR_BIST_BIST_GENERAL_CONFIGURATIONS_NUM_COLS_BITS 3 1380 #define YDC_DDR_BIST_BIST_GENERAL_CONFIGURATIONS_NUM_COLS_SHIFT 4 1381 #define YDC_DDR_BIST_BIST_GENERAL_CONFIGURATIONS_NUM_COLS_DEFAULT 0x00000002 1382 1383 /* YDC_DDR_BIST :: BIST_GENERAL_CONFIGURATIONS :: reserved2 [03:00] */ 1384 #define YDC_DDR_BIST_BIST_GENERAL_CONFIGURATIONS_RESERVED2_MASK 0x0000000f 1385 #define YDC_DDR_BIST_BIST_GENERAL_CONFIGURATIONS_RESERVED2_ALIGN 0 1386 #define YDC_DDR_BIST_BIST_GENERAL_CONFIGURATIONS_RESERVED2_BITS 4 1387 #define YDC_DDR_BIST_BIST_GENERAL_CONFIGURATIONS_RESERVED2_SHIFT 0 1388 #define YDC_DDR_BIST_BIST_GENERAL_CONFIGURATIONS_RESERVED2_DEFAULT 0x00000000 1389 1390 1391 /**************************************************************************** 1392 * YDC_DDR_BIST :: DRAM_SPECIAL_FEATURES 1393 */ 1394 /* YDC_DDR_BIST :: DRAM_SPECIAL_FEATURES :: reserved0 [31:04] */ 1395 #define YDC_DDR_BIST_DRAM_SPECIAL_FEATURES_RESERVED0_MASK 0xfffffff0 1396 #define YDC_DDR_BIST_DRAM_SPECIAL_FEATURES_RESERVED0_ALIGN 0 1397 #define YDC_DDR_BIST_DRAM_SPECIAL_FEATURES_RESERVED0_BITS 28 1398 #define YDC_DDR_BIST_DRAM_SPECIAL_FEATURES_RESERVED0_SHIFT 4 1399 #define YDC_DDR_BIST_DRAM_SPECIAL_FEATURES_RESERVED0_DEFAULT 0x00000000 1400 1401 /* YDC_DDR_BIST :: DRAM_SPECIAL_FEATURES :: READ_DBI [03:03] */ 1402 #define YDC_DDR_BIST_DRAM_SPECIAL_FEATURES_READ_DBI_MASK 0x00000008 1403 #define YDC_DDR_BIST_DRAM_SPECIAL_FEATURES_READ_DBI_ALIGN 0 1404 #define YDC_DDR_BIST_DRAM_SPECIAL_FEATURES_READ_DBI_BITS 1 1405 #define YDC_DDR_BIST_DRAM_SPECIAL_FEATURES_READ_DBI_SHIFT 3 1406 #define YDC_DDR_BIST_DRAM_SPECIAL_FEATURES_READ_DBI_DEFAULT 0x00000000 1407 1408 /* YDC_DDR_BIST :: DRAM_SPECIAL_FEATURES :: reserved1 [02:00] */ 1409 #define YDC_DDR_BIST_DRAM_SPECIAL_FEATURES_RESERVED1_MASK 0x00000007 1410 #define YDC_DDR_BIST_DRAM_SPECIAL_FEATURES_RESERVED1_ALIGN 0 1411 #define YDC_DDR_BIST_DRAM_SPECIAL_FEATURES_RESERVED1_BITS 3 1412 #define YDC_DDR_BIST_DRAM_SPECIAL_FEATURES_RESERVED1_SHIFT 0 1413 #define YDC_DDR_BIST_DRAM_SPECIAL_FEATURES_RESERVED1_DEFAULT 0x00000000 1414 1415 1416 /**************************************************************************** 1417 * YDC_DDR_BIST :: BIST_CONFIGURATIONS_0 1418 */ 1419 /* YDC_DDR_BIST :: BIST_CONFIGURATIONS_0 :: MPR_READOUT_MPR_LOCATION [31:28] */ 1420 #define YDC_DDR_BIST_BIST_CONFIGURATIONS_0_MPR_READOUT_MPR_LOCATION_MASK 0xf0000000 1421 #define YDC_DDR_BIST_BIST_CONFIGURATIONS_0_MPR_READOUT_MPR_LOCATION_ALIGN 0 1422 #define YDC_DDR_BIST_BIST_CONFIGURATIONS_0_MPR_READOUT_MPR_LOCATION_BITS 4 1423 #define YDC_DDR_BIST_BIST_CONFIGURATIONS_0_MPR_READOUT_MPR_LOCATION_SHIFT 28 1424 #define YDC_DDR_BIST_BIST_CONFIGURATIONS_0_MPR_READOUT_MPR_LOCATION_DEFAULT 0x00000000 1425 1426 /* YDC_DDR_BIST :: BIST_CONFIGURATIONS_0 :: MPR_READOUT_MODE [27:27] */ 1427 #define YDC_DDR_BIST_BIST_CONFIGURATIONS_0_MPR_READOUT_MODE_MASK 0x08000000 1428 #define YDC_DDR_BIST_BIST_CONFIGURATIONS_0_MPR_READOUT_MODE_ALIGN 0 1429 #define YDC_DDR_BIST_BIST_CONFIGURATIONS_0_MPR_READOUT_MODE_BITS 1 1430 #define YDC_DDR_BIST_BIST_CONFIGURATIONS_0_MPR_READOUT_MODE_SHIFT 27 1431 #define YDC_DDR_BIST_BIST_CONFIGURATIONS_0_MPR_READOUT_MODE_DEFAULT 0x00000000 1432 1433 /* YDC_DDR_BIST :: BIST_CONFIGURATIONS_0 :: MPR_STAGGER_INCREMENT_MODE [26:26] */ 1434 #define YDC_DDR_BIST_BIST_CONFIGURATIONS_0_MPR_STAGGER_INCREMENT_MODE_MASK 0x04000000 1435 #define YDC_DDR_BIST_BIST_CONFIGURATIONS_0_MPR_STAGGER_INCREMENT_MODE_ALIGN 0 1436 #define YDC_DDR_BIST_BIST_CONFIGURATIONS_0_MPR_STAGGER_INCREMENT_MODE_BITS 1 1437 #define YDC_DDR_BIST_BIST_CONFIGURATIONS_0_MPR_STAGGER_INCREMENT_MODE_SHIFT 26 1438 #define YDC_DDR_BIST_BIST_CONFIGURATIONS_0_MPR_STAGGER_INCREMENT_MODE_DEFAULT 0x00000000 1439 1440 /* YDC_DDR_BIST :: BIST_CONFIGURATIONS_0 :: MPR_STAGGER_MODE [25:25] */ 1441 #define YDC_DDR_BIST_BIST_CONFIGURATIONS_0_MPR_STAGGER_MODE_MASK 0x02000000 1442 #define YDC_DDR_BIST_BIST_CONFIGURATIONS_0_MPR_STAGGER_MODE_ALIGN 0 1443 #define YDC_DDR_BIST_BIST_CONFIGURATIONS_0_MPR_STAGGER_MODE_BITS 1 1444 #define YDC_DDR_BIST_BIST_CONFIGURATIONS_0_MPR_STAGGER_MODE_SHIFT 25 1445 #define YDC_DDR_BIST_BIST_CONFIGURATIONS_0_MPR_STAGGER_MODE_DEFAULT 0x00000000 1446 1447 /* YDC_DDR_BIST :: BIST_CONFIGURATIONS_0 :: DATA_ADDR_MODE [24:24] */ 1448 #define YDC_DDR_BIST_BIST_CONFIGURATIONS_0_DATA_ADDR_MODE_MASK 0x01000000 1449 #define YDC_DDR_BIST_BIST_CONFIGURATIONS_0_DATA_ADDR_MODE_ALIGN 0 1450 #define YDC_DDR_BIST_BIST_CONFIGURATIONS_0_DATA_ADDR_MODE_BITS 1 1451 #define YDC_DDR_BIST_BIST_CONFIGURATIONS_0_DATA_ADDR_MODE_SHIFT 24 1452 #define YDC_DDR_BIST_BIST_CONFIGURATIONS_0_DATA_ADDR_MODE_DEFAULT 0x00000000 1453 1454 /* YDC_DDR_BIST :: BIST_CONFIGURATIONS_0 :: DATA_SHIFT_MODE [23:23] */ 1455 #define YDC_DDR_BIST_BIST_CONFIGURATIONS_0_DATA_SHIFT_MODE_MASK 0x00800000 1456 #define YDC_DDR_BIST_BIST_CONFIGURATIONS_0_DATA_SHIFT_MODE_ALIGN 0 1457 #define YDC_DDR_BIST_BIST_CONFIGURATIONS_0_DATA_SHIFT_MODE_BITS 1 1458 #define YDC_DDR_BIST_BIST_CONFIGURATIONS_0_DATA_SHIFT_MODE_SHIFT 23 1459 #define YDC_DDR_BIST_BIST_CONFIGURATIONS_0_DATA_SHIFT_MODE_DEFAULT 0x00000000 1460 1461 /* YDC_DDR_BIST :: BIST_CONFIGURATIONS_0 :: ADDRESS_SHIFT_MODE [22:22] */ 1462 #define YDC_DDR_BIST_BIST_CONFIGURATIONS_0_ADDRESS_SHIFT_MODE_MASK 0x00400000 1463 #define YDC_DDR_BIST_BIST_CONFIGURATIONS_0_ADDRESS_SHIFT_MODE_ALIGN 0 1464 #define YDC_DDR_BIST_BIST_CONFIGURATIONS_0_ADDRESS_SHIFT_MODE_BITS 1 1465 #define YDC_DDR_BIST_BIST_CONFIGURATIONS_0_ADDRESS_SHIFT_MODE_SHIFT 22 1466 #define YDC_DDR_BIST_BIST_CONFIGURATIONS_0_ADDRESS_SHIFT_MODE_DEFAULT 0x00000000 1467 1468 /* YDC_DDR_BIST :: BIST_CONFIGURATIONS_0 :: REPEAT_MODE [21:21] */ 1469 #define YDC_DDR_BIST_BIST_CONFIGURATIONS_0_REPEAT_MODE_MASK 0x00200000 1470 #define YDC_DDR_BIST_BIST_CONFIGURATIONS_0_REPEAT_MODE_ALIGN 0 1471 #define YDC_DDR_BIST_BIST_CONFIGURATIONS_0_REPEAT_MODE_BITS 1 1472 #define YDC_DDR_BIST_BIST_CONFIGURATIONS_0_REPEAT_MODE_SHIFT 21 1473 #define YDC_DDR_BIST_BIST_CONFIGURATIONS_0_REPEAT_MODE_DEFAULT 0x00000000 1474 1475 /* YDC_DDR_BIST :: BIST_CONFIGURATIONS_0 :: SINGLE_BANK_TEST [20:20] */ 1476 #define YDC_DDR_BIST_BIST_CONFIGURATIONS_0_SINGLE_BANK_TEST_MASK 0x00100000 1477 #define YDC_DDR_BIST_BIST_CONFIGURATIONS_0_SINGLE_BANK_TEST_ALIGN 0 1478 #define YDC_DDR_BIST_BIST_CONFIGURATIONS_0_SINGLE_BANK_TEST_BITS 1 1479 #define YDC_DDR_BIST_BIST_CONFIGURATIONS_0_SINGLE_BANK_TEST_SHIFT 20 1480 #define YDC_DDR_BIST_BIST_CONFIGURATIONS_0_SINGLE_BANK_TEST_DEFAULT 0x00000000 1481 1482 /* YDC_DDR_BIST :: BIST_CONFIGURATIONS_0 :: BG_INTERLEAVE [19:19] */ 1483 #define YDC_DDR_BIST_BIST_CONFIGURATIONS_0_BG_INTERLEAVE_MASK 0x00080000 1484 #define YDC_DDR_BIST_BIST_CONFIGURATIONS_0_BG_INTERLEAVE_ALIGN 0 1485 #define YDC_DDR_BIST_BIST_CONFIGURATIONS_0_BG_INTERLEAVE_BITS 1 1486 #define YDC_DDR_BIST_BIST_CONFIGURATIONS_0_BG_INTERLEAVE_SHIFT 19 1487 #define YDC_DDR_BIST_BIST_CONFIGURATIONS_0_BG_INTERLEAVE_DEFAULT 0x00000000 1488 1489 /* YDC_DDR_BIST :: BIST_CONFIGURATIONS_0 :: PRBS_MODE [18:18] */ 1490 #define YDC_DDR_BIST_BIST_CONFIGURATIONS_0_PRBS_MODE_MASK 0x00040000 1491 #define YDC_DDR_BIST_BIST_CONFIGURATIONS_0_PRBS_MODE_ALIGN 0 1492 #define YDC_DDR_BIST_BIST_CONFIGURATIONS_0_PRBS_MODE_BITS 1 1493 #define YDC_DDR_BIST_BIST_CONFIGURATIONS_0_PRBS_MODE_SHIFT 18 1494 #define YDC_DDR_BIST_BIST_CONFIGURATIONS_0_PRBS_MODE_DEFAULT 0x00000000 1495 1496 /* YDC_DDR_BIST :: BIST_CONFIGURATIONS_0 :: TWO_ADDR_MODE [17:17] */ 1497 #define YDC_DDR_BIST_BIST_CONFIGURATIONS_0_TWO_ADDR_MODE_MASK 0x00020000 1498 #define YDC_DDR_BIST_BIST_CONFIGURATIONS_0_TWO_ADDR_MODE_ALIGN 0 1499 #define YDC_DDR_BIST_BIST_CONFIGURATIONS_0_TWO_ADDR_MODE_BITS 1 1500 #define YDC_DDR_BIST_BIST_CONFIGURATIONS_0_TWO_ADDR_MODE_SHIFT 17 1501 #define YDC_DDR_BIST_BIST_CONFIGURATIONS_0_TWO_ADDR_MODE_DEFAULT 0x00000000 1502 1503 /* YDC_DDR_BIST :: BIST_CONFIGURATIONS_0 :: PATTERN_BIT_MODE [16:16] */ 1504 #define YDC_DDR_BIST_BIST_CONFIGURATIONS_0_PATTERN_BIT_MODE_MASK 0x00010000 1505 #define YDC_DDR_BIST_BIST_CONFIGURATIONS_0_PATTERN_BIT_MODE_ALIGN 0 1506 #define YDC_DDR_BIST_BIST_CONFIGURATIONS_0_PATTERN_BIT_MODE_BITS 1 1507 #define YDC_DDR_BIST_BIST_CONFIGURATIONS_0_PATTERN_BIT_MODE_SHIFT 16 1508 #define YDC_DDR_BIST_BIST_CONFIGURATIONS_0_PATTERN_BIT_MODE_DEFAULT 0x00000000 1509 1510 /* YDC_DDR_BIST :: BIST_CONFIGURATIONS_0 :: READ_WEIGHT [15:08] */ 1511 #define YDC_DDR_BIST_BIST_CONFIGURATIONS_0_READ_WEIGHT_MASK 0x0000ff00 1512 #define YDC_DDR_BIST_BIST_CONFIGURATIONS_0_READ_WEIGHT_ALIGN 0 1513 #define YDC_DDR_BIST_BIST_CONFIGURATIONS_0_READ_WEIGHT_BITS 8 1514 #define YDC_DDR_BIST_BIST_CONFIGURATIONS_0_READ_WEIGHT_SHIFT 8 1515 #define YDC_DDR_BIST_BIST_CONFIGURATIONS_0_READ_WEIGHT_DEFAULT 0x00000000 1516 1517 /* YDC_DDR_BIST :: BIST_CONFIGURATIONS_0 :: WRITE_WEIGHT [07:00] */ 1518 #define YDC_DDR_BIST_BIST_CONFIGURATIONS_0_WRITE_WEIGHT_MASK 0x000000ff 1519 #define YDC_DDR_BIST_BIST_CONFIGURATIONS_0_WRITE_WEIGHT_ALIGN 0 1520 #define YDC_DDR_BIST_BIST_CONFIGURATIONS_0_WRITE_WEIGHT_BITS 8 1521 #define YDC_DDR_BIST_BIST_CONFIGURATIONS_0_WRITE_WEIGHT_SHIFT 0 1522 #define YDC_DDR_BIST_BIST_CONFIGURATIONS_0_WRITE_WEIGHT_DEFAULT 0x00000000 1523 1524 1525 /**************************************************************************** 1526 * YDC_DDR_BIST :: BIST_CONFIGURATIONS_1 1527 */ 1528 /* YDC_DDR_BIST :: BIST_CONFIGURATIONS_1 :: reserved0 [31:04] */ 1529 #define YDC_DDR_BIST_BIST_CONFIGURATIONS_1_RESERVED0_MASK 0xfffffff0 1530 #define YDC_DDR_BIST_BIST_CONFIGURATIONS_1_RESERVED0_ALIGN 0 1531 #define YDC_DDR_BIST_BIST_CONFIGURATIONS_1_RESERVED0_BITS 28 1532 #define YDC_DDR_BIST_BIST_CONFIGURATIONS_1_RESERVED0_SHIFT 4 1533 #define YDC_DDR_BIST_BIST_CONFIGURATIONS_1_RESERVED0_DEFAULT 0x00000000 1534 1535 /* YDC_DDR_BIST :: BIST_CONFIGURATIONS_1 :: BIST_EN [03:03] */ 1536 #define YDC_DDR_BIST_BIST_CONFIGURATIONS_1_BIST_EN_MASK 0x00000008 1537 #define YDC_DDR_BIST_BIST_CONFIGURATIONS_1_BIST_EN_ALIGN 0 1538 #define YDC_DDR_BIST_BIST_CONFIGURATIONS_1_BIST_EN_BITS 1 1539 #define YDC_DDR_BIST_BIST_CONFIGURATIONS_1_BIST_EN_SHIFT 3 1540 #define YDC_DDR_BIST_BIST_CONFIGURATIONS_1_BIST_EN_DEFAULT 0x00000000 1541 1542 /* YDC_DDR_BIST :: BIST_CONFIGURATIONS_1 :: BIST_8_BANKS_CYCLE [02:02] */ 1543 #define YDC_DDR_BIST_BIST_CONFIGURATIONS_1_BIST_8_BANKS_CYCLE_MASK 0x00000004 1544 #define YDC_DDR_BIST_BIST_CONFIGURATIONS_1_BIST_8_BANKS_CYCLE_ALIGN 0 1545 #define YDC_DDR_BIST_BIST_CONFIGURATIONS_1_BIST_8_BANKS_CYCLE_BITS 1 1546 #define YDC_DDR_BIST_BIST_CONFIGURATIONS_1_BIST_8_BANKS_CYCLE_SHIFT 2 1547 #define YDC_DDR_BIST_BIST_CONFIGURATIONS_1_BIST_8_BANKS_CYCLE_DEFAULT 0x00000000 1548 1549 /* YDC_DDR_BIST :: BIST_CONFIGURATIONS_1 :: reserved1 [01:01] */ 1550 #define YDC_DDR_BIST_BIST_CONFIGURATIONS_1_RESERVED1_MASK 0x00000002 1551 #define YDC_DDR_BIST_BIST_CONFIGURATIONS_1_RESERVED1_ALIGN 0 1552 #define YDC_DDR_BIST_BIST_CONFIGURATIONS_1_RESERVED1_BITS 1 1553 #define YDC_DDR_BIST_BIST_CONFIGURATIONS_1_RESERVED1_SHIFT 1 1554 #define YDC_DDR_BIST_BIST_CONFIGURATIONS_1_RESERVED1_DEFAULT 0x00000000 1555 1556 /* YDC_DDR_BIST :: BIST_CONFIGURATIONS_1 :: ADDRESS_PRBS_MODE [00:00] */ 1557 #define YDC_DDR_BIST_BIST_CONFIGURATIONS_1_ADDRESS_PRBS_MODE_MASK 0x00000001 1558 #define YDC_DDR_BIST_BIST_CONFIGURATIONS_1_ADDRESS_PRBS_MODE_ALIGN 0 1559 #define YDC_DDR_BIST_BIST_CONFIGURATIONS_1_ADDRESS_PRBS_MODE_BITS 1 1560 #define YDC_DDR_BIST_BIST_CONFIGURATIONS_1_ADDRESS_PRBS_MODE_SHIFT 0 1561 #define YDC_DDR_BIST_BIST_CONFIGURATIONS_1_ADDRESS_PRBS_MODE_DEFAULT 0x00000000 1562 1563 1564 /**************************************************************************** 1565 * YDC_DDR_BIST :: BIST_PRBS_DATA_SEED_MSB_31_TO_0 1566 */ 1567 /* YDC_DDR_BIST :: BIST_PRBS_DATA_SEED_MSB_31_TO_0 :: VAL [31:00] */ 1568 #define YDC_DDR_BIST_BIST_PRBS_DATA_SEED_MSB_31_TO_0_VAL_MASK 0xffffffff 1569 #define YDC_DDR_BIST_BIST_PRBS_DATA_SEED_MSB_31_TO_0_VAL_ALIGN 0 1570 #define YDC_DDR_BIST_BIST_PRBS_DATA_SEED_MSB_31_TO_0_VAL_BITS 32 1571 #define YDC_DDR_BIST_BIST_PRBS_DATA_SEED_MSB_31_TO_0_VAL_SHIFT 0 1572 #define YDC_DDR_BIST_BIST_PRBS_DATA_SEED_MSB_31_TO_0_VAL_DEFAULT 0x00000000 1573 1574 1575 /**************************************************************************** 1576 * YDC_DDR_BIST :: BIST_PRBS_DATA_SEED_MSB_63_TO_32 1577 */ 1578 /* YDC_DDR_BIST :: BIST_PRBS_DATA_SEED_MSB_63_TO_32 :: VAL [31:00] */ 1579 #define YDC_DDR_BIST_BIST_PRBS_DATA_SEED_MSB_63_TO_32_VAL_MASK 0xffffffff 1580 #define YDC_DDR_BIST_BIST_PRBS_DATA_SEED_MSB_63_TO_32_VAL_ALIGN 0 1581 #define YDC_DDR_BIST_BIST_PRBS_DATA_SEED_MSB_63_TO_32_VAL_BITS 32 1582 #define YDC_DDR_BIST_BIST_PRBS_DATA_SEED_MSB_63_TO_32_VAL_SHIFT 0 1583 #define YDC_DDR_BIST_BIST_PRBS_DATA_SEED_MSB_63_TO_32_VAL_DEFAULT 0x00000000 1584 1585 1586 /**************************************************************************** 1587 * YDC_DDR_BIST :: BIST_PRBS_DATA_SEED_MSB_95_TO_64 1588 */ 1589 /* YDC_DDR_BIST :: BIST_PRBS_DATA_SEED_MSB_95_TO_64 :: VAL [31:00] */ 1590 #define YDC_DDR_BIST_BIST_PRBS_DATA_SEED_MSB_95_TO_64_VAL_MASK 0xffffffff 1591 #define YDC_DDR_BIST_BIST_PRBS_DATA_SEED_MSB_95_TO_64_VAL_ALIGN 0 1592 #define YDC_DDR_BIST_BIST_PRBS_DATA_SEED_MSB_95_TO_64_VAL_BITS 32 1593 #define YDC_DDR_BIST_BIST_PRBS_DATA_SEED_MSB_95_TO_64_VAL_SHIFT 0 1594 #define YDC_DDR_BIST_BIST_PRBS_DATA_SEED_MSB_95_TO_64_VAL_DEFAULT 0x00000000 1595 1596 1597 /**************************************************************************** 1598 * YDC_DDR_BIST :: BIST_PRBS_DATA_SEED_MSB_127_TO_96 1599 */ 1600 /* YDC_DDR_BIST :: BIST_PRBS_DATA_SEED_MSB_127_TO_96 :: VAL [31:00] */ 1601 #define YDC_DDR_BIST_BIST_PRBS_DATA_SEED_MSB_127_TO_96_VAL_MASK 0xffffffff 1602 #define YDC_DDR_BIST_BIST_PRBS_DATA_SEED_MSB_127_TO_96_VAL_ALIGN 0 1603 #define YDC_DDR_BIST_BIST_PRBS_DATA_SEED_MSB_127_TO_96_VAL_BITS 32 1604 #define YDC_DDR_BIST_BIST_PRBS_DATA_SEED_MSB_127_TO_96_VAL_SHIFT 0 1605 #define YDC_DDR_BIST_BIST_PRBS_DATA_SEED_MSB_127_TO_96_VAL_DEFAULT 0x00000000 1606 1607 1608 /**************************************************************************** 1609 * YDC_DDR_BIST :: BIST_PRBS_DATA_SEED_LSB_31_TO_0 1610 */ 1611 /* YDC_DDR_BIST :: BIST_PRBS_DATA_SEED_LSB_31_TO_0 :: VAL [31:00] */ 1612 #define YDC_DDR_BIST_BIST_PRBS_DATA_SEED_LSB_31_TO_0_VAL_MASK 0xffffffff 1613 #define YDC_DDR_BIST_BIST_PRBS_DATA_SEED_LSB_31_TO_0_VAL_ALIGN 0 1614 #define YDC_DDR_BIST_BIST_PRBS_DATA_SEED_LSB_31_TO_0_VAL_BITS 32 1615 #define YDC_DDR_BIST_BIST_PRBS_DATA_SEED_LSB_31_TO_0_VAL_SHIFT 0 1616 #define YDC_DDR_BIST_BIST_PRBS_DATA_SEED_LSB_31_TO_0_VAL_DEFAULT 0x00000000 1617 1618 1619 /**************************************************************************** 1620 * YDC_DDR_BIST :: BIST_PRBS_DATA_SEED_LSB_63_TO_32 1621 */ 1622 /* YDC_DDR_BIST :: BIST_PRBS_DATA_SEED_LSB_63_TO_32 :: VAL [31:00] */ 1623 #define YDC_DDR_BIST_BIST_PRBS_DATA_SEED_LSB_63_TO_32_VAL_MASK 0xffffffff 1624 #define YDC_DDR_BIST_BIST_PRBS_DATA_SEED_LSB_63_TO_32_VAL_ALIGN 0 1625 #define YDC_DDR_BIST_BIST_PRBS_DATA_SEED_LSB_63_TO_32_VAL_BITS 32 1626 #define YDC_DDR_BIST_BIST_PRBS_DATA_SEED_LSB_63_TO_32_VAL_SHIFT 0 1627 #define YDC_DDR_BIST_BIST_PRBS_DATA_SEED_LSB_63_TO_32_VAL_DEFAULT 0x00000000 1628 1629 1630 /**************************************************************************** 1631 * YDC_DDR_BIST :: BIST_PRBS_DATA_SEED_LSB_95_TO_64 1632 */ 1633 /* YDC_DDR_BIST :: BIST_PRBS_DATA_SEED_LSB_95_TO_64 :: VAL [31:00] */ 1634 #define YDC_DDR_BIST_BIST_PRBS_DATA_SEED_LSB_95_TO_64_VAL_MASK 0xffffffff 1635 #define YDC_DDR_BIST_BIST_PRBS_DATA_SEED_LSB_95_TO_64_VAL_ALIGN 0 1636 #define YDC_DDR_BIST_BIST_PRBS_DATA_SEED_LSB_95_TO_64_VAL_BITS 32 1637 #define YDC_DDR_BIST_BIST_PRBS_DATA_SEED_LSB_95_TO_64_VAL_SHIFT 0 1638 #define YDC_DDR_BIST_BIST_PRBS_DATA_SEED_LSB_95_TO_64_VAL_DEFAULT 0x00000000 1639 1640 1641 /**************************************************************************** 1642 * YDC_DDR_BIST :: BIST_PRBS_DATA_SEED_LSB_127_TO_96 1643 */ 1644 /* YDC_DDR_BIST :: BIST_PRBS_DATA_SEED_LSB_127_TO_96 :: VAL [31:00] */ 1645 #define YDC_DDR_BIST_BIST_PRBS_DATA_SEED_LSB_127_TO_96_VAL_MASK 0xffffffff 1646 #define YDC_DDR_BIST_BIST_PRBS_DATA_SEED_LSB_127_TO_96_VAL_ALIGN 0 1647 #define YDC_DDR_BIST_BIST_PRBS_DATA_SEED_LSB_127_TO_96_VAL_BITS 32 1648 #define YDC_DDR_BIST_BIST_PRBS_DATA_SEED_LSB_127_TO_96_VAL_SHIFT 0 1649 #define YDC_DDR_BIST_BIST_PRBS_DATA_SEED_LSB_127_TO_96_VAL_DEFAULT 0x00000000 1650 1651 1652 /**************************************************************************** 1653 * YDC_DDR_BIST :: BIST_PRBS_ADDR_SEED 1654 */ 1655 /* YDC_DDR_BIST :: BIST_PRBS_ADDR_SEED :: reserved0 [31:27] */ 1656 #define YDC_DDR_BIST_BIST_PRBS_ADDR_SEED_RESERVED0_MASK 0xf8000000 1657 #define YDC_DDR_BIST_BIST_PRBS_ADDR_SEED_RESERVED0_ALIGN 0 1658 #define YDC_DDR_BIST_BIST_PRBS_ADDR_SEED_RESERVED0_BITS 5 1659 #define YDC_DDR_BIST_BIST_PRBS_ADDR_SEED_RESERVED0_SHIFT 27 1660 #define YDC_DDR_BIST_BIST_PRBS_ADDR_SEED_RESERVED0_DEFAULT 0x00000000 1661 1662 /* YDC_DDR_BIST :: BIST_PRBS_ADDR_SEED :: VAL [26:00] */ 1663 #define YDC_DDR_BIST_BIST_PRBS_ADDR_SEED_VAL_MASK 0x07ffffff 1664 #define YDC_DDR_BIST_BIST_PRBS_ADDR_SEED_VAL_ALIGN 0 1665 #define YDC_DDR_BIST_BIST_PRBS_ADDR_SEED_VAL_BITS 27 1666 #define YDC_DDR_BIST_BIST_PRBS_ADDR_SEED_VAL_SHIFT 0 1667 #define YDC_DDR_BIST_BIST_PRBS_ADDR_SEED_VAL_DEFAULT 0x00000000 1668 1669 1670 /**************************************************************************** 1671 * YDC_DDR_BIST :: BIST_MPR_STAGGER_WEIGHTS 1672 */ 1673 /* YDC_DDR_BIST :: BIST_MPR_STAGGER_WEIGHTS :: BIST_MPR_STAGGER_WEIGHT_3 [31:24] */ 1674 #define YDC_DDR_BIST_BIST_MPR_STAGGER_WEIGHTS_BIST_MPR_STAGGER_WEIGHT_3_MASK 0xff000000 1675 #define YDC_DDR_BIST_BIST_MPR_STAGGER_WEIGHTS_BIST_MPR_STAGGER_WEIGHT_3_ALIGN 0 1676 #define YDC_DDR_BIST_BIST_MPR_STAGGER_WEIGHTS_BIST_MPR_STAGGER_WEIGHT_3_BITS 8 1677 #define YDC_DDR_BIST_BIST_MPR_STAGGER_WEIGHTS_BIST_MPR_STAGGER_WEIGHT_3_SHIFT 24 1678 #define YDC_DDR_BIST_BIST_MPR_STAGGER_WEIGHTS_BIST_MPR_STAGGER_WEIGHT_3_DEFAULT 0x00000001 1679 1680 /* YDC_DDR_BIST :: BIST_MPR_STAGGER_WEIGHTS :: BIST_MPR_STAGGER_WEIGHT_2 [23:16] */ 1681 #define YDC_DDR_BIST_BIST_MPR_STAGGER_WEIGHTS_BIST_MPR_STAGGER_WEIGHT_2_MASK 0x00ff0000 1682 #define YDC_DDR_BIST_BIST_MPR_STAGGER_WEIGHTS_BIST_MPR_STAGGER_WEIGHT_2_ALIGN 0 1683 #define YDC_DDR_BIST_BIST_MPR_STAGGER_WEIGHTS_BIST_MPR_STAGGER_WEIGHT_2_BITS 8 1684 #define YDC_DDR_BIST_BIST_MPR_STAGGER_WEIGHTS_BIST_MPR_STAGGER_WEIGHT_2_SHIFT 16 1685 #define YDC_DDR_BIST_BIST_MPR_STAGGER_WEIGHTS_BIST_MPR_STAGGER_WEIGHT_2_DEFAULT 0x00000001 1686 1687 /* YDC_DDR_BIST :: BIST_MPR_STAGGER_WEIGHTS :: BIST_MPR_STAGGER_WEIGHT_1 [15:08] */ 1688 #define YDC_DDR_BIST_BIST_MPR_STAGGER_WEIGHTS_BIST_MPR_STAGGER_WEIGHT_1_MASK 0x0000ff00 1689 #define YDC_DDR_BIST_BIST_MPR_STAGGER_WEIGHTS_BIST_MPR_STAGGER_WEIGHT_1_ALIGN 0 1690 #define YDC_DDR_BIST_BIST_MPR_STAGGER_WEIGHTS_BIST_MPR_STAGGER_WEIGHT_1_BITS 8 1691 #define YDC_DDR_BIST_BIST_MPR_STAGGER_WEIGHTS_BIST_MPR_STAGGER_WEIGHT_1_SHIFT 8 1692 #define YDC_DDR_BIST_BIST_MPR_STAGGER_WEIGHTS_BIST_MPR_STAGGER_WEIGHT_1_DEFAULT 0x00000001 1693 1694 /* YDC_DDR_BIST :: BIST_MPR_STAGGER_WEIGHTS :: BIST_MPR_STAGGER_WEIGHT_0 [07:00] */ 1695 #define YDC_DDR_BIST_BIST_MPR_STAGGER_WEIGHTS_BIST_MPR_STAGGER_WEIGHT_0_MASK 0x000000ff 1696 #define YDC_DDR_BIST_BIST_MPR_STAGGER_WEIGHTS_BIST_MPR_STAGGER_WEIGHT_0_ALIGN 0 1697 #define YDC_DDR_BIST_BIST_MPR_STAGGER_WEIGHTS_BIST_MPR_STAGGER_WEIGHT_0_BITS 8 1698 #define YDC_DDR_BIST_BIST_MPR_STAGGER_WEIGHTS_BIST_MPR_STAGGER_WEIGHT_0_SHIFT 0 1699 #define YDC_DDR_BIST_BIST_MPR_STAGGER_WEIGHTS_BIST_MPR_STAGGER_WEIGHT_0_DEFAULT 0x00000001 1700 1701 1702 /**************************************************************************** 1703 * YDC_DDR_BIST :: BIST_MPR_STAGGER_PATTERNS 1704 */ 1705 /* YDC_DDR_BIST :: BIST_MPR_STAGGER_PATTERNS :: BIST_MPR_STAGGER_PATTERN_3 [31:24] */ 1706 #define YDC_DDR_BIST_BIST_MPR_STAGGER_PATTERNS_BIST_MPR_STAGGER_PATTERN_3_MASK 0xff000000 1707 #define YDC_DDR_BIST_BIST_MPR_STAGGER_PATTERNS_BIST_MPR_STAGGER_PATTERN_3_ALIGN 0 1708 #define YDC_DDR_BIST_BIST_MPR_STAGGER_PATTERNS_BIST_MPR_STAGGER_PATTERN_3_BITS 8 1709 #define YDC_DDR_BIST_BIST_MPR_STAGGER_PATTERNS_BIST_MPR_STAGGER_PATTERN_3_SHIFT 24 1710 #define YDC_DDR_BIST_BIST_MPR_STAGGER_PATTERNS_BIST_MPR_STAGGER_PATTERN_3_DEFAULT 0x000000ff 1711 1712 /* YDC_DDR_BIST :: BIST_MPR_STAGGER_PATTERNS :: BIST_MPR_STAGGER_PATTERN_2 [23:16] */ 1713 #define YDC_DDR_BIST_BIST_MPR_STAGGER_PATTERNS_BIST_MPR_STAGGER_PATTERN_2_MASK 0x00ff0000 1714 #define YDC_DDR_BIST_BIST_MPR_STAGGER_PATTERNS_BIST_MPR_STAGGER_PATTERN_2_ALIGN 0 1715 #define YDC_DDR_BIST_BIST_MPR_STAGGER_PATTERNS_BIST_MPR_STAGGER_PATTERN_2_BITS 8 1716 #define YDC_DDR_BIST_BIST_MPR_STAGGER_PATTERNS_BIST_MPR_STAGGER_PATTERN_2_SHIFT 16 1717 #define YDC_DDR_BIST_BIST_MPR_STAGGER_PATTERNS_BIST_MPR_STAGGER_PATTERN_2_DEFAULT 0x00000000 1718 1719 /* YDC_DDR_BIST :: BIST_MPR_STAGGER_PATTERNS :: BIST_MPR_STAGGER_PATTERN_1 [15:08] */ 1720 #define YDC_DDR_BIST_BIST_MPR_STAGGER_PATTERNS_BIST_MPR_STAGGER_PATTERN_1_MASK 0x0000ff00 1721 #define YDC_DDR_BIST_BIST_MPR_STAGGER_PATTERNS_BIST_MPR_STAGGER_PATTERN_1_ALIGN 0 1722 #define YDC_DDR_BIST_BIST_MPR_STAGGER_PATTERNS_BIST_MPR_STAGGER_PATTERN_1_BITS 8 1723 #define YDC_DDR_BIST_BIST_MPR_STAGGER_PATTERNS_BIST_MPR_STAGGER_PATTERN_1_SHIFT 8 1724 #define YDC_DDR_BIST_BIST_MPR_STAGGER_PATTERNS_BIST_MPR_STAGGER_PATTERN_1_DEFAULT 0x000000ff 1725 1726 /* YDC_DDR_BIST :: BIST_MPR_STAGGER_PATTERNS :: BIST_MPR_STAGGER_PATTERN_0 [07:00] */ 1727 #define YDC_DDR_BIST_BIST_MPR_STAGGER_PATTERNS_BIST_MPR_STAGGER_PATTERN_0_MASK 0x000000ff 1728 #define YDC_DDR_BIST_BIST_MPR_STAGGER_PATTERNS_BIST_MPR_STAGGER_PATTERN_0_ALIGN 0 1729 #define YDC_DDR_BIST_BIST_MPR_STAGGER_PATTERNS_BIST_MPR_STAGGER_PATTERN_0_BITS 8 1730 #define YDC_DDR_BIST_BIST_MPR_STAGGER_PATTERNS_BIST_MPR_STAGGER_PATTERN_0_SHIFT 0 1731 #define YDC_DDR_BIST_BIST_MPR_STAGGER_PATTERNS_BIST_MPR_STAGGER_PATTERN_0_DEFAULT 0x00000000 1732 1733 1734 /**************************************************************************** 1735 * YDC_DDR_BIST :: BIST_PATTERN_REPETITION_0 1736 */ 1737 /* YDC_DDR_BIST :: BIST_PATTERN_REPETITION_0 :: NUM_OF_REPEAT_3 [31:24] */ 1738 #define YDC_DDR_BIST_BIST_PATTERN_REPETITION_0_NUM_OF_REPEAT_3_MASK 0xff000000 1739 #define YDC_DDR_BIST_BIST_PATTERN_REPETITION_0_NUM_OF_REPEAT_3_ALIGN 0 1740 #define YDC_DDR_BIST_BIST_PATTERN_REPETITION_0_NUM_OF_REPEAT_3_BITS 8 1741 #define YDC_DDR_BIST_BIST_PATTERN_REPETITION_0_NUM_OF_REPEAT_3_SHIFT 24 1742 #define YDC_DDR_BIST_BIST_PATTERN_REPETITION_0_NUM_OF_REPEAT_3_DEFAULT 0x000000ff 1743 1744 /* YDC_DDR_BIST :: BIST_PATTERN_REPETITION_0 :: NUM_OF_REPEAT_2 [23:16] */ 1745 #define YDC_DDR_BIST_BIST_PATTERN_REPETITION_0_NUM_OF_REPEAT_2_MASK 0x00ff0000 1746 #define YDC_DDR_BIST_BIST_PATTERN_REPETITION_0_NUM_OF_REPEAT_2_ALIGN 0 1747 #define YDC_DDR_BIST_BIST_PATTERN_REPETITION_0_NUM_OF_REPEAT_2_BITS 8 1748 #define YDC_DDR_BIST_BIST_PATTERN_REPETITION_0_NUM_OF_REPEAT_2_SHIFT 16 1749 #define YDC_DDR_BIST_BIST_PATTERN_REPETITION_0_NUM_OF_REPEAT_2_DEFAULT 0x00000000 1750 1751 /* YDC_DDR_BIST :: BIST_PATTERN_REPETITION_0 :: NUM_OF_REPEAT_1 [15:08] */ 1752 #define YDC_DDR_BIST_BIST_PATTERN_REPETITION_0_NUM_OF_REPEAT_1_MASK 0x0000ff00 1753 #define YDC_DDR_BIST_BIST_PATTERN_REPETITION_0_NUM_OF_REPEAT_1_ALIGN 0 1754 #define YDC_DDR_BIST_BIST_PATTERN_REPETITION_0_NUM_OF_REPEAT_1_BITS 8 1755 #define YDC_DDR_BIST_BIST_PATTERN_REPETITION_0_NUM_OF_REPEAT_1_SHIFT 8 1756 #define YDC_DDR_BIST_BIST_PATTERN_REPETITION_0_NUM_OF_REPEAT_1_DEFAULT 0x000000ff 1757 1758 /* YDC_DDR_BIST :: BIST_PATTERN_REPETITION_0 :: NUM_OF_REPEAT_0 [07:00] */ 1759 #define YDC_DDR_BIST_BIST_PATTERN_REPETITION_0_NUM_OF_REPEAT_0_MASK 0x000000ff 1760 #define YDC_DDR_BIST_BIST_PATTERN_REPETITION_0_NUM_OF_REPEAT_0_ALIGN 0 1761 #define YDC_DDR_BIST_BIST_PATTERN_REPETITION_0_NUM_OF_REPEAT_0_BITS 8 1762 #define YDC_DDR_BIST_BIST_PATTERN_REPETITION_0_NUM_OF_REPEAT_0_SHIFT 0 1763 #define YDC_DDR_BIST_BIST_PATTERN_REPETITION_0_NUM_OF_REPEAT_0_DEFAULT 0x00000000 1764 1765 1766 /**************************************************************************** 1767 * YDC_DDR_BIST :: BIST_PATTERN_REPETITION_1 1768 */ 1769 /* YDC_DDR_BIST :: BIST_PATTERN_REPETITION_1 :: NUM_OF_REPEAT_7 [31:24] */ 1770 #define YDC_DDR_BIST_BIST_PATTERN_REPETITION_1_NUM_OF_REPEAT_7_MASK 0xff000000 1771 #define YDC_DDR_BIST_BIST_PATTERN_REPETITION_1_NUM_OF_REPEAT_7_ALIGN 0 1772 #define YDC_DDR_BIST_BIST_PATTERN_REPETITION_1_NUM_OF_REPEAT_7_BITS 8 1773 #define YDC_DDR_BIST_BIST_PATTERN_REPETITION_1_NUM_OF_REPEAT_7_SHIFT 24 1774 #define YDC_DDR_BIST_BIST_PATTERN_REPETITION_1_NUM_OF_REPEAT_7_DEFAULT 0x000000ff 1775 1776 /* YDC_DDR_BIST :: BIST_PATTERN_REPETITION_1 :: NUM_OF_REPEAT_6 [23:16] */ 1777 #define YDC_DDR_BIST_BIST_PATTERN_REPETITION_1_NUM_OF_REPEAT_6_MASK 0x00ff0000 1778 #define YDC_DDR_BIST_BIST_PATTERN_REPETITION_1_NUM_OF_REPEAT_6_ALIGN 0 1779 #define YDC_DDR_BIST_BIST_PATTERN_REPETITION_1_NUM_OF_REPEAT_6_BITS 8 1780 #define YDC_DDR_BIST_BIST_PATTERN_REPETITION_1_NUM_OF_REPEAT_6_SHIFT 16 1781 #define YDC_DDR_BIST_BIST_PATTERN_REPETITION_1_NUM_OF_REPEAT_6_DEFAULT 0x00000000 1782 1783 /* YDC_DDR_BIST :: BIST_PATTERN_REPETITION_1 :: NUM_OF_REPEAT_5 [15:08] */ 1784 #define YDC_DDR_BIST_BIST_PATTERN_REPETITION_1_NUM_OF_REPEAT_5_MASK 0x0000ff00 1785 #define YDC_DDR_BIST_BIST_PATTERN_REPETITION_1_NUM_OF_REPEAT_5_ALIGN 0 1786 #define YDC_DDR_BIST_BIST_PATTERN_REPETITION_1_NUM_OF_REPEAT_5_BITS 8 1787 #define YDC_DDR_BIST_BIST_PATTERN_REPETITION_1_NUM_OF_REPEAT_5_SHIFT 8 1788 #define YDC_DDR_BIST_BIST_PATTERN_REPETITION_1_NUM_OF_REPEAT_5_DEFAULT 0x000000ff 1789 1790 /* YDC_DDR_BIST :: BIST_PATTERN_REPETITION_1 :: NUM_OF_REPEAT_4 [07:00] */ 1791 #define YDC_DDR_BIST_BIST_PATTERN_REPETITION_1_NUM_OF_REPEAT_4_MASK 0x000000ff 1792 #define YDC_DDR_BIST_BIST_PATTERN_REPETITION_1_NUM_OF_REPEAT_4_ALIGN 0 1793 #define YDC_DDR_BIST_BIST_PATTERN_REPETITION_1_NUM_OF_REPEAT_4_BITS 8 1794 #define YDC_DDR_BIST_BIST_PATTERN_REPETITION_1_NUM_OF_REPEAT_4_SHIFT 0 1795 #define YDC_DDR_BIST_BIST_PATTERN_REPETITION_1_NUM_OF_REPEAT_4_DEFAULT 0x00000000 1796 1797 1798 /**************************************************************************** 1799 * YDC_DDR_BIST :: BIST_REPEAT_PATTERN_1_MSB_31_TO_0 1800 */ 1801 /* YDC_DDR_BIST :: BIST_REPEAT_PATTERN_1_MSB_31_TO_0 :: VAL [31:00] */ 1802 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_1_MSB_31_TO_0_VAL_MASK 0xffffffff 1803 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_1_MSB_31_TO_0_VAL_ALIGN 0 1804 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_1_MSB_31_TO_0_VAL_BITS 32 1805 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_1_MSB_31_TO_0_VAL_SHIFT 0 1806 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_1_MSB_31_TO_0_VAL_DEFAULT 0x00000000 1807 1808 1809 /**************************************************************************** 1810 * YDC_DDR_BIST :: BIST_REPEAT_PATTERN_1_MSB_63_TO_32 1811 */ 1812 /* YDC_DDR_BIST :: BIST_REPEAT_PATTERN_1_MSB_63_TO_32 :: VAL [31:00] */ 1813 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_1_MSB_63_TO_32_VAL_MASK 0xffffffff 1814 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_1_MSB_63_TO_32_VAL_ALIGN 0 1815 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_1_MSB_63_TO_32_VAL_BITS 32 1816 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_1_MSB_63_TO_32_VAL_SHIFT 0 1817 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_1_MSB_63_TO_32_VAL_DEFAULT 0x00000000 1818 1819 1820 /**************************************************************************** 1821 * YDC_DDR_BIST :: BIST_REPEAT_PATTERN_1_MSB_95_TO_64 1822 */ 1823 /* YDC_DDR_BIST :: BIST_REPEAT_PATTERN_1_MSB_95_TO_64 :: VAL [31:00] */ 1824 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_1_MSB_95_TO_64_VAL_MASK 0xffffffff 1825 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_1_MSB_95_TO_64_VAL_ALIGN 0 1826 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_1_MSB_95_TO_64_VAL_BITS 32 1827 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_1_MSB_95_TO_64_VAL_SHIFT 0 1828 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_1_MSB_95_TO_64_VAL_DEFAULT 0x00000000 1829 1830 1831 /**************************************************************************** 1832 * YDC_DDR_BIST :: BIST_REPEAT_PATTERN_1_MSB_127_TO_96 1833 */ 1834 /* YDC_DDR_BIST :: BIST_REPEAT_PATTERN_1_MSB_127_TO_96 :: VAL [31:00] */ 1835 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_1_MSB_127_TO_96_VAL_MASK 0xffffffff 1836 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_1_MSB_127_TO_96_VAL_ALIGN 0 1837 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_1_MSB_127_TO_96_VAL_BITS 32 1838 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_1_MSB_127_TO_96_VAL_SHIFT 0 1839 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_1_MSB_127_TO_96_VAL_DEFAULT 0x00000000 1840 1841 1842 /**************************************************************************** 1843 * YDC_DDR_BIST :: BIST_REPEAT_PATTERN_1_LSB_31_TO_0 1844 */ 1845 /* YDC_DDR_BIST :: BIST_REPEAT_PATTERN_1_LSB_31_TO_0 :: VAL [31:00] */ 1846 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_1_LSB_31_TO_0_VAL_MASK 0xffffffff 1847 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_1_LSB_31_TO_0_VAL_ALIGN 0 1848 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_1_LSB_31_TO_0_VAL_BITS 32 1849 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_1_LSB_31_TO_0_VAL_SHIFT 0 1850 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_1_LSB_31_TO_0_VAL_DEFAULT 0x00000000 1851 1852 1853 /**************************************************************************** 1854 * YDC_DDR_BIST :: BIST_REPEAT_PATTERN_1_LSB_63_TO_32 1855 */ 1856 /* YDC_DDR_BIST :: BIST_REPEAT_PATTERN_1_LSB_63_TO_32 :: VAL [31:00] */ 1857 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_1_LSB_63_TO_32_VAL_MASK 0xffffffff 1858 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_1_LSB_63_TO_32_VAL_ALIGN 0 1859 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_1_LSB_63_TO_32_VAL_BITS 32 1860 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_1_LSB_63_TO_32_VAL_SHIFT 0 1861 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_1_LSB_63_TO_32_VAL_DEFAULT 0x00000000 1862 1863 1864 /**************************************************************************** 1865 * YDC_DDR_BIST :: BIST_REPEAT_PATTERN_1_LSB_95_TO_64 1866 */ 1867 /* YDC_DDR_BIST :: BIST_REPEAT_PATTERN_1_LSB_95_TO_64 :: VAL [31:00] */ 1868 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_1_LSB_95_TO_64_VAL_MASK 0xffffffff 1869 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_1_LSB_95_TO_64_VAL_ALIGN 0 1870 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_1_LSB_95_TO_64_VAL_BITS 32 1871 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_1_LSB_95_TO_64_VAL_SHIFT 0 1872 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_1_LSB_95_TO_64_VAL_DEFAULT 0x00000000 1873 1874 1875 /**************************************************************************** 1876 * YDC_DDR_BIST :: BIST_REPEAT_PATTERN_1_LSB_127_TO_96 1877 */ 1878 /* YDC_DDR_BIST :: BIST_REPEAT_PATTERN_1_LSB_127_TO_96 :: VAL [31:00] */ 1879 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_1_LSB_127_TO_96_VAL_MASK 0xffffffff 1880 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_1_LSB_127_TO_96_VAL_ALIGN 0 1881 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_1_LSB_127_TO_96_VAL_BITS 32 1882 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_1_LSB_127_TO_96_VAL_SHIFT 0 1883 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_1_LSB_127_TO_96_VAL_DEFAULT 0x00000000 1884 1885 1886 /**************************************************************************** 1887 * YDC_DDR_BIST :: BIST_REPEAT_PATTERN_2_MSB_31_TO_0 1888 */ 1889 /* YDC_DDR_BIST :: BIST_REPEAT_PATTERN_2_MSB_31_TO_0 :: VAL [31:00] */ 1890 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_2_MSB_31_TO_0_VAL_MASK 0xffffffff 1891 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_2_MSB_31_TO_0_VAL_ALIGN 0 1892 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_2_MSB_31_TO_0_VAL_BITS 32 1893 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_2_MSB_31_TO_0_VAL_SHIFT 0 1894 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_2_MSB_31_TO_0_VAL_DEFAULT 0x00000000 1895 1896 1897 /**************************************************************************** 1898 * YDC_DDR_BIST :: BIST_REPEAT_PATTERN_2_MSB_63_TO_32 1899 */ 1900 /* YDC_DDR_BIST :: BIST_REPEAT_PATTERN_2_MSB_63_TO_32 :: VAL [31:00] */ 1901 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_2_MSB_63_TO_32_VAL_MASK 0xffffffff 1902 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_2_MSB_63_TO_32_VAL_ALIGN 0 1903 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_2_MSB_63_TO_32_VAL_BITS 32 1904 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_2_MSB_63_TO_32_VAL_SHIFT 0 1905 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_2_MSB_63_TO_32_VAL_DEFAULT 0x00000000 1906 1907 1908 /**************************************************************************** 1909 * YDC_DDR_BIST :: BIST_REPEAT_PATTERN_2_MSB_95_TO_64 1910 */ 1911 /* YDC_DDR_BIST :: BIST_REPEAT_PATTERN_2_MSB_95_TO_64 :: VAL [31:00] */ 1912 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_2_MSB_95_TO_64_VAL_MASK 0xffffffff 1913 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_2_MSB_95_TO_64_VAL_ALIGN 0 1914 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_2_MSB_95_TO_64_VAL_BITS 32 1915 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_2_MSB_95_TO_64_VAL_SHIFT 0 1916 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_2_MSB_95_TO_64_VAL_DEFAULT 0x00000000 1917 1918 1919 /**************************************************************************** 1920 * YDC_DDR_BIST :: BIST_REPEAT_PATTERN_2_MSB_127_TO_96 1921 */ 1922 /* YDC_DDR_BIST :: BIST_REPEAT_PATTERN_2_MSB_127_TO_96 :: VAL [31:00] */ 1923 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_2_MSB_127_TO_96_VAL_MASK 0xffffffff 1924 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_2_MSB_127_TO_96_VAL_ALIGN 0 1925 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_2_MSB_127_TO_96_VAL_BITS 32 1926 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_2_MSB_127_TO_96_VAL_SHIFT 0 1927 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_2_MSB_127_TO_96_VAL_DEFAULT 0x00000000 1928 1929 1930 /**************************************************************************** 1931 * YDC_DDR_BIST :: BIST_REPEAT_PATTERN_2_LSB_31_TO_0 1932 */ 1933 /* YDC_DDR_BIST :: BIST_REPEAT_PATTERN_2_LSB_31_TO_0 :: VAL [31:00] */ 1934 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_2_LSB_31_TO_0_VAL_MASK 0xffffffff 1935 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_2_LSB_31_TO_0_VAL_ALIGN 0 1936 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_2_LSB_31_TO_0_VAL_BITS 32 1937 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_2_LSB_31_TO_0_VAL_SHIFT 0 1938 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_2_LSB_31_TO_0_VAL_DEFAULT 0x00000000 1939 1940 1941 /**************************************************************************** 1942 * YDC_DDR_BIST :: BIST_REPEAT_PATTERN_2_LSB_63_TO_32 1943 */ 1944 /* YDC_DDR_BIST :: BIST_REPEAT_PATTERN_2_LSB_63_TO_32 :: VAL [31:00] */ 1945 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_2_LSB_63_TO_32_VAL_MASK 0xffffffff 1946 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_2_LSB_63_TO_32_VAL_ALIGN 0 1947 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_2_LSB_63_TO_32_VAL_BITS 32 1948 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_2_LSB_63_TO_32_VAL_SHIFT 0 1949 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_2_LSB_63_TO_32_VAL_DEFAULT 0x00000000 1950 1951 1952 /**************************************************************************** 1953 * YDC_DDR_BIST :: BIST_REPEAT_PATTERN_2_LSB_95_TO_64 1954 */ 1955 /* YDC_DDR_BIST :: BIST_REPEAT_PATTERN_2_LSB_95_TO_64 :: VAL [31:00] */ 1956 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_2_LSB_95_TO_64_VAL_MASK 0xffffffff 1957 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_2_LSB_95_TO_64_VAL_ALIGN 0 1958 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_2_LSB_95_TO_64_VAL_BITS 32 1959 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_2_LSB_95_TO_64_VAL_SHIFT 0 1960 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_2_LSB_95_TO_64_VAL_DEFAULT 0x00000000 1961 1962 1963 /**************************************************************************** 1964 * YDC_DDR_BIST :: BIST_REPEAT_PATTERN_2_LSB_127_TO_96 1965 */ 1966 /* YDC_DDR_BIST :: BIST_REPEAT_PATTERN_2_LSB_127_TO_96 :: VAL [31:00] */ 1967 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_2_LSB_127_TO_96_VAL_MASK 0xffffffff 1968 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_2_LSB_127_TO_96_VAL_ALIGN 0 1969 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_2_LSB_127_TO_96_VAL_BITS 32 1970 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_2_LSB_127_TO_96_VAL_SHIFT 0 1971 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_2_LSB_127_TO_96_VAL_DEFAULT 0x00000000 1972 1973 1974 /**************************************************************************** 1975 * YDC_DDR_BIST :: BIST_REPEAT_PATTERN_3_MSB_31_TO_0 1976 */ 1977 /* YDC_DDR_BIST :: BIST_REPEAT_PATTERN_3_MSB_31_TO_0 :: VAL [31:00] */ 1978 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_3_MSB_31_TO_0_VAL_MASK 0xffffffff 1979 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_3_MSB_31_TO_0_VAL_ALIGN 0 1980 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_3_MSB_31_TO_0_VAL_BITS 32 1981 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_3_MSB_31_TO_0_VAL_SHIFT 0 1982 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_3_MSB_31_TO_0_VAL_DEFAULT 0x00000000 1983 1984 1985 /**************************************************************************** 1986 * YDC_DDR_BIST :: BIST_REPEAT_PATTERN_3_MSB_63_TO_32 1987 */ 1988 /* YDC_DDR_BIST :: BIST_REPEAT_PATTERN_3_MSB_63_TO_32 :: VAL [31:00] */ 1989 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_3_MSB_63_TO_32_VAL_MASK 0xffffffff 1990 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_3_MSB_63_TO_32_VAL_ALIGN 0 1991 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_3_MSB_63_TO_32_VAL_BITS 32 1992 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_3_MSB_63_TO_32_VAL_SHIFT 0 1993 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_3_MSB_63_TO_32_VAL_DEFAULT 0x00000000 1994 1995 1996 /**************************************************************************** 1997 * YDC_DDR_BIST :: BIST_REPEAT_PATTERN_3_MSB_95_TO_64 1998 */ 1999 /* YDC_DDR_BIST :: BIST_REPEAT_PATTERN_3_MSB_95_TO_64 :: VAL [31:00] */ 2000 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_3_MSB_95_TO_64_VAL_MASK 0xffffffff 2001 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_3_MSB_95_TO_64_VAL_ALIGN 0 2002 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_3_MSB_95_TO_64_VAL_BITS 32 2003 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_3_MSB_95_TO_64_VAL_SHIFT 0 2004 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_3_MSB_95_TO_64_VAL_DEFAULT 0x00000000 2005 2006 2007 /**************************************************************************** 2008 * YDC_DDR_BIST :: BIST_REPEAT_PATTERN_3_MSB_127_TO_96 2009 */ 2010 /* YDC_DDR_BIST :: BIST_REPEAT_PATTERN_3_MSB_127_TO_96 :: VAL [31:00] */ 2011 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_3_MSB_127_TO_96_VAL_MASK 0xffffffff 2012 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_3_MSB_127_TO_96_VAL_ALIGN 0 2013 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_3_MSB_127_TO_96_VAL_BITS 32 2014 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_3_MSB_127_TO_96_VAL_SHIFT 0 2015 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_3_MSB_127_TO_96_VAL_DEFAULT 0x00000000 2016 2017 2018 /**************************************************************************** 2019 * YDC_DDR_BIST :: BIST_REPEAT_PATTERN_3_LSB_31_TO_0 2020 */ 2021 /* YDC_DDR_BIST :: BIST_REPEAT_PATTERN_3_LSB_31_TO_0 :: VAL [31:00] */ 2022 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_3_LSB_31_TO_0_VAL_MASK 0xffffffff 2023 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_3_LSB_31_TO_0_VAL_ALIGN 0 2024 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_3_LSB_31_TO_0_VAL_BITS 32 2025 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_3_LSB_31_TO_0_VAL_SHIFT 0 2026 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_3_LSB_31_TO_0_VAL_DEFAULT 0x00000000 2027 2028 2029 /**************************************************************************** 2030 * YDC_DDR_BIST :: BIST_REPEAT_PATTERN_3_LSB_63_TO_32 2031 */ 2032 /* YDC_DDR_BIST :: BIST_REPEAT_PATTERN_3_LSB_63_TO_32 :: VAL [31:00] */ 2033 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_3_LSB_63_TO_32_VAL_MASK 0xffffffff 2034 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_3_LSB_63_TO_32_VAL_ALIGN 0 2035 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_3_LSB_63_TO_32_VAL_BITS 32 2036 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_3_LSB_63_TO_32_VAL_SHIFT 0 2037 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_3_LSB_63_TO_32_VAL_DEFAULT 0x00000000 2038 2039 2040 /**************************************************************************** 2041 * YDC_DDR_BIST :: BIST_REPEAT_PATTERN_3_LSB_95_TO_64 2042 */ 2043 /* YDC_DDR_BIST :: BIST_REPEAT_PATTERN_3_LSB_95_TO_64 :: VAL [31:00] */ 2044 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_3_LSB_95_TO_64_VAL_MASK 0xffffffff 2045 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_3_LSB_95_TO_64_VAL_ALIGN 0 2046 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_3_LSB_95_TO_64_VAL_BITS 32 2047 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_3_LSB_95_TO_64_VAL_SHIFT 0 2048 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_3_LSB_95_TO_64_VAL_DEFAULT 0x00000000 2049 2050 2051 /**************************************************************************** 2052 * YDC_DDR_BIST :: BIST_REPEAT_PATTERN_3_LSB_127_TO_96 2053 */ 2054 /* YDC_DDR_BIST :: BIST_REPEAT_PATTERN_3_LSB_127_TO_96 :: VAL [31:00] */ 2055 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_3_LSB_127_TO_96_VAL_MASK 0xffffffff 2056 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_3_LSB_127_TO_96_VAL_ALIGN 0 2057 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_3_LSB_127_TO_96_VAL_BITS 32 2058 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_3_LSB_127_TO_96_VAL_SHIFT 0 2059 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_3_LSB_127_TO_96_VAL_DEFAULT 0x00000000 2060 2061 2062 /**************************************************************************** 2063 * YDC_DDR_BIST :: BIST_REPEAT_PATTERN_4_MSB_31_TO_0 2064 */ 2065 /* YDC_DDR_BIST :: BIST_REPEAT_PATTERN_4_MSB_31_TO_0 :: VAL [31:00] */ 2066 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_4_MSB_31_TO_0_VAL_MASK 0xffffffff 2067 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_4_MSB_31_TO_0_VAL_ALIGN 0 2068 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_4_MSB_31_TO_0_VAL_BITS 32 2069 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_4_MSB_31_TO_0_VAL_SHIFT 0 2070 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_4_MSB_31_TO_0_VAL_DEFAULT 0x00000000 2071 2072 2073 /**************************************************************************** 2074 * YDC_DDR_BIST :: BIST_REPEAT_PATTERN_4_MSB_63_TO_32 2075 */ 2076 /* YDC_DDR_BIST :: BIST_REPEAT_PATTERN_4_MSB_63_TO_32 :: VAL [31:00] */ 2077 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_4_MSB_63_TO_32_VAL_MASK 0xffffffff 2078 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_4_MSB_63_TO_32_VAL_ALIGN 0 2079 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_4_MSB_63_TO_32_VAL_BITS 32 2080 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_4_MSB_63_TO_32_VAL_SHIFT 0 2081 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_4_MSB_63_TO_32_VAL_DEFAULT 0x00000000 2082 2083 2084 /**************************************************************************** 2085 * YDC_DDR_BIST :: BIST_REPEAT_PATTERN_4_MSB_95_TO_64 2086 */ 2087 /* YDC_DDR_BIST :: BIST_REPEAT_PATTERN_4_MSB_95_TO_64 :: VAL [31:00] */ 2088 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_4_MSB_95_TO_64_VAL_MASK 0xffffffff 2089 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_4_MSB_95_TO_64_VAL_ALIGN 0 2090 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_4_MSB_95_TO_64_VAL_BITS 32 2091 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_4_MSB_95_TO_64_VAL_SHIFT 0 2092 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_4_MSB_95_TO_64_VAL_DEFAULT 0x00000000 2093 2094 2095 /**************************************************************************** 2096 * YDC_DDR_BIST :: BIST_REPEAT_PATTERN_4_MSB_127_TO_96 2097 */ 2098 /* YDC_DDR_BIST :: BIST_REPEAT_PATTERN_4_MSB_127_TO_96 :: VAL [31:00] */ 2099 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_4_MSB_127_TO_96_VAL_MASK 0xffffffff 2100 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_4_MSB_127_TO_96_VAL_ALIGN 0 2101 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_4_MSB_127_TO_96_VAL_BITS 32 2102 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_4_MSB_127_TO_96_VAL_SHIFT 0 2103 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_4_MSB_127_TO_96_VAL_DEFAULT 0x00000000 2104 2105 2106 /**************************************************************************** 2107 * YDC_DDR_BIST :: BIST_REPEAT_PATTERN_4_LSB_31_TO_0 2108 */ 2109 /* YDC_DDR_BIST :: BIST_REPEAT_PATTERN_4_LSB_31_TO_0 :: VAL [31:00] */ 2110 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_4_LSB_31_TO_0_VAL_MASK 0xffffffff 2111 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_4_LSB_31_TO_0_VAL_ALIGN 0 2112 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_4_LSB_31_TO_0_VAL_BITS 32 2113 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_4_LSB_31_TO_0_VAL_SHIFT 0 2114 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_4_LSB_31_TO_0_VAL_DEFAULT 0x00000000 2115 2116 2117 /**************************************************************************** 2118 * YDC_DDR_BIST :: BIST_REPEAT_PATTERN_4_LSB_63_TO_32 2119 */ 2120 /* YDC_DDR_BIST :: BIST_REPEAT_PATTERN_4_LSB_63_TO_32 :: VAL [31:00] */ 2121 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_4_LSB_63_TO_32_VAL_MASK 0xffffffff 2122 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_4_LSB_63_TO_32_VAL_ALIGN 0 2123 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_4_LSB_63_TO_32_VAL_BITS 32 2124 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_4_LSB_63_TO_32_VAL_SHIFT 0 2125 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_4_LSB_63_TO_32_VAL_DEFAULT 0x00000000 2126 2127 2128 /**************************************************************************** 2129 * YDC_DDR_BIST :: BIST_REPEAT_PATTERN_4_LSB_95_TO_64 2130 */ 2131 /* YDC_DDR_BIST :: BIST_REPEAT_PATTERN_4_LSB_95_TO_64 :: VAL [31:00] */ 2132 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_4_LSB_95_TO_64_VAL_MASK 0xffffffff 2133 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_4_LSB_95_TO_64_VAL_ALIGN 0 2134 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_4_LSB_95_TO_64_VAL_BITS 32 2135 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_4_LSB_95_TO_64_VAL_SHIFT 0 2136 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_4_LSB_95_TO_64_VAL_DEFAULT 0x00000000 2137 2138 2139 /**************************************************************************** 2140 * YDC_DDR_BIST :: BIST_REPEAT_PATTERN_4_LSB_127_TO_96 2141 */ 2142 /* YDC_DDR_BIST :: BIST_REPEAT_PATTERN_4_LSB_127_TO_96 :: VAL [31:00] */ 2143 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_4_LSB_127_TO_96_VAL_MASK 0xffffffff 2144 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_4_LSB_127_TO_96_VAL_ALIGN 0 2145 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_4_LSB_127_TO_96_VAL_BITS 32 2146 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_4_LSB_127_TO_96_VAL_SHIFT 0 2147 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_4_LSB_127_TO_96_VAL_DEFAULT 0x00000000 2148 2149 2150 /**************************************************************************** 2151 * YDC_DDR_BIST :: BIST_REPEAT_PATTERN_5_MSB_31_TO_0 2152 */ 2153 /* YDC_DDR_BIST :: BIST_REPEAT_PATTERN_5_MSB_31_TO_0 :: VAL [31:00] */ 2154 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_5_MSB_31_TO_0_VAL_MASK 0xffffffff 2155 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_5_MSB_31_TO_0_VAL_ALIGN 0 2156 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_5_MSB_31_TO_0_VAL_BITS 32 2157 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_5_MSB_31_TO_0_VAL_SHIFT 0 2158 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_5_MSB_31_TO_0_VAL_DEFAULT 0x00000000 2159 2160 2161 /**************************************************************************** 2162 * YDC_DDR_BIST :: BIST_REPEAT_PATTERN_5_MSB_63_TO_32 2163 */ 2164 /* YDC_DDR_BIST :: BIST_REPEAT_PATTERN_5_MSB_63_TO_32 :: VAL [31:00] */ 2165 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_5_MSB_63_TO_32_VAL_MASK 0xffffffff 2166 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_5_MSB_63_TO_32_VAL_ALIGN 0 2167 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_5_MSB_63_TO_32_VAL_BITS 32 2168 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_5_MSB_63_TO_32_VAL_SHIFT 0 2169 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_5_MSB_63_TO_32_VAL_DEFAULT 0x00000000 2170 2171 2172 /**************************************************************************** 2173 * YDC_DDR_BIST :: BIST_REPEAT_PATTERN_5_MSB_95_TO_64 2174 */ 2175 /* YDC_DDR_BIST :: BIST_REPEAT_PATTERN_5_MSB_95_TO_64 :: VAL [31:00] */ 2176 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_5_MSB_95_TO_64_VAL_MASK 0xffffffff 2177 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_5_MSB_95_TO_64_VAL_ALIGN 0 2178 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_5_MSB_95_TO_64_VAL_BITS 32 2179 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_5_MSB_95_TO_64_VAL_SHIFT 0 2180 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_5_MSB_95_TO_64_VAL_DEFAULT 0x00000000 2181 2182 2183 /**************************************************************************** 2184 * YDC_DDR_BIST :: BIST_REPEAT_PATTERN_5_MSB_127_TO_96 2185 */ 2186 /* YDC_DDR_BIST :: BIST_REPEAT_PATTERN_5_MSB_127_TO_96 :: VAL [31:00] */ 2187 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_5_MSB_127_TO_96_VAL_MASK 0xffffffff 2188 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_5_MSB_127_TO_96_VAL_ALIGN 0 2189 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_5_MSB_127_TO_96_VAL_BITS 32 2190 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_5_MSB_127_TO_96_VAL_SHIFT 0 2191 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_5_MSB_127_TO_96_VAL_DEFAULT 0x00000000 2192 2193 2194 /**************************************************************************** 2195 * YDC_DDR_BIST :: BIST_REPEAT_PATTERN_5_LSB_31_TO_0 2196 */ 2197 /* YDC_DDR_BIST :: BIST_REPEAT_PATTERN_5_LSB_31_TO_0 :: VAL [31:00] */ 2198 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_5_LSB_31_TO_0_VAL_MASK 0xffffffff 2199 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_5_LSB_31_TO_0_VAL_ALIGN 0 2200 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_5_LSB_31_TO_0_VAL_BITS 32 2201 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_5_LSB_31_TO_0_VAL_SHIFT 0 2202 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_5_LSB_31_TO_0_VAL_DEFAULT 0x00000000 2203 2204 2205 /**************************************************************************** 2206 * YDC_DDR_BIST :: BIST_REPEAT_PATTERN_5_LSB_63_TO_32 2207 */ 2208 /* YDC_DDR_BIST :: BIST_REPEAT_PATTERN_5_LSB_63_TO_32 :: VAL [31:00] */ 2209 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_5_LSB_63_TO_32_VAL_MASK 0xffffffff 2210 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_5_LSB_63_TO_32_VAL_ALIGN 0 2211 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_5_LSB_63_TO_32_VAL_BITS 32 2212 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_5_LSB_63_TO_32_VAL_SHIFT 0 2213 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_5_LSB_63_TO_32_VAL_DEFAULT 0x00000000 2214 2215 2216 /**************************************************************************** 2217 * YDC_DDR_BIST :: BIST_REPEAT_PATTERN_5_LSB_95_TO_64 2218 */ 2219 /* YDC_DDR_BIST :: BIST_REPEAT_PATTERN_5_LSB_95_TO_64 :: VAL [31:00] */ 2220 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_5_LSB_95_TO_64_VAL_MASK 0xffffffff 2221 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_5_LSB_95_TO_64_VAL_ALIGN 0 2222 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_5_LSB_95_TO_64_VAL_BITS 32 2223 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_5_LSB_95_TO_64_VAL_SHIFT 0 2224 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_5_LSB_95_TO_64_VAL_DEFAULT 0x00000000 2225 2226 2227 /**************************************************************************** 2228 * YDC_DDR_BIST :: BIST_REPEAT_PATTERN_5_LSB_127_TO_96 2229 */ 2230 /* YDC_DDR_BIST :: BIST_REPEAT_PATTERN_5_LSB_127_TO_96 :: VAL [31:00] */ 2231 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_5_LSB_127_TO_96_VAL_MASK 0xffffffff 2232 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_5_LSB_127_TO_96_VAL_ALIGN 0 2233 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_5_LSB_127_TO_96_VAL_BITS 32 2234 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_5_LSB_127_TO_96_VAL_SHIFT 0 2235 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_5_LSB_127_TO_96_VAL_DEFAULT 0x00000000 2236 2237 2238 /**************************************************************************** 2239 * YDC_DDR_BIST :: BIST_REPEAT_PATTERN_6_MSB_31_TO_0 2240 */ 2241 /* YDC_DDR_BIST :: BIST_REPEAT_PATTERN_6_MSB_31_TO_0 :: VAL [31:00] */ 2242 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_6_MSB_31_TO_0_VAL_MASK 0xffffffff 2243 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_6_MSB_31_TO_0_VAL_ALIGN 0 2244 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_6_MSB_31_TO_0_VAL_BITS 32 2245 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_6_MSB_31_TO_0_VAL_SHIFT 0 2246 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_6_MSB_31_TO_0_VAL_DEFAULT 0x00000000 2247 2248 2249 /**************************************************************************** 2250 * YDC_DDR_BIST :: BIST_REPEAT_PATTERN_6_MSB_63_TO_32 2251 */ 2252 /* YDC_DDR_BIST :: BIST_REPEAT_PATTERN_6_MSB_63_TO_32 :: VAL [31:00] */ 2253 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_6_MSB_63_TO_32_VAL_MASK 0xffffffff 2254 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_6_MSB_63_TO_32_VAL_ALIGN 0 2255 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_6_MSB_63_TO_32_VAL_BITS 32 2256 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_6_MSB_63_TO_32_VAL_SHIFT 0 2257 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_6_MSB_63_TO_32_VAL_DEFAULT 0x00000000 2258 2259 2260 /**************************************************************************** 2261 * YDC_DDR_BIST :: BIST_REPEAT_PATTERN_6_MSB_95_TO_64 2262 */ 2263 /* YDC_DDR_BIST :: BIST_REPEAT_PATTERN_6_MSB_95_TO_64 :: VAL [31:00] */ 2264 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_6_MSB_95_TO_64_VAL_MASK 0xffffffff 2265 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_6_MSB_95_TO_64_VAL_ALIGN 0 2266 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_6_MSB_95_TO_64_VAL_BITS 32 2267 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_6_MSB_95_TO_64_VAL_SHIFT 0 2268 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_6_MSB_95_TO_64_VAL_DEFAULT 0x00000000 2269 2270 2271 /**************************************************************************** 2272 * YDC_DDR_BIST :: BIST_REPEAT_PATTERN_6_MSB_127_TO_96 2273 */ 2274 /* YDC_DDR_BIST :: BIST_REPEAT_PATTERN_6_MSB_127_TO_96 :: VAL [31:00] */ 2275 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_6_MSB_127_TO_96_VAL_MASK 0xffffffff 2276 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_6_MSB_127_TO_96_VAL_ALIGN 0 2277 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_6_MSB_127_TO_96_VAL_BITS 32 2278 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_6_MSB_127_TO_96_VAL_SHIFT 0 2279 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_6_MSB_127_TO_96_VAL_DEFAULT 0x00000000 2280 2281 2282 /**************************************************************************** 2283 * YDC_DDR_BIST :: BIST_REPEAT_PATTERN_6_LSB_31_TO_0 2284 */ 2285 /* YDC_DDR_BIST :: BIST_REPEAT_PATTERN_6_LSB_31_TO_0 :: VAL [31:00] */ 2286 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_6_LSB_31_TO_0_VAL_MASK 0xffffffff 2287 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_6_LSB_31_TO_0_VAL_ALIGN 0 2288 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_6_LSB_31_TO_0_VAL_BITS 32 2289 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_6_LSB_31_TO_0_VAL_SHIFT 0 2290 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_6_LSB_31_TO_0_VAL_DEFAULT 0x00000000 2291 2292 2293 /**************************************************************************** 2294 * YDC_DDR_BIST :: BIST_REPEAT_PATTERN_6_LSB_63_TO_32 2295 */ 2296 /* YDC_DDR_BIST :: BIST_REPEAT_PATTERN_6_LSB_63_TO_32 :: VAL [31:00] */ 2297 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_6_LSB_63_TO_32_VAL_MASK 0xffffffff 2298 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_6_LSB_63_TO_32_VAL_ALIGN 0 2299 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_6_LSB_63_TO_32_VAL_BITS 32 2300 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_6_LSB_63_TO_32_VAL_SHIFT 0 2301 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_6_LSB_63_TO_32_VAL_DEFAULT 0x00000000 2302 2303 2304 /**************************************************************************** 2305 * YDC_DDR_BIST :: BIST_REPEAT_PATTERN_6_LSB_95_TO_64 2306 */ 2307 /* YDC_DDR_BIST :: BIST_REPEAT_PATTERN_6_LSB_95_TO_64 :: VAL [31:00] */ 2308 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_6_LSB_95_TO_64_VAL_MASK 0xffffffff 2309 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_6_LSB_95_TO_64_VAL_ALIGN 0 2310 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_6_LSB_95_TO_64_VAL_BITS 32 2311 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_6_LSB_95_TO_64_VAL_SHIFT 0 2312 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_6_LSB_95_TO_64_VAL_DEFAULT 0x00000000 2313 2314 2315 /**************************************************************************** 2316 * YDC_DDR_BIST :: BIST_REPEAT_PATTERN_6_LSB_127_TO_96 2317 */ 2318 /* YDC_DDR_BIST :: BIST_REPEAT_PATTERN_6_LSB_127_TO_96 :: VAL [31:00] */ 2319 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_6_LSB_127_TO_96_VAL_MASK 0xffffffff 2320 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_6_LSB_127_TO_96_VAL_ALIGN 0 2321 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_6_LSB_127_TO_96_VAL_BITS 32 2322 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_6_LSB_127_TO_96_VAL_SHIFT 0 2323 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_6_LSB_127_TO_96_VAL_DEFAULT 0x00000000 2324 2325 2326 /**************************************************************************** 2327 * YDC_DDR_BIST :: BIST_REPEAT_PATTERN_7_MSB_31_TO_0 2328 */ 2329 /* YDC_DDR_BIST :: BIST_REPEAT_PATTERN_7_MSB_31_TO_0 :: VAL [31:00] */ 2330 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_7_MSB_31_TO_0_VAL_MASK 0xffffffff 2331 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_7_MSB_31_TO_0_VAL_ALIGN 0 2332 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_7_MSB_31_TO_0_VAL_BITS 32 2333 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_7_MSB_31_TO_0_VAL_SHIFT 0 2334 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_7_MSB_31_TO_0_VAL_DEFAULT 0x00000000 2335 2336 2337 /**************************************************************************** 2338 * YDC_DDR_BIST :: BIST_REPEAT_PATTERN_7_MSB_63_TO_32 2339 */ 2340 /* YDC_DDR_BIST :: BIST_REPEAT_PATTERN_7_MSB_63_TO_32 :: VAL [31:00] */ 2341 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_7_MSB_63_TO_32_VAL_MASK 0xffffffff 2342 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_7_MSB_63_TO_32_VAL_ALIGN 0 2343 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_7_MSB_63_TO_32_VAL_BITS 32 2344 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_7_MSB_63_TO_32_VAL_SHIFT 0 2345 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_7_MSB_63_TO_32_VAL_DEFAULT 0x00000000 2346 2347 2348 /**************************************************************************** 2349 * YDC_DDR_BIST :: BIST_REPEAT_PATTERN_7_MSB_95_TO_64 2350 */ 2351 /* YDC_DDR_BIST :: BIST_REPEAT_PATTERN_7_MSB_95_TO_64 :: VAL [31:00] */ 2352 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_7_MSB_95_TO_64_VAL_MASK 0xffffffff 2353 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_7_MSB_95_TO_64_VAL_ALIGN 0 2354 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_7_MSB_95_TO_64_VAL_BITS 32 2355 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_7_MSB_95_TO_64_VAL_SHIFT 0 2356 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_7_MSB_95_TO_64_VAL_DEFAULT 0x00000000 2357 2358 2359 /**************************************************************************** 2360 * YDC_DDR_BIST :: BIST_REPEAT_PATTERN_7_MSB_127_TO_96 2361 */ 2362 /* YDC_DDR_BIST :: BIST_REPEAT_PATTERN_7_MSB_127_TO_96 :: VAL [31:00] */ 2363 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_7_MSB_127_TO_96_VAL_MASK 0xffffffff 2364 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_7_MSB_127_TO_96_VAL_ALIGN 0 2365 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_7_MSB_127_TO_96_VAL_BITS 32 2366 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_7_MSB_127_TO_96_VAL_SHIFT 0 2367 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_7_MSB_127_TO_96_VAL_DEFAULT 0x00000000 2368 2369 2370 /**************************************************************************** 2371 * YDC_DDR_BIST :: BIST_REPEAT_PATTERN_7_LSB_31_TO_0 2372 */ 2373 /* YDC_DDR_BIST :: BIST_REPEAT_PATTERN_7_LSB_31_TO_0 :: VAL [31:00] */ 2374 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_7_LSB_31_TO_0_VAL_MASK 0xffffffff 2375 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_7_LSB_31_TO_0_VAL_ALIGN 0 2376 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_7_LSB_31_TO_0_VAL_BITS 32 2377 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_7_LSB_31_TO_0_VAL_SHIFT 0 2378 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_7_LSB_31_TO_0_VAL_DEFAULT 0x00000000 2379 2380 2381 /**************************************************************************** 2382 * YDC_DDR_BIST :: BIST_REPEAT_PATTERN_7_LSB_63_TO_32 2383 */ 2384 /* YDC_DDR_BIST :: BIST_REPEAT_PATTERN_7_LSB_63_TO_32 :: VAL [31:00] */ 2385 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_7_LSB_63_TO_32_VAL_MASK 0xffffffff 2386 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_7_LSB_63_TO_32_VAL_ALIGN 0 2387 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_7_LSB_63_TO_32_VAL_BITS 32 2388 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_7_LSB_63_TO_32_VAL_SHIFT 0 2389 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_7_LSB_63_TO_32_VAL_DEFAULT 0x00000000 2390 2391 2392 /**************************************************************************** 2393 * YDC_DDR_BIST :: BIST_REPEAT_PATTERN_7_LSB_95_TO_64 2394 */ 2395 /* YDC_DDR_BIST :: BIST_REPEAT_PATTERN_7_LSB_95_TO_64 :: VAL [31:00] */ 2396 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_7_LSB_95_TO_64_VAL_MASK 0xffffffff 2397 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_7_LSB_95_TO_64_VAL_ALIGN 0 2398 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_7_LSB_95_TO_64_VAL_BITS 32 2399 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_7_LSB_95_TO_64_VAL_SHIFT 0 2400 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_7_LSB_95_TO_64_VAL_DEFAULT 0x00000000 2401 2402 2403 /**************************************************************************** 2404 * YDC_DDR_BIST :: BIST_REPEAT_PATTERN_7_LSB_127_TO_96 2405 */ 2406 /* YDC_DDR_BIST :: BIST_REPEAT_PATTERN_7_LSB_127_TO_96 :: VAL [31:00] */ 2407 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_7_LSB_127_TO_96_VAL_MASK 0xffffffff 2408 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_7_LSB_127_TO_96_VAL_ALIGN 0 2409 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_7_LSB_127_TO_96_VAL_BITS 32 2410 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_7_LSB_127_TO_96_VAL_SHIFT 0 2411 #define YDC_DDR_BIST_BIST_REPEAT_PATTERN_7_LSB_127_TO_96_VAL_DEFAULT 0x00000000 2412 2413 2414 /**************************************************************************** 2415 * YDC_DDR_BIST :: BIST_RATE_LIMITER 2416 */ 2417 /* YDC_DDR_BIST :: BIST_RATE_LIMITER :: reserved0 [31:09] */ 2418 #define YDC_DDR_BIST_BIST_RATE_LIMITER_RESERVED0_MASK 0xfffffe00 2419 #define YDC_DDR_BIST_BIST_RATE_LIMITER_RESERVED0_ALIGN 0 2420 #define YDC_DDR_BIST_BIST_RATE_LIMITER_RESERVED0_BITS 6 2421 #define YDC_DDR_BIST_BIST_RATE_LIMITER_RESERVED0_SHIFT 23 2422 #define YDC_DDR_BIST_BIST_RATE_LIMITER_RESERVED0_DEFAULT 0x00000000 2423 2424 /* YDC_DDR_BIST :: BIST_RATE_LIMITER :: BIST_CMD_WAIT_PRD [08:00] */ 2425 #define YDC_DDR_BIST_BIST_RATE_LIMITER_BIST_CMD_WAIT_PRD_MASK 0x000001ff 2426 #define YDC_DDR_BIST_BIST_RATE_LIMITER_BIST_CMD_WAIT_PRD_ALIGN 0 2427 #define YDC_DDR_BIST_BIST_RATE_LIMITER_BIST_CMD_WAIT_PRD_BITS 9 2428 #define YDC_DDR_BIST_BIST_RATE_LIMITER_BIST_CMD_WAIT_PRD_SHIFT 0 2429 #define YDC_DDR_BIST_BIST_RATE_LIMITER_BIST_CMD_WAIT_PRD_DEFAULT 0x00000000 2430 2431 2432 /**************************************************************************** 2433 * YDC_DDR_BIST :: BIST_NUMBER_OF_ACTIONS 2434 */ 2435 /* YDC_DDR_BIST :: BIST_NUMBER_OF_ACTIONS :: BIST_NUM_ACTIONS [31:00] */ 2436 #define YDC_DDR_BIST_BIST_NUMBER_OF_ACTIONS_BIST_NUM_ACTIONS_MASK 0xffffffff 2437 #define YDC_DDR_BIST_BIST_NUMBER_OF_ACTIONS_BIST_NUM_ACTIONS_ALIGN 0 2438 #define YDC_DDR_BIST_BIST_NUMBER_OF_ACTIONS_BIST_NUM_ACTIONS_BITS 32 2439 #define YDC_DDR_BIST_BIST_NUMBER_OF_ACTIONS_BIST_NUM_ACTIONS_SHIFT 0 2440 #define YDC_DDR_BIST_BIST_NUMBER_OF_ACTIONS_BIST_NUM_ACTIONS_DEFAULT 0x00000000 2441 2442 2443 /**************************************************************************** 2444 * YDC_DDR_BIST :: BIST_START_ADDRESS 2445 */ 2446 /* YDC_DDR_BIST :: BIST_START_ADDRESS :: BIST_START_ADDRESS [31:00] */ 2447 #define YDC_DDR_BIST_BIST_START_ADDRESS_BIST_START_ADDRESS_MASK 0xffffffff 2448 #define YDC_DDR_BIST_BIST_START_ADDRESS_BIST_START_ADDRESS_ALIGN 0 2449 #define YDC_DDR_BIST_BIST_START_ADDRESS_BIST_START_ADDRESS_BITS 32 2450 #define YDC_DDR_BIST_BIST_START_ADDRESS_BIST_START_ADDRESS_SHIFT 0 2451 #define YDC_DDR_BIST_BIST_START_ADDRESS_BIST_START_ADDRESS_DEFAULT 0x00000000 2452 2453 2454 /**************************************************************************** 2455 * YDC_DDR_BIST :: BIST_END_ADDRESS 2456 */ 2457 /* YDC_DDR_BIST :: BIST_END_ADDRESS :: BIST_END_ADDRESS [31:00] */ 2458 #define YDC_DDR_BIST_BIST_END_ADDRESS_BIST_END_ADDRESS_MASK 0xffffffff 2459 #define YDC_DDR_BIST_BIST_END_ADDRESS_BIST_END_ADDRESS_ALIGN 0 2460 #define YDC_DDR_BIST_BIST_END_ADDRESS_BIST_END_ADDRESS_BITS 32 2461 #define YDC_DDR_BIST_BIST_END_ADDRESS_BIST_END_ADDRESS_SHIFT 0 2462 #define YDC_DDR_BIST_BIST_END_ADDRESS_BIST_END_ADDRESS_DEFAULT 0x00000000 2463 2464 2465 /**************************************************************************** 2466 * YDC_DDR_BIST :: BIST_SINGLE_BIT_MASK 2467 */ 2468 /* YDC_DDR_BIST :: BIST_SINGLE_BIT_MASK :: BIST_SINGLE_MASK [31:00] */ 2469 #define YDC_DDR_BIST_BIST_SINGLE_BIT_MASK_BIST_SINGLE_MASK_MASK 0xffffffff 2470 #define YDC_DDR_BIST_BIST_SINGLE_BIT_MASK_BIST_SINGLE_MASK_ALIGN 0 2471 #define YDC_DDR_BIST_BIST_SINGLE_BIT_MASK_BIST_SINGLE_MASK_BITS 32 2472 #define YDC_DDR_BIST_BIST_SINGLE_BIT_MASK_BIST_SINGLE_MASK_SHIFT 0 2473 #define YDC_DDR_BIST_BIST_SINGLE_BIT_MASK_BIST_SINGLE_MASK_DEFAULT 0xffffffff 2474 2475 2476 /**************************************************************************** 2477 * YDC_DDR_BIST :: BIST_PATTERN_WORD_7 2478 */ 2479 /* YDC_DDR_BIST :: BIST_PATTERN_WORD_7 :: BIST_PATTERN_7 [31:00] */ 2480 #define YDC_DDR_BIST_BIST_PATTERN_WORD_7_BIST_PATTERN_7_MASK 0xffffffff 2481 #define YDC_DDR_BIST_BIST_PATTERN_WORD_7_BIST_PATTERN_7_ALIGN 0 2482 #define YDC_DDR_BIST_BIST_PATTERN_WORD_7_BIST_PATTERN_7_BITS 32 2483 #define YDC_DDR_BIST_BIST_PATTERN_WORD_7_BIST_PATTERN_7_SHIFT 0 2484 #define YDC_DDR_BIST_BIST_PATTERN_WORD_7_BIST_PATTERN_7_DEFAULT 0x00000000 2485 2486 2487 /**************************************************************************** 2488 * YDC_DDR_BIST :: BIST_PATTERN_WORD_6 2489 */ 2490 /* YDC_DDR_BIST :: BIST_PATTERN_WORD_6 :: BIST_PATTERN_6 [31:00] */ 2491 #define YDC_DDR_BIST_BIST_PATTERN_WORD_6_BIST_PATTERN_6_MASK 0xffffffff 2492 #define YDC_DDR_BIST_BIST_PATTERN_WORD_6_BIST_PATTERN_6_ALIGN 0 2493 #define YDC_DDR_BIST_BIST_PATTERN_WORD_6_BIST_PATTERN_6_BITS 32 2494 #define YDC_DDR_BIST_BIST_PATTERN_WORD_6_BIST_PATTERN_6_SHIFT 0 2495 #define YDC_DDR_BIST_BIST_PATTERN_WORD_6_BIST_PATTERN_6_DEFAULT 0xffffffff 2496 2497 2498 /**************************************************************************** 2499 * YDC_DDR_BIST :: BIST_PATTERN_WORD_5 2500 */ 2501 /* YDC_DDR_BIST :: BIST_PATTERN_WORD_5 :: BIST_PATTERN_5 [31:00] */ 2502 #define YDC_DDR_BIST_BIST_PATTERN_WORD_5_BIST_PATTERN_5_MASK 0xffffffff 2503 #define YDC_DDR_BIST_BIST_PATTERN_WORD_5_BIST_PATTERN_5_ALIGN 0 2504 #define YDC_DDR_BIST_BIST_PATTERN_WORD_5_BIST_PATTERN_5_BITS 32 2505 #define YDC_DDR_BIST_BIST_PATTERN_WORD_5_BIST_PATTERN_5_SHIFT 0 2506 #define YDC_DDR_BIST_BIST_PATTERN_WORD_5_BIST_PATTERN_5_DEFAULT 0xffffffff 2507 2508 2509 /**************************************************************************** 2510 * YDC_DDR_BIST :: BIST_PATTERN_WORD_4 2511 */ 2512 /* YDC_DDR_BIST :: BIST_PATTERN_WORD_4 :: BIST_PATTERN_4 [31:00] */ 2513 #define YDC_DDR_BIST_BIST_PATTERN_WORD_4_BIST_PATTERN_4_MASK 0xffffffff 2514 #define YDC_DDR_BIST_BIST_PATTERN_WORD_4_BIST_PATTERN_4_ALIGN 0 2515 #define YDC_DDR_BIST_BIST_PATTERN_WORD_4_BIST_PATTERN_4_BITS 32 2516 #define YDC_DDR_BIST_BIST_PATTERN_WORD_4_BIST_PATTERN_4_SHIFT 0 2517 #define YDC_DDR_BIST_BIST_PATTERN_WORD_4_BIST_PATTERN_4_DEFAULT 0xffffffff 2518 2519 2520 /**************************************************************************** 2521 * YDC_DDR_BIST :: BIST_PATTERN_WORD_3 2522 */ 2523 /* YDC_DDR_BIST :: BIST_PATTERN_WORD_3 :: BIST_PATTERN_3 [31:00] */ 2524 #define YDC_DDR_BIST_BIST_PATTERN_WORD_3_BIST_PATTERN_3_MASK 0xffffffff 2525 #define YDC_DDR_BIST_BIST_PATTERN_WORD_3_BIST_PATTERN_3_ALIGN 0 2526 #define YDC_DDR_BIST_BIST_PATTERN_WORD_3_BIST_PATTERN_3_BITS 32 2527 #define YDC_DDR_BIST_BIST_PATTERN_WORD_3_BIST_PATTERN_3_SHIFT 0 2528 #define YDC_DDR_BIST_BIST_PATTERN_WORD_3_BIST_PATTERN_3_DEFAULT 0x00000000 2529 2530 2531 /**************************************************************************** 2532 * YDC_DDR_BIST :: BIST_PATTERN_WORD_2 2533 */ 2534 /* YDC_DDR_BIST :: BIST_PATTERN_WORD_2 :: BIST_PATTERN_2 [31:00] */ 2535 #define YDC_DDR_BIST_BIST_PATTERN_WORD_2_BIST_PATTERN_2_MASK 0xffffffff 2536 #define YDC_DDR_BIST_BIST_PATTERN_WORD_2_BIST_PATTERN_2_ALIGN 0 2537 #define YDC_DDR_BIST_BIST_PATTERN_WORD_2_BIST_PATTERN_2_BITS 32 2538 #define YDC_DDR_BIST_BIST_PATTERN_WORD_2_BIST_PATTERN_2_SHIFT 0 2539 #define YDC_DDR_BIST_BIST_PATTERN_WORD_2_BIST_PATTERN_2_DEFAULT 0xffffffff 2540 2541 2542 /**************************************************************************** 2543 * YDC_DDR_BIST :: BIST_PATTERN_WORD_1 2544 */ 2545 /* YDC_DDR_BIST :: BIST_PATTERN_WORD_1 :: BIST_PATTERN_1 [31:00] */ 2546 #define YDC_DDR_BIST_BIST_PATTERN_WORD_1_BIST_PATTERN_1_MASK 0xffffffff 2547 #define YDC_DDR_BIST_BIST_PATTERN_WORD_1_BIST_PATTERN_1_ALIGN 0 2548 #define YDC_DDR_BIST_BIST_PATTERN_WORD_1_BIST_PATTERN_1_BITS 32 2549 #define YDC_DDR_BIST_BIST_PATTERN_WORD_1_BIST_PATTERN_1_SHIFT 0 2550 #define YDC_DDR_BIST_BIST_PATTERN_WORD_1_BIST_PATTERN_1_DEFAULT 0x00000000 2551 2552 2553 /**************************************************************************** 2554 * YDC_DDR_BIST :: BIST_PATTERN_WORD_0 2555 */ 2556 /* YDC_DDR_BIST :: BIST_PATTERN_WORD_0 :: BIST_PATTERN_0 [31:00] */ 2557 #define YDC_DDR_BIST_BIST_PATTERN_WORD_0_BIST_PATTERN_0_MASK 0xffffffff 2558 #define YDC_DDR_BIST_BIST_PATTERN_WORD_0_BIST_PATTERN_0_ALIGN 0 2559 #define YDC_DDR_BIST_BIST_PATTERN_WORD_0_BIST_PATTERN_0_BITS 32 2560 #define YDC_DDR_BIST_BIST_PATTERN_WORD_0_BIST_PATTERN_0_SHIFT 0 2561 #define YDC_DDR_BIST_BIST_PATTERN_WORD_0_BIST_PATTERN_0_DEFAULT 0x00000000 2562 2563 2564 /**************************************************************************** 2565 * YDC_DDR_BIST :: BIST_FULL_MASK_WORD_7 2566 */ 2567 /* YDC_DDR_BIST :: BIST_FULL_MASK_WORD_7 :: BIST_FULL_MASK_7 [31:00] */ 2568 #define YDC_DDR_BIST_BIST_FULL_MASK_WORD_7_BIST_FULL_MASK_7_MASK 0xffffffff 2569 #define YDC_DDR_BIST_BIST_FULL_MASK_WORD_7_BIST_FULL_MASK_7_ALIGN 0 2570 #define YDC_DDR_BIST_BIST_FULL_MASK_WORD_7_BIST_FULL_MASK_7_BITS 32 2571 #define YDC_DDR_BIST_BIST_FULL_MASK_WORD_7_BIST_FULL_MASK_7_SHIFT 0 2572 #define YDC_DDR_BIST_BIST_FULL_MASK_WORD_7_BIST_FULL_MASK_7_DEFAULT 0xffffffff 2573 2574 2575 /**************************************************************************** 2576 * YDC_DDR_BIST :: BIST_FULL_MASK_WORD_6 2577 */ 2578 /* YDC_DDR_BIST :: BIST_FULL_MASK_WORD_6 :: BIST_FULL_MASK_6 [31:00] */ 2579 #define YDC_DDR_BIST_BIST_FULL_MASK_WORD_6_BIST_FULL_MASK_6_MASK 0xffffffff 2580 #define YDC_DDR_BIST_BIST_FULL_MASK_WORD_6_BIST_FULL_MASK_6_ALIGN 0 2581 #define YDC_DDR_BIST_BIST_FULL_MASK_WORD_6_BIST_FULL_MASK_6_BITS 32 2582 #define YDC_DDR_BIST_BIST_FULL_MASK_WORD_6_BIST_FULL_MASK_6_SHIFT 0 2583 #define YDC_DDR_BIST_BIST_FULL_MASK_WORD_6_BIST_FULL_MASK_6_DEFAULT 0xffffffff 2584 2585 2586 /**************************************************************************** 2587 * YDC_DDR_BIST :: BIST_FULL_MASK_WORD_5 2588 */ 2589 /* YDC_DDR_BIST :: BIST_FULL_MASK_WORD_5 :: BIST_FULL_MASK_5 [31:00] */ 2590 #define YDC_DDR_BIST_BIST_FULL_MASK_WORD_5_BIST_FULL_MASK_5_MASK 0xffffffff 2591 #define YDC_DDR_BIST_BIST_FULL_MASK_WORD_5_BIST_FULL_MASK_5_ALIGN 0 2592 #define YDC_DDR_BIST_BIST_FULL_MASK_WORD_5_BIST_FULL_MASK_5_BITS 32 2593 #define YDC_DDR_BIST_BIST_FULL_MASK_WORD_5_BIST_FULL_MASK_5_SHIFT 0 2594 #define YDC_DDR_BIST_BIST_FULL_MASK_WORD_5_BIST_FULL_MASK_5_DEFAULT 0xffffffff 2595 2596 2597 /**************************************************************************** 2598 * YDC_DDR_BIST :: BIST_FULL_MASK_WORD_4 2599 */ 2600 /* YDC_DDR_BIST :: BIST_FULL_MASK_WORD_4 :: BIST_FULL_MASK_4 [31:00] */ 2601 #define YDC_DDR_BIST_BIST_FULL_MASK_WORD_4_BIST_FULL_MASK_4_MASK 0xffffffff 2602 #define YDC_DDR_BIST_BIST_FULL_MASK_WORD_4_BIST_FULL_MASK_4_ALIGN 0 2603 #define YDC_DDR_BIST_BIST_FULL_MASK_WORD_4_BIST_FULL_MASK_4_BITS 32 2604 #define YDC_DDR_BIST_BIST_FULL_MASK_WORD_4_BIST_FULL_MASK_4_SHIFT 0 2605 #define YDC_DDR_BIST_BIST_FULL_MASK_WORD_4_BIST_FULL_MASK_4_DEFAULT 0xffffffff 2606 2607 2608 /**************************************************************************** 2609 * YDC_DDR_BIST :: BIST_FULL_MASK_WORD_3 2610 */ 2611 /* YDC_DDR_BIST :: BIST_FULL_MASK_WORD_3 :: BIST_FULL_MASK_3 [31:00] */ 2612 #define YDC_DDR_BIST_BIST_FULL_MASK_WORD_3_BIST_FULL_MASK_3_MASK 0xffffffff 2613 #define YDC_DDR_BIST_BIST_FULL_MASK_WORD_3_BIST_FULL_MASK_3_ALIGN 0 2614 #define YDC_DDR_BIST_BIST_FULL_MASK_WORD_3_BIST_FULL_MASK_3_BITS 32 2615 #define YDC_DDR_BIST_BIST_FULL_MASK_WORD_3_BIST_FULL_MASK_3_SHIFT 0 2616 #define YDC_DDR_BIST_BIST_FULL_MASK_WORD_3_BIST_FULL_MASK_3_DEFAULT 0xffffffff 2617 2618 2619 /**************************************************************************** 2620 * YDC_DDR_BIST :: BIST_FULL_MASK_WORD_2 2621 */ 2622 /* YDC_DDR_BIST :: BIST_FULL_MASK_WORD_2 :: BIST_FULL_MASK_2 [31:00] */ 2623 #define YDC_DDR_BIST_BIST_FULL_MASK_WORD_2_BIST_FULL_MASK_2_MASK 0xffffffff 2624 #define YDC_DDR_BIST_BIST_FULL_MASK_WORD_2_BIST_FULL_MASK_2_ALIGN 0 2625 #define YDC_DDR_BIST_BIST_FULL_MASK_WORD_2_BIST_FULL_MASK_2_BITS 32 2626 #define YDC_DDR_BIST_BIST_FULL_MASK_WORD_2_BIST_FULL_MASK_2_SHIFT 0 2627 #define YDC_DDR_BIST_BIST_FULL_MASK_WORD_2_BIST_FULL_MASK_2_DEFAULT 0xffffffff 2628 2629 2630 /**************************************************************************** 2631 * YDC_DDR_BIST :: BIST_FULL_MASK_WORD_1 2632 */ 2633 /* YDC_DDR_BIST :: BIST_FULL_MASK_WORD_1 :: BIST_FULL_MASK_1 [31:00] */ 2634 #define YDC_DDR_BIST_BIST_FULL_MASK_WORD_1_BIST_FULL_MASK_1_MASK 0xffffffff 2635 #define YDC_DDR_BIST_BIST_FULL_MASK_WORD_1_BIST_FULL_MASK_1_ALIGN 0 2636 #define YDC_DDR_BIST_BIST_FULL_MASK_WORD_1_BIST_FULL_MASK_1_BITS 32 2637 #define YDC_DDR_BIST_BIST_FULL_MASK_WORD_1_BIST_FULL_MASK_1_SHIFT 0 2638 #define YDC_DDR_BIST_BIST_FULL_MASK_WORD_1_BIST_FULL_MASK_1_DEFAULT 0xffffffff 2639 2640 2641 /**************************************************************************** 2642 * YDC_DDR_BIST :: BIST_FULL_MASK_WORD_0 2643 */ 2644 /* YDC_DDR_BIST :: BIST_FULL_MASK_WORD_0 :: BIST_FULL_MASK_0 [31:00] */ 2645 #define YDC_DDR_BIST_BIST_FULL_MASK_WORD_0_BIST_FULL_MASK_0_MASK 0xffffffff 2646 #define YDC_DDR_BIST_BIST_FULL_MASK_WORD_0_BIST_FULL_MASK_0_ALIGN 0 2647 #define YDC_DDR_BIST_BIST_FULL_MASK_WORD_0_BIST_FULL_MASK_0_BITS 32 2648 #define YDC_DDR_BIST_BIST_FULL_MASK_WORD_0_BIST_FULL_MASK_0_SHIFT 0 2649 #define YDC_DDR_BIST_BIST_FULL_MASK_WORD_0_BIST_FULL_MASK_0_DEFAULT 0xffffffff 2650 2651 2652 /**************************************************************************** 2653 * YDC_DDR_BIST :: BIST_STATUSES 2654 */ 2655 /* YDC_DDR_BIST :: BIST_STATUSES :: BIST_RD_ACT_CNT [31:01] */ 2656 #define YDC_DDR_BIST_BIST_STATUSES_BIST_RD_ACT_CNT_MASK 0xfffffffe 2657 #define YDC_DDR_BIST_BIST_STATUSES_BIST_RD_ACT_CNT_ALIGN 0 2658 #define YDC_DDR_BIST_BIST_STATUSES_BIST_RD_ACT_CNT_BITS 31 2659 #define YDC_DDR_BIST_BIST_STATUSES_BIST_RD_ACT_CNT_SHIFT 1 2660 #define YDC_DDR_BIST_BIST_STATUSES_BIST_RD_ACT_CNT_DEFAULT 0x00000000 2661 2662 /* YDC_DDR_BIST :: BIST_STATUSES :: BIST_FINISHED [00:00] */ 2663 #define YDC_DDR_BIST_BIST_STATUSES_BIST_FINISHED_MASK 0x00000001 2664 #define YDC_DDR_BIST_BIST_STATUSES_BIST_FINISHED_ALIGN 0 2665 #define YDC_DDR_BIST_BIST_STATUSES_BIST_FINISHED_BITS 1 2666 #define YDC_DDR_BIST_BIST_STATUSES_BIST_FINISHED_SHIFT 0 2667 #define YDC_DDR_BIST_BIST_STATUSES_BIST_FINISHED_DEFAULT 0x00000000 2668 2669 2670 /**************************************************************************** 2671 * YDC_DDR_BIST :: BIST_FULL_MASK_ERROR_COUNTER 2672 */ 2673 /* YDC_DDR_BIST :: BIST_FULL_MASK_ERROR_COUNTER :: FULL_ERR_CNT [31:00] */ 2674 #define YDC_DDR_BIST_BIST_FULL_MASK_ERROR_COUNTER_FULL_ERR_CNT_MASK 0xffffffff 2675 #define YDC_DDR_BIST_BIST_FULL_MASK_ERROR_COUNTER_FULL_ERR_CNT_ALIGN 0 2676 #define YDC_DDR_BIST_BIST_FULL_MASK_ERROR_COUNTER_FULL_ERR_CNT_BITS 32 2677 #define YDC_DDR_BIST_BIST_FULL_MASK_ERROR_COUNTER_FULL_ERR_CNT_SHIFT 0 2678 #define YDC_DDR_BIST_BIST_FULL_MASK_ERROR_COUNTER_FULL_ERR_CNT_DEFAULT 0x00000000 2679 2680 2681 /**************************************************************************** 2682 * YDC_DDR_BIST :: BIST_SINGLE_BIT_MASK_ERROR_COUNTER 2683 */ 2684 /* YDC_DDR_BIST :: BIST_SINGLE_BIT_MASK_ERROR_COUNTER :: SINGLE_ERR_CNT [31:00] */ 2685 #define YDC_DDR_BIST_BIST_SINGLE_BIT_MASK_ERROR_COUNTER_SINGLE_ERR_CNT_MASK 0xffffffff 2686 #define YDC_DDR_BIST_BIST_SINGLE_BIT_MASK_ERROR_COUNTER_SINGLE_ERR_CNT_ALIGN 0 2687 #define YDC_DDR_BIST_BIST_SINGLE_BIT_MASK_ERROR_COUNTER_SINGLE_ERR_CNT_BITS 32 2688 #define YDC_DDR_BIST_BIST_SINGLE_BIT_MASK_ERROR_COUNTER_SINGLE_ERR_CNT_SHIFT 0 2689 #define YDC_DDR_BIST_BIST_SINGLE_BIT_MASK_ERROR_COUNTER_SINGLE_ERR_CNT_DEFAULT 0x00000000 2690 2691 2692 /**************************************************************************** 2693 * YDC_DDR_BIST :: BIST_ERROR_OCCURRED 2694 */ 2695 /* YDC_DDR_BIST :: BIST_ERROR_OCCURRED :: ERR_OCCURRED [31:00] */ 2696 #define YDC_DDR_BIST_BIST_ERROR_OCCURRED_ERR_OCCURRED_MASK 0xffffffff 2697 #define YDC_DDR_BIST_BIST_ERROR_OCCURRED_ERR_OCCURRED_ALIGN 0 2698 #define YDC_DDR_BIST_BIST_ERROR_OCCURRED_ERR_OCCURRED_BITS 32 2699 #define YDC_DDR_BIST_BIST_ERROR_OCCURRED_ERR_OCCURRED_SHIFT 0 2700 #define YDC_DDR_BIST_BIST_ERROR_OCCURRED_ERR_OCCURRED_DEFAULT 0x00000000 2701 2702 2703 /**************************************************************************** 2704 * YDC_DDR_BIST :: BIST_GLOBAL_ERROR_COUNTER 2705 */ 2706 /* YDC_DDR_BIST :: BIST_GLOBAL_ERROR_COUNTER :: GLOBAL_ERR_CNT [31:00] */ 2707 #define YDC_DDR_BIST_BIST_GLOBAL_ERROR_COUNTER_GLOBAL_ERR_CNT_MASK 0xffffffff 2708 #define YDC_DDR_BIST_BIST_GLOBAL_ERROR_COUNTER_GLOBAL_ERR_CNT_ALIGN 0 2709 #define YDC_DDR_BIST_BIST_GLOBAL_ERROR_COUNTER_GLOBAL_ERR_CNT_BITS 32 2710 #define YDC_DDR_BIST_BIST_GLOBAL_ERROR_COUNTER_GLOBAL_ERR_CNT_SHIFT 0 2711 #define YDC_DDR_BIST_BIST_GLOBAL_ERROR_COUNTER_GLOBAL_ERR_CNT_DEFAULT 0x00000000 2712 2713 2714 /**************************************************************************** 2715 * YDC_DDR_BIST :: CNT_BIST_DBI_ERR_GLOBAL 2716 */ 2717 /* YDC_DDR_BIST :: CNT_BIST_DBI_ERR_GLOBAL :: VAL [31:00] */ 2718 #define YDC_DDR_BIST_CNT_BIST_DBI_ERR_GLOBAL_VAL_MASK 0xffffffff 2719 #define YDC_DDR_BIST_CNT_BIST_DBI_ERR_GLOBAL_VAL_ALIGN 0 2720 #define YDC_DDR_BIST_CNT_BIST_DBI_ERR_GLOBAL_VAL_BITS 32 2721 #define YDC_DDR_BIST_CNT_BIST_DBI_ERR_GLOBAL_VAL_SHIFT 0 2722 #define YDC_DDR_BIST_CNT_BIST_DBI_ERR_GLOBAL_VAL_DEFAULT 0x00000000 2723 2724 2725 /**************************************************************************** 2726 * YDC_DDR_BIST :: BIST_DBI_ERR_OCCURED 2727 */ 2728 /* YDC_DDR_BIST :: BIST_DBI_ERR_OCCURED :: reserved0 [31:04] */ 2729 #define YDC_DDR_BIST_BIST_DBI_ERR_OCCURED_RESERVED0_MASK 0xfffffff0 2730 #define YDC_DDR_BIST_BIST_DBI_ERR_OCCURED_RESERVED0_ALIGN 0 2731 #define YDC_DDR_BIST_BIST_DBI_ERR_OCCURED_RESERVED0_BITS 28 2732 #define YDC_DDR_BIST_BIST_DBI_ERR_OCCURED_RESERVED0_SHIFT 4 2733 #define YDC_DDR_BIST_BIST_DBI_ERR_OCCURED_RESERVED0_DEFAULT 0x00000000 2734 2735 /* YDC_DDR_BIST :: BIST_DBI_ERR_OCCURED :: VAL [03:00] */ 2736 #define YDC_DDR_BIST_BIST_DBI_ERR_OCCURED_VAL_MASK 0x0000000f 2737 #define YDC_DDR_BIST_BIST_DBI_ERR_OCCURED_VAL_ALIGN 0 2738 #define YDC_DDR_BIST_BIST_DBI_ERR_OCCURED_VAL_BITS 4 2739 #define YDC_DDR_BIST_BIST_DBI_ERR_OCCURED_VAL_SHIFT 0 2740 #define YDC_DDR_BIST_BIST_DBI_ERR_OCCURED_VAL_DEFAULT 0x03ffffff 2741 2742 2743 /**************************************************************************** 2744 * YDC_DDR_BIST :: CNT_BIST_EDC_ERR_GLOBAL 2745 */ 2746 /* YDC_DDR_BIST :: CNT_BIST_EDC_ERR_GLOBAL :: VAL [31:00] */ 2747 #define YDC_DDR_BIST_CNT_BIST_EDC_ERR_GLOBAL_VAL_MASK 0xffffffff 2748 #define YDC_DDR_BIST_CNT_BIST_EDC_ERR_GLOBAL_VAL_ALIGN 0 2749 #define YDC_DDR_BIST_CNT_BIST_EDC_ERR_GLOBAL_VAL_BITS 32 2750 #define YDC_DDR_BIST_CNT_BIST_EDC_ERR_GLOBAL_VAL_SHIFT 0 2751 #define YDC_DDR_BIST_CNT_BIST_EDC_ERR_GLOBAL_VAL_DEFAULT 0x00000000 2752 2753 2754 /**************************************************************************** 2755 * YDC_DDR_BIST :: BIST_EDC_ERR_OCCURED 2756 */ 2757 /* YDC_DDR_BIST :: BIST_EDC_ERR_OCCURED :: reserved0 [31:04] */ 2758 #define YDC_DDR_BIST_BIST_EDC_ERR_OCCURED_RESERVED0_MASK 0xfffffff0 2759 #define YDC_DDR_BIST_BIST_EDC_ERR_OCCURED_RESERVED0_ALIGN 0 2760 #define YDC_DDR_BIST_BIST_EDC_ERR_OCCURED_RESERVED0_BITS 28 2761 #define YDC_DDR_BIST_BIST_EDC_ERR_OCCURED_RESERVED0_SHIFT 4 2762 #define YDC_DDR_BIST_BIST_EDC_ERR_OCCURED_RESERVED0_DEFAULT 0x00000000 2763 2764 /* YDC_DDR_BIST :: BIST_EDC_ERR_OCCURED :: VAL [03:00] */ 2765 #define YDC_DDR_BIST_BIST_EDC_ERR_OCCURED_VAL_MASK 0x0000000f 2766 #define YDC_DDR_BIST_BIST_EDC_ERR_OCCURED_VAL_ALIGN 0 2767 #define YDC_DDR_BIST_BIST_EDC_ERR_OCCURED_VAL_BITS 4 2768 #define YDC_DDR_BIST_BIST_EDC_ERR_OCCURED_VAL_SHIFT 0 2769 #define YDC_DDR_BIST_BIST_EDC_ERR_OCCURED_VAL_DEFAULT 0x03ffffff 2770 2771 2772 /**************************************************************************** 2773 * YDC_DDR_BIST :: BIST_LAST_ADDR_ERR 2774 */ 2775 /* YDC_DDR_BIST :: BIST_LAST_ADDR_ERR :: reserved0 [31:27] */ 2776 #define YDC_DDR_BIST_BIST_LAST_ADDR_ERR_RESERVED0_MASK 0xf8000000 2777 #define YDC_DDR_BIST_BIST_LAST_ADDR_ERR_RESERVED0_ALIGN 0 2778 #define YDC_DDR_BIST_BIST_LAST_ADDR_ERR_RESERVED0_BITS 5 2779 #define YDC_DDR_BIST_BIST_LAST_ADDR_ERR_RESERVED0_SHIFT 27 2780 #define YDC_DDR_BIST_BIST_LAST_ADDR_ERR_RESERVED0_DEFAULT 0x00000000 2781 2782 /* YDC_DDR_BIST :: BIST_LAST_ADDR_ERR :: VAL [26:00] */ 2783 #define YDC_DDR_BIST_BIST_LAST_ADDR_ERR_VAL_MASK 0x07ffffff 2784 #define YDC_DDR_BIST_BIST_LAST_ADDR_ERR_VAL_ALIGN 0 2785 #define YDC_DDR_BIST_BIST_LAST_ADDR_ERR_VAL_BITS 27 2786 #define YDC_DDR_BIST_BIST_LAST_ADDR_ERR_VAL_SHIFT 0 2787 #define YDC_DDR_BIST_BIST_LAST_ADDR_ERR_VAL_DEFAULT 0x03ffffff 2788 2789 2790 /**************************************************************************** 2791 * YDC_DDR_BIST :: BIST_LAST_DATA_ERR_MSB_31_TO_0 2792 */ 2793 /* YDC_DDR_BIST :: BIST_LAST_DATA_ERR_MSB_31_TO_0 :: VAL [31:00] */ 2794 #define YDC_DDR_BIST_BIST_LAST_DATA_ERR_MSB_31_TO_0_VAL_MASK 0xffffffff 2795 #define YDC_DDR_BIST_BIST_LAST_DATA_ERR_MSB_31_TO_0_VAL_ALIGN 0 2796 #define YDC_DDR_BIST_BIST_LAST_DATA_ERR_MSB_31_TO_0_VAL_BITS 32 2797 #define YDC_DDR_BIST_BIST_LAST_DATA_ERR_MSB_31_TO_0_VAL_SHIFT 0 2798 #define YDC_DDR_BIST_BIST_LAST_DATA_ERR_MSB_31_TO_0_VAL_DEFAULT 0x00000000 2799 2800 2801 /**************************************************************************** 2802 * YDC_DDR_BIST :: BIST_LAST_DATA_ERR_MSB_63_TO_32 2803 */ 2804 /* YDC_DDR_BIST :: BIST_LAST_DATA_ERR_MSB_63_TO_32 :: VAL [31:00] */ 2805 #define YDC_DDR_BIST_BIST_LAST_DATA_ERR_MSB_63_TO_32_VAL_MASK 0xffffffff 2806 #define YDC_DDR_BIST_BIST_LAST_DATA_ERR_MSB_63_TO_32_VAL_ALIGN 0 2807 #define YDC_DDR_BIST_BIST_LAST_DATA_ERR_MSB_63_TO_32_VAL_BITS 32 2808 #define YDC_DDR_BIST_BIST_LAST_DATA_ERR_MSB_63_TO_32_VAL_SHIFT 0 2809 #define YDC_DDR_BIST_BIST_LAST_DATA_ERR_MSB_63_TO_32_VAL_DEFAULT 0x00000000 2810 2811 2812 /**************************************************************************** 2813 * YDC_DDR_BIST :: BIST_LAST_DATA_ERR_MSB_95_TO_64 2814 */ 2815 /* YDC_DDR_BIST :: BIST_LAST_DATA_ERR_MSB_95_TO_64 :: VAL [31:00] */ 2816 #define YDC_DDR_BIST_BIST_LAST_DATA_ERR_MSB_95_TO_64_VAL_MASK 0xffffffff 2817 #define YDC_DDR_BIST_BIST_LAST_DATA_ERR_MSB_95_TO_64_VAL_ALIGN 0 2818 #define YDC_DDR_BIST_BIST_LAST_DATA_ERR_MSB_95_TO_64_VAL_BITS 32 2819 #define YDC_DDR_BIST_BIST_LAST_DATA_ERR_MSB_95_TO_64_VAL_SHIFT 0 2820 #define YDC_DDR_BIST_BIST_LAST_DATA_ERR_MSB_95_TO_64_VAL_DEFAULT 0x00000000 2821 2822 2823 /**************************************************************************** 2824 * YDC_DDR_BIST :: BIST_LAST_DATA_ERR_MSB_127_TO_96 2825 */ 2826 /* YDC_DDR_BIST :: BIST_LAST_DATA_ERR_MSB_127_TO_96 :: VAL [31:00] */ 2827 #define YDC_DDR_BIST_BIST_LAST_DATA_ERR_MSB_127_TO_96_VAL_MASK 0xffffffff 2828 #define YDC_DDR_BIST_BIST_LAST_DATA_ERR_MSB_127_TO_96_VAL_ALIGN 0 2829 #define YDC_DDR_BIST_BIST_LAST_DATA_ERR_MSB_127_TO_96_VAL_BITS 32 2830 #define YDC_DDR_BIST_BIST_LAST_DATA_ERR_MSB_127_TO_96_VAL_SHIFT 0 2831 #define YDC_DDR_BIST_BIST_LAST_DATA_ERR_MSB_127_TO_96_VAL_DEFAULT 0x00000000 2832 2833 2834 /**************************************************************************** 2835 * YDC_DDR_BIST :: BIST_LAST_DATA_ERR_LSB_31_TO_0 2836 */ 2837 /* YDC_DDR_BIST :: BIST_LAST_DATA_ERR_LSB_31_TO_0 :: VAL [31:00] */ 2838 #define YDC_DDR_BIST_BIST_LAST_DATA_ERR_LSB_31_TO_0_VAL_MASK 0xffffffff 2839 #define YDC_DDR_BIST_BIST_LAST_DATA_ERR_LSB_31_TO_0_VAL_ALIGN 0 2840 #define YDC_DDR_BIST_BIST_LAST_DATA_ERR_LSB_31_TO_0_VAL_BITS 32 2841 #define YDC_DDR_BIST_BIST_LAST_DATA_ERR_LSB_31_TO_0_VAL_SHIFT 0 2842 #define YDC_DDR_BIST_BIST_LAST_DATA_ERR_LSB_31_TO_0_VAL_DEFAULT 0x00000000 2843 2844 2845 /**************************************************************************** 2846 * YDC_DDR_BIST :: BIST_LAST_DATA_ERR_LSB_63_TO_32 2847 */ 2848 /* YDC_DDR_BIST :: BIST_LAST_DATA_ERR_LSB_63_TO_32 :: VAL [31:00] */ 2849 #define YDC_DDR_BIST_BIST_LAST_DATA_ERR_LSB_63_TO_32_VAL_MASK 0xffffffff 2850 #define YDC_DDR_BIST_BIST_LAST_DATA_ERR_LSB_63_TO_32_VAL_ALIGN 0 2851 #define YDC_DDR_BIST_BIST_LAST_DATA_ERR_LSB_63_TO_32_VAL_BITS 32 2852 #define YDC_DDR_BIST_BIST_LAST_DATA_ERR_LSB_63_TO_32_VAL_SHIFT 0 2853 #define YDC_DDR_BIST_BIST_LAST_DATA_ERR_LSB_63_TO_32_VAL_DEFAULT 0x00000000 2854 2855 2856 /**************************************************************************** 2857 * YDC_DDR_BIST :: BIST_LAST_DATA_ERR_LSB_95_TO_64 2858 */ 2859 /* YDC_DDR_BIST :: BIST_LAST_DATA_ERR_LSB_95_TO_64 :: VAL [31:00] */ 2860 #define YDC_DDR_BIST_BIST_LAST_DATA_ERR_LSB_95_TO_64_VAL_MASK 0xffffffff 2861 #define YDC_DDR_BIST_BIST_LAST_DATA_ERR_LSB_95_TO_64_VAL_ALIGN 0 2862 #define YDC_DDR_BIST_BIST_LAST_DATA_ERR_LSB_95_TO_64_VAL_BITS 32 2863 #define YDC_DDR_BIST_BIST_LAST_DATA_ERR_LSB_95_TO_64_VAL_SHIFT 0 2864 #define YDC_DDR_BIST_BIST_LAST_DATA_ERR_LSB_95_TO_64_VAL_DEFAULT 0x00000000 2865 2866 2867 /**************************************************************************** 2868 * YDC_DDR_BIST :: BIST_LAST_DATA_ERR_LSB_127_TO_96 2869 */ 2870 /* YDC_DDR_BIST :: BIST_LAST_DATA_ERR_LSB_127_TO_96 :: VAL [31:00] */ 2871 #define YDC_DDR_BIST_BIST_LAST_DATA_ERR_LSB_127_TO_96_VAL_MASK 0xffffffff 2872 #define YDC_DDR_BIST_BIST_LAST_DATA_ERR_LSB_127_TO_96_VAL_ALIGN 0 2873 #define YDC_DDR_BIST_BIST_LAST_DATA_ERR_LSB_127_TO_96_VAL_BITS 32 2874 #define YDC_DDR_BIST_BIST_LAST_DATA_ERR_LSB_127_TO_96_VAL_SHIFT 0 2875 #define YDC_DDR_BIST_BIST_LAST_DATA_ERR_LSB_127_TO_96_VAL_DEFAULT 0x00000000 2876 2877 2878 /**************************************************************************** 2879 * YDC_DDR_BIST :: BIST_LAST_READ_DATA_MSB_31_TO_0 2880 */ 2881 /* YDC_DDR_BIST :: BIST_LAST_READ_DATA_MSB_31_TO_0 :: VAL [31:00] */ 2882 #define YDC_DDR_BIST_BIST_LAST_READ_DATA_MSB_31_TO_0_VAL_MASK 0xffffffff 2883 #define YDC_DDR_BIST_BIST_LAST_READ_DATA_MSB_31_TO_0_VAL_ALIGN 0 2884 #define YDC_DDR_BIST_BIST_LAST_READ_DATA_MSB_31_TO_0_VAL_BITS 32 2885 #define YDC_DDR_BIST_BIST_LAST_READ_DATA_MSB_31_TO_0_VAL_SHIFT 0 2886 #define YDC_DDR_BIST_BIST_LAST_READ_DATA_MSB_31_TO_0_VAL_DEFAULT 0x00000000 2887 2888 2889 /**************************************************************************** 2890 * YDC_DDR_BIST :: BIST_LAST_READ_DATA_MSB_63_TO_32 2891 */ 2892 /* YDC_DDR_BIST :: BIST_LAST_READ_DATA_MSB_63_TO_32 :: VAL [31:00] */ 2893 #define YDC_DDR_BIST_BIST_LAST_READ_DATA_MSB_63_TO_32_VAL_MASK 0xffffffff 2894 #define YDC_DDR_BIST_BIST_LAST_READ_DATA_MSB_63_TO_32_VAL_ALIGN 0 2895 #define YDC_DDR_BIST_BIST_LAST_READ_DATA_MSB_63_TO_32_VAL_BITS 32 2896 #define YDC_DDR_BIST_BIST_LAST_READ_DATA_MSB_63_TO_32_VAL_SHIFT 0 2897 #define YDC_DDR_BIST_BIST_LAST_READ_DATA_MSB_63_TO_32_VAL_DEFAULT 0x00000000 2898 2899 2900 /**************************************************************************** 2901 * YDC_DDR_BIST :: BIST_LAST_READ_DATA_MSB_95_TO_64 2902 */ 2903 /* YDC_DDR_BIST :: BIST_LAST_READ_DATA_MSB_95_TO_64 :: VAL [31:00] */ 2904 #define YDC_DDR_BIST_BIST_LAST_READ_DATA_MSB_95_TO_64_VAL_MASK 0xffffffff 2905 #define YDC_DDR_BIST_BIST_LAST_READ_DATA_MSB_95_TO_64_VAL_ALIGN 0 2906 #define YDC_DDR_BIST_BIST_LAST_READ_DATA_MSB_95_TO_64_VAL_BITS 32 2907 #define YDC_DDR_BIST_BIST_LAST_READ_DATA_MSB_95_TO_64_VAL_SHIFT 0 2908 #define YDC_DDR_BIST_BIST_LAST_READ_DATA_MSB_95_TO_64_VAL_DEFAULT 0x00000000 2909 2910 2911 /**************************************************************************** 2912 * YDC_DDR_BIST :: BIST_LAST_READ_DATA_MSB_127_TO_96 2913 */ 2914 /* YDC_DDR_BIST :: BIST_LAST_READ_DATA_MSB_127_TO_96 :: VAL [31:00] */ 2915 #define YDC_DDR_BIST_BIST_LAST_READ_DATA_MSB_127_TO_96_VAL_MASK 0xffffffff 2916 #define YDC_DDR_BIST_BIST_LAST_READ_DATA_MSB_127_TO_96_VAL_ALIGN 0 2917 #define YDC_DDR_BIST_BIST_LAST_READ_DATA_MSB_127_TO_96_VAL_BITS 32 2918 #define YDC_DDR_BIST_BIST_LAST_READ_DATA_MSB_127_TO_96_VAL_SHIFT 0 2919 #define YDC_DDR_BIST_BIST_LAST_READ_DATA_MSB_127_TO_96_VAL_DEFAULT 0x00000000 2920 2921 2922 /**************************************************************************** 2923 * YDC_DDR_BIST :: BIST_LAST_READ_DATA_LSB_31_TO_0 2924 */ 2925 /* YDC_DDR_BIST :: BIST_LAST_READ_DATA_LSB_31_TO_0 :: VAL [31:00] */ 2926 #define YDC_DDR_BIST_BIST_LAST_READ_DATA_LSB_31_TO_0_VAL_MASK 0xffffffff 2927 #define YDC_DDR_BIST_BIST_LAST_READ_DATA_LSB_31_TO_0_VAL_ALIGN 0 2928 #define YDC_DDR_BIST_BIST_LAST_READ_DATA_LSB_31_TO_0_VAL_BITS 32 2929 #define YDC_DDR_BIST_BIST_LAST_READ_DATA_LSB_31_TO_0_VAL_SHIFT 0 2930 #define YDC_DDR_BIST_BIST_LAST_READ_DATA_LSB_31_TO_0_VAL_DEFAULT 0x00000000 2931 2932 2933 /**************************************************************************** 2934 * YDC_DDR_BIST :: BIST_LAST_READ_DATA_LSB_63_TO_32 2935 */ 2936 /* YDC_DDR_BIST :: BIST_LAST_READ_DATA_LSB_63_TO_32 :: VAL [31:00] */ 2937 #define YDC_DDR_BIST_BIST_LAST_READ_DATA_LSB_63_TO_32_VAL_MASK 0xffffffff 2938 #define YDC_DDR_BIST_BIST_LAST_READ_DATA_LSB_63_TO_32_VAL_ALIGN 0 2939 #define YDC_DDR_BIST_BIST_LAST_READ_DATA_LSB_63_TO_32_VAL_BITS 32 2940 #define YDC_DDR_BIST_BIST_LAST_READ_DATA_LSB_63_TO_32_VAL_SHIFT 0 2941 #define YDC_DDR_BIST_BIST_LAST_READ_DATA_LSB_63_TO_32_VAL_DEFAULT 0x00000000 2942 2943 2944 /**************************************************************************** 2945 * YDC_DDR_BIST :: BIST_LAST_READ_DATA_LSB_95_TO_64 2946 */ 2947 /* YDC_DDR_BIST :: BIST_LAST_READ_DATA_LSB_95_TO_64 :: VAL [31:00] */ 2948 #define YDC_DDR_BIST_BIST_LAST_READ_DATA_LSB_95_TO_64_VAL_MASK 0xffffffff 2949 #define YDC_DDR_BIST_BIST_LAST_READ_DATA_LSB_95_TO_64_VAL_ALIGN 0 2950 #define YDC_DDR_BIST_BIST_LAST_READ_DATA_LSB_95_TO_64_VAL_BITS 32 2951 #define YDC_DDR_BIST_BIST_LAST_READ_DATA_LSB_95_TO_64_VAL_SHIFT 0 2952 #define YDC_DDR_BIST_BIST_LAST_READ_DATA_LSB_95_TO_64_VAL_DEFAULT 0x00000000 2953 2954 2955 /**************************************************************************** 2956 * YDC_DDR_BIST :: BIST_LAST_READ_DATA_LSB_127_TO_96 2957 */ 2958 /* YDC_DDR_BIST :: BIST_LAST_READ_DATA_LSB_127_TO_96 :: VAL [31:00] */ 2959 #define YDC_DDR_BIST_BIST_LAST_READ_DATA_LSB_127_TO_96_VAL_MASK 0xffffffff 2960 #define YDC_DDR_BIST_BIST_LAST_READ_DATA_LSB_127_TO_96_VAL_ALIGN 0 2961 #define YDC_DDR_BIST_BIST_LAST_READ_DATA_LSB_127_TO_96_VAL_BITS 32 2962 #define YDC_DDR_BIST_BIST_LAST_READ_DATA_LSB_127_TO_96_VAL_SHIFT 0 2963 #define YDC_DDR_BIST_BIST_LAST_READ_DATA_LSB_127_TO_96_VAL_DEFAULT 0x00000000 2964 2965 2966 /**************************************************************************** 2967 * YDC_DDR_BIST :: GDDR5_BIST_FINISH_PRD 2968 */ 2969 /* YDC_DDR_BIST :: GDDR5_BIST_FINISH_PRD :: reserved0 [31:08] */ 2970 #define YDC_DDR_BIST_GDDR5_BIST_FINISH_PRD_RESERVED0_MASK 0xffffff00 2971 #define YDC_DDR_BIST_GDDR5_BIST_FINISH_PRD_RESERVED0_ALIGN 0 2972 #define YDC_DDR_BIST_GDDR5_BIST_FINISH_PRD_RESERVED0_BITS 24 2973 #define YDC_DDR_BIST_GDDR5_BIST_FINISH_PRD_RESERVED0_SHIFT 8 2974 #define YDC_DDR_BIST_GDDR5_BIST_FINISH_PRD_RESERVED0_DEFAULT 0x00000000 2975 2976 /* YDC_DDR_BIST :: GDDR5_BIST_FINISH_PRD :: VAL [07:00] */ 2977 #define YDC_DDR_BIST_GDDR5_BIST_FINISH_PRD_VAL_MASK 0x000000ff 2978 #define YDC_DDR_BIST_GDDR5_BIST_FINISH_PRD_VAL_ALIGN 0 2979 #define YDC_DDR_BIST_GDDR5_BIST_FINISH_PRD_VAL_BITS 8 2980 #define YDC_DDR_BIST_GDDR5_BIST_FINISH_PRD_VAL_SHIFT 0 2981 #define YDC_DDR_BIST_GDDR5_BIST_FINISH_PRD_VAL_DEFAULT 0x00000000 2982 2983 2984 /**************************************************************************** 2985 * YDC_DDR_BIST :: INTIAL_CALIB_USE_MPR 2986 */ 2987 /* YDC_DDR_BIST :: INTIAL_CALIB_USE_MPR :: reserved0 [31:08] */ 2988 #define YDC_DDR_BIST_INTIAL_CALIB_USE_MPR_RESERVED0_MASK 0xfffffffe 2989 #define YDC_DDR_BIST_INTIAL_CALIB_USE_MPR_RESERVED0_ALIGN 0 2990 #define YDC_DDR_BIST_INTIAL_CALIB_USE_MPR_RESERVED0_BITS 31 2991 #define YDC_DDR_BIST_INTIAL_CALIB_USE_MPR_RESERVED0_SHIFT 1 2992 #define YDC_DDR_BIST_INTIAL_CALIB_USE_MPR_RESERVED0_DEFAULT 0x00000000 2993 2994 /* YDC_DDR_BIST :: INTIAL_CALIB_USE_MPR :: INTIAL_CALIB_READ_MPR [00:00] */ 2995 #define YDC_DDR_BIST_INTIAL_CALIB_USE_MPR_INTIAL_CALIB_READ_MPR_MASK 0x00000001 2996 #define YDC_DDR_BIST_INTIAL_CALIB_USE_MPR_INTIAL_CALIB_READ_MPR_ALIGN 0 2997 #define YDC_DDR_BIST_INTIAL_CALIB_USE_MPR_INTIAL_CALIB_READ_MPR_BITS 1 2998 #define YDC_DDR_BIST_INTIAL_CALIB_USE_MPR_INTIAL_CALIB_READ_MPR_SHIFT 0 2999 #define YDC_DDR_BIST_INTIAL_CALIB_USE_MPR_INTIAL_CALIB_READ_MPR_DEFAULT 0x00000000 3000 3001 3002 /**************************************************************************** 3003 * Datatype Definitions. 3004 */ 3005 #endif /* #ifndef YDC_DDR_BIST_BIST_H__ */ 3006 3007 /* End of File */ 3008