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phymod_ctrl.h (2913B)

      1 /*
      2  * 
      3  * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file.
      4  * 
      5  * Copyright 2007-2019 Broadcom Inc. All rights reserved.
      6  */
      7 
      8 #ifndef _PHY_PHYMOD_CTRL_H_
      9 #define _PHY_PHYMOD_CTRL_H_
     10 
     11 #include <soc/types.h>
     12 #include <phymod/phymod.h>
     13 #include <phymod/phymod_symbols.h>
     14 
     15 /*
     16  * Generic object for managing cores and lanes.
     17  */
     18 typedef struct soc_phy_obj_s {
     19     struct soc_phy_obj_s *next;
     20     int obj_id;
     21     void *owner;
     22 } soc_phy_obj_t;
     23 
     24 
     25 /*
     26  *  Ardon core init flags
     27  *  per core: core_init was called at each stage
     28  */ 
     29 #define ARDON_CORE_INIT_CALLED_1 0x1 /** Ardon core init stage 1 done */
     30 #define ARDON_CORE_INIT_CALLED_2 0x2 /** Ardon core init stage 2 done  */
     31 
     32 
     33 /*
     34  * Core object
     35  *
     36  * The core object is a physical entity which is independent of other
     37  * physical entities.
     38  */
     39 typedef struct soc_phymod_core_s {
     40     soc_phy_obj_t obj;
     41     phymod_core_access_t pm_core;
     42     phymod_bus_t pm_bus;
     43     int ref_cnt;
     44     int init;
     45     int unit;
     46     int port;
     47     int (*read)(int, uint32, uint32, uint16*);
     48     int (*write)(int, uint32, uint32, uint16);
     49     int (*wrmask)(int, uint32, uint32, uint16, uint16);
     50     void *device_aux_modes ;
     51     phymod_core_init_config_t init_config;
     52     uint32_t flags;
     53 } soc_phymod_core_t;
     54 
     55 /*
     56  * PHY object
     57  *
     58  * A PHY is one or more lanes belonging to the same core object. Most
     59  * PHY hardware is capable of configuring multiple lanes
     60  * simultaneously, so we do not create an object for each lane of a
     61  * logical port.
     62  */
     63 typedef struct soc_phymod_phy_s {
     64     soc_phy_obj_t obj;
     65     phymod_phy_access_t pm_phy;
     66     soc_phymod_core_t *core;
     67     phymod_phy_init_config_t  init_config;
     68 } soc_phymod_phy_t;
     69 
     70 /*
     71  * Logical port object
     72  *
     73  * This object represents a logical port as seen from the MAC (and
     74  * usually also the application). It consists of one or more lane
     75  * groups, depending on how many core objects the logical port spans.
     76  */
     77 typedef struct soc_phymod_ctrl_s {
     78     int unit;
     79     int num_phys;
     80     int main_phy;
     81     soc_phymod_phy_t *phy[PHYMOD_CONFIG_MAX_CORES_PER_PORT];
     82     phymod_symbols_t *symbols;
     83     void (*cleanup)(struct soc_phymod_ctrl_s*);
     84 } soc_phymod_ctrl_t;
     85 
     86 
     87 extern int
     88 soc_phymod_miim_bus_read(int unit, uint32_t addr, uint32_t reg, uint32_t *data);
     89 
     90 extern int
     91 soc_phymod_miim_bus_write(int unit, uint32_t addr, uint32_t reg, uint32_t data);
     92 
     93 extern int
     94 soc_phymod_core_create(int unit, int core_id, soc_phymod_core_t **core);
     95 
     96 extern int
     97 soc_phymod_core_destroy(int unit, soc_phymod_core_t *core);
     98 
     99 extern int
    100 soc_phymod_core_find_by_id(int unit, int core_id, soc_phymod_core_t **core);
    101 
    102 extern int
    103 soc_phymod_phy_create(int unit, int phy_id, soc_phymod_phy_t **phy);
    104 
    105 extern int
    106 soc_phymod_phy_destroy(int unit, soc_phymod_phy_t *phy);
    107 
    108 extern int
    109 soc_phymod_phy_find_by_id(int unit, int phy_id, soc_phymod_phy_t **phy);
    110 
    111 #endif /* _PHY_PHYMOD_CTRL_H_ */