phyctrl.h (12927B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * File: phyctrl.h 8 * Purpose: Data structures and function prototypes for PHY configuration. 9 * Note: This header file is for PHY driver module. Should not include 10 * this header file in SOC or BCM layers except 11 * soc/common/phyctrl.c 12 */ 13 14 #ifndef _PHY_PHYCTRL_H_ 15 #define _PHY_PHYCTRL_H_ 16 17 #include <sal/core/time.h> 18 #include <soc/types.h> 19 #include <soc/portmode.h> 20 #ifdef PHYMOD_SUPPORT 21 #include <soc/phy/phymod_ctrl.h> 22 #endif 23 24 /* Data Structures */ 25 typedef struct phy_ctrl_s { 26 int unit; /* BCM unit number */ 27 soc_port_t port; /* BCM port number */ 28 uint16 phy_id0; /* PHY ID0 register */ 29 uint16 phy_id1; /* PHY ID1 register */ 30 uint16 phy_model; /* PHY model from ID reg */ 31 uint16 phy_rev; /* PHY revision from ID reg */ 32 uint32 phy_oui; /* PHY oui from ID reg */ 33 uint16 phy_id; /* PHY ID on MDIO bus */ 34 uint8 block_init_flag; /* Block Init Flag */ 35 uint8 lane_num; /* Lane number in a device */ 36 uint8 phy_mode; /* configuration mode */ 37 uint16 chip_num; /* chip number */ 38 int speed_max; /* Restrict support to speed max */ 39 uint8 ledmode[4]; /* LED1..4 selectors */ 40 uint16 ledctrl; /* LED control */ 41 uint16 ledselect; /* LED select */ 42 int automedium; /* Medium auto-select active */ 43 int ext_phy_autodetect_en; /* Enable/disable autodetect */ 44 int ext_phy_fiber_iface; /* Fiber Iface when Autodetect is disabled*/ 45 int tbi_capable; /* PHY & SOC both support TBI */ 46 int medium; /* Last active medium type */ 47 int fiber_detect; /* Fiber Signal Detection */ 48 int halfout; /* Transmit half amplitude */ 49 int fiber_plug_dely; /* De-glitch time from property */ 50 sal_usecs_t fiber_plug_time; /* Time de-glitch started */ 51 int fiber_plug_wait; /* De-glitch timer is running */ 52 int fiber_plug_done; /* De-glitch period satisfied */ 53 sal_usecs_t an_state_time; 54 int an_state_valid; 55 uint16 sgmii_an_state; 56 uint16 mii_stat; 57 soc_port_if_t interface; /* Operating mode of PHY */ 58 soc_phy_config_t copper; /* Current copper config */ 59 soc_phy_config_t fiber; /* Current fiber config */ 60 uint32 stop; /* Power up/down state */ 61 uint32 flags; /* PHY_STOP flags */ 62 uint32 power_mode; /* various power saving modes */ 63 char *dev_name; /* device name */ 64 struct phy_driver_s *pd; /* PHY driver functions */ 65 #if defined (INCLUDE_MACSEC) || defined(INCLUDE_PLP_IMACSEC) 66 int macsec_dev_addr; /* MACSEC PHY MDIO address */ 67 int macsec_dev_port; /* MACSEC PHY Port Number */ 68 int macsec_mac_policy; /* MACSEC PHY Switch MAC Policy */ 69 int macsec_enable; /* MACSEC Enable/Disabled */ 70 int macsec_switch_fixed; /* Switch Fixed Policy */ 71 int macsec_switch_fixed_speed; /* Switch Fixed Speed */ 72 int macsec_switch_fixed_duplex;/* Switch Fixed Duplex */ 73 int macsec_switch_fixed_pause; /* Switch Fixed Pause */ 74 int macsec_pause_rx_fwd; /* RX pause Forward or consume */ 75 int macsec_pause_tx_fwd; /* TX pause Forward or consume */ 76 int macsec_line_ipg; /* Line side IPG */ 77 int macsec_switch_ipg; /* Switch side IPG */ 78 #endif 79 #ifdef INCLUDE_FCMAP 80 int fcmap_dev_addr; /* FCMAP PHY MDIO address */ 81 int fcmap_uc_dev_addr; /* FCMAP MDIO address for uc */ 82 int fcmap_dev_port; /* FCMAP PHY Port Number */ 83 int fcmap_mac_policy; /* FCMAP PHY Switch MAC Policy */ 84 int fcmap_enable; /* FCMAP Enable/Disabled */ 85 int fcmap_switch_fixed; /* Switch Fixed Policy */ 86 int fcmap_switch_fixed_speed; /* Switch Fixed Speed */ 87 int fcmap_switch_fixed_duplex;/* Switch Fixed Duplex */ 88 int fcmap_switch_fixed_pause; /* Switch Fixed Pause */ 89 int fcmap_pause_rx_fwd; /* RX pause Forward or consume */ 90 int fcmap_pause_tx_fwd; /* TX pause Forward or consume */ 91 int fcmap_line_ipg; /* Line side IPG */ 92 int fcmap_switch_ipg; /* Switch side IPG */ 93 void *fcmap_port_cfg; /* Port Config */ 94 #endif 95 #ifdef PHYMOD_SUPPORT 96 soc_phymod_ctrl_t phymod_ctrl; 97 #endif 98 int (*read)(int, uint32, uint32, uint16*); /* HW read */ 99 int (*write)(int, uint32, uint32, uint16); /* HW write */ 100 int (*wb_write)(int, uint32, uint32, uint16); /* HW write */ 101 int (*data_write)(int, uint32, uint8, uint16); /* HW write */ 102 int (*addr_write)(int, uint32, uint8, uint16); /* HW write */ 103 int (*wrmask)(int, uint32, uint32, uint16, uint16); 104 void *driver_data; /* driver private data */ 105 int size; /* additional memory space requested by driver */ 106 } phy_ctrl_t; 107 108 extern phy_ctrl_t **int_phy_ctrl[SOC_MAX_NUM_DEVICES]; 109 extern phy_ctrl_t **ext_phy_ctrl[SOC_MAX_NUM_DEVICES]; 110 111 #define INT_PHY_SW_STATE(unit, port) (int_phy_ctrl[unit][port]) 112 #define EXT_PHY_SW_STATE(unit, port) (ext_phy_ctrl[unit][port]) 113 114 /* Param check macros */ 115 #define EXT_PHY_INIT_CHECK(unit, port) \ 116 if (EXT_PHY_SW_STATE(unit, port) == NULL) { return SOC_E_INIT; } 117 #define INT_PHY_INIT_CHECK(unit, port) \ 118 if (INT_PHY_SW_STATE(unit, port) == NULL) { return SOC_E_INIT; } 119 #define PHY_CONTROL_TYPE_CHECK(type) \ 120 if ((((int)(type)) < 0) || (((int)(type)) >= ((int)(SOC_PHY_CONTROL_COUNT)))){\ 121 return SOC_E_PARAM; \ 122 } 123 124 /* phy bus read/write function type */ 125 typedef int (*soc_phy_bus_rd_t)(int,uint32,uint32,uint16 *); 126 typedef int (*soc_phy_bus_wr_t)(int,uint32,uint32,uint16); 127 128 extern int 129 soc_phy_probe(int unit, soc_port_t port, phy_ctrl_t *ext_pc, 130 phy_ctrl_t *int_pc); 131 132 extern int 133 soc_phy_check_sim(int unit, int port, phy_ctrl_t *pc); 134 135 typedef enum phyident_core_type_e { 136 phyident_core_type_wc = 0, 137 phyident_core_type_mld, 138 phyident_core_type_qsmii, 139 phyident_core_types_count 140 } phyident_core_type_t; 141 142 typedef struct phyident_core_info_s { 143 uint16 mdio_addr; 144 phyident_core_type_t core_type; 145 uint32 mld_index; 146 uint32 index_in_mld; 147 uint32 qsmii_lane; 148 uint32 first_phy_in_core; 149 uint32 nof_lanes_in_core; 150 } phyident_core_info_t; 151 152 #define PHYIDENT_INFO_NOT_SET 0xFFFFFFFF 153 154 extern void phyident_core_info_t_init(phyident_core_info_t* core_info); 155 156 #ifdef BCM_PETRA_SUPPORT 157 extern int 158 _dpp_phy_addr_multi_get(int unit, soc_port_t port, int is_logical, int array_max, 159 int *array_size, phyident_core_info_t *core_info); 160 #endif 161 162 extern int 163 soc_phy_addr_multi_get(int unit, soc_port_t port, int array_size, 164 int *addr_num, phyident_core_info_t *core_info); 165 166 extern int 167 soc_phy_list_get(char *phy_list[],int phy_list_size,int *phys_in_list); 168 169 #ifdef INCLUDE_I2C 170 extern int 171 phy_i2c_miireg_write (int unit,uint32 phy_id,uint32 phy_reg_addr, 172 uint16 phy_wr_data); 173 extern int 174 phy_i2c_miireg_read (int unit,uint32 phy_id,uint32 phy_reg_addr, 175 uint16 *phy_rd_data); 176 extern int 177 phy_i2c_bus_func_hook_set (int unit, soc_phy_bus_rd_t rd, 178 soc_phy_bus_wr_t wr); 179 #endif 180 181 #define _PHYCTRL_CALL(_pc, _pf, _pa) \ 182 ((_pc) == 0 ? SOC_E_INIT : \ 183 (((_pc)->pd)->_pf == 0 ? SOC_E_UNAVAIL : ((_pc)->pd)->_pf _pa)) 184 185 #define PHYCTRL_INIT(_pc, _u, _p) \ 186 _PHYCTRL_CALL((_pc), pd_init, ((_u), (_p))) 187 188 #define PHYCTRL_RESET(_pc, _u, _p) \ 189 _PHYCTRL_CALL((_pc), pd_reset, ((_u), (_p), NULL)) 190 191 #define PHYCTRL_LINK_GET(_pc, _u, _p, _l) \ 192 _PHYCTRL_CALL((_pc), pd_link_get, ((_u), (_p), (_l))) 193 194 #define PHYCTRL_ENABLE_SET(_pc, _u, _p, _l) \ 195 _PHYCTRL_CALL((_pc), pd_enable_set, ((_u), (_p), (_l))) 196 197 #define PHYCTRL_ENABLE_GET(_pc, _u, _p, _l) \ 198 _PHYCTRL_CALL((_pc), pd_enable_get, ((_u), (_p), (_l))) 199 200 #define PHYCTRL_DUPLEX_SET(_pc, _u, _p, _d) \ 201 _PHYCTRL_CALL((_pc), pd_duplex_set, ((_u), (_p), (_d))) 202 203 #define PHYCTRL_DUPLEX_GET(_pc, _u, _p, _d) \ 204 _PHYCTRL_CALL((_pc), pd_duplex_get, ((_u), (_p), (_d))) 205 206 #define PHYCTRL_SPEED_SET(_pc, _u, _p, _s) \ 207 _PHYCTRL_CALL((_pc), pd_speed_set, ((_u), (_p), (_s))) 208 209 #define PHYCTRL_SPEED_GET(_pc, _u, _p, _s) \ 210 _PHYCTRL_CALL((_pc), pd_speed_get, ((_u), (_p), (_s))) 211 212 #define PHYCTRL_MASTER_SET(_pc, _u, _p, _s) \ 213 _PHYCTRL_CALL((_pc), pd_master_set, ((_u), (_p), (_s))) 214 215 #define PHYCTRL_MASTER_GET(_pc, _u, _p, _s) \ 216 _PHYCTRL_CALL((_pc), pd_master_get, ((_u), (_p), (_s))) 217 218 #define PHYCTRL_AUTO_NEGOTIATE_SET(_pc, _u, _p, _a) \ 219 _PHYCTRL_CALL((_pc), pd_an_set, ((_u), (_p), (_a))) 220 221 #define PHYCTRL_AUTO_NEGOTIATE_GET(_pc, _u, _p, _a, _b) \ 222 _PHYCTRL_CALL((_pc), pd_an_get, ((_u), (_p), (_a), (_b))) 223 224 #define PHYCTRL_ADV_SET(_pc, _u, _p, _a) \ 225 _PHYCTRL_CALL((_pc), pd_adv_local_set, ((_u), (_p), (_a))) 226 227 #define PHYCTRL_ADV_GET(_pc, _u, _p, _a) \ 228 _PHYCTRL_CALL((_pc), pd_adv_local_get, ((_u), (_p), (_a))) 229 230 #define PHYCTRL_LOOPBACK_SET(_pc, _u, _p, _l) \ 231 _PHYCTRL_CALL((_pc), pd_lb_set, ((_u), (_p), (_l))) 232 233 #define PHYCTRL_LOOPBACK_GET(_pc, _u, _p, _l) \ 234 _PHYCTRL_CALL((_pc), pd_lb_get, ((_u), (_p), (_l))) 235 236 #define PHYCTRL_INTERFACE_SET(_pc, _u, _p, _i) \ 237 _PHYCTRL_CALL((_pc), pd_interface_set, ((_u), (_p), (_i))) 238 239 #define PHYCTRL_INTERFACE_GET(_pc, _u, _p, _i) \ 240 _PHYCTRL_CALL((_pc), pd_interface_get, ((_u), (_p), (_i))) 241 242 #define PHYCTRL_ABILITY_GET(_pc, _u, _p, _m) \ 243 _PHYCTRL_CALL((_pc), pd_ability, ((_u), (_p), (_m))) 244 245 #define PHYCTRL_LINKUP_EVT(_pc, _u, _p) \ 246 _PHYCTRL_CALL((_pc), pd_linkup_evt, ((_u), (_p))) 247 248 #define PHYCTRL_LINKDN_EVT(_pc, _u, _p) \ 249 _PHYCTRL_CALL((_pc), pd_linkdn_evt, ((_u), (_p))) 250 251 #define PHYCTRL_ADV_REMOTE_GET(_pc, _u, _p, _m) \ 252 _PHYCTRL_CALL((_pc), pd_adv_remote_get, ((_u), (_p), (_m))) 253 254 #define PHYCTRL_MDIX_SET(_pc, _u, _p, _m) \ 255 _PHYCTRL_CALL((_pc), pd_mdix_set, ((_u), (_p), (_m))) 256 257 #define PHYCTRL_MDIX_GET(_pc, _u, _p, _m) \ 258 _PHYCTRL_CALL((_pc), pd_mdix_get, ((_u), (_p), (_m))) 259 260 #define PHYCTRL_MDIX_STATUS_GET(_pc, _u, _p, _s) \ 261 _PHYCTRL_CALL((_pc), pd_mdix_status_get, ((_u), (_p), (_s))) 262 263 #define PHYCTRL_MEDIUM_CONFIG_SET(_pc, _u, _p, _m, _c) \ 264 _PHYCTRL_CALL((_pc), pd_medium_config_set, ((_u), (_p), (_m), (_c))) 265 266 #define PHYCTRL_MEDIUM_CONFIG_GET(_pc, _u, _p, _m, _c) \ 267 _PHYCTRL_CALL((_pc), pd_medium_config_get, ((_u), (_p), (_m), (_c))) 268 269 #define PHYCTRL_MEDIUM_GET(_pc, _u, _p, _m) \ 270 _PHYCTRL_CALL((_pc), pd_medium_get, ((_u), (_p), (_m))) 271 272 #define PHYCTRL_CABLE_DIAG(_pc, _u, _p, _status) \ 273 _PHYCTRL_CALL((_pc), pd_cable_diag, ((_u), (_p), (_status))) 274 275 #define PHYCTRL_LINK_CHANGE(_pc, _u, _p, _l) \ 276 _PHYCTRL_CALL((_pc), pd_link_change, ((_u), (_p), (_l))) 277 278 #define PHYCTRL_CONTROL_SET(_pc, _u, _p, _t, _v) \ 279 _PHYCTRL_CALL((_pc), pd_control_set, ((_u), (_p), (_t), (_v))) 280 281 #define PHYCTRL_CONTROL_GET(_pc, _u, _p, _t, _v) \ 282 _PHYCTRL_CALL((_pc), pd_control_get, ((_u), (_p), (_t), (_v))) 283 284 #define PHYCTRL_REG_READ(_pc, _u, _p, _f, _a, _v) \ 285 _PHYCTRL_CALL((_pc), pd_reg_read, ((_u), (_p), (_f), (_a), (_v))) 286 287 #define PHYCTRL_REG_WRITE(_pc, _u, _p, _f, _a, _v) \ 288 _PHYCTRL_CALL((_pc), pd_reg_write, ((_u), (_p), (_f), (_a), (_v))) 289 290 #define PHYCTRL_REG_MODIFY(_pc, _u, _p, _f, _a, _v, _m) \ 291 _PHYCTRL_CALL((_pc), pd_reg_modify, ((_u), (_p), (_f), (_a), (_v), (_m))) 292 293 #define PHYCTRL_NOTIFY(_pc, _u, _p, _e, _v) \ 294 _PHYCTRL_CALL((_pc), pd_notify, ((_u), (_p), (_e), (_v))) 295 296 #endif /* _PHY_PHYCTRL_H_ */