openbcm

phy_sjc16.h (1168197B)

---

 /******************************************************************************
  *
  *  This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file.
  * 
  *  Copyright 2007-2019 Broadcom Inc. All rights reserved.
  *
  *  No portions of this material may be reproduced in any
  *  form without the written permission of Broadcom Corporation
  *  All information contained in this document is considered
  *  company private, proprietary, and trade secret.
  *                                                          _
  *                                                         / \
  *                                                  _     /   \     _
  * ________________________/ \   /     \   / \_
  *                                                    \_/       \_/
  *  Project     : iProc
  *
  *  Description : socregs.h
  */
 
 /*
  * m = memory, c = core, r = register, f = field, d = data.
  */
 #if !defined(GET_FIELD) && !defined(SET_FIELD)
 #define BRCM_ALIGN(c,r,f)   c##_##r##_##f##_ALIGN
 #define BRCM_BITS(c,r,f)    c##_##r##_##f##_BITS
 #define BRCM_MASK(c,r,f)    c##_##r##_##f##_MASK
 #define BRCM_SHIFT(c,r,f)   c##_##r##_##f##_SHIFT
 
 #define GET_FIELD(m,c,r,f) \
 	((((m) & BRCM_MASK(c,r,f)) >> BRCM_SHIFT(c,r,f)) << BRCM_ALIGN(c,r,f))
 
 #define SET_FIELD(m,c,r,f,d) \
 	((m) = (((m) & ~BRCM_MASK(c,r,f)) | ((((d) >> BRCM_ALIGN(c,r,f)) << \
 	 BRCM_SHIFT(c,r,f)) & BRCM_MASK(c,r,f))) \
 	)
 
 #define SET_TYPE_FIELD(m,c,r,f,d) SET_FIELD(m,c,r,f,c##_##d)
 #define SET_NAME_FIELD(m,c,r,f,d) SET_FIELD(m,c,r,f,c##_##r##_##f##_##d)
 #define SET_VALUE_FIELD(m,c,r,f,d) SET_FIELD(m,c,r,f,d)
 
 #define DDR_PHY_GET_FIELD(m,c,r,f) \
             GET_FIELD(m,c,r,f)
 #define DDR_PHY_SET_FIELD(m,c,r,f,d) \
             SET_FIELD(m,c,r,f,d)
 
 
 #endif /* GET & SET */
 
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT0 0x1023c000
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT0_BASE 0x000
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT0_MIN_VDL_STEP_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT0_MIN_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT0_MIN_VDL_STEP_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT0_MIN_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT0_MIN_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT0_RESERVED_MASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT0_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT0_RESERVED_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT0_RESERVED_SHIFT 7
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT0_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT0_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT0_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT0_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT0_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT0_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT0_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT0_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT0_DATAMASK 0x0000007f
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT0_RDWRMASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT0_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT1 0x1023c004
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT1_BASE 0x004
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT1_MIN_VDL_STEP_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT1_MIN_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT1_MIN_VDL_STEP_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT1_MIN_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT1_MIN_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT1_RESERVED_MASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT1_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT1_RESERVED_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT1_RESERVED_SHIFT 7
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT1_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT1_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT1_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT1_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT1_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT1_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT1_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT1_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT1_DATAMASK 0x0000007f
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT1_RDWRMASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT1_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT2 0x1023c008
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT2_BASE 0x008
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT2_MIN_VDL_STEP_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT2_MIN_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT2_MIN_VDL_STEP_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT2_MIN_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT2_MIN_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT2_RESERVED_MASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT2_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT2_RESERVED_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT2_RESERVED_SHIFT 7
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT2_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT2_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT2_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT2_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT2_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT2_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT2_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT2_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT2_DATAMASK 0x0000007f
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT2_RDWRMASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT2_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT3 0x1023c00c
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT3_BASE 0x00c
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT3_MIN_VDL_STEP_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT3_MIN_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT3_MIN_VDL_STEP_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT3_MIN_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT3_MIN_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT3_RESERVED_MASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT3_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT3_RESERVED_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT3_RESERVED_SHIFT 7
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT3_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT3_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT3_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT3_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT3_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT3_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT3_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT3_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT3_DATAMASK 0x0000007f
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT3_RDWRMASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT3_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT4 0x1023c010
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT4_BASE 0x010
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT4_MIN_VDL_STEP_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT4_MIN_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT4_MIN_VDL_STEP_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT4_MIN_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT4_MIN_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT4_RESERVED_MASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT4_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT4_RESERVED_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT4_RESERVED_SHIFT 7
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT4_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT4_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT4_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT4_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT4_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT4_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT4_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT4_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT4_DATAMASK 0x0000007f
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT4_RDWRMASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT4_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT5 0x1023c014
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT5_BASE 0x014
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT5_MIN_VDL_STEP_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT5_MIN_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT5_MIN_VDL_STEP_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT5_MIN_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT5_MIN_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT5_RESERVED_MASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT5_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT5_RESERVED_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT5_RESERVED_SHIFT 7
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT5_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT5_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT5_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT5_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT5_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT5_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT5_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT5_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT5_DATAMASK 0x0000007f
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT5_RDWRMASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT5_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT6 0x1023c018
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT6_BASE 0x018
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT6_MIN_VDL_STEP_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT6_MIN_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT6_MIN_VDL_STEP_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT6_MIN_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT6_MIN_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT6_RESERVED_MASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT6_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT6_RESERVED_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT6_RESERVED_SHIFT 7
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT6_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT6_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT6_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT6_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT6_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT6_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT6_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT6_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT6_DATAMASK 0x0000007f
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT6_RDWRMASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT6_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT7 0x1023c01c
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT7_BASE 0x01c
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT7_MIN_VDL_STEP_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT7_MIN_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT7_MIN_VDL_STEP_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT7_MIN_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT7_MIN_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT7_RESERVED_MASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT7_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT7_RESERVED_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT7_RESERVED_SHIFT 7
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT7_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT7_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT7_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT7_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT7_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT7_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT7_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT7_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT7_DATAMASK 0x0000007f
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT7_RDWRMASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT7_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_DBI 0x1023c020
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_DBI_BASE 0x020
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_DBI_MIN_VDL_STEP_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_DBI_MIN_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_DBI_MIN_VDL_STEP_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_DBI_MIN_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_DBI_MIN_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_DBI_RESERVED_MASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_DBI_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_DBI_RESERVED_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_DBI_RESERVED_SHIFT 7
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_DBI_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_DBI_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_DBI_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_DBI_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_DBI_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_DBI_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_DBI_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_DBI_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_DBI_DATAMASK 0x0000007f
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_DBI_RDWRMASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_DBI_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_EDC 0x1023c024
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_EDC_BASE 0x024
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_EDC_MIN_VDL_STEP_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_EDC_MIN_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_EDC_MIN_VDL_STEP_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_EDC_MIN_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_EDC_MIN_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_EDC_RESERVED_MASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_EDC_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_EDC_RESERVED_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_EDC_RESERVED_SHIFT 7
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_EDC_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_EDC_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_EDC_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_EDC_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_EDC_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_EDC_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_EDC_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_EDC_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_EDC_DATAMASK 0x0000007f
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_EDC_RDWRMASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_EDC_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MAX_VDL_DATA 0x1023c028
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MAX_VDL_DATA_BASE 0x028
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MAX_VDL_DATA_UI_SHIFT_MASK 0xe00
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MAX_VDL_DATA_UI_SHIFT_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MAX_VDL_DATA_UI_SHIFT_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MAX_VDL_DATA_UI_SHIFT_SHIFT 9
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MAX_VDL_DATA_UI_SHIFT_RESETVALUE 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MAX_VDL_DATA_MAX_VDL_STEP_MASK 0x1ff
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MAX_VDL_DATA_MAX_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MAX_VDL_DATA_MAX_VDL_STEP_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MAX_VDL_DATA_MAX_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MAX_VDL_DATA_MAX_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MAX_VDL_DATA_RESERVED_MASK 0xfffff000
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MAX_VDL_DATA_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MAX_VDL_DATA_RESERVED_BITS 20
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MAX_VDL_DATA_RESERVED_SHIFT 12
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MAX_VDL_DATA_ALL_MASK 0xfff
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MAX_VDL_DATA_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MAX_VDL_DATA_ALL_BITS 12
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MAX_VDL_DATA_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MAX_VDL_DATA_ALL_MASK 0xfff
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MAX_VDL_DATA_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MAX_VDL_DATA_ALL_BITS 12
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MAX_VDL_DATA_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MAX_VDL_DATA_DATAMASK 0x00000fff
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MAX_VDL_DATA_RDWRMASK 0xfffff000
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MAX_VDL_DATA_RESETVALUE 0x200
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MAX_VDL_DATA_SHADOW 0x1023c02c
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MAX_VDL_DATA_SHADOW_BASE 0x02c
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MAX_VDL_DATA_SHADOW_UI_SHIFT_MASK 0xe00
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MAX_VDL_DATA_SHADOW_UI_SHIFT_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MAX_VDL_DATA_SHADOW_UI_SHIFT_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MAX_VDL_DATA_SHADOW_UI_SHIFT_SHIFT 9
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MAX_VDL_DATA_SHADOW_UI_SHIFT_RESETVALUE 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MAX_VDL_DATA_SHADOW_MAX_VDL_STEP_MASK 0x1ff
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MAX_VDL_DATA_SHADOW_MAX_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MAX_VDL_DATA_SHADOW_MAX_VDL_STEP_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MAX_VDL_DATA_SHADOW_MAX_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MAX_VDL_DATA_SHADOW_MAX_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MAX_VDL_DATA_SHADOW_RESERVED_MASK 0xfffff000
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MAX_VDL_DATA_SHADOW_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MAX_VDL_DATA_SHADOW_RESERVED_BITS 20
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MAX_VDL_DATA_SHADOW_RESERVED_SHIFT 12
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MAX_VDL_DATA_SHADOW_ALL_MASK 0xfff
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MAX_VDL_DATA_SHADOW_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MAX_VDL_DATA_SHADOW_ALL_BITS 12
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MAX_VDL_DATA_SHADOW_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MAX_VDL_DATA_SHADOW_ALL_MASK 0xfff
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MAX_VDL_DATA_SHADOW_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MAX_VDL_DATA_SHADOW_ALL_BITS 12
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MAX_VDL_DATA_SHADOW_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MAX_VDL_DATA_SHADOW_DATAMASK 0x00000fff
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MAX_VDL_DATA_SHADOW_RDWRMASK 0xfffff000
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MAX_VDL_DATA_SHADOW_RESETVALUE 0x200
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MAX_VDL_DQS 0x1023c030
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MAX_VDL_DQS_BASE 0x030
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MAX_VDL_DQS_UI_SHIFT_MASK 0xe00
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MAX_VDL_DQS_UI_SHIFT_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MAX_VDL_DQS_UI_SHIFT_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MAX_VDL_DQS_UI_SHIFT_SHIFT 9
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MAX_VDL_DQS_UI_SHIFT_RESETVALUE 0x2
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MAX_VDL_DQS_MAX_VDL_STEP_MASK 0x1ff
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MAX_VDL_DQS_MAX_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MAX_VDL_DQS_MAX_VDL_STEP_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MAX_VDL_DQS_MAX_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MAX_VDL_DQS_MAX_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MAX_VDL_DQS_RESERVED_MASK 0xfffff000
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MAX_VDL_DQS_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MAX_VDL_DQS_RESERVED_BITS 20
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MAX_VDL_DQS_RESERVED_SHIFT 12
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MAX_VDL_DQS_ALL_MASK 0xfff
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MAX_VDL_DQS_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MAX_VDL_DQS_ALL_BITS 12
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MAX_VDL_DQS_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MAX_VDL_DQS_ALL_MASK 0xfff
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MAX_VDL_DQS_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MAX_VDL_DQS_ALL_BITS 12
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MAX_VDL_DQS_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MAX_VDL_DQS_DATAMASK 0x00000fff
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MAX_VDL_DQS_RDWRMASK 0xfffff000
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_MAX_VDL_DQS_RESETVALUE 0x400
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT0 0x1023c034
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT0_BASE 0x034
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT0_MIN_VDL_STEP_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT0_MIN_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT0_MIN_VDL_STEP_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT0_MIN_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT0_MIN_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT0_RESERVED_MASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT0_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT0_RESERVED_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT0_RESERVED_SHIFT 7
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT0_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT0_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT0_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT0_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT0_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT0_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT0_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT0_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT0_DATAMASK 0x0000007f
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT0_RDWRMASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT0_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT1 0x1023c038
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT1_BASE 0x038
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT1_MIN_VDL_STEP_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT1_MIN_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT1_MIN_VDL_STEP_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT1_MIN_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT1_MIN_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT1_RESERVED_MASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT1_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT1_RESERVED_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT1_RESERVED_SHIFT 7
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT1_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT1_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT1_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT1_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT1_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT1_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT1_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT1_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT1_DATAMASK 0x0000007f
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT1_RDWRMASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT1_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT2 0x1023c03c
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT2_BASE 0x03c
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT2_MIN_VDL_STEP_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT2_MIN_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT2_MIN_VDL_STEP_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT2_MIN_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT2_MIN_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT2_RESERVED_MASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT2_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT2_RESERVED_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT2_RESERVED_SHIFT 7
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT2_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT2_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT2_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT2_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT2_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT2_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT2_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT2_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT2_DATAMASK 0x0000007f
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT2_RDWRMASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT2_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT3 0x1023c040
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT3_BASE 0x040
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT3_MIN_VDL_STEP_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT3_MIN_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT3_MIN_VDL_STEP_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT3_MIN_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT3_MIN_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT3_RESERVED_MASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT3_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT3_RESERVED_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT3_RESERVED_SHIFT 7
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT3_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT3_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT3_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT3_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT3_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT3_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT3_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT3_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT3_DATAMASK 0x0000007f
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT3_RDWRMASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT3_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT4 0x1023c044
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT4_BASE 0x044
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT4_MIN_VDL_STEP_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT4_MIN_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT4_MIN_VDL_STEP_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT4_MIN_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT4_MIN_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT4_RESERVED_MASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT4_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT4_RESERVED_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT4_RESERVED_SHIFT 7
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT4_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT4_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT4_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT4_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT4_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT4_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT4_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT4_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT4_DATAMASK 0x0000007f
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT4_RDWRMASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT4_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT5 0x1023c048
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT5_BASE 0x048
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT5_MIN_VDL_STEP_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT5_MIN_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT5_MIN_VDL_STEP_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT5_MIN_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT5_MIN_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT5_RESERVED_MASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT5_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT5_RESERVED_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT5_RESERVED_SHIFT 7
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT5_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT5_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT5_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT5_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT5_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT5_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT5_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT5_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT5_DATAMASK 0x0000007f
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT5_RDWRMASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT5_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT6 0x1023c04c
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT6_BASE 0x04c
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT6_MIN_VDL_STEP_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT6_MIN_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT6_MIN_VDL_STEP_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT6_MIN_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT6_MIN_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT6_RESERVED_MASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT6_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT6_RESERVED_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT6_RESERVED_SHIFT 7
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT6_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT6_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT6_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT6_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT6_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT6_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT6_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT6_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT6_DATAMASK 0x0000007f
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT6_RDWRMASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT6_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT7 0x1023c050
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT7_BASE 0x050
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT7_MIN_VDL_STEP_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT7_MIN_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT7_MIN_VDL_STEP_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT7_MIN_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT7_MIN_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT7_RESERVED_MASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT7_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT7_RESERVED_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT7_RESERVED_SHIFT 7
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT7_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT7_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT7_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT7_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT7_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT7_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT7_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT7_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT7_DATAMASK 0x0000007f
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT7_RDWRMASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT7_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_DBI 0x1023c054
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_DBI_BASE 0x054
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_DBI_MIN_VDL_STEP_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_DBI_MIN_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_DBI_MIN_VDL_STEP_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_DBI_MIN_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_DBI_MIN_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_DBI_RESERVED_MASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_DBI_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_DBI_RESERVED_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_DBI_RESERVED_SHIFT 7
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_DBI_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_DBI_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_DBI_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_DBI_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_DBI_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_DBI_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_DBI_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_DBI_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_DBI_DATAMASK 0x0000007f
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_DBI_RDWRMASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_DBI_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_EDC 0x1023c058
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_EDC_BASE 0x058
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_EDC_MIN_VDL_STEP_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_EDC_MIN_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_EDC_MIN_VDL_STEP_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_EDC_MIN_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_EDC_MIN_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_EDC_RESERVED_MASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_EDC_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_EDC_RESERVED_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_EDC_RESERVED_SHIFT 7
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_EDC_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_EDC_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_EDC_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_EDC_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_EDC_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_EDC_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_EDC_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_EDC_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_EDC_DATAMASK 0x0000007f
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_EDC_RDWRMASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_EDC_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQS_MASTER_CTRL 0x1023c05c
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQS_MASTER_CTRL_BASE 0x05c
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQS_MASTER_CTRL_MASTER_MODE_MASK 0x10000
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQS_MASTER_CTRL_MASTER_MODE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQS_MASTER_CTRL_MASTER_MODE_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQS_MASTER_CTRL_MASTER_MODE_SHIFT 16
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQS_MASTER_CTRL_MASTER_MODE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQS_MASTER_CTRL_FORCE_UPDATE_MASK 0x1000
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQS_MASTER_CTRL_FORCE_UPDATE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQS_MASTER_CTRL_FORCE_UPDATE_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQS_MASTER_CTRL_FORCE_UPDATE_SHIFT 12
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQS_MASTER_CTRL_FORCE_UPDATE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQS_MASTER_CTRL_MAX_VDL_STEP_MASK 0x1ff
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQS_MASTER_CTRL_MAX_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQS_MASTER_CTRL_MAX_VDL_STEP_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQS_MASTER_CTRL_MAX_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQS_MASTER_CTRL_MAX_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQS_MASTER_CTRL_RESERVED_0_MASK 0xfffe0000
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQS_MASTER_CTRL_RESERVED_0_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQS_MASTER_CTRL_RESERVED_0_BITS 15
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQS_MASTER_CTRL_RESERVED_0_SHIFT 17
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQS_MASTER_CTRL_RESERVED_1_MASK 0xe000
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQS_MASTER_CTRL_RESERVED_1_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQS_MASTER_CTRL_RESERVED_1_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQS_MASTER_CTRL_RESERVED_1_SHIFT 13
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQS_MASTER_CTRL_RESERVED_2_MASK 0xe00
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQS_MASTER_CTRL_RESERVED_2_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQS_MASTER_CTRL_RESERVED_2_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQS_MASTER_CTRL_RESERVED_2_SHIFT 9
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQS_MASTER_CTRL_RESERVED_MASK 0xfffe0000
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQS_MASTER_CTRL_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQS_MASTER_CTRL_RESERVED_BITS 15
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQS_MASTER_CTRL_RESERVED_SHIFT 17
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQS_MASTER_CTRL_ALL_MASK 0x1ffff
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQS_MASTER_CTRL_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQS_MASTER_CTRL_ALL_BITS 17
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQS_MASTER_CTRL_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQS_MASTER_CTRL_ALL_MASK 0x1ffff
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQS_MASTER_CTRL_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQS_MASTER_CTRL_ALL_BITS 17
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQS_MASTER_CTRL_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQS_MASTER_CTRL_DATAMASK 0x000111ff
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQS_MASTER_CTRL_RDWRMASK 0xfffeee00
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQS_MASTER_CTRL_RESETVALUE 0x00000
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQSEP 0x1023c060
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQSEP_BASE 0x060
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQSEP_MAX_VDL_STEP_MASK 0x1ff
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQSEP_MAX_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQSEP_MAX_VDL_STEP_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQSEP_MAX_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQSEP_MAX_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQSEP_RESERVED_MASK 0xfffffe00
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQSEP_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQSEP_RESERVED_BITS 23
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQSEP_RESERVED_SHIFT 9
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQSEP_ALL_MASK 0x1ff
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQSEP_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQSEP_ALL_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQSEP_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQSEP_ALL_MASK 0x1ff
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQSEP_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQSEP_ALL_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQSEP_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQSEP_DATAMASK 0x000001ff
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQSEP_RDWRMASK 0xfffffe00
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQSEP_RESETVALUE 0x000
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQSDP 0x1023c064
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQSDP_BASE 0x064
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQSDP_MAX_VDL_STEP_MASK 0x1ff
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQSDP_MAX_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQSDP_MAX_VDL_STEP_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQSDP_MAX_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQSDP_MAX_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQSDP_RESERVED_MASK 0xfffffe00
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQSDP_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQSDP_RESERVED_BITS 23
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQSDP_RESERVED_SHIFT 9
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQSDP_ALL_MASK 0x1ff
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQSDP_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQSDP_ALL_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQSDP_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQSDP_ALL_MASK 0x1ff
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQSDP_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQSDP_ALL_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQSDP_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQSDP_DATAMASK 0x000001ff
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQSDP_RDWRMASK 0xfffffe00
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQSDP_RESETVALUE 0x000
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQSEN 0x1023c068
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQSEN_BASE 0x068
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQSEN_MAX_VDL_STEP_MASK 0x1ff
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQSEN_MAX_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQSEN_MAX_VDL_STEP_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQSEN_MAX_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQSEN_MAX_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQSEN_RESERVED_MASK 0xfffffe00
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQSEN_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQSEN_RESERVED_BITS 23
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQSEN_RESERVED_SHIFT 9
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQSEN_ALL_MASK 0x1ff
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQSEN_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQSEN_ALL_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQSEN_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQSEN_ALL_MASK 0x1ff
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQSEN_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQSEN_ALL_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQSEN_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQSEN_DATAMASK 0x000001ff
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQSEN_RDWRMASK 0xfffffe00
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQSEN_RESETVALUE 0x000
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQSDN 0x1023c06c
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQSDN_BASE 0x06c
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQSDN_MAX_VDL_STEP_MASK 0x1ff
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQSDN_MAX_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQSDN_MAX_VDL_STEP_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQSDN_MAX_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQSDN_MAX_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQSDN_RESERVED_MASK 0xfffffe00
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQSDN_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQSDN_RESERVED_BITS 23
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQSDN_RESERVED_SHIFT 9
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQSDN_ALL_MASK 0x1ff
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQSDN_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQSDN_ALL_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQSDN_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQSDN_ALL_MASK 0x1ff
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQSDN_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQSDN_ALL_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQSDN_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQSDN_DATAMASK 0x000001ff
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQSDN_RDWRMASK 0xfffffe00
 #define SJC16_DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQSDN_RESETVALUE 0x000
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_LEVELING_CONFIG 0x1023c070
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_LEVELING_CONFIG_BASE 0x070
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_LEVELING_CONFIG_WRITE_LEVELING_MODE_MASK 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_LEVELING_CONFIG_WRITE_LEVELING_MODE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_LEVELING_CONFIG_WRITE_LEVELING_MODE_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_LEVELING_CONFIG_WRITE_LEVELING_MODE_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_LEVELING_CONFIG_WRITE_LEVELING_MODE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_LEVELING_CONFIG_RESERVED_MASK 0xfffffffe
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_LEVELING_CONFIG_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_LEVELING_CONFIG_RESERVED_BITS 31
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_LEVELING_CONFIG_RESERVED_SHIFT 1
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_LEVELING_CONFIG_WRITE_LEVELING_MODE_MASK 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_LEVELING_CONFIG_WRITE_LEVELING_MODE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_LEVELING_CONFIG_WRITE_LEVELING_MODE_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_LEVELING_CONFIG_WRITE_LEVELING_MODE_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_LEVELING_CONFIG_WRITE_LEVELING_MODE_MASK 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_LEVELING_CONFIG_WRITE_LEVELING_MODE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_LEVELING_CONFIG_WRITE_LEVELING_MODE_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_LEVELING_CONFIG_WRITE_LEVELING_MODE_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_LEVELING_CONFIG_ALL_MASK 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_LEVELING_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_LEVELING_CONFIG_ALL_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_LEVELING_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_LEVELING_CONFIG_ALL_MASK 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_LEVELING_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_LEVELING_CONFIG_ALL_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_LEVELING_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_LEVELING_CONFIG_DATAMASK 0x00000001
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_LEVELING_CONFIG_RDWRMASK 0xfffffffe
 #define SJC16_DDR4_PHY_DQ_BYTE0_WRITE_LEVELING_CONFIG_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_REN_GEN_ERR_CTRL 0x1023c074
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_REN_GEN_ERR_CTRL_BASE 0x074
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_REN_GEN_ERR_CTRL_ERR2_CLEAR_MASK 0x2
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_REN_GEN_ERR_CTRL_ERR2_CLEAR_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_REN_GEN_ERR_CTRL_ERR2_CLEAR_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_REN_GEN_ERR_CTRL_ERR2_CLEAR_SHIFT 1
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_REN_GEN_ERR_CTRL_ERR2_CLEAR_RESETVALUE 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_REN_GEN_ERR_CTRL_ERR1_CLEAR_MASK 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_REN_GEN_ERR_CTRL_ERR1_CLEAR_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_REN_GEN_ERR_CTRL_ERR1_CLEAR_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_REN_GEN_ERR_CTRL_ERR1_CLEAR_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_REN_GEN_ERR_CTRL_ERR1_CLEAR_RESETVALUE 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_REN_GEN_ERR_CTRL_RESERVED_MASK 0xfffffffc
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_REN_GEN_ERR_CTRL_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_REN_GEN_ERR_CTRL_RESERVED_BITS 30
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_REN_GEN_ERR_CTRL_RESERVED_SHIFT 2
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_REN_GEN_ERR_CTRL_ALL_MASK 0x3
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_REN_GEN_ERR_CTRL_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_REN_GEN_ERR_CTRL_ALL_BITS 2
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_REN_GEN_ERR_CTRL_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_REN_GEN_ERR_CTRL_ALL_MASK 0x3
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_REN_GEN_ERR_CTRL_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_REN_GEN_ERR_CTRL_ALL_BITS 2
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_REN_GEN_ERR_CTRL_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_REN_GEN_ERR_CTRL_DATAMASK 0x00000003
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_REN_GEN_ERR_CTRL_RDWRMASK 0xfffffffc
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_REN_GEN_ERR_CTRL_RESETVALUE 0x3
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_REN_FIFO_CONFIG 0x1023c078
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_REN_FIFO_CONFIG_BASE 0x078
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_REN_FIFO_CONFIG_RD_2G_DELAY_DEC_MASK 0x800
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_REN_FIFO_CONFIG_RD_2G_DELAY_DEC_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_REN_FIFO_CONFIG_RD_2G_DELAY_DEC_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_REN_FIFO_CONFIG_RD_2G_DELAY_DEC_SHIFT 11
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_REN_FIFO_CONFIG_RD_2G_DELAY_DEC_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_REN_FIFO_CONFIG_RD_2G_DELAY_INC_MASK 0x400
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_REN_FIFO_CONFIG_RD_2G_DELAY_INC_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_REN_FIFO_CONFIG_RD_2G_DELAY_INC_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_REN_FIFO_CONFIG_RD_2G_DELAY_INC_SHIFT 10
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_REN_FIFO_CONFIG_RD_2G_DELAY_INC_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_REN_FIFO_CONFIG_RD2_2G_DELAY_MASK 0x3e0
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_REN_FIFO_CONFIG_RD2_2G_DELAY_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_REN_FIFO_CONFIG_RD2_2G_DELAY_BITS 5
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_REN_FIFO_CONFIG_RD2_2G_DELAY_SHIFT 5
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_REN_FIFO_CONFIG_RD2_2G_DELAY_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_REN_FIFO_CONFIG_RD_2G_DELAY_MASK 0x1f
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_REN_FIFO_CONFIG_RD_2G_DELAY_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_REN_FIFO_CONFIG_RD_2G_DELAY_BITS 5
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_REN_FIFO_CONFIG_RD_2G_DELAY_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_REN_FIFO_CONFIG_RD_2G_DELAY_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_REN_FIFO_CONFIG_RESERVED_MASK 0xfffff000
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_REN_FIFO_CONFIG_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_REN_FIFO_CONFIG_RESERVED_BITS 20
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_REN_FIFO_CONFIG_RESERVED_SHIFT 12
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_REN_FIFO_CONFIG_ALL_MASK 0xfff
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_REN_FIFO_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_REN_FIFO_CONFIG_ALL_BITS 12
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_REN_FIFO_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_REN_FIFO_CONFIG_ALL_MASK 0xfff
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_REN_FIFO_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_REN_FIFO_CONFIG_ALL_BITS 12
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_REN_FIFO_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_REN_FIFO_CONFIG_DATAMASK 0x00000fff
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_REN_FIFO_CONFIG_RDWRMASK 0xfffff000
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_REN_FIFO_CONFIG_RESETVALUE 0x000
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_REN_STRETCH_CONFIG 0x1023c07c
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_REN_STRETCH_CONFIG_BASE 0x07c
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_REN_STRETCH_CONFIG_A_PLUS_2_MASK 0x20
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_REN_STRETCH_CONFIG_A_PLUS_2_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_REN_STRETCH_CONFIG_A_PLUS_2_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_REN_STRETCH_CONFIG_A_PLUS_2_SHIFT 5
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_REN_STRETCH_CONFIG_A_PLUS_2_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_REN_STRETCH_CONFIG_A_PLUS_1_MASK 0x10
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_REN_STRETCH_CONFIG_A_PLUS_1_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_REN_STRETCH_CONFIG_A_PLUS_1_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_REN_STRETCH_CONFIG_A_PLUS_1_SHIFT 4
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_REN_STRETCH_CONFIG_A_PLUS_1_RESETVALUE 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_REN_STRETCH_CONFIG_A_0_MASK 0x8
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_REN_STRETCH_CONFIG_A_0_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_REN_STRETCH_CONFIG_A_0_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_REN_STRETCH_CONFIG_A_0_SHIFT 3
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_REN_STRETCH_CONFIG_A_0_RESETVALUE 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_REN_STRETCH_CONFIG_A_MINUS_1_MASK 0x4
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_REN_STRETCH_CONFIG_A_MINUS_1_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_REN_STRETCH_CONFIG_A_MINUS_1_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_REN_STRETCH_CONFIG_A_MINUS_1_SHIFT 2
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_REN_STRETCH_CONFIG_A_MINUS_1_RESETVALUE 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_REN_STRETCH_CONFIG_A_MINUS_2_MASK 0x2
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_REN_STRETCH_CONFIG_A_MINUS_2_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_REN_STRETCH_CONFIG_A_MINUS_2_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_REN_STRETCH_CONFIG_A_MINUS_2_SHIFT 1
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_REN_STRETCH_CONFIG_A_MINUS_2_RESETVALUE 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_REN_STRETCH_CONFIG_A_MINUS_3_MASK 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_REN_STRETCH_CONFIG_A_MINUS_3_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_REN_STRETCH_CONFIG_A_MINUS_3_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_REN_STRETCH_CONFIG_A_MINUS_3_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_REN_STRETCH_CONFIG_A_MINUS_3_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_REN_STRETCH_CONFIG_RESERVED_MASK 0xffffffc0
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_REN_STRETCH_CONFIG_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_REN_STRETCH_CONFIG_RESERVED_BITS 26
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_REN_STRETCH_CONFIG_RESERVED_SHIFT 6
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_REN_STRETCH_CONFIG_ALL_MASK 0x3f
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_REN_STRETCH_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_REN_STRETCH_CONFIG_ALL_BITS 6
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_REN_STRETCH_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_REN_STRETCH_CONFIG_ALL_MASK 0x3f
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_REN_STRETCH_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_REN_STRETCH_CONFIG_ALL_BITS 6
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_REN_STRETCH_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_REN_STRETCH_CONFIG_DATAMASK 0x0000003f
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_REN_STRETCH_CONFIG_RDWRMASK 0xffffffc0
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_REN_STRETCH_CONFIG_RESETVALUE 0x1e
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_READ_MAX_VDL_FSM 0x1023c080
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_READ_MAX_VDL_FSM_BASE 0x080
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_READ_MAX_VDL_FSM_MAX_VDL_STEP_MASK 0x1ff
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_READ_MAX_VDL_FSM_MAX_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_READ_MAX_VDL_FSM_MAX_VDL_STEP_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_READ_MAX_VDL_FSM_MAX_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_READ_MAX_VDL_FSM_MAX_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_READ_MAX_VDL_FSM_RESERVED_MASK 0xfffffe00
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_READ_MAX_VDL_FSM_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_READ_MAX_VDL_FSM_RESERVED_BITS 23
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_READ_MAX_VDL_FSM_RESERVED_SHIFT 9
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_READ_MAX_VDL_FSM_ALL_MASK 0x1ff
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_READ_MAX_VDL_FSM_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_READ_MAX_VDL_FSM_ALL_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_READ_MAX_VDL_FSM_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_READ_MAX_VDL_FSM_ALL_MASK 0x1ff
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_READ_MAX_VDL_FSM_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_READ_MAX_VDL_FSM_ALL_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_READ_MAX_VDL_FSM_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_READ_MAX_VDL_FSM_DATAMASK 0x000001ff
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_READ_MAX_VDL_FSM_RDWRMASK 0xfffffe00
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_READ_MAX_VDL_FSM_RESETVALUE 0x000
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_OE_CONFIG 0x1023c084
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_OE_CONFIG_BASE 0x084
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_OE_CONFIG_OE_POST_CYCLES_MASK 0x38
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_OE_CONFIG_OE_POST_CYCLES_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_OE_CONFIG_OE_POST_CYCLES_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_OE_CONFIG_OE_POST_CYCLES_SHIFT 3
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_OE_CONFIG_OE_POST_CYCLES_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_OE_CONFIG_OE_PRE_CYCLES_MASK 0x7
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_OE_CONFIG_OE_PRE_CYCLES_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_OE_CONFIG_OE_PRE_CYCLES_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_OE_CONFIG_OE_PRE_CYCLES_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_OE_CONFIG_OE_PRE_CYCLES_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_OE_CONFIG_RESERVED_MASK 0xffffffc0
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_OE_CONFIG_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_OE_CONFIG_RESERVED_BITS 26
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_OE_CONFIG_RESERVED_SHIFT 6
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_OE_CONFIG_ALL_MASK 0x3f
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_OE_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_OE_CONFIG_ALL_BITS 6
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_OE_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_OE_CONFIG_ALL_MASK 0x3f
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_OE_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_OE_CONFIG_ALL_BITS 6
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_OE_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_OE_CONFIG_DATAMASK 0x0000003f
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_OE_CONFIG_RDWRMASK 0xffffffc0
 #define SJC16_DDR4_PHY_DQ_BYTE0_DDR4_OE_CONFIG_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE0_GDDR5_READ_ALIGNMENT_CTRL 0x1023c088
 #define SJC16_DDR4_PHY_DQ_BYTE0_GDDR5_READ_ALIGNMENT_CTRL_BASE 0x088
 #define SJC16_DDR4_PHY_DQ_BYTE0_GDDR5_READ_ALIGNMENT_CTRL_RDATA_WR2RD_DELAY_DEC_MASK 0x20000000
 #define SJC16_DDR4_PHY_DQ_BYTE0_GDDR5_READ_ALIGNMENT_CTRL_RDATA_WR2RD_DELAY_DEC_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_GDDR5_READ_ALIGNMENT_CTRL_RDATA_WR2RD_DELAY_DEC_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE0_GDDR5_READ_ALIGNMENT_CTRL_RDATA_WR2RD_DELAY_DEC_SHIFT 29
 #define SJC16_DDR4_PHY_DQ_BYTE0_GDDR5_READ_ALIGNMENT_CTRL_RDATA_WR2RD_DELAY_DEC_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_GDDR5_READ_ALIGNMENT_CTRL_RDATA_WR2RD_DELAY_INC_MASK 0x10000000
 #define SJC16_DDR4_PHY_DQ_BYTE0_GDDR5_READ_ALIGNMENT_CTRL_RDATA_WR2RD_DELAY_INC_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_GDDR5_READ_ALIGNMENT_CTRL_RDATA_WR2RD_DELAY_INC_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE0_GDDR5_READ_ALIGNMENT_CTRL_RDATA_WR2RD_DELAY_INC_SHIFT 28
 #define SJC16_DDR4_PHY_DQ_BYTE0_GDDR5_READ_ALIGNMENT_CTRL_RDATA_WR2RD_DELAY_INC_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_GDDR5_READ_ALIGNMENT_CTRL_RDATA_WR2RD_DELAY_MASK 0xf000000
 #define SJC16_DDR4_PHY_DQ_BYTE0_GDDR5_READ_ALIGNMENT_CTRL_RDATA_WR2RD_DELAY_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_GDDR5_READ_ALIGNMENT_CTRL_RDATA_WR2RD_DELAY_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE0_GDDR5_READ_ALIGNMENT_CTRL_RDATA_WR2RD_DELAY_SHIFT 24
 #define SJC16_DDR4_PHY_DQ_BYTE0_GDDR5_READ_ALIGNMENT_CTRL_RDATA_WR2RD_DELAY_RESETVALUE 0x4
 #define SJC16_DDR4_PHY_DQ_BYTE0_GDDR5_READ_ALIGNMENT_CTRL_EDC_HALF_RATE_UI_SELECT_MASK 0x800000
 #define SJC16_DDR4_PHY_DQ_BYTE0_GDDR5_READ_ALIGNMENT_CTRL_EDC_HALF_RATE_UI_SELECT_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_GDDR5_READ_ALIGNMENT_CTRL_EDC_HALF_RATE_UI_SELECT_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE0_GDDR5_READ_ALIGNMENT_CTRL_EDC_HALF_RATE_UI_SELECT_SHIFT 23
 #define SJC16_DDR4_PHY_DQ_BYTE0_GDDR5_READ_ALIGNMENT_CTRL_EDC_HALF_RATE_UI_SELECT_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_GDDR5_READ_ALIGNMENT_CTRL_EDC_HALF_RATE_ENABLE_MASK 0x400000
 #define SJC16_DDR4_PHY_DQ_BYTE0_GDDR5_READ_ALIGNMENT_CTRL_EDC_HALF_RATE_ENABLE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_GDDR5_READ_ALIGNMENT_CTRL_EDC_HALF_RATE_ENABLE_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE0_GDDR5_READ_ALIGNMENT_CTRL_EDC_HALF_RATE_ENABLE_SHIFT 22
 #define SJC16_DDR4_PHY_DQ_BYTE0_GDDR5_READ_ALIGNMENT_CTRL_EDC_HALF_RATE_ENABLE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_GDDR5_READ_ALIGNMENT_CTRL_EDC_VALID_WR2RD_DELAY_DEC_MASK 0x200000
 #define SJC16_DDR4_PHY_DQ_BYTE0_GDDR5_READ_ALIGNMENT_CTRL_EDC_VALID_WR2RD_DELAY_DEC_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_GDDR5_READ_ALIGNMENT_CTRL_EDC_VALID_WR2RD_DELAY_DEC_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE0_GDDR5_READ_ALIGNMENT_CTRL_EDC_VALID_WR2RD_DELAY_DEC_SHIFT 21
 #define SJC16_DDR4_PHY_DQ_BYTE0_GDDR5_READ_ALIGNMENT_CTRL_EDC_VALID_WR2RD_DELAY_DEC_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_GDDR5_READ_ALIGNMENT_CTRL_EDC_VALID_WR2RD_DELAY_INC_MASK 0x100000
 #define SJC16_DDR4_PHY_DQ_BYTE0_GDDR5_READ_ALIGNMENT_CTRL_EDC_VALID_WR2RD_DELAY_INC_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_GDDR5_READ_ALIGNMENT_CTRL_EDC_VALID_WR2RD_DELAY_INC_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE0_GDDR5_READ_ALIGNMENT_CTRL_EDC_VALID_WR2RD_DELAY_INC_SHIFT 20
 #define SJC16_DDR4_PHY_DQ_BYTE0_GDDR5_READ_ALIGNMENT_CTRL_EDC_VALID_WR2RD_DELAY_INC_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_GDDR5_READ_ALIGNMENT_CTRL_EDC_VALID_WR2RD_DELAY_MASK 0xf0000
 #define SJC16_DDR4_PHY_DQ_BYTE0_GDDR5_READ_ALIGNMENT_CTRL_EDC_VALID_WR2RD_DELAY_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_GDDR5_READ_ALIGNMENT_CTRL_EDC_VALID_WR2RD_DELAY_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE0_GDDR5_READ_ALIGNMENT_CTRL_EDC_VALID_WR2RD_DELAY_SHIFT 16
 #define SJC16_DDR4_PHY_DQ_BYTE0_GDDR5_READ_ALIGNMENT_CTRL_EDC_VALID_WR2RD_DELAY_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_GDDR5_READ_ALIGNMENT_CTRL_EDC_UI_SHIFT_MASK 0x7000
 #define SJC16_DDR4_PHY_DQ_BYTE0_GDDR5_READ_ALIGNMENT_CTRL_EDC_UI_SHIFT_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_GDDR5_READ_ALIGNMENT_CTRL_EDC_UI_SHIFT_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE0_GDDR5_READ_ALIGNMENT_CTRL_EDC_UI_SHIFT_SHIFT 12
 #define SJC16_DDR4_PHY_DQ_BYTE0_GDDR5_READ_ALIGNMENT_CTRL_EDC_UI_SHIFT_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_GDDR5_READ_ALIGNMENT_CTRL_DATA_VALID_WR2RD_DELAY_DEC_MASK 0x200
 #define SJC16_DDR4_PHY_DQ_BYTE0_GDDR5_READ_ALIGNMENT_CTRL_DATA_VALID_WR2RD_DELAY_DEC_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_GDDR5_READ_ALIGNMENT_CTRL_DATA_VALID_WR2RD_DELAY_DEC_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE0_GDDR5_READ_ALIGNMENT_CTRL_DATA_VALID_WR2RD_DELAY_DEC_SHIFT 9
 #define SJC16_DDR4_PHY_DQ_BYTE0_GDDR5_READ_ALIGNMENT_CTRL_DATA_VALID_WR2RD_DELAY_DEC_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_GDDR5_READ_ALIGNMENT_CTRL_DATA_VALID_WR2RD_DELAY_INC_MASK 0x100
 #define SJC16_DDR4_PHY_DQ_BYTE0_GDDR5_READ_ALIGNMENT_CTRL_DATA_VALID_WR2RD_DELAY_INC_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_GDDR5_READ_ALIGNMENT_CTRL_DATA_VALID_WR2RD_DELAY_INC_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE0_GDDR5_READ_ALIGNMENT_CTRL_DATA_VALID_WR2RD_DELAY_INC_SHIFT 8
 #define SJC16_DDR4_PHY_DQ_BYTE0_GDDR5_READ_ALIGNMENT_CTRL_DATA_VALID_WR2RD_DELAY_INC_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_GDDR5_READ_ALIGNMENT_CTRL_DATA_VALID_WR2RD_DELAY_MASK 0xf0
 #define SJC16_DDR4_PHY_DQ_BYTE0_GDDR5_READ_ALIGNMENT_CTRL_DATA_VALID_WR2RD_DELAY_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_GDDR5_READ_ALIGNMENT_CTRL_DATA_VALID_WR2RD_DELAY_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE0_GDDR5_READ_ALIGNMENT_CTRL_DATA_VALID_WR2RD_DELAY_SHIFT 4
 #define SJC16_DDR4_PHY_DQ_BYTE0_GDDR5_READ_ALIGNMENT_CTRL_DATA_VALID_WR2RD_DELAY_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_GDDR5_READ_ALIGNMENT_CTRL_DATA_UI_SHIFT_MASK 0x7
 #define SJC16_DDR4_PHY_DQ_BYTE0_GDDR5_READ_ALIGNMENT_CTRL_DATA_UI_SHIFT_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_GDDR5_READ_ALIGNMENT_CTRL_DATA_UI_SHIFT_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE0_GDDR5_READ_ALIGNMENT_CTRL_DATA_UI_SHIFT_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_GDDR5_READ_ALIGNMENT_CTRL_DATA_UI_SHIFT_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_GDDR5_READ_ALIGNMENT_CTRL_RESERVED_0_MASK 0xc0000000
 #define SJC16_DDR4_PHY_DQ_BYTE0_GDDR5_READ_ALIGNMENT_CTRL_RESERVED_0_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_GDDR5_READ_ALIGNMENT_CTRL_RESERVED_0_BITS 2
 #define SJC16_DDR4_PHY_DQ_BYTE0_GDDR5_READ_ALIGNMENT_CTRL_RESERVED_0_SHIFT 30
 #define SJC16_DDR4_PHY_DQ_BYTE0_GDDR5_READ_ALIGNMENT_CTRL_RESERVED_2_MASK 0xc00
 #define SJC16_DDR4_PHY_DQ_BYTE0_GDDR5_READ_ALIGNMENT_CTRL_RESERVED_2_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_GDDR5_READ_ALIGNMENT_CTRL_RESERVED_2_BITS 2
 #define SJC16_DDR4_PHY_DQ_BYTE0_GDDR5_READ_ALIGNMENT_CTRL_RESERVED_2_SHIFT 10
 #define SJC16_DDR4_PHY_DQ_BYTE0_GDDR5_READ_ALIGNMENT_CTRL_RESERVED_MASK 0xc0000000
 #define SJC16_DDR4_PHY_DQ_BYTE0_GDDR5_READ_ALIGNMENT_CTRL_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_GDDR5_READ_ALIGNMENT_CTRL_RESERVED_BITS 2
 #define SJC16_DDR4_PHY_DQ_BYTE0_GDDR5_READ_ALIGNMENT_CTRL_RESERVED_SHIFT 30
 #define SJC16_DDR4_PHY_DQ_BYTE0_GDDR5_READ_ALIGNMENT_CTRL_ALL_MASK 0x3fffffff
 #define SJC16_DDR4_PHY_DQ_BYTE0_GDDR5_READ_ALIGNMENT_CTRL_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_GDDR5_READ_ALIGNMENT_CTRL_ALL_BITS 30
 #define SJC16_DDR4_PHY_DQ_BYTE0_GDDR5_READ_ALIGNMENT_CTRL_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_GDDR5_READ_ALIGNMENT_CTRL_ALL_MASK 0x3fffffff
 #define SJC16_DDR4_PHY_DQ_BYTE0_GDDR5_READ_ALIGNMENT_CTRL_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_GDDR5_READ_ALIGNMENT_CTRL_ALL_BITS 30
 #define SJC16_DDR4_PHY_DQ_BYTE0_GDDR5_READ_ALIGNMENT_CTRL_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_GDDR5_READ_ALIGNMENT_CTRL_DATAMASK 0x3fff73f7
 #define SJC16_DDR4_PHY_DQ_BYTE0_GDDR5_READ_ALIGNMENT_CTRL_RDWRMASK 0xc0008c08
 #define SJC16_DDR4_PHY_DQ_BYTE0_GDDR5_READ_ALIGNMENT_CTRL_RESETVALUE 0x04000000
 #define SJC16_DDR4_PHY_DQ_BYTE0_GDDR5_READ_FSM_CTRL 0x1023c08c
 #define SJC16_DDR4_PHY_DQ_BYTE0_GDDR5_READ_FSM_CTRL_BASE 0x08c
 #define SJC16_DDR4_PHY_DQ_BYTE0_GDDR5_READ_FSM_CTRL_QDR_MODE_MASK 0x8
 #define SJC16_DDR4_PHY_DQ_BYTE0_GDDR5_READ_FSM_CTRL_QDR_MODE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_GDDR5_READ_FSM_CTRL_QDR_MODE_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE0_GDDR5_READ_FSM_CTRL_QDR_MODE_SHIFT 3
 #define SJC16_DDR4_PHY_DQ_BYTE0_GDDR5_READ_FSM_CTRL_QDR_MODE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_GDDR5_READ_FSM_CTRL_DATA_VALID_GEN_ERROR_CLEAR_MASK 0x4
 #define SJC16_DDR4_PHY_DQ_BYTE0_GDDR5_READ_FSM_CTRL_DATA_VALID_GEN_ERROR_CLEAR_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_GDDR5_READ_FSM_CTRL_DATA_VALID_GEN_ERROR_CLEAR_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE0_GDDR5_READ_FSM_CTRL_DATA_VALID_GEN_ERROR_CLEAR_SHIFT 2
 #define SJC16_DDR4_PHY_DQ_BYTE0_GDDR5_READ_FSM_CTRL_DATA_VALID_GEN_ERROR_CLEAR_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_GDDR5_READ_FSM_CTRL_DATA_VALID_GEN_ENABLE_MASK 0x2
 #define SJC16_DDR4_PHY_DQ_BYTE0_GDDR5_READ_FSM_CTRL_DATA_VALID_GEN_ENABLE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_GDDR5_READ_FSM_CTRL_DATA_VALID_GEN_ENABLE_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE0_GDDR5_READ_FSM_CTRL_DATA_VALID_GEN_ENABLE_SHIFT 1
 #define SJC16_DDR4_PHY_DQ_BYTE0_GDDR5_READ_FSM_CTRL_DATA_VALID_GEN_ENABLE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_GDDR5_READ_FSM_CTRL_SYSTEM_ENABLE_MASK 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE0_GDDR5_READ_FSM_CTRL_SYSTEM_ENABLE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_GDDR5_READ_FSM_CTRL_SYSTEM_ENABLE_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE0_GDDR5_READ_FSM_CTRL_SYSTEM_ENABLE_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_GDDR5_READ_FSM_CTRL_SYSTEM_ENABLE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_GDDR5_READ_FSM_CTRL_RESERVED_MASK 0xfffffff0
 #define SJC16_DDR4_PHY_DQ_BYTE0_GDDR5_READ_FSM_CTRL_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_GDDR5_READ_FSM_CTRL_RESERVED_BITS 28
 #define SJC16_DDR4_PHY_DQ_BYTE0_GDDR5_READ_FSM_CTRL_RESERVED_SHIFT 4
 #define SJC16_DDR4_PHY_DQ_BYTE0_GDDR5_READ_FSM_CTRL_ALL_MASK 0xf
 #define SJC16_DDR4_PHY_DQ_BYTE0_GDDR5_READ_FSM_CTRL_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_GDDR5_READ_FSM_CTRL_ALL_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE0_GDDR5_READ_FSM_CTRL_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_GDDR5_READ_FSM_CTRL_ALL_MASK 0xf
 #define SJC16_DDR4_PHY_DQ_BYTE0_GDDR5_READ_FSM_CTRL_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_GDDR5_READ_FSM_CTRL_ALL_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE0_GDDR5_READ_FSM_CTRL_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_GDDR5_READ_FSM_CTRL_DATAMASK 0x0000000f
 #define SJC16_DDR4_PHY_DQ_BYTE0_GDDR5_READ_FSM_CTRL_RDWRMASK 0xfffffff0
 #define SJC16_DDR4_PHY_DQ_BYTE0_GDDR5_READ_FSM_CTRL_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_DATA_IO_CONFIG 0x1023c090
 #define SJC16_DDR4_PHY_DQ_BYTE0_DATA_IO_CONFIG_BASE 0x090
 #define SJC16_DDR4_PHY_DQ_BYTE0_DATA_IO_CONFIG_PTERM_MASK 0x1f000000
 #define SJC16_DDR4_PHY_DQ_BYTE0_DATA_IO_CONFIG_PTERM_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_DATA_IO_CONFIG_PTERM_BITS 5
 #define SJC16_DDR4_PHY_DQ_BYTE0_DATA_IO_CONFIG_PTERM_SHIFT 24
 #define SJC16_DDR4_PHY_DQ_BYTE0_DATA_IO_CONFIG_PTERM_RESETVALUE 0x10
 #define SJC16_DDR4_PHY_DQ_BYTE0_DATA_IO_CONFIG_NTERM_MASK 0xf80000
 #define SJC16_DDR4_PHY_DQ_BYTE0_DATA_IO_CONFIG_NTERM_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_DATA_IO_CONFIG_NTERM_BITS 5
 #define SJC16_DDR4_PHY_DQ_BYTE0_DATA_IO_CONFIG_NTERM_SHIFT 19
 #define SJC16_DDR4_PHY_DQ_BYTE0_DATA_IO_CONFIG_NTERM_RESETVALUE 0xf
 #define SJC16_DDR4_PHY_DQ_BYTE0_DATA_IO_CONFIG_PULL_UP_OFF_B_MASK 0x20000
 #define SJC16_DDR4_PHY_DQ_BYTE0_DATA_IO_CONFIG_PULL_UP_OFF_B_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_DATA_IO_CONFIG_PULL_UP_OFF_B_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE0_DATA_IO_CONFIG_PULL_UP_OFF_B_SHIFT 17
 #define SJC16_DDR4_PHY_DQ_BYTE0_DATA_IO_CONFIG_PULL_UP_OFF_B_RESETVALUE 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE0_DATA_IO_CONFIG_RX_BIAS_MASK 0x18000
 #define SJC16_DDR4_PHY_DQ_BYTE0_DATA_IO_CONFIG_RX_BIAS_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_DATA_IO_CONFIG_RX_BIAS_BITS 2
 #define SJC16_DDR4_PHY_DQ_BYTE0_DATA_IO_CONFIG_RX_BIAS_SHIFT 15
 #define SJC16_DDR4_PHY_DQ_BYTE0_DATA_IO_CONFIG_RX_BIAS_RESETVALUE 0x3
 #define SJC16_DDR4_PHY_DQ_BYTE0_DATA_IO_CONFIG_PEAK_MASK 0x6000
 #define SJC16_DDR4_PHY_DQ_BYTE0_DATA_IO_CONFIG_PEAK_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_DATA_IO_CONFIG_PEAK_BITS 2
 #define SJC16_DDR4_PHY_DQ_BYTE0_DATA_IO_CONFIG_PEAK_SHIFT 13
 #define SJC16_DDR4_PHY_DQ_BYTE0_DATA_IO_CONFIG_PEAK_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_DATA_IO_CONFIG_DEM_MASK 0x1800
 #define SJC16_DDR4_PHY_DQ_BYTE0_DATA_IO_CONFIG_DEM_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_DATA_IO_CONFIG_DEM_BITS 2
 #define SJC16_DDR4_PHY_DQ_BYTE0_DATA_IO_CONFIG_DEM_SHIFT 11
 #define SJC16_DDR4_PHY_DQ_BYTE0_DATA_IO_CONFIG_DEM_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_DATA_IO_CONFIG_RXENB_MASK 0x400
 #define SJC16_DDR4_PHY_DQ_BYTE0_DATA_IO_CONFIG_RXENB_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_DATA_IO_CONFIG_RXENB_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE0_DATA_IO_CONFIG_RXENB_SHIFT 10
 #define SJC16_DDR4_PHY_DQ_BYTE0_DATA_IO_CONFIG_RXENB_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_DATA_IO_CONFIG_PD_MASK 0x3e0
 #define SJC16_DDR4_PHY_DQ_BYTE0_DATA_IO_CONFIG_PD_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_DATA_IO_CONFIG_PD_BITS 5
 #define SJC16_DDR4_PHY_DQ_BYTE0_DATA_IO_CONFIG_PD_SHIFT 5
 #define SJC16_DDR4_PHY_DQ_BYTE0_DATA_IO_CONFIG_PD_RESETVALUE 0x10
 #define SJC16_DDR4_PHY_DQ_BYTE0_DATA_IO_CONFIG_ND_MASK 0x1f
 #define SJC16_DDR4_PHY_DQ_BYTE0_DATA_IO_CONFIG_ND_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_DATA_IO_CONFIG_ND_BITS 5
 #define SJC16_DDR4_PHY_DQ_BYTE0_DATA_IO_CONFIG_ND_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_DATA_IO_CONFIG_ND_RESETVALUE 0xf
 #define SJC16_DDR4_PHY_DQ_BYTE0_DATA_IO_CONFIG_RESERVED_MASK 0xe0000000
 #define SJC16_DDR4_PHY_DQ_BYTE0_DATA_IO_CONFIG_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_DATA_IO_CONFIG_RESERVED_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE0_DATA_IO_CONFIG_RESERVED_SHIFT 29
 #define SJC16_DDR4_PHY_DQ_BYTE0_DATA_IO_CONFIG_ALL_MASK 0x1fffffff
 #define SJC16_DDR4_PHY_DQ_BYTE0_DATA_IO_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_DATA_IO_CONFIG_ALL_BITS 29
 #define SJC16_DDR4_PHY_DQ_BYTE0_DATA_IO_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_DATA_IO_CONFIG_ALL_MASK 0x1fffffff
 #define SJC16_DDR4_PHY_DQ_BYTE0_DATA_IO_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_DATA_IO_CONFIG_ALL_BITS 29
 #define SJC16_DDR4_PHY_DQ_BYTE0_DATA_IO_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_DATA_IO_CONFIG_DATAMASK 0x1ffbffff
 #define SJC16_DDR4_PHY_DQ_BYTE0_DATA_IO_CONFIG_RDWRMASK 0xe0040000
 #define SJC16_DDR4_PHY_DQ_BYTE0_DATA_IO_CONFIG_RESETVALUE 0x107b820f
 #define SJC16_DDR4_PHY_DQ_BYTE0_DQS_IO_CONFIG 0x1023c094
 #define SJC16_DDR4_PHY_DQ_BYTE0_DQS_IO_CONFIG_BASE 0x094
 #define SJC16_DDR4_PHY_DQ_BYTE0_DQS_IO_CONFIG_PTERM_MASK 0x1f000000
 #define SJC16_DDR4_PHY_DQ_BYTE0_DQS_IO_CONFIG_PTERM_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_DQS_IO_CONFIG_PTERM_BITS 5
 #define SJC16_DDR4_PHY_DQ_BYTE0_DQS_IO_CONFIG_PTERM_SHIFT 24
 #define SJC16_DDR4_PHY_DQ_BYTE0_DQS_IO_CONFIG_PTERM_RESETVALUE 0x10
 #define SJC16_DDR4_PHY_DQ_BYTE0_DQS_IO_CONFIG_NTERM_MASK 0xf80000
 #define SJC16_DDR4_PHY_DQ_BYTE0_DQS_IO_CONFIG_NTERM_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_DQS_IO_CONFIG_NTERM_BITS 5
 #define SJC16_DDR4_PHY_DQ_BYTE0_DQS_IO_CONFIG_NTERM_SHIFT 19
 #define SJC16_DDR4_PHY_DQ_BYTE0_DQS_IO_CONFIG_NTERM_RESETVALUE 0xf
 #define SJC16_DDR4_PHY_DQ_BYTE0_DQS_IO_CONFIG_PULL_UP_OFF_B_MASK 0x20000
 #define SJC16_DDR4_PHY_DQ_BYTE0_DQS_IO_CONFIG_PULL_UP_OFF_B_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_DQS_IO_CONFIG_PULL_UP_OFF_B_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE0_DQS_IO_CONFIG_PULL_UP_OFF_B_SHIFT 17
 #define SJC16_DDR4_PHY_DQ_BYTE0_DQS_IO_CONFIG_PULL_UP_OFF_B_RESETVALUE 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE0_DQS_IO_CONFIG_RX_BIAS_MASK 0x18000
 #define SJC16_DDR4_PHY_DQ_BYTE0_DQS_IO_CONFIG_RX_BIAS_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_DQS_IO_CONFIG_RX_BIAS_BITS 2
 #define SJC16_DDR4_PHY_DQ_BYTE0_DQS_IO_CONFIG_RX_BIAS_SHIFT 15
 #define SJC16_DDR4_PHY_DQ_BYTE0_DQS_IO_CONFIG_RX_BIAS_RESETVALUE 0x3
 #define SJC16_DDR4_PHY_DQ_BYTE0_DQS_IO_CONFIG_PEAK_MASK 0x6000
 #define SJC16_DDR4_PHY_DQ_BYTE0_DQS_IO_CONFIG_PEAK_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_DQS_IO_CONFIG_PEAK_BITS 2
 #define SJC16_DDR4_PHY_DQ_BYTE0_DQS_IO_CONFIG_PEAK_SHIFT 13
 #define SJC16_DDR4_PHY_DQ_BYTE0_DQS_IO_CONFIG_PEAK_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_DQS_IO_CONFIG_DEM_MASK 0x1800
 #define SJC16_DDR4_PHY_DQ_BYTE0_DQS_IO_CONFIG_DEM_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_DQS_IO_CONFIG_DEM_BITS 2
 #define SJC16_DDR4_PHY_DQ_BYTE0_DQS_IO_CONFIG_DEM_SHIFT 11
 #define SJC16_DDR4_PHY_DQ_BYTE0_DQS_IO_CONFIG_DEM_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_DQS_IO_CONFIG_RXENB_MASK 0x400
 #define SJC16_DDR4_PHY_DQ_BYTE0_DQS_IO_CONFIG_RXENB_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_DQS_IO_CONFIG_RXENB_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE0_DQS_IO_CONFIG_RXENB_SHIFT 10
 #define SJC16_DDR4_PHY_DQ_BYTE0_DQS_IO_CONFIG_RXENB_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_DQS_IO_CONFIG_PD_MASK 0x3e0
 #define SJC16_DDR4_PHY_DQ_BYTE0_DQS_IO_CONFIG_PD_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_DQS_IO_CONFIG_PD_BITS 5
 #define SJC16_DDR4_PHY_DQ_BYTE0_DQS_IO_CONFIG_PD_SHIFT 5
 #define SJC16_DDR4_PHY_DQ_BYTE0_DQS_IO_CONFIG_PD_RESETVALUE 0x10
 #define SJC16_DDR4_PHY_DQ_BYTE0_DQS_IO_CONFIG_ND_MASK 0x1f
 #define SJC16_DDR4_PHY_DQ_BYTE0_DQS_IO_CONFIG_ND_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_DQS_IO_CONFIG_ND_BITS 5
 #define SJC16_DDR4_PHY_DQ_BYTE0_DQS_IO_CONFIG_ND_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_DQS_IO_CONFIG_ND_RESETVALUE 0xf
 #define SJC16_DDR4_PHY_DQ_BYTE0_DQS_IO_CONFIG_RESERVED_MASK 0xe0000000
 #define SJC16_DDR4_PHY_DQ_BYTE0_DQS_IO_CONFIG_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_DQS_IO_CONFIG_RESERVED_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE0_DQS_IO_CONFIG_RESERVED_SHIFT 29
 #define SJC16_DDR4_PHY_DQ_BYTE0_DQS_IO_CONFIG_ALL_MASK 0x1fffffff
 #define SJC16_DDR4_PHY_DQ_BYTE0_DQS_IO_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_DQS_IO_CONFIG_ALL_BITS 29
 #define SJC16_DDR4_PHY_DQ_BYTE0_DQS_IO_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_DQS_IO_CONFIG_ALL_MASK 0x1fffffff
 #define SJC16_DDR4_PHY_DQ_BYTE0_DQS_IO_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_DQS_IO_CONFIG_ALL_BITS 29
 #define SJC16_DDR4_PHY_DQ_BYTE0_DQS_IO_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_DQS_IO_CONFIG_DATAMASK 0x1ffbffff
 #define SJC16_DDR4_PHY_DQ_BYTE0_DQS_IO_CONFIG_RDWRMASK 0xe0040000
 #define SJC16_DDR4_PHY_DQ_BYTE0_DQS_IO_CONFIG_RESETVALUE 0x107b820f
 #define SJC16_DDR4_PHY_DQ_BYTE0_VREF_DAC_CONFIG 0x1023c098
 #define SJC16_DDR4_PHY_DQ_BYTE0_VREF_DAC_CONFIG_BASE 0x098
 #define SJC16_DDR4_PHY_DQ_BYTE0_VREF_DAC_CONFIG_DATA_MASK 0xff0000
 #define SJC16_DDR4_PHY_DQ_BYTE0_VREF_DAC_CONFIG_DATA_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_VREF_DAC_CONFIG_DATA_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE0_VREF_DAC_CONFIG_DATA_SHIFT 16
 #define SJC16_DDR4_PHY_DQ_BYTE0_VREF_DAC_CONFIG_DATA_RESETVALUE 0x92
 #define SJC16_DDR4_PHY_DQ_BYTE0_VREF_DAC_CONFIG_CTRL_MASK 0xff
 #define SJC16_DDR4_PHY_DQ_BYTE0_VREF_DAC_CONFIG_CTRL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_VREF_DAC_CONFIG_CTRL_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE0_VREF_DAC_CONFIG_CTRL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_VREF_DAC_CONFIG_CTRL_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE0_VREF_DAC_CONFIG_RESERVED_MASK 0xff000000
 #define SJC16_DDR4_PHY_DQ_BYTE0_VREF_DAC_CONFIG_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_VREF_DAC_CONFIG_RESERVED_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE0_VREF_DAC_CONFIG_RESERVED_SHIFT 24
 #define SJC16_DDR4_PHY_DQ_BYTE0_VREF_DAC_CONFIG_ALL_MASK 0xffffff
 #define SJC16_DDR4_PHY_DQ_BYTE0_VREF_DAC_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_VREF_DAC_CONFIG_ALL_BITS 24
 #define SJC16_DDR4_PHY_DQ_BYTE0_VREF_DAC_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_VREF_DAC_CONFIG_ALL_MASK 0xffffff
 #define SJC16_DDR4_PHY_DQ_BYTE0_VREF_DAC_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_VREF_DAC_CONFIG_ALL_BITS 24
 #define SJC16_DDR4_PHY_DQ_BYTE0_VREF_DAC_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_VREF_DAC_CONFIG_DATAMASK 0x00ff00ff
 #define SJC16_DDR4_PHY_DQ_BYTE0_VREF_DAC_CONFIG_RDWRMASK 0xff00ff00
 #define SJC16_DDR4_PHY_DQ_BYTE0_VREF_DAC_CONFIG_RESETVALUE 0x920000
 #define SJC16_DDR4_PHY_DQ_BYTE0_LDO_R_CONFIG 0x1023c09c
 #define SJC16_DDR4_PHY_DQ_BYTE0_LDO_R_CONFIG_BASE 0x09c
 #define SJC16_DDR4_PHY_DQ_BYTE0_LDO_R_CONFIG_REF_SEL_EXT_MASK 0x2000
 #define SJC16_DDR4_PHY_DQ_BYTE0_LDO_R_CONFIG_REF_SEL_EXT_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_LDO_R_CONFIG_REF_SEL_EXT_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE0_LDO_R_CONFIG_REF_SEL_EXT_SHIFT 13
 #define SJC16_DDR4_PHY_DQ_BYTE0_LDO_R_CONFIG_REF_SEL_EXT_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_LDO_R_CONFIG_REF_EXT_MASK 0x1000
 #define SJC16_DDR4_PHY_DQ_BYTE0_LDO_R_CONFIG_REF_EXT_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_LDO_R_CONFIG_REF_EXT_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE0_LDO_R_CONFIG_REF_EXT_SHIFT 12
 #define SJC16_DDR4_PHY_DQ_BYTE0_LDO_R_CONFIG_REF_EXT_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_LDO_R_CONFIG_PWRDN_MASK 0x200
 #define SJC16_DDR4_PHY_DQ_BYTE0_LDO_R_CONFIG_PWRDN_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_LDO_R_CONFIG_PWRDN_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE0_LDO_R_CONFIG_PWRDN_SHIFT 9
 #define SJC16_DDR4_PHY_DQ_BYTE0_LDO_R_CONFIG_PWRDN_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_LDO_R_CONFIG_CTRL_MASK 0x1f8
 #define SJC16_DDR4_PHY_DQ_BYTE0_LDO_R_CONFIG_CTRL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_LDO_R_CONFIG_CTRL_BITS 6
 #define SJC16_DDR4_PHY_DQ_BYTE0_LDO_R_CONFIG_CTRL_SHIFT 3
 #define SJC16_DDR4_PHY_DQ_BYTE0_LDO_R_CONFIG_CTRL_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_LDO_R_CONFIG_BYPASS_MASK 0x4
 #define SJC16_DDR4_PHY_DQ_BYTE0_LDO_R_CONFIG_BYPASS_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_LDO_R_CONFIG_BYPASS_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE0_LDO_R_CONFIG_BYPASS_SHIFT 2
 #define SJC16_DDR4_PHY_DQ_BYTE0_LDO_R_CONFIG_BYPASS_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_LDO_R_CONFIG_BIAS_CTRL_MASK 0x3
 #define SJC16_DDR4_PHY_DQ_BYTE0_LDO_R_CONFIG_BIAS_CTRL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_LDO_R_CONFIG_BIAS_CTRL_BITS 2
 #define SJC16_DDR4_PHY_DQ_BYTE0_LDO_R_CONFIG_BIAS_CTRL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_LDO_R_CONFIG_BIAS_CTRL_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_LDO_R_CONFIG_RESERVED_MASK 0xffffc000
 #define SJC16_DDR4_PHY_DQ_BYTE0_LDO_R_CONFIG_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_LDO_R_CONFIG_RESERVED_BITS 18
 #define SJC16_DDR4_PHY_DQ_BYTE0_LDO_R_CONFIG_RESERVED_SHIFT 14
 #define SJC16_DDR4_PHY_DQ_BYTE0_LDO_R_CONFIG_ALL_MASK 0x3fff
 #define SJC16_DDR4_PHY_DQ_BYTE0_LDO_R_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_LDO_R_CONFIG_ALL_BITS 14
 #define SJC16_DDR4_PHY_DQ_BYTE0_LDO_R_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_LDO_R_CONFIG_ALL_MASK 0x3fff
 #define SJC16_DDR4_PHY_DQ_BYTE0_LDO_R_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_LDO_R_CONFIG_ALL_BITS 14
 #define SJC16_DDR4_PHY_DQ_BYTE0_LDO_R_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_LDO_R_CONFIG_DATAMASK 0x000033ff
 #define SJC16_DDR4_PHY_DQ_BYTE0_LDO_R_CONFIG_RDWRMASK 0xffffcc00
 #define SJC16_DDR4_PHY_DQ_BYTE0_LDO_R_CONFIG_RESETVALUE 0x0000
 #define SJC16_DDR4_PHY_DQ_BYTE0_LDO_W_CONFIG 0x1023c0a0
 #define SJC16_DDR4_PHY_DQ_BYTE0_LDO_W_CONFIG_BASE 0x0a0
 #define SJC16_DDR4_PHY_DQ_BYTE0_LDO_W_CONFIG_REF_SEL_EXT_MASK 0x2000
 #define SJC16_DDR4_PHY_DQ_BYTE0_LDO_W_CONFIG_REF_SEL_EXT_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_LDO_W_CONFIG_REF_SEL_EXT_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE0_LDO_W_CONFIG_REF_SEL_EXT_SHIFT 13
 #define SJC16_DDR4_PHY_DQ_BYTE0_LDO_W_CONFIG_REF_SEL_EXT_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_LDO_W_CONFIG_REF_EXT_MASK 0x1000
 #define SJC16_DDR4_PHY_DQ_BYTE0_LDO_W_CONFIG_REF_EXT_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_LDO_W_CONFIG_REF_EXT_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE0_LDO_W_CONFIG_REF_EXT_SHIFT 12
 #define SJC16_DDR4_PHY_DQ_BYTE0_LDO_W_CONFIG_REF_EXT_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_LDO_W_CONFIG_PWRDN_MASK 0x200
 #define SJC16_DDR4_PHY_DQ_BYTE0_LDO_W_CONFIG_PWRDN_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_LDO_W_CONFIG_PWRDN_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE0_LDO_W_CONFIG_PWRDN_SHIFT 9
 #define SJC16_DDR4_PHY_DQ_BYTE0_LDO_W_CONFIG_PWRDN_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_LDO_W_CONFIG_CTRL_MASK 0x1f8
 #define SJC16_DDR4_PHY_DQ_BYTE0_LDO_W_CONFIG_CTRL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_LDO_W_CONFIG_CTRL_BITS 6
 #define SJC16_DDR4_PHY_DQ_BYTE0_LDO_W_CONFIG_CTRL_SHIFT 3
 #define SJC16_DDR4_PHY_DQ_BYTE0_LDO_W_CONFIG_CTRL_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_LDO_W_CONFIG_BYPASS_MASK 0x4
 #define SJC16_DDR4_PHY_DQ_BYTE0_LDO_W_CONFIG_BYPASS_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_LDO_W_CONFIG_BYPASS_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE0_LDO_W_CONFIG_BYPASS_SHIFT 2
 #define SJC16_DDR4_PHY_DQ_BYTE0_LDO_W_CONFIG_BYPASS_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_LDO_W_CONFIG_BIAS_CTRL_MASK 0x3
 #define SJC16_DDR4_PHY_DQ_BYTE0_LDO_W_CONFIG_BIAS_CTRL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_LDO_W_CONFIG_BIAS_CTRL_BITS 2
 #define SJC16_DDR4_PHY_DQ_BYTE0_LDO_W_CONFIG_BIAS_CTRL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_LDO_W_CONFIG_BIAS_CTRL_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_LDO_W_CONFIG_RESERVED_MASK 0xffffc000
 #define SJC16_DDR4_PHY_DQ_BYTE0_LDO_W_CONFIG_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_LDO_W_CONFIG_RESERVED_BITS 18
 #define SJC16_DDR4_PHY_DQ_BYTE0_LDO_W_CONFIG_RESERVED_SHIFT 14
 #define SJC16_DDR4_PHY_DQ_BYTE0_LDO_W_CONFIG_ALL_MASK 0x3fff
 #define SJC16_DDR4_PHY_DQ_BYTE0_LDO_W_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_LDO_W_CONFIG_ALL_BITS 14
 #define SJC16_DDR4_PHY_DQ_BYTE0_LDO_W_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_LDO_W_CONFIG_ALL_MASK 0x3fff
 #define SJC16_DDR4_PHY_DQ_BYTE0_LDO_W_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_LDO_W_CONFIG_ALL_BITS 14
 #define SJC16_DDR4_PHY_DQ_BYTE0_LDO_W_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_LDO_W_CONFIG_DATAMASK 0x000033ff
 #define SJC16_DDR4_PHY_DQ_BYTE0_LDO_W_CONFIG_RDWRMASK 0xffffcc00
 #define SJC16_DDR4_PHY_DQ_BYTE0_LDO_W_CONFIG_RESETVALUE 0x0000
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_OPERATION_CONFIG 0x1023c0a4
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_OPERATION_CONFIG_BASE 0x0a4
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_OPERATION_CONFIG_CLEAR_ACTIVITY_STATS_MASK 0x10000000
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_OPERATION_CONFIG_CLEAR_ACTIVITY_STATS_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_OPERATION_CONFIG_CLEAR_ACTIVITY_STATS_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_OPERATION_CONFIG_CLEAR_ACTIVITY_STATS_SHIFT 28
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_OPERATION_CONFIG_CLEAR_ACTIVITY_STATS_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_OPERATION_CONFIG_FIFO_W2R_MIN_DELAY_2_MASK 0x8000000
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_OPERATION_CONFIG_FIFO_W2R_MIN_DELAY_2_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_OPERATION_CONFIG_FIFO_W2R_MIN_DELAY_2_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_OPERATION_CONFIG_FIFO_W2R_MIN_DELAY_2_SHIFT 27
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_OPERATION_CONFIG_FIFO_W2R_MIN_DELAY_2_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_OPERATION_CONFIG_ROLLOVER_MODE_MASK 0x7000000
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_OPERATION_CONFIG_ROLLOVER_MODE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_OPERATION_CONFIG_ROLLOVER_MODE_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_OPERATION_CONFIG_ROLLOVER_MODE_SHIFT 24
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_OPERATION_CONFIG_ROLLOVER_MODE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_OPERATION_CONFIG_HALF_RATE_MODE_MASK 0x800000
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_OPERATION_CONFIG_HALF_RATE_MODE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_OPERATION_CONFIG_HALF_RATE_MODE_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_OPERATION_CONFIG_HALF_RATE_MODE_SHIFT 23
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_OPERATION_CONFIG_HALF_RATE_MODE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_OPERATION_CONFIG_INIT_TRACK_OPTIONS_MASK 0x600000
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_OPERATION_CONFIG_INIT_TRACK_OPTIONS_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_OPERATION_CONFIG_INIT_TRACK_OPTIONS_BITS 2
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_OPERATION_CONFIG_INIT_TRACK_OPTIONS_SHIFT 21
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_OPERATION_CONFIG_INIT_TRACK_OPTIONS_RESETVALUE 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_OPERATION_CONFIG_INIT_TRACK_TRANSITION_MASK 0x100000
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_OPERATION_CONFIG_INIT_TRACK_TRANSITION_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_OPERATION_CONFIG_INIT_TRACK_TRANSITION_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_OPERATION_CONFIG_INIT_TRACK_TRANSITION_SHIFT 20
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_OPERATION_CONFIG_INIT_TRACK_TRANSITION_RESETVALUE 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_OPERATION_CONFIG_ACCU_POS_THRESHOLD_MASK 0xff000
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_OPERATION_CONFIG_ACCU_POS_THRESHOLD_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_OPERATION_CONFIG_ACCU_POS_THRESHOLD_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_OPERATION_CONFIG_ACCU_POS_THRESHOLD_SHIFT 12
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_OPERATION_CONFIG_ACCU_POS_THRESHOLD_RESETVALUE 0x10
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_OPERATION_CONFIG_ACCU_LOAD_VALUE_MASK 0xff0
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_OPERATION_CONFIG_ACCU_LOAD_VALUE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_OPERATION_CONFIG_ACCU_LOAD_VALUE_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_OPERATION_CONFIG_ACCU_LOAD_VALUE_SHIFT 4
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_OPERATION_CONFIG_ACCU_LOAD_VALUE_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_OPERATION_CONFIG_ACCU_LOAD_MASK 0x8
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_OPERATION_CONFIG_ACCU_LOAD_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_OPERATION_CONFIG_ACCU_LOAD_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_OPERATION_CONFIG_ACCU_LOAD_SHIFT 3
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_OPERATION_CONFIG_ACCU_LOAD_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_OPERATION_CONFIG_UPDATE_MODE_MASK 0x6
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_OPERATION_CONFIG_UPDATE_MODE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_OPERATION_CONFIG_UPDATE_MODE_BITS 2
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_OPERATION_CONFIG_UPDATE_MODE_SHIFT 1
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_OPERATION_CONFIG_UPDATE_MODE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_OPERATION_CONFIG_ENABLE_MASK 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_OPERATION_CONFIG_ENABLE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_OPERATION_CONFIG_ENABLE_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_OPERATION_CONFIG_ENABLE_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_OPERATION_CONFIG_ENABLE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_OPERATION_CONFIG_RESERVED_MASK 0xe0000000
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_OPERATION_CONFIG_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_OPERATION_CONFIG_RESERVED_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_OPERATION_CONFIG_RESERVED_SHIFT 29
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_OPERATION_CONFIG_ALL_MASK 0x1fffffff
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_OPERATION_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_OPERATION_CONFIG_ALL_BITS 29
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_OPERATION_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_OPERATION_CONFIG_ALL_MASK 0x1fffffff
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_OPERATION_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_OPERATION_CONFIG_ALL_BITS 29
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_OPERATION_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_OPERATION_CONFIG_DATAMASK 0x1fffffff
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_OPERATION_CONFIG_RDWRMASK 0xe0000000
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_OPERATION_CONFIG_RESETVALUE 0x00310000
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_UPDATE_CONFIG 0x1023c0a8
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_UPDATE_CONFIG_BASE 0x0a8
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_UPDATE_CONFIG_ROLLOVER_PHASE_GAP_MASK 0xfc000000
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_UPDATE_CONFIG_ROLLOVER_PHASE_GAP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_UPDATE_CONFIG_ROLLOVER_PHASE_GAP_BITS 6
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_UPDATE_CONFIG_ROLLOVER_PHASE_GAP_SHIFT 26
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_UPDATE_CONFIG_ROLLOVER_PHASE_GAP_RESETVALUE 0x3
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_UPDATE_CONFIG_ROLLOVER_AMOUNT_MASK 0x1ff0000
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_UPDATE_CONFIG_ROLLOVER_AMOUNT_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_UPDATE_CONFIG_ROLLOVER_AMOUNT_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_UPDATE_CONFIG_ROLLOVER_AMOUNT_SHIFT 16
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_UPDATE_CONFIG_ROLLOVER_AMOUNT_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_UPDATE_CONFIG_UPDATE_ENABLE_DELAY_MASK 0x3f00
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_UPDATE_CONFIG_UPDATE_ENABLE_DELAY_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_UPDATE_CONFIG_UPDATE_ENABLE_DELAY_BITS 6
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_UPDATE_CONFIG_UPDATE_ENABLE_DELAY_SHIFT 8
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_UPDATE_CONFIG_UPDATE_ENABLE_DELAY_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_UPDATE_CONFIG_IMMEDIATE_UPDATE_THRESHOLD_MASK 0xf0
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_UPDATE_CONFIG_IMMEDIATE_UPDATE_THRESHOLD_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_UPDATE_CONFIG_IMMEDIATE_UPDATE_THRESHOLD_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_UPDATE_CONFIG_IMMEDIATE_UPDATE_THRESHOLD_SHIFT 4
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_UPDATE_CONFIG_IMMEDIATE_UPDATE_THRESHOLD_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_UPDATE_CONFIG_VDL_UPDATE_GAP_MASK 0xf
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_UPDATE_CONFIG_VDL_UPDATE_GAP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_UPDATE_CONFIG_VDL_UPDATE_GAP_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_UPDATE_CONFIG_VDL_UPDATE_GAP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_UPDATE_CONFIG_VDL_UPDATE_GAP_RESETVALUE 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_UPDATE_CONFIG_ALL_MASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_UPDATE_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_UPDATE_CONFIG_ALL_BITS 32
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_UPDATE_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_UPDATE_CONFIG_ALL_MASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_UPDATE_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_UPDATE_CONFIG_ALL_BITS 32
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_UPDATE_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_UPDATE_CONFIG_DATAMASK 0xfdff3fff
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_UPDATE_CONFIG_RDWRMASK 0x0200c000
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_UPDATE_CONFIG_RESETVALUE 0x0c000001
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_TRACK_CONFIG 0x1023c0ac
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_TRACK_CONFIG_BASE 0x0ac
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_TRACK_CONFIG_SEARCH_ACTIVE_TIMEOUT_MASK 0xf000
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_TRACK_CONFIG_SEARCH_ACTIVE_TIMEOUT_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_TRACK_CONFIG_SEARCH_ACTIVE_TIMEOUT_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_TRACK_CONFIG_SEARCH_ACTIVE_TIMEOUT_SHIFT 12
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_TRACK_CONFIG_SEARCH_ACTIVE_TIMEOUT_RESETVALUE 0xf
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_TRACK_CONFIG_TRACK_ACTIVE_TIMEOUT_MASK 0xf00
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_TRACK_CONFIG_TRACK_ACTIVE_TIMEOUT_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_TRACK_CONFIG_TRACK_ACTIVE_TIMEOUT_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_TRACK_CONFIG_TRACK_ACTIVE_TIMEOUT_SHIFT 8
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_TRACK_CONFIG_TRACK_ACTIVE_TIMEOUT_RESETVALUE 0xf
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_TRACK_CONFIG_ACCU_ACTIVE_TIMEOUT_MASK 0xff
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_TRACK_CONFIG_ACCU_ACTIVE_TIMEOUT_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_TRACK_CONFIG_ACCU_ACTIVE_TIMEOUT_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_TRACK_CONFIG_ACCU_ACTIVE_TIMEOUT_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_TRACK_CONFIG_ACCU_ACTIVE_TIMEOUT_RESETVALUE 0xff
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_TRACK_CONFIG_RESERVED_MASK 0xffff0000
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_TRACK_CONFIG_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_TRACK_CONFIG_RESERVED_BITS 16
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_TRACK_CONFIG_RESERVED_SHIFT 16
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_TRACK_CONFIG_ALL_MASK 0xffff
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_TRACK_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_TRACK_CONFIG_ALL_BITS 16
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_TRACK_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_TRACK_CONFIG_ALL_MASK 0xffff
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_TRACK_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_TRACK_CONFIG_ALL_BITS 16
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_TRACK_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_TRACK_CONFIG_DATAMASK 0x0000ffff
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_TRACK_CONFIG_RDWRMASK 0xffff0000
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_TRACK_CONFIG_RESETVALUE 0xffff
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_TIMING_CONFIG 0x1023c0b0
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_TIMING_CONFIG_BASE 0x0b0
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_TIMING_CONFIG_DATA_VALID_WR2RD_DELAY_LOAD_VALUE_MASK 0xf0000
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_TIMING_CONFIG_DATA_VALID_WR2RD_DELAY_LOAD_VALUE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_TIMING_CONFIG_DATA_VALID_WR2RD_DELAY_LOAD_VALUE_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_TIMING_CONFIG_DATA_VALID_WR2RD_DELAY_LOAD_VALUE_SHIFT 16
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_TIMING_CONFIG_DATA_VALID_WR2RD_DELAY_LOAD_VALUE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_TIMING_CONFIG_EDC_VALID_WR2RD_DELAY_LOAD_VALUE_MASK 0xf000
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_TIMING_CONFIG_EDC_VALID_WR2RD_DELAY_LOAD_VALUE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_TIMING_CONFIG_EDC_VALID_WR2RD_DELAY_LOAD_VALUE_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_TIMING_CONFIG_EDC_VALID_WR2RD_DELAY_LOAD_VALUE_SHIFT 12
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_TIMING_CONFIG_EDC_VALID_WR2RD_DELAY_LOAD_VALUE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_TIMING_CONFIG_DATA_READ_UI_SHIFT_LOAD_VALUE_MASK 0x700
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_TIMING_CONFIG_DATA_READ_UI_SHIFT_LOAD_VALUE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_TIMING_CONFIG_DATA_READ_UI_SHIFT_LOAD_VALUE_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_TIMING_CONFIG_DATA_READ_UI_SHIFT_LOAD_VALUE_SHIFT 8
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_TIMING_CONFIG_DATA_READ_UI_SHIFT_LOAD_VALUE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_TIMING_CONFIG_EDC_READ_UI_SHIFT_LOAD_VALUE_MASK 0x70
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_TIMING_CONFIG_EDC_READ_UI_SHIFT_LOAD_VALUE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_TIMING_CONFIG_EDC_READ_UI_SHIFT_LOAD_VALUE_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_TIMING_CONFIG_EDC_READ_UI_SHIFT_LOAD_VALUE_SHIFT 4
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_TIMING_CONFIG_EDC_READ_UI_SHIFT_LOAD_VALUE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_TIMING_CONFIG_CLEAR_VDL_STATS_ON_ROLLOVER_MASK 0x8
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_TIMING_CONFIG_CLEAR_VDL_STATS_ON_ROLLOVER_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_TIMING_CONFIG_CLEAR_VDL_STATS_ON_ROLLOVER_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_TIMING_CONFIG_CLEAR_VDL_STATS_ON_ROLLOVER_SHIFT 3
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_TIMING_CONFIG_CLEAR_VDL_STATS_ON_ROLLOVER_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_TIMING_CONFIG_CLEAR_VDL_STATS_MASK 0x4
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_TIMING_CONFIG_CLEAR_VDL_STATS_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_TIMING_CONFIG_CLEAR_VDL_STATS_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_TIMING_CONFIG_CLEAR_VDL_STATS_SHIFT 2
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_TIMING_CONFIG_CLEAR_VDL_STATS_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_TIMING_CONFIG_VDL_SWITCH_MASK 0x2
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_TIMING_CONFIG_VDL_SWITCH_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_TIMING_CONFIG_VDL_SWITCH_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_TIMING_CONFIG_VDL_SWITCH_SHIFT 1
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_TIMING_CONFIG_VDL_SWITCH_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_TIMING_CONFIG_VDL_LOAD_MASK 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_TIMING_CONFIG_VDL_LOAD_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_TIMING_CONFIG_VDL_LOAD_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_TIMING_CONFIG_VDL_LOAD_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_TIMING_CONFIG_VDL_LOAD_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_TIMING_CONFIG_RESERVED_0_MASK 0xfff00000
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_TIMING_CONFIG_RESERVED_0_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_TIMING_CONFIG_RESERVED_0_BITS 12
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_TIMING_CONFIG_RESERVED_0_SHIFT 20
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_TIMING_CONFIG_RESERVED_MASK 0xfff00000
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_TIMING_CONFIG_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_TIMING_CONFIG_RESERVED_BITS 12
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_TIMING_CONFIG_RESERVED_SHIFT 20
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_TIMING_CONFIG_ALL_MASK 0xfffff
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_TIMING_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_TIMING_CONFIG_ALL_BITS 20
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_TIMING_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_TIMING_CONFIG_ALL_MASK 0xfffff
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_TIMING_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_TIMING_CONFIG_ALL_BITS 20
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_TIMING_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_TIMING_CONFIG_DATAMASK 0x000ff77f
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_TIMING_CONFIG_RDWRMASK 0xfff00880
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_TIMING_CONFIG_RESETVALUE 0x00000
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_VDL_CAP_CONFIG 0x1023c0b4
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_VDL_CAP_CONFIG_BASE 0x0b4
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_VDL_CAP_CONFIG_FLEXIBLE_VDL_CAP_MASK 0x10000000
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_VDL_CAP_CONFIG_FLEXIBLE_VDL_CAP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_VDL_CAP_CONFIG_FLEXIBLE_VDL_CAP_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_VDL_CAP_CONFIG_FLEXIBLE_VDL_CAP_SHIFT 28
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_VDL_CAP_CONFIG_FLEXIBLE_VDL_CAP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_VDL_CAP_CONFIG_VDL_MAX_VALUE_CAP_MASK 0x1ff0000
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_VDL_CAP_CONFIG_VDL_MAX_VALUE_CAP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_VDL_CAP_CONFIG_VDL_MAX_VALUE_CAP_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_VDL_CAP_CONFIG_VDL_MAX_VALUE_CAP_SHIFT 16
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_VDL_CAP_CONFIG_VDL_MAX_VALUE_CAP_RESETVALUE 0x1ff
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_VDL_CAP_CONFIG_VDL_MIN_VALUE_CAP_MASK 0x1ff
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_VDL_CAP_CONFIG_VDL_MIN_VALUE_CAP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_VDL_CAP_CONFIG_VDL_MIN_VALUE_CAP_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_VDL_CAP_CONFIG_VDL_MIN_VALUE_CAP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_VDL_CAP_CONFIG_VDL_MIN_VALUE_CAP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_VDL_CAP_CONFIG_RESERVED_0_MASK 0xe0000000
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_VDL_CAP_CONFIG_RESERVED_0_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_VDL_CAP_CONFIG_RESERVED_0_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_VDL_CAP_CONFIG_RESERVED_0_SHIFT 29
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_VDL_CAP_CONFIG_RESERVED_1_MASK 0xe000000
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_VDL_CAP_CONFIG_RESERVED_1_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_VDL_CAP_CONFIG_RESERVED_1_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_VDL_CAP_CONFIG_RESERVED_1_SHIFT 25
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_VDL_CAP_CONFIG_RESERVED_2_MASK 0xfe00
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_VDL_CAP_CONFIG_RESERVED_2_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_VDL_CAP_CONFIG_RESERVED_2_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_VDL_CAP_CONFIG_RESERVED_2_SHIFT 9
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_VDL_CAP_CONFIG_RESERVED_MASK 0xe0000000
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_VDL_CAP_CONFIG_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_VDL_CAP_CONFIG_RESERVED_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_VDL_CAP_CONFIG_RESERVED_SHIFT 29
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_VDL_CAP_CONFIG_ALL_MASK 0x1fffffff
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_VDL_CAP_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_VDL_CAP_CONFIG_ALL_BITS 29
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_VDL_CAP_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_VDL_CAP_CONFIG_ALL_MASK 0x1fffffff
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_VDL_CAP_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_VDL_CAP_CONFIG_ALL_BITS 29
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_VDL_CAP_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_VDL_CAP_CONFIG_DATAMASK 0x11ff01ff
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_VDL_CAP_CONFIG_RDWRMASK 0xee00fe00
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_VDL_CAP_CONFIG_RESETVALUE 0x01ff0000
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_P_VDL_CONFIG 0x1023c0b8
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_P_VDL_CONFIG_BASE 0x0b8
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_P_VDL_CONFIG_DP_VDL_LOAD_VALUE_MASK 0x1ff0000
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_P_VDL_CONFIG_DP_VDL_LOAD_VALUE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_P_VDL_CONFIG_DP_VDL_LOAD_VALUE_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_P_VDL_CONFIG_DP_VDL_LOAD_VALUE_SHIFT 16
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_P_VDL_CONFIG_DP_VDL_LOAD_VALUE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_P_VDL_CONFIG_EP_VDL_LOAD_VALUE_MASK 0x1ff
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_P_VDL_CONFIG_EP_VDL_LOAD_VALUE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_P_VDL_CONFIG_EP_VDL_LOAD_VALUE_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_P_VDL_CONFIG_EP_VDL_LOAD_VALUE_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_P_VDL_CONFIG_EP_VDL_LOAD_VALUE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_P_VDL_CONFIG_RESERVED_MASK 0xfe000000
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_P_VDL_CONFIG_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_P_VDL_CONFIG_RESERVED_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_P_VDL_CONFIG_RESERVED_SHIFT 25
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_P_VDL_CONFIG_ALL_MASK 0x1ffffff
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_P_VDL_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_P_VDL_CONFIG_ALL_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_P_VDL_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_P_VDL_CONFIG_ALL_MASK 0x1ffffff
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_P_VDL_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_P_VDL_CONFIG_ALL_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_P_VDL_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_P_VDL_CONFIG_DATAMASK 0x01ff01ff
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_P_VDL_CONFIG_RDWRMASK 0xfe00fe00
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_P_VDL_CONFIG_RESETVALUE 0x0000000
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_N_VDL_CONFIG 0x1023c0bc
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_N_VDL_CONFIG_BASE 0x0bc
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_N_VDL_CONFIG_DN_VDL_LOAD_VALUE_MASK 0x1ff0000
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_N_VDL_CONFIG_DN_VDL_LOAD_VALUE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_N_VDL_CONFIG_DN_VDL_LOAD_VALUE_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_N_VDL_CONFIG_DN_VDL_LOAD_VALUE_SHIFT 16
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_N_VDL_CONFIG_DN_VDL_LOAD_VALUE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_N_VDL_CONFIG_EN_VDL_LOAD_VALUE_MASK 0x1ff
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_N_VDL_CONFIG_EN_VDL_LOAD_VALUE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_N_VDL_CONFIG_EN_VDL_LOAD_VALUE_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_N_VDL_CONFIG_EN_VDL_LOAD_VALUE_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_N_VDL_CONFIG_EN_VDL_LOAD_VALUE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_N_VDL_CONFIG_RESERVED_MASK 0xfe000000
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_N_VDL_CONFIG_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_N_VDL_CONFIG_RESERVED_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_N_VDL_CONFIG_RESERVED_SHIFT 25
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_N_VDL_CONFIG_ALL_MASK 0x1ffffff
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_N_VDL_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_N_VDL_CONFIG_ALL_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_N_VDL_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_N_VDL_CONFIG_ALL_MASK 0x1ffffff
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_N_VDL_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_N_VDL_CONFIG_ALL_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_N_VDL_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_N_VDL_CONFIG_DATAMASK 0x01ff01ff
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_N_VDL_CONFIG_RDWRMASK 0xfe00fe00
 #define SJC16_DDR4_PHY_DQ_BYTE0_CDR_N_VDL_CONFIG_RESETVALUE 0x0000000
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_P_VDL 0x1023c0c0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_P_VDL_BASE 0x0c0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_P_VDL_DP_VDL_VALUE_MASK 0x1ff0000
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_P_VDL_DP_VDL_VALUE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_P_VDL_DP_VDL_VALUE_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_P_VDL_DP_VDL_VALUE_SHIFT 16
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_P_VDL_DP_VDL_VALUE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_P_VDL_EP_VDL_VALUE_MASK 0x1ff
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_P_VDL_EP_VDL_VALUE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_P_VDL_EP_VDL_VALUE_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_P_VDL_EP_VDL_VALUE_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_P_VDL_EP_VDL_VALUE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_P_VDL_RESERVED_MASK 0xfe000000
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_P_VDL_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_P_VDL_RESERVED_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_P_VDL_RESERVED_SHIFT 25
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_P_VDL_ALL_MASK 0x1ffffff
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_P_VDL_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_P_VDL_ALL_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_P_VDL_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_P_VDL_ALL_MASK 0x1ffffff
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_P_VDL_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_P_VDL_ALL_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_P_VDL_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_P_VDL_DATAMASK 0x01ff01ff
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_P_VDL_RDWRMASK 0xfe00fe00
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_P_VDL_RESETVALUE 0x0000000
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_N_VDL 0x1023c0c4
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_N_VDL_BASE 0x0c4
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_N_VDL_DN_VDL_VALUE_MASK 0x1ff0000
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_N_VDL_DN_VDL_VALUE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_N_VDL_DN_VDL_VALUE_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_N_VDL_DN_VDL_VALUE_SHIFT 16
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_N_VDL_DN_VDL_VALUE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_N_VDL_EN_VDL_VALUE_MASK 0x1ff
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_N_VDL_EN_VDL_VALUE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_N_VDL_EN_VDL_VALUE_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_N_VDL_EN_VDL_VALUE_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_N_VDL_EN_VDL_VALUE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_N_VDL_RESERVED_MASK 0xfe000000
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_N_VDL_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_N_VDL_RESERVED_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_N_VDL_RESERVED_SHIFT 25
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_N_VDL_ALL_MASK 0x1ffffff
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_N_VDL_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_N_VDL_ALL_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_N_VDL_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_N_VDL_ALL_MASK 0x1ffffff
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_N_VDL_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_N_VDL_ALL_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_N_VDL_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_N_VDL_DATAMASK 0x01ff01ff
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_N_VDL_RDWRMASK 0xfe00fe00
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_N_VDL_RESETVALUE 0x0000000
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_EP_VDL_STAT 0x1023c0c8
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_EP_VDL_STAT_BASE 0x0c8
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_EP_VDL_STAT_MAX_VDL_VALUE_MASK 0x1ff0000
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_EP_VDL_STAT_MAX_VDL_VALUE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_EP_VDL_STAT_MAX_VDL_VALUE_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_EP_VDL_STAT_MAX_VDL_VALUE_SHIFT 16
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_EP_VDL_STAT_MAX_VDL_VALUE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_EP_VDL_STAT_MIN_VDL_VALUE_MASK 0x1ff
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_EP_VDL_STAT_MIN_VDL_VALUE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_EP_VDL_STAT_MIN_VDL_VALUE_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_EP_VDL_STAT_MIN_VDL_VALUE_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_EP_VDL_STAT_MIN_VDL_VALUE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_EP_VDL_STAT_RESERVED_MASK 0xfe000000
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_EP_VDL_STAT_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_EP_VDL_STAT_RESERVED_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_EP_VDL_STAT_RESERVED_SHIFT 25
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_EP_VDL_STAT_ALL_MASK 0x1ffffff
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_EP_VDL_STAT_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_EP_VDL_STAT_ALL_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_EP_VDL_STAT_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_EP_VDL_STAT_ALL_MASK 0x1ffffff
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_EP_VDL_STAT_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_EP_VDL_STAT_ALL_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_EP_VDL_STAT_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_EP_VDL_STAT_DATAMASK 0x01ff01ff
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_EP_VDL_STAT_RDWRMASK 0xfe00fe00
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_EP_VDL_STAT_RESETVALUE 0x0000000
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_DP_VDL_STAT 0x1023c0cc
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_DP_VDL_STAT_BASE 0x0cc
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_DP_VDL_STAT_MAX_VDL_VALUE_MASK 0x1ff0000
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_DP_VDL_STAT_MAX_VDL_VALUE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_DP_VDL_STAT_MAX_VDL_VALUE_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_DP_VDL_STAT_MAX_VDL_VALUE_SHIFT 16
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_DP_VDL_STAT_MAX_VDL_VALUE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_DP_VDL_STAT_MIN_VDL_VALUE_MASK 0x1ff
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_DP_VDL_STAT_MIN_VDL_VALUE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_DP_VDL_STAT_MIN_VDL_VALUE_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_DP_VDL_STAT_MIN_VDL_VALUE_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_DP_VDL_STAT_MIN_VDL_VALUE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_DP_VDL_STAT_RESERVED_MASK 0xfe000000
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_DP_VDL_STAT_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_DP_VDL_STAT_RESERVED_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_DP_VDL_STAT_RESERVED_SHIFT 25
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_DP_VDL_STAT_ALL_MASK 0x1ffffff
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_DP_VDL_STAT_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_DP_VDL_STAT_ALL_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_DP_VDL_STAT_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_DP_VDL_STAT_ALL_MASK 0x1ffffff
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_DP_VDL_STAT_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_DP_VDL_STAT_ALL_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_DP_VDL_STAT_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_DP_VDL_STAT_DATAMASK 0x01ff01ff
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_DP_VDL_STAT_RDWRMASK 0xfe00fe00
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_DP_VDL_STAT_RESETVALUE 0x0000000
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_EN_VDL_STAT 0x1023c0d0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_EN_VDL_STAT_BASE 0x0d0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_EN_VDL_STAT_MAX_VDL_VALUE_MASK 0x1ff0000
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_EN_VDL_STAT_MAX_VDL_VALUE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_EN_VDL_STAT_MAX_VDL_VALUE_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_EN_VDL_STAT_MAX_VDL_VALUE_SHIFT 16
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_EN_VDL_STAT_MAX_VDL_VALUE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_EN_VDL_STAT_MIN_VDL_VALUE_MASK 0x1ff
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_EN_VDL_STAT_MIN_VDL_VALUE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_EN_VDL_STAT_MIN_VDL_VALUE_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_EN_VDL_STAT_MIN_VDL_VALUE_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_EN_VDL_STAT_MIN_VDL_VALUE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_EN_VDL_STAT_RESERVED_MASK 0xfe000000
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_EN_VDL_STAT_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_EN_VDL_STAT_RESERVED_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_EN_VDL_STAT_RESERVED_SHIFT 25
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_EN_VDL_STAT_ALL_MASK 0x1ffffff
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_EN_VDL_STAT_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_EN_VDL_STAT_ALL_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_EN_VDL_STAT_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_EN_VDL_STAT_ALL_MASK 0x1ffffff
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_EN_VDL_STAT_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_EN_VDL_STAT_ALL_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_EN_VDL_STAT_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_EN_VDL_STAT_DATAMASK 0x01ff01ff
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_EN_VDL_STAT_RDWRMASK 0xfe00fe00
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_EN_VDL_STAT_RESETVALUE 0x0000000
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_DN_VDL_STAT 0x1023c0d4
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_DN_VDL_STAT_BASE 0x0d4
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_DN_VDL_STAT_MAX_VDL_VALUE_MASK 0x1ff0000
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_DN_VDL_STAT_MAX_VDL_VALUE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_DN_VDL_STAT_MAX_VDL_VALUE_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_DN_VDL_STAT_MAX_VDL_VALUE_SHIFT 16
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_DN_VDL_STAT_MAX_VDL_VALUE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_DN_VDL_STAT_MIN_VDL_VALUE_MASK 0x1ff
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_DN_VDL_STAT_MIN_VDL_VALUE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_DN_VDL_STAT_MIN_VDL_VALUE_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_DN_VDL_STAT_MIN_VDL_VALUE_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_DN_VDL_STAT_MIN_VDL_VALUE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_DN_VDL_STAT_RESERVED_MASK 0xfe000000
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_DN_VDL_STAT_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_DN_VDL_STAT_RESERVED_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_DN_VDL_STAT_RESERVED_SHIFT 25
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_DN_VDL_STAT_ALL_MASK 0x1ffffff
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_DN_VDL_STAT_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_DN_VDL_STAT_ALL_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_DN_VDL_STAT_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_DN_VDL_STAT_ALL_MASK 0x1ffffff
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_DN_VDL_STAT_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_DN_VDL_STAT_ALL_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_DN_VDL_STAT_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_DN_VDL_STAT_DATAMASK 0x01ff01ff
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_DN_VDL_STAT_RDWRMASK 0xfe00fe00
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_DN_VDL_STAT_RESETVALUE 0x0000000
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_OPERATION 0x1023c0d8
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_OPERATION_BASE 0x0d8
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_OPERATION_ROLLOVER_OVERFLOW_MASK 0x10000000
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_OPERATION_ROLLOVER_OVERFLOW_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_OPERATION_ROLLOVER_OVERFLOW_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_OPERATION_ROLLOVER_OVERFLOW_SHIFT 28
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_OPERATION_ROLLOVER_OVERFLOW_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_OPERATION_ROLLOVER_COUNT_MASK 0xff00000
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_OPERATION_ROLLOVER_COUNT_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_OPERATION_ROLLOVER_COUNT_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_OPERATION_ROLLOVER_COUNT_SHIFT 20
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_OPERATION_ROLLOVER_COUNT_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_OPERATION_SEARCH_ACTIVE_RETRIGGERED_MASK 0x20000
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_OPERATION_SEARCH_ACTIVE_RETRIGGERED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_OPERATION_SEARCH_ACTIVE_RETRIGGERED_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_OPERATION_SEARCH_ACTIVE_RETRIGGERED_SHIFT 17
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_OPERATION_SEARCH_ACTIVE_RETRIGGERED_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_OPERATION_INIT_SEARCH_COMPLETE_MASK 0x10000
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_OPERATION_INIT_SEARCH_COMPLETE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_OPERATION_INIT_SEARCH_COMPLETE_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_OPERATION_INIT_SEARCH_COMPLETE_SHIFT 16
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_OPERATION_INIT_SEARCH_COMPLETE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_OPERATION_INIT_SEARCH_ACTIVE_MASK 0x8000
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_OPERATION_INIT_SEARCH_ACTIVE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_OPERATION_INIT_SEARCH_ACTIVE_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_OPERATION_INIT_SEARCH_ACTIVE_SHIFT 15
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_OPERATION_INIT_SEARCH_ACTIVE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_OPERATION_TRACK_ACTIVE_LOST_MASK 0x4000
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_OPERATION_TRACK_ACTIVE_LOST_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_OPERATION_TRACK_ACTIVE_LOST_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_OPERATION_TRACK_ACTIVE_LOST_SHIFT 14
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_OPERATION_TRACK_ACTIVE_LOST_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_OPERATION_INIT_TRACK_ACTIVE_MASK 0x2000
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_OPERATION_INIT_TRACK_ACTIVE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_OPERATION_INIT_TRACK_ACTIVE_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_OPERATION_INIT_TRACK_ACTIVE_SHIFT 13
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_OPERATION_INIT_TRACK_ACTIVE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_OPERATION_ACCU_ACTIVE_LOST_MASK 0x1000
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_OPERATION_ACCU_ACTIVE_LOST_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_OPERATION_ACCU_ACTIVE_LOST_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_OPERATION_ACCU_ACTIVE_LOST_SHIFT 12
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_OPERATION_ACCU_ACTIVE_LOST_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_OPERATION_INIT_ACCU_ACTIVE_MASK 0x800
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_OPERATION_INIT_ACCU_ACTIVE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_OPERATION_INIT_ACCU_ACTIVE_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_OPERATION_INIT_ACCU_ACTIVE_SHIFT 11
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_OPERATION_INIT_ACCU_ACTIVE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_OPERATION_SEARCH_ACTIVE_MASK 0x400
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_OPERATION_SEARCH_ACTIVE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_OPERATION_SEARCH_ACTIVE_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_OPERATION_SEARCH_ACTIVE_SHIFT 10
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_OPERATION_SEARCH_ACTIVE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_OPERATION_TRACK_ACTIVE_MASK 0x200
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_OPERATION_TRACK_ACTIVE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_OPERATION_TRACK_ACTIVE_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_OPERATION_TRACK_ACTIVE_SHIFT 9
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_OPERATION_TRACK_ACTIVE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_OPERATION_ACCU_ACTIVE_MASK 0x100
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_OPERATION_ACCU_ACTIVE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_OPERATION_ACCU_ACTIVE_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_OPERATION_ACCU_ACTIVE_SHIFT 8
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_OPERATION_ACCU_ACTIVE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_OPERATION_ACCU_VALUE_MASK 0xff
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_OPERATION_ACCU_VALUE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_OPERATION_ACCU_VALUE_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_OPERATION_ACCU_VALUE_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_OPERATION_ACCU_VALUE_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_OPERATION_RESERVED_MASK 0xe0000000
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_OPERATION_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_OPERATION_RESERVED_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_OPERATION_RESERVED_SHIFT 29
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_OPERATION_ALL_MASK 0x1fffffff
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_OPERATION_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_OPERATION_ALL_BITS 29
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_OPERATION_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_OPERATION_ALL_MASK 0x1fffffff
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_OPERATION_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_OPERATION_ALL_BITS 29
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_OPERATION_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_OPERATION_DATAMASK 0x1ff3ffff
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_OPERATION_RDWRMASK 0xe00c0000
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_OPERATION_RESETVALUE 0x00000000
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_TIMING 0x1023c0dc
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_TIMING_BASE 0x0dc
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_TIMING_DATA_VALID_WR2RD_DELAY_MASK 0xf0000
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_TIMING_DATA_VALID_WR2RD_DELAY_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_TIMING_DATA_VALID_WR2RD_DELAY_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_TIMING_DATA_VALID_WR2RD_DELAY_SHIFT 16
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_TIMING_DATA_VALID_WR2RD_DELAY_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_TIMING_EDC_VALID_WR2RD_DELAY_MASK 0xf000
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_TIMING_EDC_VALID_WR2RD_DELAY_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_TIMING_EDC_VALID_WR2RD_DELAY_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_TIMING_EDC_VALID_WR2RD_DELAY_SHIFT 12
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_TIMING_EDC_VALID_WR2RD_DELAY_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_TIMING_DATA_READ_UI_SHIFT_MASK 0x700
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_TIMING_DATA_READ_UI_SHIFT_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_TIMING_DATA_READ_UI_SHIFT_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_TIMING_DATA_READ_UI_SHIFT_SHIFT 8
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_TIMING_DATA_READ_UI_SHIFT_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_TIMING_EDC_READ_UI_SHIFT_MASK 0x70
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_TIMING_EDC_READ_UI_SHIFT_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_TIMING_EDC_READ_UI_SHIFT_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_TIMING_EDC_READ_UI_SHIFT_SHIFT 4
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_TIMING_EDC_READ_UI_SHIFT_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_TIMING_DATA_VALID_WR2RD_DELAY_DEC_MASK 0x8
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_TIMING_DATA_VALID_WR2RD_DELAY_DEC_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_TIMING_DATA_VALID_WR2RD_DELAY_DEC_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_TIMING_DATA_VALID_WR2RD_DELAY_DEC_SHIFT 3
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_TIMING_DATA_VALID_WR2RD_DELAY_DEC_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_TIMING_DATA_VALID_WR2RD_DELAY_INC_MASK 0x4
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_TIMING_DATA_VALID_WR2RD_DELAY_INC_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_TIMING_DATA_VALID_WR2RD_DELAY_INC_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_TIMING_DATA_VALID_WR2RD_DELAY_INC_SHIFT 2
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_TIMING_DATA_VALID_WR2RD_DELAY_INC_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_TIMING_EDC_VALID_WR2RD_DELAY_DEC_MASK 0x2
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_TIMING_EDC_VALID_WR2RD_DELAY_DEC_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_TIMING_EDC_VALID_WR2RD_DELAY_DEC_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_TIMING_EDC_VALID_WR2RD_DELAY_DEC_SHIFT 1
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_TIMING_EDC_VALID_WR2RD_DELAY_DEC_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_TIMING_EDC_VALID_WR2RD_DELAY_INC_MASK 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_TIMING_EDC_VALID_WR2RD_DELAY_INC_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_TIMING_EDC_VALID_WR2RD_DELAY_INC_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_TIMING_EDC_VALID_WR2RD_DELAY_INC_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_TIMING_EDC_VALID_WR2RD_DELAY_INC_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_TIMING_RESERVED_0_MASK 0xfff00000
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_TIMING_RESERVED_0_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_TIMING_RESERVED_0_BITS 12
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_TIMING_RESERVED_0_SHIFT 20
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_TIMING_RESERVED_MASK 0xfff00000
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_TIMING_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_TIMING_RESERVED_BITS 12
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_TIMING_RESERVED_SHIFT 20
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_TIMING_ALL_MASK 0xfffff
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_TIMING_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_TIMING_ALL_BITS 20
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_TIMING_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_TIMING_ALL_MASK 0xfffff
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_TIMING_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_TIMING_ALL_BITS 20
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_TIMING_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_TIMING_DATAMASK 0x000ff77f
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_TIMING_RDWRMASK 0xfff00880
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_CDR_TIMING_RESETVALUE 0x00000
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_FIFO_PTR 0x1023c0e0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_FIFO_PTR_BASE 0x0e0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_FIFO_PTR_RP_XMSB_MASK 0x20000
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_FIFO_PTR_RP_XMSB_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_FIFO_PTR_RP_XMSB_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_FIFO_PTR_RP_XMSB_SHIFT 17
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_FIFO_PTR_RP_XMSB_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_FIFO_PTR_RP_MASK 0x1f000
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_FIFO_PTR_RP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_FIFO_PTR_RP_BITS 5
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_FIFO_PTR_RP_SHIFT 12
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_FIFO_PTR_RP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_FIFO_PTR_WP1_XMSB_MASK 0x800
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_FIFO_PTR_WP1_XMSB_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_FIFO_PTR_WP1_XMSB_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_FIFO_PTR_WP1_XMSB_SHIFT 11
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_FIFO_PTR_WP1_XMSB_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_FIFO_PTR_WP1_MASK 0x7c0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_FIFO_PTR_WP1_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_FIFO_PTR_WP1_BITS 5
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_FIFO_PTR_WP1_SHIFT 6
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_FIFO_PTR_WP1_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_FIFO_PTR_WP0_XMSB_MASK 0x20
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_FIFO_PTR_WP0_XMSB_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_FIFO_PTR_WP0_XMSB_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_FIFO_PTR_WP0_XMSB_SHIFT 5
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_FIFO_PTR_WP0_XMSB_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_FIFO_PTR_WP0_MASK 0x1f
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_FIFO_PTR_WP0_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_FIFO_PTR_WP0_BITS 5
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_FIFO_PTR_WP0_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_FIFO_PTR_WP0_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_FIFO_PTR_RESERVED_MASK 0xfffc0000
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_FIFO_PTR_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_FIFO_PTR_RESERVED_BITS 14
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_FIFO_PTR_RESERVED_SHIFT 18
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_FIFO_PTR_ALL_MASK 0x3ffff
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_FIFO_PTR_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_FIFO_PTR_ALL_BITS 18
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_FIFO_PTR_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_FIFO_PTR_ALL_MASK 0x3ffff
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_FIFO_PTR_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_FIFO_PTR_ALL_BITS 18
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_FIFO_PTR_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_FIFO_PTR_DATAMASK 0x0003ffff
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_FIFO_PTR_RDWRMASK 0xfffc0000
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_FIFO_PTR_RESETVALUE 0x00000
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_FIFO_CTR 0x1023c0e4
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_FIFO_CTR_BASE 0x0e4
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_FIFO_CTR_MAX_WCOUNT_MASK 0x3f00
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_FIFO_CTR_MAX_WCOUNT_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_FIFO_CTR_MAX_WCOUNT_BITS 6
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_FIFO_CTR_MAX_WCOUNT_SHIFT 8
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_FIFO_CTR_MAX_WCOUNT_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_FIFO_CTR_CUR_WCOUNT_MASK 0xfc
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_FIFO_CTR_CUR_WCOUNT_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_FIFO_CTR_CUR_WCOUNT_BITS 6
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_FIFO_CTR_CUR_WCOUNT_SHIFT 2
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_FIFO_CTR_CUR_WCOUNT_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_FIFO_CTR_WFULL_MASK 0x2
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_FIFO_CTR_WFULL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_FIFO_CTR_WFULL_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_FIFO_CTR_WFULL_SHIFT 1
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_FIFO_CTR_WFULL_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_FIFO_CTR_WRITE_ERROR_MASK 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_FIFO_CTR_WRITE_ERROR_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_FIFO_CTR_WRITE_ERROR_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_FIFO_CTR_WRITE_ERROR_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_FIFO_CTR_WRITE_ERROR_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_FIFO_CTR_RESERVED_MASK 0xffffc000
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_FIFO_CTR_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_FIFO_CTR_RESERVED_BITS 18
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_FIFO_CTR_RESERVED_SHIFT 14
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_FIFO_CTR_ALL_MASK 0x3fff
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_FIFO_CTR_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_FIFO_CTR_ALL_BITS 14
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_FIFO_CTR_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_FIFO_CTR_ALL_MASK 0x3fff
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_FIFO_CTR_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_FIFO_CTR_ALL_BITS 14
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_FIFO_CTR_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_FIFO_CTR_DATAMASK 0x00003fff
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_FIFO_CTR_RDWRMASK 0xffffc000
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_FIFO_CTR_RESETVALUE 0x0000
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH 0x1023c0e8
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_BASE 0x0e8
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_PAST_STATE7_MASK 0x7000000
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_PAST_STATE7_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_PAST_STATE7_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_PAST_STATE7_SHIFT 24
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_PAST_STATE7_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_PAST_STATE6_MASK 0xe00000
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_PAST_STATE6_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_PAST_STATE6_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_PAST_STATE6_SHIFT 21
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_PAST_STATE6_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_PAST_STATE5_MASK 0x1c0000
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_PAST_STATE5_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_PAST_STATE5_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_PAST_STATE5_SHIFT 18
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_PAST_STATE5_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_PAST_STATE4_MASK 0x38000
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_PAST_STATE4_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_PAST_STATE4_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_PAST_STATE4_SHIFT 15
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_PAST_STATE4_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_PAST_STATE3_MASK 0x7000
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_PAST_STATE3_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_PAST_STATE3_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_PAST_STATE3_SHIFT 12
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_PAST_STATE3_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_PAST_STATE2_MASK 0xe00
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_PAST_STATE2_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_PAST_STATE2_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_PAST_STATE2_SHIFT 9
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_PAST_STATE2_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_PAST_STATE1_MASK 0x1c0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_PAST_STATE1_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_PAST_STATE1_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_PAST_STATE1_SHIFT 6
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_PAST_STATE1_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_PAST_STATE0_MASK 0x38
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_PAST_STATE0_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_PAST_STATE0_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_PAST_STATE0_SHIFT 3
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_PAST_STATE0_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_CUR_STATE_MASK 0x7
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_CUR_STATE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_CUR_STATE_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_CUR_STATE_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_CUR_STATE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_RESERVED_MASK 0xf8000000
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_RESERVED_BITS 5
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_RESERVED_SHIFT 27
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_ALL_MASK 0x7ffffff
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_ALL_BITS 27
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_ALL_MASK 0x7ffffff
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_ALL_BITS 27
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_DATAMASK 0x07ffffff
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_RDWRMASK 0xf8000000
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_RESETVALUE 0x0000000
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_ERR1 0x1023c0ec
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_ERR1_BASE 0x0ec
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_ERR1_RCMD_FIFO_RD_MASK 0x1000
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_ERR1_RCMD_FIFO_RD_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_ERR1_RCMD_FIFO_RD_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_ERR1_RCMD_FIFO_RD_SHIFT 12
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_ERR1_RCMD_FIFO_RD_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_ERR1_RCMD_FIFO_RDATA_MASK 0xff0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_ERR1_RCMD_FIFO_RDATA_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_ERR1_RCMD_FIFO_RDATA_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_ERR1_RCMD_FIFO_RDATA_SHIFT 4
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_ERR1_RCMD_FIFO_RDATA_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_ERR1_STATE_MASK 0xe
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_ERR1_STATE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_ERR1_STATE_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_ERR1_STATE_SHIFT 1
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_ERR1_STATE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_ERR1_ERROR_MASK 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_ERR1_ERROR_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_ERR1_ERROR_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_ERR1_ERROR_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_ERR1_ERROR_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_ERR1_RESERVED_MASK 0xffffe000
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_ERR1_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_ERR1_RESERVED_BITS 19
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_ERR1_RESERVED_SHIFT 13
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_ERR1_ALL_MASK 0x1fff
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_ERR1_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_ERR1_ALL_BITS 13
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_ERR1_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_ERR1_ALL_MASK 0x1fff
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_ERR1_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_ERR1_ALL_BITS 13
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_ERR1_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_ERR1_DATAMASK 0x00001fff
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_ERR1_RDWRMASK 0xffffe000
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_ERR1_RESETVALUE 0x0000
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_ERR2 0x1023c0f0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_ERR2_BASE 0x0f0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_ERR2_RCMD_FIFO_RD_MASK 0x1000
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_ERR2_RCMD_FIFO_RD_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_ERR2_RCMD_FIFO_RD_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_ERR2_RCMD_FIFO_RD_SHIFT 12
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_ERR2_RCMD_FIFO_RD_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_ERR2_RCMD_FIFO_RDATA_MASK 0xff0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_ERR2_RCMD_FIFO_RDATA_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_ERR2_RCMD_FIFO_RDATA_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_ERR2_RCMD_FIFO_RDATA_SHIFT 4
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_ERR2_RCMD_FIFO_RDATA_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_ERR2_STATE_MASK 0xe
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_ERR2_STATE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_ERR2_STATE_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_ERR2_STATE_SHIFT 1
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_ERR2_STATE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_ERR2_ERROR_MASK 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_ERR2_ERROR_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_ERR2_ERROR_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_ERR2_ERROR_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_ERR2_ERROR_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_ERR2_RESERVED_MASK 0xffffe000
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_ERR2_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_ERR2_RESERVED_BITS 19
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_ERR2_RESERVED_SHIFT 13
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_ERR2_ALL_MASK 0x1fff
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_ERR2_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_ERR2_ALL_BITS 13
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_ERR2_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_ERR2_ALL_MASK 0x1fff
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_ERR2_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_ERR2_ALL_BITS 13
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_ERR2_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_ERR2_DATAMASK 0x00001fff
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_ERR2_RDWRMASK 0xffffe000
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_ERR2_RESETVALUE 0x0000
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_ERR3 0x1023c0f4
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_ERR3_BASE 0x0f4
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_ERR3_EXP_RCMD_ID_MASK 0xfc00
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_ERR3_EXP_RCMD_ID_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_ERR3_EXP_RCMD_ID_BITS 6
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_ERR3_EXP_RCMD_ID_SHIFT 10
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_ERR3_EXP_RCMD_ID_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_ERR3_OBS_RCMD_ID_MASK 0x3f0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_ERR3_OBS_RCMD_ID_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_ERR3_OBS_RCMD_ID_BITS 6
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_ERR3_OBS_RCMD_ID_SHIFT 4
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_ERR3_OBS_RCMD_ID_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_ERR3_STATE_MASK 0xe
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_ERR3_STATE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_ERR3_STATE_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_ERR3_STATE_SHIFT 1
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_ERR3_STATE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_ERR3_ERROR_MASK 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_ERR3_ERROR_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_ERR3_ERROR_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_ERR3_ERROR_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_ERR3_ERROR_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_ERR3_RESERVED_MASK 0xffff0000
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_ERR3_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_ERR3_RESERVED_BITS 16
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_ERR3_RESERVED_SHIFT 16
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_ERR3_ALL_MASK 0xffff
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_ERR3_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_ERR3_ALL_BITS 16
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_ERR3_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_ERR3_ALL_MASK 0xffff
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_ERR3_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_ERR3_ALL_BITS 16
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_ERR3_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_ERR3_DATAMASK 0x0000ffff
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_ERR3_RDWRMASK 0xffff0000
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_ERR3_RESETVALUE 0x0000
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_RCMD_ID 0x1023c0f8
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_RCMD_ID_BASE 0x0f8
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_RCMD_ID_ID8_MASK 0xfc0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_RCMD_ID_ID8_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_RCMD_ID_ID8_BITS 6
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_RCMD_ID_ID8_SHIFT 6
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_RCMD_ID_ID8_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_RCMD_ID_ID4_MASK 0x3f
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_RCMD_ID_ID4_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_RCMD_ID_ID4_BITS 6
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_RCMD_ID_ID4_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_RCMD_ID_ID4_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_RCMD_ID_RESERVED_MASK 0xfffff000
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_RCMD_ID_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_RCMD_ID_RESERVED_BITS 20
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_RCMD_ID_RESERVED_SHIFT 12
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_RCMD_ID_ALL_MASK 0xfff
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_RCMD_ID_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_RCMD_ID_ALL_BITS 12
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_RCMD_ID_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_RCMD_ID_ALL_MASK 0xfff
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_RCMD_ID_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_RCMD_ID_ALL_BITS 12
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_RCMD_ID_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_RCMD_ID_DATAMASK 0x00000fff
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_RCMD_ID_RDWRMASK 0xfffff000
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_RCMD_ID_RESETVALUE 0x000
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RDATA_FIFO 0x1023c0fc
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RDATA_FIFO_BASE 0x0fc
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RDATA_FIFO_RP1_XMSB_MASK 0x4000
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RDATA_FIFO_RP1_XMSB_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RDATA_FIFO_RP1_XMSB_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RDATA_FIFO_RP1_XMSB_SHIFT 14
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RDATA_FIFO_RP1_XMSB_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RDATA_FIFO_RP1_MASK 0x3c00
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RDATA_FIFO_RP1_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RDATA_FIFO_RP1_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RDATA_FIFO_RP1_SHIFT 10
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RDATA_FIFO_RP1_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RDATA_FIFO_RP0_XMSB_MASK 0x200
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RDATA_FIFO_RP0_XMSB_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RDATA_FIFO_RP0_XMSB_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RDATA_FIFO_RP0_XMSB_SHIFT 9
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RDATA_FIFO_RP0_XMSB_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RDATA_FIFO_RP0_MASK 0x1e0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RDATA_FIFO_RP0_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RDATA_FIFO_RP0_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RDATA_FIFO_RP0_SHIFT 5
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RDATA_FIFO_RP0_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RDATA_FIFO_WP_XMSB_MASK 0x10
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RDATA_FIFO_WP_XMSB_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RDATA_FIFO_WP_XMSB_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RDATA_FIFO_WP_XMSB_SHIFT 4
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RDATA_FIFO_WP_XMSB_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RDATA_FIFO_WP_MASK 0xf
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RDATA_FIFO_WP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RDATA_FIFO_WP_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RDATA_FIFO_WP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RDATA_FIFO_WP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RDATA_FIFO_RESERVED_MASK 0xffff8000
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RDATA_FIFO_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RDATA_FIFO_RESERVED_BITS 17
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RDATA_FIFO_RESERVED_SHIFT 15
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RDATA_FIFO_ALL_MASK 0x7fff
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RDATA_FIFO_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RDATA_FIFO_ALL_BITS 15
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RDATA_FIFO_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RDATA_FIFO_ALL_MASK 0x7fff
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RDATA_FIFO_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RDATA_FIFO_ALL_BITS 15
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RDATA_FIFO_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RDATA_FIFO_DATAMASK 0x00007fff
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RDATA_FIFO_RDWRMASK 0xffff8000
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RDATA_FIFO_RESETVALUE 0x0000
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_FIFO 0x1023c100
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_FIFO_BASE 0x100
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_FIFO_RP_2G_XMSB_MASK 0x20000
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_FIFO_RP_2G_XMSB_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_FIFO_RP_2G_XMSB_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_FIFO_RP_2G_XMSB_SHIFT 17
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_FIFO_RP_2G_XMSB_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_FIFO_RP_2G_MASK 0x1f000
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_FIFO_RP_2G_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_FIFO_RP_2G_BITS 5
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_FIFO_RP_2G_SHIFT 12
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_FIFO_RP_2G_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_FIFO_RP_1G_XMSB_MASK 0x800
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_FIFO_RP_1G_XMSB_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_FIFO_RP_1G_XMSB_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_FIFO_RP_1G_XMSB_SHIFT 11
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_FIFO_RP_1G_XMSB_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_FIFO_RP_1G_MASK 0x7c0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_FIFO_RP_1G_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_FIFO_RP_1G_BITS 5
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_FIFO_RP_1G_SHIFT 6
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_FIFO_RP_1G_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_FIFO_WP_XMSB_MASK 0x20
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_FIFO_WP_XMSB_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_FIFO_WP_XMSB_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_FIFO_WP_XMSB_SHIFT 5
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_FIFO_WP_XMSB_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_FIFO_WP_MASK 0x1f
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_FIFO_WP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_FIFO_WP_BITS 5
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_FIFO_WP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_FIFO_WP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_FIFO_RESERVED_MASK 0xfffc0000
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_FIFO_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_FIFO_RESERVED_BITS 14
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_FIFO_RESERVED_SHIFT 18
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_FIFO_ALL_MASK 0x3ffff
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_FIFO_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_FIFO_ALL_BITS 18
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_FIFO_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_FIFO_ALL_MASK 0x3ffff
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_FIFO_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_FIFO_ALL_BITS 18
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_FIFO_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_FIFO_DATAMASK 0x0003ffff
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_FIFO_RDWRMASK 0xfffc0000
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_FIFO_RESETVALUE 0x00000
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_RCMD_ID 0x1023c104
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_RCMD_ID_BASE 0x104
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_RCMD_ID_ID8_MASK 0xfc0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_RCMD_ID_ID8_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_RCMD_ID_ID8_BITS 6
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_RCMD_ID_ID8_SHIFT 6
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_RCMD_ID_ID8_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_RCMD_ID_ID4_MASK 0x3f
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_RCMD_ID_ID4_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_RCMD_ID_ID4_BITS 6
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_RCMD_ID_ID4_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_RCMD_ID_ID4_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_RCMD_ID_RESERVED_MASK 0xfffff000
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_RCMD_ID_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_RCMD_ID_RESERVED_BITS 20
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_RCMD_ID_RESERVED_SHIFT 12
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_RCMD_ID_ALL_MASK 0xfff
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_RCMD_ID_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_RCMD_ID_ALL_BITS 12
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_RCMD_ID_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_RCMD_ID_ALL_MASK 0xfff
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_RCMD_ID_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_RCMD_ID_ALL_BITS 12
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_RCMD_ID_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_RCMD_ID_DATAMASK 0x00000fff
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_RCMD_ID_RDWRMASK 0xfffff000
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_RCMD_ID_RESETVALUE 0x000
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_ERR1 0x1023c108
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_ERR1_BASE 0x108
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_ERR1_NXT_RCMD_FIFO_WDATA1_MASK 0x7f800000
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_ERR1_NXT_RCMD_FIFO_WDATA1_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_ERR1_NXT_RCMD_FIFO_WDATA1_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_ERR1_NXT_RCMD_FIFO_WDATA1_SHIFT 23
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_ERR1_NXT_RCMD_FIFO_WDATA1_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_ERR1_NXT_RCMD_FIFO_WDATA0_MASK 0x7f8000
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_ERR1_NXT_RCMD_FIFO_WDATA0_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_ERR1_NXT_RCMD_FIFO_WDATA0_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_ERR1_NXT_RCMD_FIFO_WDATA0_SHIFT 15
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_ERR1_NXT_RCMD_FIFO_WDATA0_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_ERR1_NXT_RCMD_FIFO_WR1_MASK 0x4000
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_ERR1_NXT_RCMD_FIFO_WR1_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_ERR1_NXT_RCMD_FIFO_WR1_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_ERR1_NXT_RCMD_FIFO_WR1_SHIFT 14
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_ERR1_NXT_RCMD_FIFO_WR1_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_ERR1_NXT_RCMD_FIFO_WR0_MASK 0x2000
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_ERR1_NXT_RCMD_FIFO_WR0_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_ERR1_NXT_RCMD_FIFO_WR0_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_ERR1_NXT_RCMD_FIFO_WR0_SHIFT 13
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_ERR1_NXT_RCMD_FIFO_WR0_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_ERR1_NXT_RD_EN_UI23_MASK 0x1000
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_ERR1_NXT_RD_EN_UI23_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_ERR1_NXT_RD_EN_UI23_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_ERR1_NXT_RD_EN_UI23_SHIFT 12
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_ERR1_NXT_RD_EN_UI23_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_ERR1_NXT_RD_EN_UI01_MASK 0x800
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_ERR1_NXT_RD_EN_UI01_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_ERR1_NXT_RD_EN_UI01_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_ERR1_NXT_RD_EN_UI01_SHIFT 11
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_ERR1_NXT_RD_EN_UI01_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_ERR1_NXT_STATE_MASK 0x600
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_ERR1_NXT_STATE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_ERR1_NXT_STATE_BITS 2
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_ERR1_NXT_STATE_SHIFT 9
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_ERR1_NXT_STATE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_ERR1_RCMD_PAIR_MASK 0x1e0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_ERR1_RCMD_PAIR_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_ERR1_RCMD_PAIR_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_ERR1_RCMD_PAIR_SHIFT 5
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_ERR1_RCMD_PAIR_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_ERR1_RD_EN_UI23_MASK 0x10
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_ERR1_RD_EN_UI23_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_ERR1_RD_EN_UI23_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_ERR1_RD_EN_UI23_SHIFT 4
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_ERR1_RD_EN_UI23_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_ERR1_RD_EN_UI01_MASK 0x8
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_ERR1_RD_EN_UI01_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_ERR1_RD_EN_UI01_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_ERR1_RD_EN_UI01_SHIFT 3
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_ERR1_RD_EN_UI01_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_ERR1_STATE_MASK 0x6
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_ERR1_STATE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_ERR1_STATE_BITS 2
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_ERR1_STATE_SHIFT 1
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_ERR1_STATE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_ERR1_ERROR_MASK 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_ERR1_ERROR_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_ERR1_ERROR_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_ERR1_ERROR_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_ERR1_ERROR_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_ERR1_ALL_MASK 0x7fffffff
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_ERR1_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_ERR1_ALL_BITS 31
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_ERR1_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_ERR1_ALL_MASK 0x7fffffff
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_ERR1_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_ERR1_ALL_BITS 31
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_ERR1_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_ERR1_DATAMASK 0x7fffffff
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_ERR1_RDWRMASK 0x80000000
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_ERR1_RESETVALUE 0x00000000
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_ERR2 0x1023c10c
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_ERR2_BASE 0x10c
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_ERR2_NXT_RCMD_FIFO_WDATA1_MASK 0x7f800000
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_ERR2_NXT_RCMD_FIFO_WDATA1_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_ERR2_NXT_RCMD_FIFO_WDATA1_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_ERR2_NXT_RCMD_FIFO_WDATA1_SHIFT 23
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_ERR2_NXT_RCMD_FIFO_WDATA1_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_ERR2_NXT_RCMD_FIFO_WDATA0_MASK 0x7f8000
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_ERR2_NXT_RCMD_FIFO_WDATA0_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_ERR2_NXT_RCMD_FIFO_WDATA0_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_ERR2_NXT_RCMD_FIFO_WDATA0_SHIFT 15
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_ERR2_NXT_RCMD_FIFO_WDATA0_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_ERR2_NXT_RCMD_FIFO_WR1_MASK 0x4000
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_ERR2_NXT_RCMD_FIFO_WR1_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_ERR2_NXT_RCMD_FIFO_WR1_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_ERR2_NXT_RCMD_FIFO_WR1_SHIFT 14
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_ERR2_NXT_RCMD_FIFO_WR1_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_ERR2_NXT_RCMD_FIFO_WR0_MASK 0x2000
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_ERR2_NXT_RCMD_FIFO_WR0_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_ERR2_NXT_RCMD_FIFO_WR0_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_ERR2_NXT_RCMD_FIFO_WR0_SHIFT 13
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_ERR2_NXT_RCMD_FIFO_WR0_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_ERR2_NXT_RD_EN_UI23_MASK 0x1000
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_ERR2_NXT_RD_EN_UI23_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_ERR2_NXT_RD_EN_UI23_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_ERR2_NXT_RD_EN_UI23_SHIFT 12
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_ERR2_NXT_RD_EN_UI23_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_ERR2_NXT_RD_EN_UI01_MASK 0x800
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_ERR2_NXT_RD_EN_UI01_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_ERR2_NXT_RD_EN_UI01_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_ERR2_NXT_RD_EN_UI01_SHIFT 11
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_ERR2_NXT_RD_EN_UI01_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_ERR2_NXT_STATE_MASK 0x600
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_ERR2_NXT_STATE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_ERR2_NXT_STATE_BITS 2
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_ERR2_NXT_STATE_SHIFT 9
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_ERR2_NXT_STATE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_ERR2_RCMD_PAIR_MASK 0x1e0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_ERR2_RCMD_PAIR_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_ERR2_RCMD_PAIR_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_ERR2_RCMD_PAIR_SHIFT 5
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_ERR2_RCMD_PAIR_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_ERR2_RD_EN_UI23_MASK 0x10
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_ERR2_RD_EN_UI23_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_ERR2_RD_EN_UI23_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_ERR2_RD_EN_UI23_SHIFT 4
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_ERR2_RD_EN_UI23_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_ERR2_RD_EN_UI01_MASK 0x8
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_ERR2_RD_EN_UI01_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_ERR2_RD_EN_UI01_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_ERR2_RD_EN_UI01_SHIFT 3
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_ERR2_RD_EN_UI01_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_ERR2_STATE_MASK 0x6
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_ERR2_STATE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_ERR2_STATE_BITS 2
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_ERR2_STATE_SHIFT 1
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_ERR2_STATE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_ERR2_ERROR_MASK 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_ERR2_ERROR_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_ERR2_ERROR_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_ERR2_ERROR_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_ERR2_ERROR_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_ERR2_ALL_MASK 0x7fffffff
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_ERR2_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_ERR2_ALL_BITS 31
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_ERR2_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_ERR2_ALL_MASK 0x7fffffff
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_ERR2_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_ERR2_ALL_BITS 31
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_ERR2_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_ERR2_DATAMASK 0x7fffffff
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_ERR2_RDWRMASK 0x80000000
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_ERR2_RESETVALUE 0x00000000
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_FIFO_POINTERS 0x1023c110
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_FIFO_POINTERS_BASE 0x110
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_FIFO_POINTERS_RDATA_RP_MASK 0xf00000
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_FIFO_POINTERS_RDATA_RP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_FIFO_POINTERS_RDATA_RP_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_FIFO_POINTERS_RDATA_RP_SHIFT 20
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_FIFO_POINTERS_RDATA_RP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_FIFO_POINTERS_RDATA_WP_MASK 0xf0000
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_FIFO_POINTERS_RDATA_WP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_FIFO_POINTERS_RDATA_WP_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_FIFO_POINTERS_RDATA_WP_SHIFT 16
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_FIFO_POINTERS_RDATA_WP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_FIFO_POINTERS_EDC_VALID_RP_MASK 0xf000
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_FIFO_POINTERS_EDC_VALID_RP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_FIFO_POINTERS_EDC_VALID_RP_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_FIFO_POINTERS_EDC_VALID_RP_SHIFT 12
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_FIFO_POINTERS_EDC_VALID_RP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_FIFO_POINTERS_EDC_VALID_WP_MASK 0xf00
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_FIFO_POINTERS_EDC_VALID_WP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_FIFO_POINTERS_EDC_VALID_WP_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_FIFO_POINTERS_EDC_VALID_WP_SHIFT 8
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_FIFO_POINTERS_EDC_VALID_WP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_FIFO_POINTERS_DATA_VALID_RP_MASK 0xf0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_FIFO_POINTERS_DATA_VALID_RP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_FIFO_POINTERS_DATA_VALID_RP_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_FIFO_POINTERS_DATA_VALID_RP_SHIFT 4
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_FIFO_POINTERS_DATA_VALID_RP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_FIFO_POINTERS_DATA_VALID_WP_MASK 0xf
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_FIFO_POINTERS_DATA_VALID_WP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_FIFO_POINTERS_DATA_VALID_WP_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_FIFO_POINTERS_DATA_VALID_WP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_FIFO_POINTERS_DATA_VALID_WP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_FIFO_POINTERS_RESERVED_MASK 0xff000000
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_FIFO_POINTERS_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_FIFO_POINTERS_RESERVED_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_FIFO_POINTERS_RESERVED_SHIFT 24
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_FIFO_POINTERS_ALL_MASK 0xffffff
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_FIFO_POINTERS_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_FIFO_POINTERS_ALL_BITS 24
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_FIFO_POINTERS_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_FIFO_POINTERS_ALL_MASK 0xffffff
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_FIFO_POINTERS_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_FIFO_POINTERS_ALL_BITS 24
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_FIFO_POINTERS_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_FIFO_POINTERS_DATAMASK 0x00ffffff
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_FIFO_POINTERS_RDWRMASK 0xff000000
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_FIFO_POINTERS_RESETVALUE 0x000000
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB 0x1023c114
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_BASE 0x114
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_RCMD_4_MASK 0xff000000
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_RCMD_4_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_RCMD_4_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_RCMD_4_SHIFT 24
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_RCMD_4_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_RCMD_3_MASK 0xff0000
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_RCMD_3_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_RCMD_3_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_RCMD_3_SHIFT 16
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_RCMD_3_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_RCMD_2_MASK 0xff00
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_RCMD_2_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_RCMD_2_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_RCMD_2_SHIFT 8
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_RCMD_2_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_RCMD_1_MASK 0xff
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_RCMD_1_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_RCMD_1_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_RCMD_1_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_RCMD_1_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_ALL_MASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_ALL_BITS 32
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_ALL_MASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_ALL_BITS 32
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_DATAMASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_RDWRMASK 0x00000000
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_RESETVALUE 0x00000000
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB 0x1023c118
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_BASE 0x118
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_RCMD_8_MASK 0xff000000
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_RCMD_8_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_RCMD_8_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_RCMD_8_SHIFT 24
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_RCMD_8_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_RCMD_7_MASK 0xff0000
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_RCMD_7_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_RCMD_7_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_RCMD_7_SHIFT 16
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_RCMD_7_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_RCMD_6_MASK 0xff00
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_RCMD_6_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_RCMD_6_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_RCMD_6_SHIFT 8
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_RCMD_6_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_RCMD_5_MASK 0xff
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_RCMD_5_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_RCMD_5_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_RCMD_5_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_RCMD_5_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_ALL_MASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_ALL_BITS 32
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_ALL_MASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_ALL_BITS 32
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_DATAMASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_RDWRMASK 0x00000000
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_RESETVALUE 0x00000000
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES 0x1023c11c
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_BASE 0x11c
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_7_MASK 0xf0000000
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_7_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_7_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_7_SHIFT 28
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_7_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_6_MASK 0xf000000
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_6_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_6_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_6_SHIFT 24
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_6_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_5_MASK 0xf00000
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_5_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_5_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_5_SHIFT 20
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_5_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_4_MASK 0xf0000
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_4_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_4_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_4_SHIFT 16
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_4_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_3_MASK 0xf000
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_3_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_3_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_3_SHIFT 12
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_3_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_2_MASK 0xf00
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_2_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_2_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_2_SHIFT 8
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_2_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_1_MASK 0xf0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_1_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_1_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_1_SHIFT 4
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_1_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_0_MASK 0xf
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_0_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_0_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_0_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_0_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_ALL_MASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_ALL_BITS 32
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_ALL_MASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_ALL_BITS 32
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_DATAMASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_RDWRMASK 0x00000000
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_RESETVALUE 0x00000000
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS 0x1023c120
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_BASE 0x120
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_7_MASK 0xf0000000
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_7_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_7_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_7_SHIFT 28
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_7_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_6_MASK 0xf000000
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_6_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_6_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_6_SHIFT 24
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_6_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_5_MASK 0xf00000
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_5_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_5_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_5_SHIFT 20
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_5_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_4_MASK 0xf0000
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_4_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_4_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_4_SHIFT 16
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_4_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_3_MASK 0xf000
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_3_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_3_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_3_SHIFT 12
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_3_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_2_MASK 0xf00
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_2_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_2_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_2_SHIFT 8
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_2_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_1_MASK 0xf0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_1_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_1_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_1_SHIFT 4
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_1_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_0_MASK 0xf
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_0_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_0_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_0_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_0_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_ALL_MASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_ALL_BITS 32
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_ALL_MASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_ALL_BITS 32
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_DATAMASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_RDWRMASK 0x00000000
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_RESETVALUE 0x00000000
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR 0x1023c124
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_BASE 0x124
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STICKY_ERROR_MASK 0xf0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STICKY_ERROR_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STICKY_ERROR_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STICKY_ERROR_SHIFT 4
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STICKY_ERROR_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_CURRENT_ERROR_MASK 0xf
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_CURRENT_ERROR_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_CURRENT_ERROR_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_CURRENT_ERROR_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_CURRENT_ERROR_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RESERVED_MASK 0xffffff00
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RESERVED_BITS 24
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RESERVED_SHIFT 8
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_ALL_MASK 0xff
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_ALL_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_ALL_MASK 0xff
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_ALL_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_DATAMASK 0x000000ff
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RDWRMASK 0xffffff00
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB 0x1023c128
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_BASE 0x128
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_RCMD_4_MASK 0xff000000
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_RCMD_4_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_RCMD_4_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_RCMD_4_SHIFT 24
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_RCMD_4_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_RCMD_3_MASK 0xff0000
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_RCMD_3_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_RCMD_3_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_RCMD_3_SHIFT 16
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_RCMD_3_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_RCMD_2_MASK 0xff00
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_RCMD_2_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_RCMD_2_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_RCMD_2_SHIFT 8
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_RCMD_2_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_RCMD_1_MASK 0xff
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_RCMD_1_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_RCMD_1_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_RCMD_1_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_RCMD_1_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_ALL_MASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_ALL_BITS 32
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_ALL_MASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_ALL_BITS 32
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_DATAMASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_RDWRMASK 0x00000000
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_RESETVALUE 0x00000000
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB 0x1023c12c
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_BASE 0x12c
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_RCMD_8_MASK 0xff000000
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_RCMD_8_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_RCMD_8_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_RCMD_8_SHIFT 24
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_RCMD_8_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_RCMD_7_MASK 0xff0000
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_RCMD_7_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_RCMD_7_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_RCMD_7_SHIFT 16
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_RCMD_7_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_RCMD_6_MASK 0xff00
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_RCMD_6_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_RCMD_6_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_RCMD_6_SHIFT 8
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_RCMD_6_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_RCMD_5_MASK 0xff
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_RCMD_5_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_RCMD_5_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_RCMD_5_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_RCMD_5_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_ALL_MASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_ALL_BITS 32
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_ALL_MASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_ALL_BITS 32
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_DATAMASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_RDWRMASK 0x00000000
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_RESETVALUE 0x00000000
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES 0x1023c130
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_BASE 0x130
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_7_MASK 0xf0000000
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_7_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_7_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_7_SHIFT 28
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_7_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_6_MASK 0xf000000
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_6_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_6_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_6_SHIFT 24
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_6_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_5_MASK 0xf00000
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_5_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_5_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_5_SHIFT 20
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_5_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_4_MASK 0xf0000
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_4_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_4_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_4_SHIFT 16
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_4_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_3_MASK 0xf000
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_3_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_3_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_3_SHIFT 12
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_3_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_2_MASK 0xf00
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_2_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_2_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_2_SHIFT 8
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_2_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_1_MASK 0xf0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_1_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_1_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_1_SHIFT 4
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_1_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_0_MASK 0xf
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_0_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_0_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_0_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_0_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_ALL_MASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_ALL_BITS 32
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_ALL_MASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_ALL_BITS 32
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_DATAMASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_RDWRMASK 0x00000000
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_RESETVALUE 0x00000000
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS 0x1023c134
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_BASE 0x134
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_7_MASK 0xf0000000
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_7_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_7_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_7_SHIFT 28
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_7_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_6_MASK 0xf000000
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_6_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_6_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_6_SHIFT 24
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_6_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_5_MASK 0xf00000
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_5_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_5_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_5_SHIFT 20
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_5_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_4_MASK 0xf0000
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_4_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_4_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_4_SHIFT 16
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_4_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_3_MASK 0xf000
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_3_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_3_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_3_SHIFT 12
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_3_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_2_MASK 0xf00
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_2_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_2_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_2_SHIFT 8
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_2_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_1_MASK 0xf0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_1_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_1_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_1_SHIFT 4
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_1_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_0_MASK 0xf
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_0_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_0_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_0_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_0_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_ALL_MASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_ALL_BITS 32
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_ALL_MASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_ALL_BITS 32
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_DATAMASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_RDWRMASK 0x00000000
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_RESETVALUE 0x00000000
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_WRITE_LEVELING 0x1023c138
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_WRITE_LEVELING_BASE 0x138
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_WRITE_LEVELING_DQS_MASK 0x400
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_WRITE_LEVELING_DQS_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_WRITE_LEVELING_DQS_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_WRITE_LEVELING_DQS_SHIFT 10
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_WRITE_LEVELING_DQS_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_WRITE_LEVELING_EDC_MASK 0x200
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_WRITE_LEVELING_EDC_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_WRITE_LEVELING_EDC_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_WRITE_LEVELING_EDC_SHIFT 9
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_WRITE_LEVELING_EDC_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_WRITE_LEVELING_DBI_MASK 0x100
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_WRITE_LEVELING_DBI_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_WRITE_LEVELING_DBI_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_WRITE_LEVELING_DBI_SHIFT 8
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_WRITE_LEVELING_DBI_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_WRITE_LEVELING_DATA_MASK 0xff
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_WRITE_LEVELING_DATA_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_WRITE_LEVELING_DATA_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_WRITE_LEVELING_DATA_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_WRITE_LEVELING_DATA_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_WRITE_LEVELING_RESERVED_MASK 0xfffff800
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_WRITE_LEVELING_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_WRITE_LEVELING_RESERVED_BITS 21
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_WRITE_LEVELING_RESERVED_SHIFT 11
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_WRITE_LEVELING_ALL_MASK 0x7ff
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_WRITE_LEVELING_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_WRITE_LEVELING_ALL_BITS 11
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_WRITE_LEVELING_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_WRITE_LEVELING_ALL_MASK 0x7ff
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_WRITE_LEVELING_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_WRITE_LEVELING_ALL_BITS 11
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_WRITE_LEVELING_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_WRITE_LEVELING_DATAMASK 0x000007ff
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_WRITE_LEVELING_RDWRMASK 0xfffff800
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_WRITE_LEVELING_RESETVALUE 0x000
 #define SJC16_DDR4_PHY_DQ_BYTE0_MACRO_RESERVED_REG 0x1023c13c
 #define SJC16_DDR4_PHY_DQ_BYTE0_MACRO_RESERVED_REG_BASE 0x13c
 #define SJC16_DDR4_PHY_DQ_BYTE0_MACRO_RESERVED_REG_RESERVED_MASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE0_MACRO_RESERVED_REG_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_MACRO_RESERVED_REG_RESERVED_BITS 32
 #define SJC16_DDR4_PHY_DQ_BYTE0_MACRO_RESERVED_REG_RESERVED_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_MACRO_RESERVED_REG_RESERVED_RESETVALUE 0x00000000
 #define SJC16_DDR4_PHY_DQ_BYTE0_MACRO_RESERVED_REG_ALL_MASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE0_MACRO_RESERVED_REG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_MACRO_RESERVED_REG_ALL_BITS 32
 #define SJC16_DDR4_PHY_DQ_BYTE0_MACRO_RESERVED_REG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_MACRO_RESERVED_REG_ALL_MASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE0_MACRO_RESERVED_REG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_MACRO_RESERVED_REG_ALL_BITS 32
 #define SJC16_DDR4_PHY_DQ_BYTE0_MACRO_RESERVED_REG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_MACRO_RESERVED_REG_DATAMASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE0_MACRO_RESERVED_REG_RDWRMASK 0x00000000
 #define SJC16_DDR4_PHY_DQ_BYTE0_MACRO_RESERVED_REG_RESETVALUE 0x00000000
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_MACRO_RESERVED 0x1023c140
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_MACRO_RESERVED_BASE 0x140
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_MACRO_RESERVED_RESERVED_MASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_MACRO_RESERVED_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_MACRO_RESERVED_RESERVED_BITS 32
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_MACRO_RESERVED_RESERVED_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_MACRO_RESERVED_RESERVED_RESETVALUE 0x00000000
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_MACRO_RESERVED_ALL_MASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_MACRO_RESERVED_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_MACRO_RESERVED_ALL_BITS 32
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_MACRO_RESERVED_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_MACRO_RESERVED_ALL_MASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_MACRO_RESERVED_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_MACRO_RESERVED_ALL_BITS 32
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_MACRO_RESERVED_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_MACRO_RESERVED_DATAMASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_MACRO_RESERVED_RDWRMASK 0x00000000
 #define SJC16_DDR4_PHY_DQ_BYTE0_STATUS_MACRO_RESERVED_RESETVALUE 0x00000000
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT0 0x1023c400
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT0_BASE 0x400
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT0_MIN_VDL_STEP_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT0_MIN_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT0_MIN_VDL_STEP_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT0_MIN_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT0_MIN_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT0_RESERVED_MASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT0_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT0_RESERVED_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT0_RESERVED_SHIFT 7
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT0_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT0_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT0_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT0_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT0_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT0_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT0_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT0_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT0_DATAMASK 0x0000007f
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT0_RDWRMASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT0_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT1 0x1023c404
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT1_BASE 0x404
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT1_MIN_VDL_STEP_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT1_MIN_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT1_MIN_VDL_STEP_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT1_MIN_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT1_MIN_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT1_RESERVED_MASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT1_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT1_RESERVED_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT1_RESERVED_SHIFT 7
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT1_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT1_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT1_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT1_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT1_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT1_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT1_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT1_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT1_DATAMASK 0x0000007f
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT1_RDWRMASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT1_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT2 0x1023c408
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT2_BASE 0x408
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT2_MIN_VDL_STEP_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT2_MIN_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT2_MIN_VDL_STEP_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT2_MIN_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT2_MIN_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT2_RESERVED_MASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT2_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT2_RESERVED_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT2_RESERVED_SHIFT 7
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT2_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT2_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT2_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT2_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT2_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT2_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT2_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT2_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT2_DATAMASK 0x0000007f
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT2_RDWRMASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT2_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT3 0x1023c40c
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT3_BASE 0x40c
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT3_MIN_VDL_STEP_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT3_MIN_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT3_MIN_VDL_STEP_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT3_MIN_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT3_MIN_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT3_RESERVED_MASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT3_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT3_RESERVED_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT3_RESERVED_SHIFT 7
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT3_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT3_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT3_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT3_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT3_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT3_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT3_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT3_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT3_DATAMASK 0x0000007f
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT3_RDWRMASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT3_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT4 0x1023c410
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT4_BASE 0x410
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT4_MIN_VDL_STEP_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT4_MIN_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT4_MIN_VDL_STEP_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT4_MIN_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT4_MIN_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT4_RESERVED_MASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT4_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT4_RESERVED_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT4_RESERVED_SHIFT 7
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT4_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT4_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT4_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT4_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT4_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT4_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT4_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT4_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT4_DATAMASK 0x0000007f
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT4_RDWRMASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT4_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT5 0x1023c414
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT5_BASE 0x414
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT5_MIN_VDL_STEP_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT5_MIN_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT5_MIN_VDL_STEP_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT5_MIN_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT5_MIN_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT5_RESERVED_MASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT5_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT5_RESERVED_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT5_RESERVED_SHIFT 7
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT5_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT5_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT5_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT5_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT5_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT5_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT5_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT5_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT5_DATAMASK 0x0000007f
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT5_RDWRMASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT5_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT6 0x1023c418
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT6_BASE 0x418
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT6_MIN_VDL_STEP_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT6_MIN_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT6_MIN_VDL_STEP_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT6_MIN_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT6_MIN_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT6_RESERVED_MASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT6_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT6_RESERVED_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT6_RESERVED_SHIFT 7
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT6_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT6_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT6_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT6_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT6_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT6_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT6_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT6_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT6_DATAMASK 0x0000007f
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT6_RDWRMASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT6_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT7 0x1023c41c
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT7_BASE 0x41c
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT7_MIN_VDL_STEP_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT7_MIN_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT7_MIN_VDL_STEP_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT7_MIN_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT7_MIN_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT7_RESERVED_MASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT7_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT7_RESERVED_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT7_RESERVED_SHIFT 7
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT7_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT7_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT7_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT7_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT7_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT7_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT7_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT7_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT7_DATAMASK 0x0000007f
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT7_RDWRMASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT7_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_DBI 0x1023c420
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_DBI_BASE 0x420
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_DBI_MIN_VDL_STEP_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_DBI_MIN_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_DBI_MIN_VDL_STEP_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_DBI_MIN_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_DBI_MIN_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_DBI_RESERVED_MASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_DBI_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_DBI_RESERVED_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_DBI_RESERVED_SHIFT 7
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_DBI_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_DBI_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_DBI_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_DBI_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_DBI_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_DBI_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_DBI_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_DBI_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_DBI_DATAMASK 0x0000007f
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_DBI_RDWRMASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_DBI_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_EDC 0x1023c424
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_EDC_BASE 0x424
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_EDC_MIN_VDL_STEP_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_EDC_MIN_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_EDC_MIN_VDL_STEP_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_EDC_MIN_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_EDC_MIN_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_EDC_RESERVED_MASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_EDC_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_EDC_RESERVED_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_EDC_RESERVED_SHIFT 7
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_EDC_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_EDC_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_EDC_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_EDC_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_EDC_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_EDC_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_EDC_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_EDC_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_EDC_DATAMASK 0x0000007f
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_EDC_RDWRMASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_EDC_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MAX_VDL_DATA 0x1023c428
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MAX_VDL_DATA_BASE 0x428
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MAX_VDL_DATA_UI_SHIFT_MASK 0xe00
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MAX_VDL_DATA_UI_SHIFT_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MAX_VDL_DATA_UI_SHIFT_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MAX_VDL_DATA_UI_SHIFT_SHIFT 9
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MAX_VDL_DATA_UI_SHIFT_RESETVALUE 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MAX_VDL_DATA_MAX_VDL_STEP_MASK 0x1ff
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MAX_VDL_DATA_MAX_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MAX_VDL_DATA_MAX_VDL_STEP_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MAX_VDL_DATA_MAX_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MAX_VDL_DATA_MAX_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MAX_VDL_DATA_RESERVED_MASK 0xfffff000
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MAX_VDL_DATA_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MAX_VDL_DATA_RESERVED_BITS 20
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MAX_VDL_DATA_RESERVED_SHIFT 12
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MAX_VDL_DATA_ALL_MASK 0xfff
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MAX_VDL_DATA_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MAX_VDL_DATA_ALL_BITS 12
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MAX_VDL_DATA_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MAX_VDL_DATA_ALL_MASK 0xfff
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MAX_VDL_DATA_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MAX_VDL_DATA_ALL_BITS 12
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MAX_VDL_DATA_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MAX_VDL_DATA_DATAMASK 0x00000fff
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MAX_VDL_DATA_RDWRMASK 0xfffff000
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MAX_VDL_DATA_RESETVALUE 0x200
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MAX_VDL_DATA_SHADOW 0x1023c42c
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MAX_VDL_DATA_SHADOW_BASE 0x42c
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MAX_VDL_DATA_SHADOW_UI_SHIFT_MASK 0xe00
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MAX_VDL_DATA_SHADOW_UI_SHIFT_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MAX_VDL_DATA_SHADOW_UI_SHIFT_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MAX_VDL_DATA_SHADOW_UI_SHIFT_SHIFT 9
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MAX_VDL_DATA_SHADOW_UI_SHIFT_RESETVALUE 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MAX_VDL_DATA_SHADOW_MAX_VDL_STEP_MASK 0x1ff
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MAX_VDL_DATA_SHADOW_MAX_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MAX_VDL_DATA_SHADOW_MAX_VDL_STEP_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MAX_VDL_DATA_SHADOW_MAX_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MAX_VDL_DATA_SHADOW_MAX_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MAX_VDL_DATA_SHADOW_RESERVED_MASK 0xfffff000
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MAX_VDL_DATA_SHADOW_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MAX_VDL_DATA_SHADOW_RESERVED_BITS 20
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MAX_VDL_DATA_SHADOW_RESERVED_SHIFT 12
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MAX_VDL_DATA_SHADOW_ALL_MASK 0xfff
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MAX_VDL_DATA_SHADOW_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MAX_VDL_DATA_SHADOW_ALL_BITS 12
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MAX_VDL_DATA_SHADOW_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MAX_VDL_DATA_SHADOW_ALL_MASK 0xfff
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MAX_VDL_DATA_SHADOW_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MAX_VDL_DATA_SHADOW_ALL_BITS 12
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MAX_VDL_DATA_SHADOW_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MAX_VDL_DATA_SHADOW_DATAMASK 0x00000fff
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MAX_VDL_DATA_SHADOW_RDWRMASK 0xfffff000
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MAX_VDL_DATA_SHADOW_RESETVALUE 0x200
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MAX_VDL_DQS 0x1023c430
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MAX_VDL_DQS_BASE 0x430
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MAX_VDL_DQS_UI_SHIFT_MASK 0xe00
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MAX_VDL_DQS_UI_SHIFT_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MAX_VDL_DQS_UI_SHIFT_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MAX_VDL_DQS_UI_SHIFT_SHIFT 9
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MAX_VDL_DQS_UI_SHIFT_RESETVALUE 0x2
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MAX_VDL_DQS_MAX_VDL_STEP_MASK 0x1ff
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MAX_VDL_DQS_MAX_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MAX_VDL_DQS_MAX_VDL_STEP_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MAX_VDL_DQS_MAX_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MAX_VDL_DQS_MAX_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MAX_VDL_DQS_RESERVED_MASK 0xfffff000
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MAX_VDL_DQS_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MAX_VDL_DQS_RESERVED_BITS 20
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MAX_VDL_DQS_RESERVED_SHIFT 12
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MAX_VDL_DQS_ALL_MASK 0xfff
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MAX_VDL_DQS_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MAX_VDL_DQS_ALL_BITS 12
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MAX_VDL_DQS_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MAX_VDL_DQS_ALL_MASK 0xfff
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MAX_VDL_DQS_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MAX_VDL_DQS_ALL_BITS 12
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MAX_VDL_DQS_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MAX_VDL_DQS_DATAMASK 0x00000fff
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MAX_VDL_DQS_RDWRMASK 0xfffff000
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_MAX_VDL_DQS_RESETVALUE 0x400
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT0 0x1023c434
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT0_BASE 0x434
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT0_MIN_VDL_STEP_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT0_MIN_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT0_MIN_VDL_STEP_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT0_MIN_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT0_MIN_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT0_RESERVED_MASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT0_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT0_RESERVED_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT0_RESERVED_SHIFT 7
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT0_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT0_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT0_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT0_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT0_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT0_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT0_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT0_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT0_DATAMASK 0x0000007f
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT0_RDWRMASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT0_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT1 0x1023c438
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT1_BASE 0x438
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT1_MIN_VDL_STEP_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT1_MIN_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT1_MIN_VDL_STEP_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT1_MIN_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT1_MIN_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT1_RESERVED_MASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT1_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT1_RESERVED_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT1_RESERVED_SHIFT 7
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT1_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT1_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT1_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT1_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT1_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT1_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT1_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT1_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT1_DATAMASK 0x0000007f
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT1_RDWRMASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT1_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT2 0x1023c43c
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT2_BASE 0x43c
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT2_MIN_VDL_STEP_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT2_MIN_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT2_MIN_VDL_STEP_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT2_MIN_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT2_MIN_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT2_RESERVED_MASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT2_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT2_RESERVED_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT2_RESERVED_SHIFT 7
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT2_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT2_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT2_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT2_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT2_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT2_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT2_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT2_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT2_DATAMASK 0x0000007f
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT2_RDWRMASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT2_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT3 0x1023c440
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT3_BASE 0x440
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT3_MIN_VDL_STEP_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT3_MIN_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT3_MIN_VDL_STEP_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT3_MIN_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT3_MIN_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT3_RESERVED_MASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT3_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT3_RESERVED_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT3_RESERVED_SHIFT 7
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT3_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT3_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT3_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT3_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT3_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT3_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT3_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT3_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT3_DATAMASK 0x0000007f
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT3_RDWRMASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT3_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT4 0x1023c444
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT4_BASE 0x444
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT4_MIN_VDL_STEP_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT4_MIN_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT4_MIN_VDL_STEP_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT4_MIN_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT4_MIN_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT4_RESERVED_MASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT4_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT4_RESERVED_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT4_RESERVED_SHIFT 7
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT4_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT4_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT4_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT4_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT4_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT4_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT4_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT4_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT4_DATAMASK 0x0000007f
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT4_RDWRMASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT4_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT5 0x1023c448
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT5_BASE 0x448
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT5_MIN_VDL_STEP_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT5_MIN_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT5_MIN_VDL_STEP_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT5_MIN_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT5_MIN_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT5_RESERVED_MASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT5_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT5_RESERVED_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT5_RESERVED_SHIFT 7
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT5_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT5_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT5_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT5_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT5_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT5_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT5_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT5_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT5_DATAMASK 0x0000007f
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT5_RDWRMASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT5_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT6 0x1023c44c
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT6_BASE 0x44c
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT6_MIN_VDL_STEP_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT6_MIN_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT6_MIN_VDL_STEP_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT6_MIN_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT6_MIN_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT6_RESERVED_MASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT6_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT6_RESERVED_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT6_RESERVED_SHIFT 7
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT6_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT6_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT6_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT6_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT6_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT6_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT6_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT6_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT6_DATAMASK 0x0000007f
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT6_RDWRMASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT6_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT7 0x1023c450
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT7_BASE 0x450
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT7_MIN_VDL_STEP_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT7_MIN_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT7_MIN_VDL_STEP_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT7_MIN_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT7_MIN_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT7_RESERVED_MASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT7_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT7_RESERVED_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT7_RESERVED_SHIFT 7
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT7_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT7_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT7_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT7_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT7_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT7_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT7_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT7_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT7_DATAMASK 0x0000007f
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT7_RDWRMASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT7_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_DBI 0x1023c454
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_DBI_BASE 0x454
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_DBI_MIN_VDL_STEP_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_DBI_MIN_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_DBI_MIN_VDL_STEP_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_DBI_MIN_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_DBI_MIN_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_DBI_RESERVED_MASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_DBI_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_DBI_RESERVED_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_DBI_RESERVED_SHIFT 7
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_DBI_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_DBI_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_DBI_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_DBI_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_DBI_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_DBI_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_DBI_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_DBI_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_DBI_DATAMASK 0x0000007f
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_DBI_RDWRMASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_DBI_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_EDC 0x1023c458
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_EDC_BASE 0x458
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_EDC_MIN_VDL_STEP_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_EDC_MIN_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_EDC_MIN_VDL_STEP_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_EDC_MIN_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_EDC_MIN_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_EDC_RESERVED_MASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_EDC_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_EDC_RESERVED_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_EDC_RESERVED_SHIFT 7
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_EDC_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_EDC_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_EDC_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_EDC_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_EDC_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_EDC_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_EDC_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_EDC_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_EDC_DATAMASK 0x0000007f
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_EDC_RDWRMASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_EDC_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQS_MASTER_CTRL 0x1023c45c
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQS_MASTER_CTRL_BASE 0x45c
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQS_MASTER_CTRL_MASTER_MODE_MASK 0x10000
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQS_MASTER_CTRL_MASTER_MODE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQS_MASTER_CTRL_MASTER_MODE_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQS_MASTER_CTRL_MASTER_MODE_SHIFT 16
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQS_MASTER_CTRL_MASTER_MODE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQS_MASTER_CTRL_FORCE_UPDATE_MASK 0x1000
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQS_MASTER_CTRL_FORCE_UPDATE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQS_MASTER_CTRL_FORCE_UPDATE_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQS_MASTER_CTRL_FORCE_UPDATE_SHIFT 12
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQS_MASTER_CTRL_FORCE_UPDATE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQS_MASTER_CTRL_MAX_VDL_STEP_MASK 0x1ff
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQS_MASTER_CTRL_MAX_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQS_MASTER_CTRL_MAX_VDL_STEP_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQS_MASTER_CTRL_MAX_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQS_MASTER_CTRL_MAX_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQS_MASTER_CTRL_RESERVED_0_MASK 0xfffe0000
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQS_MASTER_CTRL_RESERVED_0_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQS_MASTER_CTRL_RESERVED_0_BITS 15
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQS_MASTER_CTRL_RESERVED_0_SHIFT 17
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQS_MASTER_CTRL_RESERVED_1_MASK 0xe000
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQS_MASTER_CTRL_RESERVED_1_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQS_MASTER_CTRL_RESERVED_1_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQS_MASTER_CTRL_RESERVED_1_SHIFT 13
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQS_MASTER_CTRL_RESERVED_2_MASK 0xe00
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQS_MASTER_CTRL_RESERVED_2_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQS_MASTER_CTRL_RESERVED_2_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQS_MASTER_CTRL_RESERVED_2_SHIFT 9
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQS_MASTER_CTRL_RESERVED_MASK 0xfffe0000
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQS_MASTER_CTRL_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQS_MASTER_CTRL_RESERVED_BITS 15
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQS_MASTER_CTRL_RESERVED_SHIFT 17
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQS_MASTER_CTRL_ALL_MASK 0x1ffff
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQS_MASTER_CTRL_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQS_MASTER_CTRL_ALL_BITS 17
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQS_MASTER_CTRL_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQS_MASTER_CTRL_ALL_MASK 0x1ffff
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQS_MASTER_CTRL_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQS_MASTER_CTRL_ALL_BITS 17
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQS_MASTER_CTRL_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQS_MASTER_CTRL_DATAMASK 0x000111ff
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQS_MASTER_CTRL_RDWRMASK 0xfffeee00
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQS_MASTER_CTRL_RESETVALUE 0x00000
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQSEP 0x1023c460
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQSEP_BASE 0x460
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQSEP_MAX_VDL_STEP_MASK 0x1ff
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQSEP_MAX_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQSEP_MAX_VDL_STEP_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQSEP_MAX_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQSEP_MAX_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQSEP_RESERVED_MASK 0xfffffe00
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQSEP_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQSEP_RESERVED_BITS 23
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQSEP_RESERVED_SHIFT 9
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQSEP_ALL_MASK 0x1ff
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQSEP_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQSEP_ALL_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQSEP_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQSEP_ALL_MASK 0x1ff
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQSEP_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQSEP_ALL_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQSEP_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQSEP_DATAMASK 0x000001ff
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQSEP_RDWRMASK 0xfffffe00
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQSEP_RESETVALUE 0x000
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQSDP 0x1023c464
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQSDP_BASE 0x464
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQSDP_MAX_VDL_STEP_MASK 0x1ff
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQSDP_MAX_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQSDP_MAX_VDL_STEP_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQSDP_MAX_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQSDP_MAX_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQSDP_RESERVED_MASK 0xfffffe00
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQSDP_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQSDP_RESERVED_BITS 23
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQSDP_RESERVED_SHIFT 9
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQSDP_ALL_MASK 0x1ff
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQSDP_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQSDP_ALL_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQSDP_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQSDP_ALL_MASK 0x1ff
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQSDP_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQSDP_ALL_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQSDP_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQSDP_DATAMASK 0x000001ff
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQSDP_RDWRMASK 0xfffffe00
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQSDP_RESETVALUE 0x000
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQSEN 0x1023c468
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQSEN_BASE 0x468
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQSEN_MAX_VDL_STEP_MASK 0x1ff
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQSEN_MAX_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQSEN_MAX_VDL_STEP_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQSEN_MAX_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQSEN_MAX_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQSEN_RESERVED_MASK 0xfffffe00
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQSEN_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQSEN_RESERVED_BITS 23
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQSEN_RESERVED_SHIFT 9
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQSEN_ALL_MASK 0x1ff
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQSEN_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQSEN_ALL_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQSEN_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQSEN_ALL_MASK 0x1ff
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQSEN_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQSEN_ALL_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQSEN_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQSEN_DATAMASK 0x000001ff
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQSEN_RDWRMASK 0xfffffe00
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQSEN_RESETVALUE 0x000
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQSDN 0x1023c46c
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQSDN_BASE 0x46c
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQSDN_MAX_VDL_STEP_MASK 0x1ff
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQSDN_MAX_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQSDN_MAX_VDL_STEP_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQSDN_MAX_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQSDN_MAX_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQSDN_RESERVED_MASK 0xfffffe00
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQSDN_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQSDN_RESERVED_BITS 23
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQSDN_RESERVED_SHIFT 9
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQSDN_ALL_MASK 0x1ff
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQSDN_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQSDN_ALL_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQSDN_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQSDN_ALL_MASK 0x1ff
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQSDN_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQSDN_ALL_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQSDN_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQSDN_DATAMASK 0x000001ff
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQSDN_RDWRMASK 0xfffffe00
 #define SJC16_DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQSDN_RESETVALUE 0x000
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_LEVELING_CONFIG 0x1023c470
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_LEVELING_CONFIG_BASE 0x470
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_LEVELING_CONFIG_WRITE_LEVELING_MODE_MASK 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_LEVELING_CONFIG_WRITE_LEVELING_MODE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_LEVELING_CONFIG_WRITE_LEVELING_MODE_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_LEVELING_CONFIG_WRITE_LEVELING_MODE_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_LEVELING_CONFIG_WRITE_LEVELING_MODE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_LEVELING_CONFIG_RESERVED_MASK 0xfffffffe
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_LEVELING_CONFIG_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_LEVELING_CONFIG_RESERVED_BITS 31
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_LEVELING_CONFIG_RESERVED_SHIFT 1
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_LEVELING_CONFIG_WRITE_LEVELING_MODE_MASK 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_LEVELING_CONFIG_WRITE_LEVELING_MODE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_LEVELING_CONFIG_WRITE_LEVELING_MODE_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_LEVELING_CONFIG_WRITE_LEVELING_MODE_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_LEVELING_CONFIG_WRITE_LEVELING_MODE_MASK 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_LEVELING_CONFIG_WRITE_LEVELING_MODE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_LEVELING_CONFIG_WRITE_LEVELING_MODE_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_LEVELING_CONFIG_WRITE_LEVELING_MODE_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_LEVELING_CONFIG_ALL_MASK 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_LEVELING_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_LEVELING_CONFIG_ALL_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_LEVELING_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_LEVELING_CONFIG_ALL_MASK 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_LEVELING_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_LEVELING_CONFIG_ALL_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_LEVELING_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_LEVELING_CONFIG_DATAMASK 0x00000001
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_LEVELING_CONFIG_RDWRMASK 0xfffffffe
 #define SJC16_DDR4_PHY_DQ_BYTE1_WRITE_LEVELING_CONFIG_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_REN_GEN_ERR_CTRL 0x1023c474
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_REN_GEN_ERR_CTRL_BASE 0x474
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_REN_GEN_ERR_CTRL_ERR2_CLEAR_MASK 0x2
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_REN_GEN_ERR_CTRL_ERR2_CLEAR_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_REN_GEN_ERR_CTRL_ERR2_CLEAR_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_REN_GEN_ERR_CTRL_ERR2_CLEAR_SHIFT 1
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_REN_GEN_ERR_CTRL_ERR2_CLEAR_RESETVALUE 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_REN_GEN_ERR_CTRL_ERR1_CLEAR_MASK 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_REN_GEN_ERR_CTRL_ERR1_CLEAR_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_REN_GEN_ERR_CTRL_ERR1_CLEAR_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_REN_GEN_ERR_CTRL_ERR1_CLEAR_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_REN_GEN_ERR_CTRL_ERR1_CLEAR_RESETVALUE 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_REN_GEN_ERR_CTRL_RESERVED_MASK 0xfffffffc
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_REN_GEN_ERR_CTRL_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_REN_GEN_ERR_CTRL_RESERVED_BITS 30
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_REN_GEN_ERR_CTRL_RESERVED_SHIFT 2
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_REN_GEN_ERR_CTRL_ALL_MASK 0x3
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_REN_GEN_ERR_CTRL_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_REN_GEN_ERR_CTRL_ALL_BITS 2
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_REN_GEN_ERR_CTRL_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_REN_GEN_ERR_CTRL_ALL_MASK 0x3
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_REN_GEN_ERR_CTRL_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_REN_GEN_ERR_CTRL_ALL_BITS 2
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_REN_GEN_ERR_CTRL_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_REN_GEN_ERR_CTRL_DATAMASK 0x00000003
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_REN_GEN_ERR_CTRL_RDWRMASK 0xfffffffc
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_REN_GEN_ERR_CTRL_RESETVALUE 0x3
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_REN_FIFO_CONFIG 0x1023c478
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_REN_FIFO_CONFIG_BASE 0x478
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_REN_FIFO_CONFIG_RD_2G_DELAY_DEC_MASK 0x800
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_REN_FIFO_CONFIG_RD_2G_DELAY_DEC_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_REN_FIFO_CONFIG_RD_2G_DELAY_DEC_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_REN_FIFO_CONFIG_RD_2G_DELAY_DEC_SHIFT 11
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_REN_FIFO_CONFIG_RD_2G_DELAY_DEC_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_REN_FIFO_CONFIG_RD_2G_DELAY_INC_MASK 0x400
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_REN_FIFO_CONFIG_RD_2G_DELAY_INC_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_REN_FIFO_CONFIG_RD_2G_DELAY_INC_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_REN_FIFO_CONFIG_RD_2G_DELAY_INC_SHIFT 10
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_REN_FIFO_CONFIG_RD_2G_DELAY_INC_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_REN_FIFO_CONFIG_RD2_2G_DELAY_MASK 0x3e0
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_REN_FIFO_CONFIG_RD2_2G_DELAY_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_REN_FIFO_CONFIG_RD2_2G_DELAY_BITS 5
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_REN_FIFO_CONFIG_RD2_2G_DELAY_SHIFT 5
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_REN_FIFO_CONFIG_RD2_2G_DELAY_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_REN_FIFO_CONFIG_RD_2G_DELAY_MASK 0x1f
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_REN_FIFO_CONFIG_RD_2G_DELAY_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_REN_FIFO_CONFIG_RD_2G_DELAY_BITS 5
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_REN_FIFO_CONFIG_RD_2G_DELAY_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_REN_FIFO_CONFIG_RD_2G_DELAY_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_REN_FIFO_CONFIG_RESERVED_MASK 0xfffff000
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_REN_FIFO_CONFIG_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_REN_FIFO_CONFIG_RESERVED_BITS 20
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_REN_FIFO_CONFIG_RESERVED_SHIFT 12
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_REN_FIFO_CONFIG_ALL_MASK 0xfff
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_REN_FIFO_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_REN_FIFO_CONFIG_ALL_BITS 12
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_REN_FIFO_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_REN_FIFO_CONFIG_ALL_MASK 0xfff
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_REN_FIFO_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_REN_FIFO_CONFIG_ALL_BITS 12
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_REN_FIFO_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_REN_FIFO_CONFIG_DATAMASK 0x00000fff
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_REN_FIFO_CONFIG_RDWRMASK 0xfffff000
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_REN_FIFO_CONFIG_RESETVALUE 0x000
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_REN_STRETCH_CONFIG 0x1023c47c
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_REN_STRETCH_CONFIG_BASE 0x47c
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_REN_STRETCH_CONFIG_A_PLUS_2_MASK 0x20
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_REN_STRETCH_CONFIG_A_PLUS_2_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_REN_STRETCH_CONFIG_A_PLUS_2_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_REN_STRETCH_CONFIG_A_PLUS_2_SHIFT 5
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_REN_STRETCH_CONFIG_A_PLUS_2_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_REN_STRETCH_CONFIG_A_PLUS_1_MASK 0x10
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_REN_STRETCH_CONFIG_A_PLUS_1_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_REN_STRETCH_CONFIG_A_PLUS_1_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_REN_STRETCH_CONFIG_A_PLUS_1_SHIFT 4
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_REN_STRETCH_CONFIG_A_PLUS_1_RESETVALUE 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_REN_STRETCH_CONFIG_A_0_MASK 0x8
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_REN_STRETCH_CONFIG_A_0_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_REN_STRETCH_CONFIG_A_0_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_REN_STRETCH_CONFIG_A_0_SHIFT 3
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_REN_STRETCH_CONFIG_A_0_RESETVALUE 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_REN_STRETCH_CONFIG_A_MINUS_1_MASK 0x4
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_REN_STRETCH_CONFIG_A_MINUS_1_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_REN_STRETCH_CONFIG_A_MINUS_1_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_REN_STRETCH_CONFIG_A_MINUS_1_SHIFT 2
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_REN_STRETCH_CONFIG_A_MINUS_1_RESETVALUE 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_REN_STRETCH_CONFIG_A_MINUS_2_MASK 0x2
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_REN_STRETCH_CONFIG_A_MINUS_2_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_REN_STRETCH_CONFIG_A_MINUS_2_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_REN_STRETCH_CONFIG_A_MINUS_2_SHIFT 1
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_REN_STRETCH_CONFIG_A_MINUS_2_RESETVALUE 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_REN_STRETCH_CONFIG_A_MINUS_3_MASK 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_REN_STRETCH_CONFIG_A_MINUS_3_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_REN_STRETCH_CONFIG_A_MINUS_3_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_REN_STRETCH_CONFIG_A_MINUS_3_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_REN_STRETCH_CONFIG_A_MINUS_3_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_REN_STRETCH_CONFIG_RESERVED_MASK 0xffffffc0
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_REN_STRETCH_CONFIG_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_REN_STRETCH_CONFIG_RESERVED_BITS 26
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_REN_STRETCH_CONFIG_RESERVED_SHIFT 6
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_REN_STRETCH_CONFIG_ALL_MASK 0x3f
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_REN_STRETCH_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_REN_STRETCH_CONFIG_ALL_BITS 6
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_REN_STRETCH_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_REN_STRETCH_CONFIG_ALL_MASK 0x3f
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_REN_STRETCH_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_REN_STRETCH_CONFIG_ALL_BITS 6
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_REN_STRETCH_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_REN_STRETCH_CONFIG_DATAMASK 0x0000003f
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_REN_STRETCH_CONFIG_RDWRMASK 0xffffffc0
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_REN_STRETCH_CONFIG_RESETVALUE 0x1e
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_READ_MAX_VDL_FSM 0x1023c480
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_READ_MAX_VDL_FSM_BASE 0x480
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_READ_MAX_VDL_FSM_MAX_VDL_STEP_MASK 0x1ff
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_READ_MAX_VDL_FSM_MAX_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_READ_MAX_VDL_FSM_MAX_VDL_STEP_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_READ_MAX_VDL_FSM_MAX_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_READ_MAX_VDL_FSM_MAX_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_READ_MAX_VDL_FSM_RESERVED_MASK 0xfffffe00
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_READ_MAX_VDL_FSM_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_READ_MAX_VDL_FSM_RESERVED_BITS 23
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_READ_MAX_VDL_FSM_RESERVED_SHIFT 9
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_READ_MAX_VDL_FSM_ALL_MASK 0x1ff
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_READ_MAX_VDL_FSM_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_READ_MAX_VDL_FSM_ALL_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_READ_MAX_VDL_FSM_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_READ_MAX_VDL_FSM_ALL_MASK 0x1ff
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_READ_MAX_VDL_FSM_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_READ_MAX_VDL_FSM_ALL_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_READ_MAX_VDL_FSM_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_READ_MAX_VDL_FSM_DATAMASK 0x000001ff
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_READ_MAX_VDL_FSM_RDWRMASK 0xfffffe00
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_READ_MAX_VDL_FSM_RESETVALUE 0x000
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_OE_CONFIG 0x1023c484
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_OE_CONFIG_BASE 0x484
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_OE_CONFIG_OE_POST_CYCLES_MASK 0x38
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_OE_CONFIG_OE_POST_CYCLES_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_OE_CONFIG_OE_POST_CYCLES_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_OE_CONFIG_OE_POST_CYCLES_SHIFT 3
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_OE_CONFIG_OE_POST_CYCLES_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_OE_CONFIG_OE_PRE_CYCLES_MASK 0x7
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_OE_CONFIG_OE_PRE_CYCLES_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_OE_CONFIG_OE_PRE_CYCLES_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_OE_CONFIG_OE_PRE_CYCLES_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_OE_CONFIG_OE_PRE_CYCLES_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_OE_CONFIG_RESERVED_MASK 0xffffffc0
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_OE_CONFIG_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_OE_CONFIG_RESERVED_BITS 26
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_OE_CONFIG_RESERVED_SHIFT 6
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_OE_CONFIG_ALL_MASK 0x3f
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_OE_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_OE_CONFIG_ALL_BITS 6
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_OE_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_OE_CONFIG_ALL_MASK 0x3f
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_OE_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_OE_CONFIG_ALL_BITS 6
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_OE_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_OE_CONFIG_DATAMASK 0x0000003f
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_OE_CONFIG_RDWRMASK 0xffffffc0
 #define SJC16_DDR4_PHY_DQ_BYTE1_DDR4_OE_CONFIG_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE1_GDDR5_READ_ALIGNMENT_CTRL 0x1023c488
 #define SJC16_DDR4_PHY_DQ_BYTE1_GDDR5_READ_ALIGNMENT_CTRL_BASE 0x488
 #define SJC16_DDR4_PHY_DQ_BYTE1_GDDR5_READ_ALIGNMENT_CTRL_RDATA_WR2RD_DELAY_DEC_MASK 0x20000000
 #define SJC16_DDR4_PHY_DQ_BYTE1_GDDR5_READ_ALIGNMENT_CTRL_RDATA_WR2RD_DELAY_DEC_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_GDDR5_READ_ALIGNMENT_CTRL_RDATA_WR2RD_DELAY_DEC_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE1_GDDR5_READ_ALIGNMENT_CTRL_RDATA_WR2RD_DELAY_DEC_SHIFT 29
 #define SJC16_DDR4_PHY_DQ_BYTE1_GDDR5_READ_ALIGNMENT_CTRL_RDATA_WR2RD_DELAY_DEC_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_GDDR5_READ_ALIGNMENT_CTRL_RDATA_WR2RD_DELAY_INC_MASK 0x10000000
 #define SJC16_DDR4_PHY_DQ_BYTE1_GDDR5_READ_ALIGNMENT_CTRL_RDATA_WR2RD_DELAY_INC_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_GDDR5_READ_ALIGNMENT_CTRL_RDATA_WR2RD_DELAY_INC_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE1_GDDR5_READ_ALIGNMENT_CTRL_RDATA_WR2RD_DELAY_INC_SHIFT 28
 #define SJC16_DDR4_PHY_DQ_BYTE1_GDDR5_READ_ALIGNMENT_CTRL_RDATA_WR2RD_DELAY_INC_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_GDDR5_READ_ALIGNMENT_CTRL_RDATA_WR2RD_DELAY_MASK 0xf000000
 #define SJC16_DDR4_PHY_DQ_BYTE1_GDDR5_READ_ALIGNMENT_CTRL_RDATA_WR2RD_DELAY_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_GDDR5_READ_ALIGNMENT_CTRL_RDATA_WR2RD_DELAY_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE1_GDDR5_READ_ALIGNMENT_CTRL_RDATA_WR2RD_DELAY_SHIFT 24
 #define SJC16_DDR4_PHY_DQ_BYTE1_GDDR5_READ_ALIGNMENT_CTRL_RDATA_WR2RD_DELAY_RESETVALUE 0x4
 #define SJC16_DDR4_PHY_DQ_BYTE1_GDDR5_READ_ALIGNMENT_CTRL_EDC_HALF_RATE_UI_SELECT_MASK 0x800000
 #define SJC16_DDR4_PHY_DQ_BYTE1_GDDR5_READ_ALIGNMENT_CTRL_EDC_HALF_RATE_UI_SELECT_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_GDDR5_READ_ALIGNMENT_CTRL_EDC_HALF_RATE_UI_SELECT_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE1_GDDR5_READ_ALIGNMENT_CTRL_EDC_HALF_RATE_UI_SELECT_SHIFT 23
 #define SJC16_DDR4_PHY_DQ_BYTE1_GDDR5_READ_ALIGNMENT_CTRL_EDC_HALF_RATE_UI_SELECT_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_GDDR5_READ_ALIGNMENT_CTRL_EDC_HALF_RATE_ENABLE_MASK 0x400000
 #define SJC16_DDR4_PHY_DQ_BYTE1_GDDR5_READ_ALIGNMENT_CTRL_EDC_HALF_RATE_ENABLE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_GDDR5_READ_ALIGNMENT_CTRL_EDC_HALF_RATE_ENABLE_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE1_GDDR5_READ_ALIGNMENT_CTRL_EDC_HALF_RATE_ENABLE_SHIFT 22
 #define SJC16_DDR4_PHY_DQ_BYTE1_GDDR5_READ_ALIGNMENT_CTRL_EDC_HALF_RATE_ENABLE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_GDDR5_READ_ALIGNMENT_CTRL_EDC_VALID_WR2RD_DELAY_DEC_MASK 0x200000
 #define SJC16_DDR4_PHY_DQ_BYTE1_GDDR5_READ_ALIGNMENT_CTRL_EDC_VALID_WR2RD_DELAY_DEC_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_GDDR5_READ_ALIGNMENT_CTRL_EDC_VALID_WR2RD_DELAY_DEC_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE1_GDDR5_READ_ALIGNMENT_CTRL_EDC_VALID_WR2RD_DELAY_DEC_SHIFT 21
 #define SJC16_DDR4_PHY_DQ_BYTE1_GDDR5_READ_ALIGNMENT_CTRL_EDC_VALID_WR2RD_DELAY_DEC_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_GDDR5_READ_ALIGNMENT_CTRL_EDC_VALID_WR2RD_DELAY_INC_MASK 0x100000
 #define SJC16_DDR4_PHY_DQ_BYTE1_GDDR5_READ_ALIGNMENT_CTRL_EDC_VALID_WR2RD_DELAY_INC_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_GDDR5_READ_ALIGNMENT_CTRL_EDC_VALID_WR2RD_DELAY_INC_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE1_GDDR5_READ_ALIGNMENT_CTRL_EDC_VALID_WR2RD_DELAY_INC_SHIFT 20
 #define SJC16_DDR4_PHY_DQ_BYTE1_GDDR5_READ_ALIGNMENT_CTRL_EDC_VALID_WR2RD_DELAY_INC_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_GDDR5_READ_ALIGNMENT_CTRL_EDC_VALID_WR2RD_DELAY_MASK 0xf0000
 #define SJC16_DDR4_PHY_DQ_BYTE1_GDDR5_READ_ALIGNMENT_CTRL_EDC_VALID_WR2RD_DELAY_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_GDDR5_READ_ALIGNMENT_CTRL_EDC_VALID_WR2RD_DELAY_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE1_GDDR5_READ_ALIGNMENT_CTRL_EDC_VALID_WR2RD_DELAY_SHIFT 16
 #define SJC16_DDR4_PHY_DQ_BYTE1_GDDR5_READ_ALIGNMENT_CTRL_EDC_VALID_WR2RD_DELAY_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_GDDR5_READ_ALIGNMENT_CTRL_EDC_UI_SHIFT_MASK 0x7000
 #define SJC16_DDR4_PHY_DQ_BYTE1_GDDR5_READ_ALIGNMENT_CTRL_EDC_UI_SHIFT_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_GDDR5_READ_ALIGNMENT_CTRL_EDC_UI_SHIFT_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE1_GDDR5_READ_ALIGNMENT_CTRL_EDC_UI_SHIFT_SHIFT 12
 #define SJC16_DDR4_PHY_DQ_BYTE1_GDDR5_READ_ALIGNMENT_CTRL_EDC_UI_SHIFT_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_GDDR5_READ_ALIGNMENT_CTRL_DATA_VALID_WR2RD_DELAY_DEC_MASK 0x200
 #define SJC16_DDR4_PHY_DQ_BYTE1_GDDR5_READ_ALIGNMENT_CTRL_DATA_VALID_WR2RD_DELAY_DEC_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_GDDR5_READ_ALIGNMENT_CTRL_DATA_VALID_WR2RD_DELAY_DEC_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE1_GDDR5_READ_ALIGNMENT_CTRL_DATA_VALID_WR2RD_DELAY_DEC_SHIFT 9
 #define SJC16_DDR4_PHY_DQ_BYTE1_GDDR5_READ_ALIGNMENT_CTRL_DATA_VALID_WR2RD_DELAY_DEC_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_GDDR5_READ_ALIGNMENT_CTRL_DATA_VALID_WR2RD_DELAY_INC_MASK 0x100
 #define SJC16_DDR4_PHY_DQ_BYTE1_GDDR5_READ_ALIGNMENT_CTRL_DATA_VALID_WR2RD_DELAY_INC_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_GDDR5_READ_ALIGNMENT_CTRL_DATA_VALID_WR2RD_DELAY_INC_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE1_GDDR5_READ_ALIGNMENT_CTRL_DATA_VALID_WR2RD_DELAY_INC_SHIFT 8
 #define SJC16_DDR4_PHY_DQ_BYTE1_GDDR5_READ_ALIGNMENT_CTRL_DATA_VALID_WR2RD_DELAY_INC_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_GDDR5_READ_ALIGNMENT_CTRL_DATA_VALID_WR2RD_DELAY_MASK 0xf0
 #define SJC16_DDR4_PHY_DQ_BYTE1_GDDR5_READ_ALIGNMENT_CTRL_DATA_VALID_WR2RD_DELAY_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_GDDR5_READ_ALIGNMENT_CTRL_DATA_VALID_WR2RD_DELAY_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE1_GDDR5_READ_ALIGNMENT_CTRL_DATA_VALID_WR2RD_DELAY_SHIFT 4
 #define SJC16_DDR4_PHY_DQ_BYTE1_GDDR5_READ_ALIGNMENT_CTRL_DATA_VALID_WR2RD_DELAY_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_GDDR5_READ_ALIGNMENT_CTRL_DATA_UI_SHIFT_MASK 0x7
 #define SJC16_DDR4_PHY_DQ_BYTE1_GDDR5_READ_ALIGNMENT_CTRL_DATA_UI_SHIFT_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_GDDR5_READ_ALIGNMENT_CTRL_DATA_UI_SHIFT_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE1_GDDR5_READ_ALIGNMENT_CTRL_DATA_UI_SHIFT_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_GDDR5_READ_ALIGNMENT_CTRL_DATA_UI_SHIFT_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_GDDR5_READ_ALIGNMENT_CTRL_RESERVED_0_MASK 0xc0000000
 #define SJC16_DDR4_PHY_DQ_BYTE1_GDDR5_READ_ALIGNMENT_CTRL_RESERVED_0_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_GDDR5_READ_ALIGNMENT_CTRL_RESERVED_0_BITS 2
 #define SJC16_DDR4_PHY_DQ_BYTE1_GDDR5_READ_ALIGNMENT_CTRL_RESERVED_0_SHIFT 30
 #define SJC16_DDR4_PHY_DQ_BYTE1_GDDR5_READ_ALIGNMENT_CTRL_RESERVED_2_MASK 0xc00
 #define SJC16_DDR4_PHY_DQ_BYTE1_GDDR5_READ_ALIGNMENT_CTRL_RESERVED_2_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_GDDR5_READ_ALIGNMENT_CTRL_RESERVED_2_BITS 2
 #define SJC16_DDR4_PHY_DQ_BYTE1_GDDR5_READ_ALIGNMENT_CTRL_RESERVED_2_SHIFT 10
 #define SJC16_DDR4_PHY_DQ_BYTE1_GDDR5_READ_ALIGNMENT_CTRL_RESERVED_MASK 0xc0000000
 #define SJC16_DDR4_PHY_DQ_BYTE1_GDDR5_READ_ALIGNMENT_CTRL_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_GDDR5_READ_ALIGNMENT_CTRL_RESERVED_BITS 2
 #define SJC16_DDR4_PHY_DQ_BYTE1_GDDR5_READ_ALIGNMENT_CTRL_RESERVED_SHIFT 30
 #define SJC16_DDR4_PHY_DQ_BYTE1_GDDR5_READ_ALIGNMENT_CTRL_ALL_MASK 0x3fffffff
 #define SJC16_DDR4_PHY_DQ_BYTE1_GDDR5_READ_ALIGNMENT_CTRL_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_GDDR5_READ_ALIGNMENT_CTRL_ALL_BITS 30
 #define SJC16_DDR4_PHY_DQ_BYTE1_GDDR5_READ_ALIGNMENT_CTRL_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_GDDR5_READ_ALIGNMENT_CTRL_ALL_MASK 0x3fffffff
 #define SJC16_DDR4_PHY_DQ_BYTE1_GDDR5_READ_ALIGNMENT_CTRL_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_GDDR5_READ_ALIGNMENT_CTRL_ALL_BITS 30
 #define SJC16_DDR4_PHY_DQ_BYTE1_GDDR5_READ_ALIGNMENT_CTRL_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_GDDR5_READ_ALIGNMENT_CTRL_DATAMASK 0x3fff73f7
 #define SJC16_DDR4_PHY_DQ_BYTE1_GDDR5_READ_ALIGNMENT_CTRL_RDWRMASK 0xc0008c08
 #define SJC16_DDR4_PHY_DQ_BYTE1_GDDR5_READ_ALIGNMENT_CTRL_RESETVALUE 0x04000000
 #define SJC16_DDR4_PHY_DQ_BYTE1_GDDR5_READ_FSM_CTRL 0x1023c48c
 #define SJC16_DDR4_PHY_DQ_BYTE1_GDDR5_READ_FSM_CTRL_BASE 0x48c
 #define SJC16_DDR4_PHY_DQ_BYTE1_GDDR5_READ_FSM_CTRL_QDR_MODE_MASK 0x8
 #define SJC16_DDR4_PHY_DQ_BYTE1_GDDR5_READ_FSM_CTRL_QDR_MODE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_GDDR5_READ_FSM_CTRL_QDR_MODE_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE1_GDDR5_READ_FSM_CTRL_QDR_MODE_SHIFT 3
 #define SJC16_DDR4_PHY_DQ_BYTE1_GDDR5_READ_FSM_CTRL_QDR_MODE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_GDDR5_READ_FSM_CTRL_DATA_VALID_GEN_ERROR_CLEAR_MASK 0x4
 #define SJC16_DDR4_PHY_DQ_BYTE1_GDDR5_READ_FSM_CTRL_DATA_VALID_GEN_ERROR_CLEAR_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_GDDR5_READ_FSM_CTRL_DATA_VALID_GEN_ERROR_CLEAR_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE1_GDDR5_READ_FSM_CTRL_DATA_VALID_GEN_ERROR_CLEAR_SHIFT 2
 #define SJC16_DDR4_PHY_DQ_BYTE1_GDDR5_READ_FSM_CTRL_DATA_VALID_GEN_ERROR_CLEAR_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_GDDR5_READ_FSM_CTRL_DATA_VALID_GEN_ENABLE_MASK 0x2
 #define SJC16_DDR4_PHY_DQ_BYTE1_GDDR5_READ_FSM_CTRL_DATA_VALID_GEN_ENABLE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_GDDR5_READ_FSM_CTRL_DATA_VALID_GEN_ENABLE_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE1_GDDR5_READ_FSM_CTRL_DATA_VALID_GEN_ENABLE_SHIFT 1
 #define SJC16_DDR4_PHY_DQ_BYTE1_GDDR5_READ_FSM_CTRL_DATA_VALID_GEN_ENABLE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_GDDR5_READ_FSM_CTRL_SYSTEM_ENABLE_MASK 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE1_GDDR5_READ_FSM_CTRL_SYSTEM_ENABLE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_GDDR5_READ_FSM_CTRL_SYSTEM_ENABLE_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE1_GDDR5_READ_FSM_CTRL_SYSTEM_ENABLE_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_GDDR5_READ_FSM_CTRL_SYSTEM_ENABLE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_GDDR5_READ_FSM_CTRL_RESERVED_MASK 0xfffffff0
 #define SJC16_DDR4_PHY_DQ_BYTE1_GDDR5_READ_FSM_CTRL_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_GDDR5_READ_FSM_CTRL_RESERVED_BITS 28
 #define SJC16_DDR4_PHY_DQ_BYTE1_GDDR5_READ_FSM_CTRL_RESERVED_SHIFT 4
 #define SJC16_DDR4_PHY_DQ_BYTE1_GDDR5_READ_FSM_CTRL_ALL_MASK 0xf
 #define SJC16_DDR4_PHY_DQ_BYTE1_GDDR5_READ_FSM_CTRL_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_GDDR5_READ_FSM_CTRL_ALL_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE1_GDDR5_READ_FSM_CTRL_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_GDDR5_READ_FSM_CTRL_ALL_MASK 0xf
 #define SJC16_DDR4_PHY_DQ_BYTE1_GDDR5_READ_FSM_CTRL_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_GDDR5_READ_FSM_CTRL_ALL_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE1_GDDR5_READ_FSM_CTRL_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_GDDR5_READ_FSM_CTRL_DATAMASK 0x0000000f
 #define SJC16_DDR4_PHY_DQ_BYTE1_GDDR5_READ_FSM_CTRL_RDWRMASK 0xfffffff0
 #define SJC16_DDR4_PHY_DQ_BYTE1_GDDR5_READ_FSM_CTRL_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_DATA_IO_CONFIG 0x1023c490
 #define SJC16_DDR4_PHY_DQ_BYTE1_DATA_IO_CONFIG_BASE 0x490
 #define SJC16_DDR4_PHY_DQ_BYTE1_DATA_IO_CONFIG_PTERM_MASK 0x1f000000
 #define SJC16_DDR4_PHY_DQ_BYTE1_DATA_IO_CONFIG_PTERM_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_DATA_IO_CONFIG_PTERM_BITS 5
 #define SJC16_DDR4_PHY_DQ_BYTE1_DATA_IO_CONFIG_PTERM_SHIFT 24
 #define SJC16_DDR4_PHY_DQ_BYTE1_DATA_IO_CONFIG_PTERM_RESETVALUE 0x10
 #define SJC16_DDR4_PHY_DQ_BYTE1_DATA_IO_CONFIG_NTERM_MASK 0xf80000
 #define SJC16_DDR4_PHY_DQ_BYTE1_DATA_IO_CONFIG_NTERM_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_DATA_IO_CONFIG_NTERM_BITS 5
 #define SJC16_DDR4_PHY_DQ_BYTE1_DATA_IO_CONFIG_NTERM_SHIFT 19
 #define SJC16_DDR4_PHY_DQ_BYTE1_DATA_IO_CONFIG_NTERM_RESETVALUE 0xf
 #define SJC16_DDR4_PHY_DQ_BYTE1_DATA_IO_CONFIG_PULL_UP_OFF_B_MASK 0x20000
 #define SJC16_DDR4_PHY_DQ_BYTE1_DATA_IO_CONFIG_PULL_UP_OFF_B_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_DATA_IO_CONFIG_PULL_UP_OFF_B_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE1_DATA_IO_CONFIG_PULL_UP_OFF_B_SHIFT 17
 #define SJC16_DDR4_PHY_DQ_BYTE1_DATA_IO_CONFIG_PULL_UP_OFF_B_RESETVALUE 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE1_DATA_IO_CONFIG_RX_BIAS_MASK 0x18000
 #define SJC16_DDR4_PHY_DQ_BYTE1_DATA_IO_CONFIG_RX_BIAS_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_DATA_IO_CONFIG_RX_BIAS_BITS 2
 #define SJC16_DDR4_PHY_DQ_BYTE1_DATA_IO_CONFIG_RX_BIAS_SHIFT 15
 #define SJC16_DDR4_PHY_DQ_BYTE1_DATA_IO_CONFIG_RX_BIAS_RESETVALUE 0x3
 #define SJC16_DDR4_PHY_DQ_BYTE1_DATA_IO_CONFIG_PEAK_MASK 0x6000
 #define SJC16_DDR4_PHY_DQ_BYTE1_DATA_IO_CONFIG_PEAK_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_DATA_IO_CONFIG_PEAK_BITS 2
 #define SJC16_DDR4_PHY_DQ_BYTE1_DATA_IO_CONFIG_PEAK_SHIFT 13
 #define SJC16_DDR4_PHY_DQ_BYTE1_DATA_IO_CONFIG_PEAK_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_DATA_IO_CONFIG_DEM_MASK 0x1800
 #define SJC16_DDR4_PHY_DQ_BYTE1_DATA_IO_CONFIG_DEM_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_DATA_IO_CONFIG_DEM_BITS 2
 #define SJC16_DDR4_PHY_DQ_BYTE1_DATA_IO_CONFIG_DEM_SHIFT 11
 #define SJC16_DDR4_PHY_DQ_BYTE1_DATA_IO_CONFIG_DEM_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_DATA_IO_CONFIG_RXENB_MASK 0x400
 #define SJC16_DDR4_PHY_DQ_BYTE1_DATA_IO_CONFIG_RXENB_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_DATA_IO_CONFIG_RXENB_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE1_DATA_IO_CONFIG_RXENB_SHIFT 10
 #define SJC16_DDR4_PHY_DQ_BYTE1_DATA_IO_CONFIG_RXENB_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_DATA_IO_CONFIG_PD_MASK 0x3e0
 #define SJC16_DDR4_PHY_DQ_BYTE1_DATA_IO_CONFIG_PD_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_DATA_IO_CONFIG_PD_BITS 5
 #define SJC16_DDR4_PHY_DQ_BYTE1_DATA_IO_CONFIG_PD_SHIFT 5
 #define SJC16_DDR4_PHY_DQ_BYTE1_DATA_IO_CONFIG_PD_RESETVALUE 0x10
 #define SJC16_DDR4_PHY_DQ_BYTE1_DATA_IO_CONFIG_ND_MASK 0x1f
 #define SJC16_DDR4_PHY_DQ_BYTE1_DATA_IO_CONFIG_ND_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_DATA_IO_CONFIG_ND_BITS 5
 #define SJC16_DDR4_PHY_DQ_BYTE1_DATA_IO_CONFIG_ND_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_DATA_IO_CONFIG_ND_RESETVALUE 0xf
 #define SJC16_DDR4_PHY_DQ_BYTE1_DATA_IO_CONFIG_RESERVED_MASK 0xe0000000
 #define SJC16_DDR4_PHY_DQ_BYTE1_DATA_IO_CONFIG_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_DATA_IO_CONFIG_RESERVED_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE1_DATA_IO_CONFIG_RESERVED_SHIFT 29
 #define SJC16_DDR4_PHY_DQ_BYTE1_DATA_IO_CONFIG_ALL_MASK 0x1fffffff
 #define SJC16_DDR4_PHY_DQ_BYTE1_DATA_IO_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_DATA_IO_CONFIG_ALL_BITS 29
 #define SJC16_DDR4_PHY_DQ_BYTE1_DATA_IO_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_DATA_IO_CONFIG_ALL_MASK 0x1fffffff
 #define SJC16_DDR4_PHY_DQ_BYTE1_DATA_IO_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_DATA_IO_CONFIG_ALL_BITS 29
 #define SJC16_DDR4_PHY_DQ_BYTE1_DATA_IO_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_DATA_IO_CONFIG_DATAMASK 0x1ffbffff
 #define SJC16_DDR4_PHY_DQ_BYTE1_DATA_IO_CONFIG_RDWRMASK 0xe0040000
 #define SJC16_DDR4_PHY_DQ_BYTE1_DATA_IO_CONFIG_RESETVALUE 0x107b820f
 #define SJC16_DDR4_PHY_DQ_BYTE1_DQS_IO_CONFIG 0x1023c494
 #define SJC16_DDR4_PHY_DQ_BYTE1_DQS_IO_CONFIG_BASE 0x494
 #define SJC16_DDR4_PHY_DQ_BYTE1_DQS_IO_CONFIG_PTERM_MASK 0x1f000000
 #define SJC16_DDR4_PHY_DQ_BYTE1_DQS_IO_CONFIG_PTERM_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_DQS_IO_CONFIG_PTERM_BITS 5
 #define SJC16_DDR4_PHY_DQ_BYTE1_DQS_IO_CONFIG_PTERM_SHIFT 24
 #define SJC16_DDR4_PHY_DQ_BYTE1_DQS_IO_CONFIG_PTERM_RESETVALUE 0x10
 #define SJC16_DDR4_PHY_DQ_BYTE1_DQS_IO_CONFIG_NTERM_MASK 0xf80000
 #define SJC16_DDR4_PHY_DQ_BYTE1_DQS_IO_CONFIG_NTERM_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_DQS_IO_CONFIG_NTERM_BITS 5
 #define SJC16_DDR4_PHY_DQ_BYTE1_DQS_IO_CONFIG_NTERM_SHIFT 19
 #define SJC16_DDR4_PHY_DQ_BYTE1_DQS_IO_CONFIG_NTERM_RESETVALUE 0xf
 #define SJC16_DDR4_PHY_DQ_BYTE1_DQS_IO_CONFIG_PULL_UP_OFF_B_MASK 0x20000
 #define SJC16_DDR4_PHY_DQ_BYTE1_DQS_IO_CONFIG_PULL_UP_OFF_B_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_DQS_IO_CONFIG_PULL_UP_OFF_B_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE1_DQS_IO_CONFIG_PULL_UP_OFF_B_SHIFT 17
 #define SJC16_DDR4_PHY_DQ_BYTE1_DQS_IO_CONFIG_PULL_UP_OFF_B_RESETVALUE 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE1_DQS_IO_CONFIG_RX_BIAS_MASK 0x18000
 #define SJC16_DDR4_PHY_DQ_BYTE1_DQS_IO_CONFIG_RX_BIAS_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_DQS_IO_CONFIG_RX_BIAS_BITS 2
 #define SJC16_DDR4_PHY_DQ_BYTE1_DQS_IO_CONFIG_RX_BIAS_SHIFT 15
 #define SJC16_DDR4_PHY_DQ_BYTE1_DQS_IO_CONFIG_RX_BIAS_RESETVALUE 0x3
 #define SJC16_DDR4_PHY_DQ_BYTE1_DQS_IO_CONFIG_PEAK_MASK 0x6000
 #define SJC16_DDR4_PHY_DQ_BYTE1_DQS_IO_CONFIG_PEAK_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_DQS_IO_CONFIG_PEAK_BITS 2
 #define SJC16_DDR4_PHY_DQ_BYTE1_DQS_IO_CONFIG_PEAK_SHIFT 13
 #define SJC16_DDR4_PHY_DQ_BYTE1_DQS_IO_CONFIG_PEAK_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_DQS_IO_CONFIG_DEM_MASK 0x1800
 #define SJC16_DDR4_PHY_DQ_BYTE1_DQS_IO_CONFIG_DEM_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_DQS_IO_CONFIG_DEM_BITS 2
 #define SJC16_DDR4_PHY_DQ_BYTE1_DQS_IO_CONFIG_DEM_SHIFT 11
 #define SJC16_DDR4_PHY_DQ_BYTE1_DQS_IO_CONFIG_DEM_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_DQS_IO_CONFIG_RXENB_MASK 0x400
 #define SJC16_DDR4_PHY_DQ_BYTE1_DQS_IO_CONFIG_RXENB_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_DQS_IO_CONFIG_RXENB_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE1_DQS_IO_CONFIG_RXENB_SHIFT 10
 #define SJC16_DDR4_PHY_DQ_BYTE1_DQS_IO_CONFIG_RXENB_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_DQS_IO_CONFIG_PD_MASK 0x3e0
 #define SJC16_DDR4_PHY_DQ_BYTE1_DQS_IO_CONFIG_PD_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_DQS_IO_CONFIG_PD_BITS 5
 #define SJC16_DDR4_PHY_DQ_BYTE1_DQS_IO_CONFIG_PD_SHIFT 5
 #define SJC16_DDR4_PHY_DQ_BYTE1_DQS_IO_CONFIG_PD_RESETVALUE 0x10
 #define SJC16_DDR4_PHY_DQ_BYTE1_DQS_IO_CONFIG_ND_MASK 0x1f
 #define SJC16_DDR4_PHY_DQ_BYTE1_DQS_IO_CONFIG_ND_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_DQS_IO_CONFIG_ND_BITS 5
 #define SJC16_DDR4_PHY_DQ_BYTE1_DQS_IO_CONFIG_ND_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_DQS_IO_CONFIG_ND_RESETVALUE 0xf
 #define SJC16_DDR4_PHY_DQ_BYTE1_DQS_IO_CONFIG_RESERVED_MASK 0xe0000000
 #define SJC16_DDR4_PHY_DQ_BYTE1_DQS_IO_CONFIG_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_DQS_IO_CONFIG_RESERVED_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE1_DQS_IO_CONFIG_RESERVED_SHIFT 29
 #define SJC16_DDR4_PHY_DQ_BYTE1_DQS_IO_CONFIG_ALL_MASK 0x1fffffff
 #define SJC16_DDR4_PHY_DQ_BYTE1_DQS_IO_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_DQS_IO_CONFIG_ALL_BITS 29
 #define SJC16_DDR4_PHY_DQ_BYTE1_DQS_IO_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_DQS_IO_CONFIG_ALL_MASK 0x1fffffff
 #define SJC16_DDR4_PHY_DQ_BYTE1_DQS_IO_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_DQS_IO_CONFIG_ALL_BITS 29
 #define SJC16_DDR4_PHY_DQ_BYTE1_DQS_IO_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_DQS_IO_CONFIG_DATAMASK 0x1ffbffff
 #define SJC16_DDR4_PHY_DQ_BYTE1_DQS_IO_CONFIG_RDWRMASK 0xe0040000
 #define SJC16_DDR4_PHY_DQ_BYTE1_DQS_IO_CONFIG_RESETVALUE 0x107b820f
 #define SJC16_DDR4_PHY_DQ_BYTE1_VREF_DAC_CONFIG 0x1023c498
 #define SJC16_DDR4_PHY_DQ_BYTE1_VREF_DAC_CONFIG_BASE 0x498
 #define SJC16_DDR4_PHY_DQ_BYTE1_VREF_DAC_CONFIG_DATA_MASK 0xff0000
 #define SJC16_DDR4_PHY_DQ_BYTE1_VREF_DAC_CONFIG_DATA_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_VREF_DAC_CONFIG_DATA_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE1_VREF_DAC_CONFIG_DATA_SHIFT 16
 #define SJC16_DDR4_PHY_DQ_BYTE1_VREF_DAC_CONFIG_DATA_RESETVALUE 0x92
 #define SJC16_DDR4_PHY_DQ_BYTE1_VREF_DAC_CONFIG_CTRL_MASK 0xff
 #define SJC16_DDR4_PHY_DQ_BYTE1_VREF_DAC_CONFIG_CTRL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_VREF_DAC_CONFIG_CTRL_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE1_VREF_DAC_CONFIG_CTRL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_VREF_DAC_CONFIG_CTRL_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE1_VREF_DAC_CONFIG_RESERVED_MASK 0xff000000
 #define SJC16_DDR4_PHY_DQ_BYTE1_VREF_DAC_CONFIG_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_VREF_DAC_CONFIG_RESERVED_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE1_VREF_DAC_CONFIG_RESERVED_SHIFT 24
 #define SJC16_DDR4_PHY_DQ_BYTE1_VREF_DAC_CONFIG_ALL_MASK 0xffffff
 #define SJC16_DDR4_PHY_DQ_BYTE1_VREF_DAC_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_VREF_DAC_CONFIG_ALL_BITS 24
 #define SJC16_DDR4_PHY_DQ_BYTE1_VREF_DAC_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_VREF_DAC_CONFIG_ALL_MASK 0xffffff
 #define SJC16_DDR4_PHY_DQ_BYTE1_VREF_DAC_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_VREF_DAC_CONFIG_ALL_BITS 24
 #define SJC16_DDR4_PHY_DQ_BYTE1_VREF_DAC_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_VREF_DAC_CONFIG_DATAMASK 0x00ff00ff
 #define SJC16_DDR4_PHY_DQ_BYTE1_VREF_DAC_CONFIG_RDWRMASK 0xff00ff00
 #define SJC16_DDR4_PHY_DQ_BYTE1_VREF_DAC_CONFIG_RESETVALUE 0x920000
 #define SJC16_DDR4_PHY_DQ_BYTE1_LDO_R_CONFIG 0x1023c49c
 #define SJC16_DDR4_PHY_DQ_BYTE1_LDO_R_CONFIG_BASE 0x49c
 #define SJC16_DDR4_PHY_DQ_BYTE1_LDO_R_CONFIG_REF_SEL_EXT_MASK 0x2000
 #define SJC16_DDR4_PHY_DQ_BYTE1_LDO_R_CONFIG_REF_SEL_EXT_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_LDO_R_CONFIG_REF_SEL_EXT_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE1_LDO_R_CONFIG_REF_SEL_EXT_SHIFT 13
 #define SJC16_DDR4_PHY_DQ_BYTE1_LDO_R_CONFIG_REF_SEL_EXT_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_LDO_R_CONFIG_REF_EXT_MASK 0x1000
 #define SJC16_DDR4_PHY_DQ_BYTE1_LDO_R_CONFIG_REF_EXT_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_LDO_R_CONFIG_REF_EXT_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE1_LDO_R_CONFIG_REF_EXT_SHIFT 12
 #define SJC16_DDR4_PHY_DQ_BYTE1_LDO_R_CONFIG_REF_EXT_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_LDO_R_CONFIG_PWRDN_MASK 0x200
 #define SJC16_DDR4_PHY_DQ_BYTE1_LDO_R_CONFIG_PWRDN_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_LDO_R_CONFIG_PWRDN_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE1_LDO_R_CONFIG_PWRDN_SHIFT 9
 #define SJC16_DDR4_PHY_DQ_BYTE1_LDO_R_CONFIG_PWRDN_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_LDO_R_CONFIG_CTRL_MASK 0x1f8
 #define SJC16_DDR4_PHY_DQ_BYTE1_LDO_R_CONFIG_CTRL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_LDO_R_CONFIG_CTRL_BITS 6
 #define SJC16_DDR4_PHY_DQ_BYTE1_LDO_R_CONFIG_CTRL_SHIFT 3
 #define SJC16_DDR4_PHY_DQ_BYTE1_LDO_R_CONFIG_CTRL_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_LDO_R_CONFIG_BYPASS_MASK 0x4
 #define SJC16_DDR4_PHY_DQ_BYTE1_LDO_R_CONFIG_BYPASS_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_LDO_R_CONFIG_BYPASS_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE1_LDO_R_CONFIG_BYPASS_SHIFT 2
 #define SJC16_DDR4_PHY_DQ_BYTE1_LDO_R_CONFIG_BYPASS_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_LDO_R_CONFIG_BIAS_CTRL_MASK 0x3
 #define SJC16_DDR4_PHY_DQ_BYTE1_LDO_R_CONFIG_BIAS_CTRL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_LDO_R_CONFIG_BIAS_CTRL_BITS 2
 #define SJC16_DDR4_PHY_DQ_BYTE1_LDO_R_CONFIG_BIAS_CTRL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_LDO_R_CONFIG_BIAS_CTRL_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_LDO_R_CONFIG_RESERVED_MASK 0xffffc000
 #define SJC16_DDR4_PHY_DQ_BYTE1_LDO_R_CONFIG_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_LDO_R_CONFIG_RESERVED_BITS 18
 #define SJC16_DDR4_PHY_DQ_BYTE1_LDO_R_CONFIG_RESERVED_SHIFT 14
 #define SJC16_DDR4_PHY_DQ_BYTE1_LDO_R_CONFIG_ALL_MASK 0x3fff
 #define SJC16_DDR4_PHY_DQ_BYTE1_LDO_R_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_LDO_R_CONFIG_ALL_BITS 14
 #define SJC16_DDR4_PHY_DQ_BYTE1_LDO_R_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_LDO_R_CONFIG_ALL_MASK 0x3fff
 #define SJC16_DDR4_PHY_DQ_BYTE1_LDO_R_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_LDO_R_CONFIG_ALL_BITS 14
 #define SJC16_DDR4_PHY_DQ_BYTE1_LDO_R_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_LDO_R_CONFIG_DATAMASK 0x000033ff
 #define SJC16_DDR4_PHY_DQ_BYTE1_LDO_R_CONFIG_RDWRMASK 0xffffcc00
 #define SJC16_DDR4_PHY_DQ_BYTE1_LDO_R_CONFIG_RESETVALUE 0x0000
 #define SJC16_DDR4_PHY_DQ_BYTE1_LDO_W_CONFIG 0x1023c4a0
 #define SJC16_DDR4_PHY_DQ_BYTE1_LDO_W_CONFIG_BASE 0x4a0
 #define SJC16_DDR4_PHY_DQ_BYTE1_LDO_W_CONFIG_REF_SEL_EXT_MASK 0x2000
 #define SJC16_DDR4_PHY_DQ_BYTE1_LDO_W_CONFIG_REF_SEL_EXT_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_LDO_W_CONFIG_REF_SEL_EXT_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE1_LDO_W_CONFIG_REF_SEL_EXT_SHIFT 13
 #define SJC16_DDR4_PHY_DQ_BYTE1_LDO_W_CONFIG_REF_SEL_EXT_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_LDO_W_CONFIG_REF_EXT_MASK 0x1000
 #define SJC16_DDR4_PHY_DQ_BYTE1_LDO_W_CONFIG_REF_EXT_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_LDO_W_CONFIG_REF_EXT_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE1_LDO_W_CONFIG_REF_EXT_SHIFT 12
 #define SJC16_DDR4_PHY_DQ_BYTE1_LDO_W_CONFIG_REF_EXT_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_LDO_W_CONFIG_PWRDN_MASK 0x200
 #define SJC16_DDR4_PHY_DQ_BYTE1_LDO_W_CONFIG_PWRDN_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_LDO_W_CONFIG_PWRDN_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE1_LDO_W_CONFIG_PWRDN_SHIFT 9
 #define SJC16_DDR4_PHY_DQ_BYTE1_LDO_W_CONFIG_PWRDN_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_LDO_W_CONFIG_CTRL_MASK 0x1f8
 #define SJC16_DDR4_PHY_DQ_BYTE1_LDO_W_CONFIG_CTRL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_LDO_W_CONFIG_CTRL_BITS 6
 #define SJC16_DDR4_PHY_DQ_BYTE1_LDO_W_CONFIG_CTRL_SHIFT 3
 #define SJC16_DDR4_PHY_DQ_BYTE1_LDO_W_CONFIG_CTRL_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_LDO_W_CONFIG_BYPASS_MASK 0x4
 #define SJC16_DDR4_PHY_DQ_BYTE1_LDO_W_CONFIG_BYPASS_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_LDO_W_CONFIG_BYPASS_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE1_LDO_W_CONFIG_BYPASS_SHIFT 2
 #define SJC16_DDR4_PHY_DQ_BYTE1_LDO_W_CONFIG_BYPASS_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_LDO_W_CONFIG_BIAS_CTRL_MASK 0x3
 #define SJC16_DDR4_PHY_DQ_BYTE1_LDO_W_CONFIG_BIAS_CTRL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_LDO_W_CONFIG_BIAS_CTRL_BITS 2
 #define SJC16_DDR4_PHY_DQ_BYTE1_LDO_W_CONFIG_BIAS_CTRL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_LDO_W_CONFIG_BIAS_CTRL_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_LDO_W_CONFIG_RESERVED_MASK 0xffffc000
 #define SJC16_DDR4_PHY_DQ_BYTE1_LDO_W_CONFIG_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_LDO_W_CONFIG_RESERVED_BITS 18
 #define SJC16_DDR4_PHY_DQ_BYTE1_LDO_W_CONFIG_RESERVED_SHIFT 14
 #define SJC16_DDR4_PHY_DQ_BYTE1_LDO_W_CONFIG_ALL_MASK 0x3fff
 #define SJC16_DDR4_PHY_DQ_BYTE1_LDO_W_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_LDO_W_CONFIG_ALL_BITS 14
 #define SJC16_DDR4_PHY_DQ_BYTE1_LDO_W_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_LDO_W_CONFIG_ALL_MASK 0x3fff
 #define SJC16_DDR4_PHY_DQ_BYTE1_LDO_W_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_LDO_W_CONFIG_ALL_BITS 14
 #define SJC16_DDR4_PHY_DQ_BYTE1_LDO_W_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_LDO_W_CONFIG_DATAMASK 0x000033ff
 #define SJC16_DDR4_PHY_DQ_BYTE1_LDO_W_CONFIG_RDWRMASK 0xffffcc00
 #define SJC16_DDR4_PHY_DQ_BYTE1_LDO_W_CONFIG_RESETVALUE 0x0000
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_OPERATION_CONFIG 0x1023c4a4
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_OPERATION_CONFIG_BASE 0x4a4
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_OPERATION_CONFIG_CLEAR_ACTIVITY_STATS_MASK 0x10000000
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_OPERATION_CONFIG_CLEAR_ACTIVITY_STATS_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_OPERATION_CONFIG_CLEAR_ACTIVITY_STATS_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_OPERATION_CONFIG_CLEAR_ACTIVITY_STATS_SHIFT 28
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_OPERATION_CONFIG_CLEAR_ACTIVITY_STATS_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_OPERATION_CONFIG_FIFO_W2R_MIN_DELAY_2_MASK 0x8000000
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_OPERATION_CONFIG_FIFO_W2R_MIN_DELAY_2_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_OPERATION_CONFIG_FIFO_W2R_MIN_DELAY_2_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_OPERATION_CONFIG_FIFO_W2R_MIN_DELAY_2_SHIFT 27
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_OPERATION_CONFIG_FIFO_W2R_MIN_DELAY_2_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_OPERATION_CONFIG_ROLLOVER_MODE_MASK 0x7000000
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_OPERATION_CONFIG_ROLLOVER_MODE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_OPERATION_CONFIG_ROLLOVER_MODE_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_OPERATION_CONFIG_ROLLOVER_MODE_SHIFT 24
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_OPERATION_CONFIG_ROLLOVER_MODE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_OPERATION_CONFIG_HALF_RATE_MODE_MASK 0x800000
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_OPERATION_CONFIG_HALF_RATE_MODE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_OPERATION_CONFIG_HALF_RATE_MODE_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_OPERATION_CONFIG_HALF_RATE_MODE_SHIFT 23
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_OPERATION_CONFIG_HALF_RATE_MODE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_OPERATION_CONFIG_INIT_TRACK_OPTIONS_MASK 0x600000
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_OPERATION_CONFIG_INIT_TRACK_OPTIONS_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_OPERATION_CONFIG_INIT_TRACK_OPTIONS_BITS 2
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_OPERATION_CONFIG_INIT_TRACK_OPTIONS_SHIFT 21
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_OPERATION_CONFIG_INIT_TRACK_OPTIONS_RESETVALUE 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_OPERATION_CONFIG_INIT_TRACK_TRANSITION_MASK 0x100000
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_OPERATION_CONFIG_INIT_TRACK_TRANSITION_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_OPERATION_CONFIG_INIT_TRACK_TRANSITION_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_OPERATION_CONFIG_INIT_TRACK_TRANSITION_SHIFT 20
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_OPERATION_CONFIG_INIT_TRACK_TRANSITION_RESETVALUE 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_OPERATION_CONFIG_ACCU_POS_THRESHOLD_MASK 0xff000
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_OPERATION_CONFIG_ACCU_POS_THRESHOLD_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_OPERATION_CONFIG_ACCU_POS_THRESHOLD_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_OPERATION_CONFIG_ACCU_POS_THRESHOLD_SHIFT 12
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_OPERATION_CONFIG_ACCU_POS_THRESHOLD_RESETVALUE 0x10
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_OPERATION_CONFIG_ACCU_LOAD_VALUE_MASK 0xff0
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_OPERATION_CONFIG_ACCU_LOAD_VALUE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_OPERATION_CONFIG_ACCU_LOAD_VALUE_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_OPERATION_CONFIG_ACCU_LOAD_VALUE_SHIFT 4
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_OPERATION_CONFIG_ACCU_LOAD_VALUE_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_OPERATION_CONFIG_ACCU_LOAD_MASK 0x8
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_OPERATION_CONFIG_ACCU_LOAD_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_OPERATION_CONFIG_ACCU_LOAD_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_OPERATION_CONFIG_ACCU_LOAD_SHIFT 3
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_OPERATION_CONFIG_ACCU_LOAD_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_OPERATION_CONFIG_UPDATE_MODE_MASK 0x6
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_OPERATION_CONFIG_UPDATE_MODE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_OPERATION_CONFIG_UPDATE_MODE_BITS 2
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_OPERATION_CONFIG_UPDATE_MODE_SHIFT 1
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_OPERATION_CONFIG_UPDATE_MODE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_OPERATION_CONFIG_ENABLE_MASK 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_OPERATION_CONFIG_ENABLE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_OPERATION_CONFIG_ENABLE_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_OPERATION_CONFIG_ENABLE_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_OPERATION_CONFIG_ENABLE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_OPERATION_CONFIG_RESERVED_MASK 0xe0000000
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_OPERATION_CONFIG_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_OPERATION_CONFIG_RESERVED_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_OPERATION_CONFIG_RESERVED_SHIFT 29
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_OPERATION_CONFIG_ALL_MASK 0x1fffffff
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_OPERATION_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_OPERATION_CONFIG_ALL_BITS 29
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_OPERATION_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_OPERATION_CONFIG_ALL_MASK 0x1fffffff
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_OPERATION_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_OPERATION_CONFIG_ALL_BITS 29
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_OPERATION_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_OPERATION_CONFIG_DATAMASK 0x1fffffff
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_OPERATION_CONFIG_RDWRMASK 0xe0000000
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_OPERATION_CONFIG_RESETVALUE 0x00310000
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_UPDATE_CONFIG 0x1023c4a8
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_UPDATE_CONFIG_BASE 0x4a8
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_UPDATE_CONFIG_ROLLOVER_PHASE_GAP_MASK 0xfc000000
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_UPDATE_CONFIG_ROLLOVER_PHASE_GAP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_UPDATE_CONFIG_ROLLOVER_PHASE_GAP_BITS 6
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_UPDATE_CONFIG_ROLLOVER_PHASE_GAP_SHIFT 26
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_UPDATE_CONFIG_ROLLOVER_PHASE_GAP_RESETVALUE 0x3
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_UPDATE_CONFIG_ROLLOVER_AMOUNT_MASK 0x1ff0000
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_UPDATE_CONFIG_ROLLOVER_AMOUNT_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_UPDATE_CONFIG_ROLLOVER_AMOUNT_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_UPDATE_CONFIG_ROLLOVER_AMOUNT_SHIFT 16
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_UPDATE_CONFIG_ROLLOVER_AMOUNT_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_UPDATE_CONFIG_UPDATE_ENABLE_DELAY_MASK 0x3f00
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_UPDATE_CONFIG_UPDATE_ENABLE_DELAY_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_UPDATE_CONFIG_UPDATE_ENABLE_DELAY_BITS 6
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_UPDATE_CONFIG_UPDATE_ENABLE_DELAY_SHIFT 8
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_UPDATE_CONFIG_UPDATE_ENABLE_DELAY_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_UPDATE_CONFIG_IMMEDIATE_UPDATE_THRESHOLD_MASK 0xf0
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_UPDATE_CONFIG_IMMEDIATE_UPDATE_THRESHOLD_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_UPDATE_CONFIG_IMMEDIATE_UPDATE_THRESHOLD_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_UPDATE_CONFIG_IMMEDIATE_UPDATE_THRESHOLD_SHIFT 4
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_UPDATE_CONFIG_IMMEDIATE_UPDATE_THRESHOLD_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_UPDATE_CONFIG_VDL_UPDATE_GAP_MASK 0xf
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_UPDATE_CONFIG_VDL_UPDATE_GAP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_UPDATE_CONFIG_VDL_UPDATE_GAP_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_UPDATE_CONFIG_VDL_UPDATE_GAP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_UPDATE_CONFIG_VDL_UPDATE_GAP_RESETVALUE 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_UPDATE_CONFIG_ALL_MASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_UPDATE_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_UPDATE_CONFIG_ALL_BITS 32
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_UPDATE_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_UPDATE_CONFIG_ALL_MASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_UPDATE_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_UPDATE_CONFIG_ALL_BITS 32
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_UPDATE_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_UPDATE_CONFIG_DATAMASK 0xfdff3fff
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_UPDATE_CONFIG_RDWRMASK 0x0200c000
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_UPDATE_CONFIG_RESETVALUE 0x0c000001
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_TRACK_CONFIG 0x1023c4ac
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_TRACK_CONFIG_BASE 0x4ac
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_TRACK_CONFIG_SEARCH_ACTIVE_TIMEOUT_MASK 0xf000
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_TRACK_CONFIG_SEARCH_ACTIVE_TIMEOUT_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_TRACK_CONFIG_SEARCH_ACTIVE_TIMEOUT_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_TRACK_CONFIG_SEARCH_ACTIVE_TIMEOUT_SHIFT 12
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_TRACK_CONFIG_SEARCH_ACTIVE_TIMEOUT_RESETVALUE 0xf
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_TRACK_CONFIG_TRACK_ACTIVE_TIMEOUT_MASK 0xf00
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_TRACK_CONFIG_TRACK_ACTIVE_TIMEOUT_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_TRACK_CONFIG_TRACK_ACTIVE_TIMEOUT_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_TRACK_CONFIG_TRACK_ACTIVE_TIMEOUT_SHIFT 8
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_TRACK_CONFIG_TRACK_ACTIVE_TIMEOUT_RESETVALUE 0xf
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_TRACK_CONFIG_ACCU_ACTIVE_TIMEOUT_MASK 0xff
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_TRACK_CONFIG_ACCU_ACTIVE_TIMEOUT_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_TRACK_CONFIG_ACCU_ACTIVE_TIMEOUT_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_TRACK_CONFIG_ACCU_ACTIVE_TIMEOUT_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_TRACK_CONFIG_ACCU_ACTIVE_TIMEOUT_RESETVALUE 0xff
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_TRACK_CONFIG_RESERVED_MASK 0xffff0000
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_TRACK_CONFIG_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_TRACK_CONFIG_RESERVED_BITS 16
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_TRACK_CONFIG_RESERVED_SHIFT 16
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_TRACK_CONFIG_ALL_MASK 0xffff
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_TRACK_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_TRACK_CONFIG_ALL_BITS 16
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_TRACK_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_TRACK_CONFIG_ALL_MASK 0xffff
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_TRACK_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_TRACK_CONFIG_ALL_BITS 16
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_TRACK_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_TRACK_CONFIG_DATAMASK 0x0000ffff
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_TRACK_CONFIG_RDWRMASK 0xffff0000
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_TRACK_CONFIG_RESETVALUE 0xffff
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_TIMING_CONFIG 0x1023c4b0
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_TIMING_CONFIG_BASE 0x4b0
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_TIMING_CONFIG_DATA_VALID_WR2RD_DELAY_LOAD_VALUE_MASK 0xf0000
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_TIMING_CONFIG_DATA_VALID_WR2RD_DELAY_LOAD_VALUE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_TIMING_CONFIG_DATA_VALID_WR2RD_DELAY_LOAD_VALUE_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_TIMING_CONFIG_DATA_VALID_WR2RD_DELAY_LOAD_VALUE_SHIFT 16
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_TIMING_CONFIG_DATA_VALID_WR2RD_DELAY_LOAD_VALUE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_TIMING_CONFIG_EDC_VALID_WR2RD_DELAY_LOAD_VALUE_MASK 0xf000
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_TIMING_CONFIG_EDC_VALID_WR2RD_DELAY_LOAD_VALUE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_TIMING_CONFIG_EDC_VALID_WR2RD_DELAY_LOAD_VALUE_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_TIMING_CONFIG_EDC_VALID_WR2RD_DELAY_LOAD_VALUE_SHIFT 12
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_TIMING_CONFIG_EDC_VALID_WR2RD_DELAY_LOAD_VALUE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_TIMING_CONFIG_DATA_READ_UI_SHIFT_LOAD_VALUE_MASK 0x700
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_TIMING_CONFIG_DATA_READ_UI_SHIFT_LOAD_VALUE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_TIMING_CONFIG_DATA_READ_UI_SHIFT_LOAD_VALUE_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_TIMING_CONFIG_DATA_READ_UI_SHIFT_LOAD_VALUE_SHIFT 8
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_TIMING_CONFIG_DATA_READ_UI_SHIFT_LOAD_VALUE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_TIMING_CONFIG_EDC_READ_UI_SHIFT_LOAD_VALUE_MASK 0x70
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_TIMING_CONFIG_EDC_READ_UI_SHIFT_LOAD_VALUE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_TIMING_CONFIG_EDC_READ_UI_SHIFT_LOAD_VALUE_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_TIMING_CONFIG_EDC_READ_UI_SHIFT_LOAD_VALUE_SHIFT 4
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_TIMING_CONFIG_EDC_READ_UI_SHIFT_LOAD_VALUE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_TIMING_CONFIG_CLEAR_VDL_STATS_ON_ROLLOVER_MASK 0x8
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_TIMING_CONFIG_CLEAR_VDL_STATS_ON_ROLLOVER_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_TIMING_CONFIG_CLEAR_VDL_STATS_ON_ROLLOVER_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_TIMING_CONFIG_CLEAR_VDL_STATS_ON_ROLLOVER_SHIFT 3
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_TIMING_CONFIG_CLEAR_VDL_STATS_ON_ROLLOVER_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_TIMING_CONFIG_CLEAR_VDL_STATS_MASK 0x4
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_TIMING_CONFIG_CLEAR_VDL_STATS_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_TIMING_CONFIG_CLEAR_VDL_STATS_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_TIMING_CONFIG_CLEAR_VDL_STATS_SHIFT 2
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_TIMING_CONFIG_CLEAR_VDL_STATS_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_TIMING_CONFIG_VDL_SWITCH_MASK 0x2
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_TIMING_CONFIG_VDL_SWITCH_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_TIMING_CONFIG_VDL_SWITCH_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_TIMING_CONFIG_VDL_SWITCH_SHIFT 1
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_TIMING_CONFIG_VDL_SWITCH_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_TIMING_CONFIG_VDL_LOAD_MASK 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_TIMING_CONFIG_VDL_LOAD_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_TIMING_CONFIG_VDL_LOAD_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_TIMING_CONFIG_VDL_LOAD_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_TIMING_CONFIG_VDL_LOAD_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_TIMING_CONFIG_RESERVED_0_MASK 0xfff00000
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_TIMING_CONFIG_RESERVED_0_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_TIMING_CONFIG_RESERVED_0_BITS 12
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_TIMING_CONFIG_RESERVED_0_SHIFT 20
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_TIMING_CONFIG_RESERVED_MASK 0xfff00000
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_TIMING_CONFIG_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_TIMING_CONFIG_RESERVED_BITS 12
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_TIMING_CONFIG_RESERVED_SHIFT 20
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_TIMING_CONFIG_ALL_MASK 0xfffff
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_TIMING_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_TIMING_CONFIG_ALL_BITS 20
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_TIMING_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_TIMING_CONFIG_ALL_MASK 0xfffff
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_TIMING_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_TIMING_CONFIG_ALL_BITS 20
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_TIMING_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_TIMING_CONFIG_DATAMASK 0x000ff77f
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_TIMING_CONFIG_RDWRMASK 0xfff00880
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_TIMING_CONFIG_RESETVALUE 0x00000
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_VDL_CAP_CONFIG 0x1023c4b4
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_VDL_CAP_CONFIG_BASE 0x4b4
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_VDL_CAP_CONFIG_FLEXIBLE_VDL_CAP_MASK 0x10000000
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_VDL_CAP_CONFIG_FLEXIBLE_VDL_CAP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_VDL_CAP_CONFIG_FLEXIBLE_VDL_CAP_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_VDL_CAP_CONFIG_FLEXIBLE_VDL_CAP_SHIFT 28
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_VDL_CAP_CONFIG_FLEXIBLE_VDL_CAP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_VDL_CAP_CONFIG_VDL_MAX_VALUE_CAP_MASK 0x1ff0000
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_VDL_CAP_CONFIG_VDL_MAX_VALUE_CAP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_VDL_CAP_CONFIG_VDL_MAX_VALUE_CAP_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_VDL_CAP_CONFIG_VDL_MAX_VALUE_CAP_SHIFT 16
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_VDL_CAP_CONFIG_VDL_MAX_VALUE_CAP_RESETVALUE 0x1ff
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_VDL_CAP_CONFIG_VDL_MIN_VALUE_CAP_MASK 0x1ff
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_VDL_CAP_CONFIG_VDL_MIN_VALUE_CAP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_VDL_CAP_CONFIG_VDL_MIN_VALUE_CAP_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_VDL_CAP_CONFIG_VDL_MIN_VALUE_CAP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_VDL_CAP_CONFIG_VDL_MIN_VALUE_CAP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_VDL_CAP_CONFIG_RESERVED_0_MASK 0xe0000000
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_VDL_CAP_CONFIG_RESERVED_0_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_VDL_CAP_CONFIG_RESERVED_0_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_VDL_CAP_CONFIG_RESERVED_0_SHIFT 29
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_VDL_CAP_CONFIG_RESERVED_1_MASK 0xe000000
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_VDL_CAP_CONFIG_RESERVED_1_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_VDL_CAP_CONFIG_RESERVED_1_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_VDL_CAP_CONFIG_RESERVED_1_SHIFT 25
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_VDL_CAP_CONFIG_RESERVED_2_MASK 0xfe00
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_VDL_CAP_CONFIG_RESERVED_2_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_VDL_CAP_CONFIG_RESERVED_2_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_VDL_CAP_CONFIG_RESERVED_2_SHIFT 9
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_VDL_CAP_CONFIG_RESERVED_MASK 0xe0000000
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_VDL_CAP_CONFIG_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_VDL_CAP_CONFIG_RESERVED_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_VDL_CAP_CONFIG_RESERVED_SHIFT 29
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_VDL_CAP_CONFIG_ALL_MASK 0x1fffffff
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_VDL_CAP_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_VDL_CAP_CONFIG_ALL_BITS 29
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_VDL_CAP_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_VDL_CAP_CONFIG_ALL_MASK 0x1fffffff
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_VDL_CAP_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_VDL_CAP_CONFIG_ALL_BITS 29
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_VDL_CAP_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_VDL_CAP_CONFIG_DATAMASK 0x11ff01ff
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_VDL_CAP_CONFIG_RDWRMASK 0xee00fe00
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_VDL_CAP_CONFIG_RESETVALUE 0x01ff0000
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_P_VDL_CONFIG 0x1023c4b8
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_P_VDL_CONFIG_BASE 0x4b8
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_P_VDL_CONFIG_DP_VDL_LOAD_VALUE_MASK 0x1ff0000
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_P_VDL_CONFIG_DP_VDL_LOAD_VALUE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_P_VDL_CONFIG_DP_VDL_LOAD_VALUE_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_P_VDL_CONFIG_DP_VDL_LOAD_VALUE_SHIFT 16
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_P_VDL_CONFIG_DP_VDL_LOAD_VALUE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_P_VDL_CONFIG_EP_VDL_LOAD_VALUE_MASK 0x1ff
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_P_VDL_CONFIG_EP_VDL_LOAD_VALUE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_P_VDL_CONFIG_EP_VDL_LOAD_VALUE_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_P_VDL_CONFIG_EP_VDL_LOAD_VALUE_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_P_VDL_CONFIG_EP_VDL_LOAD_VALUE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_P_VDL_CONFIG_RESERVED_MASK 0xfe000000
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_P_VDL_CONFIG_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_P_VDL_CONFIG_RESERVED_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_P_VDL_CONFIG_RESERVED_SHIFT 25
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_P_VDL_CONFIG_ALL_MASK 0x1ffffff
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_P_VDL_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_P_VDL_CONFIG_ALL_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_P_VDL_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_P_VDL_CONFIG_ALL_MASK 0x1ffffff
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_P_VDL_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_P_VDL_CONFIG_ALL_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_P_VDL_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_P_VDL_CONFIG_DATAMASK 0x01ff01ff
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_P_VDL_CONFIG_RDWRMASK 0xfe00fe00
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_P_VDL_CONFIG_RESETVALUE 0x0000000
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_N_VDL_CONFIG 0x1023c4bc
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_N_VDL_CONFIG_BASE 0x4bc
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_N_VDL_CONFIG_DN_VDL_LOAD_VALUE_MASK 0x1ff0000
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_N_VDL_CONFIG_DN_VDL_LOAD_VALUE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_N_VDL_CONFIG_DN_VDL_LOAD_VALUE_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_N_VDL_CONFIG_DN_VDL_LOAD_VALUE_SHIFT 16
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_N_VDL_CONFIG_DN_VDL_LOAD_VALUE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_N_VDL_CONFIG_EN_VDL_LOAD_VALUE_MASK 0x1ff
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_N_VDL_CONFIG_EN_VDL_LOAD_VALUE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_N_VDL_CONFIG_EN_VDL_LOAD_VALUE_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_N_VDL_CONFIG_EN_VDL_LOAD_VALUE_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_N_VDL_CONFIG_EN_VDL_LOAD_VALUE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_N_VDL_CONFIG_RESERVED_MASK 0xfe000000
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_N_VDL_CONFIG_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_N_VDL_CONFIG_RESERVED_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_N_VDL_CONFIG_RESERVED_SHIFT 25
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_N_VDL_CONFIG_ALL_MASK 0x1ffffff
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_N_VDL_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_N_VDL_CONFIG_ALL_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_N_VDL_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_N_VDL_CONFIG_ALL_MASK 0x1ffffff
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_N_VDL_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_N_VDL_CONFIG_ALL_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_N_VDL_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_N_VDL_CONFIG_DATAMASK 0x01ff01ff
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_N_VDL_CONFIG_RDWRMASK 0xfe00fe00
 #define SJC16_DDR4_PHY_DQ_BYTE1_CDR_N_VDL_CONFIG_RESETVALUE 0x0000000
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_P_VDL 0x1023c4c0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_P_VDL_BASE 0x4c0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_P_VDL_DP_VDL_VALUE_MASK 0x1ff0000
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_P_VDL_DP_VDL_VALUE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_P_VDL_DP_VDL_VALUE_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_P_VDL_DP_VDL_VALUE_SHIFT 16
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_P_VDL_DP_VDL_VALUE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_P_VDL_EP_VDL_VALUE_MASK 0x1ff
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_P_VDL_EP_VDL_VALUE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_P_VDL_EP_VDL_VALUE_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_P_VDL_EP_VDL_VALUE_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_P_VDL_EP_VDL_VALUE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_P_VDL_RESERVED_MASK 0xfe000000
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_P_VDL_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_P_VDL_RESERVED_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_P_VDL_RESERVED_SHIFT 25
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_P_VDL_ALL_MASK 0x1ffffff
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_P_VDL_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_P_VDL_ALL_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_P_VDL_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_P_VDL_ALL_MASK 0x1ffffff
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_P_VDL_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_P_VDL_ALL_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_P_VDL_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_P_VDL_DATAMASK 0x01ff01ff
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_P_VDL_RDWRMASK 0xfe00fe00
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_P_VDL_RESETVALUE 0x0000000
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_N_VDL 0x1023c4c4
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_N_VDL_BASE 0x4c4
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_N_VDL_DN_VDL_VALUE_MASK 0x1ff0000
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_N_VDL_DN_VDL_VALUE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_N_VDL_DN_VDL_VALUE_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_N_VDL_DN_VDL_VALUE_SHIFT 16
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_N_VDL_DN_VDL_VALUE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_N_VDL_EN_VDL_VALUE_MASK 0x1ff
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_N_VDL_EN_VDL_VALUE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_N_VDL_EN_VDL_VALUE_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_N_VDL_EN_VDL_VALUE_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_N_VDL_EN_VDL_VALUE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_N_VDL_RESERVED_MASK 0xfe000000
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_N_VDL_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_N_VDL_RESERVED_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_N_VDL_RESERVED_SHIFT 25
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_N_VDL_ALL_MASK 0x1ffffff
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_N_VDL_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_N_VDL_ALL_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_N_VDL_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_N_VDL_ALL_MASK 0x1ffffff
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_N_VDL_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_N_VDL_ALL_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_N_VDL_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_N_VDL_DATAMASK 0x01ff01ff
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_N_VDL_RDWRMASK 0xfe00fe00
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_N_VDL_RESETVALUE 0x0000000
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_EP_VDL_STAT 0x1023c4c8
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_EP_VDL_STAT_BASE 0x4c8
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_EP_VDL_STAT_MAX_VDL_VALUE_MASK 0x1ff0000
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_EP_VDL_STAT_MAX_VDL_VALUE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_EP_VDL_STAT_MAX_VDL_VALUE_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_EP_VDL_STAT_MAX_VDL_VALUE_SHIFT 16
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_EP_VDL_STAT_MAX_VDL_VALUE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_EP_VDL_STAT_MIN_VDL_VALUE_MASK 0x1ff
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_EP_VDL_STAT_MIN_VDL_VALUE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_EP_VDL_STAT_MIN_VDL_VALUE_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_EP_VDL_STAT_MIN_VDL_VALUE_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_EP_VDL_STAT_MIN_VDL_VALUE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_EP_VDL_STAT_RESERVED_MASK 0xfe000000
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_EP_VDL_STAT_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_EP_VDL_STAT_RESERVED_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_EP_VDL_STAT_RESERVED_SHIFT 25
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_EP_VDL_STAT_ALL_MASK 0x1ffffff
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_EP_VDL_STAT_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_EP_VDL_STAT_ALL_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_EP_VDL_STAT_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_EP_VDL_STAT_ALL_MASK 0x1ffffff
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_EP_VDL_STAT_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_EP_VDL_STAT_ALL_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_EP_VDL_STAT_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_EP_VDL_STAT_DATAMASK 0x01ff01ff
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_EP_VDL_STAT_RDWRMASK 0xfe00fe00
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_EP_VDL_STAT_RESETVALUE 0x0000000
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_DP_VDL_STAT 0x1023c4cc
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_DP_VDL_STAT_BASE 0x4cc
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_DP_VDL_STAT_MAX_VDL_VALUE_MASK 0x1ff0000
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_DP_VDL_STAT_MAX_VDL_VALUE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_DP_VDL_STAT_MAX_VDL_VALUE_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_DP_VDL_STAT_MAX_VDL_VALUE_SHIFT 16
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_DP_VDL_STAT_MAX_VDL_VALUE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_DP_VDL_STAT_MIN_VDL_VALUE_MASK 0x1ff
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_DP_VDL_STAT_MIN_VDL_VALUE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_DP_VDL_STAT_MIN_VDL_VALUE_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_DP_VDL_STAT_MIN_VDL_VALUE_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_DP_VDL_STAT_MIN_VDL_VALUE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_DP_VDL_STAT_RESERVED_MASK 0xfe000000
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_DP_VDL_STAT_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_DP_VDL_STAT_RESERVED_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_DP_VDL_STAT_RESERVED_SHIFT 25
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_DP_VDL_STAT_ALL_MASK 0x1ffffff
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_DP_VDL_STAT_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_DP_VDL_STAT_ALL_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_DP_VDL_STAT_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_DP_VDL_STAT_ALL_MASK 0x1ffffff
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_DP_VDL_STAT_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_DP_VDL_STAT_ALL_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_DP_VDL_STAT_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_DP_VDL_STAT_DATAMASK 0x01ff01ff
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_DP_VDL_STAT_RDWRMASK 0xfe00fe00
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_DP_VDL_STAT_RESETVALUE 0x0000000
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_EN_VDL_STAT 0x1023c4d0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_EN_VDL_STAT_BASE 0x4d0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_EN_VDL_STAT_MAX_VDL_VALUE_MASK 0x1ff0000
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_EN_VDL_STAT_MAX_VDL_VALUE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_EN_VDL_STAT_MAX_VDL_VALUE_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_EN_VDL_STAT_MAX_VDL_VALUE_SHIFT 16
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_EN_VDL_STAT_MAX_VDL_VALUE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_EN_VDL_STAT_MIN_VDL_VALUE_MASK 0x1ff
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_EN_VDL_STAT_MIN_VDL_VALUE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_EN_VDL_STAT_MIN_VDL_VALUE_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_EN_VDL_STAT_MIN_VDL_VALUE_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_EN_VDL_STAT_MIN_VDL_VALUE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_EN_VDL_STAT_RESERVED_MASK 0xfe000000
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_EN_VDL_STAT_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_EN_VDL_STAT_RESERVED_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_EN_VDL_STAT_RESERVED_SHIFT 25
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_EN_VDL_STAT_ALL_MASK 0x1ffffff
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_EN_VDL_STAT_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_EN_VDL_STAT_ALL_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_EN_VDL_STAT_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_EN_VDL_STAT_ALL_MASK 0x1ffffff
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_EN_VDL_STAT_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_EN_VDL_STAT_ALL_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_EN_VDL_STAT_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_EN_VDL_STAT_DATAMASK 0x01ff01ff
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_EN_VDL_STAT_RDWRMASK 0xfe00fe00
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_EN_VDL_STAT_RESETVALUE 0x0000000
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_DN_VDL_STAT 0x1023c4d4
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_DN_VDL_STAT_BASE 0x4d4
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_DN_VDL_STAT_MAX_VDL_VALUE_MASK 0x1ff0000
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_DN_VDL_STAT_MAX_VDL_VALUE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_DN_VDL_STAT_MAX_VDL_VALUE_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_DN_VDL_STAT_MAX_VDL_VALUE_SHIFT 16
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_DN_VDL_STAT_MAX_VDL_VALUE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_DN_VDL_STAT_MIN_VDL_VALUE_MASK 0x1ff
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_DN_VDL_STAT_MIN_VDL_VALUE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_DN_VDL_STAT_MIN_VDL_VALUE_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_DN_VDL_STAT_MIN_VDL_VALUE_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_DN_VDL_STAT_MIN_VDL_VALUE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_DN_VDL_STAT_RESERVED_MASK 0xfe000000
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_DN_VDL_STAT_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_DN_VDL_STAT_RESERVED_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_DN_VDL_STAT_RESERVED_SHIFT 25
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_DN_VDL_STAT_ALL_MASK 0x1ffffff
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_DN_VDL_STAT_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_DN_VDL_STAT_ALL_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_DN_VDL_STAT_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_DN_VDL_STAT_ALL_MASK 0x1ffffff
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_DN_VDL_STAT_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_DN_VDL_STAT_ALL_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_DN_VDL_STAT_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_DN_VDL_STAT_DATAMASK 0x01ff01ff
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_DN_VDL_STAT_RDWRMASK 0xfe00fe00
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_DN_VDL_STAT_RESETVALUE 0x0000000
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_OPERATION 0x1023c4d8
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_OPERATION_BASE 0x4d8
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_OPERATION_ROLLOVER_OVERFLOW_MASK 0x10000000
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_OPERATION_ROLLOVER_OVERFLOW_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_OPERATION_ROLLOVER_OVERFLOW_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_OPERATION_ROLLOVER_OVERFLOW_SHIFT 28
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_OPERATION_ROLLOVER_OVERFLOW_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_OPERATION_ROLLOVER_COUNT_MASK 0xff00000
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_OPERATION_ROLLOVER_COUNT_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_OPERATION_ROLLOVER_COUNT_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_OPERATION_ROLLOVER_COUNT_SHIFT 20
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_OPERATION_ROLLOVER_COUNT_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_OPERATION_SEARCH_ACTIVE_RETRIGGERED_MASK 0x20000
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_OPERATION_SEARCH_ACTIVE_RETRIGGERED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_OPERATION_SEARCH_ACTIVE_RETRIGGERED_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_OPERATION_SEARCH_ACTIVE_RETRIGGERED_SHIFT 17
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_OPERATION_SEARCH_ACTIVE_RETRIGGERED_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_OPERATION_INIT_SEARCH_COMPLETE_MASK 0x10000
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_OPERATION_INIT_SEARCH_COMPLETE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_OPERATION_INIT_SEARCH_COMPLETE_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_OPERATION_INIT_SEARCH_COMPLETE_SHIFT 16
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_OPERATION_INIT_SEARCH_COMPLETE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_OPERATION_INIT_SEARCH_ACTIVE_MASK 0x8000
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_OPERATION_INIT_SEARCH_ACTIVE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_OPERATION_INIT_SEARCH_ACTIVE_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_OPERATION_INIT_SEARCH_ACTIVE_SHIFT 15
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_OPERATION_INIT_SEARCH_ACTIVE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_OPERATION_TRACK_ACTIVE_LOST_MASK 0x4000
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_OPERATION_TRACK_ACTIVE_LOST_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_OPERATION_TRACK_ACTIVE_LOST_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_OPERATION_TRACK_ACTIVE_LOST_SHIFT 14
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_OPERATION_TRACK_ACTIVE_LOST_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_OPERATION_INIT_TRACK_ACTIVE_MASK 0x2000
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_OPERATION_INIT_TRACK_ACTIVE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_OPERATION_INIT_TRACK_ACTIVE_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_OPERATION_INIT_TRACK_ACTIVE_SHIFT 13
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_OPERATION_INIT_TRACK_ACTIVE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_OPERATION_ACCU_ACTIVE_LOST_MASK 0x1000
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_OPERATION_ACCU_ACTIVE_LOST_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_OPERATION_ACCU_ACTIVE_LOST_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_OPERATION_ACCU_ACTIVE_LOST_SHIFT 12
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_OPERATION_ACCU_ACTIVE_LOST_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_OPERATION_INIT_ACCU_ACTIVE_MASK 0x800
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_OPERATION_INIT_ACCU_ACTIVE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_OPERATION_INIT_ACCU_ACTIVE_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_OPERATION_INIT_ACCU_ACTIVE_SHIFT 11
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_OPERATION_INIT_ACCU_ACTIVE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_OPERATION_SEARCH_ACTIVE_MASK 0x400
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_OPERATION_SEARCH_ACTIVE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_OPERATION_SEARCH_ACTIVE_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_OPERATION_SEARCH_ACTIVE_SHIFT 10
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_OPERATION_SEARCH_ACTIVE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_OPERATION_TRACK_ACTIVE_MASK 0x200
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_OPERATION_TRACK_ACTIVE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_OPERATION_TRACK_ACTIVE_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_OPERATION_TRACK_ACTIVE_SHIFT 9
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_OPERATION_TRACK_ACTIVE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_OPERATION_ACCU_ACTIVE_MASK 0x100
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_OPERATION_ACCU_ACTIVE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_OPERATION_ACCU_ACTIVE_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_OPERATION_ACCU_ACTIVE_SHIFT 8
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_OPERATION_ACCU_ACTIVE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_OPERATION_ACCU_VALUE_MASK 0xff
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_OPERATION_ACCU_VALUE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_OPERATION_ACCU_VALUE_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_OPERATION_ACCU_VALUE_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_OPERATION_ACCU_VALUE_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_OPERATION_RESERVED_MASK 0xe0000000
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_OPERATION_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_OPERATION_RESERVED_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_OPERATION_RESERVED_SHIFT 29
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_OPERATION_ALL_MASK 0x1fffffff
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_OPERATION_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_OPERATION_ALL_BITS 29
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_OPERATION_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_OPERATION_ALL_MASK 0x1fffffff
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_OPERATION_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_OPERATION_ALL_BITS 29
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_OPERATION_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_OPERATION_DATAMASK 0x1ff3ffff
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_OPERATION_RDWRMASK 0xe00c0000
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_OPERATION_RESETVALUE 0x00000000
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_TIMING 0x1023c4dc
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_TIMING_BASE 0x4dc
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_TIMING_DATA_VALID_WR2RD_DELAY_MASK 0xf0000
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_TIMING_DATA_VALID_WR2RD_DELAY_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_TIMING_DATA_VALID_WR2RD_DELAY_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_TIMING_DATA_VALID_WR2RD_DELAY_SHIFT 16
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_TIMING_DATA_VALID_WR2RD_DELAY_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_TIMING_EDC_VALID_WR2RD_DELAY_MASK 0xf000
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_TIMING_EDC_VALID_WR2RD_DELAY_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_TIMING_EDC_VALID_WR2RD_DELAY_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_TIMING_EDC_VALID_WR2RD_DELAY_SHIFT 12
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_TIMING_EDC_VALID_WR2RD_DELAY_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_TIMING_DATA_READ_UI_SHIFT_MASK 0x700
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_TIMING_DATA_READ_UI_SHIFT_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_TIMING_DATA_READ_UI_SHIFT_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_TIMING_DATA_READ_UI_SHIFT_SHIFT 8
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_TIMING_DATA_READ_UI_SHIFT_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_TIMING_EDC_READ_UI_SHIFT_MASK 0x70
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_TIMING_EDC_READ_UI_SHIFT_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_TIMING_EDC_READ_UI_SHIFT_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_TIMING_EDC_READ_UI_SHIFT_SHIFT 4
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_TIMING_EDC_READ_UI_SHIFT_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_TIMING_DATA_VALID_WR2RD_DELAY_DEC_MASK 0x8
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_TIMING_DATA_VALID_WR2RD_DELAY_DEC_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_TIMING_DATA_VALID_WR2RD_DELAY_DEC_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_TIMING_DATA_VALID_WR2RD_DELAY_DEC_SHIFT 3
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_TIMING_DATA_VALID_WR2RD_DELAY_DEC_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_TIMING_DATA_VALID_WR2RD_DELAY_INC_MASK 0x4
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_TIMING_DATA_VALID_WR2RD_DELAY_INC_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_TIMING_DATA_VALID_WR2RD_DELAY_INC_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_TIMING_DATA_VALID_WR2RD_DELAY_INC_SHIFT 2
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_TIMING_DATA_VALID_WR2RD_DELAY_INC_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_TIMING_EDC_VALID_WR2RD_DELAY_DEC_MASK 0x2
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_TIMING_EDC_VALID_WR2RD_DELAY_DEC_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_TIMING_EDC_VALID_WR2RD_DELAY_DEC_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_TIMING_EDC_VALID_WR2RD_DELAY_DEC_SHIFT 1
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_TIMING_EDC_VALID_WR2RD_DELAY_DEC_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_TIMING_EDC_VALID_WR2RD_DELAY_INC_MASK 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_TIMING_EDC_VALID_WR2RD_DELAY_INC_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_TIMING_EDC_VALID_WR2RD_DELAY_INC_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_TIMING_EDC_VALID_WR2RD_DELAY_INC_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_TIMING_EDC_VALID_WR2RD_DELAY_INC_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_TIMING_RESERVED_0_MASK 0xfff00000
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_TIMING_RESERVED_0_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_TIMING_RESERVED_0_BITS 12
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_TIMING_RESERVED_0_SHIFT 20
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_TIMING_RESERVED_MASK 0xfff00000
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_TIMING_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_TIMING_RESERVED_BITS 12
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_TIMING_RESERVED_SHIFT 20
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_TIMING_ALL_MASK 0xfffff
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_TIMING_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_TIMING_ALL_BITS 20
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_TIMING_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_TIMING_ALL_MASK 0xfffff
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_TIMING_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_TIMING_ALL_BITS 20
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_TIMING_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_TIMING_DATAMASK 0x000ff77f
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_TIMING_RDWRMASK 0xfff00880
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_CDR_TIMING_RESETVALUE 0x00000
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_FIFO_PTR 0x1023c4e0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_FIFO_PTR_BASE 0x4e0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_FIFO_PTR_RP_XMSB_MASK 0x20000
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_FIFO_PTR_RP_XMSB_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_FIFO_PTR_RP_XMSB_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_FIFO_PTR_RP_XMSB_SHIFT 17
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_FIFO_PTR_RP_XMSB_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_FIFO_PTR_RP_MASK 0x1f000
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_FIFO_PTR_RP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_FIFO_PTR_RP_BITS 5
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_FIFO_PTR_RP_SHIFT 12
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_FIFO_PTR_RP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_FIFO_PTR_WP1_XMSB_MASK 0x800
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_FIFO_PTR_WP1_XMSB_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_FIFO_PTR_WP1_XMSB_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_FIFO_PTR_WP1_XMSB_SHIFT 11
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_FIFO_PTR_WP1_XMSB_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_FIFO_PTR_WP1_MASK 0x7c0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_FIFO_PTR_WP1_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_FIFO_PTR_WP1_BITS 5
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_FIFO_PTR_WP1_SHIFT 6
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_FIFO_PTR_WP1_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_FIFO_PTR_WP0_XMSB_MASK 0x20
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_FIFO_PTR_WP0_XMSB_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_FIFO_PTR_WP0_XMSB_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_FIFO_PTR_WP0_XMSB_SHIFT 5
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_FIFO_PTR_WP0_XMSB_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_FIFO_PTR_WP0_MASK 0x1f
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_FIFO_PTR_WP0_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_FIFO_PTR_WP0_BITS 5
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_FIFO_PTR_WP0_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_FIFO_PTR_WP0_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_FIFO_PTR_RESERVED_MASK 0xfffc0000
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_FIFO_PTR_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_FIFO_PTR_RESERVED_BITS 14
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_FIFO_PTR_RESERVED_SHIFT 18
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_FIFO_PTR_ALL_MASK 0x3ffff
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_FIFO_PTR_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_FIFO_PTR_ALL_BITS 18
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_FIFO_PTR_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_FIFO_PTR_ALL_MASK 0x3ffff
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_FIFO_PTR_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_FIFO_PTR_ALL_BITS 18
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_FIFO_PTR_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_FIFO_PTR_DATAMASK 0x0003ffff
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_FIFO_PTR_RDWRMASK 0xfffc0000
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_FIFO_PTR_RESETVALUE 0x00000
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_FIFO_CTR 0x1023c4e4
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_FIFO_CTR_BASE 0x4e4
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_FIFO_CTR_MAX_WCOUNT_MASK 0x3f00
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_FIFO_CTR_MAX_WCOUNT_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_FIFO_CTR_MAX_WCOUNT_BITS 6
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_FIFO_CTR_MAX_WCOUNT_SHIFT 8
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_FIFO_CTR_MAX_WCOUNT_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_FIFO_CTR_CUR_WCOUNT_MASK 0xfc
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_FIFO_CTR_CUR_WCOUNT_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_FIFO_CTR_CUR_WCOUNT_BITS 6
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_FIFO_CTR_CUR_WCOUNT_SHIFT 2
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_FIFO_CTR_CUR_WCOUNT_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_FIFO_CTR_WFULL_MASK 0x2
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_FIFO_CTR_WFULL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_FIFO_CTR_WFULL_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_FIFO_CTR_WFULL_SHIFT 1
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_FIFO_CTR_WFULL_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_FIFO_CTR_WRITE_ERROR_MASK 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_FIFO_CTR_WRITE_ERROR_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_FIFO_CTR_WRITE_ERROR_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_FIFO_CTR_WRITE_ERROR_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_FIFO_CTR_WRITE_ERROR_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_FIFO_CTR_RESERVED_MASK 0xffffc000
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_FIFO_CTR_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_FIFO_CTR_RESERVED_BITS 18
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_FIFO_CTR_RESERVED_SHIFT 14
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_FIFO_CTR_ALL_MASK 0x3fff
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_FIFO_CTR_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_FIFO_CTR_ALL_BITS 14
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_FIFO_CTR_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_FIFO_CTR_ALL_MASK 0x3fff
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_FIFO_CTR_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_FIFO_CTR_ALL_BITS 14
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_FIFO_CTR_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_FIFO_CTR_DATAMASK 0x00003fff
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_FIFO_CTR_RDWRMASK 0xffffc000
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_FIFO_CTR_RESETVALUE 0x0000
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH 0x1023c4e8
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_BASE 0x4e8
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_PAST_STATE7_MASK 0x7000000
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_PAST_STATE7_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_PAST_STATE7_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_PAST_STATE7_SHIFT 24
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_PAST_STATE7_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_PAST_STATE6_MASK 0xe00000
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_PAST_STATE6_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_PAST_STATE6_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_PAST_STATE6_SHIFT 21
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_PAST_STATE6_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_PAST_STATE5_MASK 0x1c0000
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_PAST_STATE5_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_PAST_STATE5_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_PAST_STATE5_SHIFT 18
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_PAST_STATE5_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_PAST_STATE4_MASK 0x38000
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_PAST_STATE4_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_PAST_STATE4_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_PAST_STATE4_SHIFT 15
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_PAST_STATE4_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_PAST_STATE3_MASK 0x7000
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_PAST_STATE3_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_PAST_STATE3_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_PAST_STATE3_SHIFT 12
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_PAST_STATE3_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_PAST_STATE2_MASK 0xe00
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_PAST_STATE2_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_PAST_STATE2_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_PAST_STATE2_SHIFT 9
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_PAST_STATE2_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_PAST_STATE1_MASK 0x1c0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_PAST_STATE1_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_PAST_STATE1_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_PAST_STATE1_SHIFT 6
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_PAST_STATE1_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_PAST_STATE0_MASK 0x38
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_PAST_STATE0_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_PAST_STATE0_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_PAST_STATE0_SHIFT 3
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_PAST_STATE0_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_CUR_STATE_MASK 0x7
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_CUR_STATE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_CUR_STATE_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_CUR_STATE_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_CUR_STATE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_RESERVED_MASK 0xf8000000
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_RESERVED_BITS 5
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_RESERVED_SHIFT 27
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_ALL_MASK 0x7ffffff
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_ALL_BITS 27
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_ALL_MASK 0x7ffffff
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_ALL_BITS 27
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_DATAMASK 0x07ffffff
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_RDWRMASK 0xf8000000
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_RESETVALUE 0x0000000
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_ERR1 0x1023c4ec
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_ERR1_BASE 0x4ec
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_ERR1_RCMD_FIFO_RD_MASK 0x1000
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_ERR1_RCMD_FIFO_RD_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_ERR1_RCMD_FIFO_RD_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_ERR1_RCMD_FIFO_RD_SHIFT 12
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_ERR1_RCMD_FIFO_RD_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_ERR1_RCMD_FIFO_RDATA_MASK 0xff0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_ERR1_RCMD_FIFO_RDATA_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_ERR1_RCMD_FIFO_RDATA_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_ERR1_RCMD_FIFO_RDATA_SHIFT 4
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_ERR1_RCMD_FIFO_RDATA_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_ERR1_STATE_MASK 0xe
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_ERR1_STATE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_ERR1_STATE_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_ERR1_STATE_SHIFT 1
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_ERR1_STATE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_ERR1_ERROR_MASK 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_ERR1_ERROR_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_ERR1_ERROR_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_ERR1_ERROR_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_ERR1_ERROR_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_ERR1_RESERVED_MASK 0xffffe000
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_ERR1_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_ERR1_RESERVED_BITS 19
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_ERR1_RESERVED_SHIFT 13
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_ERR1_ALL_MASK 0x1fff
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_ERR1_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_ERR1_ALL_BITS 13
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_ERR1_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_ERR1_ALL_MASK 0x1fff
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_ERR1_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_ERR1_ALL_BITS 13
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_ERR1_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_ERR1_DATAMASK 0x00001fff
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_ERR1_RDWRMASK 0xffffe000
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_ERR1_RESETVALUE 0x0000
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_ERR2 0x1023c4f0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_ERR2_BASE 0x4f0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_ERR2_RCMD_FIFO_RD_MASK 0x1000
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_ERR2_RCMD_FIFO_RD_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_ERR2_RCMD_FIFO_RD_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_ERR2_RCMD_FIFO_RD_SHIFT 12
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_ERR2_RCMD_FIFO_RD_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_ERR2_RCMD_FIFO_RDATA_MASK 0xff0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_ERR2_RCMD_FIFO_RDATA_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_ERR2_RCMD_FIFO_RDATA_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_ERR2_RCMD_FIFO_RDATA_SHIFT 4
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_ERR2_RCMD_FIFO_RDATA_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_ERR2_STATE_MASK 0xe
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_ERR2_STATE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_ERR2_STATE_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_ERR2_STATE_SHIFT 1
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_ERR2_STATE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_ERR2_ERROR_MASK 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_ERR2_ERROR_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_ERR2_ERROR_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_ERR2_ERROR_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_ERR2_ERROR_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_ERR2_RESERVED_MASK 0xffffe000
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_ERR2_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_ERR2_RESERVED_BITS 19
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_ERR2_RESERVED_SHIFT 13
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_ERR2_ALL_MASK 0x1fff
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_ERR2_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_ERR2_ALL_BITS 13
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_ERR2_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_ERR2_ALL_MASK 0x1fff
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_ERR2_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_ERR2_ALL_BITS 13
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_ERR2_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_ERR2_DATAMASK 0x00001fff
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_ERR2_RDWRMASK 0xffffe000
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_ERR2_RESETVALUE 0x0000
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_ERR3 0x1023c4f4
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_ERR3_BASE 0x4f4
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_ERR3_EXP_RCMD_ID_MASK 0xfc00
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_ERR3_EXP_RCMD_ID_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_ERR3_EXP_RCMD_ID_BITS 6
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_ERR3_EXP_RCMD_ID_SHIFT 10
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_ERR3_EXP_RCMD_ID_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_ERR3_OBS_RCMD_ID_MASK 0x3f0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_ERR3_OBS_RCMD_ID_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_ERR3_OBS_RCMD_ID_BITS 6
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_ERR3_OBS_RCMD_ID_SHIFT 4
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_ERR3_OBS_RCMD_ID_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_ERR3_STATE_MASK 0xe
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_ERR3_STATE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_ERR3_STATE_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_ERR3_STATE_SHIFT 1
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_ERR3_STATE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_ERR3_ERROR_MASK 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_ERR3_ERROR_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_ERR3_ERROR_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_ERR3_ERROR_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_ERR3_ERROR_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_ERR3_RESERVED_MASK 0xffff0000
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_ERR3_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_ERR3_RESERVED_BITS 16
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_ERR3_RESERVED_SHIFT 16
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_ERR3_ALL_MASK 0xffff
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_ERR3_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_ERR3_ALL_BITS 16
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_ERR3_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_ERR3_ALL_MASK 0xffff
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_ERR3_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_ERR3_ALL_BITS 16
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_ERR3_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_ERR3_DATAMASK 0x0000ffff
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_ERR3_RDWRMASK 0xffff0000
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_ERR3_RESETVALUE 0x0000
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_RCMD_ID 0x1023c4f8
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_RCMD_ID_BASE 0x4f8
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_RCMD_ID_ID8_MASK 0xfc0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_RCMD_ID_ID8_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_RCMD_ID_ID8_BITS 6
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_RCMD_ID_ID8_SHIFT 6
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_RCMD_ID_ID8_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_RCMD_ID_ID4_MASK 0x3f
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_RCMD_ID_ID4_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_RCMD_ID_ID4_BITS 6
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_RCMD_ID_ID4_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_RCMD_ID_ID4_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_RCMD_ID_RESERVED_MASK 0xfffff000
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_RCMD_ID_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_RCMD_ID_RESERVED_BITS 20
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_RCMD_ID_RESERVED_SHIFT 12
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_RCMD_ID_ALL_MASK 0xfff
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_RCMD_ID_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_RCMD_ID_ALL_BITS 12
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_RCMD_ID_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_RCMD_ID_ALL_MASK 0xfff
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_RCMD_ID_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_RCMD_ID_ALL_BITS 12
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_RCMD_ID_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_RCMD_ID_DATAMASK 0x00000fff
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_RCMD_ID_RDWRMASK 0xfffff000
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_RCMD_ID_RESETVALUE 0x000
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RDATA_FIFO 0x1023c4fc
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RDATA_FIFO_BASE 0x4fc
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RDATA_FIFO_RP1_XMSB_MASK 0x4000
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RDATA_FIFO_RP1_XMSB_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RDATA_FIFO_RP1_XMSB_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RDATA_FIFO_RP1_XMSB_SHIFT 14
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RDATA_FIFO_RP1_XMSB_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RDATA_FIFO_RP1_MASK 0x3c00
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RDATA_FIFO_RP1_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RDATA_FIFO_RP1_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RDATA_FIFO_RP1_SHIFT 10
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RDATA_FIFO_RP1_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RDATA_FIFO_RP0_XMSB_MASK 0x200
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RDATA_FIFO_RP0_XMSB_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RDATA_FIFO_RP0_XMSB_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RDATA_FIFO_RP0_XMSB_SHIFT 9
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RDATA_FIFO_RP0_XMSB_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RDATA_FIFO_RP0_MASK 0x1e0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RDATA_FIFO_RP0_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RDATA_FIFO_RP0_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RDATA_FIFO_RP0_SHIFT 5
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RDATA_FIFO_RP0_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RDATA_FIFO_WP_XMSB_MASK 0x10
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RDATA_FIFO_WP_XMSB_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RDATA_FIFO_WP_XMSB_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RDATA_FIFO_WP_XMSB_SHIFT 4
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RDATA_FIFO_WP_XMSB_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RDATA_FIFO_WP_MASK 0xf
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RDATA_FIFO_WP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RDATA_FIFO_WP_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RDATA_FIFO_WP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RDATA_FIFO_WP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RDATA_FIFO_RESERVED_MASK 0xffff8000
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RDATA_FIFO_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RDATA_FIFO_RESERVED_BITS 17
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RDATA_FIFO_RESERVED_SHIFT 15
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RDATA_FIFO_ALL_MASK 0x7fff
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RDATA_FIFO_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RDATA_FIFO_ALL_BITS 15
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RDATA_FIFO_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RDATA_FIFO_ALL_MASK 0x7fff
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RDATA_FIFO_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RDATA_FIFO_ALL_BITS 15
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RDATA_FIFO_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RDATA_FIFO_DATAMASK 0x00007fff
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RDATA_FIFO_RDWRMASK 0xffff8000
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RDATA_FIFO_RESETVALUE 0x0000
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_FIFO 0x1023c500
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_FIFO_BASE 0x500
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_FIFO_RP_2G_XMSB_MASK 0x20000
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_FIFO_RP_2G_XMSB_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_FIFO_RP_2G_XMSB_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_FIFO_RP_2G_XMSB_SHIFT 17
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_FIFO_RP_2G_XMSB_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_FIFO_RP_2G_MASK 0x1f000
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_FIFO_RP_2G_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_FIFO_RP_2G_BITS 5
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_FIFO_RP_2G_SHIFT 12
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_FIFO_RP_2G_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_FIFO_RP_1G_XMSB_MASK 0x800
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_FIFO_RP_1G_XMSB_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_FIFO_RP_1G_XMSB_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_FIFO_RP_1G_XMSB_SHIFT 11
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_FIFO_RP_1G_XMSB_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_FIFO_RP_1G_MASK 0x7c0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_FIFO_RP_1G_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_FIFO_RP_1G_BITS 5
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_FIFO_RP_1G_SHIFT 6
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_FIFO_RP_1G_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_FIFO_WP_XMSB_MASK 0x20
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_FIFO_WP_XMSB_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_FIFO_WP_XMSB_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_FIFO_WP_XMSB_SHIFT 5
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_FIFO_WP_XMSB_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_FIFO_WP_MASK 0x1f
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_FIFO_WP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_FIFO_WP_BITS 5
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_FIFO_WP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_FIFO_WP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_FIFO_RESERVED_MASK 0xfffc0000
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_FIFO_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_FIFO_RESERVED_BITS 14
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_FIFO_RESERVED_SHIFT 18
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_FIFO_ALL_MASK 0x3ffff
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_FIFO_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_FIFO_ALL_BITS 18
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_FIFO_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_FIFO_ALL_MASK 0x3ffff
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_FIFO_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_FIFO_ALL_BITS 18
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_FIFO_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_FIFO_DATAMASK 0x0003ffff
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_FIFO_RDWRMASK 0xfffc0000
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_FIFO_RESETVALUE 0x00000
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_RCMD_ID 0x1023c504
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_RCMD_ID_BASE 0x504
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_RCMD_ID_ID8_MASK 0xfc0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_RCMD_ID_ID8_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_RCMD_ID_ID8_BITS 6
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_RCMD_ID_ID8_SHIFT 6
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_RCMD_ID_ID8_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_RCMD_ID_ID4_MASK 0x3f
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_RCMD_ID_ID4_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_RCMD_ID_ID4_BITS 6
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_RCMD_ID_ID4_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_RCMD_ID_ID4_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_RCMD_ID_RESERVED_MASK 0xfffff000
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_RCMD_ID_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_RCMD_ID_RESERVED_BITS 20
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_RCMD_ID_RESERVED_SHIFT 12
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_RCMD_ID_ALL_MASK 0xfff
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_RCMD_ID_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_RCMD_ID_ALL_BITS 12
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_RCMD_ID_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_RCMD_ID_ALL_MASK 0xfff
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_RCMD_ID_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_RCMD_ID_ALL_BITS 12
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_RCMD_ID_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_RCMD_ID_DATAMASK 0x00000fff
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_RCMD_ID_RDWRMASK 0xfffff000
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_RCMD_ID_RESETVALUE 0x000
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_ERR1 0x1023c508
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_ERR1_BASE 0x508
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_ERR1_NXT_RCMD_FIFO_WDATA1_MASK 0x7f800000
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_ERR1_NXT_RCMD_FIFO_WDATA1_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_ERR1_NXT_RCMD_FIFO_WDATA1_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_ERR1_NXT_RCMD_FIFO_WDATA1_SHIFT 23
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_ERR1_NXT_RCMD_FIFO_WDATA1_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_ERR1_NXT_RCMD_FIFO_WDATA0_MASK 0x7f8000
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_ERR1_NXT_RCMD_FIFO_WDATA0_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_ERR1_NXT_RCMD_FIFO_WDATA0_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_ERR1_NXT_RCMD_FIFO_WDATA0_SHIFT 15
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_ERR1_NXT_RCMD_FIFO_WDATA0_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_ERR1_NXT_RCMD_FIFO_WR1_MASK 0x4000
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_ERR1_NXT_RCMD_FIFO_WR1_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_ERR1_NXT_RCMD_FIFO_WR1_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_ERR1_NXT_RCMD_FIFO_WR1_SHIFT 14
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_ERR1_NXT_RCMD_FIFO_WR1_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_ERR1_NXT_RCMD_FIFO_WR0_MASK 0x2000
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_ERR1_NXT_RCMD_FIFO_WR0_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_ERR1_NXT_RCMD_FIFO_WR0_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_ERR1_NXT_RCMD_FIFO_WR0_SHIFT 13
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_ERR1_NXT_RCMD_FIFO_WR0_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_ERR1_NXT_RD_EN_UI23_MASK 0x1000
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_ERR1_NXT_RD_EN_UI23_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_ERR1_NXT_RD_EN_UI23_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_ERR1_NXT_RD_EN_UI23_SHIFT 12
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_ERR1_NXT_RD_EN_UI23_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_ERR1_NXT_RD_EN_UI01_MASK 0x800
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_ERR1_NXT_RD_EN_UI01_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_ERR1_NXT_RD_EN_UI01_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_ERR1_NXT_RD_EN_UI01_SHIFT 11
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_ERR1_NXT_RD_EN_UI01_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_ERR1_NXT_STATE_MASK 0x600
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_ERR1_NXT_STATE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_ERR1_NXT_STATE_BITS 2
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_ERR1_NXT_STATE_SHIFT 9
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_ERR1_NXT_STATE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_ERR1_RCMD_PAIR_MASK 0x1e0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_ERR1_RCMD_PAIR_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_ERR1_RCMD_PAIR_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_ERR1_RCMD_PAIR_SHIFT 5
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_ERR1_RCMD_PAIR_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_ERR1_RD_EN_UI23_MASK 0x10
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_ERR1_RD_EN_UI23_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_ERR1_RD_EN_UI23_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_ERR1_RD_EN_UI23_SHIFT 4
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_ERR1_RD_EN_UI23_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_ERR1_RD_EN_UI01_MASK 0x8
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_ERR1_RD_EN_UI01_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_ERR1_RD_EN_UI01_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_ERR1_RD_EN_UI01_SHIFT 3
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_ERR1_RD_EN_UI01_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_ERR1_STATE_MASK 0x6
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_ERR1_STATE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_ERR1_STATE_BITS 2
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_ERR1_STATE_SHIFT 1
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_ERR1_STATE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_ERR1_ERROR_MASK 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_ERR1_ERROR_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_ERR1_ERROR_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_ERR1_ERROR_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_ERR1_ERROR_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_ERR1_ALL_MASK 0x7fffffff
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_ERR1_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_ERR1_ALL_BITS 31
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_ERR1_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_ERR1_ALL_MASK 0x7fffffff
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_ERR1_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_ERR1_ALL_BITS 31
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_ERR1_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_ERR1_DATAMASK 0x7fffffff
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_ERR1_RDWRMASK 0x80000000
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_ERR1_RESETVALUE 0x00000000
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_ERR2 0x1023c50c
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_ERR2_BASE 0x50c
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_ERR2_NXT_RCMD_FIFO_WDATA1_MASK 0x7f800000
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_ERR2_NXT_RCMD_FIFO_WDATA1_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_ERR2_NXT_RCMD_FIFO_WDATA1_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_ERR2_NXT_RCMD_FIFO_WDATA1_SHIFT 23
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_ERR2_NXT_RCMD_FIFO_WDATA1_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_ERR2_NXT_RCMD_FIFO_WDATA0_MASK 0x7f8000
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_ERR2_NXT_RCMD_FIFO_WDATA0_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_ERR2_NXT_RCMD_FIFO_WDATA0_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_ERR2_NXT_RCMD_FIFO_WDATA0_SHIFT 15
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_ERR2_NXT_RCMD_FIFO_WDATA0_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_ERR2_NXT_RCMD_FIFO_WR1_MASK 0x4000
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_ERR2_NXT_RCMD_FIFO_WR1_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_ERR2_NXT_RCMD_FIFO_WR1_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_ERR2_NXT_RCMD_FIFO_WR1_SHIFT 14
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_ERR2_NXT_RCMD_FIFO_WR1_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_ERR2_NXT_RCMD_FIFO_WR0_MASK 0x2000
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_ERR2_NXT_RCMD_FIFO_WR0_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_ERR2_NXT_RCMD_FIFO_WR0_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_ERR2_NXT_RCMD_FIFO_WR0_SHIFT 13
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_ERR2_NXT_RCMD_FIFO_WR0_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_ERR2_NXT_RD_EN_UI23_MASK 0x1000
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_ERR2_NXT_RD_EN_UI23_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_ERR2_NXT_RD_EN_UI23_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_ERR2_NXT_RD_EN_UI23_SHIFT 12
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_ERR2_NXT_RD_EN_UI23_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_ERR2_NXT_RD_EN_UI01_MASK 0x800
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_ERR2_NXT_RD_EN_UI01_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_ERR2_NXT_RD_EN_UI01_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_ERR2_NXT_RD_EN_UI01_SHIFT 11
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_ERR2_NXT_RD_EN_UI01_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_ERR2_NXT_STATE_MASK 0x600
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_ERR2_NXT_STATE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_ERR2_NXT_STATE_BITS 2
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_ERR2_NXT_STATE_SHIFT 9
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_ERR2_NXT_STATE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_ERR2_RCMD_PAIR_MASK 0x1e0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_ERR2_RCMD_PAIR_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_ERR2_RCMD_PAIR_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_ERR2_RCMD_PAIR_SHIFT 5
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_ERR2_RCMD_PAIR_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_ERR2_RD_EN_UI23_MASK 0x10
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_ERR2_RD_EN_UI23_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_ERR2_RD_EN_UI23_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_ERR2_RD_EN_UI23_SHIFT 4
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_ERR2_RD_EN_UI23_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_ERR2_RD_EN_UI01_MASK 0x8
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_ERR2_RD_EN_UI01_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_ERR2_RD_EN_UI01_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_ERR2_RD_EN_UI01_SHIFT 3
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_ERR2_RD_EN_UI01_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_ERR2_STATE_MASK 0x6
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_ERR2_STATE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_ERR2_STATE_BITS 2
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_ERR2_STATE_SHIFT 1
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_ERR2_STATE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_ERR2_ERROR_MASK 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_ERR2_ERROR_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_ERR2_ERROR_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_ERR2_ERROR_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_ERR2_ERROR_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_ERR2_ALL_MASK 0x7fffffff
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_ERR2_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_ERR2_ALL_BITS 31
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_ERR2_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_ERR2_ALL_MASK 0x7fffffff
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_ERR2_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_ERR2_ALL_BITS 31
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_ERR2_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_ERR2_DATAMASK 0x7fffffff
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_ERR2_RDWRMASK 0x80000000
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_ERR2_RESETVALUE 0x00000000
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_FIFO_POINTERS 0x1023c510
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_FIFO_POINTERS_BASE 0x510
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_FIFO_POINTERS_RDATA_RP_MASK 0xf00000
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_FIFO_POINTERS_RDATA_RP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_FIFO_POINTERS_RDATA_RP_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_FIFO_POINTERS_RDATA_RP_SHIFT 20
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_FIFO_POINTERS_RDATA_RP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_FIFO_POINTERS_RDATA_WP_MASK 0xf0000
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_FIFO_POINTERS_RDATA_WP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_FIFO_POINTERS_RDATA_WP_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_FIFO_POINTERS_RDATA_WP_SHIFT 16
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_FIFO_POINTERS_RDATA_WP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_FIFO_POINTERS_EDC_VALID_RP_MASK 0xf000
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_FIFO_POINTERS_EDC_VALID_RP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_FIFO_POINTERS_EDC_VALID_RP_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_FIFO_POINTERS_EDC_VALID_RP_SHIFT 12
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_FIFO_POINTERS_EDC_VALID_RP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_FIFO_POINTERS_EDC_VALID_WP_MASK 0xf00
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_FIFO_POINTERS_EDC_VALID_WP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_FIFO_POINTERS_EDC_VALID_WP_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_FIFO_POINTERS_EDC_VALID_WP_SHIFT 8
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_FIFO_POINTERS_EDC_VALID_WP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_FIFO_POINTERS_DATA_VALID_RP_MASK 0xf0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_FIFO_POINTERS_DATA_VALID_RP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_FIFO_POINTERS_DATA_VALID_RP_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_FIFO_POINTERS_DATA_VALID_RP_SHIFT 4
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_FIFO_POINTERS_DATA_VALID_RP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_FIFO_POINTERS_DATA_VALID_WP_MASK 0xf
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_FIFO_POINTERS_DATA_VALID_WP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_FIFO_POINTERS_DATA_VALID_WP_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_FIFO_POINTERS_DATA_VALID_WP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_FIFO_POINTERS_DATA_VALID_WP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_FIFO_POINTERS_RESERVED_MASK 0xff000000
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_FIFO_POINTERS_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_FIFO_POINTERS_RESERVED_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_FIFO_POINTERS_RESERVED_SHIFT 24
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_FIFO_POINTERS_ALL_MASK 0xffffff
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_FIFO_POINTERS_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_FIFO_POINTERS_ALL_BITS 24
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_FIFO_POINTERS_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_FIFO_POINTERS_ALL_MASK 0xffffff
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_FIFO_POINTERS_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_FIFO_POINTERS_ALL_BITS 24
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_FIFO_POINTERS_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_FIFO_POINTERS_DATAMASK 0x00ffffff
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_FIFO_POINTERS_RDWRMASK 0xff000000
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_FIFO_POINTERS_RESETVALUE 0x000000
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB 0x1023c514
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_BASE 0x514
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_RCMD_4_MASK 0xff000000
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_RCMD_4_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_RCMD_4_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_RCMD_4_SHIFT 24
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_RCMD_4_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_RCMD_3_MASK 0xff0000
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_RCMD_3_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_RCMD_3_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_RCMD_3_SHIFT 16
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_RCMD_3_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_RCMD_2_MASK 0xff00
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_RCMD_2_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_RCMD_2_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_RCMD_2_SHIFT 8
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_RCMD_2_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_RCMD_1_MASK 0xff
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_RCMD_1_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_RCMD_1_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_RCMD_1_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_RCMD_1_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_ALL_MASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_ALL_BITS 32
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_ALL_MASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_ALL_BITS 32
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_DATAMASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_RDWRMASK 0x00000000
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_RESETVALUE 0x00000000
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB 0x1023c518
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_BASE 0x518
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_RCMD_8_MASK 0xff000000
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_RCMD_8_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_RCMD_8_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_RCMD_8_SHIFT 24
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_RCMD_8_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_RCMD_7_MASK 0xff0000
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_RCMD_7_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_RCMD_7_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_RCMD_7_SHIFT 16
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_RCMD_7_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_RCMD_6_MASK 0xff00
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_RCMD_6_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_RCMD_6_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_RCMD_6_SHIFT 8
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_RCMD_6_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_RCMD_5_MASK 0xff
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_RCMD_5_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_RCMD_5_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_RCMD_5_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_RCMD_5_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_ALL_MASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_ALL_BITS 32
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_ALL_MASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_ALL_BITS 32
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_DATAMASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_RDWRMASK 0x00000000
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_RESETVALUE 0x00000000
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES 0x1023c51c
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_BASE 0x51c
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_7_MASK 0xf0000000
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_7_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_7_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_7_SHIFT 28
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_7_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_6_MASK 0xf000000
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_6_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_6_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_6_SHIFT 24
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_6_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_5_MASK 0xf00000
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_5_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_5_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_5_SHIFT 20
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_5_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_4_MASK 0xf0000
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_4_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_4_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_4_SHIFT 16
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_4_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_3_MASK 0xf000
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_3_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_3_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_3_SHIFT 12
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_3_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_2_MASK 0xf00
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_2_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_2_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_2_SHIFT 8
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_2_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_1_MASK 0xf0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_1_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_1_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_1_SHIFT 4
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_1_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_0_MASK 0xf
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_0_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_0_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_0_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_0_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_ALL_MASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_ALL_BITS 32
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_ALL_MASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_ALL_BITS 32
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_DATAMASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_RDWRMASK 0x00000000
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_RESETVALUE 0x00000000
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS 0x1023c520
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_BASE 0x520
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_7_MASK 0xf0000000
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_7_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_7_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_7_SHIFT 28
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_7_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_6_MASK 0xf000000
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_6_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_6_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_6_SHIFT 24
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_6_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_5_MASK 0xf00000
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_5_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_5_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_5_SHIFT 20
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_5_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_4_MASK 0xf0000
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_4_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_4_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_4_SHIFT 16
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_4_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_3_MASK 0xf000
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_3_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_3_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_3_SHIFT 12
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_3_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_2_MASK 0xf00
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_2_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_2_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_2_SHIFT 8
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_2_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_1_MASK 0xf0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_1_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_1_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_1_SHIFT 4
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_1_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_0_MASK 0xf
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_0_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_0_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_0_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_0_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_ALL_MASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_ALL_BITS 32
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_ALL_MASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_ALL_BITS 32
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_DATAMASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_RDWRMASK 0x00000000
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_RESETVALUE 0x00000000
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR 0x1023c524
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_BASE 0x524
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STICKY_ERROR_MASK 0xf0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STICKY_ERROR_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STICKY_ERROR_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STICKY_ERROR_SHIFT 4
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STICKY_ERROR_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_CURRENT_ERROR_MASK 0xf
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_CURRENT_ERROR_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_CURRENT_ERROR_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_CURRENT_ERROR_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_CURRENT_ERROR_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RESERVED_MASK 0xffffff00
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RESERVED_BITS 24
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RESERVED_SHIFT 8
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_ALL_MASK 0xff
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_ALL_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_ALL_MASK 0xff
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_ALL_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_DATAMASK 0x000000ff
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RDWRMASK 0xffffff00
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB 0x1023c528
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_BASE 0x528
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_RCMD_4_MASK 0xff000000
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_RCMD_4_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_RCMD_4_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_RCMD_4_SHIFT 24
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_RCMD_4_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_RCMD_3_MASK 0xff0000
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_RCMD_3_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_RCMD_3_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_RCMD_3_SHIFT 16
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_RCMD_3_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_RCMD_2_MASK 0xff00
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_RCMD_2_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_RCMD_2_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_RCMD_2_SHIFT 8
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_RCMD_2_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_RCMD_1_MASK 0xff
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_RCMD_1_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_RCMD_1_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_RCMD_1_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_RCMD_1_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_ALL_MASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_ALL_BITS 32
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_ALL_MASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_ALL_BITS 32
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_DATAMASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_RDWRMASK 0x00000000
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_RESETVALUE 0x00000000
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB 0x1023c52c
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_BASE 0x52c
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_RCMD_8_MASK 0xff000000
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_RCMD_8_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_RCMD_8_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_RCMD_8_SHIFT 24
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_RCMD_8_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_RCMD_7_MASK 0xff0000
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_RCMD_7_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_RCMD_7_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_RCMD_7_SHIFT 16
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_RCMD_7_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_RCMD_6_MASK 0xff00
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_RCMD_6_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_RCMD_6_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_RCMD_6_SHIFT 8
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_RCMD_6_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_RCMD_5_MASK 0xff
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_RCMD_5_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_RCMD_5_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_RCMD_5_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_RCMD_5_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_ALL_MASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_ALL_BITS 32
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_ALL_MASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_ALL_BITS 32
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_DATAMASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_RDWRMASK 0x00000000
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_RESETVALUE 0x00000000
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES 0x1023c530
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_BASE 0x530
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_7_MASK 0xf0000000
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_7_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_7_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_7_SHIFT 28
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_7_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_6_MASK 0xf000000
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_6_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_6_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_6_SHIFT 24
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_6_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_5_MASK 0xf00000
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_5_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_5_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_5_SHIFT 20
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_5_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_4_MASK 0xf0000
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_4_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_4_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_4_SHIFT 16
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_4_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_3_MASK 0xf000
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_3_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_3_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_3_SHIFT 12
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_3_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_2_MASK 0xf00
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_2_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_2_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_2_SHIFT 8
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_2_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_1_MASK 0xf0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_1_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_1_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_1_SHIFT 4
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_1_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_0_MASK 0xf
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_0_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_0_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_0_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_0_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_ALL_MASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_ALL_BITS 32
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_ALL_MASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_ALL_BITS 32
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_DATAMASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_RDWRMASK 0x00000000
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_RESETVALUE 0x00000000
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS 0x1023c534
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_BASE 0x534
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_7_MASK 0xf0000000
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_7_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_7_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_7_SHIFT 28
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_7_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_6_MASK 0xf000000
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_6_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_6_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_6_SHIFT 24
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_6_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_5_MASK 0xf00000
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_5_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_5_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_5_SHIFT 20
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_5_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_4_MASK 0xf0000
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_4_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_4_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_4_SHIFT 16
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_4_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_3_MASK 0xf000
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_3_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_3_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_3_SHIFT 12
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_3_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_2_MASK 0xf00
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_2_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_2_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_2_SHIFT 8
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_2_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_1_MASK 0xf0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_1_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_1_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_1_SHIFT 4
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_1_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_0_MASK 0xf
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_0_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_0_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_0_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_0_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_ALL_MASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_ALL_BITS 32
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_ALL_MASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_ALL_BITS 32
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_DATAMASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_RDWRMASK 0x00000000
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_RESETVALUE 0x00000000
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_WRITE_LEVELING 0x1023c538
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_WRITE_LEVELING_BASE 0x538
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_WRITE_LEVELING_DQS_MASK 0x400
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_WRITE_LEVELING_DQS_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_WRITE_LEVELING_DQS_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_WRITE_LEVELING_DQS_SHIFT 10
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_WRITE_LEVELING_DQS_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_WRITE_LEVELING_EDC_MASK 0x200
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_WRITE_LEVELING_EDC_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_WRITE_LEVELING_EDC_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_WRITE_LEVELING_EDC_SHIFT 9
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_WRITE_LEVELING_EDC_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_WRITE_LEVELING_DBI_MASK 0x100
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_WRITE_LEVELING_DBI_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_WRITE_LEVELING_DBI_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_WRITE_LEVELING_DBI_SHIFT 8
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_WRITE_LEVELING_DBI_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_WRITE_LEVELING_DATA_MASK 0xff
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_WRITE_LEVELING_DATA_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_WRITE_LEVELING_DATA_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_WRITE_LEVELING_DATA_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_WRITE_LEVELING_DATA_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_WRITE_LEVELING_RESERVED_MASK 0xfffff800
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_WRITE_LEVELING_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_WRITE_LEVELING_RESERVED_BITS 21
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_WRITE_LEVELING_RESERVED_SHIFT 11
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_WRITE_LEVELING_ALL_MASK 0x7ff
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_WRITE_LEVELING_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_WRITE_LEVELING_ALL_BITS 11
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_WRITE_LEVELING_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_WRITE_LEVELING_ALL_MASK 0x7ff
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_WRITE_LEVELING_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_WRITE_LEVELING_ALL_BITS 11
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_WRITE_LEVELING_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_WRITE_LEVELING_DATAMASK 0x000007ff
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_WRITE_LEVELING_RDWRMASK 0xfffff800
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_WRITE_LEVELING_RESETVALUE 0x000
 #define SJC16_DDR4_PHY_DQ_BYTE1_MACRO_RESERVED_REG 0x1023c53c
 #define SJC16_DDR4_PHY_DQ_BYTE1_MACRO_RESERVED_REG_BASE 0x53c
 #define SJC16_DDR4_PHY_DQ_BYTE1_MACRO_RESERVED_REG_RESERVED_MASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE1_MACRO_RESERVED_REG_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_MACRO_RESERVED_REG_RESERVED_BITS 32
 #define SJC16_DDR4_PHY_DQ_BYTE1_MACRO_RESERVED_REG_RESERVED_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_MACRO_RESERVED_REG_RESERVED_RESETVALUE 0x00000000
 #define SJC16_DDR4_PHY_DQ_BYTE1_MACRO_RESERVED_REG_ALL_MASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE1_MACRO_RESERVED_REG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_MACRO_RESERVED_REG_ALL_BITS 32
 #define SJC16_DDR4_PHY_DQ_BYTE1_MACRO_RESERVED_REG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_MACRO_RESERVED_REG_ALL_MASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE1_MACRO_RESERVED_REG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_MACRO_RESERVED_REG_ALL_BITS 32
 #define SJC16_DDR4_PHY_DQ_BYTE1_MACRO_RESERVED_REG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_MACRO_RESERVED_REG_DATAMASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE1_MACRO_RESERVED_REG_RDWRMASK 0x00000000
 #define SJC16_DDR4_PHY_DQ_BYTE1_MACRO_RESERVED_REG_RESETVALUE 0x00000000
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_MACRO_RESERVED 0x1023c540
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_MACRO_RESERVED_BASE 0x540
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_MACRO_RESERVED_RESERVED_MASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_MACRO_RESERVED_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_MACRO_RESERVED_RESERVED_BITS 32
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_MACRO_RESERVED_RESERVED_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_MACRO_RESERVED_RESERVED_RESETVALUE 0x00000000
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_MACRO_RESERVED_ALL_MASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_MACRO_RESERVED_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_MACRO_RESERVED_ALL_BITS 32
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_MACRO_RESERVED_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_MACRO_RESERVED_ALL_MASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_MACRO_RESERVED_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_MACRO_RESERVED_ALL_BITS 32
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_MACRO_RESERVED_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_MACRO_RESERVED_DATAMASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_MACRO_RESERVED_RDWRMASK 0x00000000
 #define SJC16_DDR4_PHY_DQ_BYTE1_STATUS_MACRO_RESERVED_RESETVALUE 0x00000000
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT0 0x1023c800
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT0_BASE 0x800
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT0_MIN_VDL_STEP_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT0_MIN_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT0_MIN_VDL_STEP_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT0_MIN_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT0_MIN_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT0_RESERVED_MASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT0_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT0_RESERVED_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT0_RESERVED_SHIFT 7
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT0_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT0_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT0_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT0_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT0_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT0_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT0_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT0_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT0_DATAMASK 0x0000007f
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT0_RDWRMASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT0_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT1 0x1023c804
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT1_BASE 0x804
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT1_MIN_VDL_STEP_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT1_MIN_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT1_MIN_VDL_STEP_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT1_MIN_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT1_MIN_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT1_RESERVED_MASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT1_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT1_RESERVED_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT1_RESERVED_SHIFT 7
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT1_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT1_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT1_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT1_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT1_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT1_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT1_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT1_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT1_DATAMASK 0x0000007f
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT1_RDWRMASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT1_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT2 0x1023c808
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT2_BASE 0x808
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT2_MIN_VDL_STEP_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT2_MIN_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT2_MIN_VDL_STEP_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT2_MIN_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT2_MIN_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT2_RESERVED_MASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT2_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT2_RESERVED_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT2_RESERVED_SHIFT 7
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT2_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT2_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT2_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT2_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT2_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT2_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT2_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT2_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT2_DATAMASK 0x0000007f
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT2_RDWRMASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT2_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT3 0x1023c80c
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT3_BASE 0x80c
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT3_MIN_VDL_STEP_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT3_MIN_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT3_MIN_VDL_STEP_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT3_MIN_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT3_MIN_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT3_RESERVED_MASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT3_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT3_RESERVED_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT3_RESERVED_SHIFT 7
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT3_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT3_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT3_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT3_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT3_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT3_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT3_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT3_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT3_DATAMASK 0x0000007f
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT3_RDWRMASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT3_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT4 0x1023c810
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT4_BASE 0x810
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT4_MIN_VDL_STEP_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT4_MIN_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT4_MIN_VDL_STEP_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT4_MIN_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT4_MIN_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT4_RESERVED_MASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT4_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT4_RESERVED_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT4_RESERVED_SHIFT 7
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT4_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT4_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT4_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT4_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT4_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT4_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT4_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT4_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT4_DATAMASK 0x0000007f
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT4_RDWRMASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT4_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT5 0x1023c814
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT5_BASE 0x814
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT5_MIN_VDL_STEP_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT5_MIN_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT5_MIN_VDL_STEP_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT5_MIN_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT5_MIN_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT5_RESERVED_MASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT5_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT5_RESERVED_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT5_RESERVED_SHIFT 7
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT5_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT5_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT5_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT5_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT5_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT5_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT5_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT5_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT5_DATAMASK 0x0000007f
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT5_RDWRMASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT5_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT6 0x1023c818
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT6_BASE 0x818
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT6_MIN_VDL_STEP_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT6_MIN_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT6_MIN_VDL_STEP_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT6_MIN_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT6_MIN_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT6_RESERVED_MASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT6_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT6_RESERVED_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT6_RESERVED_SHIFT 7
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT6_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT6_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT6_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT6_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT6_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT6_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT6_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT6_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT6_DATAMASK 0x0000007f
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT6_RDWRMASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT6_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT7 0x1023c81c
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT7_BASE 0x81c
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT7_MIN_VDL_STEP_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT7_MIN_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT7_MIN_VDL_STEP_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT7_MIN_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT7_MIN_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT7_RESERVED_MASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT7_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT7_RESERVED_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT7_RESERVED_SHIFT 7
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT7_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT7_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT7_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT7_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT7_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT7_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT7_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT7_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT7_DATAMASK 0x0000007f
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT7_RDWRMASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT7_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_DBI 0x1023c820
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_DBI_BASE 0x820
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_DBI_MIN_VDL_STEP_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_DBI_MIN_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_DBI_MIN_VDL_STEP_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_DBI_MIN_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_DBI_MIN_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_DBI_RESERVED_MASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_DBI_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_DBI_RESERVED_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_DBI_RESERVED_SHIFT 7
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_DBI_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_DBI_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_DBI_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_DBI_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_DBI_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_DBI_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_DBI_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_DBI_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_DBI_DATAMASK 0x0000007f
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_DBI_RDWRMASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_DBI_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_EDC 0x1023c824
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_EDC_BASE 0x824
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_EDC_MIN_VDL_STEP_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_EDC_MIN_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_EDC_MIN_VDL_STEP_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_EDC_MIN_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_EDC_MIN_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_EDC_RESERVED_MASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_EDC_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_EDC_RESERVED_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_EDC_RESERVED_SHIFT 7
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_EDC_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_EDC_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_EDC_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_EDC_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_EDC_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_EDC_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_EDC_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_EDC_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_EDC_DATAMASK 0x0000007f
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_EDC_RDWRMASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_EDC_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MAX_VDL_DATA 0x1023c828
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MAX_VDL_DATA_BASE 0x828
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MAX_VDL_DATA_UI_SHIFT_MASK 0xe00
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MAX_VDL_DATA_UI_SHIFT_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MAX_VDL_DATA_UI_SHIFT_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MAX_VDL_DATA_UI_SHIFT_SHIFT 9
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MAX_VDL_DATA_UI_SHIFT_RESETVALUE 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MAX_VDL_DATA_MAX_VDL_STEP_MASK 0x1ff
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MAX_VDL_DATA_MAX_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MAX_VDL_DATA_MAX_VDL_STEP_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MAX_VDL_DATA_MAX_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MAX_VDL_DATA_MAX_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MAX_VDL_DATA_RESERVED_MASK 0xfffff000
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MAX_VDL_DATA_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MAX_VDL_DATA_RESERVED_BITS 20
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MAX_VDL_DATA_RESERVED_SHIFT 12
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MAX_VDL_DATA_ALL_MASK 0xfff
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MAX_VDL_DATA_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MAX_VDL_DATA_ALL_BITS 12
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MAX_VDL_DATA_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MAX_VDL_DATA_ALL_MASK 0xfff
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MAX_VDL_DATA_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MAX_VDL_DATA_ALL_BITS 12
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MAX_VDL_DATA_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MAX_VDL_DATA_DATAMASK 0x00000fff
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MAX_VDL_DATA_RDWRMASK 0xfffff000
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MAX_VDL_DATA_RESETVALUE 0x200
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MAX_VDL_DATA_SHADOW 0x1023c82c
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MAX_VDL_DATA_SHADOW_BASE 0x82c
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MAX_VDL_DATA_SHADOW_UI_SHIFT_MASK 0xe00
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MAX_VDL_DATA_SHADOW_UI_SHIFT_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MAX_VDL_DATA_SHADOW_UI_SHIFT_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MAX_VDL_DATA_SHADOW_UI_SHIFT_SHIFT 9
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MAX_VDL_DATA_SHADOW_UI_SHIFT_RESETVALUE 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MAX_VDL_DATA_SHADOW_MAX_VDL_STEP_MASK 0x1ff
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MAX_VDL_DATA_SHADOW_MAX_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MAX_VDL_DATA_SHADOW_MAX_VDL_STEP_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MAX_VDL_DATA_SHADOW_MAX_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MAX_VDL_DATA_SHADOW_MAX_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MAX_VDL_DATA_SHADOW_RESERVED_MASK 0xfffff000
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MAX_VDL_DATA_SHADOW_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MAX_VDL_DATA_SHADOW_RESERVED_BITS 20
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MAX_VDL_DATA_SHADOW_RESERVED_SHIFT 12
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MAX_VDL_DATA_SHADOW_ALL_MASK 0xfff
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MAX_VDL_DATA_SHADOW_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MAX_VDL_DATA_SHADOW_ALL_BITS 12
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MAX_VDL_DATA_SHADOW_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MAX_VDL_DATA_SHADOW_ALL_MASK 0xfff
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MAX_VDL_DATA_SHADOW_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MAX_VDL_DATA_SHADOW_ALL_BITS 12
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MAX_VDL_DATA_SHADOW_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MAX_VDL_DATA_SHADOW_DATAMASK 0x00000fff
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MAX_VDL_DATA_SHADOW_RDWRMASK 0xfffff000
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MAX_VDL_DATA_SHADOW_RESETVALUE 0x200
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MAX_VDL_DQS 0x1023c830
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MAX_VDL_DQS_BASE 0x830
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MAX_VDL_DQS_UI_SHIFT_MASK 0xe00
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MAX_VDL_DQS_UI_SHIFT_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MAX_VDL_DQS_UI_SHIFT_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MAX_VDL_DQS_UI_SHIFT_SHIFT 9
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MAX_VDL_DQS_UI_SHIFT_RESETVALUE 0x2
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MAX_VDL_DQS_MAX_VDL_STEP_MASK 0x1ff
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MAX_VDL_DQS_MAX_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MAX_VDL_DQS_MAX_VDL_STEP_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MAX_VDL_DQS_MAX_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MAX_VDL_DQS_MAX_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MAX_VDL_DQS_RESERVED_MASK 0xfffff000
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MAX_VDL_DQS_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MAX_VDL_DQS_RESERVED_BITS 20
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MAX_VDL_DQS_RESERVED_SHIFT 12
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MAX_VDL_DQS_ALL_MASK 0xfff
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MAX_VDL_DQS_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MAX_VDL_DQS_ALL_BITS 12
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MAX_VDL_DQS_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MAX_VDL_DQS_ALL_MASK 0xfff
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MAX_VDL_DQS_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MAX_VDL_DQS_ALL_BITS 12
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MAX_VDL_DQS_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MAX_VDL_DQS_DATAMASK 0x00000fff
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MAX_VDL_DQS_RDWRMASK 0xfffff000
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_MAX_VDL_DQS_RESETVALUE 0x400
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT0 0x1023c834
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT0_BASE 0x834
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT0_MIN_VDL_STEP_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT0_MIN_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT0_MIN_VDL_STEP_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT0_MIN_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT0_MIN_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT0_RESERVED_MASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT0_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT0_RESERVED_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT0_RESERVED_SHIFT 7
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT0_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT0_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT0_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT0_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT0_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT0_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT0_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT0_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT0_DATAMASK 0x0000007f
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT0_RDWRMASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT0_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT1 0x1023c838
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT1_BASE 0x838
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT1_MIN_VDL_STEP_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT1_MIN_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT1_MIN_VDL_STEP_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT1_MIN_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT1_MIN_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT1_RESERVED_MASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT1_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT1_RESERVED_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT1_RESERVED_SHIFT 7
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT1_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT1_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT1_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT1_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT1_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT1_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT1_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT1_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT1_DATAMASK 0x0000007f
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT1_RDWRMASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT1_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT2 0x1023c83c
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT2_BASE 0x83c
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT2_MIN_VDL_STEP_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT2_MIN_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT2_MIN_VDL_STEP_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT2_MIN_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT2_MIN_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT2_RESERVED_MASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT2_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT2_RESERVED_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT2_RESERVED_SHIFT 7
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT2_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT2_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT2_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT2_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT2_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT2_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT2_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT2_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT2_DATAMASK 0x0000007f
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT2_RDWRMASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT2_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT3 0x1023c840
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT3_BASE 0x840
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT3_MIN_VDL_STEP_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT3_MIN_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT3_MIN_VDL_STEP_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT3_MIN_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT3_MIN_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT3_RESERVED_MASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT3_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT3_RESERVED_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT3_RESERVED_SHIFT 7
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT3_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT3_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT3_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT3_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT3_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT3_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT3_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT3_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT3_DATAMASK 0x0000007f
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT3_RDWRMASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT3_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT4 0x1023c844
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT4_BASE 0x844
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT4_MIN_VDL_STEP_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT4_MIN_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT4_MIN_VDL_STEP_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT4_MIN_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT4_MIN_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT4_RESERVED_MASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT4_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT4_RESERVED_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT4_RESERVED_SHIFT 7
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT4_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT4_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT4_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT4_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT4_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT4_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT4_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT4_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT4_DATAMASK 0x0000007f
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT4_RDWRMASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT4_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT5 0x1023c848
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT5_BASE 0x848
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT5_MIN_VDL_STEP_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT5_MIN_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT5_MIN_VDL_STEP_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT5_MIN_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT5_MIN_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT5_RESERVED_MASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT5_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT5_RESERVED_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT5_RESERVED_SHIFT 7
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT5_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT5_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT5_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT5_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT5_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT5_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT5_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT5_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT5_DATAMASK 0x0000007f
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT5_RDWRMASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT5_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT6 0x1023c84c
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT6_BASE 0x84c
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT6_MIN_VDL_STEP_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT6_MIN_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT6_MIN_VDL_STEP_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT6_MIN_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT6_MIN_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT6_RESERVED_MASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT6_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT6_RESERVED_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT6_RESERVED_SHIFT 7
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT6_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT6_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT6_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT6_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT6_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT6_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT6_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT6_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT6_DATAMASK 0x0000007f
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT6_RDWRMASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT6_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT7 0x1023c850
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT7_BASE 0x850
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT7_MIN_VDL_STEP_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT7_MIN_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT7_MIN_VDL_STEP_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT7_MIN_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT7_MIN_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT7_RESERVED_MASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT7_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT7_RESERVED_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT7_RESERVED_SHIFT 7
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT7_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT7_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT7_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT7_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT7_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT7_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT7_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT7_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT7_DATAMASK 0x0000007f
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT7_RDWRMASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT7_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_DBI 0x1023c854
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_DBI_BASE 0x854
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_DBI_MIN_VDL_STEP_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_DBI_MIN_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_DBI_MIN_VDL_STEP_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_DBI_MIN_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_DBI_MIN_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_DBI_RESERVED_MASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_DBI_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_DBI_RESERVED_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_DBI_RESERVED_SHIFT 7
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_DBI_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_DBI_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_DBI_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_DBI_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_DBI_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_DBI_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_DBI_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_DBI_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_DBI_DATAMASK 0x0000007f
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_DBI_RDWRMASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_DBI_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_EDC 0x1023c858
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_EDC_BASE 0x858
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_EDC_MIN_VDL_STEP_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_EDC_MIN_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_EDC_MIN_VDL_STEP_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_EDC_MIN_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_EDC_MIN_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_EDC_RESERVED_MASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_EDC_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_EDC_RESERVED_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_EDC_RESERVED_SHIFT 7
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_EDC_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_EDC_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_EDC_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_EDC_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_EDC_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_EDC_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_EDC_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_EDC_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_EDC_DATAMASK 0x0000007f
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_EDC_RDWRMASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_EDC_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQS_MASTER_CTRL 0x1023c85c
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQS_MASTER_CTRL_BASE 0x85c
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQS_MASTER_CTRL_MASTER_MODE_MASK 0x10000
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQS_MASTER_CTRL_MASTER_MODE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQS_MASTER_CTRL_MASTER_MODE_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQS_MASTER_CTRL_MASTER_MODE_SHIFT 16
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQS_MASTER_CTRL_MASTER_MODE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQS_MASTER_CTRL_FORCE_UPDATE_MASK 0x1000
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQS_MASTER_CTRL_FORCE_UPDATE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQS_MASTER_CTRL_FORCE_UPDATE_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQS_MASTER_CTRL_FORCE_UPDATE_SHIFT 12
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQS_MASTER_CTRL_FORCE_UPDATE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQS_MASTER_CTRL_MAX_VDL_STEP_MASK 0x1ff
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQS_MASTER_CTRL_MAX_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQS_MASTER_CTRL_MAX_VDL_STEP_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQS_MASTER_CTRL_MAX_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQS_MASTER_CTRL_MAX_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQS_MASTER_CTRL_RESERVED_0_MASK 0xfffe0000
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQS_MASTER_CTRL_RESERVED_0_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQS_MASTER_CTRL_RESERVED_0_BITS 15
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQS_MASTER_CTRL_RESERVED_0_SHIFT 17
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQS_MASTER_CTRL_RESERVED_1_MASK 0xe000
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQS_MASTER_CTRL_RESERVED_1_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQS_MASTER_CTRL_RESERVED_1_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQS_MASTER_CTRL_RESERVED_1_SHIFT 13
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQS_MASTER_CTRL_RESERVED_2_MASK 0xe00
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQS_MASTER_CTRL_RESERVED_2_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQS_MASTER_CTRL_RESERVED_2_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQS_MASTER_CTRL_RESERVED_2_SHIFT 9
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQS_MASTER_CTRL_RESERVED_MASK 0xfffe0000
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQS_MASTER_CTRL_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQS_MASTER_CTRL_RESERVED_BITS 15
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQS_MASTER_CTRL_RESERVED_SHIFT 17
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQS_MASTER_CTRL_ALL_MASK 0x1ffff
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQS_MASTER_CTRL_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQS_MASTER_CTRL_ALL_BITS 17
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQS_MASTER_CTRL_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQS_MASTER_CTRL_ALL_MASK 0x1ffff
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQS_MASTER_CTRL_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQS_MASTER_CTRL_ALL_BITS 17
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQS_MASTER_CTRL_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQS_MASTER_CTRL_DATAMASK 0x000111ff
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQS_MASTER_CTRL_RDWRMASK 0xfffeee00
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQS_MASTER_CTRL_RESETVALUE 0x00000
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQSEP 0x1023c860
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQSEP_BASE 0x860
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQSEP_MAX_VDL_STEP_MASK 0x1ff
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQSEP_MAX_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQSEP_MAX_VDL_STEP_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQSEP_MAX_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQSEP_MAX_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQSEP_RESERVED_MASK 0xfffffe00
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQSEP_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQSEP_RESERVED_BITS 23
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQSEP_RESERVED_SHIFT 9
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQSEP_ALL_MASK 0x1ff
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQSEP_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQSEP_ALL_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQSEP_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQSEP_ALL_MASK 0x1ff
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQSEP_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQSEP_ALL_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQSEP_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQSEP_DATAMASK 0x000001ff
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQSEP_RDWRMASK 0xfffffe00
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQSEP_RESETVALUE 0x000
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQSDP 0x1023c864
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQSDP_BASE 0x864
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQSDP_MAX_VDL_STEP_MASK 0x1ff
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQSDP_MAX_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQSDP_MAX_VDL_STEP_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQSDP_MAX_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQSDP_MAX_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQSDP_RESERVED_MASK 0xfffffe00
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQSDP_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQSDP_RESERVED_BITS 23
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQSDP_RESERVED_SHIFT 9
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQSDP_ALL_MASK 0x1ff
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQSDP_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQSDP_ALL_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQSDP_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQSDP_ALL_MASK 0x1ff
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQSDP_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQSDP_ALL_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQSDP_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQSDP_DATAMASK 0x000001ff
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQSDP_RDWRMASK 0xfffffe00
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQSDP_RESETVALUE 0x000
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQSEN 0x1023c868
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQSEN_BASE 0x868
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQSEN_MAX_VDL_STEP_MASK 0x1ff
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQSEN_MAX_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQSEN_MAX_VDL_STEP_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQSEN_MAX_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQSEN_MAX_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQSEN_RESERVED_MASK 0xfffffe00
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQSEN_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQSEN_RESERVED_BITS 23
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQSEN_RESERVED_SHIFT 9
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQSEN_ALL_MASK 0x1ff
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQSEN_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQSEN_ALL_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQSEN_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQSEN_ALL_MASK 0x1ff
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQSEN_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQSEN_ALL_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQSEN_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQSEN_DATAMASK 0x000001ff
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQSEN_RDWRMASK 0xfffffe00
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQSEN_RESETVALUE 0x000
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQSDN 0x1023c86c
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQSDN_BASE 0x86c
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQSDN_MAX_VDL_STEP_MASK 0x1ff
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQSDN_MAX_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQSDN_MAX_VDL_STEP_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQSDN_MAX_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQSDN_MAX_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQSDN_RESERVED_MASK 0xfffffe00
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQSDN_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQSDN_RESERVED_BITS 23
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQSDN_RESERVED_SHIFT 9
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQSDN_ALL_MASK 0x1ff
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQSDN_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQSDN_ALL_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQSDN_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQSDN_ALL_MASK 0x1ff
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQSDN_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQSDN_ALL_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQSDN_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQSDN_DATAMASK 0x000001ff
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQSDN_RDWRMASK 0xfffffe00
 #define SJC16_DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQSDN_RESETVALUE 0x000
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_LEVELING_CONFIG 0x1023c870
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_LEVELING_CONFIG_BASE 0x870
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_LEVELING_CONFIG_WRITE_LEVELING_MODE_MASK 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_LEVELING_CONFIG_WRITE_LEVELING_MODE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_LEVELING_CONFIG_WRITE_LEVELING_MODE_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_LEVELING_CONFIG_WRITE_LEVELING_MODE_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_LEVELING_CONFIG_WRITE_LEVELING_MODE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_LEVELING_CONFIG_RESERVED_MASK 0xfffffffe
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_LEVELING_CONFIG_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_LEVELING_CONFIG_RESERVED_BITS 31
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_LEVELING_CONFIG_RESERVED_SHIFT 1
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_LEVELING_CONFIG_WRITE_LEVELING_MODE_MASK 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_LEVELING_CONFIG_WRITE_LEVELING_MODE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_LEVELING_CONFIG_WRITE_LEVELING_MODE_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_LEVELING_CONFIG_WRITE_LEVELING_MODE_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_LEVELING_CONFIG_WRITE_LEVELING_MODE_MASK 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_LEVELING_CONFIG_WRITE_LEVELING_MODE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_LEVELING_CONFIG_WRITE_LEVELING_MODE_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_LEVELING_CONFIG_WRITE_LEVELING_MODE_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_LEVELING_CONFIG_ALL_MASK 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_LEVELING_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_LEVELING_CONFIG_ALL_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_LEVELING_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_LEVELING_CONFIG_ALL_MASK 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_LEVELING_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_LEVELING_CONFIG_ALL_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_LEVELING_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_LEVELING_CONFIG_DATAMASK 0x00000001
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_LEVELING_CONFIG_RDWRMASK 0xfffffffe
 #define SJC16_DDR4_PHY_DQ_BYTE2_WRITE_LEVELING_CONFIG_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_REN_GEN_ERR_CTRL 0x1023c874
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_REN_GEN_ERR_CTRL_BASE 0x874
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_REN_GEN_ERR_CTRL_ERR2_CLEAR_MASK 0x2
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_REN_GEN_ERR_CTRL_ERR2_CLEAR_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_REN_GEN_ERR_CTRL_ERR2_CLEAR_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_REN_GEN_ERR_CTRL_ERR2_CLEAR_SHIFT 1
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_REN_GEN_ERR_CTRL_ERR2_CLEAR_RESETVALUE 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_REN_GEN_ERR_CTRL_ERR1_CLEAR_MASK 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_REN_GEN_ERR_CTRL_ERR1_CLEAR_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_REN_GEN_ERR_CTRL_ERR1_CLEAR_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_REN_GEN_ERR_CTRL_ERR1_CLEAR_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_REN_GEN_ERR_CTRL_ERR1_CLEAR_RESETVALUE 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_REN_GEN_ERR_CTRL_RESERVED_MASK 0xfffffffc
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_REN_GEN_ERR_CTRL_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_REN_GEN_ERR_CTRL_RESERVED_BITS 30
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_REN_GEN_ERR_CTRL_RESERVED_SHIFT 2
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_REN_GEN_ERR_CTRL_ALL_MASK 0x3
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_REN_GEN_ERR_CTRL_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_REN_GEN_ERR_CTRL_ALL_BITS 2
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_REN_GEN_ERR_CTRL_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_REN_GEN_ERR_CTRL_ALL_MASK 0x3
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_REN_GEN_ERR_CTRL_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_REN_GEN_ERR_CTRL_ALL_BITS 2
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_REN_GEN_ERR_CTRL_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_REN_GEN_ERR_CTRL_DATAMASK 0x00000003
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_REN_GEN_ERR_CTRL_RDWRMASK 0xfffffffc
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_REN_GEN_ERR_CTRL_RESETVALUE 0x3
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_REN_FIFO_CONFIG 0x1023c878
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_REN_FIFO_CONFIG_BASE 0x878
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_REN_FIFO_CONFIG_RD_2G_DELAY_DEC_MASK 0x800
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_REN_FIFO_CONFIG_RD_2G_DELAY_DEC_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_REN_FIFO_CONFIG_RD_2G_DELAY_DEC_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_REN_FIFO_CONFIG_RD_2G_DELAY_DEC_SHIFT 11
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_REN_FIFO_CONFIG_RD_2G_DELAY_DEC_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_REN_FIFO_CONFIG_RD_2G_DELAY_INC_MASK 0x400
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_REN_FIFO_CONFIG_RD_2G_DELAY_INC_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_REN_FIFO_CONFIG_RD_2G_DELAY_INC_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_REN_FIFO_CONFIG_RD_2G_DELAY_INC_SHIFT 10
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_REN_FIFO_CONFIG_RD_2G_DELAY_INC_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_REN_FIFO_CONFIG_RD2_2G_DELAY_MASK 0x3e0
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_REN_FIFO_CONFIG_RD2_2G_DELAY_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_REN_FIFO_CONFIG_RD2_2G_DELAY_BITS 5
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_REN_FIFO_CONFIG_RD2_2G_DELAY_SHIFT 5
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_REN_FIFO_CONFIG_RD2_2G_DELAY_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_REN_FIFO_CONFIG_RD_2G_DELAY_MASK 0x1f
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_REN_FIFO_CONFIG_RD_2G_DELAY_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_REN_FIFO_CONFIG_RD_2G_DELAY_BITS 5
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_REN_FIFO_CONFIG_RD_2G_DELAY_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_REN_FIFO_CONFIG_RD_2G_DELAY_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_REN_FIFO_CONFIG_RESERVED_MASK 0xfffff000
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_REN_FIFO_CONFIG_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_REN_FIFO_CONFIG_RESERVED_BITS 20
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_REN_FIFO_CONFIG_RESERVED_SHIFT 12
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_REN_FIFO_CONFIG_ALL_MASK 0xfff
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_REN_FIFO_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_REN_FIFO_CONFIG_ALL_BITS 12
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_REN_FIFO_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_REN_FIFO_CONFIG_ALL_MASK 0xfff
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_REN_FIFO_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_REN_FIFO_CONFIG_ALL_BITS 12
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_REN_FIFO_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_REN_FIFO_CONFIG_DATAMASK 0x00000fff
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_REN_FIFO_CONFIG_RDWRMASK 0xfffff000
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_REN_FIFO_CONFIG_RESETVALUE 0x000
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_REN_STRETCH_CONFIG 0x1023c87c
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_REN_STRETCH_CONFIG_BASE 0x87c
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_REN_STRETCH_CONFIG_A_PLUS_2_MASK 0x20
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_REN_STRETCH_CONFIG_A_PLUS_2_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_REN_STRETCH_CONFIG_A_PLUS_2_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_REN_STRETCH_CONFIG_A_PLUS_2_SHIFT 5
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_REN_STRETCH_CONFIG_A_PLUS_2_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_REN_STRETCH_CONFIG_A_PLUS_1_MASK 0x10
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_REN_STRETCH_CONFIG_A_PLUS_1_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_REN_STRETCH_CONFIG_A_PLUS_1_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_REN_STRETCH_CONFIG_A_PLUS_1_SHIFT 4
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_REN_STRETCH_CONFIG_A_PLUS_1_RESETVALUE 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_REN_STRETCH_CONFIG_A_0_MASK 0x8
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_REN_STRETCH_CONFIG_A_0_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_REN_STRETCH_CONFIG_A_0_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_REN_STRETCH_CONFIG_A_0_SHIFT 3
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_REN_STRETCH_CONFIG_A_0_RESETVALUE 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_REN_STRETCH_CONFIG_A_MINUS_1_MASK 0x4
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_REN_STRETCH_CONFIG_A_MINUS_1_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_REN_STRETCH_CONFIG_A_MINUS_1_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_REN_STRETCH_CONFIG_A_MINUS_1_SHIFT 2
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_REN_STRETCH_CONFIG_A_MINUS_1_RESETVALUE 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_REN_STRETCH_CONFIG_A_MINUS_2_MASK 0x2
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_REN_STRETCH_CONFIG_A_MINUS_2_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_REN_STRETCH_CONFIG_A_MINUS_2_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_REN_STRETCH_CONFIG_A_MINUS_2_SHIFT 1
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_REN_STRETCH_CONFIG_A_MINUS_2_RESETVALUE 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_REN_STRETCH_CONFIG_A_MINUS_3_MASK 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_REN_STRETCH_CONFIG_A_MINUS_3_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_REN_STRETCH_CONFIG_A_MINUS_3_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_REN_STRETCH_CONFIG_A_MINUS_3_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_REN_STRETCH_CONFIG_A_MINUS_3_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_REN_STRETCH_CONFIG_RESERVED_MASK 0xffffffc0
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_REN_STRETCH_CONFIG_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_REN_STRETCH_CONFIG_RESERVED_BITS 26
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_REN_STRETCH_CONFIG_RESERVED_SHIFT 6
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_REN_STRETCH_CONFIG_ALL_MASK 0x3f
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_REN_STRETCH_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_REN_STRETCH_CONFIG_ALL_BITS 6
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_REN_STRETCH_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_REN_STRETCH_CONFIG_ALL_MASK 0x3f
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_REN_STRETCH_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_REN_STRETCH_CONFIG_ALL_BITS 6
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_REN_STRETCH_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_REN_STRETCH_CONFIG_DATAMASK 0x0000003f
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_REN_STRETCH_CONFIG_RDWRMASK 0xffffffc0
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_REN_STRETCH_CONFIG_RESETVALUE 0x1e
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_READ_MAX_VDL_FSM 0x1023c880
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_READ_MAX_VDL_FSM_BASE 0x880
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_READ_MAX_VDL_FSM_MAX_VDL_STEP_MASK 0x1ff
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_READ_MAX_VDL_FSM_MAX_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_READ_MAX_VDL_FSM_MAX_VDL_STEP_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_READ_MAX_VDL_FSM_MAX_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_READ_MAX_VDL_FSM_MAX_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_READ_MAX_VDL_FSM_RESERVED_MASK 0xfffffe00
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_READ_MAX_VDL_FSM_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_READ_MAX_VDL_FSM_RESERVED_BITS 23
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_READ_MAX_VDL_FSM_RESERVED_SHIFT 9
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_READ_MAX_VDL_FSM_ALL_MASK 0x1ff
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_READ_MAX_VDL_FSM_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_READ_MAX_VDL_FSM_ALL_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_READ_MAX_VDL_FSM_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_READ_MAX_VDL_FSM_ALL_MASK 0x1ff
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_READ_MAX_VDL_FSM_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_READ_MAX_VDL_FSM_ALL_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_READ_MAX_VDL_FSM_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_READ_MAX_VDL_FSM_DATAMASK 0x000001ff
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_READ_MAX_VDL_FSM_RDWRMASK 0xfffffe00
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_READ_MAX_VDL_FSM_RESETVALUE 0x000
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_OE_CONFIG 0x1023c884
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_OE_CONFIG_BASE 0x884
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_OE_CONFIG_OE_POST_CYCLES_MASK 0x38
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_OE_CONFIG_OE_POST_CYCLES_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_OE_CONFIG_OE_POST_CYCLES_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_OE_CONFIG_OE_POST_CYCLES_SHIFT 3
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_OE_CONFIG_OE_POST_CYCLES_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_OE_CONFIG_OE_PRE_CYCLES_MASK 0x7
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_OE_CONFIG_OE_PRE_CYCLES_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_OE_CONFIG_OE_PRE_CYCLES_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_OE_CONFIG_OE_PRE_CYCLES_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_OE_CONFIG_OE_PRE_CYCLES_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_OE_CONFIG_RESERVED_MASK 0xffffffc0
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_OE_CONFIG_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_OE_CONFIG_RESERVED_BITS 26
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_OE_CONFIG_RESERVED_SHIFT 6
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_OE_CONFIG_ALL_MASK 0x3f
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_OE_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_OE_CONFIG_ALL_BITS 6
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_OE_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_OE_CONFIG_ALL_MASK 0x3f
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_OE_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_OE_CONFIG_ALL_BITS 6
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_OE_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_OE_CONFIG_DATAMASK 0x0000003f
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_OE_CONFIG_RDWRMASK 0xffffffc0
 #define SJC16_DDR4_PHY_DQ_BYTE2_DDR4_OE_CONFIG_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE2_GDDR5_READ_ALIGNMENT_CTRL 0x1023c888
 #define SJC16_DDR4_PHY_DQ_BYTE2_GDDR5_READ_ALIGNMENT_CTRL_BASE 0x888
 #define SJC16_DDR4_PHY_DQ_BYTE2_GDDR5_READ_ALIGNMENT_CTRL_RDATA_WR2RD_DELAY_DEC_MASK 0x20000000
 #define SJC16_DDR4_PHY_DQ_BYTE2_GDDR5_READ_ALIGNMENT_CTRL_RDATA_WR2RD_DELAY_DEC_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_GDDR5_READ_ALIGNMENT_CTRL_RDATA_WR2RD_DELAY_DEC_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE2_GDDR5_READ_ALIGNMENT_CTRL_RDATA_WR2RD_DELAY_DEC_SHIFT 29
 #define SJC16_DDR4_PHY_DQ_BYTE2_GDDR5_READ_ALIGNMENT_CTRL_RDATA_WR2RD_DELAY_DEC_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_GDDR5_READ_ALIGNMENT_CTRL_RDATA_WR2RD_DELAY_INC_MASK 0x10000000
 #define SJC16_DDR4_PHY_DQ_BYTE2_GDDR5_READ_ALIGNMENT_CTRL_RDATA_WR2RD_DELAY_INC_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_GDDR5_READ_ALIGNMENT_CTRL_RDATA_WR2RD_DELAY_INC_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE2_GDDR5_READ_ALIGNMENT_CTRL_RDATA_WR2RD_DELAY_INC_SHIFT 28
 #define SJC16_DDR4_PHY_DQ_BYTE2_GDDR5_READ_ALIGNMENT_CTRL_RDATA_WR2RD_DELAY_INC_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_GDDR5_READ_ALIGNMENT_CTRL_RDATA_WR2RD_DELAY_MASK 0xf000000
 #define SJC16_DDR4_PHY_DQ_BYTE2_GDDR5_READ_ALIGNMENT_CTRL_RDATA_WR2RD_DELAY_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_GDDR5_READ_ALIGNMENT_CTRL_RDATA_WR2RD_DELAY_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE2_GDDR5_READ_ALIGNMENT_CTRL_RDATA_WR2RD_DELAY_SHIFT 24
 #define SJC16_DDR4_PHY_DQ_BYTE2_GDDR5_READ_ALIGNMENT_CTRL_RDATA_WR2RD_DELAY_RESETVALUE 0x4
 #define SJC16_DDR4_PHY_DQ_BYTE2_GDDR5_READ_ALIGNMENT_CTRL_EDC_HALF_RATE_UI_SELECT_MASK 0x800000
 #define SJC16_DDR4_PHY_DQ_BYTE2_GDDR5_READ_ALIGNMENT_CTRL_EDC_HALF_RATE_UI_SELECT_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_GDDR5_READ_ALIGNMENT_CTRL_EDC_HALF_RATE_UI_SELECT_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE2_GDDR5_READ_ALIGNMENT_CTRL_EDC_HALF_RATE_UI_SELECT_SHIFT 23
 #define SJC16_DDR4_PHY_DQ_BYTE2_GDDR5_READ_ALIGNMENT_CTRL_EDC_HALF_RATE_UI_SELECT_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_GDDR5_READ_ALIGNMENT_CTRL_EDC_HALF_RATE_ENABLE_MASK 0x400000
 #define SJC16_DDR4_PHY_DQ_BYTE2_GDDR5_READ_ALIGNMENT_CTRL_EDC_HALF_RATE_ENABLE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_GDDR5_READ_ALIGNMENT_CTRL_EDC_HALF_RATE_ENABLE_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE2_GDDR5_READ_ALIGNMENT_CTRL_EDC_HALF_RATE_ENABLE_SHIFT 22
 #define SJC16_DDR4_PHY_DQ_BYTE2_GDDR5_READ_ALIGNMENT_CTRL_EDC_HALF_RATE_ENABLE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_GDDR5_READ_ALIGNMENT_CTRL_EDC_VALID_WR2RD_DELAY_DEC_MASK 0x200000
 #define SJC16_DDR4_PHY_DQ_BYTE2_GDDR5_READ_ALIGNMENT_CTRL_EDC_VALID_WR2RD_DELAY_DEC_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_GDDR5_READ_ALIGNMENT_CTRL_EDC_VALID_WR2RD_DELAY_DEC_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE2_GDDR5_READ_ALIGNMENT_CTRL_EDC_VALID_WR2RD_DELAY_DEC_SHIFT 21
 #define SJC16_DDR4_PHY_DQ_BYTE2_GDDR5_READ_ALIGNMENT_CTRL_EDC_VALID_WR2RD_DELAY_DEC_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_GDDR5_READ_ALIGNMENT_CTRL_EDC_VALID_WR2RD_DELAY_INC_MASK 0x100000
 #define SJC16_DDR4_PHY_DQ_BYTE2_GDDR5_READ_ALIGNMENT_CTRL_EDC_VALID_WR2RD_DELAY_INC_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_GDDR5_READ_ALIGNMENT_CTRL_EDC_VALID_WR2RD_DELAY_INC_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE2_GDDR5_READ_ALIGNMENT_CTRL_EDC_VALID_WR2RD_DELAY_INC_SHIFT 20
 #define SJC16_DDR4_PHY_DQ_BYTE2_GDDR5_READ_ALIGNMENT_CTRL_EDC_VALID_WR2RD_DELAY_INC_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_GDDR5_READ_ALIGNMENT_CTRL_EDC_VALID_WR2RD_DELAY_MASK 0xf0000
 #define SJC16_DDR4_PHY_DQ_BYTE2_GDDR5_READ_ALIGNMENT_CTRL_EDC_VALID_WR2RD_DELAY_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_GDDR5_READ_ALIGNMENT_CTRL_EDC_VALID_WR2RD_DELAY_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE2_GDDR5_READ_ALIGNMENT_CTRL_EDC_VALID_WR2RD_DELAY_SHIFT 16
 #define SJC16_DDR4_PHY_DQ_BYTE2_GDDR5_READ_ALIGNMENT_CTRL_EDC_VALID_WR2RD_DELAY_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_GDDR5_READ_ALIGNMENT_CTRL_EDC_UI_SHIFT_MASK 0x7000
 #define SJC16_DDR4_PHY_DQ_BYTE2_GDDR5_READ_ALIGNMENT_CTRL_EDC_UI_SHIFT_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_GDDR5_READ_ALIGNMENT_CTRL_EDC_UI_SHIFT_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE2_GDDR5_READ_ALIGNMENT_CTRL_EDC_UI_SHIFT_SHIFT 12
 #define SJC16_DDR4_PHY_DQ_BYTE2_GDDR5_READ_ALIGNMENT_CTRL_EDC_UI_SHIFT_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_GDDR5_READ_ALIGNMENT_CTRL_DATA_VALID_WR2RD_DELAY_DEC_MASK 0x200
 #define SJC16_DDR4_PHY_DQ_BYTE2_GDDR5_READ_ALIGNMENT_CTRL_DATA_VALID_WR2RD_DELAY_DEC_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_GDDR5_READ_ALIGNMENT_CTRL_DATA_VALID_WR2RD_DELAY_DEC_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE2_GDDR5_READ_ALIGNMENT_CTRL_DATA_VALID_WR2RD_DELAY_DEC_SHIFT 9
 #define SJC16_DDR4_PHY_DQ_BYTE2_GDDR5_READ_ALIGNMENT_CTRL_DATA_VALID_WR2RD_DELAY_DEC_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_GDDR5_READ_ALIGNMENT_CTRL_DATA_VALID_WR2RD_DELAY_INC_MASK 0x100
 #define SJC16_DDR4_PHY_DQ_BYTE2_GDDR5_READ_ALIGNMENT_CTRL_DATA_VALID_WR2RD_DELAY_INC_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_GDDR5_READ_ALIGNMENT_CTRL_DATA_VALID_WR2RD_DELAY_INC_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE2_GDDR5_READ_ALIGNMENT_CTRL_DATA_VALID_WR2RD_DELAY_INC_SHIFT 8
 #define SJC16_DDR4_PHY_DQ_BYTE2_GDDR5_READ_ALIGNMENT_CTRL_DATA_VALID_WR2RD_DELAY_INC_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_GDDR5_READ_ALIGNMENT_CTRL_DATA_VALID_WR2RD_DELAY_MASK 0xf0
 #define SJC16_DDR4_PHY_DQ_BYTE2_GDDR5_READ_ALIGNMENT_CTRL_DATA_VALID_WR2RD_DELAY_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_GDDR5_READ_ALIGNMENT_CTRL_DATA_VALID_WR2RD_DELAY_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE2_GDDR5_READ_ALIGNMENT_CTRL_DATA_VALID_WR2RD_DELAY_SHIFT 4
 #define SJC16_DDR4_PHY_DQ_BYTE2_GDDR5_READ_ALIGNMENT_CTRL_DATA_VALID_WR2RD_DELAY_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_GDDR5_READ_ALIGNMENT_CTRL_DATA_UI_SHIFT_MASK 0x7
 #define SJC16_DDR4_PHY_DQ_BYTE2_GDDR5_READ_ALIGNMENT_CTRL_DATA_UI_SHIFT_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_GDDR5_READ_ALIGNMENT_CTRL_DATA_UI_SHIFT_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE2_GDDR5_READ_ALIGNMENT_CTRL_DATA_UI_SHIFT_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_GDDR5_READ_ALIGNMENT_CTRL_DATA_UI_SHIFT_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_GDDR5_READ_ALIGNMENT_CTRL_RESERVED_0_MASK 0xc0000000
 #define SJC16_DDR4_PHY_DQ_BYTE2_GDDR5_READ_ALIGNMENT_CTRL_RESERVED_0_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_GDDR5_READ_ALIGNMENT_CTRL_RESERVED_0_BITS 2
 #define SJC16_DDR4_PHY_DQ_BYTE2_GDDR5_READ_ALIGNMENT_CTRL_RESERVED_0_SHIFT 30
 #define SJC16_DDR4_PHY_DQ_BYTE2_GDDR5_READ_ALIGNMENT_CTRL_RESERVED_2_MASK 0xc00
 #define SJC16_DDR4_PHY_DQ_BYTE2_GDDR5_READ_ALIGNMENT_CTRL_RESERVED_2_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_GDDR5_READ_ALIGNMENT_CTRL_RESERVED_2_BITS 2
 #define SJC16_DDR4_PHY_DQ_BYTE2_GDDR5_READ_ALIGNMENT_CTRL_RESERVED_2_SHIFT 10
 #define SJC16_DDR4_PHY_DQ_BYTE2_GDDR5_READ_ALIGNMENT_CTRL_RESERVED_MASK 0xc0000000
 #define SJC16_DDR4_PHY_DQ_BYTE2_GDDR5_READ_ALIGNMENT_CTRL_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_GDDR5_READ_ALIGNMENT_CTRL_RESERVED_BITS 2
 #define SJC16_DDR4_PHY_DQ_BYTE2_GDDR5_READ_ALIGNMENT_CTRL_RESERVED_SHIFT 30
 #define SJC16_DDR4_PHY_DQ_BYTE2_GDDR5_READ_ALIGNMENT_CTRL_ALL_MASK 0x3fffffff
 #define SJC16_DDR4_PHY_DQ_BYTE2_GDDR5_READ_ALIGNMENT_CTRL_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_GDDR5_READ_ALIGNMENT_CTRL_ALL_BITS 30
 #define SJC16_DDR4_PHY_DQ_BYTE2_GDDR5_READ_ALIGNMENT_CTRL_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_GDDR5_READ_ALIGNMENT_CTRL_ALL_MASK 0x3fffffff
 #define SJC16_DDR4_PHY_DQ_BYTE2_GDDR5_READ_ALIGNMENT_CTRL_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_GDDR5_READ_ALIGNMENT_CTRL_ALL_BITS 30
 #define SJC16_DDR4_PHY_DQ_BYTE2_GDDR5_READ_ALIGNMENT_CTRL_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_GDDR5_READ_ALIGNMENT_CTRL_DATAMASK 0x3fff73f7
 #define SJC16_DDR4_PHY_DQ_BYTE2_GDDR5_READ_ALIGNMENT_CTRL_RDWRMASK 0xc0008c08
 #define SJC16_DDR4_PHY_DQ_BYTE2_GDDR5_READ_ALIGNMENT_CTRL_RESETVALUE 0x04000000
 #define SJC16_DDR4_PHY_DQ_BYTE2_GDDR5_READ_FSM_CTRL 0x1023c88c
 #define SJC16_DDR4_PHY_DQ_BYTE2_GDDR5_READ_FSM_CTRL_BASE 0x88c
 #define SJC16_DDR4_PHY_DQ_BYTE2_GDDR5_READ_FSM_CTRL_QDR_MODE_MASK 0x8
 #define SJC16_DDR4_PHY_DQ_BYTE2_GDDR5_READ_FSM_CTRL_QDR_MODE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_GDDR5_READ_FSM_CTRL_QDR_MODE_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE2_GDDR5_READ_FSM_CTRL_QDR_MODE_SHIFT 3
 #define SJC16_DDR4_PHY_DQ_BYTE2_GDDR5_READ_FSM_CTRL_QDR_MODE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_GDDR5_READ_FSM_CTRL_DATA_VALID_GEN_ERROR_CLEAR_MASK 0x4
 #define SJC16_DDR4_PHY_DQ_BYTE2_GDDR5_READ_FSM_CTRL_DATA_VALID_GEN_ERROR_CLEAR_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_GDDR5_READ_FSM_CTRL_DATA_VALID_GEN_ERROR_CLEAR_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE2_GDDR5_READ_FSM_CTRL_DATA_VALID_GEN_ERROR_CLEAR_SHIFT 2
 #define SJC16_DDR4_PHY_DQ_BYTE2_GDDR5_READ_FSM_CTRL_DATA_VALID_GEN_ERROR_CLEAR_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_GDDR5_READ_FSM_CTRL_DATA_VALID_GEN_ENABLE_MASK 0x2
 #define SJC16_DDR4_PHY_DQ_BYTE2_GDDR5_READ_FSM_CTRL_DATA_VALID_GEN_ENABLE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_GDDR5_READ_FSM_CTRL_DATA_VALID_GEN_ENABLE_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE2_GDDR5_READ_FSM_CTRL_DATA_VALID_GEN_ENABLE_SHIFT 1
 #define SJC16_DDR4_PHY_DQ_BYTE2_GDDR5_READ_FSM_CTRL_DATA_VALID_GEN_ENABLE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_GDDR5_READ_FSM_CTRL_SYSTEM_ENABLE_MASK 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE2_GDDR5_READ_FSM_CTRL_SYSTEM_ENABLE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_GDDR5_READ_FSM_CTRL_SYSTEM_ENABLE_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE2_GDDR5_READ_FSM_CTRL_SYSTEM_ENABLE_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_GDDR5_READ_FSM_CTRL_SYSTEM_ENABLE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_GDDR5_READ_FSM_CTRL_RESERVED_MASK 0xfffffff0
 #define SJC16_DDR4_PHY_DQ_BYTE2_GDDR5_READ_FSM_CTRL_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_GDDR5_READ_FSM_CTRL_RESERVED_BITS 28
 #define SJC16_DDR4_PHY_DQ_BYTE2_GDDR5_READ_FSM_CTRL_RESERVED_SHIFT 4
 #define SJC16_DDR4_PHY_DQ_BYTE2_GDDR5_READ_FSM_CTRL_ALL_MASK 0xf
 #define SJC16_DDR4_PHY_DQ_BYTE2_GDDR5_READ_FSM_CTRL_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_GDDR5_READ_FSM_CTRL_ALL_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE2_GDDR5_READ_FSM_CTRL_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_GDDR5_READ_FSM_CTRL_ALL_MASK 0xf
 #define SJC16_DDR4_PHY_DQ_BYTE2_GDDR5_READ_FSM_CTRL_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_GDDR5_READ_FSM_CTRL_ALL_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE2_GDDR5_READ_FSM_CTRL_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_GDDR5_READ_FSM_CTRL_DATAMASK 0x0000000f
 #define SJC16_DDR4_PHY_DQ_BYTE2_GDDR5_READ_FSM_CTRL_RDWRMASK 0xfffffff0
 #define SJC16_DDR4_PHY_DQ_BYTE2_GDDR5_READ_FSM_CTRL_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_DATA_IO_CONFIG 0x1023c890
 #define SJC16_DDR4_PHY_DQ_BYTE2_DATA_IO_CONFIG_BASE 0x890
 #define SJC16_DDR4_PHY_DQ_BYTE2_DATA_IO_CONFIG_PTERM_MASK 0x1f000000
 #define SJC16_DDR4_PHY_DQ_BYTE2_DATA_IO_CONFIG_PTERM_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_DATA_IO_CONFIG_PTERM_BITS 5
 #define SJC16_DDR4_PHY_DQ_BYTE2_DATA_IO_CONFIG_PTERM_SHIFT 24
 #define SJC16_DDR4_PHY_DQ_BYTE2_DATA_IO_CONFIG_PTERM_RESETVALUE 0x10
 #define SJC16_DDR4_PHY_DQ_BYTE2_DATA_IO_CONFIG_NTERM_MASK 0xf80000
 #define SJC16_DDR4_PHY_DQ_BYTE2_DATA_IO_CONFIG_NTERM_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_DATA_IO_CONFIG_NTERM_BITS 5
 #define SJC16_DDR4_PHY_DQ_BYTE2_DATA_IO_CONFIG_NTERM_SHIFT 19
 #define SJC16_DDR4_PHY_DQ_BYTE2_DATA_IO_CONFIG_NTERM_RESETVALUE 0xf
 #define SJC16_DDR4_PHY_DQ_BYTE2_DATA_IO_CONFIG_PULL_UP_OFF_B_MASK 0x20000
 #define SJC16_DDR4_PHY_DQ_BYTE2_DATA_IO_CONFIG_PULL_UP_OFF_B_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_DATA_IO_CONFIG_PULL_UP_OFF_B_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE2_DATA_IO_CONFIG_PULL_UP_OFF_B_SHIFT 17
 #define SJC16_DDR4_PHY_DQ_BYTE2_DATA_IO_CONFIG_PULL_UP_OFF_B_RESETVALUE 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE2_DATA_IO_CONFIG_RX_BIAS_MASK 0x18000
 #define SJC16_DDR4_PHY_DQ_BYTE2_DATA_IO_CONFIG_RX_BIAS_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_DATA_IO_CONFIG_RX_BIAS_BITS 2
 #define SJC16_DDR4_PHY_DQ_BYTE2_DATA_IO_CONFIG_RX_BIAS_SHIFT 15
 #define SJC16_DDR4_PHY_DQ_BYTE2_DATA_IO_CONFIG_RX_BIAS_RESETVALUE 0x3
 #define SJC16_DDR4_PHY_DQ_BYTE2_DATA_IO_CONFIG_PEAK_MASK 0x6000
 #define SJC16_DDR4_PHY_DQ_BYTE2_DATA_IO_CONFIG_PEAK_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_DATA_IO_CONFIG_PEAK_BITS 2
 #define SJC16_DDR4_PHY_DQ_BYTE2_DATA_IO_CONFIG_PEAK_SHIFT 13
 #define SJC16_DDR4_PHY_DQ_BYTE2_DATA_IO_CONFIG_PEAK_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_DATA_IO_CONFIG_DEM_MASK 0x1800
 #define SJC16_DDR4_PHY_DQ_BYTE2_DATA_IO_CONFIG_DEM_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_DATA_IO_CONFIG_DEM_BITS 2
 #define SJC16_DDR4_PHY_DQ_BYTE2_DATA_IO_CONFIG_DEM_SHIFT 11
 #define SJC16_DDR4_PHY_DQ_BYTE2_DATA_IO_CONFIG_DEM_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_DATA_IO_CONFIG_RXENB_MASK 0x400
 #define SJC16_DDR4_PHY_DQ_BYTE2_DATA_IO_CONFIG_RXENB_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_DATA_IO_CONFIG_RXENB_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE2_DATA_IO_CONFIG_RXENB_SHIFT 10
 #define SJC16_DDR4_PHY_DQ_BYTE2_DATA_IO_CONFIG_RXENB_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_DATA_IO_CONFIG_PD_MASK 0x3e0
 #define SJC16_DDR4_PHY_DQ_BYTE2_DATA_IO_CONFIG_PD_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_DATA_IO_CONFIG_PD_BITS 5
 #define SJC16_DDR4_PHY_DQ_BYTE2_DATA_IO_CONFIG_PD_SHIFT 5
 #define SJC16_DDR4_PHY_DQ_BYTE2_DATA_IO_CONFIG_PD_RESETVALUE 0x10
 #define SJC16_DDR4_PHY_DQ_BYTE2_DATA_IO_CONFIG_ND_MASK 0x1f
 #define SJC16_DDR4_PHY_DQ_BYTE2_DATA_IO_CONFIG_ND_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_DATA_IO_CONFIG_ND_BITS 5
 #define SJC16_DDR4_PHY_DQ_BYTE2_DATA_IO_CONFIG_ND_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_DATA_IO_CONFIG_ND_RESETVALUE 0xf
 #define SJC16_DDR4_PHY_DQ_BYTE2_DATA_IO_CONFIG_RESERVED_MASK 0xe0000000
 #define SJC16_DDR4_PHY_DQ_BYTE2_DATA_IO_CONFIG_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_DATA_IO_CONFIG_RESERVED_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE2_DATA_IO_CONFIG_RESERVED_SHIFT 29
 #define SJC16_DDR4_PHY_DQ_BYTE2_DATA_IO_CONFIG_ALL_MASK 0x1fffffff
 #define SJC16_DDR4_PHY_DQ_BYTE2_DATA_IO_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_DATA_IO_CONFIG_ALL_BITS 29
 #define SJC16_DDR4_PHY_DQ_BYTE2_DATA_IO_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_DATA_IO_CONFIG_ALL_MASK 0x1fffffff
 #define SJC16_DDR4_PHY_DQ_BYTE2_DATA_IO_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_DATA_IO_CONFIG_ALL_BITS 29
 #define SJC16_DDR4_PHY_DQ_BYTE2_DATA_IO_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_DATA_IO_CONFIG_DATAMASK 0x1ffbffff
 #define SJC16_DDR4_PHY_DQ_BYTE2_DATA_IO_CONFIG_RDWRMASK 0xe0040000
 #define SJC16_DDR4_PHY_DQ_BYTE2_DATA_IO_CONFIG_RESETVALUE 0x107b820f
 #define SJC16_DDR4_PHY_DQ_BYTE2_DQS_IO_CONFIG 0x1023c894
 #define SJC16_DDR4_PHY_DQ_BYTE2_DQS_IO_CONFIG_BASE 0x894
 #define SJC16_DDR4_PHY_DQ_BYTE2_DQS_IO_CONFIG_PTERM_MASK 0x1f000000
 #define SJC16_DDR4_PHY_DQ_BYTE2_DQS_IO_CONFIG_PTERM_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_DQS_IO_CONFIG_PTERM_BITS 5
 #define SJC16_DDR4_PHY_DQ_BYTE2_DQS_IO_CONFIG_PTERM_SHIFT 24
 #define SJC16_DDR4_PHY_DQ_BYTE2_DQS_IO_CONFIG_PTERM_RESETVALUE 0x10
 #define SJC16_DDR4_PHY_DQ_BYTE2_DQS_IO_CONFIG_NTERM_MASK 0xf80000
 #define SJC16_DDR4_PHY_DQ_BYTE2_DQS_IO_CONFIG_NTERM_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_DQS_IO_CONFIG_NTERM_BITS 5
 #define SJC16_DDR4_PHY_DQ_BYTE2_DQS_IO_CONFIG_NTERM_SHIFT 19
 #define SJC16_DDR4_PHY_DQ_BYTE2_DQS_IO_CONFIG_NTERM_RESETVALUE 0xf
 #define SJC16_DDR4_PHY_DQ_BYTE2_DQS_IO_CONFIG_PULL_UP_OFF_B_MASK 0x20000
 #define SJC16_DDR4_PHY_DQ_BYTE2_DQS_IO_CONFIG_PULL_UP_OFF_B_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_DQS_IO_CONFIG_PULL_UP_OFF_B_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE2_DQS_IO_CONFIG_PULL_UP_OFF_B_SHIFT 17
 #define SJC16_DDR4_PHY_DQ_BYTE2_DQS_IO_CONFIG_PULL_UP_OFF_B_RESETVALUE 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE2_DQS_IO_CONFIG_RX_BIAS_MASK 0x18000
 #define SJC16_DDR4_PHY_DQ_BYTE2_DQS_IO_CONFIG_RX_BIAS_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_DQS_IO_CONFIG_RX_BIAS_BITS 2
 #define SJC16_DDR4_PHY_DQ_BYTE2_DQS_IO_CONFIG_RX_BIAS_SHIFT 15
 #define SJC16_DDR4_PHY_DQ_BYTE2_DQS_IO_CONFIG_RX_BIAS_RESETVALUE 0x3
 #define SJC16_DDR4_PHY_DQ_BYTE2_DQS_IO_CONFIG_PEAK_MASK 0x6000
 #define SJC16_DDR4_PHY_DQ_BYTE2_DQS_IO_CONFIG_PEAK_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_DQS_IO_CONFIG_PEAK_BITS 2
 #define SJC16_DDR4_PHY_DQ_BYTE2_DQS_IO_CONFIG_PEAK_SHIFT 13
 #define SJC16_DDR4_PHY_DQ_BYTE2_DQS_IO_CONFIG_PEAK_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_DQS_IO_CONFIG_DEM_MASK 0x1800
 #define SJC16_DDR4_PHY_DQ_BYTE2_DQS_IO_CONFIG_DEM_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_DQS_IO_CONFIG_DEM_BITS 2
 #define SJC16_DDR4_PHY_DQ_BYTE2_DQS_IO_CONFIG_DEM_SHIFT 11
 #define SJC16_DDR4_PHY_DQ_BYTE2_DQS_IO_CONFIG_DEM_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_DQS_IO_CONFIG_RXENB_MASK 0x400
 #define SJC16_DDR4_PHY_DQ_BYTE2_DQS_IO_CONFIG_RXENB_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_DQS_IO_CONFIG_RXENB_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE2_DQS_IO_CONFIG_RXENB_SHIFT 10
 #define SJC16_DDR4_PHY_DQ_BYTE2_DQS_IO_CONFIG_RXENB_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_DQS_IO_CONFIG_PD_MASK 0x3e0
 #define SJC16_DDR4_PHY_DQ_BYTE2_DQS_IO_CONFIG_PD_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_DQS_IO_CONFIG_PD_BITS 5
 #define SJC16_DDR4_PHY_DQ_BYTE2_DQS_IO_CONFIG_PD_SHIFT 5
 #define SJC16_DDR4_PHY_DQ_BYTE2_DQS_IO_CONFIG_PD_RESETVALUE 0x10
 #define SJC16_DDR4_PHY_DQ_BYTE2_DQS_IO_CONFIG_ND_MASK 0x1f
 #define SJC16_DDR4_PHY_DQ_BYTE2_DQS_IO_CONFIG_ND_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_DQS_IO_CONFIG_ND_BITS 5
 #define SJC16_DDR4_PHY_DQ_BYTE2_DQS_IO_CONFIG_ND_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_DQS_IO_CONFIG_ND_RESETVALUE 0xf
 #define SJC16_DDR4_PHY_DQ_BYTE2_DQS_IO_CONFIG_RESERVED_MASK 0xe0000000
 #define SJC16_DDR4_PHY_DQ_BYTE2_DQS_IO_CONFIG_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_DQS_IO_CONFIG_RESERVED_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE2_DQS_IO_CONFIG_RESERVED_SHIFT 29
 #define SJC16_DDR4_PHY_DQ_BYTE2_DQS_IO_CONFIG_ALL_MASK 0x1fffffff
 #define SJC16_DDR4_PHY_DQ_BYTE2_DQS_IO_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_DQS_IO_CONFIG_ALL_BITS 29
 #define SJC16_DDR4_PHY_DQ_BYTE2_DQS_IO_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_DQS_IO_CONFIG_ALL_MASK 0x1fffffff
 #define SJC16_DDR4_PHY_DQ_BYTE2_DQS_IO_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_DQS_IO_CONFIG_ALL_BITS 29
 #define SJC16_DDR4_PHY_DQ_BYTE2_DQS_IO_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_DQS_IO_CONFIG_DATAMASK 0x1ffbffff
 #define SJC16_DDR4_PHY_DQ_BYTE2_DQS_IO_CONFIG_RDWRMASK 0xe0040000
 #define SJC16_DDR4_PHY_DQ_BYTE2_DQS_IO_CONFIG_RESETVALUE 0x107b820f
 #define SJC16_DDR4_PHY_DQ_BYTE2_VREF_DAC_CONFIG 0x1023c898
 #define SJC16_DDR4_PHY_DQ_BYTE2_VREF_DAC_CONFIG_BASE 0x898
 #define SJC16_DDR4_PHY_DQ_BYTE2_VREF_DAC_CONFIG_DATA_MASK 0xff0000
 #define SJC16_DDR4_PHY_DQ_BYTE2_VREF_DAC_CONFIG_DATA_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_VREF_DAC_CONFIG_DATA_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE2_VREF_DAC_CONFIG_DATA_SHIFT 16
 #define SJC16_DDR4_PHY_DQ_BYTE2_VREF_DAC_CONFIG_DATA_RESETVALUE 0x92
 #define SJC16_DDR4_PHY_DQ_BYTE2_VREF_DAC_CONFIG_CTRL_MASK 0xff
 #define SJC16_DDR4_PHY_DQ_BYTE2_VREF_DAC_CONFIG_CTRL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_VREF_DAC_CONFIG_CTRL_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE2_VREF_DAC_CONFIG_CTRL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_VREF_DAC_CONFIG_CTRL_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE2_VREF_DAC_CONFIG_RESERVED_MASK 0xff000000
 #define SJC16_DDR4_PHY_DQ_BYTE2_VREF_DAC_CONFIG_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_VREF_DAC_CONFIG_RESERVED_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE2_VREF_DAC_CONFIG_RESERVED_SHIFT 24
 #define SJC16_DDR4_PHY_DQ_BYTE2_VREF_DAC_CONFIG_ALL_MASK 0xffffff
 #define SJC16_DDR4_PHY_DQ_BYTE2_VREF_DAC_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_VREF_DAC_CONFIG_ALL_BITS 24
 #define SJC16_DDR4_PHY_DQ_BYTE2_VREF_DAC_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_VREF_DAC_CONFIG_ALL_MASK 0xffffff
 #define SJC16_DDR4_PHY_DQ_BYTE2_VREF_DAC_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_VREF_DAC_CONFIG_ALL_BITS 24
 #define SJC16_DDR4_PHY_DQ_BYTE2_VREF_DAC_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_VREF_DAC_CONFIG_DATAMASK 0x00ff00ff
 #define SJC16_DDR4_PHY_DQ_BYTE2_VREF_DAC_CONFIG_RDWRMASK 0xff00ff00
 #define SJC16_DDR4_PHY_DQ_BYTE2_VREF_DAC_CONFIG_RESETVALUE 0x920000
 #define SJC16_DDR4_PHY_DQ_BYTE2_LDO_R_CONFIG 0x1023c89c
 #define SJC16_DDR4_PHY_DQ_BYTE2_LDO_R_CONFIG_BASE 0x89c
 #define SJC16_DDR4_PHY_DQ_BYTE2_LDO_R_CONFIG_REF_SEL_EXT_MASK 0x2000
 #define SJC16_DDR4_PHY_DQ_BYTE2_LDO_R_CONFIG_REF_SEL_EXT_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_LDO_R_CONFIG_REF_SEL_EXT_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE2_LDO_R_CONFIG_REF_SEL_EXT_SHIFT 13
 #define SJC16_DDR4_PHY_DQ_BYTE2_LDO_R_CONFIG_REF_SEL_EXT_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_LDO_R_CONFIG_REF_EXT_MASK 0x1000
 #define SJC16_DDR4_PHY_DQ_BYTE2_LDO_R_CONFIG_REF_EXT_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_LDO_R_CONFIG_REF_EXT_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE2_LDO_R_CONFIG_REF_EXT_SHIFT 12
 #define SJC16_DDR4_PHY_DQ_BYTE2_LDO_R_CONFIG_REF_EXT_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_LDO_R_CONFIG_PWRDN_MASK 0x200
 #define SJC16_DDR4_PHY_DQ_BYTE2_LDO_R_CONFIG_PWRDN_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_LDO_R_CONFIG_PWRDN_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE2_LDO_R_CONFIG_PWRDN_SHIFT 9
 #define SJC16_DDR4_PHY_DQ_BYTE2_LDO_R_CONFIG_PWRDN_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_LDO_R_CONFIG_CTRL_MASK 0x1f8
 #define SJC16_DDR4_PHY_DQ_BYTE2_LDO_R_CONFIG_CTRL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_LDO_R_CONFIG_CTRL_BITS 6
 #define SJC16_DDR4_PHY_DQ_BYTE2_LDO_R_CONFIG_CTRL_SHIFT 3
 #define SJC16_DDR4_PHY_DQ_BYTE2_LDO_R_CONFIG_CTRL_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_LDO_R_CONFIG_BYPASS_MASK 0x4
 #define SJC16_DDR4_PHY_DQ_BYTE2_LDO_R_CONFIG_BYPASS_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_LDO_R_CONFIG_BYPASS_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE2_LDO_R_CONFIG_BYPASS_SHIFT 2
 #define SJC16_DDR4_PHY_DQ_BYTE2_LDO_R_CONFIG_BYPASS_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_LDO_R_CONFIG_BIAS_CTRL_MASK 0x3
 #define SJC16_DDR4_PHY_DQ_BYTE2_LDO_R_CONFIG_BIAS_CTRL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_LDO_R_CONFIG_BIAS_CTRL_BITS 2
 #define SJC16_DDR4_PHY_DQ_BYTE2_LDO_R_CONFIG_BIAS_CTRL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_LDO_R_CONFIG_BIAS_CTRL_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_LDO_R_CONFIG_RESERVED_MASK 0xffffc000
 #define SJC16_DDR4_PHY_DQ_BYTE2_LDO_R_CONFIG_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_LDO_R_CONFIG_RESERVED_BITS 18
 #define SJC16_DDR4_PHY_DQ_BYTE2_LDO_R_CONFIG_RESERVED_SHIFT 14
 #define SJC16_DDR4_PHY_DQ_BYTE2_LDO_R_CONFIG_ALL_MASK 0x3fff
 #define SJC16_DDR4_PHY_DQ_BYTE2_LDO_R_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_LDO_R_CONFIG_ALL_BITS 14
 #define SJC16_DDR4_PHY_DQ_BYTE2_LDO_R_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_LDO_R_CONFIG_ALL_MASK 0x3fff
 #define SJC16_DDR4_PHY_DQ_BYTE2_LDO_R_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_LDO_R_CONFIG_ALL_BITS 14
 #define SJC16_DDR4_PHY_DQ_BYTE2_LDO_R_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_LDO_R_CONFIG_DATAMASK 0x000033ff
 #define SJC16_DDR4_PHY_DQ_BYTE2_LDO_R_CONFIG_RDWRMASK 0xffffcc00
 #define SJC16_DDR4_PHY_DQ_BYTE2_LDO_R_CONFIG_RESETVALUE 0x0000
 #define SJC16_DDR4_PHY_DQ_BYTE2_LDO_W_CONFIG 0x1023c8a0
 #define SJC16_DDR4_PHY_DQ_BYTE2_LDO_W_CONFIG_BASE 0x8a0
 #define SJC16_DDR4_PHY_DQ_BYTE2_LDO_W_CONFIG_REF_SEL_EXT_MASK 0x2000
 #define SJC16_DDR4_PHY_DQ_BYTE2_LDO_W_CONFIG_REF_SEL_EXT_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_LDO_W_CONFIG_REF_SEL_EXT_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE2_LDO_W_CONFIG_REF_SEL_EXT_SHIFT 13
 #define SJC16_DDR4_PHY_DQ_BYTE2_LDO_W_CONFIG_REF_SEL_EXT_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_LDO_W_CONFIG_REF_EXT_MASK 0x1000
 #define SJC16_DDR4_PHY_DQ_BYTE2_LDO_W_CONFIG_REF_EXT_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_LDO_W_CONFIG_REF_EXT_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE2_LDO_W_CONFIG_REF_EXT_SHIFT 12
 #define SJC16_DDR4_PHY_DQ_BYTE2_LDO_W_CONFIG_REF_EXT_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_LDO_W_CONFIG_PWRDN_MASK 0x200
 #define SJC16_DDR4_PHY_DQ_BYTE2_LDO_W_CONFIG_PWRDN_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_LDO_W_CONFIG_PWRDN_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE2_LDO_W_CONFIG_PWRDN_SHIFT 9
 #define SJC16_DDR4_PHY_DQ_BYTE2_LDO_W_CONFIG_PWRDN_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_LDO_W_CONFIG_CTRL_MASK 0x1f8
 #define SJC16_DDR4_PHY_DQ_BYTE2_LDO_W_CONFIG_CTRL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_LDO_W_CONFIG_CTRL_BITS 6
 #define SJC16_DDR4_PHY_DQ_BYTE2_LDO_W_CONFIG_CTRL_SHIFT 3
 #define SJC16_DDR4_PHY_DQ_BYTE2_LDO_W_CONFIG_CTRL_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_LDO_W_CONFIG_BYPASS_MASK 0x4
 #define SJC16_DDR4_PHY_DQ_BYTE2_LDO_W_CONFIG_BYPASS_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_LDO_W_CONFIG_BYPASS_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE2_LDO_W_CONFIG_BYPASS_SHIFT 2
 #define SJC16_DDR4_PHY_DQ_BYTE2_LDO_W_CONFIG_BYPASS_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_LDO_W_CONFIG_BIAS_CTRL_MASK 0x3
 #define SJC16_DDR4_PHY_DQ_BYTE2_LDO_W_CONFIG_BIAS_CTRL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_LDO_W_CONFIG_BIAS_CTRL_BITS 2
 #define SJC16_DDR4_PHY_DQ_BYTE2_LDO_W_CONFIG_BIAS_CTRL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_LDO_W_CONFIG_BIAS_CTRL_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_LDO_W_CONFIG_RESERVED_MASK 0xffffc000
 #define SJC16_DDR4_PHY_DQ_BYTE2_LDO_W_CONFIG_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_LDO_W_CONFIG_RESERVED_BITS 18
 #define SJC16_DDR4_PHY_DQ_BYTE2_LDO_W_CONFIG_RESERVED_SHIFT 14
 #define SJC16_DDR4_PHY_DQ_BYTE2_LDO_W_CONFIG_ALL_MASK 0x3fff
 #define SJC16_DDR4_PHY_DQ_BYTE2_LDO_W_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_LDO_W_CONFIG_ALL_BITS 14
 #define SJC16_DDR4_PHY_DQ_BYTE2_LDO_W_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_LDO_W_CONFIG_ALL_MASK 0x3fff
 #define SJC16_DDR4_PHY_DQ_BYTE2_LDO_W_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_LDO_W_CONFIG_ALL_BITS 14
 #define SJC16_DDR4_PHY_DQ_BYTE2_LDO_W_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_LDO_W_CONFIG_DATAMASK 0x000033ff
 #define SJC16_DDR4_PHY_DQ_BYTE2_LDO_W_CONFIG_RDWRMASK 0xffffcc00
 #define SJC16_DDR4_PHY_DQ_BYTE2_LDO_W_CONFIG_RESETVALUE 0x0000
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_OPERATION_CONFIG 0x1023c8a4
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_OPERATION_CONFIG_BASE 0x8a4
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_OPERATION_CONFIG_CLEAR_ACTIVITY_STATS_MASK 0x10000000
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_OPERATION_CONFIG_CLEAR_ACTIVITY_STATS_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_OPERATION_CONFIG_CLEAR_ACTIVITY_STATS_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_OPERATION_CONFIG_CLEAR_ACTIVITY_STATS_SHIFT 28
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_OPERATION_CONFIG_CLEAR_ACTIVITY_STATS_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_OPERATION_CONFIG_FIFO_W2R_MIN_DELAY_2_MASK 0x8000000
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_OPERATION_CONFIG_FIFO_W2R_MIN_DELAY_2_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_OPERATION_CONFIG_FIFO_W2R_MIN_DELAY_2_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_OPERATION_CONFIG_FIFO_W2R_MIN_DELAY_2_SHIFT 27
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_OPERATION_CONFIG_FIFO_W2R_MIN_DELAY_2_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_OPERATION_CONFIG_ROLLOVER_MODE_MASK 0x7000000
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_OPERATION_CONFIG_ROLLOVER_MODE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_OPERATION_CONFIG_ROLLOVER_MODE_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_OPERATION_CONFIG_ROLLOVER_MODE_SHIFT 24
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_OPERATION_CONFIG_ROLLOVER_MODE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_OPERATION_CONFIG_HALF_RATE_MODE_MASK 0x800000
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_OPERATION_CONFIG_HALF_RATE_MODE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_OPERATION_CONFIG_HALF_RATE_MODE_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_OPERATION_CONFIG_HALF_RATE_MODE_SHIFT 23
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_OPERATION_CONFIG_HALF_RATE_MODE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_OPERATION_CONFIG_INIT_TRACK_OPTIONS_MASK 0x600000
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_OPERATION_CONFIG_INIT_TRACK_OPTIONS_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_OPERATION_CONFIG_INIT_TRACK_OPTIONS_BITS 2
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_OPERATION_CONFIG_INIT_TRACK_OPTIONS_SHIFT 21
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_OPERATION_CONFIG_INIT_TRACK_OPTIONS_RESETVALUE 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_OPERATION_CONFIG_INIT_TRACK_TRANSITION_MASK 0x100000
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_OPERATION_CONFIG_INIT_TRACK_TRANSITION_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_OPERATION_CONFIG_INIT_TRACK_TRANSITION_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_OPERATION_CONFIG_INIT_TRACK_TRANSITION_SHIFT 20
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_OPERATION_CONFIG_INIT_TRACK_TRANSITION_RESETVALUE 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_OPERATION_CONFIG_ACCU_POS_THRESHOLD_MASK 0xff000
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_OPERATION_CONFIG_ACCU_POS_THRESHOLD_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_OPERATION_CONFIG_ACCU_POS_THRESHOLD_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_OPERATION_CONFIG_ACCU_POS_THRESHOLD_SHIFT 12
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_OPERATION_CONFIG_ACCU_POS_THRESHOLD_RESETVALUE 0x10
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_OPERATION_CONFIG_ACCU_LOAD_VALUE_MASK 0xff0
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_OPERATION_CONFIG_ACCU_LOAD_VALUE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_OPERATION_CONFIG_ACCU_LOAD_VALUE_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_OPERATION_CONFIG_ACCU_LOAD_VALUE_SHIFT 4
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_OPERATION_CONFIG_ACCU_LOAD_VALUE_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_OPERATION_CONFIG_ACCU_LOAD_MASK 0x8
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_OPERATION_CONFIG_ACCU_LOAD_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_OPERATION_CONFIG_ACCU_LOAD_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_OPERATION_CONFIG_ACCU_LOAD_SHIFT 3
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_OPERATION_CONFIG_ACCU_LOAD_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_OPERATION_CONFIG_UPDATE_MODE_MASK 0x6
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_OPERATION_CONFIG_UPDATE_MODE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_OPERATION_CONFIG_UPDATE_MODE_BITS 2
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_OPERATION_CONFIG_UPDATE_MODE_SHIFT 1
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_OPERATION_CONFIG_UPDATE_MODE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_OPERATION_CONFIG_ENABLE_MASK 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_OPERATION_CONFIG_ENABLE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_OPERATION_CONFIG_ENABLE_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_OPERATION_CONFIG_ENABLE_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_OPERATION_CONFIG_ENABLE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_OPERATION_CONFIG_RESERVED_MASK 0xe0000000
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_OPERATION_CONFIG_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_OPERATION_CONFIG_RESERVED_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_OPERATION_CONFIG_RESERVED_SHIFT 29
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_OPERATION_CONFIG_ALL_MASK 0x1fffffff
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_OPERATION_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_OPERATION_CONFIG_ALL_BITS 29
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_OPERATION_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_OPERATION_CONFIG_ALL_MASK 0x1fffffff
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_OPERATION_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_OPERATION_CONFIG_ALL_BITS 29
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_OPERATION_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_OPERATION_CONFIG_DATAMASK 0x1fffffff
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_OPERATION_CONFIG_RDWRMASK 0xe0000000
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_OPERATION_CONFIG_RESETVALUE 0x00310000
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_UPDATE_CONFIG 0x1023c8a8
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_UPDATE_CONFIG_BASE 0x8a8
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_UPDATE_CONFIG_ROLLOVER_PHASE_GAP_MASK 0xfc000000
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_UPDATE_CONFIG_ROLLOVER_PHASE_GAP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_UPDATE_CONFIG_ROLLOVER_PHASE_GAP_BITS 6
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_UPDATE_CONFIG_ROLLOVER_PHASE_GAP_SHIFT 26
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_UPDATE_CONFIG_ROLLOVER_PHASE_GAP_RESETVALUE 0x3
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_UPDATE_CONFIG_ROLLOVER_AMOUNT_MASK 0x1ff0000
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_UPDATE_CONFIG_ROLLOVER_AMOUNT_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_UPDATE_CONFIG_ROLLOVER_AMOUNT_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_UPDATE_CONFIG_ROLLOVER_AMOUNT_SHIFT 16
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_UPDATE_CONFIG_ROLLOVER_AMOUNT_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_UPDATE_CONFIG_UPDATE_ENABLE_DELAY_MASK 0x3f00
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_UPDATE_CONFIG_UPDATE_ENABLE_DELAY_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_UPDATE_CONFIG_UPDATE_ENABLE_DELAY_BITS 6
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_UPDATE_CONFIG_UPDATE_ENABLE_DELAY_SHIFT 8
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_UPDATE_CONFIG_UPDATE_ENABLE_DELAY_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_UPDATE_CONFIG_IMMEDIATE_UPDATE_THRESHOLD_MASK 0xf0
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_UPDATE_CONFIG_IMMEDIATE_UPDATE_THRESHOLD_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_UPDATE_CONFIG_IMMEDIATE_UPDATE_THRESHOLD_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_UPDATE_CONFIG_IMMEDIATE_UPDATE_THRESHOLD_SHIFT 4
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_UPDATE_CONFIG_IMMEDIATE_UPDATE_THRESHOLD_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_UPDATE_CONFIG_VDL_UPDATE_GAP_MASK 0xf
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_UPDATE_CONFIG_VDL_UPDATE_GAP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_UPDATE_CONFIG_VDL_UPDATE_GAP_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_UPDATE_CONFIG_VDL_UPDATE_GAP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_UPDATE_CONFIG_VDL_UPDATE_GAP_RESETVALUE 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_UPDATE_CONFIG_ALL_MASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_UPDATE_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_UPDATE_CONFIG_ALL_BITS 32
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_UPDATE_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_UPDATE_CONFIG_ALL_MASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_UPDATE_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_UPDATE_CONFIG_ALL_BITS 32
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_UPDATE_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_UPDATE_CONFIG_DATAMASK 0xfdff3fff
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_UPDATE_CONFIG_RDWRMASK 0x0200c000
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_UPDATE_CONFIG_RESETVALUE 0x0c000001
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_TRACK_CONFIG 0x1023c8ac
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_TRACK_CONFIG_BASE 0x8ac
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_TRACK_CONFIG_SEARCH_ACTIVE_TIMEOUT_MASK 0xf000
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_TRACK_CONFIG_SEARCH_ACTIVE_TIMEOUT_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_TRACK_CONFIG_SEARCH_ACTIVE_TIMEOUT_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_TRACK_CONFIG_SEARCH_ACTIVE_TIMEOUT_SHIFT 12
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_TRACK_CONFIG_SEARCH_ACTIVE_TIMEOUT_RESETVALUE 0xf
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_TRACK_CONFIG_TRACK_ACTIVE_TIMEOUT_MASK 0xf00
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_TRACK_CONFIG_TRACK_ACTIVE_TIMEOUT_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_TRACK_CONFIG_TRACK_ACTIVE_TIMEOUT_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_TRACK_CONFIG_TRACK_ACTIVE_TIMEOUT_SHIFT 8
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_TRACK_CONFIG_TRACK_ACTIVE_TIMEOUT_RESETVALUE 0xf
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_TRACK_CONFIG_ACCU_ACTIVE_TIMEOUT_MASK 0xff
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_TRACK_CONFIG_ACCU_ACTIVE_TIMEOUT_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_TRACK_CONFIG_ACCU_ACTIVE_TIMEOUT_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_TRACK_CONFIG_ACCU_ACTIVE_TIMEOUT_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_TRACK_CONFIG_ACCU_ACTIVE_TIMEOUT_RESETVALUE 0xff
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_TRACK_CONFIG_RESERVED_MASK 0xffff0000
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_TRACK_CONFIG_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_TRACK_CONFIG_RESERVED_BITS 16
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_TRACK_CONFIG_RESERVED_SHIFT 16
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_TRACK_CONFIG_ALL_MASK 0xffff
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_TRACK_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_TRACK_CONFIG_ALL_BITS 16
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_TRACK_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_TRACK_CONFIG_ALL_MASK 0xffff
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_TRACK_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_TRACK_CONFIG_ALL_BITS 16
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_TRACK_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_TRACK_CONFIG_DATAMASK 0x0000ffff
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_TRACK_CONFIG_RDWRMASK 0xffff0000
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_TRACK_CONFIG_RESETVALUE 0xffff
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_TIMING_CONFIG 0x1023c8b0
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_TIMING_CONFIG_BASE 0x8b0
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_TIMING_CONFIG_DATA_VALID_WR2RD_DELAY_LOAD_VALUE_MASK 0xf0000
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_TIMING_CONFIG_DATA_VALID_WR2RD_DELAY_LOAD_VALUE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_TIMING_CONFIG_DATA_VALID_WR2RD_DELAY_LOAD_VALUE_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_TIMING_CONFIG_DATA_VALID_WR2RD_DELAY_LOAD_VALUE_SHIFT 16
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_TIMING_CONFIG_DATA_VALID_WR2RD_DELAY_LOAD_VALUE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_TIMING_CONFIG_EDC_VALID_WR2RD_DELAY_LOAD_VALUE_MASK 0xf000
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_TIMING_CONFIG_EDC_VALID_WR2RD_DELAY_LOAD_VALUE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_TIMING_CONFIG_EDC_VALID_WR2RD_DELAY_LOAD_VALUE_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_TIMING_CONFIG_EDC_VALID_WR2RD_DELAY_LOAD_VALUE_SHIFT 12
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_TIMING_CONFIG_EDC_VALID_WR2RD_DELAY_LOAD_VALUE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_TIMING_CONFIG_DATA_READ_UI_SHIFT_LOAD_VALUE_MASK 0x700
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_TIMING_CONFIG_DATA_READ_UI_SHIFT_LOAD_VALUE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_TIMING_CONFIG_DATA_READ_UI_SHIFT_LOAD_VALUE_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_TIMING_CONFIG_DATA_READ_UI_SHIFT_LOAD_VALUE_SHIFT 8
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_TIMING_CONFIG_DATA_READ_UI_SHIFT_LOAD_VALUE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_TIMING_CONFIG_EDC_READ_UI_SHIFT_LOAD_VALUE_MASK 0x70
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_TIMING_CONFIG_EDC_READ_UI_SHIFT_LOAD_VALUE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_TIMING_CONFIG_EDC_READ_UI_SHIFT_LOAD_VALUE_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_TIMING_CONFIG_EDC_READ_UI_SHIFT_LOAD_VALUE_SHIFT 4
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_TIMING_CONFIG_EDC_READ_UI_SHIFT_LOAD_VALUE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_TIMING_CONFIG_CLEAR_VDL_STATS_ON_ROLLOVER_MASK 0x8
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_TIMING_CONFIG_CLEAR_VDL_STATS_ON_ROLLOVER_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_TIMING_CONFIG_CLEAR_VDL_STATS_ON_ROLLOVER_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_TIMING_CONFIG_CLEAR_VDL_STATS_ON_ROLLOVER_SHIFT 3
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_TIMING_CONFIG_CLEAR_VDL_STATS_ON_ROLLOVER_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_TIMING_CONFIG_CLEAR_VDL_STATS_MASK 0x4
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_TIMING_CONFIG_CLEAR_VDL_STATS_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_TIMING_CONFIG_CLEAR_VDL_STATS_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_TIMING_CONFIG_CLEAR_VDL_STATS_SHIFT 2
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_TIMING_CONFIG_CLEAR_VDL_STATS_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_TIMING_CONFIG_VDL_SWITCH_MASK 0x2
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_TIMING_CONFIG_VDL_SWITCH_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_TIMING_CONFIG_VDL_SWITCH_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_TIMING_CONFIG_VDL_SWITCH_SHIFT 1
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_TIMING_CONFIG_VDL_SWITCH_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_TIMING_CONFIG_VDL_LOAD_MASK 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_TIMING_CONFIG_VDL_LOAD_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_TIMING_CONFIG_VDL_LOAD_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_TIMING_CONFIG_VDL_LOAD_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_TIMING_CONFIG_VDL_LOAD_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_TIMING_CONFIG_RESERVED_0_MASK 0xfff00000
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_TIMING_CONFIG_RESERVED_0_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_TIMING_CONFIG_RESERVED_0_BITS 12
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_TIMING_CONFIG_RESERVED_0_SHIFT 20
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_TIMING_CONFIG_RESERVED_MASK 0xfff00000
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_TIMING_CONFIG_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_TIMING_CONFIG_RESERVED_BITS 12
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_TIMING_CONFIG_RESERVED_SHIFT 20
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_TIMING_CONFIG_ALL_MASK 0xfffff
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_TIMING_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_TIMING_CONFIG_ALL_BITS 20
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_TIMING_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_TIMING_CONFIG_ALL_MASK 0xfffff
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_TIMING_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_TIMING_CONFIG_ALL_BITS 20
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_TIMING_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_TIMING_CONFIG_DATAMASK 0x000ff77f
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_TIMING_CONFIG_RDWRMASK 0xfff00880
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_TIMING_CONFIG_RESETVALUE 0x00000
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_VDL_CAP_CONFIG 0x1023c8b4
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_VDL_CAP_CONFIG_BASE 0x8b4
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_VDL_CAP_CONFIG_FLEXIBLE_VDL_CAP_MASK 0x10000000
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_VDL_CAP_CONFIG_FLEXIBLE_VDL_CAP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_VDL_CAP_CONFIG_FLEXIBLE_VDL_CAP_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_VDL_CAP_CONFIG_FLEXIBLE_VDL_CAP_SHIFT 28
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_VDL_CAP_CONFIG_FLEXIBLE_VDL_CAP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_VDL_CAP_CONFIG_VDL_MAX_VALUE_CAP_MASK 0x1ff0000
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_VDL_CAP_CONFIG_VDL_MAX_VALUE_CAP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_VDL_CAP_CONFIG_VDL_MAX_VALUE_CAP_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_VDL_CAP_CONFIG_VDL_MAX_VALUE_CAP_SHIFT 16
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_VDL_CAP_CONFIG_VDL_MAX_VALUE_CAP_RESETVALUE 0x1ff
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_VDL_CAP_CONFIG_VDL_MIN_VALUE_CAP_MASK 0x1ff
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_VDL_CAP_CONFIG_VDL_MIN_VALUE_CAP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_VDL_CAP_CONFIG_VDL_MIN_VALUE_CAP_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_VDL_CAP_CONFIG_VDL_MIN_VALUE_CAP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_VDL_CAP_CONFIG_VDL_MIN_VALUE_CAP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_VDL_CAP_CONFIG_RESERVED_0_MASK 0xe0000000
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_VDL_CAP_CONFIG_RESERVED_0_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_VDL_CAP_CONFIG_RESERVED_0_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_VDL_CAP_CONFIG_RESERVED_0_SHIFT 29
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_VDL_CAP_CONFIG_RESERVED_1_MASK 0xe000000
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_VDL_CAP_CONFIG_RESERVED_1_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_VDL_CAP_CONFIG_RESERVED_1_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_VDL_CAP_CONFIG_RESERVED_1_SHIFT 25
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_VDL_CAP_CONFIG_RESERVED_2_MASK 0xfe00
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_VDL_CAP_CONFIG_RESERVED_2_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_VDL_CAP_CONFIG_RESERVED_2_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_VDL_CAP_CONFIG_RESERVED_2_SHIFT 9
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_VDL_CAP_CONFIG_RESERVED_MASK 0xe0000000
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_VDL_CAP_CONFIG_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_VDL_CAP_CONFIG_RESERVED_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_VDL_CAP_CONFIG_RESERVED_SHIFT 29
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_VDL_CAP_CONFIG_ALL_MASK 0x1fffffff
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_VDL_CAP_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_VDL_CAP_CONFIG_ALL_BITS 29
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_VDL_CAP_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_VDL_CAP_CONFIG_ALL_MASK 0x1fffffff
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_VDL_CAP_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_VDL_CAP_CONFIG_ALL_BITS 29
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_VDL_CAP_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_VDL_CAP_CONFIG_DATAMASK 0x11ff01ff
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_VDL_CAP_CONFIG_RDWRMASK 0xee00fe00
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_VDL_CAP_CONFIG_RESETVALUE 0x01ff0000
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_P_VDL_CONFIG 0x1023c8b8
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_P_VDL_CONFIG_BASE 0x8b8
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_P_VDL_CONFIG_DP_VDL_LOAD_VALUE_MASK 0x1ff0000
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_P_VDL_CONFIG_DP_VDL_LOAD_VALUE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_P_VDL_CONFIG_DP_VDL_LOAD_VALUE_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_P_VDL_CONFIG_DP_VDL_LOAD_VALUE_SHIFT 16
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_P_VDL_CONFIG_DP_VDL_LOAD_VALUE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_P_VDL_CONFIG_EP_VDL_LOAD_VALUE_MASK 0x1ff
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_P_VDL_CONFIG_EP_VDL_LOAD_VALUE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_P_VDL_CONFIG_EP_VDL_LOAD_VALUE_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_P_VDL_CONFIG_EP_VDL_LOAD_VALUE_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_P_VDL_CONFIG_EP_VDL_LOAD_VALUE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_P_VDL_CONFIG_RESERVED_MASK 0xfe000000
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_P_VDL_CONFIG_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_P_VDL_CONFIG_RESERVED_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_P_VDL_CONFIG_RESERVED_SHIFT 25
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_P_VDL_CONFIG_ALL_MASK 0x1ffffff
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_P_VDL_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_P_VDL_CONFIG_ALL_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_P_VDL_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_P_VDL_CONFIG_ALL_MASK 0x1ffffff
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_P_VDL_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_P_VDL_CONFIG_ALL_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_P_VDL_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_P_VDL_CONFIG_DATAMASK 0x01ff01ff
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_P_VDL_CONFIG_RDWRMASK 0xfe00fe00
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_P_VDL_CONFIG_RESETVALUE 0x0000000
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_N_VDL_CONFIG 0x1023c8bc
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_N_VDL_CONFIG_BASE 0x8bc
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_N_VDL_CONFIG_DN_VDL_LOAD_VALUE_MASK 0x1ff0000
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_N_VDL_CONFIG_DN_VDL_LOAD_VALUE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_N_VDL_CONFIG_DN_VDL_LOAD_VALUE_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_N_VDL_CONFIG_DN_VDL_LOAD_VALUE_SHIFT 16
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_N_VDL_CONFIG_DN_VDL_LOAD_VALUE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_N_VDL_CONFIG_EN_VDL_LOAD_VALUE_MASK 0x1ff
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_N_VDL_CONFIG_EN_VDL_LOAD_VALUE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_N_VDL_CONFIG_EN_VDL_LOAD_VALUE_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_N_VDL_CONFIG_EN_VDL_LOAD_VALUE_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_N_VDL_CONFIG_EN_VDL_LOAD_VALUE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_N_VDL_CONFIG_RESERVED_MASK 0xfe000000
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_N_VDL_CONFIG_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_N_VDL_CONFIG_RESERVED_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_N_VDL_CONFIG_RESERVED_SHIFT 25
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_N_VDL_CONFIG_ALL_MASK 0x1ffffff
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_N_VDL_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_N_VDL_CONFIG_ALL_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_N_VDL_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_N_VDL_CONFIG_ALL_MASK 0x1ffffff
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_N_VDL_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_N_VDL_CONFIG_ALL_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_N_VDL_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_N_VDL_CONFIG_DATAMASK 0x01ff01ff
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_N_VDL_CONFIG_RDWRMASK 0xfe00fe00
 #define SJC16_DDR4_PHY_DQ_BYTE2_CDR_N_VDL_CONFIG_RESETVALUE 0x0000000
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_P_VDL 0x1023c8c0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_P_VDL_BASE 0x8c0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_P_VDL_DP_VDL_VALUE_MASK 0x1ff0000
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_P_VDL_DP_VDL_VALUE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_P_VDL_DP_VDL_VALUE_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_P_VDL_DP_VDL_VALUE_SHIFT 16
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_P_VDL_DP_VDL_VALUE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_P_VDL_EP_VDL_VALUE_MASK 0x1ff
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_P_VDL_EP_VDL_VALUE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_P_VDL_EP_VDL_VALUE_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_P_VDL_EP_VDL_VALUE_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_P_VDL_EP_VDL_VALUE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_P_VDL_RESERVED_MASK 0xfe000000
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_P_VDL_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_P_VDL_RESERVED_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_P_VDL_RESERVED_SHIFT 25
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_P_VDL_ALL_MASK 0x1ffffff
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_P_VDL_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_P_VDL_ALL_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_P_VDL_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_P_VDL_ALL_MASK 0x1ffffff
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_P_VDL_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_P_VDL_ALL_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_P_VDL_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_P_VDL_DATAMASK 0x01ff01ff
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_P_VDL_RDWRMASK 0xfe00fe00
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_P_VDL_RESETVALUE 0x0000000
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_N_VDL 0x1023c8c4
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_N_VDL_BASE 0x8c4
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_N_VDL_DN_VDL_VALUE_MASK 0x1ff0000
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_N_VDL_DN_VDL_VALUE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_N_VDL_DN_VDL_VALUE_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_N_VDL_DN_VDL_VALUE_SHIFT 16
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_N_VDL_DN_VDL_VALUE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_N_VDL_EN_VDL_VALUE_MASK 0x1ff
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_N_VDL_EN_VDL_VALUE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_N_VDL_EN_VDL_VALUE_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_N_VDL_EN_VDL_VALUE_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_N_VDL_EN_VDL_VALUE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_N_VDL_RESERVED_MASK 0xfe000000
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_N_VDL_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_N_VDL_RESERVED_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_N_VDL_RESERVED_SHIFT 25
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_N_VDL_ALL_MASK 0x1ffffff
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_N_VDL_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_N_VDL_ALL_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_N_VDL_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_N_VDL_ALL_MASK 0x1ffffff
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_N_VDL_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_N_VDL_ALL_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_N_VDL_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_N_VDL_DATAMASK 0x01ff01ff
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_N_VDL_RDWRMASK 0xfe00fe00
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_N_VDL_RESETVALUE 0x0000000
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_EP_VDL_STAT 0x1023c8c8
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_EP_VDL_STAT_BASE 0x8c8
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_EP_VDL_STAT_MAX_VDL_VALUE_MASK 0x1ff0000
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_EP_VDL_STAT_MAX_VDL_VALUE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_EP_VDL_STAT_MAX_VDL_VALUE_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_EP_VDL_STAT_MAX_VDL_VALUE_SHIFT 16
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_EP_VDL_STAT_MAX_VDL_VALUE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_EP_VDL_STAT_MIN_VDL_VALUE_MASK 0x1ff
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_EP_VDL_STAT_MIN_VDL_VALUE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_EP_VDL_STAT_MIN_VDL_VALUE_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_EP_VDL_STAT_MIN_VDL_VALUE_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_EP_VDL_STAT_MIN_VDL_VALUE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_EP_VDL_STAT_RESERVED_MASK 0xfe000000
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_EP_VDL_STAT_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_EP_VDL_STAT_RESERVED_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_EP_VDL_STAT_RESERVED_SHIFT 25
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_EP_VDL_STAT_ALL_MASK 0x1ffffff
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_EP_VDL_STAT_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_EP_VDL_STAT_ALL_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_EP_VDL_STAT_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_EP_VDL_STAT_ALL_MASK 0x1ffffff
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_EP_VDL_STAT_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_EP_VDL_STAT_ALL_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_EP_VDL_STAT_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_EP_VDL_STAT_DATAMASK 0x01ff01ff
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_EP_VDL_STAT_RDWRMASK 0xfe00fe00
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_EP_VDL_STAT_RESETVALUE 0x0000000
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_DP_VDL_STAT 0x1023c8cc
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_DP_VDL_STAT_BASE 0x8cc
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_DP_VDL_STAT_MAX_VDL_VALUE_MASK 0x1ff0000
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_DP_VDL_STAT_MAX_VDL_VALUE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_DP_VDL_STAT_MAX_VDL_VALUE_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_DP_VDL_STAT_MAX_VDL_VALUE_SHIFT 16
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_DP_VDL_STAT_MAX_VDL_VALUE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_DP_VDL_STAT_MIN_VDL_VALUE_MASK 0x1ff
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_DP_VDL_STAT_MIN_VDL_VALUE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_DP_VDL_STAT_MIN_VDL_VALUE_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_DP_VDL_STAT_MIN_VDL_VALUE_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_DP_VDL_STAT_MIN_VDL_VALUE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_DP_VDL_STAT_RESERVED_MASK 0xfe000000
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_DP_VDL_STAT_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_DP_VDL_STAT_RESERVED_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_DP_VDL_STAT_RESERVED_SHIFT 25
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_DP_VDL_STAT_ALL_MASK 0x1ffffff
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_DP_VDL_STAT_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_DP_VDL_STAT_ALL_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_DP_VDL_STAT_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_DP_VDL_STAT_ALL_MASK 0x1ffffff
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_DP_VDL_STAT_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_DP_VDL_STAT_ALL_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_DP_VDL_STAT_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_DP_VDL_STAT_DATAMASK 0x01ff01ff
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_DP_VDL_STAT_RDWRMASK 0xfe00fe00
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_DP_VDL_STAT_RESETVALUE 0x0000000
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_EN_VDL_STAT 0x1023c8d0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_EN_VDL_STAT_BASE 0x8d0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_EN_VDL_STAT_MAX_VDL_VALUE_MASK 0x1ff0000
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_EN_VDL_STAT_MAX_VDL_VALUE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_EN_VDL_STAT_MAX_VDL_VALUE_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_EN_VDL_STAT_MAX_VDL_VALUE_SHIFT 16
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_EN_VDL_STAT_MAX_VDL_VALUE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_EN_VDL_STAT_MIN_VDL_VALUE_MASK 0x1ff
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_EN_VDL_STAT_MIN_VDL_VALUE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_EN_VDL_STAT_MIN_VDL_VALUE_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_EN_VDL_STAT_MIN_VDL_VALUE_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_EN_VDL_STAT_MIN_VDL_VALUE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_EN_VDL_STAT_RESERVED_MASK 0xfe000000
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_EN_VDL_STAT_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_EN_VDL_STAT_RESERVED_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_EN_VDL_STAT_RESERVED_SHIFT 25
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_EN_VDL_STAT_ALL_MASK 0x1ffffff
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_EN_VDL_STAT_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_EN_VDL_STAT_ALL_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_EN_VDL_STAT_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_EN_VDL_STAT_ALL_MASK 0x1ffffff
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_EN_VDL_STAT_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_EN_VDL_STAT_ALL_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_EN_VDL_STAT_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_EN_VDL_STAT_DATAMASK 0x01ff01ff
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_EN_VDL_STAT_RDWRMASK 0xfe00fe00
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_EN_VDL_STAT_RESETVALUE 0x0000000
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_DN_VDL_STAT 0x1023c8d4
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_DN_VDL_STAT_BASE 0x8d4
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_DN_VDL_STAT_MAX_VDL_VALUE_MASK 0x1ff0000
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_DN_VDL_STAT_MAX_VDL_VALUE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_DN_VDL_STAT_MAX_VDL_VALUE_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_DN_VDL_STAT_MAX_VDL_VALUE_SHIFT 16
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_DN_VDL_STAT_MAX_VDL_VALUE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_DN_VDL_STAT_MIN_VDL_VALUE_MASK 0x1ff
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_DN_VDL_STAT_MIN_VDL_VALUE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_DN_VDL_STAT_MIN_VDL_VALUE_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_DN_VDL_STAT_MIN_VDL_VALUE_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_DN_VDL_STAT_MIN_VDL_VALUE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_DN_VDL_STAT_RESERVED_MASK 0xfe000000
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_DN_VDL_STAT_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_DN_VDL_STAT_RESERVED_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_DN_VDL_STAT_RESERVED_SHIFT 25
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_DN_VDL_STAT_ALL_MASK 0x1ffffff
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_DN_VDL_STAT_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_DN_VDL_STAT_ALL_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_DN_VDL_STAT_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_DN_VDL_STAT_ALL_MASK 0x1ffffff
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_DN_VDL_STAT_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_DN_VDL_STAT_ALL_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_DN_VDL_STAT_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_DN_VDL_STAT_DATAMASK 0x01ff01ff
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_DN_VDL_STAT_RDWRMASK 0xfe00fe00
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_DN_VDL_STAT_RESETVALUE 0x0000000
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_OPERATION 0x1023c8d8
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_OPERATION_BASE 0x8d8
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_OPERATION_ROLLOVER_OVERFLOW_MASK 0x10000000
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_OPERATION_ROLLOVER_OVERFLOW_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_OPERATION_ROLLOVER_OVERFLOW_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_OPERATION_ROLLOVER_OVERFLOW_SHIFT 28
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_OPERATION_ROLLOVER_OVERFLOW_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_OPERATION_ROLLOVER_COUNT_MASK 0xff00000
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_OPERATION_ROLLOVER_COUNT_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_OPERATION_ROLLOVER_COUNT_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_OPERATION_ROLLOVER_COUNT_SHIFT 20
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_OPERATION_ROLLOVER_COUNT_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_OPERATION_SEARCH_ACTIVE_RETRIGGERED_MASK 0x20000
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_OPERATION_SEARCH_ACTIVE_RETRIGGERED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_OPERATION_SEARCH_ACTIVE_RETRIGGERED_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_OPERATION_SEARCH_ACTIVE_RETRIGGERED_SHIFT 17
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_OPERATION_SEARCH_ACTIVE_RETRIGGERED_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_OPERATION_INIT_SEARCH_COMPLETE_MASK 0x10000
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_OPERATION_INIT_SEARCH_COMPLETE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_OPERATION_INIT_SEARCH_COMPLETE_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_OPERATION_INIT_SEARCH_COMPLETE_SHIFT 16
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_OPERATION_INIT_SEARCH_COMPLETE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_OPERATION_INIT_SEARCH_ACTIVE_MASK 0x8000
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_OPERATION_INIT_SEARCH_ACTIVE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_OPERATION_INIT_SEARCH_ACTIVE_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_OPERATION_INIT_SEARCH_ACTIVE_SHIFT 15
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_OPERATION_INIT_SEARCH_ACTIVE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_OPERATION_TRACK_ACTIVE_LOST_MASK 0x4000
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_OPERATION_TRACK_ACTIVE_LOST_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_OPERATION_TRACK_ACTIVE_LOST_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_OPERATION_TRACK_ACTIVE_LOST_SHIFT 14
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_OPERATION_TRACK_ACTIVE_LOST_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_OPERATION_INIT_TRACK_ACTIVE_MASK 0x2000
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_OPERATION_INIT_TRACK_ACTIVE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_OPERATION_INIT_TRACK_ACTIVE_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_OPERATION_INIT_TRACK_ACTIVE_SHIFT 13
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_OPERATION_INIT_TRACK_ACTIVE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_OPERATION_ACCU_ACTIVE_LOST_MASK 0x1000
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_OPERATION_ACCU_ACTIVE_LOST_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_OPERATION_ACCU_ACTIVE_LOST_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_OPERATION_ACCU_ACTIVE_LOST_SHIFT 12
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_OPERATION_ACCU_ACTIVE_LOST_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_OPERATION_INIT_ACCU_ACTIVE_MASK 0x800
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_OPERATION_INIT_ACCU_ACTIVE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_OPERATION_INIT_ACCU_ACTIVE_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_OPERATION_INIT_ACCU_ACTIVE_SHIFT 11
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_OPERATION_INIT_ACCU_ACTIVE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_OPERATION_SEARCH_ACTIVE_MASK 0x400
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_OPERATION_SEARCH_ACTIVE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_OPERATION_SEARCH_ACTIVE_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_OPERATION_SEARCH_ACTIVE_SHIFT 10
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_OPERATION_SEARCH_ACTIVE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_OPERATION_TRACK_ACTIVE_MASK 0x200
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_OPERATION_TRACK_ACTIVE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_OPERATION_TRACK_ACTIVE_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_OPERATION_TRACK_ACTIVE_SHIFT 9
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_OPERATION_TRACK_ACTIVE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_OPERATION_ACCU_ACTIVE_MASK 0x100
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_OPERATION_ACCU_ACTIVE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_OPERATION_ACCU_ACTIVE_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_OPERATION_ACCU_ACTIVE_SHIFT 8
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_OPERATION_ACCU_ACTIVE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_OPERATION_ACCU_VALUE_MASK 0xff
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_OPERATION_ACCU_VALUE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_OPERATION_ACCU_VALUE_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_OPERATION_ACCU_VALUE_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_OPERATION_ACCU_VALUE_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_OPERATION_RESERVED_MASK 0xe0000000
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_OPERATION_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_OPERATION_RESERVED_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_OPERATION_RESERVED_SHIFT 29
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_OPERATION_ALL_MASK 0x1fffffff
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_OPERATION_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_OPERATION_ALL_BITS 29
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_OPERATION_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_OPERATION_ALL_MASK 0x1fffffff
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_OPERATION_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_OPERATION_ALL_BITS 29
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_OPERATION_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_OPERATION_DATAMASK 0x1ff3ffff
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_OPERATION_RDWRMASK 0xe00c0000
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_OPERATION_RESETVALUE 0x00000000
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_TIMING 0x1023c8dc
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_TIMING_BASE 0x8dc
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_TIMING_DATA_VALID_WR2RD_DELAY_MASK 0xf0000
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_TIMING_DATA_VALID_WR2RD_DELAY_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_TIMING_DATA_VALID_WR2RD_DELAY_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_TIMING_DATA_VALID_WR2RD_DELAY_SHIFT 16
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_TIMING_DATA_VALID_WR2RD_DELAY_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_TIMING_EDC_VALID_WR2RD_DELAY_MASK 0xf000
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_TIMING_EDC_VALID_WR2RD_DELAY_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_TIMING_EDC_VALID_WR2RD_DELAY_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_TIMING_EDC_VALID_WR2RD_DELAY_SHIFT 12
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_TIMING_EDC_VALID_WR2RD_DELAY_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_TIMING_DATA_READ_UI_SHIFT_MASK 0x700
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_TIMING_DATA_READ_UI_SHIFT_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_TIMING_DATA_READ_UI_SHIFT_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_TIMING_DATA_READ_UI_SHIFT_SHIFT 8
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_TIMING_DATA_READ_UI_SHIFT_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_TIMING_EDC_READ_UI_SHIFT_MASK 0x70
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_TIMING_EDC_READ_UI_SHIFT_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_TIMING_EDC_READ_UI_SHIFT_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_TIMING_EDC_READ_UI_SHIFT_SHIFT 4
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_TIMING_EDC_READ_UI_SHIFT_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_TIMING_DATA_VALID_WR2RD_DELAY_DEC_MASK 0x8
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_TIMING_DATA_VALID_WR2RD_DELAY_DEC_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_TIMING_DATA_VALID_WR2RD_DELAY_DEC_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_TIMING_DATA_VALID_WR2RD_DELAY_DEC_SHIFT 3
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_TIMING_DATA_VALID_WR2RD_DELAY_DEC_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_TIMING_DATA_VALID_WR2RD_DELAY_INC_MASK 0x4
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_TIMING_DATA_VALID_WR2RD_DELAY_INC_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_TIMING_DATA_VALID_WR2RD_DELAY_INC_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_TIMING_DATA_VALID_WR2RD_DELAY_INC_SHIFT 2
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_TIMING_DATA_VALID_WR2RD_DELAY_INC_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_TIMING_EDC_VALID_WR2RD_DELAY_DEC_MASK 0x2
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_TIMING_EDC_VALID_WR2RD_DELAY_DEC_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_TIMING_EDC_VALID_WR2RD_DELAY_DEC_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_TIMING_EDC_VALID_WR2RD_DELAY_DEC_SHIFT 1
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_TIMING_EDC_VALID_WR2RD_DELAY_DEC_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_TIMING_EDC_VALID_WR2RD_DELAY_INC_MASK 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_TIMING_EDC_VALID_WR2RD_DELAY_INC_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_TIMING_EDC_VALID_WR2RD_DELAY_INC_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_TIMING_EDC_VALID_WR2RD_DELAY_INC_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_TIMING_EDC_VALID_WR2RD_DELAY_INC_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_TIMING_RESERVED_0_MASK 0xfff00000
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_TIMING_RESERVED_0_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_TIMING_RESERVED_0_BITS 12
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_TIMING_RESERVED_0_SHIFT 20
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_TIMING_RESERVED_MASK 0xfff00000
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_TIMING_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_TIMING_RESERVED_BITS 12
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_TIMING_RESERVED_SHIFT 20
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_TIMING_ALL_MASK 0xfffff
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_TIMING_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_TIMING_ALL_BITS 20
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_TIMING_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_TIMING_ALL_MASK 0xfffff
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_TIMING_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_TIMING_ALL_BITS 20
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_TIMING_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_TIMING_DATAMASK 0x000ff77f
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_TIMING_RDWRMASK 0xfff00880
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_CDR_TIMING_RESETVALUE 0x00000
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_FIFO_PTR 0x1023c8e0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_FIFO_PTR_BASE 0x8e0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_FIFO_PTR_RP_XMSB_MASK 0x20000
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_FIFO_PTR_RP_XMSB_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_FIFO_PTR_RP_XMSB_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_FIFO_PTR_RP_XMSB_SHIFT 17
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_FIFO_PTR_RP_XMSB_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_FIFO_PTR_RP_MASK 0x1f000
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_FIFO_PTR_RP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_FIFO_PTR_RP_BITS 5
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_FIFO_PTR_RP_SHIFT 12
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_FIFO_PTR_RP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_FIFO_PTR_WP1_XMSB_MASK 0x800
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_FIFO_PTR_WP1_XMSB_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_FIFO_PTR_WP1_XMSB_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_FIFO_PTR_WP1_XMSB_SHIFT 11
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_FIFO_PTR_WP1_XMSB_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_FIFO_PTR_WP1_MASK 0x7c0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_FIFO_PTR_WP1_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_FIFO_PTR_WP1_BITS 5
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_FIFO_PTR_WP1_SHIFT 6
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_FIFO_PTR_WP1_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_FIFO_PTR_WP0_XMSB_MASK 0x20
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_FIFO_PTR_WP0_XMSB_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_FIFO_PTR_WP0_XMSB_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_FIFO_PTR_WP0_XMSB_SHIFT 5
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_FIFO_PTR_WP0_XMSB_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_FIFO_PTR_WP0_MASK 0x1f
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_FIFO_PTR_WP0_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_FIFO_PTR_WP0_BITS 5
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_FIFO_PTR_WP0_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_FIFO_PTR_WP0_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_FIFO_PTR_RESERVED_MASK 0xfffc0000
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_FIFO_PTR_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_FIFO_PTR_RESERVED_BITS 14
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_FIFO_PTR_RESERVED_SHIFT 18
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_FIFO_PTR_ALL_MASK 0x3ffff
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_FIFO_PTR_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_FIFO_PTR_ALL_BITS 18
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_FIFO_PTR_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_FIFO_PTR_ALL_MASK 0x3ffff
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_FIFO_PTR_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_FIFO_PTR_ALL_BITS 18
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_FIFO_PTR_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_FIFO_PTR_DATAMASK 0x0003ffff
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_FIFO_PTR_RDWRMASK 0xfffc0000
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_FIFO_PTR_RESETVALUE 0x00000
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_FIFO_CTR 0x1023c8e4
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_FIFO_CTR_BASE 0x8e4
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_FIFO_CTR_MAX_WCOUNT_MASK 0x3f00
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_FIFO_CTR_MAX_WCOUNT_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_FIFO_CTR_MAX_WCOUNT_BITS 6
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_FIFO_CTR_MAX_WCOUNT_SHIFT 8
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_FIFO_CTR_MAX_WCOUNT_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_FIFO_CTR_CUR_WCOUNT_MASK 0xfc
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_FIFO_CTR_CUR_WCOUNT_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_FIFO_CTR_CUR_WCOUNT_BITS 6
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_FIFO_CTR_CUR_WCOUNT_SHIFT 2
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_FIFO_CTR_CUR_WCOUNT_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_FIFO_CTR_WFULL_MASK 0x2
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_FIFO_CTR_WFULL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_FIFO_CTR_WFULL_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_FIFO_CTR_WFULL_SHIFT 1
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_FIFO_CTR_WFULL_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_FIFO_CTR_WRITE_ERROR_MASK 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_FIFO_CTR_WRITE_ERROR_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_FIFO_CTR_WRITE_ERROR_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_FIFO_CTR_WRITE_ERROR_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_FIFO_CTR_WRITE_ERROR_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_FIFO_CTR_RESERVED_MASK 0xffffc000
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_FIFO_CTR_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_FIFO_CTR_RESERVED_BITS 18
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_FIFO_CTR_RESERVED_SHIFT 14
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_FIFO_CTR_ALL_MASK 0x3fff
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_FIFO_CTR_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_FIFO_CTR_ALL_BITS 14
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_FIFO_CTR_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_FIFO_CTR_ALL_MASK 0x3fff
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_FIFO_CTR_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_FIFO_CTR_ALL_BITS 14
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_FIFO_CTR_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_FIFO_CTR_DATAMASK 0x00003fff
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_FIFO_CTR_RDWRMASK 0xffffc000
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_FIFO_CTR_RESETVALUE 0x0000
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH 0x1023c8e8
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_BASE 0x8e8
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_PAST_STATE7_MASK 0x7000000
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_PAST_STATE7_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_PAST_STATE7_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_PAST_STATE7_SHIFT 24
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_PAST_STATE7_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_PAST_STATE6_MASK 0xe00000
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_PAST_STATE6_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_PAST_STATE6_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_PAST_STATE6_SHIFT 21
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_PAST_STATE6_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_PAST_STATE5_MASK 0x1c0000
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_PAST_STATE5_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_PAST_STATE5_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_PAST_STATE5_SHIFT 18
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_PAST_STATE5_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_PAST_STATE4_MASK 0x38000
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_PAST_STATE4_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_PAST_STATE4_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_PAST_STATE4_SHIFT 15
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_PAST_STATE4_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_PAST_STATE3_MASK 0x7000
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_PAST_STATE3_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_PAST_STATE3_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_PAST_STATE3_SHIFT 12
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_PAST_STATE3_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_PAST_STATE2_MASK 0xe00
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_PAST_STATE2_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_PAST_STATE2_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_PAST_STATE2_SHIFT 9
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_PAST_STATE2_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_PAST_STATE1_MASK 0x1c0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_PAST_STATE1_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_PAST_STATE1_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_PAST_STATE1_SHIFT 6
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_PAST_STATE1_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_PAST_STATE0_MASK 0x38
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_PAST_STATE0_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_PAST_STATE0_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_PAST_STATE0_SHIFT 3
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_PAST_STATE0_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_CUR_STATE_MASK 0x7
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_CUR_STATE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_CUR_STATE_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_CUR_STATE_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_CUR_STATE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_RESERVED_MASK 0xf8000000
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_RESERVED_BITS 5
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_RESERVED_SHIFT 27
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_ALL_MASK 0x7ffffff
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_ALL_BITS 27
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_ALL_MASK 0x7ffffff
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_ALL_BITS 27
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_DATAMASK 0x07ffffff
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_RDWRMASK 0xf8000000
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_RESETVALUE 0x0000000
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_ERR1 0x1023c8ec
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_ERR1_BASE 0x8ec
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_ERR1_RCMD_FIFO_RD_MASK 0x1000
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_ERR1_RCMD_FIFO_RD_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_ERR1_RCMD_FIFO_RD_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_ERR1_RCMD_FIFO_RD_SHIFT 12
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_ERR1_RCMD_FIFO_RD_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_ERR1_RCMD_FIFO_RDATA_MASK 0xff0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_ERR1_RCMD_FIFO_RDATA_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_ERR1_RCMD_FIFO_RDATA_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_ERR1_RCMD_FIFO_RDATA_SHIFT 4
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_ERR1_RCMD_FIFO_RDATA_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_ERR1_STATE_MASK 0xe
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_ERR1_STATE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_ERR1_STATE_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_ERR1_STATE_SHIFT 1
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_ERR1_STATE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_ERR1_ERROR_MASK 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_ERR1_ERROR_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_ERR1_ERROR_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_ERR1_ERROR_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_ERR1_ERROR_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_ERR1_RESERVED_MASK 0xffffe000
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_ERR1_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_ERR1_RESERVED_BITS 19
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_ERR1_RESERVED_SHIFT 13
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_ERR1_ALL_MASK 0x1fff
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_ERR1_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_ERR1_ALL_BITS 13
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_ERR1_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_ERR1_ALL_MASK 0x1fff
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_ERR1_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_ERR1_ALL_BITS 13
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_ERR1_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_ERR1_DATAMASK 0x00001fff
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_ERR1_RDWRMASK 0xffffe000
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_ERR1_RESETVALUE 0x0000
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_ERR2 0x1023c8f0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_ERR2_BASE 0x8f0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_ERR2_RCMD_FIFO_RD_MASK 0x1000
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_ERR2_RCMD_FIFO_RD_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_ERR2_RCMD_FIFO_RD_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_ERR2_RCMD_FIFO_RD_SHIFT 12
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_ERR2_RCMD_FIFO_RD_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_ERR2_RCMD_FIFO_RDATA_MASK 0xff0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_ERR2_RCMD_FIFO_RDATA_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_ERR2_RCMD_FIFO_RDATA_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_ERR2_RCMD_FIFO_RDATA_SHIFT 4
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_ERR2_RCMD_FIFO_RDATA_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_ERR2_STATE_MASK 0xe
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_ERR2_STATE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_ERR2_STATE_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_ERR2_STATE_SHIFT 1
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_ERR2_STATE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_ERR2_ERROR_MASK 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_ERR2_ERROR_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_ERR2_ERROR_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_ERR2_ERROR_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_ERR2_ERROR_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_ERR2_RESERVED_MASK 0xffffe000
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_ERR2_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_ERR2_RESERVED_BITS 19
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_ERR2_RESERVED_SHIFT 13
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_ERR2_ALL_MASK 0x1fff
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_ERR2_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_ERR2_ALL_BITS 13
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_ERR2_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_ERR2_ALL_MASK 0x1fff
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_ERR2_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_ERR2_ALL_BITS 13
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_ERR2_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_ERR2_DATAMASK 0x00001fff
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_ERR2_RDWRMASK 0xffffe000
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_ERR2_RESETVALUE 0x0000
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_ERR3 0x1023c8f4
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_ERR3_BASE 0x8f4
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_ERR3_EXP_RCMD_ID_MASK 0xfc00
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_ERR3_EXP_RCMD_ID_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_ERR3_EXP_RCMD_ID_BITS 6
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_ERR3_EXP_RCMD_ID_SHIFT 10
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_ERR3_EXP_RCMD_ID_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_ERR3_OBS_RCMD_ID_MASK 0x3f0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_ERR3_OBS_RCMD_ID_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_ERR3_OBS_RCMD_ID_BITS 6
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_ERR3_OBS_RCMD_ID_SHIFT 4
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_ERR3_OBS_RCMD_ID_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_ERR3_STATE_MASK 0xe
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_ERR3_STATE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_ERR3_STATE_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_ERR3_STATE_SHIFT 1
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_ERR3_STATE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_ERR3_ERROR_MASK 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_ERR3_ERROR_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_ERR3_ERROR_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_ERR3_ERROR_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_ERR3_ERROR_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_ERR3_RESERVED_MASK 0xffff0000
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_ERR3_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_ERR3_RESERVED_BITS 16
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_ERR3_RESERVED_SHIFT 16
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_ERR3_ALL_MASK 0xffff
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_ERR3_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_ERR3_ALL_BITS 16
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_ERR3_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_ERR3_ALL_MASK 0xffff
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_ERR3_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_ERR3_ALL_BITS 16
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_ERR3_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_ERR3_DATAMASK 0x0000ffff
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_ERR3_RDWRMASK 0xffff0000
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_ERR3_RESETVALUE 0x0000
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_RCMD_ID 0x1023c8f8
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_RCMD_ID_BASE 0x8f8
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_RCMD_ID_ID8_MASK 0xfc0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_RCMD_ID_ID8_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_RCMD_ID_ID8_BITS 6
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_RCMD_ID_ID8_SHIFT 6
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_RCMD_ID_ID8_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_RCMD_ID_ID4_MASK 0x3f
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_RCMD_ID_ID4_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_RCMD_ID_ID4_BITS 6
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_RCMD_ID_ID4_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_RCMD_ID_ID4_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_RCMD_ID_RESERVED_MASK 0xfffff000
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_RCMD_ID_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_RCMD_ID_RESERVED_BITS 20
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_RCMD_ID_RESERVED_SHIFT 12
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_RCMD_ID_ALL_MASK 0xfff
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_RCMD_ID_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_RCMD_ID_ALL_BITS 12
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_RCMD_ID_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_RCMD_ID_ALL_MASK 0xfff
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_RCMD_ID_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_RCMD_ID_ALL_BITS 12
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_RCMD_ID_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_RCMD_ID_DATAMASK 0x00000fff
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_RCMD_ID_RDWRMASK 0xfffff000
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_RCMD_ID_RESETVALUE 0x000
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RDATA_FIFO 0x1023c8fc
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RDATA_FIFO_BASE 0x8fc
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RDATA_FIFO_RP1_XMSB_MASK 0x4000
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RDATA_FIFO_RP1_XMSB_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RDATA_FIFO_RP1_XMSB_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RDATA_FIFO_RP1_XMSB_SHIFT 14
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RDATA_FIFO_RP1_XMSB_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RDATA_FIFO_RP1_MASK 0x3c00
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RDATA_FIFO_RP1_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RDATA_FIFO_RP1_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RDATA_FIFO_RP1_SHIFT 10
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RDATA_FIFO_RP1_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RDATA_FIFO_RP0_XMSB_MASK 0x200
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RDATA_FIFO_RP0_XMSB_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RDATA_FIFO_RP0_XMSB_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RDATA_FIFO_RP0_XMSB_SHIFT 9
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RDATA_FIFO_RP0_XMSB_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RDATA_FIFO_RP0_MASK 0x1e0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RDATA_FIFO_RP0_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RDATA_FIFO_RP0_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RDATA_FIFO_RP0_SHIFT 5
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RDATA_FIFO_RP0_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RDATA_FIFO_WP_XMSB_MASK 0x10
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RDATA_FIFO_WP_XMSB_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RDATA_FIFO_WP_XMSB_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RDATA_FIFO_WP_XMSB_SHIFT 4
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RDATA_FIFO_WP_XMSB_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RDATA_FIFO_WP_MASK 0xf
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RDATA_FIFO_WP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RDATA_FIFO_WP_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RDATA_FIFO_WP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RDATA_FIFO_WP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RDATA_FIFO_RESERVED_MASK 0xffff8000
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RDATA_FIFO_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RDATA_FIFO_RESERVED_BITS 17
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RDATA_FIFO_RESERVED_SHIFT 15
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RDATA_FIFO_ALL_MASK 0x7fff
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RDATA_FIFO_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RDATA_FIFO_ALL_BITS 15
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RDATA_FIFO_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RDATA_FIFO_ALL_MASK 0x7fff
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RDATA_FIFO_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RDATA_FIFO_ALL_BITS 15
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RDATA_FIFO_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RDATA_FIFO_DATAMASK 0x00007fff
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RDATA_FIFO_RDWRMASK 0xffff8000
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RDATA_FIFO_RESETVALUE 0x0000
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_FIFO 0x1023c900
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_FIFO_BASE 0x900
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_FIFO_RP_2G_XMSB_MASK 0x20000
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_FIFO_RP_2G_XMSB_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_FIFO_RP_2G_XMSB_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_FIFO_RP_2G_XMSB_SHIFT 17
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_FIFO_RP_2G_XMSB_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_FIFO_RP_2G_MASK 0x1f000
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_FIFO_RP_2G_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_FIFO_RP_2G_BITS 5
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_FIFO_RP_2G_SHIFT 12
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_FIFO_RP_2G_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_FIFO_RP_1G_XMSB_MASK 0x800
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_FIFO_RP_1G_XMSB_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_FIFO_RP_1G_XMSB_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_FIFO_RP_1G_XMSB_SHIFT 11
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_FIFO_RP_1G_XMSB_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_FIFO_RP_1G_MASK 0x7c0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_FIFO_RP_1G_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_FIFO_RP_1G_BITS 5
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_FIFO_RP_1G_SHIFT 6
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_FIFO_RP_1G_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_FIFO_WP_XMSB_MASK 0x20
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_FIFO_WP_XMSB_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_FIFO_WP_XMSB_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_FIFO_WP_XMSB_SHIFT 5
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_FIFO_WP_XMSB_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_FIFO_WP_MASK 0x1f
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_FIFO_WP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_FIFO_WP_BITS 5
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_FIFO_WP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_FIFO_WP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_FIFO_RESERVED_MASK 0xfffc0000
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_FIFO_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_FIFO_RESERVED_BITS 14
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_FIFO_RESERVED_SHIFT 18
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_FIFO_ALL_MASK 0x3ffff
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_FIFO_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_FIFO_ALL_BITS 18
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_FIFO_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_FIFO_ALL_MASK 0x3ffff
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_FIFO_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_FIFO_ALL_BITS 18
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_FIFO_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_FIFO_DATAMASK 0x0003ffff
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_FIFO_RDWRMASK 0xfffc0000
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_FIFO_RESETVALUE 0x00000
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_RCMD_ID 0x1023c904
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_RCMD_ID_BASE 0x904
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_RCMD_ID_ID8_MASK 0xfc0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_RCMD_ID_ID8_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_RCMD_ID_ID8_BITS 6
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_RCMD_ID_ID8_SHIFT 6
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_RCMD_ID_ID8_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_RCMD_ID_ID4_MASK 0x3f
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_RCMD_ID_ID4_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_RCMD_ID_ID4_BITS 6
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_RCMD_ID_ID4_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_RCMD_ID_ID4_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_RCMD_ID_RESERVED_MASK 0xfffff000
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_RCMD_ID_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_RCMD_ID_RESERVED_BITS 20
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_RCMD_ID_RESERVED_SHIFT 12
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_RCMD_ID_ALL_MASK 0xfff
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_RCMD_ID_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_RCMD_ID_ALL_BITS 12
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_RCMD_ID_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_RCMD_ID_ALL_MASK 0xfff
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_RCMD_ID_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_RCMD_ID_ALL_BITS 12
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_RCMD_ID_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_RCMD_ID_DATAMASK 0x00000fff
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_RCMD_ID_RDWRMASK 0xfffff000
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_RCMD_ID_RESETVALUE 0x000
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_ERR1 0x1023c908
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_ERR1_BASE 0x908
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_ERR1_NXT_RCMD_FIFO_WDATA1_MASK 0x7f800000
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_ERR1_NXT_RCMD_FIFO_WDATA1_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_ERR1_NXT_RCMD_FIFO_WDATA1_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_ERR1_NXT_RCMD_FIFO_WDATA1_SHIFT 23
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_ERR1_NXT_RCMD_FIFO_WDATA1_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_ERR1_NXT_RCMD_FIFO_WDATA0_MASK 0x7f8000
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_ERR1_NXT_RCMD_FIFO_WDATA0_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_ERR1_NXT_RCMD_FIFO_WDATA0_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_ERR1_NXT_RCMD_FIFO_WDATA0_SHIFT 15
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_ERR1_NXT_RCMD_FIFO_WDATA0_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_ERR1_NXT_RCMD_FIFO_WR1_MASK 0x4000
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_ERR1_NXT_RCMD_FIFO_WR1_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_ERR1_NXT_RCMD_FIFO_WR1_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_ERR1_NXT_RCMD_FIFO_WR1_SHIFT 14
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_ERR1_NXT_RCMD_FIFO_WR1_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_ERR1_NXT_RCMD_FIFO_WR0_MASK 0x2000
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_ERR1_NXT_RCMD_FIFO_WR0_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_ERR1_NXT_RCMD_FIFO_WR0_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_ERR1_NXT_RCMD_FIFO_WR0_SHIFT 13
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_ERR1_NXT_RCMD_FIFO_WR0_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_ERR1_NXT_RD_EN_UI23_MASK 0x1000
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_ERR1_NXT_RD_EN_UI23_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_ERR1_NXT_RD_EN_UI23_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_ERR1_NXT_RD_EN_UI23_SHIFT 12
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_ERR1_NXT_RD_EN_UI23_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_ERR1_NXT_RD_EN_UI01_MASK 0x800
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_ERR1_NXT_RD_EN_UI01_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_ERR1_NXT_RD_EN_UI01_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_ERR1_NXT_RD_EN_UI01_SHIFT 11
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_ERR1_NXT_RD_EN_UI01_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_ERR1_NXT_STATE_MASK 0x600
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_ERR1_NXT_STATE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_ERR1_NXT_STATE_BITS 2
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_ERR1_NXT_STATE_SHIFT 9
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_ERR1_NXT_STATE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_ERR1_RCMD_PAIR_MASK 0x1e0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_ERR1_RCMD_PAIR_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_ERR1_RCMD_PAIR_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_ERR1_RCMD_PAIR_SHIFT 5
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_ERR1_RCMD_PAIR_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_ERR1_RD_EN_UI23_MASK 0x10
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_ERR1_RD_EN_UI23_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_ERR1_RD_EN_UI23_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_ERR1_RD_EN_UI23_SHIFT 4
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_ERR1_RD_EN_UI23_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_ERR1_RD_EN_UI01_MASK 0x8
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_ERR1_RD_EN_UI01_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_ERR1_RD_EN_UI01_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_ERR1_RD_EN_UI01_SHIFT 3
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_ERR1_RD_EN_UI01_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_ERR1_STATE_MASK 0x6
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_ERR1_STATE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_ERR1_STATE_BITS 2
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_ERR1_STATE_SHIFT 1
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_ERR1_STATE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_ERR1_ERROR_MASK 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_ERR1_ERROR_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_ERR1_ERROR_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_ERR1_ERROR_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_ERR1_ERROR_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_ERR1_ALL_MASK 0x7fffffff
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_ERR1_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_ERR1_ALL_BITS 31
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_ERR1_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_ERR1_ALL_MASK 0x7fffffff
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_ERR1_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_ERR1_ALL_BITS 31
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_ERR1_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_ERR1_DATAMASK 0x7fffffff
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_ERR1_RDWRMASK 0x80000000
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_ERR1_RESETVALUE 0x00000000
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_ERR2 0x1023c90c
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_ERR2_BASE 0x90c
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_ERR2_NXT_RCMD_FIFO_WDATA1_MASK 0x7f800000
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_ERR2_NXT_RCMD_FIFO_WDATA1_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_ERR2_NXT_RCMD_FIFO_WDATA1_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_ERR2_NXT_RCMD_FIFO_WDATA1_SHIFT 23
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_ERR2_NXT_RCMD_FIFO_WDATA1_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_ERR2_NXT_RCMD_FIFO_WDATA0_MASK 0x7f8000
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_ERR2_NXT_RCMD_FIFO_WDATA0_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_ERR2_NXT_RCMD_FIFO_WDATA0_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_ERR2_NXT_RCMD_FIFO_WDATA0_SHIFT 15
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_ERR2_NXT_RCMD_FIFO_WDATA0_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_ERR2_NXT_RCMD_FIFO_WR1_MASK 0x4000
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_ERR2_NXT_RCMD_FIFO_WR1_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_ERR2_NXT_RCMD_FIFO_WR1_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_ERR2_NXT_RCMD_FIFO_WR1_SHIFT 14
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_ERR2_NXT_RCMD_FIFO_WR1_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_ERR2_NXT_RCMD_FIFO_WR0_MASK 0x2000
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_ERR2_NXT_RCMD_FIFO_WR0_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_ERR2_NXT_RCMD_FIFO_WR0_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_ERR2_NXT_RCMD_FIFO_WR0_SHIFT 13
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_ERR2_NXT_RCMD_FIFO_WR0_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_ERR2_NXT_RD_EN_UI23_MASK 0x1000
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_ERR2_NXT_RD_EN_UI23_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_ERR2_NXT_RD_EN_UI23_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_ERR2_NXT_RD_EN_UI23_SHIFT 12
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_ERR2_NXT_RD_EN_UI23_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_ERR2_NXT_RD_EN_UI01_MASK 0x800
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_ERR2_NXT_RD_EN_UI01_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_ERR2_NXT_RD_EN_UI01_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_ERR2_NXT_RD_EN_UI01_SHIFT 11
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_ERR2_NXT_RD_EN_UI01_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_ERR2_NXT_STATE_MASK 0x600
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_ERR2_NXT_STATE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_ERR2_NXT_STATE_BITS 2
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_ERR2_NXT_STATE_SHIFT 9
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_ERR2_NXT_STATE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_ERR2_RCMD_PAIR_MASK 0x1e0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_ERR2_RCMD_PAIR_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_ERR2_RCMD_PAIR_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_ERR2_RCMD_PAIR_SHIFT 5
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_ERR2_RCMD_PAIR_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_ERR2_RD_EN_UI23_MASK 0x10
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_ERR2_RD_EN_UI23_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_ERR2_RD_EN_UI23_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_ERR2_RD_EN_UI23_SHIFT 4
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_ERR2_RD_EN_UI23_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_ERR2_RD_EN_UI01_MASK 0x8
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_ERR2_RD_EN_UI01_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_ERR2_RD_EN_UI01_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_ERR2_RD_EN_UI01_SHIFT 3
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_ERR2_RD_EN_UI01_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_ERR2_STATE_MASK 0x6
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_ERR2_STATE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_ERR2_STATE_BITS 2
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_ERR2_STATE_SHIFT 1
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_ERR2_STATE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_ERR2_ERROR_MASK 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_ERR2_ERROR_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_ERR2_ERROR_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_ERR2_ERROR_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_ERR2_ERROR_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_ERR2_ALL_MASK 0x7fffffff
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_ERR2_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_ERR2_ALL_BITS 31
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_ERR2_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_ERR2_ALL_MASK 0x7fffffff
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_ERR2_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_ERR2_ALL_BITS 31
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_ERR2_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_ERR2_DATAMASK 0x7fffffff
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_ERR2_RDWRMASK 0x80000000
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_ERR2_RESETVALUE 0x00000000
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_FIFO_POINTERS 0x1023c910
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_FIFO_POINTERS_BASE 0x910
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_FIFO_POINTERS_RDATA_RP_MASK 0xf00000
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_FIFO_POINTERS_RDATA_RP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_FIFO_POINTERS_RDATA_RP_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_FIFO_POINTERS_RDATA_RP_SHIFT 20
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_FIFO_POINTERS_RDATA_RP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_FIFO_POINTERS_RDATA_WP_MASK 0xf0000
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_FIFO_POINTERS_RDATA_WP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_FIFO_POINTERS_RDATA_WP_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_FIFO_POINTERS_RDATA_WP_SHIFT 16
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_FIFO_POINTERS_RDATA_WP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_FIFO_POINTERS_EDC_VALID_RP_MASK 0xf000
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_FIFO_POINTERS_EDC_VALID_RP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_FIFO_POINTERS_EDC_VALID_RP_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_FIFO_POINTERS_EDC_VALID_RP_SHIFT 12
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_FIFO_POINTERS_EDC_VALID_RP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_FIFO_POINTERS_EDC_VALID_WP_MASK 0xf00
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_FIFO_POINTERS_EDC_VALID_WP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_FIFO_POINTERS_EDC_VALID_WP_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_FIFO_POINTERS_EDC_VALID_WP_SHIFT 8
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_FIFO_POINTERS_EDC_VALID_WP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_FIFO_POINTERS_DATA_VALID_RP_MASK 0xf0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_FIFO_POINTERS_DATA_VALID_RP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_FIFO_POINTERS_DATA_VALID_RP_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_FIFO_POINTERS_DATA_VALID_RP_SHIFT 4
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_FIFO_POINTERS_DATA_VALID_RP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_FIFO_POINTERS_DATA_VALID_WP_MASK 0xf
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_FIFO_POINTERS_DATA_VALID_WP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_FIFO_POINTERS_DATA_VALID_WP_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_FIFO_POINTERS_DATA_VALID_WP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_FIFO_POINTERS_DATA_VALID_WP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_FIFO_POINTERS_RESERVED_MASK 0xff000000
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_FIFO_POINTERS_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_FIFO_POINTERS_RESERVED_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_FIFO_POINTERS_RESERVED_SHIFT 24
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_FIFO_POINTERS_ALL_MASK 0xffffff
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_FIFO_POINTERS_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_FIFO_POINTERS_ALL_BITS 24
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_FIFO_POINTERS_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_FIFO_POINTERS_ALL_MASK 0xffffff
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_FIFO_POINTERS_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_FIFO_POINTERS_ALL_BITS 24
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_FIFO_POINTERS_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_FIFO_POINTERS_DATAMASK 0x00ffffff
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_FIFO_POINTERS_RDWRMASK 0xff000000
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_FIFO_POINTERS_RESETVALUE 0x000000
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB 0x1023c914
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_BASE 0x914
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_RCMD_4_MASK 0xff000000
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_RCMD_4_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_RCMD_4_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_RCMD_4_SHIFT 24
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_RCMD_4_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_RCMD_3_MASK 0xff0000
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_RCMD_3_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_RCMD_3_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_RCMD_3_SHIFT 16
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_RCMD_3_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_RCMD_2_MASK 0xff00
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_RCMD_2_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_RCMD_2_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_RCMD_2_SHIFT 8
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_RCMD_2_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_RCMD_1_MASK 0xff
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_RCMD_1_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_RCMD_1_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_RCMD_1_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_RCMD_1_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_ALL_MASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_ALL_BITS 32
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_ALL_MASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_ALL_BITS 32
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_DATAMASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_RDWRMASK 0x00000000
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_RESETVALUE 0x00000000
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB 0x1023c918
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_BASE 0x918
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_RCMD_8_MASK 0xff000000
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_RCMD_8_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_RCMD_8_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_RCMD_8_SHIFT 24
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_RCMD_8_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_RCMD_7_MASK 0xff0000
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_RCMD_7_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_RCMD_7_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_RCMD_7_SHIFT 16
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_RCMD_7_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_RCMD_6_MASK 0xff00
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_RCMD_6_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_RCMD_6_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_RCMD_6_SHIFT 8
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_RCMD_6_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_RCMD_5_MASK 0xff
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_RCMD_5_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_RCMD_5_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_RCMD_5_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_RCMD_5_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_ALL_MASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_ALL_BITS 32
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_ALL_MASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_ALL_BITS 32
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_DATAMASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_RDWRMASK 0x00000000
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_RESETVALUE 0x00000000
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES 0x1023c91c
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_BASE 0x91c
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_7_MASK 0xf0000000
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_7_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_7_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_7_SHIFT 28
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_7_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_6_MASK 0xf000000
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_6_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_6_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_6_SHIFT 24
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_6_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_5_MASK 0xf00000
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_5_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_5_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_5_SHIFT 20
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_5_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_4_MASK 0xf0000
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_4_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_4_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_4_SHIFT 16
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_4_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_3_MASK 0xf000
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_3_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_3_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_3_SHIFT 12
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_3_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_2_MASK 0xf00
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_2_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_2_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_2_SHIFT 8
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_2_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_1_MASK 0xf0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_1_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_1_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_1_SHIFT 4
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_1_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_0_MASK 0xf
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_0_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_0_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_0_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_0_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_ALL_MASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_ALL_BITS 32
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_ALL_MASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_ALL_BITS 32
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_DATAMASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_RDWRMASK 0x00000000
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_RESETVALUE 0x00000000
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS 0x1023c920
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_BASE 0x920
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_7_MASK 0xf0000000
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_7_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_7_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_7_SHIFT 28
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_7_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_6_MASK 0xf000000
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_6_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_6_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_6_SHIFT 24
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_6_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_5_MASK 0xf00000
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_5_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_5_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_5_SHIFT 20
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_5_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_4_MASK 0xf0000
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_4_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_4_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_4_SHIFT 16
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_4_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_3_MASK 0xf000
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_3_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_3_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_3_SHIFT 12
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_3_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_2_MASK 0xf00
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_2_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_2_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_2_SHIFT 8
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_2_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_1_MASK 0xf0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_1_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_1_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_1_SHIFT 4
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_1_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_0_MASK 0xf
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_0_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_0_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_0_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_0_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_ALL_MASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_ALL_BITS 32
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_ALL_MASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_ALL_BITS 32
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_DATAMASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_RDWRMASK 0x00000000
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_RESETVALUE 0x00000000
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR 0x1023c924
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_BASE 0x924
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STICKY_ERROR_MASK 0xf0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STICKY_ERROR_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STICKY_ERROR_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STICKY_ERROR_SHIFT 4
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STICKY_ERROR_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_CURRENT_ERROR_MASK 0xf
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_CURRENT_ERROR_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_CURRENT_ERROR_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_CURRENT_ERROR_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_CURRENT_ERROR_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RESERVED_MASK 0xffffff00
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RESERVED_BITS 24
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RESERVED_SHIFT 8
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_ALL_MASK 0xff
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_ALL_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_ALL_MASK 0xff
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_ALL_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_DATAMASK 0x000000ff
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RDWRMASK 0xffffff00
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB 0x1023c928
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_BASE 0x928
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_RCMD_4_MASK 0xff000000
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_RCMD_4_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_RCMD_4_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_RCMD_4_SHIFT 24
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_RCMD_4_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_RCMD_3_MASK 0xff0000
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_RCMD_3_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_RCMD_3_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_RCMD_3_SHIFT 16
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_RCMD_3_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_RCMD_2_MASK 0xff00
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_RCMD_2_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_RCMD_2_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_RCMD_2_SHIFT 8
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_RCMD_2_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_RCMD_1_MASK 0xff
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_RCMD_1_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_RCMD_1_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_RCMD_1_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_RCMD_1_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_ALL_MASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_ALL_BITS 32
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_ALL_MASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_ALL_BITS 32
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_DATAMASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_RDWRMASK 0x00000000
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_RESETVALUE 0x00000000
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB 0x1023c92c
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_BASE 0x92c
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_RCMD_8_MASK 0xff000000
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_RCMD_8_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_RCMD_8_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_RCMD_8_SHIFT 24
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_RCMD_8_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_RCMD_7_MASK 0xff0000
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_RCMD_7_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_RCMD_7_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_RCMD_7_SHIFT 16
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_RCMD_7_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_RCMD_6_MASK 0xff00
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_RCMD_6_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_RCMD_6_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_RCMD_6_SHIFT 8
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_RCMD_6_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_RCMD_5_MASK 0xff
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_RCMD_5_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_RCMD_5_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_RCMD_5_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_RCMD_5_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_ALL_MASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_ALL_BITS 32
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_ALL_MASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_ALL_BITS 32
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_DATAMASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_RDWRMASK 0x00000000
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_RESETVALUE 0x00000000
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES 0x1023c930
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_BASE 0x930
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_7_MASK 0xf0000000
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_7_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_7_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_7_SHIFT 28
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_7_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_6_MASK 0xf000000
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_6_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_6_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_6_SHIFT 24
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_6_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_5_MASK 0xf00000
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_5_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_5_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_5_SHIFT 20
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_5_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_4_MASK 0xf0000
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_4_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_4_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_4_SHIFT 16
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_4_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_3_MASK 0xf000
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_3_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_3_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_3_SHIFT 12
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_3_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_2_MASK 0xf00
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_2_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_2_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_2_SHIFT 8
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_2_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_1_MASK 0xf0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_1_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_1_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_1_SHIFT 4
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_1_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_0_MASK 0xf
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_0_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_0_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_0_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_0_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_ALL_MASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_ALL_BITS 32
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_ALL_MASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_ALL_BITS 32
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_DATAMASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_RDWRMASK 0x00000000
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_RESETVALUE 0x00000000
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS 0x1023c934
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_BASE 0x934
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_7_MASK 0xf0000000
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_7_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_7_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_7_SHIFT 28
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_7_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_6_MASK 0xf000000
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_6_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_6_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_6_SHIFT 24
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_6_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_5_MASK 0xf00000
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_5_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_5_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_5_SHIFT 20
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_5_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_4_MASK 0xf0000
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_4_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_4_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_4_SHIFT 16
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_4_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_3_MASK 0xf000
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_3_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_3_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_3_SHIFT 12
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_3_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_2_MASK 0xf00
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_2_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_2_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_2_SHIFT 8
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_2_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_1_MASK 0xf0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_1_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_1_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_1_SHIFT 4
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_1_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_0_MASK 0xf
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_0_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_0_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_0_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_0_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_ALL_MASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_ALL_BITS 32
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_ALL_MASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_ALL_BITS 32
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_DATAMASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_RDWRMASK 0x00000000
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_RESETVALUE 0x00000000
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_WRITE_LEVELING 0x1023c938
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_WRITE_LEVELING_BASE 0x938
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_WRITE_LEVELING_DQS_MASK 0x400
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_WRITE_LEVELING_DQS_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_WRITE_LEVELING_DQS_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_WRITE_LEVELING_DQS_SHIFT 10
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_WRITE_LEVELING_DQS_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_WRITE_LEVELING_EDC_MASK 0x200
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_WRITE_LEVELING_EDC_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_WRITE_LEVELING_EDC_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_WRITE_LEVELING_EDC_SHIFT 9
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_WRITE_LEVELING_EDC_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_WRITE_LEVELING_DBI_MASK 0x100
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_WRITE_LEVELING_DBI_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_WRITE_LEVELING_DBI_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_WRITE_LEVELING_DBI_SHIFT 8
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_WRITE_LEVELING_DBI_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_WRITE_LEVELING_DATA_MASK 0xff
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_WRITE_LEVELING_DATA_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_WRITE_LEVELING_DATA_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_WRITE_LEVELING_DATA_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_WRITE_LEVELING_DATA_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_WRITE_LEVELING_RESERVED_MASK 0xfffff800
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_WRITE_LEVELING_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_WRITE_LEVELING_RESERVED_BITS 21
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_WRITE_LEVELING_RESERVED_SHIFT 11
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_WRITE_LEVELING_ALL_MASK 0x7ff
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_WRITE_LEVELING_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_WRITE_LEVELING_ALL_BITS 11
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_WRITE_LEVELING_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_WRITE_LEVELING_ALL_MASK 0x7ff
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_WRITE_LEVELING_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_WRITE_LEVELING_ALL_BITS 11
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_WRITE_LEVELING_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_WRITE_LEVELING_DATAMASK 0x000007ff
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_WRITE_LEVELING_RDWRMASK 0xfffff800
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_WRITE_LEVELING_RESETVALUE 0x000
 #define SJC16_DDR4_PHY_DQ_BYTE2_MACRO_RESERVED_REG 0x1023c93c
 #define SJC16_DDR4_PHY_DQ_BYTE2_MACRO_RESERVED_REG_BASE 0x93c
 #define SJC16_DDR4_PHY_DQ_BYTE2_MACRO_RESERVED_REG_RESERVED_MASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE2_MACRO_RESERVED_REG_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_MACRO_RESERVED_REG_RESERVED_BITS 32
 #define SJC16_DDR4_PHY_DQ_BYTE2_MACRO_RESERVED_REG_RESERVED_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_MACRO_RESERVED_REG_RESERVED_RESETVALUE 0x00000000
 #define SJC16_DDR4_PHY_DQ_BYTE2_MACRO_RESERVED_REG_ALL_MASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE2_MACRO_RESERVED_REG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_MACRO_RESERVED_REG_ALL_BITS 32
 #define SJC16_DDR4_PHY_DQ_BYTE2_MACRO_RESERVED_REG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_MACRO_RESERVED_REG_ALL_MASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE2_MACRO_RESERVED_REG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_MACRO_RESERVED_REG_ALL_BITS 32
 #define SJC16_DDR4_PHY_DQ_BYTE2_MACRO_RESERVED_REG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_MACRO_RESERVED_REG_DATAMASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE2_MACRO_RESERVED_REG_RDWRMASK 0x00000000
 #define SJC16_DDR4_PHY_DQ_BYTE2_MACRO_RESERVED_REG_RESETVALUE 0x00000000
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_MACRO_RESERVED 0x1023c940
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_MACRO_RESERVED_BASE 0x940
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_MACRO_RESERVED_RESERVED_MASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_MACRO_RESERVED_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_MACRO_RESERVED_RESERVED_BITS 32
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_MACRO_RESERVED_RESERVED_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_MACRO_RESERVED_RESERVED_RESETVALUE 0x00000000
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_MACRO_RESERVED_ALL_MASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_MACRO_RESERVED_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_MACRO_RESERVED_ALL_BITS 32
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_MACRO_RESERVED_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_MACRO_RESERVED_ALL_MASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_MACRO_RESERVED_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_MACRO_RESERVED_ALL_BITS 32
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_MACRO_RESERVED_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_MACRO_RESERVED_DATAMASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_MACRO_RESERVED_RDWRMASK 0x00000000
 #define SJC16_DDR4_PHY_DQ_BYTE2_STATUS_MACRO_RESERVED_RESETVALUE 0x00000000
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT0 0x1023cc00
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT0_BASE 0xc00
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT0_MIN_VDL_STEP_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT0_MIN_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT0_MIN_VDL_STEP_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT0_MIN_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT0_MIN_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT0_RESERVED_MASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT0_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT0_RESERVED_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT0_RESERVED_SHIFT 7
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT0_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT0_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT0_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT0_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT0_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT0_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT0_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT0_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT0_DATAMASK 0x0000007f
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT0_RDWRMASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT0_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT1 0x1023cc04
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT1_BASE 0xc04
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT1_MIN_VDL_STEP_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT1_MIN_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT1_MIN_VDL_STEP_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT1_MIN_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT1_MIN_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT1_RESERVED_MASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT1_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT1_RESERVED_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT1_RESERVED_SHIFT 7
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT1_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT1_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT1_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT1_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT1_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT1_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT1_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT1_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT1_DATAMASK 0x0000007f
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT1_RDWRMASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT1_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT2 0x1023cc08
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT2_BASE 0xc08
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT2_MIN_VDL_STEP_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT2_MIN_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT2_MIN_VDL_STEP_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT2_MIN_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT2_MIN_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT2_RESERVED_MASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT2_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT2_RESERVED_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT2_RESERVED_SHIFT 7
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT2_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT2_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT2_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT2_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT2_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT2_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT2_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT2_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT2_DATAMASK 0x0000007f
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT2_RDWRMASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT2_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT3 0x1023cc0c
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT3_BASE 0xc0c
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT3_MIN_VDL_STEP_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT3_MIN_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT3_MIN_VDL_STEP_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT3_MIN_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT3_MIN_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT3_RESERVED_MASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT3_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT3_RESERVED_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT3_RESERVED_SHIFT 7
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT3_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT3_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT3_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT3_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT3_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT3_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT3_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT3_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT3_DATAMASK 0x0000007f
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT3_RDWRMASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT3_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT4 0x1023cc10
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT4_BASE 0xc10
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT4_MIN_VDL_STEP_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT4_MIN_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT4_MIN_VDL_STEP_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT4_MIN_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT4_MIN_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT4_RESERVED_MASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT4_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT4_RESERVED_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT4_RESERVED_SHIFT 7
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT4_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT4_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT4_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT4_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT4_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT4_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT4_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT4_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT4_DATAMASK 0x0000007f
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT4_RDWRMASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT4_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT5 0x1023cc14
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT5_BASE 0xc14
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT5_MIN_VDL_STEP_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT5_MIN_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT5_MIN_VDL_STEP_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT5_MIN_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT5_MIN_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT5_RESERVED_MASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT5_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT5_RESERVED_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT5_RESERVED_SHIFT 7
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT5_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT5_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT5_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT5_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT5_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT5_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT5_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT5_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT5_DATAMASK 0x0000007f
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT5_RDWRMASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT5_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT6 0x1023cc18
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT6_BASE 0xc18
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT6_MIN_VDL_STEP_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT6_MIN_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT6_MIN_VDL_STEP_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT6_MIN_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT6_MIN_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT6_RESERVED_MASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT6_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT6_RESERVED_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT6_RESERVED_SHIFT 7
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT6_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT6_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT6_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT6_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT6_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT6_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT6_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT6_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT6_DATAMASK 0x0000007f
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT6_RDWRMASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT6_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT7 0x1023cc1c
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT7_BASE 0xc1c
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT7_MIN_VDL_STEP_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT7_MIN_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT7_MIN_VDL_STEP_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT7_MIN_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT7_MIN_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT7_RESERVED_MASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT7_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT7_RESERVED_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT7_RESERVED_SHIFT 7
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT7_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT7_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT7_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT7_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT7_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT7_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT7_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT7_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT7_DATAMASK 0x0000007f
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT7_RDWRMASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT7_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_DBI 0x1023cc20
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_DBI_BASE 0xc20
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_DBI_MIN_VDL_STEP_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_DBI_MIN_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_DBI_MIN_VDL_STEP_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_DBI_MIN_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_DBI_MIN_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_DBI_RESERVED_MASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_DBI_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_DBI_RESERVED_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_DBI_RESERVED_SHIFT 7
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_DBI_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_DBI_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_DBI_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_DBI_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_DBI_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_DBI_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_DBI_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_DBI_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_DBI_DATAMASK 0x0000007f
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_DBI_RDWRMASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_DBI_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_EDC 0x1023cc24
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_EDC_BASE 0xc24
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_EDC_MIN_VDL_STEP_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_EDC_MIN_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_EDC_MIN_VDL_STEP_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_EDC_MIN_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_EDC_MIN_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_EDC_RESERVED_MASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_EDC_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_EDC_RESERVED_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_EDC_RESERVED_SHIFT 7
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_EDC_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_EDC_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_EDC_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_EDC_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_EDC_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_EDC_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_EDC_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_EDC_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_EDC_DATAMASK 0x0000007f
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_EDC_RDWRMASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_EDC_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MAX_VDL_DATA 0x1023cc28
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MAX_VDL_DATA_BASE 0xc28
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MAX_VDL_DATA_UI_SHIFT_MASK 0xe00
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MAX_VDL_DATA_UI_SHIFT_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MAX_VDL_DATA_UI_SHIFT_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MAX_VDL_DATA_UI_SHIFT_SHIFT 9
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MAX_VDL_DATA_UI_SHIFT_RESETVALUE 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MAX_VDL_DATA_MAX_VDL_STEP_MASK 0x1ff
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MAX_VDL_DATA_MAX_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MAX_VDL_DATA_MAX_VDL_STEP_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MAX_VDL_DATA_MAX_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MAX_VDL_DATA_MAX_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MAX_VDL_DATA_RESERVED_MASK 0xfffff000
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MAX_VDL_DATA_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MAX_VDL_DATA_RESERVED_BITS 20
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MAX_VDL_DATA_RESERVED_SHIFT 12
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MAX_VDL_DATA_ALL_MASK 0xfff
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MAX_VDL_DATA_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MAX_VDL_DATA_ALL_BITS 12
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MAX_VDL_DATA_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MAX_VDL_DATA_ALL_MASK 0xfff
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MAX_VDL_DATA_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MAX_VDL_DATA_ALL_BITS 12
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MAX_VDL_DATA_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MAX_VDL_DATA_DATAMASK 0x00000fff
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MAX_VDL_DATA_RDWRMASK 0xfffff000
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MAX_VDL_DATA_RESETVALUE 0x200
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MAX_VDL_DATA_SHADOW 0x1023cc2c
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MAX_VDL_DATA_SHADOW_BASE 0xc2c
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MAX_VDL_DATA_SHADOW_UI_SHIFT_MASK 0xe00
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MAX_VDL_DATA_SHADOW_UI_SHIFT_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MAX_VDL_DATA_SHADOW_UI_SHIFT_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MAX_VDL_DATA_SHADOW_UI_SHIFT_SHIFT 9
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MAX_VDL_DATA_SHADOW_UI_SHIFT_RESETVALUE 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MAX_VDL_DATA_SHADOW_MAX_VDL_STEP_MASK 0x1ff
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MAX_VDL_DATA_SHADOW_MAX_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MAX_VDL_DATA_SHADOW_MAX_VDL_STEP_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MAX_VDL_DATA_SHADOW_MAX_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MAX_VDL_DATA_SHADOW_MAX_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MAX_VDL_DATA_SHADOW_RESERVED_MASK 0xfffff000
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MAX_VDL_DATA_SHADOW_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MAX_VDL_DATA_SHADOW_RESERVED_BITS 20
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MAX_VDL_DATA_SHADOW_RESERVED_SHIFT 12
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MAX_VDL_DATA_SHADOW_ALL_MASK 0xfff
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MAX_VDL_DATA_SHADOW_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MAX_VDL_DATA_SHADOW_ALL_BITS 12
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MAX_VDL_DATA_SHADOW_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MAX_VDL_DATA_SHADOW_ALL_MASK 0xfff
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MAX_VDL_DATA_SHADOW_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MAX_VDL_DATA_SHADOW_ALL_BITS 12
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MAX_VDL_DATA_SHADOW_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MAX_VDL_DATA_SHADOW_DATAMASK 0x00000fff
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MAX_VDL_DATA_SHADOW_RDWRMASK 0xfffff000
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MAX_VDL_DATA_SHADOW_RESETVALUE 0x200
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MAX_VDL_DQS 0x1023cc30
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MAX_VDL_DQS_BASE 0xc30
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MAX_VDL_DQS_UI_SHIFT_MASK 0xe00
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MAX_VDL_DQS_UI_SHIFT_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MAX_VDL_DQS_UI_SHIFT_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MAX_VDL_DQS_UI_SHIFT_SHIFT 9
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MAX_VDL_DQS_UI_SHIFT_RESETVALUE 0x2
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MAX_VDL_DQS_MAX_VDL_STEP_MASK 0x1ff
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MAX_VDL_DQS_MAX_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MAX_VDL_DQS_MAX_VDL_STEP_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MAX_VDL_DQS_MAX_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MAX_VDL_DQS_MAX_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MAX_VDL_DQS_RESERVED_MASK 0xfffff000
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MAX_VDL_DQS_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MAX_VDL_DQS_RESERVED_BITS 20
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MAX_VDL_DQS_RESERVED_SHIFT 12
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MAX_VDL_DQS_ALL_MASK 0xfff
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MAX_VDL_DQS_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MAX_VDL_DQS_ALL_BITS 12
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MAX_VDL_DQS_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MAX_VDL_DQS_ALL_MASK 0xfff
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MAX_VDL_DQS_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MAX_VDL_DQS_ALL_BITS 12
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MAX_VDL_DQS_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MAX_VDL_DQS_DATAMASK 0x00000fff
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MAX_VDL_DQS_RDWRMASK 0xfffff000
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_MAX_VDL_DQS_RESETVALUE 0x400
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT0 0x1023cc34
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT0_BASE 0xc34
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT0_MIN_VDL_STEP_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT0_MIN_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT0_MIN_VDL_STEP_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT0_MIN_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT0_MIN_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT0_RESERVED_MASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT0_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT0_RESERVED_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT0_RESERVED_SHIFT 7
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT0_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT0_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT0_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT0_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT0_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT0_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT0_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT0_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT0_DATAMASK 0x0000007f
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT0_RDWRMASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT0_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT1 0x1023cc38
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT1_BASE 0xc38
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT1_MIN_VDL_STEP_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT1_MIN_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT1_MIN_VDL_STEP_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT1_MIN_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT1_MIN_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT1_RESERVED_MASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT1_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT1_RESERVED_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT1_RESERVED_SHIFT 7
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT1_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT1_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT1_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT1_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT1_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT1_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT1_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT1_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT1_DATAMASK 0x0000007f
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT1_RDWRMASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT1_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT2 0x1023cc3c
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT2_BASE 0xc3c
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT2_MIN_VDL_STEP_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT2_MIN_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT2_MIN_VDL_STEP_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT2_MIN_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT2_MIN_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT2_RESERVED_MASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT2_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT2_RESERVED_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT2_RESERVED_SHIFT 7
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT2_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT2_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT2_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT2_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT2_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT2_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT2_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT2_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT2_DATAMASK 0x0000007f
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT2_RDWRMASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT2_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT3 0x1023cc40
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT3_BASE 0xc40
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT3_MIN_VDL_STEP_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT3_MIN_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT3_MIN_VDL_STEP_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT3_MIN_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT3_MIN_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT3_RESERVED_MASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT3_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT3_RESERVED_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT3_RESERVED_SHIFT 7
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT3_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT3_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT3_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT3_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT3_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT3_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT3_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT3_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT3_DATAMASK 0x0000007f
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT3_RDWRMASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT3_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT4 0x1023cc44
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT4_BASE 0xc44
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT4_MIN_VDL_STEP_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT4_MIN_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT4_MIN_VDL_STEP_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT4_MIN_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT4_MIN_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT4_RESERVED_MASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT4_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT4_RESERVED_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT4_RESERVED_SHIFT 7
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT4_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT4_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT4_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT4_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT4_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT4_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT4_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT4_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT4_DATAMASK 0x0000007f
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT4_RDWRMASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT4_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT5 0x1023cc48
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT5_BASE 0xc48
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT5_MIN_VDL_STEP_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT5_MIN_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT5_MIN_VDL_STEP_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT5_MIN_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT5_MIN_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT5_RESERVED_MASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT5_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT5_RESERVED_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT5_RESERVED_SHIFT 7
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT5_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT5_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT5_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT5_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT5_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT5_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT5_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT5_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT5_DATAMASK 0x0000007f
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT5_RDWRMASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT5_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT6 0x1023cc4c
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT6_BASE 0xc4c
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT6_MIN_VDL_STEP_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT6_MIN_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT6_MIN_VDL_STEP_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT6_MIN_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT6_MIN_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT6_RESERVED_MASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT6_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT6_RESERVED_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT6_RESERVED_SHIFT 7
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT6_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT6_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT6_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT6_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT6_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT6_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT6_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT6_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT6_DATAMASK 0x0000007f
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT6_RDWRMASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT6_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT7 0x1023cc50
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT7_BASE 0xc50
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT7_MIN_VDL_STEP_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT7_MIN_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT7_MIN_VDL_STEP_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT7_MIN_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT7_MIN_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT7_RESERVED_MASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT7_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT7_RESERVED_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT7_RESERVED_SHIFT 7
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT7_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT7_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT7_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT7_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT7_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT7_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT7_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT7_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT7_DATAMASK 0x0000007f
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT7_RDWRMASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT7_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_DBI 0x1023cc54
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_DBI_BASE 0xc54
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_DBI_MIN_VDL_STEP_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_DBI_MIN_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_DBI_MIN_VDL_STEP_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_DBI_MIN_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_DBI_MIN_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_DBI_RESERVED_MASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_DBI_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_DBI_RESERVED_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_DBI_RESERVED_SHIFT 7
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_DBI_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_DBI_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_DBI_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_DBI_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_DBI_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_DBI_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_DBI_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_DBI_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_DBI_DATAMASK 0x0000007f
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_DBI_RDWRMASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_DBI_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_EDC 0x1023cc58
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_EDC_BASE 0xc58
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_EDC_MIN_VDL_STEP_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_EDC_MIN_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_EDC_MIN_VDL_STEP_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_EDC_MIN_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_EDC_MIN_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_EDC_RESERVED_MASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_EDC_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_EDC_RESERVED_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_EDC_RESERVED_SHIFT 7
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_EDC_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_EDC_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_EDC_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_EDC_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_EDC_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_EDC_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_EDC_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_EDC_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_EDC_DATAMASK 0x0000007f
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_EDC_RDWRMASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_EDC_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQS_MASTER_CTRL 0x1023cc5c
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQS_MASTER_CTRL_BASE 0xc5c
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQS_MASTER_CTRL_MASTER_MODE_MASK 0x10000
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQS_MASTER_CTRL_MASTER_MODE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQS_MASTER_CTRL_MASTER_MODE_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQS_MASTER_CTRL_MASTER_MODE_SHIFT 16
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQS_MASTER_CTRL_MASTER_MODE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQS_MASTER_CTRL_FORCE_UPDATE_MASK 0x1000
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQS_MASTER_CTRL_FORCE_UPDATE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQS_MASTER_CTRL_FORCE_UPDATE_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQS_MASTER_CTRL_FORCE_UPDATE_SHIFT 12
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQS_MASTER_CTRL_FORCE_UPDATE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQS_MASTER_CTRL_MAX_VDL_STEP_MASK 0x1ff
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQS_MASTER_CTRL_MAX_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQS_MASTER_CTRL_MAX_VDL_STEP_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQS_MASTER_CTRL_MAX_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQS_MASTER_CTRL_MAX_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQS_MASTER_CTRL_RESERVED_0_MASK 0xfffe0000
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQS_MASTER_CTRL_RESERVED_0_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQS_MASTER_CTRL_RESERVED_0_BITS 15
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQS_MASTER_CTRL_RESERVED_0_SHIFT 17
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQS_MASTER_CTRL_RESERVED_1_MASK 0xe000
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQS_MASTER_CTRL_RESERVED_1_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQS_MASTER_CTRL_RESERVED_1_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQS_MASTER_CTRL_RESERVED_1_SHIFT 13
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQS_MASTER_CTRL_RESERVED_2_MASK 0xe00
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQS_MASTER_CTRL_RESERVED_2_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQS_MASTER_CTRL_RESERVED_2_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQS_MASTER_CTRL_RESERVED_2_SHIFT 9
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQS_MASTER_CTRL_RESERVED_MASK 0xfffe0000
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQS_MASTER_CTRL_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQS_MASTER_CTRL_RESERVED_BITS 15
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQS_MASTER_CTRL_RESERVED_SHIFT 17
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQS_MASTER_CTRL_ALL_MASK 0x1ffff
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQS_MASTER_CTRL_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQS_MASTER_CTRL_ALL_BITS 17
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQS_MASTER_CTRL_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQS_MASTER_CTRL_ALL_MASK 0x1ffff
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQS_MASTER_CTRL_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQS_MASTER_CTRL_ALL_BITS 17
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQS_MASTER_CTRL_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQS_MASTER_CTRL_DATAMASK 0x000111ff
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQS_MASTER_CTRL_RDWRMASK 0xfffeee00
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQS_MASTER_CTRL_RESETVALUE 0x00000
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQSEP 0x1023cc60
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQSEP_BASE 0xc60
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQSEP_MAX_VDL_STEP_MASK 0x1ff
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQSEP_MAX_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQSEP_MAX_VDL_STEP_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQSEP_MAX_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQSEP_MAX_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQSEP_RESERVED_MASK 0xfffffe00
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQSEP_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQSEP_RESERVED_BITS 23
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQSEP_RESERVED_SHIFT 9
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQSEP_ALL_MASK 0x1ff
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQSEP_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQSEP_ALL_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQSEP_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQSEP_ALL_MASK 0x1ff
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQSEP_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQSEP_ALL_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQSEP_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQSEP_DATAMASK 0x000001ff
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQSEP_RDWRMASK 0xfffffe00
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQSEP_RESETVALUE 0x000
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQSDP 0x1023cc64
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQSDP_BASE 0xc64
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQSDP_MAX_VDL_STEP_MASK 0x1ff
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQSDP_MAX_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQSDP_MAX_VDL_STEP_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQSDP_MAX_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQSDP_MAX_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQSDP_RESERVED_MASK 0xfffffe00
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQSDP_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQSDP_RESERVED_BITS 23
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQSDP_RESERVED_SHIFT 9
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQSDP_ALL_MASK 0x1ff
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQSDP_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQSDP_ALL_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQSDP_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQSDP_ALL_MASK 0x1ff
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQSDP_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQSDP_ALL_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQSDP_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQSDP_DATAMASK 0x000001ff
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQSDP_RDWRMASK 0xfffffe00
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQSDP_RESETVALUE 0x000
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQSEN 0x1023cc68
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQSEN_BASE 0xc68
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQSEN_MAX_VDL_STEP_MASK 0x1ff
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQSEN_MAX_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQSEN_MAX_VDL_STEP_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQSEN_MAX_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQSEN_MAX_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQSEN_RESERVED_MASK 0xfffffe00
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQSEN_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQSEN_RESERVED_BITS 23
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQSEN_RESERVED_SHIFT 9
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQSEN_ALL_MASK 0x1ff
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQSEN_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQSEN_ALL_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQSEN_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQSEN_ALL_MASK 0x1ff
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQSEN_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQSEN_ALL_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQSEN_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQSEN_DATAMASK 0x000001ff
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQSEN_RDWRMASK 0xfffffe00
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQSEN_RESETVALUE 0x000
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQSDN 0x1023cc6c
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQSDN_BASE 0xc6c
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQSDN_MAX_VDL_STEP_MASK 0x1ff
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQSDN_MAX_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQSDN_MAX_VDL_STEP_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQSDN_MAX_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQSDN_MAX_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQSDN_RESERVED_MASK 0xfffffe00
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQSDN_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQSDN_RESERVED_BITS 23
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQSDN_RESERVED_SHIFT 9
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQSDN_ALL_MASK 0x1ff
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQSDN_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQSDN_ALL_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQSDN_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQSDN_ALL_MASK 0x1ff
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQSDN_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQSDN_ALL_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQSDN_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQSDN_DATAMASK 0x000001ff
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQSDN_RDWRMASK 0xfffffe00
 #define SJC16_DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQSDN_RESETVALUE 0x000
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_LEVELING_CONFIG 0x1023cc70
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_LEVELING_CONFIG_BASE 0xc70
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_LEVELING_CONFIG_WRITE_LEVELING_MODE_MASK 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_LEVELING_CONFIG_WRITE_LEVELING_MODE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_LEVELING_CONFIG_WRITE_LEVELING_MODE_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_LEVELING_CONFIG_WRITE_LEVELING_MODE_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_LEVELING_CONFIG_WRITE_LEVELING_MODE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_LEVELING_CONFIG_RESERVED_MASK 0xfffffffe
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_LEVELING_CONFIG_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_LEVELING_CONFIG_RESERVED_BITS 31
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_LEVELING_CONFIG_RESERVED_SHIFT 1
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_LEVELING_CONFIG_WRITE_LEVELING_MODE_MASK 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_LEVELING_CONFIG_WRITE_LEVELING_MODE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_LEVELING_CONFIG_WRITE_LEVELING_MODE_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_LEVELING_CONFIG_WRITE_LEVELING_MODE_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_LEVELING_CONFIG_WRITE_LEVELING_MODE_MASK 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_LEVELING_CONFIG_WRITE_LEVELING_MODE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_LEVELING_CONFIG_WRITE_LEVELING_MODE_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_LEVELING_CONFIG_WRITE_LEVELING_MODE_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_LEVELING_CONFIG_ALL_MASK 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_LEVELING_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_LEVELING_CONFIG_ALL_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_LEVELING_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_LEVELING_CONFIG_ALL_MASK 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_LEVELING_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_LEVELING_CONFIG_ALL_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_LEVELING_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_LEVELING_CONFIG_DATAMASK 0x00000001
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_LEVELING_CONFIG_RDWRMASK 0xfffffffe
 #define SJC16_DDR4_PHY_DQ_BYTE3_WRITE_LEVELING_CONFIG_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_REN_GEN_ERR_CTRL 0x1023cc74
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_REN_GEN_ERR_CTRL_BASE 0xc74
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_REN_GEN_ERR_CTRL_ERR2_CLEAR_MASK 0x2
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_REN_GEN_ERR_CTRL_ERR2_CLEAR_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_REN_GEN_ERR_CTRL_ERR2_CLEAR_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_REN_GEN_ERR_CTRL_ERR2_CLEAR_SHIFT 1
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_REN_GEN_ERR_CTRL_ERR2_CLEAR_RESETVALUE 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_REN_GEN_ERR_CTRL_ERR1_CLEAR_MASK 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_REN_GEN_ERR_CTRL_ERR1_CLEAR_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_REN_GEN_ERR_CTRL_ERR1_CLEAR_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_REN_GEN_ERR_CTRL_ERR1_CLEAR_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_REN_GEN_ERR_CTRL_ERR1_CLEAR_RESETVALUE 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_REN_GEN_ERR_CTRL_RESERVED_MASK 0xfffffffc
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_REN_GEN_ERR_CTRL_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_REN_GEN_ERR_CTRL_RESERVED_BITS 30
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_REN_GEN_ERR_CTRL_RESERVED_SHIFT 2
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_REN_GEN_ERR_CTRL_ALL_MASK 0x3
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_REN_GEN_ERR_CTRL_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_REN_GEN_ERR_CTRL_ALL_BITS 2
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_REN_GEN_ERR_CTRL_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_REN_GEN_ERR_CTRL_ALL_MASK 0x3
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_REN_GEN_ERR_CTRL_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_REN_GEN_ERR_CTRL_ALL_BITS 2
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_REN_GEN_ERR_CTRL_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_REN_GEN_ERR_CTRL_DATAMASK 0x00000003
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_REN_GEN_ERR_CTRL_RDWRMASK 0xfffffffc
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_REN_GEN_ERR_CTRL_RESETVALUE 0x3
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_REN_FIFO_CONFIG 0x1023cc78
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_REN_FIFO_CONFIG_BASE 0xc78
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_REN_FIFO_CONFIG_RD_2G_DELAY_DEC_MASK 0x800
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_REN_FIFO_CONFIG_RD_2G_DELAY_DEC_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_REN_FIFO_CONFIG_RD_2G_DELAY_DEC_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_REN_FIFO_CONFIG_RD_2G_DELAY_DEC_SHIFT 11
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_REN_FIFO_CONFIG_RD_2G_DELAY_DEC_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_REN_FIFO_CONFIG_RD_2G_DELAY_INC_MASK 0x400
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_REN_FIFO_CONFIG_RD_2G_DELAY_INC_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_REN_FIFO_CONFIG_RD_2G_DELAY_INC_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_REN_FIFO_CONFIG_RD_2G_DELAY_INC_SHIFT 10
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_REN_FIFO_CONFIG_RD_2G_DELAY_INC_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_REN_FIFO_CONFIG_RD2_2G_DELAY_MASK 0x3e0
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_REN_FIFO_CONFIG_RD2_2G_DELAY_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_REN_FIFO_CONFIG_RD2_2G_DELAY_BITS 5
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_REN_FIFO_CONFIG_RD2_2G_DELAY_SHIFT 5
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_REN_FIFO_CONFIG_RD2_2G_DELAY_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_REN_FIFO_CONFIG_RD_2G_DELAY_MASK 0x1f
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_REN_FIFO_CONFIG_RD_2G_DELAY_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_REN_FIFO_CONFIG_RD_2G_DELAY_BITS 5
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_REN_FIFO_CONFIG_RD_2G_DELAY_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_REN_FIFO_CONFIG_RD_2G_DELAY_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_REN_FIFO_CONFIG_RESERVED_MASK 0xfffff000
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_REN_FIFO_CONFIG_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_REN_FIFO_CONFIG_RESERVED_BITS 20
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_REN_FIFO_CONFIG_RESERVED_SHIFT 12
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_REN_FIFO_CONFIG_ALL_MASK 0xfff
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_REN_FIFO_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_REN_FIFO_CONFIG_ALL_BITS 12
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_REN_FIFO_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_REN_FIFO_CONFIG_ALL_MASK 0xfff
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_REN_FIFO_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_REN_FIFO_CONFIG_ALL_BITS 12
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_REN_FIFO_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_REN_FIFO_CONFIG_DATAMASK 0x00000fff
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_REN_FIFO_CONFIG_RDWRMASK 0xfffff000
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_REN_FIFO_CONFIG_RESETVALUE 0x000
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_REN_STRETCH_CONFIG 0x1023cc7c
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_REN_STRETCH_CONFIG_BASE 0xc7c
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_REN_STRETCH_CONFIG_A_PLUS_2_MASK 0x20
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_REN_STRETCH_CONFIG_A_PLUS_2_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_REN_STRETCH_CONFIG_A_PLUS_2_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_REN_STRETCH_CONFIG_A_PLUS_2_SHIFT 5
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_REN_STRETCH_CONFIG_A_PLUS_2_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_REN_STRETCH_CONFIG_A_PLUS_1_MASK 0x10
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_REN_STRETCH_CONFIG_A_PLUS_1_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_REN_STRETCH_CONFIG_A_PLUS_1_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_REN_STRETCH_CONFIG_A_PLUS_1_SHIFT 4
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_REN_STRETCH_CONFIG_A_PLUS_1_RESETVALUE 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_REN_STRETCH_CONFIG_A_0_MASK 0x8
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_REN_STRETCH_CONFIG_A_0_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_REN_STRETCH_CONFIG_A_0_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_REN_STRETCH_CONFIG_A_0_SHIFT 3
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_REN_STRETCH_CONFIG_A_0_RESETVALUE 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_REN_STRETCH_CONFIG_A_MINUS_1_MASK 0x4
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_REN_STRETCH_CONFIG_A_MINUS_1_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_REN_STRETCH_CONFIG_A_MINUS_1_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_REN_STRETCH_CONFIG_A_MINUS_1_SHIFT 2
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_REN_STRETCH_CONFIG_A_MINUS_1_RESETVALUE 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_REN_STRETCH_CONFIG_A_MINUS_2_MASK 0x2
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_REN_STRETCH_CONFIG_A_MINUS_2_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_REN_STRETCH_CONFIG_A_MINUS_2_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_REN_STRETCH_CONFIG_A_MINUS_2_SHIFT 1
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_REN_STRETCH_CONFIG_A_MINUS_2_RESETVALUE 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_REN_STRETCH_CONFIG_A_MINUS_3_MASK 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_REN_STRETCH_CONFIG_A_MINUS_3_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_REN_STRETCH_CONFIG_A_MINUS_3_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_REN_STRETCH_CONFIG_A_MINUS_3_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_REN_STRETCH_CONFIG_A_MINUS_3_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_REN_STRETCH_CONFIG_RESERVED_MASK 0xffffffc0
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_REN_STRETCH_CONFIG_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_REN_STRETCH_CONFIG_RESERVED_BITS 26
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_REN_STRETCH_CONFIG_RESERVED_SHIFT 6
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_REN_STRETCH_CONFIG_ALL_MASK 0x3f
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_REN_STRETCH_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_REN_STRETCH_CONFIG_ALL_BITS 6
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_REN_STRETCH_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_REN_STRETCH_CONFIG_ALL_MASK 0x3f
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_REN_STRETCH_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_REN_STRETCH_CONFIG_ALL_BITS 6
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_REN_STRETCH_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_REN_STRETCH_CONFIG_DATAMASK 0x0000003f
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_REN_STRETCH_CONFIG_RDWRMASK 0xffffffc0
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_REN_STRETCH_CONFIG_RESETVALUE 0x1e
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_READ_MAX_VDL_FSM 0x1023cc80
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_READ_MAX_VDL_FSM_BASE 0xc80
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_READ_MAX_VDL_FSM_MAX_VDL_STEP_MASK 0x1ff
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_READ_MAX_VDL_FSM_MAX_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_READ_MAX_VDL_FSM_MAX_VDL_STEP_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_READ_MAX_VDL_FSM_MAX_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_READ_MAX_VDL_FSM_MAX_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_READ_MAX_VDL_FSM_RESERVED_MASK 0xfffffe00
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_READ_MAX_VDL_FSM_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_READ_MAX_VDL_FSM_RESERVED_BITS 23
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_READ_MAX_VDL_FSM_RESERVED_SHIFT 9
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_READ_MAX_VDL_FSM_ALL_MASK 0x1ff
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_READ_MAX_VDL_FSM_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_READ_MAX_VDL_FSM_ALL_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_READ_MAX_VDL_FSM_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_READ_MAX_VDL_FSM_ALL_MASK 0x1ff
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_READ_MAX_VDL_FSM_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_READ_MAX_VDL_FSM_ALL_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_READ_MAX_VDL_FSM_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_READ_MAX_VDL_FSM_DATAMASK 0x000001ff
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_READ_MAX_VDL_FSM_RDWRMASK 0xfffffe00
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_READ_MAX_VDL_FSM_RESETVALUE 0x000
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_OE_CONFIG 0x1023cc84
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_OE_CONFIG_BASE 0xc84
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_OE_CONFIG_OE_POST_CYCLES_MASK 0x38
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_OE_CONFIG_OE_POST_CYCLES_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_OE_CONFIG_OE_POST_CYCLES_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_OE_CONFIG_OE_POST_CYCLES_SHIFT 3
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_OE_CONFIG_OE_POST_CYCLES_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_OE_CONFIG_OE_PRE_CYCLES_MASK 0x7
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_OE_CONFIG_OE_PRE_CYCLES_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_OE_CONFIG_OE_PRE_CYCLES_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_OE_CONFIG_OE_PRE_CYCLES_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_OE_CONFIG_OE_PRE_CYCLES_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_OE_CONFIG_RESERVED_MASK 0xffffffc0
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_OE_CONFIG_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_OE_CONFIG_RESERVED_BITS 26
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_OE_CONFIG_RESERVED_SHIFT 6
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_OE_CONFIG_ALL_MASK 0x3f
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_OE_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_OE_CONFIG_ALL_BITS 6
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_OE_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_OE_CONFIG_ALL_MASK 0x3f
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_OE_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_OE_CONFIG_ALL_BITS 6
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_OE_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_OE_CONFIG_DATAMASK 0x0000003f
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_OE_CONFIG_RDWRMASK 0xffffffc0
 #define SJC16_DDR4_PHY_DQ_BYTE3_DDR4_OE_CONFIG_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE3_GDDR5_READ_ALIGNMENT_CTRL 0x1023cc88
 #define SJC16_DDR4_PHY_DQ_BYTE3_GDDR5_READ_ALIGNMENT_CTRL_BASE 0xc88
 #define SJC16_DDR4_PHY_DQ_BYTE3_GDDR5_READ_ALIGNMENT_CTRL_RDATA_WR2RD_DELAY_DEC_MASK 0x20000000
 #define SJC16_DDR4_PHY_DQ_BYTE3_GDDR5_READ_ALIGNMENT_CTRL_RDATA_WR2RD_DELAY_DEC_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_GDDR5_READ_ALIGNMENT_CTRL_RDATA_WR2RD_DELAY_DEC_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE3_GDDR5_READ_ALIGNMENT_CTRL_RDATA_WR2RD_DELAY_DEC_SHIFT 29
 #define SJC16_DDR4_PHY_DQ_BYTE3_GDDR5_READ_ALIGNMENT_CTRL_RDATA_WR2RD_DELAY_DEC_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_GDDR5_READ_ALIGNMENT_CTRL_RDATA_WR2RD_DELAY_INC_MASK 0x10000000
 #define SJC16_DDR4_PHY_DQ_BYTE3_GDDR5_READ_ALIGNMENT_CTRL_RDATA_WR2RD_DELAY_INC_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_GDDR5_READ_ALIGNMENT_CTRL_RDATA_WR2RD_DELAY_INC_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE3_GDDR5_READ_ALIGNMENT_CTRL_RDATA_WR2RD_DELAY_INC_SHIFT 28
 #define SJC16_DDR4_PHY_DQ_BYTE3_GDDR5_READ_ALIGNMENT_CTRL_RDATA_WR2RD_DELAY_INC_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_GDDR5_READ_ALIGNMENT_CTRL_RDATA_WR2RD_DELAY_MASK 0xf000000
 #define SJC16_DDR4_PHY_DQ_BYTE3_GDDR5_READ_ALIGNMENT_CTRL_RDATA_WR2RD_DELAY_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_GDDR5_READ_ALIGNMENT_CTRL_RDATA_WR2RD_DELAY_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE3_GDDR5_READ_ALIGNMENT_CTRL_RDATA_WR2RD_DELAY_SHIFT 24
 #define SJC16_DDR4_PHY_DQ_BYTE3_GDDR5_READ_ALIGNMENT_CTRL_RDATA_WR2RD_DELAY_RESETVALUE 0x4
 #define SJC16_DDR4_PHY_DQ_BYTE3_GDDR5_READ_ALIGNMENT_CTRL_EDC_HALF_RATE_UI_SELECT_MASK 0x800000
 #define SJC16_DDR4_PHY_DQ_BYTE3_GDDR5_READ_ALIGNMENT_CTRL_EDC_HALF_RATE_UI_SELECT_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_GDDR5_READ_ALIGNMENT_CTRL_EDC_HALF_RATE_UI_SELECT_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE3_GDDR5_READ_ALIGNMENT_CTRL_EDC_HALF_RATE_UI_SELECT_SHIFT 23
 #define SJC16_DDR4_PHY_DQ_BYTE3_GDDR5_READ_ALIGNMENT_CTRL_EDC_HALF_RATE_UI_SELECT_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_GDDR5_READ_ALIGNMENT_CTRL_EDC_HALF_RATE_ENABLE_MASK 0x400000
 #define SJC16_DDR4_PHY_DQ_BYTE3_GDDR5_READ_ALIGNMENT_CTRL_EDC_HALF_RATE_ENABLE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_GDDR5_READ_ALIGNMENT_CTRL_EDC_HALF_RATE_ENABLE_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE3_GDDR5_READ_ALIGNMENT_CTRL_EDC_HALF_RATE_ENABLE_SHIFT 22
 #define SJC16_DDR4_PHY_DQ_BYTE3_GDDR5_READ_ALIGNMENT_CTRL_EDC_HALF_RATE_ENABLE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_GDDR5_READ_ALIGNMENT_CTRL_EDC_VALID_WR2RD_DELAY_DEC_MASK 0x200000
 #define SJC16_DDR4_PHY_DQ_BYTE3_GDDR5_READ_ALIGNMENT_CTRL_EDC_VALID_WR2RD_DELAY_DEC_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_GDDR5_READ_ALIGNMENT_CTRL_EDC_VALID_WR2RD_DELAY_DEC_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE3_GDDR5_READ_ALIGNMENT_CTRL_EDC_VALID_WR2RD_DELAY_DEC_SHIFT 21
 #define SJC16_DDR4_PHY_DQ_BYTE3_GDDR5_READ_ALIGNMENT_CTRL_EDC_VALID_WR2RD_DELAY_DEC_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_GDDR5_READ_ALIGNMENT_CTRL_EDC_VALID_WR2RD_DELAY_INC_MASK 0x100000
 #define SJC16_DDR4_PHY_DQ_BYTE3_GDDR5_READ_ALIGNMENT_CTRL_EDC_VALID_WR2RD_DELAY_INC_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_GDDR5_READ_ALIGNMENT_CTRL_EDC_VALID_WR2RD_DELAY_INC_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE3_GDDR5_READ_ALIGNMENT_CTRL_EDC_VALID_WR2RD_DELAY_INC_SHIFT 20
 #define SJC16_DDR4_PHY_DQ_BYTE3_GDDR5_READ_ALIGNMENT_CTRL_EDC_VALID_WR2RD_DELAY_INC_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_GDDR5_READ_ALIGNMENT_CTRL_EDC_VALID_WR2RD_DELAY_MASK 0xf0000
 #define SJC16_DDR4_PHY_DQ_BYTE3_GDDR5_READ_ALIGNMENT_CTRL_EDC_VALID_WR2RD_DELAY_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_GDDR5_READ_ALIGNMENT_CTRL_EDC_VALID_WR2RD_DELAY_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE3_GDDR5_READ_ALIGNMENT_CTRL_EDC_VALID_WR2RD_DELAY_SHIFT 16
 #define SJC16_DDR4_PHY_DQ_BYTE3_GDDR5_READ_ALIGNMENT_CTRL_EDC_VALID_WR2RD_DELAY_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_GDDR5_READ_ALIGNMENT_CTRL_EDC_UI_SHIFT_MASK 0x7000
 #define SJC16_DDR4_PHY_DQ_BYTE3_GDDR5_READ_ALIGNMENT_CTRL_EDC_UI_SHIFT_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_GDDR5_READ_ALIGNMENT_CTRL_EDC_UI_SHIFT_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE3_GDDR5_READ_ALIGNMENT_CTRL_EDC_UI_SHIFT_SHIFT 12
 #define SJC16_DDR4_PHY_DQ_BYTE3_GDDR5_READ_ALIGNMENT_CTRL_EDC_UI_SHIFT_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_GDDR5_READ_ALIGNMENT_CTRL_DATA_VALID_WR2RD_DELAY_DEC_MASK 0x200
 #define SJC16_DDR4_PHY_DQ_BYTE3_GDDR5_READ_ALIGNMENT_CTRL_DATA_VALID_WR2RD_DELAY_DEC_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_GDDR5_READ_ALIGNMENT_CTRL_DATA_VALID_WR2RD_DELAY_DEC_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE3_GDDR5_READ_ALIGNMENT_CTRL_DATA_VALID_WR2RD_DELAY_DEC_SHIFT 9
 #define SJC16_DDR4_PHY_DQ_BYTE3_GDDR5_READ_ALIGNMENT_CTRL_DATA_VALID_WR2RD_DELAY_DEC_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_GDDR5_READ_ALIGNMENT_CTRL_DATA_VALID_WR2RD_DELAY_INC_MASK 0x100
 #define SJC16_DDR4_PHY_DQ_BYTE3_GDDR5_READ_ALIGNMENT_CTRL_DATA_VALID_WR2RD_DELAY_INC_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_GDDR5_READ_ALIGNMENT_CTRL_DATA_VALID_WR2RD_DELAY_INC_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE3_GDDR5_READ_ALIGNMENT_CTRL_DATA_VALID_WR2RD_DELAY_INC_SHIFT 8
 #define SJC16_DDR4_PHY_DQ_BYTE3_GDDR5_READ_ALIGNMENT_CTRL_DATA_VALID_WR2RD_DELAY_INC_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_GDDR5_READ_ALIGNMENT_CTRL_DATA_VALID_WR2RD_DELAY_MASK 0xf0
 #define SJC16_DDR4_PHY_DQ_BYTE3_GDDR5_READ_ALIGNMENT_CTRL_DATA_VALID_WR2RD_DELAY_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_GDDR5_READ_ALIGNMENT_CTRL_DATA_VALID_WR2RD_DELAY_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE3_GDDR5_READ_ALIGNMENT_CTRL_DATA_VALID_WR2RD_DELAY_SHIFT 4
 #define SJC16_DDR4_PHY_DQ_BYTE3_GDDR5_READ_ALIGNMENT_CTRL_DATA_VALID_WR2RD_DELAY_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_GDDR5_READ_ALIGNMENT_CTRL_DATA_UI_SHIFT_MASK 0x7
 #define SJC16_DDR4_PHY_DQ_BYTE3_GDDR5_READ_ALIGNMENT_CTRL_DATA_UI_SHIFT_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_GDDR5_READ_ALIGNMENT_CTRL_DATA_UI_SHIFT_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE3_GDDR5_READ_ALIGNMENT_CTRL_DATA_UI_SHIFT_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_GDDR5_READ_ALIGNMENT_CTRL_DATA_UI_SHIFT_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_GDDR5_READ_ALIGNMENT_CTRL_RESERVED_0_MASK 0xc0000000
 #define SJC16_DDR4_PHY_DQ_BYTE3_GDDR5_READ_ALIGNMENT_CTRL_RESERVED_0_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_GDDR5_READ_ALIGNMENT_CTRL_RESERVED_0_BITS 2
 #define SJC16_DDR4_PHY_DQ_BYTE3_GDDR5_READ_ALIGNMENT_CTRL_RESERVED_0_SHIFT 30
 #define SJC16_DDR4_PHY_DQ_BYTE3_GDDR5_READ_ALIGNMENT_CTRL_RESERVED_2_MASK 0xc00
 #define SJC16_DDR4_PHY_DQ_BYTE3_GDDR5_READ_ALIGNMENT_CTRL_RESERVED_2_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_GDDR5_READ_ALIGNMENT_CTRL_RESERVED_2_BITS 2
 #define SJC16_DDR4_PHY_DQ_BYTE3_GDDR5_READ_ALIGNMENT_CTRL_RESERVED_2_SHIFT 10
 #define SJC16_DDR4_PHY_DQ_BYTE3_GDDR5_READ_ALIGNMENT_CTRL_RESERVED_MASK 0xc0000000
 #define SJC16_DDR4_PHY_DQ_BYTE3_GDDR5_READ_ALIGNMENT_CTRL_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_GDDR5_READ_ALIGNMENT_CTRL_RESERVED_BITS 2
 #define SJC16_DDR4_PHY_DQ_BYTE3_GDDR5_READ_ALIGNMENT_CTRL_RESERVED_SHIFT 30
 #define SJC16_DDR4_PHY_DQ_BYTE3_GDDR5_READ_ALIGNMENT_CTRL_ALL_MASK 0x3fffffff
 #define SJC16_DDR4_PHY_DQ_BYTE3_GDDR5_READ_ALIGNMENT_CTRL_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_GDDR5_READ_ALIGNMENT_CTRL_ALL_BITS 30
 #define SJC16_DDR4_PHY_DQ_BYTE3_GDDR5_READ_ALIGNMENT_CTRL_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_GDDR5_READ_ALIGNMENT_CTRL_ALL_MASK 0x3fffffff
 #define SJC16_DDR4_PHY_DQ_BYTE3_GDDR5_READ_ALIGNMENT_CTRL_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_GDDR5_READ_ALIGNMENT_CTRL_ALL_BITS 30
 #define SJC16_DDR4_PHY_DQ_BYTE3_GDDR5_READ_ALIGNMENT_CTRL_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_GDDR5_READ_ALIGNMENT_CTRL_DATAMASK 0x3fff73f7
 #define SJC16_DDR4_PHY_DQ_BYTE3_GDDR5_READ_ALIGNMENT_CTRL_RDWRMASK 0xc0008c08
 #define SJC16_DDR4_PHY_DQ_BYTE3_GDDR5_READ_ALIGNMENT_CTRL_RESETVALUE 0x04000000
 #define SJC16_DDR4_PHY_DQ_BYTE3_GDDR5_READ_FSM_CTRL 0x1023cc8c
 #define SJC16_DDR4_PHY_DQ_BYTE3_GDDR5_READ_FSM_CTRL_BASE 0xc8c
 #define SJC16_DDR4_PHY_DQ_BYTE3_GDDR5_READ_FSM_CTRL_QDR_MODE_MASK 0x8
 #define SJC16_DDR4_PHY_DQ_BYTE3_GDDR5_READ_FSM_CTRL_QDR_MODE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_GDDR5_READ_FSM_CTRL_QDR_MODE_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE3_GDDR5_READ_FSM_CTRL_QDR_MODE_SHIFT 3
 #define SJC16_DDR4_PHY_DQ_BYTE3_GDDR5_READ_FSM_CTRL_QDR_MODE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_GDDR5_READ_FSM_CTRL_DATA_VALID_GEN_ERROR_CLEAR_MASK 0x4
 #define SJC16_DDR4_PHY_DQ_BYTE3_GDDR5_READ_FSM_CTRL_DATA_VALID_GEN_ERROR_CLEAR_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_GDDR5_READ_FSM_CTRL_DATA_VALID_GEN_ERROR_CLEAR_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE3_GDDR5_READ_FSM_CTRL_DATA_VALID_GEN_ERROR_CLEAR_SHIFT 2
 #define SJC16_DDR4_PHY_DQ_BYTE3_GDDR5_READ_FSM_CTRL_DATA_VALID_GEN_ERROR_CLEAR_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_GDDR5_READ_FSM_CTRL_DATA_VALID_GEN_ENABLE_MASK 0x2
 #define SJC16_DDR4_PHY_DQ_BYTE3_GDDR5_READ_FSM_CTRL_DATA_VALID_GEN_ENABLE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_GDDR5_READ_FSM_CTRL_DATA_VALID_GEN_ENABLE_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE3_GDDR5_READ_FSM_CTRL_DATA_VALID_GEN_ENABLE_SHIFT 1
 #define SJC16_DDR4_PHY_DQ_BYTE3_GDDR5_READ_FSM_CTRL_DATA_VALID_GEN_ENABLE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_GDDR5_READ_FSM_CTRL_SYSTEM_ENABLE_MASK 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE3_GDDR5_READ_FSM_CTRL_SYSTEM_ENABLE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_GDDR5_READ_FSM_CTRL_SYSTEM_ENABLE_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE3_GDDR5_READ_FSM_CTRL_SYSTEM_ENABLE_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_GDDR5_READ_FSM_CTRL_SYSTEM_ENABLE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_GDDR5_READ_FSM_CTRL_RESERVED_MASK 0xfffffff0
 #define SJC16_DDR4_PHY_DQ_BYTE3_GDDR5_READ_FSM_CTRL_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_GDDR5_READ_FSM_CTRL_RESERVED_BITS 28
 #define SJC16_DDR4_PHY_DQ_BYTE3_GDDR5_READ_FSM_CTRL_RESERVED_SHIFT 4
 #define SJC16_DDR4_PHY_DQ_BYTE3_GDDR5_READ_FSM_CTRL_ALL_MASK 0xf
 #define SJC16_DDR4_PHY_DQ_BYTE3_GDDR5_READ_FSM_CTRL_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_GDDR5_READ_FSM_CTRL_ALL_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE3_GDDR5_READ_FSM_CTRL_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_GDDR5_READ_FSM_CTRL_ALL_MASK 0xf
 #define SJC16_DDR4_PHY_DQ_BYTE3_GDDR5_READ_FSM_CTRL_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_GDDR5_READ_FSM_CTRL_ALL_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE3_GDDR5_READ_FSM_CTRL_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_GDDR5_READ_FSM_CTRL_DATAMASK 0x0000000f
 #define SJC16_DDR4_PHY_DQ_BYTE3_GDDR5_READ_FSM_CTRL_RDWRMASK 0xfffffff0
 #define SJC16_DDR4_PHY_DQ_BYTE3_GDDR5_READ_FSM_CTRL_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_DATA_IO_CONFIG 0x1023cc90
 #define SJC16_DDR4_PHY_DQ_BYTE3_DATA_IO_CONFIG_BASE 0xc90
 #define SJC16_DDR4_PHY_DQ_BYTE3_DATA_IO_CONFIG_PTERM_MASK 0x1f000000
 #define SJC16_DDR4_PHY_DQ_BYTE3_DATA_IO_CONFIG_PTERM_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_DATA_IO_CONFIG_PTERM_BITS 5
 #define SJC16_DDR4_PHY_DQ_BYTE3_DATA_IO_CONFIG_PTERM_SHIFT 24
 #define SJC16_DDR4_PHY_DQ_BYTE3_DATA_IO_CONFIG_PTERM_RESETVALUE 0x10
 #define SJC16_DDR4_PHY_DQ_BYTE3_DATA_IO_CONFIG_NTERM_MASK 0xf80000
 #define SJC16_DDR4_PHY_DQ_BYTE3_DATA_IO_CONFIG_NTERM_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_DATA_IO_CONFIG_NTERM_BITS 5
 #define SJC16_DDR4_PHY_DQ_BYTE3_DATA_IO_CONFIG_NTERM_SHIFT 19
 #define SJC16_DDR4_PHY_DQ_BYTE3_DATA_IO_CONFIG_NTERM_RESETVALUE 0xf
 #define SJC16_DDR4_PHY_DQ_BYTE3_DATA_IO_CONFIG_PULL_UP_OFF_B_MASK 0x20000
 #define SJC16_DDR4_PHY_DQ_BYTE3_DATA_IO_CONFIG_PULL_UP_OFF_B_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_DATA_IO_CONFIG_PULL_UP_OFF_B_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE3_DATA_IO_CONFIG_PULL_UP_OFF_B_SHIFT 17
 #define SJC16_DDR4_PHY_DQ_BYTE3_DATA_IO_CONFIG_PULL_UP_OFF_B_RESETVALUE 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE3_DATA_IO_CONFIG_RX_BIAS_MASK 0x18000
 #define SJC16_DDR4_PHY_DQ_BYTE3_DATA_IO_CONFIG_RX_BIAS_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_DATA_IO_CONFIG_RX_BIAS_BITS 2
 #define SJC16_DDR4_PHY_DQ_BYTE3_DATA_IO_CONFIG_RX_BIAS_SHIFT 15
 #define SJC16_DDR4_PHY_DQ_BYTE3_DATA_IO_CONFIG_RX_BIAS_RESETVALUE 0x3
 #define SJC16_DDR4_PHY_DQ_BYTE3_DATA_IO_CONFIG_PEAK_MASK 0x6000
 #define SJC16_DDR4_PHY_DQ_BYTE3_DATA_IO_CONFIG_PEAK_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_DATA_IO_CONFIG_PEAK_BITS 2
 #define SJC16_DDR4_PHY_DQ_BYTE3_DATA_IO_CONFIG_PEAK_SHIFT 13
 #define SJC16_DDR4_PHY_DQ_BYTE3_DATA_IO_CONFIG_PEAK_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_DATA_IO_CONFIG_DEM_MASK 0x1800
 #define SJC16_DDR4_PHY_DQ_BYTE3_DATA_IO_CONFIG_DEM_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_DATA_IO_CONFIG_DEM_BITS 2
 #define SJC16_DDR4_PHY_DQ_BYTE3_DATA_IO_CONFIG_DEM_SHIFT 11
 #define SJC16_DDR4_PHY_DQ_BYTE3_DATA_IO_CONFIG_DEM_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_DATA_IO_CONFIG_RXENB_MASK 0x400
 #define SJC16_DDR4_PHY_DQ_BYTE3_DATA_IO_CONFIG_RXENB_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_DATA_IO_CONFIG_RXENB_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE3_DATA_IO_CONFIG_RXENB_SHIFT 10
 #define SJC16_DDR4_PHY_DQ_BYTE3_DATA_IO_CONFIG_RXENB_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_DATA_IO_CONFIG_PD_MASK 0x3e0
 #define SJC16_DDR4_PHY_DQ_BYTE3_DATA_IO_CONFIG_PD_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_DATA_IO_CONFIG_PD_BITS 5
 #define SJC16_DDR4_PHY_DQ_BYTE3_DATA_IO_CONFIG_PD_SHIFT 5
 #define SJC16_DDR4_PHY_DQ_BYTE3_DATA_IO_CONFIG_PD_RESETVALUE 0x10
 #define SJC16_DDR4_PHY_DQ_BYTE3_DATA_IO_CONFIG_ND_MASK 0x1f
 #define SJC16_DDR4_PHY_DQ_BYTE3_DATA_IO_CONFIG_ND_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_DATA_IO_CONFIG_ND_BITS 5
 #define SJC16_DDR4_PHY_DQ_BYTE3_DATA_IO_CONFIG_ND_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_DATA_IO_CONFIG_ND_RESETVALUE 0xf
 #define SJC16_DDR4_PHY_DQ_BYTE3_DATA_IO_CONFIG_RESERVED_MASK 0xe0000000
 #define SJC16_DDR4_PHY_DQ_BYTE3_DATA_IO_CONFIG_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_DATA_IO_CONFIG_RESERVED_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE3_DATA_IO_CONFIG_RESERVED_SHIFT 29
 #define SJC16_DDR4_PHY_DQ_BYTE3_DATA_IO_CONFIG_ALL_MASK 0x1fffffff
 #define SJC16_DDR4_PHY_DQ_BYTE3_DATA_IO_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_DATA_IO_CONFIG_ALL_BITS 29
 #define SJC16_DDR4_PHY_DQ_BYTE3_DATA_IO_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_DATA_IO_CONFIG_ALL_MASK 0x1fffffff
 #define SJC16_DDR4_PHY_DQ_BYTE3_DATA_IO_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_DATA_IO_CONFIG_ALL_BITS 29
 #define SJC16_DDR4_PHY_DQ_BYTE3_DATA_IO_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_DATA_IO_CONFIG_DATAMASK 0x1ffbffff
 #define SJC16_DDR4_PHY_DQ_BYTE3_DATA_IO_CONFIG_RDWRMASK 0xe0040000
 #define SJC16_DDR4_PHY_DQ_BYTE3_DATA_IO_CONFIG_RESETVALUE 0x107b820f
 #define SJC16_DDR4_PHY_DQ_BYTE3_DQS_IO_CONFIG 0x1023cc94
 #define SJC16_DDR4_PHY_DQ_BYTE3_DQS_IO_CONFIG_BASE 0xc94
 #define SJC16_DDR4_PHY_DQ_BYTE3_DQS_IO_CONFIG_PTERM_MASK 0x1f000000
 #define SJC16_DDR4_PHY_DQ_BYTE3_DQS_IO_CONFIG_PTERM_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_DQS_IO_CONFIG_PTERM_BITS 5
 #define SJC16_DDR4_PHY_DQ_BYTE3_DQS_IO_CONFIG_PTERM_SHIFT 24
 #define SJC16_DDR4_PHY_DQ_BYTE3_DQS_IO_CONFIG_PTERM_RESETVALUE 0x10
 #define SJC16_DDR4_PHY_DQ_BYTE3_DQS_IO_CONFIG_NTERM_MASK 0xf80000
 #define SJC16_DDR4_PHY_DQ_BYTE3_DQS_IO_CONFIG_NTERM_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_DQS_IO_CONFIG_NTERM_BITS 5
 #define SJC16_DDR4_PHY_DQ_BYTE3_DQS_IO_CONFIG_NTERM_SHIFT 19
 #define SJC16_DDR4_PHY_DQ_BYTE3_DQS_IO_CONFIG_NTERM_RESETVALUE 0xf
 #define SJC16_DDR4_PHY_DQ_BYTE3_DQS_IO_CONFIG_PULL_UP_OFF_B_MASK 0x20000
 #define SJC16_DDR4_PHY_DQ_BYTE3_DQS_IO_CONFIG_PULL_UP_OFF_B_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_DQS_IO_CONFIG_PULL_UP_OFF_B_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE3_DQS_IO_CONFIG_PULL_UP_OFF_B_SHIFT 17
 #define SJC16_DDR4_PHY_DQ_BYTE3_DQS_IO_CONFIG_PULL_UP_OFF_B_RESETVALUE 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE3_DQS_IO_CONFIG_RX_BIAS_MASK 0x18000
 #define SJC16_DDR4_PHY_DQ_BYTE3_DQS_IO_CONFIG_RX_BIAS_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_DQS_IO_CONFIG_RX_BIAS_BITS 2
 #define SJC16_DDR4_PHY_DQ_BYTE3_DQS_IO_CONFIG_RX_BIAS_SHIFT 15
 #define SJC16_DDR4_PHY_DQ_BYTE3_DQS_IO_CONFIG_RX_BIAS_RESETVALUE 0x3
 #define SJC16_DDR4_PHY_DQ_BYTE3_DQS_IO_CONFIG_PEAK_MASK 0x6000
 #define SJC16_DDR4_PHY_DQ_BYTE3_DQS_IO_CONFIG_PEAK_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_DQS_IO_CONFIG_PEAK_BITS 2
 #define SJC16_DDR4_PHY_DQ_BYTE3_DQS_IO_CONFIG_PEAK_SHIFT 13
 #define SJC16_DDR4_PHY_DQ_BYTE3_DQS_IO_CONFIG_PEAK_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_DQS_IO_CONFIG_DEM_MASK 0x1800
 #define SJC16_DDR4_PHY_DQ_BYTE3_DQS_IO_CONFIG_DEM_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_DQS_IO_CONFIG_DEM_BITS 2
 #define SJC16_DDR4_PHY_DQ_BYTE3_DQS_IO_CONFIG_DEM_SHIFT 11
 #define SJC16_DDR4_PHY_DQ_BYTE3_DQS_IO_CONFIG_DEM_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_DQS_IO_CONFIG_RXENB_MASK 0x400
 #define SJC16_DDR4_PHY_DQ_BYTE3_DQS_IO_CONFIG_RXENB_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_DQS_IO_CONFIG_RXENB_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE3_DQS_IO_CONFIG_RXENB_SHIFT 10
 #define SJC16_DDR4_PHY_DQ_BYTE3_DQS_IO_CONFIG_RXENB_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_DQS_IO_CONFIG_PD_MASK 0x3e0
 #define SJC16_DDR4_PHY_DQ_BYTE3_DQS_IO_CONFIG_PD_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_DQS_IO_CONFIG_PD_BITS 5
 #define SJC16_DDR4_PHY_DQ_BYTE3_DQS_IO_CONFIG_PD_SHIFT 5
 #define SJC16_DDR4_PHY_DQ_BYTE3_DQS_IO_CONFIG_PD_RESETVALUE 0x10
 #define SJC16_DDR4_PHY_DQ_BYTE3_DQS_IO_CONFIG_ND_MASK 0x1f
 #define SJC16_DDR4_PHY_DQ_BYTE3_DQS_IO_CONFIG_ND_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_DQS_IO_CONFIG_ND_BITS 5
 #define SJC16_DDR4_PHY_DQ_BYTE3_DQS_IO_CONFIG_ND_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_DQS_IO_CONFIG_ND_RESETVALUE 0xf
 #define SJC16_DDR4_PHY_DQ_BYTE3_DQS_IO_CONFIG_RESERVED_MASK 0xe0000000
 #define SJC16_DDR4_PHY_DQ_BYTE3_DQS_IO_CONFIG_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_DQS_IO_CONFIG_RESERVED_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE3_DQS_IO_CONFIG_RESERVED_SHIFT 29
 #define SJC16_DDR4_PHY_DQ_BYTE3_DQS_IO_CONFIG_ALL_MASK 0x1fffffff
 #define SJC16_DDR4_PHY_DQ_BYTE3_DQS_IO_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_DQS_IO_CONFIG_ALL_BITS 29
 #define SJC16_DDR4_PHY_DQ_BYTE3_DQS_IO_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_DQS_IO_CONFIG_ALL_MASK 0x1fffffff
 #define SJC16_DDR4_PHY_DQ_BYTE3_DQS_IO_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_DQS_IO_CONFIG_ALL_BITS 29
 #define SJC16_DDR4_PHY_DQ_BYTE3_DQS_IO_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_DQS_IO_CONFIG_DATAMASK 0x1ffbffff
 #define SJC16_DDR4_PHY_DQ_BYTE3_DQS_IO_CONFIG_RDWRMASK 0xe0040000
 #define SJC16_DDR4_PHY_DQ_BYTE3_DQS_IO_CONFIG_RESETVALUE 0x107b820f
 #define SJC16_DDR4_PHY_DQ_BYTE3_VREF_DAC_CONFIG 0x1023cc98
 #define SJC16_DDR4_PHY_DQ_BYTE3_VREF_DAC_CONFIG_BASE 0xc98
 #define SJC16_DDR4_PHY_DQ_BYTE3_VREF_DAC_CONFIG_DATA_MASK 0xff0000
 #define SJC16_DDR4_PHY_DQ_BYTE3_VREF_DAC_CONFIG_DATA_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_VREF_DAC_CONFIG_DATA_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE3_VREF_DAC_CONFIG_DATA_SHIFT 16
 #define SJC16_DDR4_PHY_DQ_BYTE3_VREF_DAC_CONFIG_DATA_RESETVALUE 0x92
 #define SJC16_DDR4_PHY_DQ_BYTE3_VREF_DAC_CONFIG_CTRL_MASK 0xff
 #define SJC16_DDR4_PHY_DQ_BYTE3_VREF_DAC_CONFIG_CTRL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_VREF_DAC_CONFIG_CTRL_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE3_VREF_DAC_CONFIG_CTRL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_VREF_DAC_CONFIG_CTRL_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE3_VREF_DAC_CONFIG_RESERVED_MASK 0xff000000
 #define SJC16_DDR4_PHY_DQ_BYTE3_VREF_DAC_CONFIG_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_VREF_DAC_CONFIG_RESERVED_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE3_VREF_DAC_CONFIG_RESERVED_SHIFT 24
 #define SJC16_DDR4_PHY_DQ_BYTE3_VREF_DAC_CONFIG_ALL_MASK 0xffffff
 #define SJC16_DDR4_PHY_DQ_BYTE3_VREF_DAC_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_VREF_DAC_CONFIG_ALL_BITS 24
 #define SJC16_DDR4_PHY_DQ_BYTE3_VREF_DAC_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_VREF_DAC_CONFIG_ALL_MASK 0xffffff
 #define SJC16_DDR4_PHY_DQ_BYTE3_VREF_DAC_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_VREF_DAC_CONFIG_ALL_BITS 24
 #define SJC16_DDR4_PHY_DQ_BYTE3_VREF_DAC_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_VREF_DAC_CONFIG_DATAMASK 0x00ff00ff
 #define SJC16_DDR4_PHY_DQ_BYTE3_VREF_DAC_CONFIG_RDWRMASK 0xff00ff00
 #define SJC16_DDR4_PHY_DQ_BYTE3_VREF_DAC_CONFIG_RESETVALUE 0x920000
 #define SJC16_DDR4_PHY_DQ_BYTE3_LDO_R_CONFIG 0x1023cc9c
 #define SJC16_DDR4_PHY_DQ_BYTE3_LDO_R_CONFIG_BASE 0xc9c
 #define SJC16_DDR4_PHY_DQ_BYTE3_LDO_R_CONFIG_REF_SEL_EXT_MASK 0x2000
 #define SJC16_DDR4_PHY_DQ_BYTE3_LDO_R_CONFIG_REF_SEL_EXT_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_LDO_R_CONFIG_REF_SEL_EXT_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE3_LDO_R_CONFIG_REF_SEL_EXT_SHIFT 13
 #define SJC16_DDR4_PHY_DQ_BYTE3_LDO_R_CONFIG_REF_SEL_EXT_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_LDO_R_CONFIG_REF_EXT_MASK 0x1000
 #define SJC16_DDR4_PHY_DQ_BYTE3_LDO_R_CONFIG_REF_EXT_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_LDO_R_CONFIG_REF_EXT_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE3_LDO_R_CONFIG_REF_EXT_SHIFT 12
 #define SJC16_DDR4_PHY_DQ_BYTE3_LDO_R_CONFIG_REF_EXT_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_LDO_R_CONFIG_PWRDN_MASK 0x200
 #define SJC16_DDR4_PHY_DQ_BYTE3_LDO_R_CONFIG_PWRDN_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_LDO_R_CONFIG_PWRDN_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE3_LDO_R_CONFIG_PWRDN_SHIFT 9
 #define SJC16_DDR4_PHY_DQ_BYTE3_LDO_R_CONFIG_PWRDN_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_LDO_R_CONFIG_CTRL_MASK 0x1f8
 #define SJC16_DDR4_PHY_DQ_BYTE3_LDO_R_CONFIG_CTRL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_LDO_R_CONFIG_CTRL_BITS 6
 #define SJC16_DDR4_PHY_DQ_BYTE3_LDO_R_CONFIG_CTRL_SHIFT 3
 #define SJC16_DDR4_PHY_DQ_BYTE3_LDO_R_CONFIG_CTRL_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_LDO_R_CONFIG_BYPASS_MASK 0x4
 #define SJC16_DDR4_PHY_DQ_BYTE3_LDO_R_CONFIG_BYPASS_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_LDO_R_CONFIG_BYPASS_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE3_LDO_R_CONFIG_BYPASS_SHIFT 2
 #define SJC16_DDR4_PHY_DQ_BYTE3_LDO_R_CONFIG_BYPASS_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_LDO_R_CONFIG_BIAS_CTRL_MASK 0x3
 #define SJC16_DDR4_PHY_DQ_BYTE3_LDO_R_CONFIG_BIAS_CTRL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_LDO_R_CONFIG_BIAS_CTRL_BITS 2
 #define SJC16_DDR4_PHY_DQ_BYTE3_LDO_R_CONFIG_BIAS_CTRL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_LDO_R_CONFIG_BIAS_CTRL_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_LDO_R_CONFIG_RESERVED_MASK 0xffffc000
 #define SJC16_DDR4_PHY_DQ_BYTE3_LDO_R_CONFIG_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_LDO_R_CONFIG_RESERVED_BITS 18
 #define SJC16_DDR4_PHY_DQ_BYTE3_LDO_R_CONFIG_RESERVED_SHIFT 14
 #define SJC16_DDR4_PHY_DQ_BYTE3_LDO_R_CONFIG_ALL_MASK 0x3fff
 #define SJC16_DDR4_PHY_DQ_BYTE3_LDO_R_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_LDO_R_CONFIG_ALL_BITS 14
 #define SJC16_DDR4_PHY_DQ_BYTE3_LDO_R_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_LDO_R_CONFIG_ALL_MASK 0x3fff
 #define SJC16_DDR4_PHY_DQ_BYTE3_LDO_R_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_LDO_R_CONFIG_ALL_BITS 14
 #define SJC16_DDR4_PHY_DQ_BYTE3_LDO_R_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_LDO_R_CONFIG_DATAMASK 0x000033ff
 #define SJC16_DDR4_PHY_DQ_BYTE3_LDO_R_CONFIG_RDWRMASK 0xffffcc00
 #define SJC16_DDR4_PHY_DQ_BYTE3_LDO_R_CONFIG_RESETVALUE 0x0000
 #define SJC16_DDR4_PHY_DQ_BYTE3_LDO_W_CONFIG 0x1023cca0
 #define SJC16_DDR4_PHY_DQ_BYTE3_LDO_W_CONFIG_BASE 0xca0
 #define SJC16_DDR4_PHY_DQ_BYTE3_LDO_W_CONFIG_REF_SEL_EXT_MASK 0x2000
 #define SJC16_DDR4_PHY_DQ_BYTE3_LDO_W_CONFIG_REF_SEL_EXT_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_LDO_W_CONFIG_REF_SEL_EXT_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE3_LDO_W_CONFIG_REF_SEL_EXT_SHIFT 13
 #define SJC16_DDR4_PHY_DQ_BYTE3_LDO_W_CONFIG_REF_SEL_EXT_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_LDO_W_CONFIG_REF_EXT_MASK 0x1000
 #define SJC16_DDR4_PHY_DQ_BYTE3_LDO_W_CONFIG_REF_EXT_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_LDO_W_CONFIG_REF_EXT_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE3_LDO_W_CONFIG_REF_EXT_SHIFT 12
 #define SJC16_DDR4_PHY_DQ_BYTE3_LDO_W_CONFIG_REF_EXT_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_LDO_W_CONFIG_PWRDN_MASK 0x200
 #define SJC16_DDR4_PHY_DQ_BYTE3_LDO_W_CONFIG_PWRDN_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_LDO_W_CONFIG_PWRDN_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE3_LDO_W_CONFIG_PWRDN_SHIFT 9
 #define SJC16_DDR4_PHY_DQ_BYTE3_LDO_W_CONFIG_PWRDN_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_LDO_W_CONFIG_CTRL_MASK 0x1f8
 #define SJC16_DDR4_PHY_DQ_BYTE3_LDO_W_CONFIG_CTRL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_LDO_W_CONFIG_CTRL_BITS 6
 #define SJC16_DDR4_PHY_DQ_BYTE3_LDO_W_CONFIG_CTRL_SHIFT 3
 #define SJC16_DDR4_PHY_DQ_BYTE3_LDO_W_CONFIG_CTRL_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_LDO_W_CONFIG_BYPASS_MASK 0x4
 #define SJC16_DDR4_PHY_DQ_BYTE3_LDO_W_CONFIG_BYPASS_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_LDO_W_CONFIG_BYPASS_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE3_LDO_W_CONFIG_BYPASS_SHIFT 2
 #define SJC16_DDR4_PHY_DQ_BYTE3_LDO_W_CONFIG_BYPASS_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_LDO_W_CONFIG_BIAS_CTRL_MASK 0x3
 #define SJC16_DDR4_PHY_DQ_BYTE3_LDO_W_CONFIG_BIAS_CTRL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_LDO_W_CONFIG_BIAS_CTRL_BITS 2
 #define SJC16_DDR4_PHY_DQ_BYTE3_LDO_W_CONFIG_BIAS_CTRL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_LDO_W_CONFIG_BIAS_CTRL_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_LDO_W_CONFIG_RESERVED_MASK 0xffffc000
 #define SJC16_DDR4_PHY_DQ_BYTE3_LDO_W_CONFIG_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_LDO_W_CONFIG_RESERVED_BITS 18
 #define SJC16_DDR4_PHY_DQ_BYTE3_LDO_W_CONFIG_RESERVED_SHIFT 14
 #define SJC16_DDR4_PHY_DQ_BYTE3_LDO_W_CONFIG_ALL_MASK 0x3fff
 #define SJC16_DDR4_PHY_DQ_BYTE3_LDO_W_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_LDO_W_CONFIG_ALL_BITS 14
 #define SJC16_DDR4_PHY_DQ_BYTE3_LDO_W_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_LDO_W_CONFIG_ALL_MASK 0x3fff
 #define SJC16_DDR4_PHY_DQ_BYTE3_LDO_W_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_LDO_W_CONFIG_ALL_BITS 14
 #define SJC16_DDR4_PHY_DQ_BYTE3_LDO_W_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_LDO_W_CONFIG_DATAMASK 0x000033ff
 #define SJC16_DDR4_PHY_DQ_BYTE3_LDO_W_CONFIG_RDWRMASK 0xffffcc00
 #define SJC16_DDR4_PHY_DQ_BYTE3_LDO_W_CONFIG_RESETVALUE 0x0000
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_OPERATION_CONFIG 0x1023cca4
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_OPERATION_CONFIG_BASE 0xca4
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_OPERATION_CONFIG_CLEAR_ACTIVITY_STATS_MASK 0x10000000
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_OPERATION_CONFIG_CLEAR_ACTIVITY_STATS_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_OPERATION_CONFIG_CLEAR_ACTIVITY_STATS_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_OPERATION_CONFIG_CLEAR_ACTIVITY_STATS_SHIFT 28
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_OPERATION_CONFIG_CLEAR_ACTIVITY_STATS_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_OPERATION_CONFIG_FIFO_W2R_MIN_DELAY_2_MASK 0x8000000
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_OPERATION_CONFIG_FIFO_W2R_MIN_DELAY_2_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_OPERATION_CONFIG_FIFO_W2R_MIN_DELAY_2_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_OPERATION_CONFIG_FIFO_W2R_MIN_DELAY_2_SHIFT 27
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_OPERATION_CONFIG_FIFO_W2R_MIN_DELAY_2_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_OPERATION_CONFIG_ROLLOVER_MODE_MASK 0x7000000
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_OPERATION_CONFIG_ROLLOVER_MODE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_OPERATION_CONFIG_ROLLOVER_MODE_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_OPERATION_CONFIG_ROLLOVER_MODE_SHIFT 24
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_OPERATION_CONFIG_ROLLOVER_MODE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_OPERATION_CONFIG_HALF_RATE_MODE_MASK 0x800000
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_OPERATION_CONFIG_HALF_RATE_MODE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_OPERATION_CONFIG_HALF_RATE_MODE_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_OPERATION_CONFIG_HALF_RATE_MODE_SHIFT 23
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_OPERATION_CONFIG_HALF_RATE_MODE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_OPERATION_CONFIG_INIT_TRACK_OPTIONS_MASK 0x600000
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_OPERATION_CONFIG_INIT_TRACK_OPTIONS_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_OPERATION_CONFIG_INIT_TRACK_OPTIONS_BITS 2
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_OPERATION_CONFIG_INIT_TRACK_OPTIONS_SHIFT 21
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_OPERATION_CONFIG_INIT_TRACK_OPTIONS_RESETVALUE 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_OPERATION_CONFIG_INIT_TRACK_TRANSITION_MASK 0x100000
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_OPERATION_CONFIG_INIT_TRACK_TRANSITION_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_OPERATION_CONFIG_INIT_TRACK_TRANSITION_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_OPERATION_CONFIG_INIT_TRACK_TRANSITION_SHIFT 20
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_OPERATION_CONFIG_INIT_TRACK_TRANSITION_RESETVALUE 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_OPERATION_CONFIG_ACCU_POS_THRESHOLD_MASK 0xff000
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_OPERATION_CONFIG_ACCU_POS_THRESHOLD_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_OPERATION_CONFIG_ACCU_POS_THRESHOLD_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_OPERATION_CONFIG_ACCU_POS_THRESHOLD_SHIFT 12
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_OPERATION_CONFIG_ACCU_POS_THRESHOLD_RESETVALUE 0x10
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_OPERATION_CONFIG_ACCU_LOAD_VALUE_MASK 0xff0
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_OPERATION_CONFIG_ACCU_LOAD_VALUE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_OPERATION_CONFIG_ACCU_LOAD_VALUE_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_OPERATION_CONFIG_ACCU_LOAD_VALUE_SHIFT 4
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_OPERATION_CONFIG_ACCU_LOAD_VALUE_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_OPERATION_CONFIG_ACCU_LOAD_MASK 0x8
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_OPERATION_CONFIG_ACCU_LOAD_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_OPERATION_CONFIG_ACCU_LOAD_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_OPERATION_CONFIG_ACCU_LOAD_SHIFT 3
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_OPERATION_CONFIG_ACCU_LOAD_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_OPERATION_CONFIG_UPDATE_MODE_MASK 0x6
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_OPERATION_CONFIG_UPDATE_MODE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_OPERATION_CONFIG_UPDATE_MODE_BITS 2
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_OPERATION_CONFIG_UPDATE_MODE_SHIFT 1
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_OPERATION_CONFIG_UPDATE_MODE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_OPERATION_CONFIG_ENABLE_MASK 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_OPERATION_CONFIG_ENABLE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_OPERATION_CONFIG_ENABLE_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_OPERATION_CONFIG_ENABLE_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_OPERATION_CONFIG_ENABLE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_OPERATION_CONFIG_RESERVED_MASK 0xe0000000
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_OPERATION_CONFIG_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_OPERATION_CONFIG_RESERVED_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_OPERATION_CONFIG_RESERVED_SHIFT 29
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_OPERATION_CONFIG_ALL_MASK 0x1fffffff
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_OPERATION_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_OPERATION_CONFIG_ALL_BITS 29
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_OPERATION_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_OPERATION_CONFIG_ALL_MASK 0x1fffffff
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_OPERATION_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_OPERATION_CONFIG_ALL_BITS 29
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_OPERATION_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_OPERATION_CONFIG_DATAMASK 0x1fffffff
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_OPERATION_CONFIG_RDWRMASK 0xe0000000
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_OPERATION_CONFIG_RESETVALUE 0x00310000
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_UPDATE_CONFIG 0x1023cca8
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_UPDATE_CONFIG_BASE 0xca8
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_UPDATE_CONFIG_ROLLOVER_PHASE_GAP_MASK 0xfc000000
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_UPDATE_CONFIG_ROLLOVER_PHASE_GAP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_UPDATE_CONFIG_ROLLOVER_PHASE_GAP_BITS 6
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_UPDATE_CONFIG_ROLLOVER_PHASE_GAP_SHIFT 26
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_UPDATE_CONFIG_ROLLOVER_PHASE_GAP_RESETVALUE 0x3
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_UPDATE_CONFIG_ROLLOVER_AMOUNT_MASK 0x1ff0000
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_UPDATE_CONFIG_ROLLOVER_AMOUNT_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_UPDATE_CONFIG_ROLLOVER_AMOUNT_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_UPDATE_CONFIG_ROLLOVER_AMOUNT_SHIFT 16
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_UPDATE_CONFIG_ROLLOVER_AMOUNT_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_UPDATE_CONFIG_UPDATE_ENABLE_DELAY_MASK 0x3f00
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_UPDATE_CONFIG_UPDATE_ENABLE_DELAY_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_UPDATE_CONFIG_UPDATE_ENABLE_DELAY_BITS 6
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_UPDATE_CONFIG_UPDATE_ENABLE_DELAY_SHIFT 8
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_UPDATE_CONFIG_UPDATE_ENABLE_DELAY_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_UPDATE_CONFIG_IMMEDIATE_UPDATE_THRESHOLD_MASK 0xf0
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_UPDATE_CONFIG_IMMEDIATE_UPDATE_THRESHOLD_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_UPDATE_CONFIG_IMMEDIATE_UPDATE_THRESHOLD_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_UPDATE_CONFIG_IMMEDIATE_UPDATE_THRESHOLD_SHIFT 4
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_UPDATE_CONFIG_IMMEDIATE_UPDATE_THRESHOLD_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_UPDATE_CONFIG_VDL_UPDATE_GAP_MASK 0xf
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_UPDATE_CONFIG_VDL_UPDATE_GAP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_UPDATE_CONFIG_VDL_UPDATE_GAP_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_UPDATE_CONFIG_VDL_UPDATE_GAP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_UPDATE_CONFIG_VDL_UPDATE_GAP_RESETVALUE 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_UPDATE_CONFIG_ALL_MASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_UPDATE_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_UPDATE_CONFIG_ALL_BITS 32
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_UPDATE_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_UPDATE_CONFIG_ALL_MASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_UPDATE_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_UPDATE_CONFIG_ALL_BITS 32
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_UPDATE_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_UPDATE_CONFIG_DATAMASK 0xfdff3fff
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_UPDATE_CONFIG_RDWRMASK 0x0200c000
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_UPDATE_CONFIG_RESETVALUE 0x0c000001
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_TRACK_CONFIG 0x1023ccac
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_TRACK_CONFIG_BASE 0xcac
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_TRACK_CONFIG_SEARCH_ACTIVE_TIMEOUT_MASK 0xf000
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_TRACK_CONFIG_SEARCH_ACTIVE_TIMEOUT_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_TRACK_CONFIG_SEARCH_ACTIVE_TIMEOUT_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_TRACK_CONFIG_SEARCH_ACTIVE_TIMEOUT_SHIFT 12
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_TRACK_CONFIG_SEARCH_ACTIVE_TIMEOUT_RESETVALUE 0xf
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_TRACK_CONFIG_TRACK_ACTIVE_TIMEOUT_MASK 0xf00
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_TRACK_CONFIG_TRACK_ACTIVE_TIMEOUT_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_TRACK_CONFIG_TRACK_ACTIVE_TIMEOUT_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_TRACK_CONFIG_TRACK_ACTIVE_TIMEOUT_SHIFT 8
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_TRACK_CONFIG_TRACK_ACTIVE_TIMEOUT_RESETVALUE 0xf
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_TRACK_CONFIG_ACCU_ACTIVE_TIMEOUT_MASK 0xff
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_TRACK_CONFIG_ACCU_ACTIVE_TIMEOUT_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_TRACK_CONFIG_ACCU_ACTIVE_TIMEOUT_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_TRACK_CONFIG_ACCU_ACTIVE_TIMEOUT_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_TRACK_CONFIG_ACCU_ACTIVE_TIMEOUT_RESETVALUE 0xff
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_TRACK_CONFIG_RESERVED_MASK 0xffff0000
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_TRACK_CONFIG_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_TRACK_CONFIG_RESERVED_BITS 16
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_TRACK_CONFIG_RESERVED_SHIFT 16
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_TRACK_CONFIG_ALL_MASK 0xffff
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_TRACK_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_TRACK_CONFIG_ALL_BITS 16
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_TRACK_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_TRACK_CONFIG_ALL_MASK 0xffff
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_TRACK_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_TRACK_CONFIG_ALL_BITS 16
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_TRACK_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_TRACK_CONFIG_DATAMASK 0x0000ffff
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_TRACK_CONFIG_RDWRMASK 0xffff0000
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_TRACK_CONFIG_RESETVALUE 0xffff
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_TIMING_CONFIG 0x1023ccb0
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_TIMING_CONFIG_BASE 0xcb0
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_TIMING_CONFIG_DATA_VALID_WR2RD_DELAY_LOAD_VALUE_MASK 0xf0000
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_TIMING_CONFIG_DATA_VALID_WR2RD_DELAY_LOAD_VALUE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_TIMING_CONFIG_DATA_VALID_WR2RD_DELAY_LOAD_VALUE_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_TIMING_CONFIG_DATA_VALID_WR2RD_DELAY_LOAD_VALUE_SHIFT 16
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_TIMING_CONFIG_DATA_VALID_WR2RD_DELAY_LOAD_VALUE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_TIMING_CONFIG_EDC_VALID_WR2RD_DELAY_LOAD_VALUE_MASK 0xf000
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_TIMING_CONFIG_EDC_VALID_WR2RD_DELAY_LOAD_VALUE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_TIMING_CONFIG_EDC_VALID_WR2RD_DELAY_LOAD_VALUE_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_TIMING_CONFIG_EDC_VALID_WR2RD_DELAY_LOAD_VALUE_SHIFT 12
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_TIMING_CONFIG_EDC_VALID_WR2RD_DELAY_LOAD_VALUE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_TIMING_CONFIG_DATA_READ_UI_SHIFT_LOAD_VALUE_MASK 0x700
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_TIMING_CONFIG_DATA_READ_UI_SHIFT_LOAD_VALUE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_TIMING_CONFIG_DATA_READ_UI_SHIFT_LOAD_VALUE_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_TIMING_CONFIG_DATA_READ_UI_SHIFT_LOAD_VALUE_SHIFT 8
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_TIMING_CONFIG_DATA_READ_UI_SHIFT_LOAD_VALUE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_TIMING_CONFIG_EDC_READ_UI_SHIFT_LOAD_VALUE_MASK 0x70
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_TIMING_CONFIG_EDC_READ_UI_SHIFT_LOAD_VALUE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_TIMING_CONFIG_EDC_READ_UI_SHIFT_LOAD_VALUE_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_TIMING_CONFIG_EDC_READ_UI_SHIFT_LOAD_VALUE_SHIFT 4
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_TIMING_CONFIG_EDC_READ_UI_SHIFT_LOAD_VALUE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_TIMING_CONFIG_CLEAR_VDL_STATS_ON_ROLLOVER_MASK 0x8
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_TIMING_CONFIG_CLEAR_VDL_STATS_ON_ROLLOVER_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_TIMING_CONFIG_CLEAR_VDL_STATS_ON_ROLLOVER_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_TIMING_CONFIG_CLEAR_VDL_STATS_ON_ROLLOVER_SHIFT 3
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_TIMING_CONFIG_CLEAR_VDL_STATS_ON_ROLLOVER_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_TIMING_CONFIG_CLEAR_VDL_STATS_MASK 0x4
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_TIMING_CONFIG_CLEAR_VDL_STATS_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_TIMING_CONFIG_CLEAR_VDL_STATS_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_TIMING_CONFIG_CLEAR_VDL_STATS_SHIFT 2
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_TIMING_CONFIG_CLEAR_VDL_STATS_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_TIMING_CONFIG_VDL_SWITCH_MASK 0x2
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_TIMING_CONFIG_VDL_SWITCH_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_TIMING_CONFIG_VDL_SWITCH_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_TIMING_CONFIG_VDL_SWITCH_SHIFT 1
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_TIMING_CONFIG_VDL_SWITCH_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_TIMING_CONFIG_VDL_LOAD_MASK 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_TIMING_CONFIG_VDL_LOAD_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_TIMING_CONFIG_VDL_LOAD_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_TIMING_CONFIG_VDL_LOAD_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_TIMING_CONFIG_VDL_LOAD_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_TIMING_CONFIG_RESERVED_0_MASK 0xfff00000
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_TIMING_CONFIG_RESERVED_0_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_TIMING_CONFIG_RESERVED_0_BITS 12
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_TIMING_CONFIG_RESERVED_0_SHIFT 20
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_TIMING_CONFIG_RESERVED_MASK 0xfff00000
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_TIMING_CONFIG_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_TIMING_CONFIG_RESERVED_BITS 12
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_TIMING_CONFIG_RESERVED_SHIFT 20
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_TIMING_CONFIG_ALL_MASK 0xfffff
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_TIMING_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_TIMING_CONFIG_ALL_BITS 20
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_TIMING_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_TIMING_CONFIG_ALL_MASK 0xfffff
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_TIMING_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_TIMING_CONFIG_ALL_BITS 20
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_TIMING_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_TIMING_CONFIG_DATAMASK 0x000ff77f
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_TIMING_CONFIG_RDWRMASK 0xfff00880
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_TIMING_CONFIG_RESETVALUE 0x00000
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_VDL_CAP_CONFIG 0x1023ccb4
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_VDL_CAP_CONFIG_BASE 0xcb4
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_VDL_CAP_CONFIG_FLEXIBLE_VDL_CAP_MASK 0x10000000
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_VDL_CAP_CONFIG_FLEXIBLE_VDL_CAP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_VDL_CAP_CONFIG_FLEXIBLE_VDL_CAP_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_VDL_CAP_CONFIG_FLEXIBLE_VDL_CAP_SHIFT 28
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_VDL_CAP_CONFIG_FLEXIBLE_VDL_CAP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_VDL_CAP_CONFIG_VDL_MAX_VALUE_CAP_MASK 0x1ff0000
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_VDL_CAP_CONFIG_VDL_MAX_VALUE_CAP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_VDL_CAP_CONFIG_VDL_MAX_VALUE_CAP_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_VDL_CAP_CONFIG_VDL_MAX_VALUE_CAP_SHIFT 16
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_VDL_CAP_CONFIG_VDL_MAX_VALUE_CAP_RESETVALUE 0x1ff
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_VDL_CAP_CONFIG_VDL_MIN_VALUE_CAP_MASK 0x1ff
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_VDL_CAP_CONFIG_VDL_MIN_VALUE_CAP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_VDL_CAP_CONFIG_VDL_MIN_VALUE_CAP_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_VDL_CAP_CONFIG_VDL_MIN_VALUE_CAP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_VDL_CAP_CONFIG_VDL_MIN_VALUE_CAP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_VDL_CAP_CONFIG_RESERVED_0_MASK 0xe0000000
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_VDL_CAP_CONFIG_RESERVED_0_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_VDL_CAP_CONFIG_RESERVED_0_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_VDL_CAP_CONFIG_RESERVED_0_SHIFT 29
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_VDL_CAP_CONFIG_RESERVED_1_MASK 0xe000000
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_VDL_CAP_CONFIG_RESERVED_1_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_VDL_CAP_CONFIG_RESERVED_1_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_VDL_CAP_CONFIG_RESERVED_1_SHIFT 25
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_VDL_CAP_CONFIG_RESERVED_2_MASK 0xfe00
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_VDL_CAP_CONFIG_RESERVED_2_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_VDL_CAP_CONFIG_RESERVED_2_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_VDL_CAP_CONFIG_RESERVED_2_SHIFT 9
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_VDL_CAP_CONFIG_RESERVED_MASK 0xe0000000
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_VDL_CAP_CONFIG_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_VDL_CAP_CONFIG_RESERVED_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_VDL_CAP_CONFIG_RESERVED_SHIFT 29
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_VDL_CAP_CONFIG_ALL_MASK 0x1fffffff
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_VDL_CAP_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_VDL_CAP_CONFIG_ALL_BITS 29
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_VDL_CAP_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_VDL_CAP_CONFIG_ALL_MASK 0x1fffffff
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_VDL_CAP_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_VDL_CAP_CONFIG_ALL_BITS 29
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_VDL_CAP_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_VDL_CAP_CONFIG_DATAMASK 0x11ff01ff
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_VDL_CAP_CONFIG_RDWRMASK 0xee00fe00
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_VDL_CAP_CONFIG_RESETVALUE 0x01ff0000
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_P_VDL_CONFIG 0x1023ccb8
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_P_VDL_CONFIG_BASE 0xcb8
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_P_VDL_CONFIG_DP_VDL_LOAD_VALUE_MASK 0x1ff0000
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_P_VDL_CONFIG_DP_VDL_LOAD_VALUE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_P_VDL_CONFIG_DP_VDL_LOAD_VALUE_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_P_VDL_CONFIG_DP_VDL_LOAD_VALUE_SHIFT 16
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_P_VDL_CONFIG_DP_VDL_LOAD_VALUE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_P_VDL_CONFIG_EP_VDL_LOAD_VALUE_MASK 0x1ff
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_P_VDL_CONFIG_EP_VDL_LOAD_VALUE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_P_VDL_CONFIG_EP_VDL_LOAD_VALUE_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_P_VDL_CONFIG_EP_VDL_LOAD_VALUE_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_P_VDL_CONFIG_EP_VDL_LOAD_VALUE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_P_VDL_CONFIG_RESERVED_MASK 0xfe000000
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_P_VDL_CONFIG_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_P_VDL_CONFIG_RESERVED_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_P_VDL_CONFIG_RESERVED_SHIFT 25
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_P_VDL_CONFIG_ALL_MASK 0x1ffffff
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_P_VDL_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_P_VDL_CONFIG_ALL_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_P_VDL_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_P_VDL_CONFIG_ALL_MASK 0x1ffffff
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_P_VDL_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_P_VDL_CONFIG_ALL_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_P_VDL_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_P_VDL_CONFIG_DATAMASK 0x01ff01ff
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_P_VDL_CONFIG_RDWRMASK 0xfe00fe00
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_P_VDL_CONFIG_RESETVALUE 0x0000000
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_N_VDL_CONFIG 0x1023ccbc
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_N_VDL_CONFIG_BASE 0xcbc
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_N_VDL_CONFIG_DN_VDL_LOAD_VALUE_MASK 0x1ff0000
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_N_VDL_CONFIG_DN_VDL_LOAD_VALUE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_N_VDL_CONFIG_DN_VDL_LOAD_VALUE_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_N_VDL_CONFIG_DN_VDL_LOAD_VALUE_SHIFT 16
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_N_VDL_CONFIG_DN_VDL_LOAD_VALUE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_N_VDL_CONFIG_EN_VDL_LOAD_VALUE_MASK 0x1ff
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_N_VDL_CONFIG_EN_VDL_LOAD_VALUE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_N_VDL_CONFIG_EN_VDL_LOAD_VALUE_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_N_VDL_CONFIG_EN_VDL_LOAD_VALUE_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_N_VDL_CONFIG_EN_VDL_LOAD_VALUE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_N_VDL_CONFIG_RESERVED_MASK 0xfe000000
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_N_VDL_CONFIG_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_N_VDL_CONFIG_RESERVED_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_N_VDL_CONFIG_RESERVED_SHIFT 25
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_N_VDL_CONFIG_ALL_MASK 0x1ffffff
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_N_VDL_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_N_VDL_CONFIG_ALL_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_N_VDL_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_N_VDL_CONFIG_ALL_MASK 0x1ffffff
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_N_VDL_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_N_VDL_CONFIG_ALL_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_N_VDL_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_N_VDL_CONFIG_DATAMASK 0x01ff01ff
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_N_VDL_CONFIG_RDWRMASK 0xfe00fe00
 #define SJC16_DDR4_PHY_DQ_BYTE3_CDR_N_VDL_CONFIG_RESETVALUE 0x0000000
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_P_VDL 0x1023ccc0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_P_VDL_BASE 0xcc0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_P_VDL_DP_VDL_VALUE_MASK 0x1ff0000
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_P_VDL_DP_VDL_VALUE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_P_VDL_DP_VDL_VALUE_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_P_VDL_DP_VDL_VALUE_SHIFT 16
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_P_VDL_DP_VDL_VALUE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_P_VDL_EP_VDL_VALUE_MASK 0x1ff
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_P_VDL_EP_VDL_VALUE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_P_VDL_EP_VDL_VALUE_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_P_VDL_EP_VDL_VALUE_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_P_VDL_EP_VDL_VALUE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_P_VDL_RESERVED_MASK 0xfe000000
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_P_VDL_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_P_VDL_RESERVED_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_P_VDL_RESERVED_SHIFT 25
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_P_VDL_ALL_MASK 0x1ffffff
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_P_VDL_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_P_VDL_ALL_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_P_VDL_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_P_VDL_ALL_MASK 0x1ffffff
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_P_VDL_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_P_VDL_ALL_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_P_VDL_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_P_VDL_DATAMASK 0x01ff01ff
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_P_VDL_RDWRMASK 0xfe00fe00
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_P_VDL_RESETVALUE 0x0000000
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_N_VDL 0x1023ccc4
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_N_VDL_BASE 0xcc4
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_N_VDL_DN_VDL_VALUE_MASK 0x1ff0000
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_N_VDL_DN_VDL_VALUE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_N_VDL_DN_VDL_VALUE_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_N_VDL_DN_VDL_VALUE_SHIFT 16
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_N_VDL_DN_VDL_VALUE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_N_VDL_EN_VDL_VALUE_MASK 0x1ff
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_N_VDL_EN_VDL_VALUE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_N_VDL_EN_VDL_VALUE_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_N_VDL_EN_VDL_VALUE_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_N_VDL_EN_VDL_VALUE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_N_VDL_RESERVED_MASK 0xfe000000
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_N_VDL_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_N_VDL_RESERVED_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_N_VDL_RESERVED_SHIFT 25
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_N_VDL_ALL_MASK 0x1ffffff
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_N_VDL_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_N_VDL_ALL_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_N_VDL_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_N_VDL_ALL_MASK 0x1ffffff
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_N_VDL_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_N_VDL_ALL_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_N_VDL_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_N_VDL_DATAMASK 0x01ff01ff
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_N_VDL_RDWRMASK 0xfe00fe00
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_N_VDL_RESETVALUE 0x0000000
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_EP_VDL_STAT 0x1023ccc8
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_EP_VDL_STAT_BASE 0xcc8
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_EP_VDL_STAT_MAX_VDL_VALUE_MASK 0x1ff0000
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_EP_VDL_STAT_MAX_VDL_VALUE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_EP_VDL_STAT_MAX_VDL_VALUE_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_EP_VDL_STAT_MAX_VDL_VALUE_SHIFT 16
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_EP_VDL_STAT_MAX_VDL_VALUE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_EP_VDL_STAT_MIN_VDL_VALUE_MASK 0x1ff
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_EP_VDL_STAT_MIN_VDL_VALUE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_EP_VDL_STAT_MIN_VDL_VALUE_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_EP_VDL_STAT_MIN_VDL_VALUE_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_EP_VDL_STAT_MIN_VDL_VALUE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_EP_VDL_STAT_RESERVED_MASK 0xfe000000
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_EP_VDL_STAT_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_EP_VDL_STAT_RESERVED_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_EP_VDL_STAT_RESERVED_SHIFT 25
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_EP_VDL_STAT_ALL_MASK 0x1ffffff
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_EP_VDL_STAT_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_EP_VDL_STAT_ALL_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_EP_VDL_STAT_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_EP_VDL_STAT_ALL_MASK 0x1ffffff
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_EP_VDL_STAT_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_EP_VDL_STAT_ALL_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_EP_VDL_STAT_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_EP_VDL_STAT_DATAMASK 0x01ff01ff
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_EP_VDL_STAT_RDWRMASK 0xfe00fe00
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_EP_VDL_STAT_RESETVALUE 0x0000000
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_DP_VDL_STAT 0x1023cccc
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_DP_VDL_STAT_BASE 0xccc
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_DP_VDL_STAT_MAX_VDL_VALUE_MASK 0x1ff0000
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_DP_VDL_STAT_MAX_VDL_VALUE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_DP_VDL_STAT_MAX_VDL_VALUE_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_DP_VDL_STAT_MAX_VDL_VALUE_SHIFT 16
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_DP_VDL_STAT_MAX_VDL_VALUE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_DP_VDL_STAT_MIN_VDL_VALUE_MASK 0x1ff
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_DP_VDL_STAT_MIN_VDL_VALUE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_DP_VDL_STAT_MIN_VDL_VALUE_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_DP_VDL_STAT_MIN_VDL_VALUE_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_DP_VDL_STAT_MIN_VDL_VALUE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_DP_VDL_STAT_RESERVED_MASK 0xfe000000
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_DP_VDL_STAT_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_DP_VDL_STAT_RESERVED_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_DP_VDL_STAT_RESERVED_SHIFT 25
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_DP_VDL_STAT_ALL_MASK 0x1ffffff
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_DP_VDL_STAT_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_DP_VDL_STAT_ALL_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_DP_VDL_STAT_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_DP_VDL_STAT_ALL_MASK 0x1ffffff
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_DP_VDL_STAT_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_DP_VDL_STAT_ALL_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_DP_VDL_STAT_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_DP_VDL_STAT_DATAMASK 0x01ff01ff
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_DP_VDL_STAT_RDWRMASK 0xfe00fe00
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_DP_VDL_STAT_RESETVALUE 0x0000000
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_EN_VDL_STAT 0x1023ccd0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_EN_VDL_STAT_BASE 0xcd0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_EN_VDL_STAT_MAX_VDL_VALUE_MASK 0x1ff0000
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_EN_VDL_STAT_MAX_VDL_VALUE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_EN_VDL_STAT_MAX_VDL_VALUE_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_EN_VDL_STAT_MAX_VDL_VALUE_SHIFT 16
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_EN_VDL_STAT_MAX_VDL_VALUE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_EN_VDL_STAT_MIN_VDL_VALUE_MASK 0x1ff
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_EN_VDL_STAT_MIN_VDL_VALUE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_EN_VDL_STAT_MIN_VDL_VALUE_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_EN_VDL_STAT_MIN_VDL_VALUE_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_EN_VDL_STAT_MIN_VDL_VALUE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_EN_VDL_STAT_RESERVED_MASK 0xfe000000
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_EN_VDL_STAT_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_EN_VDL_STAT_RESERVED_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_EN_VDL_STAT_RESERVED_SHIFT 25
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_EN_VDL_STAT_ALL_MASK 0x1ffffff
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_EN_VDL_STAT_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_EN_VDL_STAT_ALL_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_EN_VDL_STAT_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_EN_VDL_STAT_ALL_MASK 0x1ffffff
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_EN_VDL_STAT_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_EN_VDL_STAT_ALL_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_EN_VDL_STAT_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_EN_VDL_STAT_DATAMASK 0x01ff01ff
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_EN_VDL_STAT_RDWRMASK 0xfe00fe00
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_EN_VDL_STAT_RESETVALUE 0x0000000
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_DN_VDL_STAT 0x1023ccd4
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_DN_VDL_STAT_BASE 0xcd4
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_DN_VDL_STAT_MAX_VDL_VALUE_MASK 0x1ff0000
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_DN_VDL_STAT_MAX_VDL_VALUE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_DN_VDL_STAT_MAX_VDL_VALUE_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_DN_VDL_STAT_MAX_VDL_VALUE_SHIFT 16
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_DN_VDL_STAT_MAX_VDL_VALUE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_DN_VDL_STAT_MIN_VDL_VALUE_MASK 0x1ff
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_DN_VDL_STAT_MIN_VDL_VALUE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_DN_VDL_STAT_MIN_VDL_VALUE_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_DN_VDL_STAT_MIN_VDL_VALUE_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_DN_VDL_STAT_MIN_VDL_VALUE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_DN_VDL_STAT_RESERVED_MASK 0xfe000000
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_DN_VDL_STAT_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_DN_VDL_STAT_RESERVED_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_DN_VDL_STAT_RESERVED_SHIFT 25
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_DN_VDL_STAT_ALL_MASK 0x1ffffff
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_DN_VDL_STAT_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_DN_VDL_STAT_ALL_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_DN_VDL_STAT_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_DN_VDL_STAT_ALL_MASK 0x1ffffff
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_DN_VDL_STAT_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_DN_VDL_STAT_ALL_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_DN_VDL_STAT_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_DN_VDL_STAT_DATAMASK 0x01ff01ff
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_DN_VDL_STAT_RDWRMASK 0xfe00fe00
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_DN_VDL_STAT_RESETVALUE 0x0000000
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_OPERATION 0x1023ccd8
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_OPERATION_BASE 0xcd8
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_OPERATION_ROLLOVER_OVERFLOW_MASK 0x10000000
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_OPERATION_ROLLOVER_OVERFLOW_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_OPERATION_ROLLOVER_OVERFLOW_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_OPERATION_ROLLOVER_OVERFLOW_SHIFT 28
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_OPERATION_ROLLOVER_OVERFLOW_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_OPERATION_ROLLOVER_COUNT_MASK 0xff00000
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_OPERATION_ROLLOVER_COUNT_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_OPERATION_ROLLOVER_COUNT_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_OPERATION_ROLLOVER_COUNT_SHIFT 20
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_OPERATION_ROLLOVER_COUNT_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_OPERATION_SEARCH_ACTIVE_RETRIGGERED_MASK 0x20000
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_OPERATION_SEARCH_ACTIVE_RETRIGGERED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_OPERATION_SEARCH_ACTIVE_RETRIGGERED_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_OPERATION_SEARCH_ACTIVE_RETRIGGERED_SHIFT 17
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_OPERATION_SEARCH_ACTIVE_RETRIGGERED_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_OPERATION_INIT_SEARCH_COMPLETE_MASK 0x10000
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_OPERATION_INIT_SEARCH_COMPLETE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_OPERATION_INIT_SEARCH_COMPLETE_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_OPERATION_INIT_SEARCH_COMPLETE_SHIFT 16
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_OPERATION_INIT_SEARCH_COMPLETE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_OPERATION_INIT_SEARCH_ACTIVE_MASK 0x8000
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_OPERATION_INIT_SEARCH_ACTIVE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_OPERATION_INIT_SEARCH_ACTIVE_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_OPERATION_INIT_SEARCH_ACTIVE_SHIFT 15
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_OPERATION_INIT_SEARCH_ACTIVE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_OPERATION_TRACK_ACTIVE_LOST_MASK 0x4000
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_OPERATION_TRACK_ACTIVE_LOST_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_OPERATION_TRACK_ACTIVE_LOST_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_OPERATION_TRACK_ACTIVE_LOST_SHIFT 14
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_OPERATION_TRACK_ACTIVE_LOST_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_OPERATION_INIT_TRACK_ACTIVE_MASK 0x2000
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_OPERATION_INIT_TRACK_ACTIVE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_OPERATION_INIT_TRACK_ACTIVE_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_OPERATION_INIT_TRACK_ACTIVE_SHIFT 13
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_OPERATION_INIT_TRACK_ACTIVE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_OPERATION_ACCU_ACTIVE_LOST_MASK 0x1000
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_OPERATION_ACCU_ACTIVE_LOST_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_OPERATION_ACCU_ACTIVE_LOST_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_OPERATION_ACCU_ACTIVE_LOST_SHIFT 12
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_OPERATION_ACCU_ACTIVE_LOST_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_OPERATION_INIT_ACCU_ACTIVE_MASK 0x800
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_OPERATION_INIT_ACCU_ACTIVE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_OPERATION_INIT_ACCU_ACTIVE_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_OPERATION_INIT_ACCU_ACTIVE_SHIFT 11
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_OPERATION_INIT_ACCU_ACTIVE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_OPERATION_SEARCH_ACTIVE_MASK 0x400
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_OPERATION_SEARCH_ACTIVE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_OPERATION_SEARCH_ACTIVE_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_OPERATION_SEARCH_ACTIVE_SHIFT 10
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_OPERATION_SEARCH_ACTIVE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_OPERATION_TRACK_ACTIVE_MASK 0x200
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_OPERATION_TRACK_ACTIVE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_OPERATION_TRACK_ACTIVE_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_OPERATION_TRACK_ACTIVE_SHIFT 9
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_OPERATION_TRACK_ACTIVE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_OPERATION_ACCU_ACTIVE_MASK 0x100
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_OPERATION_ACCU_ACTIVE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_OPERATION_ACCU_ACTIVE_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_OPERATION_ACCU_ACTIVE_SHIFT 8
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_OPERATION_ACCU_ACTIVE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_OPERATION_ACCU_VALUE_MASK 0xff
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_OPERATION_ACCU_VALUE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_OPERATION_ACCU_VALUE_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_OPERATION_ACCU_VALUE_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_OPERATION_ACCU_VALUE_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_OPERATION_RESERVED_MASK 0xe0000000
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_OPERATION_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_OPERATION_RESERVED_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_OPERATION_RESERVED_SHIFT 29
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_OPERATION_ALL_MASK 0x1fffffff
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_OPERATION_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_OPERATION_ALL_BITS 29
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_OPERATION_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_OPERATION_ALL_MASK 0x1fffffff
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_OPERATION_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_OPERATION_ALL_BITS 29
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_OPERATION_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_OPERATION_DATAMASK 0x1ff3ffff
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_OPERATION_RDWRMASK 0xe00c0000
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_OPERATION_RESETVALUE 0x00000000
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_TIMING 0x1023ccdc
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_TIMING_BASE 0xcdc
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_TIMING_DATA_VALID_WR2RD_DELAY_MASK 0xf0000
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_TIMING_DATA_VALID_WR2RD_DELAY_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_TIMING_DATA_VALID_WR2RD_DELAY_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_TIMING_DATA_VALID_WR2RD_DELAY_SHIFT 16
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_TIMING_DATA_VALID_WR2RD_DELAY_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_TIMING_EDC_VALID_WR2RD_DELAY_MASK 0xf000
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_TIMING_EDC_VALID_WR2RD_DELAY_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_TIMING_EDC_VALID_WR2RD_DELAY_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_TIMING_EDC_VALID_WR2RD_DELAY_SHIFT 12
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_TIMING_EDC_VALID_WR2RD_DELAY_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_TIMING_DATA_READ_UI_SHIFT_MASK 0x700
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_TIMING_DATA_READ_UI_SHIFT_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_TIMING_DATA_READ_UI_SHIFT_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_TIMING_DATA_READ_UI_SHIFT_SHIFT 8
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_TIMING_DATA_READ_UI_SHIFT_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_TIMING_EDC_READ_UI_SHIFT_MASK 0x70
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_TIMING_EDC_READ_UI_SHIFT_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_TIMING_EDC_READ_UI_SHIFT_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_TIMING_EDC_READ_UI_SHIFT_SHIFT 4
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_TIMING_EDC_READ_UI_SHIFT_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_TIMING_DATA_VALID_WR2RD_DELAY_DEC_MASK 0x8
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_TIMING_DATA_VALID_WR2RD_DELAY_DEC_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_TIMING_DATA_VALID_WR2RD_DELAY_DEC_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_TIMING_DATA_VALID_WR2RD_DELAY_DEC_SHIFT 3
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_TIMING_DATA_VALID_WR2RD_DELAY_DEC_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_TIMING_DATA_VALID_WR2RD_DELAY_INC_MASK 0x4
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_TIMING_DATA_VALID_WR2RD_DELAY_INC_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_TIMING_DATA_VALID_WR2RD_DELAY_INC_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_TIMING_DATA_VALID_WR2RD_DELAY_INC_SHIFT 2
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_TIMING_DATA_VALID_WR2RD_DELAY_INC_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_TIMING_EDC_VALID_WR2RD_DELAY_DEC_MASK 0x2
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_TIMING_EDC_VALID_WR2RD_DELAY_DEC_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_TIMING_EDC_VALID_WR2RD_DELAY_DEC_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_TIMING_EDC_VALID_WR2RD_DELAY_DEC_SHIFT 1
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_TIMING_EDC_VALID_WR2RD_DELAY_DEC_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_TIMING_EDC_VALID_WR2RD_DELAY_INC_MASK 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_TIMING_EDC_VALID_WR2RD_DELAY_INC_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_TIMING_EDC_VALID_WR2RD_DELAY_INC_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_TIMING_EDC_VALID_WR2RD_DELAY_INC_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_TIMING_EDC_VALID_WR2RD_DELAY_INC_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_TIMING_RESERVED_0_MASK 0xfff00000
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_TIMING_RESERVED_0_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_TIMING_RESERVED_0_BITS 12
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_TIMING_RESERVED_0_SHIFT 20
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_TIMING_RESERVED_MASK 0xfff00000
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_TIMING_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_TIMING_RESERVED_BITS 12
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_TIMING_RESERVED_SHIFT 20
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_TIMING_ALL_MASK 0xfffff
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_TIMING_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_TIMING_ALL_BITS 20
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_TIMING_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_TIMING_ALL_MASK 0xfffff
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_TIMING_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_TIMING_ALL_BITS 20
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_TIMING_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_TIMING_DATAMASK 0x000ff77f
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_TIMING_RDWRMASK 0xfff00880
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_CDR_TIMING_RESETVALUE 0x00000
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_FIFO_PTR 0x1023cce0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_FIFO_PTR_BASE 0xce0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_FIFO_PTR_RP_XMSB_MASK 0x20000
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_FIFO_PTR_RP_XMSB_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_FIFO_PTR_RP_XMSB_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_FIFO_PTR_RP_XMSB_SHIFT 17
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_FIFO_PTR_RP_XMSB_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_FIFO_PTR_RP_MASK 0x1f000
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_FIFO_PTR_RP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_FIFO_PTR_RP_BITS 5
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_FIFO_PTR_RP_SHIFT 12
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_FIFO_PTR_RP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_FIFO_PTR_WP1_XMSB_MASK 0x800
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_FIFO_PTR_WP1_XMSB_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_FIFO_PTR_WP1_XMSB_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_FIFO_PTR_WP1_XMSB_SHIFT 11
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_FIFO_PTR_WP1_XMSB_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_FIFO_PTR_WP1_MASK 0x7c0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_FIFO_PTR_WP1_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_FIFO_PTR_WP1_BITS 5
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_FIFO_PTR_WP1_SHIFT 6
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_FIFO_PTR_WP1_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_FIFO_PTR_WP0_XMSB_MASK 0x20
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_FIFO_PTR_WP0_XMSB_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_FIFO_PTR_WP0_XMSB_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_FIFO_PTR_WP0_XMSB_SHIFT 5
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_FIFO_PTR_WP0_XMSB_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_FIFO_PTR_WP0_MASK 0x1f
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_FIFO_PTR_WP0_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_FIFO_PTR_WP0_BITS 5
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_FIFO_PTR_WP0_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_FIFO_PTR_WP0_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_FIFO_PTR_RESERVED_MASK 0xfffc0000
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_FIFO_PTR_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_FIFO_PTR_RESERVED_BITS 14
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_FIFO_PTR_RESERVED_SHIFT 18
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_FIFO_PTR_ALL_MASK 0x3ffff
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_FIFO_PTR_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_FIFO_PTR_ALL_BITS 18
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_FIFO_PTR_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_FIFO_PTR_ALL_MASK 0x3ffff
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_FIFO_PTR_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_FIFO_PTR_ALL_BITS 18
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_FIFO_PTR_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_FIFO_PTR_DATAMASK 0x0003ffff
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_FIFO_PTR_RDWRMASK 0xfffc0000
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_FIFO_PTR_RESETVALUE 0x00000
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_FIFO_CTR 0x1023cce4
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_FIFO_CTR_BASE 0xce4
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_FIFO_CTR_MAX_WCOUNT_MASK 0x3f00
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_FIFO_CTR_MAX_WCOUNT_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_FIFO_CTR_MAX_WCOUNT_BITS 6
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_FIFO_CTR_MAX_WCOUNT_SHIFT 8
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_FIFO_CTR_MAX_WCOUNT_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_FIFO_CTR_CUR_WCOUNT_MASK 0xfc
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_FIFO_CTR_CUR_WCOUNT_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_FIFO_CTR_CUR_WCOUNT_BITS 6
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_FIFO_CTR_CUR_WCOUNT_SHIFT 2
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_FIFO_CTR_CUR_WCOUNT_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_FIFO_CTR_WFULL_MASK 0x2
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_FIFO_CTR_WFULL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_FIFO_CTR_WFULL_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_FIFO_CTR_WFULL_SHIFT 1
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_FIFO_CTR_WFULL_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_FIFO_CTR_WRITE_ERROR_MASK 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_FIFO_CTR_WRITE_ERROR_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_FIFO_CTR_WRITE_ERROR_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_FIFO_CTR_WRITE_ERROR_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_FIFO_CTR_WRITE_ERROR_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_FIFO_CTR_RESERVED_MASK 0xffffc000
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_FIFO_CTR_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_FIFO_CTR_RESERVED_BITS 18
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_FIFO_CTR_RESERVED_SHIFT 14
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_FIFO_CTR_ALL_MASK 0x3fff
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_FIFO_CTR_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_FIFO_CTR_ALL_BITS 14
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_FIFO_CTR_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_FIFO_CTR_ALL_MASK 0x3fff
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_FIFO_CTR_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_FIFO_CTR_ALL_BITS 14
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_FIFO_CTR_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_FIFO_CTR_DATAMASK 0x00003fff
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_FIFO_CTR_RDWRMASK 0xffffc000
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_FIFO_CTR_RESETVALUE 0x0000
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH 0x1023cce8
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_BASE 0xce8
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_PAST_STATE7_MASK 0x7000000
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_PAST_STATE7_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_PAST_STATE7_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_PAST_STATE7_SHIFT 24
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_PAST_STATE7_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_PAST_STATE6_MASK 0xe00000
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_PAST_STATE6_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_PAST_STATE6_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_PAST_STATE6_SHIFT 21
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_PAST_STATE6_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_PAST_STATE5_MASK 0x1c0000
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_PAST_STATE5_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_PAST_STATE5_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_PAST_STATE5_SHIFT 18
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_PAST_STATE5_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_PAST_STATE4_MASK 0x38000
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_PAST_STATE4_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_PAST_STATE4_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_PAST_STATE4_SHIFT 15
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_PAST_STATE4_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_PAST_STATE3_MASK 0x7000
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_PAST_STATE3_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_PAST_STATE3_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_PAST_STATE3_SHIFT 12
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_PAST_STATE3_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_PAST_STATE2_MASK 0xe00
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_PAST_STATE2_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_PAST_STATE2_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_PAST_STATE2_SHIFT 9
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_PAST_STATE2_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_PAST_STATE1_MASK 0x1c0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_PAST_STATE1_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_PAST_STATE1_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_PAST_STATE1_SHIFT 6
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_PAST_STATE1_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_PAST_STATE0_MASK 0x38
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_PAST_STATE0_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_PAST_STATE0_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_PAST_STATE0_SHIFT 3
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_PAST_STATE0_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_CUR_STATE_MASK 0x7
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_CUR_STATE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_CUR_STATE_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_CUR_STATE_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_CUR_STATE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_RESERVED_MASK 0xf8000000
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_RESERVED_BITS 5
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_RESERVED_SHIFT 27
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_ALL_MASK 0x7ffffff
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_ALL_BITS 27
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_ALL_MASK 0x7ffffff
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_ALL_BITS 27
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_DATAMASK 0x07ffffff
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_RDWRMASK 0xf8000000
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_RESETVALUE 0x0000000
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_ERR1 0x1023ccec
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_ERR1_BASE 0xcec
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_ERR1_RCMD_FIFO_RD_MASK 0x1000
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_ERR1_RCMD_FIFO_RD_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_ERR1_RCMD_FIFO_RD_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_ERR1_RCMD_FIFO_RD_SHIFT 12
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_ERR1_RCMD_FIFO_RD_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_ERR1_RCMD_FIFO_RDATA_MASK 0xff0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_ERR1_RCMD_FIFO_RDATA_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_ERR1_RCMD_FIFO_RDATA_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_ERR1_RCMD_FIFO_RDATA_SHIFT 4
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_ERR1_RCMD_FIFO_RDATA_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_ERR1_STATE_MASK 0xe
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_ERR1_STATE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_ERR1_STATE_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_ERR1_STATE_SHIFT 1
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_ERR1_STATE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_ERR1_ERROR_MASK 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_ERR1_ERROR_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_ERR1_ERROR_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_ERR1_ERROR_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_ERR1_ERROR_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_ERR1_RESERVED_MASK 0xffffe000
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_ERR1_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_ERR1_RESERVED_BITS 19
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_ERR1_RESERVED_SHIFT 13
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_ERR1_ALL_MASK 0x1fff
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_ERR1_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_ERR1_ALL_BITS 13
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_ERR1_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_ERR1_ALL_MASK 0x1fff
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_ERR1_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_ERR1_ALL_BITS 13
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_ERR1_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_ERR1_DATAMASK 0x00001fff
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_ERR1_RDWRMASK 0xffffe000
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_ERR1_RESETVALUE 0x0000
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_ERR2 0x1023ccf0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_ERR2_BASE 0xcf0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_ERR2_RCMD_FIFO_RD_MASK 0x1000
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_ERR2_RCMD_FIFO_RD_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_ERR2_RCMD_FIFO_RD_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_ERR2_RCMD_FIFO_RD_SHIFT 12
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_ERR2_RCMD_FIFO_RD_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_ERR2_RCMD_FIFO_RDATA_MASK 0xff0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_ERR2_RCMD_FIFO_RDATA_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_ERR2_RCMD_FIFO_RDATA_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_ERR2_RCMD_FIFO_RDATA_SHIFT 4
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_ERR2_RCMD_FIFO_RDATA_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_ERR2_STATE_MASK 0xe
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_ERR2_STATE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_ERR2_STATE_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_ERR2_STATE_SHIFT 1
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_ERR2_STATE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_ERR2_ERROR_MASK 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_ERR2_ERROR_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_ERR2_ERROR_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_ERR2_ERROR_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_ERR2_ERROR_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_ERR2_RESERVED_MASK 0xffffe000
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_ERR2_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_ERR2_RESERVED_BITS 19
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_ERR2_RESERVED_SHIFT 13
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_ERR2_ALL_MASK 0x1fff
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_ERR2_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_ERR2_ALL_BITS 13
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_ERR2_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_ERR2_ALL_MASK 0x1fff
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_ERR2_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_ERR2_ALL_BITS 13
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_ERR2_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_ERR2_DATAMASK 0x00001fff
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_ERR2_RDWRMASK 0xffffe000
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_ERR2_RESETVALUE 0x0000
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_ERR3 0x1023ccf4
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_ERR3_BASE 0xcf4
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_ERR3_EXP_RCMD_ID_MASK 0xfc00
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_ERR3_EXP_RCMD_ID_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_ERR3_EXP_RCMD_ID_BITS 6
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_ERR3_EXP_RCMD_ID_SHIFT 10
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_ERR3_EXP_RCMD_ID_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_ERR3_OBS_RCMD_ID_MASK 0x3f0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_ERR3_OBS_RCMD_ID_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_ERR3_OBS_RCMD_ID_BITS 6
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_ERR3_OBS_RCMD_ID_SHIFT 4
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_ERR3_OBS_RCMD_ID_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_ERR3_STATE_MASK 0xe
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_ERR3_STATE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_ERR3_STATE_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_ERR3_STATE_SHIFT 1
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_ERR3_STATE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_ERR3_ERROR_MASK 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_ERR3_ERROR_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_ERR3_ERROR_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_ERR3_ERROR_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_ERR3_ERROR_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_ERR3_RESERVED_MASK 0xffff0000
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_ERR3_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_ERR3_RESERVED_BITS 16
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_ERR3_RESERVED_SHIFT 16
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_ERR3_ALL_MASK 0xffff
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_ERR3_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_ERR3_ALL_BITS 16
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_ERR3_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_ERR3_ALL_MASK 0xffff
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_ERR3_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_ERR3_ALL_BITS 16
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_ERR3_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_ERR3_DATAMASK 0x0000ffff
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_ERR3_RDWRMASK 0xffff0000
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_ERR3_RESETVALUE 0x0000
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_RCMD_ID 0x1023ccf8
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_RCMD_ID_BASE 0xcf8
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_RCMD_ID_ID8_MASK 0xfc0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_RCMD_ID_ID8_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_RCMD_ID_ID8_BITS 6
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_RCMD_ID_ID8_SHIFT 6
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_RCMD_ID_ID8_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_RCMD_ID_ID4_MASK 0x3f
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_RCMD_ID_ID4_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_RCMD_ID_ID4_BITS 6
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_RCMD_ID_ID4_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_RCMD_ID_ID4_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_RCMD_ID_RESERVED_MASK 0xfffff000
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_RCMD_ID_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_RCMD_ID_RESERVED_BITS 20
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_RCMD_ID_RESERVED_SHIFT 12
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_RCMD_ID_ALL_MASK 0xfff
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_RCMD_ID_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_RCMD_ID_ALL_BITS 12
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_RCMD_ID_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_RCMD_ID_ALL_MASK 0xfff
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_RCMD_ID_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_RCMD_ID_ALL_BITS 12
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_RCMD_ID_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_RCMD_ID_DATAMASK 0x00000fff
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_RCMD_ID_RDWRMASK 0xfffff000
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_RCMD_ID_RESETVALUE 0x000
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RDATA_FIFO 0x1023ccfc
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RDATA_FIFO_BASE 0xcfc
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RDATA_FIFO_RP1_XMSB_MASK 0x4000
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RDATA_FIFO_RP1_XMSB_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RDATA_FIFO_RP1_XMSB_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RDATA_FIFO_RP1_XMSB_SHIFT 14
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RDATA_FIFO_RP1_XMSB_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RDATA_FIFO_RP1_MASK 0x3c00
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RDATA_FIFO_RP1_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RDATA_FIFO_RP1_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RDATA_FIFO_RP1_SHIFT 10
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RDATA_FIFO_RP1_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RDATA_FIFO_RP0_XMSB_MASK 0x200
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RDATA_FIFO_RP0_XMSB_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RDATA_FIFO_RP0_XMSB_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RDATA_FIFO_RP0_XMSB_SHIFT 9
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RDATA_FIFO_RP0_XMSB_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RDATA_FIFO_RP0_MASK 0x1e0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RDATA_FIFO_RP0_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RDATA_FIFO_RP0_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RDATA_FIFO_RP0_SHIFT 5
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RDATA_FIFO_RP0_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RDATA_FIFO_WP_XMSB_MASK 0x10
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RDATA_FIFO_WP_XMSB_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RDATA_FIFO_WP_XMSB_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RDATA_FIFO_WP_XMSB_SHIFT 4
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RDATA_FIFO_WP_XMSB_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RDATA_FIFO_WP_MASK 0xf
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RDATA_FIFO_WP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RDATA_FIFO_WP_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RDATA_FIFO_WP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RDATA_FIFO_WP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RDATA_FIFO_RESERVED_MASK 0xffff8000
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RDATA_FIFO_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RDATA_FIFO_RESERVED_BITS 17
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RDATA_FIFO_RESERVED_SHIFT 15
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RDATA_FIFO_ALL_MASK 0x7fff
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RDATA_FIFO_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RDATA_FIFO_ALL_BITS 15
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RDATA_FIFO_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RDATA_FIFO_ALL_MASK 0x7fff
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RDATA_FIFO_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RDATA_FIFO_ALL_BITS 15
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RDATA_FIFO_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RDATA_FIFO_DATAMASK 0x00007fff
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RDATA_FIFO_RDWRMASK 0xffff8000
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RDATA_FIFO_RESETVALUE 0x0000
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_FIFO 0x1023cd00
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_FIFO_BASE 0xd00
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_FIFO_RP_2G_XMSB_MASK 0x20000
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_FIFO_RP_2G_XMSB_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_FIFO_RP_2G_XMSB_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_FIFO_RP_2G_XMSB_SHIFT 17
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_FIFO_RP_2G_XMSB_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_FIFO_RP_2G_MASK 0x1f000
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_FIFO_RP_2G_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_FIFO_RP_2G_BITS 5
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_FIFO_RP_2G_SHIFT 12
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_FIFO_RP_2G_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_FIFO_RP_1G_XMSB_MASK 0x800
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_FIFO_RP_1G_XMSB_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_FIFO_RP_1G_XMSB_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_FIFO_RP_1G_XMSB_SHIFT 11
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_FIFO_RP_1G_XMSB_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_FIFO_RP_1G_MASK 0x7c0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_FIFO_RP_1G_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_FIFO_RP_1G_BITS 5
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_FIFO_RP_1G_SHIFT 6
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_FIFO_RP_1G_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_FIFO_WP_XMSB_MASK 0x20
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_FIFO_WP_XMSB_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_FIFO_WP_XMSB_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_FIFO_WP_XMSB_SHIFT 5
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_FIFO_WP_XMSB_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_FIFO_WP_MASK 0x1f
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_FIFO_WP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_FIFO_WP_BITS 5
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_FIFO_WP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_FIFO_WP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_FIFO_RESERVED_MASK 0xfffc0000
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_FIFO_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_FIFO_RESERVED_BITS 14
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_FIFO_RESERVED_SHIFT 18
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_FIFO_ALL_MASK 0x3ffff
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_FIFO_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_FIFO_ALL_BITS 18
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_FIFO_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_FIFO_ALL_MASK 0x3ffff
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_FIFO_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_FIFO_ALL_BITS 18
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_FIFO_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_FIFO_DATAMASK 0x0003ffff
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_FIFO_RDWRMASK 0xfffc0000
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_FIFO_RESETVALUE 0x00000
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_RCMD_ID 0x1023cd04
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_RCMD_ID_BASE 0xd04
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_RCMD_ID_ID8_MASK 0xfc0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_RCMD_ID_ID8_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_RCMD_ID_ID8_BITS 6
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_RCMD_ID_ID8_SHIFT 6
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_RCMD_ID_ID8_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_RCMD_ID_ID4_MASK 0x3f
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_RCMD_ID_ID4_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_RCMD_ID_ID4_BITS 6
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_RCMD_ID_ID4_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_RCMD_ID_ID4_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_RCMD_ID_RESERVED_MASK 0xfffff000
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_RCMD_ID_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_RCMD_ID_RESERVED_BITS 20
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_RCMD_ID_RESERVED_SHIFT 12
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_RCMD_ID_ALL_MASK 0xfff
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_RCMD_ID_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_RCMD_ID_ALL_BITS 12
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_RCMD_ID_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_RCMD_ID_ALL_MASK 0xfff
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_RCMD_ID_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_RCMD_ID_ALL_BITS 12
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_RCMD_ID_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_RCMD_ID_DATAMASK 0x00000fff
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_RCMD_ID_RDWRMASK 0xfffff000
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_RCMD_ID_RESETVALUE 0x000
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_ERR1 0x1023cd08
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_ERR1_BASE 0xd08
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_ERR1_NXT_RCMD_FIFO_WDATA1_MASK 0x7f800000
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_ERR1_NXT_RCMD_FIFO_WDATA1_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_ERR1_NXT_RCMD_FIFO_WDATA1_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_ERR1_NXT_RCMD_FIFO_WDATA1_SHIFT 23
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_ERR1_NXT_RCMD_FIFO_WDATA1_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_ERR1_NXT_RCMD_FIFO_WDATA0_MASK 0x7f8000
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_ERR1_NXT_RCMD_FIFO_WDATA0_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_ERR1_NXT_RCMD_FIFO_WDATA0_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_ERR1_NXT_RCMD_FIFO_WDATA0_SHIFT 15
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_ERR1_NXT_RCMD_FIFO_WDATA0_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_ERR1_NXT_RCMD_FIFO_WR1_MASK 0x4000
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_ERR1_NXT_RCMD_FIFO_WR1_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_ERR1_NXT_RCMD_FIFO_WR1_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_ERR1_NXT_RCMD_FIFO_WR1_SHIFT 14
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_ERR1_NXT_RCMD_FIFO_WR1_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_ERR1_NXT_RCMD_FIFO_WR0_MASK 0x2000
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_ERR1_NXT_RCMD_FIFO_WR0_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_ERR1_NXT_RCMD_FIFO_WR0_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_ERR1_NXT_RCMD_FIFO_WR0_SHIFT 13
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_ERR1_NXT_RCMD_FIFO_WR0_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_ERR1_NXT_RD_EN_UI23_MASK 0x1000
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_ERR1_NXT_RD_EN_UI23_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_ERR1_NXT_RD_EN_UI23_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_ERR1_NXT_RD_EN_UI23_SHIFT 12
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_ERR1_NXT_RD_EN_UI23_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_ERR1_NXT_RD_EN_UI01_MASK 0x800
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_ERR1_NXT_RD_EN_UI01_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_ERR1_NXT_RD_EN_UI01_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_ERR1_NXT_RD_EN_UI01_SHIFT 11
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_ERR1_NXT_RD_EN_UI01_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_ERR1_NXT_STATE_MASK 0x600
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_ERR1_NXT_STATE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_ERR1_NXT_STATE_BITS 2
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_ERR1_NXT_STATE_SHIFT 9
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_ERR1_NXT_STATE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_ERR1_RCMD_PAIR_MASK 0x1e0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_ERR1_RCMD_PAIR_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_ERR1_RCMD_PAIR_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_ERR1_RCMD_PAIR_SHIFT 5
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_ERR1_RCMD_PAIR_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_ERR1_RD_EN_UI23_MASK 0x10
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_ERR1_RD_EN_UI23_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_ERR1_RD_EN_UI23_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_ERR1_RD_EN_UI23_SHIFT 4
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_ERR1_RD_EN_UI23_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_ERR1_RD_EN_UI01_MASK 0x8
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_ERR1_RD_EN_UI01_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_ERR1_RD_EN_UI01_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_ERR1_RD_EN_UI01_SHIFT 3
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_ERR1_RD_EN_UI01_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_ERR1_STATE_MASK 0x6
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_ERR1_STATE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_ERR1_STATE_BITS 2
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_ERR1_STATE_SHIFT 1
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_ERR1_STATE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_ERR1_ERROR_MASK 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_ERR1_ERROR_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_ERR1_ERROR_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_ERR1_ERROR_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_ERR1_ERROR_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_ERR1_ALL_MASK 0x7fffffff
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_ERR1_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_ERR1_ALL_BITS 31
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_ERR1_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_ERR1_ALL_MASK 0x7fffffff
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_ERR1_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_ERR1_ALL_BITS 31
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_ERR1_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_ERR1_DATAMASK 0x7fffffff
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_ERR1_RDWRMASK 0x80000000
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_ERR1_RESETVALUE 0x00000000
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_ERR2 0x1023cd0c
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_ERR2_BASE 0xd0c
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_ERR2_NXT_RCMD_FIFO_WDATA1_MASK 0x7f800000
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_ERR2_NXT_RCMD_FIFO_WDATA1_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_ERR2_NXT_RCMD_FIFO_WDATA1_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_ERR2_NXT_RCMD_FIFO_WDATA1_SHIFT 23
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_ERR2_NXT_RCMD_FIFO_WDATA1_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_ERR2_NXT_RCMD_FIFO_WDATA0_MASK 0x7f8000
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_ERR2_NXT_RCMD_FIFO_WDATA0_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_ERR2_NXT_RCMD_FIFO_WDATA0_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_ERR2_NXT_RCMD_FIFO_WDATA0_SHIFT 15
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_ERR2_NXT_RCMD_FIFO_WDATA0_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_ERR2_NXT_RCMD_FIFO_WR1_MASK 0x4000
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_ERR2_NXT_RCMD_FIFO_WR1_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_ERR2_NXT_RCMD_FIFO_WR1_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_ERR2_NXT_RCMD_FIFO_WR1_SHIFT 14
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_ERR2_NXT_RCMD_FIFO_WR1_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_ERR2_NXT_RCMD_FIFO_WR0_MASK 0x2000
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_ERR2_NXT_RCMD_FIFO_WR0_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_ERR2_NXT_RCMD_FIFO_WR0_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_ERR2_NXT_RCMD_FIFO_WR0_SHIFT 13
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_ERR2_NXT_RCMD_FIFO_WR0_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_ERR2_NXT_RD_EN_UI23_MASK 0x1000
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_ERR2_NXT_RD_EN_UI23_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_ERR2_NXT_RD_EN_UI23_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_ERR2_NXT_RD_EN_UI23_SHIFT 12
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_ERR2_NXT_RD_EN_UI23_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_ERR2_NXT_RD_EN_UI01_MASK 0x800
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_ERR2_NXT_RD_EN_UI01_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_ERR2_NXT_RD_EN_UI01_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_ERR2_NXT_RD_EN_UI01_SHIFT 11
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_ERR2_NXT_RD_EN_UI01_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_ERR2_NXT_STATE_MASK 0x600
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_ERR2_NXT_STATE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_ERR2_NXT_STATE_BITS 2
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_ERR2_NXT_STATE_SHIFT 9
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_ERR2_NXT_STATE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_ERR2_RCMD_PAIR_MASK 0x1e0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_ERR2_RCMD_PAIR_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_ERR2_RCMD_PAIR_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_ERR2_RCMD_PAIR_SHIFT 5
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_ERR2_RCMD_PAIR_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_ERR2_RD_EN_UI23_MASK 0x10
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_ERR2_RD_EN_UI23_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_ERR2_RD_EN_UI23_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_ERR2_RD_EN_UI23_SHIFT 4
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_ERR2_RD_EN_UI23_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_ERR2_RD_EN_UI01_MASK 0x8
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_ERR2_RD_EN_UI01_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_ERR2_RD_EN_UI01_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_ERR2_RD_EN_UI01_SHIFT 3
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_ERR2_RD_EN_UI01_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_ERR2_STATE_MASK 0x6
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_ERR2_STATE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_ERR2_STATE_BITS 2
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_ERR2_STATE_SHIFT 1
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_ERR2_STATE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_ERR2_ERROR_MASK 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_ERR2_ERROR_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_ERR2_ERROR_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_ERR2_ERROR_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_ERR2_ERROR_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_ERR2_ALL_MASK 0x7fffffff
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_ERR2_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_ERR2_ALL_BITS 31
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_ERR2_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_ERR2_ALL_MASK 0x7fffffff
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_ERR2_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_ERR2_ALL_BITS 31
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_ERR2_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_ERR2_DATAMASK 0x7fffffff
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_ERR2_RDWRMASK 0x80000000
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_ERR2_RESETVALUE 0x00000000
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_FIFO_POINTERS 0x1023cd10
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_FIFO_POINTERS_BASE 0xd10
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_FIFO_POINTERS_RDATA_RP_MASK 0xf00000
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_FIFO_POINTERS_RDATA_RP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_FIFO_POINTERS_RDATA_RP_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_FIFO_POINTERS_RDATA_RP_SHIFT 20
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_FIFO_POINTERS_RDATA_RP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_FIFO_POINTERS_RDATA_WP_MASK 0xf0000
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_FIFO_POINTERS_RDATA_WP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_FIFO_POINTERS_RDATA_WP_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_FIFO_POINTERS_RDATA_WP_SHIFT 16
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_FIFO_POINTERS_RDATA_WP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_FIFO_POINTERS_EDC_VALID_RP_MASK 0xf000
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_FIFO_POINTERS_EDC_VALID_RP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_FIFO_POINTERS_EDC_VALID_RP_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_FIFO_POINTERS_EDC_VALID_RP_SHIFT 12
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_FIFO_POINTERS_EDC_VALID_RP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_FIFO_POINTERS_EDC_VALID_WP_MASK 0xf00
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_FIFO_POINTERS_EDC_VALID_WP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_FIFO_POINTERS_EDC_VALID_WP_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_FIFO_POINTERS_EDC_VALID_WP_SHIFT 8
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_FIFO_POINTERS_EDC_VALID_WP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_FIFO_POINTERS_DATA_VALID_RP_MASK 0xf0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_FIFO_POINTERS_DATA_VALID_RP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_FIFO_POINTERS_DATA_VALID_RP_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_FIFO_POINTERS_DATA_VALID_RP_SHIFT 4
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_FIFO_POINTERS_DATA_VALID_RP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_FIFO_POINTERS_DATA_VALID_WP_MASK 0xf
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_FIFO_POINTERS_DATA_VALID_WP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_FIFO_POINTERS_DATA_VALID_WP_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_FIFO_POINTERS_DATA_VALID_WP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_FIFO_POINTERS_DATA_VALID_WP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_FIFO_POINTERS_RESERVED_MASK 0xff000000
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_FIFO_POINTERS_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_FIFO_POINTERS_RESERVED_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_FIFO_POINTERS_RESERVED_SHIFT 24
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_FIFO_POINTERS_ALL_MASK 0xffffff
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_FIFO_POINTERS_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_FIFO_POINTERS_ALL_BITS 24
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_FIFO_POINTERS_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_FIFO_POINTERS_ALL_MASK 0xffffff
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_FIFO_POINTERS_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_FIFO_POINTERS_ALL_BITS 24
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_FIFO_POINTERS_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_FIFO_POINTERS_DATAMASK 0x00ffffff
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_FIFO_POINTERS_RDWRMASK 0xff000000
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_FIFO_POINTERS_RESETVALUE 0x000000
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB 0x1023cd14
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_BASE 0xd14
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_RCMD_4_MASK 0xff000000
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_RCMD_4_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_RCMD_4_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_RCMD_4_SHIFT 24
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_RCMD_4_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_RCMD_3_MASK 0xff0000
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_RCMD_3_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_RCMD_3_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_RCMD_3_SHIFT 16
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_RCMD_3_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_RCMD_2_MASK 0xff00
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_RCMD_2_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_RCMD_2_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_RCMD_2_SHIFT 8
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_RCMD_2_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_RCMD_1_MASK 0xff
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_RCMD_1_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_RCMD_1_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_RCMD_1_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_RCMD_1_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_ALL_MASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_ALL_BITS 32
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_ALL_MASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_ALL_BITS 32
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_DATAMASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_RDWRMASK 0x00000000
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_RESETVALUE 0x00000000
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB 0x1023cd18
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_BASE 0xd18
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_RCMD_8_MASK 0xff000000
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_RCMD_8_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_RCMD_8_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_RCMD_8_SHIFT 24
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_RCMD_8_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_RCMD_7_MASK 0xff0000
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_RCMD_7_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_RCMD_7_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_RCMD_7_SHIFT 16
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_RCMD_7_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_RCMD_6_MASK 0xff00
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_RCMD_6_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_RCMD_6_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_RCMD_6_SHIFT 8
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_RCMD_6_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_RCMD_5_MASK 0xff
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_RCMD_5_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_RCMD_5_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_RCMD_5_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_RCMD_5_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_ALL_MASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_ALL_BITS 32
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_ALL_MASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_ALL_BITS 32
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_DATAMASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_RDWRMASK 0x00000000
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_RESETVALUE 0x00000000
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES 0x1023cd1c
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_BASE 0xd1c
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_7_MASK 0xf0000000
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_7_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_7_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_7_SHIFT 28
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_7_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_6_MASK 0xf000000
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_6_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_6_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_6_SHIFT 24
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_6_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_5_MASK 0xf00000
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_5_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_5_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_5_SHIFT 20
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_5_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_4_MASK 0xf0000
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_4_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_4_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_4_SHIFT 16
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_4_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_3_MASK 0xf000
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_3_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_3_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_3_SHIFT 12
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_3_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_2_MASK 0xf00
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_2_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_2_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_2_SHIFT 8
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_2_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_1_MASK 0xf0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_1_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_1_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_1_SHIFT 4
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_1_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_0_MASK 0xf
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_0_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_0_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_0_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_0_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_ALL_MASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_ALL_BITS 32
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_ALL_MASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_ALL_BITS 32
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_DATAMASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_RDWRMASK 0x00000000
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_RESETVALUE 0x00000000
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS 0x1023cd20
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_BASE 0xd20
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_7_MASK 0xf0000000
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_7_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_7_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_7_SHIFT 28
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_7_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_6_MASK 0xf000000
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_6_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_6_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_6_SHIFT 24
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_6_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_5_MASK 0xf00000
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_5_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_5_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_5_SHIFT 20
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_5_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_4_MASK 0xf0000
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_4_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_4_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_4_SHIFT 16
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_4_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_3_MASK 0xf000
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_3_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_3_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_3_SHIFT 12
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_3_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_2_MASK 0xf00
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_2_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_2_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_2_SHIFT 8
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_2_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_1_MASK 0xf0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_1_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_1_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_1_SHIFT 4
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_1_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_0_MASK 0xf
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_0_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_0_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_0_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_0_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_ALL_MASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_ALL_BITS 32
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_ALL_MASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_ALL_BITS 32
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_DATAMASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_RDWRMASK 0x00000000
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_RESETVALUE 0x00000000
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR 0x1023cd24
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_BASE 0xd24
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STICKY_ERROR_MASK 0xf0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STICKY_ERROR_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STICKY_ERROR_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STICKY_ERROR_SHIFT 4
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STICKY_ERROR_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_CURRENT_ERROR_MASK 0xf
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_CURRENT_ERROR_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_CURRENT_ERROR_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_CURRENT_ERROR_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_CURRENT_ERROR_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RESERVED_MASK 0xffffff00
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RESERVED_BITS 24
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RESERVED_SHIFT 8
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_ALL_MASK 0xff
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_ALL_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_ALL_MASK 0xff
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_ALL_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_DATAMASK 0x000000ff
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RDWRMASK 0xffffff00
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB 0x1023cd28
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_BASE 0xd28
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_RCMD_4_MASK 0xff000000
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_RCMD_4_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_RCMD_4_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_RCMD_4_SHIFT 24
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_RCMD_4_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_RCMD_3_MASK 0xff0000
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_RCMD_3_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_RCMD_3_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_RCMD_3_SHIFT 16
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_RCMD_3_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_RCMD_2_MASK 0xff00
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_RCMD_2_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_RCMD_2_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_RCMD_2_SHIFT 8
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_RCMD_2_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_RCMD_1_MASK 0xff
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_RCMD_1_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_RCMD_1_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_RCMD_1_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_RCMD_1_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_ALL_MASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_ALL_BITS 32
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_ALL_MASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_ALL_BITS 32
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_DATAMASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_RDWRMASK 0x00000000
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_RESETVALUE 0x00000000
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB 0x1023cd2c
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_BASE 0xd2c
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_RCMD_8_MASK 0xff000000
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_RCMD_8_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_RCMD_8_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_RCMD_8_SHIFT 24
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_RCMD_8_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_RCMD_7_MASK 0xff0000
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_RCMD_7_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_RCMD_7_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_RCMD_7_SHIFT 16
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_RCMD_7_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_RCMD_6_MASK 0xff00
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_RCMD_6_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_RCMD_6_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_RCMD_6_SHIFT 8
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_RCMD_6_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_RCMD_5_MASK 0xff
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_RCMD_5_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_RCMD_5_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_RCMD_5_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_RCMD_5_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_ALL_MASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_ALL_BITS 32
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_ALL_MASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_ALL_BITS 32
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_DATAMASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_RDWRMASK 0x00000000
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_RESETVALUE 0x00000000
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES 0x1023cd30
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_BASE 0xd30
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_7_MASK 0xf0000000
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_7_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_7_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_7_SHIFT 28
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_7_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_6_MASK 0xf000000
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_6_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_6_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_6_SHIFT 24
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_6_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_5_MASK 0xf00000
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_5_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_5_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_5_SHIFT 20
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_5_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_4_MASK 0xf0000
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_4_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_4_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_4_SHIFT 16
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_4_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_3_MASK 0xf000
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_3_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_3_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_3_SHIFT 12
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_3_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_2_MASK 0xf00
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_2_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_2_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_2_SHIFT 8
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_2_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_1_MASK 0xf0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_1_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_1_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_1_SHIFT 4
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_1_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_0_MASK 0xf
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_0_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_0_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_0_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_0_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_ALL_MASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_ALL_BITS 32
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_ALL_MASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_ALL_BITS 32
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_DATAMASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_RDWRMASK 0x00000000
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_RESETVALUE 0x00000000
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS 0x1023cd34
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_BASE 0xd34
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_7_MASK 0xf0000000
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_7_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_7_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_7_SHIFT 28
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_7_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_6_MASK 0xf000000
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_6_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_6_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_6_SHIFT 24
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_6_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_5_MASK 0xf00000
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_5_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_5_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_5_SHIFT 20
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_5_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_4_MASK 0xf0000
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_4_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_4_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_4_SHIFT 16
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_4_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_3_MASK 0xf000
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_3_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_3_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_3_SHIFT 12
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_3_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_2_MASK 0xf00
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_2_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_2_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_2_SHIFT 8
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_2_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_1_MASK 0xf0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_1_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_1_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_1_SHIFT 4
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_1_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_0_MASK 0xf
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_0_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_0_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_0_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_0_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_ALL_MASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_ALL_BITS 32
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_ALL_MASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_ALL_BITS 32
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_DATAMASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_RDWRMASK 0x00000000
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_RESETVALUE 0x00000000
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_WRITE_LEVELING 0x1023cd38
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_WRITE_LEVELING_BASE 0xd38
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_WRITE_LEVELING_DQS_MASK 0x400
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_WRITE_LEVELING_DQS_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_WRITE_LEVELING_DQS_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_WRITE_LEVELING_DQS_SHIFT 10
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_WRITE_LEVELING_DQS_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_WRITE_LEVELING_EDC_MASK 0x200
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_WRITE_LEVELING_EDC_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_WRITE_LEVELING_EDC_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_WRITE_LEVELING_EDC_SHIFT 9
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_WRITE_LEVELING_EDC_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_WRITE_LEVELING_DBI_MASK 0x100
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_WRITE_LEVELING_DBI_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_WRITE_LEVELING_DBI_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_WRITE_LEVELING_DBI_SHIFT 8
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_WRITE_LEVELING_DBI_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_WRITE_LEVELING_DATA_MASK 0xff
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_WRITE_LEVELING_DATA_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_WRITE_LEVELING_DATA_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_WRITE_LEVELING_DATA_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_WRITE_LEVELING_DATA_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_WRITE_LEVELING_RESERVED_MASK 0xfffff800
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_WRITE_LEVELING_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_WRITE_LEVELING_RESERVED_BITS 21
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_WRITE_LEVELING_RESERVED_SHIFT 11
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_WRITE_LEVELING_ALL_MASK 0x7ff
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_WRITE_LEVELING_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_WRITE_LEVELING_ALL_BITS 11
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_WRITE_LEVELING_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_WRITE_LEVELING_ALL_MASK 0x7ff
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_WRITE_LEVELING_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_WRITE_LEVELING_ALL_BITS 11
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_WRITE_LEVELING_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_WRITE_LEVELING_DATAMASK 0x000007ff
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_WRITE_LEVELING_RDWRMASK 0xfffff800
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_WRITE_LEVELING_RESETVALUE 0x000
 #define SJC16_DDR4_PHY_DQ_BYTE3_MACRO_RESERVED_REG 0x1023cd3c
 #define SJC16_DDR4_PHY_DQ_BYTE3_MACRO_RESERVED_REG_BASE 0xd3c
 #define SJC16_DDR4_PHY_DQ_BYTE3_MACRO_RESERVED_REG_RESERVED_MASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE3_MACRO_RESERVED_REG_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_MACRO_RESERVED_REG_RESERVED_BITS 32
 #define SJC16_DDR4_PHY_DQ_BYTE3_MACRO_RESERVED_REG_RESERVED_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_MACRO_RESERVED_REG_RESERVED_RESETVALUE 0x00000000
 #define SJC16_DDR4_PHY_DQ_BYTE3_MACRO_RESERVED_REG_ALL_MASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE3_MACRO_RESERVED_REG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_MACRO_RESERVED_REG_ALL_BITS 32
 #define SJC16_DDR4_PHY_DQ_BYTE3_MACRO_RESERVED_REG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_MACRO_RESERVED_REG_ALL_MASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE3_MACRO_RESERVED_REG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_MACRO_RESERVED_REG_ALL_BITS 32
 #define SJC16_DDR4_PHY_DQ_BYTE3_MACRO_RESERVED_REG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_MACRO_RESERVED_REG_DATAMASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE3_MACRO_RESERVED_REG_RDWRMASK 0x00000000
 #define SJC16_DDR4_PHY_DQ_BYTE3_MACRO_RESERVED_REG_RESETVALUE 0x00000000
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_MACRO_RESERVED 0x1023cd40
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_MACRO_RESERVED_BASE 0xd40
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_MACRO_RESERVED_RESERVED_MASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_MACRO_RESERVED_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_MACRO_RESERVED_RESERVED_BITS 32
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_MACRO_RESERVED_RESERVED_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_MACRO_RESERVED_RESERVED_RESETVALUE 0x00000000
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_MACRO_RESERVED_ALL_MASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_MACRO_RESERVED_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_MACRO_RESERVED_ALL_BITS 32
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_MACRO_RESERVED_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_MACRO_RESERVED_ALL_MASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_MACRO_RESERVED_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_MACRO_RESERVED_ALL_BITS 32
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_MACRO_RESERVED_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_MACRO_RESERVED_DATAMASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_MACRO_RESERVED_RDWRMASK 0x00000000
 #define SJC16_DDR4_PHY_DQ_BYTE3_STATUS_MACRO_RESERVED_RESETVALUE 0x00000000
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT0 0x1023d000
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT0_BASE 0x000
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT0_MIN_VDL_STEP_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT0_MIN_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT0_MIN_VDL_STEP_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT0_MIN_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT0_MIN_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT0_RESERVED_MASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT0_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT0_RESERVED_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT0_RESERVED_SHIFT 7
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT0_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT0_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT0_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT0_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT0_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT0_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT0_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT0_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT0_DATAMASK 0x0000007f
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT0_RDWRMASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT0_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT1 0x1023d004
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT1_BASE 0x004
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT1_MIN_VDL_STEP_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT1_MIN_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT1_MIN_VDL_STEP_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT1_MIN_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT1_MIN_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT1_RESERVED_MASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT1_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT1_RESERVED_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT1_RESERVED_SHIFT 7
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT1_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT1_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT1_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT1_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT1_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT1_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT1_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT1_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT1_DATAMASK 0x0000007f
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT1_RDWRMASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT1_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT2 0x1023d008
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT2_BASE 0x008
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT2_MIN_VDL_STEP_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT2_MIN_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT2_MIN_VDL_STEP_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT2_MIN_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT2_MIN_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT2_RESERVED_MASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT2_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT2_RESERVED_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT2_RESERVED_SHIFT 7
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT2_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT2_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT2_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT2_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT2_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT2_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT2_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT2_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT2_DATAMASK 0x0000007f
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT2_RDWRMASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT2_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT3 0x1023d00c
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT3_BASE 0x00c
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT3_MIN_VDL_STEP_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT3_MIN_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT3_MIN_VDL_STEP_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT3_MIN_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT3_MIN_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT3_RESERVED_MASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT3_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT3_RESERVED_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT3_RESERVED_SHIFT 7
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT3_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT3_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT3_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT3_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT3_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT3_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT3_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT3_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT3_DATAMASK 0x0000007f
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT3_RDWRMASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT3_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT4 0x1023d010
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT4_BASE 0x010
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT4_MIN_VDL_STEP_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT4_MIN_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT4_MIN_VDL_STEP_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT4_MIN_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT4_MIN_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT4_RESERVED_MASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT4_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT4_RESERVED_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT4_RESERVED_SHIFT 7
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT4_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT4_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT4_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT4_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT4_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT4_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT4_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT4_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT4_DATAMASK 0x0000007f
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT4_RDWRMASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT4_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT5 0x1023d014
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT5_BASE 0x014
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT5_MIN_VDL_STEP_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT5_MIN_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT5_MIN_VDL_STEP_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT5_MIN_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT5_MIN_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT5_RESERVED_MASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT5_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT5_RESERVED_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT5_RESERVED_SHIFT 7
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT5_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT5_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT5_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT5_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT5_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT5_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT5_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT5_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT5_DATAMASK 0x0000007f
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT5_RDWRMASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT5_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT6 0x1023d018
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT6_BASE 0x018
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT6_MIN_VDL_STEP_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT6_MIN_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT6_MIN_VDL_STEP_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT6_MIN_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT6_MIN_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT6_RESERVED_MASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT6_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT6_RESERVED_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT6_RESERVED_SHIFT 7
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT6_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT6_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT6_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT6_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT6_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT6_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT6_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT6_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT6_DATAMASK 0x0000007f
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT6_RDWRMASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT6_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT7 0x1023d01c
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT7_BASE 0x01c
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT7_MIN_VDL_STEP_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT7_MIN_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT7_MIN_VDL_STEP_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT7_MIN_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT7_MIN_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT7_RESERVED_MASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT7_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT7_RESERVED_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT7_RESERVED_SHIFT 7
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT7_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT7_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT7_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT7_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT7_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT7_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT7_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT7_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT7_DATAMASK 0x0000007f
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT7_RDWRMASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT7_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_DBI 0x1023d020
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_DBI_BASE 0x020
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_DBI_MIN_VDL_STEP_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_DBI_MIN_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_DBI_MIN_VDL_STEP_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_DBI_MIN_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_DBI_MIN_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_DBI_RESERVED_MASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_DBI_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_DBI_RESERVED_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_DBI_RESERVED_SHIFT 7
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_DBI_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_DBI_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_DBI_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_DBI_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_DBI_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_DBI_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_DBI_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_DBI_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_DBI_DATAMASK 0x0000007f
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_DBI_RDWRMASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_DBI_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_EDC 0x1023d024
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_EDC_BASE 0x024
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_EDC_MIN_VDL_STEP_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_EDC_MIN_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_EDC_MIN_VDL_STEP_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_EDC_MIN_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_EDC_MIN_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_EDC_RESERVED_MASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_EDC_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_EDC_RESERVED_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_EDC_RESERVED_SHIFT 7
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_EDC_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_EDC_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_EDC_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_EDC_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_EDC_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_EDC_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_EDC_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_EDC_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_EDC_DATAMASK 0x0000007f
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_EDC_RDWRMASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_EDC_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MAX_VDL_DATA 0x1023d028
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MAX_VDL_DATA_BASE 0x028
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MAX_VDL_DATA_UI_SHIFT_MASK 0xe00
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MAX_VDL_DATA_UI_SHIFT_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MAX_VDL_DATA_UI_SHIFT_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MAX_VDL_DATA_UI_SHIFT_SHIFT 9
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MAX_VDL_DATA_UI_SHIFT_RESETVALUE 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MAX_VDL_DATA_MAX_VDL_STEP_MASK 0x1ff
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MAX_VDL_DATA_MAX_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MAX_VDL_DATA_MAX_VDL_STEP_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MAX_VDL_DATA_MAX_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MAX_VDL_DATA_MAX_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MAX_VDL_DATA_RESERVED_MASK 0xfffff000
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MAX_VDL_DATA_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MAX_VDL_DATA_RESERVED_BITS 20
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MAX_VDL_DATA_RESERVED_SHIFT 12
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MAX_VDL_DATA_ALL_MASK 0xfff
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MAX_VDL_DATA_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MAX_VDL_DATA_ALL_BITS 12
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MAX_VDL_DATA_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MAX_VDL_DATA_ALL_MASK 0xfff
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MAX_VDL_DATA_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MAX_VDL_DATA_ALL_BITS 12
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MAX_VDL_DATA_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MAX_VDL_DATA_DATAMASK 0x00000fff
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MAX_VDL_DATA_RDWRMASK 0xfffff000
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MAX_VDL_DATA_RESETVALUE 0x200
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MAX_VDL_DATA_SHADOW 0x1023d02c
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MAX_VDL_DATA_SHADOW_BASE 0x02c
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MAX_VDL_DATA_SHADOW_UI_SHIFT_MASK 0xe00
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MAX_VDL_DATA_SHADOW_UI_SHIFT_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MAX_VDL_DATA_SHADOW_UI_SHIFT_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MAX_VDL_DATA_SHADOW_UI_SHIFT_SHIFT 9
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MAX_VDL_DATA_SHADOW_UI_SHIFT_RESETVALUE 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MAX_VDL_DATA_SHADOW_MAX_VDL_STEP_MASK 0x1ff
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MAX_VDL_DATA_SHADOW_MAX_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MAX_VDL_DATA_SHADOW_MAX_VDL_STEP_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MAX_VDL_DATA_SHADOW_MAX_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MAX_VDL_DATA_SHADOW_MAX_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MAX_VDL_DATA_SHADOW_RESERVED_MASK 0xfffff000
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MAX_VDL_DATA_SHADOW_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MAX_VDL_DATA_SHADOW_RESERVED_BITS 20
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MAX_VDL_DATA_SHADOW_RESERVED_SHIFT 12
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MAX_VDL_DATA_SHADOW_ALL_MASK 0xfff
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MAX_VDL_DATA_SHADOW_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MAX_VDL_DATA_SHADOW_ALL_BITS 12
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MAX_VDL_DATA_SHADOW_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MAX_VDL_DATA_SHADOW_ALL_MASK 0xfff
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MAX_VDL_DATA_SHADOW_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MAX_VDL_DATA_SHADOW_ALL_BITS 12
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MAX_VDL_DATA_SHADOW_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MAX_VDL_DATA_SHADOW_DATAMASK 0x00000fff
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MAX_VDL_DATA_SHADOW_RDWRMASK 0xfffff000
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MAX_VDL_DATA_SHADOW_RESETVALUE 0x200
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MAX_VDL_DQS 0x1023d030
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MAX_VDL_DQS_BASE 0x030
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MAX_VDL_DQS_UI_SHIFT_MASK 0xe00
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MAX_VDL_DQS_UI_SHIFT_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MAX_VDL_DQS_UI_SHIFT_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MAX_VDL_DQS_UI_SHIFT_SHIFT 9
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MAX_VDL_DQS_UI_SHIFT_RESETVALUE 0x2
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MAX_VDL_DQS_MAX_VDL_STEP_MASK 0x1ff
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MAX_VDL_DQS_MAX_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MAX_VDL_DQS_MAX_VDL_STEP_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MAX_VDL_DQS_MAX_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MAX_VDL_DQS_MAX_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MAX_VDL_DQS_RESERVED_MASK 0xfffff000
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MAX_VDL_DQS_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MAX_VDL_DQS_RESERVED_BITS 20
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MAX_VDL_DQS_RESERVED_SHIFT 12
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MAX_VDL_DQS_ALL_MASK 0xfff
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MAX_VDL_DQS_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MAX_VDL_DQS_ALL_BITS 12
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MAX_VDL_DQS_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MAX_VDL_DQS_ALL_MASK 0xfff
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MAX_VDL_DQS_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MAX_VDL_DQS_ALL_BITS 12
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MAX_VDL_DQS_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MAX_VDL_DQS_DATAMASK 0x00000fff
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MAX_VDL_DQS_RDWRMASK 0xfffff000
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_MAX_VDL_DQS_RESETVALUE 0x400
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT0 0x1023d034
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT0_BASE 0x034
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT0_MIN_VDL_STEP_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT0_MIN_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT0_MIN_VDL_STEP_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT0_MIN_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT0_MIN_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT0_RESERVED_MASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT0_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT0_RESERVED_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT0_RESERVED_SHIFT 7
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT0_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT0_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT0_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT0_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT0_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT0_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT0_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT0_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT0_DATAMASK 0x0000007f
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT0_RDWRMASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT0_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT1 0x1023d038
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT1_BASE 0x038
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT1_MIN_VDL_STEP_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT1_MIN_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT1_MIN_VDL_STEP_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT1_MIN_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT1_MIN_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT1_RESERVED_MASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT1_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT1_RESERVED_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT1_RESERVED_SHIFT 7
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT1_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT1_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT1_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT1_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT1_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT1_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT1_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT1_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT1_DATAMASK 0x0000007f
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT1_RDWRMASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT1_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT2 0x1023d03c
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT2_BASE 0x03c
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT2_MIN_VDL_STEP_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT2_MIN_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT2_MIN_VDL_STEP_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT2_MIN_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT2_MIN_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT2_RESERVED_MASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT2_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT2_RESERVED_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT2_RESERVED_SHIFT 7
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT2_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT2_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT2_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT2_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT2_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT2_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT2_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT2_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT2_DATAMASK 0x0000007f
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT2_RDWRMASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT2_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT3 0x1023d040
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT3_BASE 0x040
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT3_MIN_VDL_STEP_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT3_MIN_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT3_MIN_VDL_STEP_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT3_MIN_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT3_MIN_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT3_RESERVED_MASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT3_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT3_RESERVED_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT3_RESERVED_SHIFT 7
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT3_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT3_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT3_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT3_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT3_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT3_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT3_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT3_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT3_DATAMASK 0x0000007f
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT3_RDWRMASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT3_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT4 0x1023d044
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT4_BASE 0x044
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT4_MIN_VDL_STEP_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT4_MIN_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT4_MIN_VDL_STEP_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT4_MIN_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT4_MIN_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT4_RESERVED_MASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT4_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT4_RESERVED_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT4_RESERVED_SHIFT 7
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT4_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT4_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT4_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT4_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT4_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT4_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT4_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT4_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT4_DATAMASK 0x0000007f
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT4_RDWRMASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT4_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT5 0x1023d048
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT5_BASE 0x048
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT5_MIN_VDL_STEP_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT5_MIN_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT5_MIN_VDL_STEP_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT5_MIN_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT5_MIN_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT5_RESERVED_MASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT5_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT5_RESERVED_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT5_RESERVED_SHIFT 7
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT5_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT5_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT5_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT5_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT5_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT5_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT5_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT5_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT5_DATAMASK 0x0000007f
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT5_RDWRMASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT5_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT6 0x1023d04c
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT6_BASE 0x04c
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT6_MIN_VDL_STEP_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT6_MIN_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT6_MIN_VDL_STEP_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT6_MIN_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT6_MIN_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT6_RESERVED_MASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT6_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT6_RESERVED_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT6_RESERVED_SHIFT 7
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT6_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT6_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT6_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT6_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT6_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT6_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT6_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT6_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT6_DATAMASK 0x0000007f
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT6_RDWRMASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT6_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT7 0x1023d050
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT7_BASE 0x050
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT7_MIN_VDL_STEP_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT7_MIN_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT7_MIN_VDL_STEP_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT7_MIN_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT7_MIN_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT7_RESERVED_MASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT7_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT7_RESERVED_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT7_RESERVED_SHIFT 7
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT7_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT7_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT7_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT7_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT7_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT7_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT7_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT7_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT7_DATAMASK 0x0000007f
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT7_RDWRMASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT7_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_DBI 0x1023d054
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_DBI_BASE 0x054
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_DBI_MIN_VDL_STEP_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_DBI_MIN_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_DBI_MIN_VDL_STEP_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_DBI_MIN_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_DBI_MIN_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_DBI_RESERVED_MASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_DBI_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_DBI_RESERVED_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_DBI_RESERVED_SHIFT 7
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_DBI_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_DBI_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_DBI_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_DBI_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_DBI_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_DBI_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_DBI_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_DBI_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_DBI_DATAMASK 0x0000007f
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_DBI_RDWRMASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_DBI_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_EDC 0x1023d058
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_EDC_BASE 0x058
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_EDC_MIN_VDL_STEP_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_EDC_MIN_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_EDC_MIN_VDL_STEP_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_EDC_MIN_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_EDC_MIN_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_EDC_RESERVED_MASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_EDC_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_EDC_RESERVED_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_EDC_RESERVED_SHIFT 7
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_EDC_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_EDC_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_EDC_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_EDC_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_EDC_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_EDC_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_EDC_ALL_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_EDC_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_EDC_DATAMASK 0x0000007f
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_EDC_RDWRMASK 0xffffff80
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_EDC_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQS_MASTER_CTRL 0x1023d05c
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQS_MASTER_CTRL_BASE 0x05c
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQS_MASTER_CTRL_MASTER_MODE_MASK 0x10000
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQS_MASTER_CTRL_MASTER_MODE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQS_MASTER_CTRL_MASTER_MODE_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQS_MASTER_CTRL_MASTER_MODE_SHIFT 16
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQS_MASTER_CTRL_MASTER_MODE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQS_MASTER_CTRL_FORCE_UPDATE_MASK 0x1000
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQS_MASTER_CTRL_FORCE_UPDATE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQS_MASTER_CTRL_FORCE_UPDATE_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQS_MASTER_CTRL_FORCE_UPDATE_SHIFT 12
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQS_MASTER_CTRL_FORCE_UPDATE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQS_MASTER_CTRL_MAX_VDL_STEP_MASK 0x1ff
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQS_MASTER_CTRL_MAX_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQS_MASTER_CTRL_MAX_VDL_STEP_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQS_MASTER_CTRL_MAX_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQS_MASTER_CTRL_MAX_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQS_MASTER_CTRL_RESERVED_0_MASK 0xfffe0000
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQS_MASTER_CTRL_RESERVED_0_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQS_MASTER_CTRL_RESERVED_0_BITS 15
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQS_MASTER_CTRL_RESERVED_0_SHIFT 17
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQS_MASTER_CTRL_RESERVED_1_MASK 0xe000
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQS_MASTER_CTRL_RESERVED_1_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQS_MASTER_CTRL_RESERVED_1_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQS_MASTER_CTRL_RESERVED_1_SHIFT 13
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQS_MASTER_CTRL_RESERVED_2_MASK 0xe00
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQS_MASTER_CTRL_RESERVED_2_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQS_MASTER_CTRL_RESERVED_2_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQS_MASTER_CTRL_RESERVED_2_SHIFT 9
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQS_MASTER_CTRL_RESERVED_MASK 0xfffe0000
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQS_MASTER_CTRL_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQS_MASTER_CTRL_RESERVED_BITS 15
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQS_MASTER_CTRL_RESERVED_SHIFT 17
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQS_MASTER_CTRL_ALL_MASK 0x1ffff
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQS_MASTER_CTRL_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQS_MASTER_CTRL_ALL_BITS 17
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQS_MASTER_CTRL_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQS_MASTER_CTRL_ALL_MASK 0x1ffff
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQS_MASTER_CTRL_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQS_MASTER_CTRL_ALL_BITS 17
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQS_MASTER_CTRL_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQS_MASTER_CTRL_DATAMASK 0x000111ff
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQS_MASTER_CTRL_RDWRMASK 0xfffeee00
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQS_MASTER_CTRL_RESETVALUE 0x00000
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQSEP 0x1023d060
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQSEP_BASE 0x060
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQSEP_MAX_VDL_STEP_MASK 0x1ff
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQSEP_MAX_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQSEP_MAX_VDL_STEP_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQSEP_MAX_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQSEP_MAX_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQSEP_RESERVED_MASK 0xfffffe00
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQSEP_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQSEP_RESERVED_BITS 23
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQSEP_RESERVED_SHIFT 9
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQSEP_ALL_MASK 0x1ff
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQSEP_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQSEP_ALL_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQSEP_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQSEP_ALL_MASK 0x1ff
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQSEP_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQSEP_ALL_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQSEP_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQSEP_DATAMASK 0x000001ff
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQSEP_RDWRMASK 0xfffffe00
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQSEP_RESETVALUE 0x000
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQSDP 0x1023d064
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQSDP_BASE 0x064
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQSDP_MAX_VDL_STEP_MASK 0x1ff
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQSDP_MAX_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQSDP_MAX_VDL_STEP_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQSDP_MAX_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQSDP_MAX_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQSDP_RESERVED_MASK 0xfffffe00
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQSDP_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQSDP_RESERVED_BITS 23
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQSDP_RESERVED_SHIFT 9
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQSDP_ALL_MASK 0x1ff
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQSDP_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQSDP_ALL_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQSDP_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQSDP_ALL_MASK 0x1ff
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQSDP_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQSDP_ALL_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQSDP_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQSDP_DATAMASK 0x000001ff
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQSDP_RDWRMASK 0xfffffe00
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQSDP_RESETVALUE 0x000
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQSEN 0x1023d068
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQSEN_BASE 0x068
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQSEN_MAX_VDL_STEP_MASK 0x1ff
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQSEN_MAX_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQSEN_MAX_VDL_STEP_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQSEN_MAX_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQSEN_MAX_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQSEN_RESERVED_MASK 0xfffffe00
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQSEN_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQSEN_RESERVED_BITS 23
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQSEN_RESERVED_SHIFT 9
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQSEN_ALL_MASK 0x1ff
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQSEN_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQSEN_ALL_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQSEN_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQSEN_ALL_MASK 0x1ff
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQSEN_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQSEN_ALL_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQSEN_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQSEN_DATAMASK 0x000001ff
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQSEN_RDWRMASK 0xfffffe00
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQSEN_RESETVALUE 0x000
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQSDN 0x1023d06c
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQSDN_BASE 0x06c
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQSDN_MAX_VDL_STEP_MASK 0x1ff
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQSDN_MAX_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQSDN_MAX_VDL_STEP_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQSDN_MAX_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQSDN_MAX_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQSDN_RESERVED_MASK 0xfffffe00
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQSDN_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQSDN_RESERVED_BITS 23
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQSDN_RESERVED_SHIFT 9
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQSDN_ALL_MASK 0x1ff
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQSDN_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQSDN_ALL_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQSDN_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQSDN_ALL_MASK 0x1ff
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQSDN_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQSDN_ALL_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQSDN_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQSDN_DATAMASK 0x000001ff
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQSDN_RDWRMASK 0xfffffe00
 #define SJC16_DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQSDN_RESETVALUE 0x000
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_LEVELING_CONFIG 0x1023d070
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_LEVELING_CONFIG_BASE 0x070
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_LEVELING_CONFIG_WRITE_LEVELING_MODE_MASK 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_LEVELING_CONFIG_WRITE_LEVELING_MODE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_LEVELING_CONFIG_WRITE_LEVELING_MODE_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_LEVELING_CONFIG_WRITE_LEVELING_MODE_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_LEVELING_CONFIG_WRITE_LEVELING_MODE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_LEVELING_CONFIG_RESERVED_MASK 0xfffffffe
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_LEVELING_CONFIG_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_LEVELING_CONFIG_RESERVED_BITS 31
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_LEVELING_CONFIG_RESERVED_SHIFT 1
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_LEVELING_CONFIG_WRITE_LEVELING_MODE_MASK 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_LEVELING_CONFIG_WRITE_LEVELING_MODE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_LEVELING_CONFIG_WRITE_LEVELING_MODE_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_LEVELING_CONFIG_WRITE_LEVELING_MODE_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_LEVELING_CONFIG_WRITE_LEVELING_MODE_MASK 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_LEVELING_CONFIG_WRITE_LEVELING_MODE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_LEVELING_CONFIG_WRITE_LEVELING_MODE_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_LEVELING_CONFIG_WRITE_LEVELING_MODE_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_LEVELING_CONFIG_ALL_MASK 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_LEVELING_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_LEVELING_CONFIG_ALL_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_LEVELING_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_LEVELING_CONFIG_ALL_MASK 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_LEVELING_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_LEVELING_CONFIG_ALL_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_LEVELING_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_LEVELING_CONFIG_DATAMASK 0x00000001
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_LEVELING_CONFIG_RDWRMASK 0xfffffffe
 #define SJC16_DDR4_PHY_DQ_BYTE4_WRITE_LEVELING_CONFIG_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_REN_GEN_ERR_CTRL 0x1023d074
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_REN_GEN_ERR_CTRL_BASE 0x074
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_REN_GEN_ERR_CTRL_ERR2_CLEAR_MASK 0x2
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_REN_GEN_ERR_CTRL_ERR2_CLEAR_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_REN_GEN_ERR_CTRL_ERR2_CLEAR_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_REN_GEN_ERR_CTRL_ERR2_CLEAR_SHIFT 1
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_REN_GEN_ERR_CTRL_ERR2_CLEAR_RESETVALUE 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_REN_GEN_ERR_CTRL_ERR1_CLEAR_MASK 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_REN_GEN_ERR_CTRL_ERR1_CLEAR_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_REN_GEN_ERR_CTRL_ERR1_CLEAR_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_REN_GEN_ERR_CTRL_ERR1_CLEAR_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_REN_GEN_ERR_CTRL_ERR1_CLEAR_RESETVALUE 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_REN_GEN_ERR_CTRL_RESERVED_MASK 0xfffffffc
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_REN_GEN_ERR_CTRL_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_REN_GEN_ERR_CTRL_RESERVED_BITS 30
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_REN_GEN_ERR_CTRL_RESERVED_SHIFT 2
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_REN_GEN_ERR_CTRL_ALL_MASK 0x3
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_REN_GEN_ERR_CTRL_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_REN_GEN_ERR_CTRL_ALL_BITS 2
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_REN_GEN_ERR_CTRL_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_REN_GEN_ERR_CTRL_ALL_MASK 0x3
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_REN_GEN_ERR_CTRL_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_REN_GEN_ERR_CTRL_ALL_BITS 2
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_REN_GEN_ERR_CTRL_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_REN_GEN_ERR_CTRL_DATAMASK 0x00000003
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_REN_GEN_ERR_CTRL_RDWRMASK 0xfffffffc
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_REN_GEN_ERR_CTRL_RESETVALUE 0x3
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_REN_FIFO_CONFIG 0x1023d078
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_REN_FIFO_CONFIG_BASE 0x078
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_REN_FIFO_CONFIG_RD_2G_DELAY_DEC_MASK 0x800
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_REN_FIFO_CONFIG_RD_2G_DELAY_DEC_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_REN_FIFO_CONFIG_RD_2G_DELAY_DEC_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_REN_FIFO_CONFIG_RD_2G_DELAY_DEC_SHIFT 11
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_REN_FIFO_CONFIG_RD_2G_DELAY_DEC_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_REN_FIFO_CONFIG_RD_2G_DELAY_INC_MASK 0x400
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_REN_FIFO_CONFIG_RD_2G_DELAY_INC_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_REN_FIFO_CONFIG_RD_2G_DELAY_INC_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_REN_FIFO_CONFIG_RD_2G_DELAY_INC_SHIFT 10
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_REN_FIFO_CONFIG_RD_2G_DELAY_INC_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_REN_FIFO_CONFIG_RD2_2G_DELAY_MASK 0x3e0
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_REN_FIFO_CONFIG_RD2_2G_DELAY_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_REN_FIFO_CONFIG_RD2_2G_DELAY_BITS 5
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_REN_FIFO_CONFIG_RD2_2G_DELAY_SHIFT 5
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_REN_FIFO_CONFIG_RD2_2G_DELAY_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_REN_FIFO_CONFIG_RD_2G_DELAY_MASK 0x1f
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_REN_FIFO_CONFIG_RD_2G_DELAY_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_REN_FIFO_CONFIG_RD_2G_DELAY_BITS 5
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_REN_FIFO_CONFIG_RD_2G_DELAY_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_REN_FIFO_CONFIG_RD_2G_DELAY_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_REN_FIFO_CONFIG_RESERVED_MASK 0xfffff000
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_REN_FIFO_CONFIG_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_REN_FIFO_CONFIG_RESERVED_BITS 20
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_REN_FIFO_CONFIG_RESERVED_SHIFT 12
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_REN_FIFO_CONFIG_ALL_MASK 0xfff
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_REN_FIFO_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_REN_FIFO_CONFIG_ALL_BITS 12
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_REN_FIFO_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_REN_FIFO_CONFIG_ALL_MASK 0xfff
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_REN_FIFO_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_REN_FIFO_CONFIG_ALL_BITS 12
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_REN_FIFO_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_REN_FIFO_CONFIG_DATAMASK 0x00000fff
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_REN_FIFO_CONFIG_RDWRMASK 0xfffff000
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_REN_FIFO_CONFIG_RESETVALUE 0x000
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_REN_STRETCH_CONFIG 0x1023d07c
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_REN_STRETCH_CONFIG_BASE 0x07c
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_REN_STRETCH_CONFIG_A_PLUS_2_MASK 0x20
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_REN_STRETCH_CONFIG_A_PLUS_2_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_REN_STRETCH_CONFIG_A_PLUS_2_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_REN_STRETCH_CONFIG_A_PLUS_2_SHIFT 5
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_REN_STRETCH_CONFIG_A_PLUS_2_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_REN_STRETCH_CONFIG_A_PLUS_1_MASK 0x10
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_REN_STRETCH_CONFIG_A_PLUS_1_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_REN_STRETCH_CONFIG_A_PLUS_1_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_REN_STRETCH_CONFIG_A_PLUS_1_SHIFT 4
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_REN_STRETCH_CONFIG_A_PLUS_1_RESETVALUE 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_REN_STRETCH_CONFIG_A_0_MASK 0x8
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_REN_STRETCH_CONFIG_A_0_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_REN_STRETCH_CONFIG_A_0_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_REN_STRETCH_CONFIG_A_0_SHIFT 3
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_REN_STRETCH_CONFIG_A_0_RESETVALUE 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_REN_STRETCH_CONFIG_A_MINUS_1_MASK 0x4
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_REN_STRETCH_CONFIG_A_MINUS_1_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_REN_STRETCH_CONFIG_A_MINUS_1_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_REN_STRETCH_CONFIG_A_MINUS_1_SHIFT 2
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_REN_STRETCH_CONFIG_A_MINUS_1_RESETVALUE 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_REN_STRETCH_CONFIG_A_MINUS_2_MASK 0x2
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_REN_STRETCH_CONFIG_A_MINUS_2_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_REN_STRETCH_CONFIG_A_MINUS_2_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_REN_STRETCH_CONFIG_A_MINUS_2_SHIFT 1
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_REN_STRETCH_CONFIG_A_MINUS_2_RESETVALUE 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_REN_STRETCH_CONFIG_A_MINUS_3_MASK 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_REN_STRETCH_CONFIG_A_MINUS_3_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_REN_STRETCH_CONFIG_A_MINUS_3_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_REN_STRETCH_CONFIG_A_MINUS_3_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_REN_STRETCH_CONFIG_A_MINUS_3_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_REN_STRETCH_CONFIG_RESERVED_MASK 0xffffffc0
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_REN_STRETCH_CONFIG_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_REN_STRETCH_CONFIG_RESERVED_BITS 26
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_REN_STRETCH_CONFIG_RESERVED_SHIFT 6
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_REN_STRETCH_CONFIG_ALL_MASK 0x3f
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_REN_STRETCH_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_REN_STRETCH_CONFIG_ALL_BITS 6
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_REN_STRETCH_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_REN_STRETCH_CONFIG_ALL_MASK 0x3f
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_REN_STRETCH_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_REN_STRETCH_CONFIG_ALL_BITS 6
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_REN_STRETCH_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_REN_STRETCH_CONFIG_DATAMASK 0x0000003f
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_REN_STRETCH_CONFIG_RDWRMASK 0xffffffc0
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_REN_STRETCH_CONFIG_RESETVALUE 0x1e
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_READ_MAX_VDL_FSM 0x1023d080
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_READ_MAX_VDL_FSM_BASE 0x080
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_READ_MAX_VDL_FSM_MAX_VDL_STEP_MASK 0x1ff
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_READ_MAX_VDL_FSM_MAX_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_READ_MAX_VDL_FSM_MAX_VDL_STEP_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_READ_MAX_VDL_FSM_MAX_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_READ_MAX_VDL_FSM_MAX_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_READ_MAX_VDL_FSM_RESERVED_MASK 0xfffffe00
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_READ_MAX_VDL_FSM_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_READ_MAX_VDL_FSM_RESERVED_BITS 23
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_READ_MAX_VDL_FSM_RESERVED_SHIFT 9
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_READ_MAX_VDL_FSM_ALL_MASK 0x1ff
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_READ_MAX_VDL_FSM_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_READ_MAX_VDL_FSM_ALL_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_READ_MAX_VDL_FSM_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_READ_MAX_VDL_FSM_ALL_MASK 0x1ff
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_READ_MAX_VDL_FSM_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_READ_MAX_VDL_FSM_ALL_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_READ_MAX_VDL_FSM_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_READ_MAX_VDL_FSM_DATAMASK 0x000001ff
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_READ_MAX_VDL_FSM_RDWRMASK 0xfffffe00
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_READ_MAX_VDL_FSM_RESETVALUE 0x000
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_OE_CONFIG 0x1023d084
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_OE_CONFIG_BASE 0x084
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_OE_CONFIG_OE_POST_CYCLES_MASK 0x38
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_OE_CONFIG_OE_POST_CYCLES_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_OE_CONFIG_OE_POST_CYCLES_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_OE_CONFIG_OE_POST_CYCLES_SHIFT 3
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_OE_CONFIG_OE_POST_CYCLES_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_OE_CONFIG_OE_PRE_CYCLES_MASK 0x7
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_OE_CONFIG_OE_PRE_CYCLES_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_OE_CONFIG_OE_PRE_CYCLES_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_OE_CONFIG_OE_PRE_CYCLES_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_OE_CONFIG_OE_PRE_CYCLES_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_OE_CONFIG_RESERVED_MASK 0xffffffc0
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_OE_CONFIG_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_OE_CONFIG_RESERVED_BITS 26
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_OE_CONFIG_RESERVED_SHIFT 6
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_OE_CONFIG_ALL_MASK 0x3f
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_OE_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_OE_CONFIG_ALL_BITS 6
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_OE_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_OE_CONFIG_ALL_MASK 0x3f
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_OE_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_OE_CONFIG_ALL_BITS 6
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_OE_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_OE_CONFIG_DATAMASK 0x0000003f
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_OE_CONFIG_RDWRMASK 0xffffffc0
 #define SJC16_DDR4_PHY_DQ_BYTE4_DDR4_OE_CONFIG_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE4_GDDR5_READ_ALIGNMENT_CTRL 0x1023d088
 #define SJC16_DDR4_PHY_DQ_BYTE4_GDDR5_READ_ALIGNMENT_CTRL_BASE 0x088
 #define SJC16_DDR4_PHY_DQ_BYTE4_GDDR5_READ_ALIGNMENT_CTRL_RDATA_WR2RD_DELAY_DEC_MASK 0x20000000
 #define SJC16_DDR4_PHY_DQ_BYTE4_GDDR5_READ_ALIGNMENT_CTRL_RDATA_WR2RD_DELAY_DEC_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_GDDR5_READ_ALIGNMENT_CTRL_RDATA_WR2RD_DELAY_DEC_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE4_GDDR5_READ_ALIGNMENT_CTRL_RDATA_WR2RD_DELAY_DEC_SHIFT 29
 #define SJC16_DDR4_PHY_DQ_BYTE4_GDDR5_READ_ALIGNMENT_CTRL_RDATA_WR2RD_DELAY_DEC_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_GDDR5_READ_ALIGNMENT_CTRL_RDATA_WR2RD_DELAY_INC_MASK 0x10000000
 #define SJC16_DDR4_PHY_DQ_BYTE4_GDDR5_READ_ALIGNMENT_CTRL_RDATA_WR2RD_DELAY_INC_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_GDDR5_READ_ALIGNMENT_CTRL_RDATA_WR2RD_DELAY_INC_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE4_GDDR5_READ_ALIGNMENT_CTRL_RDATA_WR2RD_DELAY_INC_SHIFT 28
 #define SJC16_DDR4_PHY_DQ_BYTE4_GDDR5_READ_ALIGNMENT_CTRL_RDATA_WR2RD_DELAY_INC_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_GDDR5_READ_ALIGNMENT_CTRL_RDATA_WR2RD_DELAY_MASK 0xf000000
 #define SJC16_DDR4_PHY_DQ_BYTE4_GDDR5_READ_ALIGNMENT_CTRL_RDATA_WR2RD_DELAY_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_GDDR5_READ_ALIGNMENT_CTRL_RDATA_WR2RD_DELAY_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE4_GDDR5_READ_ALIGNMENT_CTRL_RDATA_WR2RD_DELAY_SHIFT 24
 #define SJC16_DDR4_PHY_DQ_BYTE4_GDDR5_READ_ALIGNMENT_CTRL_RDATA_WR2RD_DELAY_RESETVALUE 0x4
 #define SJC16_DDR4_PHY_DQ_BYTE4_GDDR5_READ_ALIGNMENT_CTRL_EDC_HALF_RATE_UI_SELECT_MASK 0x800000
 #define SJC16_DDR4_PHY_DQ_BYTE4_GDDR5_READ_ALIGNMENT_CTRL_EDC_HALF_RATE_UI_SELECT_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_GDDR5_READ_ALIGNMENT_CTRL_EDC_HALF_RATE_UI_SELECT_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE4_GDDR5_READ_ALIGNMENT_CTRL_EDC_HALF_RATE_UI_SELECT_SHIFT 23
 #define SJC16_DDR4_PHY_DQ_BYTE4_GDDR5_READ_ALIGNMENT_CTRL_EDC_HALF_RATE_UI_SELECT_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_GDDR5_READ_ALIGNMENT_CTRL_EDC_HALF_RATE_ENABLE_MASK 0x400000
 #define SJC16_DDR4_PHY_DQ_BYTE4_GDDR5_READ_ALIGNMENT_CTRL_EDC_HALF_RATE_ENABLE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_GDDR5_READ_ALIGNMENT_CTRL_EDC_HALF_RATE_ENABLE_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE4_GDDR5_READ_ALIGNMENT_CTRL_EDC_HALF_RATE_ENABLE_SHIFT 22
 #define SJC16_DDR4_PHY_DQ_BYTE4_GDDR5_READ_ALIGNMENT_CTRL_EDC_HALF_RATE_ENABLE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_GDDR5_READ_ALIGNMENT_CTRL_EDC_VALID_WR2RD_DELAY_DEC_MASK 0x200000
 #define SJC16_DDR4_PHY_DQ_BYTE4_GDDR5_READ_ALIGNMENT_CTRL_EDC_VALID_WR2RD_DELAY_DEC_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_GDDR5_READ_ALIGNMENT_CTRL_EDC_VALID_WR2RD_DELAY_DEC_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE4_GDDR5_READ_ALIGNMENT_CTRL_EDC_VALID_WR2RD_DELAY_DEC_SHIFT 21
 #define SJC16_DDR4_PHY_DQ_BYTE4_GDDR5_READ_ALIGNMENT_CTRL_EDC_VALID_WR2RD_DELAY_DEC_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_GDDR5_READ_ALIGNMENT_CTRL_EDC_VALID_WR2RD_DELAY_INC_MASK 0x100000
 #define SJC16_DDR4_PHY_DQ_BYTE4_GDDR5_READ_ALIGNMENT_CTRL_EDC_VALID_WR2RD_DELAY_INC_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_GDDR5_READ_ALIGNMENT_CTRL_EDC_VALID_WR2RD_DELAY_INC_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE4_GDDR5_READ_ALIGNMENT_CTRL_EDC_VALID_WR2RD_DELAY_INC_SHIFT 20
 #define SJC16_DDR4_PHY_DQ_BYTE4_GDDR5_READ_ALIGNMENT_CTRL_EDC_VALID_WR2RD_DELAY_INC_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_GDDR5_READ_ALIGNMENT_CTRL_EDC_VALID_WR2RD_DELAY_MASK 0xf0000
 #define SJC16_DDR4_PHY_DQ_BYTE4_GDDR5_READ_ALIGNMENT_CTRL_EDC_VALID_WR2RD_DELAY_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_GDDR5_READ_ALIGNMENT_CTRL_EDC_VALID_WR2RD_DELAY_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE4_GDDR5_READ_ALIGNMENT_CTRL_EDC_VALID_WR2RD_DELAY_SHIFT 16
 #define SJC16_DDR4_PHY_DQ_BYTE4_GDDR5_READ_ALIGNMENT_CTRL_EDC_VALID_WR2RD_DELAY_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_GDDR5_READ_ALIGNMENT_CTRL_EDC_UI_SHIFT_MASK 0x7000
 #define SJC16_DDR4_PHY_DQ_BYTE4_GDDR5_READ_ALIGNMENT_CTRL_EDC_UI_SHIFT_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_GDDR5_READ_ALIGNMENT_CTRL_EDC_UI_SHIFT_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE4_GDDR5_READ_ALIGNMENT_CTRL_EDC_UI_SHIFT_SHIFT 12
 #define SJC16_DDR4_PHY_DQ_BYTE4_GDDR5_READ_ALIGNMENT_CTRL_EDC_UI_SHIFT_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_GDDR5_READ_ALIGNMENT_CTRL_DATA_VALID_WR2RD_DELAY_DEC_MASK 0x200
 #define SJC16_DDR4_PHY_DQ_BYTE4_GDDR5_READ_ALIGNMENT_CTRL_DATA_VALID_WR2RD_DELAY_DEC_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_GDDR5_READ_ALIGNMENT_CTRL_DATA_VALID_WR2RD_DELAY_DEC_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE4_GDDR5_READ_ALIGNMENT_CTRL_DATA_VALID_WR2RD_DELAY_DEC_SHIFT 9
 #define SJC16_DDR4_PHY_DQ_BYTE4_GDDR5_READ_ALIGNMENT_CTRL_DATA_VALID_WR2RD_DELAY_DEC_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_GDDR5_READ_ALIGNMENT_CTRL_DATA_VALID_WR2RD_DELAY_INC_MASK 0x100
 #define SJC16_DDR4_PHY_DQ_BYTE4_GDDR5_READ_ALIGNMENT_CTRL_DATA_VALID_WR2RD_DELAY_INC_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_GDDR5_READ_ALIGNMENT_CTRL_DATA_VALID_WR2RD_DELAY_INC_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE4_GDDR5_READ_ALIGNMENT_CTRL_DATA_VALID_WR2RD_DELAY_INC_SHIFT 8
 #define SJC16_DDR4_PHY_DQ_BYTE4_GDDR5_READ_ALIGNMENT_CTRL_DATA_VALID_WR2RD_DELAY_INC_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_GDDR5_READ_ALIGNMENT_CTRL_DATA_VALID_WR2RD_DELAY_MASK 0xf0
 #define SJC16_DDR4_PHY_DQ_BYTE4_GDDR5_READ_ALIGNMENT_CTRL_DATA_VALID_WR2RD_DELAY_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_GDDR5_READ_ALIGNMENT_CTRL_DATA_VALID_WR2RD_DELAY_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE4_GDDR5_READ_ALIGNMENT_CTRL_DATA_VALID_WR2RD_DELAY_SHIFT 4
 #define SJC16_DDR4_PHY_DQ_BYTE4_GDDR5_READ_ALIGNMENT_CTRL_DATA_VALID_WR2RD_DELAY_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_GDDR5_READ_ALIGNMENT_CTRL_DATA_UI_SHIFT_MASK 0x7
 #define SJC16_DDR4_PHY_DQ_BYTE4_GDDR5_READ_ALIGNMENT_CTRL_DATA_UI_SHIFT_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_GDDR5_READ_ALIGNMENT_CTRL_DATA_UI_SHIFT_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE4_GDDR5_READ_ALIGNMENT_CTRL_DATA_UI_SHIFT_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_GDDR5_READ_ALIGNMENT_CTRL_DATA_UI_SHIFT_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_GDDR5_READ_ALIGNMENT_CTRL_RESERVED_0_MASK 0xc0000000
 #define SJC16_DDR4_PHY_DQ_BYTE4_GDDR5_READ_ALIGNMENT_CTRL_RESERVED_0_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_GDDR5_READ_ALIGNMENT_CTRL_RESERVED_0_BITS 2
 #define SJC16_DDR4_PHY_DQ_BYTE4_GDDR5_READ_ALIGNMENT_CTRL_RESERVED_0_SHIFT 30
 #define SJC16_DDR4_PHY_DQ_BYTE4_GDDR5_READ_ALIGNMENT_CTRL_RESERVED_2_MASK 0xc00
 #define SJC16_DDR4_PHY_DQ_BYTE4_GDDR5_READ_ALIGNMENT_CTRL_RESERVED_2_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_GDDR5_READ_ALIGNMENT_CTRL_RESERVED_2_BITS 2
 #define SJC16_DDR4_PHY_DQ_BYTE4_GDDR5_READ_ALIGNMENT_CTRL_RESERVED_2_SHIFT 10
 #define SJC16_DDR4_PHY_DQ_BYTE4_GDDR5_READ_ALIGNMENT_CTRL_RESERVED_MASK 0xc0000000
 #define SJC16_DDR4_PHY_DQ_BYTE4_GDDR5_READ_ALIGNMENT_CTRL_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_GDDR5_READ_ALIGNMENT_CTRL_RESERVED_BITS 2
 #define SJC16_DDR4_PHY_DQ_BYTE4_GDDR5_READ_ALIGNMENT_CTRL_RESERVED_SHIFT 30
 #define SJC16_DDR4_PHY_DQ_BYTE4_GDDR5_READ_ALIGNMENT_CTRL_ALL_MASK 0x3fffffff
 #define SJC16_DDR4_PHY_DQ_BYTE4_GDDR5_READ_ALIGNMENT_CTRL_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_GDDR5_READ_ALIGNMENT_CTRL_ALL_BITS 30
 #define SJC16_DDR4_PHY_DQ_BYTE4_GDDR5_READ_ALIGNMENT_CTRL_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_GDDR5_READ_ALIGNMENT_CTRL_ALL_MASK 0x3fffffff
 #define SJC16_DDR4_PHY_DQ_BYTE4_GDDR5_READ_ALIGNMENT_CTRL_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_GDDR5_READ_ALIGNMENT_CTRL_ALL_BITS 30
 #define SJC16_DDR4_PHY_DQ_BYTE4_GDDR5_READ_ALIGNMENT_CTRL_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_GDDR5_READ_ALIGNMENT_CTRL_DATAMASK 0x3fff73f7
 #define SJC16_DDR4_PHY_DQ_BYTE4_GDDR5_READ_ALIGNMENT_CTRL_RDWRMASK 0xc0008c08
 #define SJC16_DDR4_PHY_DQ_BYTE4_GDDR5_READ_ALIGNMENT_CTRL_RESETVALUE 0x04000000
 #define SJC16_DDR4_PHY_DQ_BYTE4_GDDR5_READ_FSM_CTRL 0x1023d08c
 #define SJC16_DDR4_PHY_DQ_BYTE4_GDDR5_READ_FSM_CTRL_BASE 0x08c
 #define SJC16_DDR4_PHY_DQ_BYTE4_GDDR5_READ_FSM_CTRL_QDR_MODE_MASK 0x8
 #define SJC16_DDR4_PHY_DQ_BYTE4_GDDR5_READ_FSM_CTRL_QDR_MODE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_GDDR5_READ_FSM_CTRL_QDR_MODE_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE4_GDDR5_READ_FSM_CTRL_QDR_MODE_SHIFT 3
 #define SJC16_DDR4_PHY_DQ_BYTE4_GDDR5_READ_FSM_CTRL_QDR_MODE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_GDDR5_READ_FSM_CTRL_DATA_VALID_GEN_ERROR_CLEAR_MASK 0x4
 #define SJC16_DDR4_PHY_DQ_BYTE4_GDDR5_READ_FSM_CTRL_DATA_VALID_GEN_ERROR_CLEAR_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_GDDR5_READ_FSM_CTRL_DATA_VALID_GEN_ERROR_CLEAR_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE4_GDDR5_READ_FSM_CTRL_DATA_VALID_GEN_ERROR_CLEAR_SHIFT 2
 #define SJC16_DDR4_PHY_DQ_BYTE4_GDDR5_READ_FSM_CTRL_DATA_VALID_GEN_ERROR_CLEAR_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_GDDR5_READ_FSM_CTRL_DATA_VALID_GEN_ENABLE_MASK 0x2
 #define SJC16_DDR4_PHY_DQ_BYTE4_GDDR5_READ_FSM_CTRL_DATA_VALID_GEN_ENABLE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_GDDR5_READ_FSM_CTRL_DATA_VALID_GEN_ENABLE_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE4_GDDR5_READ_FSM_CTRL_DATA_VALID_GEN_ENABLE_SHIFT 1
 #define SJC16_DDR4_PHY_DQ_BYTE4_GDDR5_READ_FSM_CTRL_DATA_VALID_GEN_ENABLE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_GDDR5_READ_FSM_CTRL_SYSTEM_ENABLE_MASK 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE4_GDDR5_READ_FSM_CTRL_SYSTEM_ENABLE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_GDDR5_READ_FSM_CTRL_SYSTEM_ENABLE_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE4_GDDR5_READ_FSM_CTRL_SYSTEM_ENABLE_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_GDDR5_READ_FSM_CTRL_SYSTEM_ENABLE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_GDDR5_READ_FSM_CTRL_RESERVED_MASK 0xfffffff0
 #define SJC16_DDR4_PHY_DQ_BYTE4_GDDR5_READ_FSM_CTRL_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_GDDR5_READ_FSM_CTRL_RESERVED_BITS 28
 #define SJC16_DDR4_PHY_DQ_BYTE4_GDDR5_READ_FSM_CTRL_RESERVED_SHIFT 4
 #define SJC16_DDR4_PHY_DQ_BYTE4_GDDR5_READ_FSM_CTRL_ALL_MASK 0xf
 #define SJC16_DDR4_PHY_DQ_BYTE4_GDDR5_READ_FSM_CTRL_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_GDDR5_READ_FSM_CTRL_ALL_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE4_GDDR5_READ_FSM_CTRL_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_GDDR5_READ_FSM_CTRL_ALL_MASK 0xf
 #define SJC16_DDR4_PHY_DQ_BYTE4_GDDR5_READ_FSM_CTRL_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_GDDR5_READ_FSM_CTRL_ALL_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE4_GDDR5_READ_FSM_CTRL_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_GDDR5_READ_FSM_CTRL_DATAMASK 0x0000000f
 #define SJC16_DDR4_PHY_DQ_BYTE4_GDDR5_READ_FSM_CTRL_RDWRMASK 0xfffffff0
 #define SJC16_DDR4_PHY_DQ_BYTE4_GDDR5_READ_FSM_CTRL_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_DATA_IO_CONFIG 0x1023d090
 #define SJC16_DDR4_PHY_DQ_BYTE4_DATA_IO_CONFIG_BASE 0x090
 #define SJC16_DDR4_PHY_DQ_BYTE4_DATA_IO_CONFIG_PTERM_MASK 0x1f000000
 #define SJC16_DDR4_PHY_DQ_BYTE4_DATA_IO_CONFIG_PTERM_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_DATA_IO_CONFIG_PTERM_BITS 5
 #define SJC16_DDR4_PHY_DQ_BYTE4_DATA_IO_CONFIG_PTERM_SHIFT 24
 #define SJC16_DDR4_PHY_DQ_BYTE4_DATA_IO_CONFIG_PTERM_RESETVALUE 0x10
 #define SJC16_DDR4_PHY_DQ_BYTE4_DATA_IO_CONFIG_NTERM_MASK 0xf80000
 #define SJC16_DDR4_PHY_DQ_BYTE4_DATA_IO_CONFIG_NTERM_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_DATA_IO_CONFIG_NTERM_BITS 5
 #define SJC16_DDR4_PHY_DQ_BYTE4_DATA_IO_CONFIG_NTERM_SHIFT 19
 #define SJC16_DDR4_PHY_DQ_BYTE4_DATA_IO_CONFIG_NTERM_RESETVALUE 0xf
 #define SJC16_DDR4_PHY_DQ_BYTE4_DATA_IO_CONFIG_PULL_UP_OFF_B_MASK 0x20000
 #define SJC16_DDR4_PHY_DQ_BYTE4_DATA_IO_CONFIG_PULL_UP_OFF_B_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_DATA_IO_CONFIG_PULL_UP_OFF_B_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE4_DATA_IO_CONFIG_PULL_UP_OFF_B_SHIFT 17
 #define SJC16_DDR4_PHY_DQ_BYTE4_DATA_IO_CONFIG_PULL_UP_OFF_B_RESETVALUE 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE4_DATA_IO_CONFIG_RX_BIAS_MASK 0x18000
 #define SJC16_DDR4_PHY_DQ_BYTE4_DATA_IO_CONFIG_RX_BIAS_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_DATA_IO_CONFIG_RX_BIAS_BITS 2
 #define SJC16_DDR4_PHY_DQ_BYTE4_DATA_IO_CONFIG_RX_BIAS_SHIFT 15
 #define SJC16_DDR4_PHY_DQ_BYTE4_DATA_IO_CONFIG_RX_BIAS_RESETVALUE 0x3
 #define SJC16_DDR4_PHY_DQ_BYTE4_DATA_IO_CONFIG_PEAK_MASK 0x6000
 #define SJC16_DDR4_PHY_DQ_BYTE4_DATA_IO_CONFIG_PEAK_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_DATA_IO_CONFIG_PEAK_BITS 2
 #define SJC16_DDR4_PHY_DQ_BYTE4_DATA_IO_CONFIG_PEAK_SHIFT 13
 #define SJC16_DDR4_PHY_DQ_BYTE4_DATA_IO_CONFIG_PEAK_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_DATA_IO_CONFIG_DEM_MASK 0x1800
 #define SJC16_DDR4_PHY_DQ_BYTE4_DATA_IO_CONFIG_DEM_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_DATA_IO_CONFIG_DEM_BITS 2
 #define SJC16_DDR4_PHY_DQ_BYTE4_DATA_IO_CONFIG_DEM_SHIFT 11
 #define SJC16_DDR4_PHY_DQ_BYTE4_DATA_IO_CONFIG_DEM_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_DATA_IO_CONFIG_RXENB_MASK 0x400
 #define SJC16_DDR4_PHY_DQ_BYTE4_DATA_IO_CONFIG_RXENB_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_DATA_IO_CONFIG_RXENB_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE4_DATA_IO_CONFIG_RXENB_SHIFT 10
 #define SJC16_DDR4_PHY_DQ_BYTE4_DATA_IO_CONFIG_RXENB_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_DATA_IO_CONFIG_PD_MASK 0x3e0
 #define SJC16_DDR4_PHY_DQ_BYTE4_DATA_IO_CONFIG_PD_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_DATA_IO_CONFIG_PD_BITS 5
 #define SJC16_DDR4_PHY_DQ_BYTE4_DATA_IO_CONFIG_PD_SHIFT 5
 #define SJC16_DDR4_PHY_DQ_BYTE4_DATA_IO_CONFIG_PD_RESETVALUE 0x10
 #define SJC16_DDR4_PHY_DQ_BYTE4_DATA_IO_CONFIG_ND_MASK 0x1f
 #define SJC16_DDR4_PHY_DQ_BYTE4_DATA_IO_CONFIG_ND_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_DATA_IO_CONFIG_ND_BITS 5
 #define SJC16_DDR4_PHY_DQ_BYTE4_DATA_IO_CONFIG_ND_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_DATA_IO_CONFIG_ND_RESETVALUE 0xf
 #define SJC16_DDR4_PHY_DQ_BYTE4_DATA_IO_CONFIG_RESERVED_MASK 0xe0000000
 #define SJC16_DDR4_PHY_DQ_BYTE4_DATA_IO_CONFIG_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_DATA_IO_CONFIG_RESERVED_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE4_DATA_IO_CONFIG_RESERVED_SHIFT 29
 #define SJC16_DDR4_PHY_DQ_BYTE4_DATA_IO_CONFIG_ALL_MASK 0x1fffffff
 #define SJC16_DDR4_PHY_DQ_BYTE4_DATA_IO_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_DATA_IO_CONFIG_ALL_BITS 29
 #define SJC16_DDR4_PHY_DQ_BYTE4_DATA_IO_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_DATA_IO_CONFIG_ALL_MASK 0x1fffffff
 #define SJC16_DDR4_PHY_DQ_BYTE4_DATA_IO_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_DATA_IO_CONFIG_ALL_BITS 29
 #define SJC16_DDR4_PHY_DQ_BYTE4_DATA_IO_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_DATA_IO_CONFIG_DATAMASK 0x1ffbffff
 #define SJC16_DDR4_PHY_DQ_BYTE4_DATA_IO_CONFIG_RDWRMASK 0xe0040000
 #define SJC16_DDR4_PHY_DQ_BYTE4_DATA_IO_CONFIG_RESETVALUE 0x107b820f
 #define SJC16_DDR4_PHY_DQ_BYTE4_DQS_IO_CONFIG 0x1023d094
 #define SJC16_DDR4_PHY_DQ_BYTE4_DQS_IO_CONFIG_BASE 0x094
 #define SJC16_DDR4_PHY_DQ_BYTE4_DQS_IO_CONFIG_PTERM_MASK 0x1f000000
 #define SJC16_DDR4_PHY_DQ_BYTE4_DQS_IO_CONFIG_PTERM_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_DQS_IO_CONFIG_PTERM_BITS 5
 #define SJC16_DDR4_PHY_DQ_BYTE4_DQS_IO_CONFIG_PTERM_SHIFT 24
 #define SJC16_DDR4_PHY_DQ_BYTE4_DQS_IO_CONFIG_PTERM_RESETVALUE 0x10
 #define SJC16_DDR4_PHY_DQ_BYTE4_DQS_IO_CONFIG_NTERM_MASK 0xf80000
 #define SJC16_DDR4_PHY_DQ_BYTE4_DQS_IO_CONFIG_NTERM_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_DQS_IO_CONFIG_NTERM_BITS 5
 #define SJC16_DDR4_PHY_DQ_BYTE4_DQS_IO_CONFIG_NTERM_SHIFT 19
 #define SJC16_DDR4_PHY_DQ_BYTE4_DQS_IO_CONFIG_NTERM_RESETVALUE 0xf
 #define SJC16_DDR4_PHY_DQ_BYTE4_DQS_IO_CONFIG_PULL_UP_OFF_B_MASK 0x20000
 #define SJC16_DDR4_PHY_DQ_BYTE4_DQS_IO_CONFIG_PULL_UP_OFF_B_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_DQS_IO_CONFIG_PULL_UP_OFF_B_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE4_DQS_IO_CONFIG_PULL_UP_OFF_B_SHIFT 17
 #define SJC16_DDR4_PHY_DQ_BYTE4_DQS_IO_CONFIG_PULL_UP_OFF_B_RESETVALUE 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE4_DQS_IO_CONFIG_RX_BIAS_MASK 0x18000
 #define SJC16_DDR4_PHY_DQ_BYTE4_DQS_IO_CONFIG_RX_BIAS_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_DQS_IO_CONFIG_RX_BIAS_BITS 2
 #define SJC16_DDR4_PHY_DQ_BYTE4_DQS_IO_CONFIG_RX_BIAS_SHIFT 15
 #define SJC16_DDR4_PHY_DQ_BYTE4_DQS_IO_CONFIG_RX_BIAS_RESETVALUE 0x3
 #define SJC16_DDR4_PHY_DQ_BYTE4_DQS_IO_CONFIG_PEAK_MASK 0x6000
 #define SJC16_DDR4_PHY_DQ_BYTE4_DQS_IO_CONFIG_PEAK_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_DQS_IO_CONFIG_PEAK_BITS 2
 #define SJC16_DDR4_PHY_DQ_BYTE4_DQS_IO_CONFIG_PEAK_SHIFT 13
 #define SJC16_DDR4_PHY_DQ_BYTE4_DQS_IO_CONFIG_PEAK_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_DQS_IO_CONFIG_DEM_MASK 0x1800
 #define SJC16_DDR4_PHY_DQ_BYTE4_DQS_IO_CONFIG_DEM_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_DQS_IO_CONFIG_DEM_BITS 2
 #define SJC16_DDR4_PHY_DQ_BYTE4_DQS_IO_CONFIG_DEM_SHIFT 11
 #define SJC16_DDR4_PHY_DQ_BYTE4_DQS_IO_CONFIG_DEM_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_DQS_IO_CONFIG_RXENB_MASK 0x400
 #define SJC16_DDR4_PHY_DQ_BYTE4_DQS_IO_CONFIG_RXENB_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_DQS_IO_CONFIG_RXENB_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE4_DQS_IO_CONFIG_RXENB_SHIFT 10
 #define SJC16_DDR4_PHY_DQ_BYTE4_DQS_IO_CONFIG_RXENB_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_DQS_IO_CONFIG_PD_MASK 0x3e0
 #define SJC16_DDR4_PHY_DQ_BYTE4_DQS_IO_CONFIG_PD_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_DQS_IO_CONFIG_PD_BITS 5
 #define SJC16_DDR4_PHY_DQ_BYTE4_DQS_IO_CONFIG_PD_SHIFT 5
 #define SJC16_DDR4_PHY_DQ_BYTE4_DQS_IO_CONFIG_PD_RESETVALUE 0x10
 #define SJC16_DDR4_PHY_DQ_BYTE4_DQS_IO_CONFIG_ND_MASK 0x1f
 #define SJC16_DDR4_PHY_DQ_BYTE4_DQS_IO_CONFIG_ND_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_DQS_IO_CONFIG_ND_BITS 5
 #define SJC16_DDR4_PHY_DQ_BYTE4_DQS_IO_CONFIG_ND_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_DQS_IO_CONFIG_ND_RESETVALUE 0xf
 #define SJC16_DDR4_PHY_DQ_BYTE4_DQS_IO_CONFIG_RESERVED_MASK 0xe0000000
 #define SJC16_DDR4_PHY_DQ_BYTE4_DQS_IO_CONFIG_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_DQS_IO_CONFIG_RESERVED_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE4_DQS_IO_CONFIG_RESERVED_SHIFT 29
 #define SJC16_DDR4_PHY_DQ_BYTE4_DQS_IO_CONFIG_ALL_MASK 0x1fffffff
 #define SJC16_DDR4_PHY_DQ_BYTE4_DQS_IO_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_DQS_IO_CONFIG_ALL_BITS 29
 #define SJC16_DDR4_PHY_DQ_BYTE4_DQS_IO_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_DQS_IO_CONFIG_ALL_MASK 0x1fffffff
 #define SJC16_DDR4_PHY_DQ_BYTE4_DQS_IO_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_DQS_IO_CONFIG_ALL_BITS 29
 #define SJC16_DDR4_PHY_DQ_BYTE4_DQS_IO_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_DQS_IO_CONFIG_DATAMASK 0x1ffbffff
 #define SJC16_DDR4_PHY_DQ_BYTE4_DQS_IO_CONFIG_RDWRMASK 0xe0040000
 #define SJC16_DDR4_PHY_DQ_BYTE4_DQS_IO_CONFIG_RESETVALUE 0x107b820f
 #define SJC16_DDR4_PHY_DQ_BYTE4_VREF_DAC_CONFIG 0x1023d098
 #define SJC16_DDR4_PHY_DQ_BYTE4_VREF_DAC_CONFIG_BASE 0x098
 #define SJC16_DDR4_PHY_DQ_BYTE4_VREF_DAC_CONFIG_DATA_MASK 0xff0000
 #define SJC16_DDR4_PHY_DQ_BYTE4_VREF_DAC_CONFIG_DATA_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_VREF_DAC_CONFIG_DATA_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE4_VREF_DAC_CONFIG_DATA_SHIFT 16
 #define SJC16_DDR4_PHY_DQ_BYTE4_VREF_DAC_CONFIG_DATA_RESETVALUE 0x92
 #define SJC16_DDR4_PHY_DQ_BYTE4_VREF_DAC_CONFIG_CTRL_MASK 0xff
 #define SJC16_DDR4_PHY_DQ_BYTE4_VREF_DAC_CONFIG_CTRL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_VREF_DAC_CONFIG_CTRL_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE4_VREF_DAC_CONFIG_CTRL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_VREF_DAC_CONFIG_CTRL_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE4_VREF_DAC_CONFIG_RESERVED_MASK 0xff000000
 #define SJC16_DDR4_PHY_DQ_BYTE4_VREF_DAC_CONFIG_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_VREF_DAC_CONFIG_RESERVED_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE4_VREF_DAC_CONFIG_RESERVED_SHIFT 24
 #define SJC16_DDR4_PHY_DQ_BYTE4_VREF_DAC_CONFIG_ALL_MASK 0xffffff
 #define SJC16_DDR4_PHY_DQ_BYTE4_VREF_DAC_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_VREF_DAC_CONFIG_ALL_BITS 24
 #define SJC16_DDR4_PHY_DQ_BYTE4_VREF_DAC_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_VREF_DAC_CONFIG_ALL_MASK 0xffffff
 #define SJC16_DDR4_PHY_DQ_BYTE4_VREF_DAC_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_VREF_DAC_CONFIG_ALL_BITS 24
 #define SJC16_DDR4_PHY_DQ_BYTE4_VREF_DAC_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_VREF_DAC_CONFIG_DATAMASK 0x00ff00ff
 #define SJC16_DDR4_PHY_DQ_BYTE4_VREF_DAC_CONFIG_RDWRMASK 0xff00ff00
 #define SJC16_DDR4_PHY_DQ_BYTE4_VREF_DAC_CONFIG_RESETVALUE 0x920000
 #define SJC16_DDR4_PHY_DQ_BYTE4_LDO_R_CONFIG 0x1023d09c
 #define SJC16_DDR4_PHY_DQ_BYTE4_LDO_R_CONFIG_BASE 0x09c
 #define SJC16_DDR4_PHY_DQ_BYTE4_LDO_R_CONFIG_REF_SEL_EXT_MASK 0x2000
 #define SJC16_DDR4_PHY_DQ_BYTE4_LDO_R_CONFIG_REF_SEL_EXT_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_LDO_R_CONFIG_REF_SEL_EXT_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE4_LDO_R_CONFIG_REF_SEL_EXT_SHIFT 13
 #define SJC16_DDR4_PHY_DQ_BYTE4_LDO_R_CONFIG_REF_SEL_EXT_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_LDO_R_CONFIG_REF_EXT_MASK 0x1000
 #define SJC16_DDR4_PHY_DQ_BYTE4_LDO_R_CONFIG_REF_EXT_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_LDO_R_CONFIG_REF_EXT_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE4_LDO_R_CONFIG_REF_EXT_SHIFT 12
 #define SJC16_DDR4_PHY_DQ_BYTE4_LDO_R_CONFIG_REF_EXT_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_LDO_R_CONFIG_PWRDN_MASK 0x200
 #define SJC16_DDR4_PHY_DQ_BYTE4_LDO_R_CONFIG_PWRDN_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_LDO_R_CONFIG_PWRDN_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE4_LDO_R_CONFIG_PWRDN_SHIFT 9
 #define SJC16_DDR4_PHY_DQ_BYTE4_LDO_R_CONFIG_PWRDN_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_LDO_R_CONFIG_CTRL_MASK 0x1f8
 #define SJC16_DDR4_PHY_DQ_BYTE4_LDO_R_CONFIG_CTRL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_LDO_R_CONFIG_CTRL_BITS 6
 #define SJC16_DDR4_PHY_DQ_BYTE4_LDO_R_CONFIG_CTRL_SHIFT 3
 #define SJC16_DDR4_PHY_DQ_BYTE4_LDO_R_CONFIG_CTRL_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_LDO_R_CONFIG_BYPASS_MASK 0x4
 #define SJC16_DDR4_PHY_DQ_BYTE4_LDO_R_CONFIG_BYPASS_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_LDO_R_CONFIG_BYPASS_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE4_LDO_R_CONFIG_BYPASS_SHIFT 2
 #define SJC16_DDR4_PHY_DQ_BYTE4_LDO_R_CONFIG_BYPASS_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_LDO_R_CONFIG_BIAS_CTRL_MASK 0x3
 #define SJC16_DDR4_PHY_DQ_BYTE4_LDO_R_CONFIG_BIAS_CTRL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_LDO_R_CONFIG_BIAS_CTRL_BITS 2
 #define SJC16_DDR4_PHY_DQ_BYTE4_LDO_R_CONFIG_BIAS_CTRL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_LDO_R_CONFIG_BIAS_CTRL_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_LDO_R_CONFIG_RESERVED_MASK 0xffffc000
 #define SJC16_DDR4_PHY_DQ_BYTE4_LDO_R_CONFIG_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_LDO_R_CONFIG_RESERVED_BITS 18
 #define SJC16_DDR4_PHY_DQ_BYTE4_LDO_R_CONFIG_RESERVED_SHIFT 14
 #define SJC16_DDR4_PHY_DQ_BYTE4_LDO_R_CONFIG_ALL_MASK 0x3fff
 #define SJC16_DDR4_PHY_DQ_BYTE4_LDO_R_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_LDO_R_CONFIG_ALL_BITS 14
 #define SJC16_DDR4_PHY_DQ_BYTE4_LDO_R_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_LDO_R_CONFIG_ALL_MASK 0x3fff
 #define SJC16_DDR4_PHY_DQ_BYTE4_LDO_R_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_LDO_R_CONFIG_ALL_BITS 14
 #define SJC16_DDR4_PHY_DQ_BYTE4_LDO_R_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_LDO_R_CONFIG_DATAMASK 0x000033ff
 #define SJC16_DDR4_PHY_DQ_BYTE4_LDO_R_CONFIG_RDWRMASK 0xffffcc00
 #define SJC16_DDR4_PHY_DQ_BYTE4_LDO_R_CONFIG_RESETVALUE 0x0000
 #define SJC16_DDR4_PHY_DQ_BYTE4_LDO_W_CONFIG 0x1023d0a0
 #define SJC16_DDR4_PHY_DQ_BYTE4_LDO_W_CONFIG_BASE 0x0a0
 #define SJC16_DDR4_PHY_DQ_BYTE4_LDO_W_CONFIG_REF_SEL_EXT_MASK 0x2000
 #define SJC16_DDR4_PHY_DQ_BYTE4_LDO_W_CONFIG_REF_SEL_EXT_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_LDO_W_CONFIG_REF_SEL_EXT_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE4_LDO_W_CONFIG_REF_SEL_EXT_SHIFT 13
 #define SJC16_DDR4_PHY_DQ_BYTE4_LDO_W_CONFIG_REF_SEL_EXT_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_LDO_W_CONFIG_REF_EXT_MASK 0x1000
 #define SJC16_DDR4_PHY_DQ_BYTE4_LDO_W_CONFIG_REF_EXT_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_LDO_W_CONFIG_REF_EXT_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE4_LDO_W_CONFIG_REF_EXT_SHIFT 12
 #define SJC16_DDR4_PHY_DQ_BYTE4_LDO_W_CONFIG_REF_EXT_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_LDO_W_CONFIG_PWRDN_MASK 0x200
 #define SJC16_DDR4_PHY_DQ_BYTE4_LDO_W_CONFIG_PWRDN_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_LDO_W_CONFIG_PWRDN_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE4_LDO_W_CONFIG_PWRDN_SHIFT 9
 #define SJC16_DDR4_PHY_DQ_BYTE4_LDO_W_CONFIG_PWRDN_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_LDO_W_CONFIG_CTRL_MASK 0x1f8
 #define SJC16_DDR4_PHY_DQ_BYTE4_LDO_W_CONFIG_CTRL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_LDO_W_CONFIG_CTRL_BITS 6
 #define SJC16_DDR4_PHY_DQ_BYTE4_LDO_W_CONFIG_CTRL_SHIFT 3
 #define SJC16_DDR4_PHY_DQ_BYTE4_LDO_W_CONFIG_CTRL_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_LDO_W_CONFIG_BYPASS_MASK 0x4
 #define SJC16_DDR4_PHY_DQ_BYTE4_LDO_W_CONFIG_BYPASS_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_LDO_W_CONFIG_BYPASS_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE4_LDO_W_CONFIG_BYPASS_SHIFT 2
 #define SJC16_DDR4_PHY_DQ_BYTE4_LDO_W_CONFIG_BYPASS_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_LDO_W_CONFIG_BIAS_CTRL_MASK 0x3
 #define SJC16_DDR4_PHY_DQ_BYTE4_LDO_W_CONFIG_BIAS_CTRL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_LDO_W_CONFIG_BIAS_CTRL_BITS 2
 #define SJC16_DDR4_PHY_DQ_BYTE4_LDO_W_CONFIG_BIAS_CTRL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_LDO_W_CONFIG_BIAS_CTRL_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_LDO_W_CONFIG_RESERVED_MASK 0xffffc000
 #define SJC16_DDR4_PHY_DQ_BYTE4_LDO_W_CONFIG_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_LDO_W_CONFIG_RESERVED_BITS 18
 #define SJC16_DDR4_PHY_DQ_BYTE4_LDO_W_CONFIG_RESERVED_SHIFT 14
 #define SJC16_DDR4_PHY_DQ_BYTE4_LDO_W_CONFIG_ALL_MASK 0x3fff
 #define SJC16_DDR4_PHY_DQ_BYTE4_LDO_W_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_LDO_W_CONFIG_ALL_BITS 14
 #define SJC16_DDR4_PHY_DQ_BYTE4_LDO_W_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_LDO_W_CONFIG_ALL_MASK 0x3fff
 #define SJC16_DDR4_PHY_DQ_BYTE4_LDO_W_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_LDO_W_CONFIG_ALL_BITS 14
 #define SJC16_DDR4_PHY_DQ_BYTE4_LDO_W_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_LDO_W_CONFIG_DATAMASK 0x000033ff
 #define SJC16_DDR4_PHY_DQ_BYTE4_LDO_W_CONFIG_RDWRMASK 0xffffcc00
 #define SJC16_DDR4_PHY_DQ_BYTE4_LDO_W_CONFIG_RESETVALUE 0x0000
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_OPERATION_CONFIG 0x1023d0a4
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_OPERATION_CONFIG_BASE 0x0a4
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_OPERATION_CONFIG_CLEAR_ACTIVITY_STATS_MASK 0x10000000
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_OPERATION_CONFIG_CLEAR_ACTIVITY_STATS_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_OPERATION_CONFIG_CLEAR_ACTIVITY_STATS_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_OPERATION_CONFIG_CLEAR_ACTIVITY_STATS_SHIFT 28
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_OPERATION_CONFIG_CLEAR_ACTIVITY_STATS_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_OPERATION_CONFIG_FIFO_W2R_MIN_DELAY_2_MASK 0x8000000
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_OPERATION_CONFIG_FIFO_W2R_MIN_DELAY_2_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_OPERATION_CONFIG_FIFO_W2R_MIN_DELAY_2_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_OPERATION_CONFIG_FIFO_W2R_MIN_DELAY_2_SHIFT 27
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_OPERATION_CONFIG_FIFO_W2R_MIN_DELAY_2_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_OPERATION_CONFIG_ROLLOVER_MODE_MASK 0x7000000
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_OPERATION_CONFIG_ROLLOVER_MODE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_OPERATION_CONFIG_ROLLOVER_MODE_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_OPERATION_CONFIG_ROLLOVER_MODE_SHIFT 24
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_OPERATION_CONFIG_ROLLOVER_MODE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_OPERATION_CONFIG_HALF_RATE_MODE_MASK 0x800000
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_OPERATION_CONFIG_HALF_RATE_MODE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_OPERATION_CONFIG_HALF_RATE_MODE_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_OPERATION_CONFIG_HALF_RATE_MODE_SHIFT 23
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_OPERATION_CONFIG_HALF_RATE_MODE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_OPERATION_CONFIG_INIT_TRACK_OPTIONS_MASK 0x600000
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_OPERATION_CONFIG_INIT_TRACK_OPTIONS_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_OPERATION_CONFIG_INIT_TRACK_OPTIONS_BITS 2
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_OPERATION_CONFIG_INIT_TRACK_OPTIONS_SHIFT 21
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_OPERATION_CONFIG_INIT_TRACK_OPTIONS_RESETVALUE 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_OPERATION_CONFIG_INIT_TRACK_TRANSITION_MASK 0x100000
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_OPERATION_CONFIG_INIT_TRACK_TRANSITION_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_OPERATION_CONFIG_INIT_TRACK_TRANSITION_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_OPERATION_CONFIG_INIT_TRACK_TRANSITION_SHIFT 20
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_OPERATION_CONFIG_INIT_TRACK_TRANSITION_RESETVALUE 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_OPERATION_CONFIG_ACCU_POS_THRESHOLD_MASK 0xff000
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_OPERATION_CONFIG_ACCU_POS_THRESHOLD_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_OPERATION_CONFIG_ACCU_POS_THRESHOLD_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_OPERATION_CONFIG_ACCU_POS_THRESHOLD_SHIFT 12
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_OPERATION_CONFIG_ACCU_POS_THRESHOLD_RESETVALUE 0x10
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_OPERATION_CONFIG_ACCU_LOAD_VALUE_MASK 0xff0
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_OPERATION_CONFIG_ACCU_LOAD_VALUE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_OPERATION_CONFIG_ACCU_LOAD_VALUE_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_OPERATION_CONFIG_ACCU_LOAD_VALUE_SHIFT 4
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_OPERATION_CONFIG_ACCU_LOAD_VALUE_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_OPERATION_CONFIG_ACCU_LOAD_MASK 0x8
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_OPERATION_CONFIG_ACCU_LOAD_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_OPERATION_CONFIG_ACCU_LOAD_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_OPERATION_CONFIG_ACCU_LOAD_SHIFT 3
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_OPERATION_CONFIG_ACCU_LOAD_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_OPERATION_CONFIG_UPDATE_MODE_MASK 0x6
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_OPERATION_CONFIG_UPDATE_MODE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_OPERATION_CONFIG_UPDATE_MODE_BITS 2
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_OPERATION_CONFIG_UPDATE_MODE_SHIFT 1
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_OPERATION_CONFIG_UPDATE_MODE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_OPERATION_CONFIG_ENABLE_MASK 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_OPERATION_CONFIG_ENABLE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_OPERATION_CONFIG_ENABLE_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_OPERATION_CONFIG_ENABLE_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_OPERATION_CONFIG_ENABLE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_OPERATION_CONFIG_RESERVED_MASK 0xe0000000
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_OPERATION_CONFIG_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_OPERATION_CONFIG_RESERVED_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_OPERATION_CONFIG_RESERVED_SHIFT 29
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_OPERATION_CONFIG_ALL_MASK 0x1fffffff
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_OPERATION_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_OPERATION_CONFIG_ALL_BITS 29
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_OPERATION_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_OPERATION_CONFIG_ALL_MASK 0x1fffffff
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_OPERATION_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_OPERATION_CONFIG_ALL_BITS 29
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_OPERATION_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_OPERATION_CONFIG_DATAMASK 0x1fffffff
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_OPERATION_CONFIG_RDWRMASK 0xe0000000
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_OPERATION_CONFIG_RESETVALUE 0x00310000
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_UPDATE_CONFIG 0x1023d0a8
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_UPDATE_CONFIG_BASE 0x0a8
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_UPDATE_CONFIG_ROLLOVER_PHASE_GAP_MASK 0xfc000000
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_UPDATE_CONFIG_ROLLOVER_PHASE_GAP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_UPDATE_CONFIG_ROLLOVER_PHASE_GAP_BITS 6
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_UPDATE_CONFIG_ROLLOVER_PHASE_GAP_SHIFT 26
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_UPDATE_CONFIG_ROLLOVER_PHASE_GAP_RESETVALUE 0x3
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_UPDATE_CONFIG_ROLLOVER_AMOUNT_MASK 0x1ff0000
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_UPDATE_CONFIG_ROLLOVER_AMOUNT_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_UPDATE_CONFIG_ROLLOVER_AMOUNT_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_UPDATE_CONFIG_ROLLOVER_AMOUNT_SHIFT 16
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_UPDATE_CONFIG_ROLLOVER_AMOUNT_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_UPDATE_CONFIG_UPDATE_ENABLE_DELAY_MASK 0x3f00
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_UPDATE_CONFIG_UPDATE_ENABLE_DELAY_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_UPDATE_CONFIG_UPDATE_ENABLE_DELAY_BITS 6
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_UPDATE_CONFIG_UPDATE_ENABLE_DELAY_SHIFT 8
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_UPDATE_CONFIG_UPDATE_ENABLE_DELAY_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_UPDATE_CONFIG_IMMEDIATE_UPDATE_THRESHOLD_MASK 0xf0
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_UPDATE_CONFIG_IMMEDIATE_UPDATE_THRESHOLD_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_UPDATE_CONFIG_IMMEDIATE_UPDATE_THRESHOLD_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_UPDATE_CONFIG_IMMEDIATE_UPDATE_THRESHOLD_SHIFT 4
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_UPDATE_CONFIG_IMMEDIATE_UPDATE_THRESHOLD_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_UPDATE_CONFIG_VDL_UPDATE_GAP_MASK 0xf
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_UPDATE_CONFIG_VDL_UPDATE_GAP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_UPDATE_CONFIG_VDL_UPDATE_GAP_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_UPDATE_CONFIG_VDL_UPDATE_GAP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_UPDATE_CONFIG_VDL_UPDATE_GAP_RESETVALUE 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_UPDATE_CONFIG_ALL_MASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_UPDATE_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_UPDATE_CONFIG_ALL_BITS 32
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_UPDATE_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_UPDATE_CONFIG_ALL_MASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_UPDATE_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_UPDATE_CONFIG_ALL_BITS 32
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_UPDATE_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_UPDATE_CONFIG_DATAMASK 0xfdff3fff
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_UPDATE_CONFIG_RDWRMASK 0x0200c000
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_UPDATE_CONFIG_RESETVALUE 0x0c000001
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_TRACK_CONFIG 0x1023d0ac
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_TRACK_CONFIG_BASE 0x0ac
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_TRACK_CONFIG_SEARCH_ACTIVE_TIMEOUT_MASK 0xf000
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_TRACK_CONFIG_SEARCH_ACTIVE_TIMEOUT_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_TRACK_CONFIG_SEARCH_ACTIVE_TIMEOUT_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_TRACK_CONFIG_SEARCH_ACTIVE_TIMEOUT_SHIFT 12
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_TRACK_CONFIG_SEARCH_ACTIVE_TIMEOUT_RESETVALUE 0xf
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_TRACK_CONFIG_TRACK_ACTIVE_TIMEOUT_MASK 0xf00
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_TRACK_CONFIG_TRACK_ACTIVE_TIMEOUT_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_TRACK_CONFIG_TRACK_ACTIVE_TIMEOUT_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_TRACK_CONFIG_TRACK_ACTIVE_TIMEOUT_SHIFT 8
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_TRACK_CONFIG_TRACK_ACTIVE_TIMEOUT_RESETVALUE 0xf
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_TRACK_CONFIG_ACCU_ACTIVE_TIMEOUT_MASK 0xff
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_TRACK_CONFIG_ACCU_ACTIVE_TIMEOUT_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_TRACK_CONFIG_ACCU_ACTIVE_TIMEOUT_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_TRACK_CONFIG_ACCU_ACTIVE_TIMEOUT_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_TRACK_CONFIG_ACCU_ACTIVE_TIMEOUT_RESETVALUE 0xff
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_TRACK_CONFIG_RESERVED_MASK 0xffff0000
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_TRACK_CONFIG_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_TRACK_CONFIG_RESERVED_BITS 16
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_TRACK_CONFIG_RESERVED_SHIFT 16
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_TRACK_CONFIG_ALL_MASK 0xffff
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_TRACK_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_TRACK_CONFIG_ALL_BITS 16
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_TRACK_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_TRACK_CONFIG_ALL_MASK 0xffff
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_TRACK_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_TRACK_CONFIG_ALL_BITS 16
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_TRACK_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_TRACK_CONFIG_DATAMASK 0x0000ffff
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_TRACK_CONFIG_RDWRMASK 0xffff0000
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_TRACK_CONFIG_RESETVALUE 0xffff
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_TIMING_CONFIG 0x1023d0b0
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_TIMING_CONFIG_BASE 0x0b0
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_TIMING_CONFIG_DATA_VALID_WR2RD_DELAY_LOAD_VALUE_MASK 0xf0000
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_TIMING_CONFIG_DATA_VALID_WR2RD_DELAY_LOAD_VALUE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_TIMING_CONFIG_DATA_VALID_WR2RD_DELAY_LOAD_VALUE_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_TIMING_CONFIG_DATA_VALID_WR2RD_DELAY_LOAD_VALUE_SHIFT 16
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_TIMING_CONFIG_DATA_VALID_WR2RD_DELAY_LOAD_VALUE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_TIMING_CONFIG_EDC_VALID_WR2RD_DELAY_LOAD_VALUE_MASK 0xf000
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_TIMING_CONFIG_EDC_VALID_WR2RD_DELAY_LOAD_VALUE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_TIMING_CONFIG_EDC_VALID_WR2RD_DELAY_LOAD_VALUE_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_TIMING_CONFIG_EDC_VALID_WR2RD_DELAY_LOAD_VALUE_SHIFT 12
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_TIMING_CONFIG_EDC_VALID_WR2RD_DELAY_LOAD_VALUE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_TIMING_CONFIG_DATA_READ_UI_SHIFT_LOAD_VALUE_MASK 0x700
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_TIMING_CONFIG_DATA_READ_UI_SHIFT_LOAD_VALUE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_TIMING_CONFIG_DATA_READ_UI_SHIFT_LOAD_VALUE_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_TIMING_CONFIG_DATA_READ_UI_SHIFT_LOAD_VALUE_SHIFT 8
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_TIMING_CONFIG_DATA_READ_UI_SHIFT_LOAD_VALUE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_TIMING_CONFIG_EDC_READ_UI_SHIFT_LOAD_VALUE_MASK 0x70
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_TIMING_CONFIG_EDC_READ_UI_SHIFT_LOAD_VALUE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_TIMING_CONFIG_EDC_READ_UI_SHIFT_LOAD_VALUE_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_TIMING_CONFIG_EDC_READ_UI_SHIFT_LOAD_VALUE_SHIFT 4
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_TIMING_CONFIG_EDC_READ_UI_SHIFT_LOAD_VALUE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_TIMING_CONFIG_CLEAR_VDL_STATS_ON_ROLLOVER_MASK 0x8
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_TIMING_CONFIG_CLEAR_VDL_STATS_ON_ROLLOVER_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_TIMING_CONFIG_CLEAR_VDL_STATS_ON_ROLLOVER_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_TIMING_CONFIG_CLEAR_VDL_STATS_ON_ROLLOVER_SHIFT 3
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_TIMING_CONFIG_CLEAR_VDL_STATS_ON_ROLLOVER_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_TIMING_CONFIG_CLEAR_VDL_STATS_MASK 0x4
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_TIMING_CONFIG_CLEAR_VDL_STATS_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_TIMING_CONFIG_CLEAR_VDL_STATS_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_TIMING_CONFIG_CLEAR_VDL_STATS_SHIFT 2
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_TIMING_CONFIG_CLEAR_VDL_STATS_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_TIMING_CONFIG_VDL_SWITCH_MASK 0x2
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_TIMING_CONFIG_VDL_SWITCH_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_TIMING_CONFIG_VDL_SWITCH_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_TIMING_CONFIG_VDL_SWITCH_SHIFT 1
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_TIMING_CONFIG_VDL_SWITCH_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_TIMING_CONFIG_VDL_LOAD_MASK 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_TIMING_CONFIG_VDL_LOAD_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_TIMING_CONFIG_VDL_LOAD_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_TIMING_CONFIG_VDL_LOAD_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_TIMING_CONFIG_VDL_LOAD_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_TIMING_CONFIG_RESERVED_0_MASK 0xfff00000
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_TIMING_CONFIG_RESERVED_0_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_TIMING_CONFIG_RESERVED_0_BITS 12
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_TIMING_CONFIG_RESERVED_0_SHIFT 20
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_TIMING_CONFIG_RESERVED_MASK 0xfff00000
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_TIMING_CONFIG_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_TIMING_CONFIG_RESERVED_BITS 12
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_TIMING_CONFIG_RESERVED_SHIFT 20
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_TIMING_CONFIG_ALL_MASK 0xfffff
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_TIMING_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_TIMING_CONFIG_ALL_BITS 20
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_TIMING_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_TIMING_CONFIG_ALL_MASK 0xfffff
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_TIMING_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_TIMING_CONFIG_ALL_BITS 20
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_TIMING_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_TIMING_CONFIG_DATAMASK 0x000ff77f
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_TIMING_CONFIG_RDWRMASK 0xfff00880
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_TIMING_CONFIG_RESETVALUE 0x00000
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_VDL_CAP_CONFIG 0x1023d0b4
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_VDL_CAP_CONFIG_BASE 0x0b4
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_VDL_CAP_CONFIG_FLEXIBLE_VDL_CAP_MASK 0x10000000
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_VDL_CAP_CONFIG_FLEXIBLE_VDL_CAP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_VDL_CAP_CONFIG_FLEXIBLE_VDL_CAP_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_VDL_CAP_CONFIG_FLEXIBLE_VDL_CAP_SHIFT 28
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_VDL_CAP_CONFIG_FLEXIBLE_VDL_CAP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_VDL_CAP_CONFIG_VDL_MAX_VALUE_CAP_MASK 0x1ff0000
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_VDL_CAP_CONFIG_VDL_MAX_VALUE_CAP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_VDL_CAP_CONFIG_VDL_MAX_VALUE_CAP_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_VDL_CAP_CONFIG_VDL_MAX_VALUE_CAP_SHIFT 16
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_VDL_CAP_CONFIG_VDL_MAX_VALUE_CAP_RESETVALUE 0x1ff
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_VDL_CAP_CONFIG_VDL_MIN_VALUE_CAP_MASK 0x1ff
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_VDL_CAP_CONFIG_VDL_MIN_VALUE_CAP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_VDL_CAP_CONFIG_VDL_MIN_VALUE_CAP_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_VDL_CAP_CONFIG_VDL_MIN_VALUE_CAP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_VDL_CAP_CONFIG_VDL_MIN_VALUE_CAP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_VDL_CAP_CONFIG_RESERVED_0_MASK 0xe0000000
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_VDL_CAP_CONFIG_RESERVED_0_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_VDL_CAP_CONFIG_RESERVED_0_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_VDL_CAP_CONFIG_RESERVED_0_SHIFT 29
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_VDL_CAP_CONFIG_RESERVED_1_MASK 0xe000000
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_VDL_CAP_CONFIG_RESERVED_1_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_VDL_CAP_CONFIG_RESERVED_1_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_VDL_CAP_CONFIG_RESERVED_1_SHIFT 25
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_VDL_CAP_CONFIG_RESERVED_2_MASK 0xfe00
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_VDL_CAP_CONFIG_RESERVED_2_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_VDL_CAP_CONFIG_RESERVED_2_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_VDL_CAP_CONFIG_RESERVED_2_SHIFT 9
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_VDL_CAP_CONFIG_RESERVED_MASK 0xe0000000
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_VDL_CAP_CONFIG_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_VDL_CAP_CONFIG_RESERVED_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_VDL_CAP_CONFIG_RESERVED_SHIFT 29
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_VDL_CAP_CONFIG_ALL_MASK 0x1fffffff
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_VDL_CAP_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_VDL_CAP_CONFIG_ALL_BITS 29
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_VDL_CAP_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_VDL_CAP_CONFIG_ALL_MASK 0x1fffffff
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_VDL_CAP_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_VDL_CAP_CONFIG_ALL_BITS 29
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_VDL_CAP_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_VDL_CAP_CONFIG_DATAMASK 0x11ff01ff
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_VDL_CAP_CONFIG_RDWRMASK 0xee00fe00
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_VDL_CAP_CONFIG_RESETVALUE 0x01ff0000
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_P_VDL_CONFIG 0x1023d0b8
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_P_VDL_CONFIG_BASE 0x0b8
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_P_VDL_CONFIG_DP_VDL_LOAD_VALUE_MASK 0x1ff0000
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_P_VDL_CONFIG_DP_VDL_LOAD_VALUE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_P_VDL_CONFIG_DP_VDL_LOAD_VALUE_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_P_VDL_CONFIG_DP_VDL_LOAD_VALUE_SHIFT 16
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_P_VDL_CONFIG_DP_VDL_LOAD_VALUE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_P_VDL_CONFIG_EP_VDL_LOAD_VALUE_MASK 0x1ff
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_P_VDL_CONFIG_EP_VDL_LOAD_VALUE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_P_VDL_CONFIG_EP_VDL_LOAD_VALUE_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_P_VDL_CONFIG_EP_VDL_LOAD_VALUE_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_P_VDL_CONFIG_EP_VDL_LOAD_VALUE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_P_VDL_CONFIG_RESERVED_MASK 0xfe000000
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_P_VDL_CONFIG_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_P_VDL_CONFIG_RESERVED_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_P_VDL_CONFIG_RESERVED_SHIFT 25
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_P_VDL_CONFIG_ALL_MASK 0x1ffffff
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_P_VDL_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_P_VDL_CONFIG_ALL_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_P_VDL_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_P_VDL_CONFIG_ALL_MASK 0x1ffffff
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_P_VDL_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_P_VDL_CONFIG_ALL_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_P_VDL_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_P_VDL_CONFIG_DATAMASK 0x01ff01ff
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_P_VDL_CONFIG_RDWRMASK 0xfe00fe00
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_P_VDL_CONFIG_RESETVALUE 0x0000000
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_N_VDL_CONFIG 0x1023d0bc
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_N_VDL_CONFIG_BASE 0x0bc
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_N_VDL_CONFIG_DN_VDL_LOAD_VALUE_MASK 0x1ff0000
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_N_VDL_CONFIG_DN_VDL_LOAD_VALUE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_N_VDL_CONFIG_DN_VDL_LOAD_VALUE_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_N_VDL_CONFIG_DN_VDL_LOAD_VALUE_SHIFT 16
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_N_VDL_CONFIG_DN_VDL_LOAD_VALUE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_N_VDL_CONFIG_EN_VDL_LOAD_VALUE_MASK 0x1ff
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_N_VDL_CONFIG_EN_VDL_LOAD_VALUE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_N_VDL_CONFIG_EN_VDL_LOAD_VALUE_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_N_VDL_CONFIG_EN_VDL_LOAD_VALUE_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_N_VDL_CONFIG_EN_VDL_LOAD_VALUE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_N_VDL_CONFIG_RESERVED_MASK 0xfe000000
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_N_VDL_CONFIG_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_N_VDL_CONFIG_RESERVED_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_N_VDL_CONFIG_RESERVED_SHIFT 25
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_N_VDL_CONFIG_ALL_MASK 0x1ffffff
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_N_VDL_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_N_VDL_CONFIG_ALL_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_N_VDL_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_N_VDL_CONFIG_ALL_MASK 0x1ffffff
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_N_VDL_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_N_VDL_CONFIG_ALL_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_N_VDL_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_N_VDL_CONFIG_DATAMASK 0x01ff01ff
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_N_VDL_CONFIG_RDWRMASK 0xfe00fe00
 #define SJC16_DDR4_PHY_DQ_BYTE4_CDR_N_VDL_CONFIG_RESETVALUE 0x0000000
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_P_VDL 0x1023d0c0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_P_VDL_BASE 0x0c0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_P_VDL_DP_VDL_VALUE_MASK 0x1ff0000
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_P_VDL_DP_VDL_VALUE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_P_VDL_DP_VDL_VALUE_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_P_VDL_DP_VDL_VALUE_SHIFT 16
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_P_VDL_DP_VDL_VALUE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_P_VDL_EP_VDL_VALUE_MASK 0x1ff
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_P_VDL_EP_VDL_VALUE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_P_VDL_EP_VDL_VALUE_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_P_VDL_EP_VDL_VALUE_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_P_VDL_EP_VDL_VALUE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_P_VDL_RESERVED_MASK 0xfe000000
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_P_VDL_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_P_VDL_RESERVED_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_P_VDL_RESERVED_SHIFT 25
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_P_VDL_ALL_MASK 0x1ffffff
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_P_VDL_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_P_VDL_ALL_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_P_VDL_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_P_VDL_ALL_MASK 0x1ffffff
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_P_VDL_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_P_VDL_ALL_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_P_VDL_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_P_VDL_DATAMASK 0x01ff01ff
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_P_VDL_RDWRMASK 0xfe00fe00
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_P_VDL_RESETVALUE 0x0000000
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_N_VDL 0x1023d0c4
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_N_VDL_BASE 0x0c4
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_N_VDL_DN_VDL_VALUE_MASK 0x1ff0000
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_N_VDL_DN_VDL_VALUE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_N_VDL_DN_VDL_VALUE_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_N_VDL_DN_VDL_VALUE_SHIFT 16
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_N_VDL_DN_VDL_VALUE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_N_VDL_EN_VDL_VALUE_MASK 0x1ff
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_N_VDL_EN_VDL_VALUE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_N_VDL_EN_VDL_VALUE_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_N_VDL_EN_VDL_VALUE_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_N_VDL_EN_VDL_VALUE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_N_VDL_RESERVED_MASK 0xfe000000
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_N_VDL_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_N_VDL_RESERVED_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_N_VDL_RESERVED_SHIFT 25
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_N_VDL_ALL_MASK 0x1ffffff
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_N_VDL_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_N_VDL_ALL_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_N_VDL_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_N_VDL_ALL_MASK 0x1ffffff
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_N_VDL_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_N_VDL_ALL_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_N_VDL_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_N_VDL_DATAMASK 0x01ff01ff
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_N_VDL_RDWRMASK 0xfe00fe00
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_N_VDL_RESETVALUE 0x0000000
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_EP_VDL_STAT 0x1023d0c8
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_EP_VDL_STAT_BASE 0x0c8
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_EP_VDL_STAT_MAX_VDL_VALUE_MASK 0x1ff0000
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_EP_VDL_STAT_MAX_VDL_VALUE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_EP_VDL_STAT_MAX_VDL_VALUE_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_EP_VDL_STAT_MAX_VDL_VALUE_SHIFT 16
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_EP_VDL_STAT_MAX_VDL_VALUE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_EP_VDL_STAT_MIN_VDL_VALUE_MASK 0x1ff
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_EP_VDL_STAT_MIN_VDL_VALUE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_EP_VDL_STAT_MIN_VDL_VALUE_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_EP_VDL_STAT_MIN_VDL_VALUE_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_EP_VDL_STAT_MIN_VDL_VALUE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_EP_VDL_STAT_RESERVED_MASK 0xfe000000
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_EP_VDL_STAT_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_EP_VDL_STAT_RESERVED_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_EP_VDL_STAT_RESERVED_SHIFT 25
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_EP_VDL_STAT_ALL_MASK 0x1ffffff
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_EP_VDL_STAT_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_EP_VDL_STAT_ALL_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_EP_VDL_STAT_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_EP_VDL_STAT_ALL_MASK 0x1ffffff
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_EP_VDL_STAT_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_EP_VDL_STAT_ALL_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_EP_VDL_STAT_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_EP_VDL_STAT_DATAMASK 0x01ff01ff
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_EP_VDL_STAT_RDWRMASK 0xfe00fe00
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_EP_VDL_STAT_RESETVALUE 0x0000000
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_DP_VDL_STAT 0x1023d0cc
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_DP_VDL_STAT_BASE 0x0cc
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_DP_VDL_STAT_MAX_VDL_VALUE_MASK 0x1ff0000
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_DP_VDL_STAT_MAX_VDL_VALUE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_DP_VDL_STAT_MAX_VDL_VALUE_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_DP_VDL_STAT_MAX_VDL_VALUE_SHIFT 16
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_DP_VDL_STAT_MAX_VDL_VALUE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_DP_VDL_STAT_MIN_VDL_VALUE_MASK 0x1ff
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_DP_VDL_STAT_MIN_VDL_VALUE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_DP_VDL_STAT_MIN_VDL_VALUE_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_DP_VDL_STAT_MIN_VDL_VALUE_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_DP_VDL_STAT_MIN_VDL_VALUE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_DP_VDL_STAT_RESERVED_MASK 0xfe000000
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_DP_VDL_STAT_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_DP_VDL_STAT_RESERVED_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_DP_VDL_STAT_RESERVED_SHIFT 25
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_DP_VDL_STAT_ALL_MASK 0x1ffffff
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_DP_VDL_STAT_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_DP_VDL_STAT_ALL_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_DP_VDL_STAT_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_DP_VDL_STAT_ALL_MASK 0x1ffffff
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_DP_VDL_STAT_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_DP_VDL_STAT_ALL_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_DP_VDL_STAT_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_DP_VDL_STAT_DATAMASK 0x01ff01ff
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_DP_VDL_STAT_RDWRMASK 0xfe00fe00
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_DP_VDL_STAT_RESETVALUE 0x0000000
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_EN_VDL_STAT 0x1023d0d0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_EN_VDL_STAT_BASE 0x0d0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_EN_VDL_STAT_MAX_VDL_VALUE_MASK 0x1ff0000
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_EN_VDL_STAT_MAX_VDL_VALUE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_EN_VDL_STAT_MAX_VDL_VALUE_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_EN_VDL_STAT_MAX_VDL_VALUE_SHIFT 16
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_EN_VDL_STAT_MAX_VDL_VALUE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_EN_VDL_STAT_MIN_VDL_VALUE_MASK 0x1ff
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_EN_VDL_STAT_MIN_VDL_VALUE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_EN_VDL_STAT_MIN_VDL_VALUE_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_EN_VDL_STAT_MIN_VDL_VALUE_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_EN_VDL_STAT_MIN_VDL_VALUE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_EN_VDL_STAT_RESERVED_MASK 0xfe000000
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_EN_VDL_STAT_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_EN_VDL_STAT_RESERVED_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_EN_VDL_STAT_RESERVED_SHIFT 25
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_EN_VDL_STAT_ALL_MASK 0x1ffffff
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_EN_VDL_STAT_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_EN_VDL_STAT_ALL_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_EN_VDL_STAT_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_EN_VDL_STAT_ALL_MASK 0x1ffffff
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_EN_VDL_STAT_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_EN_VDL_STAT_ALL_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_EN_VDL_STAT_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_EN_VDL_STAT_DATAMASK 0x01ff01ff
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_EN_VDL_STAT_RDWRMASK 0xfe00fe00
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_EN_VDL_STAT_RESETVALUE 0x0000000
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_DN_VDL_STAT 0x1023d0d4
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_DN_VDL_STAT_BASE 0x0d4
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_DN_VDL_STAT_MAX_VDL_VALUE_MASK 0x1ff0000
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_DN_VDL_STAT_MAX_VDL_VALUE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_DN_VDL_STAT_MAX_VDL_VALUE_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_DN_VDL_STAT_MAX_VDL_VALUE_SHIFT 16
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_DN_VDL_STAT_MAX_VDL_VALUE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_DN_VDL_STAT_MIN_VDL_VALUE_MASK 0x1ff
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_DN_VDL_STAT_MIN_VDL_VALUE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_DN_VDL_STAT_MIN_VDL_VALUE_BITS 9
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_DN_VDL_STAT_MIN_VDL_VALUE_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_DN_VDL_STAT_MIN_VDL_VALUE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_DN_VDL_STAT_RESERVED_MASK 0xfe000000
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_DN_VDL_STAT_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_DN_VDL_STAT_RESERVED_BITS 7
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_DN_VDL_STAT_RESERVED_SHIFT 25
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_DN_VDL_STAT_ALL_MASK 0x1ffffff
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_DN_VDL_STAT_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_DN_VDL_STAT_ALL_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_DN_VDL_STAT_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_DN_VDL_STAT_ALL_MASK 0x1ffffff
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_DN_VDL_STAT_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_DN_VDL_STAT_ALL_BITS 25
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_DN_VDL_STAT_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_DN_VDL_STAT_DATAMASK 0x01ff01ff
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_DN_VDL_STAT_RDWRMASK 0xfe00fe00
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_DN_VDL_STAT_RESETVALUE 0x0000000
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_OPERATION 0x1023d0d8
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_OPERATION_BASE 0x0d8
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_OPERATION_ROLLOVER_OVERFLOW_MASK 0x10000000
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_OPERATION_ROLLOVER_OVERFLOW_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_OPERATION_ROLLOVER_OVERFLOW_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_OPERATION_ROLLOVER_OVERFLOW_SHIFT 28
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_OPERATION_ROLLOVER_OVERFLOW_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_OPERATION_ROLLOVER_COUNT_MASK 0xff00000
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_OPERATION_ROLLOVER_COUNT_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_OPERATION_ROLLOVER_COUNT_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_OPERATION_ROLLOVER_COUNT_SHIFT 20
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_OPERATION_ROLLOVER_COUNT_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_OPERATION_SEARCH_ACTIVE_RETRIGGERED_MASK 0x20000
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_OPERATION_SEARCH_ACTIVE_RETRIGGERED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_OPERATION_SEARCH_ACTIVE_RETRIGGERED_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_OPERATION_SEARCH_ACTIVE_RETRIGGERED_SHIFT 17
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_OPERATION_SEARCH_ACTIVE_RETRIGGERED_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_OPERATION_INIT_SEARCH_COMPLETE_MASK 0x10000
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_OPERATION_INIT_SEARCH_COMPLETE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_OPERATION_INIT_SEARCH_COMPLETE_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_OPERATION_INIT_SEARCH_COMPLETE_SHIFT 16
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_OPERATION_INIT_SEARCH_COMPLETE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_OPERATION_INIT_SEARCH_ACTIVE_MASK 0x8000
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_OPERATION_INIT_SEARCH_ACTIVE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_OPERATION_INIT_SEARCH_ACTIVE_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_OPERATION_INIT_SEARCH_ACTIVE_SHIFT 15
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_OPERATION_INIT_SEARCH_ACTIVE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_OPERATION_TRACK_ACTIVE_LOST_MASK 0x4000
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_OPERATION_TRACK_ACTIVE_LOST_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_OPERATION_TRACK_ACTIVE_LOST_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_OPERATION_TRACK_ACTIVE_LOST_SHIFT 14
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_OPERATION_TRACK_ACTIVE_LOST_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_OPERATION_INIT_TRACK_ACTIVE_MASK 0x2000
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_OPERATION_INIT_TRACK_ACTIVE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_OPERATION_INIT_TRACK_ACTIVE_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_OPERATION_INIT_TRACK_ACTIVE_SHIFT 13
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_OPERATION_INIT_TRACK_ACTIVE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_OPERATION_ACCU_ACTIVE_LOST_MASK 0x1000
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_OPERATION_ACCU_ACTIVE_LOST_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_OPERATION_ACCU_ACTIVE_LOST_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_OPERATION_ACCU_ACTIVE_LOST_SHIFT 12
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_OPERATION_ACCU_ACTIVE_LOST_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_OPERATION_INIT_ACCU_ACTIVE_MASK 0x800
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_OPERATION_INIT_ACCU_ACTIVE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_OPERATION_INIT_ACCU_ACTIVE_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_OPERATION_INIT_ACCU_ACTIVE_SHIFT 11
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_OPERATION_INIT_ACCU_ACTIVE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_OPERATION_SEARCH_ACTIVE_MASK 0x400
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_OPERATION_SEARCH_ACTIVE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_OPERATION_SEARCH_ACTIVE_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_OPERATION_SEARCH_ACTIVE_SHIFT 10
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_OPERATION_SEARCH_ACTIVE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_OPERATION_TRACK_ACTIVE_MASK 0x200
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_OPERATION_TRACK_ACTIVE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_OPERATION_TRACK_ACTIVE_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_OPERATION_TRACK_ACTIVE_SHIFT 9
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_OPERATION_TRACK_ACTIVE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_OPERATION_ACCU_ACTIVE_MASK 0x100
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_OPERATION_ACCU_ACTIVE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_OPERATION_ACCU_ACTIVE_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_OPERATION_ACCU_ACTIVE_SHIFT 8
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_OPERATION_ACCU_ACTIVE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_OPERATION_ACCU_VALUE_MASK 0xff
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_OPERATION_ACCU_VALUE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_OPERATION_ACCU_VALUE_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_OPERATION_ACCU_VALUE_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_OPERATION_ACCU_VALUE_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_OPERATION_RESERVED_MASK 0xe0000000
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_OPERATION_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_OPERATION_RESERVED_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_OPERATION_RESERVED_SHIFT 29
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_OPERATION_ALL_MASK 0x1fffffff
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_OPERATION_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_OPERATION_ALL_BITS 29
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_OPERATION_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_OPERATION_ALL_MASK 0x1fffffff
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_OPERATION_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_OPERATION_ALL_BITS 29
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_OPERATION_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_OPERATION_DATAMASK 0x1ff3ffff
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_OPERATION_RDWRMASK 0xe00c0000
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_OPERATION_RESETVALUE 0x00000000
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_TIMING 0x1023d0dc
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_TIMING_BASE 0x0dc
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_TIMING_DATA_VALID_WR2RD_DELAY_MASK 0xf0000
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_TIMING_DATA_VALID_WR2RD_DELAY_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_TIMING_DATA_VALID_WR2RD_DELAY_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_TIMING_DATA_VALID_WR2RD_DELAY_SHIFT 16
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_TIMING_DATA_VALID_WR2RD_DELAY_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_TIMING_EDC_VALID_WR2RD_DELAY_MASK 0xf000
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_TIMING_EDC_VALID_WR2RD_DELAY_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_TIMING_EDC_VALID_WR2RD_DELAY_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_TIMING_EDC_VALID_WR2RD_DELAY_SHIFT 12
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_TIMING_EDC_VALID_WR2RD_DELAY_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_TIMING_DATA_READ_UI_SHIFT_MASK 0x700
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_TIMING_DATA_READ_UI_SHIFT_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_TIMING_DATA_READ_UI_SHIFT_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_TIMING_DATA_READ_UI_SHIFT_SHIFT 8
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_TIMING_DATA_READ_UI_SHIFT_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_TIMING_EDC_READ_UI_SHIFT_MASK 0x70
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_TIMING_EDC_READ_UI_SHIFT_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_TIMING_EDC_READ_UI_SHIFT_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_TIMING_EDC_READ_UI_SHIFT_SHIFT 4
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_TIMING_EDC_READ_UI_SHIFT_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_TIMING_DATA_VALID_WR2RD_DELAY_DEC_MASK 0x8
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_TIMING_DATA_VALID_WR2RD_DELAY_DEC_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_TIMING_DATA_VALID_WR2RD_DELAY_DEC_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_TIMING_DATA_VALID_WR2RD_DELAY_DEC_SHIFT 3
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_TIMING_DATA_VALID_WR2RD_DELAY_DEC_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_TIMING_DATA_VALID_WR2RD_DELAY_INC_MASK 0x4
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_TIMING_DATA_VALID_WR2RD_DELAY_INC_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_TIMING_DATA_VALID_WR2RD_DELAY_INC_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_TIMING_DATA_VALID_WR2RD_DELAY_INC_SHIFT 2
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_TIMING_DATA_VALID_WR2RD_DELAY_INC_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_TIMING_EDC_VALID_WR2RD_DELAY_DEC_MASK 0x2
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_TIMING_EDC_VALID_WR2RD_DELAY_DEC_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_TIMING_EDC_VALID_WR2RD_DELAY_DEC_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_TIMING_EDC_VALID_WR2RD_DELAY_DEC_SHIFT 1
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_TIMING_EDC_VALID_WR2RD_DELAY_DEC_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_TIMING_EDC_VALID_WR2RD_DELAY_INC_MASK 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_TIMING_EDC_VALID_WR2RD_DELAY_INC_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_TIMING_EDC_VALID_WR2RD_DELAY_INC_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_TIMING_EDC_VALID_WR2RD_DELAY_INC_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_TIMING_EDC_VALID_WR2RD_DELAY_INC_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_TIMING_RESERVED_0_MASK 0xfff00000
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_TIMING_RESERVED_0_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_TIMING_RESERVED_0_BITS 12
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_TIMING_RESERVED_0_SHIFT 20
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_TIMING_RESERVED_MASK 0xfff00000
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_TIMING_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_TIMING_RESERVED_BITS 12
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_TIMING_RESERVED_SHIFT 20
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_TIMING_ALL_MASK 0xfffff
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_TIMING_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_TIMING_ALL_BITS 20
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_TIMING_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_TIMING_ALL_MASK 0xfffff
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_TIMING_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_TIMING_ALL_BITS 20
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_TIMING_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_TIMING_DATAMASK 0x000ff77f
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_TIMING_RDWRMASK 0xfff00880
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_CDR_TIMING_RESETVALUE 0x00000
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_FIFO_PTR 0x1023d0e0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_FIFO_PTR_BASE 0x0e0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_FIFO_PTR_RP_XMSB_MASK 0x20000
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_FIFO_PTR_RP_XMSB_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_FIFO_PTR_RP_XMSB_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_FIFO_PTR_RP_XMSB_SHIFT 17
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_FIFO_PTR_RP_XMSB_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_FIFO_PTR_RP_MASK 0x1f000
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_FIFO_PTR_RP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_FIFO_PTR_RP_BITS 5
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_FIFO_PTR_RP_SHIFT 12
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_FIFO_PTR_RP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_FIFO_PTR_WP1_XMSB_MASK 0x800
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_FIFO_PTR_WP1_XMSB_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_FIFO_PTR_WP1_XMSB_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_FIFO_PTR_WP1_XMSB_SHIFT 11
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_FIFO_PTR_WP1_XMSB_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_FIFO_PTR_WP1_MASK 0x7c0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_FIFO_PTR_WP1_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_FIFO_PTR_WP1_BITS 5
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_FIFO_PTR_WP1_SHIFT 6
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_FIFO_PTR_WP1_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_FIFO_PTR_WP0_XMSB_MASK 0x20
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_FIFO_PTR_WP0_XMSB_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_FIFO_PTR_WP0_XMSB_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_FIFO_PTR_WP0_XMSB_SHIFT 5
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_FIFO_PTR_WP0_XMSB_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_FIFO_PTR_WP0_MASK 0x1f
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_FIFO_PTR_WP0_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_FIFO_PTR_WP0_BITS 5
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_FIFO_PTR_WP0_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_FIFO_PTR_WP0_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_FIFO_PTR_RESERVED_MASK 0xfffc0000
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_FIFO_PTR_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_FIFO_PTR_RESERVED_BITS 14
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_FIFO_PTR_RESERVED_SHIFT 18
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_FIFO_PTR_ALL_MASK 0x3ffff
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_FIFO_PTR_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_FIFO_PTR_ALL_BITS 18
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_FIFO_PTR_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_FIFO_PTR_ALL_MASK 0x3ffff
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_FIFO_PTR_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_FIFO_PTR_ALL_BITS 18
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_FIFO_PTR_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_FIFO_PTR_DATAMASK 0x0003ffff
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_FIFO_PTR_RDWRMASK 0xfffc0000
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_FIFO_PTR_RESETVALUE 0x00000
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_FIFO_CTR 0x1023d0e4
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_FIFO_CTR_BASE 0x0e4
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_FIFO_CTR_MAX_WCOUNT_MASK 0x3f00
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_FIFO_CTR_MAX_WCOUNT_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_FIFO_CTR_MAX_WCOUNT_BITS 6
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_FIFO_CTR_MAX_WCOUNT_SHIFT 8
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_FIFO_CTR_MAX_WCOUNT_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_FIFO_CTR_CUR_WCOUNT_MASK 0xfc
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_FIFO_CTR_CUR_WCOUNT_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_FIFO_CTR_CUR_WCOUNT_BITS 6
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_FIFO_CTR_CUR_WCOUNT_SHIFT 2
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_FIFO_CTR_CUR_WCOUNT_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_FIFO_CTR_WFULL_MASK 0x2
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_FIFO_CTR_WFULL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_FIFO_CTR_WFULL_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_FIFO_CTR_WFULL_SHIFT 1
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_FIFO_CTR_WFULL_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_FIFO_CTR_WRITE_ERROR_MASK 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_FIFO_CTR_WRITE_ERROR_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_FIFO_CTR_WRITE_ERROR_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_FIFO_CTR_WRITE_ERROR_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_FIFO_CTR_WRITE_ERROR_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_FIFO_CTR_RESERVED_MASK 0xffffc000
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_FIFO_CTR_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_FIFO_CTR_RESERVED_BITS 18
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_FIFO_CTR_RESERVED_SHIFT 14
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_FIFO_CTR_ALL_MASK 0x3fff
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_FIFO_CTR_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_FIFO_CTR_ALL_BITS 14
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_FIFO_CTR_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_FIFO_CTR_ALL_MASK 0x3fff
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_FIFO_CTR_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_FIFO_CTR_ALL_BITS 14
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_FIFO_CTR_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_FIFO_CTR_DATAMASK 0x00003fff
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_FIFO_CTR_RDWRMASK 0xffffc000
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_FIFO_CTR_RESETVALUE 0x0000
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH 0x1023d0e8
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_BASE 0x0e8
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_PAST_STATE7_MASK 0x7000000
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_PAST_STATE7_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_PAST_STATE7_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_PAST_STATE7_SHIFT 24
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_PAST_STATE7_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_PAST_STATE6_MASK 0xe00000
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_PAST_STATE6_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_PAST_STATE6_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_PAST_STATE6_SHIFT 21
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_PAST_STATE6_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_PAST_STATE5_MASK 0x1c0000
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_PAST_STATE5_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_PAST_STATE5_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_PAST_STATE5_SHIFT 18
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_PAST_STATE5_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_PAST_STATE4_MASK 0x38000
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_PAST_STATE4_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_PAST_STATE4_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_PAST_STATE4_SHIFT 15
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_PAST_STATE4_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_PAST_STATE3_MASK 0x7000
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_PAST_STATE3_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_PAST_STATE3_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_PAST_STATE3_SHIFT 12
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_PAST_STATE3_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_PAST_STATE2_MASK 0xe00
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_PAST_STATE2_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_PAST_STATE2_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_PAST_STATE2_SHIFT 9
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_PAST_STATE2_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_PAST_STATE1_MASK 0x1c0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_PAST_STATE1_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_PAST_STATE1_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_PAST_STATE1_SHIFT 6
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_PAST_STATE1_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_PAST_STATE0_MASK 0x38
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_PAST_STATE0_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_PAST_STATE0_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_PAST_STATE0_SHIFT 3
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_PAST_STATE0_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_CUR_STATE_MASK 0x7
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_CUR_STATE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_CUR_STATE_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_CUR_STATE_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_CUR_STATE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_RESERVED_MASK 0xf8000000
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_RESERVED_BITS 5
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_RESERVED_SHIFT 27
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_ALL_MASK 0x7ffffff
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_ALL_BITS 27
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_ALL_MASK 0x7ffffff
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_ALL_BITS 27
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_DATAMASK 0x07ffffff
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_RDWRMASK 0xf8000000
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_RESETVALUE 0x0000000
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_ERR1 0x1023d0ec
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_ERR1_BASE 0x0ec
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_ERR1_RCMD_FIFO_RD_MASK 0x1000
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_ERR1_RCMD_FIFO_RD_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_ERR1_RCMD_FIFO_RD_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_ERR1_RCMD_FIFO_RD_SHIFT 12
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_ERR1_RCMD_FIFO_RD_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_ERR1_RCMD_FIFO_RDATA_MASK 0xff0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_ERR1_RCMD_FIFO_RDATA_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_ERR1_RCMD_FIFO_RDATA_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_ERR1_RCMD_FIFO_RDATA_SHIFT 4
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_ERR1_RCMD_FIFO_RDATA_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_ERR1_STATE_MASK 0xe
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_ERR1_STATE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_ERR1_STATE_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_ERR1_STATE_SHIFT 1
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_ERR1_STATE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_ERR1_ERROR_MASK 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_ERR1_ERROR_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_ERR1_ERROR_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_ERR1_ERROR_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_ERR1_ERROR_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_ERR1_RESERVED_MASK 0xffffe000
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_ERR1_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_ERR1_RESERVED_BITS 19
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_ERR1_RESERVED_SHIFT 13
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_ERR1_ALL_MASK 0x1fff
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_ERR1_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_ERR1_ALL_BITS 13
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_ERR1_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_ERR1_ALL_MASK 0x1fff
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_ERR1_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_ERR1_ALL_BITS 13
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_ERR1_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_ERR1_DATAMASK 0x00001fff
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_ERR1_RDWRMASK 0xffffe000
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_ERR1_RESETVALUE 0x0000
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_ERR2 0x1023d0f0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_ERR2_BASE 0x0f0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_ERR2_RCMD_FIFO_RD_MASK 0x1000
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_ERR2_RCMD_FIFO_RD_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_ERR2_RCMD_FIFO_RD_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_ERR2_RCMD_FIFO_RD_SHIFT 12
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_ERR2_RCMD_FIFO_RD_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_ERR2_RCMD_FIFO_RDATA_MASK 0xff0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_ERR2_RCMD_FIFO_RDATA_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_ERR2_RCMD_FIFO_RDATA_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_ERR2_RCMD_FIFO_RDATA_SHIFT 4
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_ERR2_RCMD_FIFO_RDATA_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_ERR2_STATE_MASK 0xe
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_ERR2_STATE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_ERR2_STATE_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_ERR2_STATE_SHIFT 1
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_ERR2_STATE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_ERR2_ERROR_MASK 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_ERR2_ERROR_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_ERR2_ERROR_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_ERR2_ERROR_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_ERR2_ERROR_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_ERR2_RESERVED_MASK 0xffffe000
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_ERR2_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_ERR2_RESERVED_BITS 19
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_ERR2_RESERVED_SHIFT 13
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_ERR2_ALL_MASK 0x1fff
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_ERR2_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_ERR2_ALL_BITS 13
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_ERR2_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_ERR2_ALL_MASK 0x1fff
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_ERR2_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_ERR2_ALL_BITS 13
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_ERR2_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_ERR2_DATAMASK 0x00001fff
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_ERR2_RDWRMASK 0xffffe000
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_ERR2_RESETVALUE 0x0000
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_ERR3 0x1023d0f4
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_ERR3_BASE 0x0f4
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_ERR3_EXP_RCMD_ID_MASK 0xfc00
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_ERR3_EXP_RCMD_ID_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_ERR3_EXP_RCMD_ID_BITS 6
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_ERR3_EXP_RCMD_ID_SHIFT 10
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_ERR3_EXP_RCMD_ID_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_ERR3_OBS_RCMD_ID_MASK 0x3f0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_ERR3_OBS_RCMD_ID_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_ERR3_OBS_RCMD_ID_BITS 6
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_ERR3_OBS_RCMD_ID_SHIFT 4
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_ERR3_OBS_RCMD_ID_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_ERR3_STATE_MASK 0xe
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_ERR3_STATE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_ERR3_STATE_BITS 3
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_ERR3_STATE_SHIFT 1
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_ERR3_STATE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_ERR3_ERROR_MASK 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_ERR3_ERROR_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_ERR3_ERROR_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_ERR3_ERROR_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_ERR3_ERROR_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_ERR3_RESERVED_MASK 0xffff0000
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_ERR3_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_ERR3_RESERVED_BITS 16
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_ERR3_RESERVED_SHIFT 16
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_ERR3_ALL_MASK 0xffff
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_ERR3_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_ERR3_ALL_BITS 16
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_ERR3_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_ERR3_ALL_MASK 0xffff
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_ERR3_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_ERR3_ALL_BITS 16
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_ERR3_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_ERR3_DATAMASK 0x0000ffff
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_ERR3_RDWRMASK 0xffff0000
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_ERR3_RESETVALUE 0x0000
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_RCMD_ID 0x1023d0f8
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_RCMD_ID_BASE 0x0f8
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_RCMD_ID_ID8_MASK 0xfc0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_RCMD_ID_ID8_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_RCMD_ID_ID8_BITS 6
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_RCMD_ID_ID8_SHIFT 6
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_RCMD_ID_ID8_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_RCMD_ID_ID4_MASK 0x3f
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_RCMD_ID_ID4_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_RCMD_ID_ID4_BITS 6
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_RCMD_ID_ID4_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_RCMD_ID_ID4_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_RCMD_ID_RESERVED_MASK 0xfffff000
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_RCMD_ID_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_RCMD_ID_RESERVED_BITS 20
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_RCMD_ID_RESERVED_SHIFT 12
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_RCMD_ID_ALL_MASK 0xfff
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_RCMD_ID_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_RCMD_ID_ALL_BITS 12
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_RCMD_ID_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_RCMD_ID_ALL_MASK 0xfff
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_RCMD_ID_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_RCMD_ID_ALL_BITS 12
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_RCMD_ID_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_RCMD_ID_DATAMASK 0x00000fff
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_RCMD_ID_RDWRMASK 0xfffff000
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_RCMD_ID_RESETVALUE 0x000
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RDATA_FIFO 0x1023d0fc
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RDATA_FIFO_BASE 0x0fc
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RDATA_FIFO_RP1_XMSB_MASK 0x4000
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RDATA_FIFO_RP1_XMSB_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RDATA_FIFO_RP1_XMSB_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RDATA_FIFO_RP1_XMSB_SHIFT 14
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RDATA_FIFO_RP1_XMSB_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RDATA_FIFO_RP1_MASK 0x3c00
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RDATA_FIFO_RP1_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RDATA_FIFO_RP1_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RDATA_FIFO_RP1_SHIFT 10
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RDATA_FIFO_RP1_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RDATA_FIFO_RP0_XMSB_MASK 0x200
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RDATA_FIFO_RP0_XMSB_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RDATA_FIFO_RP0_XMSB_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RDATA_FIFO_RP0_XMSB_SHIFT 9
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RDATA_FIFO_RP0_XMSB_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RDATA_FIFO_RP0_MASK 0x1e0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RDATA_FIFO_RP0_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RDATA_FIFO_RP0_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RDATA_FIFO_RP0_SHIFT 5
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RDATA_FIFO_RP0_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RDATA_FIFO_WP_XMSB_MASK 0x10
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RDATA_FIFO_WP_XMSB_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RDATA_FIFO_WP_XMSB_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RDATA_FIFO_WP_XMSB_SHIFT 4
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RDATA_FIFO_WP_XMSB_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RDATA_FIFO_WP_MASK 0xf
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RDATA_FIFO_WP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RDATA_FIFO_WP_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RDATA_FIFO_WP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RDATA_FIFO_WP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RDATA_FIFO_RESERVED_MASK 0xffff8000
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RDATA_FIFO_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RDATA_FIFO_RESERVED_BITS 17
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RDATA_FIFO_RESERVED_SHIFT 15
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RDATA_FIFO_ALL_MASK 0x7fff
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RDATA_FIFO_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RDATA_FIFO_ALL_BITS 15
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RDATA_FIFO_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RDATA_FIFO_ALL_MASK 0x7fff
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RDATA_FIFO_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RDATA_FIFO_ALL_BITS 15
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RDATA_FIFO_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RDATA_FIFO_DATAMASK 0x00007fff
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RDATA_FIFO_RDWRMASK 0xffff8000
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RDATA_FIFO_RESETVALUE 0x0000
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_FIFO 0x1023d100
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_FIFO_BASE 0x100
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_FIFO_RP_2G_XMSB_MASK 0x20000
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_FIFO_RP_2G_XMSB_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_FIFO_RP_2G_XMSB_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_FIFO_RP_2G_XMSB_SHIFT 17
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_FIFO_RP_2G_XMSB_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_FIFO_RP_2G_MASK 0x1f000
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_FIFO_RP_2G_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_FIFO_RP_2G_BITS 5
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_FIFO_RP_2G_SHIFT 12
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_FIFO_RP_2G_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_FIFO_RP_1G_XMSB_MASK 0x800
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_FIFO_RP_1G_XMSB_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_FIFO_RP_1G_XMSB_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_FIFO_RP_1G_XMSB_SHIFT 11
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_FIFO_RP_1G_XMSB_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_FIFO_RP_1G_MASK 0x7c0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_FIFO_RP_1G_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_FIFO_RP_1G_BITS 5
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_FIFO_RP_1G_SHIFT 6
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_FIFO_RP_1G_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_FIFO_WP_XMSB_MASK 0x20
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_FIFO_WP_XMSB_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_FIFO_WP_XMSB_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_FIFO_WP_XMSB_SHIFT 5
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_FIFO_WP_XMSB_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_FIFO_WP_MASK 0x1f
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_FIFO_WP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_FIFO_WP_BITS 5
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_FIFO_WP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_FIFO_WP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_FIFO_RESERVED_MASK 0xfffc0000
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_FIFO_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_FIFO_RESERVED_BITS 14
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_FIFO_RESERVED_SHIFT 18
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_FIFO_ALL_MASK 0x3ffff
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_FIFO_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_FIFO_ALL_BITS 18
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_FIFO_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_FIFO_ALL_MASK 0x3ffff
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_FIFO_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_FIFO_ALL_BITS 18
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_FIFO_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_FIFO_DATAMASK 0x0003ffff
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_FIFO_RDWRMASK 0xfffc0000
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_FIFO_RESETVALUE 0x00000
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_RCMD_ID 0x1023d104
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_RCMD_ID_BASE 0x104
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_RCMD_ID_ID8_MASK 0xfc0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_RCMD_ID_ID8_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_RCMD_ID_ID8_BITS 6
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_RCMD_ID_ID8_SHIFT 6
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_RCMD_ID_ID8_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_RCMD_ID_ID4_MASK 0x3f
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_RCMD_ID_ID4_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_RCMD_ID_ID4_BITS 6
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_RCMD_ID_ID4_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_RCMD_ID_ID4_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_RCMD_ID_RESERVED_MASK 0xfffff000
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_RCMD_ID_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_RCMD_ID_RESERVED_BITS 20
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_RCMD_ID_RESERVED_SHIFT 12
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_RCMD_ID_ALL_MASK 0xfff
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_RCMD_ID_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_RCMD_ID_ALL_BITS 12
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_RCMD_ID_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_RCMD_ID_ALL_MASK 0xfff
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_RCMD_ID_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_RCMD_ID_ALL_BITS 12
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_RCMD_ID_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_RCMD_ID_DATAMASK 0x00000fff
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_RCMD_ID_RDWRMASK 0xfffff000
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_RCMD_ID_RESETVALUE 0x000
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_ERR1 0x1023d108
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_ERR1_BASE 0x108
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_ERR1_NXT_RCMD_FIFO_WDATA1_MASK 0x7f800000
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_ERR1_NXT_RCMD_FIFO_WDATA1_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_ERR1_NXT_RCMD_FIFO_WDATA1_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_ERR1_NXT_RCMD_FIFO_WDATA1_SHIFT 23
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_ERR1_NXT_RCMD_FIFO_WDATA1_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_ERR1_NXT_RCMD_FIFO_WDATA0_MASK 0x7f8000
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_ERR1_NXT_RCMD_FIFO_WDATA0_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_ERR1_NXT_RCMD_FIFO_WDATA0_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_ERR1_NXT_RCMD_FIFO_WDATA0_SHIFT 15
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_ERR1_NXT_RCMD_FIFO_WDATA0_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_ERR1_NXT_RCMD_FIFO_WR1_MASK 0x4000
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_ERR1_NXT_RCMD_FIFO_WR1_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_ERR1_NXT_RCMD_FIFO_WR1_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_ERR1_NXT_RCMD_FIFO_WR1_SHIFT 14
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_ERR1_NXT_RCMD_FIFO_WR1_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_ERR1_NXT_RCMD_FIFO_WR0_MASK 0x2000
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_ERR1_NXT_RCMD_FIFO_WR0_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_ERR1_NXT_RCMD_FIFO_WR0_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_ERR1_NXT_RCMD_FIFO_WR0_SHIFT 13
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_ERR1_NXT_RCMD_FIFO_WR0_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_ERR1_NXT_RD_EN_UI23_MASK 0x1000
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_ERR1_NXT_RD_EN_UI23_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_ERR1_NXT_RD_EN_UI23_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_ERR1_NXT_RD_EN_UI23_SHIFT 12
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_ERR1_NXT_RD_EN_UI23_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_ERR1_NXT_RD_EN_UI01_MASK 0x800
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_ERR1_NXT_RD_EN_UI01_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_ERR1_NXT_RD_EN_UI01_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_ERR1_NXT_RD_EN_UI01_SHIFT 11
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_ERR1_NXT_RD_EN_UI01_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_ERR1_NXT_STATE_MASK 0x600
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_ERR1_NXT_STATE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_ERR1_NXT_STATE_BITS 2
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_ERR1_NXT_STATE_SHIFT 9
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_ERR1_NXT_STATE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_ERR1_RCMD_PAIR_MASK 0x1e0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_ERR1_RCMD_PAIR_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_ERR1_RCMD_PAIR_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_ERR1_RCMD_PAIR_SHIFT 5
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_ERR1_RCMD_PAIR_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_ERR1_RD_EN_UI23_MASK 0x10
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_ERR1_RD_EN_UI23_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_ERR1_RD_EN_UI23_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_ERR1_RD_EN_UI23_SHIFT 4
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_ERR1_RD_EN_UI23_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_ERR1_RD_EN_UI01_MASK 0x8
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_ERR1_RD_EN_UI01_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_ERR1_RD_EN_UI01_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_ERR1_RD_EN_UI01_SHIFT 3
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_ERR1_RD_EN_UI01_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_ERR1_STATE_MASK 0x6
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_ERR1_STATE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_ERR1_STATE_BITS 2
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_ERR1_STATE_SHIFT 1
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_ERR1_STATE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_ERR1_ERROR_MASK 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_ERR1_ERROR_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_ERR1_ERROR_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_ERR1_ERROR_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_ERR1_ERROR_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_ERR1_ALL_MASK 0x7fffffff
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_ERR1_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_ERR1_ALL_BITS 31
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_ERR1_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_ERR1_ALL_MASK 0x7fffffff
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_ERR1_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_ERR1_ALL_BITS 31
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_ERR1_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_ERR1_DATAMASK 0x7fffffff
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_ERR1_RDWRMASK 0x80000000
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_ERR1_RESETVALUE 0x00000000
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_ERR2 0x1023d10c
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_ERR2_BASE 0x10c
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_ERR2_NXT_RCMD_FIFO_WDATA1_MASK 0x7f800000
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_ERR2_NXT_RCMD_FIFO_WDATA1_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_ERR2_NXT_RCMD_FIFO_WDATA1_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_ERR2_NXT_RCMD_FIFO_WDATA1_SHIFT 23
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_ERR2_NXT_RCMD_FIFO_WDATA1_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_ERR2_NXT_RCMD_FIFO_WDATA0_MASK 0x7f8000
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_ERR2_NXT_RCMD_FIFO_WDATA0_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_ERR2_NXT_RCMD_FIFO_WDATA0_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_ERR2_NXT_RCMD_FIFO_WDATA0_SHIFT 15
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_ERR2_NXT_RCMD_FIFO_WDATA0_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_ERR2_NXT_RCMD_FIFO_WR1_MASK 0x4000
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_ERR2_NXT_RCMD_FIFO_WR1_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_ERR2_NXT_RCMD_FIFO_WR1_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_ERR2_NXT_RCMD_FIFO_WR1_SHIFT 14
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_ERR2_NXT_RCMD_FIFO_WR1_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_ERR2_NXT_RCMD_FIFO_WR0_MASK 0x2000
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_ERR2_NXT_RCMD_FIFO_WR0_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_ERR2_NXT_RCMD_FIFO_WR0_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_ERR2_NXT_RCMD_FIFO_WR0_SHIFT 13
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_ERR2_NXT_RCMD_FIFO_WR0_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_ERR2_NXT_RD_EN_UI23_MASK 0x1000
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_ERR2_NXT_RD_EN_UI23_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_ERR2_NXT_RD_EN_UI23_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_ERR2_NXT_RD_EN_UI23_SHIFT 12
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_ERR2_NXT_RD_EN_UI23_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_ERR2_NXT_RD_EN_UI01_MASK 0x800
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_ERR2_NXT_RD_EN_UI01_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_ERR2_NXT_RD_EN_UI01_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_ERR2_NXT_RD_EN_UI01_SHIFT 11
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_ERR2_NXT_RD_EN_UI01_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_ERR2_NXT_STATE_MASK 0x600
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_ERR2_NXT_STATE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_ERR2_NXT_STATE_BITS 2
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_ERR2_NXT_STATE_SHIFT 9
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_ERR2_NXT_STATE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_ERR2_RCMD_PAIR_MASK 0x1e0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_ERR2_RCMD_PAIR_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_ERR2_RCMD_PAIR_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_ERR2_RCMD_PAIR_SHIFT 5
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_ERR2_RCMD_PAIR_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_ERR2_RD_EN_UI23_MASK 0x10
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_ERR2_RD_EN_UI23_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_ERR2_RD_EN_UI23_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_ERR2_RD_EN_UI23_SHIFT 4
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_ERR2_RD_EN_UI23_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_ERR2_RD_EN_UI01_MASK 0x8
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_ERR2_RD_EN_UI01_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_ERR2_RD_EN_UI01_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_ERR2_RD_EN_UI01_SHIFT 3
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_ERR2_RD_EN_UI01_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_ERR2_STATE_MASK 0x6
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_ERR2_STATE_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_ERR2_STATE_BITS 2
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_ERR2_STATE_SHIFT 1
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_ERR2_STATE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_ERR2_ERROR_MASK 0x1
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_ERR2_ERROR_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_ERR2_ERROR_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_ERR2_ERROR_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_ERR2_ERROR_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_ERR2_ALL_MASK 0x7fffffff
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_ERR2_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_ERR2_ALL_BITS 31
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_ERR2_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_ERR2_ALL_MASK 0x7fffffff
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_ERR2_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_ERR2_ALL_BITS 31
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_ERR2_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_ERR2_DATAMASK 0x7fffffff
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_ERR2_RDWRMASK 0x80000000
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_ERR2_RESETVALUE 0x00000000
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_FIFO_POINTERS 0x1023d110
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_FIFO_POINTERS_BASE 0x110
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_FIFO_POINTERS_RDATA_RP_MASK 0xf00000
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_FIFO_POINTERS_RDATA_RP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_FIFO_POINTERS_RDATA_RP_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_FIFO_POINTERS_RDATA_RP_SHIFT 20
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_FIFO_POINTERS_RDATA_RP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_FIFO_POINTERS_RDATA_WP_MASK 0xf0000
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_FIFO_POINTERS_RDATA_WP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_FIFO_POINTERS_RDATA_WP_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_FIFO_POINTERS_RDATA_WP_SHIFT 16
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_FIFO_POINTERS_RDATA_WP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_FIFO_POINTERS_EDC_VALID_RP_MASK 0xf000
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_FIFO_POINTERS_EDC_VALID_RP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_FIFO_POINTERS_EDC_VALID_RP_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_FIFO_POINTERS_EDC_VALID_RP_SHIFT 12
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_FIFO_POINTERS_EDC_VALID_RP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_FIFO_POINTERS_EDC_VALID_WP_MASK 0xf00
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_FIFO_POINTERS_EDC_VALID_WP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_FIFO_POINTERS_EDC_VALID_WP_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_FIFO_POINTERS_EDC_VALID_WP_SHIFT 8
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_FIFO_POINTERS_EDC_VALID_WP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_FIFO_POINTERS_DATA_VALID_RP_MASK 0xf0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_FIFO_POINTERS_DATA_VALID_RP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_FIFO_POINTERS_DATA_VALID_RP_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_FIFO_POINTERS_DATA_VALID_RP_SHIFT 4
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_FIFO_POINTERS_DATA_VALID_RP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_FIFO_POINTERS_DATA_VALID_WP_MASK 0xf
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_FIFO_POINTERS_DATA_VALID_WP_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_FIFO_POINTERS_DATA_VALID_WP_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_FIFO_POINTERS_DATA_VALID_WP_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_FIFO_POINTERS_DATA_VALID_WP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_FIFO_POINTERS_RESERVED_MASK 0xff000000
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_FIFO_POINTERS_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_FIFO_POINTERS_RESERVED_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_FIFO_POINTERS_RESERVED_SHIFT 24
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_FIFO_POINTERS_ALL_MASK 0xffffff
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_FIFO_POINTERS_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_FIFO_POINTERS_ALL_BITS 24
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_FIFO_POINTERS_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_FIFO_POINTERS_ALL_MASK 0xffffff
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_FIFO_POINTERS_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_FIFO_POINTERS_ALL_BITS 24
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_FIFO_POINTERS_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_FIFO_POINTERS_DATAMASK 0x00ffffff
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_FIFO_POINTERS_RDWRMASK 0xff000000
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_FIFO_POINTERS_RESETVALUE 0x000000
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB 0x1023d114
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_BASE 0x114
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_RCMD_4_MASK 0xff000000
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_RCMD_4_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_RCMD_4_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_RCMD_4_SHIFT 24
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_RCMD_4_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_RCMD_3_MASK 0xff0000
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_RCMD_3_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_RCMD_3_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_RCMD_3_SHIFT 16
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_RCMD_3_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_RCMD_2_MASK 0xff00
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_RCMD_2_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_RCMD_2_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_RCMD_2_SHIFT 8
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_RCMD_2_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_RCMD_1_MASK 0xff
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_RCMD_1_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_RCMD_1_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_RCMD_1_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_RCMD_1_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_ALL_MASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_ALL_BITS 32
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_ALL_MASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_ALL_BITS 32
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_DATAMASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_RDWRMASK 0x00000000
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB_RESETVALUE 0x00000000
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB 0x1023d118
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_BASE 0x118
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_RCMD_8_MASK 0xff000000
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_RCMD_8_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_RCMD_8_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_RCMD_8_SHIFT 24
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_RCMD_8_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_RCMD_7_MASK 0xff0000
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_RCMD_7_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_RCMD_7_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_RCMD_7_SHIFT 16
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_RCMD_7_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_RCMD_6_MASK 0xff00
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_RCMD_6_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_RCMD_6_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_RCMD_6_SHIFT 8
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_RCMD_6_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_RCMD_5_MASK 0xff
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_RCMD_5_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_RCMD_5_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_RCMD_5_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_RCMD_5_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_ALL_MASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_ALL_BITS 32
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_ALL_MASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_ALL_BITS 32
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_DATAMASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_RDWRMASK 0x00000000
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB_RESETVALUE 0x00000000
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES 0x1023d11c
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_BASE 0x11c
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_7_MASK 0xf0000000
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_7_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_7_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_7_SHIFT 28
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_7_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_6_MASK 0xf000000
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_6_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_6_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_6_SHIFT 24
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_6_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_5_MASK 0xf00000
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_5_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_5_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_5_SHIFT 20
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_5_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_4_MASK 0xf0000
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_4_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_4_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_4_SHIFT 16
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_4_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_3_MASK 0xf000
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_3_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_3_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_3_SHIFT 12
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_3_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_2_MASK 0xf00
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_2_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_2_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_2_SHIFT 8
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_2_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_1_MASK 0xf0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_1_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_1_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_1_SHIFT 4
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_1_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_0_MASK 0xf
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_0_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_0_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_0_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_STATE_0_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_ALL_MASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_ALL_BITS 32
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_ALL_MASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_ALL_BITS 32
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_DATAMASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_RDWRMASK 0x00000000
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES_RESETVALUE 0x00000000
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS 0x1023d120
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_BASE 0x120
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_7_MASK 0xf0000000
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_7_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_7_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_7_SHIFT 28
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_7_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_6_MASK 0xf000000
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_6_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_6_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_6_SHIFT 24
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_6_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_5_MASK 0xf00000
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_5_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_5_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_5_SHIFT 20
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_5_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_4_MASK 0xf0000
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_4_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_4_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_4_SHIFT 16
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_4_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_3_MASK 0xf000
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_3_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_3_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_3_SHIFT 12
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_3_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_2_MASK 0xf00
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_2_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_2_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_2_SHIFT 8
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_2_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_1_MASK 0xf0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_1_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_1_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_1_SHIFT 4
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_1_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_0_MASK 0xf
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_0_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_0_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_0_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_VALID_0_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_ALL_MASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_ALL_BITS 32
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_ALL_MASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_ALL_BITS 32
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_DATAMASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_RDWRMASK 0x00000000
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS_RESETVALUE 0x00000000
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR 0x1023d124
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_BASE 0x124
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STICKY_ERROR_MASK 0xf0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STICKY_ERROR_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STICKY_ERROR_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STICKY_ERROR_SHIFT 4
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STICKY_ERROR_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_CURRENT_ERROR_MASK 0xf
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_CURRENT_ERROR_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_CURRENT_ERROR_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_CURRENT_ERROR_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_CURRENT_ERROR_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RESERVED_MASK 0xffffff00
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RESERVED_BITS 24
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RESERVED_SHIFT 8
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_ALL_MASK 0xff
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_ALL_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_ALL_MASK 0xff
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_ALL_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_DATAMASK 0x000000ff
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RDWRMASK 0xffffff00
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB 0x1023d128
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_BASE 0x128
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_RCMD_4_MASK 0xff000000
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_RCMD_4_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_RCMD_4_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_RCMD_4_SHIFT 24
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_RCMD_4_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_RCMD_3_MASK 0xff0000
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_RCMD_3_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_RCMD_3_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_RCMD_3_SHIFT 16
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_RCMD_3_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_RCMD_2_MASK 0xff00
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_RCMD_2_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_RCMD_2_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_RCMD_2_SHIFT 8
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_RCMD_2_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_RCMD_1_MASK 0xff
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_RCMD_1_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_RCMD_1_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_RCMD_1_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_RCMD_1_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_ALL_MASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_ALL_BITS 32
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_ALL_MASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_ALL_BITS 32
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_DATAMASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_RDWRMASK 0x00000000
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB_RESETVALUE 0x00000000
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB 0x1023d12c
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_BASE 0x12c
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_RCMD_8_MASK 0xff000000
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_RCMD_8_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_RCMD_8_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_RCMD_8_SHIFT 24
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_RCMD_8_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_RCMD_7_MASK 0xff0000
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_RCMD_7_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_RCMD_7_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_RCMD_7_SHIFT 16
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_RCMD_7_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_RCMD_6_MASK 0xff00
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_RCMD_6_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_RCMD_6_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_RCMD_6_SHIFT 8
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_RCMD_6_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_RCMD_5_MASK 0xff
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_RCMD_5_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_RCMD_5_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_RCMD_5_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_RCMD_5_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_ALL_MASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_ALL_BITS 32
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_ALL_MASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_ALL_BITS 32
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_DATAMASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_RDWRMASK 0x00000000
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB_RESETVALUE 0x00000000
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES 0x1023d130
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_BASE 0x130
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_7_MASK 0xf0000000
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_7_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_7_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_7_SHIFT 28
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_7_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_6_MASK 0xf000000
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_6_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_6_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_6_SHIFT 24
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_6_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_5_MASK 0xf00000
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_5_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_5_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_5_SHIFT 20
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_5_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_4_MASK 0xf0000
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_4_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_4_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_4_SHIFT 16
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_4_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_3_MASK 0xf000
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_3_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_3_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_3_SHIFT 12
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_3_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_2_MASK 0xf00
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_2_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_2_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_2_SHIFT 8
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_2_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_1_MASK 0xf0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_1_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_1_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_1_SHIFT 4
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_1_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_0_MASK 0xf
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_0_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_0_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_0_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_STATE_0_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_ALL_MASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_ALL_BITS 32
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_ALL_MASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_ALL_BITS 32
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_DATAMASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_RDWRMASK 0x00000000
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES_RESETVALUE 0x00000000
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS 0x1023d134
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_BASE 0x134
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_7_MASK 0xf0000000
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_7_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_7_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_7_SHIFT 28
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_7_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_6_MASK 0xf000000
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_6_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_6_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_6_SHIFT 24
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_6_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_5_MASK 0xf00000
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_5_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_5_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_5_SHIFT 20
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_5_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_4_MASK 0xf0000
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_4_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_4_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_4_SHIFT 16
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_4_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_3_MASK 0xf000
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_3_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_3_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_3_SHIFT 12
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_3_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_2_MASK 0xf00
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_2_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_2_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_2_SHIFT 8
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_2_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_1_MASK 0xf0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_1_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_1_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_1_SHIFT 4
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_1_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_0_MASK 0xf
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_0_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_0_BITS 4
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_0_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_VALID_0_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_ALL_MASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_ALL_BITS 32
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_ALL_MASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_ALL_BITS 32
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_DATAMASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_RDWRMASK 0x00000000
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS_RESETVALUE 0x00000000
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_WRITE_LEVELING 0x1023d138
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_WRITE_LEVELING_BASE 0x138
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_WRITE_LEVELING_DQS_MASK 0x400
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_WRITE_LEVELING_DQS_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_WRITE_LEVELING_DQS_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_WRITE_LEVELING_DQS_SHIFT 10
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_WRITE_LEVELING_DQS_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_WRITE_LEVELING_EDC_MASK 0x200
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_WRITE_LEVELING_EDC_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_WRITE_LEVELING_EDC_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_WRITE_LEVELING_EDC_SHIFT 9
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_WRITE_LEVELING_EDC_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_WRITE_LEVELING_DBI_MASK 0x100
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_WRITE_LEVELING_DBI_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_WRITE_LEVELING_DBI_BITS 1
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_WRITE_LEVELING_DBI_SHIFT 8
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_WRITE_LEVELING_DBI_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_WRITE_LEVELING_DATA_MASK 0xff
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_WRITE_LEVELING_DATA_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_WRITE_LEVELING_DATA_BITS 8
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_WRITE_LEVELING_DATA_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_WRITE_LEVELING_DATA_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_WRITE_LEVELING_RESERVED_MASK 0xfffff800
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_WRITE_LEVELING_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_WRITE_LEVELING_RESERVED_BITS 21
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_WRITE_LEVELING_RESERVED_SHIFT 11
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_WRITE_LEVELING_ALL_MASK 0x7ff
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_WRITE_LEVELING_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_WRITE_LEVELING_ALL_BITS 11
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_WRITE_LEVELING_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_WRITE_LEVELING_ALL_MASK 0x7ff
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_WRITE_LEVELING_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_WRITE_LEVELING_ALL_BITS 11
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_WRITE_LEVELING_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_WRITE_LEVELING_DATAMASK 0x000007ff
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_WRITE_LEVELING_RDWRMASK 0xfffff800
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_WRITE_LEVELING_RESETVALUE 0x000
 #define SJC16_DDR4_PHY_DQ_BYTE4_MACRO_RESERVED_REG 0x1023d13c
 #define SJC16_DDR4_PHY_DQ_BYTE4_MACRO_RESERVED_REG_BASE 0x13c
 #define SJC16_DDR4_PHY_DQ_BYTE4_MACRO_RESERVED_REG_RESERVED_MASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE4_MACRO_RESERVED_REG_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_MACRO_RESERVED_REG_RESERVED_BITS 32
 #define SJC16_DDR4_PHY_DQ_BYTE4_MACRO_RESERVED_REG_RESERVED_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_MACRO_RESERVED_REG_RESERVED_RESETVALUE 0x00000000
 #define SJC16_DDR4_PHY_DQ_BYTE4_MACRO_RESERVED_REG_ALL_MASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE4_MACRO_RESERVED_REG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_MACRO_RESERVED_REG_ALL_BITS 32
 #define SJC16_DDR4_PHY_DQ_BYTE4_MACRO_RESERVED_REG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_MACRO_RESERVED_REG_ALL_MASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE4_MACRO_RESERVED_REG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_MACRO_RESERVED_REG_ALL_BITS 32
 #define SJC16_DDR4_PHY_DQ_BYTE4_MACRO_RESERVED_REG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_MACRO_RESERVED_REG_DATAMASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE4_MACRO_RESERVED_REG_RDWRMASK 0x00000000
 #define SJC16_DDR4_PHY_DQ_BYTE4_MACRO_RESERVED_REG_RESETVALUE 0x00000000
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_MACRO_RESERVED 0x1023d140
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_MACRO_RESERVED_BASE 0x140
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_MACRO_RESERVED_RESERVED_MASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_MACRO_RESERVED_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_MACRO_RESERVED_RESERVED_BITS 32
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_MACRO_RESERVED_RESERVED_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_MACRO_RESERVED_RESERVED_RESETVALUE 0x00000000
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_MACRO_RESERVED_ALL_MASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_MACRO_RESERVED_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_MACRO_RESERVED_ALL_BITS 32
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_MACRO_RESERVED_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_MACRO_RESERVED_ALL_MASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_MACRO_RESERVED_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_MACRO_RESERVED_ALL_BITS 32
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_MACRO_RESERVED_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_MACRO_RESERVED_DATAMASK 0xffffffff
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_MACRO_RESERVED_RDWRMASK 0x00000000
 #define SJC16_DDR4_PHY_DQ_BYTE4_STATUS_MACRO_RESERVED_RESETVALUE 0x00000000
 #define SJC16_DDR4_PHY_SUPPLEMENT_IO_CONFIG 0x1023f000
 #define SJC16_DDR4_PHY_SUPPLEMENT_IO_CONFIG_BASE 0x000
 #define SJC16_DDR4_PHY_SUPPLEMENT_IO_CONFIG_RXENB_ALERT_N_4_MASK 0x80000000
 #define SJC16_DDR4_PHY_SUPPLEMENT_IO_CONFIG_RXENB_ALERT_N_4_ALIGN 0
 #define SJC16_DDR4_PHY_SUPPLEMENT_IO_CONFIG_RXENB_ALERT_N_4_BITS 1
 #define SJC16_DDR4_PHY_SUPPLEMENT_IO_CONFIG_RXENB_ALERT_N_4_SHIFT 31
 #define SJC16_DDR4_PHY_SUPPLEMENT_IO_CONFIG_RXENB_ALERT_N_4_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_SUPPLEMENT_IO_CONFIG_RXENB_ALERT_N_3_MASK 0x40000000
 #define SJC16_DDR4_PHY_SUPPLEMENT_IO_CONFIG_RXENB_ALERT_N_3_ALIGN 0
 #define SJC16_DDR4_PHY_SUPPLEMENT_IO_CONFIG_RXENB_ALERT_N_3_BITS 1
 #define SJC16_DDR4_PHY_SUPPLEMENT_IO_CONFIG_RXENB_ALERT_N_3_SHIFT 30
 #define SJC16_DDR4_PHY_SUPPLEMENT_IO_CONFIG_RXENB_ALERT_N_3_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_SUPPLEMENT_IO_CONFIG_RXENB_ALERT_N_2_MASK 0x20000000
 #define SJC16_DDR4_PHY_SUPPLEMENT_IO_CONFIG_RXENB_ALERT_N_2_ALIGN 0
 #define SJC16_DDR4_PHY_SUPPLEMENT_IO_CONFIG_RXENB_ALERT_N_2_BITS 1
 #define SJC16_DDR4_PHY_SUPPLEMENT_IO_CONFIG_RXENB_ALERT_N_2_SHIFT 29
 #define SJC16_DDR4_PHY_SUPPLEMENT_IO_CONFIG_RXENB_ALERT_N_2_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_SUPPLEMENT_IO_CONFIG_PTERM_MASK 0x1f000000
 #define SJC16_DDR4_PHY_SUPPLEMENT_IO_CONFIG_PTERM_ALIGN 0
 #define SJC16_DDR4_PHY_SUPPLEMENT_IO_CONFIG_PTERM_BITS 5
 #define SJC16_DDR4_PHY_SUPPLEMENT_IO_CONFIG_PTERM_SHIFT 24
 #define SJC16_DDR4_PHY_SUPPLEMENT_IO_CONFIG_PTERM_RESETVALUE 0x10
 #define SJC16_DDR4_PHY_SUPPLEMENT_IO_CONFIG_NTERM_MASK 0xf80000
 #define SJC16_DDR4_PHY_SUPPLEMENT_IO_CONFIG_NTERM_ALIGN 0
 #define SJC16_DDR4_PHY_SUPPLEMENT_IO_CONFIG_NTERM_BITS 5
 #define SJC16_DDR4_PHY_SUPPLEMENT_IO_CONFIG_NTERM_SHIFT 19
 #define SJC16_DDR4_PHY_SUPPLEMENT_IO_CONFIG_NTERM_RESETVALUE 0xf
 #define SJC16_DDR4_PHY_SUPPLEMENT_IO_CONFIG_PULL_UP_OFF_B_MASK 0x20000
 #define SJC16_DDR4_PHY_SUPPLEMENT_IO_CONFIG_PULL_UP_OFF_B_ALIGN 0
 #define SJC16_DDR4_PHY_SUPPLEMENT_IO_CONFIG_PULL_UP_OFF_B_BITS 1
 #define SJC16_DDR4_PHY_SUPPLEMENT_IO_CONFIG_PULL_UP_OFF_B_SHIFT 17
 #define SJC16_DDR4_PHY_SUPPLEMENT_IO_CONFIG_PULL_UP_OFF_B_RESETVALUE 0x1
 #define SJC16_DDR4_PHY_SUPPLEMENT_IO_CONFIG_RX_BIAS_MASK 0x18000
 #define SJC16_DDR4_PHY_SUPPLEMENT_IO_CONFIG_RX_BIAS_ALIGN 0
 #define SJC16_DDR4_PHY_SUPPLEMENT_IO_CONFIG_RX_BIAS_BITS 2
 #define SJC16_DDR4_PHY_SUPPLEMENT_IO_CONFIG_RX_BIAS_SHIFT 15
 #define SJC16_DDR4_PHY_SUPPLEMENT_IO_CONFIG_RX_BIAS_RESETVALUE 0x3
 #define SJC16_DDR4_PHY_SUPPLEMENT_IO_CONFIG_PEAK_MASK 0x6000
 #define SJC16_DDR4_PHY_SUPPLEMENT_IO_CONFIG_PEAK_ALIGN 0
 #define SJC16_DDR4_PHY_SUPPLEMENT_IO_CONFIG_PEAK_BITS 2
 #define SJC16_DDR4_PHY_SUPPLEMENT_IO_CONFIG_PEAK_SHIFT 13
 #define SJC16_DDR4_PHY_SUPPLEMENT_IO_CONFIG_PEAK_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_SUPPLEMENT_IO_CONFIG_DEM_MASK 0x1800
 #define SJC16_DDR4_PHY_SUPPLEMENT_IO_CONFIG_DEM_ALIGN 0
 #define SJC16_DDR4_PHY_SUPPLEMENT_IO_CONFIG_DEM_BITS 2
 #define SJC16_DDR4_PHY_SUPPLEMENT_IO_CONFIG_DEM_SHIFT 11
 #define SJC16_DDR4_PHY_SUPPLEMENT_IO_CONFIG_DEM_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_SUPPLEMENT_IO_CONFIG_PD_MASK 0x3e0
 #define SJC16_DDR4_PHY_SUPPLEMENT_IO_CONFIG_PD_ALIGN 0
 #define SJC16_DDR4_PHY_SUPPLEMENT_IO_CONFIG_PD_BITS 5
 #define SJC16_DDR4_PHY_SUPPLEMENT_IO_CONFIG_PD_SHIFT 5
 #define SJC16_DDR4_PHY_SUPPLEMENT_IO_CONFIG_PD_RESETVALUE 0x10
 #define SJC16_DDR4_PHY_SUPPLEMENT_IO_CONFIG_ND_MASK 0x1f
 #define SJC16_DDR4_PHY_SUPPLEMENT_IO_CONFIG_ND_ALIGN 0
 #define SJC16_DDR4_PHY_SUPPLEMENT_IO_CONFIG_ND_BITS 5
 #define SJC16_DDR4_PHY_SUPPLEMENT_IO_CONFIG_ND_SHIFT 0
 #define SJC16_DDR4_PHY_SUPPLEMENT_IO_CONFIG_ND_RESETVALUE 0xf
 #define SJC16_DDR4_PHY_SUPPLEMENT_IO_CONFIG_ALL_MASK 0xffffffff
 #define SJC16_DDR4_PHY_SUPPLEMENT_IO_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_SUPPLEMENT_IO_CONFIG_ALL_BITS 32
 #define SJC16_DDR4_PHY_SUPPLEMENT_IO_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_SUPPLEMENT_IO_CONFIG_ALL_MASK 0xffffffff
 #define SJC16_DDR4_PHY_SUPPLEMENT_IO_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_SUPPLEMENT_IO_CONFIG_ALL_BITS 32
 #define SJC16_DDR4_PHY_SUPPLEMENT_IO_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_SUPPLEMENT_IO_CONFIG_DATAMASK 0xfffbfbff
 #define SJC16_DDR4_PHY_SUPPLEMENT_IO_CONFIG_RDWRMASK 0x00040400
 #define SJC16_DDR4_PHY_SUPPLEMENT_IO_CONFIG_RESETVALUE 0x107b820f
 #define SJC16_DDR4_PHY_SUPPLEMENT_MACRO_RESERVED_REG 0x1023f004
 #define SJC16_DDR4_PHY_SUPPLEMENT_MACRO_RESERVED_REG_BASE 0x004
 #define SJC16_DDR4_PHY_SUPPLEMENT_MACRO_RESERVED_REG_RESERVED_MASK 0xffffffff
 #define SJC16_DDR4_PHY_SUPPLEMENT_MACRO_RESERVED_REG_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_SUPPLEMENT_MACRO_RESERVED_REG_RESERVED_BITS 32
 #define SJC16_DDR4_PHY_SUPPLEMENT_MACRO_RESERVED_REG_RESERVED_SHIFT 0
 #define SJC16_DDR4_PHY_SUPPLEMENT_MACRO_RESERVED_REG_RESERVED_RESETVALUE 0x00000000
 #define SJC16_DDR4_PHY_SUPPLEMENT_MACRO_RESERVED_REG_ALL_MASK 0xffffffff
 #define SJC16_DDR4_PHY_SUPPLEMENT_MACRO_RESERVED_REG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_SUPPLEMENT_MACRO_RESERVED_REG_ALL_BITS 32
 #define SJC16_DDR4_PHY_SUPPLEMENT_MACRO_RESERVED_REG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_SUPPLEMENT_MACRO_RESERVED_REG_ALL_MASK 0xffffffff
 #define SJC16_DDR4_PHY_SUPPLEMENT_MACRO_RESERVED_REG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_SUPPLEMENT_MACRO_RESERVED_REG_ALL_BITS 32
 #define SJC16_DDR4_PHY_SUPPLEMENT_MACRO_RESERVED_REG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_SUPPLEMENT_MACRO_RESERVED_REG_DATAMASK 0xffffffff
 #define SJC16_DDR4_PHY_SUPPLEMENT_MACRO_RESERVED_REG_RDWRMASK 0x00000000
 #define SJC16_DDR4_PHY_SUPPLEMENT_MACRO_RESERVED_REG_RESETVALUE 0x00000000
 #define SJC16_DDR4_PHY_SUPPLEMENT_STATUS_MACRO_RESERVED 0x1023f008
 #define SJC16_DDR4_PHY_SUPPLEMENT_STATUS_MACRO_RESERVED_BASE 0x008
 #define SJC16_DDR4_PHY_SUPPLEMENT_STATUS_MACRO_RESERVED_RESERVED_MASK 0xffffffff
 #define SJC16_DDR4_PHY_SUPPLEMENT_STATUS_MACRO_RESERVED_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_SUPPLEMENT_STATUS_MACRO_RESERVED_RESERVED_BITS 32
 #define SJC16_DDR4_PHY_SUPPLEMENT_STATUS_MACRO_RESERVED_RESERVED_SHIFT 0
 #define SJC16_DDR4_PHY_SUPPLEMENT_STATUS_MACRO_RESERVED_RESERVED_RESETVALUE 0x00000000
 #define SJC16_DDR4_PHY_SUPPLEMENT_STATUS_MACRO_RESERVED_ALL_MASK 0xffffffff
 #define SJC16_DDR4_PHY_SUPPLEMENT_STATUS_MACRO_RESERVED_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_SUPPLEMENT_STATUS_MACRO_RESERVED_ALL_BITS 32
 #define SJC16_DDR4_PHY_SUPPLEMENT_STATUS_MACRO_RESERVED_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_SUPPLEMENT_STATUS_MACRO_RESERVED_ALL_MASK 0xffffffff
 #define SJC16_DDR4_PHY_SUPPLEMENT_STATUS_MACRO_RESERVED_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_SUPPLEMENT_STATUS_MACRO_RESERVED_ALL_BITS 32
 #define SJC16_DDR4_PHY_SUPPLEMENT_STATUS_MACRO_RESERVED_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_SUPPLEMENT_STATUS_MACRO_RESERVED_DATAMASK 0xffffffff
 #define SJC16_DDR4_PHY_SUPPLEMENT_STATUS_MACRO_RESERVED_RDWRMASK 0x00000000
 #define SJC16_DDR4_PHY_SUPPLEMENT_STATUS_MACRO_RESERVED_RESETVALUE 0x00000000
 #define SJC16_DDR4_PHY_AQ_L_MAX_VDL_ADDR 0x1023f400
 #define SJC16_DDR4_PHY_AQ_L_MAX_VDL_ADDR_BASE 0x400
 #define SJC16_DDR4_PHY_AQ_L_MAX_VDL_ADDR_UI_SHIFT_MASK 0x600
 #define SJC16_DDR4_PHY_AQ_L_MAX_VDL_ADDR_UI_SHIFT_ALIGN 0
 #define SJC16_DDR4_PHY_AQ_L_MAX_VDL_ADDR_UI_SHIFT_BITS 2
 #define SJC16_DDR4_PHY_AQ_L_MAX_VDL_ADDR_UI_SHIFT_SHIFT 9
 #define SJC16_DDR4_PHY_AQ_L_MAX_VDL_ADDR_UI_SHIFT_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_AQ_L_MAX_VDL_ADDR_MAX_VDL_STEP_MASK 0x1ff
 #define SJC16_DDR4_PHY_AQ_L_MAX_VDL_ADDR_MAX_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_AQ_L_MAX_VDL_ADDR_MAX_VDL_STEP_BITS 9
 #define SJC16_DDR4_PHY_AQ_L_MAX_VDL_ADDR_MAX_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_AQ_L_MAX_VDL_ADDR_MAX_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_AQ_L_MAX_VDL_ADDR_RESERVED_MASK 0xfffff800
 #define SJC16_DDR4_PHY_AQ_L_MAX_VDL_ADDR_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_AQ_L_MAX_VDL_ADDR_RESERVED_BITS 21
 #define SJC16_DDR4_PHY_AQ_L_MAX_VDL_ADDR_RESERVED_SHIFT 11
 #define SJC16_DDR4_PHY_AQ_L_MAX_VDL_ADDR_ALL_MASK 0x7ff
 #define SJC16_DDR4_PHY_AQ_L_MAX_VDL_ADDR_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_AQ_L_MAX_VDL_ADDR_ALL_BITS 11
 #define SJC16_DDR4_PHY_AQ_L_MAX_VDL_ADDR_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_AQ_L_MAX_VDL_ADDR_ALL_MASK 0x7ff
 #define SJC16_DDR4_PHY_AQ_L_MAX_VDL_ADDR_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_AQ_L_MAX_VDL_ADDR_ALL_BITS 11
 #define SJC16_DDR4_PHY_AQ_L_MAX_VDL_ADDR_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_AQ_L_MAX_VDL_ADDR_DATAMASK 0x000007ff
 #define SJC16_DDR4_PHY_AQ_L_MAX_VDL_ADDR_RDWRMASK 0xfffff800
 #define SJC16_DDR4_PHY_AQ_L_MAX_VDL_ADDR_RESETVALUE 0x000
 #define SJC16_DDR4_PHY_AQ_L_MAX_VDL_CTRL 0x1023f404
 #define SJC16_DDR4_PHY_AQ_L_MAX_VDL_CTRL_BASE 0x404
 #define SJC16_DDR4_PHY_AQ_L_MAX_VDL_CTRL_UI_SHIFT_MASK 0x600
 #define SJC16_DDR4_PHY_AQ_L_MAX_VDL_CTRL_UI_SHIFT_ALIGN 0
 #define SJC16_DDR4_PHY_AQ_L_MAX_VDL_CTRL_UI_SHIFT_BITS 2
 #define SJC16_DDR4_PHY_AQ_L_MAX_VDL_CTRL_UI_SHIFT_SHIFT 9
 #define SJC16_DDR4_PHY_AQ_L_MAX_VDL_CTRL_UI_SHIFT_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_AQ_L_MAX_VDL_CTRL_MAX_VDL_STEP_MASK 0x1ff
 #define SJC16_DDR4_PHY_AQ_L_MAX_VDL_CTRL_MAX_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_AQ_L_MAX_VDL_CTRL_MAX_VDL_STEP_BITS 9
 #define SJC16_DDR4_PHY_AQ_L_MAX_VDL_CTRL_MAX_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_AQ_L_MAX_VDL_CTRL_MAX_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_AQ_L_MAX_VDL_CTRL_RESERVED_MASK 0xfffff800
 #define SJC16_DDR4_PHY_AQ_L_MAX_VDL_CTRL_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_AQ_L_MAX_VDL_CTRL_RESERVED_BITS 21
 #define SJC16_DDR4_PHY_AQ_L_MAX_VDL_CTRL_RESERVED_SHIFT 11
 #define SJC16_DDR4_PHY_AQ_L_MAX_VDL_CTRL_ALL_MASK 0x7ff
 #define SJC16_DDR4_PHY_AQ_L_MAX_VDL_CTRL_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_AQ_L_MAX_VDL_CTRL_ALL_BITS 11
 #define SJC16_DDR4_PHY_AQ_L_MAX_VDL_CTRL_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_AQ_L_MAX_VDL_CTRL_ALL_MASK 0x7ff
 #define SJC16_DDR4_PHY_AQ_L_MAX_VDL_CTRL_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_AQ_L_MAX_VDL_CTRL_ALL_BITS 11
 #define SJC16_DDR4_PHY_AQ_L_MAX_VDL_CTRL_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_AQ_L_MAX_VDL_CTRL_DATAMASK 0x000007ff
 #define SJC16_DDR4_PHY_AQ_L_MAX_VDL_CTRL_RDWRMASK 0xfffff800
 #define SJC16_DDR4_PHY_AQ_L_MAX_VDL_CTRL_RESETVALUE 0x000
 #define SJC16_DDR4_PHY_AQ_U_MAX_VDL_ADDR 0x1023f408
 #define SJC16_DDR4_PHY_AQ_U_MAX_VDL_ADDR_BASE 0x408
 #define SJC16_DDR4_PHY_AQ_U_MAX_VDL_ADDR_UI_SHIFT_MASK 0x600
 #define SJC16_DDR4_PHY_AQ_U_MAX_VDL_ADDR_UI_SHIFT_ALIGN 0
 #define SJC16_DDR4_PHY_AQ_U_MAX_VDL_ADDR_UI_SHIFT_BITS 2
 #define SJC16_DDR4_PHY_AQ_U_MAX_VDL_ADDR_UI_SHIFT_SHIFT 9
 #define SJC16_DDR4_PHY_AQ_U_MAX_VDL_ADDR_UI_SHIFT_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_AQ_U_MAX_VDL_ADDR_MAX_VDL_STEP_MASK 0x1ff
 #define SJC16_DDR4_PHY_AQ_U_MAX_VDL_ADDR_MAX_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_AQ_U_MAX_VDL_ADDR_MAX_VDL_STEP_BITS 9
 #define SJC16_DDR4_PHY_AQ_U_MAX_VDL_ADDR_MAX_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_AQ_U_MAX_VDL_ADDR_MAX_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_AQ_U_MAX_VDL_ADDR_RESERVED_MASK 0xfffff800
 #define SJC16_DDR4_PHY_AQ_U_MAX_VDL_ADDR_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_AQ_U_MAX_VDL_ADDR_RESERVED_BITS 21
 #define SJC16_DDR4_PHY_AQ_U_MAX_VDL_ADDR_RESERVED_SHIFT 11
 #define SJC16_DDR4_PHY_AQ_U_MAX_VDL_ADDR_ALL_MASK 0x7ff
 #define SJC16_DDR4_PHY_AQ_U_MAX_VDL_ADDR_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_AQ_U_MAX_VDL_ADDR_ALL_BITS 11
 #define SJC16_DDR4_PHY_AQ_U_MAX_VDL_ADDR_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_AQ_U_MAX_VDL_ADDR_ALL_MASK 0x7ff
 #define SJC16_DDR4_PHY_AQ_U_MAX_VDL_ADDR_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_AQ_U_MAX_VDL_ADDR_ALL_BITS 11
 #define SJC16_DDR4_PHY_AQ_U_MAX_VDL_ADDR_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_AQ_U_MAX_VDL_ADDR_DATAMASK 0x000007ff
 #define SJC16_DDR4_PHY_AQ_U_MAX_VDL_ADDR_RDWRMASK 0xfffff800
 #define SJC16_DDR4_PHY_AQ_U_MAX_VDL_ADDR_RESETVALUE 0x000
 #define SJC16_DDR4_PHY_AQ_U_MAX_VDL_CTRL 0x1023f40c
 #define SJC16_DDR4_PHY_AQ_U_MAX_VDL_CTRL_BASE 0x40c
 #define SJC16_DDR4_PHY_AQ_U_MAX_VDL_CTRL_UI_SHIFT_MASK 0x600
 #define SJC16_DDR4_PHY_AQ_U_MAX_VDL_CTRL_UI_SHIFT_ALIGN 0
 #define SJC16_DDR4_PHY_AQ_U_MAX_VDL_CTRL_UI_SHIFT_BITS 2
 #define SJC16_DDR4_PHY_AQ_U_MAX_VDL_CTRL_UI_SHIFT_SHIFT 9
 #define SJC16_DDR4_PHY_AQ_U_MAX_VDL_CTRL_UI_SHIFT_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_AQ_U_MAX_VDL_CTRL_MAX_VDL_STEP_MASK 0x1ff
 #define SJC16_DDR4_PHY_AQ_U_MAX_VDL_CTRL_MAX_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_AQ_U_MAX_VDL_CTRL_MAX_VDL_STEP_BITS 9
 #define SJC16_DDR4_PHY_AQ_U_MAX_VDL_CTRL_MAX_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_AQ_U_MAX_VDL_CTRL_MAX_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_AQ_U_MAX_VDL_CTRL_RESERVED_MASK 0xfffff800
 #define SJC16_DDR4_PHY_AQ_U_MAX_VDL_CTRL_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_AQ_U_MAX_VDL_CTRL_RESERVED_BITS 21
 #define SJC16_DDR4_PHY_AQ_U_MAX_VDL_CTRL_RESERVED_SHIFT 11
 #define SJC16_DDR4_PHY_AQ_U_MAX_VDL_CTRL_ALL_MASK 0x7ff
 #define SJC16_DDR4_PHY_AQ_U_MAX_VDL_CTRL_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_AQ_U_MAX_VDL_CTRL_ALL_BITS 11
 #define SJC16_DDR4_PHY_AQ_U_MAX_VDL_CTRL_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_AQ_U_MAX_VDL_CTRL_ALL_MASK 0x7ff
 #define SJC16_DDR4_PHY_AQ_U_MAX_VDL_CTRL_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_AQ_U_MAX_VDL_CTRL_ALL_BITS 11
 #define SJC16_DDR4_PHY_AQ_U_MAX_VDL_CTRL_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_AQ_U_MAX_VDL_CTRL_DATAMASK 0x000007ff
 #define SJC16_DDR4_PHY_AQ_U_MAX_VDL_CTRL_RDWRMASK 0xfffff800
 #define SJC16_DDR4_PHY_AQ_U_MAX_VDL_CTRL_RESETVALUE 0x000
 #define SJC16_DDR4_PHY_AQ_IO_CONFIG 0x1023f410
 #define SJC16_DDR4_PHY_AQ_IO_CONFIG_BASE 0x410
 #define SJC16_DDR4_PHY_AQ_IO_CONFIG_RXENB_ALERT_N_MASK 0x20000000
 #define SJC16_DDR4_PHY_AQ_IO_CONFIG_RXENB_ALERT_N_ALIGN 0
 #define SJC16_DDR4_PHY_AQ_IO_CONFIG_RXENB_ALERT_N_BITS 1
 #define SJC16_DDR4_PHY_AQ_IO_CONFIG_RXENB_ALERT_N_SHIFT 29
 #define SJC16_DDR4_PHY_AQ_IO_CONFIG_RXENB_ALERT_N_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_AQ_IO_CONFIG_PTERM_MASK 0x1f000000
 #define SJC16_DDR4_PHY_AQ_IO_CONFIG_PTERM_ALIGN 0
 #define SJC16_DDR4_PHY_AQ_IO_CONFIG_PTERM_BITS 5
 #define SJC16_DDR4_PHY_AQ_IO_CONFIG_PTERM_SHIFT 24
 #define SJC16_DDR4_PHY_AQ_IO_CONFIG_PTERM_RESETVALUE 0x10
 #define SJC16_DDR4_PHY_AQ_IO_CONFIG_NTERM_MASK 0xf80000
 #define SJC16_DDR4_PHY_AQ_IO_CONFIG_NTERM_ALIGN 0
 #define SJC16_DDR4_PHY_AQ_IO_CONFIG_NTERM_BITS 5
 #define SJC16_DDR4_PHY_AQ_IO_CONFIG_NTERM_SHIFT 19
 #define SJC16_DDR4_PHY_AQ_IO_CONFIG_NTERM_RESETVALUE 0xf
 #define SJC16_DDR4_PHY_AQ_IO_CONFIG_PULL_UP_OFF_B_MASK 0x20000
 #define SJC16_DDR4_PHY_AQ_IO_CONFIG_PULL_UP_OFF_B_ALIGN 0
 #define SJC16_DDR4_PHY_AQ_IO_CONFIG_PULL_UP_OFF_B_BITS 1
 #define SJC16_DDR4_PHY_AQ_IO_CONFIG_PULL_UP_OFF_B_SHIFT 17
 #define SJC16_DDR4_PHY_AQ_IO_CONFIG_PULL_UP_OFF_B_RESETVALUE 0x1
 #define SJC16_DDR4_PHY_AQ_IO_CONFIG_RX_BIAS_MASK 0x18000
 #define SJC16_DDR4_PHY_AQ_IO_CONFIG_RX_BIAS_ALIGN 0
 #define SJC16_DDR4_PHY_AQ_IO_CONFIG_RX_BIAS_BITS 2
 #define SJC16_DDR4_PHY_AQ_IO_CONFIG_RX_BIAS_SHIFT 15
 #define SJC16_DDR4_PHY_AQ_IO_CONFIG_RX_BIAS_RESETVALUE 0x3
 #define SJC16_DDR4_PHY_AQ_IO_CONFIG_PEAK_MASK 0x6000
 #define SJC16_DDR4_PHY_AQ_IO_CONFIG_PEAK_ALIGN 0
 #define SJC16_DDR4_PHY_AQ_IO_CONFIG_PEAK_BITS 2
 #define SJC16_DDR4_PHY_AQ_IO_CONFIG_PEAK_SHIFT 13
 #define SJC16_DDR4_PHY_AQ_IO_CONFIG_PEAK_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_AQ_IO_CONFIG_DEM_MASK 0x1800
 #define SJC16_DDR4_PHY_AQ_IO_CONFIG_DEM_ALIGN 0
 #define SJC16_DDR4_PHY_AQ_IO_CONFIG_DEM_BITS 2
 #define SJC16_DDR4_PHY_AQ_IO_CONFIG_DEM_SHIFT 11
 #define SJC16_DDR4_PHY_AQ_IO_CONFIG_DEM_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_AQ_IO_CONFIG_RXENB_MASK 0x400
 #define SJC16_DDR4_PHY_AQ_IO_CONFIG_RXENB_ALIGN 0
 #define SJC16_DDR4_PHY_AQ_IO_CONFIG_RXENB_BITS 1
 #define SJC16_DDR4_PHY_AQ_IO_CONFIG_RXENB_SHIFT 10
 #define SJC16_DDR4_PHY_AQ_IO_CONFIG_RXENB_RESETVALUE 0x1
 #define SJC16_DDR4_PHY_AQ_IO_CONFIG_PD_MASK 0x3e0
 #define SJC16_DDR4_PHY_AQ_IO_CONFIG_PD_ALIGN 0
 #define SJC16_DDR4_PHY_AQ_IO_CONFIG_PD_BITS 5
 #define SJC16_DDR4_PHY_AQ_IO_CONFIG_PD_SHIFT 5
 #define SJC16_DDR4_PHY_AQ_IO_CONFIG_PD_RESETVALUE 0x10
 #define SJC16_DDR4_PHY_AQ_IO_CONFIG_ND_MASK 0x1f
 #define SJC16_DDR4_PHY_AQ_IO_CONFIG_ND_ALIGN 0
 #define SJC16_DDR4_PHY_AQ_IO_CONFIG_ND_BITS 5
 #define SJC16_DDR4_PHY_AQ_IO_CONFIG_ND_SHIFT 0
 #define SJC16_DDR4_PHY_AQ_IO_CONFIG_ND_RESETVALUE 0xf
 #define SJC16_DDR4_PHY_AQ_IO_CONFIG_RESERVED_MASK 0xc0000000
 #define SJC16_DDR4_PHY_AQ_IO_CONFIG_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_AQ_IO_CONFIG_RESERVED_BITS 2
 #define SJC16_DDR4_PHY_AQ_IO_CONFIG_RESERVED_SHIFT 30
 #define SJC16_DDR4_PHY_AQ_IO_CONFIG_ALL_MASK 0x3fffffff
 #define SJC16_DDR4_PHY_AQ_IO_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_AQ_IO_CONFIG_ALL_BITS 30
 #define SJC16_DDR4_PHY_AQ_IO_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_AQ_IO_CONFIG_ALL_MASK 0x3fffffff
 #define SJC16_DDR4_PHY_AQ_IO_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_AQ_IO_CONFIG_ALL_BITS 30
 #define SJC16_DDR4_PHY_AQ_IO_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_AQ_IO_CONFIG_DATAMASK 0x3ffbffff
 #define SJC16_DDR4_PHY_AQ_IO_CONFIG_RDWRMASK 0xc0040000
 #define SJC16_DDR4_PHY_AQ_IO_CONFIG_RESETVALUE 0x107b860f
 #define SJC16_DDR4_PHY_AQ_LDO_CONFIG 0x1023f414
 #define SJC16_DDR4_PHY_AQ_LDO_CONFIG_BASE 0x414
 #define SJC16_DDR4_PHY_AQ_LDO_CONFIG_REF_SEL_EXT_MASK 0x2000
 #define SJC16_DDR4_PHY_AQ_LDO_CONFIG_REF_SEL_EXT_ALIGN 0
 #define SJC16_DDR4_PHY_AQ_LDO_CONFIG_REF_SEL_EXT_BITS 1
 #define SJC16_DDR4_PHY_AQ_LDO_CONFIG_REF_SEL_EXT_SHIFT 13
 #define SJC16_DDR4_PHY_AQ_LDO_CONFIG_REF_SEL_EXT_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_AQ_LDO_CONFIG_REF_EXT_MASK 0x1000
 #define SJC16_DDR4_PHY_AQ_LDO_CONFIG_REF_EXT_ALIGN 0
 #define SJC16_DDR4_PHY_AQ_LDO_CONFIG_REF_EXT_BITS 1
 #define SJC16_DDR4_PHY_AQ_LDO_CONFIG_REF_EXT_SHIFT 12
 #define SJC16_DDR4_PHY_AQ_LDO_CONFIG_REF_EXT_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_AQ_LDO_CONFIG_PWRDN_MASK 0x200
 #define SJC16_DDR4_PHY_AQ_LDO_CONFIG_PWRDN_ALIGN 0
 #define SJC16_DDR4_PHY_AQ_LDO_CONFIG_PWRDN_BITS 1
 #define SJC16_DDR4_PHY_AQ_LDO_CONFIG_PWRDN_SHIFT 9
 #define SJC16_DDR4_PHY_AQ_LDO_CONFIG_PWRDN_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_AQ_LDO_CONFIG_CTRL_MASK 0x1f8
 #define SJC16_DDR4_PHY_AQ_LDO_CONFIG_CTRL_ALIGN 0
 #define SJC16_DDR4_PHY_AQ_LDO_CONFIG_CTRL_BITS 6
 #define SJC16_DDR4_PHY_AQ_LDO_CONFIG_CTRL_SHIFT 3
 #define SJC16_DDR4_PHY_AQ_LDO_CONFIG_CTRL_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_AQ_LDO_CONFIG_BYPASS_MASK 0x4
 #define SJC16_DDR4_PHY_AQ_LDO_CONFIG_BYPASS_ALIGN 0
 #define SJC16_DDR4_PHY_AQ_LDO_CONFIG_BYPASS_BITS 1
 #define SJC16_DDR4_PHY_AQ_LDO_CONFIG_BYPASS_SHIFT 2
 #define SJC16_DDR4_PHY_AQ_LDO_CONFIG_BYPASS_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_AQ_LDO_CONFIG_BIAS_CTRL_MASK 0x3
 #define SJC16_DDR4_PHY_AQ_LDO_CONFIG_BIAS_CTRL_ALIGN 0
 #define SJC16_DDR4_PHY_AQ_LDO_CONFIG_BIAS_CTRL_BITS 2
 #define SJC16_DDR4_PHY_AQ_LDO_CONFIG_BIAS_CTRL_SHIFT 0
 #define SJC16_DDR4_PHY_AQ_LDO_CONFIG_BIAS_CTRL_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_AQ_LDO_CONFIG_RESERVED_MASK 0xffffc000
 #define SJC16_DDR4_PHY_AQ_LDO_CONFIG_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_AQ_LDO_CONFIG_RESERVED_BITS 18
 #define SJC16_DDR4_PHY_AQ_LDO_CONFIG_RESERVED_SHIFT 14
 #define SJC16_DDR4_PHY_AQ_LDO_CONFIG_ALL_MASK 0x3fff
 #define SJC16_DDR4_PHY_AQ_LDO_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_AQ_LDO_CONFIG_ALL_BITS 14
 #define SJC16_DDR4_PHY_AQ_LDO_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_AQ_LDO_CONFIG_ALL_MASK 0x3fff
 #define SJC16_DDR4_PHY_AQ_LDO_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_AQ_LDO_CONFIG_ALL_BITS 14
 #define SJC16_DDR4_PHY_AQ_LDO_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_AQ_LDO_CONFIG_DATAMASK 0x000033ff
 #define SJC16_DDR4_PHY_AQ_LDO_CONFIG_RDWRMASK 0xffffcc00
 #define SJC16_DDR4_PHY_AQ_LDO_CONFIG_RESETVALUE 0x0000
 #define SJC16_DDR4_PHY_AQ_L_MACRO_RESERVED_REG 0x1023f418
 #define SJC16_DDR4_PHY_AQ_L_MACRO_RESERVED_REG_BASE 0x418
 #define SJC16_DDR4_PHY_AQ_L_MACRO_RESERVED_REG_RESERVED_MASK 0xffffffff
 #define SJC16_DDR4_PHY_AQ_L_MACRO_RESERVED_REG_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_AQ_L_MACRO_RESERVED_REG_RESERVED_BITS 32
 #define SJC16_DDR4_PHY_AQ_L_MACRO_RESERVED_REG_RESERVED_SHIFT 0
 #define SJC16_DDR4_PHY_AQ_L_MACRO_RESERVED_REG_RESERVED_RESETVALUE 0x00000000
 #define SJC16_DDR4_PHY_AQ_L_MACRO_RESERVED_REG_ALL_MASK 0xffffffff
 #define SJC16_DDR4_PHY_AQ_L_MACRO_RESERVED_REG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_AQ_L_MACRO_RESERVED_REG_ALL_BITS 32
 #define SJC16_DDR4_PHY_AQ_L_MACRO_RESERVED_REG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_AQ_L_MACRO_RESERVED_REG_ALL_MASK 0xffffffff
 #define SJC16_DDR4_PHY_AQ_L_MACRO_RESERVED_REG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_AQ_L_MACRO_RESERVED_REG_ALL_BITS 32
 #define SJC16_DDR4_PHY_AQ_L_MACRO_RESERVED_REG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_AQ_L_MACRO_RESERVED_REG_DATAMASK 0xffffffff
 #define SJC16_DDR4_PHY_AQ_L_MACRO_RESERVED_REG_RDWRMASK 0x00000000
 #define SJC16_DDR4_PHY_AQ_L_MACRO_RESERVED_REG_RESETVALUE 0x00000000
 #define SJC16_DDR4_PHY_AQ_L_STATUS_MACRO_RESERVED 0x1023f41c
 #define SJC16_DDR4_PHY_AQ_L_STATUS_MACRO_RESERVED_BASE 0x41c
 #define SJC16_DDR4_PHY_AQ_L_STATUS_MACRO_RESERVED_RESERVED_MASK 0xffffffff
 #define SJC16_DDR4_PHY_AQ_L_STATUS_MACRO_RESERVED_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_AQ_L_STATUS_MACRO_RESERVED_RESERVED_BITS 32
 #define SJC16_DDR4_PHY_AQ_L_STATUS_MACRO_RESERVED_RESERVED_SHIFT 0
 #define SJC16_DDR4_PHY_AQ_L_STATUS_MACRO_RESERVED_RESERVED_RESETVALUE 0x00000000
 #define SJC16_DDR4_PHY_AQ_L_STATUS_MACRO_RESERVED_ALL_MASK 0xffffffff
 #define SJC16_DDR4_PHY_AQ_L_STATUS_MACRO_RESERVED_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_AQ_L_STATUS_MACRO_RESERVED_ALL_BITS 32
 #define SJC16_DDR4_PHY_AQ_L_STATUS_MACRO_RESERVED_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_AQ_L_STATUS_MACRO_RESERVED_ALL_MASK 0xffffffff
 #define SJC16_DDR4_PHY_AQ_L_STATUS_MACRO_RESERVED_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_AQ_L_STATUS_MACRO_RESERVED_ALL_BITS 32
 #define SJC16_DDR4_PHY_AQ_L_STATUS_MACRO_RESERVED_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_AQ_L_STATUS_MACRO_RESERVED_DATAMASK 0xffffffff
 #define SJC16_DDR4_PHY_AQ_L_STATUS_MACRO_RESERVED_RDWRMASK 0x00000000
 #define SJC16_DDR4_PHY_AQ_L_STATUS_MACRO_RESERVED_RESETVALUE 0x00000000
 #define SJC16_DDR4_PHY_AQ_U_MACRO_RESERVED_REG 0x1023f420
 #define SJC16_DDR4_PHY_AQ_U_MACRO_RESERVED_REG_BASE 0x420
 #define SJC16_DDR4_PHY_AQ_U_MACRO_RESERVED_REG_RESERVED_MASK 0xffffffff
 #define SJC16_DDR4_PHY_AQ_U_MACRO_RESERVED_REG_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_AQ_U_MACRO_RESERVED_REG_RESERVED_BITS 32
 #define SJC16_DDR4_PHY_AQ_U_MACRO_RESERVED_REG_RESERVED_SHIFT 0
 #define SJC16_DDR4_PHY_AQ_U_MACRO_RESERVED_REG_RESERVED_RESETVALUE 0x00000000
 #define SJC16_DDR4_PHY_AQ_U_MACRO_RESERVED_REG_ALL_MASK 0xffffffff
 #define SJC16_DDR4_PHY_AQ_U_MACRO_RESERVED_REG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_AQ_U_MACRO_RESERVED_REG_ALL_BITS 32
 #define SJC16_DDR4_PHY_AQ_U_MACRO_RESERVED_REG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_AQ_U_MACRO_RESERVED_REG_ALL_MASK 0xffffffff
 #define SJC16_DDR4_PHY_AQ_U_MACRO_RESERVED_REG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_AQ_U_MACRO_RESERVED_REG_ALL_BITS 32
 #define SJC16_DDR4_PHY_AQ_U_MACRO_RESERVED_REG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_AQ_U_MACRO_RESERVED_REG_DATAMASK 0xffffffff
 #define SJC16_DDR4_PHY_AQ_U_MACRO_RESERVED_REG_RDWRMASK 0x00000000
 #define SJC16_DDR4_PHY_AQ_U_MACRO_RESERVED_REG_RESETVALUE 0x00000000
 #define SJC16_DDR4_PHY_AQ_U_STATUS_MACRO_RESERVED 0x1023f424
 #define SJC16_DDR4_PHY_AQ_U_STATUS_MACRO_RESERVED_BASE 0x424
 #define SJC16_DDR4_PHY_AQ_U_STATUS_MACRO_RESERVED_RESERVED_MASK 0xffffffff
 #define SJC16_DDR4_PHY_AQ_U_STATUS_MACRO_RESERVED_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_AQ_U_STATUS_MACRO_RESERVED_RESERVED_BITS 32
 #define SJC16_DDR4_PHY_AQ_U_STATUS_MACRO_RESERVED_RESERVED_SHIFT 0
 #define SJC16_DDR4_PHY_AQ_U_STATUS_MACRO_RESERVED_RESERVED_RESETVALUE 0x00000000
 #define SJC16_DDR4_PHY_AQ_U_STATUS_MACRO_RESERVED_ALL_MASK 0xffffffff
 #define SJC16_DDR4_PHY_AQ_U_STATUS_MACRO_RESERVED_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_AQ_U_STATUS_MACRO_RESERVED_ALL_BITS 32
 #define SJC16_DDR4_PHY_AQ_U_STATUS_MACRO_RESERVED_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_AQ_U_STATUS_MACRO_RESERVED_ALL_MASK 0xffffffff
 #define SJC16_DDR4_PHY_AQ_U_STATUS_MACRO_RESERVED_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_AQ_U_STATUS_MACRO_RESERVED_ALL_BITS 32
 #define SJC16_DDR4_PHY_AQ_U_STATUS_MACRO_RESERVED_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_AQ_U_STATUS_MACRO_RESERVED_DATAMASK 0xffffffff
 #define SJC16_DDR4_PHY_AQ_U_STATUS_MACRO_RESERVED_RDWRMASK 0x00000000
 #define SJC16_DDR4_PHY_AQ_U_STATUS_MACRO_RESERVED_RESETVALUE 0x00000000
 #define SJC16_DDR4_PHY_COMMON_MAX_VDL_CK 0x1023f800
 #define SJC16_DDR4_PHY_COMMON_MAX_VDL_CK_BASE 0x800
 #define SJC16_DDR4_PHY_COMMON_MAX_VDL_CK_UI_SHIFT_MASK 0xe00
 #define SJC16_DDR4_PHY_COMMON_MAX_VDL_CK_UI_SHIFT_ALIGN 0
 #define SJC16_DDR4_PHY_COMMON_MAX_VDL_CK_UI_SHIFT_BITS 3
 #define SJC16_DDR4_PHY_COMMON_MAX_VDL_CK_UI_SHIFT_SHIFT 9
 #define SJC16_DDR4_PHY_COMMON_MAX_VDL_CK_UI_SHIFT_RESETVALUE 0x3
 #define SJC16_DDR4_PHY_COMMON_MAX_VDL_CK_MAX_VDL_STEP_MASK 0x1ff
 #define SJC16_DDR4_PHY_COMMON_MAX_VDL_CK_MAX_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_COMMON_MAX_VDL_CK_MAX_VDL_STEP_BITS 9
 #define SJC16_DDR4_PHY_COMMON_MAX_VDL_CK_MAX_VDL_STEP_SHIFT 0
 #define SJC16_DDR4_PHY_COMMON_MAX_VDL_CK_MAX_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_COMMON_MAX_VDL_CK_RESERVED_MASK 0xfffff000
 #define SJC16_DDR4_PHY_COMMON_MAX_VDL_CK_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_COMMON_MAX_VDL_CK_RESERVED_BITS 20
 #define SJC16_DDR4_PHY_COMMON_MAX_VDL_CK_RESERVED_SHIFT 12
 #define SJC16_DDR4_PHY_COMMON_MAX_VDL_CK_ALL_MASK 0xfff
 #define SJC16_DDR4_PHY_COMMON_MAX_VDL_CK_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_COMMON_MAX_VDL_CK_ALL_BITS 12
 #define SJC16_DDR4_PHY_COMMON_MAX_VDL_CK_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_COMMON_MAX_VDL_CK_ALL_MASK 0xfff
 #define SJC16_DDR4_PHY_COMMON_MAX_VDL_CK_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_COMMON_MAX_VDL_CK_ALL_BITS 12
 #define SJC16_DDR4_PHY_COMMON_MAX_VDL_CK_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_COMMON_MAX_VDL_CK_DATAMASK 0x00000fff
 #define SJC16_DDR4_PHY_COMMON_MAX_VDL_CK_RDWRMASK 0xfffff000
 #define SJC16_DDR4_PHY_COMMON_MAX_VDL_CK_RESETVALUE 0x600
 #define SJC16_DDR4_PHY_COMMON_CK_CONFIG 0x1023f804
 #define SJC16_DDR4_PHY_COMMON_CK_CONFIG_BASE 0x804
 #define SJC16_DDR4_PHY_COMMON_CK_CONFIG_CK_ENABLE_MASK 0x100
 #define SJC16_DDR4_PHY_COMMON_CK_CONFIG_CK_ENABLE_ALIGN 0
 #define SJC16_DDR4_PHY_COMMON_CK_CONFIG_CK_ENABLE_BITS 1
 #define SJC16_DDR4_PHY_COMMON_CK_CONFIG_CK_ENABLE_SHIFT 8
 #define SJC16_DDR4_PHY_COMMON_CK_CONFIG_CK_ENABLE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_COMMON_CK_CONFIG_CK_PATTERN_MASK 0xff
 #define SJC16_DDR4_PHY_COMMON_CK_CONFIG_CK_PATTERN_ALIGN 0
 #define SJC16_DDR4_PHY_COMMON_CK_CONFIG_CK_PATTERN_BITS 8
 #define SJC16_DDR4_PHY_COMMON_CK_CONFIG_CK_PATTERN_SHIFT 0
 #define SJC16_DDR4_PHY_COMMON_CK_CONFIG_CK_PATTERN_RESETVALUE 0x33
 #define SJC16_DDR4_PHY_COMMON_CK_CONFIG_RESERVED_MASK 0xfffffe00
 #define SJC16_DDR4_PHY_COMMON_CK_CONFIG_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_COMMON_CK_CONFIG_RESERVED_BITS 23
 #define SJC16_DDR4_PHY_COMMON_CK_CONFIG_RESERVED_SHIFT 9
 #define SJC16_DDR4_PHY_COMMON_CK_CONFIG_ALL_MASK 0x1ff
 #define SJC16_DDR4_PHY_COMMON_CK_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_COMMON_CK_CONFIG_ALL_BITS 9
 #define SJC16_DDR4_PHY_COMMON_CK_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_COMMON_CK_CONFIG_ALL_MASK 0x1ff
 #define SJC16_DDR4_PHY_COMMON_CK_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_COMMON_CK_CONFIG_ALL_BITS 9
 #define SJC16_DDR4_PHY_COMMON_CK_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_COMMON_CK_CONFIG_DATAMASK 0x000001ff
 #define SJC16_DDR4_PHY_COMMON_CK_CONFIG_RDWRMASK 0xfffffe00
 #define SJC16_DDR4_PHY_COMMON_CK_CONFIG_RESETVALUE 0x033
 #define SJC16_DDR4_PHY_COMMON_IO_CONFIG 0x1023f808
 #define SJC16_DDR4_PHY_COMMON_IO_CONFIG_BASE 0x808
 #define SJC16_DDR4_PHY_COMMON_IO_CONFIG_PTERM_MASK 0x1f000000
 #define SJC16_DDR4_PHY_COMMON_IO_CONFIG_PTERM_ALIGN 0
 #define SJC16_DDR4_PHY_COMMON_IO_CONFIG_PTERM_BITS 5
 #define SJC16_DDR4_PHY_COMMON_IO_CONFIG_PTERM_SHIFT 24
 #define SJC16_DDR4_PHY_COMMON_IO_CONFIG_PTERM_RESETVALUE 0x10
 #define SJC16_DDR4_PHY_COMMON_IO_CONFIG_NTERM_MASK 0xf80000
 #define SJC16_DDR4_PHY_COMMON_IO_CONFIG_NTERM_ALIGN 0
 #define SJC16_DDR4_PHY_COMMON_IO_CONFIG_NTERM_BITS 5
 #define SJC16_DDR4_PHY_COMMON_IO_CONFIG_NTERM_SHIFT 19
 #define SJC16_DDR4_PHY_COMMON_IO_CONFIG_NTERM_RESETVALUE 0xf
 #define SJC16_DDR4_PHY_COMMON_IO_CONFIG_PULL_UP_OFF_B_MASK 0x20000
 #define SJC16_DDR4_PHY_COMMON_IO_CONFIG_PULL_UP_OFF_B_ALIGN 0
 #define SJC16_DDR4_PHY_COMMON_IO_CONFIG_PULL_UP_OFF_B_BITS 1
 #define SJC16_DDR4_PHY_COMMON_IO_CONFIG_PULL_UP_OFF_B_SHIFT 17
 #define SJC16_DDR4_PHY_COMMON_IO_CONFIG_PULL_UP_OFF_B_RESETVALUE 0x1
 #define SJC16_DDR4_PHY_COMMON_IO_CONFIG_RX_BIAS_MASK 0x18000
 #define SJC16_DDR4_PHY_COMMON_IO_CONFIG_RX_BIAS_ALIGN 0
 #define SJC16_DDR4_PHY_COMMON_IO_CONFIG_RX_BIAS_BITS 2
 #define SJC16_DDR4_PHY_COMMON_IO_CONFIG_RX_BIAS_SHIFT 15
 #define SJC16_DDR4_PHY_COMMON_IO_CONFIG_RX_BIAS_RESETVALUE 0x3
 #define SJC16_DDR4_PHY_COMMON_IO_CONFIG_PEAK_MASK 0x6000
 #define SJC16_DDR4_PHY_COMMON_IO_CONFIG_PEAK_ALIGN 0
 #define SJC16_DDR4_PHY_COMMON_IO_CONFIG_PEAK_BITS 2
 #define SJC16_DDR4_PHY_COMMON_IO_CONFIG_PEAK_SHIFT 13
 #define SJC16_DDR4_PHY_COMMON_IO_CONFIG_PEAK_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_COMMON_IO_CONFIG_DEM_MASK 0x1800
 #define SJC16_DDR4_PHY_COMMON_IO_CONFIG_DEM_ALIGN 0
 #define SJC16_DDR4_PHY_COMMON_IO_CONFIG_DEM_BITS 2
 #define SJC16_DDR4_PHY_COMMON_IO_CONFIG_DEM_SHIFT 11
 #define SJC16_DDR4_PHY_COMMON_IO_CONFIG_DEM_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_COMMON_IO_CONFIG_RXENB_MASK 0x400
 #define SJC16_DDR4_PHY_COMMON_IO_CONFIG_RXENB_ALIGN 0
 #define SJC16_DDR4_PHY_COMMON_IO_CONFIG_RXENB_BITS 1
 #define SJC16_DDR4_PHY_COMMON_IO_CONFIG_RXENB_SHIFT 10
 #define SJC16_DDR4_PHY_COMMON_IO_CONFIG_RXENB_RESETVALUE 0x1
 #define SJC16_DDR4_PHY_COMMON_IO_CONFIG_PD_MASK 0x3e0
 #define SJC16_DDR4_PHY_COMMON_IO_CONFIG_PD_ALIGN 0
 #define SJC16_DDR4_PHY_COMMON_IO_CONFIG_PD_BITS 5
 #define SJC16_DDR4_PHY_COMMON_IO_CONFIG_PD_SHIFT 5
 #define SJC16_DDR4_PHY_COMMON_IO_CONFIG_PD_RESETVALUE 0x10
 #define SJC16_DDR4_PHY_COMMON_IO_CONFIG_ND_MASK 0x1f
 #define SJC16_DDR4_PHY_COMMON_IO_CONFIG_ND_ALIGN 0
 #define SJC16_DDR4_PHY_COMMON_IO_CONFIG_ND_BITS 5
 #define SJC16_DDR4_PHY_COMMON_IO_CONFIG_ND_SHIFT 0
 #define SJC16_DDR4_PHY_COMMON_IO_CONFIG_ND_RESETVALUE 0xf
 #define SJC16_DDR4_PHY_COMMON_IO_CONFIG_RESERVED_MASK 0xe0000000
 #define SJC16_DDR4_PHY_COMMON_IO_CONFIG_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_COMMON_IO_CONFIG_RESERVED_BITS 3
 #define SJC16_DDR4_PHY_COMMON_IO_CONFIG_RESERVED_SHIFT 29
 #define SJC16_DDR4_PHY_COMMON_IO_CONFIG_ALL_MASK 0x1fffffff
 #define SJC16_DDR4_PHY_COMMON_IO_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_COMMON_IO_CONFIG_ALL_BITS 29
 #define SJC16_DDR4_PHY_COMMON_IO_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_COMMON_IO_CONFIG_ALL_MASK 0x1fffffff
 #define SJC16_DDR4_PHY_COMMON_IO_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_COMMON_IO_CONFIG_ALL_BITS 29
 #define SJC16_DDR4_PHY_COMMON_IO_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_COMMON_IO_CONFIG_DATAMASK 0x1ffbffff
 #define SJC16_DDR4_PHY_COMMON_IO_CONFIG_RDWRMASK 0xe0040000
 #define SJC16_DDR4_PHY_COMMON_IO_CONFIG_RESETVALUE 0x107b860f
 #define SJC16_DDR4_PHY_COMMON_LDO_CONFIG 0x1023f80c
 #define SJC16_DDR4_PHY_COMMON_LDO_CONFIG_BASE 0x80c
 #define SJC16_DDR4_PHY_COMMON_LDO_CONFIG_REF_SEL_EXT_MASK 0x2000
 #define SJC16_DDR4_PHY_COMMON_LDO_CONFIG_REF_SEL_EXT_ALIGN 0
 #define SJC16_DDR4_PHY_COMMON_LDO_CONFIG_REF_SEL_EXT_BITS 1
 #define SJC16_DDR4_PHY_COMMON_LDO_CONFIG_REF_SEL_EXT_SHIFT 13
 #define SJC16_DDR4_PHY_COMMON_LDO_CONFIG_REF_SEL_EXT_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_COMMON_LDO_CONFIG_REF_EXT_MASK 0x1000
 #define SJC16_DDR4_PHY_COMMON_LDO_CONFIG_REF_EXT_ALIGN 0
 #define SJC16_DDR4_PHY_COMMON_LDO_CONFIG_REF_EXT_BITS 1
 #define SJC16_DDR4_PHY_COMMON_LDO_CONFIG_REF_EXT_SHIFT 12
 #define SJC16_DDR4_PHY_COMMON_LDO_CONFIG_REF_EXT_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_COMMON_LDO_CONFIG_PWRDN_MASK 0x200
 #define SJC16_DDR4_PHY_COMMON_LDO_CONFIG_PWRDN_ALIGN 0
 #define SJC16_DDR4_PHY_COMMON_LDO_CONFIG_PWRDN_BITS 1
 #define SJC16_DDR4_PHY_COMMON_LDO_CONFIG_PWRDN_SHIFT 9
 #define SJC16_DDR4_PHY_COMMON_LDO_CONFIG_PWRDN_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_COMMON_LDO_CONFIG_CTRL_MASK 0x1f8
 #define SJC16_DDR4_PHY_COMMON_LDO_CONFIG_CTRL_ALIGN 0
 #define SJC16_DDR4_PHY_COMMON_LDO_CONFIG_CTRL_BITS 6
 #define SJC16_DDR4_PHY_COMMON_LDO_CONFIG_CTRL_SHIFT 3
 #define SJC16_DDR4_PHY_COMMON_LDO_CONFIG_CTRL_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_COMMON_LDO_CONFIG_BYPASS_MASK 0x4
 #define SJC16_DDR4_PHY_COMMON_LDO_CONFIG_BYPASS_ALIGN 0
 #define SJC16_DDR4_PHY_COMMON_LDO_CONFIG_BYPASS_BITS 1
 #define SJC16_DDR4_PHY_COMMON_LDO_CONFIG_BYPASS_SHIFT 2
 #define SJC16_DDR4_PHY_COMMON_LDO_CONFIG_BYPASS_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_COMMON_LDO_CONFIG_BIAS_CTRL_MASK 0x3
 #define SJC16_DDR4_PHY_COMMON_LDO_CONFIG_BIAS_CTRL_ALIGN 0
 #define SJC16_DDR4_PHY_COMMON_LDO_CONFIG_BIAS_CTRL_BITS 2
 #define SJC16_DDR4_PHY_COMMON_LDO_CONFIG_BIAS_CTRL_SHIFT 0
 #define SJC16_DDR4_PHY_COMMON_LDO_CONFIG_BIAS_CTRL_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_COMMON_LDO_CONFIG_RESERVED_MASK 0xffffc000
 #define SJC16_DDR4_PHY_COMMON_LDO_CONFIG_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_COMMON_LDO_CONFIG_RESERVED_BITS 18
 #define SJC16_DDR4_PHY_COMMON_LDO_CONFIG_RESERVED_SHIFT 14
 #define SJC16_DDR4_PHY_COMMON_LDO_CONFIG_ALL_MASK 0x3fff
 #define SJC16_DDR4_PHY_COMMON_LDO_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_COMMON_LDO_CONFIG_ALL_BITS 14
 #define SJC16_DDR4_PHY_COMMON_LDO_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_COMMON_LDO_CONFIG_ALL_MASK 0x3fff
 #define SJC16_DDR4_PHY_COMMON_LDO_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_COMMON_LDO_CONFIG_ALL_BITS 14
 #define SJC16_DDR4_PHY_COMMON_LDO_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_COMMON_LDO_CONFIG_DATAMASK 0x000033ff
 #define SJC16_DDR4_PHY_COMMON_LDO_CONFIG_RDWRMASK 0xffffcc00
 #define SJC16_DDR4_PHY_COMMON_LDO_CONFIG_RESETVALUE 0x0000
 #define SJC16_DDR4_PHY_COMMON_RESCAL_INIT_CONFIG 0x1023f810
 #define SJC16_DDR4_PHY_COMMON_RESCAL_INIT_CONFIG_BASE 0x810
 #define SJC16_DDR4_PHY_COMMON_RESCAL_INIT_CONFIG_CLK_DIV_RATIO_MASK 0x7000000
 #define SJC16_DDR4_PHY_COMMON_RESCAL_INIT_CONFIG_CLK_DIV_RATIO_ALIGN 0
 #define SJC16_DDR4_PHY_COMMON_RESCAL_INIT_CONFIG_CLK_DIV_RATIO_BITS 3
 #define SJC16_DDR4_PHY_COMMON_RESCAL_INIT_CONFIG_CLK_DIV_RATIO_SHIFT 24
 #define SJC16_DDR4_PHY_COMMON_RESCAL_INIT_CONFIG_CLK_DIV_RATIO_RESETVALUE 0x3
 #define SJC16_DDR4_PHY_COMMON_RESCAL_INIT_CONFIG_COMP_INIT_FDEPTH_MASK 0xf00000
 #define SJC16_DDR4_PHY_COMMON_RESCAL_INIT_CONFIG_COMP_INIT_FDEPTH_ALIGN 0
 #define SJC16_DDR4_PHY_COMMON_RESCAL_INIT_CONFIG_COMP_INIT_FDEPTH_BITS 4
 #define SJC16_DDR4_PHY_COMMON_RESCAL_INIT_CONFIG_COMP_INIT_FDEPTH_SHIFT 20
 #define SJC16_DDR4_PHY_COMMON_RESCAL_INIT_CONFIG_COMP_INIT_FDEPTH_RESETVALUE 0x7
 #define SJC16_DDR4_PHY_COMMON_RESCAL_INIT_CONFIG_COMP_INIT_OFFSET_MASK 0xf8000
 #define SJC16_DDR4_PHY_COMMON_RESCAL_INIT_CONFIG_COMP_INIT_OFFSET_ALIGN 0
 #define SJC16_DDR4_PHY_COMMON_RESCAL_INIT_CONFIG_COMP_INIT_OFFSET_BITS 5
 #define SJC16_DDR4_PHY_COMMON_RESCAL_INIT_CONFIG_COMP_INIT_OFFSET_SHIFT 15
 #define SJC16_DDR4_PHY_COMMON_RESCAL_INIT_CONFIG_COMP_INIT_OFFSET_RESETVALUE 0x2
 #define SJC16_DDR4_PHY_COMMON_RESCAL_INIT_CONFIG_PNCOMP_INIT_DIFF_MASK 0x7c00
 #define SJC16_DDR4_PHY_COMMON_RESCAL_INIT_CONFIG_PNCOMP_INIT_DIFF_ALIGN 0
 #define SJC16_DDR4_PHY_COMMON_RESCAL_INIT_CONFIG_PNCOMP_INIT_DIFF_BITS 5
 #define SJC16_DDR4_PHY_COMMON_RESCAL_INIT_CONFIG_PNCOMP_INIT_DIFF_SHIFT 10
 #define SJC16_DDR4_PHY_COMMON_RESCAL_INIT_CONFIG_PNCOMP_INIT_DIFF_RESETVALUE 0x10
 #define SJC16_DDR4_PHY_COMMON_RESCAL_INIT_CONFIG_NCOMP_INIT_CODE_MASK 0x3e0
 #define SJC16_DDR4_PHY_COMMON_RESCAL_INIT_CONFIG_NCOMP_INIT_CODE_ALIGN 0
 #define SJC16_DDR4_PHY_COMMON_RESCAL_INIT_CONFIG_NCOMP_INIT_CODE_BITS 5
 #define SJC16_DDR4_PHY_COMMON_RESCAL_INIT_CONFIG_NCOMP_INIT_CODE_SHIFT 5
 #define SJC16_DDR4_PHY_COMMON_RESCAL_INIT_CONFIG_NCOMP_INIT_CODE_RESETVALUE 0xf
 #define SJC16_DDR4_PHY_COMMON_RESCAL_INIT_CONFIG_PCOMP_INIT_CODE_MASK 0x1f
 #define SJC16_DDR4_PHY_COMMON_RESCAL_INIT_CONFIG_PCOMP_INIT_CODE_ALIGN 0
 #define SJC16_DDR4_PHY_COMMON_RESCAL_INIT_CONFIG_PCOMP_INIT_CODE_BITS 5
 #define SJC16_DDR4_PHY_COMMON_RESCAL_INIT_CONFIG_PCOMP_INIT_CODE_SHIFT 0
 #define SJC16_DDR4_PHY_COMMON_RESCAL_INIT_CONFIG_PCOMP_INIT_CODE_RESETVALUE 0x10
 #define SJC16_DDR4_PHY_COMMON_RESCAL_INIT_CONFIG_RESERVED_MASK 0xf8000000
 #define SJC16_DDR4_PHY_COMMON_RESCAL_INIT_CONFIG_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_COMMON_RESCAL_INIT_CONFIG_RESERVED_BITS 5
 #define SJC16_DDR4_PHY_COMMON_RESCAL_INIT_CONFIG_RESERVED_SHIFT 27
 #define SJC16_DDR4_PHY_COMMON_RESCAL_INIT_CONFIG_ALL_MASK 0x7ffffff
 #define SJC16_DDR4_PHY_COMMON_RESCAL_INIT_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_COMMON_RESCAL_INIT_CONFIG_ALL_BITS 27
 #define SJC16_DDR4_PHY_COMMON_RESCAL_INIT_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_COMMON_RESCAL_INIT_CONFIG_ALL_MASK 0x7ffffff
 #define SJC16_DDR4_PHY_COMMON_RESCAL_INIT_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_COMMON_RESCAL_INIT_CONFIG_ALL_BITS 27
 #define SJC16_DDR4_PHY_COMMON_RESCAL_INIT_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_COMMON_RESCAL_INIT_CONFIG_DATAMASK 0x07ffffff
 #define SJC16_DDR4_PHY_COMMON_RESCAL_INIT_CONFIG_RDWRMASK 0xf8000000
 #define SJC16_DDR4_PHY_COMMON_RESCAL_INIT_CONFIG_RESETVALUE 0x37141f0
 #define SJC16_DDR4_PHY_COMMON_RESCAL_OPERATION_CONFIG 0x1023f814
 #define SJC16_DDR4_PHY_COMMON_RESCAL_OPERATION_CONFIG_BASE 0x814
 #define SJC16_DDR4_PHY_COMMON_RESCAL_OPERATION_CONFIG_TEST_EN_MASK 0x4000
 #define SJC16_DDR4_PHY_COMMON_RESCAL_OPERATION_CONFIG_TEST_EN_ALIGN 0
 #define SJC16_DDR4_PHY_COMMON_RESCAL_OPERATION_CONFIG_TEST_EN_BITS 1
 #define SJC16_DDR4_PHY_COMMON_RESCAL_OPERATION_CONFIG_TEST_EN_SHIFT 14
 #define SJC16_DDR4_PHY_COMMON_RESCAL_OPERATION_CONFIG_TEST_EN_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_COMMON_RESCAL_OPERATION_CONFIG_MANUAL_OVERRIDE_EN_MASK 0x2000
 #define SJC16_DDR4_PHY_COMMON_RESCAL_OPERATION_CONFIG_MANUAL_OVERRIDE_EN_ALIGN 0
 #define SJC16_DDR4_PHY_COMMON_RESCAL_OPERATION_CONFIG_MANUAL_OVERRIDE_EN_BITS 1
 #define SJC16_DDR4_PHY_COMMON_RESCAL_OPERATION_CONFIG_MANUAL_OVERRIDE_EN_SHIFT 13
 #define SJC16_DDR4_PHY_COMMON_RESCAL_OPERATION_CONFIG_MANUAL_OVERRIDE_EN_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_COMMON_RESCAL_OPERATION_CONFIG_POWERSAVE_EN_MASK 0x1000
 #define SJC16_DDR4_PHY_COMMON_RESCAL_OPERATION_CONFIG_POWERSAVE_EN_ALIGN 0
 #define SJC16_DDR4_PHY_COMMON_RESCAL_OPERATION_CONFIG_POWERSAVE_EN_BITS 1
 #define SJC16_DDR4_PHY_COMMON_RESCAL_OPERATION_CONFIG_POWERSAVE_EN_SHIFT 12
 #define SJC16_DDR4_PHY_COMMON_RESCAL_OPERATION_CONFIG_POWERSAVE_EN_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_COMMON_RESCAL_OPERATION_CONFIG_COMP_EN_MASK 0x800
 #define SJC16_DDR4_PHY_COMMON_RESCAL_OPERATION_CONFIG_COMP_EN_ALIGN 0
 #define SJC16_DDR4_PHY_COMMON_RESCAL_OPERATION_CONFIG_COMP_EN_BITS 1
 #define SJC16_DDR4_PHY_COMMON_RESCAL_OPERATION_CONFIG_COMP_EN_SHIFT 11
 #define SJC16_DDR4_PHY_COMMON_RESCAL_OPERATION_CONFIG_COMP_EN_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_COMMON_RESCAL_OPERATION_CONFIG_COMP_OFFSET_EN_MASK 0x400
 #define SJC16_DDR4_PHY_COMMON_RESCAL_OPERATION_CONFIG_COMP_OFFSET_EN_ALIGN 0
 #define SJC16_DDR4_PHY_COMMON_RESCAL_OPERATION_CONFIG_COMP_OFFSET_EN_BITS 1
 #define SJC16_DDR4_PHY_COMMON_RESCAL_OPERATION_CONFIG_COMP_OFFSET_EN_SHIFT 10
 #define SJC16_DDR4_PHY_COMMON_RESCAL_OPERATION_CONFIG_COMP_OFFSET_EN_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_COMMON_RESCAL_OPERATION_CONFIG_COMP_OFFSET_OP_MASK 0x200
 #define SJC16_DDR4_PHY_COMMON_RESCAL_OPERATION_CONFIG_COMP_OFFSET_OP_ALIGN 0
 #define SJC16_DDR4_PHY_COMMON_RESCAL_OPERATION_CONFIG_COMP_OFFSET_OP_BITS 1
 #define SJC16_DDR4_PHY_COMMON_RESCAL_OPERATION_CONFIG_COMP_OFFSET_OP_SHIFT 9
 #define SJC16_DDR4_PHY_COMMON_RESCAL_OPERATION_CONFIG_COMP_OFFSET_OP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_COMMON_RESCAL_OPERATION_CONFIG_OVERRIDE_EN_MASK 0x100
 #define SJC16_DDR4_PHY_COMMON_RESCAL_OPERATION_CONFIG_OVERRIDE_EN_ALIGN 0
 #define SJC16_DDR4_PHY_COMMON_RESCAL_OPERATION_CONFIG_OVERRIDE_EN_BITS 1
 #define SJC16_DDR4_PHY_COMMON_RESCAL_OPERATION_CONFIG_OVERRIDE_EN_SHIFT 8
 #define SJC16_DDR4_PHY_COMMON_RESCAL_OPERATION_CONFIG_OVERRIDE_EN_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_COMMON_RESCAL_OPERATION_CONFIG_OVERRIDE_MODE_MASK 0xe0
 #define SJC16_DDR4_PHY_COMMON_RESCAL_OPERATION_CONFIG_OVERRIDE_MODE_ALIGN 0
 #define SJC16_DDR4_PHY_COMMON_RESCAL_OPERATION_CONFIG_OVERRIDE_MODE_BITS 3
 #define SJC16_DDR4_PHY_COMMON_RESCAL_OPERATION_CONFIG_OVERRIDE_MODE_SHIFT 5
 #define SJC16_DDR4_PHY_COMMON_RESCAL_OPERATION_CONFIG_OVERRIDE_MODE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_COMMON_RESCAL_OPERATION_CONFIG_OVERRIDE_VALUE_MASK 0x1f
 #define SJC16_DDR4_PHY_COMMON_RESCAL_OPERATION_CONFIG_OVERRIDE_VALUE_ALIGN 0
 #define SJC16_DDR4_PHY_COMMON_RESCAL_OPERATION_CONFIG_OVERRIDE_VALUE_BITS 5
 #define SJC16_DDR4_PHY_COMMON_RESCAL_OPERATION_CONFIG_OVERRIDE_VALUE_SHIFT 0
 #define SJC16_DDR4_PHY_COMMON_RESCAL_OPERATION_CONFIG_OVERRIDE_VALUE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_COMMON_RESCAL_OPERATION_CONFIG_RESERVED_MASK 0xffff8000
 #define SJC16_DDR4_PHY_COMMON_RESCAL_OPERATION_CONFIG_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_COMMON_RESCAL_OPERATION_CONFIG_RESERVED_BITS 17
 #define SJC16_DDR4_PHY_COMMON_RESCAL_OPERATION_CONFIG_RESERVED_SHIFT 15
 #define SJC16_DDR4_PHY_COMMON_RESCAL_OPERATION_CONFIG_ALL_MASK 0x7fff
 #define SJC16_DDR4_PHY_COMMON_RESCAL_OPERATION_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_COMMON_RESCAL_OPERATION_CONFIG_ALL_BITS 15
 #define SJC16_DDR4_PHY_COMMON_RESCAL_OPERATION_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_COMMON_RESCAL_OPERATION_CONFIG_ALL_MASK 0x7fff
 #define SJC16_DDR4_PHY_COMMON_RESCAL_OPERATION_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_COMMON_RESCAL_OPERATION_CONFIG_ALL_BITS 15
 #define SJC16_DDR4_PHY_COMMON_RESCAL_OPERATION_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_COMMON_RESCAL_OPERATION_CONFIG_DATAMASK 0x00007fff
 #define SJC16_DDR4_PHY_COMMON_RESCAL_OPERATION_CONFIG_RDWRMASK 0xffff8000
 #define SJC16_DDR4_PHY_COMMON_RESCAL_OPERATION_CONFIG_RESETVALUE 0x0000
 #define SJC16_DDR4_PHY_COMMON_STATUS_RESCAL 0x1023f818
 #define SJC16_DDR4_PHY_COMMON_STATUS_RESCAL_BASE 0x818
 #define SJC16_DDR4_PHY_COMMON_STATUS_RESCAL_NCOMP_DIN_MASK 0x800000
 #define SJC16_DDR4_PHY_COMMON_STATUS_RESCAL_NCOMP_DIN_ALIGN 0
 #define SJC16_DDR4_PHY_COMMON_STATUS_RESCAL_NCOMP_DIN_BITS 1
 #define SJC16_DDR4_PHY_COMMON_STATUS_RESCAL_NCOMP_DIN_SHIFT 23
 #define SJC16_DDR4_PHY_COMMON_STATUS_RESCAL_NCOMP_DIN_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_COMMON_STATUS_RESCAL_PCOMP_DIN_MASK 0x400000
 #define SJC16_DDR4_PHY_COMMON_STATUS_RESCAL_PCOMP_DIN_ALIGN 0
 #define SJC16_DDR4_PHY_COMMON_STATUS_RESCAL_PCOMP_DIN_BITS 1
 #define SJC16_DDR4_PHY_COMMON_STATUS_RESCAL_PCOMP_DIN_SHIFT 22
 #define SJC16_DDR4_PHY_COMMON_STATUS_RESCAL_PCOMP_DIN_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_COMMON_STATUS_RESCAL_NCOMP_CODE_2CORE_MASK 0x3e0000
 #define SJC16_DDR4_PHY_COMMON_STATUS_RESCAL_NCOMP_CODE_2CORE_ALIGN 0
 #define SJC16_DDR4_PHY_COMMON_STATUS_RESCAL_NCOMP_CODE_2CORE_BITS 5
 #define SJC16_DDR4_PHY_COMMON_STATUS_RESCAL_NCOMP_CODE_2CORE_SHIFT 17
 #define SJC16_DDR4_PHY_COMMON_STATUS_RESCAL_NCOMP_CODE_2CORE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_COMMON_STATUS_RESCAL_PCOMP_CODE_2CORE_MASK 0x1f000
 #define SJC16_DDR4_PHY_COMMON_STATUS_RESCAL_PCOMP_CODE_2CORE_ALIGN 0
 #define SJC16_DDR4_PHY_COMMON_STATUS_RESCAL_PCOMP_CODE_2CORE_BITS 5
 #define SJC16_DDR4_PHY_COMMON_STATUS_RESCAL_PCOMP_CODE_2CORE_SHIFT 12
 #define SJC16_DDR4_PHY_COMMON_STATUS_RESCAL_PCOMP_CODE_2CORE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_COMMON_STATUS_RESCAL_NDONE_2CORE_MASK 0x800
 #define SJC16_DDR4_PHY_COMMON_STATUS_RESCAL_NDONE_2CORE_ALIGN 0
 #define SJC16_DDR4_PHY_COMMON_STATUS_RESCAL_NDONE_2CORE_BITS 1
 #define SJC16_DDR4_PHY_COMMON_STATUS_RESCAL_NDONE_2CORE_SHIFT 11
 #define SJC16_DDR4_PHY_COMMON_STATUS_RESCAL_NDONE_2CORE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_COMMON_STATUS_RESCAL_PDONE_2CORE_MASK 0x400
 #define SJC16_DDR4_PHY_COMMON_STATUS_RESCAL_PDONE_2CORE_ALIGN 0
 #define SJC16_DDR4_PHY_COMMON_STATUS_RESCAL_PDONE_2CORE_BITS 1
 #define SJC16_DDR4_PHY_COMMON_STATUS_RESCAL_PDONE_2CORE_SHIFT 10
 #define SJC16_DDR4_PHY_COMMON_STATUS_RESCAL_PDONE_2CORE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_COMMON_STATUS_RESCAL_NCOMP_ENB_2CORE_MASK 0x200
 #define SJC16_DDR4_PHY_COMMON_STATUS_RESCAL_NCOMP_ENB_2CORE_ALIGN 0
 #define SJC16_DDR4_PHY_COMMON_STATUS_RESCAL_NCOMP_ENB_2CORE_BITS 1
 #define SJC16_DDR4_PHY_COMMON_STATUS_RESCAL_NCOMP_ENB_2CORE_SHIFT 9
 #define SJC16_DDR4_PHY_COMMON_STATUS_RESCAL_NCOMP_ENB_2CORE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_COMMON_STATUS_RESCAL_PCOMP_ENB_2CORE_MASK 0x100
 #define SJC16_DDR4_PHY_COMMON_STATUS_RESCAL_PCOMP_ENB_2CORE_ALIGN 0
 #define SJC16_DDR4_PHY_COMMON_STATUS_RESCAL_PCOMP_ENB_2CORE_BITS 1
 #define SJC16_DDR4_PHY_COMMON_STATUS_RESCAL_PCOMP_ENB_2CORE_SHIFT 8
 #define SJC16_DDR4_PHY_COMMON_STATUS_RESCAL_PCOMP_ENB_2CORE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_COMMON_STATUS_RESCAL_COMP_ERROR_MASK 0xfc
 #define SJC16_DDR4_PHY_COMMON_STATUS_RESCAL_COMP_ERROR_ALIGN 0
 #define SJC16_DDR4_PHY_COMMON_STATUS_RESCAL_COMP_ERROR_BITS 6
 #define SJC16_DDR4_PHY_COMMON_STATUS_RESCAL_COMP_ERROR_SHIFT 2
 #define SJC16_DDR4_PHY_COMMON_STATUS_RESCAL_COMP_ERROR_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_COMMON_STATUS_RESCAL_COMP_DONE_MASK 0x2
 #define SJC16_DDR4_PHY_COMMON_STATUS_RESCAL_COMP_DONE_ALIGN 0
 #define SJC16_DDR4_PHY_COMMON_STATUS_RESCAL_COMP_DONE_BITS 1
 #define SJC16_DDR4_PHY_COMMON_STATUS_RESCAL_COMP_DONE_SHIFT 1
 #define SJC16_DDR4_PHY_COMMON_STATUS_RESCAL_COMP_DONE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_COMMON_STATUS_RESCAL_COMP_ACK_MASK 0x1
 #define SJC16_DDR4_PHY_COMMON_STATUS_RESCAL_COMP_ACK_ALIGN 0
 #define SJC16_DDR4_PHY_COMMON_STATUS_RESCAL_COMP_ACK_BITS 1
 #define SJC16_DDR4_PHY_COMMON_STATUS_RESCAL_COMP_ACK_SHIFT 0
 #define SJC16_DDR4_PHY_COMMON_STATUS_RESCAL_COMP_ACK_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_COMMON_STATUS_RESCAL_RESERVED_MASK 0xff000000
 #define SJC16_DDR4_PHY_COMMON_STATUS_RESCAL_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_COMMON_STATUS_RESCAL_RESERVED_BITS 8
 #define SJC16_DDR4_PHY_COMMON_STATUS_RESCAL_RESERVED_SHIFT 24
 #define SJC16_DDR4_PHY_COMMON_STATUS_RESCAL_ALL_MASK 0xffffff
 #define SJC16_DDR4_PHY_COMMON_STATUS_RESCAL_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_COMMON_STATUS_RESCAL_ALL_BITS 24
 #define SJC16_DDR4_PHY_COMMON_STATUS_RESCAL_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_COMMON_STATUS_RESCAL_ALL_MASK 0xffffff
 #define SJC16_DDR4_PHY_COMMON_STATUS_RESCAL_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_COMMON_STATUS_RESCAL_ALL_BITS 24
 #define SJC16_DDR4_PHY_COMMON_STATUS_RESCAL_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_COMMON_STATUS_RESCAL_DATAMASK 0x00ffffff
 #define SJC16_DDR4_PHY_COMMON_STATUS_RESCAL_RDWRMASK 0xff000000
 #define SJC16_DDR4_PHY_COMMON_STATUS_RESCAL_RESETVALUE 0x000000
 #define SJC16_DDR4_PHY_COMMON_MACRO_RESERVED_REG 0x1023f81c
 #define SJC16_DDR4_PHY_COMMON_MACRO_RESERVED_REG_BASE 0x81c
 #define SJC16_DDR4_PHY_COMMON_MACRO_RESERVED_REG_RESERVED_MASK 0xffffffff
 #define SJC16_DDR4_PHY_COMMON_MACRO_RESERVED_REG_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_COMMON_MACRO_RESERVED_REG_RESERVED_BITS 32
 #define SJC16_DDR4_PHY_COMMON_MACRO_RESERVED_REG_RESERVED_SHIFT 0
 #define SJC16_DDR4_PHY_COMMON_MACRO_RESERVED_REG_RESERVED_RESETVALUE 0x00000000
 #define SJC16_DDR4_PHY_COMMON_MACRO_RESERVED_REG_ALL_MASK 0xffffffff
 #define SJC16_DDR4_PHY_COMMON_MACRO_RESERVED_REG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_COMMON_MACRO_RESERVED_REG_ALL_BITS 32
 #define SJC16_DDR4_PHY_COMMON_MACRO_RESERVED_REG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_COMMON_MACRO_RESERVED_REG_ALL_MASK 0xffffffff
 #define SJC16_DDR4_PHY_COMMON_MACRO_RESERVED_REG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_COMMON_MACRO_RESERVED_REG_ALL_BITS 32
 #define SJC16_DDR4_PHY_COMMON_MACRO_RESERVED_REG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_COMMON_MACRO_RESERVED_REG_DATAMASK 0xffffffff
 #define SJC16_DDR4_PHY_COMMON_MACRO_RESERVED_REG_RDWRMASK 0x00000000
 #define SJC16_DDR4_PHY_COMMON_MACRO_RESERVED_REG_RESETVALUE 0x00000000
 #define SJC16_DDR4_PHY_COMMON_STATUS_MACRO_RESERVED 0x1023f820
 #define SJC16_DDR4_PHY_COMMON_STATUS_MACRO_RESERVED_BASE 0x820
 #define SJC16_DDR4_PHY_COMMON_STATUS_MACRO_RESERVED_RESERVED_MASK 0xffffffff
 #define SJC16_DDR4_PHY_COMMON_STATUS_MACRO_RESERVED_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_COMMON_STATUS_MACRO_RESERVED_RESERVED_BITS 32
 #define SJC16_DDR4_PHY_COMMON_STATUS_MACRO_RESERVED_RESERVED_SHIFT 0
 #define SJC16_DDR4_PHY_COMMON_STATUS_MACRO_RESERVED_RESERVED_RESETVALUE 0x00000000
 #define SJC16_DDR4_PHY_COMMON_STATUS_MACRO_RESERVED_ALL_MASK 0xffffffff
 #define SJC16_DDR4_PHY_COMMON_STATUS_MACRO_RESERVED_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_COMMON_STATUS_MACRO_RESERVED_ALL_BITS 32
 #define SJC16_DDR4_PHY_COMMON_STATUS_MACRO_RESERVED_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_COMMON_STATUS_MACRO_RESERVED_ALL_MASK 0xffffffff
 #define SJC16_DDR4_PHY_COMMON_STATUS_MACRO_RESERVED_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_COMMON_STATUS_MACRO_RESERVED_ALL_BITS 32
 #define SJC16_DDR4_PHY_COMMON_STATUS_MACRO_RESERVED_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_COMMON_STATUS_MACRO_RESERVED_DATAMASK 0xffffffff
 #define SJC16_DDR4_PHY_COMMON_STATUS_MACRO_RESERVED_RDWRMASK 0x00000000
 #define SJC16_DDR4_PHY_COMMON_STATUS_MACRO_RESERVED_RESETVALUE 0x00000000
 #define SJC16_DDR4_PHY_CONTROL_REGS_REVISION 0x1023fc00
 #define SJC16_DDR4_PHY_CONTROL_REGS_REVISION_BASE 0xc00
 #define SJC16_DDR4_PHY_CONTROL_REGS_REVISION_MAJOR_MASK 0xff00
 #define SJC16_DDR4_PHY_CONTROL_REGS_REVISION_MAJOR_ALIGN 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_REVISION_MAJOR_BITS 8
 #define SJC16_DDR4_PHY_CONTROL_REGS_REVISION_MAJOR_SHIFT 8
 #define SJC16_DDR4_PHY_CONTROL_REGS_REVISION_MAJOR_RESETVALUE 0xb0
 #define SJC16_DDR4_PHY_CONTROL_REGS_REVISION_MINOR_MASK 0xff
 #define SJC16_DDR4_PHY_CONTROL_REGS_REVISION_MINOR_ALIGN 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_REVISION_MINOR_BITS 8
 #define SJC16_DDR4_PHY_CONTROL_REGS_REVISION_MINOR_SHIFT 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_REVISION_MINOR_RESETVALUE 0x4c
 #define SJC16_DDR4_PHY_CONTROL_REGS_REVISION_RESERVED_MASK 0xffff0000
 #define SJC16_DDR4_PHY_CONTROL_REGS_REVISION_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_REVISION_RESERVED_BITS 16
 #define SJC16_DDR4_PHY_CONTROL_REGS_REVISION_RESERVED_SHIFT 16
 #define SJC16_DDR4_PHY_CONTROL_REGS_REVISION_ALL_MASK 0xffff
 #define SJC16_DDR4_PHY_CONTROL_REGS_REVISION_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_REVISION_ALL_BITS 16
 #define SJC16_DDR4_PHY_CONTROL_REGS_REVISION_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_REVISION_ALL_MASK 0xffff
 #define SJC16_DDR4_PHY_CONTROL_REGS_REVISION_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_REVISION_ALL_BITS 16
 #define SJC16_DDR4_PHY_CONTROL_REGS_REVISION_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_REVISION_DATAMASK 0x0000ffff
 #define SJC16_DDR4_PHY_CONTROL_REGS_REVISION_RDWRMASK 0xffff0000
 #define SJC16_DDR4_PHY_CONTROL_REGS_REVISION_RESETVALUE 0xb04c
 #define SJC16_DDR4_PHY_CONTROL_REGS_RESET_CTRL 0x1023fc04
 #define SJC16_DDR4_PHY_CONTROL_REGS_RESET_CTRL_BASE 0xc04
 #define SJC16_DDR4_PHY_CONTROL_REGS_RESET_CTRL_CLOCK_DIV_RESET_N_MASK 0x800
 #define SJC16_DDR4_PHY_CONTROL_REGS_RESET_CTRL_CLOCK_DIV_RESET_N_ALIGN 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_RESET_CTRL_CLOCK_DIV_RESET_N_BITS 1
 #define SJC16_DDR4_PHY_CONTROL_REGS_RESET_CTRL_CLOCK_DIV_RESET_N_SHIFT 11
 #define SJC16_DDR4_PHY_CONTROL_REGS_RESET_CTRL_CLOCK_DIV_RESET_N_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_CONTROL_REGS_RESET_CTRL_VDL_1G_RESET_N_MASK 0x400
 #define SJC16_DDR4_PHY_CONTROL_REGS_RESET_CTRL_VDL_1G_RESET_N_ALIGN 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_RESET_CTRL_VDL_1G_RESET_N_BITS 1
 #define SJC16_DDR4_PHY_CONTROL_REGS_RESET_CTRL_VDL_1G_RESET_N_SHIFT 10
 #define SJC16_DDR4_PHY_CONTROL_REGS_RESET_CTRL_VDL_1G_RESET_N_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_CONTROL_REGS_RESET_CTRL_FREQ_CNTR_RO_RESET_N_MASK 0x200
 #define SJC16_DDR4_PHY_CONTROL_REGS_RESET_CTRL_FREQ_CNTR_RO_RESET_N_ALIGN 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_RESET_CTRL_FREQ_CNTR_RO_RESET_N_BITS 1
 #define SJC16_DDR4_PHY_CONTROL_REGS_RESET_CTRL_FREQ_CNTR_RO_RESET_N_SHIFT 9
 #define SJC16_DDR4_PHY_CONTROL_REGS_RESET_CTRL_FREQ_CNTR_RO_RESET_N_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_CONTROL_REGS_RESET_CTRL_FREQ_CNTR_FC_RESET_N_MASK 0x100
 #define SJC16_DDR4_PHY_CONTROL_REGS_RESET_CTRL_FREQ_CNTR_FC_RESET_N_ALIGN 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_RESET_CTRL_FREQ_CNTR_FC_RESET_N_BITS 1
 #define SJC16_DDR4_PHY_CONTROL_REGS_RESET_CTRL_FREQ_CNTR_FC_RESET_N_SHIFT 8
 #define SJC16_DDR4_PHY_CONTROL_REGS_RESET_CTRL_FREQ_CNTR_FC_RESET_N_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_CONTROL_REGS_RESET_CTRL_RESCAL_RESET_N_MASK 0x80
 #define SJC16_DDR4_PHY_CONTROL_REGS_RESET_CTRL_RESCAL_RESET_N_ALIGN 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_RESET_CTRL_RESCAL_RESET_N_BITS 1
 #define SJC16_DDR4_PHY_CONTROL_REGS_RESET_CTRL_RESCAL_RESET_N_SHIFT 7
 #define SJC16_DDR4_PHY_CONTROL_REGS_RESET_CTRL_RESCAL_RESET_N_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_CONTROL_REGS_RESET_CTRL_CDR_RESET_N_MASK 0x40
 #define SJC16_DDR4_PHY_CONTROL_REGS_RESET_CTRL_CDR_RESET_N_ALIGN 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_RESET_CTRL_CDR_RESET_N_BITS 1
 #define SJC16_DDR4_PHY_CONTROL_REGS_RESET_CTRL_CDR_RESET_N_SHIFT 6
 #define SJC16_DDR4_PHY_CONTROL_REGS_RESET_CTRL_CDR_RESET_N_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_CONTROL_REGS_RESET_CTRL_READ_FIFO_RESET_N_MASK 0x20
 #define SJC16_DDR4_PHY_CONTROL_REGS_RESET_CTRL_READ_FIFO_RESET_N_ALIGN 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_RESET_CTRL_READ_FIFO_RESET_N_BITS 1
 #define SJC16_DDR4_PHY_CONTROL_REGS_RESET_CTRL_READ_FIFO_RESET_N_SHIFT 5
 #define SJC16_DDR4_PHY_CONTROL_REGS_RESET_CTRL_READ_FIFO_RESET_N_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_CONTROL_REGS_RESET_CTRL_RCMD_FIFO_RESET_N_MASK 0x10
 #define SJC16_DDR4_PHY_CONTROL_REGS_RESET_CTRL_RCMD_FIFO_RESET_N_ALIGN 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_RESET_CTRL_RCMD_FIFO_RESET_N_BITS 1
 #define SJC16_DDR4_PHY_CONTROL_REGS_RESET_CTRL_RCMD_FIFO_RESET_N_SHIFT 4
 #define SJC16_DDR4_PHY_CONTROL_REGS_RESET_CTRL_RCMD_FIFO_RESET_N_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_CONTROL_REGS_RESET_CTRL_DDR4_GLUE_RESET_N_MASK 0x8
 #define SJC16_DDR4_PHY_CONTROL_REGS_RESET_CTRL_DDR4_GLUE_RESET_N_ALIGN 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_RESET_CTRL_DDR4_GLUE_RESET_N_BITS 1
 #define SJC16_DDR4_PHY_CONTROL_REGS_RESET_CTRL_DDR4_GLUE_RESET_N_SHIFT 3
 #define SJC16_DDR4_PHY_CONTROL_REGS_RESET_CTRL_DDR4_GLUE_RESET_N_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_CONTROL_REGS_RESET_CTRL_PHY_2G_RESET_N_MASK 0x4
 #define SJC16_DDR4_PHY_CONTROL_REGS_RESET_CTRL_PHY_2G_RESET_N_ALIGN 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_RESET_CTRL_PHY_2G_RESET_N_BITS 1
 #define SJC16_DDR4_PHY_CONTROL_REGS_RESET_CTRL_PHY_2G_RESET_N_SHIFT 2
 #define SJC16_DDR4_PHY_CONTROL_REGS_RESET_CTRL_PHY_2G_RESET_N_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_CONTROL_REGS_RESET_CTRL_PHY_1G_RESET_N_MASK 0x2
 #define SJC16_DDR4_PHY_CONTROL_REGS_RESET_CTRL_PHY_1G_RESET_N_ALIGN 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_RESET_CTRL_PHY_1G_RESET_N_BITS 1
 #define SJC16_DDR4_PHY_CONTROL_REGS_RESET_CTRL_PHY_1G_RESET_N_SHIFT 1
 #define SJC16_DDR4_PHY_CONTROL_REGS_RESET_CTRL_PHY_1G_RESET_N_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_CONTROL_REGS_RESET_CTRL_DRC_1G_RESET_N_MASK 0x1
 #define SJC16_DDR4_PHY_CONTROL_REGS_RESET_CTRL_DRC_1G_RESET_N_ALIGN 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_RESET_CTRL_DRC_1G_RESET_N_BITS 1
 #define SJC16_DDR4_PHY_CONTROL_REGS_RESET_CTRL_DRC_1G_RESET_N_SHIFT 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_RESET_CTRL_DRC_1G_RESET_N_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_CONTROL_REGS_RESET_CTRL_RESERVED_MASK 0xfffff000
 #define SJC16_DDR4_PHY_CONTROL_REGS_RESET_CTRL_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_RESET_CTRL_RESERVED_BITS 20
 #define SJC16_DDR4_PHY_CONTROL_REGS_RESET_CTRL_RESERVED_SHIFT 12
 #define SJC16_DDR4_PHY_CONTROL_REGS_RESET_CTRL_ALL_MASK 0xfff
 #define SJC16_DDR4_PHY_CONTROL_REGS_RESET_CTRL_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_RESET_CTRL_ALL_BITS 12
 #define SJC16_DDR4_PHY_CONTROL_REGS_RESET_CTRL_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_RESET_CTRL_ALL_MASK 0xfff
 #define SJC16_DDR4_PHY_CONTROL_REGS_RESET_CTRL_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_RESET_CTRL_ALL_BITS 12
 #define SJC16_DDR4_PHY_CONTROL_REGS_RESET_CTRL_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_RESET_CTRL_DATAMASK 0x00000fff
 #define SJC16_DDR4_PHY_CONTROL_REGS_RESET_CTRL_RDWRMASK 0xfffff000
 #define SJC16_DDR4_PHY_CONTROL_REGS_RESET_CTRL_RESETVALUE 0x000
 #define SJC16_DDR4_PHY_CONTROL_REGS_READ_FIFO_CTRL 0x1023fc08
 #define SJC16_DDR4_PHY_CONTROL_REGS_READ_FIFO_CTRL_BASE 0xc08
 #define SJC16_DDR4_PHY_CONTROL_REGS_READ_FIFO_CTRL_ENABLE_MASK 0x2
 #define SJC16_DDR4_PHY_CONTROL_REGS_READ_FIFO_CTRL_ENABLE_ALIGN 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_READ_FIFO_CTRL_ENABLE_BITS 1
 #define SJC16_DDR4_PHY_CONTROL_REGS_READ_FIFO_CTRL_ENABLE_SHIFT 1
 #define SJC16_DDR4_PHY_CONTROL_REGS_READ_FIFO_CTRL_ENABLE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_CONTROL_REGS_READ_FIFO_CTRL_W2R_MIN_DELAY_2_MASK 0x1
 #define SJC16_DDR4_PHY_CONTROL_REGS_READ_FIFO_CTRL_W2R_MIN_DELAY_2_ALIGN 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_READ_FIFO_CTRL_W2R_MIN_DELAY_2_BITS 1
 #define SJC16_DDR4_PHY_CONTROL_REGS_READ_FIFO_CTRL_W2R_MIN_DELAY_2_SHIFT 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_READ_FIFO_CTRL_W2R_MIN_DELAY_2_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_CONTROL_REGS_READ_FIFO_CTRL_RESERVED_MASK 0xfffffffc
 #define SJC16_DDR4_PHY_CONTROL_REGS_READ_FIFO_CTRL_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_READ_FIFO_CTRL_RESERVED_BITS 30
 #define SJC16_DDR4_PHY_CONTROL_REGS_READ_FIFO_CTRL_RESERVED_SHIFT 2
 #define SJC16_DDR4_PHY_CONTROL_REGS_READ_FIFO_CTRL_ALL_MASK 0x3
 #define SJC16_DDR4_PHY_CONTROL_REGS_READ_FIFO_CTRL_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_READ_FIFO_CTRL_ALL_BITS 2
 #define SJC16_DDR4_PHY_CONTROL_REGS_READ_FIFO_CTRL_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_READ_FIFO_CTRL_ALL_MASK 0x3
 #define SJC16_DDR4_PHY_CONTROL_REGS_READ_FIFO_CTRL_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_READ_FIFO_CTRL_ALL_BITS 2
 #define SJC16_DDR4_PHY_CONTROL_REGS_READ_FIFO_CTRL_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_READ_FIFO_CTRL_DATAMASK 0x00000003
 #define SJC16_DDR4_PHY_CONTROL_REGS_READ_FIFO_CTRL_RDWRMASK 0xfffffffc
 #define SJC16_DDR4_PHY_CONTROL_REGS_READ_FIFO_CTRL_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_CONTROL_REGS_WRITE_FIFO_CTRL 0x1023fc0c
 #define SJC16_DDR4_PHY_CONTROL_REGS_WRITE_FIFO_CTRL_BASE 0xc0c
 #define SJC16_DDR4_PHY_CONTROL_REGS_WRITE_FIFO_CTRL_W2R_MIN_DELAY_2_MASK 0x1
 #define SJC16_DDR4_PHY_CONTROL_REGS_WRITE_FIFO_CTRL_W2R_MIN_DELAY_2_ALIGN 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_WRITE_FIFO_CTRL_W2R_MIN_DELAY_2_BITS 1
 #define SJC16_DDR4_PHY_CONTROL_REGS_WRITE_FIFO_CTRL_W2R_MIN_DELAY_2_SHIFT 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_WRITE_FIFO_CTRL_W2R_MIN_DELAY_2_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_CONTROL_REGS_WRITE_FIFO_CTRL_RESERVED_MASK 0xfffffffe
 #define SJC16_DDR4_PHY_CONTROL_REGS_WRITE_FIFO_CTRL_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_WRITE_FIFO_CTRL_RESERVED_BITS 31
 #define SJC16_DDR4_PHY_CONTROL_REGS_WRITE_FIFO_CTRL_RESERVED_SHIFT 1
 #define SJC16_DDR4_PHY_CONTROL_REGS_WRITE_FIFO_CTRL_W2R_MIN_DELAY_2_MASK 0x1
 #define SJC16_DDR4_PHY_CONTROL_REGS_WRITE_FIFO_CTRL_W2R_MIN_DELAY_2_ALIGN 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_WRITE_FIFO_CTRL_W2R_MIN_DELAY_2_BITS 1
 #define SJC16_DDR4_PHY_CONTROL_REGS_WRITE_FIFO_CTRL_W2R_MIN_DELAY_2_SHIFT 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_WRITE_FIFO_CTRL_W2R_MIN_DELAY_2_MASK 0x1
 #define SJC16_DDR4_PHY_CONTROL_REGS_WRITE_FIFO_CTRL_W2R_MIN_DELAY_2_ALIGN 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_WRITE_FIFO_CTRL_W2R_MIN_DELAY_2_BITS 1
 #define SJC16_DDR4_PHY_CONTROL_REGS_WRITE_FIFO_CTRL_W2R_MIN_DELAY_2_SHIFT 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_WRITE_FIFO_CTRL_ALL_MASK 0x1
 #define SJC16_DDR4_PHY_CONTROL_REGS_WRITE_FIFO_CTRL_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_WRITE_FIFO_CTRL_ALL_BITS 1
 #define SJC16_DDR4_PHY_CONTROL_REGS_WRITE_FIFO_CTRL_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_WRITE_FIFO_CTRL_ALL_MASK 0x1
 #define SJC16_DDR4_PHY_CONTROL_REGS_WRITE_FIFO_CTRL_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_WRITE_FIFO_CTRL_ALL_BITS 1
 #define SJC16_DDR4_PHY_CONTROL_REGS_WRITE_FIFO_CTRL_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_WRITE_FIFO_CTRL_DATAMASK 0x00000001
 #define SJC16_DDR4_PHY_CONTROL_REGS_WRITE_FIFO_CTRL_RDWRMASK 0xfffffffe
 #define SJC16_DDR4_PHY_CONTROL_REGS_WRITE_FIFO_CTRL_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_CONTROL_REGS_READ_CLOCK_CONFIG 0x1023fc10
 #define SJC16_DDR4_PHY_CONTROL_REGS_READ_CLOCK_CONFIG_BASE 0xc10
 #define SJC16_DDR4_PHY_CONTROL_REGS_READ_CLOCK_CONFIG_FREE_RUNNING_MODE_MASK 0x1
 #define SJC16_DDR4_PHY_CONTROL_REGS_READ_CLOCK_CONFIG_FREE_RUNNING_MODE_ALIGN 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_READ_CLOCK_CONFIG_FREE_RUNNING_MODE_BITS 1
 #define SJC16_DDR4_PHY_CONTROL_REGS_READ_CLOCK_CONFIG_FREE_RUNNING_MODE_SHIFT 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_READ_CLOCK_CONFIG_FREE_RUNNING_MODE_RESETVALUE 0x1
 #define SJC16_DDR4_PHY_CONTROL_REGS_READ_CLOCK_CONFIG_RESERVED_MASK 0xfffffffe
 #define SJC16_DDR4_PHY_CONTROL_REGS_READ_CLOCK_CONFIG_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_READ_CLOCK_CONFIG_RESERVED_BITS 31
 #define SJC16_DDR4_PHY_CONTROL_REGS_READ_CLOCK_CONFIG_RESERVED_SHIFT 1
 #define SJC16_DDR4_PHY_CONTROL_REGS_READ_CLOCK_CONFIG_FREE_RUNNING_MODE_MASK 0x1
 #define SJC16_DDR4_PHY_CONTROL_REGS_READ_CLOCK_CONFIG_FREE_RUNNING_MODE_ALIGN 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_READ_CLOCK_CONFIG_FREE_RUNNING_MODE_BITS 1
 #define SJC16_DDR4_PHY_CONTROL_REGS_READ_CLOCK_CONFIG_FREE_RUNNING_MODE_SHIFT 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_READ_CLOCK_CONFIG_FREE_RUNNING_MODE_MASK 0x1
 #define SJC16_DDR4_PHY_CONTROL_REGS_READ_CLOCK_CONFIG_FREE_RUNNING_MODE_ALIGN 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_READ_CLOCK_CONFIG_FREE_RUNNING_MODE_BITS 1
 #define SJC16_DDR4_PHY_CONTROL_REGS_READ_CLOCK_CONFIG_FREE_RUNNING_MODE_SHIFT 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_READ_CLOCK_CONFIG_ALL_MASK 0x1
 #define SJC16_DDR4_PHY_CONTROL_REGS_READ_CLOCK_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_READ_CLOCK_CONFIG_ALL_BITS 1
 #define SJC16_DDR4_PHY_CONTROL_REGS_READ_CLOCK_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_READ_CLOCK_CONFIG_ALL_MASK 0x1
 #define SJC16_DDR4_PHY_CONTROL_REGS_READ_CLOCK_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_READ_CLOCK_CONFIG_ALL_BITS 1
 #define SJC16_DDR4_PHY_CONTROL_REGS_READ_CLOCK_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_READ_CLOCK_CONFIG_DATAMASK 0x00000001
 #define SJC16_DDR4_PHY_CONTROL_REGS_READ_CLOCK_CONFIG_RDWRMASK 0xfffffffe
 #define SJC16_DDR4_PHY_CONTROL_REGS_READ_CLOCK_CONFIG_RESETVALUE 0x1
 #define SJC16_DDR4_PHY_CONTROL_REGS_INPUT_SHIFT_CTRL 0x1023fc14
 #define SJC16_DDR4_PHY_CONTROL_REGS_INPUT_SHIFT_CTRL_BASE 0xc14
 #define SJC16_DDR4_PHY_CONTROL_REGS_INPUT_SHIFT_CTRL_RCMD_ADDITIONAL_LATENCY_MASK 0x7e00
 #define SJC16_DDR4_PHY_CONTROL_REGS_INPUT_SHIFT_CTRL_RCMD_ADDITIONAL_LATENCY_ALIGN 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_INPUT_SHIFT_CTRL_RCMD_ADDITIONAL_LATENCY_BITS 6
 #define SJC16_DDR4_PHY_CONTROL_REGS_INPUT_SHIFT_CTRL_RCMD_ADDITIONAL_LATENCY_SHIFT 9
 #define SJC16_DDR4_PHY_CONTROL_REGS_INPUT_SHIFT_CTRL_RCMD_ADDITIONAL_LATENCY_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_CONTROL_REGS_INPUT_SHIFT_CTRL_RCMD_SHIFT_ENABLE_MASK 0x100
 #define SJC16_DDR4_PHY_CONTROL_REGS_INPUT_SHIFT_CTRL_RCMD_SHIFT_ENABLE_ALIGN 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_INPUT_SHIFT_CTRL_RCMD_SHIFT_ENABLE_BITS 1
 #define SJC16_DDR4_PHY_CONTROL_REGS_INPUT_SHIFT_CTRL_RCMD_SHIFT_ENABLE_SHIFT 8
 #define SJC16_DDR4_PHY_CONTROL_REGS_INPUT_SHIFT_CTRL_RCMD_SHIFT_ENABLE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_CONTROL_REGS_INPUT_SHIFT_CTRL_ADDRPATH_ADDITIONAL_LATENCY_MASK 0xe0
 #define SJC16_DDR4_PHY_CONTROL_REGS_INPUT_SHIFT_CTRL_ADDRPATH_ADDITIONAL_LATENCY_ALIGN 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_INPUT_SHIFT_CTRL_ADDRPATH_ADDITIONAL_LATENCY_BITS 3
 #define SJC16_DDR4_PHY_CONTROL_REGS_INPUT_SHIFT_CTRL_ADDRPATH_ADDITIONAL_LATENCY_SHIFT 5
 #define SJC16_DDR4_PHY_CONTROL_REGS_INPUT_SHIFT_CTRL_ADDRPATH_ADDITIONAL_LATENCY_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_CONTROL_REGS_INPUT_SHIFT_CTRL_ADDRPATH_SHIFT_ENABLE_MASK 0x10
 #define SJC16_DDR4_PHY_CONTROL_REGS_INPUT_SHIFT_CTRL_ADDRPATH_SHIFT_ENABLE_ALIGN 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_INPUT_SHIFT_CTRL_ADDRPATH_SHIFT_ENABLE_BITS 1
 #define SJC16_DDR4_PHY_CONTROL_REGS_INPUT_SHIFT_CTRL_ADDRPATH_SHIFT_ENABLE_SHIFT 4
 #define SJC16_DDR4_PHY_CONTROL_REGS_INPUT_SHIFT_CTRL_ADDRPATH_SHIFT_ENABLE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_CONTROL_REGS_INPUT_SHIFT_CTRL_DATAPATH_ADDITIONAL_LATENCY_MASK 0xe
 #define SJC16_DDR4_PHY_CONTROL_REGS_INPUT_SHIFT_CTRL_DATAPATH_ADDITIONAL_LATENCY_ALIGN 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_INPUT_SHIFT_CTRL_DATAPATH_ADDITIONAL_LATENCY_BITS 3
 #define SJC16_DDR4_PHY_CONTROL_REGS_INPUT_SHIFT_CTRL_DATAPATH_ADDITIONAL_LATENCY_SHIFT 1
 #define SJC16_DDR4_PHY_CONTROL_REGS_INPUT_SHIFT_CTRL_DATAPATH_ADDITIONAL_LATENCY_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_CONTROL_REGS_INPUT_SHIFT_CTRL_DATAPATH_SHIFT_ENABLE_MASK 0x1
 #define SJC16_DDR4_PHY_CONTROL_REGS_INPUT_SHIFT_CTRL_DATAPATH_SHIFT_ENABLE_ALIGN 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_INPUT_SHIFT_CTRL_DATAPATH_SHIFT_ENABLE_BITS 1
 #define SJC16_DDR4_PHY_CONTROL_REGS_INPUT_SHIFT_CTRL_DATAPATH_SHIFT_ENABLE_SHIFT 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_INPUT_SHIFT_CTRL_DATAPATH_SHIFT_ENABLE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_CONTROL_REGS_INPUT_SHIFT_CTRL_RESERVED_MASK 0xffff8000
 #define SJC16_DDR4_PHY_CONTROL_REGS_INPUT_SHIFT_CTRL_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_INPUT_SHIFT_CTRL_RESERVED_BITS 17
 #define SJC16_DDR4_PHY_CONTROL_REGS_INPUT_SHIFT_CTRL_RESERVED_SHIFT 15
 #define SJC16_DDR4_PHY_CONTROL_REGS_INPUT_SHIFT_CTRL_ALL_MASK 0x7fff
 #define SJC16_DDR4_PHY_CONTROL_REGS_INPUT_SHIFT_CTRL_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_INPUT_SHIFT_CTRL_ALL_BITS 15
 #define SJC16_DDR4_PHY_CONTROL_REGS_INPUT_SHIFT_CTRL_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_INPUT_SHIFT_CTRL_ALL_MASK 0x7fff
 #define SJC16_DDR4_PHY_CONTROL_REGS_INPUT_SHIFT_CTRL_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_INPUT_SHIFT_CTRL_ALL_BITS 15
 #define SJC16_DDR4_PHY_CONTROL_REGS_INPUT_SHIFT_CTRL_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_INPUT_SHIFT_CTRL_DATAMASK 0x00007fff
 #define SJC16_DDR4_PHY_CONTROL_REGS_INPUT_SHIFT_CTRL_RDWRMASK 0xffff8000
 #define SJC16_DDR4_PHY_CONTROL_REGS_INPUT_SHIFT_CTRL_RESETVALUE 0x0000
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_INITIALIZER 0x1023fc18
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_INITIALIZER_BASE 0xc18
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_INITIALIZER_DQ_BYTE4_RD2_2G_SELECT_MASK 0x7000000
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_INITIALIZER_DQ_BYTE4_RD2_2G_SELECT_ALIGN 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_INITIALIZER_DQ_BYTE4_RD2_2G_SELECT_BITS 3
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_INITIALIZER_DQ_BYTE4_RD2_2G_SELECT_SHIFT 24
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_INITIALIZER_DQ_BYTE4_RD2_2G_SELECT_RESETVALUE 0x4
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_INITIALIZER_DQ_BYTE3_RD2_2G_SELECT_MASK 0x700000
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_INITIALIZER_DQ_BYTE3_RD2_2G_SELECT_ALIGN 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_INITIALIZER_DQ_BYTE3_RD2_2G_SELECT_BITS 3
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_INITIALIZER_DQ_BYTE3_RD2_2G_SELECT_SHIFT 20
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_INITIALIZER_DQ_BYTE3_RD2_2G_SELECT_RESETVALUE 0x3
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_INITIALIZER_DQ_BYTE2_RD2_2G_SELECT_MASK 0x70000
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_INITIALIZER_DQ_BYTE2_RD2_2G_SELECT_ALIGN 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_INITIALIZER_DQ_BYTE2_RD2_2G_SELECT_BITS 3
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_INITIALIZER_DQ_BYTE2_RD2_2G_SELECT_SHIFT 16
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_INITIALIZER_DQ_BYTE2_RD2_2G_SELECT_RESETVALUE 0x2
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_INITIALIZER_DQ_BYTE1_RD2_2G_SELECT_MASK 0x7000
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_INITIALIZER_DQ_BYTE1_RD2_2G_SELECT_ALIGN 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_INITIALIZER_DQ_BYTE1_RD2_2G_SELECT_BITS 3
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_INITIALIZER_DQ_BYTE1_RD2_2G_SELECT_SHIFT 12
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_INITIALIZER_DQ_BYTE1_RD2_2G_SELECT_RESETVALUE 0x1
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_INITIALIZER_DQ_BYTE0_RD2_2G_SELECT_MASK 0x700
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_INITIALIZER_DQ_BYTE0_RD2_2G_SELECT_ALIGN 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_INITIALIZER_DQ_BYTE0_RD2_2G_SELECT_BITS 3
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_INITIALIZER_DQ_BYTE0_RD2_2G_SELECT_SHIFT 8
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_INITIALIZER_DQ_BYTE0_RD2_2G_SELECT_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_INITIALIZER_DQ_BYTE4_WRITE_ENABLE_MASK 0x10
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_INITIALIZER_DQ_BYTE4_WRITE_ENABLE_ALIGN 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_INITIALIZER_DQ_BYTE4_WRITE_ENABLE_BITS 1
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_INITIALIZER_DQ_BYTE4_WRITE_ENABLE_SHIFT 4
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_INITIALIZER_DQ_BYTE4_WRITE_ENABLE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_INITIALIZER_DQ_BYTE3_WRITE_ENABLE_MASK 0x8
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_INITIALIZER_DQ_BYTE3_WRITE_ENABLE_ALIGN 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_INITIALIZER_DQ_BYTE3_WRITE_ENABLE_BITS 1
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_INITIALIZER_DQ_BYTE3_WRITE_ENABLE_SHIFT 3
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_INITIALIZER_DQ_BYTE3_WRITE_ENABLE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_INITIALIZER_DQ_BYTE2_WRITE_ENABLE_MASK 0x4
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_INITIALIZER_DQ_BYTE2_WRITE_ENABLE_ALIGN 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_INITIALIZER_DQ_BYTE2_WRITE_ENABLE_BITS 1
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_INITIALIZER_DQ_BYTE2_WRITE_ENABLE_SHIFT 2
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_INITIALIZER_DQ_BYTE2_WRITE_ENABLE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_INITIALIZER_DQ_BYTE1_WRITE_ENABLE_MASK 0x2
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_INITIALIZER_DQ_BYTE1_WRITE_ENABLE_ALIGN 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_INITIALIZER_DQ_BYTE1_WRITE_ENABLE_BITS 1
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_INITIALIZER_DQ_BYTE1_WRITE_ENABLE_SHIFT 1
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_INITIALIZER_DQ_BYTE1_WRITE_ENABLE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_INITIALIZER_DQ_BYTE0_WRITE_ENABLE_MASK 0x1
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_INITIALIZER_DQ_BYTE0_WRITE_ENABLE_ALIGN 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_INITIALIZER_DQ_BYTE0_WRITE_ENABLE_BITS 1
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_INITIALIZER_DQ_BYTE0_WRITE_ENABLE_SHIFT 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_INITIALIZER_DQ_BYTE0_WRITE_ENABLE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_INITIALIZER_RESERVED_0_MASK 0xf8000000
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_INITIALIZER_RESERVED_0_ALIGN 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_INITIALIZER_RESERVED_0_BITS 5
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_INITIALIZER_RESERVED_0_SHIFT 27
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_INITIALIZER_RESERVED_5_MASK 0xe0
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_INITIALIZER_RESERVED_5_ALIGN 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_INITIALIZER_RESERVED_5_BITS 3
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_INITIALIZER_RESERVED_5_SHIFT 5
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_INITIALIZER_RESERVED_MASK 0xf8000000
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_INITIALIZER_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_INITIALIZER_RESERVED_BITS 5
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_INITIALIZER_RESERVED_SHIFT 27
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_INITIALIZER_ALL_MASK 0x7ffffff
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_INITIALIZER_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_INITIALIZER_ALL_BITS 27
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_INITIALIZER_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_INITIALIZER_ALL_MASK 0x7ffffff
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_INITIALIZER_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_INITIALIZER_ALL_BITS 27
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_INITIALIZER_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_INITIALIZER_DATAMASK 0x0777771f
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_INITIALIZER_RDWRMASK 0xf88888e0
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_INITIALIZER_RESETVALUE 0x4321000
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_MODIFIER_LSB 0x1023fc1c
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_MODIFIER_LSB_BASE 0xc1c
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_MODIFIER_LSB_DQ_BYTE3_RD2_2G_DELAY_DEC_MASK 0x40000000
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_MODIFIER_LSB_DQ_BYTE3_RD2_2G_DELAY_DEC_ALIGN 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_MODIFIER_LSB_DQ_BYTE3_RD2_2G_DELAY_DEC_BITS 1
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_MODIFIER_LSB_DQ_BYTE3_RD2_2G_DELAY_DEC_SHIFT 30
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_MODIFIER_LSB_DQ_BYTE3_RD2_2G_DELAY_DEC_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_MODIFIER_LSB_DQ_BYTE3_RD2_2G_DELAY_INC_MASK 0x20000000
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_MODIFIER_LSB_DQ_BYTE3_RD2_2G_DELAY_INC_ALIGN 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_MODIFIER_LSB_DQ_BYTE3_RD2_2G_DELAY_INC_BITS 1
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_MODIFIER_LSB_DQ_BYTE3_RD2_2G_DELAY_INC_SHIFT 29
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_MODIFIER_LSB_DQ_BYTE3_RD2_2G_DELAY_INC_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_MODIFIER_LSB_DQ_BYTE3_RD2_2G_DELAY_IN_USE_MASK 0x1f000000
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_MODIFIER_LSB_DQ_BYTE3_RD2_2G_DELAY_IN_USE_ALIGN 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_MODIFIER_LSB_DQ_BYTE3_RD2_2G_DELAY_IN_USE_BITS 5
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_MODIFIER_LSB_DQ_BYTE3_RD2_2G_DELAY_IN_USE_SHIFT 24
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_MODIFIER_LSB_DQ_BYTE3_RD2_2G_DELAY_IN_USE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_MODIFIER_LSB_DQ_BYTE2_RD2_2G_DELAY_DEC_MASK 0x400000
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_MODIFIER_LSB_DQ_BYTE2_RD2_2G_DELAY_DEC_ALIGN 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_MODIFIER_LSB_DQ_BYTE2_RD2_2G_DELAY_DEC_BITS 1
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_MODIFIER_LSB_DQ_BYTE2_RD2_2G_DELAY_DEC_SHIFT 22
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_MODIFIER_LSB_DQ_BYTE2_RD2_2G_DELAY_DEC_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_MODIFIER_LSB_DQ_BYTE2_RD2_2G_DELAY_INC_MASK 0x200000
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_MODIFIER_LSB_DQ_BYTE2_RD2_2G_DELAY_INC_ALIGN 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_MODIFIER_LSB_DQ_BYTE2_RD2_2G_DELAY_INC_BITS 1
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_MODIFIER_LSB_DQ_BYTE2_RD2_2G_DELAY_INC_SHIFT 21
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_MODIFIER_LSB_DQ_BYTE2_RD2_2G_DELAY_INC_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_MODIFIER_LSB_DQ_BYTE2_RD2_2G_DELAY_IN_USE_MASK 0x1f0000
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_MODIFIER_LSB_DQ_BYTE2_RD2_2G_DELAY_IN_USE_ALIGN 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_MODIFIER_LSB_DQ_BYTE2_RD2_2G_DELAY_IN_USE_BITS 5
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_MODIFIER_LSB_DQ_BYTE2_RD2_2G_DELAY_IN_USE_SHIFT 16
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_MODIFIER_LSB_DQ_BYTE2_RD2_2G_DELAY_IN_USE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_MODIFIER_LSB_DQ_BYTE1_RD2_2G_DELAY_DEC_MASK 0x4000
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_MODIFIER_LSB_DQ_BYTE1_RD2_2G_DELAY_DEC_ALIGN 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_MODIFIER_LSB_DQ_BYTE1_RD2_2G_DELAY_DEC_BITS 1
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_MODIFIER_LSB_DQ_BYTE1_RD2_2G_DELAY_DEC_SHIFT 14
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_MODIFIER_LSB_DQ_BYTE1_RD2_2G_DELAY_DEC_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_MODIFIER_LSB_DQ_BYTE1_RD2_2G_DELAY_INC_MASK 0x2000
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_MODIFIER_LSB_DQ_BYTE1_RD2_2G_DELAY_INC_ALIGN 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_MODIFIER_LSB_DQ_BYTE1_RD2_2G_DELAY_INC_BITS 1
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_MODIFIER_LSB_DQ_BYTE1_RD2_2G_DELAY_INC_SHIFT 13
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_MODIFIER_LSB_DQ_BYTE1_RD2_2G_DELAY_INC_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_MODIFIER_LSB_DQ_BYTE1_RD2_2G_DELAY_IN_USE_MASK 0x1f00
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_MODIFIER_LSB_DQ_BYTE1_RD2_2G_DELAY_IN_USE_ALIGN 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_MODIFIER_LSB_DQ_BYTE1_RD2_2G_DELAY_IN_USE_BITS 5
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_MODIFIER_LSB_DQ_BYTE1_RD2_2G_DELAY_IN_USE_SHIFT 8
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_MODIFIER_LSB_DQ_BYTE1_RD2_2G_DELAY_IN_USE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_MODIFIER_LSB_DQ_BYTE0_RD2_2G_DELAY_DEC_MASK 0x40
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_MODIFIER_LSB_DQ_BYTE0_RD2_2G_DELAY_DEC_ALIGN 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_MODIFIER_LSB_DQ_BYTE0_RD2_2G_DELAY_DEC_BITS 1
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_MODIFIER_LSB_DQ_BYTE0_RD2_2G_DELAY_DEC_SHIFT 6
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_MODIFIER_LSB_DQ_BYTE0_RD2_2G_DELAY_DEC_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_MODIFIER_LSB_DQ_BYTE0_RD2_2G_DELAY_INC_MASK 0x20
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_MODIFIER_LSB_DQ_BYTE0_RD2_2G_DELAY_INC_ALIGN 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_MODIFIER_LSB_DQ_BYTE0_RD2_2G_DELAY_INC_BITS 1
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_MODIFIER_LSB_DQ_BYTE0_RD2_2G_DELAY_INC_SHIFT 5
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_MODIFIER_LSB_DQ_BYTE0_RD2_2G_DELAY_INC_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_MODIFIER_LSB_DQ_BYTE0_RD2_2G_DELAY_IN_USE_MASK 0x1f
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_MODIFIER_LSB_DQ_BYTE0_RD2_2G_DELAY_IN_USE_ALIGN 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_MODIFIER_LSB_DQ_BYTE0_RD2_2G_DELAY_IN_USE_BITS 5
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_MODIFIER_LSB_DQ_BYTE0_RD2_2G_DELAY_IN_USE_SHIFT 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_MODIFIER_LSB_DQ_BYTE0_RD2_2G_DELAY_IN_USE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_MODIFIER_LSB_ALL_MASK 0x7fffffff
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_MODIFIER_LSB_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_MODIFIER_LSB_ALL_BITS 31
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_MODIFIER_LSB_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_MODIFIER_LSB_ALL_MASK 0x7fffffff
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_MODIFIER_LSB_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_MODIFIER_LSB_ALL_BITS 31
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_MODIFIER_LSB_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_MODIFIER_LSB_DATAMASK 0x7f7f7f7f
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_MODIFIER_LSB_RDWRMASK 0x80808080
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_MODIFIER_LSB_RESETVALUE 0x00000000
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_MODIFIER_MSB 0x1023fc20
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_MODIFIER_MSB_BASE 0xc20
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_MODIFIER_MSB_DQ_BYTE4_RD2_2G_DELAY_DEC_MASK 0x40
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_MODIFIER_MSB_DQ_BYTE4_RD2_2G_DELAY_DEC_ALIGN 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_MODIFIER_MSB_DQ_BYTE4_RD2_2G_DELAY_DEC_BITS 1
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_MODIFIER_MSB_DQ_BYTE4_RD2_2G_DELAY_DEC_SHIFT 6
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_MODIFIER_MSB_DQ_BYTE4_RD2_2G_DELAY_DEC_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_MODIFIER_MSB_DQ_BYTE4_RD2_2G_DELAY_INC_MASK 0x20
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_MODIFIER_MSB_DQ_BYTE4_RD2_2G_DELAY_INC_ALIGN 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_MODIFIER_MSB_DQ_BYTE4_RD2_2G_DELAY_INC_BITS 1
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_MODIFIER_MSB_DQ_BYTE4_RD2_2G_DELAY_INC_SHIFT 5
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_MODIFIER_MSB_DQ_BYTE4_RD2_2G_DELAY_INC_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_MODIFIER_MSB_DQ_BYTE4_RD2_2G_DELAY_IN_USE_MASK 0x1f
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_MODIFIER_MSB_DQ_BYTE4_RD2_2G_DELAY_IN_USE_ALIGN 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_MODIFIER_MSB_DQ_BYTE4_RD2_2G_DELAY_IN_USE_BITS 5
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_MODIFIER_MSB_DQ_BYTE4_RD2_2G_DELAY_IN_USE_SHIFT 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_MODIFIER_MSB_DQ_BYTE4_RD2_2G_DELAY_IN_USE_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_MODIFIER_MSB_RESERVED_MASK 0xffffff80
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_MODIFIER_MSB_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_MODIFIER_MSB_RESERVED_BITS 25
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_MODIFIER_MSB_RESERVED_SHIFT 7
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_MODIFIER_MSB_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_MODIFIER_MSB_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_MODIFIER_MSB_ALL_BITS 7
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_MODIFIER_MSB_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_MODIFIER_MSB_ALL_MASK 0x7f
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_MODIFIER_MSB_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_MODIFIER_MSB_ALL_BITS 7
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_MODIFIER_MSB_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_MODIFIER_MSB_DATAMASK 0x0000007f
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_MODIFIER_MSB_RDWRMASK 0xffffff80
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_MODIFIER_MSB_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_DRAM_PARAMETER_CONFIG 0x1023fc24
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_DRAM_PARAMETER_CONFIG_BASE 0xc24
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_DRAM_PARAMETER_CONFIG_T_PHY_WRDATA_MASK 0x1c
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_DRAM_PARAMETER_CONFIG_T_PHY_WRDATA_ALIGN 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_DRAM_PARAMETER_CONFIG_T_PHY_WRDATA_BITS 3
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_DRAM_PARAMETER_CONFIG_T_PHY_WRDATA_SHIFT 2
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_DRAM_PARAMETER_CONFIG_T_PHY_WRDATA_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_DRAM_PARAMETER_CONFIG_BURST_LENGTH_MASK 0x3
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_DRAM_PARAMETER_CONFIG_BURST_LENGTH_ALIGN 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_DRAM_PARAMETER_CONFIG_BURST_LENGTH_BITS 2
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_DRAM_PARAMETER_CONFIG_BURST_LENGTH_SHIFT 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_DRAM_PARAMETER_CONFIG_BURST_LENGTH_RESETVALUE 0x1
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_DRAM_PARAMETER_CONFIG_RESERVED_MASK 0xffffffe0
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_DRAM_PARAMETER_CONFIG_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_DRAM_PARAMETER_CONFIG_RESERVED_BITS 27
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_DRAM_PARAMETER_CONFIG_RESERVED_SHIFT 5
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_DRAM_PARAMETER_CONFIG_ALL_MASK 0x1f
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_DRAM_PARAMETER_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_DRAM_PARAMETER_CONFIG_ALL_BITS 5
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_DRAM_PARAMETER_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_DRAM_PARAMETER_CONFIG_ALL_MASK 0x1f
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_DRAM_PARAMETER_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_DRAM_PARAMETER_CONFIG_ALL_BITS 5
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_DRAM_PARAMETER_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_DRAM_PARAMETER_CONFIG_DATAMASK 0x0000001f
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_DRAM_PARAMETER_CONFIG_RDWRMASK 0xffffffe0
 #define SJC16_DDR4_PHY_CONTROL_REGS_DDR4_DRAM_PARAMETER_CONFIG_RESETVALUE 0x01
 #define SJC16_DDR4_PHY_CONTROL_REGS_SHARED_VREF_DAC_CONFIG 0x1023fc28
 #define SJC16_DDR4_PHY_CONTROL_REGS_SHARED_VREF_DAC_CONFIG_BASE 0xc28
 #define SJC16_DDR4_PHY_CONTROL_REGS_SHARED_VREF_DAC_CONFIG_DATA_MASK 0xff0000
 #define SJC16_DDR4_PHY_CONTROL_REGS_SHARED_VREF_DAC_CONFIG_DATA_ALIGN 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_SHARED_VREF_DAC_CONFIG_DATA_BITS 8
 #define SJC16_DDR4_PHY_CONTROL_REGS_SHARED_VREF_DAC_CONFIG_DATA_SHIFT 16
 #define SJC16_DDR4_PHY_CONTROL_REGS_SHARED_VREF_DAC_CONFIG_DATA_RESETVALUE 0x92
 #define SJC16_DDR4_PHY_CONTROL_REGS_SHARED_VREF_DAC_CONFIG_CTRL_MASK 0xff
 #define SJC16_DDR4_PHY_CONTROL_REGS_SHARED_VREF_DAC_CONFIG_CTRL_ALIGN 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_SHARED_VREF_DAC_CONFIG_CTRL_BITS 8
 #define SJC16_DDR4_PHY_CONTROL_REGS_SHARED_VREF_DAC_CONFIG_CTRL_SHIFT 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_SHARED_VREF_DAC_CONFIG_CTRL_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_CONTROL_REGS_SHARED_VREF_DAC_CONFIG_RESERVED_MASK 0xff000000
 #define SJC16_DDR4_PHY_CONTROL_REGS_SHARED_VREF_DAC_CONFIG_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_SHARED_VREF_DAC_CONFIG_RESERVED_BITS 8
 #define SJC16_DDR4_PHY_CONTROL_REGS_SHARED_VREF_DAC_CONFIG_RESERVED_SHIFT 24
 #define SJC16_DDR4_PHY_CONTROL_REGS_SHARED_VREF_DAC_CONFIG_ALL_MASK 0xffffff
 #define SJC16_DDR4_PHY_CONTROL_REGS_SHARED_VREF_DAC_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_SHARED_VREF_DAC_CONFIG_ALL_BITS 24
 #define SJC16_DDR4_PHY_CONTROL_REGS_SHARED_VREF_DAC_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_SHARED_VREF_DAC_CONFIG_ALL_MASK 0xffffff
 #define SJC16_DDR4_PHY_CONTROL_REGS_SHARED_VREF_DAC_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_SHARED_VREF_DAC_CONFIG_ALL_BITS 24
 #define SJC16_DDR4_PHY_CONTROL_REGS_SHARED_VREF_DAC_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_SHARED_VREF_DAC_CONFIG_DATAMASK 0x00ff00ff
 #define SJC16_DDR4_PHY_CONTROL_REGS_SHARED_VREF_DAC_CONFIG_RDWRMASK 0xff00ff00
 #define SJC16_DDR4_PHY_CONTROL_REGS_SHARED_VREF_DAC_CONFIG_RESETVALUE 0x920000
 #define SJC16_DDR4_PHY_CONTROL_REGS_SUPPLEMENT_VREF_DAC_CONFIG 0x1023fc2c
 #define SJC16_DDR4_PHY_CONTROL_REGS_SUPPLEMENT_VREF_DAC_CONFIG_BASE 0xc2c
 #define SJC16_DDR4_PHY_CONTROL_REGS_SUPPLEMENT_VREF_DAC_CONFIG_DATA_MASK 0xff0000
 #define SJC16_DDR4_PHY_CONTROL_REGS_SUPPLEMENT_VREF_DAC_CONFIG_DATA_ALIGN 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_SUPPLEMENT_VREF_DAC_CONFIG_DATA_BITS 8
 #define SJC16_DDR4_PHY_CONTROL_REGS_SUPPLEMENT_VREF_DAC_CONFIG_DATA_SHIFT 16
 #define SJC16_DDR4_PHY_CONTROL_REGS_SUPPLEMENT_VREF_DAC_CONFIG_DATA_RESETVALUE 0x92
 #define SJC16_DDR4_PHY_CONTROL_REGS_SUPPLEMENT_VREF_DAC_CONFIG_CTRL_MASK 0xff
 #define SJC16_DDR4_PHY_CONTROL_REGS_SUPPLEMENT_VREF_DAC_CONFIG_CTRL_ALIGN 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_SUPPLEMENT_VREF_DAC_CONFIG_CTRL_BITS 8
 #define SJC16_DDR4_PHY_CONTROL_REGS_SUPPLEMENT_VREF_DAC_CONFIG_CTRL_SHIFT 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_SUPPLEMENT_VREF_DAC_CONFIG_CTRL_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_CONTROL_REGS_SUPPLEMENT_VREF_DAC_CONFIG_RESERVED_MASK 0xff000000
 #define SJC16_DDR4_PHY_CONTROL_REGS_SUPPLEMENT_VREF_DAC_CONFIG_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_SUPPLEMENT_VREF_DAC_CONFIG_RESERVED_BITS 8
 #define SJC16_DDR4_PHY_CONTROL_REGS_SUPPLEMENT_VREF_DAC_CONFIG_RESERVED_SHIFT 24
 #define SJC16_DDR4_PHY_CONTROL_REGS_SUPPLEMENT_VREF_DAC_CONFIG_ALL_MASK 0xffffff
 #define SJC16_DDR4_PHY_CONTROL_REGS_SUPPLEMENT_VREF_DAC_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_SUPPLEMENT_VREF_DAC_CONFIG_ALL_BITS 24
 #define SJC16_DDR4_PHY_CONTROL_REGS_SUPPLEMENT_VREF_DAC_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_SUPPLEMENT_VREF_DAC_CONFIG_ALL_MASK 0xffffff
 #define SJC16_DDR4_PHY_CONTROL_REGS_SUPPLEMENT_VREF_DAC_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_SUPPLEMENT_VREF_DAC_CONFIG_ALL_BITS 24
 #define SJC16_DDR4_PHY_CONTROL_REGS_SUPPLEMENT_VREF_DAC_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_SUPPLEMENT_VREF_DAC_CONFIG_DATAMASK 0x00ff00ff
 #define SJC16_DDR4_PHY_CONTROL_REGS_SUPPLEMENT_VREF_DAC_CONFIG_RDWRMASK 0xff00ff00
 #define SJC16_DDR4_PHY_CONTROL_REGS_SUPPLEMENT_VREF_DAC_CONFIG_RESETVALUE 0x920000
 #define SJC16_DDR4_PHY_CONTROL_REGS_ACTIVE_INTERFACES_CONFIG 0x1023fc30
 #define SJC16_DDR4_PHY_CONTROL_REGS_ACTIVE_INTERFACES_CONFIG_BASE 0xc30
 #define SJC16_DDR4_PHY_CONTROL_REGS_ACTIVE_INTERFACES_CONFIG_ACTIVE_ADDRESS_MASK 0x20
 #define SJC16_DDR4_PHY_CONTROL_REGS_ACTIVE_INTERFACES_CONFIG_ACTIVE_ADDRESS_ALIGN 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_ACTIVE_INTERFACES_CONFIG_ACTIVE_ADDRESS_BITS 1
 #define SJC16_DDR4_PHY_CONTROL_REGS_ACTIVE_INTERFACES_CONFIG_ACTIVE_ADDRESS_SHIFT 5
 #define SJC16_DDR4_PHY_CONTROL_REGS_ACTIVE_INTERFACES_CONFIG_ACTIVE_ADDRESS_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_CONTROL_REGS_ACTIVE_INTERFACES_CONFIG_ACTIVE_BYTES_BITMAP_MASK 0x1f
 #define SJC16_DDR4_PHY_CONTROL_REGS_ACTIVE_INTERFACES_CONFIG_ACTIVE_BYTES_BITMAP_ALIGN 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_ACTIVE_INTERFACES_CONFIG_ACTIVE_BYTES_BITMAP_BITS 5
 #define SJC16_DDR4_PHY_CONTROL_REGS_ACTIVE_INTERFACES_CONFIG_ACTIVE_BYTES_BITMAP_SHIFT 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_ACTIVE_INTERFACES_CONFIG_ACTIVE_BYTES_BITMAP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_CONTROL_REGS_ACTIVE_INTERFACES_CONFIG_RESERVED_MASK 0xffffffc0
 #define SJC16_DDR4_PHY_CONTROL_REGS_ACTIVE_INTERFACES_CONFIG_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_ACTIVE_INTERFACES_CONFIG_RESERVED_BITS 26
 #define SJC16_DDR4_PHY_CONTROL_REGS_ACTIVE_INTERFACES_CONFIG_RESERVED_SHIFT 6
 #define SJC16_DDR4_PHY_CONTROL_REGS_ACTIVE_INTERFACES_CONFIG_ALL_MASK 0x3f
 #define SJC16_DDR4_PHY_CONTROL_REGS_ACTIVE_INTERFACES_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_ACTIVE_INTERFACES_CONFIG_ALL_BITS 6
 #define SJC16_DDR4_PHY_CONTROL_REGS_ACTIVE_INTERFACES_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_ACTIVE_INTERFACES_CONFIG_ALL_MASK 0x3f
 #define SJC16_DDR4_PHY_CONTROL_REGS_ACTIVE_INTERFACES_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_ACTIVE_INTERFACES_CONFIG_ALL_BITS 6
 #define SJC16_DDR4_PHY_CONTROL_REGS_ACTIVE_INTERFACES_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_ACTIVE_INTERFACES_CONFIG_DATAMASK 0x0000003f
 #define SJC16_DDR4_PHY_CONTROL_REGS_ACTIVE_INTERFACES_CONFIG_RDWRMASK 0xffffffc0
 #define SJC16_DDR4_PHY_CONTROL_REGS_ACTIVE_INTERFACES_CONFIG_RESETVALUE 0x00
 #define SJC16_DDR4_PHY_CONTROL_REGS_FREQ_CNTR_CONFIG 0x1023fc34
 #define SJC16_DDR4_PHY_CONTROL_REGS_FREQ_CNTR_CONFIG_BASE 0xc34
 #define SJC16_DDR4_PHY_CONTROL_REGS_FREQ_CNTR_CONFIG_EN_EXTERNAL_PHY_2G_WCLK_MASK 0x80000000
 #define SJC16_DDR4_PHY_CONTROL_REGS_FREQ_CNTR_CONFIG_EN_EXTERNAL_PHY_2G_WCLK_ALIGN 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_FREQ_CNTR_CONFIG_EN_EXTERNAL_PHY_2G_WCLK_BITS 1
 #define SJC16_DDR4_PHY_CONTROL_REGS_FREQ_CNTR_CONFIG_EN_EXTERNAL_PHY_2G_WCLK_SHIFT 31
 #define SJC16_DDR4_PHY_CONTROL_REGS_FREQ_CNTR_CONFIG_EN_EXTERNAL_PHY_2G_WCLK_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_CONTROL_REGS_FREQ_CNTR_CONFIG_TEST_PIN_DIV_SEL_MASK 0x70000000
 #define SJC16_DDR4_PHY_CONTROL_REGS_FREQ_CNTR_CONFIG_TEST_PIN_DIV_SEL_ALIGN 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_FREQ_CNTR_CONFIG_TEST_PIN_DIV_SEL_BITS 3
 #define SJC16_DDR4_PHY_CONTROL_REGS_FREQ_CNTR_CONFIG_TEST_PIN_DIV_SEL_SHIFT 28
 #define SJC16_DDR4_PHY_CONTROL_REGS_FREQ_CNTR_CONFIG_TEST_PIN_DIV_SEL_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_CONTROL_REGS_FREQ_CNTR_CONFIG_START_OBS_MASK 0x8000000
 #define SJC16_DDR4_PHY_CONTROL_REGS_FREQ_CNTR_CONFIG_START_OBS_ALIGN 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_FREQ_CNTR_CONFIG_START_OBS_BITS 1
 #define SJC16_DDR4_PHY_CONTROL_REGS_FREQ_CNTR_CONFIG_START_OBS_SHIFT 27
 #define SJC16_DDR4_PHY_CONTROL_REGS_FREQ_CNTR_CONFIG_START_OBS_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_CONTROL_REGS_FREQ_CNTR_CONFIG_EN_NLDL_CLKOUT_BAR_MASK 0x4000000
 #define SJC16_DDR4_PHY_CONTROL_REGS_FREQ_CNTR_CONFIG_EN_NLDL_CLKOUT_BAR_ALIGN 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_FREQ_CNTR_CONFIG_EN_NLDL_CLKOUT_BAR_BITS 1
 #define SJC16_DDR4_PHY_CONTROL_REGS_FREQ_CNTR_CONFIG_EN_NLDL_CLKOUT_BAR_SHIFT 26
 #define SJC16_DDR4_PHY_CONTROL_REGS_FREQ_CNTR_CONFIG_EN_NLDL_CLKOUT_BAR_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_CONTROL_REGS_FREQ_CNTR_CONFIG_SEL_FC_REFCLK_MASK 0x2000000
 #define SJC16_DDR4_PHY_CONTROL_REGS_FREQ_CNTR_CONFIG_SEL_FC_REFCLK_ALIGN 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_FREQ_CNTR_CONFIG_SEL_FC_REFCLK_BITS 1
 #define SJC16_DDR4_PHY_CONTROL_REGS_FREQ_CNTR_CONFIG_SEL_FC_REFCLK_SHIFT 25
 #define SJC16_DDR4_PHY_CONTROL_REGS_FREQ_CNTR_CONFIG_SEL_FC_REFCLK_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_CONTROL_REGS_FREQ_CNTR_CONFIG_RO_VDL_STEP_MASK 0x1ff0000
 #define SJC16_DDR4_PHY_CONTROL_REGS_FREQ_CNTR_CONFIG_RO_VDL_STEP_ALIGN 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_FREQ_CNTR_CONFIG_RO_VDL_STEP_BITS 9
 #define SJC16_DDR4_PHY_CONTROL_REGS_FREQ_CNTR_CONFIG_RO_VDL_STEP_SHIFT 16
 #define SJC16_DDR4_PHY_CONTROL_REGS_FREQ_CNTR_CONFIG_RO_VDL_STEP_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_CONTROL_REGS_FREQ_CNTR_CONFIG_OBS_INTERVAL_MASK 0xffff
 #define SJC16_DDR4_PHY_CONTROL_REGS_FREQ_CNTR_CONFIG_OBS_INTERVAL_ALIGN 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_FREQ_CNTR_CONFIG_OBS_INTERVAL_BITS 16
 #define SJC16_DDR4_PHY_CONTROL_REGS_FREQ_CNTR_CONFIG_OBS_INTERVAL_SHIFT 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_FREQ_CNTR_CONFIG_OBS_INTERVAL_RESETVALUE 0x0000
 #define SJC16_DDR4_PHY_CONTROL_REGS_FREQ_CNTR_CONFIG_ALL_MASK 0xffffffff
 #define SJC16_DDR4_PHY_CONTROL_REGS_FREQ_CNTR_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_FREQ_CNTR_CONFIG_ALL_BITS 32
 #define SJC16_DDR4_PHY_CONTROL_REGS_FREQ_CNTR_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_FREQ_CNTR_CONFIG_ALL_MASK 0xffffffff
 #define SJC16_DDR4_PHY_CONTROL_REGS_FREQ_CNTR_CONFIG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_FREQ_CNTR_CONFIG_ALL_BITS 32
 #define SJC16_DDR4_PHY_CONTROL_REGS_FREQ_CNTR_CONFIG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_FREQ_CNTR_CONFIG_DATAMASK 0xffffffff
 #define SJC16_DDR4_PHY_CONTROL_REGS_FREQ_CNTR_CONFIG_RDWRMASK 0x00000000
 #define SJC16_DDR4_PHY_CONTROL_REGS_FREQ_CNTR_CONFIG_RESETVALUE 0x00000000
 #define SJC16_DDR4_PHY_CONTROL_REGS_STATUS_FREQ_CNTR_DCOUNT 0x1023fc38
 #define SJC16_DDR4_PHY_CONTROL_REGS_STATUS_FREQ_CNTR_DCOUNT_BASE 0xc38
 #define SJC16_DDR4_PHY_CONTROL_REGS_STATUS_FREQ_CNTR_DCOUNT_DCOUNT_MASK 0xffff
 #define SJC16_DDR4_PHY_CONTROL_REGS_STATUS_FREQ_CNTR_DCOUNT_DCOUNT_ALIGN 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_STATUS_FREQ_CNTR_DCOUNT_DCOUNT_BITS 16
 #define SJC16_DDR4_PHY_CONTROL_REGS_STATUS_FREQ_CNTR_DCOUNT_DCOUNT_SHIFT 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_STATUS_FREQ_CNTR_DCOUNT_DCOUNT_RESETVALUE 0x0000
 #define SJC16_DDR4_PHY_CONTROL_REGS_STATUS_FREQ_CNTR_DCOUNT_RESERVED_MASK 0xffff0000
 #define SJC16_DDR4_PHY_CONTROL_REGS_STATUS_FREQ_CNTR_DCOUNT_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_STATUS_FREQ_CNTR_DCOUNT_RESERVED_BITS 16
 #define SJC16_DDR4_PHY_CONTROL_REGS_STATUS_FREQ_CNTR_DCOUNT_RESERVED_SHIFT 16
 #define SJC16_DDR4_PHY_CONTROL_REGS_STATUS_FREQ_CNTR_DCOUNT_ALL_MASK 0xffff
 #define SJC16_DDR4_PHY_CONTROL_REGS_STATUS_FREQ_CNTR_DCOUNT_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_STATUS_FREQ_CNTR_DCOUNT_ALL_BITS 16
 #define SJC16_DDR4_PHY_CONTROL_REGS_STATUS_FREQ_CNTR_DCOUNT_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_STATUS_FREQ_CNTR_DCOUNT_ALL_MASK 0xffff
 #define SJC16_DDR4_PHY_CONTROL_REGS_STATUS_FREQ_CNTR_DCOUNT_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_STATUS_FREQ_CNTR_DCOUNT_ALL_BITS 16
 #define SJC16_DDR4_PHY_CONTROL_REGS_STATUS_FREQ_CNTR_DCOUNT_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_STATUS_FREQ_CNTR_DCOUNT_DATAMASK 0x0000ffff
 #define SJC16_DDR4_PHY_CONTROL_REGS_STATUS_FREQ_CNTR_DCOUNT_RDWRMASK 0xffff0000
 #define SJC16_DDR4_PHY_CONTROL_REGS_STATUS_FREQ_CNTR_DCOUNT_RESETVALUE 0x0000
 #define SJC16_DDR4_PHY_CONTROL_REGS_STATUS_FREQ_CNTR_UCOUNT 0x1023fc3c
 #define SJC16_DDR4_PHY_CONTROL_REGS_STATUS_FREQ_CNTR_UCOUNT_BASE 0xc3c
 #define SJC16_DDR4_PHY_CONTROL_REGS_STATUS_FREQ_CNTR_UCOUNT_RO_OVERFLOW_MASK 0x7000000
 #define SJC16_DDR4_PHY_CONTROL_REGS_STATUS_FREQ_CNTR_UCOUNT_RO_OVERFLOW_ALIGN 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_STATUS_FREQ_CNTR_UCOUNT_RO_OVERFLOW_BITS 3
 #define SJC16_DDR4_PHY_CONTROL_REGS_STATUS_FREQ_CNTR_UCOUNT_RO_OVERFLOW_SHIFT 24
 #define SJC16_DDR4_PHY_CONTROL_REGS_STATUS_FREQ_CNTR_UCOUNT_RO_OVERFLOW_RESETVALUE 0x0
 #define SJC16_DDR4_PHY_CONTROL_REGS_STATUS_FREQ_CNTR_UCOUNT_RO_UCOUNT_MASK 0xffffff
 #define SJC16_DDR4_PHY_CONTROL_REGS_STATUS_FREQ_CNTR_UCOUNT_RO_UCOUNT_ALIGN 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_STATUS_FREQ_CNTR_UCOUNT_RO_UCOUNT_BITS 24
 #define SJC16_DDR4_PHY_CONTROL_REGS_STATUS_FREQ_CNTR_UCOUNT_RO_UCOUNT_SHIFT 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_STATUS_FREQ_CNTR_UCOUNT_RO_UCOUNT_RESETVALUE 0x000000
 #define SJC16_DDR4_PHY_CONTROL_REGS_STATUS_FREQ_CNTR_UCOUNT_RESERVED_MASK 0xf8000000
 #define SJC16_DDR4_PHY_CONTROL_REGS_STATUS_FREQ_CNTR_UCOUNT_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_STATUS_FREQ_CNTR_UCOUNT_RESERVED_BITS 5
 #define SJC16_DDR4_PHY_CONTROL_REGS_STATUS_FREQ_CNTR_UCOUNT_RESERVED_SHIFT 27
 #define SJC16_DDR4_PHY_CONTROL_REGS_STATUS_FREQ_CNTR_UCOUNT_ALL_MASK 0x7ffffff
 #define SJC16_DDR4_PHY_CONTROL_REGS_STATUS_FREQ_CNTR_UCOUNT_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_STATUS_FREQ_CNTR_UCOUNT_ALL_BITS 27
 #define SJC16_DDR4_PHY_CONTROL_REGS_STATUS_FREQ_CNTR_UCOUNT_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_STATUS_FREQ_CNTR_UCOUNT_ALL_MASK 0x7ffffff
 #define SJC16_DDR4_PHY_CONTROL_REGS_STATUS_FREQ_CNTR_UCOUNT_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_STATUS_FREQ_CNTR_UCOUNT_ALL_BITS 27
 #define SJC16_DDR4_PHY_CONTROL_REGS_STATUS_FREQ_CNTR_UCOUNT_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_STATUS_FREQ_CNTR_UCOUNT_DATAMASK 0x07ffffff
 #define SJC16_DDR4_PHY_CONTROL_REGS_STATUS_FREQ_CNTR_UCOUNT_RDWRMASK 0xf8000000
 #define SJC16_DDR4_PHY_CONTROL_REGS_STATUS_FREQ_CNTR_UCOUNT_RESETVALUE 0x0000000
 #define SJC16_DDR4_PHY_CONTROL_REGS_RESERVED_REG 0x1023fc40
 #define SJC16_DDR4_PHY_CONTROL_REGS_RESERVED_REG_BASE 0xc40
 #define SJC16_DDR4_PHY_CONTROL_REGS_RESERVED_REG_RESERVED_MASK 0xffffffff
 #define SJC16_DDR4_PHY_CONTROL_REGS_RESERVED_REG_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_RESERVED_REG_RESERVED_BITS 32
 #define SJC16_DDR4_PHY_CONTROL_REGS_RESERVED_REG_RESERVED_SHIFT 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_RESERVED_REG_RESERVED_RESETVALUE 0x00000000
 #define SJC16_DDR4_PHY_CONTROL_REGS_RESERVED_REG_ALL_MASK 0xffffffff
 #define SJC16_DDR4_PHY_CONTROL_REGS_RESERVED_REG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_RESERVED_REG_ALL_BITS 32
 #define SJC16_DDR4_PHY_CONTROL_REGS_RESERVED_REG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_RESERVED_REG_ALL_MASK 0xffffffff
 #define SJC16_DDR4_PHY_CONTROL_REGS_RESERVED_REG_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_RESERVED_REG_ALL_BITS 32
 #define SJC16_DDR4_PHY_CONTROL_REGS_RESERVED_REG_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_RESERVED_REG_DATAMASK 0xffffffff
 #define SJC16_DDR4_PHY_CONTROL_REGS_RESERVED_REG_RDWRMASK 0x00000000
 #define SJC16_DDR4_PHY_CONTROL_REGS_RESERVED_REG_RESETVALUE 0x00000000
 #define SJC16_DDR4_PHY_CONTROL_REGS_STATUS_MACRO_RESERVED 0x1023fc44
 #define SJC16_DDR4_PHY_CONTROL_REGS_STATUS_MACRO_RESERVED_BASE 0xc44
 #define SJC16_DDR4_PHY_CONTROL_REGS_STATUS_MACRO_RESERVED_RESERVED_MASK 0xffffffff
 #define SJC16_DDR4_PHY_CONTROL_REGS_STATUS_MACRO_RESERVED_RESERVED_ALIGN 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_STATUS_MACRO_RESERVED_RESERVED_BITS 32
 #define SJC16_DDR4_PHY_CONTROL_REGS_STATUS_MACRO_RESERVED_RESERVED_SHIFT 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_STATUS_MACRO_RESERVED_RESERVED_RESETVALUE 0x00000000
 #define SJC16_DDR4_PHY_CONTROL_REGS_STATUS_MACRO_RESERVED_ALL_MASK 0xffffffff
 #define SJC16_DDR4_PHY_CONTROL_REGS_STATUS_MACRO_RESERVED_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_STATUS_MACRO_RESERVED_ALL_BITS 32
 #define SJC16_DDR4_PHY_CONTROL_REGS_STATUS_MACRO_RESERVED_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_STATUS_MACRO_RESERVED_ALL_MASK 0xffffffff
 #define SJC16_DDR4_PHY_CONTROL_REGS_STATUS_MACRO_RESERVED_ALL_ALIGN 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_STATUS_MACRO_RESERVED_ALL_BITS 32
 #define SJC16_DDR4_PHY_CONTROL_REGS_STATUS_MACRO_RESERVED_ALL_SHIFT 0
 #define SJC16_DDR4_PHY_CONTROL_REGS_STATUS_MACRO_RESERVED_DATAMASK 0xffffffff
 #define SJC16_DDR4_PHY_CONTROL_REGS_STATUS_MACRO_RESERVED_RDWRMASK 0x00000000
 #define SJC16_DDR4_PHY_CONTROL_REGS_STATUS_MACRO_RESERVED_RESETVALUE 0x00000000