phy_and28_f0.h (905306B)
1 /* 2 * 3 * 4 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 5 * 6 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 7 * 8 * THIS SOFTWARE MAY ONLY BE USED SUBJECT TO AN EXECUTED SOFTWARE LICENSE 9 * AGREEMENT BETWEEN THE USER AND BROADCOM. YOU HAVE NO RIGHT TO USE OR 10 * EXPLOIT THIS MATERIAL EXCEPT SUBJECT TO THE TERMS OF SUCH AN AGREEMENT. 11 * 12 * $brcm_Workfile: $ 13 * $brcm_Revision: $ 14 * $brcm_Date: $ 15 * 16 * Module Description: 17 * DO NOT EDIT THIS FILE DIRECTLY 18 * 19 * This module was generated magically with RDB from a source description 20 * file. You must edit the source file for changes to be made to this file. 21 * 22 * 23 * Date: Generated on Fri Oct 3 13:28:10 2014 24 * MD5 Checksum 53eb1bfa56a0a70733d895957409458e 25 * 26 * Compiled with: RDB Utility 5.0 27 * RDB Parser 3.0 28 * rdb2macro.pm 4.0 29 * Perl Interpreter 5.014001 30 * Operating System linux 31 * 32 * Spec Versions: DDR34_PHY_ADDR_CTL 04 33 * DDR34_PHY_BYTE_LANE 04 34 * 35 * RDB Files: /projects/ntsw_ddr/users/mbasoglu/sw/SDK_TOT/src/soc/phy/regs/ddr34/ddr34_phy_top_blockdef.rdb 36 * /projects/ntsw_ddr/users/mbasoglu/sw/SDK_TOT/src/soc/phy/regs/ddr34/ddr34_phy_addr_ctl.rdb 37 * /projects/ntsw_ddr/users/mbasoglu/sw/SDK_TOT/src/soc/phy/regs/ddr34/ddr34_phy_regtypes.rdb 38 * /projects/ntsw_ddr/users/mbasoglu/sw/SDK_TOT/src/soc/phy/regs/ddr34/ddr34_phy_byte_lane.rdb 39 * /projects/ntsw_ddr/users/mbasoglu/sw/SDK_TOT/src/soc/phy/regs/ddr34/ddr34_phy_regtypes.rdb 40 * /projects/ntsw_ddr/users/mbasoglu/sw/SDK_TOT/src/soc/phy/regs/ddr34/ddr34_phy_byte_lane_regtypes.rdb 41 * 42 * Revision History: 43 * 44 * $brcm_Log: $ 45 */ 46 47 #ifndef DDR34_F0_PHY_H__ 48 #define DDR34_F0_PHY_H__ 49 50 /** 51 * m = memory, c = core, r = register, f = field, d = data. 52 */ 53 #if !defined(GET_FIELD) && !defined(SET_FIELD) 54 #define BRCM_ALIGN(c,r,f) c##_##r##_##f##_ALIGN 55 #define BRCM_BITS(c,r,f) c##_##r##_##f##_BITS 56 #define BRCM_MASK(c,r,f) c##_##r##_##f##_MASK 57 #define BRCM_SHIFT(c,r,f) c##_##r##_##f##_SHIFT 58 59 #define GET_FIELD(m,c,r,f) \ 60 ((((m) & BRCM_MASK(c,r,f)) >> BRCM_SHIFT(c,r,f)) << BRCM_ALIGN(c,r,f)) 61 62 #define SET_FIELD(m,c,r,f,d) \ 63 ((m) = (((m) & ~BRCM_MASK(c,r,f)) | ((((d) >> BRCM_ALIGN(c,r,f)) << \ 64 BRCM_SHIFT(c,r,f)) & BRCM_MASK(c,r,f))) \ 65 ) 66 67 #define SET_TYPE_FIELD(m,c,r,f,d) SET_FIELD(m,c,r,f,c##_##d) 68 #define SET_NAME_FIELD(m,c,r,f,d) SET_FIELD(m,c,r,f,c##_##r##_##f##_##d) 69 #define SET_VALUE_FIELD(m,c,r,f,d) SET_FIELD(m,c,r,f,d) 70 71 #endif /* GET & SET */ 72 73 /**************************************************************************** 74 * DDR34_F0_PHY_CONTROL_REGS 75 */ 76 #define DDR34_F0_PHY_CONTROL_REGS_REVISION 0x00000000 77 #define DDR34_F0_PHY_CONTROL_REGS_PLL_STATUS 0x00000004 78 #define DDR34_F0_PHY_CONTROL_REGS_PLL_CONFIG 0x00000008 79 #define DDR34_F0_PHY_CONTROL_REGS_PLL_CONTROL1 0x0000000c 80 #define DDR34_F0_PHY_CONTROL_REGS_PLL_CONTROL2 0x00000010 81 #define DDR34_F0_PHY_CONTROL_REGS_PLL_CONTROL3 0x00000014 82 #define DDR34_F0_PHY_CONTROL_REGS_PLL_DIVIDERS 0x00000018 83 #define DDR34_F0_PHY_CONTROL_REGS_PLL_FRAC_DIVIDER 0x0000001c 84 #define DDR34_F0_PHY_CONTROL_REGS_PLL_SS_CONTROL 0x00000020 85 #define DDR34_F0_PHY_CONTROL_REGS_PLL_SS_LIMIT 0x00000024 86 #define DDR34_F0_PHY_CONTROL_REGS_AUX_CONTROL 0x00000028 87 #define DDR34_F0_PHY_CONTROL_REGS_IDLE_PAD_CONTROL 0x0000002c 88 #define DDR34_F0_PHY_CONTROL_REGS_IDLE_PAD_ENABLE0 0x00000030 89 #define DDR34_F0_PHY_CONTROL_REGS_IDLE_PAD_ENABLE1 0x00000034 90 #define DDR34_F0_PHY_CONTROL_REGS_DRIVE_PAD_CTL 0x00000038 91 #define DDR34_F0_PHY_CONTROL_REGS_DRIVE_PAD_CTL_2T 0x0000003c 92 #define DDR34_F0_PHY_CONTROL_REGS_STATIC_PAD_CTL 0x00000040 93 #define DDR34_F0_PHY_CONTROL_REGS_DRAM_CONFIG 0x00000044 94 #define DDR34_F0_PHY_CONTROL_REGS_DRAM_TIMING1 0x00000048 95 #define DDR34_F0_PHY_CONTROL_REGS_DRAM_TIMING2 0x0000004c 96 #define DDR34_F0_PHY_CONTROL_REGS_DRAM_TIMING3 0x00000050 97 #define DDR34_F0_PHY_CONTROL_REGS_DRAM_TIMING4 0x00000054 98 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CALIBRATE 0x00000058 99 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CALIB_STATUS1 0x0000005c 100 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CALIB_STATUS2 0x00000060 101 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_CONTROL 0x00000064 102 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_REF 0x00000068 103 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_STATUS 0x0000006c 104 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDE 0x00000070 105 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_OUT_CONTROL 0x00000074 106 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS 0x00000078 107 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_CLEAR 0x0000007c 108 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD00 0x00000080 109 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD01 0x00000084 110 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD02 0x00000088 111 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD03 0x0000008c 112 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD04 0x00000090 113 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD05 0x00000094 114 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD06 0x00000098 115 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD07 0x0000009c 116 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD08 0x000000a0 117 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD09 0x000000a4 118 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD10 0x000000a8 119 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD11 0x000000ac 120 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD12 0x000000b0 121 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD13 0x000000b4 122 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD14 0x000000b8 123 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD15 0x000000bc 124 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_BA0 0x000000c0 125 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_BA1 0x000000c4 126 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_BA2 0x000000c8 127 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AUX0 0x000000cc 128 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AUX1 0x000000d0 129 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AUX2 0x000000d4 130 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_CS0 0x000000d8 131 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_CS1 0x000000dc 132 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_PAR 0x000000e0 133 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_RAS_N 0x000000e4 134 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_CAS_N 0x000000e8 135 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_CKE 0x000000ec 136 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_RST_N 0x000000f0 137 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_ODT 0x000000f4 138 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_WE_N 0x000000f8 139 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK 0x000000fc 140 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CLK_CONTROL 0x00000100 141 #define DDR34_F0_PHY_CONTROL_REGS_VDL_LDE_CONTROL 0x00000104 142 #define DDR34_F0_PHY_CONTROL_REGS_CMD_CYC_DLY 0x00000108 143 #define DDR34_F0_PHY_CONTROL_REGS_UPDATE_VDL 0x0000010c 144 #define DDR34_F0_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1 0x00000110 145 #define DDR34_F0_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2 0x00000114 146 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG1 0x00000118 147 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_AUX_REG1 0x0000011c 148 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG2 0x00000120 149 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_AUX_REG2 0x00000124 150 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG3 0x00000128 151 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_AUX_REG3 0x0000012c 152 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG4 0x00000130 153 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_AUX_REG4 0x00000134 154 #define DDR34_F0_PHY_CONTROL_REGS_MODE_REG0 0x00000138 155 #define DDR34_F0_PHY_CONTROL_REGS_MODE_REG1 0x0000013c 156 #define DDR34_F0_PHY_CONTROL_REGS_MODE_REG2 0x00000140 157 #define DDR34_F0_PHY_CONTROL_REGS_MODE_REG3 0x00000144 158 #define DDR34_F0_PHY_CONTROL_REGS_MODE_REG4 0x00000148 159 #define DDR34_F0_PHY_CONTROL_REGS_MODE_REG5 0x0000014c 160 #define DDR34_F0_PHY_CONTROL_REGS_MODE_REG6 0x00000150 161 #define DDR34_F0_PHY_CONTROL_REGS_MODE_REG7 0x00000154 162 #define DDR34_F0_PHY_CONTROL_REGS_MODE_REG8 0x00000158 163 #define DDR34_F0_PHY_CONTROL_REGS_MODE_REG15 0x0000015c 164 #define DDR34_F0_PHY_CONTROL_REGS_MODE_REG63 0x00000160 165 #define DDR34_F0_PHY_CONTROL_REGS_ALERT_CLEAR 0x00000164 166 #define DDR34_F0_PHY_CONTROL_REGS_ALERT_STATUS 0x00000168 167 #define DDR34_F0_PHY_CONTROL_REGS_ALERT_DFI 0x0000016c 168 #define DDR34_F0_PHY_CONTROL_REGS_CA_PLAYBACK_CONTROL 0x00000170 169 #define DDR34_F0_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS0 0x00000174 170 #define DDR34_F0_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS1 0x00000178 171 #define DDR34_F0_PHY_CONTROL_REGS_WRITE_LEVELING_CONTROL 0x0000017c 172 #define DDR34_F0_PHY_CONTROL_REGS_WRITE_LEVELING_STATUS 0x00000180 173 #define DDR34_F0_PHY_CONTROL_REGS_READ_ENABLE_CONTROL 0x00000184 174 #define DDR34_F0_PHY_CONTROL_REGS_READ_ENABLE_STATUS 0x00000188 175 #define DDR34_F0_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL 0x0000018c 176 #define DDR34_F0_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS 0x00000190 177 #define DDR34_F0_PHY_CONTROL_REGS_VIRTUAL_VTT_CONNECTIONS 0x00000194 178 #define DDR34_F0_PHY_CONTROL_REGS_VIRTUAL_VTT_OVERRIDE 0x00000198 179 #define DDR34_F0_PHY_CONTROL_REGS_VREF_DAC_CONTROL 0x0000019c 180 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_CNTRL 0x000001a0 181 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_SEED 0x000001a4 182 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_CA_MASK 0x000001a8 183 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_DQ_MASK1 0x000001ac 184 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_DQ_MASK2 0x000001b0 185 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_STATUS 0x000001b4 186 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_CTL_STATUS 0x000001b8 187 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_BL0_STATUS 0x000001bc 188 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_BL1_STATUS 0x000001c0 189 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_BL2_STATUS 0x000001c4 190 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_BL3_STATUS 0x000001c8 191 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_BL4_STATUS 0x000001cc 192 #define DDR34_F0_PHY_CONTROL_REGS_STANDBY_CONTROL 0x000001d0 193 #define DDR34_F0_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE 0x000001d4 194 #define DDR34_F0_PHY_CONTROL_REGS_DEBUG_MUX_CONTROL 0x000001d8 195 #define DDR34_F0_PHY_CONTROL_REGS_DFI_CNTRL 0x000001dc 196 #define DDR34_F0_PHY_CONTROL_REGS_WRITE_ODT_CNTRL 0x000001e0 197 #define DDR34_F0_PHY_CONTROL_REGS_ABI_PAR_CNTRL 0x000001e4 198 #define DDR34_F0_PHY_CONTROL_REGS_ZQ_CAL 0x000001e8 199 #define DDR34_F0_PHY_CONTROL_REGS_ZQ_CAL2 0x000001ec 200 #define DDR34_F0_PHY_CONTROL_REGS_RO_PROC_MON_CTL 0x000001f0 201 #define DDR34_F0_PHY_CONTROL_REGS_RO_PROC_MON_STATUS 0x000001f4 202 #define DDR34_F0_PHY_CONTROL_REGS_CK_DRIVE_PAD_CTL 0x000001f8 203 #define DDR34_F0_PHY_CONTROL_REGS_BYTE_LANE_ALIGN_MASKS 0x000001fc 204 #define DDR34_F0_PHY_CONTROL_REGS_CLOCK_IDLE 0x00000200 205 #define DDR34_F0_PHY_CONTROL_REGS_AC_SPARE_REG 0x00000204 206 207 /**************************************************************************** 208 * DDR34_F0_PHY_BYTE_LANE_0 209 */ 210 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS 0x00000400 211 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0 0x00000404 212 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1 0x00000408 213 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2 0x0000040c 214 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3 0x00000410 215 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4 0x00000414 216 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5 0x00000418 217 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6 0x0000041c 218 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7 0x00000420 219 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DM 0x00000424 220 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_ALERT 0x00000428 221 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSP 0x0000042c 222 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSN 0x00000430 223 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0P 0x00000434 224 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0N 0x00000438 225 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1P 0x0000043c 226 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1N 0x00000440 227 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2P 0x00000444 228 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2N 0x00000448 229 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3P 0x0000044c 230 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3N 0x00000450 231 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4P 0x00000454 232 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4N 0x00000458 233 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5P 0x0000045c 234 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5N 0x00000460 235 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6P 0x00000464 236 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6N 0x00000468 237 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7P 0x0000046c 238 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7N 0x00000470 239 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMP 0x00000474 240 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMN 0x00000478 241 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0 0x0000047c 242 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1 0x00000480 243 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CLK_CONTROL 0x00000484 244 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_LDE_CONTROL 0x00000488 245 #define DDR34_F0_PHY_BYTE_LANE_0_RD_EN_DLY_CYC 0x0000048c 246 #define DDR34_F0_PHY_BYTE_LANE_0_WR_CHAN_DLY_CYC 0x00000490 247 #define DDR34_F0_PHY_BYTE_LANE_0_READ_CONTROL 0x00000494 248 #define DDR34_F0_PHY_BYTE_LANE_0_READ_FIFO_ADDR 0x00000498 249 #define DDR34_F0_PHY_BYTE_LANE_0_READ_FIFO_DATA 0x0000049c 250 #define DDR34_F0_PHY_BYTE_LANE_0_READ_FIFO_DM_DBI 0x000004a0 251 #define DDR34_F0_PHY_BYTE_LANE_0_READ_FIFO_STATUS 0x000004a4 252 #define DDR34_F0_PHY_BYTE_LANE_0_READ_FIFO_CLEAR 0x000004a8 253 #define DDR34_F0_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL 0x000004ac 254 #define DDR34_F0_PHY_BYTE_LANE_0_DRIVE_PAD_CTL 0x000004b0 255 #define DDR34_F0_PHY_BYTE_LANE_0_DQSP_DRIVE_PAD_CTL 0x000004b4 256 #define DDR34_F0_PHY_BYTE_LANE_0_DQSN_DRIVE_PAD_CTL 0x000004b8 257 #define DDR34_F0_PHY_BYTE_LANE_0_ALERT_DRIVE_PAD_CTL 0x000004bc 258 #define DDR34_F0_PHY_BYTE_LANE_0_RD_EN_DRIVE_PAD_CTL 0x000004c0 259 #define DDR34_F0_PHY_BYTE_LANE_0_STATIC_PAD_CTL 0x000004c4 260 #define DDR34_F0_PHY_BYTE_LANE_0_WR_PREAMBLE_MODE 0x000004c8 261 #define DDR34_F0_PHY_BYTE_LANE_0_ODT_CONTROL 0x000004cc 262 #define DDR34_F0_PHY_BYTE_LANE_0_CLOCK_ENABLE 0x000004d0 263 #define DDR34_F0_PHY_BYTE_LANE_0_CLOCK_IDLE 0x000004d4 264 #define DDR34_F0_PHY_BYTE_LANE_0_BL_SPARE_REG 0x000004d8 265 266 /**************************************************************************** 267 * DDR34_F0_PHY_BYTE_LANE_1 268 */ 269 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS 0x00000600 270 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0 0x00000604 271 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1 0x00000608 272 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2 0x0000060c 273 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3 0x00000610 274 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4 0x00000614 275 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5 0x00000618 276 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6 0x0000061c 277 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7 0x00000620 278 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DM 0x00000624 279 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_ALERT 0x00000628 280 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSP 0x0000062c 281 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSN 0x00000630 282 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0P 0x00000634 283 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0N 0x00000638 284 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1P 0x0000063c 285 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1N 0x00000640 286 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2P 0x00000644 287 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2N 0x00000648 288 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3P 0x0000064c 289 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3N 0x00000650 290 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4P 0x00000654 291 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4N 0x00000658 292 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5P 0x0000065c 293 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5N 0x00000660 294 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6P 0x00000664 295 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6N 0x00000668 296 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7P 0x0000066c 297 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7N 0x00000670 298 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMP 0x00000674 299 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMN 0x00000678 300 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0 0x0000067c 301 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1 0x00000680 302 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CLK_CONTROL 0x00000684 303 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_LDE_CONTROL 0x00000688 304 #define DDR34_F0_PHY_BYTE_LANE_1_RD_EN_DLY_CYC 0x0000068c 305 #define DDR34_F0_PHY_BYTE_LANE_1_WR_CHAN_DLY_CYC 0x00000690 306 #define DDR34_F0_PHY_BYTE_LANE_1_READ_CONTROL 0x00000694 307 #define DDR34_F0_PHY_BYTE_LANE_1_READ_FIFO_ADDR 0x00000698 308 #define DDR34_F0_PHY_BYTE_LANE_1_READ_FIFO_DATA 0x0000069c 309 #define DDR34_F0_PHY_BYTE_LANE_1_READ_FIFO_DM_DBI 0x000006a0 310 #define DDR34_F0_PHY_BYTE_LANE_1_READ_FIFO_STATUS 0x000006a4 311 #define DDR34_F0_PHY_BYTE_LANE_1_READ_FIFO_CLEAR 0x000006a8 312 #define DDR34_F0_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL 0x000006ac 313 #define DDR34_F0_PHY_BYTE_LANE_1_DRIVE_PAD_CTL 0x000006b0 314 #define DDR34_F0_PHY_BYTE_LANE_1_DQSP_DRIVE_PAD_CTL 0x000006b4 315 #define DDR34_F0_PHY_BYTE_LANE_1_DQSN_DRIVE_PAD_CTL 0x000006b8 316 #define DDR34_F0_PHY_BYTE_LANE_1_ALERT_DRIVE_PAD_CTL 0x000006bc 317 #define DDR34_F0_PHY_BYTE_LANE_1_RD_EN_DRIVE_PAD_CTL 0x000006c0 318 #define DDR34_F0_PHY_BYTE_LANE_1_STATIC_PAD_CTL 0x000006c4 319 #define DDR34_F0_PHY_BYTE_LANE_1_WR_PREAMBLE_MODE 0x000006c8 320 #define DDR34_F0_PHY_BYTE_LANE_1_ODT_CONTROL 0x000006cc 321 #define DDR34_F0_PHY_BYTE_LANE_1_CLOCK_ENABLE 0x000006d0 322 #define DDR34_F0_PHY_BYTE_LANE_1_CLOCK_IDLE 0x000006d4 323 #define DDR34_F0_PHY_BYTE_LANE_1_BL_SPARE_REG 0x000006d8 324 325 /**************************************************************************** 326 * DDR34_F0_PHY_BYTE_LANE_2 327 */ 328 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS 0x00000800 329 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ0 0x00000804 330 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ1 0x00000808 331 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ2 0x0000080c 332 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ3 0x00000810 333 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ4 0x00000814 334 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ5 0x00000818 335 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ6 0x0000081c 336 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ7 0x00000820 337 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DM 0x00000824 338 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_ALERT 0x00000828 339 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSP 0x0000082c 340 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSN 0x00000830 341 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0P 0x00000834 342 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0N 0x00000838 343 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1P 0x0000083c 344 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1N 0x00000840 345 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2P 0x00000844 346 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2N 0x00000848 347 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3P 0x0000084c 348 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3N 0x00000850 349 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4P 0x00000854 350 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4N 0x00000858 351 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5P 0x0000085c 352 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5N 0x00000860 353 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6P 0x00000864 354 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6N 0x00000868 355 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7P 0x0000086c 356 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7N 0x00000870 357 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMP 0x00000874 358 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMN 0x00000878 359 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS0 0x0000087c 360 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS1 0x00000880 361 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CLK_CONTROL 0x00000884 362 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_LDE_CONTROL 0x00000888 363 #define DDR34_F0_PHY_BYTE_LANE_2_RD_EN_DLY_CYC 0x0000088c 364 #define DDR34_F0_PHY_BYTE_LANE_2_WR_CHAN_DLY_CYC 0x00000890 365 #define DDR34_F0_PHY_BYTE_LANE_2_READ_CONTROL 0x00000894 366 #define DDR34_F0_PHY_BYTE_LANE_2_READ_FIFO_ADDR 0x00000898 367 #define DDR34_F0_PHY_BYTE_LANE_2_READ_FIFO_DATA 0x0000089c 368 #define DDR34_F0_PHY_BYTE_LANE_2_READ_FIFO_DM_DBI 0x000008a0 369 #define DDR34_F0_PHY_BYTE_LANE_2_READ_FIFO_STATUS 0x000008a4 370 #define DDR34_F0_PHY_BYTE_LANE_2_READ_FIFO_CLEAR 0x000008a8 371 #define DDR34_F0_PHY_BYTE_LANE_2_IDLE_PAD_CONTROL 0x000008ac 372 #define DDR34_F0_PHY_BYTE_LANE_2_DRIVE_PAD_CTL 0x000008b0 373 #define DDR34_F0_PHY_BYTE_LANE_2_DQSP_DRIVE_PAD_CTL 0x000008b4 374 #define DDR34_F0_PHY_BYTE_LANE_2_DQSN_DRIVE_PAD_CTL 0x000008b8 375 #define DDR34_F0_PHY_BYTE_LANE_2_ALERT_DRIVE_PAD_CTL 0x000008bc 376 #define DDR34_F0_PHY_BYTE_LANE_2_RD_EN_DRIVE_PAD_CTL 0x000008c0 377 #define DDR34_F0_PHY_BYTE_LANE_2_STATIC_PAD_CTL 0x000008c4 378 #define DDR34_F0_PHY_BYTE_LANE_2_WR_PREAMBLE_MODE 0x000008c8 379 #define DDR34_F0_PHY_BYTE_LANE_2_ODT_CONTROL 0x000008cc 380 #define DDR34_F0_PHY_BYTE_LANE_2_CLOCK_ENABLE 0x000008d0 381 #define DDR34_F0_PHY_BYTE_LANE_2_CLOCK_IDLE 0x000008d4 382 #define DDR34_F0_PHY_BYTE_LANE_2_BL_SPARE_REG 0x000008d8 383 384 /**************************************************************************** 385 * DDR34_F0_PHY_BYTE_LANE_3 386 */ 387 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS 0x00000a00 388 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ0 0x00000a04 389 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ1 0x00000a08 390 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ2 0x00000a0c 391 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ3 0x00000a10 392 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ4 0x00000a14 393 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ5 0x00000a18 394 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ6 0x00000a1c 395 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ7 0x00000a20 396 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DM 0x00000a24 397 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_ALERT 0x00000a28 398 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSP 0x00000a2c 399 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSN 0x00000a30 400 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0P 0x00000a34 401 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0N 0x00000a38 402 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1P 0x00000a3c 403 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1N 0x00000a40 404 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2P 0x00000a44 405 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2N 0x00000a48 406 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3P 0x00000a4c 407 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3N 0x00000a50 408 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4P 0x00000a54 409 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4N 0x00000a58 410 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5P 0x00000a5c 411 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5N 0x00000a60 412 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6P 0x00000a64 413 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6N 0x00000a68 414 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7P 0x00000a6c 415 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7N 0x00000a70 416 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMP 0x00000a74 417 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMN 0x00000a78 418 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS0 0x00000a7c 419 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS1 0x00000a80 420 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CLK_CONTROL 0x00000a84 421 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_LDE_CONTROL 0x00000a88 422 #define DDR34_F0_PHY_BYTE_LANE_3_RD_EN_DLY_CYC 0x00000a8c 423 #define DDR34_F0_PHY_BYTE_LANE_3_WR_CHAN_DLY_CYC 0x00000a90 424 #define DDR34_F0_PHY_BYTE_LANE_3_READ_CONTROL 0x00000a94 425 #define DDR34_F0_PHY_BYTE_LANE_3_READ_FIFO_ADDR 0x00000a98 426 #define DDR34_F0_PHY_BYTE_LANE_3_READ_FIFO_DATA 0x00000a9c 427 #define DDR34_F0_PHY_BYTE_LANE_3_READ_FIFO_DM_DBI 0x00000aa0 428 #define DDR34_F0_PHY_BYTE_LANE_3_READ_FIFO_STATUS 0x00000aa4 429 #define DDR34_F0_PHY_BYTE_LANE_3_READ_FIFO_CLEAR 0x00000aa8 430 #define DDR34_F0_PHY_BYTE_LANE_3_IDLE_PAD_CONTROL 0x00000aac 431 #define DDR34_F0_PHY_BYTE_LANE_3_DRIVE_PAD_CTL 0x00000ab0 432 #define DDR34_F0_PHY_BYTE_LANE_3_DQSP_DRIVE_PAD_CTL 0x00000ab4 433 #define DDR34_F0_PHY_BYTE_LANE_3_DQSN_DRIVE_PAD_CTL 0x00000ab8 434 #define DDR34_F0_PHY_BYTE_LANE_3_ALERT_DRIVE_PAD_CTL 0x00000abc 435 #define DDR34_F0_PHY_BYTE_LANE_3_RD_EN_DRIVE_PAD_CTL 0x00000ac0 436 #define DDR34_F0_PHY_BYTE_LANE_3_STATIC_PAD_CTL 0x00000ac4 437 #define DDR34_F0_PHY_BYTE_LANE_3_WR_PREAMBLE_MODE 0x00000ac8 438 #define DDR34_F0_PHY_BYTE_LANE_3_ODT_CONTROL 0x00000acc 439 #define DDR34_F0_PHY_BYTE_LANE_3_CLOCK_ENABLE 0x00000ad0 440 #define DDR34_F0_PHY_BYTE_LANE_3_CLOCK_IDLE 0x00000ad4 441 #define DDR34_F0_PHY_BYTE_LANE_3_BL_SPARE_REG 0x00000ad8 442 443 444 /**************************************************************************** 445 * DDR34_F0_PHY_CONTROL_REGS :: REVISION 446 */ 447 /* DDR34_F0_PHY_CONTROL_REGS :: REVISION :: reserved0 [31:25] */ 448 #define DDR34_F0_PHY_CONTROL_REGS_REVISION_RESERVED0_MASK 0xfe000000 449 #define DDR34_F0_PHY_CONTROL_REGS_REVISION_RESERVED0_ALIGN 0 450 #define DDR34_F0_PHY_CONTROL_REGS_REVISION_RESERVED0_BITS 7 451 #define DDR34_F0_PHY_CONTROL_REGS_REVISION_RESERVED0_SHIFT 25 452 453 /* DDR34_F0_PHY_CONTROL_REGS :: REVISION :: PERFORMANCE [24:23] */ 454 #define DDR34_F0_PHY_CONTROL_REGS_REVISION_PERFORMANCE_MASK 0x01800000 455 #define DDR34_F0_PHY_CONTROL_REGS_REVISION_PERFORMANCE_ALIGN 0 456 #define DDR34_F0_PHY_CONTROL_REGS_REVISION_PERFORMANCE_BITS 2 457 #define DDR34_F0_PHY_CONTROL_REGS_REVISION_PERFORMANCE_SHIFT 23 458 459 /* DDR34_F0_PHY_CONTROL_REGS :: REVISION :: TECHNOLOGY [22:20] */ 460 #define DDR34_F0_PHY_CONTROL_REGS_REVISION_TECHNOLOGY_MASK 0x00700000 461 #define DDR34_F0_PHY_CONTROL_REGS_REVISION_TECHNOLOGY_ALIGN 0 462 #define DDR34_F0_PHY_CONTROL_REGS_REVISION_TECHNOLOGY_BITS 3 463 #define DDR34_F0_PHY_CONTROL_REGS_REVISION_TECHNOLOGY_SHIFT 20 464 465 /* DDR34_F0_PHY_CONTROL_REGS :: REVISION :: WB [19:19] */ 466 #define DDR34_F0_PHY_CONTROL_REGS_REVISION_WB_MASK 0x00080000 467 #define DDR34_F0_PHY_CONTROL_REGS_REVISION_WB_ALIGN 0 468 #define DDR34_F0_PHY_CONTROL_REGS_REVISION_WB_BITS 1 469 #define DDR34_F0_PHY_CONTROL_REGS_REVISION_WB_SHIFT 19 470 471 /* DDR34_F0_PHY_CONTROL_REGS :: REVISION :: BITS [18:16] */ 472 #define DDR34_F0_PHY_CONTROL_REGS_REVISION_BITS_MASK 0x00070000 473 #define DDR34_F0_PHY_CONTROL_REGS_REVISION_BITS_ALIGN 0 474 #define DDR34_F0_PHY_CONTROL_REGS_REVISION_BITS_BITS 3 475 #define DDR34_F0_PHY_CONTROL_REGS_REVISION_BITS_SHIFT 16 476 477 /* DDR34_F0_PHY_CONTROL_REGS :: REVISION :: MAJOR [15:08] */ 478 #define DDR34_F0_PHY_CONTROL_REGS_REVISION_MAJOR_MASK 0x0000ff00 479 #define DDR34_F0_PHY_CONTROL_REGS_REVISION_MAJOR_ALIGN 0 480 #define DDR34_F0_PHY_CONTROL_REGS_REVISION_MAJOR_BITS 8 481 #define DDR34_F0_PHY_CONTROL_REGS_REVISION_MAJOR_SHIFT 8 482 483 /* DDR34_F0_PHY_CONTROL_REGS :: REVISION :: MINOR [07:00] */ 484 #define DDR34_F0_PHY_CONTROL_REGS_REVISION_MINOR_MASK 0x000000ff 485 #define DDR34_F0_PHY_CONTROL_REGS_REVISION_MINOR_ALIGN 0 486 #define DDR34_F0_PHY_CONTROL_REGS_REVISION_MINOR_BITS 8 487 #define DDR34_F0_PHY_CONTROL_REGS_REVISION_MINOR_SHIFT 0 488 489 490 /**************************************************************************** 491 * DDR34_F0_PHY_CONTROL_REGS :: PLL_STATUS 492 */ 493 /* DDR34_F0_PHY_CONTROL_REGS :: PLL_STATUS :: reserved0 [31:17] */ 494 #define DDR34_F0_PHY_CONTROL_REGS_PLL_STATUS_RESERVED0_MASK 0xfffe0000 495 #define DDR34_F0_PHY_CONTROL_REGS_PLL_STATUS_RESERVED0_ALIGN 0 496 #define DDR34_F0_PHY_CONTROL_REGS_PLL_STATUS_RESERVED0_BITS 15 497 #define DDR34_F0_PHY_CONTROL_REGS_PLL_STATUS_RESERVED0_SHIFT 17 498 499 /* DDR34_F0_PHY_CONTROL_REGS :: PLL_STATUS :: LOCK_LOST [16:16] */ 500 #define DDR34_F0_PHY_CONTROL_REGS_PLL_STATUS_LOCK_LOST_MASK 0x00010000 501 #define DDR34_F0_PHY_CONTROL_REGS_PLL_STATUS_LOCK_LOST_ALIGN 0 502 #define DDR34_F0_PHY_CONTROL_REGS_PLL_STATUS_LOCK_LOST_BITS 1 503 #define DDR34_F0_PHY_CONTROL_REGS_PLL_STATUS_LOCK_LOST_SHIFT 16 504 505 /* DDR34_F0_PHY_CONTROL_REGS :: PLL_STATUS :: CLOCKING_8X [15:15] */ 506 #define DDR34_F0_PHY_CONTROL_REGS_PLL_STATUS_CLOCKING_8X_MASK 0x00008000 507 #define DDR34_F0_PHY_CONTROL_REGS_PLL_STATUS_CLOCKING_8X_ALIGN 0 508 #define DDR34_F0_PHY_CONTROL_REGS_PLL_STATUS_CLOCKING_8X_BITS 1 509 #define DDR34_F0_PHY_CONTROL_REGS_PLL_STATUS_CLOCKING_8X_SHIFT 15 510 511 /* DDR34_F0_PHY_CONTROL_REGS :: PLL_STATUS :: CLOCKING_4X [14:14] */ 512 #define DDR34_F0_PHY_CONTROL_REGS_PLL_STATUS_CLOCKING_4X_MASK 0x00004000 513 #define DDR34_F0_PHY_CONTROL_REGS_PLL_STATUS_CLOCKING_4X_ALIGN 0 514 #define DDR34_F0_PHY_CONTROL_REGS_PLL_STATUS_CLOCKING_4X_BITS 1 515 #define DDR34_F0_PHY_CONTROL_REGS_PLL_STATUS_CLOCKING_4X_SHIFT 14 516 517 /* DDR34_F0_PHY_CONTROL_REGS :: PLL_STATUS :: CLOCKING_2X [13:13] */ 518 #define DDR34_F0_PHY_CONTROL_REGS_PLL_STATUS_CLOCKING_2X_MASK 0x00002000 519 #define DDR34_F0_PHY_CONTROL_REGS_PLL_STATUS_CLOCKING_2X_ALIGN 0 520 #define DDR34_F0_PHY_CONTROL_REGS_PLL_STATUS_CLOCKING_2X_BITS 1 521 #define DDR34_F0_PHY_CONTROL_REGS_PLL_STATUS_CLOCKING_2X_SHIFT 13 522 523 /* DDR34_F0_PHY_CONTROL_REGS :: PLL_STATUS :: STATUS [12:01] */ 524 #define DDR34_F0_PHY_CONTROL_REGS_PLL_STATUS_STATUS_MASK 0x00001ffe 525 #define DDR34_F0_PHY_CONTROL_REGS_PLL_STATUS_STATUS_ALIGN 0 526 #define DDR34_F0_PHY_CONTROL_REGS_PLL_STATUS_STATUS_BITS 12 527 #define DDR34_F0_PHY_CONTROL_REGS_PLL_STATUS_STATUS_SHIFT 1 528 529 /* DDR34_F0_PHY_CONTROL_REGS :: PLL_STATUS :: LOCK [00:00] */ 530 #define DDR34_F0_PHY_CONTROL_REGS_PLL_STATUS_LOCK_MASK 0x00000001 531 #define DDR34_F0_PHY_CONTROL_REGS_PLL_STATUS_LOCK_ALIGN 0 532 #define DDR34_F0_PHY_CONTROL_REGS_PLL_STATUS_LOCK_BITS 1 533 #define DDR34_F0_PHY_CONTROL_REGS_PLL_STATUS_LOCK_SHIFT 0 534 535 536 /**************************************************************************** 537 * DDR34_F0_PHY_CONTROL_REGS :: PLL_CONFIG 538 */ 539 /* DDR34_F0_PHY_CONTROL_REGS :: PLL_CONFIG :: reserved0 [31:24] */ 540 #define DDR34_F0_PHY_CONTROL_REGS_PLL_CONFIG_RESERVED0_MASK 0xff000000 541 #define DDR34_F0_PHY_CONTROL_REGS_PLL_CONFIG_RESERVED0_ALIGN 0 542 #define DDR34_F0_PHY_CONTROL_REGS_PLL_CONFIG_RESERVED0_BITS 8 543 #define DDR34_F0_PHY_CONTROL_REGS_PLL_CONFIG_RESERVED0_SHIFT 24 544 545 /* DDR34_F0_PHY_CONTROL_REGS :: PLL_CONFIG :: PLL_LDO_REF_SEL [23:23] */ 546 #define DDR34_F0_PHY_CONTROL_REGS_PLL_CONFIG_PLL_LDO_REF_SEL_MASK 0x00800000 547 #define DDR34_F0_PHY_CONTROL_REGS_PLL_CONFIG_PLL_LDO_REF_SEL_ALIGN 0 548 #define DDR34_F0_PHY_CONTROL_REGS_PLL_CONFIG_PLL_LDO_REF_SEL_BITS 1 549 #define DDR34_F0_PHY_CONTROL_REGS_PLL_CONFIG_PLL_LDO_REF_SEL_SHIFT 23 550 551 /* DDR34_F0_PHY_CONTROL_REGS :: PLL_CONFIG :: PLL_LDO_REF_CTRL [22:21] */ 552 #define DDR34_F0_PHY_CONTROL_REGS_PLL_CONFIG_PLL_LDO_REF_CTRL_MASK 0x00600000 553 #define DDR34_F0_PHY_CONTROL_REGS_PLL_CONFIG_PLL_LDO_REF_CTRL_ALIGN 0 554 #define DDR34_F0_PHY_CONTROL_REGS_PLL_CONFIG_PLL_LDO_REF_CTRL_BITS 2 555 #define DDR34_F0_PHY_CONTROL_REGS_PLL_CONFIG_PLL_LDO_REF_CTRL_SHIFT 21 556 557 /* DDR34_F0_PHY_CONTROL_REGS :: PLL_CONFIG :: PLL_LDO_BIAS [20:19] */ 558 #define DDR34_F0_PHY_CONTROL_REGS_PLL_CONFIG_PLL_LDO_BIAS_MASK 0x00180000 559 #define DDR34_F0_PHY_CONTROL_REGS_PLL_CONFIG_PLL_LDO_BIAS_ALIGN 0 560 #define DDR34_F0_PHY_CONTROL_REGS_PLL_CONFIG_PLL_LDO_BIAS_BITS 2 561 #define DDR34_F0_PHY_CONTROL_REGS_PLL_CONFIG_PLL_LDO_BIAS_SHIFT 19 562 563 /* DDR34_F0_PHY_CONTROL_REGS :: PLL_CONFIG :: PLL_LDO_PWRDOWN [18:18] */ 564 #define DDR34_F0_PHY_CONTROL_REGS_PLL_CONFIG_PLL_LDO_PWRDOWN_MASK 0x00040000 565 #define DDR34_F0_PHY_CONTROL_REGS_PLL_CONFIG_PLL_LDO_PWRDOWN_ALIGN 0 566 #define DDR34_F0_PHY_CONTROL_REGS_PLL_CONFIG_PLL_LDO_PWRDOWN_BITS 1 567 #define DDR34_F0_PHY_CONTROL_REGS_PLL_CONFIG_PLL_LDO_PWRDOWN_SHIFT 18 568 569 /* DDR34_F0_PHY_CONTROL_REGS :: PLL_CONFIG :: HOLD [17:17] */ 570 #define DDR34_F0_PHY_CONTROL_REGS_PLL_CONFIG_HOLD_MASK 0x00020000 571 #define DDR34_F0_PHY_CONTROL_REGS_PLL_CONFIG_HOLD_ALIGN 0 572 #define DDR34_F0_PHY_CONTROL_REGS_PLL_CONFIG_HOLD_BITS 1 573 #define DDR34_F0_PHY_CONTROL_REGS_PLL_CONFIG_HOLD_SHIFT 17 574 575 /* DDR34_F0_PHY_CONTROL_REGS :: PLL_CONFIG :: ENABLE [16:16] */ 576 #define DDR34_F0_PHY_CONTROL_REGS_PLL_CONFIG_ENABLE_MASK 0x00010000 577 #define DDR34_F0_PHY_CONTROL_REGS_PLL_CONFIG_ENABLE_ALIGN 0 578 #define DDR34_F0_PHY_CONTROL_REGS_PLL_CONFIG_ENABLE_BITS 1 579 #define DDR34_F0_PHY_CONTROL_REGS_PLL_CONFIG_ENABLE_SHIFT 16 580 581 /* DDR34_F0_PHY_CONTROL_REGS :: PLL_CONFIG :: reserved1 [15:06] */ 582 #define DDR34_F0_PHY_CONTROL_REGS_PLL_CONFIG_RESERVED1_MASK 0x0000ffc0 583 #define DDR34_F0_PHY_CONTROL_REGS_PLL_CONFIG_RESERVED1_ALIGN 0 584 #define DDR34_F0_PHY_CONTROL_REGS_PLL_CONFIG_RESERVED1_BITS 10 585 #define DDR34_F0_PHY_CONTROL_REGS_PLL_CONFIG_RESERVED1_SHIFT 6 586 587 /* DDR34_F0_PHY_CONTROL_REGS :: PLL_CONFIG :: ENABLE_EXT_CTRL [05:05] */ 588 #define DDR34_F0_PHY_CONTROL_REGS_PLL_CONFIG_ENABLE_EXT_CTRL_MASK 0x00000020 589 #define DDR34_F0_PHY_CONTROL_REGS_PLL_CONFIG_ENABLE_EXT_CTRL_ALIGN 0 590 #define DDR34_F0_PHY_CONTROL_REGS_PLL_CONFIG_ENABLE_EXT_CTRL_BITS 1 591 #define DDR34_F0_PHY_CONTROL_REGS_PLL_CONFIG_ENABLE_EXT_CTRL_SHIFT 5 592 593 /* DDR34_F0_PHY_CONTROL_REGS :: PLL_CONFIG :: RESET_POST_DIV [04:04] */ 594 #define DDR34_F0_PHY_CONTROL_REGS_PLL_CONFIG_RESET_POST_DIV_MASK 0x00000010 595 #define DDR34_F0_PHY_CONTROL_REGS_PLL_CONFIG_RESET_POST_DIV_ALIGN 0 596 #define DDR34_F0_PHY_CONTROL_REGS_PLL_CONFIG_RESET_POST_DIV_BITS 1 597 #define DDR34_F0_PHY_CONTROL_REGS_PLL_CONFIG_RESET_POST_DIV_SHIFT 4 598 599 /* DDR34_F0_PHY_CONTROL_REGS :: PLL_CONFIG :: ISO_OUT [03:03] */ 600 #define DDR34_F0_PHY_CONTROL_REGS_PLL_CONFIG_ISO_OUT_MASK 0x00000008 601 #define DDR34_F0_PHY_CONTROL_REGS_PLL_CONFIG_ISO_OUT_ALIGN 0 602 #define DDR34_F0_PHY_CONTROL_REGS_PLL_CONFIG_ISO_OUT_BITS 1 603 #define DDR34_F0_PHY_CONTROL_REGS_PLL_CONFIG_ISO_OUT_SHIFT 3 604 605 /* DDR34_F0_PHY_CONTROL_REGS :: PLL_CONFIG :: ISO_IN [02:02] */ 606 #define DDR34_F0_PHY_CONTROL_REGS_PLL_CONFIG_ISO_IN_MASK 0x00000004 607 #define DDR34_F0_PHY_CONTROL_REGS_PLL_CONFIG_ISO_IN_ALIGN 0 608 #define DDR34_F0_PHY_CONTROL_REGS_PLL_CONFIG_ISO_IN_BITS 1 609 #define DDR34_F0_PHY_CONTROL_REGS_PLL_CONFIG_ISO_IN_SHIFT 2 610 611 /* DDR34_F0_PHY_CONTROL_REGS :: PLL_CONFIG :: RESET [01:01] */ 612 #define DDR34_F0_PHY_CONTROL_REGS_PLL_CONFIG_RESET_MASK 0x00000002 613 #define DDR34_F0_PHY_CONTROL_REGS_PLL_CONFIG_RESET_ALIGN 0 614 #define DDR34_F0_PHY_CONTROL_REGS_PLL_CONFIG_RESET_BITS 1 615 #define DDR34_F0_PHY_CONTROL_REGS_PLL_CONFIG_RESET_SHIFT 1 616 617 /* DDR34_F0_PHY_CONTROL_REGS :: PLL_CONFIG :: PWRDN [00:00] */ 618 #define DDR34_F0_PHY_CONTROL_REGS_PLL_CONFIG_PWRDN_MASK 0x00000001 619 #define DDR34_F0_PHY_CONTROL_REGS_PLL_CONFIG_PWRDN_ALIGN 0 620 #define DDR34_F0_PHY_CONTROL_REGS_PLL_CONFIG_PWRDN_BITS 1 621 #define DDR34_F0_PHY_CONTROL_REGS_PLL_CONFIG_PWRDN_SHIFT 0 622 623 624 /**************************************************************************** 625 * DDR34_F0_PHY_CONTROL_REGS :: PLL_CONTROL1 626 */ 627 /* DDR34_F0_PHY_CONTROL_REGS :: PLL_CONTROL1 :: reserved0 [31:10] */ 628 #define DDR34_F0_PHY_CONTROL_REGS_PLL_CONTROL1_RESERVED0_MASK 0xfffffc00 629 #define DDR34_F0_PHY_CONTROL_REGS_PLL_CONTROL1_RESERVED0_ALIGN 0 630 #define DDR34_F0_PHY_CONTROL_REGS_PLL_CONTROL1_RESERVED0_BITS 22 631 #define DDR34_F0_PHY_CONTROL_REGS_PLL_CONTROL1_RESERVED0_SHIFT 10 632 633 /* DDR34_F0_PHY_CONTROL_REGS :: PLL_CONTROL1 :: I_KP [09:06] */ 634 #define DDR34_F0_PHY_CONTROL_REGS_PLL_CONTROL1_I_KP_MASK 0x000003c0 635 #define DDR34_F0_PHY_CONTROL_REGS_PLL_CONTROL1_I_KP_ALIGN 0 636 #define DDR34_F0_PHY_CONTROL_REGS_PLL_CONTROL1_I_KP_BITS 4 637 #define DDR34_F0_PHY_CONTROL_REGS_PLL_CONTROL1_I_KP_SHIFT 6 638 639 /* DDR34_F0_PHY_CONTROL_REGS :: PLL_CONTROL1 :: I_KI [05:03] */ 640 #define DDR34_F0_PHY_CONTROL_REGS_PLL_CONTROL1_I_KI_MASK 0x00000038 641 #define DDR34_F0_PHY_CONTROL_REGS_PLL_CONTROL1_I_KI_ALIGN 0 642 #define DDR34_F0_PHY_CONTROL_REGS_PLL_CONTROL1_I_KI_BITS 3 643 #define DDR34_F0_PHY_CONTROL_REGS_PLL_CONTROL1_I_KI_SHIFT 3 644 645 /* DDR34_F0_PHY_CONTROL_REGS :: PLL_CONTROL1 :: I_KA [02:00] */ 646 #define DDR34_F0_PHY_CONTROL_REGS_PLL_CONTROL1_I_KA_MASK 0x00000007 647 #define DDR34_F0_PHY_CONTROL_REGS_PLL_CONTROL1_I_KA_ALIGN 0 648 #define DDR34_F0_PHY_CONTROL_REGS_PLL_CONTROL1_I_KA_BITS 3 649 #define DDR34_F0_PHY_CONTROL_REGS_PLL_CONTROL1_I_KA_SHIFT 0 650 651 652 /**************************************************************************** 653 * DDR34_F0_PHY_CONTROL_REGS :: PLL_CONTROL2 654 */ 655 /* DDR34_F0_PHY_CONTROL_REGS :: PLL_CONTROL2 :: VCO_RANGE [31:30] */ 656 #define DDR34_F0_PHY_CONTROL_REGS_PLL_CONTROL2_VCO_RANGE_MASK 0xc0000000 657 #define DDR34_F0_PHY_CONTROL_REGS_PLL_CONTROL2_VCO_RANGE_ALIGN 0 658 #define DDR34_F0_PHY_CONTROL_REGS_PLL_CONTROL2_VCO_RANGE_BITS 2 659 #define DDR34_F0_PHY_CONTROL_REGS_PLL_CONTROL2_VCO_RANGE_SHIFT 30 660 661 /* DDR34_F0_PHY_CONTROL_REGS :: PLL_CONTROL2 :: UNUSED2 [29:29] */ 662 #define DDR34_F0_PHY_CONTROL_REGS_PLL_CONTROL2_UNUSED2_MASK 0x20000000 663 #define DDR34_F0_PHY_CONTROL_REGS_PLL_CONTROL2_UNUSED2_ALIGN 0 664 #define DDR34_F0_PHY_CONTROL_REGS_PLL_CONTROL2_UNUSED2_BITS 1 665 #define DDR34_F0_PHY_CONTROL_REGS_PLL_CONTROL2_UNUSED2_SHIFT 29 666 667 /* DDR34_F0_PHY_CONTROL_REGS :: PLL_CONTROL2 :: NDIV_RELOCK [28:28] */ 668 #define DDR34_F0_PHY_CONTROL_REGS_PLL_CONTROL2_NDIV_RELOCK_MASK 0x10000000 669 #define DDR34_F0_PHY_CONTROL_REGS_PLL_CONTROL2_NDIV_RELOCK_ALIGN 0 670 #define DDR34_F0_PHY_CONTROL_REGS_PLL_CONTROL2_NDIV_RELOCK_BITS 1 671 #define DDR34_F0_PHY_CONTROL_REGS_PLL_CONTROL2_NDIV_RELOCK_SHIFT 28 672 673 /* DDR34_F0_PHY_CONTROL_REGS :: PLL_CONTROL2 :: FAST_LOCK [27:27] */ 674 #define DDR34_F0_PHY_CONTROL_REGS_PLL_CONTROL2_FAST_LOCK_MASK 0x08000000 675 #define DDR34_F0_PHY_CONTROL_REGS_PLL_CONTROL2_FAST_LOCK_ALIGN 0 676 #define DDR34_F0_PHY_CONTROL_REGS_PLL_CONTROL2_FAST_LOCK_BITS 1 677 #define DDR34_F0_PHY_CONTROL_REGS_PLL_CONTROL2_FAST_LOCK_SHIFT 27 678 679 /* DDR34_F0_PHY_CONTROL_REGS :: PLL_CONTROL2 :: VCO_FB_DIV2 [26:26] */ 680 #define DDR34_F0_PHY_CONTROL_REGS_PLL_CONTROL2_VCO_FB_DIV2_MASK 0x04000000 681 #define DDR34_F0_PHY_CONTROL_REGS_PLL_CONTROL2_VCO_FB_DIV2_ALIGN 0 682 #define DDR34_F0_PHY_CONTROL_REGS_PLL_CONTROL2_VCO_FB_DIV2_BITS 1 683 #define DDR34_F0_PHY_CONTROL_REGS_PLL_CONTROL2_VCO_FB_DIV2_SHIFT 26 684 685 /* DDR34_F0_PHY_CONTROL_REGS :: PLL_CONTROL2 :: POST_CTRL_RESETB [25:24] */ 686 #define DDR34_F0_PHY_CONTROL_REGS_PLL_CONTROL2_POST_CTRL_RESETB_MASK 0x03000000 687 #define DDR34_F0_PHY_CONTROL_REGS_PLL_CONTROL2_POST_CTRL_RESETB_ALIGN 0 688 #define DDR34_F0_PHY_CONTROL_REGS_PLL_CONTROL2_POST_CTRL_RESETB_BITS 2 689 #define DDR34_F0_PHY_CONTROL_REGS_PLL_CONTROL2_POST_CTRL_RESETB_SHIFT 24 690 691 /* DDR34_F0_PHY_CONTROL_REGS :: PLL_CONTROL2 :: PWM_RATE [23:22] */ 692 #define DDR34_F0_PHY_CONTROL_REGS_PLL_CONTROL2_PWM_RATE_MASK 0x00c00000 693 #define DDR34_F0_PHY_CONTROL_REGS_PLL_CONTROL2_PWM_RATE_ALIGN 0 694 #define DDR34_F0_PHY_CONTROL_REGS_PLL_CONTROL2_PWM_RATE_BITS 2 695 #define DDR34_F0_PHY_CONTROL_REGS_PLL_CONTROL2_PWM_RATE_SHIFT 22 696 697 /* DDR34_F0_PHY_CONTROL_REGS :: PLL_CONTROL2 :: STAT_MODE [21:20] */ 698 #define DDR34_F0_PHY_CONTROL_REGS_PLL_CONTROL2_STAT_MODE_MASK 0x00300000 699 #define DDR34_F0_PHY_CONTROL_REGS_PLL_CONTROL2_STAT_MODE_ALIGN 0 700 #define DDR34_F0_PHY_CONTROL_REGS_PLL_CONTROL2_STAT_MODE_BITS 2 701 #define DDR34_F0_PHY_CONTROL_REGS_PLL_CONTROL2_STAT_MODE_SHIFT 20 702 703 /* DDR34_F0_PHY_CONTROL_REGS :: PLL_CONTROL2 :: UNUSED1 [19:18] */ 704 #define DDR34_F0_PHY_CONTROL_REGS_PLL_CONTROL2_UNUSED1_MASK 0x000c0000 705 #define DDR34_F0_PHY_CONTROL_REGS_PLL_CONTROL2_UNUSED1_ALIGN 0 706 #define DDR34_F0_PHY_CONTROL_REGS_PLL_CONTROL2_UNUSED1_BITS 2 707 #define DDR34_F0_PHY_CONTROL_REGS_PLL_CONTROL2_UNUSED1_SHIFT 18 708 709 /* DDR34_F0_PHY_CONTROL_REGS :: PLL_CONTROL2 :: STAT_UPDATE [17:17] */ 710 #define DDR34_F0_PHY_CONTROL_REGS_PLL_CONTROL2_STAT_UPDATE_MASK 0x00020000 711 #define DDR34_F0_PHY_CONTROL_REGS_PLL_CONTROL2_STAT_UPDATE_ALIGN 0 712 #define DDR34_F0_PHY_CONTROL_REGS_PLL_CONTROL2_STAT_UPDATE_BITS 1 713 #define DDR34_F0_PHY_CONTROL_REGS_PLL_CONTROL2_STAT_UPDATE_SHIFT 17 714 715 /* DDR34_F0_PHY_CONTROL_REGS :: PLL_CONTROL2 :: STAT_SELECT [16:14] */ 716 #define DDR34_F0_PHY_CONTROL_REGS_PLL_CONTROL2_STAT_SELECT_MASK 0x0001c000 717 #define DDR34_F0_PHY_CONTROL_REGS_PLL_CONTROL2_STAT_SELECT_ALIGN 0 718 #define DDR34_F0_PHY_CONTROL_REGS_PLL_CONTROL2_STAT_SELECT_BITS 3 719 #define DDR34_F0_PHY_CONTROL_REGS_PLL_CONTROL2_STAT_SELECT_SHIFT 14 720 721 /* DDR34_F0_PHY_CONTROL_REGS :: PLL_CONTROL2 :: STAT_RESET [13:13] */ 722 #define DDR34_F0_PHY_CONTROL_REGS_PLL_CONTROL2_STAT_RESET_MASK 0x00002000 723 #define DDR34_F0_PHY_CONTROL_REGS_PLL_CONTROL2_STAT_RESET_ALIGN 0 724 #define DDR34_F0_PHY_CONTROL_REGS_PLL_CONTROL2_STAT_RESET_BITS 1 725 #define DDR34_F0_PHY_CONTROL_REGS_PLL_CONTROL2_STAT_RESET_SHIFT 13 726 727 /* DDR34_F0_PHY_CONTROL_REGS :: PLL_CONTROL2 :: DCO_CTRL_BYPASS_ENABLE [12:12] */ 728 #define DDR34_F0_PHY_CONTROL_REGS_PLL_CONTROL2_DCO_CTRL_BYPASS_ENABLE_MASK 0x00001000 729 #define DDR34_F0_PHY_CONTROL_REGS_PLL_CONTROL2_DCO_CTRL_BYPASS_ENABLE_ALIGN 0 730 #define DDR34_F0_PHY_CONTROL_REGS_PLL_CONTROL2_DCO_CTRL_BYPASS_ENABLE_BITS 1 731 #define DDR34_F0_PHY_CONTROL_REGS_PLL_CONTROL2_DCO_CTRL_BYPASS_ENABLE_SHIFT 12 732 733 /* DDR34_F0_PHY_CONTROL_REGS :: PLL_CONTROL2 :: DCO_CTRL_BYPASS [11:00] */ 734 #define DDR34_F0_PHY_CONTROL_REGS_PLL_CONTROL2_DCO_CTRL_BYPASS_MASK 0x00000fff 735 #define DDR34_F0_PHY_CONTROL_REGS_PLL_CONTROL2_DCO_CTRL_BYPASS_ALIGN 0 736 #define DDR34_F0_PHY_CONTROL_REGS_PLL_CONTROL2_DCO_CTRL_BYPASS_BITS 12 737 #define DDR34_F0_PHY_CONTROL_REGS_PLL_CONTROL2_DCO_CTRL_BYPASS_SHIFT 0 738 739 740 /**************************************************************************** 741 * DDR34_F0_PHY_CONTROL_REGS :: PLL_CONTROL3 742 */ 743 /* DDR34_F0_PHY_CONTROL_REGS :: PLL_CONTROL3 :: PLL_CONTROL [31:00] */ 744 #define DDR34_F0_PHY_CONTROL_REGS_PLL_CONTROL3_PLL_CONTROL_MASK 0xffffffff 745 #define DDR34_F0_PHY_CONTROL_REGS_PLL_CONTROL3_PLL_CONTROL_ALIGN 0 746 #define DDR34_F0_PHY_CONTROL_REGS_PLL_CONTROL3_PLL_CONTROL_BITS 32 747 #define DDR34_F0_PHY_CONTROL_REGS_PLL_CONTROL3_PLL_CONTROL_SHIFT 0 748 749 750 /**************************************************************************** 751 * DDR34_F0_PHY_CONTROL_REGS :: PLL_DIVIDERS 752 */ 753 /* DDR34_F0_PHY_CONTROL_REGS :: PLL_DIVIDERS :: reserved0 [31:28] */ 754 #define DDR34_F0_PHY_CONTROL_REGS_PLL_DIVIDERS_RESERVED0_MASK 0xf0000000 755 #define DDR34_F0_PHY_CONTROL_REGS_PLL_DIVIDERS_RESERVED0_ALIGN 0 756 #define DDR34_F0_PHY_CONTROL_REGS_PLL_DIVIDERS_RESERVED0_BITS 4 757 #define DDR34_F0_PHY_CONTROL_REGS_PLL_DIVIDERS_RESERVED0_SHIFT 28 758 759 /* DDR34_F0_PHY_CONTROL_REGS :: PLL_DIVIDERS :: MDIV [27:20] */ 760 #define DDR34_F0_PHY_CONTROL_REGS_PLL_DIVIDERS_MDIV_MASK 0x0ff00000 761 #define DDR34_F0_PHY_CONTROL_REGS_PLL_DIVIDERS_MDIV_ALIGN 0 762 #define DDR34_F0_PHY_CONTROL_REGS_PLL_DIVIDERS_MDIV_BITS 8 763 #define DDR34_F0_PHY_CONTROL_REGS_PLL_DIVIDERS_MDIV_SHIFT 20 764 765 /* DDR34_F0_PHY_CONTROL_REGS :: PLL_DIVIDERS :: reserved1 [19:16] */ 766 #define DDR34_F0_PHY_CONTROL_REGS_PLL_DIVIDERS_RESERVED1_MASK 0x000f0000 767 #define DDR34_F0_PHY_CONTROL_REGS_PLL_DIVIDERS_RESERVED1_ALIGN 0 768 #define DDR34_F0_PHY_CONTROL_REGS_PLL_DIVIDERS_RESERVED1_BITS 4 769 #define DDR34_F0_PHY_CONTROL_REGS_PLL_DIVIDERS_RESERVED1_SHIFT 16 770 771 /* DDR34_F0_PHY_CONTROL_REGS :: PLL_DIVIDERS :: PDIV [15:12] */ 772 #define DDR34_F0_PHY_CONTROL_REGS_PLL_DIVIDERS_PDIV_MASK 0x0000f000 773 #define DDR34_F0_PHY_CONTROL_REGS_PLL_DIVIDERS_PDIV_ALIGN 0 774 #define DDR34_F0_PHY_CONTROL_REGS_PLL_DIVIDERS_PDIV_BITS 4 775 #define DDR34_F0_PHY_CONTROL_REGS_PLL_DIVIDERS_PDIV_SHIFT 12 776 777 /* DDR34_F0_PHY_CONTROL_REGS :: PLL_DIVIDERS :: reserved2 [11:10] */ 778 #define DDR34_F0_PHY_CONTROL_REGS_PLL_DIVIDERS_RESERVED2_MASK 0x00000c00 779 #define DDR34_F0_PHY_CONTROL_REGS_PLL_DIVIDERS_RESERVED2_ALIGN 0 780 #define DDR34_F0_PHY_CONTROL_REGS_PLL_DIVIDERS_RESERVED2_BITS 2 781 #define DDR34_F0_PHY_CONTROL_REGS_PLL_DIVIDERS_RESERVED2_SHIFT 10 782 783 /* DDR34_F0_PHY_CONTROL_REGS :: PLL_DIVIDERS :: NDIV_INT [09:00] */ 784 #define DDR34_F0_PHY_CONTROL_REGS_PLL_DIVIDERS_NDIV_INT_MASK 0x000003ff 785 #define DDR34_F0_PHY_CONTROL_REGS_PLL_DIVIDERS_NDIV_INT_ALIGN 0 786 #define DDR34_F0_PHY_CONTROL_REGS_PLL_DIVIDERS_NDIV_INT_BITS 10 787 #define DDR34_F0_PHY_CONTROL_REGS_PLL_DIVIDERS_NDIV_INT_SHIFT 0 788 789 790 /**************************************************************************** 791 * DDR34_F0_PHY_CONTROL_REGS :: PLL_FRAC_DIVIDER 792 */ 793 /* DDR34_F0_PHY_CONTROL_REGS :: PLL_FRAC_DIVIDER :: reserved0 [31:20] */ 794 #define DDR34_F0_PHY_CONTROL_REGS_PLL_FRAC_DIVIDER_RESERVED0_MASK 0xfff00000 795 #define DDR34_F0_PHY_CONTROL_REGS_PLL_FRAC_DIVIDER_RESERVED0_ALIGN 0 796 #define DDR34_F0_PHY_CONTROL_REGS_PLL_FRAC_DIVIDER_RESERVED0_BITS 12 797 #define DDR34_F0_PHY_CONTROL_REGS_PLL_FRAC_DIVIDER_RESERVED0_SHIFT 20 798 799 /* DDR34_F0_PHY_CONTROL_REGS :: PLL_FRAC_DIVIDER :: NDIV_FRAC [19:00] */ 800 #define DDR34_F0_PHY_CONTROL_REGS_PLL_FRAC_DIVIDER_NDIV_FRAC_MASK 0x000fffff 801 #define DDR34_F0_PHY_CONTROL_REGS_PLL_FRAC_DIVIDER_NDIV_FRAC_ALIGN 0 802 #define DDR34_F0_PHY_CONTROL_REGS_PLL_FRAC_DIVIDER_NDIV_FRAC_BITS 20 803 #define DDR34_F0_PHY_CONTROL_REGS_PLL_FRAC_DIVIDER_NDIV_FRAC_SHIFT 0 804 805 806 /**************************************************************************** 807 * DDR34_F0_PHY_CONTROL_REGS :: PLL_SS_CONTROL 808 */ 809 /* DDR34_F0_PHY_CONTROL_REGS :: PLL_SS_CONTROL :: reserved0 [31:20] */ 810 #define DDR34_F0_PHY_CONTROL_REGS_PLL_SS_CONTROL_RESERVED0_MASK 0xfff00000 811 #define DDR34_F0_PHY_CONTROL_REGS_PLL_SS_CONTROL_RESERVED0_ALIGN 0 812 #define DDR34_F0_PHY_CONTROL_REGS_PLL_SS_CONTROL_RESERVED0_BITS 12 813 #define DDR34_F0_PHY_CONTROL_REGS_PLL_SS_CONTROL_RESERVED0_SHIFT 20 814 815 /* DDR34_F0_PHY_CONTROL_REGS :: PLL_SS_CONTROL :: SSC_STEP [19:04] */ 816 #define DDR34_F0_PHY_CONTROL_REGS_PLL_SS_CONTROL_SSC_STEP_MASK 0x000ffff0 817 #define DDR34_F0_PHY_CONTROL_REGS_PLL_SS_CONTROL_SSC_STEP_ALIGN 0 818 #define DDR34_F0_PHY_CONTROL_REGS_PLL_SS_CONTROL_SSC_STEP_BITS 16 819 #define DDR34_F0_PHY_CONTROL_REGS_PLL_SS_CONTROL_SSC_STEP_SHIFT 4 820 821 /* DDR34_F0_PHY_CONTROL_REGS :: PLL_SS_CONTROL :: reserved1 [03:01] */ 822 #define DDR34_F0_PHY_CONTROL_REGS_PLL_SS_CONTROL_RESERVED1_MASK 0x0000000e 823 #define DDR34_F0_PHY_CONTROL_REGS_PLL_SS_CONTROL_RESERVED1_ALIGN 0 824 #define DDR34_F0_PHY_CONTROL_REGS_PLL_SS_CONTROL_RESERVED1_BITS 3 825 #define DDR34_F0_PHY_CONTROL_REGS_PLL_SS_CONTROL_RESERVED1_SHIFT 1 826 827 /* DDR34_F0_PHY_CONTROL_REGS :: PLL_SS_CONTROL :: SSC_MODE [00:00] */ 828 #define DDR34_F0_PHY_CONTROL_REGS_PLL_SS_CONTROL_SSC_MODE_MASK 0x00000001 829 #define DDR34_F0_PHY_CONTROL_REGS_PLL_SS_CONTROL_SSC_MODE_ALIGN 0 830 #define DDR34_F0_PHY_CONTROL_REGS_PLL_SS_CONTROL_SSC_MODE_BITS 1 831 #define DDR34_F0_PHY_CONTROL_REGS_PLL_SS_CONTROL_SSC_MODE_SHIFT 0 832 833 834 /**************************************************************************** 835 * DDR34_F0_PHY_CONTROL_REGS :: PLL_SS_LIMIT 836 */ 837 /* DDR34_F0_PHY_CONTROL_REGS :: PLL_SS_LIMIT :: reserved0 [31:26] */ 838 #define DDR34_F0_PHY_CONTROL_REGS_PLL_SS_LIMIT_RESERVED0_MASK 0xfc000000 839 #define DDR34_F0_PHY_CONTROL_REGS_PLL_SS_LIMIT_RESERVED0_ALIGN 0 840 #define DDR34_F0_PHY_CONTROL_REGS_PLL_SS_LIMIT_RESERVED0_BITS 6 841 #define DDR34_F0_PHY_CONTROL_REGS_PLL_SS_LIMIT_RESERVED0_SHIFT 26 842 843 /* DDR34_F0_PHY_CONTROL_REGS :: PLL_SS_LIMIT :: SSC_LIMIT [25:04] */ 844 #define DDR34_F0_PHY_CONTROL_REGS_PLL_SS_LIMIT_SSC_LIMIT_MASK 0x03fffff0 845 #define DDR34_F0_PHY_CONTROL_REGS_PLL_SS_LIMIT_SSC_LIMIT_ALIGN 0 846 #define DDR34_F0_PHY_CONTROL_REGS_PLL_SS_LIMIT_SSC_LIMIT_BITS 22 847 #define DDR34_F0_PHY_CONTROL_REGS_PLL_SS_LIMIT_SSC_LIMIT_SHIFT 4 848 849 /* DDR34_F0_PHY_CONTROL_REGS :: PLL_SS_LIMIT :: reserved1 [03:00] */ 850 #define DDR34_F0_PHY_CONTROL_REGS_PLL_SS_LIMIT_RESERVED1_MASK 0x0000000f 851 #define DDR34_F0_PHY_CONTROL_REGS_PLL_SS_LIMIT_RESERVED1_ALIGN 0 852 #define DDR34_F0_PHY_CONTROL_REGS_PLL_SS_LIMIT_RESERVED1_BITS 4 853 #define DDR34_F0_PHY_CONTROL_REGS_PLL_SS_LIMIT_RESERVED1_SHIFT 0 854 855 856 /**************************************************************************** 857 * DDR34_F0_PHY_CONTROL_REGS :: AUX_CONTROL 858 */ 859 /* DDR34_F0_PHY_CONTROL_REGS :: AUX_CONTROL :: reserved0 [31:05] */ 860 #define DDR34_F0_PHY_CONTROL_REGS_AUX_CONTROL_RESERVED0_MASK 0xffffffe0 861 #define DDR34_F0_PHY_CONTROL_REGS_AUX_CONTROL_RESERVED0_ALIGN 0 862 #define DDR34_F0_PHY_CONTROL_REGS_AUX_CONTROL_RESERVED0_BITS 27 863 #define DDR34_F0_PHY_CONTROL_REGS_AUX_CONTROL_RESERVED0_SHIFT 5 864 865 /* DDR34_F0_PHY_CONTROL_REGS :: AUX_CONTROL :: AUX0_IS_ODT [04:04] */ 866 #define DDR34_F0_PHY_CONTROL_REGS_AUX_CONTROL_AUX0_IS_ODT_MASK 0x00000010 867 #define DDR34_F0_PHY_CONTROL_REGS_AUX_CONTROL_AUX0_IS_ODT_ALIGN 0 868 #define DDR34_F0_PHY_CONTROL_REGS_AUX_CONTROL_AUX0_IS_ODT_BITS 1 869 #define DDR34_F0_PHY_CONTROL_REGS_AUX_CONTROL_AUX0_IS_ODT_SHIFT 4 870 871 /* DDR34_F0_PHY_CONTROL_REGS :: AUX_CONTROL :: PAR_IS_ODT [03:03] */ 872 #define DDR34_F0_PHY_CONTROL_REGS_AUX_CONTROL_PAR_IS_ODT_MASK 0x00000008 873 #define DDR34_F0_PHY_CONTROL_REGS_AUX_CONTROL_PAR_IS_ODT_ALIGN 0 874 #define DDR34_F0_PHY_CONTROL_REGS_AUX_CONTROL_PAR_IS_ODT_BITS 1 875 #define DDR34_F0_PHY_CONTROL_REGS_AUX_CONTROL_PAR_IS_ODT_SHIFT 3 876 877 /* DDR34_F0_PHY_CONTROL_REGS :: AUX_CONTROL :: reserved1 [02:00] */ 878 #define DDR34_F0_PHY_CONTROL_REGS_AUX_CONTROL_RESERVED1_MASK 0x00000007 879 #define DDR34_F0_PHY_CONTROL_REGS_AUX_CONTROL_RESERVED1_ALIGN 0 880 #define DDR34_F0_PHY_CONTROL_REGS_AUX_CONTROL_RESERVED1_BITS 3 881 #define DDR34_F0_PHY_CONTROL_REGS_AUX_CONTROL_RESERVED1_SHIFT 0 882 883 884 /**************************************************************************** 885 * DDR34_F0_PHY_CONTROL_REGS :: IDLE_PAD_CONTROL 886 */ 887 /* DDR34_F0_PHY_CONTROL_REGS :: IDLE_PAD_CONTROL :: IDLE [31:31] */ 888 #define DDR34_F0_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_IDLE_MASK 0x80000000 889 #define DDR34_F0_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_IDLE_ALIGN 0 890 #define DDR34_F0_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_IDLE_BITS 1 891 #define DDR34_F0_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_IDLE_SHIFT 31 892 893 /* DDR34_F0_PHY_CONTROL_REGS :: IDLE_PAD_CONTROL :: DIB_MODE [30:30] */ 894 #define DDR34_F0_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_DIB_MODE_MASK 0x40000000 895 #define DDR34_F0_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_DIB_MODE_ALIGN 0 896 #define DDR34_F0_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_DIB_MODE_BITS 1 897 #define DDR34_F0_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_DIB_MODE_SHIFT 30 898 899 /* DDR34_F0_PHY_CONTROL_REGS :: IDLE_PAD_CONTROL :: reserved0 [29:04] */ 900 #define DDR34_F0_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_RESERVED0_MASK 0x3ffffff0 901 #define DDR34_F0_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_RESERVED0_ALIGN 0 902 #define DDR34_F0_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_RESERVED0_BITS 26 903 #define DDR34_F0_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_RESERVED0_SHIFT 4 904 905 /* DDR34_F0_PHY_CONTROL_REGS :: IDLE_PAD_CONTROL :: RXENB [03:03] */ 906 #define DDR34_F0_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_RXENB_MASK 0x00000008 907 #define DDR34_F0_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_RXENB_ALIGN 0 908 #define DDR34_F0_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_RXENB_BITS 1 909 #define DDR34_F0_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_RXENB_SHIFT 3 910 911 /* DDR34_F0_PHY_CONTROL_REGS :: IDLE_PAD_CONTROL :: IDDQ [02:02] */ 912 #define DDR34_F0_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_IDDQ_MASK 0x00000004 913 #define DDR34_F0_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_IDDQ_ALIGN 0 914 #define DDR34_F0_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_IDDQ_BITS 1 915 #define DDR34_F0_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_IDDQ_SHIFT 2 916 917 /* DDR34_F0_PHY_CONTROL_REGS :: IDLE_PAD_CONTROL :: DOUT_N [01:01] */ 918 #define DDR34_F0_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_DOUT_N_MASK 0x00000002 919 #define DDR34_F0_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_DOUT_N_ALIGN 0 920 #define DDR34_F0_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_DOUT_N_BITS 1 921 #define DDR34_F0_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_DOUT_N_SHIFT 1 922 923 /* DDR34_F0_PHY_CONTROL_REGS :: IDLE_PAD_CONTROL :: DOUT_P [00:00] */ 924 #define DDR34_F0_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_DOUT_P_MASK 0x00000001 925 #define DDR34_F0_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_DOUT_P_ALIGN 0 926 #define DDR34_F0_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_DOUT_P_BITS 1 927 #define DDR34_F0_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_DOUT_P_SHIFT 0 928 929 930 /**************************************************************************** 931 * DDR34_F0_PHY_CONTROL_REGS :: IDLE_PAD_ENABLE0 932 */ 933 /* DDR34_F0_PHY_CONTROL_REGS :: IDLE_PAD_ENABLE0 :: reserved0 [31:11] */ 934 #define DDR34_F0_PHY_CONTROL_REGS_IDLE_PAD_ENABLE0_RESERVED0_MASK 0xfffff800 935 #define DDR34_F0_PHY_CONTROL_REGS_IDLE_PAD_ENABLE0_RESERVED0_ALIGN 0 936 #define DDR34_F0_PHY_CONTROL_REGS_IDLE_PAD_ENABLE0_RESERVED0_BITS 21 937 #define DDR34_F0_PHY_CONTROL_REGS_IDLE_PAD_ENABLE0_RESERVED0_SHIFT 11 938 939 /* DDR34_F0_PHY_CONTROL_REGS :: IDLE_PAD_ENABLE0 :: IO_IDLE_ENABLE [10:00] */ 940 #define DDR34_F0_PHY_CONTROL_REGS_IDLE_PAD_ENABLE0_IO_IDLE_ENABLE_MASK 0x000007ff 941 #define DDR34_F0_PHY_CONTROL_REGS_IDLE_PAD_ENABLE0_IO_IDLE_ENABLE_ALIGN 0 942 #define DDR34_F0_PHY_CONTROL_REGS_IDLE_PAD_ENABLE0_IO_IDLE_ENABLE_BITS 11 943 #define DDR34_F0_PHY_CONTROL_REGS_IDLE_PAD_ENABLE0_IO_IDLE_ENABLE_SHIFT 0 944 945 946 /**************************************************************************** 947 * DDR34_F0_PHY_CONTROL_REGS :: IDLE_PAD_ENABLE1 948 */ 949 /* DDR34_F0_PHY_CONTROL_REGS :: IDLE_PAD_ENABLE1 :: reserved0 [31:22] */ 950 #define DDR34_F0_PHY_CONTROL_REGS_IDLE_PAD_ENABLE1_RESERVED0_MASK 0xffc00000 951 #define DDR34_F0_PHY_CONTROL_REGS_IDLE_PAD_ENABLE1_RESERVED0_ALIGN 0 952 #define DDR34_F0_PHY_CONTROL_REGS_IDLE_PAD_ENABLE1_RESERVED0_BITS 10 953 #define DDR34_F0_PHY_CONTROL_REGS_IDLE_PAD_ENABLE1_RESERVED0_SHIFT 22 954 955 /* DDR34_F0_PHY_CONTROL_REGS :: IDLE_PAD_ENABLE1 :: IO_IDLE_ENABLE [21:00] */ 956 #define DDR34_F0_PHY_CONTROL_REGS_IDLE_PAD_ENABLE1_IO_IDLE_ENABLE_MASK 0x003fffff 957 #define DDR34_F0_PHY_CONTROL_REGS_IDLE_PAD_ENABLE1_IO_IDLE_ENABLE_ALIGN 0 958 #define DDR34_F0_PHY_CONTROL_REGS_IDLE_PAD_ENABLE1_IO_IDLE_ENABLE_BITS 22 959 #define DDR34_F0_PHY_CONTROL_REGS_IDLE_PAD_ENABLE1_IO_IDLE_ENABLE_SHIFT 0 960 961 962 /**************************************************************************** 963 * DDR34_F0_PHY_CONTROL_REGS :: DRIVE_PAD_CTL 964 */ 965 /* DDR34_F0_PHY_CONTROL_REGS :: DRIVE_PAD_CTL :: reserved0 [31:30] */ 966 #define DDR34_F0_PHY_CONTROL_REGS_DRIVE_PAD_CTL_RESERVED0_MASK 0xc0000000 967 #define DDR34_F0_PHY_CONTROL_REGS_DRIVE_PAD_CTL_RESERVED0_ALIGN 0 968 #define DDR34_F0_PHY_CONTROL_REGS_DRIVE_PAD_CTL_RESERVED0_BITS 2 969 #define DDR34_F0_PHY_CONTROL_REGS_DRIVE_PAD_CTL_RESERVED0_SHIFT 30 970 971 /* DDR34_F0_PHY_CONTROL_REGS :: DRIVE_PAD_CTL :: ADDR_CTL_PD_IDLE_STRENGTH [29:25] */ 972 #define DDR34_F0_PHY_CONTROL_REGS_DRIVE_PAD_CTL_ADDR_CTL_PD_IDLE_STRENGTH_MASK 0x3e000000 973 #define DDR34_F0_PHY_CONTROL_REGS_DRIVE_PAD_CTL_ADDR_CTL_PD_IDLE_STRENGTH_ALIGN 0 974 #define DDR34_F0_PHY_CONTROL_REGS_DRIVE_PAD_CTL_ADDR_CTL_PD_IDLE_STRENGTH_BITS 5 975 #define DDR34_F0_PHY_CONTROL_REGS_DRIVE_PAD_CTL_ADDR_CTL_PD_IDLE_STRENGTH_SHIFT 25 976 977 /* DDR34_F0_PHY_CONTROL_REGS :: DRIVE_PAD_CTL :: ADDR_CTL_ND_IDLE_STRENGTH [24:20] */ 978 #define DDR34_F0_PHY_CONTROL_REGS_DRIVE_PAD_CTL_ADDR_CTL_ND_IDLE_STRENGTH_MASK 0x01f00000 979 #define DDR34_F0_PHY_CONTROL_REGS_DRIVE_PAD_CTL_ADDR_CTL_ND_IDLE_STRENGTH_ALIGN 0 980 #define DDR34_F0_PHY_CONTROL_REGS_DRIVE_PAD_CTL_ADDR_CTL_ND_IDLE_STRENGTH_BITS 5 981 #define DDR34_F0_PHY_CONTROL_REGS_DRIVE_PAD_CTL_ADDR_CTL_ND_IDLE_STRENGTH_SHIFT 20 982 983 /* DDR34_F0_PHY_CONTROL_REGS :: DRIVE_PAD_CTL :: ADDR_CTL_PD_TERM_STRENGTH [19:15] */ 984 #define DDR34_F0_PHY_CONTROL_REGS_DRIVE_PAD_CTL_ADDR_CTL_PD_TERM_STRENGTH_MASK 0x000f8000 985 #define DDR34_F0_PHY_CONTROL_REGS_DRIVE_PAD_CTL_ADDR_CTL_PD_TERM_STRENGTH_ALIGN 0 986 #define DDR34_F0_PHY_CONTROL_REGS_DRIVE_PAD_CTL_ADDR_CTL_PD_TERM_STRENGTH_BITS 5 987 #define DDR34_F0_PHY_CONTROL_REGS_DRIVE_PAD_CTL_ADDR_CTL_PD_TERM_STRENGTH_SHIFT 15 988 989 /* DDR34_F0_PHY_CONTROL_REGS :: DRIVE_PAD_CTL :: ADDR_CTL_ND_TERM_STRENGTH [14:10] */ 990 #define DDR34_F0_PHY_CONTROL_REGS_DRIVE_PAD_CTL_ADDR_CTL_ND_TERM_STRENGTH_MASK 0x00007c00 991 #define DDR34_F0_PHY_CONTROL_REGS_DRIVE_PAD_CTL_ADDR_CTL_ND_TERM_STRENGTH_ALIGN 0 992 #define DDR34_F0_PHY_CONTROL_REGS_DRIVE_PAD_CTL_ADDR_CTL_ND_TERM_STRENGTH_BITS 5 993 #define DDR34_F0_PHY_CONTROL_REGS_DRIVE_PAD_CTL_ADDR_CTL_ND_TERM_STRENGTH_SHIFT 10 994 995 /* DDR34_F0_PHY_CONTROL_REGS :: DRIVE_PAD_CTL :: ADDR_CTL_PD_STRENGTH [09:05] */ 996 #define DDR34_F0_PHY_CONTROL_REGS_DRIVE_PAD_CTL_ADDR_CTL_PD_STRENGTH_MASK 0x000003e0 997 #define DDR34_F0_PHY_CONTROL_REGS_DRIVE_PAD_CTL_ADDR_CTL_PD_STRENGTH_ALIGN 0 998 #define DDR34_F0_PHY_CONTROL_REGS_DRIVE_PAD_CTL_ADDR_CTL_PD_STRENGTH_BITS 5 999 #define DDR34_F0_PHY_CONTROL_REGS_DRIVE_PAD_CTL_ADDR_CTL_PD_STRENGTH_SHIFT 5 1000 1001 /* DDR34_F0_PHY_CONTROL_REGS :: DRIVE_PAD_CTL :: ADDR_CTL_ND_STRENGTH [04:00] */ 1002 #define DDR34_F0_PHY_CONTROL_REGS_DRIVE_PAD_CTL_ADDR_CTL_ND_STRENGTH_MASK 0x0000001f 1003 #define DDR34_F0_PHY_CONTROL_REGS_DRIVE_PAD_CTL_ADDR_CTL_ND_STRENGTH_ALIGN 0 1004 #define DDR34_F0_PHY_CONTROL_REGS_DRIVE_PAD_CTL_ADDR_CTL_ND_STRENGTH_BITS 5 1005 #define DDR34_F0_PHY_CONTROL_REGS_DRIVE_PAD_CTL_ADDR_CTL_ND_STRENGTH_SHIFT 0 1006 1007 1008 /**************************************************************************** 1009 * DDR34_F0_PHY_CONTROL_REGS :: DRIVE_PAD_CTL_2T 1010 */ 1011 /* DDR34_F0_PHY_CONTROL_REGS :: DRIVE_PAD_CTL_2T :: reserved0 [31:30] */ 1012 #define DDR34_F0_PHY_CONTROL_REGS_DRIVE_PAD_CTL_2T_RESERVED0_MASK 0xc0000000 1013 #define DDR34_F0_PHY_CONTROL_REGS_DRIVE_PAD_CTL_2T_RESERVED0_ALIGN 0 1014 #define DDR34_F0_PHY_CONTROL_REGS_DRIVE_PAD_CTL_2T_RESERVED0_BITS 2 1015 #define DDR34_F0_PHY_CONTROL_REGS_DRIVE_PAD_CTL_2T_RESERVED0_SHIFT 30 1016 1017 /* DDR34_F0_PHY_CONTROL_REGS :: DRIVE_PAD_CTL_2T :: PD_IDLE_STRENGTH [29:25] */ 1018 #define DDR34_F0_PHY_CONTROL_REGS_DRIVE_PAD_CTL_2T_PD_IDLE_STRENGTH_MASK 0x3e000000 1019 #define DDR34_F0_PHY_CONTROL_REGS_DRIVE_PAD_CTL_2T_PD_IDLE_STRENGTH_ALIGN 0 1020 #define DDR34_F0_PHY_CONTROL_REGS_DRIVE_PAD_CTL_2T_PD_IDLE_STRENGTH_BITS 5 1021 #define DDR34_F0_PHY_CONTROL_REGS_DRIVE_PAD_CTL_2T_PD_IDLE_STRENGTH_SHIFT 25 1022 1023 /* DDR34_F0_PHY_CONTROL_REGS :: DRIVE_PAD_CTL_2T :: ND_IDLE_STRENGTH [24:20] */ 1024 #define DDR34_F0_PHY_CONTROL_REGS_DRIVE_PAD_CTL_2T_ND_IDLE_STRENGTH_MASK 0x01f00000 1025 #define DDR34_F0_PHY_CONTROL_REGS_DRIVE_PAD_CTL_2T_ND_IDLE_STRENGTH_ALIGN 0 1026 #define DDR34_F0_PHY_CONTROL_REGS_DRIVE_PAD_CTL_2T_ND_IDLE_STRENGTH_BITS 5 1027 #define DDR34_F0_PHY_CONTROL_REGS_DRIVE_PAD_CTL_2T_ND_IDLE_STRENGTH_SHIFT 20 1028 1029 /* DDR34_F0_PHY_CONTROL_REGS :: DRIVE_PAD_CTL_2T :: PD_TERM_STRENGTH [19:15] */ 1030 #define DDR34_F0_PHY_CONTROL_REGS_DRIVE_PAD_CTL_2T_PD_TERM_STRENGTH_MASK 0x000f8000 1031 #define DDR34_F0_PHY_CONTROL_REGS_DRIVE_PAD_CTL_2T_PD_TERM_STRENGTH_ALIGN 0 1032 #define DDR34_F0_PHY_CONTROL_REGS_DRIVE_PAD_CTL_2T_PD_TERM_STRENGTH_BITS 5 1033 #define DDR34_F0_PHY_CONTROL_REGS_DRIVE_PAD_CTL_2T_PD_TERM_STRENGTH_SHIFT 15 1034 1035 /* DDR34_F0_PHY_CONTROL_REGS :: DRIVE_PAD_CTL_2T :: ND_TERM_STRENGTH [14:10] */ 1036 #define DDR34_F0_PHY_CONTROL_REGS_DRIVE_PAD_CTL_2T_ND_TERM_STRENGTH_MASK 0x00007c00 1037 #define DDR34_F0_PHY_CONTROL_REGS_DRIVE_PAD_CTL_2T_ND_TERM_STRENGTH_ALIGN 0 1038 #define DDR34_F0_PHY_CONTROL_REGS_DRIVE_PAD_CTL_2T_ND_TERM_STRENGTH_BITS 5 1039 #define DDR34_F0_PHY_CONTROL_REGS_DRIVE_PAD_CTL_2T_ND_TERM_STRENGTH_SHIFT 10 1040 1041 /* DDR34_F0_PHY_CONTROL_REGS :: DRIVE_PAD_CTL_2T :: PD_STRENGTH [09:05] */ 1042 #define DDR34_F0_PHY_CONTROL_REGS_DRIVE_PAD_CTL_2T_PD_STRENGTH_MASK 0x000003e0 1043 #define DDR34_F0_PHY_CONTROL_REGS_DRIVE_PAD_CTL_2T_PD_STRENGTH_ALIGN 0 1044 #define DDR34_F0_PHY_CONTROL_REGS_DRIVE_PAD_CTL_2T_PD_STRENGTH_BITS 5 1045 #define DDR34_F0_PHY_CONTROL_REGS_DRIVE_PAD_CTL_2T_PD_STRENGTH_SHIFT 5 1046 1047 /* DDR34_F0_PHY_CONTROL_REGS :: DRIVE_PAD_CTL_2T :: ND_STRENGTH [04:00] */ 1048 #define DDR34_F0_PHY_CONTROL_REGS_DRIVE_PAD_CTL_2T_ND_STRENGTH_MASK 0x0000001f 1049 #define DDR34_F0_PHY_CONTROL_REGS_DRIVE_PAD_CTL_2T_ND_STRENGTH_ALIGN 0 1050 #define DDR34_F0_PHY_CONTROL_REGS_DRIVE_PAD_CTL_2T_ND_STRENGTH_BITS 5 1051 #define DDR34_F0_PHY_CONTROL_REGS_DRIVE_PAD_CTL_2T_ND_STRENGTH_SHIFT 0 1052 1053 1054 /**************************************************************************** 1055 * DDR34_F0_PHY_CONTROL_REGS :: STATIC_PAD_CTL 1056 */ 1057 /* DDR34_F0_PHY_CONTROL_REGS :: STATIC_PAD_CTL :: reserved0 [31:28] */ 1058 #define DDR34_F0_PHY_CONTROL_REGS_STATIC_PAD_CTL_RESERVED0_MASK 0xf0000000 1059 #define DDR34_F0_PHY_CONTROL_REGS_STATIC_PAD_CTL_RESERVED0_ALIGN 0 1060 #define DDR34_F0_PHY_CONTROL_REGS_STATIC_PAD_CTL_RESERVED0_BITS 4 1061 #define DDR34_F0_PHY_CONTROL_REGS_STATIC_PAD_CTL_RESERVED0_SHIFT 28 1062 1063 /* DDR34_F0_PHY_CONTROL_REGS :: STATIC_PAD_CTL :: AUTO_OEB [27:27] */ 1064 #define DDR34_F0_PHY_CONTROL_REGS_STATIC_PAD_CTL_AUTO_OEB_MASK 0x08000000 1065 #define DDR34_F0_PHY_CONTROL_REGS_STATIC_PAD_CTL_AUTO_OEB_ALIGN 0 1066 #define DDR34_F0_PHY_CONTROL_REGS_STATIC_PAD_CTL_AUTO_OEB_BITS 1 1067 #define DDR34_F0_PHY_CONTROL_REGS_STATIC_PAD_CTL_AUTO_OEB_SHIFT 27 1068 1069 /* DDR34_F0_PHY_CONTROL_REGS :: STATIC_PAD_CTL :: IDDQ_LPDDR [26:26] */ 1070 #define DDR34_F0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_LPDDR_MASK 0x04000000 1071 #define DDR34_F0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_LPDDR_ALIGN 0 1072 #define DDR34_F0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_LPDDR_BITS 1 1073 #define DDR34_F0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_LPDDR_SHIFT 26 1074 1075 /* DDR34_F0_PHY_CONTROL_REGS :: STATIC_PAD_CTL :: IDDQ_CLK0 [25:25] */ 1076 #define DDR34_F0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_CLK0_MASK 0x02000000 1077 #define DDR34_F0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_CLK0_ALIGN 0 1078 #define DDR34_F0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_CLK0_BITS 1 1079 #define DDR34_F0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_CLK0_SHIFT 25 1080 1081 /* DDR34_F0_PHY_CONTROL_REGS :: STATIC_PAD_CTL :: IDDQ_ODT [24:24] */ 1082 #define DDR34_F0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_ODT_MASK 0x01000000 1083 #define DDR34_F0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_ODT_ALIGN 0 1084 #define DDR34_F0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_ODT_BITS 1 1085 #define DDR34_F0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_ODT_SHIFT 24 1086 1087 /* DDR34_F0_PHY_CONTROL_REGS :: STATIC_PAD_CTL :: IDDQ_PAR [23:23] */ 1088 #define DDR34_F0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_PAR_MASK 0x00800000 1089 #define DDR34_F0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_PAR_ALIGN 0 1090 #define DDR34_F0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_PAR_BITS 1 1091 #define DDR34_F0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_PAR_SHIFT 23 1092 1093 /* DDR34_F0_PHY_CONTROL_REGS :: STATIC_PAD_CTL :: IDDQ_BA [22:22] */ 1094 #define DDR34_F0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_BA_MASK 0x00400000 1095 #define DDR34_F0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_BA_ALIGN 0 1096 #define DDR34_F0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_BA_BITS 1 1097 #define DDR34_F0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_BA_SHIFT 22 1098 1099 /* DDR34_F0_PHY_CONTROL_REGS :: STATIC_PAD_CTL :: IDDQ_AUX2 [21:21] */ 1100 #define DDR34_F0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_AUX2_MASK 0x00200000 1101 #define DDR34_F0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_AUX2_ALIGN 0 1102 #define DDR34_F0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_AUX2_BITS 1 1103 #define DDR34_F0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_AUX2_SHIFT 21 1104 1105 /* DDR34_F0_PHY_CONTROL_REGS :: STATIC_PAD_CTL :: IDDQ_AUX1 [20:20] */ 1106 #define DDR34_F0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_AUX1_MASK 0x00100000 1107 #define DDR34_F0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_AUX1_ALIGN 0 1108 #define DDR34_F0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_AUX1_BITS 1 1109 #define DDR34_F0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_AUX1_SHIFT 20 1110 1111 /* DDR34_F0_PHY_CONTROL_REGS :: STATIC_PAD_CTL :: IDDQ_AUX0 [19:19] */ 1112 #define DDR34_F0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_AUX0_MASK 0x00080000 1113 #define DDR34_F0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_AUX0_ALIGN 0 1114 #define DDR34_F0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_AUX0_BITS 1 1115 #define DDR34_F0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_AUX0_SHIFT 19 1116 1117 /* DDR34_F0_PHY_CONTROL_REGS :: STATIC_PAD_CTL :: IDDQ_CS1 [18:18] */ 1118 #define DDR34_F0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_CS1_MASK 0x00040000 1119 #define DDR34_F0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_CS1_ALIGN 0 1120 #define DDR34_F0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_CS1_BITS 1 1121 #define DDR34_F0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_CS1_SHIFT 18 1122 1123 /* DDR34_F0_PHY_CONTROL_REGS :: STATIC_PAD_CTL :: IDDQ_A15 [17:17] */ 1124 #define DDR34_F0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_A15_MASK 0x00020000 1125 #define DDR34_F0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_A15_ALIGN 0 1126 #define DDR34_F0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_A15_BITS 1 1127 #define DDR34_F0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_A15_SHIFT 17 1128 1129 /* DDR34_F0_PHY_CONTROL_REGS :: STATIC_PAD_CTL :: IDDQ_A14 [16:16] */ 1130 #define DDR34_F0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_A14_MASK 0x00010000 1131 #define DDR34_F0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_A14_ALIGN 0 1132 #define DDR34_F0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_A14_BITS 1 1133 #define DDR34_F0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_A14_SHIFT 16 1134 1135 /* DDR34_F0_PHY_CONTROL_REGS :: STATIC_PAD_CTL :: IDDQ_A13 [15:15] */ 1136 #define DDR34_F0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_A13_MASK 0x00008000 1137 #define DDR34_F0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_A13_ALIGN 0 1138 #define DDR34_F0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_A13_BITS 1 1139 #define DDR34_F0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_A13_SHIFT 15 1140 1141 /* DDR34_F0_PHY_CONTROL_REGS :: STATIC_PAD_CTL :: IDDQ_A12 [14:14] */ 1142 #define DDR34_F0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_A12_MASK 0x00004000 1143 #define DDR34_F0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_A12_ALIGN 0 1144 #define DDR34_F0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_A12_BITS 1 1145 #define DDR34_F0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_A12_SHIFT 14 1146 1147 /* DDR34_F0_PHY_CONTROL_REGS :: STATIC_PAD_CTL :: IDDQ_A11 [13:13] */ 1148 #define DDR34_F0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_A11_MASK 0x00002000 1149 #define DDR34_F0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_A11_ALIGN 0 1150 #define DDR34_F0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_A11_BITS 1 1151 #define DDR34_F0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_A11_SHIFT 13 1152 1153 /* DDR34_F0_PHY_CONTROL_REGS :: STATIC_PAD_CTL :: IDDQ_A10 [12:12] */ 1154 #define DDR34_F0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_A10_MASK 0x00001000 1155 #define DDR34_F0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_A10_ALIGN 0 1156 #define DDR34_F0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_A10_BITS 1 1157 #define DDR34_F0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_A10_SHIFT 12 1158 1159 /* DDR34_F0_PHY_CONTROL_REGS :: STATIC_PAD_CTL :: IDDQ_A09 [11:11] */ 1160 #define DDR34_F0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_A09_MASK 0x00000800 1161 #define DDR34_F0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_A09_ALIGN 0 1162 #define DDR34_F0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_A09_BITS 1 1163 #define DDR34_F0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_A09_SHIFT 11 1164 1165 /* DDR34_F0_PHY_CONTROL_REGS :: STATIC_PAD_CTL :: reserved1 [10:02] */ 1166 #define DDR34_F0_PHY_CONTROL_REGS_STATIC_PAD_CTL_RESERVED1_MASK 0x000007fc 1167 #define DDR34_F0_PHY_CONTROL_REGS_STATIC_PAD_CTL_RESERVED1_ALIGN 0 1168 #define DDR34_F0_PHY_CONTROL_REGS_STATIC_PAD_CTL_RESERVED1_BITS 9 1169 #define DDR34_F0_PHY_CONTROL_REGS_STATIC_PAD_CTL_RESERVED1_SHIFT 2 1170 1171 /* DDR34_F0_PHY_CONTROL_REGS :: STATIC_PAD_CTL :: RX_MODE [01:00] */ 1172 #define DDR34_F0_PHY_CONTROL_REGS_STATIC_PAD_CTL_RX_MODE_MASK 0x00000003 1173 #define DDR34_F0_PHY_CONTROL_REGS_STATIC_PAD_CTL_RX_MODE_ALIGN 0 1174 #define DDR34_F0_PHY_CONTROL_REGS_STATIC_PAD_CTL_RX_MODE_BITS 2 1175 #define DDR34_F0_PHY_CONTROL_REGS_STATIC_PAD_CTL_RX_MODE_SHIFT 0 1176 1177 1178 /**************************************************************************** 1179 * DDR34_F0_PHY_CONTROL_REGS :: DRAM_CONFIG 1180 */ 1181 /* DDR34_F0_PHY_CONTROL_REGS :: DRAM_CONFIG :: INIT_MODE [31:31] */ 1182 #define DDR34_F0_PHY_CONTROL_REGS_DRAM_CONFIG_INIT_MODE_MASK 0x80000000 1183 #define DDR34_F0_PHY_CONTROL_REGS_DRAM_CONFIG_INIT_MODE_ALIGN 0 1184 #define DDR34_F0_PHY_CONTROL_REGS_DRAM_CONFIG_INIT_MODE_BITS 1 1185 #define DDR34_F0_PHY_CONTROL_REGS_DRAM_CONFIG_INIT_MODE_SHIFT 31 1186 1187 /* DDR34_F0_PHY_CONTROL_REGS :: DRAM_CONFIG :: reserved0 [30:27] */ 1188 #define DDR34_F0_PHY_CONTROL_REGS_DRAM_CONFIG_RESERVED0_MASK 0x78000000 1189 #define DDR34_F0_PHY_CONTROL_REGS_DRAM_CONFIG_RESERVED0_ALIGN 0 1190 #define DDR34_F0_PHY_CONTROL_REGS_DRAM_CONFIG_RESERVED0_BITS 4 1191 #define DDR34_F0_PHY_CONTROL_REGS_DRAM_CONFIG_RESERVED0_SHIFT 27 1192 1193 /* DDR34_F0_PHY_CONTROL_REGS :: DRAM_CONFIG :: SPLIT_DQ_BUS [26:26] */ 1194 #define DDR34_F0_PHY_CONTROL_REGS_DRAM_CONFIG_SPLIT_DQ_BUS_MASK 0x04000000 1195 #define DDR34_F0_PHY_CONTROL_REGS_DRAM_CONFIG_SPLIT_DQ_BUS_ALIGN 0 1196 #define DDR34_F0_PHY_CONTROL_REGS_DRAM_CONFIG_SPLIT_DQ_BUS_BITS 1 1197 #define DDR34_F0_PHY_CONTROL_REGS_DRAM_CONFIG_SPLIT_DQ_BUS_SHIFT 26 1198 1199 /* DDR34_F0_PHY_CONTROL_REGS :: DRAM_CONFIG :: BUS16 [25:25] */ 1200 #define DDR34_F0_PHY_CONTROL_REGS_DRAM_CONFIG_BUS16_MASK 0x02000000 1201 #define DDR34_F0_PHY_CONTROL_REGS_DRAM_CONFIG_BUS16_ALIGN 0 1202 #define DDR34_F0_PHY_CONTROL_REGS_DRAM_CONFIG_BUS16_BITS 1 1203 #define DDR34_F0_PHY_CONTROL_REGS_DRAM_CONFIG_BUS16_SHIFT 25 1204 1205 /* DDR34_F0_PHY_CONTROL_REGS :: DRAM_CONFIG :: BUS8 [24:24] */ 1206 #define DDR34_F0_PHY_CONTROL_REGS_DRAM_CONFIG_BUS8_MASK 0x01000000 1207 #define DDR34_F0_PHY_CONTROL_REGS_DRAM_CONFIG_BUS8_ALIGN 0 1208 #define DDR34_F0_PHY_CONTROL_REGS_DRAM_CONFIG_BUS8_BITS 1 1209 #define DDR34_F0_PHY_CONTROL_REGS_DRAM_CONFIG_BUS8_SHIFT 24 1210 1211 /* DDR34_F0_PHY_CONTROL_REGS :: DRAM_CONFIG :: reserved1 [23:17] */ 1212 #define DDR34_F0_PHY_CONTROL_REGS_DRAM_CONFIG_RESERVED1_MASK 0x00fe0000 1213 #define DDR34_F0_PHY_CONTROL_REGS_DRAM_CONFIG_RESERVED1_ALIGN 0 1214 #define DDR34_F0_PHY_CONTROL_REGS_DRAM_CONFIG_RESERVED1_BITS 7 1215 #define DDR34_F0_PHY_CONTROL_REGS_DRAM_CONFIG_RESERVED1_SHIFT 17 1216 1217 /* DDR34_F0_PHY_CONTROL_REGS :: DRAM_CONFIG :: DDR4_GEARDOWN_ENABLE [16:16] */ 1218 #define DDR34_F0_PHY_CONTROL_REGS_DRAM_CONFIG_DDR4_GEARDOWN_ENABLE_MASK 0x00010000 1219 #define DDR34_F0_PHY_CONTROL_REGS_DRAM_CONFIG_DDR4_GEARDOWN_ENABLE_ALIGN 0 1220 #define DDR34_F0_PHY_CONTROL_REGS_DRAM_CONFIG_DDR4_GEARDOWN_ENABLE_BITS 1 1221 #define DDR34_F0_PHY_CONTROL_REGS_DRAM_CONFIG_DDR4_GEARDOWN_ENABLE_SHIFT 16 1222 1223 /* DDR34_F0_PHY_CONTROL_REGS :: DRAM_CONFIG :: reserved2 [15:15] */ 1224 #define DDR34_F0_PHY_CONTROL_REGS_DRAM_CONFIG_RESERVED2_MASK 0x00008000 1225 #define DDR34_F0_PHY_CONTROL_REGS_DRAM_CONFIG_RESERVED2_ALIGN 0 1226 #define DDR34_F0_PHY_CONTROL_REGS_DRAM_CONFIG_RESERVED2_BITS 1 1227 #define DDR34_F0_PHY_CONTROL_REGS_DRAM_CONFIG_RESERVED2_SHIFT 15 1228 1229 /* DDR34_F0_PHY_CONTROL_REGS :: DRAM_CONFIG :: RDQS_MODE [14:14] */ 1230 #define DDR34_F0_PHY_CONTROL_REGS_DRAM_CONFIG_RDQS_MODE_MASK 0x00004000 1231 #define DDR34_F0_PHY_CONTROL_REGS_DRAM_CONFIG_RDQS_MODE_ALIGN 0 1232 #define DDR34_F0_PHY_CONTROL_REGS_DRAM_CONFIG_RDQS_MODE_BITS 1 1233 #define DDR34_F0_PHY_CONTROL_REGS_DRAM_CONFIG_RDQS_MODE_SHIFT 14 1234 1235 /* DDR34_F0_PHY_CONTROL_REGS :: DRAM_CONFIG :: GROUP_BITS [13:12] */ 1236 #define DDR34_F0_PHY_CONTROL_REGS_DRAM_CONFIG_GROUP_BITS_MASK 0x00003000 1237 #define DDR34_F0_PHY_CONTROL_REGS_DRAM_CONFIG_GROUP_BITS_ALIGN 0 1238 #define DDR34_F0_PHY_CONTROL_REGS_DRAM_CONFIG_GROUP_BITS_BITS 2 1239 #define DDR34_F0_PHY_CONTROL_REGS_DRAM_CONFIG_GROUP_BITS_SHIFT 12 1240 1241 /* DDR34_F0_PHY_CONTROL_REGS :: DRAM_CONFIG :: BANK_BITS [11:10] */ 1242 #define DDR34_F0_PHY_CONTROL_REGS_DRAM_CONFIG_BANK_BITS_MASK 0x00000c00 1243 #define DDR34_F0_PHY_CONTROL_REGS_DRAM_CONFIG_BANK_BITS_ALIGN 0 1244 #define DDR34_F0_PHY_CONTROL_REGS_DRAM_CONFIG_BANK_BITS_BITS 2 1245 #define DDR34_F0_PHY_CONTROL_REGS_DRAM_CONFIG_BANK_BITS_SHIFT 10 1246 1247 /* DDR34_F0_PHY_CONTROL_REGS :: DRAM_CONFIG :: COL_BITS [09:08] */ 1248 #define DDR34_F0_PHY_CONTROL_REGS_DRAM_CONFIG_COL_BITS_MASK 0x00000300 1249 #define DDR34_F0_PHY_CONTROL_REGS_DRAM_CONFIG_COL_BITS_ALIGN 0 1250 #define DDR34_F0_PHY_CONTROL_REGS_DRAM_CONFIG_COL_BITS_BITS 2 1251 #define DDR34_F0_PHY_CONTROL_REGS_DRAM_CONFIG_COL_BITS_SHIFT 8 1252 1253 /* DDR34_F0_PHY_CONTROL_REGS :: DRAM_CONFIG :: ROW_BITS [07:04] */ 1254 #define DDR34_F0_PHY_CONTROL_REGS_DRAM_CONFIG_ROW_BITS_MASK 0x000000f0 1255 #define DDR34_F0_PHY_CONTROL_REGS_DRAM_CONFIG_ROW_BITS_ALIGN 0 1256 #define DDR34_F0_PHY_CONTROL_REGS_DRAM_CONFIG_ROW_BITS_BITS 4 1257 #define DDR34_F0_PHY_CONTROL_REGS_DRAM_CONFIG_ROW_BITS_SHIFT 4 1258 1259 /* DDR34_F0_PHY_CONTROL_REGS :: DRAM_CONFIG :: DRAM_TYPE [03:00] */ 1260 #define DDR34_F0_PHY_CONTROL_REGS_DRAM_CONFIG_DRAM_TYPE_MASK 0x0000000f 1261 #define DDR34_F0_PHY_CONTROL_REGS_DRAM_CONFIG_DRAM_TYPE_ALIGN 0 1262 #define DDR34_F0_PHY_CONTROL_REGS_DRAM_CONFIG_DRAM_TYPE_BITS 4 1263 #define DDR34_F0_PHY_CONTROL_REGS_DRAM_CONFIG_DRAM_TYPE_SHIFT 0 1264 1265 1266 /**************************************************************************** 1267 * DDR34_F0_PHY_CONTROL_REGS :: DRAM_TIMING1 1268 */ 1269 /* DDR34_F0_PHY_CONTROL_REGS :: DRAM_TIMING1 :: TRAS [31:24] */ 1270 #define DDR34_F0_PHY_CONTROL_REGS_DRAM_TIMING1_TRAS_MASK 0xff000000 1271 #define DDR34_F0_PHY_CONTROL_REGS_DRAM_TIMING1_TRAS_ALIGN 0 1272 #define DDR34_F0_PHY_CONTROL_REGS_DRAM_TIMING1_TRAS_BITS 8 1273 #define DDR34_F0_PHY_CONTROL_REGS_DRAM_TIMING1_TRAS_SHIFT 24 1274 1275 /* DDR34_F0_PHY_CONTROL_REGS :: DRAM_TIMING1 :: TRRD [23:16] */ 1276 #define DDR34_F0_PHY_CONTROL_REGS_DRAM_TIMING1_TRRD_MASK 0x00ff0000 1277 #define DDR34_F0_PHY_CONTROL_REGS_DRAM_TIMING1_TRRD_ALIGN 0 1278 #define DDR34_F0_PHY_CONTROL_REGS_DRAM_TIMING1_TRRD_BITS 8 1279 #define DDR34_F0_PHY_CONTROL_REGS_DRAM_TIMING1_TRRD_SHIFT 16 1280 1281 /* DDR34_F0_PHY_CONTROL_REGS :: DRAM_TIMING1 :: TRP [15:08] */ 1282 #define DDR34_F0_PHY_CONTROL_REGS_DRAM_TIMING1_TRP_MASK 0x0000ff00 1283 #define DDR34_F0_PHY_CONTROL_REGS_DRAM_TIMING1_TRP_ALIGN 0 1284 #define DDR34_F0_PHY_CONTROL_REGS_DRAM_TIMING1_TRP_BITS 8 1285 #define DDR34_F0_PHY_CONTROL_REGS_DRAM_TIMING1_TRP_SHIFT 8 1286 1287 /* DDR34_F0_PHY_CONTROL_REGS :: DRAM_TIMING1 :: TRCD [07:00] */ 1288 #define DDR34_F0_PHY_CONTROL_REGS_DRAM_TIMING1_TRCD_MASK 0x000000ff 1289 #define DDR34_F0_PHY_CONTROL_REGS_DRAM_TIMING1_TRCD_ALIGN 0 1290 #define DDR34_F0_PHY_CONTROL_REGS_DRAM_TIMING1_TRCD_BITS 8 1291 #define DDR34_F0_PHY_CONTROL_REGS_DRAM_TIMING1_TRCD_SHIFT 0 1292 1293 1294 /**************************************************************************** 1295 * DDR34_F0_PHY_CONTROL_REGS :: DRAM_TIMING2 1296 */ 1297 /* DDR34_F0_PHY_CONTROL_REGS :: DRAM_TIMING2 :: TRTP [31:24] */ 1298 #define DDR34_F0_PHY_CONTROL_REGS_DRAM_TIMING2_TRTP_MASK 0xff000000 1299 #define DDR34_F0_PHY_CONTROL_REGS_DRAM_TIMING2_TRTP_ALIGN 0 1300 #define DDR34_F0_PHY_CONTROL_REGS_DRAM_TIMING2_TRTP_BITS 8 1301 #define DDR34_F0_PHY_CONTROL_REGS_DRAM_TIMING2_TRTP_SHIFT 24 1302 1303 /* DDR34_F0_PHY_CONTROL_REGS :: DRAM_TIMING2 :: TWR [23:16] */ 1304 #define DDR34_F0_PHY_CONTROL_REGS_DRAM_TIMING2_TWR_MASK 0x00ff0000 1305 #define DDR34_F0_PHY_CONTROL_REGS_DRAM_TIMING2_TWR_ALIGN 0 1306 #define DDR34_F0_PHY_CONTROL_REGS_DRAM_TIMING2_TWR_BITS 8 1307 #define DDR34_F0_PHY_CONTROL_REGS_DRAM_TIMING2_TWR_SHIFT 16 1308 1309 /* DDR34_F0_PHY_CONTROL_REGS :: DRAM_TIMING2 :: TCWL [15:08] */ 1310 #define DDR34_F0_PHY_CONTROL_REGS_DRAM_TIMING2_TCWL_MASK 0x0000ff00 1311 #define DDR34_F0_PHY_CONTROL_REGS_DRAM_TIMING2_TCWL_ALIGN 0 1312 #define DDR34_F0_PHY_CONTROL_REGS_DRAM_TIMING2_TCWL_BITS 8 1313 #define DDR34_F0_PHY_CONTROL_REGS_DRAM_TIMING2_TCWL_SHIFT 8 1314 1315 /* DDR34_F0_PHY_CONTROL_REGS :: DRAM_TIMING2 :: TCAS [07:00] */ 1316 #define DDR34_F0_PHY_CONTROL_REGS_DRAM_TIMING2_TCAS_MASK 0x000000ff 1317 #define DDR34_F0_PHY_CONTROL_REGS_DRAM_TIMING2_TCAS_ALIGN 0 1318 #define DDR34_F0_PHY_CONTROL_REGS_DRAM_TIMING2_TCAS_BITS 8 1319 #define DDR34_F0_PHY_CONTROL_REGS_DRAM_TIMING2_TCAS_SHIFT 0 1320 1321 1322 /**************************************************************************** 1323 * DDR34_F0_PHY_CONTROL_REGS :: DRAM_TIMING3 1324 */ 1325 /* DDR34_F0_PHY_CONTROL_REGS :: DRAM_TIMING3 :: reserved0 [31:28] */ 1326 #define DDR34_F0_PHY_CONTROL_REGS_DRAM_TIMING3_RESERVED0_MASK 0xf0000000 1327 #define DDR34_F0_PHY_CONTROL_REGS_DRAM_TIMING3_RESERVED0_ALIGN 0 1328 #define DDR34_F0_PHY_CONTROL_REGS_DRAM_TIMING3_RESERVED0_BITS 4 1329 #define DDR34_F0_PHY_CONTROL_REGS_DRAM_TIMING3_RESERVED0_SHIFT 28 1330 1331 /* DDR34_F0_PHY_CONTROL_REGS :: DRAM_TIMING3 :: TCAL [27:20] */ 1332 #define DDR34_F0_PHY_CONTROL_REGS_DRAM_TIMING3_TCAL_MASK 0x0ff00000 1333 #define DDR34_F0_PHY_CONTROL_REGS_DRAM_TIMING3_TCAL_ALIGN 0 1334 #define DDR34_F0_PHY_CONTROL_REGS_DRAM_TIMING3_TCAL_BITS 8 1335 #define DDR34_F0_PHY_CONTROL_REGS_DRAM_TIMING3_TCAL_SHIFT 20 1336 1337 /* DDR34_F0_PHY_CONTROL_REGS :: DRAM_TIMING3 :: TRTW [19:16] */ 1338 #define DDR34_F0_PHY_CONTROL_REGS_DRAM_TIMING3_TRTW_MASK 0x000f0000 1339 #define DDR34_F0_PHY_CONTROL_REGS_DRAM_TIMING3_TRTW_ALIGN 0 1340 #define DDR34_F0_PHY_CONTROL_REGS_DRAM_TIMING3_TRTW_BITS 4 1341 #define DDR34_F0_PHY_CONTROL_REGS_DRAM_TIMING3_TRTW_SHIFT 16 1342 1343 /* DDR34_F0_PHY_CONTROL_REGS :: DRAM_TIMING3 :: TWTR [15:12] */ 1344 #define DDR34_F0_PHY_CONTROL_REGS_DRAM_TIMING3_TWTR_MASK 0x0000f000 1345 #define DDR34_F0_PHY_CONTROL_REGS_DRAM_TIMING3_TWTR_ALIGN 0 1346 #define DDR34_F0_PHY_CONTROL_REGS_DRAM_TIMING3_TWTR_BITS 4 1347 #define DDR34_F0_PHY_CONTROL_REGS_DRAM_TIMING3_TWTR_SHIFT 12 1348 1349 /* DDR34_F0_PHY_CONTROL_REGS :: DRAM_TIMING3 :: TRFC [11:00] */ 1350 #define DDR34_F0_PHY_CONTROL_REGS_DRAM_TIMING3_TRFC_MASK 0x00000fff 1351 #define DDR34_F0_PHY_CONTROL_REGS_DRAM_TIMING3_TRFC_ALIGN 0 1352 #define DDR34_F0_PHY_CONTROL_REGS_DRAM_TIMING3_TRFC_BITS 12 1353 #define DDR34_F0_PHY_CONTROL_REGS_DRAM_TIMING3_TRFC_SHIFT 0 1354 1355 1356 /**************************************************************************** 1357 * DDR34_F0_PHY_CONTROL_REGS :: DRAM_TIMING4 1358 */ 1359 /* DDR34_F0_PHY_CONTROL_REGS :: DRAM_TIMING4 :: temp [31:00] */ 1360 #define DDR34_F0_PHY_CONTROL_REGS_DRAM_TIMING4_TEMP_MASK 0xffffffff 1361 #define DDR34_F0_PHY_CONTROL_REGS_DRAM_TIMING4_TEMP_ALIGN 0 1362 #define DDR34_F0_PHY_CONTROL_REGS_DRAM_TIMING4_TEMP_BITS 32 1363 #define DDR34_F0_PHY_CONTROL_REGS_DRAM_TIMING4_TEMP_SHIFT 0 1364 1365 1366 /**************************************************************************** 1367 * DDR34_F0_PHY_CONTROL_REGS :: VDL_CALIBRATE 1368 */ 1369 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CALIBRATE :: reserved0 [31:07] */ 1370 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CALIBRATE_RESERVED0_MASK 0xffffff80 1371 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CALIBRATE_RESERVED0_ALIGN 0 1372 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CALIBRATE_RESERVED0_BITS 25 1373 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CALIBRATE_RESERVED0_SHIFT 7 1374 1375 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CALIBRATE :: CALIB_FAST [06:06] */ 1376 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CALIBRATE_CALIB_FAST_MASK 0x00000040 1377 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CALIBRATE_CALIB_FAST_ALIGN 0 1378 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CALIBRATE_CALIB_FAST_BITS 1 1379 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CALIBRATE_CALIB_FAST_SHIFT 6 1380 1381 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CALIBRATE :: HALF_STEPS [05:05] */ 1382 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CALIBRATE_HALF_STEPS_MASK 0x00000020 1383 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CALIBRATE_HALF_STEPS_ALIGN 0 1384 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CALIBRATE_HALF_STEPS_BITS 1 1385 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CALIBRATE_HALF_STEPS_SHIFT 5 1386 1387 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CALIBRATE :: UPDATE_FAST [04:04] */ 1388 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CALIBRATE_UPDATE_FAST_MASK 0x00000010 1389 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CALIBRATE_UPDATE_FAST_ALIGN 0 1390 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CALIBRATE_UPDATE_FAST_BITS 1 1391 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CALIBRATE_UPDATE_FAST_SHIFT 4 1392 1393 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CALIBRATE :: UPDATE_REGS [03:03] */ 1394 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CALIBRATE_UPDATE_REGS_MASK 0x00000008 1395 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CALIBRATE_UPDATE_REGS_ALIGN 0 1396 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CALIBRATE_UPDATE_REGS_BITS 1 1397 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CALIBRATE_UPDATE_REGS_SHIFT 3 1398 1399 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CALIBRATE :: CALIB_FTM2 [02:02] */ 1400 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CALIBRATE_CALIB_FTM2_MASK 0x00000004 1401 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CALIBRATE_CALIB_FTM2_ALIGN 0 1402 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CALIBRATE_CALIB_FTM2_BITS 1 1403 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CALIBRATE_CALIB_FTM2_SHIFT 2 1404 1405 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CALIBRATE :: CALIB_PHYBIST [01:01] */ 1406 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CALIBRATE_CALIB_PHYBIST_MASK 0x00000002 1407 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CALIBRATE_CALIB_PHYBIST_ALIGN 0 1408 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CALIBRATE_CALIB_PHYBIST_BITS 1 1409 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CALIBRATE_CALIB_PHYBIST_SHIFT 1 1410 1411 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CALIBRATE :: CALIB_ONCE [00:00] */ 1412 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CALIBRATE_CALIB_ONCE_MASK 0x00000001 1413 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CALIBRATE_CALIB_ONCE_ALIGN 0 1414 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CALIBRATE_CALIB_ONCE_BITS 1 1415 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CALIBRATE_CALIB_ONCE_SHIFT 0 1416 1417 1418 /**************************************************************************** 1419 * DDR34_F0_PHY_CONTROL_REGS :: VDL_CALIB_STATUS1 1420 */ 1421 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CALIB_STATUS1 :: reserved0 [31:18] */ 1422 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_RESERVED0_MASK 0xfffc0000 1423 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_RESERVED0_ALIGN 0 1424 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_RESERVED0_BITS 14 1425 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_RESERVED0_SHIFT 18 1426 1427 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CALIB_STATUS1 :: CALIB_TOTAL_STEPS [17:08] */ 1428 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_CALIB_TOTAL_STEPS_MASK 0x0003ff00 1429 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_CALIB_TOTAL_STEPS_ALIGN 0 1430 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_CALIB_TOTAL_STEPS_BITS 10 1431 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_CALIB_TOTAL_STEPS_SHIFT 8 1432 1433 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CALIB_STATUS1 :: reserved1 [07:06] */ 1434 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_RESERVED1_MASK 0x000000c0 1435 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_RESERVED1_ALIGN 0 1436 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_RESERVED1_BITS 2 1437 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_RESERVED1_SHIFT 6 1438 1439 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CALIB_STATUS1 :: CALIB_BUS_ERROR [05:05] */ 1440 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_CALIB_BUS_ERROR_MASK 0x00000020 1441 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_CALIB_BUS_ERROR_ALIGN 0 1442 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_CALIB_BUS_ERROR_BITS 1 1443 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_CALIB_BUS_ERROR_SHIFT 5 1444 1445 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CALIB_STATUS1 :: CALIB_REGS_DONE [04:04] */ 1446 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_CALIB_REGS_DONE_MASK 0x00000010 1447 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_CALIB_REGS_DONE_ALIGN 0 1448 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_CALIB_REGS_DONE_BITS 1 1449 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_CALIB_REGS_DONE_SHIFT 4 1450 1451 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CALIB_STATUS1 :: CALIB_LOCK_6B [03:03] */ 1452 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_CALIB_LOCK_6B_MASK 0x00000008 1453 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_CALIB_LOCK_6B_ALIGN 0 1454 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_CALIB_LOCK_6B_BITS 1 1455 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_CALIB_LOCK_6B_SHIFT 3 1456 1457 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CALIB_STATUS1 :: CALIB_LOCK_4B [02:02] */ 1458 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_CALIB_LOCK_4B_MASK 0x00000004 1459 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_CALIB_LOCK_4B_ALIGN 0 1460 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_CALIB_LOCK_4B_BITS 1 1461 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_CALIB_LOCK_4B_SHIFT 2 1462 1463 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CALIB_STATUS1 :: CALIB_LOCK_2B [01:01] */ 1464 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_CALIB_LOCK_2B_MASK 0x00000002 1465 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_CALIB_LOCK_2B_ALIGN 0 1466 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_CALIB_LOCK_2B_BITS 1 1467 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_CALIB_LOCK_2B_SHIFT 1 1468 1469 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CALIB_STATUS1 :: CALIB_IDLE [00:00] */ 1470 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_CALIB_IDLE_MASK 0x00000001 1471 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_CALIB_IDLE_ALIGN 0 1472 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_CALIB_IDLE_BITS 1 1473 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_CALIB_IDLE_SHIFT 0 1474 1475 1476 /**************************************************************************** 1477 * DDR34_F0_PHY_CONTROL_REGS :: VDL_CALIB_STATUS2 1478 */ 1479 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CALIB_STATUS2 :: reserved0 [31:22] */ 1480 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CALIB_STATUS2_RESERVED0_MASK 0xffc00000 1481 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CALIB_STATUS2_RESERVED0_ALIGN 0 1482 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CALIB_STATUS2_RESERVED0_BITS 10 1483 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CALIB_STATUS2_RESERVED0_SHIFT 22 1484 1485 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CALIB_STATUS2 :: CALIB_4B_STEPS [21:12] */ 1486 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CALIB_STATUS2_CALIB_4B_STEPS_MASK 0x003ff000 1487 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CALIB_STATUS2_CALIB_4B_STEPS_ALIGN 0 1488 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CALIB_STATUS2_CALIB_4B_STEPS_BITS 10 1489 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CALIB_STATUS2_CALIB_4B_STEPS_SHIFT 12 1490 1491 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CALIB_STATUS2 :: reserved1 [11:10] */ 1492 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CALIB_STATUS2_RESERVED1_MASK 0x00000c00 1493 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CALIB_STATUS2_RESERVED1_ALIGN 0 1494 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CALIB_STATUS2_RESERVED1_BITS 2 1495 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CALIB_STATUS2_RESERVED1_SHIFT 10 1496 1497 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CALIB_STATUS2 :: CALIB_2B_STEPS [09:00] */ 1498 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CALIB_STATUS2_CALIB_2B_STEPS_MASK 0x000003ff 1499 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CALIB_STATUS2_CALIB_2B_STEPS_ALIGN 0 1500 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CALIB_STATUS2_CALIB_2B_STEPS_BITS 10 1501 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CALIB_STATUS2_CALIB_2B_STEPS_SHIFT 0 1502 1503 1504 /**************************************************************************** 1505 * DDR34_F0_PHY_CONTROL_REGS :: VDL_MONITOR_CONTROL 1506 */ 1507 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_MONITOR_CONTROL :: reserved0 [31:24] */ 1508 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_CONTROL_RESERVED0_MASK 0xff000000 1509 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_CONTROL_RESERVED0_ALIGN 0 1510 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_CONTROL_RESERVED0_BITS 8 1511 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_CONTROL_RESERVED0_SHIFT 24 1512 1513 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_MONITOR_CONTROL :: INTERVAL [23:08] */ 1514 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_CONTROL_INTERVAL_MASK 0x00ffff00 1515 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_CONTROL_INTERVAL_ALIGN 0 1516 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_CONTROL_INTERVAL_BITS 16 1517 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_CONTROL_INTERVAL_SHIFT 8 1518 1519 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_MONITOR_CONTROL :: reserved1 [07:04] */ 1520 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_CONTROL_RESERVED1_MASK 0x000000f0 1521 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_CONTROL_RESERVED1_ALIGN 0 1522 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_CONTROL_RESERVED1_BITS 4 1523 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_CONTROL_RESERVED1_SHIFT 4 1524 1525 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_MONITOR_CONTROL :: UPDATE [03:03] */ 1526 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_CONTROL_UPDATE_MASK 0x00000008 1527 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_CONTROL_UPDATE_ALIGN 0 1528 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_CONTROL_UPDATE_BITS 1 1529 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_CONTROL_UPDATE_SHIFT 3 1530 1531 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_MONITOR_CONTROL :: FORCE [02:02] */ 1532 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_CONTROL_FORCE_MASK 0x00000004 1533 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_CONTROL_FORCE_ALIGN 0 1534 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_CONTROL_FORCE_BITS 1 1535 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_CONTROL_FORCE_SHIFT 2 1536 1537 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_MONITOR_CONTROL :: DATA_RATE [01:01] */ 1538 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_CONTROL_DATA_RATE_MASK 0x00000002 1539 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_CONTROL_DATA_RATE_ALIGN 0 1540 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_CONTROL_DATA_RATE_BITS 1 1541 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_CONTROL_DATA_RATE_SHIFT 1 1542 1543 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_MONITOR_CONTROL :: ENABLE [00:00] */ 1544 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_CONTROL_ENABLE_MASK 0x00000001 1545 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_CONTROL_ENABLE_ALIGN 0 1546 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_CONTROL_ENABLE_BITS 1 1547 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_CONTROL_ENABLE_SHIFT 0 1548 1549 1550 /**************************************************************************** 1551 * DDR34_F0_PHY_CONTROL_REGS :: VDL_MONITOR_REF 1552 */ 1553 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_MONITOR_REF :: reserved0 [31:22] */ 1554 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_REF_RESERVED0_MASK 0xffc00000 1555 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_REF_RESERVED0_ALIGN 0 1556 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_REF_RESERVED0_BITS 10 1557 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_REF_RESERVED0_SHIFT 22 1558 1559 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_MONITOR_REF :: MONITOR_4B_STEPS [21:12] */ 1560 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_REF_MONITOR_4B_STEPS_MASK 0x003ff000 1561 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_REF_MONITOR_4B_STEPS_ALIGN 0 1562 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_REF_MONITOR_4B_STEPS_BITS 10 1563 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_REF_MONITOR_4B_STEPS_SHIFT 12 1564 1565 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_MONITOR_REF :: reserved1 [11:10] */ 1566 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_REF_RESERVED1_MASK 0x00000c00 1567 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_REF_RESERVED1_ALIGN 0 1568 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_REF_RESERVED1_BITS 2 1569 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_REF_RESERVED1_SHIFT 10 1570 1571 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_MONITOR_REF :: MONITOR_2B_STEPS [09:00] */ 1572 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_REF_MONITOR_2B_STEPS_MASK 0x000003ff 1573 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_REF_MONITOR_2B_STEPS_ALIGN 0 1574 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_REF_MONITOR_2B_STEPS_BITS 10 1575 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_REF_MONITOR_2B_STEPS_SHIFT 0 1576 1577 1578 /**************************************************************************** 1579 * DDR34_F0_PHY_CONTROL_REGS :: VDL_MONITOR_STATUS 1580 */ 1581 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_MONITOR_STATUS :: reserved0 [31:24] */ 1582 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_STATUS_RESERVED0_MASK 0xff000000 1583 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_STATUS_RESERVED0_ALIGN 0 1584 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_STATUS_RESERVED0_BITS 8 1585 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_STATUS_RESERVED0_SHIFT 24 1586 1587 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_MONITOR_STATUS :: MONITOR_CHANGE [23:16] */ 1588 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_STATUS_MONITOR_CHANGE_MASK 0x00ff0000 1589 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_STATUS_MONITOR_CHANGE_ALIGN 0 1590 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_STATUS_MONITOR_CHANGE_BITS 8 1591 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_STATUS_MONITOR_CHANGE_SHIFT 16 1592 1593 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_MONITOR_STATUS :: reserved1 [15:14] */ 1594 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_STATUS_RESERVED1_MASK 0x0000c000 1595 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_STATUS_RESERVED1_ALIGN 0 1596 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_STATUS_RESERVED1_BITS 2 1597 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_STATUS_RESERVED1_SHIFT 14 1598 1599 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_MONITOR_STATUS :: MONITOR_TOTAL [13:04] */ 1600 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_STATUS_MONITOR_TOTAL_MASK 0x00003ff0 1601 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_STATUS_MONITOR_TOTAL_ALIGN 0 1602 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_STATUS_MONITOR_TOTAL_BITS 10 1603 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_STATUS_MONITOR_TOTAL_SHIFT 4 1604 1605 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_MONITOR_STATUS :: ERROR [03:03] */ 1606 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_STATUS_ERROR_MASK 0x00000008 1607 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_STATUS_ERROR_ALIGN 0 1608 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_STATUS_ERROR_BITS 1 1609 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_STATUS_ERROR_SHIFT 3 1610 1611 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_MONITOR_STATUS :: PAUSED [02:01] */ 1612 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_STATUS_PAUSED_MASK 0x00000006 1613 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_STATUS_PAUSED_ALIGN 0 1614 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_STATUS_PAUSED_BITS 2 1615 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_STATUS_PAUSED_SHIFT 1 1616 1617 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_MONITOR_STATUS :: BUSY [00:00] */ 1618 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_STATUS_BUSY_MASK 0x00000001 1619 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_STATUS_BUSY_ALIGN 0 1620 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_STATUS_BUSY_BITS 1 1621 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_STATUS_BUSY_SHIFT 0 1622 1623 1624 /**************************************************************************** 1625 * DDR34_F0_PHY_CONTROL_REGS :: VDL_MONITOR_OVERRIDE 1626 */ 1627 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_MONITOR_OVERRIDE :: BUSY [31:31] */ 1628 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDE_BUSY_MASK 0x80000000 1629 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDE_BUSY_ALIGN 0 1630 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDE_BUSY_BITS 1 1631 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDE_BUSY_SHIFT 31 1632 1633 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_MONITOR_OVERRIDE :: reserved0 [30:17] */ 1634 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDE_RESERVED0_MASK 0x7ffe0000 1635 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDE_RESERVED0_ALIGN 0 1636 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDE_RESERVED0_BITS 14 1637 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDE_RESERVED0_SHIFT 17 1638 1639 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_MONITOR_OVERRIDE :: FORCE [16:16] */ 1640 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDE_FORCE_MASK 0x00010000 1641 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDE_FORCE_ALIGN 0 1642 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDE_FORCE_BITS 1 1643 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDE_FORCE_SHIFT 16 1644 1645 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_MONITOR_OVERRIDE :: reserved1 [15:05] */ 1646 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDE_RESERVED1_MASK 0x0000ffe0 1647 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDE_RESERVED1_ALIGN 0 1648 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDE_RESERVED1_BITS 11 1649 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDE_RESERVED1_SHIFT 5 1650 1651 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_MONITOR_OVERRIDE :: ADJ [04:00] */ 1652 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDE_ADJ_MASK 0x0000001f 1653 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDE_ADJ_ALIGN 0 1654 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDE_ADJ_BITS 5 1655 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDE_ADJ_SHIFT 0 1656 1657 1658 /**************************************************************************** 1659 * DDR34_F0_PHY_CONTROL_REGS :: VDL_MONITOR_OUT_CONTROL 1660 */ 1661 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_MONITOR_OUT_CONTROL :: reserved0 [31:20] */ 1662 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_OUT_CONTROL_RESERVED0_MASK 0xfff00000 1663 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_OUT_CONTROL_RESERVED0_ALIGN 0 1664 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_OUT_CONTROL_RESERVED0_BITS 12 1665 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_OUT_CONTROL_RESERVED0_SHIFT 20 1666 1667 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_MONITOR_OUT_CONTROL :: LOWER_LIMIT [19:12] */ 1668 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_OUT_CONTROL_LOWER_LIMIT_MASK 0x000ff000 1669 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_OUT_CONTROL_LOWER_LIMIT_ALIGN 0 1670 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_OUT_CONTROL_LOWER_LIMIT_BITS 8 1671 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_OUT_CONTROL_LOWER_LIMIT_SHIFT 12 1672 1673 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_MONITOR_OUT_CONTROL :: UPPER_LIMIT [11:04] */ 1674 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_OUT_CONTROL_UPPER_LIMIT_MASK 0x00000ff0 1675 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_OUT_CONTROL_UPPER_LIMIT_ALIGN 0 1676 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_OUT_CONTROL_UPPER_LIMIT_BITS 8 1677 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_OUT_CONTROL_UPPER_LIMIT_SHIFT 4 1678 1679 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_MONITOR_OUT_CONTROL :: reserved1 [03:01] */ 1680 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_OUT_CONTROL_RESERVED1_MASK 0x0000000e 1681 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_OUT_CONTROL_RESERVED1_ALIGN 0 1682 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_OUT_CONTROL_RESERVED1_BITS 3 1683 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_OUT_CONTROL_RESERVED1_SHIFT 1 1684 1685 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_MONITOR_OUT_CONTROL :: ENABLE [00:00] */ 1686 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_OUT_CONTROL_ENABLE_MASK 0x00000001 1687 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_OUT_CONTROL_ENABLE_ALIGN 0 1688 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_OUT_CONTROL_ENABLE_BITS 1 1689 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_OUT_CONTROL_ENABLE_SHIFT 0 1690 1691 1692 /**************************************************************************** 1693 * DDR34_F0_PHY_CONTROL_REGS :: VDL_MONITOR_OUT_STATUS 1694 */ 1695 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_MONITOR_OUT_STATUS :: reserved0 [31:24] */ 1696 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_RESERVED0_MASK 0xff000000 1697 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_RESERVED0_ALIGN 0 1698 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_RESERVED0_BITS 8 1699 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_RESERVED0_SHIFT 24 1700 1701 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_MONITOR_OUT_STATUS :: MONITOR_CHANGE [23:16] */ 1702 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_MONITOR_CHANGE_MASK 0x00ff0000 1703 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_MONITOR_CHANGE_ALIGN 0 1704 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_MONITOR_CHANGE_BITS 8 1705 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_MONITOR_CHANGE_SHIFT 16 1706 1707 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_MONITOR_OUT_STATUS :: reserved1 [15:14] */ 1708 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_RESERVED1_MASK 0x0000c000 1709 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_RESERVED1_ALIGN 0 1710 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_RESERVED1_BITS 2 1711 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_RESERVED1_SHIFT 14 1712 1713 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_MONITOR_OUT_STATUS :: MONITOR_TOTAL [13:04] */ 1714 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_MONITOR_TOTAL_MASK 0x00003ff0 1715 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_MONITOR_TOTAL_ALIGN 0 1716 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_MONITOR_TOTAL_BITS 10 1717 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_MONITOR_TOTAL_SHIFT 4 1718 1719 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_MONITOR_OUT_STATUS :: reserved2 [03:01] */ 1720 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_RESERVED2_MASK 0x0000000e 1721 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_RESERVED2_ALIGN 0 1722 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_RESERVED2_BITS 3 1723 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_RESERVED2_SHIFT 1 1724 1725 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_MONITOR_OUT_STATUS :: VALID [00:00] */ 1726 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_VALID_MASK 0x00000001 1727 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_VALID_ALIGN 0 1728 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_VALID_BITS 1 1729 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_VALID_SHIFT 0 1730 1731 1732 /**************************************************************************** 1733 * DDR34_F0_PHY_CONTROL_REGS :: VDL_MONITOR_OUT_STATUS_CLEAR 1734 */ 1735 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_MONITOR_OUT_STATUS_CLEAR :: reserved0 [31:01] */ 1736 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_CLEAR_RESERVED0_MASK 0xfffffffe 1737 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_CLEAR_RESERVED0_ALIGN 0 1738 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_CLEAR_RESERVED0_BITS 31 1739 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_CLEAR_RESERVED0_SHIFT 1 1740 1741 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_MONITOR_OUT_STATUS_CLEAR :: CLEAR [00:00] */ 1742 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_CLEAR_CLEAR_MASK 0x00000001 1743 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_CLEAR_CLEAR_ALIGN 0 1744 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_CLEAR_CLEAR_BITS 1 1745 #define DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_CLEAR_CLEAR_SHIFT 0 1746 1747 1748 /**************************************************************************** 1749 * DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AD00 1750 */ 1751 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AD00 :: BUSY [31:31] */ 1752 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD00_BUSY_MASK 0x80000000 1753 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD00_BUSY_ALIGN 0 1754 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD00_BUSY_BITS 1 1755 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD00_BUSY_SHIFT 31 1756 1757 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AD00 :: reserved0 [30:17] */ 1758 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD00_RESERVED0_MASK 0x7ffe0000 1759 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD00_RESERVED0_ALIGN 0 1760 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD00_RESERVED0_BITS 14 1761 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD00_RESERVED0_SHIFT 17 1762 1763 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AD00 :: FORCE [16:16] */ 1764 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD00_FORCE_MASK 0x00010000 1765 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD00_FORCE_ALIGN 0 1766 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD00_FORCE_BITS 1 1767 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD00_FORCE_SHIFT 16 1768 1769 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AD00 :: reserved1 [15:13] */ 1770 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD00_RESERVED1_MASK 0x0000e000 1771 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD00_RESERVED1_ALIGN 0 1772 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD00_RESERVED1_BITS 3 1773 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD00_RESERVED1_SHIFT 13 1774 1775 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AD00 :: ADJ_EN [12:12] */ 1776 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD00_ADJ_EN_MASK 0x00001000 1777 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD00_ADJ_EN_ALIGN 0 1778 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD00_ADJ_EN_BITS 1 1779 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD00_ADJ_EN_SHIFT 12 1780 1781 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AD00 :: reserved2 [11:09] */ 1782 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD00_RESERVED2_MASK 0x00000e00 1783 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD00_RESERVED2_ALIGN 0 1784 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD00_RESERVED2_BITS 3 1785 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD00_RESERVED2_SHIFT 9 1786 1787 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AD00 :: VDL_STEP [08:00] */ 1788 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD00_VDL_STEP_MASK 0x000001ff 1789 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD00_VDL_STEP_ALIGN 0 1790 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD00_VDL_STEP_BITS 9 1791 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD00_VDL_STEP_SHIFT 0 1792 1793 1794 /**************************************************************************** 1795 * DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AD01 1796 */ 1797 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AD01 :: BUSY [31:31] */ 1798 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD01_BUSY_MASK 0x80000000 1799 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD01_BUSY_ALIGN 0 1800 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD01_BUSY_BITS 1 1801 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD01_BUSY_SHIFT 31 1802 1803 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AD01 :: reserved0 [30:17] */ 1804 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD01_RESERVED0_MASK 0x7ffe0000 1805 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD01_RESERVED0_ALIGN 0 1806 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD01_RESERVED0_BITS 14 1807 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD01_RESERVED0_SHIFT 17 1808 1809 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AD01 :: FORCE [16:16] */ 1810 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD01_FORCE_MASK 0x00010000 1811 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD01_FORCE_ALIGN 0 1812 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD01_FORCE_BITS 1 1813 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD01_FORCE_SHIFT 16 1814 1815 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AD01 :: reserved1 [15:13] */ 1816 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD01_RESERVED1_MASK 0x0000e000 1817 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD01_RESERVED1_ALIGN 0 1818 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD01_RESERVED1_BITS 3 1819 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD01_RESERVED1_SHIFT 13 1820 1821 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AD01 :: ADJ_EN [12:12] */ 1822 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD01_ADJ_EN_MASK 0x00001000 1823 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD01_ADJ_EN_ALIGN 0 1824 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD01_ADJ_EN_BITS 1 1825 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD01_ADJ_EN_SHIFT 12 1826 1827 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AD01 :: reserved2 [11:09] */ 1828 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD01_RESERVED2_MASK 0x00000e00 1829 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD01_RESERVED2_ALIGN 0 1830 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD01_RESERVED2_BITS 3 1831 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD01_RESERVED2_SHIFT 9 1832 1833 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AD01 :: VDL_STEP [08:00] */ 1834 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD01_VDL_STEP_MASK 0x000001ff 1835 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD01_VDL_STEP_ALIGN 0 1836 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD01_VDL_STEP_BITS 9 1837 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD01_VDL_STEP_SHIFT 0 1838 1839 1840 /**************************************************************************** 1841 * DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AD02 1842 */ 1843 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AD02 :: BUSY [31:31] */ 1844 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD02_BUSY_MASK 0x80000000 1845 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD02_BUSY_ALIGN 0 1846 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD02_BUSY_BITS 1 1847 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD02_BUSY_SHIFT 31 1848 1849 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AD02 :: reserved0 [30:17] */ 1850 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD02_RESERVED0_MASK 0x7ffe0000 1851 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD02_RESERVED0_ALIGN 0 1852 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD02_RESERVED0_BITS 14 1853 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD02_RESERVED0_SHIFT 17 1854 1855 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AD02 :: FORCE [16:16] */ 1856 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD02_FORCE_MASK 0x00010000 1857 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD02_FORCE_ALIGN 0 1858 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD02_FORCE_BITS 1 1859 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD02_FORCE_SHIFT 16 1860 1861 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AD02 :: reserved1 [15:13] */ 1862 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD02_RESERVED1_MASK 0x0000e000 1863 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD02_RESERVED1_ALIGN 0 1864 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD02_RESERVED1_BITS 3 1865 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD02_RESERVED1_SHIFT 13 1866 1867 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AD02 :: ADJ_EN [12:12] */ 1868 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD02_ADJ_EN_MASK 0x00001000 1869 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD02_ADJ_EN_ALIGN 0 1870 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD02_ADJ_EN_BITS 1 1871 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD02_ADJ_EN_SHIFT 12 1872 1873 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AD02 :: reserved2 [11:09] */ 1874 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD02_RESERVED2_MASK 0x00000e00 1875 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD02_RESERVED2_ALIGN 0 1876 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD02_RESERVED2_BITS 3 1877 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD02_RESERVED2_SHIFT 9 1878 1879 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AD02 :: VDL_STEP [08:00] */ 1880 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD02_VDL_STEP_MASK 0x000001ff 1881 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD02_VDL_STEP_ALIGN 0 1882 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD02_VDL_STEP_BITS 9 1883 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD02_VDL_STEP_SHIFT 0 1884 1885 1886 /**************************************************************************** 1887 * DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AD03 1888 */ 1889 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AD03 :: BUSY [31:31] */ 1890 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD03_BUSY_MASK 0x80000000 1891 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD03_BUSY_ALIGN 0 1892 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD03_BUSY_BITS 1 1893 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD03_BUSY_SHIFT 31 1894 1895 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AD03 :: reserved0 [30:17] */ 1896 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD03_RESERVED0_MASK 0x7ffe0000 1897 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD03_RESERVED0_ALIGN 0 1898 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD03_RESERVED0_BITS 14 1899 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD03_RESERVED0_SHIFT 17 1900 1901 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AD03 :: FORCE [16:16] */ 1902 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD03_FORCE_MASK 0x00010000 1903 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD03_FORCE_ALIGN 0 1904 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD03_FORCE_BITS 1 1905 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD03_FORCE_SHIFT 16 1906 1907 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AD03 :: reserved1 [15:13] */ 1908 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD03_RESERVED1_MASK 0x0000e000 1909 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD03_RESERVED1_ALIGN 0 1910 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD03_RESERVED1_BITS 3 1911 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD03_RESERVED1_SHIFT 13 1912 1913 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AD03 :: ADJ_EN [12:12] */ 1914 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD03_ADJ_EN_MASK 0x00001000 1915 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD03_ADJ_EN_ALIGN 0 1916 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD03_ADJ_EN_BITS 1 1917 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD03_ADJ_EN_SHIFT 12 1918 1919 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AD03 :: reserved2 [11:09] */ 1920 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD03_RESERVED2_MASK 0x00000e00 1921 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD03_RESERVED2_ALIGN 0 1922 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD03_RESERVED2_BITS 3 1923 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD03_RESERVED2_SHIFT 9 1924 1925 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AD03 :: VDL_STEP [08:00] */ 1926 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD03_VDL_STEP_MASK 0x000001ff 1927 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD03_VDL_STEP_ALIGN 0 1928 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD03_VDL_STEP_BITS 9 1929 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD03_VDL_STEP_SHIFT 0 1930 1931 1932 /**************************************************************************** 1933 * DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AD04 1934 */ 1935 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AD04 :: BUSY [31:31] */ 1936 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD04_BUSY_MASK 0x80000000 1937 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD04_BUSY_ALIGN 0 1938 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD04_BUSY_BITS 1 1939 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD04_BUSY_SHIFT 31 1940 1941 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AD04 :: reserved0 [30:17] */ 1942 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD04_RESERVED0_MASK 0x7ffe0000 1943 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD04_RESERVED0_ALIGN 0 1944 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD04_RESERVED0_BITS 14 1945 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD04_RESERVED0_SHIFT 17 1946 1947 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AD04 :: FORCE [16:16] */ 1948 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD04_FORCE_MASK 0x00010000 1949 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD04_FORCE_ALIGN 0 1950 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD04_FORCE_BITS 1 1951 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD04_FORCE_SHIFT 16 1952 1953 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AD04 :: reserved1 [15:13] */ 1954 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD04_RESERVED1_MASK 0x0000e000 1955 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD04_RESERVED1_ALIGN 0 1956 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD04_RESERVED1_BITS 3 1957 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD04_RESERVED1_SHIFT 13 1958 1959 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AD04 :: ADJ_EN [12:12] */ 1960 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD04_ADJ_EN_MASK 0x00001000 1961 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD04_ADJ_EN_ALIGN 0 1962 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD04_ADJ_EN_BITS 1 1963 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD04_ADJ_EN_SHIFT 12 1964 1965 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AD04 :: reserved2 [11:09] */ 1966 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD04_RESERVED2_MASK 0x00000e00 1967 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD04_RESERVED2_ALIGN 0 1968 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD04_RESERVED2_BITS 3 1969 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD04_RESERVED2_SHIFT 9 1970 1971 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AD04 :: VDL_STEP [08:00] */ 1972 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD04_VDL_STEP_MASK 0x000001ff 1973 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD04_VDL_STEP_ALIGN 0 1974 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD04_VDL_STEP_BITS 9 1975 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD04_VDL_STEP_SHIFT 0 1976 1977 1978 /**************************************************************************** 1979 * DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AD05 1980 */ 1981 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AD05 :: BUSY [31:31] */ 1982 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD05_BUSY_MASK 0x80000000 1983 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD05_BUSY_ALIGN 0 1984 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD05_BUSY_BITS 1 1985 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD05_BUSY_SHIFT 31 1986 1987 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AD05 :: reserved0 [30:17] */ 1988 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD05_RESERVED0_MASK 0x7ffe0000 1989 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD05_RESERVED0_ALIGN 0 1990 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD05_RESERVED0_BITS 14 1991 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD05_RESERVED0_SHIFT 17 1992 1993 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AD05 :: FORCE [16:16] */ 1994 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD05_FORCE_MASK 0x00010000 1995 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD05_FORCE_ALIGN 0 1996 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD05_FORCE_BITS 1 1997 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD05_FORCE_SHIFT 16 1998 1999 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AD05 :: reserved1 [15:13] */ 2000 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD05_RESERVED1_MASK 0x0000e000 2001 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD05_RESERVED1_ALIGN 0 2002 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD05_RESERVED1_BITS 3 2003 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD05_RESERVED1_SHIFT 13 2004 2005 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AD05 :: ADJ_EN [12:12] */ 2006 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD05_ADJ_EN_MASK 0x00001000 2007 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD05_ADJ_EN_ALIGN 0 2008 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD05_ADJ_EN_BITS 1 2009 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD05_ADJ_EN_SHIFT 12 2010 2011 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AD05 :: reserved2 [11:09] */ 2012 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD05_RESERVED2_MASK 0x00000e00 2013 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD05_RESERVED2_ALIGN 0 2014 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD05_RESERVED2_BITS 3 2015 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD05_RESERVED2_SHIFT 9 2016 2017 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AD05 :: VDL_STEP [08:00] */ 2018 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD05_VDL_STEP_MASK 0x000001ff 2019 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD05_VDL_STEP_ALIGN 0 2020 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD05_VDL_STEP_BITS 9 2021 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD05_VDL_STEP_SHIFT 0 2022 2023 2024 /**************************************************************************** 2025 * DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AD06 2026 */ 2027 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AD06 :: BUSY [31:31] */ 2028 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD06_BUSY_MASK 0x80000000 2029 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD06_BUSY_ALIGN 0 2030 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD06_BUSY_BITS 1 2031 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD06_BUSY_SHIFT 31 2032 2033 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AD06 :: reserved0 [30:17] */ 2034 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD06_RESERVED0_MASK 0x7ffe0000 2035 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD06_RESERVED0_ALIGN 0 2036 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD06_RESERVED0_BITS 14 2037 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD06_RESERVED0_SHIFT 17 2038 2039 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AD06 :: FORCE [16:16] */ 2040 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD06_FORCE_MASK 0x00010000 2041 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD06_FORCE_ALIGN 0 2042 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD06_FORCE_BITS 1 2043 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD06_FORCE_SHIFT 16 2044 2045 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AD06 :: reserved1 [15:13] */ 2046 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD06_RESERVED1_MASK 0x0000e000 2047 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD06_RESERVED1_ALIGN 0 2048 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD06_RESERVED1_BITS 3 2049 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD06_RESERVED1_SHIFT 13 2050 2051 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AD06 :: ADJ_EN [12:12] */ 2052 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD06_ADJ_EN_MASK 0x00001000 2053 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD06_ADJ_EN_ALIGN 0 2054 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD06_ADJ_EN_BITS 1 2055 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD06_ADJ_EN_SHIFT 12 2056 2057 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AD06 :: reserved2 [11:09] */ 2058 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD06_RESERVED2_MASK 0x00000e00 2059 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD06_RESERVED2_ALIGN 0 2060 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD06_RESERVED2_BITS 3 2061 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD06_RESERVED2_SHIFT 9 2062 2063 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AD06 :: VDL_STEP [08:00] */ 2064 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD06_VDL_STEP_MASK 0x000001ff 2065 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD06_VDL_STEP_ALIGN 0 2066 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD06_VDL_STEP_BITS 9 2067 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD06_VDL_STEP_SHIFT 0 2068 2069 2070 /**************************************************************************** 2071 * DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AD07 2072 */ 2073 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AD07 :: BUSY [31:31] */ 2074 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD07_BUSY_MASK 0x80000000 2075 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD07_BUSY_ALIGN 0 2076 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD07_BUSY_BITS 1 2077 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD07_BUSY_SHIFT 31 2078 2079 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AD07 :: reserved0 [30:17] */ 2080 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD07_RESERVED0_MASK 0x7ffe0000 2081 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD07_RESERVED0_ALIGN 0 2082 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD07_RESERVED0_BITS 14 2083 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD07_RESERVED0_SHIFT 17 2084 2085 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AD07 :: FORCE [16:16] */ 2086 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD07_FORCE_MASK 0x00010000 2087 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD07_FORCE_ALIGN 0 2088 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD07_FORCE_BITS 1 2089 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD07_FORCE_SHIFT 16 2090 2091 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AD07 :: reserved1 [15:13] */ 2092 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD07_RESERVED1_MASK 0x0000e000 2093 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD07_RESERVED1_ALIGN 0 2094 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD07_RESERVED1_BITS 3 2095 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD07_RESERVED1_SHIFT 13 2096 2097 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AD07 :: ADJ_EN [12:12] */ 2098 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD07_ADJ_EN_MASK 0x00001000 2099 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD07_ADJ_EN_ALIGN 0 2100 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD07_ADJ_EN_BITS 1 2101 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD07_ADJ_EN_SHIFT 12 2102 2103 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AD07 :: reserved2 [11:09] */ 2104 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD07_RESERVED2_MASK 0x00000e00 2105 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD07_RESERVED2_ALIGN 0 2106 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD07_RESERVED2_BITS 3 2107 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD07_RESERVED2_SHIFT 9 2108 2109 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AD07 :: VDL_STEP [08:00] */ 2110 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD07_VDL_STEP_MASK 0x000001ff 2111 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD07_VDL_STEP_ALIGN 0 2112 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD07_VDL_STEP_BITS 9 2113 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD07_VDL_STEP_SHIFT 0 2114 2115 2116 /**************************************************************************** 2117 * DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AD08 2118 */ 2119 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AD08 :: BUSY [31:31] */ 2120 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD08_BUSY_MASK 0x80000000 2121 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD08_BUSY_ALIGN 0 2122 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD08_BUSY_BITS 1 2123 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD08_BUSY_SHIFT 31 2124 2125 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AD08 :: reserved0 [30:17] */ 2126 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD08_RESERVED0_MASK 0x7ffe0000 2127 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD08_RESERVED0_ALIGN 0 2128 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD08_RESERVED0_BITS 14 2129 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD08_RESERVED0_SHIFT 17 2130 2131 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AD08 :: FORCE [16:16] */ 2132 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD08_FORCE_MASK 0x00010000 2133 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD08_FORCE_ALIGN 0 2134 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD08_FORCE_BITS 1 2135 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD08_FORCE_SHIFT 16 2136 2137 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AD08 :: reserved1 [15:13] */ 2138 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD08_RESERVED1_MASK 0x0000e000 2139 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD08_RESERVED1_ALIGN 0 2140 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD08_RESERVED1_BITS 3 2141 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD08_RESERVED1_SHIFT 13 2142 2143 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AD08 :: ADJ_EN [12:12] */ 2144 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD08_ADJ_EN_MASK 0x00001000 2145 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD08_ADJ_EN_ALIGN 0 2146 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD08_ADJ_EN_BITS 1 2147 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD08_ADJ_EN_SHIFT 12 2148 2149 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AD08 :: reserved2 [11:09] */ 2150 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD08_RESERVED2_MASK 0x00000e00 2151 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD08_RESERVED2_ALIGN 0 2152 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD08_RESERVED2_BITS 3 2153 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD08_RESERVED2_SHIFT 9 2154 2155 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AD08 :: VDL_STEP [08:00] */ 2156 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD08_VDL_STEP_MASK 0x000001ff 2157 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD08_VDL_STEP_ALIGN 0 2158 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD08_VDL_STEP_BITS 9 2159 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD08_VDL_STEP_SHIFT 0 2160 2161 2162 /**************************************************************************** 2163 * DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AD09 2164 */ 2165 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AD09 :: BUSY [31:31] */ 2166 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD09_BUSY_MASK 0x80000000 2167 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD09_BUSY_ALIGN 0 2168 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD09_BUSY_BITS 1 2169 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD09_BUSY_SHIFT 31 2170 2171 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AD09 :: reserved0 [30:17] */ 2172 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD09_RESERVED0_MASK 0x7ffe0000 2173 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD09_RESERVED0_ALIGN 0 2174 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD09_RESERVED0_BITS 14 2175 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD09_RESERVED0_SHIFT 17 2176 2177 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AD09 :: FORCE [16:16] */ 2178 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD09_FORCE_MASK 0x00010000 2179 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD09_FORCE_ALIGN 0 2180 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD09_FORCE_BITS 1 2181 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD09_FORCE_SHIFT 16 2182 2183 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AD09 :: reserved1 [15:13] */ 2184 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD09_RESERVED1_MASK 0x0000e000 2185 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD09_RESERVED1_ALIGN 0 2186 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD09_RESERVED1_BITS 3 2187 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD09_RESERVED1_SHIFT 13 2188 2189 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AD09 :: ADJ_EN [12:12] */ 2190 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD09_ADJ_EN_MASK 0x00001000 2191 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD09_ADJ_EN_ALIGN 0 2192 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD09_ADJ_EN_BITS 1 2193 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD09_ADJ_EN_SHIFT 12 2194 2195 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AD09 :: reserved2 [11:09] */ 2196 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD09_RESERVED2_MASK 0x00000e00 2197 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD09_RESERVED2_ALIGN 0 2198 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD09_RESERVED2_BITS 3 2199 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD09_RESERVED2_SHIFT 9 2200 2201 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AD09 :: VDL_STEP [08:00] */ 2202 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD09_VDL_STEP_MASK 0x000001ff 2203 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD09_VDL_STEP_ALIGN 0 2204 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD09_VDL_STEP_BITS 9 2205 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD09_VDL_STEP_SHIFT 0 2206 2207 2208 /**************************************************************************** 2209 * DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AD10 2210 */ 2211 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AD10 :: BUSY [31:31] */ 2212 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD10_BUSY_MASK 0x80000000 2213 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD10_BUSY_ALIGN 0 2214 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD10_BUSY_BITS 1 2215 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD10_BUSY_SHIFT 31 2216 2217 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AD10 :: reserved0 [30:17] */ 2218 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD10_RESERVED0_MASK 0x7ffe0000 2219 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD10_RESERVED0_ALIGN 0 2220 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD10_RESERVED0_BITS 14 2221 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD10_RESERVED0_SHIFT 17 2222 2223 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AD10 :: FORCE [16:16] */ 2224 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD10_FORCE_MASK 0x00010000 2225 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD10_FORCE_ALIGN 0 2226 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD10_FORCE_BITS 1 2227 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD10_FORCE_SHIFT 16 2228 2229 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AD10 :: reserved1 [15:13] */ 2230 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD10_RESERVED1_MASK 0x0000e000 2231 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD10_RESERVED1_ALIGN 0 2232 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD10_RESERVED1_BITS 3 2233 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD10_RESERVED1_SHIFT 13 2234 2235 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AD10 :: ADJ_EN [12:12] */ 2236 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD10_ADJ_EN_MASK 0x00001000 2237 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD10_ADJ_EN_ALIGN 0 2238 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD10_ADJ_EN_BITS 1 2239 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD10_ADJ_EN_SHIFT 12 2240 2241 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AD10 :: reserved2 [11:09] */ 2242 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD10_RESERVED2_MASK 0x00000e00 2243 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD10_RESERVED2_ALIGN 0 2244 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD10_RESERVED2_BITS 3 2245 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD10_RESERVED2_SHIFT 9 2246 2247 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AD10 :: VDL_STEP [08:00] */ 2248 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD10_VDL_STEP_MASK 0x000001ff 2249 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD10_VDL_STEP_ALIGN 0 2250 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD10_VDL_STEP_BITS 9 2251 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD10_VDL_STEP_SHIFT 0 2252 2253 2254 /**************************************************************************** 2255 * DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AD11 2256 */ 2257 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AD11 :: BUSY [31:31] */ 2258 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD11_BUSY_MASK 0x80000000 2259 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD11_BUSY_ALIGN 0 2260 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD11_BUSY_BITS 1 2261 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD11_BUSY_SHIFT 31 2262 2263 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AD11 :: reserved0 [30:17] */ 2264 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD11_RESERVED0_MASK 0x7ffe0000 2265 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD11_RESERVED0_ALIGN 0 2266 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD11_RESERVED0_BITS 14 2267 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD11_RESERVED0_SHIFT 17 2268 2269 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AD11 :: FORCE [16:16] */ 2270 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD11_FORCE_MASK 0x00010000 2271 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD11_FORCE_ALIGN 0 2272 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD11_FORCE_BITS 1 2273 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD11_FORCE_SHIFT 16 2274 2275 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AD11 :: reserved1 [15:13] */ 2276 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD11_RESERVED1_MASK 0x0000e000 2277 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD11_RESERVED1_ALIGN 0 2278 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD11_RESERVED1_BITS 3 2279 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD11_RESERVED1_SHIFT 13 2280 2281 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AD11 :: ADJ_EN [12:12] */ 2282 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD11_ADJ_EN_MASK 0x00001000 2283 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD11_ADJ_EN_ALIGN 0 2284 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD11_ADJ_EN_BITS 1 2285 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD11_ADJ_EN_SHIFT 12 2286 2287 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AD11 :: reserved2 [11:09] */ 2288 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD11_RESERVED2_MASK 0x00000e00 2289 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD11_RESERVED2_ALIGN 0 2290 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD11_RESERVED2_BITS 3 2291 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD11_RESERVED2_SHIFT 9 2292 2293 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AD11 :: VDL_STEP [08:00] */ 2294 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD11_VDL_STEP_MASK 0x000001ff 2295 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD11_VDL_STEP_ALIGN 0 2296 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD11_VDL_STEP_BITS 9 2297 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD11_VDL_STEP_SHIFT 0 2298 2299 2300 /**************************************************************************** 2301 * DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AD12 2302 */ 2303 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AD12 :: BUSY [31:31] */ 2304 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD12_BUSY_MASK 0x80000000 2305 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD12_BUSY_ALIGN 0 2306 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD12_BUSY_BITS 1 2307 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD12_BUSY_SHIFT 31 2308 2309 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AD12 :: reserved0 [30:17] */ 2310 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD12_RESERVED0_MASK 0x7ffe0000 2311 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD12_RESERVED0_ALIGN 0 2312 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD12_RESERVED0_BITS 14 2313 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD12_RESERVED0_SHIFT 17 2314 2315 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AD12 :: FORCE [16:16] */ 2316 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD12_FORCE_MASK 0x00010000 2317 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD12_FORCE_ALIGN 0 2318 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD12_FORCE_BITS 1 2319 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD12_FORCE_SHIFT 16 2320 2321 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AD12 :: reserved1 [15:13] */ 2322 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD12_RESERVED1_MASK 0x0000e000 2323 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD12_RESERVED1_ALIGN 0 2324 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD12_RESERVED1_BITS 3 2325 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD12_RESERVED1_SHIFT 13 2326 2327 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AD12 :: ADJ_EN [12:12] */ 2328 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD12_ADJ_EN_MASK 0x00001000 2329 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD12_ADJ_EN_ALIGN 0 2330 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD12_ADJ_EN_BITS 1 2331 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD12_ADJ_EN_SHIFT 12 2332 2333 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AD12 :: reserved2 [11:09] */ 2334 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD12_RESERVED2_MASK 0x00000e00 2335 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD12_RESERVED2_ALIGN 0 2336 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD12_RESERVED2_BITS 3 2337 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD12_RESERVED2_SHIFT 9 2338 2339 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AD12 :: VDL_STEP [08:00] */ 2340 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD12_VDL_STEP_MASK 0x000001ff 2341 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD12_VDL_STEP_ALIGN 0 2342 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD12_VDL_STEP_BITS 9 2343 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD12_VDL_STEP_SHIFT 0 2344 2345 2346 /**************************************************************************** 2347 * DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AD13 2348 */ 2349 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AD13 :: BUSY [31:31] */ 2350 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD13_BUSY_MASK 0x80000000 2351 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD13_BUSY_ALIGN 0 2352 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD13_BUSY_BITS 1 2353 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD13_BUSY_SHIFT 31 2354 2355 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AD13 :: reserved0 [30:17] */ 2356 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD13_RESERVED0_MASK 0x7ffe0000 2357 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD13_RESERVED0_ALIGN 0 2358 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD13_RESERVED0_BITS 14 2359 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD13_RESERVED0_SHIFT 17 2360 2361 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AD13 :: FORCE [16:16] */ 2362 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD13_FORCE_MASK 0x00010000 2363 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD13_FORCE_ALIGN 0 2364 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD13_FORCE_BITS 1 2365 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD13_FORCE_SHIFT 16 2366 2367 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AD13 :: reserved1 [15:13] */ 2368 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD13_RESERVED1_MASK 0x0000e000 2369 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD13_RESERVED1_ALIGN 0 2370 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD13_RESERVED1_BITS 3 2371 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD13_RESERVED1_SHIFT 13 2372 2373 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AD13 :: ADJ_EN [12:12] */ 2374 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD13_ADJ_EN_MASK 0x00001000 2375 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD13_ADJ_EN_ALIGN 0 2376 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD13_ADJ_EN_BITS 1 2377 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD13_ADJ_EN_SHIFT 12 2378 2379 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AD13 :: reserved2 [11:09] */ 2380 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD13_RESERVED2_MASK 0x00000e00 2381 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD13_RESERVED2_ALIGN 0 2382 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD13_RESERVED2_BITS 3 2383 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD13_RESERVED2_SHIFT 9 2384 2385 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AD13 :: VDL_STEP [08:00] */ 2386 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD13_VDL_STEP_MASK 0x000001ff 2387 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD13_VDL_STEP_ALIGN 0 2388 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD13_VDL_STEP_BITS 9 2389 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD13_VDL_STEP_SHIFT 0 2390 2391 2392 /**************************************************************************** 2393 * DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AD14 2394 */ 2395 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AD14 :: BUSY [31:31] */ 2396 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD14_BUSY_MASK 0x80000000 2397 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD14_BUSY_ALIGN 0 2398 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD14_BUSY_BITS 1 2399 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD14_BUSY_SHIFT 31 2400 2401 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AD14 :: reserved0 [30:17] */ 2402 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD14_RESERVED0_MASK 0x7ffe0000 2403 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD14_RESERVED0_ALIGN 0 2404 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD14_RESERVED0_BITS 14 2405 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD14_RESERVED0_SHIFT 17 2406 2407 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AD14 :: FORCE [16:16] */ 2408 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD14_FORCE_MASK 0x00010000 2409 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD14_FORCE_ALIGN 0 2410 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD14_FORCE_BITS 1 2411 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD14_FORCE_SHIFT 16 2412 2413 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AD14 :: reserved1 [15:13] */ 2414 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD14_RESERVED1_MASK 0x0000e000 2415 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD14_RESERVED1_ALIGN 0 2416 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD14_RESERVED1_BITS 3 2417 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD14_RESERVED1_SHIFT 13 2418 2419 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AD14 :: ADJ_EN [12:12] */ 2420 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD14_ADJ_EN_MASK 0x00001000 2421 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD14_ADJ_EN_ALIGN 0 2422 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD14_ADJ_EN_BITS 1 2423 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD14_ADJ_EN_SHIFT 12 2424 2425 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AD14 :: reserved2 [11:09] */ 2426 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD14_RESERVED2_MASK 0x00000e00 2427 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD14_RESERVED2_ALIGN 0 2428 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD14_RESERVED2_BITS 3 2429 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD14_RESERVED2_SHIFT 9 2430 2431 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AD14 :: VDL_STEP [08:00] */ 2432 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD14_VDL_STEP_MASK 0x000001ff 2433 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD14_VDL_STEP_ALIGN 0 2434 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD14_VDL_STEP_BITS 9 2435 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD14_VDL_STEP_SHIFT 0 2436 2437 2438 /**************************************************************************** 2439 * DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AD15 2440 */ 2441 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AD15 :: BUSY [31:31] */ 2442 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD15_BUSY_MASK 0x80000000 2443 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD15_BUSY_ALIGN 0 2444 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD15_BUSY_BITS 1 2445 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD15_BUSY_SHIFT 31 2446 2447 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AD15 :: reserved0 [30:17] */ 2448 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD15_RESERVED0_MASK 0x7ffe0000 2449 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD15_RESERVED0_ALIGN 0 2450 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD15_RESERVED0_BITS 14 2451 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD15_RESERVED0_SHIFT 17 2452 2453 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AD15 :: FORCE [16:16] */ 2454 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD15_FORCE_MASK 0x00010000 2455 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD15_FORCE_ALIGN 0 2456 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD15_FORCE_BITS 1 2457 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD15_FORCE_SHIFT 16 2458 2459 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AD15 :: reserved1 [15:13] */ 2460 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD15_RESERVED1_MASK 0x0000e000 2461 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD15_RESERVED1_ALIGN 0 2462 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD15_RESERVED1_BITS 3 2463 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD15_RESERVED1_SHIFT 13 2464 2465 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AD15 :: ADJ_EN [12:12] */ 2466 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD15_ADJ_EN_MASK 0x00001000 2467 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD15_ADJ_EN_ALIGN 0 2468 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD15_ADJ_EN_BITS 1 2469 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD15_ADJ_EN_SHIFT 12 2470 2471 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AD15 :: reserved2 [11:09] */ 2472 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD15_RESERVED2_MASK 0x00000e00 2473 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD15_RESERVED2_ALIGN 0 2474 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD15_RESERVED2_BITS 3 2475 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD15_RESERVED2_SHIFT 9 2476 2477 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AD15 :: VDL_STEP [08:00] */ 2478 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD15_VDL_STEP_MASK 0x000001ff 2479 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD15_VDL_STEP_ALIGN 0 2480 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD15_VDL_STEP_BITS 9 2481 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD15_VDL_STEP_SHIFT 0 2482 2483 2484 /**************************************************************************** 2485 * DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_BA0 2486 */ 2487 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_BA0 :: BUSY [31:31] */ 2488 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_BA0_BUSY_MASK 0x80000000 2489 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_BA0_BUSY_ALIGN 0 2490 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_BA0_BUSY_BITS 1 2491 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_BA0_BUSY_SHIFT 31 2492 2493 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_BA0 :: reserved0 [30:17] */ 2494 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_BA0_RESERVED0_MASK 0x7ffe0000 2495 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_BA0_RESERVED0_ALIGN 0 2496 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_BA0_RESERVED0_BITS 14 2497 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_BA0_RESERVED0_SHIFT 17 2498 2499 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_BA0 :: FORCE [16:16] */ 2500 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_BA0_FORCE_MASK 0x00010000 2501 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_BA0_FORCE_ALIGN 0 2502 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_BA0_FORCE_BITS 1 2503 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_BA0_FORCE_SHIFT 16 2504 2505 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_BA0 :: reserved1 [15:13] */ 2506 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_BA0_RESERVED1_MASK 0x0000e000 2507 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_BA0_RESERVED1_ALIGN 0 2508 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_BA0_RESERVED1_BITS 3 2509 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_BA0_RESERVED1_SHIFT 13 2510 2511 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_BA0 :: ADJ_EN [12:12] */ 2512 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_BA0_ADJ_EN_MASK 0x00001000 2513 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_BA0_ADJ_EN_ALIGN 0 2514 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_BA0_ADJ_EN_BITS 1 2515 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_BA0_ADJ_EN_SHIFT 12 2516 2517 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_BA0 :: reserved2 [11:09] */ 2518 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_BA0_RESERVED2_MASK 0x00000e00 2519 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_BA0_RESERVED2_ALIGN 0 2520 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_BA0_RESERVED2_BITS 3 2521 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_BA0_RESERVED2_SHIFT 9 2522 2523 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_BA0 :: VDL_STEP [08:00] */ 2524 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_BA0_VDL_STEP_MASK 0x000001ff 2525 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_BA0_VDL_STEP_ALIGN 0 2526 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_BA0_VDL_STEP_BITS 9 2527 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_BA0_VDL_STEP_SHIFT 0 2528 2529 2530 /**************************************************************************** 2531 * DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_BA1 2532 */ 2533 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_BA1 :: BUSY [31:31] */ 2534 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_BA1_BUSY_MASK 0x80000000 2535 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_BA1_BUSY_ALIGN 0 2536 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_BA1_BUSY_BITS 1 2537 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_BA1_BUSY_SHIFT 31 2538 2539 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_BA1 :: reserved0 [30:17] */ 2540 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_BA1_RESERVED0_MASK 0x7ffe0000 2541 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_BA1_RESERVED0_ALIGN 0 2542 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_BA1_RESERVED0_BITS 14 2543 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_BA1_RESERVED0_SHIFT 17 2544 2545 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_BA1 :: FORCE [16:16] */ 2546 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_BA1_FORCE_MASK 0x00010000 2547 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_BA1_FORCE_ALIGN 0 2548 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_BA1_FORCE_BITS 1 2549 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_BA1_FORCE_SHIFT 16 2550 2551 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_BA1 :: reserved1 [15:13] */ 2552 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_BA1_RESERVED1_MASK 0x0000e000 2553 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_BA1_RESERVED1_ALIGN 0 2554 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_BA1_RESERVED1_BITS 3 2555 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_BA1_RESERVED1_SHIFT 13 2556 2557 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_BA1 :: ADJ_EN [12:12] */ 2558 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_BA1_ADJ_EN_MASK 0x00001000 2559 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_BA1_ADJ_EN_ALIGN 0 2560 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_BA1_ADJ_EN_BITS 1 2561 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_BA1_ADJ_EN_SHIFT 12 2562 2563 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_BA1 :: reserved2 [11:09] */ 2564 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_BA1_RESERVED2_MASK 0x00000e00 2565 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_BA1_RESERVED2_ALIGN 0 2566 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_BA1_RESERVED2_BITS 3 2567 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_BA1_RESERVED2_SHIFT 9 2568 2569 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_BA1 :: VDL_STEP [08:00] */ 2570 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_BA1_VDL_STEP_MASK 0x000001ff 2571 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_BA1_VDL_STEP_ALIGN 0 2572 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_BA1_VDL_STEP_BITS 9 2573 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_BA1_VDL_STEP_SHIFT 0 2574 2575 2576 /**************************************************************************** 2577 * DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_BA2 2578 */ 2579 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_BA2 :: BUSY [31:31] */ 2580 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_BA2_BUSY_MASK 0x80000000 2581 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_BA2_BUSY_ALIGN 0 2582 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_BA2_BUSY_BITS 1 2583 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_BA2_BUSY_SHIFT 31 2584 2585 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_BA2 :: reserved0 [30:17] */ 2586 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_BA2_RESERVED0_MASK 0x7ffe0000 2587 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_BA2_RESERVED0_ALIGN 0 2588 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_BA2_RESERVED0_BITS 14 2589 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_BA2_RESERVED0_SHIFT 17 2590 2591 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_BA2 :: FORCE [16:16] */ 2592 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_BA2_FORCE_MASK 0x00010000 2593 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_BA2_FORCE_ALIGN 0 2594 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_BA2_FORCE_BITS 1 2595 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_BA2_FORCE_SHIFT 16 2596 2597 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_BA2 :: reserved1 [15:13] */ 2598 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_BA2_RESERVED1_MASK 0x0000e000 2599 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_BA2_RESERVED1_ALIGN 0 2600 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_BA2_RESERVED1_BITS 3 2601 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_BA2_RESERVED1_SHIFT 13 2602 2603 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_BA2 :: ADJ_EN [12:12] */ 2604 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_BA2_ADJ_EN_MASK 0x00001000 2605 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_BA2_ADJ_EN_ALIGN 0 2606 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_BA2_ADJ_EN_BITS 1 2607 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_BA2_ADJ_EN_SHIFT 12 2608 2609 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_BA2 :: reserved2 [11:09] */ 2610 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_BA2_RESERVED2_MASK 0x00000e00 2611 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_BA2_RESERVED2_ALIGN 0 2612 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_BA2_RESERVED2_BITS 3 2613 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_BA2_RESERVED2_SHIFT 9 2614 2615 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_BA2 :: VDL_STEP [08:00] */ 2616 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_BA2_VDL_STEP_MASK 0x000001ff 2617 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_BA2_VDL_STEP_ALIGN 0 2618 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_BA2_VDL_STEP_BITS 9 2619 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_BA2_VDL_STEP_SHIFT 0 2620 2621 2622 /**************************************************************************** 2623 * DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AUX0 2624 */ 2625 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AUX0 :: BUSY [31:31] */ 2626 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AUX0_BUSY_MASK 0x80000000 2627 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AUX0_BUSY_ALIGN 0 2628 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AUX0_BUSY_BITS 1 2629 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AUX0_BUSY_SHIFT 31 2630 2631 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AUX0 :: reserved0 [30:17] */ 2632 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AUX0_RESERVED0_MASK 0x7ffe0000 2633 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AUX0_RESERVED0_ALIGN 0 2634 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AUX0_RESERVED0_BITS 14 2635 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AUX0_RESERVED0_SHIFT 17 2636 2637 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AUX0 :: FORCE [16:16] */ 2638 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AUX0_FORCE_MASK 0x00010000 2639 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AUX0_FORCE_ALIGN 0 2640 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AUX0_FORCE_BITS 1 2641 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AUX0_FORCE_SHIFT 16 2642 2643 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AUX0 :: reserved1 [15:13] */ 2644 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AUX0_RESERVED1_MASK 0x0000e000 2645 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AUX0_RESERVED1_ALIGN 0 2646 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AUX0_RESERVED1_BITS 3 2647 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AUX0_RESERVED1_SHIFT 13 2648 2649 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AUX0 :: ADJ_EN [12:12] */ 2650 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AUX0_ADJ_EN_MASK 0x00001000 2651 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AUX0_ADJ_EN_ALIGN 0 2652 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AUX0_ADJ_EN_BITS 1 2653 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AUX0_ADJ_EN_SHIFT 12 2654 2655 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AUX0 :: reserved2 [11:09] */ 2656 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AUX0_RESERVED2_MASK 0x00000e00 2657 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AUX0_RESERVED2_ALIGN 0 2658 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AUX0_RESERVED2_BITS 3 2659 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AUX0_RESERVED2_SHIFT 9 2660 2661 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AUX0 :: VDL_STEP [08:00] */ 2662 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AUX0_VDL_STEP_MASK 0x000001ff 2663 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AUX0_VDL_STEP_ALIGN 0 2664 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AUX0_VDL_STEP_BITS 9 2665 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AUX0_VDL_STEP_SHIFT 0 2666 2667 2668 /**************************************************************************** 2669 * DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AUX1 2670 */ 2671 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AUX1 :: BUSY [31:31] */ 2672 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AUX1_BUSY_MASK 0x80000000 2673 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AUX1_BUSY_ALIGN 0 2674 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AUX1_BUSY_BITS 1 2675 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AUX1_BUSY_SHIFT 31 2676 2677 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AUX1 :: reserved0 [30:17] */ 2678 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AUX1_RESERVED0_MASK 0x7ffe0000 2679 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AUX1_RESERVED0_ALIGN 0 2680 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AUX1_RESERVED0_BITS 14 2681 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AUX1_RESERVED0_SHIFT 17 2682 2683 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AUX1 :: FORCE [16:16] */ 2684 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AUX1_FORCE_MASK 0x00010000 2685 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AUX1_FORCE_ALIGN 0 2686 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AUX1_FORCE_BITS 1 2687 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AUX1_FORCE_SHIFT 16 2688 2689 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AUX1 :: reserved1 [15:13] */ 2690 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AUX1_RESERVED1_MASK 0x0000e000 2691 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AUX1_RESERVED1_ALIGN 0 2692 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AUX1_RESERVED1_BITS 3 2693 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AUX1_RESERVED1_SHIFT 13 2694 2695 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AUX1 :: ADJ_EN [12:12] */ 2696 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AUX1_ADJ_EN_MASK 0x00001000 2697 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AUX1_ADJ_EN_ALIGN 0 2698 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AUX1_ADJ_EN_BITS 1 2699 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AUX1_ADJ_EN_SHIFT 12 2700 2701 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AUX1 :: reserved2 [11:09] */ 2702 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AUX1_RESERVED2_MASK 0x00000e00 2703 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AUX1_RESERVED2_ALIGN 0 2704 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AUX1_RESERVED2_BITS 3 2705 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AUX1_RESERVED2_SHIFT 9 2706 2707 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AUX1 :: VDL_STEP [08:00] */ 2708 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AUX1_VDL_STEP_MASK 0x000001ff 2709 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AUX1_VDL_STEP_ALIGN 0 2710 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AUX1_VDL_STEP_BITS 9 2711 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AUX1_VDL_STEP_SHIFT 0 2712 2713 2714 /**************************************************************************** 2715 * DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AUX2 2716 */ 2717 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AUX2 :: BUSY [31:31] */ 2718 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AUX2_BUSY_MASK 0x80000000 2719 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AUX2_BUSY_ALIGN 0 2720 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AUX2_BUSY_BITS 1 2721 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AUX2_BUSY_SHIFT 31 2722 2723 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AUX2 :: reserved0 [30:17] */ 2724 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AUX2_RESERVED0_MASK 0x7ffe0000 2725 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AUX2_RESERVED0_ALIGN 0 2726 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AUX2_RESERVED0_BITS 14 2727 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AUX2_RESERVED0_SHIFT 17 2728 2729 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AUX2 :: FORCE [16:16] */ 2730 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AUX2_FORCE_MASK 0x00010000 2731 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AUX2_FORCE_ALIGN 0 2732 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AUX2_FORCE_BITS 1 2733 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AUX2_FORCE_SHIFT 16 2734 2735 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AUX2 :: reserved1 [15:13] */ 2736 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AUX2_RESERVED1_MASK 0x0000e000 2737 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AUX2_RESERVED1_ALIGN 0 2738 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AUX2_RESERVED1_BITS 3 2739 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AUX2_RESERVED1_SHIFT 13 2740 2741 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AUX2 :: ADJ_EN [12:12] */ 2742 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AUX2_ADJ_EN_MASK 0x00001000 2743 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AUX2_ADJ_EN_ALIGN 0 2744 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AUX2_ADJ_EN_BITS 1 2745 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AUX2_ADJ_EN_SHIFT 12 2746 2747 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AUX2 :: reserved2 [11:09] */ 2748 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AUX2_RESERVED2_MASK 0x00000e00 2749 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AUX2_RESERVED2_ALIGN 0 2750 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AUX2_RESERVED2_BITS 3 2751 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AUX2_RESERVED2_SHIFT 9 2752 2753 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_AUX2 :: VDL_STEP [08:00] */ 2754 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AUX2_VDL_STEP_MASK 0x000001ff 2755 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AUX2_VDL_STEP_ALIGN 0 2756 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AUX2_VDL_STEP_BITS 9 2757 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AUX2_VDL_STEP_SHIFT 0 2758 2759 2760 /**************************************************************************** 2761 * DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_CS0 2762 */ 2763 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_CS0 :: BUSY [31:31] */ 2764 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_CS0_BUSY_MASK 0x80000000 2765 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_CS0_BUSY_ALIGN 0 2766 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_CS0_BUSY_BITS 1 2767 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_CS0_BUSY_SHIFT 31 2768 2769 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_CS0 :: reserved0 [30:17] */ 2770 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_CS0_RESERVED0_MASK 0x7ffe0000 2771 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_CS0_RESERVED0_ALIGN 0 2772 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_CS0_RESERVED0_BITS 14 2773 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_CS0_RESERVED0_SHIFT 17 2774 2775 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_CS0 :: FORCE [16:16] */ 2776 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_CS0_FORCE_MASK 0x00010000 2777 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_CS0_FORCE_ALIGN 0 2778 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_CS0_FORCE_BITS 1 2779 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_CS0_FORCE_SHIFT 16 2780 2781 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_CS0 :: reserved1 [15:13] */ 2782 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_CS0_RESERVED1_MASK 0x0000e000 2783 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_CS0_RESERVED1_ALIGN 0 2784 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_CS0_RESERVED1_BITS 3 2785 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_CS0_RESERVED1_SHIFT 13 2786 2787 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_CS0 :: ADJ_EN [12:12] */ 2788 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_CS0_ADJ_EN_MASK 0x00001000 2789 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_CS0_ADJ_EN_ALIGN 0 2790 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_CS0_ADJ_EN_BITS 1 2791 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_CS0_ADJ_EN_SHIFT 12 2792 2793 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_CS0 :: reserved2 [11:09] */ 2794 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_CS0_RESERVED2_MASK 0x00000e00 2795 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_CS0_RESERVED2_ALIGN 0 2796 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_CS0_RESERVED2_BITS 3 2797 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_CS0_RESERVED2_SHIFT 9 2798 2799 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_CS0 :: VDL_STEP [08:00] */ 2800 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_CS0_VDL_STEP_MASK 0x000001ff 2801 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_CS0_VDL_STEP_ALIGN 0 2802 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_CS0_VDL_STEP_BITS 9 2803 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_CS0_VDL_STEP_SHIFT 0 2804 2805 2806 /**************************************************************************** 2807 * DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_CS1 2808 */ 2809 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_CS1 :: BUSY [31:31] */ 2810 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_CS1_BUSY_MASK 0x80000000 2811 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_CS1_BUSY_ALIGN 0 2812 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_CS1_BUSY_BITS 1 2813 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_CS1_BUSY_SHIFT 31 2814 2815 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_CS1 :: reserved0 [30:17] */ 2816 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_CS1_RESERVED0_MASK 0x7ffe0000 2817 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_CS1_RESERVED0_ALIGN 0 2818 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_CS1_RESERVED0_BITS 14 2819 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_CS1_RESERVED0_SHIFT 17 2820 2821 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_CS1 :: FORCE [16:16] */ 2822 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_CS1_FORCE_MASK 0x00010000 2823 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_CS1_FORCE_ALIGN 0 2824 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_CS1_FORCE_BITS 1 2825 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_CS1_FORCE_SHIFT 16 2826 2827 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_CS1 :: reserved1 [15:13] */ 2828 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_CS1_RESERVED1_MASK 0x0000e000 2829 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_CS1_RESERVED1_ALIGN 0 2830 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_CS1_RESERVED1_BITS 3 2831 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_CS1_RESERVED1_SHIFT 13 2832 2833 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_CS1 :: ADJ_EN [12:12] */ 2834 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_CS1_ADJ_EN_MASK 0x00001000 2835 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_CS1_ADJ_EN_ALIGN 0 2836 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_CS1_ADJ_EN_BITS 1 2837 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_CS1_ADJ_EN_SHIFT 12 2838 2839 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_CS1 :: reserved2 [11:09] */ 2840 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_CS1_RESERVED2_MASK 0x00000e00 2841 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_CS1_RESERVED2_ALIGN 0 2842 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_CS1_RESERVED2_BITS 3 2843 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_CS1_RESERVED2_SHIFT 9 2844 2845 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_CS1 :: VDL_STEP [08:00] */ 2846 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_CS1_VDL_STEP_MASK 0x000001ff 2847 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_CS1_VDL_STEP_ALIGN 0 2848 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_CS1_VDL_STEP_BITS 9 2849 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_CS1_VDL_STEP_SHIFT 0 2850 2851 2852 /**************************************************************************** 2853 * DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_PAR 2854 */ 2855 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_PAR :: BUSY [31:31] */ 2856 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_PAR_BUSY_MASK 0x80000000 2857 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_PAR_BUSY_ALIGN 0 2858 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_PAR_BUSY_BITS 1 2859 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_PAR_BUSY_SHIFT 31 2860 2861 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_PAR :: reserved0 [30:17] */ 2862 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_PAR_RESERVED0_MASK 0x7ffe0000 2863 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_PAR_RESERVED0_ALIGN 0 2864 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_PAR_RESERVED0_BITS 14 2865 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_PAR_RESERVED0_SHIFT 17 2866 2867 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_PAR :: FORCE [16:16] */ 2868 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_PAR_FORCE_MASK 0x00010000 2869 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_PAR_FORCE_ALIGN 0 2870 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_PAR_FORCE_BITS 1 2871 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_PAR_FORCE_SHIFT 16 2872 2873 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_PAR :: reserved1 [15:13] */ 2874 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_PAR_RESERVED1_MASK 0x0000e000 2875 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_PAR_RESERVED1_ALIGN 0 2876 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_PAR_RESERVED1_BITS 3 2877 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_PAR_RESERVED1_SHIFT 13 2878 2879 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_PAR :: ADJ_EN [12:12] */ 2880 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_PAR_ADJ_EN_MASK 0x00001000 2881 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_PAR_ADJ_EN_ALIGN 0 2882 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_PAR_ADJ_EN_BITS 1 2883 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_PAR_ADJ_EN_SHIFT 12 2884 2885 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_PAR :: reserved2 [11:09] */ 2886 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_PAR_RESERVED2_MASK 0x00000e00 2887 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_PAR_RESERVED2_ALIGN 0 2888 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_PAR_RESERVED2_BITS 3 2889 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_PAR_RESERVED2_SHIFT 9 2890 2891 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_PAR :: VDL_STEP [08:00] */ 2892 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_PAR_VDL_STEP_MASK 0x000001ff 2893 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_PAR_VDL_STEP_ALIGN 0 2894 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_PAR_VDL_STEP_BITS 9 2895 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_PAR_VDL_STEP_SHIFT 0 2896 2897 2898 /**************************************************************************** 2899 * DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_RAS_N 2900 */ 2901 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_RAS_N :: BUSY [31:31] */ 2902 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_RAS_N_BUSY_MASK 0x80000000 2903 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_RAS_N_BUSY_ALIGN 0 2904 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_RAS_N_BUSY_BITS 1 2905 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_RAS_N_BUSY_SHIFT 31 2906 2907 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_RAS_N :: reserved0 [30:17] */ 2908 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_RAS_N_RESERVED0_MASK 0x7ffe0000 2909 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_RAS_N_RESERVED0_ALIGN 0 2910 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_RAS_N_RESERVED0_BITS 14 2911 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_RAS_N_RESERVED0_SHIFT 17 2912 2913 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_RAS_N :: FORCE [16:16] */ 2914 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_RAS_N_FORCE_MASK 0x00010000 2915 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_RAS_N_FORCE_ALIGN 0 2916 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_RAS_N_FORCE_BITS 1 2917 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_RAS_N_FORCE_SHIFT 16 2918 2919 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_RAS_N :: reserved1 [15:13] */ 2920 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_RAS_N_RESERVED1_MASK 0x0000e000 2921 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_RAS_N_RESERVED1_ALIGN 0 2922 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_RAS_N_RESERVED1_BITS 3 2923 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_RAS_N_RESERVED1_SHIFT 13 2924 2925 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_RAS_N :: ADJ_EN [12:12] */ 2926 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_RAS_N_ADJ_EN_MASK 0x00001000 2927 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_RAS_N_ADJ_EN_ALIGN 0 2928 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_RAS_N_ADJ_EN_BITS 1 2929 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_RAS_N_ADJ_EN_SHIFT 12 2930 2931 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_RAS_N :: reserved2 [11:09] */ 2932 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_RAS_N_RESERVED2_MASK 0x00000e00 2933 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_RAS_N_RESERVED2_ALIGN 0 2934 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_RAS_N_RESERVED2_BITS 3 2935 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_RAS_N_RESERVED2_SHIFT 9 2936 2937 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_RAS_N :: VDL_STEP [08:00] */ 2938 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_RAS_N_VDL_STEP_MASK 0x000001ff 2939 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_RAS_N_VDL_STEP_ALIGN 0 2940 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_RAS_N_VDL_STEP_BITS 9 2941 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_RAS_N_VDL_STEP_SHIFT 0 2942 2943 2944 /**************************************************************************** 2945 * DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_CAS_N 2946 */ 2947 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_CAS_N :: BUSY [31:31] */ 2948 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_CAS_N_BUSY_MASK 0x80000000 2949 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_CAS_N_BUSY_ALIGN 0 2950 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_CAS_N_BUSY_BITS 1 2951 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_CAS_N_BUSY_SHIFT 31 2952 2953 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_CAS_N :: reserved0 [30:17] */ 2954 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_CAS_N_RESERVED0_MASK 0x7ffe0000 2955 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_CAS_N_RESERVED0_ALIGN 0 2956 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_CAS_N_RESERVED0_BITS 14 2957 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_CAS_N_RESERVED0_SHIFT 17 2958 2959 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_CAS_N :: FORCE [16:16] */ 2960 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_CAS_N_FORCE_MASK 0x00010000 2961 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_CAS_N_FORCE_ALIGN 0 2962 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_CAS_N_FORCE_BITS 1 2963 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_CAS_N_FORCE_SHIFT 16 2964 2965 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_CAS_N :: reserved1 [15:13] */ 2966 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_CAS_N_RESERVED1_MASK 0x0000e000 2967 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_CAS_N_RESERVED1_ALIGN 0 2968 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_CAS_N_RESERVED1_BITS 3 2969 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_CAS_N_RESERVED1_SHIFT 13 2970 2971 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_CAS_N :: ADJ_EN [12:12] */ 2972 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_CAS_N_ADJ_EN_MASK 0x00001000 2973 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_CAS_N_ADJ_EN_ALIGN 0 2974 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_CAS_N_ADJ_EN_BITS 1 2975 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_CAS_N_ADJ_EN_SHIFT 12 2976 2977 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_CAS_N :: reserved2 [11:09] */ 2978 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_CAS_N_RESERVED2_MASK 0x00000e00 2979 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_CAS_N_RESERVED2_ALIGN 0 2980 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_CAS_N_RESERVED2_BITS 3 2981 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_CAS_N_RESERVED2_SHIFT 9 2982 2983 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_CAS_N :: VDL_STEP [08:00] */ 2984 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_CAS_N_VDL_STEP_MASK 0x000001ff 2985 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_CAS_N_VDL_STEP_ALIGN 0 2986 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_CAS_N_VDL_STEP_BITS 9 2987 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_CAS_N_VDL_STEP_SHIFT 0 2988 2989 2990 /**************************************************************************** 2991 * DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_CKE 2992 */ 2993 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_CKE :: BUSY [31:31] */ 2994 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_CKE_BUSY_MASK 0x80000000 2995 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_CKE_BUSY_ALIGN 0 2996 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_CKE_BUSY_BITS 1 2997 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_CKE_BUSY_SHIFT 31 2998 2999 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_CKE :: reserved0 [30:17] */ 3000 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_CKE_RESERVED0_MASK 0x7ffe0000 3001 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_CKE_RESERVED0_ALIGN 0 3002 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_CKE_RESERVED0_BITS 14 3003 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_CKE_RESERVED0_SHIFT 17 3004 3005 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_CKE :: FORCE [16:16] */ 3006 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_CKE_FORCE_MASK 0x00010000 3007 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_CKE_FORCE_ALIGN 0 3008 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_CKE_FORCE_BITS 1 3009 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_CKE_FORCE_SHIFT 16 3010 3011 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_CKE :: reserved1 [15:13] */ 3012 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_CKE_RESERVED1_MASK 0x0000e000 3013 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_CKE_RESERVED1_ALIGN 0 3014 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_CKE_RESERVED1_BITS 3 3015 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_CKE_RESERVED1_SHIFT 13 3016 3017 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_CKE :: ADJ_EN [12:12] */ 3018 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_CKE_ADJ_EN_MASK 0x00001000 3019 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_CKE_ADJ_EN_ALIGN 0 3020 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_CKE_ADJ_EN_BITS 1 3021 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_CKE_ADJ_EN_SHIFT 12 3022 3023 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_CKE :: reserved2 [11:09] */ 3024 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_CKE_RESERVED2_MASK 0x00000e00 3025 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_CKE_RESERVED2_ALIGN 0 3026 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_CKE_RESERVED2_BITS 3 3027 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_CKE_RESERVED2_SHIFT 9 3028 3029 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_CKE :: VDL_STEP [08:00] */ 3030 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_CKE_VDL_STEP_MASK 0x000001ff 3031 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_CKE_VDL_STEP_ALIGN 0 3032 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_CKE_VDL_STEP_BITS 9 3033 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_CKE_VDL_STEP_SHIFT 0 3034 3035 3036 /**************************************************************************** 3037 * DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_RST_N 3038 */ 3039 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_RST_N :: BUSY [31:31] */ 3040 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_RST_N_BUSY_MASK 0x80000000 3041 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_RST_N_BUSY_ALIGN 0 3042 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_RST_N_BUSY_BITS 1 3043 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_RST_N_BUSY_SHIFT 31 3044 3045 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_RST_N :: reserved0 [30:17] */ 3046 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_RST_N_RESERVED0_MASK 0x7ffe0000 3047 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_RST_N_RESERVED0_ALIGN 0 3048 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_RST_N_RESERVED0_BITS 14 3049 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_RST_N_RESERVED0_SHIFT 17 3050 3051 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_RST_N :: FORCE [16:16] */ 3052 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_RST_N_FORCE_MASK 0x00010000 3053 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_RST_N_FORCE_ALIGN 0 3054 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_RST_N_FORCE_BITS 1 3055 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_RST_N_FORCE_SHIFT 16 3056 3057 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_RST_N :: reserved1 [15:13] */ 3058 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_RST_N_RESERVED1_MASK 0x0000e000 3059 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_RST_N_RESERVED1_ALIGN 0 3060 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_RST_N_RESERVED1_BITS 3 3061 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_RST_N_RESERVED1_SHIFT 13 3062 3063 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_RST_N :: ADJ_EN [12:12] */ 3064 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_RST_N_ADJ_EN_MASK 0x00001000 3065 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_RST_N_ADJ_EN_ALIGN 0 3066 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_RST_N_ADJ_EN_BITS 1 3067 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_RST_N_ADJ_EN_SHIFT 12 3068 3069 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_RST_N :: reserved2 [11:09] */ 3070 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_RST_N_RESERVED2_MASK 0x00000e00 3071 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_RST_N_RESERVED2_ALIGN 0 3072 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_RST_N_RESERVED2_BITS 3 3073 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_RST_N_RESERVED2_SHIFT 9 3074 3075 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_RST_N :: VDL_STEP [08:00] */ 3076 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_RST_N_VDL_STEP_MASK 0x000001ff 3077 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_RST_N_VDL_STEP_ALIGN 0 3078 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_RST_N_VDL_STEP_BITS 9 3079 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_RST_N_VDL_STEP_SHIFT 0 3080 3081 3082 /**************************************************************************** 3083 * DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_ODT 3084 */ 3085 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_ODT :: BUSY [31:31] */ 3086 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_ODT_BUSY_MASK 0x80000000 3087 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_ODT_BUSY_ALIGN 0 3088 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_ODT_BUSY_BITS 1 3089 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_ODT_BUSY_SHIFT 31 3090 3091 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_ODT :: reserved0 [30:17] */ 3092 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_ODT_RESERVED0_MASK 0x7ffe0000 3093 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_ODT_RESERVED0_ALIGN 0 3094 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_ODT_RESERVED0_BITS 14 3095 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_ODT_RESERVED0_SHIFT 17 3096 3097 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_ODT :: FORCE [16:16] */ 3098 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_ODT_FORCE_MASK 0x00010000 3099 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_ODT_FORCE_ALIGN 0 3100 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_ODT_FORCE_BITS 1 3101 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_ODT_FORCE_SHIFT 16 3102 3103 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_ODT :: reserved1 [15:13] */ 3104 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_ODT_RESERVED1_MASK 0x0000e000 3105 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_ODT_RESERVED1_ALIGN 0 3106 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_ODT_RESERVED1_BITS 3 3107 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_ODT_RESERVED1_SHIFT 13 3108 3109 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_ODT :: ADJ_EN [12:12] */ 3110 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_ODT_ADJ_EN_MASK 0x00001000 3111 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_ODT_ADJ_EN_ALIGN 0 3112 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_ODT_ADJ_EN_BITS 1 3113 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_ODT_ADJ_EN_SHIFT 12 3114 3115 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_ODT :: reserved2 [11:09] */ 3116 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_ODT_RESERVED2_MASK 0x00000e00 3117 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_ODT_RESERVED2_ALIGN 0 3118 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_ODT_RESERVED2_BITS 3 3119 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_ODT_RESERVED2_SHIFT 9 3120 3121 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_ODT :: VDL_STEP [08:00] */ 3122 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_ODT_VDL_STEP_MASK 0x000001ff 3123 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_ODT_VDL_STEP_ALIGN 0 3124 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_ODT_VDL_STEP_BITS 9 3125 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_ODT_VDL_STEP_SHIFT 0 3126 3127 3128 /**************************************************************************** 3129 * DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_WE_N 3130 */ 3131 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_WE_N :: BUSY [31:31] */ 3132 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_WE_N_BUSY_MASK 0x80000000 3133 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_WE_N_BUSY_ALIGN 0 3134 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_WE_N_BUSY_BITS 1 3135 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_WE_N_BUSY_SHIFT 31 3136 3137 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_WE_N :: reserved0 [30:17] */ 3138 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_WE_N_RESERVED0_MASK 0x7ffe0000 3139 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_WE_N_RESERVED0_ALIGN 0 3140 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_WE_N_RESERVED0_BITS 14 3141 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_WE_N_RESERVED0_SHIFT 17 3142 3143 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_WE_N :: FORCE [16:16] */ 3144 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_WE_N_FORCE_MASK 0x00010000 3145 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_WE_N_FORCE_ALIGN 0 3146 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_WE_N_FORCE_BITS 1 3147 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_WE_N_FORCE_SHIFT 16 3148 3149 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_WE_N :: reserved1 [15:13] */ 3150 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_WE_N_RESERVED1_MASK 0x0000e000 3151 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_WE_N_RESERVED1_ALIGN 0 3152 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_WE_N_RESERVED1_BITS 3 3153 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_WE_N_RESERVED1_SHIFT 13 3154 3155 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_WE_N :: ADJ_EN [12:12] */ 3156 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_WE_N_ADJ_EN_MASK 0x00001000 3157 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_WE_N_ADJ_EN_ALIGN 0 3158 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_WE_N_ADJ_EN_BITS 1 3159 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_WE_N_ADJ_EN_SHIFT 12 3160 3161 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_WE_N :: reserved2 [11:09] */ 3162 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_WE_N_RESERVED2_MASK 0x00000e00 3163 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_WE_N_RESERVED2_ALIGN 0 3164 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_WE_N_RESERVED2_BITS 3 3165 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_WE_N_RESERVED2_SHIFT 9 3166 3167 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_WE_N :: VDL_STEP [08:00] */ 3168 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_WE_N_VDL_STEP_MASK 0x000001ff 3169 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_WE_N_VDL_STEP_ALIGN 0 3170 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_WE_N_VDL_STEP_BITS 9 3171 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_WE_N_VDL_STEP_SHIFT 0 3172 3173 3174 /**************************************************************************** 3175 * DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_DDR_CK 3176 */ 3177 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_DDR_CK :: BUSY [31:31] */ 3178 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_BUSY_MASK 0x80000000 3179 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_BUSY_ALIGN 0 3180 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_BUSY_BITS 1 3181 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_BUSY_SHIFT 31 3182 3183 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_DDR_CK :: reserved0 [30:17] */ 3184 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_RESERVED0_MASK 0x7ffe0000 3185 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_RESERVED0_ALIGN 0 3186 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_RESERVED0_BITS 14 3187 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_RESERVED0_SHIFT 17 3188 3189 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_DDR_CK :: FORCE [16:16] */ 3190 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_FORCE_MASK 0x00010000 3191 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_FORCE_ALIGN 0 3192 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_FORCE_BITS 1 3193 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_FORCE_SHIFT 16 3194 3195 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_DDR_CK :: reserved1 [15:13] */ 3196 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_RESERVED1_MASK 0x0000e000 3197 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_RESERVED1_ALIGN 0 3198 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_RESERVED1_BITS 3 3199 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_RESERVED1_SHIFT 13 3200 3201 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_DDR_CK :: ADJ_EN [12:12] */ 3202 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_ADJ_EN_MASK 0x00001000 3203 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_ADJ_EN_ALIGN 0 3204 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_ADJ_EN_BITS 1 3205 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_ADJ_EN_SHIFT 12 3206 3207 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_DDR_CK :: reserved2 [11:09] */ 3208 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_RESERVED2_MASK 0x00000e00 3209 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_RESERVED2_ALIGN 0 3210 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_RESERVED2_BITS 3 3211 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_RESERVED2_SHIFT 9 3212 3213 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CONTROL_DDR_CK :: VDL_STEP [08:00] */ 3214 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_VDL_STEP_MASK 0x000001ff 3215 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_VDL_STEP_ALIGN 0 3216 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_VDL_STEP_BITS 9 3217 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_VDL_STEP_SHIFT 0 3218 3219 3220 /**************************************************************************** 3221 * DDR34_F0_PHY_CONTROL_REGS :: VDL_CLK_CONTROL 3222 */ 3223 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CLK_CONTROL :: BUSY [31:31] */ 3224 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CLK_CONTROL_BUSY_MASK 0x80000000 3225 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CLK_CONTROL_BUSY_ALIGN 0 3226 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CLK_CONTROL_BUSY_BITS 1 3227 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CLK_CONTROL_BUSY_SHIFT 31 3228 3229 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CLK_CONTROL :: reserved0 [30:17] */ 3230 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CLK_CONTROL_RESERVED0_MASK 0x7ffe0000 3231 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CLK_CONTROL_RESERVED0_ALIGN 0 3232 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CLK_CONTROL_RESERVED0_BITS 14 3233 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CLK_CONTROL_RESERVED0_SHIFT 17 3234 3235 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CLK_CONTROL :: FORCE [16:16] */ 3236 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CLK_CONTROL_FORCE_MASK 0x00010000 3237 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CLK_CONTROL_FORCE_ALIGN 0 3238 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CLK_CONTROL_FORCE_BITS 1 3239 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CLK_CONTROL_FORCE_SHIFT 16 3240 3241 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CLK_CONTROL :: reserved1 [15:13] */ 3242 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CLK_CONTROL_RESERVED1_MASK 0x0000e000 3243 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CLK_CONTROL_RESERVED1_ALIGN 0 3244 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CLK_CONTROL_RESERVED1_BITS 3 3245 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CLK_CONTROL_RESERVED1_SHIFT 13 3246 3247 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CLK_CONTROL :: ADJ_EN [12:12] */ 3248 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CLK_CONTROL_ADJ_EN_MASK 0x00001000 3249 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CLK_CONTROL_ADJ_EN_ALIGN 0 3250 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CLK_CONTROL_ADJ_EN_BITS 1 3251 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CLK_CONTROL_ADJ_EN_SHIFT 12 3252 3253 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CLK_CONTROL :: reserved2 [11:09] */ 3254 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CLK_CONTROL_RESERVED2_MASK 0x00000e00 3255 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CLK_CONTROL_RESERVED2_ALIGN 0 3256 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CLK_CONTROL_RESERVED2_BITS 3 3257 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CLK_CONTROL_RESERVED2_SHIFT 9 3258 3259 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_CLK_CONTROL :: VDL_STEP [08:00] */ 3260 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CLK_CONTROL_VDL_STEP_MASK 0x000001ff 3261 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CLK_CONTROL_VDL_STEP_ALIGN 0 3262 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CLK_CONTROL_VDL_STEP_BITS 9 3263 #define DDR34_F0_PHY_CONTROL_REGS_VDL_CLK_CONTROL_VDL_STEP_SHIFT 0 3264 3265 3266 /**************************************************************************** 3267 * DDR34_F0_PHY_CONTROL_REGS :: VDL_LDE_CONTROL 3268 */ 3269 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_LDE_CONTROL :: BUSY [31:31] */ 3270 #define DDR34_F0_PHY_CONTROL_REGS_VDL_LDE_CONTROL_BUSY_MASK 0x80000000 3271 #define DDR34_F0_PHY_CONTROL_REGS_VDL_LDE_CONTROL_BUSY_ALIGN 0 3272 #define DDR34_F0_PHY_CONTROL_REGS_VDL_LDE_CONTROL_BUSY_BITS 1 3273 #define DDR34_F0_PHY_CONTROL_REGS_VDL_LDE_CONTROL_BUSY_SHIFT 31 3274 3275 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_LDE_CONTROL :: reserved0 [30:17] */ 3276 #define DDR34_F0_PHY_CONTROL_REGS_VDL_LDE_CONTROL_RESERVED0_MASK 0x7ffe0000 3277 #define DDR34_F0_PHY_CONTROL_REGS_VDL_LDE_CONTROL_RESERVED0_ALIGN 0 3278 #define DDR34_F0_PHY_CONTROL_REGS_VDL_LDE_CONTROL_RESERVED0_BITS 14 3279 #define DDR34_F0_PHY_CONTROL_REGS_VDL_LDE_CONTROL_RESERVED0_SHIFT 17 3280 3281 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_LDE_CONTROL :: FORCE [16:16] */ 3282 #define DDR34_F0_PHY_CONTROL_REGS_VDL_LDE_CONTROL_FORCE_MASK 0x00010000 3283 #define DDR34_F0_PHY_CONTROL_REGS_VDL_LDE_CONTROL_FORCE_ALIGN 0 3284 #define DDR34_F0_PHY_CONTROL_REGS_VDL_LDE_CONTROL_FORCE_BITS 1 3285 #define DDR34_F0_PHY_CONTROL_REGS_VDL_LDE_CONTROL_FORCE_SHIFT 16 3286 3287 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_LDE_CONTROL :: reserved1 [15:13] */ 3288 #define DDR34_F0_PHY_CONTROL_REGS_VDL_LDE_CONTROL_RESERVED1_MASK 0x0000e000 3289 #define DDR34_F0_PHY_CONTROL_REGS_VDL_LDE_CONTROL_RESERVED1_ALIGN 0 3290 #define DDR34_F0_PHY_CONTROL_REGS_VDL_LDE_CONTROL_RESERVED1_BITS 3 3291 #define DDR34_F0_PHY_CONTROL_REGS_VDL_LDE_CONTROL_RESERVED1_SHIFT 13 3292 3293 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_LDE_CONTROL :: ADJ_EN [12:12] */ 3294 #define DDR34_F0_PHY_CONTROL_REGS_VDL_LDE_CONTROL_ADJ_EN_MASK 0x00001000 3295 #define DDR34_F0_PHY_CONTROL_REGS_VDL_LDE_CONTROL_ADJ_EN_ALIGN 0 3296 #define DDR34_F0_PHY_CONTROL_REGS_VDL_LDE_CONTROL_ADJ_EN_BITS 1 3297 #define DDR34_F0_PHY_CONTROL_REGS_VDL_LDE_CONTROL_ADJ_EN_SHIFT 12 3298 3299 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_LDE_CONTROL :: reserved2 [11:09] */ 3300 #define DDR34_F0_PHY_CONTROL_REGS_VDL_LDE_CONTROL_RESERVED2_MASK 0x00000e00 3301 #define DDR34_F0_PHY_CONTROL_REGS_VDL_LDE_CONTROL_RESERVED2_ALIGN 0 3302 #define DDR34_F0_PHY_CONTROL_REGS_VDL_LDE_CONTROL_RESERVED2_BITS 3 3303 #define DDR34_F0_PHY_CONTROL_REGS_VDL_LDE_CONTROL_RESERVED2_SHIFT 9 3304 3305 /* DDR34_F0_PHY_CONTROL_REGS :: VDL_LDE_CONTROL :: VDL_STEP [08:00] */ 3306 #define DDR34_F0_PHY_CONTROL_REGS_VDL_LDE_CONTROL_VDL_STEP_MASK 0x000001ff 3307 #define DDR34_F0_PHY_CONTROL_REGS_VDL_LDE_CONTROL_VDL_STEP_ALIGN 0 3308 #define DDR34_F0_PHY_CONTROL_REGS_VDL_LDE_CONTROL_VDL_STEP_BITS 9 3309 #define DDR34_F0_PHY_CONTROL_REGS_VDL_LDE_CONTROL_VDL_STEP_SHIFT 0 3310 3311 3312 /**************************************************************************** 3313 * DDR34_F0_PHY_CONTROL_REGS :: CMD_CYC_DLY 3314 */ 3315 /* DDR34_F0_PHY_CONTROL_REGS :: CMD_CYC_DLY :: reserved0 [31:06] */ 3316 #define DDR34_F0_PHY_CONTROL_REGS_CMD_CYC_DLY_RESERVED0_MASK 0xffffffc0 3317 #define DDR34_F0_PHY_CONTROL_REGS_CMD_CYC_DLY_RESERVED0_ALIGN 0 3318 #define DDR34_F0_PHY_CONTROL_REGS_CMD_CYC_DLY_RESERVED0_BITS 26 3319 #define DDR34_F0_PHY_CONTROL_REGS_CMD_CYC_DLY_RESERVED0_SHIFT 6 3320 3321 /* DDR34_F0_PHY_CONTROL_REGS :: CMD_CYC_DLY :: CKE [05:05] */ 3322 #define DDR34_F0_PHY_CONTROL_REGS_CMD_CYC_DLY_CKE_MASK 0x00000020 3323 #define DDR34_F0_PHY_CONTROL_REGS_CMD_CYC_DLY_CKE_ALIGN 0 3324 #define DDR34_F0_PHY_CONTROL_REGS_CMD_CYC_DLY_CKE_BITS 1 3325 #define DDR34_F0_PHY_CONTROL_REGS_CMD_CYC_DLY_CKE_SHIFT 5 3326 3327 /* DDR34_F0_PHY_CONTROL_REGS :: CMD_CYC_DLY :: WE_N [04:04] */ 3328 #define DDR34_F0_PHY_CONTROL_REGS_CMD_CYC_DLY_WE_N_MASK 0x00000010 3329 #define DDR34_F0_PHY_CONTROL_REGS_CMD_CYC_DLY_WE_N_ALIGN 0 3330 #define DDR34_F0_PHY_CONTROL_REGS_CMD_CYC_DLY_WE_N_BITS 1 3331 #define DDR34_F0_PHY_CONTROL_REGS_CMD_CYC_DLY_WE_N_SHIFT 4 3332 3333 /* DDR34_F0_PHY_CONTROL_REGS :: CMD_CYC_DLY :: CAS_N [03:03] */ 3334 #define DDR34_F0_PHY_CONTROL_REGS_CMD_CYC_DLY_CAS_N_MASK 0x00000008 3335 #define DDR34_F0_PHY_CONTROL_REGS_CMD_CYC_DLY_CAS_N_ALIGN 0 3336 #define DDR34_F0_PHY_CONTROL_REGS_CMD_CYC_DLY_CAS_N_BITS 1 3337 #define DDR34_F0_PHY_CONTROL_REGS_CMD_CYC_DLY_CAS_N_SHIFT 3 3338 3339 /* DDR34_F0_PHY_CONTROL_REGS :: CMD_CYC_DLY :: RAS_N [02:02] */ 3340 #define DDR34_F0_PHY_CONTROL_REGS_CMD_CYC_DLY_RAS_N_MASK 0x00000004 3341 #define DDR34_F0_PHY_CONTROL_REGS_CMD_CYC_DLY_RAS_N_ALIGN 0 3342 #define DDR34_F0_PHY_CONTROL_REGS_CMD_CYC_DLY_RAS_N_BITS 1 3343 #define DDR34_F0_PHY_CONTROL_REGS_CMD_CYC_DLY_RAS_N_SHIFT 2 3344 3345 /* DDR34_F0_PHY_CONTROL_REGS :: CMD_CYC_DLY :: CS_N [01:00] */ 3346 #define DDR34_F0_PHY_CONTROL_REGS_CMD_CYC_DLY_CS_N_MASK 0x00000003 3347 #define DDR34_F0_PHY_CONTROL_REGS_CMD_CYC_DLY_CS_N_ALIGN 0 3348 #define DDR34_F0_PHY_CONTROL_REGS_CMD_CYC_DLY_CS_N_BITS 2 3349 #define DDR34_F0_PHY_CONTROL_REGS_CMD_CYC_DLY_CS_N_SHIFT 0 3350 3351 3352 /**************************************************************************** 3353 * DDR34_F0_PHY_CONTROL_REGS :: UPDATE_VDL 3354 */ 3355 /* DDR34_F0_PHY_CONTROL_REGS :: UPDATE_VDL :: reserved0 [31:09] */ 3356 #define DDR34_F0_PHY_CONTROL_REGS_UPDATE_VDL_RESERVED0_MASK 0xfffffe00 3357 #define DDR34_F0_PHY_CONTROL_REGS_UPDATE_VDL_RESERVED0_ALIGN 0 3358 #define DDR34_F0_PHY_CONTROL_REGS_UPDATE_VDL_RESERVED0_BITS 23 3359 #define DDR34_F0_PHY_CONTROL_REGS_UPDATE_VDL_RESERVED0_SHIFT 9 3360 3361 /* DDR34_F0_PHY_CONTROL_REGS :: UPDATE_VDL :: MODE [08:04] */ 3362 #define DDR34_F0_PHY_CONTROL_REGS_UPDATE_VDL_MODE_MASK 0x000001f0 3363 #define DDR34_F0_PHY_CONTROL_REGS_UPDATE_VDL_MODE_ALIGN 0 3364 #define DDR34_F0_PHY_CONTROL_REGS_UPDATE_VDL_MODE_BITS 5 3365 #define DDR34_F0_PHY_CONTROL_REGS_UPDATE_VDL_MODE_SHIFT 4 3366 3367 /* DDR34_F0_PHY_CONTROL_REGS :: UPDATE_VDL :: reserved1 [03:02] */ 3368 #define DDR34_F0_PHY_CONTROL_REGS_UPDATE_VDL_RESERVED1_MASK 0x0000000c 3369 #define DDR34_F0_PHY_CONTROL_REGS_UPDATE_VDL_RESERVED1_ALIGN 0 3370 #define DDR34_F0_PHY_CONTROL_REGS_UPDATE_VDL_RESERVED1_BITS 2 3371 #define DDR34_F0_PHY_CONTROL_REGS_UPDATE_VDL_RESERVED1_SHIFT 2 3372 3373 /* DDR34_F0_PHY_CONTROL_REGS :: UPDATE_VDL :: DISABLE_INPUT [01:01] */ 3374 #define DDR34_F0_PHY_CONTROL_REGS_UPDATE_VDL_DISABLE_INPUT_MASK 0x00000002 3375 #define DDR34_F0_PHY_CONTROL_REGS_UPDATE_VDL_DISABLE_INPUT_ALIGN 0 3376 #define DDR34_F0_PHY_CONTROL_REGS_UPDATE_VDL_DISABLE_INPUT_BITS 1 3377 #define DDR34_F0_PHY_CONTROL_REGS_UPDATE_VDL_DISABLE_INPUT_SHIFT 1 3378 3379 /* DDR34_F0_PHY_CONTROL_REGS :: UPDATE_VDL :: ENABLE [00:00] */ 3380 #define DDR34_F0_PHY_CONTROL_REGS_UPDATE_VDL_ENABLE_MASK 0x00000001 3381 #define DDR34_F0_PHY_CONTROL_REGS_UPDATE_VDL_ENABLE_ALIGN 0 3382 #define DDR34_F0_PHY_CONTROL_REGS_UPDATE_VDL_ENABLE_BITS 1 3383 #define DDR34_F0_PHY_CONTROL_REGS_UPDATE_VDL_ENABLE_SHIFT 0 3384 3385 3386 /**************************************************************************** 3387 * DDR34_F0_PHY_CONTROL_REGS :: UPDATE_VDL_SNOOP1 3388 */ 3389 /* DDR34_F0_PHY_CONTROL_REGS :: UPDATE_VDL_SNOOP1 :: reserved0 [31:29] */ 3390 #define DDR34_F0_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1_RESERVED0_MASK 0xe0000000 3391 #define DDR34_F0_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1_RESERVED0_ALIGN 0 3392 #define DDR34_F0_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1_RESERVED0_BITS 3 3393 #define DDR34_F0_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1_RESERVED0_SHIFT 29 3394 3395 /* DDR34_F0_PHY_CONTROL_REGS :: UPDATE_VDL_SNOOP1 :: MASK [28:20] */ 3396 #define DDR34_F0_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1_MASK_MASK 0x1ff00000 3397 #define DDR34_F0_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1_MASK_ALIGN 0 3398 #define DDR34_F0_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1_MASK_BITS 9 3399 #define DDR34_F0_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1_MASK_SHIFT 20 3400 3401 /* DDR34_F0_PHY_CONTROL_REGS :: UPDATE_VDL_SNOOP1 :: reserved1 [19:17] */ 3402 #define DDR34_F0_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1_RESERVED1_MASK 0x000e0000 3403 #define DDR34_F0_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1_RESERVED1_ALIGN 0 3404 #define DDR34_F0_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1_RESERVED1_BITS 3 3405 #define DDR34_F0_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1_RESERVED1_SHIFT 17 3406 3407 /* DDR34_F0_PHY_CONTROL_REGS :: UPDATE_VDL_SNOOP1 :: CMD [16:08] */ 3408 #define DDR34_F0_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1_CMD_MASK 0x0001ff00 3409 #define DDR34_F0_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1_CMD_ALIGN 0 3410 #define DDR34_F0_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1_CMD_BITS 9 3411 #define DDR34_F0_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1_CMD_SHIFT 8 3412 3413 /* DDR34_F0_PHY_CONTROL_REGS :: UPDATE_VDL_SNOOP1 :: reserved2 [07:05] */ 3414 #define DDR34_F0_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1_RESERVED2_MASK 0x000000e0 3415 #define DDR34_F0_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1_RESERVED2_ALIGN 0 3416 #define DDR34_F0_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1_RESERVED2_BITS 3 3417 #define DDR34_F0_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1_RESERVED2_SHIFT 5 3418 3419 /* DDR34_F0_PHY_CONTROL_REGS :: UPDATE_VDL_SNOOP1 :: ENABLE [04:00] */ 3420 #define DDR34_F0_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1_ENABLE_MASK 0x0000001f 3421 #define DDR34_F0_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1_ENABLE_ALIGN 0 3422 #define DDR34_F0_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1_ENABLE_BITS 5 3423 #define DDR34_F0_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1_ENABLE_SHIFT 0 3424 3425 3426 /**************************************************************************** 3427 * DDR34_F0_PHY_CONTROL_REGS :: UPDATE_VDL_SNOOP2 3428 */ 3429 /* DDR34_F0_PHY_CONTROL_REGS :: UPDATE_VDL_SNOOP2 :: reserved0 [31:29] */ 3430 #define DDR34_F0_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2_RESERVED0_MASK 0xe0000000 3431 #define DDR34_F0_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2_RESERVED0_ALIGN 0 3432 #define DDR34_F0_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2_RESERVED0_BITS 3 3433 #define DDR34_F0_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2_RESERVED0_SHIFT 29 3434 3435 /* DDR34_F0_PHY_CONTROL_REGS :: UPDATE_VDL_SNOOP2 :: MASK [28:20] */ 3436 #define DDR34_F0_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2_MASK_MASK 0x1ff00000 3437 #define DDR34_F0_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2_MASK_ALIGN 0 3438 #define DDR34_F0_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2_MASK_BITS 9 3439 #define DDR34_F0_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2_MASK_SHIFT 20 3440 3441 /* DDR34_F0_PHY_CONTROL_REGS :: UPDATE_VDL_SNOOP2 :: reserved1 [19:17] */ 3442 #define DDR34_F0_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2_RESERVED1_MASK 0x000e0000 3443 #define DDR34_F0_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2_RESERVED1_ALIGN 0 3444 #define DDR34_F0_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2_RESERVED1_BITS 3 3445 #define DDR34_F0_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2_RESERVED1_SHIFT 17 3446 3447 /* DDR34_F0_PHY_CONTROL_REGS :: UPDATE_VDL_SNOOP2 :: CMD [16:08] */ 3448 #define DDR34_F0_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2_CMD_MASK 0x0001ff00 3449 #define DDR34_F0_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2_CMD_ALIGN 0 3450 #define DDR34_F0_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2_CMD_BITS 9 3451 #define DDR34_F0_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2_CMD_SHIFT 8 3452 3453 /* DDR34_F0_PHY_CONTROL_REGS :: UPDATE_VDL_SNOOP2 :: reserved2 [07:05] */ 3454 #define DDR34_F0_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2_RESERVED2_MASK 0x000000e0 3455 #define DDR34_F0_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2_RESERVED2_ALIGN 0 3456 #define DDR34_F0_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2_RESERVED2_BITS 3 3457 #define DDR34_F0_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2_RESERVED2_SHIFT 5 3458 3459 /* DDR34_F0_PHY_CONTROL_REGS :: UPDATE_VDL_SNOOP2 :: ENABLE [04:00] */ 3460 #define DDR34_F0_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2_ENABLE_MASK 0x0000001f 3461 #define DDR34_F0_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2_ENABLE_ALIGN 0 3462 #define DDR34_F0_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2_ENABLE_BITS 5 3463 #define DDR34_F0_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2_ENABLE_SHIFT 0 3464 3465 3466 /**************************************************************************** 3467 * DDR34_F0_PHY_CONTROL_REGS :: COMMAND_REG1 3468 */ 3469 /* DDR34_F0_PHY_CONTROL_REGS :: COMMAND_REG1 :: MCP [31:31] */ 3470 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG1_MCP_MASK 0x80000000 3471 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG1_MCP_ALIGN 0 3472 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG1_MCP_BITS 1 3473 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG1_MCP_SHIFT 31 3474 3475 /* DDR34_F0_PHY_CONTROL_REGS :: COMMAND_REG1 :: CS [30:29] */ 3476 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG1_CS_MASK 0x60000000 3477 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG1_CS_ALIGN 0 3478 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG1_CS_BITS 2 3479 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG1_CS_SHIFT 29 3480 3481 /* DDR34_F0_PHY_CONTROL_REGS :: COMMAND_REG1 :: AUX [28:24] */ 3482 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG1_AUX_MASK 0x1f000000 3483 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG1_AUX_ALIGN 0 3484 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG1_AUX_BITS 5 3485 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG1_AUX_SHIFT 24 3486 3487 /* DDR34_F0_PHY_CONTROL_REGS :: COMMAND_REG1 :: ACT [23:23] */ 3488 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG1_ACT_MASK 0x00800000 3489 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG1_ACT_ALIGN 0 3490 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG1_ACT_BITS 1 3491 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG1_ACT_SHIFT 23 3492 3493 /* DDR34_F0_PHY_CONTROL_REGS :: COMMAND_REG1 :: WE [22:22] */ 3494 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG1_WE_MASK 0x00400000 3495 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG1_WE_ALIGN 0 3496 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG1_WE_BITS 1 3497 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG1_WE_SHIFT 22 3498 3499 /* DDR34_F0_PHY_CONTROL_REGS :: COMMAND_REG1 :: CAS [21:21] */ 3500 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG1_CAS_MASK 0x00200000 3501 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG1_CAS_ALIGN 0 3502 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG1_CAS_BITS 1 3503 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG1_CAS_SHIFT 21 3504 3505 /* DDR34_F0_PHY_CONTROL_REGS :: COMMAND_REG1 :: RAS [20:20] */ 3506 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG1_RAS_MASK 0x00100000 3507 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG1_RAS_ALIGN 0 3508 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG1_RAS_BITS 1 3509 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG1_RAS_SHIFT 20 3510 3511 /* DDR34_F0_PHY_CONTROL_REGS :: COMMAND_REG1 :: BA [19:16] */ 3512 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG1_BA_MASK 0x000f0000 3513 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG1_BA_ALIGN 0 3514 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG1_BA_BITS 4 3515 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG1_BA_SHIFT 16 3516 3517 /* DDR34_F0_PHY_CONTROL_REGS :: COMMAND_REG1 :: AD [15:00] */ 3518 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG1_AD_MASK 0x0000ffff 3519 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG1_AD_ALIGN 0 3520 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG1_AD_BITS 16 3521 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG1_AD_SHIFT 0 3522 3523 3524 /**************************************************************************** 3525 * DDR34_F0_PHY_CONTROL_REGS :: COMMAND_AUX_REG1 3526 */ 3527 /* DDR34_F0_PHY_CONTROL_REGS :: COMMAND_AUX_REG1 :: reserved0 [31:01] */ 3528 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_AUX_REG1_RESERVED0_MASK 0xfffffffe 3529 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_AUX_REG1_RESERVED0_ALIGN 0 3530 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_AUX_REG1_RESERVED0_BITS 31 3531 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_AUX_REG1_RESERVED0_SHIFT 1 3532 3533 /* DDR34_F0_PHY_CONTROL_REGS :: COMMAND_AUX_REG1 :: AD16 [00:00] */ 3534 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_AUX_REG1_AD16_MASK 0x00000001 3535 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_AUX_REG1_AD16_ALIGN 0 3536 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_AUX_REG1_AD16_BITS 1 3537 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_AUX_REG1_AD16_SHIFT 0 3538 3539 3540 /**************************************************************************** 3541 * DDR34_F0_PHY_CONTROL_REGS :: COMMAND_REG2 3542 */ 3543 /* DDR34_F0_PHY_CONTROL_REGS :: COMMAND_REG2 :: MCP [31:31] */ 3544 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG2_MCP_MASK 0x80000000 3545 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG2_MCP_ALIGN 0 3546 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG2_MCP_BITS 1 3547 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG2_MCP_SHIFT 31 3548 3549 /* DDR34_F0_PHY_CONTROL_REGS :: COMMAND_REG2 :: CS [30:29] */ 3550 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG2_CS_MASK 0x60000000 3551 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG2_CS_ALIGN 0 3552 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG2_CS_BITS 2 3553 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG2_CS_SHIFT 29 3554 3555 /* DDR34_F0_PHY_CONTROL_REGS :: COMMAND_REG2 :: AUX [28:24] */ 3556 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG2_AUX_MASK 0x1f000000 3557 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG2_AUX_ALIGN 0 3558 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG2_AUX_BITS 5 3559 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG2_AUX_SHIFT 24 3560 3561 /* DDR34_F0_PHY_CONTROL_REGS :: COMMAND_REG2 :: ACT [23:23] */ 3562 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG2_ACT_MASK 0x00800000 3563 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG2_ACT_ALIGN 0 3564 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG2_ACT_BITS 1 3565 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG2_ACT_SHIFT 23 3566 3567 /* DDR34_F0_PHY_CONTROL_REGS :: COMMAND_REG2 :: WE [22:22] */ 3568 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG2_WE_MASK 0x00400000 3569 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG2_WE_ALIGN 0 3570 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG2_WE_BITS 1 3571 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG2_WE_SHIFT 22 3572 3573 /* DDR34_F0_PHY_CONTROL_REGS :: COMMAND_REG2 :: CAS [21:21] */ 3574 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG2_CAS_MASK 0x00200000 3575 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG2_CAS_ALIGN 0 3576 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG2_CAS_BITS 1 3577 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG2_CAS_SHIFT 21 3578 3579 /* DDR34_F0_PHY_CONTROL_REGS :: COMMAND_REG2 :: RAS [20:20] */ 3580 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG2_RAS_MASK 0x00100000 3581 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG2_RAS_ALIGN 0 3582 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG2_RAS_BITS 1 3583 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG2_RAS_SHIFT 20 3584 3585 /* DDR34_F0_PHY_CONTROL_REGS :: COMMAND_REG2 :: BA [19:16] */ 3586 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG2_BA_MASK 0x000f0000 3587 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG2_BA_ALIGN 0 3588 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG2_BA_BITS 4 3589 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG2_BA_SHIFT 16 3590 3591 /* DDR34_F0_PHY_CONTROL_REGS :: COMMAND_REG2 :: AD [15:00] */ 3592 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG2_AD_MASK 0x0000ffff 3593 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG2_AD_ALIGN 0 3594 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG2_AD_BITS 16 3595 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG2_AD_SHIFT 0 3596 3597 3598 /**************************************************************************** 3599 * DDR34_F0_PHY_CONTROL_REGS :: COMMAND_AUX_REG2 3600 */ 3601 /* DDR34_F0_PHY_CONTROL_REGS :: COMMAND_AUX_REG2 :: reserved0 [31:01] */ 3602 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_AUX_REG2_RESERVED0_MASK 0xfffffffe 3603 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_AUX_REG2_RESERVED0_ALIGN 0 3604 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_AUX_REG2_RESERVED0_BITS 31 3605 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_AUX_REG2_RESERVED0_SHIFT 1 3606 3607 /* DDR34_F0_PHY_CONTROL_REGS :: COMMAND_AUX_REG2 :: AD16 [00:00] */ 3608 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_AUX_REG2_AD16_MASK 0x00000001 3609 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_AUX_REG2_AD16_ALIGN 0 3610 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_AUX_REG2_AD16_BITS 1 3611 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_AUX_REG2_AD16_SHIFT 0 3612 3613 3614 /**************************************************************************** 3615 * DDR34_F0_PHY_CONTROL_REGS :: COMMAND_REG3 3616 */ 3617 /* DDR34_F0_PHY_CONTROL_REGS :: COMMAND_REG3 :: MCP [31:31] */ 3618 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG3_MCP_MASK 0x80000000 3619 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG3_MCP_ALIGN 0 3620 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG3_MCP_BITS 1 3621 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG3_MCP_SHIFT 31 3622 3623 /* DDR34_F0_PHY_CONTROL_REGS :: COMMAND_REG3 :: CS [30:29] */ 3624 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG3_CS_MASK 0x60000000 3625 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG3_CS_ALIGN 0 3626 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG3_CS_BITS 2 3627 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG3_CS_SHIFT 29 3628 3629 /* DDR34_F0_PHY_CONTROL_REGS :: COMMAND_REG3 :: AUX [28:24] */ 3630 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG3_AUX_MASK 0x1f000000 3631 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG3_AUX_ALIGN 0 3632 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG3_AUX_BITS 5 3633 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG3_AUX_SHIFT 24 3634 3635 /* DDR34_F0_PHY_CONTROL_REGS :: COMMAND_REG3 :: ACT [23:23] */ 3636 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG3_ACT_MASK 0x00800000 3637 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG3_ACT_ALIGN 0 3638 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG3_ACT_BITS 1 3639 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG3_ACT_SHIFT 23 3640 3641 /* DDR34_F0_PHY_CONTROL_REGS :: COMMAND_REG3 :: WE [22:22] */ 3642 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG3_WE_MASK 0x00400000 3643 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG3_WE_ALIGN 0 3644 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG3_WE_BITS 1 3645 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG3_WE_SHIFT 22 3646 3647 /* DDR34_F0_PHY_CONTROL_REGS :: COMMAND_REG3 :: CAS [21:21] */ 3648 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG3_CAS_MASK 0x00200000 3649 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG3_CAS_ALIGN 0 3650 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG3_CAS_BITS 1 3651 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG3_CAS_SHIFT 21 3652 3653 /* DDR34_F0_PHY_CONTROL_REGS :: COMMAND_REG3 :: RAS [20:20] */ 3654 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG3_RAS_MASK 0x00100000 3655 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG3_RAS_ALIGN 0 3656 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG3_RAS_BITS 1 3657 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG3_RAS_SHIFT 20 3658 3659 /* DDR34_F0_PHY_CONTROL_REGS :: COMMAND_REG3 :: BA [19:16] */ 3660 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG3_BA_MASK 0x000f0000 3661 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG3_BA_ALIGN 0 3662 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG3_BA_BITS 4 3663 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG3_BA_SHIFT 16 3664 3665 /* DDR34_F0_PHY_CONTROL_REGS :: COMMAND_REG3 :: AD [15:00] */ 3666 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG3_AD_MASK 0x0000ffff 3667 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG3_AD_ALIGN 0 3668 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG3_AD_BITS 16 3669 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG3_AD_SHIFT 0 3670 3671 3672 /**************************************************************************** 3673 * DDR34_F0_PHY_CONTROL_REGS :: COMMAND_AUX_REG3 3674 */ 3675 /* DDR34_F0_PHY_CONTROL_REGS :: COMMAND_AUX_REG3 :: reserved0 [31:01] */ 3676 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_AUX_REG3_RESERVED0_MASK 0xfffffffe 3677 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_AUX_REG3_RESERVED0_ALIGN 0 3678 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_AUX_REG3_RESERVED0_BITS 31 3679 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_AUX_REG3_RESERVED0_SHIFT 1 3680 3681 /* DDR34_F0_PHY_CONTROL_REGS :: COMMAND_AUX_REG3 :: AD16 [00:00] */ 3682 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_AUX_REG3_AD16_MASK 0x00000001 3683 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_AUX_REG3_AD16_ALIGN 0 3684 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_AUX_REG3_AD16_BITS 1 3685 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_AUX_REG3_AD16_SHIFT 0 3686 3687 3688 /**************************************************************************** 3689 * DDR34_F0_PHY_CONTROL_REGS :: COMMAND_REG4 3690 */ 3691 /* DDR34_F0_PHY_CONTROL_REGS :: COMMAND_REG4 :: MCP [31:31] */ 3692 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG4_MCP_MASK 0x80000000 3693 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG4_MCP_ALIGN 0 3694 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG4_MCP_BITS 1 3695 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG4_MCP_SHIFT 31 3696 3697 /* DDR34_F0_PHY_CONTROL_REGS :: COMMAND_REG4 :: CS [30:29] */ 3698 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG4_CS_MASK 0x60000000 3699 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG4_CS_ALIGN 0 3700 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG4_CS_BITS 2 3701 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG4_CS_SHIFT 29 3702 3703 /* DDR34_F0_PHY_CONTROL_REGS :: COMMAND_REG4 :: AUX [28:24] */ 3704 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG4_AUX_MASK 0x1f000000 3705 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG4_AUX_ALIGN 0 3706 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG4_AUX_BITS 5 3707 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG4_AUX_SHIFT 24 3708 3709 /* DDR34_F0_PHY_CONTROL_REGS :: COMMAND_REG4 :: ACT [23:23] */ 3710 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG4_ACT_MASK 0x00800000 3711 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG4_ACT_ALIGN 0 3712 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG4_ACT_BITS 1 3713 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG4_ACT_SHIFT 23 3714 3715 /* DDR34_F0_PHY_CONTROL_REGS :: COMMAND_REG4 :: WE [22:22] */ 3716 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG4_WE_MASK 0x00400000 3717 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG4_WE_ALIGN 0 3718 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG4_WE_BITS 1 3719 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG4_WE_SHIFT 22 3720 3721 /* DDR34_F0_PHY_CONTROL_REGS :: COMMAND_REG4 :: CAS [21:21] */ 3722 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG4_CAS_MASK 0x00200000 3723 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG4_CAS_ALIGN 0 3724 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG4_CAS_BITS 1 3725 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG4_CAS_SHIFT 21 3726 3727 /* DDR34_F0_PHY_CONTROL_REGS :: COMMAND_REG4 :: RAS [20:20] */ 3728 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG4_RAS_MASK 0x00100000 3729 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG4_RAS_ALIGN 0 3730 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG4_RAS_BITS 1 3731 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG4_RAS_SHIFT 20 3732 3733 /* DDR34_F0_PHY_CONTROL_REGS :: COMMAND_REG4 :: BA [19:16] */ 3734 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG4_BA_MASK 0x000f0000 3735 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG4_BA_ALIGN 0 3736 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG4_BA_BITS 4 3737 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG4_BA_SHIFT 16 3738 3739 /* DDR34_F0_PHY_CONTROL_REGS :: COMMAND_REG4 :: AD [15:00] */ 3740 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG4_AD_MASK 0x0000ffff 3741 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG4_AD_ALIGN 0 3742 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG4_AD_BITS 16 3743 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG4_AD_SHIFT 0 3744 3745 3746 /**************************************************************************** 3747 * DDR34_F0_PHY_CONTROL_REGS :: COMMAND_AUX_REG4 3748 */ 3749 /* DDR34_F0_PHY_CONTROL_REGS :: COMMAND_AUX_REG4 :: reserved0 [31:01] */ 3750 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_AUX_REG4_RESERVED0_MASK 0xfffffffe 3751 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_AUX_REG4_RESERVED0_ALIGN 0 3752 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_AUX_REG4_RESERVED0_BITS 31 3753 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_AUX_REG4_RESERVED0_SHIFT 1 3754 3755 /* DDR34_F0_PHY_CONTROL_REGS :: COMMAND_AUX_REG4 :: AD16 [00:00] */ 3756 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_AUX_REG4_AD16_MASK 0x00000001 3757 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_AUX_REG4_AD16_ALIGN 0 3758 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_AUX_REG4_AD16_BITS 1 3759 #define DDR34_F0_PHY_CONTROL_REGS_COMMAND_AUX_REG4_AD16_SHIFT 0 3760 3761 3762 /**************************************************************************** 3763 * DDR34_F0_PHY_CONTROL_REGS :: MODE_REG0 3764 */ 3765 /* DDR34_F0_PHY_CONTROL_REGS :: MODE_REG0 :: reserved0 [31:17] */ 3766 #define DDR34_F0_PHY_CONTROL_REGS_MODE_REG0_RESERVED0_MASK 0xfffe0000 3767 #define DDR34_F0_PHY_CONTROL_REGS_MODE_REG0_RESERVED0_ALIGN 0 3768 #define DDR34_F0_PHY_CONTROL_REGS_MODE_REG0_RESERVED0_BITS 15 3769 #define DDR34_F0_PHY_CONTROL_REGS_MODE_REG0_RESERVED0_SHIFT 17 3770 3771 /* DDR34_F0_PHY_CONTROL_REGS :: MODE_REG0 :: VALID [16:16] */ 3772 #define DDR34_F0_PHY_CONTROL_REGS_MODE_REG0_VALID_MASK 0x00010000 3773 #define DDR34_F0_PHY_CONTROL_REGS_MODE_REG0_VALID_ALIGN 0 3774 #define DDR34_F0_PHY_CONTROL_REGS_MODE_REG0_VALID_BITS 1 3775 #define DDR34_F0_PHY_CONTROL_REGS_MODE_REG0_VALID_SHIFT 16 3776 3777 /* DDR34_F0_PHY_CONTROL_REGS :: MODE_REG0 :: AD [15:00] */ 3778 #define DDR34_F0_PHY_CONTROL_REGS_MODE_REG0_AD_MASK 0x0000ffff 3779 #define DDR34_F0_PHY_CONTROL_REGS_MODE_REG0_AD_ALIGN 0 3780 #define DDR34_F0_PHY_CONTROL_REGS_MODE_REG0_AD_BITS 16 3781 #define DDR34_F0_PHY_CONTROL_REGS_MODE_REG0_AD_SHIFT 0 3782 3783 3784 /**************************************************************************** 3785 * DDR34_F0_PHY_CONTROL_REGS :: MODE_REG1 3786 */ 3787 /* DDR34_F0_PHY_CONTROL_REGS :: MODE_REG1 :: reserved0 [31:17] */ 3788 #define DDR34_F0_PHY_CONTROL_REGS_MODE_REG1_RESERVED0_MASK 0xfffe0000 3789 #define DDR34_F0_PHY_CONTROL_REGS_MODE_REG1_RESERVED0_ALIGN 0 3790 #define DDR34_F0_PHY_CONTROL_REGS_MODE_REG1_RESERVED0_BITS 15 3791 #define DDR34_F0_PHY_CONTROL_REGS_MODE_REG1_RESERVED0_SHIFT 17 3792 3793 /* DDR34_F0_PHY_CONTROL_REGS :: MODE_REG1 :: VALID [16:16] */ 3794 #define DDR34_F0_PHY_CONTROL_REGS_MODE_REG1_VALID_MASK 0x00010000 3795 #define DDR34_F0_PHY_CONTROL_REGS_MODE_REG1_VALID_ALIGN 0 3796 #define DDR34_F0_PHY_CONTROL_REGS_MODE_REG1_VALID_BITS 1 3797 #define DDR34_F0_PHY_CONTROL_REGS_MODE_REG1_VALID_SHIFT 16 3798 3799 /* DDR34_F0_PHY_CONTROL_REGS :: MODE_REG1 :: AD [15:00] */ 3800 #define DDR34_F0_PHY_CONTROL_REGS_MODE_REG1_AD_MASK 0x0000ffff 3801 #define DDR34_F0_PHY_CONTROL_REGS_MODE_REG1_AD_ALIGN 0 3802 #define DDR34_F0_PHY_CONTROL_REGS_MODE_REG1_AD_BITS 16 3803 #define DDR34_F0_PHY_CONTROL_REGS_MODE_REG1_AD_SHIFT 0 3804 3805 3806 /**************************************************************************** 3807 * DDR34_F0_PHY_CONTROL_REGS :: MODE_REG2 3808 */ 3809 /* DDR34_F0_PHY_CONTROL_REGS :: MODE_REG2 :: reserved0 [31:17] */ 3810 #define DDR34_F0_PHY_CONTROL_REGS_MODE_REG2_RESERVED0_MASK 0xfffe0000 3811 #define DDR34_F0_PHY_CONTROL_REGS_MODE_REG2_RESERVED0_ALIGN 0 3812 #define DDR34_F0_PHY_CONTROL_REGS_MODE_REG2_RESERVED0_BITS 15 3813 #define DDR34_F0_PHY_CONTROL_REGS_MODE_REG2_RESERVED0_SHIFT 17 3814 3815 /* DDR34_F0_PHY_CONTROL_REGS :: MODE_REG2 :: VALID [16:16] */ 3816 #define DDR34_F0_PHY_CONTROL_REGS_MODE_REG2_VALID_MASK 0x00010000 3817 #define DDR34_F0_PHY_CONTROL_REGS_MODE_REG2_VALID_ALIGN 0 3818 #define DDR34_F0_PHY_CONTROL_REGS_MODE_REG2_VALID_BITS 1 3819 #define DDR34_F0_PHY_CONTROL_REGS_MODE_REG2_VALID_SHIFT 16 3820 3821 /* DDR34_F0_PHY_CONTROL_REGS :: MODE_REG2 :: AD [15:00] */ 3822 #define DDR34_F0_PHY_CONTROL_REGS_MODE_REG2_AD_MASK 0x0000ffff 3823 #define DDR34_F0_PHY_CONTROL_REGS_MODE_REG2_AD_ALIGN 0 3824 #define DDR34_F0_PHY_CONTROL_REGS_MODE_REG2_AD_BITS 16 3825 #define DDR34_F0_PHY_CONTROL_REGS_MODE_REG2_AD_SHIFT 0 3826 3827 3828 /**************************************************************************** 3829 * DDR34_F0_PHY_CONTROL_REGS :: MODE_REG3 3830 */ 3831 /* DDR34_F0_PHY_CONTROL_REGS :: MODE_REG3 :: reserved0 [31:17] */ 3832 #define DDR34_F0_PHY_CONTROL_REGS_MODE_REG3_RESERVED0_MASK 0xfffe0000 3833 #define DDR34_F0_PHY_CONTROL_REGS_MODE_REG3_RESERVED0_ALIGN 0 3834 #define DDR34_F0_PHY_CONTROL_REGS_MODE_REG3_RESERVED0_BITS 15 3835 #define DDR34_F0_PHY_CONTROL_REGS_MODE_REG3_RESERVED0_SHIFT 17 3836 3837 /* DDR34_F0_PHY_CONTROL_REGS :: MODE_REG3 :: VALID [16:16] */ 3838 #define DDR34_F0_PHY_CONTROL_REGS_MODE_REG3_VALID_MASK 0x00010000 3839 #define DDR34_F0_PHY_CONTROL_REGS_MODE_REG3_VALID_ALIGN 0 3840 #define DDR34_F0_PHY_CONTROL_REGS_MODE_REG3_VALID_BITS 1 3841 #define DDR34_F0_PHY_CONTROL_REGS_MODE_REG3_VALID_SHIFT 16 3842 3843 /* DDR34_F0_PHY_CONTROL_REGS :: MODE_REG3 :: AD [15:00] */ 3844 #define DDR34_F0_PHY_CONTROL_REGS_MODE_REG3_AD_MASK 0x0000ffff 3845 #define DDR34_F0_PHY_CONTROL_REGS_MODE_REG3_AD_ALIGN 0 3846 #define DDR34_F0_PHY_CONTROL_REGS_MODE_REG3_AD_BITS 16 3847 #define DDR34_F0_PHY_CONTROL_REGS_MODE_REG3_AD_SHIFT 0 3848 3849 3850 /**************************************************************************** 3851 * DDR34_F0_PHY_CONTROL_REGS :: MODE_REG4 3852 */ 3853 /* DDR34_F0_PHY_CONTROL_REGS :: MODE_REG4 :: reserved0 [31:17] */ 3854 #define DDR34_F0_PHY_CONTROL_REGS_MODE_REG4_RESERVED0_MASK 0xfffe0000 3855 #define DDR34_F0_PHY_CONTROL_REGS_MODE_REG4_RESERVED0_ALIGN 0 3856 #define DDR34_F0_PHY_CONTROL_REGS_MODE_REG4_RESERVED0_BITS 15 3857 #define DDR34_F0_PHY_CONTROL_REGS_MODE_REG4_RESERVED0_SHIFT 17 3858 3859 /* DDR34_F0_PHY_CONTROL_REGS :: MODE_REG4 :: VALID [16:16] */ 3860 #define DDR34_F0_PHY_CONTROL_REGS_MODE_REG4_VALID_MASK 0x00010000 3861 #define DDR34_F0_PHY_CONTROL_REGS_MODE_REG4_VALID_ALIGN 0 3862 #define DDR34_F0_PHY_CONTROL_REGS_MODE_REG4_VALID_BITS 1 3863 #define DDR34_F0_PHY_CONTROL_REGS_MODE_REG4_VALID_SHIFT 16 3864 3865 /* DDR34_F0_PHY_CONTROL_REGS :: MODE_REG4 :: AD [15:00] */ 3866 #define DDR34_F0_PHY_CONTROL_REGS_MODE_REG4_AD_MASK 0x0000ffff 3867 #define DDR34_F0_PHY_CONTROL_REGS_MODE_REG4_AD_ALIGN 0 3868 #define DDR34_F0_PHY_CONTROL_REGS_MODE_REG4_AD_BITS 16 3869 #define DDR34_F0_PHY_CONTROL_REGS_MODE_REG4_AD_SHIFT 0 3870 3871 3872 /**************************************************************************** 3873 * DDR34_F0_PHY_CONTROL_REGS :: MODE_REG5 3874 */ 3875 /* DDR34_F0_PHY_CONTROL_REGS :: MODE_REG5 :: reserved0 [31:17] */ 3876 #define DDR34_F0_PHY_CONTROL_REGS_MODE_REG5_RESERVED0_MASK 0xfffe0000 3877 #define DDR34_F0_PHY_CONTROL_REGS_MODE_REG5_RESERVED0_ALIGN 0 3878 #define DDR34_F0_PHY_CONTROL_REGS_MODE_REG5_RESERVED0_BITS 15 3879 #define DDR34_F0_PHY_CONTROL_REGS_MODE_REG5_RESERVED0_SHIFT 17 3880 3881 /* DDR34_F0_PHY_CONTROL_REGS :: MODE_REG5 :: VALID [16:16] */ 3882 #define DDR34_F0_PHY_CONTROL_REGS_MODE_REG5_VALID_MASK 0x00010000 3883 #define DDR34_F0_PHY_CONTROL_REGS_MODE_REG5_VALID_ALIGN 0 3884 #define DDR34_F0_PHY_CONTROL_REGS_MODE_REG5_VALID_BITS 1 3885 #define DDR34_F0_PHY_CONTROL_REGS_MODE_REG5_VALID_SHIFT 16 3886 3887 /* DDR34_F0_PHY_CONTROL_REGS :: MODE_REG5 :: AD [15:00] */ 3888 #define DDR34_F0_PHY_CONTROL_REGS_MODE_REG5_AD_MASK 0x0000ffff 3889 #define DDR34_F0_PHY_CONTROL_REGS_MODE_REG5_AD_ALIGN 0 3890 #define DDR34_F0_PHY_CONTROL_REGS_MODE_REG5_AD_BITS 16 3891 #define DDR34_F0_PHY_CONTROL_REGS_MODE_REG5_AD_SHIFT 0 3892 3893 3894 /**************************************************************************** 3895 * DDR34_F0_PHY_CONTROL_REGS :: MODE_REG6 3896 */ 3897 /* DDR34_F0_PHY_CONTROL_REGS :: MODE_REG6 :: reserved0 [31:17] */ 3898 #define DDR34_F0_PHY_CONTROL_REGS_MODE_REG6_RESERVED0_MASK 0xfffe0000 3899 #define DDR34_F0_PHY_CONTROL_REGS_MODE_REG6_RESERVED0_ALIGN 0 3900 #define DDR34_F0_PHY_CONTROL_REGS_MODE_REG6_RESERVED0_BITS 15 3901 #define DDR34_F0_PHY_CONTROL_REGS_MODE_REG6_RESERVED0_SHIFT 17 3902 3903 /* DDR34_F0_PHY_CONTROL_REGS :: MODE_REG6 :: VALID [16:16] */ 3904 #define DDR34_F0_PHY_CONTROL_REGS_MODE_REG6_VALID_MASK 0x00010000 3905 #define DDR34_F0_PHY_CONTROL_REGS_MODE_REG6_VALID_ALIGN 0 3906 #define DDR34_F0_PHY_CONTROL_REGS_MODE_REG6_VALID_BITS 1 3907 #define DDR34_F0_PHY_CONTROL_REGS_MODE_REG6_VALID_SHIFT 16 3908 3909 /* DDR34_F0_PHY_CONTROL_REGS :: MODE_REG6 :: AD [15:00] */ 3910 #define DDR34_F0_PHY_CONTROL_REGS_MODE_REG6_AD_MASK 0x0000ffff 3911 #define DDR34_F0_PHY_CONTROL_REGS_MODE_REG6_AD_ALIGN 0 3912 #define DDR34_F0_PHY_CONTROL_REGS_MODE_REG6_AD_BITS 16 3913 #define DDR34_F0_PHY_CONTROL_REGS_MODE_REG6_AD_SHIFT 0 3914 3915 3916 /**************************************************************************** 3917 * DDR34_F0_PHY_CONTROL_REGS :: MODE_REG7 3918 */ 3919 /* DDR34_F0_PHY_CONTROL_REGS :: MODE_REG7 :: reserved0 [31:17] */ 3920 #define DDR34_F0_PHY_CONTROL_REGS_MODE_REG7_RESERVED0_MASK 0xfffe0000 3921 #define DDR34_F0_PHY_CONTROL_REGS_MODE_REG7_RESERVED0_ALIGN 0 3922 #define DDR34_F0_PHY_CONTROL_REGS_MODE_REG7_RESERVED0_BITS 15 3923 #define DDR34_F0_PHY_CONTROL_REGS_MODE_REG7_RESERVED0_SHIFT 17 3924 3925 /* DDR34_F0_PHY_CONTROL_REGS :: MODE_REG7 :: VALID [16:16] */ 3926 #define DDR34_F0_PHY_CONTROL_REGS_MODE_REG7_VALID_MASK 0x00010000 3927 #define DDR34_F0_PHY_CONTROL_REGS_MODE_REG7_VALID_ALIGN 0 3928 #define DDR34_F0_PHY_CONTROL_REGS_MODE_REG7_VALID_BITS 1 3929 #define DDR34_F0_PHY_CONTROL_REGS_MODE_REG7_VALID_SHIFT 16 3930 3931 /* DDR34_F0_PHY_CONTROL_REGS :: MODE_REG7 :: AD [15:00] */ 3932 #define DDR34_F0_PHY_CONTROL_REGS_MODE_REG7_AD_MASK 0x0000ffff 3933 #define DDR34_F0_PHY_CONTROL_REGS_MODE_REG7_AD_ALIGN 0 3934 #define DDR34_F0_PHY_CONTROL_REGS_MODE_REG7_AD_BITS 16 3935 #define DDR34_F0_PHY_CONTROL_REGS_MODE_REG7_AD_SHIFT 0 3936 3937 3938 /**************************************************************************** 3939 * DDR34_F0_PHY_CONTROL_REGS :: MODE_REG8 3940 */ 3941 /* DDR34_F0_PHY_CONTROL_REGS :: MODE_REG8 :: reserved0 [31:17] */ 3942 #define DDR34_F0_PHY_CONTROL_REGS_MODE_REG8_RESERVED0_MASK 0xfffe0000 3943 #define DDR34_F0_PHY_CONTROL_REGS_MODE_REG8_RESERVED0_ALIGN 0 3944 #define DDR34_F0_PHY_CONTROL_REGS_MODE_REG8_RESERVED0_BITS 15 3945 #define DDR34_F0_PHY_CONTROL_REGS_MODE_REG8_RESERVED0_SHIFT 17 3946 3947 /* DDR34_F0_PHY_CONTROL_REGS :: MODE_REG8 :: VALID [16:16] */ 3948 #define DDR34_F0_PHY_CONTROL_REGS_MODE_REG8_VALID_MASK 0x00010000 3949 #define DDR34_F0_PHY_CONTROL_REGS_MODE_REG8_VALID_ALIGN 0 3950 #define DDR34_F0_PHY_CONTROL_REGS_MODE_REG8_VALID_BITS 1 3951 #define DDR34_F0_PHY_CONTROL_REGS_MODE_REG8_VALID_SHIFT 16 3952 3953 /* DDR34_F0_PHY_CONTROL_REGS :: MODE_REG8 :: AD [15:00] */ 3954 #define DDR34_F0_PHY_CONTROL_REGS_MODE_REG8_AD_MASK 0x0000ffff 3955 #define DDR34_F0_PHY_CONTROL_REGS_MODE_REG8_AD_ALIGN 0 3956 #define DDR34_F0_PHY_CONTROL_REGS_MODE_REG8_AD_BITS 16 3957 #define DDR34_F0_PHY_CONTROL_REGS_MODE_REG8_AD_SHIFT 0 3958 3959 3960 /**************************************************************************** 3961 * DDR34_F0_PHY_CONTROL_REGS :: MODE_REG15 3962 */ 3963 /* DDR34_F0_PHY_CONTROL_REGS :: MODE_REG15 :: reserved0 [31:17] */ 3964 #define DDR34_F0_PHY_CONTROL_REGS_MODE_REG15_RESERVED0_MASK 0xfffe0000 3965 #define DDR34_F0_PHY_CONTROL_REGS_MODE_REG15_RESERVED0_ALIGN 0 3966 #define DDR34_F0_PHY_CONTROL_REGS_MODE_REG15_RESERVED0_BITS 15 3967 #define DDR34_F0_PHY_CONTROL_REGS_MODE_REG15_RESERVED0_SHIFT 17 3968 3969 /* DDR34_F0_PHY_CONTROL_REGS :: MODE_REG15 :: VALID [16:16] */ 3970 #define DDR34_F0_PHY_CONTROL_REGS_MODE_REG15_VALID_MASK 0x00010000 3971 #define DDR34_F0_PHY_CONTROL_REGS_MODE_REG15_VALID_ALIGN 0 3972 #define DDR34_F0_PHY_CONTROL_REGS_MODE_REG15_VALID_BITS 1 3973 #define DDR34_F0_PHY_CONTROL_REGS_MODE_REG15_VALID_SHIFT 16 3974 3975 /* DDR34_F0_PHY_CONTROL_REGS :: MODE_REG15 :: AD [15:00] */ 3976 #define DDR34_F0_PHY_CONTROL_REGS_MODE_REG15_AD_MASK 0x0000ffff 3977 #define DDR34_F0_PHY_CONTROL_REGS_MODE_REG15_AD_ALIGN 0 3978 #define DDR34_F0_PHY_CONTROL_REGS_MODE_REG15_AD_BITS 16 3979 #define DDR34_F0_PHY_CONTROL_REGS_MODE_REG15_AD_SHIFT 0 3980 3981 3982 /**************************************************************************** 3983 * DDR34_F0_PHY_CONTROL_REGS :: MODE_REG63 3984 */ 3985 /* DDR34_F0_PHY_CONTROL_REGS :: MODE_REG63 :: reserved0 [31:17] */ 3986 #define DDR34_F0_PHY_CONTROL_REGS_MODE_REG63_RESERVED0_MASK 0xfffe0000 3987 #define DDR34_F0_PHY_CONTROL_REGS_MODE_REG63_RESERVED0_ALIGN 0 3988 #define DDR34_F0_PHY_CONTROL_REGS_MODE_REG63_RESERVED0_BITS 15 3989 #define DDR34_F0_PHY_CONTROL_REGS_MODE_REG63_RESERVED0_SHIFT 17 3990 3991 /* DDR34_F0_PHY_CONTROL_REGS :: MODE_REG63 :: VALID [16:16] */ 3992 #define DDR34_F0_PHY_CONTROL_REGS_MODE_REG63_VALID_MASK 0x00010000 3993 #define DDR34_F0_PHY_CONTROL_REGS_MODE_REG63_VALID_ALIGN 0 3994 #define DDR34_F0_PHY_CONTROL_REGS_MODE_REG63_VALID_BITS 1 3995 #define DDR34_F0_PHY_CONTROL_REGS_MODE_REG63_VALID_SHIFT 16 3996 3997 /* DDR34_F0_PHY_CONTROL_REGS :: MODE_REG63 :: AD [15:00] */ 3998 #define DDR34_F0_PHY_CONTROL_REGS_MODE_REG63_AD_MASK 0x0000ffff 3999 #define DDR34_F0_PHY_CONTROL_REGS_MODE_REG63_AD_ALIGN 0 4000 #define DDR34_F0_PHY_CONTROL_REGS_MODE_REG63_AD_BITS 16 4001 #define DDR34_F0_PHY_CONTROL_REGS_MODE_REG63_AD_SHIFT 0 4002 4003 4004 /**************************************************************************** 4005 * DDR34_F0_PHY_CONTROL_REGS :: ALERT_CLEAR 4006 */ 4007 /* DDR34_F0_PHY_CONTROL_REGS :: ALERT_CLEAR :: reserved0 [31:01] */ 4008 #define DDR34_F0_PHY_CONTROL_REGS_ALERT_CLEAR_RESERVED0_MASK 0xfffffffe 4009 #define DDR34_F0_PHY_CONTROL_REGS_ALERT_CLEAR_RESERVED0_ALIGN 0 4010 #define DDR34_F0_PHY_CONTROL_REGS_ALERT_CLEAR_RESERVED0_BITS 31 4011 #define DDR34_F0_PHY_CONTROL_REGS_ALERT_CLEAR_RESERVED0_SHIFT 1 4012 4013 /* DDR34_F0_PHY_CONTROL_REGS :: ALERT_CLEAR :: CLEAR [00:00] */ 4014 #define DDR34_F0_PHY_CONTROL_REGS_ALERT_CLEAR_CLEAR_MASK 0x00000001 4015 #define DDR34_F0_PHY_CONTROL_REGS_ALERT_CLEAR_CLEAR_ALIGN 0 4016 #define DDR34_F0_PHY_CONTROL_REGS_ALERT_CLEAR_CLEAR_BITS 1 4017 #define DDR34_F0_PHY_CONTROL_REGS_ALERT_CLEAR_CLEAR_SHIFT 0 4018 4019 4020 /**************************************************************************** 4021 * DDR34_F0_PHY_CONTROL_REGS :: ALERT_STATUS 4022 */ 4023 /* DDR34_F0_PHY_CONTROL_REGS :: ALERT_STATUS :: reserved0 [31:12] */ 4024 #define DDR34_F0_PHY_CONTROL_REGS_ALERT_STATUS_RESERVED0_MASK 0xfffff000 4025 #define DDR34_F0_PHY_CONTROL_REGS_ALERT_STATUS_RESERVED0_ALIGN 0 4026 #define DDR34_F0_PHY_CONTROL_REGS_ALERT_STATUS_RESERVED0_BITS 20 4027 #define DDR34_F0_PHY_CONTROL_REGS_ALERT_STATUS_RESERVED0_SHIFT 12 4028 4029 /* DDR34_F0_PHY_CONTROL_REGS :: ALERT_STATUS :: BL3_STATE [11:11] */ 4030 #define DDR34_F0_PHY_CONTROL_REGS_ALERT_STATUS_BL3_STATE_MASK 0x00000800 4031 #define DDR34_F0_PHY_CONTROL_REGS_ALERT_STATUS_BL3_STATE_ALIGN 0 4032 #define DDR34_F0_PHY_CONTROL_REGS_ALERT_STATUS_BL3_STATE_BITS 1 4033 #define DDR34_F0_PHY_CONTROL_REGS_ALERT_STATUS_BL3_STATE_SHIFT 11 4034 4035 /* DDR34_F0_PHY_CONTROL_REGS :: ALERT_STATUS :: BL2_STATE [10:10] */ 4036 #define DDR34_F0_PHY_CONTROL_REGS_ALERT_STATUS_BL2_STATE_MASK 0x00000400 4037 #define DDR34_F0_PHY_CONTROL_REGS_ALERT_STATUS_BL2_STATE_ALIGN 0 4038 #define DDR34_F0_PHY_CONTROL_REGS_ALERT_STATUS_BL2_STATE_BITS 1 4039 #define DDR34_F0_PHY_CONTROL_REGS_ALERT_STATUS_BL2_STATE_SHIFT 10 4040 4041 /* DDR34_F0_PHY_CONTROL_REGS :: ALERT_STATUS :: BL1_STATE [09:09] */ 4042 #define DDR34_F0_PHY_CONTROL_REGS_ALERT_STATUS_BL1_STATE_MASK 0x00000200 4043 #define DDR34_F0_PHY_CONTROL_REGS_ALERT_STATUS_BL1_STATE_ALIGN 0 4044 #define DDR34_F0_PHY_CONTROL_REGS_ALERT_STATUS_BL1_STATE_BITS 1 4045 #define DDR34_F0_PHY_CONTROL_REGS_ALERT_STATUS_BL1_STATE_SHIFT 9 4046 4047 /* DDR34_F0_PHY_CONTROL_REGS :: ALERT_STATUS :: BL0_STATE [08:08] */ 4048 #define DDR34_F0_PHY_CONTROL_REGS_ALERT_STATUS_BL0_STATE_MASK 0x00000100 4049 #define DDR34_F0_PHY_CONTROL_REGS_ALERT_STATUS_BL0_STATE_ALIGN 0 4050 #define DDR34_F0_PHY_CONTROL_REGS_ALERT_STATUS_BL0_STATE_BITS 1 4051 #define DDR34_F0_PHY_CONTROL_REGS_ALERT_STATUS_BL0_STATE_SHIFT 8 4052 4053 /* DDR34_F0_PHY_CONTROL_REGS :: ALERT_STATUS :: reserved1 [07:04] */ 4054 #define DDR34_F0_PHY_CONTROL_REGS_ALERT_STATUS_RESERVED1_MASK 0x000000f0 4055 #define DDR34_F0_PHY_CONTROL_REGS_ALERT_STATUS_RESERVED1_ALIGN 0 4056 #define DDR34_F0_PHY_CONTROL_REGS_ALERT_STATUS_RESERVED1_BITS 4 4057 #define DDR34_F0_PHY_CONTROL_REGS_ALERT_STATUS_RESERVED1_SHIFT 4 4058 4059 /* DDR34_F0_PHY_CONTROL_REGS :: ALERT_STATUS :: BL3_ALERT [03:03] */ 4060 #define DDR34_F0_PHY_CONTROL_REGS_ALERT_STATUS_BL3_ALERT_MASK 0x00000008 4061 #define DDR34_F0_PHY_CONTROL_REGS_ALERT_STATUS_BL3_ALERT_ALIGN 0 4062 #define DDR34_F0_PHY_CONTROL_REGS_ALERT_STATUS_BL3_ALERT_BITS 1 4063 #define DDR34_F0_PHY_CONTROL_REGS_ALERT_STATUS_BL3_ALERT_SHIFT 3 4064 4065 /* DDR34_F0_PHY_CONTROL_REGS :: ALERT_STATUS :: BL2_ALERT [02:02] */ 4066 #define DDR34_F0_PHY_CONTROL_REGS_ALERT_STATUS_BL2_ALERT_MASK 0x00000004 4067 #define DDR34_F0_PHY_CONTROL_REGS_ALERT_STATUS_BL2_ALERT_ALIGN 0 4068 #define DDR34_F0_PHY_CONTROL_REGS_ALERT_STATUS_BL2_ALERT_BITS 1 4069 #define DDR34_F0_PHY_CONTROL_REGS_ALERT_STATUS_BL2_ALERT_SHIFT 2 4070 4071 /* DDR34_F0_PHY_CONTROL_REGS :: ALERT_STATUS :: BL1_ALERT [01:01] */ 4072 #define DDR34_F0_PHY_CONTROL_REGS_ALERT_STATUS_BL1_ALERT_MASK 0x00000002 4073 #define DDR34_F0_PHY_CONTROL_REGS_ALERT_STATUS_BL1_ALERT_ALIGN 0 4074 #define DDR34_F0_PHY_CONTROL_REGS_ALERT_STATUS_BL1_ALERT_BITS 1 4075 #define DDR34_F0_PHY_CONTROL_REGS_ALERT_STATUS_BL1_ALERT_SHIFT 1 4076 4077 /* DDR34_F0_PHY_CONTROL_REGS :: ALERT_STATUS :: BL0_ALERT [00:00] */ 4078 #define DDR34_F0_PHY_CONTROL_REGS_ALERT_STATUS_BL0_ALERT_MASK 0x00000001 4079 #define DDR34_F0_PHY_CONTROL_REGS_ALERT_STATUS_BL0_ALERT_ALIGN 0 4080 #define DDR34_F0_PHY_CONTROL_REGS_ALERT_STATUS_BL0_ALERT_BITS 1 4081 #define DDR34_F0_PHY_CONTROL_REGS_ALERT_STATUS_BL0_ALERT_SHIFT 0 4082 4083 4084 /**************************************************************************** 4085 * DDR34_F0_PHY_CONTROL_REGS :: ALERT_DFI 4086 */ 4087 /* DDR34_F0_PHY_CONTROL_REGS :: ALERT_DFI :: reserved0 [31:04] */ 4088 #define DDR34_F0_PHY_CONTROL_REGS_ALERT_DFI_RESERVED0_MASK 0xfffffff0 4089 #define DDR34_F0_PHY_CONTROL_REGS_ALERT_DFI_RESERVED0_ALIGN 0 4090 #define DDR34_F0_PHY_CONTROL_REGS_ALERT_DFI_RESERVED0_BITS 28 4091 #define DDR34_F0_PHY_CONTROL_REGS_ALERT_DFI_RESERVED0_SHIFT 4 4092 4093 /* DDR34_F0_PHY_CONTROL_REGS :: ALERT_DFI :: MASK [03:00] */ 4094 #define DDR34_F0_PHY_CONTROL_REGS_ALERT_DFI_MASK_MASK 0x0000000f 4095 #define DDR34_F0_PHY_CONTROL_REGS_ALERT_DFI_MASK_ALIGN 0 4096 #define DDR34_F0_PHY_CONTROL_REGS_ALERT_DFI_MASK_BITS 4 4097 #define DDR34_F0_PHY_CONTROL_REGS_ALERT_DFI_MASK_SHIFT 0 4098 4099 4100 /**************************************************************************** 4101 * DDR34_F0_PHY_CONTROL_REGS :: CA_PLAYBACK_CONTROL 4102 */ 4103 /* DDR34_F0_PHY_CONTROL_REGS :: CA_PLAYBACK_CONTROL :: reserved0 [31:12] */ 4104 #define DDR34_F0_PHY_CONTROL_REGS_CA_PLAYBACK_CONTROL_RESERVED0_MASK 0xfffff000 4105 #define DDR34_F0_PHY_CONTROL_REGS_CA_PLAYBACK_CONTROL_RESERVED0_ALIGN 0 4106 #define DDR34_F0_PHY_CONTROL_REGS_CA_PLAYBACK_CONTROL_RESERVED0_BITS 20 4107 #define DDR34_F0_PHY_CONTROL_REGS_CA_PLAYBACK_CONTROL_RESERVED0_SHIFT 12 4108 4109 /* DDR34_F0_PHY_CONTROL_REGS :: CA_PLAYBACK_CONTROL :: COUNT [11:04] */ 4110 #define DDR34_F0_PHY_CONTROL_REGS_CA_PLAYBACK_CONTROL_COUNT_MASK 0x00000ff0 4111 #define DDR34_F0_PHY_CONTROL_REGS_CA_PLAYBACK_CONTROL_COUNT_ALIGN 0 4112 #define DDR34_F0_PHY_CONTROL_REGS_CA_PLAYBACK_CONTROL_COUNT_BITS 8 4113 #define DDR34_F0_PHY_CONTROL_REGS_CA_PLAYBACK_CONTROL_COUNT_SHIFT 4 4114 4115 /* DDR34_F0_PHY_CONTROL_REGS :: CA_PLAYBACK_CONTROL :: reserved1 [03:01] */ 4116 #define DDR34_F0_PHY_CONTROL_REGS_CA_PLAYBACK_CONTROL_RESERVED1_MASK 0x0000000e 4117 #define DDR34_F0_PHY_CONTROL_REGS_CA_PLAYBACK_CONTROL_RESERVED1_ALIGN 0 4118 #define DDR34_F0_PHY_CONTROL_REGS_CA_PLAYBACK_CONTROL_RESERVED1_BITS 3 4119 #define DDR34_F0_PHY_CONTROL_REGS_CA_PLAYBACK_CONTROL_RESERVED1_SHIFT 1 4120 4121 /* DDR34_F0_PHY_CONTROL_REGS :: CA_PLAYBACK_CONTROL :: SAMPLE [00:00] */ 4122 #define DDR34_F0_PHY_CONTROL_REGS_CA_PLAYBACK_CONTROL_SAMPLE_MASK 0x00000001 4123 #define DDR34_F0_PHY_CONTROL_REGS_CA_PLAYBACK_CONTROL_SAMPLE_ALIGN 0 4124 #define DDR34_F0_PHY_CONTROL_REGS_CA_PLAYBACK_CONTROL_SAMPLE_BITS 1 4125 #define DDR34_F0_PHY_CONTROL_REGS_CA_PLAYBACK_CONTROL_SAMPLE_SHIFT 0 4126 4127 4128 /**************************************************************************** 4129 * DDR34_F0_PHY_CONTROL_REGS :: CA_PLAYBACK_STATUS0 4130 */ 4131 /* DDR34_F0_PHY_CONTROL_REGS :: CA_PLAYBACK_STATUS0 :: VALID [31:31] */ 4132 #define DDR34_F0_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS0_VALID_MASK 0x80000000 4133 #define DDR34_F0_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS0_VALID_ALIGN 0 4134 #define DDR34_F0_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS0_VALID_BITS 1 4135 #define DDR34_F0_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS0_VALID_SHIFT 31 4136 4137 /* DDR34_F0_PHY_CONTROL_REGS :: CA_PLAYBACK_STATUS0 :: reserved0 [30:24] */ 4138 #define DDR34_F0_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS0_RESERVED0_MASK 0x7f000000 4139 #define DDR34_F0_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS0_RESERVED0_ALIGN 0 4140 #define DDR34_F0_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS0_RESERVED0_BITS 7 4141 #define DDR34_F0_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS0_RESERVED0_SHIFT 24 4142 4143 /* DDR34_F0_PHY_CONTROL_REGS :: CA_PLAYBACK_STATUS0 :: DATA1 [23:16] */ 4144 #define DDR34_F0_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS0_DATA1_MASK 0x00ff0000 4145 #define DDR34_F0_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS0_DATA1_ALIGN 0 4146 #define DDR34_F0_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS0_DATA1_BITS 8 4147 #define DDR34_F0_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS0_DATA1_SHIFT 16 4148 4149 /* DDR34_F0_PHY_CONTROL_REGS :: CA_PLAYBACK_STATUS0 :: reserved1 [15:08] */ 4150 #define DDR34_F0_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS0_RESERVED1_MASK 0x0000ff00 4151 #define DDR34_F0_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS0_RESERVED1_ALIGN 0 4152 #define DDR34_F0_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS0_RESERVED1_BITS 8 4153 #define DDR34_F0_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS0_RESERVED1_SHIFT 8 4154 4155 /* DDR34_F0_PHY_CONTROL_REGS :: CA_PLAYBACK_STATUS0 :: DATA0 [07:00] */ 4156 #define DDR34_F0_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS0_DATA0_MASK 0x000000ff 4157 #define DDR34_F0_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS0_DATA0_ALIGN 0 4158 #define DDR34_F0_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS0_DATA0_BITS 8 4159 #define DDR34_F0_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS0_DATA0_SHIFT 0 4160 4161 4162 /**************************************************************************** 4163 * DDR34_F0_PHY_CONTROL_REGS :: CA_PLAYBACK_STATUS1 4164 */ 4165 /* DDR34_F0_PHY_CONTROL_REGS :: CA_PLAYBACK_STATUS1 :: VALID [31:31] */ 4166 #define DDR34_F0_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS1_VALID_MASK 0x80000000 4167 #define DDR34_F0_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS1_VALID_ALIGN 0 4168 #define DDR34_F0_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS1_VALID_BITS 1 4169 #define DDR34_F0_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS1_VALID_SHIFT 31 4170 4171 /* DDR34_F0_PHY_CONTROL_REGS :: CA_PLAYBACK_STATUS1 :: reserved0 [30:24] */ 4172 #define DDR34_F0_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS1_RESERVED0_MASK 0x7f000000 4173 #define DDR34_F0_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS1_RESERVED0_ALIGN 0 4174 #define DDR34_F0_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS1_RESERVED0_BITS 7 4175 #define DDR34_F0_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS1_RESERVED0_SHIFT 24 4176 4177 /* DDR34_F0_PHY_CONTROL_REGS :: CA_PLAYBACK_STATUS1 :: DATA1 [23:16] */ 4178 #define DDR34_F0_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS1_DATA1_MASK 0x00ff0000 4179 #define DDR34_F0_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS1_DATA1_ALIGN 0 4180 #define DDR34_F0_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS1_DATA1_BITS 8 4181 #define DDR34_F0_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS1_DATA1_SHIFT 16 4182 4183 /* DDR34_F0_PHY_CONTROL_REGS :: CA_PLAYBACK_STATUS1 :: reserved1 [15:08] */ 4184 #define DDR34_F0_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS1_RESERVED1_MASK 0x0000ff00 4185 #define DDR34_F0_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS1_RESERVED1_ALIGN 0 4186 #define DDR34_F0_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS1_RESERVED1_BITS 8 4187 #define DDR34_F0_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS1_RESERVED1_SHIFT 8 4188 4189 /* DDR34_F0_PHY_CONTROL_REGS :: CA_PLAYBACK_STATUS1 :: DATA0 [07:00] */ 4190 #define DDR34_F0_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS1_DATA0_MASK 0x000000ff 4191 #define DDR34_F0_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS1_DATA0_ALIGN 0 4192 #define DDR34_F0_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS1_DATA0_BITS 8 4193 #define DDR34_F0_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS1_DATA0_SHIFT 0 4194 4195 4196 /**************************************************************************** 4197 * DDR34_F0_PHY_CONTROL_REGS :: WRITE_LEVELING_CONTROL 4198 */ 4199 /* DDR34_F0_PHY_CONTROL_REGS :: WRITE_LEVELING_CONTROL :: reserved0 [31:16] */ 4200 #define DDR34_F0_PHY_CONTROL_REGS_WRITE_LEVELING_CONTROL_RESERVED0_MASK 0xffff0000 4201 #define DDR34_F0_PHY_CONTROL_REGS_WRITE_LEVELING_CONTROL_RESERVED0_ALIGN 0 4202 #define DDR34_F0_PHY_CONTROL_REGS_WRITE_LEVELING_CONTROL_RESERVED0_BITS 16 4203 #define DDR34_F0_PHY_CONTROL_REGS_WRITE_LEVELING_CONTROL_RESERVED0_SHIFT 16 4204 4205 /* DDR34_F0_PHY_CONTROL_REGS :: WRITE_LEVELING_CONTROL :: COUNT [15:08] */ 4206 #define DDR34_F0_PHY_CONTROL_REGS_WRITE_LEVELING_CONTROL_COUNT_MASK 0x0000ff00 4207 #define DDR34_F0_PHY_CONTROL_REGS_WRITE_LEVELING_CONTROL_COUNT_ALIGN 0 4208 #define DDR34_F0_PHY_CONTROL_REGS_WRITE_LEVELING_CONTROL_COUNT_BITS 8 4209 #define DDR34_F0_PHY_CONTROL_REGS_WRITE_LEVELING_CONTROL_COUNT_SHIFT 8 4210 4211 /* DDR34_F0_PHY_CONTROL_REGS :: WRITE_LEVELING_CONTROL :: reserved1 [07:03] */ 4212 #define DDR34_F0_PHY_CONTROL_REGS_WRITE_LEVELING_CONTROL_RESERVED1_MASK 0x000000f8 4213 #define DDR34_F0_PHY_CONTROL_REGS_WRITE_LEVELING_CONTROL_RESERVED1_ALIGN 0 4214 #define DDR34_F0_PHY_CONTROL_REGS_WRITE_LEVELING_CONTROL_RESERVED1_BITS 5 4215 #define DDR34_F0_PHY_CONTROL_REGS_WRITE_LEVELING_CONTROL_RESERVED1_SHIFT 3 4216 4217 /* DDR34_F0_PHY_CONTROL_REGS :: WRITE_LEVELING_CONTROL :: SAMPLE [02:02] */ 4218 #define DDR34_F0_PHY_CONTROL_REGS_WRITE_LEVELING_CONTROL_SAMPLE_MASK 0x00000004 4219 #define DDR34_F0_PHY_CONTROL_REGS_WRITE_LEVELING_CONTROL_SAMPLE_ALIGN 0 4220 #define DDR34_F0_PHY_CONTROL_REGS_WRITE_LEVELING_CONTROL_SAMPLE_BITS 1 4221 #define DDR34_F0_PHY_CONTROL_REGS_WRITE_LEVELING_CONTROL_SAMPLE_SHIFT 2 4222 4223 /* DDR34_F0_PHY_CONTROL_REGS :: WRITE_LEVELING_CONTROL :: CONTINUOUS [01:01] */ 4224 #define DDR34_F0_PHY_CONTROL_REGS_WRITE_LEVELING_CONTROL_CONTINUOUS_MASK 0x00000002 4225 #define DDR34_F0_PHY_CONTROL_REGS_WRITE_LEVELING_CONTROL_CONTINUOUS_ALIGN 0 4226 #define DDR34_F0_PHY_CONTROL_REGS_WRITE_LEVELING_CONTROL_CONTINUOUS_BITS 1 4227 #define DDR34_F0_PHY_CONTROL_REGS_WRITE_LEVELING_CONTROL_CONTINUOUS_SHIFT 1 4228 4229 /* DDR34_F0_PHY_CONTROL_REGS :: WRITE_LEVELING_CONTROL :: ENABLE [00:00] */ 4230 #define DDR34_F0_PHY_CONTROL_REGS_WRITE_LEVELING_CONTROL_ENABLE_MASK 0x00000001 4231 #define DDR34_F0_PHY_CONTROL_REGS_WRITE_LEVELING_CONTROL_ENABLE_ALIGN 0 4232 #define DDR34_F0_PHY_CONTROL_REGS_WRITE_LEVELING_CONTROL_ENABLE_BITS 1 4233 #define DDR34_F0_PHY_CONTROL_REGS_WRITE_LEVELING_CONTROL_ENABLE_SHIFT 0 4234 4235 4236 /**************************************************************************** 4237 * DDR34_F0_PHY_CONTROL_REGS :: WRITE_LEVELING_STATUS 4238 */ 4239 /* DDR34_F0_PHY_CONTROL_REGS :: WRITE_LEVELING_STATUS :: reserved0 [31:08] */ 4240 #define DDR34_F0_PHY_CONTROL_REGS_WRITE_LEVELING_STATUS_RESERVED0_MASK 0xffffff00 4241 #define DDR34_F0_PHY_CONTROL_REGS_WRITE_LEVELING_STATUS_RESERVED0_ALIGN 0 4242 #define DDR34_F0_PHY_CONTROL_REGS_WRITE_LEVELING_STATUS_RESERVED0_BITS 24 4243 #define DDR34_F0_PHY_CONTROL_REGS_WRITE_LEVELING_STATUS_RESERVED0_SHIFT 8 4244 4245 /* DDR34_F0_PHY_CONTROL_REGS :: WRITE_LEVELING_STATUS :: STATUS [07:04] */ 4246 #define DDR34_F0_PHY_CONTROL_REGS_WRITE_LEVELING_STATUS_STATUS_MASK 0x000000f0 4247 #define DDR34_F0_PHY_CONTROL_REGS_WRITE_LEVELING_STATUS_STATUS_ALIGN 0 4248 #define DDR34_F0_PHY_CONTROL_REGS_WRITE_LEVELING_STATUS_STATUS_BITS 4 4249 #define DDR34_F0_PHY_CONTROL_REGS_WRITE_LEVELING_STATUS_STATUS_SHIFT 4 4250 4251 /* DDR34_F0_PHY_CONTROL_REGS :: WRITE_LEVELING_STATUS :: reserved1 [03:01] */ 4252 #define DDR34_F0_PHY_CONTROL_REGS_WRITE_LEVELING_STATUS_RESERVED1_MASK 0x0000000e 4253 #define DDR34_F0_PHY_CONTROL_REGS_WRITE_LEVELING_STATUS_RESERVED1_ALIGN 0 4254 #define DDR34_F0_PHY_CONTROL_REGS_WRITE_LEVELING_STATUS_RESERVED1_BITS 3 4255 #define DDR34_F0_PHY_CONTROL_REGS_WRITE_LEVELING_STATUS_RESERVED1_SHIFT 1 4256 4257 /* DDR34_F0_PHY_CONTROL_REGS :: WRITE_LEVELING_STATUS :: VALID [00:00] */ 4258 #define DDR34_F0_PHY_CONTROL_REGS_WRITE_LEVELING_STATUS_VALID_MASK 0x00000001 4259 #define DDR34_F0_PHY_CONTROL_REGS_WRITE_LEVELING_STATUS_VALID_ALIGN 0 4260 #define DDR34_F0_PHY_CONTROL_REGS_WRITE_LEVELING_STATUS_VALID_BITS 1 4261 #define DDR34_F0_PHY_CONTROL_REGS_WRITE_LEVELING_STATUS_VALID_SHIFT 0 4262 4263 4264 /**************************************************************************** 4265 * DDR34_F0_PHY_CONTROL_REGS :: READ_ENABLE_CONTROL 4266 */ 4267 /* DDR34_F0_PHY_CONTROL_REGS :: READ_ENABLE_CONTROL :: reserved0 [31:13] */ 4268 #define DDR34_F0_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_RESERVED0_MASK 0xffffe000 4269 #define DDR34_F0_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_RESERVED0_ALIGN 0 4270 #define DDR34_F0_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_RESERVED0_BITS 19 4271 #define DDR34_F0_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_RESERVED0_SHIFT 13 4272 4273 /* DDR34_F0_PHY_CONTROL_REGS :: READ_ENABLE_CONTROL :: TEST_CYCLE [12:12] */ 4274 #define DDR34_F0_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_TEST_CYCLE_MASK 0x00001000 4275 #define DDR34_F0_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_TEST_CYCLE_ALIGN 0 4276 #define DDR34_F0_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_TEST_CYCLE_BITS 1 4277 #define DDR34_F0_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_TEST_CYCLE_SHIFT 12 4278 4279 /* DDR34_F0_PHY_CONTROL_REGS :: READ_ENABLE_CONTROL :: SELECT [11:08] */ 4280 #define DDR34_F0_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_SELECT_MASK 0x00000f00 4281 #define DDR34_F0_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_SELECT_ALIGN 0 4282 #define DDR34_F0_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_SELECT_BITS 4 4283 #define DDR34_F0_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_SELECT_SHIFT 8 4284 4285 /* DDR34_F0_PHY_CONTROL_REGS :: READ_ENABLE_CONTROL :: reserved1 [07:06] */ 4286 #define DDR34_F0_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_RESERVED1_MASK 0x000000c0 4287 #define DDR34_F0_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_RESERVED1_ALIGN 0 4288 #define DDR34_F0_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_RESERVED1_BITS 2 4289 #define DDR34_F0_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_RESERVED1_SHIFT 6 4290 4291 /* DDR34_F0_PHY_CONTROL_REGS :: READ_ENABLE_CONTROL :: CS_N [05:04] */ 4292 #define DDR34_F0_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_CS_N_MASK 0x00000030 4293 #define DDR34_F0_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_CS_N_ALIGN 0 4294 #define DDR34_F0_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_CS_N_BITS 2 4295 #define DDR34_F0_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_CS_N_SHIFT 4 4296 4297 /* DDR34_F0_PHY_CONTROL_REGS :: READ_ENABLE_CONTROL :: reserved2 [03:02] */ 4298 #define DDR34_F0_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_RESERVED2_MASK 0x0000000c 4299 #define DDR34_F0_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_RESERVED2_ALIGN 0 4300 #define DDR34_F0_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_RESERVED2_BITS 2 4301 #define DDR34_F0_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_RESERVED2_SHIFT 2 4302 4303 /* DDR34_F0_PHY_CONTROL_REGS :: READ_ENABLE_CONTROL :: DQS [01:01] */ 4304 #define DDR34_F0_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_DQS_MASK 0x00000002 4305 #define DDR34_F0_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_DQS_ALIGN 0 4306 #define DDR34_F0_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_DQS_BITS 1 4307 #define DDR34_F0_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_DQS_SHIFT 1 4308 4309 /* DDR34_F0_PHY_CONTROL_REGS :: READ_ENABLE_CONTROL :: ENABLE [00:00] */ 4310 #define DDR34_F0_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_ENABLE_MASK 0x00000001 4311 #define DDR34_F0_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_ENABLE_ALIGN 0 4312 #define DDR34_F0_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_ENABLE_BITS 1 4313 #define DDR34_F0_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_ENABLE_SHIFT 0 4314 4315 4316 /**************************************************************************** 4317 * DDR34_F0_PHY_CONTROL_REGS :: READ_ENABLE_STATUS 4318 */ 4319 /* DDR34_F0_PHY_CONTROL_REGS :: READ_ENABLE_STATUS :: reserved0 [31:20] */ 4320 #define DDR34_F0_PHY_CONTROL_REGS_READ_ENABLE_STATUS_RESERVED0_MASK 0xfff00000 4321 #define DDR34_F0_PHY_CONTROL_REGS_READ_ENABLE_STATUS_RESERVED0_ALIGN 0 4322 #define DDR34_F0_PHY_CONTROL_REGS_READ_ENABLE_STATUS_RESERVED0_BITS 12 4323 #define DDR34_F0_PHY_CONTROL_REGS_READ_ENABLE_STATUS_RESERVED0_SHIFT 20 4324 4325 /* DDR34_F0_PHY_CONTROL_REGS :: READ_ENABLE_STATUS :: DATA [19:12] */ 4326 #define DDR34_F0_PHY_CONTROL_REGS_READ_ENABLE_STATUS_DATA_MASK 0x000ff000 4327 #define DDR34_F0_PHY_CONTROL_REGS_READ_ENABLE_STATUS_DATA_ALIGN 0 4328 #define DDR34_F0_PHY_CONTROL_REGS_READ_ENABLE_STATUS_DATA_BITS 8 4329 #define DDR34_F0_PHY_CONTROL_REGS_READ_ENABLE_STATUS_DATA_SHIFT 12 4330 4331 /* DDR34_F0_PHY_CONTROL_REGS :: READ_ENABLE_STATUS :: reserved1 [11:08] */ 4332 #define DDR34_F0_PHY_CONTROL_REGS_READ_ENABLE_STATUS_RESERVED1_MASK 0x00000f00 4333 #define DDR34_F0_PHY_CONTROL_REGS_READ_ENABLE_STATUS_RESERVED1_ALIGN 0 4334 #define DDR34_F0_PHY_CONTROL_REGS_READ_ENABLE_STATUS_RESERVED1_BITS 4 4335 #define DDR34_F0_PHY_CONTROL_REGS_READ_ENABLE_STATUS_RESERVED1_SHIFT 8 4336 4337 /* DDR34_F0_PHY_CONTROL_REGS :: READ_ENABLE_STATUS :: BL3_STATUS [07:07] */ 4338 #define DDR34_F0_PHY_CONTROL_REGS_READ_ENABLE_STATUS_BL3_STATUS_MASK 0x00000080 4339 #define DDR34_F0_PHY_CONTROL_REGS_READ_ENABLE_STATUS_BL3_STATUS_ALIGN 0 4340 #define DDR34_F0_PHY_CONTROL_REGS_READ_ENABLE_STATUS_BL3_STATUS_BITS 1 4341 #define DDR34_F0_PHY_CONTROL_REGS_READ_ENABLE_STATUS_BL3_STATUS_SHIFT 7 4342 4343 /* DDR34_F0_PHY_CONTROL_REGS :: READ_ENABLE_STATUS :: BL2_STATUS [06:06] */ 4344 #define DDR34_F0_PHY_CONTROL_REGS_READ_ENABLE_STATUS_BL2_STATUS_MASK 0x00000040 4345 #define DDR34_F0_PHY_CONTROL_REGS_READ_ENABLE_STATUS_BL2_STATUS_ALIGN 0 4346 #define DDR34_F0_PHY_CONTROL_REGS_READ_ENABLE_STATUS_BL2_STATUS_BITS 1 4347 #define DDR34_F0_PHY_CONTROL_REGS_READ_ENABLE_STATUS_BL2_STATUS_SHIFT 6 4348 4349 /* DDR34_F0_PHY_CONTROL_REGS :: READ_ENABLE_STATUS :: BL1_STATUS [05:05] */ 4350 #define DDR34_F0_PHY_CONTROL_REGS_READ_ENABLE_STATUS_BL1_STATUS_MASK 0x00000020 4351 #define DDR34_F0_PHY_CONTROL_REGS_READ_ENABLE_STATUS_BL1_STATUS_ALIGN 0 4352 #define DDR34_F0_PHY_CONTROL_REGS_READ_ENABLE_STATUS_BL1_STATUS_BITS 1 4353 #define DDR34_F0_PHY_CONTROL_REGS_READ_ENABLE_STATUS_BL1_STATUS_SHIFT 5 4354 4355 /* DDR34_F0_PHY_CONTROL_REGS :: READ_ENABLE_STATUS :: BL0_STATUS [04:04] */ 4356 #define DDR34_F0_PHY_CONTROL_REGS_READ_ENABLE_STATUS_BL0_STATUS_MASK 0x00000010 4357 #define DDR34_F0_PHY_CONTROL_REGS_READ_ENABLE_STATUS_BL0_STATUS_ALIGN 0 4358 #define DDR34_F0_PHY_CONTROL_REGS_READ_ENABLE_STATUS_BL0_STATUS_BITS 1 4359 #define DDR34_F0_PHY_CONTROL_REGS_READ_ENABLE_STATUS_BL0_STATUS_SHIFT 4 4360 4361 /* DDR34_F0_PHY_CONTROL_REGS :: READ_ENABLE_STATUS :: reserved2 [03:01] */ 4362 #define DDR34_F0_PHY_CONTROL_REGS_READ_ENABLE_STATUS_RESERVED2_MASK 0x0000000e 4363 #define DDR34_F0_PHY_CONTROL_REGS_READ_ENABLE_STATUS_RESERVED2_ALIGN 0 4364 #define DDR34_F0_PHY_CONTROL_REGS_READ_ENABLE_STATUS_RESERVED2_BITS 3 4365 #define DDR34_F0_PHY_CONTROL_REGS_READ_ENABLE_STATUS_RESERVED2_SHIFT 1 4366 4367 /* DDR34_F0_PHY_CONTROL_REGS :: READ_ENABLE_STATUS :: VALID [00:00] */ 4368 #define DDR34_F0_PHY_CONTROL_REGS_READ_ENABLE_STATUS_VALID_MASK 0x00000001 4369 #define DDR34_F0_PHY_CONTROL_REGS_READ_ENABLE_STATUS_VALID_ALIGN 0 4370 #define DDR34_F0_PHY_CONTROL_REGS_READ_ENABLE_STATUS_VALID_BITS 1 4371 #define DDR34_F0_PHY_CONTROL_REGS_READ_ENABLE_STATUS_VALID_SHIFT 0 4372 4373 4374 /**************************************************************************** 4375 * DDR34_F0_PHY_CONTROL_REGS :: VIRTUAL_VTT_CONTROL 4376 */ 4377 /* DDR34_F0_PHY_CONTROL_REGS :: VIRTUAL_VTT_CONTROL :: reserved0 [31:12] */ 4378 #define DDR34_F0_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_RESERVED0_MASK 0xfffff000 4379 #define DDR34_F0_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_RESERVED0_ALIGN 0 4380 #define DDR34_F0_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_RESERVED0_BITS 20 4381 #define DDR34_F0_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_RESERVED0_SHIFT 12 4382 4383 /* DDR34_F0_PHY_CONTROL_REGS :: VIRTUAL_VTT_CONTROL :: reserved_for_eco1 [11:08] */ 4384 #define DDR34_F0_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_RESERVED_FOR_ECO1_MASK 0x00000f00 4385 #define DDR34_F0_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_RESERVED_FOR_ECO1_ALIGN 0 4386 #define DDR34_F0_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_RESERVED_FOR_ECO1_BITS 4 4387 #define DDR34_F0_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_RESERVED_FOR_ECO1_SHIFT 8 4388 4389 /* DDR34_F0_PHY_CONTROL_REGS :: VIRTUAL_VTT_CONTROL :: MAX_NOISE [07:07] */ 4390 #define DDR34_F0_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_MAX_NOISE_MASK 0x00000080 4391 #define DDR34_F0_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_MAX_NOISE_ALIGN 0 4392 #define DDR34_F0_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_MAX_NOISE_BITS 1 4393 #define DDR34_F0_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_MAX_NOISE_SHIFT 7 4394 4395 /* DDR34_F0_PHY_CONTROL_REGS :: VIRTUAL_VTT_CONTROL :: LOW_NOISE [06:06] */ 4396 #define DDR34_F0_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_LOW_NOISE_MASK 0x00000040 4397 #define DDR34_F0_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_LOW_NOISE_ALIGN 0 4398 #define DDR34_F0_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_LOW_NOISE_BITS 1 4399 #define DDR34_F0_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_LOW_NOISE_SHIFT 6 4400 4401 /* DDR34_F0_PHY_CONTROL_REGS :: VIRTUAL_VTT_CONTROL :: LOW_VTT [05:05] */ 4402 #define DDR34_F0_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_LOW_VTT_MASK 0x00000020 4403 #define DDR34_F0_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_LOW_VTT_ALIGN 0 4404 #define DDR34_F0_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_LOW_VTT_BITS 1 4405 #define DDR34_F0_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_LOW_VTT_SHIFT 5 4406 4407 /* DDR34_F0_PHY_CONTROL_REGS :: VIRTUAL_VTT_CONTROL :: HIGH_VTT [04:04] */ 4408 #define DDR34_F0_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_HIGH_VTT_MASK 0x00000010 4409 #define DDR34_F0_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_HIGH_VTT_ALIGN 0 4410 #define DDR34_F0_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_HIGH_VTT_BITS 1 4411 #define DDR34_F0_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_HIGH_VTT_SHIFT 4 4412 4413 /* DDR34_F0_PHY_CONTROL_REGS :: VIRTUAL_VTT_CONTROL :: ERROR_RESET [03:03] */ 4414 #define DDR34_F0_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_ERROR_RESET_MASK 0x00000008 4415 #define DDR34_F0_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_ERROR_RESET_ALIGN 0 4416 #define DDR34_F0_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_ERROR_RESET_BITS 1 4417 #define DDR34_F0_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_ERROR_RESET_SHIFT 3 4418 4419 /* DDR34_F0_PHY_CONTROL_REGS :: VIRTUAL_VTT_CONTROL :: ENABLE_CTL_IDLE [02:02] */ 4420 #define DDR34_F0_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_ENABLE_CTL_IDLE_MASK 0x00000004 4421 #define DDR34_F0_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_ENABLE_CTL_IDLE_ALIGN 0 4422 #define DDR34_F0_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_ENABLE_CTL_IDLE_BITS 1 4423 #define DDR34_F0_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_ENABLE_CTL_IDLE_SHIFT 2 4424 4425 /* DDR34_F0_PHY_CONTROL_REGS :: VIRTUAL_VTT_CONTROL :: ENABLE_CS_IDLE [01:01] */ 4426 #define DDR34_F0_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_ENABLE_CS_IDLE_MASK 0x00000002 4427 #define DDR34_F0_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_ENABLE_CS_IDLE_ALIGN 0 4428 #define DDR34_F0_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_ENABLE_CS_IDLE_BITS 1 4429 #define DDR34_F0_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_ENABLE_CS_IDLE_SHIFT 1 4430 4431 /* DDR34_F0_PHY_CONTROL_REGS :: VIRTUAL_VTT_CONTROL :: ENABLE_CKE_IDLE [00:00] */ 4432 #define DDR34_F0_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_ENABLE_CKE_IDLE_MASK 0x00000001 4433 #define DDR34_F0_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_ENABLE_CKE_IDLE_ALIGN 0 4434 #define DDR34_F0_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_ENABLE_CKE_IDLE_BITS 1 4435 #define DDR34_F0_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_ENABLE_CKE_IDLE_SHIFT 0 4436 4437 4438 /**************************************************************************** 4439 * DDR34_F0_PHY_CONTROL_REGS :: VIRTUAL_VTT_STATUS 4440 */ 4441 /* DDR34_F0_PHY_CONTROL_REGS :: VIRTUAL_VTT_STATUS :: reserved0 [31:19] */ 4442 #define DDR34_F0_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS_RESERVED0_MASK 0xfff80000 4443 #define DDR34_F0_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS_RESERVED0_ALIGN 0 4444 #define DDR34_F0_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS_RESERVED0_BITS 13 4445 #define DDR34_F0_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS_RESERVED0_SHIFT 19 4446 4447 /* DDR34_F0_PHY_CONTROL_REGS :: VIRTUAL_VTT_STATUS :: ERROR [18:03] */ 4448 #define DDR34_F0_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS_ERROR_MASK 0x0007fff8 4449 #define DDR34_F0_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS_ERROR_ALIGN 0 4450 #define DDR34_F0_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS_ERROR_BITS 16 4451 #define DDR34_F0_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS_ERROR_SHIFT 3 4452 4453 /* DDR34_F0_PHY_CONTROL_REGS :: VIRTUAL_VTT_STATUS :: ERROR_LOW [02:02] */ 4454 #define DDR34_F0_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS_ERROR_LOW_MASK 0x00000004 4455 #define DDR34_F0_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS_ERROR_LOW_ALIGN 0 4456 #define DDR34_F0_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS_ERROR_LOW_BITS 1 4457 #define DDR34_F0_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS_ERROR_LOW_SHIFT 2 4458 4459 /* DDR34_F0_PHY_CONTROL_REGS :: VIRTUAL_VTT_STATUS :: ERROR_HIGH [01:01] */ 4460 #define DDR34_F0_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS_ERROR_HIGH_MASK 0x00000002 4461 #define DDR34_F0_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS_ERROR_HIGH_ALIGN 0 4462 #define DDR34_F0_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS_ERROR_HIGH_BITS 1 4463 #define DDR34_F0_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS_ERROR_HIGH_SHIFT 1 4464 4465 /* DDR34_F0_PHY_CONTROL_REGS :: VIRTUAL_VTT_STATUS :: READY [00:00] */ 4466 #define DDR34_F0_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS_READY_MASK 0x00000001 4467 #define DDR34_F0_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS_READY_ALIGN 0 4468 #define DDR34_F0_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS_READY_BITS 1 4469 #define DDR34_F0_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS_READY_SHIFT 0 4470 4471 4472 /**************************************************************************** 4473 * DDR34_F0_PHY_CONTROL_REGS :: VIRTUAL_VTT_CONNECTIONS 4474 */ 4475 /* DDR34_F0_PHY_CONTROL_REGS :: VIRTUAL_VTT_CONNECTIONS :: reserved0 [31:31] */ 4476 #define DDR34_F0_PHY_CONTROL_REGS_VIRTUAL_VTT_CONNECTIONS_RESERVED0_MASK 0x80000000 4477 #define DDR34_F0_PHY_CONTROL_REGS_VIRTUAL_VTT_CONNECTIONS_RESERVED0_ALIGN 0 4478 #define DDR34_F0_PHY_CONTROL_REGS_VIRTUAL_VTT_CONNECTIONS_RESERVED0_BITS 1 4479 #define DDR34_F0_PHY_CONTROL_REGS_VIRTUAL_VTT_CONNECTIONS_RESERVED0_SHIFT 31 4480 4481 /* DDR34_F0_PHY_CONTROL_REGS :: VIRTUAL_VTT_CONNECTIONS :: MASK [30:00] */ 4482 #define DDR34_F0_PHY_CONTROL_REGS_VIRTUAL_VTT_CONNECTIONS_MASK_MASK 0x7fffffff 4483 #define DDR34_F0_PHY_CONTROL_REGS_VIRTUAL_VTT_CONNECTIONS_MASK_ALIGN 0 4484 #define DDR34_F0_PHY_CONTROL_REGS_VIRTUAL_VTT_CONNECTIONS_MASK_BITS 31 4485 #define DDR34_F0_PHY_CONTROL_REGS_VIRTUAL_VTT_CONNECTIONS_MASK_SHIFT 0 4486 4487 4488 /**************************************************************************** 4489 * DDR34_F0_PHY_CONTROL_REGS :: VIRTUAL_VTT_OVERRIDE 4490 */ 4491 /* DDR34_F0_PHY_CONTROL_REGS :: VIRTUAL_VTT_OVERRIDE :: reserved0 [31:31] */ 4492 #define DDR34_F0_PHY_CONTROL_REGS_VIRTUAL_VTT_OVERRIDE_RESERVED0_MASK 0x80000000 4493 #define DDR34_F0_PHY_CONTROL_REGS_VIRTUAL_VTT_OVERRIDE_RESERVED0_ALIGN 0 4494 #define DDR34_F0_PHY_CONTROL_REGS_VIRTUAL_VTT_OVERRIDE_RESERVED0_BITS 1 4495 #define DDR34_F0_PHY_CONTROL_REGS_VIRTUAL_VTT_OVERRIDE_RESERVED0_SHIFT 31 4496 4497 /* DDR34_F0_PHY_CONTROL_REGS :: VIRTUAL_VTT_OVERRIDE :: MASK [30:00] */ 4498 #define DDR34_F0_PHY_CONTROL_REGS_VIRTUAL_VTT_OVERRIDE_MASK_MASK 0x7fffffff 4499 #define DDR34_F0_PHY_CONTROL_REGS_VIRTUAL_VTT_OVERRIDE_MASK_ALIGN 0 4500 #define DDR34_F0_PHY_CONTROL_REGS_VIRTUAL_VTT_OVERRIDE_MASK_BITS 31 4501 #define DDR34_F0_PHY_CONTROL_REGS_VIRTUAL_VTT_OVERRIDE_MASK_SHIFT 0 4502 4503 4504 /**************************************************************************** 4505 * DDR34_F0_PHY_CONTROL_REGS :: VREF_DAC_CONTROL 4506 */ 4507 /* DDR34_F0_PHY_CONTROL_REGS :: VREF_DAC_CONTROL :: reserved0 [31:21] */ 4508 #define DDR34_F0_PHY_CONTROL_REGS_VREF_DAC_CONTROL_RESERVED0_MASK 0xffe00000 4509 #define DDR34_F0_PHY_CONTROL_REGS_VREF_DAC_CONTROL_RESERVED0_ALIGN 0 4510 #define DDR34_F0_PHY_CONTROL_REGS_VREF_DAC_CONTROL_RESERVED0_BITS 11 4511 #define DDR34_F0_PHY_CONTROL_REGS_VREF_DAC_CONTROL_RESERVED0_SHIFT 21 4512 4513 /* DDR34_F0_PHY_CONTROL_REGS :: VREF_DAC_CONTROL :: AUX_GT_INT [20:20] */ 4514 #define DDR34_F0_PHY_CONTROL_REGS_VREF_DAC_CONTROL_AUX_GT_INT_MASK 0x00100000 4515 #define DDR34_F0_PHY_CONTROL_REGS_VREF_DAC_CONTROL_AUX_GT_INT_ALIGN 0 4516 #define DDR34_F0_PHY_CONTROL_REGS_VREF_DAC_CONTROL_AUX_GT_INT_BITS 1 4517 #define DDR34_F0_PHY_CONTROL_REGS_VREF_DAC_CONTROL_AUX_GT_INT_SHIFT 20 4518 4519 /* DDR34_F0_PHY_CONTROL_REGS :: VREF_DAC_CONTROL :: TESTOUT_MUX_CTL [19:17] */ 4520 #define DDR34_F0_PHY_CONTROL_REGS_VREF_DAC_CONTROL_TESTOUT_MUX_CTL_MASK 0x000e0000 4521 #define DDR34_F0_PHY_CONTROL_REGS_VREF_DAC_CONTROL_TESTOUT_MUX_CTL_ALIGN 0 4522 #define DDR34_F0_PHY_CONTROL_REGS_VREF_DAC_CONTROL_TESTOUT_MUX_CTL_BITS 3 4523 #define DDR34_F0_PHY_CONTROL_REGS_VREF_DAC_CONTROL_TESTOUT_MUX_CTL_SHIFT 17 4524 4525 /* DDR34_F0_PHY_CONTROL_REGS :: VREF_DAC_CONTROL :: TEST [16:16] */ 4526 #define DDR34_F0_PHY_CONTROL_REGS_VREF_DAC_CONTROL_TEST_MASK 0x00010000 4527 #define DDR34_F0_PHY_CONTROL_REGS_VREF_DAC_CONTROL_TEST_ALIGN 0 4528 #define DDR34_F0_PHY_CONTROL_REGS_VREF_DAC_CONTROL_TEST_BITS 1 4529 #define DDR34_F0_PHY_CONTROL_REGS_VREF_DAC_CONTROL_TEST_SHIFT 16 4530 4531 /* DDR34_F0_PHY_CONTROL_REGS :: VREF_DAC_CONTROL :: PDN3 [15:15] */ 4532 #define DDR34_F0_PHY_CONTROL_REGS_VREF_DAC_CONTROL_PDN3_MASK 0x00008000 4533 #define DDR34_F0_PHY_CONTROL_REGS_VREF_DAC_CONTROL_PDN3_ALIGN 0 4534 #define DDR34_F0_PHY_CONTROL_REGS_VREF_DAC_CONTROL_PDN3_BITS 1 4535 #define DDR34_F0_PHY_CONTROL_REGS_VREF_DAC_CONTROL_PDN3_SHIFT 15 4536 4537 /* DDR34_F0_PHY_CONTROL_REGS :: VREF_DAC_CONTROL :: PDN2 [14:14] */ 4538 #define DDR34_F0_PHY_CONTROL_REGS_VREF_DAC_CONTROL_PDN2_MASK 0x00004000 4539 #define DDR34_F0_PHY_CONTROL_REGS_VREF_DAC_CONTROL_PDN2_ALIGN 0 4540 #define DDR34_F0_PHY_CONTROL_REGS_VREF_DAC_CONTROL_PDN2_BITS 1 4541 #define DDR34_F0_PHY_CONTROL_REGS_VREF_DAC_CONTROL_PDN2_SHIFT 14 4542 4543 /* DDR34_F0_PHY_CONTROL_REGS :: VREF_DAC_CONTROL :: PDN1 [13:13] */ 4544 #define DDR34_F0_PHY_CONTROL_REGS_VREF_DAC_CONTROL_PDN1_MASK 0x00002000 4545 #define DDR34_F0_PHY_CONTROL_REGS_VREF_DAC_CONTROL_PDN1_ALIGN 0 4546 #define DDR34_F0_PHY_CONTROL_REGS_VREF_DAC_CONTROL_PDN1_BITS 1 4547 #define DDR34_F0_PHY_CONTROL_REGS_VREF_DAC_CONTROL_PDN1_SHIFT 13 4548 4549 /* DDR34_F0_PHY_CONTROL_REGS :: VREF_DAC_CONTROL :: PDN0 [12:12] */ 4550 #define DDR34_F0_PHY_CONTROL_REGS_VREF_DAC_CONTROL_PDN0_MASK 0x00001000 4551 #define DDR34_F0_PHY_CONTROL_REGS_VREF_DAC_CONTROL_PDN0_ALIGN 0 4552 #define DDR34_F0_PHY_CONTROL_REGS_VREF_DAC_CONTROL_PDN0_BITS 1 4553 #define DDR34_F0_PHY_CONTROL_REGS_VREF_DAC_CONTROL_PDN0_SHIFT 12 4554 4555 /* DDR34_F0_PHY_CONTROL_REGS :: VREF_DAC_CONTROL :: DAC1 [11:06] */ 4556 #define DDR34_F0_PHY_CONTROL_REGS_VREF_DAC_CONTROL_DAC1_MASK 0x00000fc0 4557 #define DDR34_F0_PHY_CONTROL_REGS_VREF_DAC_CONTROL_DAC1_ALIGN 0 4558 #define DDR34_F0_PHY_CONTROL_REGS_VREF_DAC_CONTROL_DAC1_BITS 6 4559 #define DDR34_F0_PHY_CONTROL_REGS_VREF_DAC_CONTROL_DAC1_SHIFT 6 4560 4561 /* DDR34_F0_PHY_CONTROL_REGS :: VREF_DAC_CONTROL :: DAC0 [05:00] */ 4562 #define DDR34_F0_PHY_CONTROL_REGS_VREF_DAC_CONTROL_DAC0_MASK 0x0000003f 4563 #define DDR34_F0_PHY_CONTROL_REGS_VREF_DAC_CONTROL_DAC0_ALIGN 0 4564 #define DDR34_F0_PHY_CONTROL_REGS_VREF_DAC_CONTROL_DAC0_BITS 6 4565 #define DDR34_F0_PHY_CONTROL_REGS_VREF_DAC_CONTROL_DAC0_SHIFT 0 4566 4567 4568 /**************************************************************************** 4569 * DDR34_F0_PHY_CONTROL_REGS :: PHYBIST_CNTRL 4570 */ 4571 /* DDR34_F0_PHY_CONTROL_REGS :: PHYBIST_CNTRL :: reserved0 [31:30] */ 4572 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_CNTRL_RESERVED0_MASK 0xc0000000 4573 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_CNTRL_RESERVED0_ALIGN 0 4574 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_CNTRL_RESERVED0_BITS 2 4575 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_CNTRL_RESERVED0_SHIFT 30 4576 4577 /* DDR34_F0_PHY_CONTROL_REGS :: PHYBIST_CNTRL :: PATTERN_SEL [29:28] */ 4578 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_CNTRL_PATTERN_SEL_MASK 0x30000000 4579 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_CNTRL_PATTERN_SEL_ALIGN 0 4580 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_CNTRL_PATTERN_SEL_BITS 2 4581 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_CNTRL_PATTERN_SEL_SHIFT 28 4582 4583 /* DDR34_F0_PHY_CONTROL_REGS :: PHYBIST_CNTRL :: FORCE_DQ_ERROR_SEL [27:24] */ 4584 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_CNTRL_FORCE_DQ_ERROR_SEL_MASK 0x0f000000 4585 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_CNTRL_FORCE_DQ_ERROR_SEL_ALIGN 0 4586 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_CNTRL_FORCE_DQ_ERROR_SEL_BITS 4 4587 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_CNTRL_FORCE_DQ_ERROR_SEL_SHIFT 24 4588 4589 /* DDR34_F0_PHY_CONTROL_REGS :: PHYBIST_CNTRL :: reserved1 [23:23] */ 4590 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_CNTRL_RESERVED1_MASK 0x00800000 4591 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_CNTRL_RESERVED1_ALIGN 0 4592 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_CNTRL_RESERVED1_BITS 1 4593 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_CNTRL_RESERVED1_SHIFT 23 4594 4595 /* DDR34_F0_PHY_CONTROL_REGS :: PHYBIST_CNTRL :: FORCE_BL_ERROR_SEL [22:20] */ 4596 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_CNTRL_FORCE_BL_ERROR_SEL_MASK 0x00700000 4597 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_CNTRL_FORCE_BL_ERROR_SEL_ALIGN 0 4598 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_CNTRL_FORCE_BL_ERROR_SEL_BITS 3 4599 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_CNTRL_FORCE_BL_ERROR_SEL_SHIFT 20 4600 4601 /* DDR34_F0_PHY_CONTROL_REGS :: PHYBIST_CNTRL :: reserved2 [19:17] */ 4602 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_CNTRL_RESERVED2_MASK 0x000e0000 4603 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_CNTRL_RESERVED2_ALIGN 0 4604 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_CNTRL_RESERVED2_BITS 3 4605 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_CNTRL_RESERVED2_SHIFT 17 4606 4607 /* DDR34_F0_PHY_CONTROL_REGS :: PHYBIST_CNTRL :: FORCE_CTL_ERROR_SEL [16:12] */ 4608 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_CNTRL_FORCE_CTL_ERROR_SEL_MASK 0x0001f000 4609 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_CNTRL_FORCE_CTL_ERROR_SEL_ALIGN 0 4610 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_CNTRL_FORCE_CTL_ERROR_SEL_BITS 5 4611 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_CNTRL_FORCE_CTL_ERROR_SEL_SHIFT 12 4612 4613 /* DDR34_F0_PHY_CONTROL_REGS :: PHYBIST_CNTRL :: reserved3 [11:10] */ 4614 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_CNTRL_RESERVED3_MASK 0x00000c00 4615 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_CNTRL_RESERVED3_ALIGN 0 4616 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_CNTRL_RESERVED3_BITS 2 4617 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_CNTRL_RESERVED3_SHIFT 10 4618 4619 /* DDR34_F0_PHY_CONTROL_REGS :: PHYBIST_CNTRL :: FORCE_DAT_ERROR [09:09] */ 4620 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_CNTRL_FORCE_DAT_ERROR_MASK 0x00000200 4621 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_CNTRL_FORCE_DAT_ERROR_ALIGN 0 4622 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_CNTRL_FORCE_DAT_ERROR_BITS 1 4623 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_CNTRL_FORCE_DAT_ERROR_SHIFT 9 4624 4625 /* DDR34_F0_PHY_CONTROL_REGS :: PHYBIST_CNTRL :: FORCE_CTL_ERROR [08:08] */ 4626 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_CNTRL_FORCE_CTL_ERROR_MASK 0x00000100 4627 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_CNTRL_FORCE_CTL_ERROR_ALIGN 0 4628 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_CNTRL_FORCE_CTL_ERROR_BITS 1 4629 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_CNTRL_FORCE_CTL_ERROR_SHIFT 8 4630 4631 /* DDR34_F0_PHY_CONTROL_REGS :: PHYBIST_CNTRL :: SSO [07:06] */ 4632 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_CNTRL_SSO_MASK 0x000000c0 4633 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_CNTRL_SSO_ALIGN 0 4634 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_CNTRL_SSO_BITS 2 4635 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_CNTRL_SSO_SHIFT 6 4636 4637 /* DDR34_F0_PHY_CONTROL_REGS :: PHYBIST_CNTRL :: LENGTH [05:04] */ 4638 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_CNTRL_LENGTH_MASK 0x00000030 4639 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_CNTRL_LENGTH_ALIGN 0 4640 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_CNTRL_LENGTH_BITS 2 4641 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_CNTRL_LENGTH_SHIFT 4 4642 4643 /* DDR34_F0_PHY_CONTROL_REGS :: PHYBIST_CNTRL :: MODE [03:01] */ 4644 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_CNTRL_MODE_MASK 0x0000000e 4645 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_CNTRL_MODE_ALIGN 0 4646 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_CNTRL_MODE_BITS 3 4647 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_CNTRL_MODE_SHIFT 1 4648 4649 /* DDR34_F0_PHY_CONTROL_REGS :: PHYBIST_CNTRL :: ENABLE [00:00] */ 4650 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_CNTRL_ENABLE_MASK 0x00000001 4651 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_CNTRL_ENABLE_ALIGN 0 4652 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_CNTRL_ENABLE_BITS 1 4653 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_CNTRL_ENABLE_SHIFT 0 4654 4655 4656 /**************************************************************************** 4657 * DDR34_F0_PHY_CONTROL_REGS :: PHYBIST_SEED 4658 */ 4659 /* DDR34_F0_PHY_CONTROL_REGS :: PHYBIST_SEED :: SEED [31:00] */ 4660 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_SEED_SEED_MASK 0xffffffff 4661 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_SEED_SEED_ALIGN 0 4662 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_SEED_SEED_BITS 32 4663 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_SEED_SEED_SHIFT 0 4664 4665 4666 /**************************************************************************** 4667 * DDR34_F0_PHY_CONTROL_REGS :: PHYBIST_CA_MASK 4668 */ 4669 /* DDR34_F0_PHY_CONTROL_REGS :: PHYBIST_CA_MASK :: MASK [31:00] */ 4670 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_CA_MASK_MASK_MASK 0xffffffff 4671 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_CA_MASK_MASK_ALIGN 0 4672 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_CA_MASK_MASK_BITS 32 4673 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_CA_MASK_MASK_SHIFT 0 4674 4675 4676 /**************************************************************************** 4677 * DDR34_F0_PHY_CONTROL_REGS :: PHYBIST_DQ_MASK1 4678 */ 4679 /* DDR34_F0_PHY_CONTROL_REGS :: PHYBIST_DQ_MASK1 :: MASK [31:00] */ 4680 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_DQ_MASK1_MASK_MASK 0xffffffff 4681 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_DQ_MASK1_MASK_ALIGN 0 4682 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_DQ_MASK1_MASK_BITS 32 4683 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_DQ_MASK1_MASK_SHIFT 0 4684 4685 4686 /**************************************************************************** 4687 * DDR34_F0_PHY_CONTROL_REGS :: PHYBIST_DQ_MASK2 4688 */ 4689 /* DDR34_F0_PHY_CONTROL_REGS :: PHYBIST_DQ_MASK2 :: reserved0 [31:16] */ 4690 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_DQ_MASK2_RESERVED0_MASK 0xffff0000 4691 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_DQ_MASK2_RESERVED0_ALIGN 0 4692 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_DQ_MASK2_RESERVED0_BITS 16 4693 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_DQ_MASK2_RESERVED0_SHIFT 16 4694 4695 /* DDR34_F0_PHY_CONTROL_REGS :: PHYBIST_DQ_MASK2 :: ALERT_MASK [15:12] */ 4696 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_DQ_MASK2_ALERT_MASK_MASK 0x0000f000 4697 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_DQ_MASK2_ALERT_MASK_ALIGN 0 4698 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_DQ_MASK2_ALERT_MASK_BITS 4 4699 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_DQ_MASK2_ALERT_MASK_SHIFT 12 4700 4701 /* DDR34_F0_PHY_CONTROL_REGS :: PHYBIST_DQ_MASK2 :: reserved1 [11:08] */ 4702 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_DQ_MASK2_RESERVED1_MASK 0x00000f00 4703 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_DQ_MASK2_RESERVED1_ALIGN 0 4704 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_DQ_MASK2_RESERVED1_BITS 4 4705 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_DQ_MASK2_RESERVED1_SHIFT 8 4706 4707 /* DDR34_F0_PHY_CONTROL_REGS :: PHYBIST_DQ_MASK2 :: DM_MASK [07:04] */ 4708 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_DQ_MASK2_DM_MASK_MASK 0x000000f0 4709 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_DQ_MASK2_DM_MASK_ALIGN 0 4710 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_DQ_MASK2_DM_MASK_BITS 4 4711 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_DQ_MASK2_DM_MASK_SHIFT 4 4712 4713 /* DDR34_F0_PHY_CONTROL_REGS :: PHYBIST_DQ_MASK2 :: reserved2 [03:00] */ 4714 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_DQ_MASK2_RESERVED2_MASK 0x0000000f 4715 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_DQ_MASK2_RESERVED2_ALIGN 0 4716 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_DQ_MASK2_RESERVED2_BITS 4 4717 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_DQ_MASK2_RESERVED2_SHIFT 0 4718 4719 4720 /**************************************************************************** 4721 * DDR34_F0_PHY_CONTROL_REGS :: PHYBIST_STATUS 4722 */ 4723 /* DDR34_F0_PHY_CONTROL_REGS :: PHYBIST_STATUS :: reserved0 [31:04] */ 4724 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_STATUS_RESERVED0_MASK 0xfffffff0 4725 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_STATUS_RESERVED0_ALIGN 0 4726 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_STATUS_RESERVED0_BITS 28 4727 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_STATUS_RESERVED0_SHIFT 4 4728 4729 /* DDR34_F0_PHY_CONTROL_REGS :: PHYBIST_STATUS :: DAT_PASS [03:03] */ 4730 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_STATUS_DAT_PASS_MASK 0x00000008 4731 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_STATUS_DAT_PASS_ALIGN 0 4732 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_STATUS_DAT_PASS_BITS 1 4733 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_STATUS_DAT_PASS_SHIFT 3 4734 4735 /* DDR34_F0_PHY_CONTROL_REGS :: PHYBIST_STATUS :: CTL_PASS [02:02] */ 4736 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_STATUS_CTL_PASS_MASK 0x00000004 4737 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_STATUS_CTL_PASS_ALIGN 0 4738 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_STATUS_CTL_PASS_BITS 1 4739 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_STATUS_CTL_PASS_SHIFT 2 4740 4741 /* DDR34_F0_PHY_CONTROL_REGS :: PHYBIST_STATUS :: DAT_DONE [01:01] */ 4742 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_STATUS_DAT_DONE_MASK 0x00000002 4743 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_STATUS_DAT_DONE_ALIGN 0 4744 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_STATUS_DAT_DONE_BITS 1 4745 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_STATUS_DAT_DONE_SHIFT 1 4746 4747 /* DDR34_F0_PHY_CONTROL_REGS :: PHYBIST_STATUS :: CTL_DONE [00:00] */ 4748 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_STATUS_CTL_DONE_MASK 0x00000001 4749 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_STATUS_CTL_DONE_ALIGN 0 4750 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_STATUS_CTL_DONE_BITS 1 4751 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_STATUS_CTL_DONE_SHIFT 0 4752 4753 4754 /**************************************************************************** 4755 * DDR34_F0_PHY_CONTROL_REGS :: PHYBIST_CTL_STATUS 4756 */ 4757 /* DDR34_F0_PHY_CONTROL_REGS :: PHYBIST_CTL_STATUS :: reserved0 [31:31] */ 4758 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_CTL_STATUS_RESERVED0_MASK 0x80000000 4759 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_CTL_STATUS_RESERVED0_ALIGN 0 4760 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_CTL_STATUS_RESERVED0_BITS 1 4761 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_CTL_STATUS_RESERVED0_SHIFT 31 4762 4763 /* DDR34_F0_PHY_CONTROL_REGS :: PHYBIST_CTL_STATUS :: CTL_ERRORS [30:00] */ 4764 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_CTL_STATUS_CTL_ERRORS_MASK 0x7fffffff 4765 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_CTL_STATUS_CTL_ERRORS_ALIGN 0 4766 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_CTL_STATUS_CTL_ERRORS_BITS 31 4767 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_CTL_STATUS_CTL_ERRORS_SHIFT 0 4768 4769 4770 /**************************************************************************** 4771 * DDR34_F0_PHY_CONTROL_REGS :: PHYBIST_BL0_STATUS 4772 */ 4773 /* DDR34_F0_PHY_CONTROL_REGS :: PHYBIST_BL0_STATUS :: reserved0 [31:10] */ 4774 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_BL0_STATUS_RESERVED0_MASK 0xfffffc00 4775 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_BL0_STATUS_RESERVED0_ALIGN 0 4776 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_BL0_STATUS_RESERVED0_BITS 22 4777 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_BL0_STATUS_RESERVED0_SHIFT 10 4778 4779 /* DDR34_F0_PHY_CONTROL_REGS :: PHYBIST_BL0_STATUS :: ALERT [09:09] */ 4780 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_BL0_STATUS_ALERT_MASK 0x00000200 4781 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_BL0_STATUS_ALERT_ALIGN 0 4782 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_BL0_STATUS_ALERT_BITS 1 4783 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_BL0_STATUS_ALERT_SHIFT 9 4784 4785 /* DDR34_F0_PHY_CONTROL_REGS :: PHYBIST_BL0_STATUS :: DM [08:08] */ 4786 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_BL0_STATUS_DM_MASK 0x00000100 4787 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_BL0_STATUS_DM_ALIGN 0 4788 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_BL0_STATUS_DM_BITS 1 4789 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_BL0_STATUS_DM_SHIFT 8 4790 4791 /* DDR34_F0_PHY_CONTROL_REGS :: PHYBIST_BL0_STATUS :: DQ [07:00] */ 4792 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_BL0_STATUS_DQ_MASK 0x000000ff 4793 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_BL0_STATUS_DQ_ALIGN 0 4794 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_BL0_STATUS_DQ_BITS 8 4795 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_BL0_STATUS_DQ_SHIFT 0 4796 4797 4798 /**************************************************************************** 4799 * DDR34_F0_PHY_CONTROL_REGS :: PHYBIST_BL1_STATUS 4800 */ 4801 /* DDR34_F0_PHY_CONTROL_REGS :: PHYBIST_BL1_STATUS :: reserved0 [31:10] */ 4802 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_BL1_STATUS_RESERVED0_MASK 0xfffffc00 4803 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_BL1_STATUS_RESERVED0_ALIGN 0 4804 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_BL1_STATUS_RESERVED0_BITS 22 4805 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_BL1_STATUS_RESERVED0_SHIFT 10 4806 4807 /* DDR34_F0_PHY_CONTROL_REGS :: PHYBIST_BL1_STATUS :: ALERT [09:09] */ 4808 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_BL1_STATUS_ALERT_MASK 0x00000200 4809 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_BL1_STATUS_ALERT_ALIGN 0 4810 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_BL1_STATUS_ALERT_BITS 1 4811 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_BL1_STATUS_ALERT_SHIFT 9 4812 4813 /* DDR34_F0_PHY_CONTROL_REGS :: PHYBIST_BL1_STATUS :: DM [08:08] */ 4814 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_BL1_STATUS_DM_MASK 0x00000100 4815 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_BL1_STATUS_DM_ALIGN 0 4816 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_BL1_STATUS_DM_BITS 1 4817 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_BL1_STATUS_DM_SHIFT 8 4818 4819 /* DDR34_F0_PHY_CONTROL_REGS :: PHYBIST_BL1_STATUS :: DQ [07:00] */ 4820 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_BL1_STATUS_DQ_MASK 0x000000ff 4821 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_BL1_STATUS_DQ_ALIGN 0 4822 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_BL1_STATUS_DQ_BITS 8 4823 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_BL1_STATUS_DQ_SHIFT 0 4824 4825 4826 /**************************************************************************** 4827 * DDR34_F0_PHY_CONTROL_REGS :: PHYBIST_BL2_STATUS 4828 */ 4829 /* DDR34_F0_PHY_CONTROL_REGS :: PHYBIST_BL2_STATUS :: reserved0 [31:10] */ 4830 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_BL2_STATUS_RESERVED0_MASK 0xfffffc00 4831 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_BL2_STATUS_RESERVED0_ALIGN 0 4832 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_BL2_STATUS_RESERVED0_BITS 22 4833 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_BL2_STATUS_RESERVED0_SHIFT 10 4834 4835 /* DDR34_F0_PHY_CONTROL_REGS :: PHYBIST_BL2_STATUS :: ALERT [09:09] */ 4836 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_BL2_STATUS_ALERT_MASK 0x00000200 4837 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_BL2_STATUS_ALERT_ALIGN 0 4838 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_BL2_STATUS_ALERT_BITS 1 4839 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_BL2_STATUS_ALERT_SHIFT 9 4840 4841 /* DDR34_F0_PHY_CONTROL_REGS :: PHYBIST_BL2_STATUS :: DM [08:08] */ 4842 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_BL2_STATUS_DM_MASK 0x00000100 4843 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_BL2_STATUS_DM_ALIGN 0 4844 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_BL2_STATUS_DM_BITS 1 4845 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_BL2_STATUS_DM_SHIFT 8 4846 4847 /* DDR34_F0_PHY_CONTROL_REGS :: PHYBIST_BL2_STATUS :: DQ [07:00] */ 4848 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_BL2_STATUS_DQ_MASK 0x000000ff 4849 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_BL2_STATUS_DQ_ALIGN 0 4850 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_BL2_STATUS_DQ_BITS 8 4851 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_BL2_STATUS_DQ_SHIFT 0 4852 4853 4854 /**************************************************************************** 4855 * DDR34_F0_PHY_CONTROL_REGS :: PHYBIST_BL3_STATUS 4856 */ 4857 /* DDR34_F0_PHY_CONTROL_REGS :: PHYBIST_BL3_STATUS :: reserved0 [31:10] */ 4858 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_BL3_STATUS_RESERVED0_MASK 0xfffffc00 4859 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_BL3_STATUS_RESERVED0_ALIGN 0 4860 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_BL3_STATUS_RESERVED0_BITS 22 4861 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_BL3_STATUS_RESERVED0_SHIFT 10 4862 4863 /* DDR34_F0_PHY_CONTROL_REGS :: PHYBIST_BL3_STATUS :: ALERT [09:09] */ 4864 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_BL3_STATUS_ALERT_MASK 0x00000200 4865 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_BL3_STATUS_ALERT_ALIGN 0 4866 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_BL3_STATUS_ALERT_BITS 1 4867 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_BL3_STATUS_ALERT_SHIFT 9 4868 4869 /* DDR34_F0_PHY_CONTROL_REGS :: PHYBIST_BL3_STATUS :: DM [08:08] */ 4870 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_BL3_STATUS_DM_MASK 0x00000100 4871 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_BL3_STATUS_DM_ALIGN 0 4872 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_BL3_STATUS_DM_BITS 1 4873 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_BL3_STATUS_DM_SHIFT 8 4874 4875 /* DDR34_F0_PHY_CONTROL_REGS :: PHYBIST_BL3_STATUS :: DQ [07:00] */ 4876 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_BL3_STATUS_DQ_MASK 0x000000ff 4877 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_BL3_STATUS_DQ_ALIGN 0 4878 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_BL3_STATUS_DQ_BITS 8 4879 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_BL3_STATUS_DQ_SHIFT 0 4880 4881 4882 /**************************************************************************** 4883 * DDR34_F0_PHY_CONTROL_REGS :: PHYBIST_BL4_STATUS 4884 */ 4885 /* DDR34_F0_PHY_CONTROL_REGS :: PHYBIST_BL4_STATUS :: reserved0 [31:10] */ 4886 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_BL4_STATUS_RESERVED0_MASK 0xfffffc00 4887 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_BL4_STATUS_RESERVED0_ALIGN 0 4888 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_BL4_STATUS_RESERVED0_BITS 22 4889 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_BL4_STATUS_RESERVED0_SHIFT 10 4890 4891 /* DDR34_F0_PHY_CONTROL_REGS :: PHYBIST_BL4_STATUS :: ALERT [09:09] */ 4892 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_BL4_STATUS_ALERT_MASK 0x00000200 4893 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_BL4_STATUS_ALERT_ALIGN 0 4894 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_BL4_STATUS_ALERT_BITS 1 4895 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_BL4_STATUS_ALERT_SHIFT 9 4896 4897 /* DDR34_F0_PHY_CONTROL_REGS :: PHYBIST_BL4_STATUS :: DM [08:08] */ 4898 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_BL4_STATUS_DM_MASK 0x00000100 4899 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_BL4_STATUS_DM_ALIGN 0 4900 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_BL4_STATUS_DM_BITS 1 4901 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_BL4_STATUS_DM_SHIFT 8 4902 4903 /* DDR34_F0_PHY_CONTROL_REGS :: PHYBIST_BL4_STATUS :: DQ [07:00] */ 4904 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_BL4_STATUS_DQ_MASK 0x000000ff 4905 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_BL4_STATUS_DQ_ALIGN 0 4906 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_BL4_STATUS_DQ_BITS 8 4907 #define DDR34_F0_PHY_CONTROL_REGS_PHYBIST_BL4_STATUS_DQ_SHIFT 0 4908 4909 4910 /**************************************************************************** 4911 * DDR34_F0_PHY_CONTROL_REGS :: STANDBY_CONTROL 4912 */ 4913 /* DDR34_F0_PHY_CONTROL_REGS :: STANDBY_CONTROL :: reserved0 [31:05] */ 4914 #define DDR34_F0_PHY_CONTROL_REGS_STANDBY_CONTROL_RESERVED0_MASK 0xffffffe0 4915 #define DDR34_F0_PHY_CONTROL_REGS_STANDBY_CONTROL_RESERVED0_ALIGN 0 4916 #define DDR34_F0_PHY_CONTROL_REGS_STANDBY_CONTROL_RESERVED0_BITS 27 4917 #define DDR34_F0_PHY_CONTROL_REGS_STANDBY_CONTROL_RESERVED0_SHIFT 5 4918 4919 /* DDR34_F0_PHY_CONTROL_REGS :: STANDBY_CONTROL :: PHY_STANDBY [04:04] */ 4920 #define DDR34_F0_PHY_CONTROL_REGS_STANDBY_CONTROL_PHY_STANDBY_MASK 0x00000010 4921 #define DDR34_F0_PHY_CONTROL_REGS_STANDBY_CONTROL_PHY_STANDBY_ALIGN 0 4922 #define DDR34_F0_PHY_CONTROL_REGS_STANDBY_CONTROL_PHY_STANDBY_BITS 1 4923 #define DDR34_F0_PHY_CONTROL_REGS_STANDBY_CONTROL_PHY_STANDBY_SHIFT 4 4924 4925 /* DDR34_F0_PHY_CONTROL_REGS :: STANDBY_CONTROL :: FORCE_CKE_RST_N [03:03] */ 4926 #define DDR34_F0_PHY_CONTROL_REGS_STANDBY_CONTROL_FORCE_CKE_RST_N_MASK 0x00000008 4927 #define DDR34_F0_PHY_CONTROL_REGS_STANDBY_CONTROL_FORCE_CKE_RST_N_ALIGN 0 4928 #define DDR34_F0_PHY_CONTROL_REGS_STANDBY_CONTROL_FORCE_CKE_RST_N_BITS 1 4929 #define DDR34_F0_PHY_CONTROL_REGS_STANDBY_CONTROL_FORCE_CKE_RST_N_SHIFT 3 4930 4931 /* DDR34_F0_PHY_CONTROL_REGS :: STANDBY_CONTROL :: RST_N [02:02] */ 4932 #define DDR34_F0_PHY_CONTROL_REGS_STANDBY_CONTROL_RST_N_MASK 0x00000004 4933 #define DDR34_F0_PHY_CONTROL_REGS_STANDBY_CONTROL_RST_N_ALIGN 0 4934 #define DDR34_F0_PHY_CONTROL_REGS_STANDBY_CONTROL_RST_N_BITS 1 4935 #define DDR34_F0_PHY_CONTROL_REGS_STANDBY_CONTROL_RST_N_SHIFT 2 4936 4937 /* DDR34_F0_PHY_CONTROL_REGS :: STANDBY_CONTROL :: CKE [01:01] */ 4938 #define DDR34_F0_PHY_CONTROL_REGS_STANDBY_CONTROL_CKE_MASK 0x00000002 4939 #define DDR34_F0_PHY_CONTROL_REGS_STANDBY_CONTROL_CKE_ALIGN 0 4940 #define DDR34_F0_PHY_CONTROL_REGS_STANDBY_CONTROL_CKE_BITS 1 4941 #define DDR34_F0_PHY_CONTROL_REGS_STANDBY_CONTROL_CKE_SHIFT 1 4942 4943 /* DDR34_F0_PHY_CONTROL_REGS :: STANDBY_CONTROL :: BIT_PIPE_RESET [00:00] */ 4944 #define DDR34_F0_PHY_CONTROL_REGS_STANDBY_CONTROL_BIT_PIPE_RESET_MASK 0x00000001 4945 #define DDR34_F0_PHY_CONTROL_REGS_STANDBY_CONTROL_BIT_PIPE_RESET_ALIGN 0 4946 #define DDR34_F0_PHY_CONTROL_REGS_STANDBY_CONTROL_BIT_PIPE_RESET_BITS 1 4947 #define DDR34_F0_PHY_CONTROL_REGS_STANDBY_CONTROL_BIT_PIPE_RESET_SHIFT 0 4948 4949 4950 /**************************************************************************** 4951 * DDR34_F0_PHY_CONTROL_REGS :: DEBUG_FREEZE_ENABLE 4952 */ 4953 /* DDR34_F0_PHY_CONTROL_REGS :: DEBUG_FREEZE_ENABLE :: reserved0 [31:04] */ 4954 #define DDR34_F0_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE_RESERVED0_MASK 0xfffffff0 4955 #define DDR34_F0_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE_RESERVED0_ALIGN 0 4956 #define DDR34_F0_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE_RESERVED0_BITS 28 4957 #define DDR34_F0_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE_RESERVED0_SHIFT 4 4958 4959 /* DDR34_F0_PHY_CONTROL_REGS :: DEBUG_FREEZE_ENABLE :: WL1_BL1 [03:03] */ 4960 #define DDR34_F0_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE_WL1_BL1_MASK 0x00000008 4961 #define DDR34_F0_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE_WL1_BL1_ALIGN 0 4962 #define DDR34_F0_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE_WL1_BL1_BITS 1 4963 #define DDR34_F0_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE_WL1_BL1_SHIFT 3 4964 4965 /* DDR34_F0_PHY_CONTROL_REGS :: DEBUG_FREEZE_ENABLE :: WL1_BL0 [02:02] */ 4966 #define DDR34_F0_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE_WL1_BL0_MASK 0x00000004 4967 #define DDR34_F0_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE_WL1_BL0_ALIGN 0 4968 #define DDR34_F0_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE_WL1_BL0_BITS 1 4969 #define DDR34_F0_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE_WL1_BL0_SHIFT 2 4970 4971 /* DDR34_F0_PHY_CONTROL_REGS :: DEBUG_FREEZE_ENABLE :: WL0_BL1 [01:01] */ 4972 #define DDR34_F0_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE_WL0_BL1_MASK 0x00000002 4973 #define DDR34_F0_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE_WL0_BL1_ALIGN 0 4974 #define DDR34_F0_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE_WL0_BL1_BITS 1 4975 #define DDR34_F0_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE_WL0_BL1_SHIFT 1 4976 4977 /* DDR34_F0_PHY_CONTROL_REGS :: DEBUG_FREEZE_ENABLE :: WL0_BL0 [00:00] */ 4978 #define DDR34_F0_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE_WL0_BL0_MASK 0x00000001 4979 #define DDR34_F0_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE_WL0_BL0_ALIGN 0 4980 #define DDR34_F0_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE_WL0_BL0_BITS 1 4981 #define DDR34_F0_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE_WL0_BL0_SHIFT 0 4982 4983 4984 /**************************************************************************** 4985 * DDR34_F0_PHY_CONTROL_REGS :: DEBUG_MUX_CONTROL 4986 */ 4987 /* DDR34_F0_PHY_CONTROL_REGS :: DEBUG_MUX_CONTROL :: reserved0 [31:11] */ 4988 #define DDR34_F0_PHY_CONTROL_REGS_DEBUG_MUX_CONTROL_RESERVED0_MASK 0xfffff800 4989 #define DDR34_F0_PHY_CONTROL_REGS_DEBUG_MUX_CONTROL_RESERVED0_ALIGN 0 4990 #define DDR34_F0_PHY_CONTROL_REGS_DEBUG_MUX_CONTROL_RESERVED0_BITS 21 4991 #define DDR34_F0_PHY_CONTROL_REGS_DEBUG_MUX_CONTROL_RESERVED0_SHIFT 11 4992 4993 /* DDR34_F0_PHY_CONTROL_REGS :: DEBUG_MUX_CONTROL :: BYTE_SEL [10:08] */ 4994 #define DDR34_F0_PHY_CONTROL_REGS_DEBUG_MUX_CONTROL_BYTE_SEL_MASK 0x00000700 4995 #define DDR34_F0_PHY_CONTROL_REGS_DEBUG_MUX_CONTROL_BYTE_SEL_ALIGN 0 4996 #define DDR34_F0_PHY_CONTROL_REGS_DEBUG_MUX_CONTROL_BYTE_SEL_BITS 3 4997 #define DDR34_F0_PHY_CONTROL_REGS_DEBUG_MUX_CONTROL_BYTE_SEL_SHIFT 8 4998 4999 /* DDR34_F0_PHY_CONTROL_REGS :: DEBUG_MUX_CONTROL :: reserved1 [07:06] */ 5000 #define DDR34_F0_PHY_CONTROL_REGS_DEBUG_MUX_CONTROL_RESERVED1_MASK 0x000000c0 5001 #define DDR34_F0_PHY_CONTROL_REGS_DEBUG_MUX_CONTROL_RESERVED1_ALIGN 0 5002 #define DDR34_F0_PHY_CONTROL_REGS_DEBUG_MUX_CONTROL_RESERVED1_BITS 2 5003 #define DDR34_F0_PHY_CONTROL_REGS_DEBUG_MUX_CONTROL_RESERVED1_SHIFT 6 5004 5005 /* DDR34_F0_PHY_CONTROL_REGS :: DEBUG_MUX_CONTROL :: PHASE_SEL [05:04] */ 5006 #define DDR34_F0_PHY_CONTROL_REGS_DEBUG_MUX_CONTROL_PHASE_SEL_MASK 0x00000030 5007 #define DDR34_F0_PHY_CONTROL_REGS_DEBUG_MUX_CONTROL_PHASE_SEL_ALIGN 0 5008 #define DDR34_F0_PHY_CONTROL_REGS_DEBUG_MUX_CONTROL_PHASE_SEL_BITS 2 5009 #define DDR34_F0_PHY_CONTROL_REGS_DEBUG_MUX_CONTROL_PHASE_SEL_SHIFT 4 5010 5011 /* DDR34_F0_PHY_CONTROL_REGS :: DEBUG_MUX_CONTROL :: SOURCE_SEL [03:00] */ 5012 #define DDR34_F0_PHY_CONTROL_REGS_DEBUG_MUX_CONTROL_SOURCE_SEL_MASK 0x0000000f 5013 #define DDR34_F0_PHY_CONTROL_REGS_DEBUG_MUX_CONTROL_SOURCE_SEL_ALIGN 0 5014 #define DDR34_F0_PHY_CONTROL_REGS_DEBUG_MUX_CONTROL_SOURCE_SEL_BITS 4 5015 #define DDR34_F0_PHY_CONTROL_REGS_DEBUG_MUX_CONTROL_SOURCE_SEL_SHIFT 0 5016 5017 5018 /**************************************************************************** 5019 * DDR34_F0_PHY_CONTROL_REGS :: DFI_CNTRL 5020 */ 5021 /* DDR34_F0_PHY_CONTROL_REGS :: DFI_CNTRL :: reserved0 [31:09] */ 5022 #define DDR34_F0_PHY_CONTROL_REGS_DFI_CNTRL_RESERVED0_MASK 0xfffffe00 5023 #define DDR34_F0_PHY_CONTROL_REGS_DFI_CNTRL_RESERVED0_ALIGN 0 5024 #define DDR34_F0_PHY_CONTROL_REGS_DFI_CNTRL_RESERVED0_BITS 23 5025 #define DDR34_F0_PHY_CONTROL_REGS_DFI_CNTRL_RESERVED0_SHIFT 9 5026 5027 /* DDR34_F0_PHY_CONTROL_REGS :: DFI_CNTRL :: SELF_REFRESH [08:08] */ 5028 #define DDR34_F0_PHY_CONTROL_REGS_DFI_CNTRL_SELF_REFRESH_MASK 0x00000100 5029 #define DDR34_F0_PHY_CONTROL_REGS_DFI_CNTRL_SELF_REFRESH_ALIGN 0 5030 #define DDR34_F0_PHY_CONTROL_REGS_DFI_CNTRL_SELF_REFRESH_BITS 1 5031 #define DDR34_F0_PHY_CONTROL_REGS_DFI_CNTRL_SELF_REFRESH_SHIFT 8 5032 5033 /* DDR34_F0_PHY_CONTROL_REGS :: DFI_CNTRL :: DFI_CS1 [07:07] */ 5034 #define DDR34_F0_PHY_CONTROL_REGS_DFI_CNTRL_DFI_CS1_MASK 0x00000080 5035 #define DDR34_F0_PHY_CONTROL_REGS_DFI_CNTRL_DFI_CS1_ALIGN 0 5036 #define DDR34_F0_PHY_CONTROL_REGS_DFI_CNTRL_DFI_CS1_BITS 1 5037 #define DDR34_F0_PHY_CONTROL_REGS_DFI_CNTRL_DFI_CS1_SHIFT 7 5038 5039 /* DDR34_F0_PHY_CONTROL_REGS :: DFI_CNTRL :: DFI_CS0 [06:06] */ 5040 #define DDR34_F0_PHY_CONTROL_REGS_DFI_CNTRL_DFI_CS0_MASK 0x00000040 5041 #define DDR34_F0_PHY_CONTROL_REGS_DFI_CNTRL_DFI_CS0_ALIGN 0 5042 #define DDR34_F0_PHY_CONTROL_REGS_DFI_CNTRL_DFI_CS0_BITS 1 5043 #define DDR34_F0_PHY_CONTROL_REGS_DFI_CNTRL_DFI_CS0_SHIFT 6 5044 5045 /* DDR34_F0_PHY_CONTROL_REGS :: DFI_CNTRL :: DFI_RST_N [05:05] */ 5046 #define DDR34_F0_PHY_CONTROL_REGS_DFI_CNTRL_DFI_RST_N_MASK 0x00000020 5047 #define DDR34_F0_PHY_CONTROL_REGS_DFI_CNTRL_DFI_RST_N_ALIGN 0 5048 #define DDR34_F0_PHY_CONTROL_REGS_DFI_CNTRL_DFI_RST_N_BITS 1 5049 #define DDR34_F0_PHY_CONTROL_REGS_DFI_CNTRL_DFI_RST_N_SHIFT 5 5050 5051 /* DDR34_F0_PHY_CONTROL_REGS :: DFI_CNTRL :: reserved1 [04:04] */ 5052 #define DDR34_F0_PHY_CONTROL_REGS_DFI_CNTRL_RESERVED1_MASK 0x00000010 5053 #define DDR34_F0_PHY_CONTROL_REGS_DFI_CNTRL_RESERVED1_ALIGN 0 5054 #define DDR34_F0_PHY_CONTROL_REGS_DFI_CNTRL_RESERVED1_BITS 1 5055 #define DDR34_F0_PHY_CONTROL_REGS_DFI_CNTRL_RESERVED1_SHIFT 4 5056 5057 /* DDR34_F0_PHY_CONTROL_REGS :: DFI_CNTRL :: DFI_CKE [03:03] */ 5058 #define DDR34_F0_PHY_CONTROL_REGS_DFI_CNTRL_DFI_CKE_MASK 0x00000008 5059 #define DDR34_F0_PHY_CONTROL_REGS_DFI_CNTRL_DFI_CKE_ALIGN 0 5060 #define DDR34_F0_PHY_CONTROL_REGS_DFI_CNTRL_DFI_CKE_BITS 1 5061 #define DDR34_F0_PHY_CONTROL_REGS_DFI_CNTRL_DFI_CKE_SHIFT 3 5062 5063 /* DDR34_F0_PHY_CONTROL_REGS :: DFI_CNTRL :: ACK_ENABLE [02:02] */ 5064 #define DDR34_F0_PHY_CONTROL_REGS_DFI_CNTRL_ACK_ENABLE_MASK 0x00000004 5065 #define DDR34_F0_PHY_CONTROL_REGS_DFI_CNTRL_ACK_ENABLE_ALIGN 0 5066 #define DDR34_F0_PHY_CONTROL_REGS_DFI_CNTRL_ACK_ENABLE_BITS 1 5067 #define DDR34_F0_PHY_CONTROL_REGS_DFI_CNTRL_ACK_ENABLE_SHIFT 2 5068 5069 /* DDR34_F0_PHY_CONTROL_REGS :: DFI_CNTRL :: ACK_STATUS [01:01] */ 5070 #define DDR34_F0_PHY_CONTROL_REGS_DFI_CNTRL_ACK_STATUS_MASK 0x00000002 5071 #define DDR34_F0_PHY_CONTROL_REGS_DFI_CNTRL_ACK_STATUS_ALIGN 0 5072 #define DDR34_F0_PHY_CONTROL_REGS_DFI_CNTRL_ACK_STATUS_BITS 1 5073 #define DDR34_F0_PHY_CONTROL_REGS_DFI_CNTRL_ACK_STATUS_SHIFT 1 5074 5075 /* DDR34_F0_PHY_CONTROL_REGS :: DFI_CNTRL :: ASSERT_REQ [00:00] */ 5076 #define DDR34_F0_PHY_CONTROL_REGS_DFI_CNTRL_ASSERT_REQ_MASK 0x00000001 5077 #define DDR34_F0_PHY_CONTROL_REGS_DFI_CNTRL_ASSERT_REQ_ALIGN 0 5078 #define DDR34_F0_PHY_CONTROL_REGS_DFI_CNTRL_ASSERT_REQ_BITS 1 5079 #define DDR34_F0_PHY_CONTROL_REGS_DFI_CNTRL_ASSERT_REQ_SHIFT 0 5080 5081 5082 /**************************************************************************** 5083 * DDR34_F0_PHY_CONTROL_REGS :: WRITE_ODT_CNTRL 5084 */ 5085 /* DDR34_F0_PHY_CONTROL_REGS :: WRITE_ODT_CNTRL :: reserved0 [31:29] */ 5086 #define DDR34_F0_PHY_CONTROL_REGS_WRITE_ODT_CNTRL_RESERVED0_MASK 0xe0000000 5087 #define DDR34_F0_PHY_CONTROL_REGS_WRITE_ODT_CNTRL_RESERVED0_ALIGN 0 5088 #define DDR34_F0_PHY_CONTROL_REGS_WRITE_ODT_CNTRL_RESERVED0_BITS 3 5089 #define DDR34_F0_PHY_CONTROL_REGS_WRITE_ODT_CNTRL_RESERVED0_SHIFT 29 5090 5091 /* DDR34_F0_PHY_CONTROL_REGS :: WRITE_ODT_CNTRL :: ODT1_FORCE_VALUE [28:28] */ 5092 #define DDR34_F0_PHY_CONTROL_REGS_WRITE_ODT_CNTRL_ODT1_FORCE_VALUE_MASK 0x10000000 5093 #define DDR34_F0_PHY_CONTROL_REGS_WRITE_ODT_CNTRL_ODT1_FORCE_VALUE_ALIGN 0 5094 #define DDR34_F0_PHY_CONTROL_REGS_WRITE_ODT_CNTRL_ODT1_FORCE_VALUE_BITS 1 5095 #define DDR34_F0_PHY_CONTROL_REGS_WRITE_ODT_CNTRL_ODT1_FORCE_VALUE_SHIFT 28 5096 5097 /* DDR34_F0_PHY_CONTROL_REGS :: WRITE_ODT_CNTRL :: ODT1_FORCE [27:27] */ 5098 #define DDR34_F0_PHY_CONTROL_REGS_WRITE_ODT_CNTRL_ODT1_FORCE_MASK 0x08000000 5099 #define DDR34_F0_PHY_CONTROL_REGS_WRITE_ODT_CNTRL_ODT1_FORCE_ALIGN 0 5100 #define DDR34_F0_PHY_CONTROL_REGS_WRITE_ODT_CNTRL_ODT1_FORCE_BITS 1 5101 #define DDR34_F0_PHY_CONTROL_REGS_WRITE_ODT_CNTRL_ODT1_FORCE_SHIFT 27 5102 5103 /* DDR34_F0_PHY_CONTROL_REGS :: WRITE_ODT_CNTRL :: ODT1_ENABLE [26:26] */ 5104 #define DDR34_F0_PHY_CONTROL_REGS_WRITE_ODT_CNTRL_ODT1_ENABLE_MASK 0x04000000 5105 #define DDR34_F0_PHY_CONTROL_REGS_WRITE_ODT_CNTRL_ODT1_ENABLE_ALIGN 0 5106 #define DDR34_F0_PHY_CONTROL_REGS_WRITE_ODT_CNTRL_ODT1_ENABLE_BITS 1 5107 #define DDR34_F0_PHY_CONTROL_REGS_WRITE_ODT_CNTRL_ODT1_ENABLE_SHIFT 26 5108 5109 /* DDR34_F0_PHY_CONTROL_REGS :: WRITE_ODT_CNTRL :: ODT1_LENGTH [25:22] */ 5110 #define DDR34_F0_PHY_CONTROL_REGS_WRITE_ODT_CNTRL_ODT1_LENGTH_MASK 0x03c00000 5111 #define DDR34_F0_PHY_CONTROL_REGS_WRITE_ODT_CNTRL_ODT1_LENGTH_ALIGN 0 5112 #define DDR34_F0_PHY_CONTROL_REGS_WRITE_ODT_CNTRL_ODT1_LENGTH_BITS 4 5113 #define DDR34_F0_PHY_CONTROL_REGS_WRITE_ODT_CNTRL_ODT1_LENGTH_SHIFT 22 5114 5115 /* DDR34_F0_PHY_CONTROL_REGS :: WRITE_ODT_CNTRL :: ODT1_DELAY [21:16] */ 5116 #define DDR34_F0_PHY_CONTROL_REGS_WRITE_ODT_CNTRL_ODT1_DELAY_MASK 0x003f0000 5117 #define DDR34_F0_PHY_CONTROL_REGS_WRITE_ODT_CNTRL_ODT1_DELAY_ALIGN 0 5118 #define DDR34_F0_PHY_CONTROL_REGS_WRITE_ODT_CNTRL_ODT1_DELAY_BITS 6 5119 #define DDR34_F0_PHY_CONTROL_REGS_WRITE_ODT_CNTRL_ODT1_DELAY_SHIFT 16 5120 5121 /* DDR34_F0_PHY_CONTROL_REGS :: WRITE_ODT_CNTRL :: reserved1 [15:13] */ 5122 #define DDR34_F0_PHY_CONTROL_REGS_WRITE_ODT_CNTRL_RESERVED1_MASK 0x0000e000 5123 #define DDR34_F0_PHY_CONTROL_REGS_WRITE_ODT_CNTRL_RESERVED1_ALIGN 0 5124 #define DDR34_F0_PHY_CONTROL_REGS_WRITE_ODT_CNTRL_RESERVED1_BITS 3 5125 #define DDR34_F0_PHY_CONTROL_REGS_WRITE_ODT_CNTRL_RESERVED1_SHIFT 13 5126 5127 /* DDR34_F0_PHY_CONTROL_REGS :: WRITE_ODT_CNTRL :: ODT0_FORCE_VALUE [12:12] */ 5128 #define DDR34_F0_PHY_CONTROL_REGS_WRITE_ODT_CNTRL_ODT0_FORCE_VALUE_MASK 0x00001000 5129 #define DDR34_F0_PHY_CONTROL_REGS_WRITE_ODT_CNTRL_ODT0_FORCE_VALUE_ALIGN 0 5130 #define DDR34_F0_PHY_CONTROL_REGS_WRITE_ODT_CNTRL_ODT0_FORCE_VALUE_BITS 1 5131 #define DDR34_F0_PHY_CONTROL_REGS_WRITE_ODT_CNTRL_ODT0_FORCE_VALUE_SHIFT 12 5132 5133 /* DDR34_F0_PHY_CONTROL_REGS :: WRITE_ODT_CNTRL :: ODT0_FORCE [11:11] */ 5134 #define DDR34_F0_PHY_CONTROL_REGS_WRITE_ODT_CNTRL_ODT0_FORCE_MASK 0x00000800 5135 #define DDR34_F0_PHY_CONTROL_REGS_WRITE_ODT_CNTRL_ODT0_FORCE_ALIGN 0 5136 #define DDR34_F0_PHY_CONTROL_REGS_WRITE_ODT_CNTRL_ODT0_FORCE_BITS 1 5137 #define DDR34_F0_PHY_CONTROL_REGS_WRITE_ODT_CNTRL_ODT0_FORCE_SHIFT 11 5138 5139 /* DDR34_F0_PHY_CONTROL_REGS :: WRITE_ODT_CNTRL :: ODT0_ENABLE [10:10] */ 5140 #define DDR34_F0_PHY_CONTROL_REGS_WRITE_ODT_CNTRL_ODT0_ENABLE_MASK 0x00000400 5141 #define DDR34_F0_PHY_CONTROL_REGS_WRITE_ODT_CNTRL_ODT0_ENABLE_ALIGN 0 5142 #define DDR34_F0_PHY_CONTROL_REGS_WRITE_ODT_CNTRL_ODT0_ENABLE_BITS 1 5143 #define DDR34_F0_PHY_CONTROL_REGS_WRITE_ODT_CNTRL_ODT0_ENABLE_SHIFT 10 5144 5145 /* DDR34_F0_PHY_CONTROL_REGS :: WRITE_ODT_CNTRL :: ODT0_LENGTH [09:06] */ 5146 #define DDR34_F0_PHY_CONTROL_REGS_WRITE_ODT_CNTRL_ODT0_LENGTH_MASK 0x000003c0 5147 #define DDR34_F0_PHY_CONTROL_REGS_WRITE_ODT_CNTRL_ODT0_LENGTH_ALIGN 0 5148 #define DDR34_F0_PHY_CONTROL_REGS_WRITE_ODT_CNTRL_ODT0_LENGTH_BITS 4 5149 #define DDR34_F0_PHY_CONTROL_REGS_WRITE_ODT_CNTRL_ODT0_LENGTH_SHIFT 6 5150 5151 /* DDR34_F0_PHY_CONTROL_REGS :: WRITE_ODT_CNTRL :: ODT0_DELAY [05:00] */ 5152 #define DDR34_F0_PHY_CONTROL_REGS_WRITE_ODT_CNTRL_ODT0_DELAY_MASK 0x0000003f 5153 #define DDR34_F0_PHY_CONTROL_REGS_WRITE_ODT_CNTRL_ODT0_DELAY_ALIGN 0 5154 #define DDR34_F0_PHY_CONTROL_REGS_WRITE_ODT_CNTRL_ODT0_DELAY_BITS 6 5155 #define DDR34_F0_PHY_CONTROL_REGS_WRITE_ODT_CNTRL_ODT0_DELAY_SHIFT 0 5156 5157 5158 /**************************************************************************** 5159 * DDR34_F0_PHY_CONTROL_REGS :: ABI_PAR_CNTRL 5160 */ 5161 /* DDR34_F0_PHY_CONTROL_REGS :: ABI_PAR_CNTRL :: reserved0 [31:08] */ 5162 #define DDR34_F0_PHY_CONTROL_REGS_ABI_PAR_CNTRL_RESERVED0_MASK 0xffffff00 5163 #define DDR34_F0_PHY_CONTROL_REGS_ABI_PAR_CNTRL_RESERVED0_ALIGN 0 5164 #define DDR34_F0_PHY_CONTROL_REGS_ABI_PAR_CNTRL_RESERVED0_BITS 24 5165 #define DDR34_F0_PHY_CONTROL_REGS_ABI_PAR_CNTRL_RESERVED0_SHIFT 8 5166 5167 /* DDR34_F0_PHY_CONTROL_REGS :: ABI_PAR_CNTRL :: PAR_ERROR [07:04] */ 5168 #define DDR34_F0_PHY_CONTROL_REGS_ABI_PAR_CNTRL_PAR_ERROR_MASK 0x000000f0 5169 #define DDR34_F0_PHY_CONTROL_REGS_ABI_PAR_CNTRL_PAR_ERROR_ALIGN 0 5170 #define DDR34_F0_PHY_CONTROL_REGS_ABI_PAR_CNTRL_PAR_ERROR_BITS 4 5171 #define DDR34_F0_PHY_CONTROL_REGS_ABI_PAR_CNTRL_PAR_ERROR_SHIFT 4 5172 5173 /* DDR34_F0_PHY_CONTROL_REGS :: ABI_PAR_CNTRL :: PAR_INCLUDE_AUX [03:03] */ 5174 #define DDR34_F0_PHY_CONTROL_REGS_ABI_PAR_CNTRL_PAR_INCLUDE_AUX_MASK 0x00000008 5175 #define DDR34_F0_PHY_CONTROL_REGS_ABI_PAR_CNTRL_PAR_INCLUDE_AUX_ALIGN 0 5176 #define DDR34_F0_PHY_CONTROL_REGS_ABI_PAR_CNTRL_PAR_INCLUDE_AUX_BITS 1 5177 #define DDR34_F0_PHY_CONTROL_REGS_ABI_PAR_CNTRL_PAR_INCLUDE_AUX_SHIFT 3 5178 5179 /* DDR34_F0_PHY_CONTROL_REGS :: ABI_PAR_CNTRL :: PAR_ENABLE [02:02] */ 5180 #define DDR34_F0_PHY_CONTROL_REGS_ABI_PAR_CNTRL_PAR_ENABLE_MASK 0x00000004 5181 #define DDR34_F0_PHY_CONTROL_REGS_ABI_PAR_CNTRL_PAR_ENABLE_ALIGN 0 5182 #define DDR34_F0_PHY_CONTROL_REGS_ABI_PAR_CNTRL_PAR_ENABLE_BITS 1 5183 #define DDR34_F0_PHY_CONTROL_REGS_ABI_PAR_CNTRL_PAR_ENABLE_SHIFT 2 5184 5185 /* DDR34_F0_PHY_CONTROL_REGS :: ABI_PAR_CNTRL :: ABI_INCLUDE_AUX [01:01] */ 5186 #define DDR34_F0_PHY_CONTROL_REGS_ABI_PAR_CNTRL_ABI_INCLUDE_AUX_MASK 0x00000002 5187 #define DDR34_F0_PHY_CONTROL_REGS_ABI_PAR_CNTRL_ABI_INCLUDE_AUX_ALIGN 0 5188 #define DDR34_F0_PHY_CONTROL_REGS_ABI_PAR_CNTRL_ABI_INCLUDE_AUX_BITS 1 5189 #define DDR34_F0_PHY_CONTROL_REGS_ABI_PAR_CNTRL_ABI_INCLUDE_AUX_SHIFT 1 5190 5191 /* DDR34_F0_PHY_CONTROL_REGS :: ABI_PAR_CNTRL :: ABI_ENABLE [00:00] */ 5192 #define DDR34_F0_PHY_CONTROL_REGS_ABI_PAR_CNTRL_ABI_ENABLE_MASK 0x00000001 5193 #define DDR34_F0_PHY_CONTROL_REGS_ABI_PAR_CNTRL_ABI_ENABLE_ALIGN 0 5194 #define DDR34_F0_PHY_CONTROL_REGS_ABI_PAR_CNTRL_ABI_ENABLE_BITS 1 5195 #define DDR34_F0_PHY_CONTROL_REGS_ABI_PAR_CNTRL_ABI_ENABLE_SHIFT 0 5196 5197 5198 /**************************************************************************** 5199 * DDR34_F0_PHY_CONTROL_REGS :: ZQ_CAL 5200 */ 5201 /* DDR34_F0_PHY_CONTROL_REGS :: ZQ_CAL :: reserved0 [31:20] */ 5202 #define DDR34_F0_PHY_CONTROL_REGS_ZQ_CAL_RESERVED0_MASK 0xfff00000 5203 #define DDR34_F0_PHY_CONTROL_REGS_ZQ_CAL_RESERVED0_ALIGN 0 5204 #define DDR34_F0_PHY_CONTROL_REGS_ZQ_CAL_RESERVED0_BITS 12 5205 #define DDR34_F0_PHY_CONTROL_REGS_ZQ_CAL_RESERVED0_SHIFT 20 5206 5207 /* DDR34_F0_PHY_CONTROL_REGS :: ZQ_CAL :: ZQ_PCOMP_STATUS [19:19] */ 5208 #define DDR34_F0_PHY_CONTROL_REGS_ZQ_CAL_ZQ_PCOMP_STATUS_MASK 0x00080000 5209 #define DDR34_F0_PHY_CONTROL_REGS_ZQ_CAL_ZQ_PCOMP_STATUS_ALIGN 0 5210 #define DDR34_F0_PHY_CONTROL_REGS_ZQ_CAL_ZQ_PCOMP_STATUS_BITS 1 5211 #define DDR34_F0_PHY_CONTROL_REGS_ZQ_CAL_ZQ_PCOMP_STATUS_SHIFT 19 5212 5213 /* DDR34_F0_PHY_CONTROL_REGS :: ZQ_CAL :: ZQ_NCOMP_STATUS [18:18] */ 5214 #define DDR34_F0_PHY_CONTROL_REGS_ZQ_CAL_ZQ_NCOMP_STATUS_MASK 0x00040000 5215 #define DDR34_F0_PHY_CONTROL_REGS_ZQ_CAL_ZQ_NCOMP_STATUS_ALIGN 0 5216 #define DDR34_F0_PHY_CONTROL_REGS_ZQ_CAL_ZQ_NCOMP_STATUS_BITS 1 5217 #define DDR34_F0_PHY_CONTROL_REGS_ZQ_CAL_ZQ_NCOMP_STATUS_SHIFT 18 5218 5219 /* DDR34_F0_PHY_CONTROL_REGS :: ZQ_CAL :: ZQ_IDDQ [17:17] */ 5220 #define DDR34_F0_PHY_CONTROL_REGS_ZQ_CAL_ZQ_IDDQ_MASK 0x00020000 5221 #define DDR34_F0_PHY_CONTROL_REGS_ZQ_CAL_ZQ_IDDQ_ALIGN 0 5222 #define DDR34_F0_PHY_CONTROL_REGS_ZQ_CAL_ZQ_IDDQ_BITS 1 5223 #define DDR34_F0_PHY_CONTROL_REGS_ZQ_CAL_ZQ_IDDQ_SHIFT 17 5224 5225 /* DDR34_F0_PHY_CONTROL_REGS :: ZQ_CAL :: ZQ_DRIVE_P [16:12] */ 5226 #define DDR34_F0_PHY_CONTROL_REGS_ZQ_CAL_ZQ_DRIVE_P_MASK 0x0001f000 5227 #define DDR34_F0_PHY_CONTROL_REGS_ZQ_CAL_ZQ_DRIVE_P_ALIGN 0 5228 #define DDR34_F0_PHY_CONTROL_REGS_ZQ_CAL_ZQ_DRIVE_P_BITS 5 5229 #define DDR34_F0_PHY_CONTROL_REGS_ZQ_CAL_ZQ_DRIVE_P_SHIFT 12 5230 5231 /* DDR34_F0_PHY_CONTROL_REGS :: ZQ_CAL :: ZQ_DRIVE_N [11:07] */ 5232 #define DDR34_F0_PHY_CONTROL_REGS_ZQ_CAL_ZQ_DRIVE_N_MASK 0x00000f80 5233 #define DDR34_F0_PHY_CONTROL_REGS_ZQ_CAL_ZQ_DRIVE_N_ALIGN 0 5234 #define DDR34_F0_PHY_CONTROL_REGS_ZQ_CAL_ZQ_DRIVE_N_BITS 5 5235 #define DDR34_F0_PHY_CONTROL_REGS_ZQ_CAL_ZQ_DRIVE_N_SHIFT 7 5236 5237 /* DDR34_F0_PHY_CONTROL_REGS :: ZQ_CAL :: reserved1 [06:02] */ 5238 #define DDR34_F0_PHY_CONTROL_REGS_ZQ_CAL_RESERVED1_MASK 0x0000007c 5239 #define DDR34_F0_PHY_CONTROL_REGS_ZQ_CAL_RESERVED1_ALIGN 0 5240 #define DDR34_F0_PHY_CONTROL_REGS_ZQ_CAL_RESERVED1_BITS 5 5241 #define DDR34_F0_PHY_CONTROL_REGS_ZQ_CAL_RESERVED1_SHIFT 2 5242 5243 /* DDR34_F0_PHY_CONTROL_REGS :: ZQ_CAL :: ZQ_PCOMP_ENB [01:01] */ 5244 #define DDR34_F0_PHY_CONTROL_REGS_ZQ_CAL_ZQ_PCOMP_ENB_MASK 0x00000002 5245 #define DDR34_F0_PHY_CONTROL_REGS_ZQ_CAL_ZQ_PCOMP_ENB_ALIGN 0 5246 #define DDR34_F0_PHY_CONTROL_REGS_ZQ_CAL_ZQ_PCOMP_ENB_BITS 1 5247 #define DDR34_F0_PHY_CONTROL_REGS_ZQ_CAL_ZQ_PCOMP_ENB_SHIFT 1 5248 5249 /* DDR34_F0_PHY_CONTROL_REGS :: ZQ_CAL :: ZQ_NCOMP_ENB [00:00] */ 5250 #define DDR34_F0_PHY_CONTROL_REGS_ZQ_CAL_ZQ_NCOMP_ENB_MASK 0x00000001 5251 #define DDR34_F0_PHY_CONTROL_REGS_ZQ_CAL_ZQ_NCOMP_ENB_ALIGN 0 5252 #define DDR34_F0_PHY_CONTROL_REGS_ZQ_CAL_ZQ_NCOMP_ENB_BITS 1 5253 #define DDR34_F0_PHY_CONTROL_REGS_ZQ_CAL_ZQ_NCOMP_ENB_SHIFT 0 5254 5255 5256 /**************************************************************************** 5257 * DDR34_F0_PHY_CONTROL_REGS :: ZQ_CAL2 5258 */ 5259 /* DDR34_F0_PHY_CONTROL_REGS :: ZQ_CAL2 :: reserved0 [31:17] */ 5260 #define DDR34_F0_PHY_CONTROL_REGS_ZQ_CAL2_RESERVED0_MASK 0xfffe0000 5261 #define DDR34_F0_PHY_CONTROL_REGS_ZQ_CAL2_RESERVED0_ALIGN 0 5262 #define DDR34_F0_PHY_CONTROL_REGS_ZQ_CAL2_RESERVED0_BITS 15 5263 #define DDR34_F0_PHY_CONTROL_REGS_ZQ_CAL2_RESERVED0_SHIFT 17 5264 5265 /* DDR34_F0_PHY_CONTROL_REGS :: ZQ_CAL2 :: ZQ_CAL_RESET [16:16] */ 5266 #define DDR34_F0_PHY_CONTROL_REGS_ZQ_CAL2_ZQ_CAL_RESET_MASK 0x00010000 5267 #define DDR34_F0_PHY_CONTROL_REGS_ZQ_CAL2_ZQ_CAL_RESET_ALIGN 0 5268 #define DDR34_F0_PHY_CONTROL_REGS_ZQ_CAL2_ZQ_CAL_RESET_BITS 1 5269 #define DDR34_F0_PHY_CONTROL_REGS_ZQ_CAL2_ZQ_CAL_RESET_SHIFT 16 5270 5271 /* DDR34_F0_PHY_CONTROL_REGS :: ZQ_CAL2 :: ZQ_CAL_ERROR_N [15:15] */ 5272 #define DDR34_F0_PHY_CONTROL_REGS_ZQ_CAL2_ZQ_CAL_ERROR_N_MASK 0x00008000 5273 #define DDR34_F0_PHY_CONTROL_REGS_ZQ_CAL2_ZQ_CAL_ERROR_N_ALIGN 0 5274 #define DDR34_F0_PHY_CONTROL_REGS_ZQ_CAL2_ZQ_CAL_ERROR_N_BITS 1 5275 #define DDR34_F0_PHY_CONTROL_REGS_ZQ_CAL2_ZQ_CAL_ERROR_N_SHIFT 15 5276 5277 /* DDR34_F0_PHY_CONTROL_REGS :: ZQ_CAL2 :: ZQ_CAL_ERROR_P [14:14] */ 5278 #define DDR34_F0_PHY_CONTROL_REGS_ZQ_CAL2_ZQ_CAL_ERROR_P_MASK 0x00004000 5279 #define DDR34_F0_PHY_CONTROL_REGS_ZQ_CAL2_ZQ_CAL_ERROR_P_ALIGN 0 5280 #define DDR34_F0_PHY_CONTROL_REGS_ZQ_CAL2_ZQ_CAL_ERROR_P_BITS 1 5281 #define DDR34_F0_PHY_CONTROL_REGS_ZQ_CAL2_ZQ_CAL_ERROR_P_SHIFT 14 5282 5283 /* DDR34_F0_PHY_CONTROL_REGS :: ZQ_CAL2 :: ZQ_NSETTING [13:09] */ 5284 #define DDR34_F0_PHY_CONTROL_REGS_ZQ_CAL2_ZQ_NSETTING_MASK 0x00003e00 5285 #define DDR34_F0_PHY_CONTROL_REGS_ZQ_CAL2_ZQ_NSETTING_ALIGN 0 5286 #define DDR34_F0_PHY_CONTROL_REGS_ZQ_CAL2_ZQ_NSETTING_BITS 5 5287 #define DDR34_F0_PHY_CONTROL_REGS_ZQ_CAL2_ZQ_NSETTING_SHIFT 9 5288 5289 /* DDR34_F0_PHY_CONTROL_REGS :: ZQ_CAL2 :: ZQ_PSETTING [08:04] */ 5290 #define DDR34_F0_PHY_CONTROL_REGS_ZQ_CAL2_ZQ_PSETTING_MASK 0x000001f0 5291 #define DDR34_F0_PHY_CONTROL_REGS_ZQ_CAL2_ZQ_PSETTING_ALIGN 0 5292 #define DDR34_F0_PHY_CONTROL_REGS_ZQ_CAL2_ZQ_PSETTING_BITS 5 5293 #define DDR34_F0_PHY_CONTROL_REGS_ZQ_CAL2_ZQ_PSETTING_SHIFT 4 5294 5295 /* DDR34_F0_PHY_CONTROL_REGS :: ZQ_CAL2 :: ZQ_CAL_OP_COMPLETE_N [03:03] */ 5296 #define DDR34_F0_PHY_CONTROL_REGS_ZQ_CAL2_ZQ_CAL_OP_COMPLETE_N_MASK 0x00000008 5297 #define DDR34_F0_PHY_CONTROL_REGS_ZQ_CAL2_ZQ_CAL_OP_COMPLETE_N_ALIGN 0 5298 #define DDR34_F0_PHY_CONTROL_REGS_ZQ_CAL2_ZQ_CAL_OP_COMPLETE_N_BITS 1 5299 #define DDR34_F0_PHY_CONTROL_REGS_ZQ_CAL2_ZQ_CAL_OP_COMPLETE_N_SHIFT 3 5300 5301 /* DDR34_F0_PHY_CONTROL_REGS :: ZQ_CAL2 :: ZQ_CAL_OP_COMPLETE_P [02:02] */ 5302 #define DDR34_F0_PHY_CONTROL_REGS_ZQ_CAL2_ZQ_CAL_OP_COMPLETE_P_MASK 0x00000004 5303 #define DDR34_F0_PHY_CONTROL_REGS_ZQ_CAL2_ZQ_CAL_OP_COMPLETE_P_ALIGN 0 5304 #define DDR34_F0_PHY_CONTROL_REGS_ZQ_CAL2_ZQ_CAL_OP_COMPLETE_P_BITS 1 5305 #define DDR34_F0_PHY_CONTROL_REGS_ZQ_CAL2_ZQ_CAL_OP_COMPLETE_P_SHIFT 2 5306 5307 /* DDR34_F0_PHY_CONTROL_REGS :: ZQ_CAL2 :: ZQ_CAL_START_N [01:01] */ 5308 #define DDR34_F0_PHY_CONTROL_REGS_ZQ_CAL2_ZQ_CAL_START_N_MASK 0x00000002 5309 #define DDR34_F0_PHY_CONTROL_REGS_ZQ_CAL2_ZQ_CAL_START_N_ALIGN 0 5310 #define DDR34_F0_PHY_CONTROL_REGS_ZQ_CAL2_ZQ_CAL_START_N_BITS 1 5311 #define DDR34_F0_PHY_CONTROL_REGS_ZQ_CAL2_ZQ_CAL_START_N_SHIFT 1 5312 5313 /* DDR34_F0_PHY_CONTROL_REGS :: ZQ_CAL2 :: ZQ_CAL_START_P [00:00] */ 5314 #define DDR34_F0_PHY_CONTROL_REGS_ZQ_CAL2_ZQ_CAL_START_P_MASK 0x00000001 5315 #define DDR34_F0_PHY_CONTROL_REGS_ZQ_CAL2_ZQ_CAL_START_P_ALIGN 0 5316 #define DDR34_F0_PHY_CONTROL_REGS_ZQ_CAL2_ZQ_CAL_START_P_BITS 1 5317 #define DDR34_F0_PHY_CONTROL_REGS_ZQ_CAL2_ZQ_CAL_START_P_SHIFT 0 5318 5319 5320 /**************************************************************************** 5321 * DDR34_F0_PHY_CONTROL_REGS :: RO_PROC_MON_CTL 5322 */ 5323 /* DDR34_F0_PHY_CONTROL_REGS :: RO_PROC_MON_CTL :: reserved0 [31:27] */ 5324 #define DDR34_F0_PHY_CONTROL_REGS_RO_PROC_MON_CTL_RESERVED0_MASK 0xf8000000 5325 #define DDR34_F0_PHY_CONTROL_REGS_RO_PROC_MON_CTL_RESERVED0_ALIGN 0 5326 #define DDR34_F0_PHY_CONTROL_REGS_RO_PROC_MON_CTL_RESERVED0_BITS 5 5327 #define DDR34_F0_PHY_CONTROL_REGS_RO_PROC_MON_CTL_RESERVED0_SHIFT 27 5328 5329 /* DDR34_F0_PHY_CONTROL_REGS :: RO_PROC_MON_CTL :: BUSY [26:26] */ 5330 #define DDR34_F0_PHY_CONTROL_REGS_RO_PROC_MON_CTL_BUSY_MASK 0x04000000 5331 #define DDR34_F0_PHY_CONTROL_REGS_RO_PROC_MON_CTL_BUSY_ALIGN 0 5332 #define DDR34_F0_PHY_CONTROL_REGS_RO_PROC_MON_CTL_BUSY_BITS 1 5333 #define DDR34_F0_PHY_CONTROL_REGS_RO_PROC_MON_CTL_BUSY_SHIFT 26 5334 5335 /* DDR34_F0_PHY_CONTROL_REGS :: RO_PROC_MON_CTL :: TRIGGER [25:25] */ 5336 #define DDR34_F0_PHY_CONTROL_REGS_RO_PROC_MON_CTL_TRIGGER_MASK 0x02000000 5337 #define DDR34_F0_PHY_CONTROL_REGS_RO_PROC_MON_CTL_TRIGGER_ALIGN 0 5338 #define DDR34_F0_PHY_CONTROL_REGS_RO_PROC_MON_CTL_TRIGGER_BITS 1 5339 #define DDR34_F0_PHY_CONTROL_REGS_RO_PROC_MON_CTL_TRIGGER_SHIFT 25 5340 5341 /* DDR34_F0_PHY_CONTROL_REGS :: RO_PROC_MON_CTL :: RESET [24:24] */ 5342 #define DDR34_F0_PHY_CONTROL_REGS_RO_PROC_MON_CTL_RESET_MASK 0x01000000 5343 #define DDR34_F0_PHY_CONTROL_REGS_RO_PROC_MON_CTL_RESET_ALIGN 0 5344 #define DDR34_F0_PHY_CONTROL_REGS_RO_PROC_MON_CTL_RESET_BITS 1 5345 #define DDR34_F0_PHY_CONTROL_REGS_RO_PROC_MON_CTL_RESET_SHIFT 24 5346 5347 /* DDR34_F0_PHY_CONTROL_REGS :: RO_PROC_MON_CTL :: SEL [23:12] */ 5348 #define DDR34_F0_PHY_CONTROL_REGS_RO_PROC_MON_CTL_SEL_MASK 0x00fff000 5349 #define DDR34_F0_PHY_CONTROL_REGS_RO_PROC_MON_CTL_SEL_ALIGN 0 5350 #define DDR34_F0_PHY_CONTROL_REGS_RO_PROC_MON_CTL_SEL_BITS 12 5351 #define DDR34_F0_PHY_CONTROL_REGS_RO_PROC_MON_CTL_SEL_SHIFT 12 5352 5353 /* DDR34_F0_PHY_CONTROL_REGS :: RO_PROC_MON_CTL :: EN [11:00] */ 5354 #define DDR34_F0_PHY_CONTROL_REGS_RO_PROC_MON_CTL_EN_MASK 0x00000fff 5355 #define DDR34_F0_PHY_CONTROL_REGS_RO_PROC_MON_CTL_EN_ALIGN 0 5356 #define DDR34_F0_PHY_CONTROL_REGS_RO_PROC_MON_CTL_EN_BITS 12 5357 #define DDR34_F0_PHY_CONTROL_REGS_RO_PROC_MON_CTL_EN_SHIFT 0 5358 5359 5360 /**************************************************************************** 5361 * DDR34_F0_PHY_CONTROL_REGS :: RO_PROC_MON_STATUS 5362 */ 5363 /* DDR34_F0_PHY_CONTROL_REGS :: RO_PROC_MON_STATUS :: CLK_COUNT [31:08] */ 5364 #define DDR34_F0_PHY_CONTROL_REGS_RO_PROC_MON_STATUS_CLK_COUNT_MASK 0xffffff00 5365 #define DDR34_F0_PHY_CONTROL_REGS_RO_PROC_MON_STATUS_CLK_COUNT_ALIGN 0 5366 #define DDR34_F0_PHY_CONTROL_REGS_RO_PROC_MON_STATUS_CLK_COUNT_BITS 24 5367 #define DDR34_F0_PHY_CONTROL_REGS_RO_PROC_MON_STATUS_CLK_COUNT_SHIFT 8 5368 5369 /* DDR34_F0_PHY_CONTROL_REGS :: RO_PROC_MON_STATUS :: RO_COUNT [07:00] */ 5370 #define DDR34_F0_PHY_CONTROL_REGS_RO_PROC_MON_STATUS_RO_COUNT_MASK 0x000000ff 5371 #define DDR34_F0_PHY_CONTROL_REGS_RO_PROC_MON_STATUS_RO_COUNT_ALIGN 0 5372 #define DDR34_F0_PHY_CONTROL_REGS_RO_PROC_MON_STATUS_RO_COUNT_BITS 8 5373 #define DDR34_F0_PHY_CONTROL_REGS_RO_PROC_MON_STATUS_RO_COUNT_SHIFT 0 5374 5375 5376 /**************************************************************************** 5377 * DDR34_F0_PHY_CONTROL_REGS :: CK_DRIVE_PAD_CTL 5378 */ 5379 /* DDR34_F0_PHY_CONTROL_REGS :: CK_DRIVE_PAD_CTL :: reserved0 [31:30] */ 5380 #define DDR34_F0_PHY_CONTROL_REGS_CK_DRIVE_PAD_CTL_RESERVED0_MASK 0xc0000000 5381 #define DDR34_F0_PHY_CONTROL_REGS_CK_DRIVE_PAD_CTL_RESERVED0_ALIGN 0 5382 #define DDR34_F0_PHY_CONTROL_REGS_CK_DRIVE_PAD_CTL_RESERVED0_BITS 2 5383 #define DDR34_F0_PHY_CONTROL_REGS_CK_DRIVE_PAD_CTL_RESERVED0_SHIFT 30 5384 5385 /* DDR34_F0_PHY_CONTROL_REGS :: CK_DRIVE_PAD_CTL :: ADDR_CTL_PD_IDLE_STRENGTH [29:25] */ 5386 #define DDR34_F0_PHY_CONTROL_REGS_CK_DRIVE_PAD_CTL_ADDR_CTL_PD_IDLE_STRENGTH_MASK 0x3e000000 5387 #define DDR34_F0_PHY_CONTROL_REGS_CK_DRIVE_PAD_CTL_ADDR_CTL_PD_IDLE_STRENGTH_ALIGN 0 5388 #define DDR34_F0_PHY_CONTROL_REGS_CK_DRIVE_PAD_CTL_ADDR_CTL_PD_IDLE_STRENGTH_BITS 5 5389 #define DDR34_F0_PHY_CONTROL_REGS_CK_DRIVE_PAD_CTL_ADDR_CTL_PD_IDLE_STRENGTH_SHIFT 25 5390 5391 /* DDR34_F0_PHY_CONTROL_REGS :: CK_DRIVE_PAD_CTL :: ADDR_CTL_ND_IDLE_STRENGTH [24:20] */ 5392 #define DDR34_F0_PHY_CONTROL_REGS_CK_DRIVE_PAD_CTL_ADDR_CTL_ND_IDLE_STRENGTH_MASK 0x01f00000 5393 #define DDR34_F0_PHY_CONTROL_REGS_CK_DRIVE_PAD_CTL_ADDR_CTL_ND_IDLE_STRENGTH_ALIGN 0 5394 #define DDR34_F0_PHY_CONTROL_REGS_CK_DRIVE_PAD_CTL_ADDR_CTL_ND_IDLE_STRENGTH_BITS 5 5395 #define DDR34_F0_PHY_CONTROL_REGS_CK_DRIVE_PAD_CTL_ADDR_CTL_ND_IDLE_STRENGTH_SHIFT 20 5396 5397 /* DDR34_F0_PHY_CONTROL_REGS :: CK_DRIVE_PAD_CTL :: ADDR_CTL_PD_TERM_STRENGTH [19:15] */ 5398 #define DDR34_F0_PHY_CONTROL_REGS_CK_DRIVE_PAD_CTL_ADDR_CTL_PD_TERM_STRENGTH_MASK 0x000f8000 5399 #define DDR34_F0_PHY_CONTROL_REGS_CK_DRIVE_PAD_CTL_ADDR_CTL_PD_TERM_STRENGTH_ALIGN 0 5400 #define DDR34_F0_PHY_CONTROL_REGS_CK_DRIVE_PAD_CTL_ADDR_CTL_PD_TERM_STRENGTH_BITS 5 5401 #define DDR34_F0_PHY_CONTROL_REGS_CK_DRIVE_PAD_CTL_ADDR_CTL_PD_TERM_STRENGTH_SHIFT 15 5402 5403 /* DDR34_F0_PHY_CONTROL_REGS :: CK_DRIVE_PAD_CTL :: ADDR_CTL_ND_TERM_STRENGTH [14:10] */ 5404 #define DDR34_F0_PHY_CONTROL_REGS_CK_DRIVE_PAD_CTL_ADDR_CTL_ND_TERM_STRENGTH_MASK 0x00007c00 5405 #define DDR34_F0_PHY_CONTROL_REGS_CK_DRIVE_PAD_CTL_ADDR_CTL_ND_TERM_STRENGTH_ALIGN 0 5406 #define DDR34_F0_PHY_CONTROL_REGS_CK_DRIVE_PAD_CTL_ADDR_CTL_ND_TERM_STRENGTH_BITS 5 5407 #define DDR34_F0_PHY_CONTROL_REGS_CK_DRIVE_PAD_CTL_ADDR_CTL_ND_TERM_STRENGTH_SHIFT 10 5408 5409 /* DDR34_F0_PHY_CONTROL_REGS :: CK_DRIVE_PAD_CTL :: ADDR_CTL_PD_STRENGTH [09:05] */ 5410 #define DDR34_F0_PHY_CONTROL_REGS_CK_DRIVE_PAD_CTL_ADDR_CTL_PD_STRENGTH_MASK 0x000003e0 5411 #define DDR34_F0_PHY_CONTROL_REGS_CK_DRIVE_PAD_CTL_ADDR_CTL_PD_STRENGTH_ALIGN 0 5412 #define DDR34_F0_PHY_CONTROL_REGS_CK_DRIVE_PAD_CTL_ADDR_CTL_PD_STRENGTH_BITS 5 5413 #define DDR34_F0_PHY_CONTROL_REGS_CK_DRIVE_PAD_CTL_ADDR_CTL_PD_STRENGTH_SHIFT 5 5414 5415 /* DDR34_F0_PHY_CONTROL_REGS :: CK_DRIVE_PAD_CTL :: ADDR_CTL_ND_STRENGTH [04:00] */ 5416 #define DDR34_F0_PHY_CONTROL_REGS_CK_DRIVE_PAD_CTL_ADDR_CTL_ND_STRENGTH_MASK 0x0000001f 5417 #define DDR34_F0_PHY_CONTROL_REGS_CK_DRIVE_PAD_CTL_ADDR_CTL_ND_STRENGTH_ALIGN 0 5418 #define DDR34_F0_PHY_CONTROL_REGS_CK_DRIVE_PAD_CTL_ADDR_CTL_ND_STRENGTH_BITS 5 5419 #define DDR34_F0_PHY_CONTROL_REGS_CK_DRIVE_PAD_CTL_ADDR_CTL_ND_STRENGTH_SHIFT 0 5420 5421 5422 /**************************************************************************** 5423 * DDR34_F0_PHY_CONTROL_REGS :: BYTE_LANE_ALIGN_MASKS 5424 */ 5425 /* DDR34_F0_PHY_CONTROL_REGS :: BYTE_LANE_ALIGN_MASKS :: reserved0 [31:26] */ 5426 #define DDR34_F0_PHY_CONTROL_REGS_BYTE_LANE_ALIGN_MASKS_RESERVED0_MASK 0xfc000000 5427 #define DDR34_F0_PHY_CONTROL_REGS_BYTE_LANE_ALIGN_MASKS_RESERVED0_ALIGN 0 5428 #define DDR34_F0_PHY_CONTROL_REGS_BYTE_LANE_ALIGN_MASKS_RESERVED0_BITS 6 5429 #define DDR34_F0_PHY_CONTROL_REGS_BYTE_LANE_ALIGN_MASKS_RESERVED0_SHIFT 26 5430 5431 /* DDR34_F0_PHY_CONTROL_REGS :: BYTE_LANE_ALIGN_MASKS :: MASK_ENABLE [25:25] */ 5432 #define DDR34_F0_PHY_CONTROL_REGS_BYTE_LANE_ALIGN_MASKS_MASK_ENABLE_MASK 0x02000000 5433 #define DDR34_F0_PHY_CONTROL_REGS_BYTE_LANE_ALIGN_MASKS_MASK_ENABLE_ALIGN 0 5434 #define DDR34_F0_PHY_CONTROL_REGS_BYTE_LANE_ALIGN_MASKS_MASK_ENABLE_BITS 1 5435 #define DDR34_F0_PHY_CONTROL_REGS_BYTE_LANE_ALIGN_MASKS_MASK_ENABLE_SHIFT 25 5436 5437 /* DDR34_F0_PHY_CONTROL_REGS :: BYTE_LANE_ALIGN_MASKS :: reserved1 [24:16] */ 5438 #define DDR34_F0_PHY_CONTROL_REGS_BYTE_LANE_ALIGN_MASKS_RESERVED1_MASK 0x01ff0000 5439 #define DDR34_F0_PHY_CONTROL_REGS_BYTE_LANE_ALIGN_MASKS_RESERVED1_ALIGN 0 5440 #define DDR34_F0_PHY_CONTROL_REGS_BYTE_LANE_ALIGN_MASKS_RESERVED1_BITS 9 5441 #define DDR34_F0_PHY_CONTROL_REGS_BYTE_LANE_ALIGN_MASKS_RESERVED1_SHIFT 16 5442 5443 /* DDR34_F0_PHY_CONTROL_REGS :: BYTE_LANE_ALIGN_MASKS :: BL3_MASK [15:12] */ 5444 #define DDR34_F0_PHY_CONTROL_REGS_BYTE_LANE_ALIGN_MASKS_BL3_MASK_MASK 0x0000f000 5445 #define DDR34_F0_PHY_CONTROL_REGS_BYTE_LANE_ALIGN_MASKS_BL3_MASK_ALIGN 0 5446 #define DDR34_F0_PHY_CONTROL_REGS_BYTE_LANE_ALIGN_MASKS_BL3_MASK_BITS 4 5447 #define DDR34_F0_PHY_CONTROL_REGS_BYTE_LANE_ALIGN_MASKS_BL3_MASK_SHIFT 12 5448 5449 /* DDR34_F0_PHY_CONTROL_REGS :: BYTE_LANE_ALIGN_MASKS :: BL2_MASK [11:08] */ 5450 #define DDR34_F0_PHY_CONTROL_REGS_BYTE_LANE_ALIGN_MASKS_BL2_MASK_MASK 0x00000f00 5451 #define DDR34_F0_PHY_CONTROL_REGS_BYTE_LANE_ALIGN_MASKS_BL2_MASK_ALIGN 0 5452 #define DDR34_F0_PHY_CONTROL_REGS_BYTE_LANE_ALIGN_MASKS_BL2_MASK_BITS 4 5453 #define DDR34_F0_PHY_CONTROL_REGS_BYTE_LANE_ALIGN_MASKS_BL2_MASK_SHIFT 8 5454 5455 /* DDR34_F0_PHY_CONTROL_REGS :: BYTE_LANE_ALIGN_MASKS :: BL1_MASK [07:04] */ 5456 #define DDR34_F0_PHY_CONTROL_REGS_BYTE_LANE_ALIGN_MASKS_BL1_MASK_MASK 0x000000f0 5457 #define DDR34_F0_PHY_CONTROL_REGS_BYTE_LANE_ALIGN_MASKS_BL1_MASK_ALIGN 0 5458 #define DDR34_F0_PHY_CONTROL_REGS_BYTE_LANE_ALIGN_MASKS_BL1_MASK_BITS 4 5459 #define DDR34_F0_PHY_CONTROL_REGS_BYTE_LANE_ALIGN_MASKS_BL1_MASK_SHIFT 4 5460 5461 /* DDR34_F0_PHY_CONTROL_REGS :: BYTE_LANE_ALIGN_MASKS :: BL0_MASK [03:00] */ 5462 #define DDR34_F0_PHY_CONTROL_REGS_BYTE_LANE_ALIGN_MASKS_BL0_MASK_MASK 0x0000000f 5463 #define DDR34_F0_PHY_CONTROL_REGS_BYTE_LANE_ALIGN_MASKS_BL0_MASK_ALIGN 0 5464 #define DDR34_F0_PHY_CONTROL_REGS_BYTE_LANE_ALIGN_MASKS_BL0_MASK_BITS 4 5465 #define DDR34_F0_PHY_CONTROL_REGS_BYTE_LANE_ALIGN_MASKS_BL0_MASK_SHIFT 0 5466 5467 5468 /**************************************************************************** 5469 * DDR34_F0_PHY_CONTROL_REGS :: CLOCK_IDLE 5470 */ 5471 /* DDR34_F0_PHY_CONTROL_REGS :: CLOCK_IDLE :: reserved0 [31:05] */ 5472 #define DDR34_F0_PHY_CONTROL_REGS_CLOCK_IDLE_RESERVED0_MASK 0xffffffe0 5473 #define DDR34_F0_PHY_CONTROL_REGS_CLOCK_IDLE_RESERVED0_ALIGN 0 5474 #define DDR34_F0_PHY_CONTROL_REGS_CLOCK_IDLE_RESERVED0_BITS 27 5475 #define DDR34_F0_PHY_CONTROL_REGS_CLOCK_IDLE_RESERVED0_SHIFT 5 5476 5477 /* DDR34_F0_PHY_CONTROL_REGS :: CLOCK_IDLE :: BIT_CLOCK_CS [04:04] */ 5478 #define DDR34_F0_PHY_CONTROL_REGS_CLOCK_IDLE_BIT_CLOCK_CS_MASK 0x00000010 5479 #define DDR34_F0_PHY_CONTROL_REGS_CLOCK_IDLE_BIT_CLOCK_CS_ALIGN 0 5480 #define DDR34_F0_PHY_CONTROL_REGS_CLOCK_IDLE_BIT_CLOCK_CS_BITS 1 5481 #define DDR34_F0_PHY_CONTROL_REGS_CLOCK_IDLE_BIT_CLOCK_CS_SHIFT 4 5482 5483 /* DDR34_F0_PHY_CONTROL_REGS :: CLOCK_IDLE :: BIT_CLOCK_LS [03:03] */ 5484 #define DDR34_F0_PHY_CONTROL_REGS_CLOCK_IDLE_BIT_CLOCK_LS_MASK 0x00000008 5485 #define DDR34_F0_PHY_CONTROL_REGS_CLOCK_IDLE_BIT_CLOCK_LS_ALIGN 0 5486 #define DDR34_F0_PHY_CONTROL_REGS_CLOCK_IDLE_BIT_CLOCK_LS_BITS 1 5487 #define DDR34_F0_PHY_CONTROL_REGS_CLOCK_IDLE_BIT_CLOCK_LS_SHIFT 3 5488 5489 /* DDR34_F0_PHY_CONTROL_REGS :: CLOCK_IDLE :: TO_MC_CLOCK [02:02] */ 5490 #define DDR34_F0_PHY_CONTROL_REGS_CLOCK_IDLE_TO_MC_CLOCK_MASK 0x00000004 5491 #define DDR34_F0_PHY_CONTROL_REGS_CLOCK_IDLE_TO_MC_CLOCK_ALIGN 0 5492 #define DDR34_F0_PHY_CONTROL_REGS_CLOCK_IDLE_TO_MC_CLOCK_BITS 1 5493 #define DDR34_F0_PHY_CONTROL_REGS_CLOCK_IDLE_TO_MC_CLOCK_SHIFT 2 5494 5495 /* DDR34_F0_PHY_CONTROL_REGS :: CLOCK_IDLE :: FROM_MC_CLOCK [01:01] */ 5496 #define DDR34_F0_PHY_CONTROL_REGS_CLOCK_IDLE_FROM_MC_CLOCK_MASK 0x00000002 5497 #define DDR34_F0_PHY_CONTROL_REGS_CLOCK_IDLE_FROM_MC_CLOCK_ALIGN 0 5498 #define DDR34_F0_PHY_CONTROL_REGS_CLOCK_IDLE_FROM_MC_CLOCK_BITS 1 5499 #define DDR34_F0_PHY_CONTROL_REGS_CLOCK_IDLE_FROM_MC_CLOCK_SHIFT 1 5500 5501 /* DDR34_F0_PHY_CONTROL_REGS :: CLOCK_IDLE :: BIT_CLOCK [00:00] */ 5502 #define DDR34_F0_PHY_CONTROL_REGS_CLOCK_IDLE_BIT_CLOCK_MASK 0x00000001 5503 #define DDR34_F0_PHY_CONTROL_REGS_CLOCK_IDLE_BIT_CLOCK_ALIGN 0 5504 #define DDR34_F0_PHY_CONTROL_REGS_CLOCK_IDLE_BIT_CLOCK_BITS 1 5505 #define DDR34_F0_PHY_CONTROL_REGS_CLOCK_IDLE_BIT_CLOCK_SHIFT 0 5506 5507 5508 /**************************************************************************** 5509 * DDR34_F0_PHY_CONTROL_REGS :: AC_SPARE_REG 5510 */ 5511 /* DDR34_F0_PHY_CONTROL_REGS :: AC_SPARE_REG :: reserved_for_eco0 [31:00] */ 5512 #define DDR34_F0_PHY_CONTROL_REGS_AC_SPARE_REG_RESERVED_FOR_ECO0_MASK 0xffffffff 5513 #define DDR34_F0_PHY_CONTROL_REGS_AC_SPARE_REG_RESERVED_FOR_ECO0_ALIGN 0 5514 #define DDR34_F0_PHY_CONTROL_REGS_AC_SPARE_REG_RESERVED_FOR_ECO0_BITS 32 5515 #define DDR34_F0_PHY_CONTROL_REGS_AC_SPARE_REG_RESERVED_FOR_ECO0_SHIFT 0 5516 5517 5518 /**************************************************************************** 5519 * DDR34_F0_PHY_DDR34_F0_PHY_BYTE_LANE_0 5520 */ 5521 /**************************************************************************** 5522 * DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQS 5523 */ 5524 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQS :: BUSY [31:31] */ 5525 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_BUSY_MASK 0x80000000 5526 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_BUSY_ALIGN 0 5527 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_BUSY_BITS 1 5528 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_BUSY_SHIFT 31 5529 5530 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQS :: reserved0 [30:17] */ 5531 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_RESERVED0_MASK 0x7ffe0000 5532 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_RESERVED0_ALIGN 0 5533 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_RESERVED0_BITS 14 5534 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_RESERVED0_SHIFT 17 5535 5536 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQS :: FORCE [16:16] */ 5537 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_FORCE_MASK 0x00010000 5538 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_FORCE_ALIGN 0 5539 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_FORCE_BITS 1 5540 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_FORCE_SHIFT 16 5541 5542 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQS :: reserved1 [15:13] */ 5543 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_RESERVED1_MASK 0x0000e000 5544 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_RESERVED1_ALIGN 0 5545 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_RESERVED1_BITS 3 5546 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_RESERVED1_SHIFT 13 5547 5548 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQS :: ADJ_EN [12:12] */ 5549 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_ADJ_EN_MASK 0x00001000 5550 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_ADJ_EN_ALIGN 0 5551 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_ADJ_EN_BITS 1 5552 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_ADJ_EN_SHIFT 12 5553 5554 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQS :: reserved2 [11:09] */ 5555 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_RESERVED2_MASK 0x00000e00 5556 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_RESERVED2_ALIGN 0 5557 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_RESERVED2_BITS 3 5558 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_RESERVED2_SHIFT 9 5559 5560 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQS :: VDL_STEP [08:00] */ 5561 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_VDL_STEP_MASK 0x000001ff 5562 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_VDL_STEP_ALIGN 0 5563 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_VDL_STEP_BITS 9 5564 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_VDL_STEP_SHIFT 0 5565 5566 5567 /**************************************************************************** 5568 * DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ0 5569 */ 5570 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ0 :: BUSY [31:31] */ 5571 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0_BUSY_MASK 0x80000000 5572 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0_BUSY_ALIGN 0 5573 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0_BUSY_BITS 1 5574 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0_BUSY_SHIFT 31 5575 5576 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ0 :: reserved0 [30:17] */ 5577 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0_RESERVED0_MASK 0x7ffe0000 5578 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0_RESERVED0_ALIGN 0 5579 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0_RESERVED0_BITS 14 5580 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0_RESERVED0_SHIFT 17 5581 5582 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ0 :: FORCE [16:16] */ 5583 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0_FORCE_MASK 0x00010000 5584 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0_FORCE_ALIGN 0 5585 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0_FORCE_BITS 1 5586 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0_FORCE_SHIFT 16 5587 5588 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ0 :: reserved1 [15:13] */ 5589 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0_RESERVED1_MASK 0x0000e000 5590 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0_RESERVED1_ALIGN 0 5591 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0_RESERVED1_BITS 3 5592 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0_RESERVED1_SHIFT 13 5593 5594 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ0 :: ADJ_EN [12:12] */ 5595 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0_ADJ_EN_MASK 0x00001000 5596 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0_ADJ_EN_ALIGN 0 5597 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0_ADJ_EN_BITS 1 5598 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0_ADJ_EN_SHIFT 12 5599 5600 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ0 :: reserved2 [11:09] */ 5601 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0_RESERVED2_MASK 0x00000e00 5602 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0_RESERVED2_ALIGN 0 5603 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0_RESERVED2_BITS 3 5604 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0_RESERVED2_SHIFT 9 5605 5606 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ0 :: VDL_STEP [08:00] */ 5607 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0_VDL_STEP_MASK 0x000001ff 5608 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0_VDL_STEP_ALIGN 0 5609 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0_VDL_STEP_BITS 9 5610 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0_VDL_STEP_SHIFT 0 5611 5612 5613 /**************************************************************************** 5614 * DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ1 5615 */ 5616 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ1 :: BUSY [31:31] */ 5617 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1_BUSY_MASK 0x80000000 5618 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1_BUSY_ALIGN 0 5619 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1_BUSY_BITS 1 5620 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1_BUSY_SHIFT 31 5621 5622 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ1 :: reserved0 [30:17] */ 5623 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1_RESERVED0_MASK 0x7ffe0000 5624 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1_RESERVED0_ALIGN 0 5625 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1_RESERVED0_BITS 14 5626 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1_RESERVED0_SHIFT 17 5627 5628 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ1 :: FORCE [16:16] */ 5629 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1_FORCE_MASK 0x00010000 5630 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1_FORCE_ALIGN 0 5631 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1_FORCE_BITS 1 5632 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1_FORCE_SHIFT 16 5633 5634 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ1 :: reserved1 [15:13] */ 5635 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1_RESERVED1_MASK 0x0000e000 5636 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1_RESERVED1_ALIGN 0 5637 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1_RESERVED1_BITS 3 5638 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1_RESERVED1_SHIFT 13 5639 5640 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ1 :: ADJ_EN [12:12] */ 5641 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1_ADJ_EN_MASK 0x00001000 5642 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1_ADJ_EN_ALIGN 0 5643 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1_ADJ_EN_BITS 1 5644 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1_ADJ_EN_SHIFT 12 5645 5646 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ1 :: reserved2 [11:09] */ 5647 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1_RESERVED2_MASK 0x00000e00 5648 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1_RESERVED2_ALIGN 0 5649 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1_RESERVED2_BITS 3 5650 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1_RESERVED2_SHIFT 9 5651 5652 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ1 :: VDL_STEP [08:00] */ 5653 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1_VDL_STEP_MASK 0x000001ff 5654 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1_VDL_STEP_ALIGN 0 5655 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1_VDL_STEP_BITS 9 5656 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1_VDL_STEP_SHIFT 0 5657 5658 5659 /**************************************************************************** 5660 * DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ2 5661 */ 5662 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ2 :: BUSY [31:31] */ 5663 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2_BUSY_MASK 0x80000000 5664 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2_BUSY_ALIGN 0 5665 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2_BUSY_BITS 1 5666 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2_BUSY_SHIFT 31 5667 5668 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ2 :: reserved0 [30:17] */ 5669 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2_RESERVED0_MASK 0x7ffe0000 5670 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2_RESERVED0_ALIGN 0 5671 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2_RESERVED0_BITS 14 5672 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2_RESERVED0_SHIFT 17 5673 5674 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ2 :: FORCE [16:16] */ 5675 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2_FORCE_MASK 0x00010000 5676 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2_FORCE_ALIGN 0 5677 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2_FORCE_BITS 1 5678 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2_FORCE_SHIFT 16 5679 5680 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ2 :: reserved1 [15:13] */ 5681 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2_RESERVED1_MASK 0x0000e000 5682 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2_RESERVED1_ALIGN 0 5683 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2_RESERVED1_BITS 3 5684 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2_RESERVED1_SHIFT 13 5685 5686 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ2 :: ADJ_EN [12:12] */ 5687 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2_ADJ_EN_MASK 0x00001000 5688 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2_ADJ_EN_ALIGN 0 5689 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2_ADJ_EN_BITS 1 5690 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2_ADJ_EN_SHIFT 12 5691 5692 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ2 :: reserved2 [11:09] */ 5693 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2_RESERVED2_MASK 0x00000e00 5694 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2_RESERVED2_ALIGN 0 5695 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2_RESERVED2_BITS 3 5696 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2_RESERVED2_SHIFT 9 5697 5698 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ2 :: VDL_STEP [08:00] */ 5699 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2_VDL_STEP_MASK 0x000001ff 5700 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2_VDL_STEP_ALIGN 0 5701 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2_VDL_STEP_BITS 9 5702 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2_VDL_STEP_SHIFT 0 5703 5704 5705 /**************************************************************************** 5706 * DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ3 5707 */ 5708 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ3 :: BUSY [31:31] */ 5709 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3_BUSY_MASK 0x80000000 5710 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3_BUSY_ALIGN 0 5711 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3_BUSY_BITS 1 5712 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3_BUSY_SHIFT 31 5713 5714 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ3 :: reserved0 [30:17] */ 5715 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3_RESERVED0_MASK 0x7ffe0000 5716 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3_RESERVED0_ALIGN 0 5717 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3_RESERVED0_BITS 14 5718 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3_RESERVED0_SHIFT 17 5719 5720 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ3 :: FORCE [16:16] */ 5721 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3_FORCE_MASK 0x00010000 5722 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3_FORCE_ALIGN 0 5723 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3_FORCE_BITS 1 5724 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3_FORCE_SHIFT 16 5725 5726 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ3 :: reserved1 [15:13] */ 5727 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3_RESERVED1_MASK 0x0000e000 5728 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3_RESERVED1_ALIGN 0 5729 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3_RESERVED1_BITS 3 5730 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3_RESERVED1_SHIFT 13 5731 5732 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ3 :: ADJ_EN [12:12] */ 5733 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3_ADJ_EN_MASK 0x00001000 5734 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3_ADJ_EN_ALIGN 0 5735 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3_ADJ_EN_BITS 1 5736 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3_ADJ_EN_SHIFT 12 5737 5738 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ3 :: reserved2 [11:09] */ 5739 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3_RESERVED2_MASK 0x00000e00 5740 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3_RESERVED2_ALIGN 0 5741 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3_RESERVED2_BITS 3 5742 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3_RESERVED2_SHIFT 9 5743 5744 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ3 :: VDL_STEP [08:00] */ 5745 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3_VDL_STEP_MASK 0x000001ff 5746 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3_VDL_STEP_ALIGN 0 5747 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3_VDL_STEP_BITS 9 5748 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3_VDL_STEP_SHIFT 0 5749 5750 5751 /**************************************************************************** 5752 * DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ4 5753 */ 5754 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ4 :: BUSY [31:31] */ 5755 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4_BUSY_MASK 0x80000000 5756 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4_BUSY_ALIGN 0 5757 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4_BUSY_BITS 1 5758 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4_BUSY_SHIFT 31 5759 5760 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ4 :: reserved0 [30:17] */ 5761 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4_RESERVED0_MASK 0x7ffe0000 5762 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4_RESERVED0_ALIGN 0 5763 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4_RESERVED0_BITS 14 5764 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4_RESERVED0_SHIFT 17 5765 5766 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ4 :: FORCE [16:16] */ 5767 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4_FORCE_MASK 0x00010000 5768 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4_FORCE_ALIGN 0 5769 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4_FORCE_BITS 1 5770 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4_FORCE_SHIFT 16 5771 5772 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ4 :: reserved1 [15:13] */ 5773 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4_RESERVED1_MASK 0x0000e000 5774 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4_RESERVED1_ALIGN 0 5775 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4_RESERVED1_BITS 3 5776 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4_RESERVED1_SHIFT 13 5777 5778 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ4 :: ADJ_EN [12:12] */ 5779 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4_ADJ_EN_MASK 0x00001000 5780 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4_ADJ_EN_ALIGN 0 5781 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4_ADJ_EN_BITS 1 5782 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4_ADJ_EN_SHIFT 12 5783 5784 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ4 :: reserved2 [11:09] */ 5785 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4_RESERVED2_MASK 0x00000e00 5786 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4_RESERVED2_ALIGN 0 5787 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4_RESERVED2_BITS 3 5788 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4_RESERVED2_SHIFT 9 5789 5790 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ4 :: VDL_STEP [08:00] */ 5791 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4_VDL_STEP_MASK 0x000001ff 5792 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4_VDL_STEP_ALIGN 0 5793 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4_VDL_STEP_BITS 9 5794 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4_VDL_STEP_SHIFT 0 5795 5796 5797 /**************************************************************************** 5798 * DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ5 5799 */ 5800 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ5 :: BUSY [31:31] */ 5801 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5_BUSY_MASK 0x80000000 5802 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5_BUSY_ALIGN 0 5803 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5_BUSY_BITS 1 5804 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5_BUSY_SHIFT 31 5805 5806 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ5 :: reserved0 [30:17] */ 5807 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5_RESERVED0_MASK 0x7ffe0000 5808 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5_RESERVED0_ALIGN 0 5809 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5_RESERVED0_BITS 14 5810 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5_RESERVED0_SHIFT 17 5811 5812 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ5 :: FORCE [16:16] */ 5813 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5_FORCE_MASK 0x00010000 5814 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5_FORCE_ALIGN 0 5815 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5_FORCE_BITS 1 5816 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5_FORCE_SHIFT 16 5817 5818 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ5 :: reserved1 [15:13] */ 5819 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5_RESERVED1_MASK 0x0000e000 5820 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5_RESERVED1_ALIGN 0 5821 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5_RESERVED1_BITS 3 5822 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5_RESERVED1_SHIFT 13 5823 5824 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ5 :: ADJ_EN [12:12] */ 5825 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5_ADJ_EN_MASK 0x00001000 5826 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5_ADJ_EN_ALIGN 0 5827 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5_ADJ_EN_BITS 1 5828 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5_ADJ_EN_SHIFT 12 5829 5830 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ5 :: reserved2 [11:09] */ 5831 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5_RESERVED2_MASK 0x00000e00 5832 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5_RESERVED2_ALIGN 0 5833 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5_RESERVED2_BITS 3 5834 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5_RESERVED2_SHIFT 9 5835 5836 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ5 :: VDL_STEP [08:00] */ 5837 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5_VDL_STEP_MASK 0x000001ff 5838 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5_VDL_STEP_ALIGN 0 5839 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5_VDL_STEP_BITS 9 5840 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5_VDL_STEP_SHIFT 0 5841 5842 5843 /**************************************************************************** 5844 * DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ6 5845 */ 5846 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ6 :: BUSY [31:31] */ 5847 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6_BUSY_MASK 0x80000000 5848 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6_BUSY_ALIGN 0 5849 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6_BUSY_BITS 1 5850 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6_BUSY_SHIFT 31 5851 5852 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ6 :: reserved0 [30:17] */ 5853 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6_RESERVED0_MASK 0x7ffe0000 5854 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6_RESERVED0_ALIGN 0 5855 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6_RESERVED0_BITS 14 5856 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6_RESERVED0_SHIFT 17 5857 5858 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ6 :: FORCE [16:16] */ 5859 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6_FORCE_MASK 0x00010000 5860 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6_FORCE_ALIGN 0 5861 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6_FORCE_BITS 1 5862 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6_FORCE_SHIFT 16 5863 5864 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ6 :: reserved1 [15:13] */ 5865 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6_RESERVED1_MASK 0x0000e000 5866 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6_RESERVED1_ALIGN 0 5867 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6_RESERVED1_BITS 3 5868 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6_RESERVED1_SHIFT 13 5869 5870 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ6 :: ADJ_EN [12:12] */ 5871 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6_ADJ_EN_MASK 0x00001000 5872 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6_ADJ_EN_ALIGN 0 5873 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6_ADJ_EN_BITS 1 5874 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6_ADJ_EN_SHIFT 12 5875 5876 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ6 :: reserved2 [11:09] */ 5877 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6_RESERVED2_MASK 0x00000e00 5878 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6_RESERVED2_ALIGN 0 5879 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6_RESERVED2_BITS 3 5880 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6_RESERVED2_SHIFT 9 5881 5882 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ6 :: VDL_STEP [08:00] */ 5883 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6_VDL_STEP_MASK 0x000001ff 5884 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6_VDL_STEP_ALIGN 0 5885 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6_VDL_STEP_BITS 9 5886 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6_VDL_STEP_SHIFT 0 5887 5888 5889 /**************************************************************************** 5890 * DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ7 5891 */ 5892 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ7 :: BUSY [31:31] */ 5893 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7_BUSY_MASK 0x80000000 5894 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7_BUSY_ALIGN 0 5895 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7_BUSY_BITS 1 5896 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7_BUSY_SHIFT 31 5897 5898 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ7 :: reserved0 [30:17] */ 5899 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7_RESERVED0_MASK 0x7ffe0000 5900 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7_RESERVED0_ALIGN 0 5901 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7_RESERVED0_BITS 14 5902 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7_RESERVED0_SHIFT 17 5903 5904 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ7 :: FORCE [16:16] */ 5905 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7_FORCE_MASK 0x00010000 5906 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7_FORCE_ALIGN 0 5907 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7_FORCE_BITS 1 5908 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7_FORCE_SHIFT 16 5909 5910 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ7 :: reserved1 [15:13] */ 5911 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7_RESERVED1_MASK 0x0000e000 5912 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7_RESERVED1_ALIGN 0 5913 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7_RESERVED1_BITS 3 5914 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7_RESERVED1_SHIFT 13 5915 5916 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ7 :: ADJ_EN [12:12] */ 5917 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7_ADJ_EN_MASK 0x00001000 5918 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7_ADJ_EN_ALIGN 0 5919 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7_ADJ_EN_BITS 1 5920 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7_ADJ_EN_SHIFT 12 5921 5922 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ7 :: reserved2 [11:09] */ 5923 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7_RESERVED2_MASK 0x00000e00 5924 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7_RESERVED2_ALIGN 0 5925 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7_RESERVED2_BITS 3 5926 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7_RESERVED2_SHIFT 9 5927 5928 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ7 :: VDL_STEP [08:00] */ 5929 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7_VDL_STEP_MASK 0x000001ff 5930 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7_VDL_STEP_ALIGN 0 5931 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7_VDL_STEP_BITS 9 5932 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7_VDL_STEP_SHIFT 0 5933 5934 5935 /**************************************************************************** 5936 * DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DM 5937 */ 5938 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DM :: BUSY [31:31] */ 5939 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DM_BUSY_MASK 0x80000000 5940 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DM_BUSY_ALIGN 0 5941 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DM_BUSY_BITS 1 5942 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DM_BUSY_SHIFT 31 5943 5944 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DM :: reserved0 [30:17] */ 5945 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DM_RESERVED0_MASK 0x7ffe0000 5946 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DM_RESERVED0_ALIGN 0 5947 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DM_RESERVED0_BITS 14 5948 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DM_RESERVED0_SHIFT 17 5949 5950 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DM :: FORCE [16:16] */ 5951 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DM_FORCE_MASK 0x00010000 5952 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DM_FORCE_ALIGN 0 5953 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DM_FORCE_BITS 1 5954 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DM_FORCE_SHIFT 16 5955 5956 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DM :: reserved1 [15:13] */ 5957 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DM_RESERVED1_MASK 0x0000e000 5958 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DM_RESERVED1_ALIGN 0 5959 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DM_RESERVED1_BITS 3 5960 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DM_RESERVED1_SHIFT 13 5961 5962 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DM :: ADJ_EN [12:12] */ 5963 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DM_ADJ_EN_MASK 0x00001000 5964 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DM_ADJ_EN_ALIGN 0 5965 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DM_ADJ_EN_BITS 1 5966 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DM_ADJ_EN_SHIFT 12 5967 5968 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DM :: reserved2 [11:09] */ 5969 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DM_RESERVED2_MASK 0x00000e00 5970 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DM_RESERVED2_ALIGN 0 5971 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DM_RESERVED2_BITS 3 5972 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DM_RESERVED2_SHIFT 9 5973 5974 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DM :: VDL_STEP [08:00] */ 5975 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DM_VDL_STEP_MASK 0x000001ff 5976 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DM_VDL_STEP_ALIGN 0 5977 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DM_VDL_STEP_BITS 9 5978 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DM_VDL_STEP_SHIFT 0 5979 5980 5981 /**************************************************************************** 5982 * DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_ALERT 5983 */ 5984 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_ALERT :: BUSY [31:31] */ 5985 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_ALERT_BUSY_MASK 0x80000000 5986 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_ALERT_BUSY_ALIGN 0 5987 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_ALERT_BUSY_BITS 1 5988 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_ALERT_BUSY_SHIFT 31 5989 5990 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_ALERT :: reserved0 [30:17] */ 5991 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_ALERT_RESERVED0_MASK 0x7ffe0000 5992 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_ALERT_RESERVED0_ALIGN 0 5993 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_ALERT_RESERVED0_BITS 14 5994 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_ALERT_RESERVED0_SHIFT 17 5995 5996 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_ALERT :: FORCE [16:16] */ 5997 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_ALERT_FORCE_MASK 0x00010000 5998 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_ALERT_FORCE_ALIGN 0 5999 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_ALERT_FORCE_BITS 1 6000 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_ALERT_FORCE_SHIFT 16 6001 6002 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_ALERT :: reserved1 [15:13] */ 6003 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_ALERT_RESERVED1_MASK 0x0000e000 6004 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_ALERT_RESERVED1_ALIGN 0 6005 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_ALERT_RESERVED1_BITS 3 6006 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_ALERT_RESERVED1_SHIFT 13 6007 6008 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_ALERT :: ADJ_EN [12:12] */ 6009 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_ALERT_ADJ_EN_MASK 0x00001000 6010 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_ALERT_ADJ_EN_ALIGN 0 6011 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_ALERT_ADJ_EN_BITS 1 6012 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_ALERT_ADJ_EN_SHIFT 12 6013 6014 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_ALERT :: reserved2 [11:09] */ 6015 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_ALERT_RESERVED2_MASK 0x00000e00 6016 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_ALERT_RESERVED2_ALIGN 0 6017 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_ALERT_RESERVED2_BITS 3 6018 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_ALERT_RESERVED2_SHIFT 9 6019 6020 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_ALERT :: VDL_STEP [08:00] */ 6021 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_ALERT_VDL_STEP_MASK 0x000001ff 6022 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_ALERT_VDL_STEP_ALIGN 0 6023 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_ALERT_VDL_STEP_BITS 9 6024 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_ALERT_VDL_STEP_SHIFT 0 6025 6026 6027 /**************************************************************************** 6028 * DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQSP 6029 */ 6030 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQSP :: BUSY [31:31] */ 6031 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSP_BUSY_MASK 0x80000000 6032 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSP_BUSY_ALIGN 0 6033 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSP_BUSY_BITS 1 6034 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSP_BUSY_SHIFT 31 6035 6036 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQSP :: reserved0 [30:17] */ 6037 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSP_RESERVED0_MASK 0x7ffe0000 6038 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSP_RESERVED0_ALIGN 0 6039 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSP_RESERVED0_BITS 14 6040 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSP_RESERVED0_SHIFT 17 6041 6042 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQSP :: FORCE [16:16] */ 6043 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSP_FORCE_MASK 0x00010000 6044 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSP_FORCE_ALIGN 0 6045 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSP_FORCE_BITS 1 6046 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSP_FORCE_SHIFT 16 6047 6048 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQSP :: reserved1 [15:13] */ 6049 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSP_RESERVED1_MASK 0x0000e000 6050 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSP_RESERVED1_ALIGN 0 6051 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSP_RESERVED1_BITS 3 6052 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSP_RESERVED1_SHIFT 13 6053 6054 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQSP :: ADJ_EN [12:12] */ 6055 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSP_ADJ_EN_MASK 0x00001000 6056 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSP_ADJ_EN_ALIGN 0 6057 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSP_ADJ_EN_BITS 1 6058 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSP_ADJ_EN_SHIFT 12 6059 6060 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQSP :: reserved2 [11:08] */ 6061 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSP_RESERVED2_MASK 0x00000f00 6062 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSP_RESERVED2_ALIGN 0 6063 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSP_RESERVED2_BITS 4 6064 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSP_RESERVED2_SHIFT 8 6065 6066 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQSP :: VDL_STEP [07:00] */ 6067 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSP_VDL_STEP_MASK 0x000000ff 6068 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSP_VDL_STEP_ALIGN 0 6069 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSP_VDL_STEP_BITS 8 6070 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSP_VDL_STEP_SHIFT 0 6071 6072 6073 /**************************************************************************** 6074 * DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQSN 6075 */ 6076 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQSN :: BUSY [31:31] */ 6077 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSN_BUSY_MASK 0x80000000 6078 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSN_BUSY_ALIGN 0 6079 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSN_BUSY_BITS 1 6080 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSN_BUSY_SHIFT 31 6081 6082 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQSN :: reserved0 [30:17] */ 6083 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSN_RESERVED0_MASK 0x7ffe0000 6084 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSN_RESERVED0_ALIGN 0 6085 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSN_RESERVED0_BITS 14 6086 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSN_RESERVED0_SHIFT 17 6087 6088 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQSN :: FORCE [16:16] */ 6089 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSN_FORCE_MASK 0x00010000 6090 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSN_FORCE_ALIGN 0 6091 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSN_FORCE_BITS 1 6092 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSN_FORCE_SHIFT 16 6093 6094 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQSN :: reserved1 [15:13] */ 6095 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSN_RESERVED1_MASK 0x0000e000 6096 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSN_RESERVED1_ALIGN 0 6097 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSN_RESERVED1_BITS 3 6098 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSN_RESERVED1_SHIFT 13 6099 6100 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQSN :: ADJ_EN [12:12] */ 6101 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSN_ADJ_EN_MASK 0x00001000 6102 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSN_ADJ_EN_ALIGN 0 6103 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSN_ADJ_EN_BITS 1 6104 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSN_ADJ_EN_SHIFT 12 6105 6106 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQSN :: reserved2 [11:08] */ 6107 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSN_RESERVED2_MASK 0x00000f00 6108 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSN_RESERVED2_ALIGN 0 6109 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSN_RESERVED2_BITS 4 6110 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSN_RESERVED2_SHIFT 8 6111 6112 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQSN :: VDL_STEP [07:00] */ 6113 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSN_VDL_STEP_MASK 0x000000ff 6114 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSN_VDL_STEP_ALIGN 0 6115 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSN_VDL_STEP_BITS 8 6116 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSN_VDL_STEP_SHIFT 0 6117 6118 6119 /**************************************************************************** 6120 * DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ0P 6121 */ 6122 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ0P :: BUSY [31:31] */ 6123 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0P_BUSY_MASK 0x80000000 6124 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0P_BUSY_ALIGN 0 6125 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0P_BUSY_BITS 1 6126 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0P_BUSY_SHIFT 31 6127 6128 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ0P :: reserved0 [30:17] */ 6129 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0P_RESERVED0_MASK 0x7ffe0000 6130 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0P_RESERVED0_ALIGN 0 6131 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0P_RESERVED0_BITS 14 6132 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0P_RESERVED0_SHIFT 17 6133 6134 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ0P :: FORCE [16:16] */ 6135 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0P_FORCE_MASK 0x00010000 6136 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0P_FORCE_ALIGN 0 6137 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0P_FORCE_BITS 1 6138 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0P_FORCE_SHIFT 16 6139 6140 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ0P :: reserved1 [15:13] */ 6141 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0P_RESERVED1_MASK 0x0000e000 6142 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0P_RESERVED1_ALIGN 0 6143 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0P_RESERVED1_BITS 3 6144 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0P_RESERVED1_SHIFT 13 6145 6146 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ0P :: ADJ_EN [12:12] */ 6147 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0P_ADJ_EN_MASK 0x00001000 6148 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0P_ADJ_EN_ALIGN 0 6149 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0P_ADJ_EN_BITS 1 6150 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0P_ADJ_EN_SHIFT 12 6151 6152 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ0P :: reserved2 [11:08] */ 6153 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0P_RESERVED2_MASK 0x00000f00 6154 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0P_RESERVED2_ALIGN 0 6155 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0P_RESERVED2_BITS 4 6156 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0P_RESERVED2_SHIFT 8 6157 6158 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ0P :: VDL_STEP [07:00] */ 6159 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0P_VDL_STEP_MASK 0x000000ff 6160 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0P_VDL_STEP_ALIGN 0 6161 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0P_VDL_STEP_BITS 8 6162 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0P_VDL_STEP_SHIFT 0 6163 6164 6165 /**************************************************************************** 6166 * DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ0N 6167 */ 6168 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ0N :: BUSY [31:31] */ 6169 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0N_BUSY_MASK 0x80000000 6170 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0N_BUSY_ALIGN 0 6171 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0N_BUSY_BITS 1 6172 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0N_BUSY_SHIFT 31 6173 6174 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ0N :: reserved0 [30:17] */ 6175 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0N_RESERVED0_MASK 0x7ffe0000 6176 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0N_RESERVED0_ALIGN 0 6177 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0N_RESERVED0_BITS 14 6178 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0N_RESERVED0_SHIFT 17 6179 6180 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ0N :: FORCE [16:16] */ 6181 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0N_FORCE_MASK 0x00010000 6182 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0N_FORCE_ALIGN 0 6183 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0N_FORCE_BITS 1 6184 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0N_FORCE_SHIFT 16 6185 6186 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ0N :: reserved1 [15:13] */ 6187 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0N_RESERVED1_MASK 0x0000e000 6188 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0N_RESERVED1_ALIGN 0 6189 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0N_RESERVED1_BITS 3 6190 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0N_RESERVED1_SHIFT 13 6191 6192 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ0N :: ADJ_EN [12:12] */ 6193 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0N_ADJ_EN_MASK 0x00001000 6194 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0N_ADJ_EN_ALIGN 0 6195 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0N_ADJ_EN_BITS 1 6196 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0N_ADJ_EN_SHIFT 12 6197 6198 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ0N :: reserved2 [11:08] */ 6199 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0N_RESERVED2_MASK 0x00000f00 6200 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0N_RESERVED2_ALIGN 0 6201 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0N_RESERVED2_BITS 4 6202 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0N_RESERVED2_SHIFT 8 6203 6204 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ0N :: VDL_STEP [07:00] */ 6205 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0N_VDL_STEP_MASK 0x000000ff 6206 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0N_VDL_STEP_ALIGN 0 6207 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0N_VDL_STEP_BITS 8 6208 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0N_VDL_STEP_SHIFT 0 6209 6210 6211 /**************************************************************************** 6212 * DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ1P 6213 */ 6214 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ1P :: BUSY [31:31] */ 6215 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1P_BUSY_MASK 0x80000000 6216 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1P_BUSY_ALIGN 0 6217 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1P_BUSY_BITS 1 6218 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1P_BUSY_SHIFT 31 6219 6220 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ1P :: reserved0 [30:17] */ 6221 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1P_RESERVED0_MASK 0x7ffe0000 6222 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1P_RESERVED0_ALIGN 0 6223 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1P_RESERVED0_BITS 14 6224 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1P_RESERVED0_SHIFT 17 6225 6226 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ1P :: FORCE [16:16] */ 6227 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1P_FORCE_MASK 0x00010000 6228 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1P_FORCE_ALIGN 0 6229 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1P_FORCE_BITS 1 6230 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1P_FORCE_SHIFT 16 6231 6232 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ1P :: reserved1 [15:13] */ 6233 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1P_RESERVED1_MASK 0x0000e000 6234 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1P_RESERVED1_ALIGN 0 6235 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1P_RESERVED1_BITS 3 6236 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1P_RESERVED1_SHIFT 13 6237 6238 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ1P :: ADJ_EN [12:12] */ 6239 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1P_ADJ_EN_MASK 0x00001000 6240 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1P_ADJ_EN_ALIGN 0 6241 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1P_ADJ_EN_BITS 1 6242 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1P_ADJ_EN_SHIFT 12 6243 6244 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ1P :: reserved2 [11:08] */ 6245 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1P_RESERVED2_MASK 0x00000f00 6246 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1P_RESERVED2_ALIGN 0 6247 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1P_RESERVED2_BITS 4 6248 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1P_RESERVED2_SHIFT 8 6249 6250 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ1P :: VDL_STEP [07:00] */ 6251 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1P_VDL_STEP_MASK 0x000000ff 6252 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1P_VDL_STEP_ALIGN 0 6253 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1P_VDL_STEP_BITS 8 6254 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1P_VDL_STEP_SHIFT 0 6255 6256 6257 /**************************************************************************** 6258 * DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ1N 6259 */ 6260 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ1N :: BUSY [31:31] */ 6261 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1N_BUSY_MASK 0x80000000 6262 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1N_BUSY_ALIGN 0 6263 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1N_BUSY_BITS 1 6264 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1N_BUSY_SHIFT 31 6265 6266 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ1N :: reserved0 [30:17] */ 6267 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1N_RESERVED0_MASK 0x7ffe0000 6268 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1N_RESERVED0_ALIGN 0 6269 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1N_RESERVED0_BITS 14 6270 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1N_RESERVED0_SHIFT 17 6271 6272 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ1N :: FORCE [16:16] */ 6273 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1N_FORCE_MASK 0x00010000 6274 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1N_FORCE_ALIGN 0 6275 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1N_FORCE_BITS 1 6276 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1N_FORCE_SHIFT 16 6277 6278 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ1N :: reserved1 [15:13] */ 6279 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1N_RESERVED1_MASK 0x0000e000 6280 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1N_RESERVED1_ALIGN 0 6281 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1N_RESERVED1_BITS 3 6282 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1N_RESERVED1_SHIFT 13 6283 6284 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ1N :: ADJ_EN [12:12] */ 6285 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1N_ADJ_EN_MASK 0x00001000 6286 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1N_ADJ_EN_ALIGN 0 6287 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1N_ADJ_EN_BITS 1 6288 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1N_ADJ_EN_SHIFT 12 6289 6290 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ1N :: reserved2 [11:08] */ 6291 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1N_RESERVED2_MASK 0x00000f00 6292 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1N_RESERVED2_ALIGN 0 6293 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1N_RESERVED2_BITS 4 6294 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1N_RESERVED2_SHIFT 8 6295 6296 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ1N :: VDL_STEP [07:00] */ 6297 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1N_VDL_STEP_MASK 0x000000ff 6298 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1N_VDL_STEP_ALIGN 0 6299 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1N_VDL_STEP_BITS 8 6300 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1N_VDL_STEP_SHIFT 0 6301 6302 6303 /**************************************************************************** 6304 * DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ2P 6305 */ 6306 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ2P :: BUSY [31:31] */ 6307 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2P_BUSY_MASK 0x80000000 6308 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2P_BUSY_ALIGN 0 6309 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2P_BUSY_BITS 1 6310 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2P_BUSY_SHIFT 31 6311 6312 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ2P :: reserved0 [30:17] */ 6313 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2P_RESERVED0_MASK 0x7ffe0000 6314 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2P_RESERVED0_ALIGN 0 6315 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2P_RESERVED0_BITS 14 6316 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2P_RESERVED0_SHIFT 17 6317 6318 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ2P :: FORCE [16:16] */ 6319 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2P_FORCE_MASK 0x00010000 6320 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2P_FORCE_ALIGN 0 6321 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2P_FORCE_BITS 1 6322 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2P_FORCE_SHIFT 16 6323 6324 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ2P :: reserved1 [15:13] */ 6325 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2P_RESERVED1_MASK 0x0000e000 6326 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2P_RESERVED1_ALIGN 0 6327 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2P_RESERVED1_BITS 3 6328 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2P_RESERVED1_SHIFT 13 6329 6330 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ2P :: ADJ_EN [12:12] */ 6331 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2P_ADJ_EN_MASK 0x00001000 6332 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2P_ADJ_EN_ALIGN 0 6333 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2P_ADJ_EN_BITS 1 6334 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2P_ADJ_EN_SHIFT 12 6335 6336 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ2P :: reserved2 [11:08] */ 6337 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2P_RESERVED2_MASK 0x00000f00 6338 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2P_RESERVED2_ALIGN 0 6339 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2P_RESERVED2_BITS 4 6340 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2P_RESERVED2_SHIFT 8 6341 6342 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ2P :: VDL_STEP [07:00] */ 6343 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2P_VDL_STEP_MASK 0x000000ff 6344 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2P_VDL_STEP_ALIGN 0 6345 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2P_VDL_STEP_BITS 8 6346 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2P_VDL_STEP_SHIFT 0 6347 6348 6349 /**************************************************************************** 6350 * DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ2N 6351 */ 6352 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ2N :: BUSY [31:31] */ 6353 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2N_BUSY_MASK 0x80000000 6354 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2N_BUSY_ALIGN 0 6355 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2N_BUSY_BITS 1 6356 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2N_BUSY_SHIFT 31 6357 6358 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ2N :: reserved0 [30:17] */ 6359 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2N_RESERVED0_MASK 0x7ffe0000 6360 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2N_RESERVED0_ALIGN 0 6361 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2N_RESERVED0_BITS 14 6362 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2N_RESERVED0_SHIFT 17 6363 6364 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ2N :: FORCE [16:16] */ 6365 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2N_FORCE_MASK 0x00010000 6366 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2N_FORCE_ALIGN 0 6367 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2N_FORCE_BITS 1 6368 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2N_FORCE_SHIFT 16 6369 6370 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ2N :: reserved1 [15:13] */ 6371 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2N_RESERVED1_MASK 0x0000e000 6372 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2N_RESERVED1_ALIGN 0 6373 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2N_RESERVED1_BITS 3 6374 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2N_RESERVED1_SHIFT 13 6375 6376 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ2N :: ADJ_EN [12:12] */ 6377 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2N_ADJ_EN_MASK 0x00001000 6378 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2N_ADJ_EN_ALIGN 0 6379 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2N_ADJ_EN_BITS 1 6380 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2N_ADJ_EN_SHIFT 12 6381 6382 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ2N :: reserved2 [11:08] */ 6383 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2N_RESERVED2_MASK 0x00000f00 6384 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2N_RESERVED2_ALIGN 0 6385 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2N_RESERVED2_BITS 4 6386 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2N_RESERVED2_SHIFT 8 6387 6388 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ2N :: VDL_STEP [07:00] */ 6389 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2N_VDL_STEP_MASK 0x000000ff 6390 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2N_VDL_STEP_ALIGN 0 6391 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2N_VDL_STEP_BITS 8 6392 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2N_VDL_STEP_SHIFT 0 6393 6394 6395 /**************************************************************************** 6396 * DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ3P 6397 */ 6398 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ3P :: BUSY [31:31] */ 6399 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3P_BUSY_MASK 0x80000000 6400 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3P_BUSY_ALIGN 0 6401 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3P_BUSY_BITS 1 6402 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3P_BUSY_SHIFT 31 6403 6404 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ3P :: reserved0 [30:17] */ 6405 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3P_RESERVED0_MASK 0x7ffe0000 6406 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3P_RESERVED0_ALIGN 0 6407 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3P_RESERVED0_BITS 14 6408 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3P_RESERVED0_SHIFT 17 6409 6410 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ3P :: FORCE [16:16] */ 6411 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3P_FORCE_MASK 0x00010000 6412 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3P_FORCE_ALIGN 0 6413 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3P_FORCE_BITS 1 6414 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3P_FORCE_SHIFT 16 6415 6416 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ3P :: reserved1 [15:13] */ 6417 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3P_RESERVED1_MASK 0x0000e000 6418 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3P_RESERVED1_ALIGN 0 6419 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3P_RESERVED1_BITS 3 6420 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3P_RESERVED1_SHIFT 13 6421 6422 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ3P :: ADJ_EN [12:12] */ 6423 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3P_ADJ_EN_MASK 0x00001000 6424 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3P_ADJ_EN_ALIGN 0 6425 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3P_ADJ_EN_BITS 1 6426 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3P_ADJ_EN_SHIFT 12 6427 6428 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ3P :: reserved2 [11:08] */ 6429 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3P_RESERVED2_MASK 0x00000f00 6430 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3P_RESERVED2_ALIGN 0 6431 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3P_RESERVED2_BITS 4 6432 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3P_RESERVED2_SHIFT 8 6433 6434 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ3P :: VDL_STEP [07:00] */ 6435 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3P_VDL_STEP_MASK 0x000000ff 6436 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3P_VDL_STEP_ALIGN 0 6437 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3P_VDL_STEP_BITS 8 6438 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3P_VDL_STEP_SHIFT 0 6439 6440 6441 /**************************************************************************** 6442 * DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ3N 6443 */ 6444 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ3N :: BUSY [31:31] */ 6445 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3N_BUSY_MASK 0x80000000 6446 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3N_BUSY_ALIGN 0 6447 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3N_BUSY_BITS 1 6448 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3N_BUSY_SHIFT 31 6449 6450 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ3N :: reserved0 [30:17] */ 6451 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3N_RESERVED0_MASK 0x7ffe0000 6452 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3N_RESERVED0_ALIGN 0 6453 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3N_RESERVED0_BITS 14 6454 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3N_RESERVED0_SHIFT 17 6455 6456 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ3N :: FORCE [16:16] */ 6457 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3N_FORCE_MASK 0x00010000 6458 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3N_FORCE_ALIGN 0 6459 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3N_FORCE_BITS 1 6460 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3N_FORCE_SHIFT 16 6461 6462 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ3N :: reserved1 [15:13] */ 6463 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3N_RESERVED1_MASK 0x0000e000 6464 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3N_RESERVED1_ALIGN 0 6465 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3N_RESERVED1_BITS 3 6466 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3N_RESERVED1_SHIFT 13 6467 6468 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ3N :: ADJ_EN [12:12] */ 6469 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3N_ADJ_EN_MASK 0x00001000 6470 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3N_ADJ_EN_ALIGN 0 6471 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3N_ADJ_EN_BITS 1 6472 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3N_ADJ_EN_SHIFT 12 6473 6474 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ3N :: reserved2 [11:08] */ 6475 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3N_RESERVED2_MASK 0x00000f00 6476 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3N_RESERVED2_ALIGN 0 6477 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3N_RESERVED2_BITS 4 6478 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3N_RESERVED2_SHIFT 8 6479 6480 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ3N :: VDL_STEP [07:00] */ 6481 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3N_VDL_STEP_MASK 0x000000ff 6482 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3N_VDL_STEP_ALIGN 0 6483 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3N_VDL_STEP_BITS 8 6484 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3N_VDL_STEP_SHIFT 0 6485 6486 6487 /**************************************************************************** 6488 * DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ4P 6489 */ 6490 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ4P :: BUSY [31:31] */ 6491 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4P_BUSY_MASK 0x80000000 6492 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4P_BUSY_ALIGN 0 6493 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4P_BUSY_BITS 1 6494 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4P_BUSY_SHIFT 31 6495 6496 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ4P :: reserved0 [30:17] */ 6497 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4P_RESERVED0_MASK 0x7ffe0000 6498 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4P_RESERVED0_ALIGN 0 6499 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4P_RESERVED0_BITS 14 6500 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4P_RESERVED0_SHIFT 17 6501 6502 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ4P :: FORCE [16:16] */ 6503 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4P_FORCE_MASK 0x00010000 6504 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4P_FORCE_ALIGN 0 6505 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4P_FORCE_BITS 1 6506 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4P_FORCE_SHIFT 16 6507 6508 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ4P :: reserved1 [15:13] */ 6509 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4P_RESERVED1_MASK 0x0000e000 6510 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4P_RESERVED1_ALIGN 0 6511 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4P_RESERVED1_BITS 3 6512 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4P_RESERVED1_SHIFT 13 6513 6514 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ4P :: ADJ_EN [12:12] */ 6515 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4P_ADJ_EN_MASK 0x00001000 6516 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4P_ADJ_EN_ALIGN 0 6517 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4P_ADJ_EN_BITS 1 6518 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4P_ADJ_EN_SHIFT 12 6519 6520 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ4P :: reserved2 [11:08] */ 6521 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4P_RESERVED2_MASK 0x00000f00 6522 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4P_RESERVED2_ALIGN 0 6523 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4P_RESERVED2_BITS 4 6524 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4P_RESERVED2_SHIFT 8 6525 6526 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ4P :: VDL_STEP [07:00] */ 6527 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4P_VDL_STEP_MASK 0x000000ff 6528 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4P_VDL_STEP_ALIGN 0 6529 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4P_VDL_STEP_BITS 8 6530 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4P_VDL_STEP_SHIFT 0 6531 6532 6533 /**************************************************************************** 6534 * DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ4N 6535 */ 6536 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ4N :: BUSY [31:31] */ 6537 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4N_BUSY_MASK 0x80000000 6538 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4N_BUSY_ALIGN 0 6539 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4N_BUSY_BITS 1 6540 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4N_BUSY_SHIFT 31 6541 6542 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ4N :: reserved0 [30:17] */ 6543 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4N_RESERVED0_MASK 0x7ffe0000 6544 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4N_RESERVED0_ALIGN 0 6545 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4N_RESERVED0_BITS 14 6546 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4N_RESERVED0_SHIFT 17 6547 6548 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ4N :: FORCE [16:16] */ 6549 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4N_FORCE_MASK 0x00010000 6550 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4N_FORCE_ALIGN 0 6551 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4N_FORCE_BITS 1 6552 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4N_FORCE_SHIFT 16 6553 6554 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ4N :: reserved1 [15:13] */ 6555 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4N_RESERVED1_MASK 0x0000e000 6556 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4N_RESERVED1_ALIGN 0 6557 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4N_RESERVED1_BITS 3 6558 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4N_RESERVED1_SHIFT 13 6559 6560 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ4N :: ADJ_EN [12:12] */ 6561 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4N_ADJ_EN_MASK 0x00001000 6562 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4N_ADJ_EN_ALIGN 0 6563 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4N_ADJ_EN_BITS 1 6564 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4N_ADJ_EN_SHIFT 12 6565 6566 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ4N :: reserved2 [11:08] */ 6567 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4N_RESERVED2_MASK 0x00000f00 6568 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4N_RESERVED2_ALIGN 0 6569 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4N_RESERVED2_BITS 4 6570 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4N_RESERVED2_SHIFT 8 6571 6572 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ4N :: VDL_STEP [07:00] */ 6573 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4N_VDL_STEP_MASK 0x000000ff 6574 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4N_VDL_STEP_ALIGN 0 6575 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4N_VDL_STEP_BITS 8 6576 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4N_VDL_STEP_SHIFT 0 6577 6578 6579 /**************************************************************************** 6580 * DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ5P 6581 */ 6582 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ5P :: BUSY [31:31] */ 6583 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5P_BUSY_MASK 0x80000000 6584 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5P_BUSY_ALIGN 0 6585 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5P_BUSY_BITS 1 6586 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5P_BUSY_SHIFT 31 6587 6588 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ5P :: reserved0 [30:17] */ 6589 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5P_RESERVED0_MASK 0x7ffe0000 6590 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5P_RESERVED0_ALIGN 0 6591 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5P_RESERVED0_BITS 14 6592 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5P_RESERVED0_SHIFT 17 6593 6594 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ5P :: FORCE [16:16] */ 6595 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5P_FORCE_MASK 0x00010000 6596 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5P_FORCE_ALIGN 0 6597 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5P_FORCE_BITS 1 6598 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5P_FORCE_SHIFT 16 6599 6600 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ5P :: reserved1 [15:13] */ 6601 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5P_RESERVED1_MASK 0x0000e000 6602 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5P_RESERVED1_ALIGN 0 6603 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5P_RESERVED1_BITS 3 6604 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5P_RESERVED1_SHIFT 13 6605 6606 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ5P :: ADJ_EN [12:12] */ 6607 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5P_ADJ_EN_MASK 0x00001000 6608 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5P_ADJ_EN_ALIGN 0 6609 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5P_ADJ_EN_BITS 1 6610 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5P_ADJ_EN_SHIFT 12 6611 6612 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ5P :: reserved2 [11:08] */ 6613 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5P_RESERVED2_MASK 0x00000f00 6614 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5P_RESERVED2_ALIGN 0 6615 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5P_RESERVED2_BITS 4 6616 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5P_RESERVED2_SHIFT 8 6617 6618 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ5P :: VDL_STEP [07:00] */ 6619 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5P_VDL_STEP_MASK 0x000000ff 6620 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5P_VDL_STEP_ALIGN 0 6621 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5P_VDL_STEP_BITS 8 6622 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5P_VDL_STEP_SHIFT 0 6623 6624 6625 /**************************************************************************** 6626 * DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ5N 6627 */ 6628 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ5N :: BUSY [31:31] */ 6629 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5N_BUSY_MASK 0x80000000 6630 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5N_BUSY_ALIGN 0 6631 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5N_BUSY_BITS 1 6632 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5N_BUSY_SHIFT 31 6633 6634 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ5N :: reserved0 [30:17] */ 6635 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5N_RESERVED0_MASK 0x7ffe0000 6636 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5N_RESERVED0_ALIGN 0 6637 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5N_RESERVED0_BITS 14 6638 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5N_RESERVED0_SHIFT 17 6639 6640 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ5N :: FORCE [16:16] */ 6641 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5N_FORCE_MASK 0x00010000 6642 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5N_FORCE_ALIGN 0 6643 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5N_FORCE_BITS 1 6644 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5N_FORCE_SHIFT 16 6645 6646 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ5N :: reserved1 [15:13] */ 6647 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5N_RESERVED1_MASK 0x0000e000 6648 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5N_RESERVED1_ALIGN 0 6649 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5N_RESERVED1_BITS 3 6650 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5N_RESERVED1_SHIFT 13 6651 6652 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ5N :: ADJ_EN [12:12] */ 6653 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5N_ADJ_EN_MASK 0x00001000 6654 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5N_ADJ_EN_ALIGN 0 6655 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5N_ADJ_EN_BITS 1 6656 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5N_ADJ_EN_SHIFT 12 6657 6658 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ5N :: reserved2 [11:08] */ 6659 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5N_RESERVED2_MASK 0x00000f00 6660 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5N_RESERVED2_ALIGN 0 6661 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5N_RESERVED2_BITS 4 6662 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5N_RESERVED2_SHIFT 8 6663 6664 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ5N :: VDL_STEP [07:00] */ 6665 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5N_VDL_STEP_MASK 0x000000ff 6666 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5N_VDL_STEP_ALIGN 0 6667 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5N_VDL_STEP_BITS 8 6668 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5N_VDL_STEP_SHIFT 0 6669 6670 6671 /**************************************************************************** 6672 * DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ6P 6673 */ 6674 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ6P :: BUSY [31:31] */ 6675 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6P_BUSY_MASK 0x80000000 6676 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6P_BUSY_ALIGN 0 6677 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6P_BUSY_BITS 1 6678 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6P_BUSY_SHIFT 31 6679 6680 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ6P :: reserved0 [30:17] */ 6681 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6P_RESERVED0_MASK 0x7ffe0000 6682 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6P_RESERVED0_ALIGN 0 6683 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6P_RESERVED0_BITS 14 6684 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6P_RESERVED0_SHIFT 17 6685 6686 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ6P :: FORCE [16:16] */ 6687 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6P_FORCE_MASK 0x00010000 6688 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6P_FORCE_ALIGN 0 6689 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6P_FORCE_BITS 1 6690 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6P_FORCE_SHIFT 16 6691 6692 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ6P :: reserved1 [15:13] */ 6693 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6P_RESERVED1_MASK 0x0000e000 6694 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6P_RESERVED1_ALIGN 0 6695 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6P_RESERVED1_BITS 3 6696 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6P_RESERVED1_SHIFT 13 6697 6698 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ6P :: ADJ_EN [12:12] */ 6699 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6P_ADJ_EN_MASK 0x00001000 6700 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6P_ADJ_EN_ALIGN 0 6701 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6P_ADJ_EN_BITS 1 6702 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6P_ADJ_EN_SHIFT 12 6703 6704 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ6P :: reserved2 [11:08] */ 6705 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6P_RESERVED2_MASK 0x00000f00 6706 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6P_RESERVED2_ALIGN 0 6707 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6P_RESERVED2_BITS 4 6708 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6P_RESERVED2_SHIFT 8 6709 6710 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ6P :: VDL_STEP [07:00] */ 6711 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6P_VDL_STEP_MASK 0x000000ff 6712 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6P_VDL_STEP_ALIGN 0 6713 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6P_VDL_STEP_BITS 8 6714 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6P_VDL_STEP_SHIFT 0 6715 6716 6717 /**************************************************************************** 6718 * DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ6N 6719 */ 6720 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ6N :: BUSY [31:31] */ 6721 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6N_BUSY_MASK 0x80000000 6722 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6N_BUSY_ALIGN 0 6723 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6N_BUSY_BITS 1 6724 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6N_BUSY_SHIFT 31 6725 6726 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ6N :: reserved0 [30:17] */ 6727 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6N_RESERVED0_MASK 0x7ffe0000 6728 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6N_RESERVED0_ALIGN 0 6729 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6N_RESERVED0_BITS 14 6730 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6N_RESERVED0_SHIFT 17 6731 6732 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ6N :: FORCE [16:16] */ 6733 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6N_FORCE_MASK 0x00010000 6734 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6N_FORCE_ALIGN 0 6735 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6N_FORCE_BITS 1 6736 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6N_FORCE_SHIFT 16 6737 6738 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ6N :: reserved1 [15:13] */ 6739 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6N_RESERVED1_MASK 0x0000e000 6740 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6N_RESERVED1_ALIGN 0 6741 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6N_RESERVED1_BITS 3 6742 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6N_RESERVED1_SHIFT 13 6743 6744 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ6N :: ADJ_EN [12:12] */ 6745 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6N_ADJ_EN_MASK 0x00001000 6746 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6N_ADJ_EN_ALIGN 0 6747 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6N_ADJ_EN_BITS 1 6748 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6N_ADJ_EN_SHIFT 12 6749 6750 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ6N :: reserved2 [11:08] */ 6751 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6N_RESERVED2_MASK 0x00000f00 6752 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6N_RESERVED2_ALIGN 0 6753 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6N_RESERVED2_BITS 4 6754 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6N_RESERVED2_SHIFT 8 6755 6756 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ6N :: VDL_STEP [07:00] */ 6757 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6N_VDL_STEP_MASK 0x000000ff 6758 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6N_VDL_STEP_ALIGN 0 6759 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6N_VDL_STEP_BITS 8 6760 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6N_VDL_STEP_SHIFT 0 6761 6762 6763 /**************************************************************************** 6764 * DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ7P 6765 */ 6766 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ7P :: BUSY [31:31] */ 6767 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7P_BUSY_MASK 0x80000000 6768 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7P_BUSY_ALIGN 0 6769 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7P_BUSY_BITS 1 6770 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7P_BUSY_SHIFT 31 6771 6772 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ7P :: reserved0 [30:17] */ 6773 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7P_RESERVED0_MASK 0x7ffe0000 6774 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7P_RESERVED0_ALIGN 0 6775 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7P_RESERVED0_BITS 14 6776 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7P_RESERVED0_SHIFT 17 6777 6778 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ7P :: FORCE [16:16] */ 6779 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7P_FORCE_MASK 0x00010000 6780 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7P_FORCE_ALIGN 0 6781 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7P_FORCE_BITS 1 6782 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7P_FORCE_SHIFT 16 6783 6784 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ7P :: reserved1 [15:13] */ 6785 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7P_RESERVED1_MASK 0x0000e000 6786 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7P_RESERVED1_ALIGN 0 6787 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7P_RESERVED1_BITS 3 6788 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7P_RESERVED1_SHIFT 13 6789 6790 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ7P :: ADJ_EN [12:12] */ 6791 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7P_ADJ_EN_MASK 0x00001000 6792 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7P_ADJ_EN_ALIGN 0 6793 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7P_ADJ_EN_BITS 1 6794 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7P_ADJ_EN_SHIFT 12 6795 6796 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ7P :: reserved2 [11:08] */ 6797 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7P_RESERVED2_MASK 0x00000f00 6798 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7P_RESERVED2_ALIGN 0 6799 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7P_RESERVED2_BITS 4 6800 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7P_RESERVED2_SHIFT 8 6801 6802 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ7P :: VDL_STEP [07:00] */ 6803 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7P_VDL_STEP_MASK 0x000000ff 6804 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7P_VDL_STEP_ALIGN 0 6805 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7P_VDL_STEP_BITS 8 6806 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7P_VDL_STEP_SHIFT 0 6807 6808 6809 /**************************************************************************** 6810 * DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ7N 6811 */ 6812 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ7N :: BUSY [31:31] */ 6813 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7N_BUSY_MASK 0x80000000 6814 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7N_BUSY_ALIGN 0 6815 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7N_BUSY_BITS 1 6816 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7N_BUSY_SHIFT 31 6817 6818 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ7N :: reserved0 [30:17] */ 6819 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7N_RESERVED0_MASK 0x7ffe0000 6820 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7N_RESERVED0_ALIGN 0 6821 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7N_RESERVED0_BITS 14 6822 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7N_RESERVED0_SHIFT 17 6823 6824 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ7N :: FORCE [16:16] */ 6825 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7N_FORCE_MASK 0x00010000 6826 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7N_FORCE_ALIGN 0 6827 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7N_FORCE_BITS 1 6828 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7N_FORCE_SHIFT 16 6829 6830 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ7N :: reserved1 [15:13] */ 6831 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7N_RESERVED1_MASK 0x0000e000 6832 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7N_RESERVED1_ALIGN 0 6833 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7N_RESERVED1_BITS 3 6834 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7N_RESERVED1_SHIFT 13 6835 6836 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ7N :: ADJ_EN [12:12] */ 6837 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7N_ADJ_EN_MASK 0x00001000 6838 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7N_ADJ_EN_ALIGN 0 6839 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7N_ADJ_EN_BITS 1 6840 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7N_ADJ_EN_SHIFT 12 6841 6842 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ7N :: reserved2 [11:08] */ 6843 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7N_RESERVED2_MASK 0x00000f00 6844 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7N_RESERVED2_ALIGN 0 6845 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7N_RESERVED2_BITS 4 6846 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7N_RESERVED2_SHIFT 8 6847 6848 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ7N :: VDL_STEP [07:00] */ 6849 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7N_VDL_STEP_MASK 0x000000ff 6850 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7N_VDL_STEP_ALIGN 0 6851 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7N_VDL_STEP_BITS 8 6852 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7N_VDL_STEP_SHIFT 0 6853 6854 6855 /**************************************************************************** 6856 * DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DMP 6857 */ 6858 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DMP :: BUSY [31:31] */ 6859 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMP_BUSY_MASK 0x80000000 6860 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMP_BUSY_ALIGN 0 6861 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMP_BUSY_BITS 1 6862 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMP_BUSY_SHIFT 31 6863 6864 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DMP :: reserved0 [30:17] */ 6865 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMP_RESERVED0_MASK 0x7ffe0000 6866 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMP_RESERVED0_ALIGN 0 6867 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMP_RESERVED0_BITS 14 6868 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMP_RESERVED0_SHIFT 17 6869 6870 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DMP :: FORCE [16:16] */ 6871 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMP_FORCE_MASK 0x00010000 6872 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMP_FORCE_ALIGN 0 6873 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMP_FORCE_BITS 1 6874 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMP_FORCE_SHIFT 16 6875 6876 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DMP :: reserved1 [15:13] */ 6877 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMP_RESERVED1_MASK 0x0000e000 6878 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMP_RESERVED1_ALIGN 0 6879 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMP_RESERVED1_BITS 3 6880 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMP_RESERVED1_SHIFT 13 6881 6882 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DMP :: ADJ_EN [12:12] */ 6883 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMP_ADJ_EN_MASK 0x00001000 6884 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMP_ADJ_EN_ALIGN 0 6885 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMP_ADJ_EN_BITS 1 6886 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMP_ADJ_EN_SHIFT 12 6887 6888 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DMP :: reserved2 [11:08] */ 6889 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMP_RESERVED2_MASK 0x00000f00 6890 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMP_RESERVED2_ALIGN 0 6891 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMP_RESERVED2_BITS 4 6892 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMP_RESERVED2_SHIFT 8 6893 6894 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DMP :: VDL_STEP [07:00] */ 6895 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMP_VDL_STEP_MASK 0x000000ff 6896 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMP_VDL_STEP_ALIGN 0 6897 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMP_VDL_STEP_BITS 8 6898 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMP_VDL_STEP_SHIFT 0 6899 6900 6901 /**************************************************************************** 6902 * DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DMN 6903 */ 6904 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DMN :: BUSY [31:31] */ 6905 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMN_BUSY_MASK 0x80000000 6906 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMN_BUSY_ALIGN 0 6907 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMN_BUSY_BITS 1 6908 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMN_BUSY_SHIFT 31 6909 6910 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DMN :: reserved0 [30:17] */ 6911 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMN_RESERVED0_MASK 0x7ffe0000 6912 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMN_RESERVED0_ALIGN 0 6913 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMN_RESERVED0_BITS 14 6914 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMN_RESERVED0_SHIFT 17 6915 6916 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DMN :: FORCE [16:16] */ 6917 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMN_FORCE_MASK 0x00010000 6918 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMN_FORCE_ALIGN 0 6919 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMN_FORCE_BITS 1 6920 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMN_FORCE_SHIFT 16 6921 6922 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DMN :: reserved1 [15:13] */ 6923 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMN_RESERVED1_MASK 0x0000e000 6924 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMN_RESERVED1_ALIGN 0 6925 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMN_RESERVED1_BITS 3 6926 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMN_RESERVED1_SHIFT 13 6927 6928 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DMN :: ADJ_EN [12:12] */ 6929 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMN_ADJ_EN_MASK 0x00001000 6930 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMN_ADJ_EN_ALIGN 0 6931 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMN_ADJ_EN_BITS 1 6932 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMN_ADJ_EN_SHIFT 12 6933 6934 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DMN :: reserved2 [11:08] */ 6935 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMN_RESERVED2_MASK 0x00000f00 6936 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMN_RESERVED2_ALIGN 0 6937 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMN_RESERVED2_BITS 4 6938 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMN_RESERVED2_SHIFT 8 6939 6940 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DMN :: VDL_STEP [07:00] */ 6941 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMN_VDL_STEP_MASK 0x000000ff 6942 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMN_VDL_STEP_ALIGN 0 6943 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMN_VDL_STEP_BITS 8 6944 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMN_VDL_STEP_SHIFT 0 6945 6946 6947 /**************************************************************************** 6948 * DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_EN_CS0 6949 */ 6950 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_EN_CS0 :: BUSY [31:31] */ 6951 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0_BUSY_MASK 0x80000000 6952 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0_BUSY_ALIGN 0 6953 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0_BUSY_BITS 1 6954 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0_BUSY_SHIFT 31 6955 6956 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_EN_CS0 :: reserved0 [30:17] */ 6957 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0_RESERVED0_MASK 0x7ffe0000 6958 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0_RESERVED0_ALIGN 0 6959 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0_RESERVED0_BITS 14 6960 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0_RESERVED0_SHIFT 17 6961 6962 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_EN_CS0 :: FORCE [16:16] */ 6963 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0_FORCE_MASK 0x00010000 6964 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0_FORCE_ALIGN 0 6965 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0_FORCE_BITS 1 6966 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0_FORCE_SHIFT 16 6967 6968 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_EN_CS0 :: reserved1 [15:13] */ 6969 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0_RESERVED1_MASK 0x0000e000 6970 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0_RESERVED1_ALIGN 0 6971 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0_RESERVED1_BITS 3 6972 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0_RESERVED1_SHIFT 13 6973 6974 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_EN_CS0 :: ADJ_EN [12:12] */ 6975 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0_ADJ_EN_MASK 0x00001000 6976 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0_ADJ_EN_ALIGN 0 6977 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0_ADJ_EN_BITS 1 6978 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0_ADJ_EN_SHIFT 12 6979 6980 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_EN_CS0 :: reserved2 [11:08] */ 6981 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0_RESERVED2_MASK 0x00000f00 6982 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0_RESERVED2_ALIGN 0 6983 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0_RESERVED2_BITS 4 6984 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0_RESERVED2_SHIFT 8 6985 6986 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_EN_CS0 :: VDL_STEP [07:00] */ 6987 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0_VDL_STEP_MASK 0x000000ff 6988 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0_VDL_STEP_ALIGN 0 6989 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0_VDL_STEP_BITS 8 6990 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0_VDL_STEP_SHIFT 0 6991 6992 6993 /**************************************************************************** 6994 * DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_EN_CS1 6995 */ 6996 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_EN_CS1 :: BUSY [31:31] */ 6997 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1_BUSY_MASK 0x80000000 6998 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1_BUSY_ALIGN 0 6999 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1_BUSY_BITS 1 7000 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1_BUSY_SHIFT 31 7001 7002 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_EN_CS1 :: reserved0 [30:17] */ 7003 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1_RESERVED0_MASK 0x7ffe0000 7004 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1_RESERVED0_ALIGN 0 7005 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1_RESERVED0_BITS 14 7006 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1_RESERVED0_SHIFT 17 7007 7008 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_EN_CS1 :: FORCE [16:16] */ 7009 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1_FORCE_MASK 0x00010000 7010 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1_FORCE_ALIGN 0 7011 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1_FORCE_BITS 1 7012 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1_FORCE_SHIFT 16 7013 7014 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_EN_CS1 :: reserved1 [15:13] */ 7015 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1_RESERVED1_MASK 0x0000e000 7016 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1_RESERVED1_ALIGN 0 7017 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1_RESERVED1_BITS 3 7018 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1_RESERVED1_SHIFT 13 7019 7020 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_EN_CS1 :: ADJ_EN [12:12] */ 7021 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1_ADJ_EN_MASK 0x00001000 7022 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1_ADJ_EN_ALIGN 0 7023 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1_ADJ_EN_BITS 1 7024 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1_ADJ_EN_SHIFT 12 7025 7026 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_EN_CS1 :: reserved2 [11:08] */ 7027 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1_RESERVED2_MASK 0x00000f00 7028 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1_RESERVED2_ALIGN 0 7029 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1_RESERVED2_BITS 4 7030 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1_RESERVED2_SHIFT 8 7031 7032 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_EN_CS1 :: VDL_STEP [07:00] */ 7033 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1_VDL_STEP_MASK 0x000000ff 7034 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1_VDL_STEP_ALIGN 0 7035 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1_VDL_STEP_BITS 8 7036 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1_VDL_STEP_SHIFT 0 7037 7038 7039 /**************************************************************************** 7040 * DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CLK_CONTROL 7041 */ 7042 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CLK_CONTROL :: BUSY [31:31] */ 7043 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CLK_CONTROL_BUSY_MASK 0x80000000 7044 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CLK_CONTROL_BUSY_ALIGN 0 7045 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CLK_CONTROL_BUSY_BITS 1 7046 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CLK_CONTROL_BUSY_SHIFT 31 7047 7048 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CLK_CONTROL :: reserved0 [30:17] */ 7049 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CLK_CONTROL_RESERVED0_MASK 0x7ffe0000 7050 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CLK_CONTROL_RESERVED0_ALIGN 0 7051 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CLK_CONTROL_RESERVED0_BITS 14 7052 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CLK_CONTROL_RESERVED0_SHIFT 17 7053 7054 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CLK_CONTROL :: FORCE [16:16] */ 7055 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CLK_CONTROL_FORCE_MASK 0x00010000 7056 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CLK_CONTROL_FORCE_ALIGN 0 7057 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CLK_CONTROL_FORCE_BITS 1 7058 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CLK_CONTROL_FORCE_SHIFT 16 7059 7060 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CLK_CONTROL :: reserved1 [15:13] */ 7061 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CLK_CONTROL_RESERVED1_MASK 0x0000e000 7062 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CLK_CONTROL_RESERVED1_ALIGN 0 7063 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CLK_CONTROL_RESERVED1_BITS 3 7064 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CLK_CONTROL_RESERVED1_SHIFT 13 7065 7066 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CLK_CONTROL :: ADJ_EN [12:12] */ 7067 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CLK_CONTROL_ADJ_EN_MASK 0x00001000 7068 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CLK_CONTROL_ADJ_EN_ALIGN 0 7069 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CLK_CONTROL_ADJ_EN_BITS 1 7070 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CLK_CONTROL_ADJ_EN_SHIFT 12 7071 7072 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CLK_CONTROL :: reserved2 [11:09] */ 7073 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CLK_CONTROL_RESERVED2_MASK 0x00000e00 7074 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CLK_CONTROL_RESERVED2_ALIGN 0 7075 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CLK_CONTROL_RESERVED2_BITS 3 7076 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CLK_CONTROL_RESERVED2_SHIFT 9 7077 7078 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_CLK_CONTROL :: VDL_STEP [08:00] */ 7079 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CLK_CONTROL_VDL_STEP_MASK 0x000001ff 7080 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CLK_CONTROL_VDL_STEP_ALIGN 0 7081 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CLK_CONTROL_VDL_STEP_BITS 9 7082 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_CLK_CONTROL_VDL_STEP_SHIFT 0 7083 7084 7085 /**************************************************************************** 7086 * DDR34_F0_PHY_BYTE_LANE_0 :: VDL_LDE_CONTROL 7087 */ 7088 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_LDE_CONTROL :: BUSY [31:31] */ 7089 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_LDE_CONTROL_BUSY_MASK 0x80000000 7090 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_LDE_CONTROL_BUSY_ALIGN 0 7091 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_LDE_CONTROL_BUSY_BITS 1 7092 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_LDE_CONTROL_BUSY_SHIFT 31 7093 7094 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_LDE_CONTROL :: reserved0 [30:17] */ 7095 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_LDE_CONTROL_RESERVED0_MASK 0x7ffe0000 7096 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_LDE_CONTROL_RESERVED0_ALIGN 0 7097 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_LDE_CONTROL_RESERVED0_BITS 14 7098 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_LDE_CONTROL_RESERVED0_SHIFT 17 7099 7100 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_LDE_CONTROL :: FORCE [16:16] */ 7101 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_LDE_CONTROL_FORCE_MASK 0x00010000 7102 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_LDE_CONTROL_FORCE_ALIGN 0 7103 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_LDE_CONTROL_FORCE_BITS 1 7104 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_LDE_CONTROL_FORCE_SHIFT 16 7105 7106 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_LDE_CONTROL :: reserved1 [15:13] */ 7107 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_LDE_CONTROL_RESERVED1_MASK 0x0000e000 7108 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_LDE_CONTROL_RESERVED1_ALIGN 0 7109 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_LDE_CONTROL_RESERVED1_BITS 3 7110 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_LDE_CONTROL_RESERVED1_SHIFT 13 7111 7112 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_LDE_CONTROL :: ADJ_EN [12:12] */ 7113 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_LDE_CONTROL_ADJ_EN_MASK 0x00001000 7114 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_LDE_CONTROL_ADJ_EN_ALIGN 0 7115 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_LDE_CONTROL_ADJ_EN_BITS 1 7116 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_LDE_CONTROL_ADJ_EN_SHIFT 12 7117 7118 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_LDE_CONTROL :: reserved2 [11:09] */ 7119 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_LDE_CONTROL_RESERVED2_MASK 0x00000e00 7120 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_LDE_CONTROL_RESERVED2_ALIGN 0 7121 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_LDE_CONTROL_RESERVED2_BITS 3 7122 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_LDE_CONTROL_RESERVED2_SHIFT 9 7123 7124 /* DDR34_F0_PHY_BYTE_LANE_0 :: VDL_LDE_CONTROL :: VDL_STEP [08:00] */ 7125 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_LDE_CONTROL_VDL_STEP_MASK 0x000001ff 7126 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_LDE_CONTROL_VDL_STEP_ALIGN 0 7127 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_LDE_CONTROL_VDL_STEP_BITS 9 7128 #define DDR34_F0_PHY_BYTE_LANE_0_VDL_LDE_CONTROL_VDL_STEP_SHIFT 0 7129 7130 7131 /**************************************************************************** 7132 * DDR34_F0_PHY_BYTE_LANE_0 :: RD_EN_DLY_CYC 7133 */ 7134 /* DDR34_F0_PHY_BYTE_LANE_0 :: RD_EN_DLY_CYC :: BUSY [31:31] */ 7135 #define DDR34_F0_PHY_BYTE_LANE_0_RD_EN_DLY_CYC_BUSY_MASK 0x80000000 7136 #define DDR34_F0_PHY_BYTE_LANE_0_RD_EN_DLY_CYC_BUSY_ALIGN 0 7137 #define DDR34_F0_PHY_BYTE_LANE_0_RD_EN_DLY_CYC_BUSY_BITS 1 7138 #define DDR34_F0_PHY_BYTE_LANE_0_RD_EN_DLY_CYC_BUSY_SHIFT 31 7139 7140 /* DDR34_F0_PHY_BYTE_LANE_0 :: RD_EN_DLY_CYC :: reserved0 [30:17] */ 7141 #define DDR34_F0_PHY_BYTE_LANE_0_RD_EN_DLY_CYC_RESERVED0_MASK 0x7ffe0000 7142 #define DDR34_F0_PHY_BYTE_LANE_0_RD_EN_DLY_CYC_RESERVED0_ALIGN 0 7143 #define DDR34_F0_PHY_BYTE_LANE_0_RD_EN_DLY_CYC_RESERVED0_BITS 14 7144 #define DDR34_F0_PHY_BYTE_LANE_0_RD_EN_DLY_CYC_RESERVED0_SHIFT 17 7145 7146 /* DDR34_F0_PHY_BYTE_LANE_0 :: RD_EN_DLY_CYC :: FORCE [16:16] */ 7147 #define DDR34_F0_PHY_BYTE_LANE_0_RD_EN_DLY_CYC_FORCE_MASK 0x00010000 7148 #define DDR34_F0_PHY_BYTE_LANE_0_RD_EN_DLY_CYC_FORCE_ALIGN 0 7149 #define DDR34_F0_PHY_BYTE_LANE_0_RD_EN_DLY_CYC_FORCE_BITS 1 7150 #define DDR34_F0_PHY_BYTE_LANE_0_RD_EN_DLY_CYC_FORCE_SHIFT 16 7151 7152 /* DDR34_F0_PHY_BYTE_LANE_0 :: RD_EN_DLY_CYC :: reserved1 [15:09] */ 7153 #define DDR34_F0_PHY_BYTE_LANE_0_RD_EN_DLY_CYC_RESERVED1_MASK 0x0000fe00 7154 #define DDR34_F0_PHY_BYTE_LANE_0_RD_EN_DLY_CYC_RESERVED1_ALIGN 0 7155 #define DDR34_F0_PHY_BYTE_LANE_0_RD_EN_DLY_CYC_RESERVED1_BITS 7 7156 #define DDR34_F0_PHY_BYTE_LANE_0_RD_EN_DLY_CYC_RESERVED1_SHIFT 9 7157 7158 /* DDR34_F0_PHY_BYTE_LANE_0 :: RD_EN_DLY_CYC :: ENABLE_CS1 [08:08] */ 7159 #define DDR34_F0_PHY_BYTE_LANE_0_RD_EN_DLY_CYC_ENABLE_CS1_MASK 0x00000100 7160 #define DDR34_F0_PHY_BYTE_LANE_0_RD_EN_DLY_CYC_ENABLE_CS1_ALIGN 0 7161 #define DDR34_F0_PHY_BYTE_LANE_0_RD_EN_DLY_CYC_ENABLE_CS1_BITS 1 7162 #define DDR34_F0_PHY_BYTE_LANE_0_RD_EN_DLY_CYC_ENABLE_CS1_SHIFT 8 7163 7164 /* DDR34_F0_PHY_BYTE_LANE_0 :: RD_EN_DLY_CYC :: CS1_CYCLES [07:04] */ 7165 #define DDR34_F0_PHY_BYTE_LANE_0_RD_EN_DLY_CYC_CS1_CYCLES_MASK 0x000000f0 7166 #define DDR34_F0_PHY_BYTE_LANE_0_RD_EN_DLY_CYC_CS1_CYCLES_ALIGN 0 7167 #define DDR34_F0_PHY_BYTE_LANE_0_RD_EN_DLY_CYC_CS1_CYCLES_BITS 4 7168 #define DDR34_F0_PHY_BYTE_LANE_0_RD_EN_DLY_CYC_CS1_CYCLES_SHIFT 4 7169 7170 /* DDR34_F0_PHY_BYTE_LANE_0 :: RD_EN_DLY_CYC :: CS0_CYCLES [03:00] */ 7171 #define DDR34_F0_PHY_BYTE_LANE_0_RD_EN_DLY_CYC_CS0_CYCLES_MASK 0x0000000f 7172 #define DDR34_F0_PHY_BYTE_LANE_0_RD_EN_DLY_CYC_CS0_CYCLES_ALIGN 0 7173 #define DDR34_F0_PHY_BYTE_LANE_0_RD_EN_DLY_CYC_CS0_CYCLES_BITS 4 7174 #define DDR34_F0_PHY_BYTE_LANE_0_RD_EN_DLY_CYC_CS0_CYCLES_SHIFT 0 7175 7176 7177 /**************************************************************************** 7178 * DDR34_F0_PHY_BYTE_LANE_0 :: WR_CHAN_DLY_CYC 7179 */ 7180 /* DDR34_F0_PHY_BYTE_LANE_0 :: WR_CHAN_DLY_CYC :: BUSY [31:31] */ 7181 #define DDR34_F0_PHY_BYTE_LANE_0_WR_CHAN_DLY_CYC_BUSY_MASK 0x80000000 7182 #define DDR34_F0_PHY_BYTE_LANE_0_WR_CHAN_DLY_CYC_BUSY_ALIGN 0 7183 #define DDR34_F0_PHY_BYTE_LANE_0_WR_CHAN_DLY_CYC_BUSY_BITS 1 7184 #define DDR34_F0_PHY_BYTE_LANE_0_WR_CHAN_DLY_CYC_BUSY_SHIFT 31 7185 7186 /* DDR34_F0_PHY_BYTE_LANE_0 :: WR_CHAN_DLY_CYC :: reserved0 [30:17] */ 7187 #define DDR34_F0_PHY_BYTE_LANE_0_WR_CHAN_DLY_CYC_RESERVED0_MASK 0x7ffe0000 7188 #define DDR34_F0_PHY_BYTE_LANE_0_WR_CHAN_DLY_CYC_RESERVED0_ALIGN 0 7189 #define DDR34_F0_PHY_BYTE_LANE_0_WR_CHAN_DLY_CYC_RESERVED0_BITS 14 7190 #define DDR34_F0_PHY_BYTE_LANE_0_WR_CHAN_DLY_CYC_RESERVED0_SHIFT 17 7191 7192 /* DDR34_F0_PHY_BYTE_LANE_0 :: WR_CHAN_DLY_CYC :: FORCE [16:16] */ 7193 #define DDR34_F0_PHY_BYTE_LANE_0_WR_CHAN_DLY_CYC_FORCE_MASK 0x00010000 7194 #define DDR34_F0_PHY_BYTE_LANE_0_WR_CHAN_DLY_CYC_FORCE_ALIGN 0 7195 #define DDR34_F0_PHY_BYTE_LANE_0_WR_CHAN_DLY_CYC_FORCE_BITS 1 7196 #define DDR34_F0_PHY_BYTE_LANE_0_WR_CHAN_DLY_CYC_FORCE_SHIFT 16 7197 7198 /* DDR34_F0_PHY_BYTE_LANE_0 :: WR_CHAN_DLY_CYC :: reserved1 [15:08] */ 7199 #define DDR34_F0_PHY_BYTE_LANE_0_WR_CHAN_DLY_CYC_RESERVED1_MASK 0x0000ff00 7200 #define DDR34_F0_PHY_BYTE_LANE_0_WR_CHAN_DLY_CYC_RESERVED1_ALIGN 0 7201 #define DDR34_F0_PHY_BYTE_LANE_0_WR_CHAN_DLY_CYC_RESERVED1_BITS 8 7202 #define DDR34_F0_PHY_BYTE_LANE_0_WR_CHAN_DLY_CYC_RESERVED1_SHIFT 8 7203 7204 /* DDR34_F0_PHY_BYTE_LANE_0 :: WR_CHAN_DLY_CYC :: DQ_CYCLES [07:04] */ 7205 #define DDR34_F0_PHY_BYTE_LANE_0_WR_CHAN_DLY_CYC_DQ_CYCLES_MASK 0x000000f0 7206 #define DDR34_F0_PHY_BYTE_LANE_0_WR_CHAN_DLY_CYC_DQ_CYCLES_ALIGN 0 7207 #define DDR34_F0_PHY_BYTE_LANE_0_WR_CHAN_DLY_CYC_DQ_CYCLES_BITS 4 7208 #define DDR34_F0_PHY_BYTE_LANE_0_WR_CHAN_DLY_CYC_DQ_CYCLES_SHIFT 4 7209 7210 /* DDR34_F0_PHY_BYTE_LANE_0 :: WR_CHAN_DLY_CYC :: reserved2 [03:03] */ 7211 #define DDR34_F0_PHY_BYTE_LANE_0_WR_CHAN_DLY_CYC_RESERVED2_MASK 0x00000008 7212 #define DDR34_F0_PHY_BYTE_LANE_0_WR_CHAN_DLY_CYC_RESERVED2_ALIGN 0 7213 #define DDR34_F0_PHY_BYTE_LANE_0_WR_CHAN_DLY_CYC_RESERVED2_BITS 1 7214 #define DDR34_F0_PHY_BYTE_LANE_0_WR_CHAN_DLY_CYC_RESERVED2_SHIFT 3 7215 7216 /* DDR34_F0_PHY_BYTE_LANE_0 :: WR_CHAN_DLY_CYC :: CYCLES [02:00] */ 7217 #define DDR34_F0_PHY_BYTE_LANE_0_WR_CHAN_DLY_CYC_CYCLES_MASK 0x00000007 7218 #define DDR34_F0_PHY_BYTE_LANE_0_WR_CHAN_DLY_CYC_CYCLES_ALIGN 0 7219 #define DDR34_F0_PHY_BYTE_LANE_0_WR_CHAN_DLY_CYC_CYCLES_BITS 3 7220 #define DDR34_F0_PHY_BYTE_LANE_0_WR_CHAN_DLY_CYC_CYCLES_SHIFT 0 7221 7222 7223 /**************************************************************************** 7224 * DDR34_F0_PHY_BYTE_LANE_0 :: READ_CONTROL 7225 */ 7226 /* DDR34_F0_PHY_BYTE_LANE_0 :: READ_CONTROL :: reserved0 [31:05] */ 7227 #define DDR34_F0_PHY_BYTE_LANE_0_READ_CONTROL_RESERVED0_MASK 0xffffffe0 7228 #define DDR34_F0_PHY_BYTE_LANE_0_READ_CONTROL_RESERVED0_ALIGN 0 7229 #define DDR34_F0_PHY_BYTE_LANE_0_READ_CONTROL_RESERVED0_BITS 27 7230 #define DDR34_F0_PHY_BYTE_LANE_0_READ_CONTROL_RESERVED0_SHIFT 5 7231 7232 /* DDR34_F0_PHY_BYTE_LANE_0 :: READ_CONTROL :: MODE [04:04] */ 7233 #define DDR34_F0_PHY_BYTE_LANE_0_READ_CONTROL_MODE_MASK 0x00000010 7234 #define DDR34_F0_PHY_BYTE_LANE_0_READ_CONTROL_MODE_ALIGN 0 7235 #define DDR34_F0_PHY_BYTE_LANE_0_READ_CONTROL_MODE_BITS 1 7236 #define DDR34_F0_PHY_BYTE_LANE_0_READ_CONTROL_MODE_SHIFT 4 7237 7238 /* DDR34_F0_PHY_BYTE_LANE_0 :: READ_CONTROL :: RD_EN_MODE [03:03] */ 7239 #define DDR34_F0_PHY_BYTE_LANE_0_READ_CONTROL_RD_EN_MODE_MASK 0x00000008 7240 #define DDR34_F0_PHY_BYTE_LANE_0_READ_CONTROL_RD_EN_MODE_ALIGN 0 7241 #define DDR34_F0_PHY_BYTE_LANE_0_READ_CONTROL_RD_EN_MODE_BITS 1 7242 #define DDR34_F0_PHY_BYTE_LANE_0_READ_CONTROL_RD_EN_MODE_SHIFT 3 7243 7244 /* DDR34_F0_PHY_BYTE_LANE_0 :: READ_CONTROL :: RD_DATA_DLY [02:00] */ 7245 #define DDR34_F0_PHY_BYTE_LANE_0_READ_CONTROL_RD_DATA_DLY_MASK 0x00000007 7246 #define DDR34_F0_PHY_BYTE_LANE_0_READ_CONTROL_RD_DATA_DLY_ALIGN 0 7247 #define DDR34_F0_PHY_BYTE_LANE_0_READ_CONTROL_RD_DATA_DLY_BITS 3 7248 #define DDR34_F0_PHY_BYTE_LANE_0_READ_CONTROL_RD_DATA_DLY_SHIFT 0 7249 7250 7251 /**************************************************************************** 7252 * DDR34_F0_PHY_BYTE_LANE_0 :: READ_FIFO_ADDR 7253 */ 7254 /* DDR34_F0_PHY_BYTE_LANE_0 :: READ_FIFO_ADDR :: reserved0 [31:03] */ 7255 #define DDR34_F0_PHY_BYTE_LANE_0_READ_FIFO_ADDR_RESERVED0_MASK 0xfffffff8 7256 #define DDR34_F0_PHY_BYTE_LANE_0_READ_FIFO_ADDR_RESERVED0_ALIGN 0 7257 #define DDR34_F0_PHY_BYTE_LANE_0_READ_FIFO_ADDR_RESERVED0_BITS 29 7258 #define DDR34_F0_PHY_BYTE_LANE_0_READ_FIFO_ADDR_RESERVED0_SHIFT 3 7259 7260 /* DDR34_F0_PHY_BYTE_LANE_0 :: READ_FIFO_ADDR :: ADDR [02:00] */ 7261 #define DDR34_F0_PHY_BYTE_LANE_0_READ_FIFO_ADDR_ADDR_MASK 0x00000007 7262 #define DDR34_F0_PHY_BYTE_LANE_0_READ_FIFO_ADDR_ADDR_ALIGN 0 7263 #define DDR34_F0_PHY_BYTE_LANE_0_READ_FIFO_ADDR_ADDR_BITS 3 7264 #define DDR34_F0_PHY_BYTE_LANE_0_READ_FIFO_ADDR_ADDR_SHIFT 0 7265 7266 7267 /**************************************************************************** 7268 * DDR34_F0_PHY_BYTE_LANE_0 :: READ_FIFO_DATA 7269 */ 7270 /* DDR34_F0_PHY_BYTE_LANE_0 :: READ_FIFO_DATA :: DATA [31:00] */ 7271 #define DDR34_F0_PHY_BYTE_LANE_0_READ_FIFO_DATA_DATA_MASK 0xffffffff 7272 #define DDR34_F0_PHY_BYTE_LANE_0_READ_FIFO_DATA_DATA_ALIGN 0 7273 #define DDR34_F0_PHY_BYTE_LANE_0_READ_FIFO_DATA_DATA_BITS 32 7274 #define DDR34_F0_PHY_BYTE_LANE_0_READ_FIFO_DATA_DATA_SHIFT 0 7275 7276 7277 /**************************************************************************** 7278 * DDR34_F0_PHY_BYTE_LANE_0 :: READ_FIFO_DM_DBI 7279 */ 7280 /* DDR34_F0_PHY_BYTE_LANE_0 :: READ_FIFO_DM_DBI :: reserved0 [31:04] */ 7281 #define DDR34_F0_PHY_BYTE_LANE_0_READ_FIFO_DM_DBI_RESERVED0_MASK 0xfffffff0 7282 #define DDR34_F0_PHY_BYTE_LANE_0_READ_FIFO_DM_DBI_RESERVED0_ALIGN 0 7283 #define DDR34_F0_PHY_BYTE_LANE_0_READ_FIFO_DM_DBI_RESERVED0_BITS 28 7284 #define DDR34_F0_PHY_BYTE_LANE_0_READ_FIFO_DM_DBI_RESERVED0_SHIFT 4 7285 7286 /* DDR34_F0_PHY_BYTE_LANE_0 :: READ_FIFO_DM_DBI :: DM_DBI [03:00] */ 7287 #define DDR34_F0_PHY_BYTE_LANE_0_READ_FIFO_DM_DBI_DM_DBI_MASK 0x0000000f 7288 #define DDR34_F0_PHY_BYTE_LANE_0_READ_FIFO_DM_DBI_DM_DBI_ALIGN 0 7289 #define DDR34_F0_PHY_BYTE_LANE_0_READ_FIFO_DM_DBI_DM_DBI_BITS 4 7290 #define DDR34_F0_PHY_BYTE_LANE_0_READ_FIFO_DM_DBI_DM_DBI_SHIFT 0 7291 7292 7293 /**************************************************************************** 7294 * DDR34_F0_PHY_BYTE_LANE_0 :: READ_FIFO_STATUS 7295 */ 7296 /* DDR34_F0_PHY_BYTE_LANE_0 :: READ_FIFO_STATUS :: reserved0 [31:02] */ 7297 #define DDR34_F0_PHY_BYTE_LANE_0_READ_FIFO_STATUS_RESERVED0_MASK 0xfffffffc 7298 #define DDR34_F0_PHY_BYTE_LANE_0_READ_FIFO_STATUS_RESERVED0_ALIGN 0 7299 #define DDR34_F0_PHY_BYTE_LANE_0_READ_FIFO_STATUS_RESERVED0_BITS 30 7300 #define DDR34_F0_PHY_BYTE_LANE_0_READ_FIFO_STATUS_RESERVED0_SHIFT 2 7301 7302 /* DDR34_F0_PHY_BYTE_LANE_0 :: READ_FIFO_STATUS :: OVERFLOW [01:01] */ 7303 #define DDR34_F0_PHY_BYTE_LANE_0_READ_FIFO_STATUS_OVERFLOW_MASK 0x00000002 7304 #define DDR34_F0_PHY_BYTE_LANE_0_READ_FIFO_STATUS_OVERFLOW_ALIGN 0 7305 #define DDR34_F0_PHY_BYTE_LANE_0_READ_FIFO_STATUS_OVERFLOW_BITS 1 7306 #define DDR34_F0_PHY_BYTE_LANE_0_READ_FIFO_STATUS_OVERFLOW_SHIFT 1 7307 7308 /* DDR34_F0_PHY_BYTE_LANE_0 :: READ_FIFO_STATUS :: UNDERFLOW [00:00] */ 7309 #define DDR34_F0_PHY_BYTE_LANE_0_READ_FIFO_STATUS_UNDERFLOW_MASK 0x00000001 7310 #define DDR34_F0_PHY_BYTE_LANE_0_READ_FIFO_STATUS_UNDERFLOW_ALIGN 0 7311 #define DDR34_F0_PHY_BYTE_LANE_0_READ_FIFO_STATUS_UNDERFLOW_BITS 1 7312 #define DDR34_F0_PHY_BYTE_LANE_0_READ_FIFO_STATUS_UNDERFLOW_SHIFT 0 7313 7314 7315 /**************************************************************************** 7316 * DDR34_F0_PHY_BYTE_LANE_0 :: READ_FIFO_CLEAR 7317 */ 7318 /* DDR34_F0_PHY_BYTE_LANE_0 :: READ_FIFO_CLEAR :: reserved0 [31:01] */ 7319 #define DDR34_F0_PHY_BYTE_LANE_0_READ_FIFO_CLEAR_RESERVED0_MASK 0xfffffffe 7320 #define DDR34_F0_PHY_BYTE_LANE_0_READ_FIFO_CLEAR_RESERVED0_ALIGN 0 7321 #define DDR34_F0_PHY_BYTE_LANE_0_READ_FIFO_CLEAR_RESERVED0_BITS 31 7322 #define DDR34_F0_PHY_BYTE_LANE_0_READ_FIFO_CLEAR_RESERVED0_SHIFT 1 7323 7324 /* DDR34_F0_PHY_BYTE_LANE_0 :: READ_FIFO_CLEAR :: CLEAR [00:00] */ 7325 #define DDR34_F0_PHY_BYTE_LANE_0_READ_FIFO_CLEAR_CLEAR_MASK 0x00000001 7326 #define DDR34_F0_PHY_BYTE_LANE_0_READ_FIFO_CLEAR_CLEAR_ALIGN 0 7327 #define DDR34_F0_PHY_BYTE_LANE_0_READ_FIFO_CLEAR_CLEAR_BITS 1 7328 #define DDR34_F0_PHY_BYTE_LANE_0_READ_FIFO_CLEAR_CLEAR_SHIFT 0 7329 7330 7331 /**************************************************************************** 7332 * DDR34_F0_PHY_BYTE_LANE_0 :: IDLE_PAD_CONTROL 7333 */ 7334 /* DDR34_F0_PHY_BYTE_LANE_0 :: IDLE_PAD_CONTROL :: IDLE [31:31] */ 7335 #define DDR34_F0_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_IDLE_MASK 0x80000000 7336 #define DDR34_F0_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_IDLE_ALIGN 0 7337 #define DDR34_F0_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_IDLE_BITS 1 7338 #define DDR34_F0_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_IDLE_SHIFT 31 7339 7340 /* DDR34_F0_PHY_BYTE_LANE_0 :: IDLE_PAD_CONTROL :: reserved0 [30:20] */ 7341 #define DDR34_F0_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_RESERVED0_MASK 0x7ff00000 7342 #define DDR34_F0_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_RESERVED0_ALIGN 0 7343 #define DDR34_F0_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_RESERVED0_BITS 11 7344 #define DDR34_F0_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_RESERVED0_SHIFT 20 7345 7346 /* DDR34_F0_PHY_BYTE_LANE_0 :: IDLE_PAD_CONTROL :: AUTO_DQ_RXENB_MODE [19:18] */ 7347 #define DDR34_F0_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_AUTO_DQ_RXENB_MODE_MASK 0x000c0000 7348 #define DDR34_F0_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_AUTO_DQ_RXENB_MODE_ALIGN 0 7349 #define DDR34_F0_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_AUTO_DQ_RXENB_MODE_BITS 2 7350 #define DDR34_F0_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_AUTO_DQ_RXENB_MODE_SHIFT 18 7351 7352 /* DDR34_F0_PHY_BYTE_LANE_0 :: IDLE_PAD_CONTROL :: AUTO_DQ_IDDQ_MODE [17:16] */ 7353 #define DDR34_F0_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_AUTO_DQ_IDDQ_MODE_MASK 0x00030000 7354 #define DDR34_F0_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_AUTO_DQ_IDDQ_MODE_ALIGN 0 7355 #define DDR34_F0_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_AUTO_DQ_IDDQ_MODE_BITS 2 7356 #define DDR34_F0_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_AUTO_DQ_IDDQ_MODE_SHIFT 16 7357 7358 /* DDR34_F0_PHY_BYTE_LANE_0 :: IDLE_PAD_CONTROL :: IO_IDLE_ENABLE [15:04] */ 7359 #define DDR34_F0_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_IO_IDLE_ENABLE_MASK 0x0000fff0 7360 #define DDR34_F0_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_IO_IDLE_ENABLE_ALIGN 0 7361 #define DDR34_F0_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_IO_IDLE_ENABLE_BITS 12 7362 #define DDR34_F0_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_IO_IDLE_ENABLE_SHIFT 4 7363 7364 /* DDR34_F0_PHY_BYTE_LANE_0 :: IDLE_PAD_CONTROL :: RXENB [03:03] */ 7365 #define DDR34_F0_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_RXENB_MASK 0x00000008 7366 #define DDR34_F0_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_RXENB_ALIGN 0 7367 #define DDR34_F0_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_RXENB_BITS 1 7368 #define DDR34_F0_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_RXENB_SHIFT 3 7369 7370 /* DDR34_F0_PHY_BYTE_LANE_0 :: IDLE_PAD_CONTROL :: IDDQ [02:02] */ 7371 #define DDR34_F0_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_IDDQ_MASK 0x00000004 7372 #define DDR34_F0_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_IDDQ_ALIGN 0 7373 #define DDR34_F0_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_IDDQ_BITS 1 7374 #define DDR34_F0_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_IDDQ_SHIFT 2 7375 7376 /* DDR34_F0_PHY_BYTE_LANE_0 :: IDLE_PAD_CONTROL :: DOUT_N [01:01] */ 7377 #define DDR34_F0_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_DOUT_N_MASK 0x00000002 7378 #define DDR34_F0_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_DOUT_N_ALIGN 0 7379 #define DDR34_F0_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_DOUT_N_BITS 1 7380 #define DDR34_F0_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_DOUT_N_SHIFT 1 7381 7382 /* DDR34_F0_PHY_BYTE_LANE_0 :: IDLE_PAD_CONTROL :: DOUT_P [00:00] */ 7383 #define DDR34_F0_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_DOUT_P_MASK 0x00000001 7384 #define DDR34_F0_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_DOUT_P_ALIGN 0 7385 #define DDR34_F0_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_DOUT_P_BITS 1 7386 #define DDR34_F0_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_DOUT_P_SHIFT 0 7387 7388 7389 /**************************************************************************** 7390 * DDR34_F0_PHY_BYTE_LANE_0 :: DRIVE_PAD_CTL 7391 */ 7392 /* DDR34_F0_PHY_BYTE_LANE_0 :: DRIVE_PAD_CTL :: reserved0 [31:20] */ 7393 #define DDR34_F0_PHY_BYTE_LANE_0_DRIVE_PAD_CTL_RESERVED0_MASK 0xfff00000 7394 #define DDR34_F0_PHY_BYTE_LANE_0_DRIVE_PAD_CTL_RESERVED0_ALIGN 0 7395 #define DDR34_F0_PHY_BYTE_LANE_0_DRIVE_PAD_CTL_RESERVED0_BITS 12 7396 #define DDR34_F0_PHY_BYTE_LANE_0_DRIVE_PAD_CTL_RESERVED0_SHIFT 20 7397 7398 /* DDR34_F0_PHY_BYTE_LANE_0 :: DRIVE_PAD_CTL :: BL_PD_TERM_STRENGTH [19:15] */ 7399 #define DDR34_F0_PHY_BYTE_LANE_0_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_MASK 0x000f8000 7400 #define DDR34_F0_PHY_BYTE_LANE_0_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_ALIGN 0 7401 #define DDR34_F0_PHY_BYTE_LANE_0_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_BITS 5 7402 #define DDR34_F0_PHY_BYTE_LANE_0_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_SHIFT 15 7403 7404 /* DDR34_F0_PHY_BYTE_LANE_0 :: DRIVE_PAD_CTL :: BL_ND_TERM_STRENGTH [14:10] */ 7405 #define DDR34_F0_PHY_BYTE_LANE_0_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_MASK 0x00007c00 7406 #define DDR34_F0_PHY_BYTE_LANE_0_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_ALIGN 0 7407 #define DDR34_F0_PHY_BYTE_LANE_0_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_BITS 5 7408 #define DDR34_F0_PHY_BYTE_LANE_0_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_SHIFT 10 7409 7410 /* DDR34_F0_PHY_BYTE_LANE_0 :: DRIVE_PAD_CTL :: BL_PD_STRENGTH [09:05] */ 7411 #define DDR34_F0_PHY_BYTE_LANE_0_DRIVE_PAD_CTL_BL_PD_STRENGTH_MASK 0x000003e0 7412 #define DDR34_F0_PHY_BYTE_LANE_0_DRIVE_PAD_CTL_BL_PD_STRENGTH_ALIGN 0 7413 #define DDR34_F0_PHY_BYTE_LANE_0_DRIVE_PAD_CTL_BL_PD_STRENGTH_BITS 5 7414 #define DDR34_F0_PHY_BYTE_LANE_0_DRIVE_PAD_CTL_BL_PD_STRENGTH_SHIFT 5 7415 7416 /* DDR34_F0_PHY_BYTE_LANE_0 :: DRIVE_PAD_CTL :: BL_ND_STRENGTH [04:00] */ 7417 #define DDR34_F0_PHY_BYTE_LANE_0_DRIVE_PAD_CTL_BL_ND_STRENGTH_MASK 0x0000001f 7418 #define DDR34_F0_PHY_BYTE_LANE_0_DRIVE_PAD_CTL_BL_ND_STRENGTH_ALIGN 0 7419 #define DDR34_F0_PHY_BYTE_LANE_0_DRIVE_PAD_CTL_BL_ND_STRENGTH_BITS 5 7420 #define DDR34_F0_PHY_BYTE_LANE_0_DRIVE_PAD_CTL_BL_ND_STRENGTH_SHIFT 0 7421 7422 7423 /**************************************************************************** 7424 * DDR34_F0_PHY_BYTE_LANE_0 :: DQSP_DRIVE_PAD_CTL 7425 */ 7426 /* DDR34_F0_PHY_BYTE_LANE_0 :: DQSP_DRIVE_PAD_CTL :: reserved0 [31:20] */ 7427 #define DDR34_F0_PHY_BYTE_LANE_0_DQSP_DRIVE_PAD_CTL_RESERVED0_MASK 0xfff00000 7428 #define DDR34_F0_PHY_BYTE_LANE_0_DQSP_DRIVE_PAD_CTL_RESERVED0_ALIGN 0 7429 #define DDR34_F0_PHY_BYTE_LANE_0_DQSP_DRIVE_PAD_CTL_RESERVED0_BITS 12 7430 #define DDR34_F0_PHY_BYTE_LANE_0_DQSP_DRIVE_PAD_CTL_RESERVED0_SHIFT 20 7431 7432 /* DDR34_F0_PHY_BYTE_LANE_0 :: DQSP_DRIVE_PAD_CTL :: BL_PD_TERM_STRENGTH [19:15] */ 7433 #define DDR34_F0_PHY_BYTE_LANE_0_DQSP_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_MASK 0x000f8000 7434 #define DDR34_F0_PHY_BYTE_LANE_0_DQSP_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_ALIGN 0 7435 #define DDR34_F0_PHY_BYTE_LANE_0_DQSP_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_BITS 5 7436 #define DDR34_F0_PHY_BYTE_LANE_0_DQSP_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_SHIFT 15 7437 7438 /* DDR34_F0_PHY_BYTE_LANE_0 :: DQSP_DRIVE_PAD_CTL :: BL_ND_TERM_STRENGTH [14:10] */ 7439 #define DDR34_F0_PHY_BYTE_LANE_0_DQSP_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_MASK 0x00007c00 7440 #define DDR34_F0_PHY_BYTE_LANE_0_DQSP_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_ALIGN 0 7441 #define DDR34_F0_PHY_BYTE_LANE_0_DQSP_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_BITS 5 7442 #define DDR34_F0_PHY_BYTE_LANE_0_DQSP_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_SHIFT 10 7443 7444 /* DDR34_F0_PHY_BYTE_LANE_0 :: DQSP_DRIVE_PAD_CTL :: BL_PD_STRENGTH [09:05] */ 7445 #define DDR34_F0_PHY_BYTE_LANE_0_DQSP_DRIVE_PAD_CTL_BL_PD_STRENGTH_MASK 0x000003e0 7446 #define DDR34_F0_PHY_BYTE_LANE_0_DQSP_DRIVE_PAD_CTL_BL_PD_STRENGTH_ALIGN 0 7447 #define DDR34_F0_PHY_BYTE_LANE_0_DQSP_DRIVE_PAD_CTL_BL_PD_STRENGTH_BITS 5 7448 #define DDR34_F0_PHY_BYTE_LANE_0_DQSP_DRIVE_PAD_CTL_BL_PD_STRENGTH_SHIFT 5 7449 7450 /* DDR34_F0_PHY_BYTE_LANE_0 :: DQSP_DRIVE_PAD_CTL :: BL_ND_STRENGTH [04:00] */ 7451 #define DDR34_F0_PHY_BYTE_LANE_0_DQSP_DRIVE_PAD_CTL_BL_ND_STRENGTH_MASK 0x0000001f 7452 #define DDR34_F0_PHY_BYTE_LANE_0_DQSP_DRIVE_PAD_CTL_BL_ND_STRENGTH_ALIGN 0 7453 #define DDR34_F0_PHY_BYTE_LANE_0_DQSP_DRIVE_PAD_CTL_BL_ND_STRENGTH_BITS 5 7454 #define DDR34_F0_PHY_BYTE_LANE_0_DQSP_DRIVE_PAD_CTL_BL_ND_STRENGTH_SHIFT 0 7455 7456 7457 /**************************************************************************** 7458 * DDR34_F0_PHY_BYTE_LANE_0 :: DQSN_DRIVE_PAD_CTL 7459 */ 7460 /* DDR34_F0_PHY_BYTE_LANE_0 :: DQSN_DRIVE_PAD_CTL :: reserved0 [31:20] */ 7461 #define DDR34_F0_PHY_BYTE_LANE_0_DQSN_DRIVE_PAD_CTL_RESERVED0_MASK 0xfff00000 7462 #define DDR34_F0_PHY_BYTE_LANE_0_DQSN_DRIVE_PAD_CTL_RESERVED0_ALIGN 0 7463 #define DDR34_F0_PHY_BYTE_LANE_0_DQSN_DRIVE_PAD_CTL_RESERVED0_BITS 12 7464 #define DDR34_F0_PHY_BYTE_LANE_0_DQSN_DRIVE_PAD_CTL_RESERVED0_SHIFT 20 7465 7466 /* DDR34_F0_PHY_BYTE_LANE_0 :: DQSN_DRIVE_PAD_CTL :: BL_PD_TERM_STRENGTH [19:15] */ 7467 #define DDR34_F0_PHY_BYTE_LANE_0_DQSN_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_MASK 0x000f8000 7468 #define DDR34_F0_PHY_BYTE_LANE_0_DQSN_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_ALIGN 0 7469 #define DDR34_F0_PHY_BYTE_LANE_0_DQSN_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_BITS 5 7470 #define DDR34_F0_PHY_BYTE_LANE_0_DQSN_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_SHIFT 15 7471 7472 /* DDR34_F0_PHY_BYTE_LANE_0 :: DQSN_DRIVE_PAD_CTL :: BL_ND_TERM_STRENGTH [14:10] */ 7473 #define DDR34_F0_PHY_BYTE_LANE_0_DQSN_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_MASK 0x00007c00 7474 #define DDR34_F0_PHY_BYTE_LANE_0_DQSN_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_ALIGN 0 7475 #define DDR34_F0_PHY_BYTE_LANE_0_DQSN_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_BITS 5 7476 #define DDR34_F0_PHY_BYTE_LANE_0_DQSN_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_SHIFT 10 7477 7478 /* DDR34_F0_PHY_BYTE_LANE_0 :: DQSN_DRIVE_PAD_CTL :: BL_PD_STRENGTH [09:05] */ 7479 #define DDR34_F0_PHY_BYTE_LANE_0_DQSN_DRIVE_PAD_CTL_BL_PD_STRENGTH_MASK 0x000003e0 7480 #define DDR34_F0_PHY_BYTE_LANE_0_DQSN_DRIVE_PAD_CTL_BL_PD_STRENGTH_ALIGN 0 7481 #define DDR34_F0_PHY_BYTE_LANE_0_DQSN_DRIVE_PAD_CTL_BL_PD_STRENGTH_BITS 5 7482 #define DDR34_F0_PHY_BYTE_LANE_0_DQSN_DRIVE_PAD_CTL_BL_PD_STRENGTH_SHIFT 5 7483 7484 /* DDR34_F0_PHY_BYTE_LANE_0 :: DQSN_DRIVE_PAD_CTL :: BL_ND_STRENGTH [04:00] */ 7485 #define DDR34_F0_PHY_BYTE_LANE_0_DQSN_DRIVE_PAD_CTL_BL_ND_STRENGTH_MASK 0x0000001f 7486 #define DDR34_F0_PHY_BYTE_LANE_0_DQSN_DRIVE_PAD_CTL_BL_ND_STRENGTH_ALIGN 0 7487 #define DDR34_F0_PHY_BYTE_LANE_0_DQSN_DRIVE_PAD_CTL_BL_ND_STRENGTH_BITS 5 7488 #define DDR34_F0_PHY_BYTE_LANE_0_DQSN_DRIVE_PAD_CTL_BL_ND_STRENGTH_SHIFT 0 7489 7490 7491 /**************************************************************************** 7492 * DDR34_F0_PHY_BYTE_LANE_0 :: ALERT_DRIVE_PAD_CTL 7493 */ 7494 /* DDR34_F0_PHY_BYTE_LANE_0 :: ALERT_DRIVE_PAD_CTL :: reserved0 [31:20] */ 7495 #define DDR34_F0_PHY_BYTE_LANE_0_ALERT_DRIVE_PAD_CTL_RESERVED0_MASK 0xfff00000 7496 #define DDR34_F0_PHY_BYTE_LANE_0_ALERT_DRIVE_PAD_CTL_RESERVED0_ALIGN 0 7497 #define DDR34_F0_PHY_BYTE_LANE_0_ALERT_DRIVE_PAD_CTL_RESERVED0_BITS 12 7498 #define DDR34_F0_PHY_BYTE_LANE_0_ALERT_DRIVE_PAD_CTL_RESERVED0_SHIFT 20 7499 7500 /* DDR34_F0_PHY_BYTE_LANE_0 :: ALERT_DRIVE_PAD_CTL :: BL_PD_TERM_STRENGTH [19:15] */ 7501 #define DDR34_F0_PHY_BYTE_LANE_0_ALERT_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_MASK 0x000f8000 7502 #define DDR34_F0_PHY_BYTE_LANE_0_ALERT_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_ALIGN 0 7503 #define DDR34_F0_PHY_BYTE_LANE_0_ALERT_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_BITS 5 7504 #define DDR34_F0_PHY_BYTE_LANE_0_ALERT_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_SHIFT 15 7505 7506 /* DDR34_F0_PHY_BYTE_LANE_0 :: ALERT_DRIVE_PAD_CTL :: BL_ND_TERM_STRENGTH [14:10] */ 7507 #define DDR34_F0_PHY_BYTE_LANE_0_ALERT_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_MASK 0x00007c00 7508 #define DDR34_F0_PHY_BYTE_LANE_0_ALERT_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_ALIGN 0 7509 #define DDR34_F0_PHY_BYTE_LANE_0_ALERT_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_BITS 5 7510 #define DDR34_F0_PHY_BYTE_LANE_0_ALERT_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_SHIFT 10 7511 7512 /* DDR34_F0_PHY_BYTE_LANE_0 :: ALERT_DRIVE_PAD_CTL :: BL_PD_STRENGTH [09:05] */ 7513 #define DDR34_F0_PHY_BYTE_LANE_0_ALERT_DRIVE_PAD_CTL_BL_PD_STRENGTH_MASK 0x000003e0 7514 #define DDR34_F0_PHY_BYTE_LANE_0_ALERT_DRIVE_PAD_CTL_BL_PD_STRENGTH_ALIGN 0 7515 #define DDR34_F0_PHY_BYTE_LANE_0_ALERT_DRIVE_PAD_CTL_BL_PD_STRENGTH_BITS 5 7516 #define DDR34_F0_PHY_BYTE_LANE_0_ALERT_DRIVE_PAD_CTL_BL_PD_STRENGTH_SHIFT 5 7517 7518 /* DDR34_F0_PHY_BYTE_LANE_0 :: ALERT_DRIVE_PAD_CTL :: BL_ND_STRENGTH [04:00] */ 7519 #define DDR34_F0_PHY_BYTE_LANE_0_ALERT_DRIVE_PAD_CTL_BL_ND_STRENGTH_MASK 0x0000001f 7520 #define DDR34_F0_PHY_BYTE_LANE_0_ALERT_DRIVE_PAD_CTL_BL_ND_STRENGTH_ALIGN 0 7521 #define DDR34_F0_PHY_BYTE_LANE_0_ALERT_DRIVE_PAD_CTL_BL_ND_STRENGTH_BITS 5 7522 #define DDR34_F0_PHY_BYTE_LANE_0_ALERT_DRIVE_PAD_CTL_BL_ND_STRENGTH_SHIFT 0 7523 7524 7525 /**************************************************************************** 7526 * DDR34_F0_PHY_BYTE_LANE_0 :: RD_EN_DRIVE_PAD_CTL 7527 */ 7528 /* DDR34_F0_PHY_BYTE_LANE_0 :: RD_EN_DRIVE_PAD_CTL :: reserved0 [31:10] */ 7529 #define DDR34_F0_PHY_BYTE_LANE_0_RD_EN_DRIVE_PAD_CTL_RESERVED0_MASK 0xfffffc00 7530 #define DDR34_F0_PHY_BYTE_LANE_0_RD_EN_DRIVE_PAD_CTL_RESERVED0_ALIGN 0 7531 #define DDR34_F0_PHY_BYTE_LANE_0_RD_EN_DRIVE_PAD_CTL_RESERVED0_BITS 22 7532 #define DDR34_F0_PHY_BYTE_LANE_0_RD_EN_DRIVE_PAD_CTL_RESERVED0_SHIFT 10 7533 7534 /* DDR34_F0_PHY_BYTE_LANE_0 :: RD_EN_DRIVE_PAD_CTL :: BL_RD_EN_PD_STRENGTH [09:05] */ 7535 #define DDR34_F0_PHY_BYTE_LANE_0_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_PD_STRENGTH_MASK 0x000003e0 7536 #define DDR34_F0_PHY_BYTE_LANE_0_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_PD_STRENGTH_ALIGN 0 7537 #define DDR34_F0_PHY_BYTE_LANE_0_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_PD_STRENGTH_BITS 5 7538 #define DDR34_F0_PHY_BYTE_LANE_0_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_PD_STRENGTH_SHIFT 5 7539 7540 /* DDR34_F0_PHY_BYTE_LANE_0 :: RD_EN_DRIVE_PAD_CTL :: BL_RD_EN_ND_STRENGTH [04:00] */ 7541 #define DDR34_F0_PHY_BYTE_LANE_0_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_ND_STRENGTH_MASK 0x0000001f 7542 #define DDR34_F0_PHY_BYTE_LANE_0_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_ND_STRENGTH_ALIGN 0 7543 #define DDR34_F0_PHY_BYTE_LANE_0_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_ND_STRENGTH_BITS 5 7544 #define DDR34_F0_PHY_BYTE_LANE_0_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_ND_STRENGTH_SHIFT 0 7545 7546 7547 /**************************************************************************** 7548 * DDR34_F0_PHY_BYTE_LANE_0 :: STATIC_PAD_CTL 7549 */ 7550 /* DDR34_F0_PHY_BYTE_LANE_0 :: STATIC_PAD_CTL :: reserved0 [31:18] */ 7551 #define DDR34_F0_PHY_BYTE_LANE_0_STATIC_PAD_CTL_RESERVED0_MASK 0xfffc0000 7552 #define DDR34_F0_PHY_BYTE_LANE_0_STATIC_PAD_CTL_RESERVED0_ALIGN 0 7553 #define DDR34_F0_PHY_BYTE_LANE_0_STATIC_PAD_CTL_RESERVED0_BITS 14 7554 #define DDR34_F0_PHY_BYTE_LANE_0_STATIC_PAD_CTL_RESERVED0_SHIFT 18 7555 7556 /* DDR34_F0_PHY_BYTE_LANE_0 :: STATIC_PAD_CTL :: DM_INVERT [17:17] */ 7557 #define DDR34_F0_PHY_BYTE_LANE_0_STATIC_PAD_CTL_DM_INVERT_MASK 0x00020000 7558 #define DDR34_F0_PHY_BYTE_LANE_0_STATIC_PAD_CTL_DM_INVERT_ALIGN 0 7559 #define DDR34_F0_PHY_BYTE_LANE_0_STATIC_PAD_CTL_DM_INVERT_BITS 1 7560 #define DDR34_F0_PHY_BYTE_LANE_0_STATIC_PAD_CTL_DM_INVERT_SHIFT 17 7561 7562 /* DDR34_F0_PHY_BYTE_LANE_0 :: STATIC_PAD_CTL :: WDBI_ENABLE [16:16] */ 7563 #define DDR34_F0_PHY_BYTE_LANE_0_STATIC_PAD_CTL_WDBI_ENABLE_MASK 0x00010000 7564 #define DDR34_F0_PHY_BYTE_LANE_0_STATIC_PAD_CTL_WDBI_ENABLE_ALIGN 0 7565 #define DDR34_F0_PHY_BYTE_LANE_0_STATIC_PAD_CTL_WDBI_ENABLE_BITS 1 7566 #define DDR34_F0_PHY_BYTE_LANE_0_STATIC_PAD_CTL_WDBI_ENABLE_SHIFT 16 7567 7568 /* DDR34_F0_PHY_BYTE_LANE_0 :: STATIC_PAD_CTL :: RDBI_ENABLE [15:15] */ 7569 #define DDR34_F0_PHY_BYTE_LANE_0_STATIC_PAD_CTL_RDBI_ENABLE_MASK 0x00008000 7570 #define DDR34_F0_PHY_BYTE_LANE_0_STATIC_PAD_CTL_RDBI_ENABLE_ALIGN 0 7571 #define DDR34_F0_PHY_BYTE_LANE_0_STATIC_PAD_CTL_RDBI_ENABLE_BITS 1 7572 #define DDR34_F0_PHY_BYTE_LANE_0_STATIC_PAD_CTL_RDBI_ENABLE_SHIFT 15 7573 7574 /* DDR34_F0_PHY_BYTE_LANE_0 :: STATIC_PAD_CTL :: DM_MODE [14:14] */ 7575 #define DDR34_F0_PHY_BYTE_LANE_0_STATIC_PAD_CTL_DM_MODE_MASK 0x00004000 7576 #define DDR34_F0_PHY_BYTE_LANE_0_STATIC_PAD_CTL_DM_MODE_ALIGN 0 7577 #define DDR34_F0_PHY_BYTE_LANE_0_STATIC_PAD_CTL_DM_MODE_BITS 1 7578 #define DDR34_F0_PHY_BYTE_LANE_0_STATIC_PAD_CTL_DM_MODE_SHIFT 14 7579 7580 /* DDR34_F0_PHY_BYTE_LANE_0 :: STATIC_PAD_CTL :: reserved1 [13:10] */ 7581 #define DDR34_F0_PHY_BYTE_LANE_0_STATIC_PAD_CTL_RESERVED1_MASK 0x00003c00 7582 #define DDR34_F0_PHY_BYTE_LANE_0_STATIC_PAD_CTL_RESERVED1_ALIGN 0 7583 #define DDR34_F0_PHY_BYTE_LANE_0_STATIC_PAD_CTL_RESERVED1_BITS 4 7584 #define DDR34_F0_PHY_BYTE_LANE_0_STATIC_PAD_CTL_RESERVED1_SHIFT 10 7585 7586 /* DDR34_F0_PHY_BYTE_LANE_0 :: STATIC_PAD_CTL :: DQS_TX_DIS [09:09] */ 7587 #define DDR34_F0_PHY_BYTE_LANE_0_STATIC_PAD_CTL_DQS_TX_DIS_MASK 0x00000200 7588 #define DDR34_F0_PHY_BYTE_LANE_0_STATIC_PAD_CTL_DQS_TX_DIS_ALIGN 0 7589 #define DDR34_F0_PHY_BYTE_LANE_0_STATIC_PAD_CTL_DQS_TX_DIS_BITS 1 7590 #define DDR34_F0_PHY_BYTE_LANE_0_STATIC_PAD_CTL_DQS_TX_DIS_SHIFT 9 7591 7592 /* DDR34_F0_PHY_BYTE_LANE_0 :: STATIC_PAD_CTL :: reserved2 [08:02] */ 7593 #define DDR34_F0_PHY_BYTE_LANE_0_STATIC_PAD_CTL_RESERVED2_MASK 0x000001fc 7594 #define DDR34_F0_PHY_BYTE_LANE_0_STATIC_PAD_CTL_RESERVED2_ALIGN 0 7595 #define DDR34_F0_PHY_BYTE_LANE_0_STATIC_PAD_CTL_RESERVED2_BITS 7 7596 #define DDR34_F0_PHY_BYTE_LANE_0_STATIC_PAD_CTL_RESERVED2_SHIFT 2 7597 7598 /* DDR34_F0_PHY_BYTE_LANE_0 :: STATIC_PAD_CTL :: RX_MODE [01:00] */ 7599 #define DDR34_F0_PHY_BYTE_LANE_0_STATIC_PAD_CTL_RX_MODE_MASK 0x00000003 7600 #define DDR34_F0_PHY_BYTE_LANE_0_STATIC_PAD_CTL_RX_MODE_ALIGN 0 7601 #define DDR34_F0_PHY_BYTE_LANE_0_STATIC_PAD_CTL_RX_MODE_BITS 2 7602 #define DDR34_F0_PHY_BYTE_LANE_0_STATIC_PAD_CTL_RX_MODE_SHIFT 0 7603 7604 7605 /**************************************************************************** 7606 * DDR34_F0_PHY_BYTE_LANE_0 :: WR_PREAMBLE_MODE 7607 */ 7608 /* DDR34_F0_PHY_BYTE_LANE_0 :: WR_PREAMBLE_MODE :: reserved0 [31:21] */ 7609 #define DDR34_F0_PHY_BYTE_LANE_0_WR_PREAMBLE_MODE_RESERVED0_MASK 0xffe00000 7610 #define DDR34_F0_PHY_BYTE_LANE_0_WR_PREAMBLE_MODE_RESERVED0_ALIGN 0 7611 #define DDR34_F0_PHY_BYTE_LANE_0_WR_PREAMBLE_MODE_RESERVED0_BITS 11 7612 #define DDR34_F0_PHY_BYTE_LANE_0_WR_PREAMBLE_MODE_RESERVED0_SHIFT 21 7613 7614 /* DDR34_F0_PHY_BYTE_LANE_0 :: WR_PREAMBLE_MODE :: POSTAM_TERM_BITS [20:19] */ 7615 #define DDR34_F0_PHY_BYTE_LANE_0_WR_PREAMBLE_MODE_POSTAM_TERM_BITS_MASK 0x00180000 7616 #define DDR34_F0_PHY_BYTE_LANE_0_WR_PREAMBLE_MODE_POSTAM_TERM_BITS_ALIGN 0 7617 #define DDR34_F0_PHY_BYTE_LANE_0_WR_PREAMBLE_MODE_POSTAM_TERM_BITS_BITS 2 7618 #define DDR34_F0_PHY_BYTE_LANE_0_WR_PREAMBLE_MODE_POSTAM_TERM_BITS_SHIFT 19 7619 7620 /* DDR34_F0_PHY_BYTE_LANE_0 :: WR_PREAMBLE_MODE :: DM_POSTAM_BITS [18:17] */ 7621 #define DDR34_F0_PHY_BYTE_LANE_0_WR_PREAMBLE_MODE_DM_POSTAM_BITS_MASK 0x00060000 7622 #define DDR34_F0_PHY_BYTE_LANE_0_WR_PREAMBLE_MODE_DM_POSTAM_BITS_ALIGN 0 7623 #define DDR34_F0_PHY_BYTE_LANE_0_WR_PREAMBLE_MODE_DM_POSTAM_BITS_BITS 2 7624 #define DDR34_F0_PHY_BYTE_LANE_0_WR_PREAMBLE_MODE_DM_POSTAM_BITS_SHIFT 17 7625 7626 /* DDR34_F0_PHY_BYTE_LANE_0 :: WR_PREAMBLE_MODE :: DM_PREAM_BITS [16:14] */ 7627 #define DDR34_F0_PHY_BYTE_LANE_0_WR_PREAMBLE_MODE_DM_PREAM_BITS_MASK 0x0001c000 7628 #define DDR34_F0_PHY_BYTE_LANE_0_WR_PREAMBLE_MODE_DM_PREAM_BITS_ALIGN 0 7629 #define DDR34_F0_PHY_BYTE_LANE_0_WR_PREAMBLE_MODE_DM_PREAM_BITS_BITS 3 7630 #define DDR34_F0_PHY_BYTE_LANE_0_WR_PREAMBLE_MODE_DM_PREAM_BITS_SHIFT 14 7631 7632 /* DDR34_F0_PHY_BYTE_LANE_0 :: WR_PREAMBLE_MODE :: DQ_POSTAM_BITS [13:12] */ 7633 #define DDR34_F0_PHY_BYTE_LANE_0_WR_PREAMBLE_MODE_DQ_POSTAM_BITS_MASK 0x00003000 7634 #define DDR34_F0_PHY_BYTE_LANE_0_WR_PREAMBLE_MODE_DQ_POSTAM_BITS_ALIGN 0 7635 #define DDR34_F0_PHY_BYTE_LANE_0_WR_PREAMBLE_MODE_DQ_POSTAM_BITS_BITS 2 7636 #define DDR34_F0_PHY_BYTE_LANE_0_WR_PREAMBLE_MODE_DQ_POSTAM_BITS_SHIFT 12 7637 7638 /* DDR34_F0_PHY_BYTE_LANE_0 :: WR_PREAMBLE_MODE :: DQ_PREAM_BITS [11:09] */ 7639 #define DDR34_F0_PHY_BYTE_LANE_0_WR_PREAMBLE_MODE_DQ_PREAM_BITS_MASK 0x00000e00 7640 #define DDR34_F0_PHY_BYTE_LANE_0_WR_PREAMBLE_MODE_DQ_PREAM_BITS_ALIGN 0 7641 #define DDR34_F0_PHY_BYTE_LANE_0_WR_PREAMBLE_MODE_DQ_PREAM_BITS_BITS 3 7642 #define DDR34_F0_PHY_BYTE_LANE_0_WR_PREAMBLE_MODE_DQ_PREAM_BITS_SHIFT 9 7643 7644 /* DDR34_F0_PHY_BYTE_LANE_0 :: WR_PREAMBLE_MODE :: DQS [08:05] */ 7645 #define DDR34_F0_PHY_BYTE_LANE_0_WR_PREAMBLE_MODE_DQS_MASK 0x000001e0 7646 #define DDR34_F0_PHY_BYTE_LANE_0_WR_PREAMBLE_MODE_DQS_ALIGN 0 7647 #define DDR34_F0_PHY_BYTE_LANE_0_WR_PREAMBLE_MODE_DQS_BITS 4 7648 #define DDR34_F0_PHY_BYTE_LANE_0_WR_PREAMBLE_MODE_DQS_SHIFT 5 7649 7650 /* DDR34_F0_PHY_BYTE_LANE_0 :: WR_PREAMBLE_MODE :: DQS_POSTAM_BITS [04:03] */ 7651 #define DDR34_F0_PHY_BYTE_LANE_0_WR_PREAMBLE_MODE_DQS_POSTAM_BITS_MASK 0x00000018 7652 #define DDR34_F0_PHY_BYTE_LANE_0_WR_PREAMBLE_MODE_DQS_POSTAM_BITS_ALIGN 0 7653 #define DDR34_F0_PHY_BYTE_LANE_0_WR_PREAMBLE_MODE_DQS_POSTAM_BITS_BITS 2 7654 #define DDR34_F0_PHY_BYTE_LANE_0_WR_PREAMBLE_MODE_DQS_POSTAM_BITS_SHIFT 3 7655 7656 /* DDR34_F0_PHY_BYTE_LANE_0 :: WR_PREAMBLE_MODE :: DQS_PREAM_BITS [02:00] */ 7657 #define DDR34_F0_PHY_BYTE_LANE_0_WR_PREAMBLE_MODE_DQS_PREAM_BITS_MASK 0x00000007 7658 #define DDR34_F0_PHY_BYTE_LANE_0_WR_PREAMBLE_MODE_DQS_PREAM_BITS_ALIGN 0 7659 #define DDR34_F0_PHY_BYTE_LANE_0_WR_PREAMBLE_MODE_DQS_PREAM_BITS_BITS 3 7660 #define DDR34_F0_PHY_BYTE_LANE_0_WR_PREAMBLE_MODE_DQS_PREAM_BITS_SHIFT 0 7661 7662 7663 /**************************************************************************** 7664 * DDR34_F0_PHY_BYTE_LANE_0 :: ODT_CONTROL 7665 */ 7666 /* DDR34_F0_PHY_BYTE_LANE_0 :: ODT_CONTROL :: reserved0 [31:10] */ 7667 #define DDR34_F0_PHY_BYTE_LANE_0_ODT_CONTROL_RESERVED0_MASK 0xfffffc00 7668 #define DDR34_F0_PHY_BYTE_LANE_0_ODT_CONTROL_RESERVED0_ALIGN 0 7669 #define DDR34_F0_PHY_BYTE_LANE_0_ODT_CONTROL_RESERVED0_BITS 22 7670 #define DDR34_F0_PHY_BYTE_LANE_0_ODT_CONTROL_RESERVED0_SHIFT 10 7671 7672 /* DDR34_F0_PHY_BYTE_LANE_0 :: ODT_CONTROL :: ODT_ENABLE [09:09] */ 7673 #define DDR34_F0_PHY_BYTE_LANE_0_ODT_CONTROL_ODT_ENABLE_MASK 0x00000200 7674 #define DDR34_F0_PHY_BYTE_LANE_0_ODT_CONTROL_ODT_ENABLE_ALIGN 0 7675 #define DDR34_F0_PHY_BYTE_LANE_0_ODT_CONTROL_ODT_ENABLE_BITS 1 7676 #define DDR34_F0_PHY_BYTE_LANE_0_ODT_CONTROL_ODT_ENABLE_SHIFT 9 7677 7678 /* DDR34_F0_PHY_BYTE_LANE_0 :: ODT_CONTROL :: ODT_DELAY [08:06] */ 7679 #define DDR34_F0_PHY_BYTE_LANE_0_ODT_CONTROL_ODT_DELAY_MASK 0x000001c0 7680 #define DDR34_F0_PHY_BYTE_LANE_0_ODT_CONTROL_ODT_DELAY_ALIGN 0 7681 #define DDR34_F0_PHY_BYTE_LANE_0_ODT_CONTROL_ODT_DELAY_BITS 3 7682 #define DDR34_F0_PHY_BYTE_LANE_0_ODT_CONTROL_ODT_DELAY_SHIFT 6 7683 7684 /* DDR34_F0_PHY_BYTE_LANE_0 :: ODT_CONTROL :: ODT_POST_LENGTH [05:03] */ 7685 #define DDR34_F0_PHY_BYTE_LANE_0_ODT_CONTROL_ODT_POST_LENGTH_MASK 0x00000038 7686 #define DDR34_F0_PHY_BYTE_LANE_0_ODT_CONTROL_ODT_POST_LENGTH_ALIGN 0 7687 #define DDR34_F0_PHY_BYTE_LANE_0_ODT_CONTROL_ODT_POST_LENGTH_BITS 3 7688 #define DDR34_F0_PHY_BYTE_LANE_0_ODT_CONTROL_ODT_POST_LENGTH_SHIFT 3 7689 7690 /* DDR34_F0_PHY_BYTE_LANE_0 :: ODT_CONTROL :: reserved1 [02:02] */ 7691 #define DDR34_F0_PHY_BYTE_LANE_0_ODT_CONTROL_RESERVED1_MASK 0x00000004 7692 #define DDR34_F0_PHY_BYTE_LANE_0_ODT_CONTROL_RESERVED1_ALIGN 0 7693 #define DDR34_F0_PHY_BYTE_LANE_0_ODT_CONTROL_RESERVED1_BITS 1 7694 #define DDR34_F0_PHY_BYTE_LANE_0_ODT_CONTROL_RESERVED1_SHIFT 2 7695 7696 /* DDR34_F0_PHY_BYTE_LANE_0 :: ODT_CONTROL :: ODT_PRE_LENGTH [01:00] */ 7697 #define DDR34_F0_PHY_BYTE_LANE_0_ODT_CONTROL_ODT_PRE_LENGTH_MASK 0x00000003 7698 #define DDR34_F0_PHY_BYTE_LANE_0_ODT_CONTROL_ODT_PRE_LENGTH_ALIGN 0 7699 #define DDR34_F0_PHY_BYTE_LANE_0_ODT_CONTROL_ODT_PRE_LENGTH_BITS 2 7700 #define DDR34_F0_PHY_BYTE_LANE_0_ODT_CONTROL_ODT_PRE_LENGTH_SHIFT 0 7701 7702 7703 /**************************************************************************** 7704 * DDR34_F0_PHY_BYTE_LANE_0 :: CLOCK_ENABLE 7705 */ 7706 /* DDR34_F0_PHY_BYTE_LANE_0 :: CLOCK_ENABLE :: reserved0 [31:03] */ 7707 #define DDR34_F0_PHY_BYTE_LANE_0_CLOCK_ENABLE_RESERVED0_MASK 0xfffffff8 7708 #define DDR34_F0_PHY_BYTE_LANE_0_CLOCK_ENABLE_RESERVED0_ALIGN 0 7709 #define DDR34_F0_PHY_BYTE_LANE_0_CLOCK_ENABLE_RESERVED0_BITS 29 7710 #define DDR34_F0_PHY_BYTE_LANE_0_CLOCK_ENABLE_RESERVED0_SHIFT 3 7711 7712 /* DDR34_F0_PHY_BYTE_LANE_0 :: CLOCK_ENABLE :: TO_MC_CLOCK [02:02] */ 7713 #define DDR34_F0_PHY_BYTE_LANE_0_CLOCK_ENABLE_TO_MC_CLOCK_MASK 0x00000004 7714 #define DDR34_F0_PHY_BYTE_LANE_0_CLOCK_ENABLE_TO_MC_CLOCK_ALIGN 0 7715 #define DDR34_F0_PHY_BYTE_LANE_0_CLOCK_ENABLE_TO_MC_CLOCK_BITS 1 7716 #define DDR34_F0_PHY_BYTE_LANE_0_CLOCK_ENABLE_TO_MC_CLOCK_SHIFT 2 7717 7718 /* DDR34_F0_PHY_BYTE_LANE_0 :: CLOCK_ENABLE :: FROM_MC_CLOCK [01:01] */ 7719 #define DDR34_F0_PHY_BYTE_LANE_0_CLOCK_ENABLE_FROM_MC_CLOCK_MASK 0x00000002 7720 #define DDR34_F0_PHY_BYTE_LANE_0_CLOCK_ENABLE_FROM_MC_CLOCK_ALIGN 0 7721 #define DDR34_F0_PHY_BYTE_LANE_0_CLOCK_ENABLE_FROM_MC_CLOCK_BITS 1 7722 #define DDR34_F0_PHY_BYTE_LANE_0_CLOCK_ENABLE_FROM_MC_CLOCK_SHIFT 1 7723 7724 /* DDR34_F0_PHY_BYTE_LANE_0 :: CLOCK_ENABLE :: BIT_CLOCK [00:00] */ 7725 #define DDR34_F0_PHY_BYTE_LANE_0_CLOCK_ENABLE_BIT_CLOCK_MASK 0x00000001 7726 #define DDR34_F0_PHY_BYTE_LANE_0_CLOCK_ENABLE_BIT_CLOCK_ALIGN 0 7727 #define DDR34_F0_PHY_BYTE_LANE_0_CLOCK_ENABLE_BIT_CLOCK_BITS 1 7728 #define DDR34_F0_PHY_BYTE_LANE_0_CLOCK_ENABLE_BIT_CLOCK_SHIFT 0 7729 7730 7731 /**************************************************************************** 7732 * DDR34_F0_PHY_BYTE_LANE_0 :: CLOCK_IDLE 7733 */ 7734 /* DDR34_F0_PHY_BYTE_LANE_0 :: CLOCK_IDLE :: reserved0 [31:03] */ 7735 #define DDR34_F0_PHY_BYTE_LANE_0_CLOCK_IDLE_RESERVED0_MASK 0xfffffff8 7736 #define DDR34_F0_PHY_BYTE_LANE_0_CLOCK_IDLE_RESERVED0_ALIGN 0 7737 #define DDR34_F0_PHY_BYTE_LANE_0_CLOCK_IDLE_RESERVED0_BITS 29 7738 #define DDR34_F0_PHY_BYTE_LANE_0_CLOCK_IDLE_RESERVED0_SHIFT 3 7739 7740 /* DDR34_F0_PHY_BYTE_LANE_0 :: CLOCK_IDLE :: TO_MC_CLOCK [02:02] */ 7741 #define DDR34_F0_PHY_BYTE_LANE_0_CLOCK_IDLE_TO_MC_CLOCK_MASK 0x00000004 7742 #define DDR34_F0_PHY_BYTE_LANE_0_CLOCK_IDLE_TO_MC_CLOCK_ALIGN 0 7743 #define DDR34_F0_PHY_BYTE_LANE_0_CLOCK_IDLE_TO_MC_CLOCK_BITS 1 7744 #define DDR34_F0_PHY_BYTE_LANE_0_CLOCK_IDLE_TO_MC_CLOCK_SHIFT 2 7745 7746 /* DDR34_F0_PHY_BYTE_LANE_0 :: CLOCK_IDLE :: FROM_MC_CLOCK [01:01] */ 7747 #define DDR34_F0_PHY_BYTE_LANE_0_CLOCK_IDLE_FROM_MC_CLOCK_MASK 0x00000002 7748 #define DDR34_F0_PHY_BYTE_LANE_0_CLOCK_IDLE_FROM_MC_CLOCK_ALIGN 0 7749 #define DDR34_F0_PHY_BYTE_LANE_0_CLOCK_IDLE_FROM_MC_CLOCK_BITS 1 7750 #define DDR34_F0_PHY_BYTE_LANE_0_CLOCK_IDLE_FROM_MC_CLOCK_SHIFT 1 7751 7752 /* DDR34_F0_PHY_BYTE_LANE_0 :: CLOCK_IDLE :: BIT_CLOCK [00:00] */ 7753 #define DDR34_F0_PHY_BYTE_LANE_0_CLOCK_IDLE_BIT_CLOCK_MASK 0x00000001 7754 #define DDR34_F0_PHY_BYTE_LANE_0_CLOCK_IDLE_BIT_CLOCK_ALIGN 0 7755 #define DDR34_F0_PHY_BYTE_LANE_0_CLOCK_IDLE_BIT_CLOCK_BITS 1 7756 #define DDR34_F0_PHY_BYTE_LANE_0_CLOCK_IDLE_BIT_CLOCK_SHIFT 0 7757 7758 7759 /**************************************************************************** 7760 * DDR34_F0_PHY_BYTE_LANE_0 :: BL_SPARE_REG 7761 */ 7762 /* DDR34_F0_PHY_BYTE_LANE_0 :: BL_SPARE_REG :: reserved_for_eco0 [31:00] */ 7763 #define DDR34_F0_PHY_BYTE_LANE_0_BL_SPARE_REG_RESERVED_FOR_ECO0_MASK 0xffffffff 7764 #define DDR34_F0_PHY_BYTE_LANE_0_BL_SPARE_REG_RESERVED_FOR_ECO0_ALIGN 0 7765 #define DDR34_F0_PHY_BYTE_LANE_0_BL_SPARE_REG_RESERVED_FOR_ECO0_BITS 32 7766 #define DDR34_F0_PHY_BYTE_LANE_0_BL_SPARE_REG_RESERVED_FOR_ECO0_SHIFT 0 7767 7768 7769 /**************************************************************************** 7770 * DDR34_F0_PHY_DDR34_F0_PHY_BYTE_LANE_1 7771 */ 7772 /**************************************************************************** 7773 * DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQS 7774 */ 7775 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQS :: BUSY [31:31] */ 7776 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_BUSY_MASK 0x80000000 7777 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_BUSY_ALIGN 0 7778 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_BUSY_BITS 1 7779 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_BUSY_SHIFT 31 7780 7781 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQS :: reserved0 [30:17] */ 7782 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_RESERVED0_MASK 0x7ffe0000 7783 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_RESERVED0_ALIGN 0 7784 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_RESERVED0_BITS 14 7785 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_RESERVED0_SHIFT 17 7786 7787 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQS :: FORCE [16:16] */ 7788 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_FORCE_MASK 0x00010000 7789 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_FORCE_ALIGN 0 7790 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_FORCE_BITS 1 7791 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_FORCE_SHIFT 16 7792 7793 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQS :: reserved1 [15:13] */ 7794 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_RESERVED1_MASK 0x0000e000 7795 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_RESERVED1_ALIGN 0 7796 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_RESERVED1_BITS 3 7797 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_RESERVED1_SHIFT 13 7798 7799 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQS :: ADJ_EN [12:12] */ 7800 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_ADJ_EN_MASK 0x00001000 7801 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_ADJ_EN_ALIGN 0 7802 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_ADJ_EN_BITS 1 7803 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_ADJ_EN_SHIFT 12 7804 7805 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQS :: reserved2 [11:09] */ 7806 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_RESERVED2_MASK 0x00000e00 7807 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_RESERVED2_ALIGN 0 7808 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_RESERVED2_BITS 3 7809 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_RESERVED2_SHIFT 9 7810 7811 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQS :: VDL_STEP [08:00] */ 7812 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_VDL_STEP_MASK 0x000001ff 7813 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_VDL_STEP_ALIGN 0 7814 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_VDL_STEP_BITS 9 7815 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_VDL_STEP_SHIFT 0 7816 7817 7818 /**************************************************************************** 7819 * DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ0 7820 */ 7821 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ0 :: BUSY [31:31] */ 7822 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0_BUSY_MASK 0x80000000 7823 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0_BUSY_ALIGN 0 7824 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0_BUSY_BITS 1 7825 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0_BUSY_SHIFT 31 7826 7827 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ0 :: reserved0 [30:17] */ 7828 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0_RESERVED0_MASK 0x7ffe0000 7829 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0_RESERVED0_ALIGN 0 7830 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0_RESERVED0_BITS 14 7831 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0_RESERVED0_SHIFT 17 7832 7833 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ0 :: FORCE [16:16] */ 7834 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0_FORCE_MASK 0x00010000 7835 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0_FORCE_ALIGN 0 7836 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0_FORCE_BITS 1 7837 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0_FORCE_SHIFT 16 7838 7839 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ0 :: reserved1 [15:13] */ 7840 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0_RESERVED1_MASK 0x0000e000 7841 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0_RESERVED1_ALIGN 0 7842 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0_RESERVED1_BITS 3 7843 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0_RESERVED1_SHIFT 13 7844 7845 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ0 :: ADJ_EN [12:12] */ 7846 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0_ADJ_EN_MASK 0x00001000 7847 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0_ADJ_EN_ALIGN 0 7848 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0_ADJ_EN_BITS 1 7849 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0_ADJ_EN_SHIFT 12 7850 7851 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ0 :: reserved2 [11:09] */ 7852 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0_RESERVED2_MASK 0x00000e00 7853 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0_RESERVED2_ALIGN 0 7854 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0_RESERVED2_BITS 3 7855 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0_RESERVED2_SHIFT 9 7856 7857 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ0 :: VDL_STEP [08:00] */ 7858 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0_VDL_STEP_MASK 0x000001ff 7859 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0_VDL_STEP_ALIGN 0 7860 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0_VDL_STEP_BITS 9 7861 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0_VDL_STEP_SHIFT 0 7862 7863 7864 /**************************************************************************** 7865 * DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ1 7866 */ 7867 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ1 :: BUSY [31:31] */ 7868 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1_BUSY_MASK 0x80000000 7869 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1_BUSY_ALIGN 0 7870 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1_BUSY_BITS 1 7871 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1_BUSY_SHIFT 31 7872 7873 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ1 :: reserved0 [30:17] */ 7874 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1_RESERVED0_MASK 0x7ffe0000 7875 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1_RESERVED0_ALIGN 0 7876 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1_RESERVED0_BITS 14 7877 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1_RESERVED0_SHIFT 17 7878 7879 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ1 :: FORCE [16:16] */ 7880 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1_FORCE_MASK 0x00010000 7881 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1_FORCE_ALIGN 0 7882 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1_FORCE_BITS 1 7883 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1_FORCE_SHIFT 16 7884 7885 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ1 :: reserved1 [15:13] */ 7886 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1_RESERVED1_MASK 0x0000e000 7887 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1_RESERVED1_ALIGN 0 7888 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1_RESERVED1_BITS 3 7889 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1_RESERVED1_SHIFT 13 7890 7891 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ1 :: ADJ_EN [12:12] */ 7892 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1_ADJ_EN_MASK 0x00001000 7893 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1_ADJ_EN_ALIGN 0 7894 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1_ADJ_EN_BITS 1 7895 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1_ADJ_EN_SHIFT 12 7896 7897 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ1 :: reserved2 [11:09] */ 7898 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1_RESERVED2_MASK 0x00000e00 7899 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1_RESERVED2_ALIGN 0 7900 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1_RESERVED2_BITS 3 7901 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1_RESERVED2_SHIFT 9 7902 7903 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ1 :: VDL_STEP [08:00] */ 7904 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1_VDL_STEP_MASK 0x000001ff 7905 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1_VDL_STEP_ALIGN 0 7906 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1_VDL_STEP_BITS 9 7907 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1_VDL_STEP_SHIFT 0 7908 7909 7910 /**************************************************************************** 7911 * DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ2 7912 */ 7913 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ2 :: BUSY [31:31] */ 7914 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2_BUSY_MASK 0x80000000 7915 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2_BUSY_ALIGN 0 7916 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2_BUSY_BITS 1 7917 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2_BUSY_SHIFT 31 7918 7919 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ2 :: reserved0 [30:17] */ 7920 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2_RESERVED0_MASK 0x7ffe0000 7921 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2_RESERVED0_ALIGN 0 7922 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2_RESERVED0_BITS 14 7923 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2_RESERVED0_SHIFT 17 7924 7925 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ2 :: FORCE [16:16] */ 7926 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2_FORCE_MASK 0x00010000 7927 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2_FORCE_ALIGN 0 7928 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2_FORCE_BITS 1 7929 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2_FORCE_SHIFT 16 7930 7931 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ2 :: reserved1 [15:13] */ 7932 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2_RESERVED1_MASK 0x0000e000 7933 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2_RESERVED1_ALIGN 0 7934 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2_RESERVED1_BITS 3 7935 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2_RESERVED1_SHIFT 13 7936 7937 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ2 :: ADJ_EN [12:12] */ 7938 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2_ADJ_EN_MASK 0x00001000 7939 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2_ADJ_EN_ALIGN 0 7940 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2_ADJ_EN_BITS 1 7941 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2_ADJ_EN_SHIFT 12 7942 7943 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ2 :: reserved2 [11:09] */ 7944 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2_RESERVED2_MASK 0x00000e00 7945 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2_RESERVED2_ALIGN 0 7946 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2_RESERVED2_BITS 3 7947 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2_RESERVED2_SHIFT 9 7948 7949 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ2 :: VDL_STEP [08:00] */ 7950 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2_VDL_STEP_MASK 0x000001ff 7951 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2_VDL_STEP_ALIGN 0 7952 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2_VDL_STEP_BITS 9 7953 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2_VDL_STEP_SHIFT 0 7954 7955 7956 /**************************************************************************** 7957 * DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ3 7958 */ 7959 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ3 :: BUSY [31:31] */ 7960 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3_BUSY_MASK 0x80000000 7961 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3_BUSY_ALIGN 0 7962 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3_BUSY_BITS 1 7963 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3_BUSY_SHIFT 31 7964 7965 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ3 :: reserved0 [30:17] */ 7966 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3_RESERVED0_MASK 0x7ffe0000 7967 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3_RESERVED0_ALIGN 0 7968 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3_RESERVED0_BITS 14 7969 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3_RESERVED0_SHIFT 17 7970 7971 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ3 :: FORCE [16:16] */ 7972 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3_FORCE_MASK 0x00010000 7973 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3_FORCE_ALIGN 0 7974 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3_FORCE_BITS 1 7975 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3_FORCE_SHIFT 16 7976 7977 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ3 :: reserved1 [15:13] */ 7978 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3_RESERVED1_MASK 0x0000e000 7979 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3_RESERVED1_ALIGN 0 7980 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3_RESERVED1_BITS 3 7981 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3_RESERVED1_SHIFT 13 7982 7983 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ3 :: ADJ_EN [12:12] */ 7984 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3_ADJ_EN_MASK 0x00001000 7985 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3_ADJ_EN_ALIGN 0 7986 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3_ADJ_EN_BITS 1 7987 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3_ADJ_EN_SHIFT 12 7988 7989 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ3 :: reserved2 [11:09] */ 7990 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3_RESERVED2_MASK 0x00000e00 7991 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3_RESERVED2_ALIGN 0 7992 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3_RESERVED2_BITS 3 7993 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3_RESERVED2_SHIFT 9 7994 7995 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ3 :: VDL_STEP [08:00] */ 7996 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3_VDL_STEP_MASK 0x000001ff 7997 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3_VDL_STEP_ALIGN 0 7998 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3_VDL_STEP_BITS 9 7999 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3_VDL_STEP_SHIFT 0 8000 8001 8002 /**************************************************************************** 8003 * DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ4 8004 */ 8005 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ4 :: BUSY [31:31] */ 8006 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4_BUSY_MASK 0x80000000 8007 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4_BUSY_ALIGN 0 8008 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4_BUSY_BITS 1 8009 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4_BUSY_SHIFT 31 8010 8011 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ4 :: reserved0 [30:17] */ 8012 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4_RESERVED0_MASK 0x7ffe0000 8013 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4_RESERVED0_ALIGN 0 8014 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4_RESERVED0_BITS 14 8015 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4_RESERVED0_SHIFT 17 8016 8017 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ4 :: FORCE [16:16] */ 8018 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4_FORCE_MASK 0x00010000 8019 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4_FORCE_ALIGN 0 8020 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4_FORCE_BITS 1 8021 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4_FORCE_SHIFT 16 8022 8023 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ4 :: reserved1 [15:13] */ 8024 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4_RESERVED1_MASK 0x0000e000 8025 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4_RESERVED1_ALIGN 0 8026 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4_RESERVED1_BITS 3 8027 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4_RESERVED1_SHIFT 13 8028 8029 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ4 :: ADJ_EN [12:12] */ 8030 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4_ADJ_EN_MASK 0x00001000 8031 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4_ADJ_EN_ALIGN 0 8032 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4_ADJ_EN_BITS 1 8033 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4_ADJ_EN_SHIFT 12 8034 8035 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ4 :: reserved2 [11:09] */ 8036 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4_RESERVED2_MASK 0x00000e00 8037 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4_RESERVED2_ALIGN 0 8038 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4_RESERVED2_BITS 3 8039 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4_RESERVED2_SHIFT 9 8040 8041 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ4 :: VDL_STEP [08:00] */ 8042 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4_VDL_STEP_MASK 0x000001ff 8043 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4_VDL_STEP_ALIGN 0 8044 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4_VDL_STEP_BITS 9 8045 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4_VDL_STEP_SHIFT 0 8046 8047 8048 /**************************************************************************** 8049 * DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ5 8050 */ 8051 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ5 :: BUSY [31:31] */ 8052 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5_BUSY_MASK 0x80000000 8053 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5_BUSY_ALIGN 0 8054 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5_BUSY_BITS 1 8055 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5_BUSY_SHIFT 31 8056 8057 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ5 :: reserved0 [30:17] */ 8058 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5_RESERVED0_MASK 0x7ffe0000 8059 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5_RESERVED0_ALIGN 0 8060 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5_RESERVED0_BITS 14 8061 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5_RESERVED0_SHIFT 17 8062 8063 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ5 :: FORCE [16:16] */ 8064 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5_FORCE_MASK 0x00010000 8065 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5_FORCE_ALIGN 0 8066 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5_FORCE_BITS 1 8067 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5_FORCE_SHIFT 16 8068 8069 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ5 :: reserved1 [15:13] */ 8070 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5_RESERVED1_MASK 0x0000e000 8071 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5_RESERVED1_ALIGN 0 8072 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5_RESERVED1_BITS 3 8073 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5_RESERVED1_SHIFT 13 8074 8075 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ5 :: ADJ_EN [12:12] */ 8076 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5_ADJ_EN_MASK 0x00001000 8077 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5_ADJ_EN_ALIGN 0 8078 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5_ADJ_EN_BITS 1 8079 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5_ADJ_EN_SHIFT 12 8080 8081 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ5 :: reserved2 [11:09] */ 8082 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5_RESERVED2_MASK 0x00000e00 8083 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5_RESERVED2_ALIGN 0 8084 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5_RESERVED2_BITS 3 8085 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5_RESERVED2_SHIFT 9 8086 8087 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ5 :: VDL_STEP [08:00] */ 8088 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5_VDL_STEP_MASK 0x000001ff 8089 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5_VDL_STEP_ALIGN 0 8090 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5_VDL_STEP_BITS 9 8091 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5_VDL_STEP_SHIFT 0 8092 8093 8094 /**************************************************************************** 8095 * DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ6 8096 */ 8097 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ6 :: BUSY [31:31] */ 8098 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6_BUSY_MASK 0x80000000 8099 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6_BUSY_ALIGN 0 8100 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6_BUSY_BITS 1 8101 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6_BUSY_SHIFT 31 8102 8103 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ6 :: reserved0 [30:17] */ 8104 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6_RESERVED0_MASK 0x7ffe0000 8105 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6_RESERVED0_ALIGN 0 8106 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6_RESERVED0_BITS 14 8107 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6_RESERVED0_SHIFT 17 8108 8109 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ6 :: FORCE [16:16] */ 8110 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6_FORCE_MASK 0x00010000 8111 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6_FORCE_ALIGN 0 8112 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6_FORCE_BITS 1 8113 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6_FORCE_SHIFT 16 8114 8115 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ6 :: reserved1 [15:13] */ 8116 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6_RESERVED1_MASK 0x0000e000 8117 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6_RESERVED1_ALIGN 0 8118 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6_RESERVED1_BITS 3 8119 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6_RESERVED1_SHIFT 13 8120 8121 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ6 :: ADJ_EN [12:12] */ 8122 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6_ADJ_EN_MASK 0x00001000 8123 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6_ADJ_EN_ALIGN 0 8124 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6_ADJ_EN_BITS 1 8125 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6_ADJ_EN_SHIFT 12 8126 8127 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ6 :: reserved2 [11:09] */ 8128 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6_RESERVED2_MASK 0x00000e00 8129 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6_RESERVED2_ALIGN 0 8130 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6_RESERVED2_BITS 3 8131 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6_RESERVED2_SHIFT 9 8132 8133 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ6 :: VDL_STEP [08:00] */ 8134 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6_VDL_STEP_MASK 0x000001ff 8135 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6_VDL_STEP_ALIGN 0 8136 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6_VDL_STEP_BITS 9 8137 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6_VDL_STEP_SHIFT 0 8138 8139 8140 /**************************************************************************** 8141 * DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ7 8142 */ 8143 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ7 :: BUSY [31:31] */ 8144 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7_BUSY_MASK 0x80000000 8145 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7_BUSY_ALIGN 0 8146 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7_BUSY_BITS 1 8147 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7_BUSY_SHIFT 31 8148 8149 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ7 :: reserved0 [30:17] */ 8150 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7_RESERVED0_MASK 0x7ffe0000 8151 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7_RESERVED0_ALIGN 0 8152 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7_RESERVED0_BITS 14 8153 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7_RESERVED0_SHIFT 17 8154 8155 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ7 :: FORCE [16:16] */ 8156 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7_FORCE_MASK 0x00010000 8157 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7_FORCE_ALIGN 0 8158 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7_FORCE_BITS 1 8159 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7_FORCE_SHIFT 16 8160 8161 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ7 :: reserved1 [15:13] */ 8162 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7_RESERVED1_MASK 0x0000e000 8163 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7_RESERVED1_ALIGN 0 8164 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7_RESERVED1_BITS 3 8165 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7_RESERVED1_SHIFT 13 8166 8167 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ7 :: ADJ_EN [12:12] */ 8168 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7_ADJ_EN_MASK 0x00001000 8169 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7_ADJ_EN_ALIGN 0 8170 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7_ADJ_EN_BITS 1 8171 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7_ADJ_EN_SHIFT 12 8172 8173 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ7 :: reserved2 [11:09] */ 8174 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7_RESERVED2_MASK 0x00000e00 8175 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7_RESERVED2_ALIGN 0 8176 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7_RESERVED2_BITS 3 8177 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7_RESERVED2_SHIFT 9 8178 8179 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ7 :: VDL_STEP [08:00] */ 8180 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7_VDL_STEP_MASK 0x000001ff 8181 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7_VDL_STEP_ALIGN 0 8182 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7_VDL_STEP_BITS 9 8183 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7_VDL_STEP_SHIFT 0 8184 8185 8186 /**************************************************************************** 8187 * DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DM 8188 */ 8189 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DM :: BUSY [31:31] */ 8190 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DM_BUSY_MASK 0x80000000 8191 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DM_BUSY_ALIGN 0 8192 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DM_BUSY_BITS 1 8193 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DM_BUSY_SHIFT 31 8194 8195 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DM :: reserved0 [30:17] */ 8196 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DM_RESERVED0_MASK 0x7ffe0000 8197 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DM_RESERVED0_ALIGN 0 8198 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DM_RESERVED0_BITS 14 8199 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DM_RESERVED0_SHIFT 17 8200 8201 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DM :: FORCE [16:16] */ 8202 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DM_FORCE_MASK 0x00010000 8203 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DM_FORCE_ALIGN 0 8204 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DM_FORCE_BITS 1 8205 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DM_FORCE_SHIFT 16 8206 8207 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DM :: reserved1 [15:13] */ 8208 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DM_RESERVED1_MASK 0x0000e000 8209 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DM_RESERVED1_ALIGN 0 8210 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DM_RESERVED1_BITS 3 8211 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DM_RESERVED1_SHIFT 13 8212 8213 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DM :: ADJ_EN [12:12] */ 8214 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DM_ADJ_EN_MASK 0x00001000 8215 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DM_ADJ_EN_ALIGN 0 8216 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DM_ADJ_EN_BITS 1 8217 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DM_ADJ_EN_SHIFT 12 8218 8219 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DM :: reserved2 [11:09] */ 8220 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DM_RESERVED2_MASK 0x00000e00 8221 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DM_RESERVED2_ALIGN 0 8222 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DM_RESERVED2_BITS 3 8223 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DM_RESERVED2_SHIFT 9 8224 8225 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DM :: VDL_STEP [08:00] */ 8226 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DM_VDL_STEP_MASK 0x000001ff 8227 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DM_VDL_STEP_ALIGN 0 8228 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DM_VDL_STEP_BITS 9 8229 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DM_VDL_STEP_SHIFT 0 8230 8231 8232 /**************************************************************************** 8233 * DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_ALERT 8234 */ 8235 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_ALERT :: BUSY [31:31] */ 8236 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_ALERT_BUSY_MASK 0x80000000 8237 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_ALERT_BUSY_ALIGN 0 8238 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_ALERT_BUSY_BITS 1 8239 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_ALERT_BUSY_SHIFT 31 8240 8241 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_ALERT :: reserved0 [30:17] */ 8242 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_ALERT_RESERVED0_MASK 0x7ffe0000 8243 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_ALERT_RESERVED0_ALIGN 0 8244 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_ALERT_RESERVED0_BITS 14 8245 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_ALERT_RESERVED0_SHIFT 17 8246 8247 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_ALERT :: FORCE [16:16] */ 8248 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_ALERT_FORCE_MASK 0x00010000 8249 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_ALERT_FORCE_ALIGN 0 8250 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_ALERT_FORCE_BITS 1 8251 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_ALERT_FORCE_SHIFT 16 8252 8253 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_ALERT :: reserved1 [15:13] */ 8254 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_ALERT_RESERVED1_MASK 0x0000e000 8255 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_ALERT_RESERVED1_ALIGN 0 8256 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_ALERT_RESERVED1_BITS 3 8257 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_ALERT_RESERVED1_SHIFT 13 8258 8259 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_ALERT :: ADJ_EN [12:12] */ 8260 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_ALERT_ADJ_EN_MASK 0x00001000 8261 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_ALERT_ADJ_EN_ALIGN 0 8262 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_ALERT_ADJ_EN_BITS 1 8263 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_ALERT_ADJ_EN_SHIFT 12 8264 8265 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_ALERT :: reserved2 [11:09] */ 8266 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_ALERT_RESERVED2_MASK 0x00000e00 8267 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_ALERT_RESERVED2_ALIGN 0 8268 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_ALERT_RESERVED2_BITS 3 8269 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_ALERT_RESERVED2_SHIFT 9 8270 8271 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_ALERT :: VDL_STEP [08:00] */ 8272 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_ALERT_VDL_STEP_MASK 0x000001ff 8273 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_ALERT_VDL_STEP_ALIGN 0 8274 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_ALERT_VDL_STEP_BITS 9 8275 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_ALERT_VDL_STEP_SHIFT 0 8276 8277 8278 /**************************************************************************** 8279 * DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQSP 8280 */ 8281 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQSP :: BUSY [31:31] */ 8282 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSP_BUSY_MASK 0x80000000 8283 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSP_BUSY_ALIGN 0 8284 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSP_BUSY_BITS 1 8285 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSP_BUSY_SHIFT 31 8286 8287 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQSP :: reserved0 [30:17] */ 8288 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSP_RESERVED0_MASK 0x7ffe0000 8289 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSP_RESERVED0_ALIGN 0 8290 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSP_RESERVED0_BITS 14 8291 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSP_RESERVED0_SHIFT 17 8292 8293 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQSP :: FORCE [16:16] */ 8294 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSP_FORCE_MASK 0x00010000 8295 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSP_FORCE_ALIGN 0 8296 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSP_FORCE_BITS 1 8297 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSP_FORCE_SHIFT 16 8298 8299 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQSP :: reserved1 [15:13] */ 8300 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSP_RESERVED1_MASK 0x0000e000 8301 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSP_RESERVED1_ALIGN 0 8302 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSP_RESERVED1_BITS 3 8303 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSP_RESERVED1_SHIFT 13 8304 8305 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQSP :: ADJ_EN [12:12] */ 8306 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSP_ADJ_EN_MASK 0x00001000 8307 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSP_ADJ_EN_ALIGN 0 8308 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSP_ADJ_EN_BITS 1 8309 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSP_ADJ_EN_SHIFT 12 8310 8311 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQSP :: reserved2 [11:08] */ 8312 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSP_RESERVED2_MASK 0x00000f00 8313 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSP_RESERVED2_ALIGN 0 8314 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSP_RESERVED2_BITS 4 8315 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSP_RESERVED2_SHIFT 8 8316 8317 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQSP :: VDL_STEP [07:00] */ 8318 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSP_VDL_STEP_MASK 0x000000ff 8319 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSP_VDL_STEP_ALIGN 0 8320 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSP_VDL_STEP_BITS 8 8321 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSP_VDL_STEP_SHIFT 0 8322 8323 8324 /**************************************************************************** 8325 * DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQSN 8326 */ 8327 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQSN :: BUSY [31:31] */ 8328 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSN_BUSY_MASK 0x80000000 8329 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSN_BUSY_ALIGN 0 8330 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSN_BUSY_BITS 1 8331 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSN_BUSY_SHIFT 31 8332 8333 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQSN :: reserved0 [30:17] */ 8334 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSN_RESERVED0_MASK 0x7ffe0000 8335 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSN_RESERVED0_ALIGN 0 8336 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSN_RESERVED0_BITS 14 8337 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSN_RESERVED0_SHIFT 17 8338 8339 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQSN :: FORCE [16:16] */ 8340 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSN_FORCE_MASK 0x00010000 8341 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSN_FORCE_ALIGN 0 8342 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSN_FORCE_BITS 1 8343 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSN_FORCE_SHIFT 16 8344 8345 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQSN :: reserved1 [15:13] */ 8346 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSN_RESERVED1_MASK 0x0000e000 8347 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSN_RESERVED1_ALIGN 0 8348 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSN_RESERVED1_BITS 3 8349 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSN_RESERVED1_SHIFT 13 8350 8351 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQSN :: ADJ_EN [12:12] */ 8352 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSN_ADJ_EN_MASK 0x00001000 8353 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSN_ADJ_EN_ALIGN 0 8354 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSN_ADJ_EN_BITS 1 8355 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSN_ADJ_EN_SHIFT 12 8356 8357 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQSN :: reserved2 [11:08] */ 8358 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSN_RESERVED2_MASK 0x00000f00 8359 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSN_RESERVED2_ALIGN 0 8360 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSN_RESERVED2_BITS 4 8361 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSN_RESERVED2_SHIFT 8 8362 8363 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQSN :: VDL_STEP [07:00] */ 8364 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSN_VDL_STEP_MASK 0x000000ff 8365 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSN_VDL_STEP_ALIGN 0 8366 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSN_VDL_STEP_BITS 8 8367 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSN_VDL_STEP_SHIFT 0 8368 8369 8370 /**************************************************************************** 8371 * DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ0P 8372 */ 8373 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ0P :: BUSY [31:31] */ 8374 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0P_BUSY_MASK 0x80000000 8375 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0P_BUSY_ALIGN 0 8376 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0P_BUSY_BITS 1 8377 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0P_BUSY_SHIFT 31 8378 8379 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ0P :: reserved0 [30:17] */ 8380 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0P_RESERVED0_MASK 0x7ffe0000 8381 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0P_RESERVED0_ALIGN 0 8382 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0P_RESERVED0_BITS 14 8383 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0P_RESERVED0_SHIFT 17 8384 8385 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ0P :: FORCE [16:16] */ 8386 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0P_FORCE_MASK 0x00010000 8387 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0P_FORCE_ALIGN 0 8388 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0P_FORCE_BITS 1 8389 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0P_FORCE_SHIFT 16 8390 8391 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ0P :: reserved1 [15:13] */ 8392 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0P_RESERVED1_MASK 0x0000e000 8393 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0P_RESERVED1_ALIGN 0 8394 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0P_RESERVED1_BITS 3 8395 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0P_RESERVED1_SHIFT 13 8396 8397 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ0P :: ADJ_EN [12:12] */ 8398 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0P_ADJ_EN_MASK 0x00001000 8399 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0P_ADJ_EN_ALIGN 0 8400 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0P_ADJ_EN_BITS 1 8401 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0P_ADJ_EN_SHIFT 12 8402 8403 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ0P :: reserved2 [11:08] */ 8404 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0P_RESERVED2_MASK 0x00000f00 8405 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0P_RESERVED2_ALIGN 0 8406 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0P_RESERVED2_BITS 4 8407 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0P_RESERVED2_SHIFT 8 8408 8409 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ0P :: VDL_STEP [07:00] */ 8410 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0P_VDL_STEP_MASK 0x000000ff 8411 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0P_VDL_STEP_ALIGN 0 8412 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0P_VDL_STEP_BITS 8 8413 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0P_VDL_STEP_SHIFT 0 8414 8415 8416 /**************************************************************************** 8417 * DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ0N 8418 */ 8419 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ0N :: BUSY [31:31] */ 8420 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0N_BUSY_MASK 0x80000000 8421 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0N_BUSY_ALIGN 0 8422 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0N_BUSY_BITS 1 8423 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0N_BUSY_SHIFT 31 8424 8425 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ0N :: reserved0 [30:17] */ 8426 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0N_RESERVED0_MASK 0x7ffe0000 8427 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0N_RESERVED0_ALIGN 0 8428 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0N_RESERVED0_BITS 14 8429 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0N_RESERVED0_SHIFT 17 8430 8431 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ0N :: FORCE [16:16] */ 8432 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0N_FORCE_MASK 0x00010000 8433 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0N_FORCE_ALIGN 0 8434 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0N_FORCE_BITS 1 8435 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0N_FORCE_SHIFT 16 8436 8437 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ0N :: reserved1 [15:13] */ 8438 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0N_RESERVED1_MASK 0x0000e000 8439 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0N_RESERVED1_ALIGN 0 8440 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0N_RESERVED1_BITS 3 8441 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0N_RESERVED1_SHIFT 13 8442 8443 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ0N :: ADJ_EN [12:12] */ 8444 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0N_ADJ_EN_MASK 0x00001000 8445 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0N_ADJ_EN_ALIGN 0 8446 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0N_ADJ_EN_BITS 1 8447 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0N_ADJ_EN_SHIFT 12 8448 8449 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ0N :: reserved2 [11:08] */ 8450 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0N_RESERVED2_MASK 0x00000f00 8451 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0N_RESERVED2_ALIGN 0 8452 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0N_RESERVED2_BITS 4 8453 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0N_RESERVED2_SHIFT 8 8454 8455 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ0N :: VDL_STEP [07:00] */ 8456 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0N_VDL_STEP_MASK 0x000000ff 8457 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0N_VDL_STEP_ALIGN 0 8458 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0N_VDL_STEP_BITS 8 8459 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0N_VDL_STEP_SHIFT 0 8460 8461 8462 /**************************************************************************** 8463 * DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ1P 8464 */ 8465 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ1P :: BUSY [31:31] */ 8466 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1P_BUSY_MASK 0x80000000 8467 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1P_BUSY_ALIGN 0 8468 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1P_BUSY_BITS 1 8469 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1P_BUSY_SHIFT 31 8470 8471 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ1P :: reserved0 [30:17] */ 8472 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1P_RESERVED0_MASK 0x7ffe0000 8473 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1P_RESERVED0_ALIGN 0 8474 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1P_RESERVED0_BITS 14 8475 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1P_RESERVED0_SHIFT 17 8476 8477 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ1P :: FORCE [16:16] */ 8478 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1P_FORCE_MASK 0x00010000 8479 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1P_FORCE_ALIGN 0 8480 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1P_FORCE_BITS 1 8481 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1P_FORCE_SHIFT 16 8482 8483 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ1P :: reserved1 [15:13] */ 8484 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1P_RESERVED1_MASK 0x0000e000 8485 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1P_RESERVED1_ALIGN 0 8486 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1P_RESERVED1_BITS 3 8487 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1P_RESERVED1_SHIFT 13 8488 8489 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ1P :: ADJ_EN [12:12] */ 8490 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1P_ADJ_EN_MASK 0x00001000 8491 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1P_ADJ_EN_ALIGN 0 8492 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1P_ADJ_EN_BITS 1 8493 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1P_ADJ_EN_SHIFT 12 8494 8495 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ1P :: reserved2 [11:08] */ 8496 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1P_RESERVED2_MASK 0x00000f00 8497 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1P_RESERVED2_ALIGN 0 8498 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1P_RESERVED2_BITS 4 8499 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1P_RESERVED2_SHIFT 8 8500 8501 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ1P :: VDL_STEP [07:00] */ 8502 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1P_VDL_STEP_MASK 0x000000ff 8503 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1P_VDL_STEP_ALIGN 0 8504 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1P_VDL_STEP_BITS 8 8505 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1P_VDL_STEP_SHIFT 0 8506 8507 8508 /**************************************************************************** 8509 * DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ1N 8510 */ 8511 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ1N :: BUSY [31:31] */ 8512 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1N_BUSY_MASK 0x80000000 8513 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1N_BUSY_ALIGN 0 8514 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1N_BUSY_BITS 1 8515 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1N_BUSY_SHIFT 31 8516 8517 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ1N :: reserved0 [30:17] */ 8518 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1N_RESERVED0_MASK 0x7ffe0000 8519 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1N_RESERVED0_ALIGN 0 8520 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1N_RESERVED0_BITS 14 8521 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1N_RESERVED0_SHIFT 17 8522 8523 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ1N :: FORCE [16:16] */ 8524 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1N_FORCE_MASK 0x00010000 8525 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1N_FORCE_ALIGN 0 8526 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1N_FORCE_BITS 1 8527 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1N_FORCE_SHIFT 16 8528 8529 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ1N :: reserved1 [15:13] */ 8530 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1N_RESERVED1_MASK 0x0000e000 8531 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1N_RESERVED1_ALIGN 0 8532 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1N_RESERVED1_BITS 3 8533 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1N_RESERVED1_SHIFT 13 8534 8535 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ1N :: ADJ_EN [12:12] */ 8536 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1N_ADJ_EN_MASK 0x00001000 8537 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1N_ADJ_EN_ALIGN 0 8538 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1N_ADJ_EN_BITS 1 8539 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1N_ADJ_EN_SHIFT 12 8540 8541 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ1N :: reserved2 [11:08] */ 8542 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1N_RESERVED2_MASK 0x00000f00 8543 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1N_RESERVED2_ALIGN 0 8544 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1N_RESERVED2_BITS 4 8545 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1N_RESERVED2_SHIFT 8 8546 8547 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ1N :: VDL_STEP [07:00] */ 8548 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1N_VDL_STEP_MASK 0x000000ff 8549 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1N_VDL_STEP_ALIGN 0 8550 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1N_VDL_STEP_BITS 8 8551 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1N_VDL_STEP_SHIFT 0 8552 8553 8554 /**************************************************************************** 8555 * DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ2P 8556 */ 8557 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ2P :: BUSY [31:31] */ 8558 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2P_BUSY_MASK 0x80000000 8559 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2P_BUSY_ALIGN 0 8560 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2P_BUSY_BITS 1 8561 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2P_BUSY_SHIFT 31 8562 8563 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ2P :: reserved0 [30:17] */ 8564 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2P_RESERVED0_MASK 0x7ffe0000 8565 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2P_RESERVED0_ALIGN 0 8566 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2P_RESERVED0_BITS 14 8567 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2P_RESERVED0_SHIFT 17 8568 8569 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ2P :: FORCE [16:16] */ 8570 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2P_FORCE_MASK 0x00010000 8571 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2P_FORCE_ALIGN 0 8572 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2P_FORCE_BITS 1 8573 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2P_FORCE_SHIFT 16 8574 8575 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ2P :: reserved1 [15:13] */ 8576 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2P_RESERVED1_MASK 0x0000e000 8577 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2P_RESERVED1_ALIGN 0 8578 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2P_RESERVED1_BITS 3 8579 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2P_RESERVED1_SHIFT 13 8580 8581 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ2P :: ADJ_EN [12:12] */ 8582 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2P_ADJ_EN_MASK 0x00001000 8583 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2P_ADJ_EN_ALIGN 0 8584 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2P_ADJ_EN_BITS 1 8585 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2P_ADJ_EN_SHIFT 12 8586 8587 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ2P :: reserved2 [11:08] */ 8588 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2P_RESERVED2_MASK 0x00000f00 8589 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2P_RESERVED2_ALIGN 0 8590 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2P_RESERVED2_BITS 4 8591 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2P_RESERVED2_SHIFT 8 8592 8593 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ2P :: VDL_STEP [07:00] */ 8594 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2P_VDL_STEP_MASK 0x000000ff 8595 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2P_VDL_STEP_ALIGN 0 8596 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2P_VDL_STEP_BITS 8 8597 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2P_VDL_STEP_SHIFT 0 8598 8599 8600 /**************************************************************************** 8601 * DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ2N 8602 */ 8603 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ2N :: BUSY [31:31] */ 8604 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2N_BUSY_MASK 0x80000000 8605 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2N_BUSY_ALIGN 0 8606 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2N_BUSY_BITS 1 8607 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2N_BUSY_SHIFT 31 8608 8609 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ2N :: reserved0 [30:17] */ 8610 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2N_RESERVED0_MASK 0x7ffe0000 8611 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2N_RESERVED0_ALIGN 0 8612 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2N_RESERVED0_BITS 14 8613 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2N_RESERVED0_SHIFT 17 8614 8615 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ2N :: FORCE [16:16] */ 8616 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2N_FORCE_MASK 0x00010000 8617 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2N_FORCE_ALIGN 0 8618 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2N_FORCE_BITS 1 8619 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2N_FORCE_SHIFT 16 8620 8621 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ2N :: reserved1 [15:13] */ 8622 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2N_RESERVED1_MASK 0x0000e000 8623 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2N_RESERVED1_ALIGN 0 8624 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2N_RESERVED1_BITS 3 8625 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2N_RESERVED1_SHIFT 13 8626 8627 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ2N :: ADJ_EN [12:12] */ 8628 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2N_ADJ_EN_MASK 0x00001000 8629 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2N_ADJ_EN_ALIGN 0 8630 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2N_ADJ_EN_BITS 1 8631 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2N_ADJ_EN_SHIFT 12 8632 8633 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ2N :: reserved2 [11:08] */ 8634 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2N_RESERVED2_MASK 0x00000f00 8635 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2N_RESERVED2_ALIGN 0 8636 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2N_RESERVED2_BITS 4 8637 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2N_RESERVED2_SHIFT 8 8638 8639 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ2N :: VDL_STEP [07:00] */ 8640 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2N_VDL_STEP_MASK 0x000000ff 8641 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2N_VDL_STEP_ALIGN 0 8642 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2N_VDL_STEP_BITS 8 8643 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2N_VDL_STEP_SHIFT 0 8644 8645 8646 /**************************************************************************** 8647 * DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ3P 8648 */ 8649 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ3P :: BUSY [31:31] */ 8650 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3P_BUSY_MASK 0x80000000 8651 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3P_BUSY_ALIGN 0 8652 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3P_BUSY_BITS 1 8653 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3P_BUSY_SHIFT 31 8654 8655 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ3P :: reserved0 [30:17] */ 8656 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3P_RESERVED0_MASK 0x7ffe0000 8657 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3P_RESERVED0_ALIGN 0 8658 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3P_RESERVED0_BITS 14 8659 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3P_RESERVED0_SHIFT 17 8660 8661 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ3P :: FORCE [16:16] */ 8662 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3P_FORCE_MASK 0x00010000 8663 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3P_FORCE_ALIGN 0 8664 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3P_FORCE_BITS 1 8665 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3P_FORCE_SHIFT 16 8666 8667 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ3P :: reserved1 [15:13] */ 8668 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3P_RESERVED1_MASK 0x0000e000 8669 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3P_RESERVED1_ALIGN 0 8670 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3P_RESERVED1_BITS 3 8671 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3P_RESERVED1_SHIFT 13 8672 8673 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ3P :: ADJ_EN [12:12] */ 8674 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3P_ADJ_EN_MASK 0x00001000 8675 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3P_ADJ_EN_ALIGN 0 8676 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3P_ADJ_EN_BITS 1 8677 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3P_ADJ_EN_SHIFT 12 8678 8679 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ3P :: reserved2 [11:08] */ 8680 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3P_RESERVED2_MASK 0x00000f00 8681 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3P_RESERVED2_ALIGN 0 8682 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3P_RESERVED2_BITS 4 8683 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3P_RESERVED2_SHIFT 8 8684 8685 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ3P :: VDL_STEP [07:00] */ 8686 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3P_VDL_STEP_MASK 0x000000ff 8687 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3P_VDL_STEP_ALIGN 0 8688 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3P_VDL_STEP_BITS 8 8689 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3P_VDL_STEP_SHIFT 0 8690 8691 8692 /**************************************************************************** 8693 * DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ3N 8694 */ 8695 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ3N :: BUSY [31:31] */ 8696 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3N_BUSY_MASK 0x80000000 8697 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3N_BUSY_ALIGN 0 8698 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3N_BUSY_BITS 1 8699 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3N_BUSY_SHIFT 31 8700 8701 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ3N :: reserved0 [30:17] */ 8702 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3N_RESERVED0_MASK 0x7ffe0000 8703 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3N_RESERVED0_ALIGN 0 8704 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3N_RESERVED0_BITS 14 8705 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3N_RESERVED0_SHIFT 17 8706 8707 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ3N :: FORCE [16:16] */ 8708 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3N_FORCE_MASK 0x00010000 8709 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3N_FORCE_ALIGN 0 8710 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3N_FORCE_BITS 1 8711 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3N_FORCE_SHIFT 16 8712 8713 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ3N :: reserved1 [15:13] */ 8714 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3N_RESERVED1_MASK 0x0000e000 8715 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3N_RESERVED1_ALIGN 0 8716 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3N_RESERVED1_BITS 3 8717 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3N_RESERVED1_SHIFT 13 8718 8719 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ3N :: ADJ_EN [12:12] */ 8720 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3N_ADJ_EN_MASK 0x00001000 8721 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3N_ADJ_EN_ALIGN 0 8722 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3N_ADJ_EN_BITS 1 8723 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3N_ADJ_EN_SHIFT 12 8724 8725 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ3N :: reserved2 [11:08] */ 8726 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3N_RESERVED2_MASK 0x00000f00 8727 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3N_RESERVED2_ALIGN 0 8728 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3N_RESERVED2_BITS 4 8729 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3N_RESERVED2_SHIFT 8 8730 8731 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ3N :: VDL_STEP [07:00] */ 8732 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3N_VDL_STEP_MASK 0x000000ff 8733 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3N_VDL_STEP_ALIGN 0 8734 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3N_VDL_STEP_BITS 8 8735 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3N_VDL_STEP_SHIFT 0 8736 8737 8738 /**************************************************************************** 8739 * DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ4P 8740 */ 8741 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ4P :: BUSY [31:31] */ 8742 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4P_BUSY_MASK 0x80000000 8743 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4P_BUSY_ALIGN 0 8744 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4P_BUSY_BITS 1 8745 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4P_BUSY_SHIFT 31 8746 8747 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ4P :: reserved0 [30:17] */ 8748 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4P_RESERVED0_MASK 0x7ffe0000 8749 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4P_RESERVED0_ALIGN 0 8750 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4P_RESERVED0_BITS 14 8751 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4P_RESERVED0_SHIFT 17 8752 8753 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ4P :: FORCE [16:16] */ 8754 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4P_FORCE_MASK 0x00010000 8755 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4P_FORCE_ALIGN 0 8756 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4P_FORCE_BITS 1 8757 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4P_FORCE_SHIFT 16 8758 8759 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ4P :: reserved1 [15:13] */ 8760 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4P_RESERVED1_MASK 0x0000e000 8761 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4P_RESERVED1_ALIGN 0 8762 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4P_RESERVED1_BITS 3 8763 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4P_RESERVED1_SHIFT 13 8764 8765 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ4P :: ADJ_EN [12:12] */ 8766 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4P_ADJ_EN_MASK 0x00001000 8767 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4P_ADJ_EN_ALIGN 0 8768 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4P_ADJ_EN_BITS 1 8769 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4P_ADJ_EN_SHIFT 12 8770 8771 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ4P :: reserved2 [11:08] */ 8772 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4P_RESERVED2_MASK 0x00000f00 8773 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4P_RESERVED2_ALIGN 0 8774 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4P_RESERVED2_BITS 4 8775 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4P_RESERVED2_SHIFT 8 8776 8777 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ4P :: VDL_STEP [07:00] */ 8778 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4P_VDL_STEP_MASK 0x000000ff 8779 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4P_VDL_STEP_ALIGN 0 8780 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4P_VDL_STEP_BITS 8 8781 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4P_VDL_STEP_SHIFT 0 8782 8783 8784 /**************************************************************************** 8785 * DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ4N 8786 */ 8787 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ4N :: BUSY [31:31] */ 8788 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4N_BUSY_MASK 0x80000000 8789 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4N_BUSY_ALIGN 0 8790 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4N_BUSY_BITS 1 8791 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4N_BUSY_SHIFT 31 8792 8793 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ4N :: reserved0 [30:17] */ 8794 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4N_RESERVED0_MASK 0x7ffe0000 8795 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4N_RESERVED0_ALIGN 0 8796 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4N_RESERVED0_BITS 14 8797 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4N_RESERVED0_SHIFT 17 8798 8799 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ4N :: FORCE [16:16] */ 8800 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4N_FORCE_MASK 0x00010000 8801 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4N_FORCE_ALIGN 0 8802 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4N_FORCE_BITS 1 8803 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4N_FORCE_SHIFT 16 8804 8805 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ4N :: reserved1 [15:13] */ 8806 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4N_RESERVED1_MASK 0x0000e000 8807 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4N_RESERVED1_ALIGN 0 8808 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4N_RESERVED1_BITS 3 8809 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4N_RESERVED1_SHIFT 13 8810 8811 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ4N :: ADJ_EN [12:12] */ 8812 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4N_ADJ_EN_MASK 0x00001000 8813 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4N_ADJ_EN_ALIGN 0 8814 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4N_ADJ_EN_BITS 1 8815 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4N_ADJ_EN_SHIFT 12 8816 8817 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ4N :: reserved2 [11:08] */ 8818 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4N_RESERVED2_MASK 0x00000f00 8819 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4N_RESERVED2_ALIGN 0 8820 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4N_RESERVED2_BITS 4 8821 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4N_RESERVED2_SHIFT 8 8822 8823 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ4N :: VDL_STEP [07:00] */ 8824 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4N_VDL_STEP_MASK 0x000000ff 8825 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4N_VDL_STEP_ALIGN 0 8826 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4N_VDL_STEP_BITS 8 8827 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4N_VDL_STEP_SHIFT 0 8828 8829 8830 /**************************************************************************** 8831 * DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ5P 8832 */ 8833 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ5P :: BUSY [31:31] */ 8834 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5P_BUSY_MASK 0x80000000 8835 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5P_BUSY_ALIGN 0 8836 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5P_BUSY_BITS 1 8837 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5P_BUSY_SHIFT 31 8838 8839 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ5P :: reserved0 [30:17] */ 8840 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5P_RESERVED0_MASK 0x7ffe0000 8841 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5P_RESERVED0_ALIGN 0 8842 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5P_RESERVED0_BITS 14 8843 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5P_RESERVED0_SHIFT 17 8844 8845 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ5P :: FORCE [16:16] */ 8846 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5P_FORCE_MASK 0x00010000 8847 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5P_FORCE_ALIGN 0 8848 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5P_FORCE_BITS 1 8849 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5P_FORCE_SHIFT 16 8850 8851 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ5P :: reserved1 [15:13] */ 8852 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5P_RESERVED1_MASK 0x0000e000 8853 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5P_RESERVED1_ALIGN 0 8854 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5P_RESERVED1_BITS 3 8855 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5P_RESERVED1_SHIFT 13 8856 8857 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ5P :: ADJ_EN [12:12] */ 8858 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5P_ADJ_EN_MASK 0x00001000 8859 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5P_ADJ_EN_ALIGN 0 8860 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5P_ADJ_EN_BITS 1 8861 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5P_ADJ_EN_SHIFT 12 8862 8863 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ5P :: reserved2 [11:08] */ 8864 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5P_RESERVED2_MASK 0x00000f00 8865 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5P_RESERVED2_ALIGN 0 8866 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5P_RESERVED2_BITS 4 8867 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5P_RESERVED2_SHIFT 8 8868 8869 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ5P :: VDL_STEP [07:00] */ 8870 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5P_VDL_STEP_MASK 0x000000ff 8871 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5P_VDL_STEP_ALIGN 0 8872 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5P_VDL_STEP_BITS 8 8873 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5P_VDL_STEP_SHIFT 0 8874 8875 8876 /**************************************************************************** 8877 * DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ5N 8878 */ 8879 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ5N :: BUSY [31:31] */ 8880 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5N_BUSY_MASK 0x80000000 8881 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5N_BUSY_ALIGN 0 8882 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5N_BUSY_BITS 1 8883 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5N_BUSY_SHIFT 31 8884 8885 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ5N :: reserved0 [30:17] */ 8886 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5N_RESERVED0_MASK 0x7ffe0000 8887 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5N_RESERVED0_ALIGN 0 8888 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5N_RESERVED0_BITS 14 8889 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5N_RESERVED0_SHIFT 17 8890 8891 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ5N :: FORCE [16:16] */ 8892 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5N_FORCE_MASK 0x00010000 8893 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5N_FORCE_ALIGN 0 8894 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5N_FORCE_BITS 1 8895 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5N_FORCE_SHIFT 16 8896 8897 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ5N :: reserved1 [15:13] */ 8898 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5N_RESERVED1_MASK 0x0000e000 8899 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5N_RESERVED1_ALIGN 0 8900 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5N_RESERVED1_BITS 3 8901 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5N_RESERVED1_SHIFT 13 8902 8903 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ5N :: ADJ_EN [12:12] */ 8904 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5N_ADJ_EN_MASK 0x00001000 8905 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5N_ADJ_EN_ALIGN 0 8906 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5N_ADJ_EN_BITS 1 8907 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5N_ADJ_EN_SHIFT 12 8908 8909 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ5N :: reserved2 [11:08] */ 8910 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5N_RESERVED2_MASK 0x00000f00 8911 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5N_RESERVED2_ALIGN 0 8912 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5N_RESERVED2_BITS 4 8913 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5N_RESERVED2_SHIFT 8 8914 8915 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ5N :: VDL_STEP [07:00] */ 8916 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5N_VDL_STEP_MASK 0x000000ff 8917 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5N_VDL_STEP_ALIGN 0 8918 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5N_VDL_STEP_BITS 8 8919 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5N_VDL_STEP_SHIFT 0 8920 8921 8922 /**************************************************************************** 8923 * DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ6P 8924 */ 8925 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ6P :: BUSY [31:31] */ 8926 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6P_BUSY_MASK 0x80000000 8927 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6P_BUSY_ALIGN 0 8928 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6P_BUSY_BITS 1 8929 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6P_BUSY_SHIFT 31 8930 8931 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ6P :: reserved0 [30:17] */ 8932 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6P_RESERVED0_MASK 0x7ffe0000 8933 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6P_RESERVED0_ALIGN 0 8934 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6P_RESERVED0_BITS 14 8935 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6P_RESERVED0_SHIFT 17 8936 8937 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ6P :: FORCE [16:16] */ 8938 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6P_FORCE_MASK 0x00010000 8939 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6P_FORCE_ALIGN 0 8940 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6P_FORCE_BITS 1 8941 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6P_FORCE_SHIFT 16 8942 8943 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ6P :: reserved1 [15:13] */ 8944 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6P_RESERVED1_MASK 0x0000e000 8945 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6P_RESERVED1_ALIGN 0 8946 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6P_RESERVED1_BITS 3 8947 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6P_RESERVED1_SHIFT 13 8948 8949 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ6P :: ADJ_EN [12:12] */ 8950 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6P_ADJ_EN_MASK 0x00001000 8951 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6P_ADJ_EN_ALIGN 0 8952 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6P_ADJ_EN_BITS 1 8953 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6P_ADJ_EN_SHIFT 12 8954 8955 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ6P :: reserved2 [11:08] */ 8956 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6P_RESERVED2_MASK 0x00000f00 8957 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6P_RESERVED2_ALIGN 0 8958 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6P_RESERVED2_BITS 4 8959 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6P_RESERVED2_SHIFT 8 8960 8961 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ6P :: VDL_STEP [07:00] */ 8962 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6P_VDL_STEP_MASK 0x000000ff 8963 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6P_VDL_STEP_ALIGN 0 8964 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6P_VDL_STEP_BITS 8 8965 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6P_VDL_STEP_SHIFT 0 8966 8967 8968 /**************************************************************************** 8969 * DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ6N 8970 */ 8971 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ6N :: BUSY [31:31] */ 8972 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6N_BUSY_MASK 0x80000000 8973 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6N_BUSY_ALIGN 0 8974 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6N_BUSY_BITS 1 8975 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6N_BUSY_SHIFT 31 8976 8977 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ6N :: reserved0 [30:17] */ 8978 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6N_RESERVED0_MASK 0x7ffe0000 8979 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6N_RESERVED0_ALIGN 0 8980 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6N_RESERVED0_BITS 14 8981 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6N_RESERVED0_SHIFT 17 8982 8983 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ6N :: FORCE [16:16] */ 8984 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6N_FORCE_MASK 0x00010000 8985 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6N_FORCE_ALIGN 0 8986 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6N_FORCE_BITS 1 8987 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6N_FORCE_SHIFT 16 8988 8989 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ6N :: reserved1 [15:13] */ 8990 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6N_RESERVED1_MASK 0x0000e000 8991 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6N_RESERVED1_ALIGN 0 8992 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6N_RESERVED1_BITS 3 8993 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6N_RESERVED1_SHIFT 13 8994 8995 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ6N :: ADJ_EN [12:12] */ 8996 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6N_ADJ_EN_MASK 0x00001000 8997 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6N_ADJ_EN_ALIGN 0 8998 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6N_ADJ_EN_BITS 1 8999 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6N_ADJ_EN_SHIFT 12 9000 9001 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ6N :: reserved2 [11:08] */ 9002 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6N_RESERVED2_MASK 0x00000f00 9003 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6N_RESERVED2_ALIGN 0 9004 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6N_RESERVED2_BITS 4 9005 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6N_RESERVED2_SHIFT 8 9006 9007 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ6N :: VDL_STEP [07:00] */ 9008 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6N_VDL_STEP_MASK 0x000000ff 9009 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6N_VDL_STEP_ALIGN 0 9010 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6N_VDL_STEP_BITS 8 9011 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6N_VDL_STEP_SHIFT 0 9012 9013 9014 /**************************************************************************** 9015 * DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ7P 9016 */ 9017 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ7P :: BUSY [31:31] */ 9018 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7P_BUSY_MASK 0x80000000 9019 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7P_BUSY_ALIGN 0 9020 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7P_BUSY_BITS 1 9021 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7P_BUSY_SHIFT 31 9022 9023 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ7P :: reserved0 [30:17] */ 9024 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7P_RESERVED0_MASK 0x7ffe0000 9025 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7P_RESERVED0_ALIGN 0 9026 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7P_RESERVED0_BITS 14 9027 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7P_RESERVED0_SHIFT 17 9028 9029 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ7P :: FORCE [16:16] */ 9030 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7P_FORCE_MASK 0x00010000 9031 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7P_FORCE_ALIGN 0 9032 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7P_FORCE_BITS 1 9033 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7P_FORCE_SHIFT 16 9034 9035 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ7P :: reserved1 [15:13] */ 9036 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7P_RESERVED1_MASK 0x0000e000 9037 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7P_RESERVED1_ALIGN 0 9038 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7P_RESERVED1_BITS 3 9039 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7P_RESERVED1_SHIFT 13 9040 9041 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ7P :: ADJ_EN [12:12] */ 9042 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7P_ADJ_EN_MASK 0x00001000 9043 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7P_ADJ_EN_ALIGN 0 9044 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7P_ADJ_EN_BITS 1 9045 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7P_ADJ_EN_SHIFT 12 9046 9047 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ7P :: reserved2 [11:08] */ 9048 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7P_RESERVED2_MASK 0x00000f00 9049 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7P_RESERVED2_ALIGN 0 9050 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7P_RESERVED2_BITS 4 9051 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7P_RESERVED2_SHIFT 8 9052 9053 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ7P :: VDL_STEP [07:00] */ 9054 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7P_VDL_STEP_MASK 0x000000ff 9055 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7P_VDL_STEP_ALIGN 0 9056 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7P_VDL_STEP_BITS 8 9057 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7P_VDL_STEP_SHIFT 0 9058 9059 9060 /**************************************************************************** 9061 * DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ7N 9062 */ 9063 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ7N :: BUSY [31:31] */ 9064 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7N_BUSY_MASK 0x80000000 9065 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7N_BUSY_ALIGN 0 9066 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7N_BUSY_BITS 1 9067 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7N_BUSY_SHIFT 31 9068 9069 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ7N :: reserved0 [30:17] */ 9070 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7N_RESERVED0_MASK 0x7ffe0000 9071 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7N_RESERVED0_ALIGN 0 9072 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7N_RESERVED0_BITS 14 9073 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7N_RESERVED0_SHIFT 17 9074 9075 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ7N :: FORCE [16:16] */ 9076 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7N_FORCE_MASK 0x00010000 9077 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7N_FORCE_ALIGN 0 9078 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7N_FORCE_BITS 1 9079 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7N_FORCE_SHIFT 16 9080 9081 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ7N :: reserved1 [15:13] */ 9082 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7N_RESERVED1_MASK 0x0000e000 9083 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7N_RESERVED1_ALIGN 0 9084 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7N_RESERVED1_BITS 3 9085 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7N_RESERVED1_SHIFT 13 9086 9087 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ7N :: ADJ_EN [12:12] */ 9088 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7N_ADJ_EN_MASK 0x00001000 9089 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7N_ADJ_EN_ALIGN 0 9090 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7N_ADJ_EN_BITS 1 9091 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7N_ADJ_EN_SHIFT 12 9092 9093 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ7N :: reserved2 [11:08] */ 9094 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7N_RESERVED2_MASK 0x00000f00 9095 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7N_RESERVED2_ALIGN 0 9096 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7N_RESERVED2_BITS 4 9097 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7N_RESERVED2_SHIFT 8 9098 9099 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ7N :: VDL_STEP [07:00] */ 9100 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7N_VDL_STEP_MASK 0x000000ff 9101 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7N_VDL_STEP_ALIGN 0 9102 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7N_VDL_STEP_BITS 8 9103 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7N_VDL_STEP_SHIFT 0 9104 9105 9106 /**************************************************************************** 9107 * DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DMP 9108 */ 9109 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DMP :: BUSY [31:31] */ 9110 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMP_BUSY_MASK 0x80000000 9111 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMP_BUSY_ALIGN 0 9112 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMP_BUSY_BITS 1 9113 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMP_BUSY_SHIFT 31 9114 9115 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DMP :: reserved0 [30:17] */ 9116 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMP_RESERVED0_MASK 0x7ffe0000 9117 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMP_RESERVED0_ALIGN 0 9118 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMP_RESERVED0_BITS 14 9119 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMP_RESERVED0_SHIFT 17 9120 9121 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DMP :: FORCE [16:16] */ 9122 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMP_FORCE_MASK 0x00010000 9123 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMP_FORCE_ALIGN 0 9124 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMP_FORCE_BITS 1 9125 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMP_FORCE_SHIFT 16 9126 9127 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DMP :: reserved1 [15:13] */ 9128 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMP_RESERVED1_MASK 0x0000e000 9129 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMP_RESERVED1_ALIGN 0 9130 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMP_RESERVED1_BITS 3 9131 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMP_RESERVED1_SHIFT 13 9132 9133 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DMP :: ADJ_EN [12:12] */ 9134 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMP_ADJ_EN_MASK 0x00001000 9135 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMP_ADJ_EN_ALIGN 0 9136 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMP_ADJ_EN_BITS 1 9137 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMP_ADJ_EN_SHIFT 12 9138 9139 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DMP :: reserved2 [11:08] */ 9140 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMP_RESERVED2_MASK 0x00000f00 9141 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMP_RESERVED2_ALIGN 0 9142 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMP_RESERVED2_BITS 4 9143 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMP_RESERVED2_SHIFT 8 9144 9145 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DMP :: VDL_STEP [07:00] */ 9146 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMP_VDL_STEP_MASK 0x000000ff 9147 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMP_VDL_STEP_ALIGN 0 9148 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMP_VDL_STEP_BITS 8 9149 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMP_VDL_STEP_SHIFT 0 9150 9151 9152 /**************************************************************************** 9153 * DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DMN 9154 */ 9155 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DMN :: BUSY [31:31] */ 9156 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMN_BUSY_MASK 0x80000000 9157 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMN_BUSY_ALIGN 0 9158 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMN_BUSY_BITS 1 9159 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMN_BUSY_SHIFT 31 9160 9161 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DMN :: reserved0 [30:17] */ 9162 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMN_RESERVED0_MASK 0x7ffe0000 9163 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMN_RESERVED0_ALIGN 0 9164 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMN_RESERVED0_BITS 14 9165 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMN_RESERVED0_SHIFT 17 9166 9167 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DMN :: FORCE [16:16] */ 9168 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMN_FORCE_MASK 0x00010000 9169 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMN_FORCE_ALIGN 0 9170 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMN_FORCE_BITS 1 9171 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMN_FORCE_SHIFT 16 9172 9173 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DMN :: reserved1 [15:13] */ 9174 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMN_RESERVED1_MASK 0x0000e000 9175 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMN_RESERVED1_ALIGN 0 9176 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMN_RESERVED1_BITS 3 9177 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMN_RESERVED1_SHIFT 13 9178 9179 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DMN :: ADJ_EN [12:12] */ 9180 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMN_ADJ_EN_MASK 0x00001000 9181 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMN_ADJ_EN_ALIGN 0 9182 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMN_ADJ_EN_BITS 1 9183 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMN_ADJ_EN_SHIFT 12 9184 9185 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DMN :: reserved2 [11:08] */ 9186 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMN_RESERVED2_MASK 0x00000f00 9187 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMN_RESERVED2_ALIGN 0 9188 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMN_RESERVED2_BITS 4 9189 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMN_RESERVED2_SHIFT 8 9190 9191 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DMN :: VDL_STEP [07:00] */ 9192 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMN_VDL_STEP_MASK 0x000000ff 9193 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMN_VDL_STEP_ALIGN 0 9194 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMN_VDL_STEP_BITS 8 9195 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMN_VDL_STEP_SHIFT 0 9196 9197 9198 /**************************************************************************** 9199 * DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_EN_CS0 9200 */ 9201 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_EN_CS0 :: BUSY [31:31] */ 9202 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0_BUSY_MASK 0x80000000 9203 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0_BUSY_ALIGN 0 9204 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0_BUSY_BITS 1 9205 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0_BUSY_SHIFT 31 9206 9207 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_EN_CS0 :: reserved0 [30:17] */ 9208 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0_RESERVED0_MASK 0x7ffe0000 9209 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0_RESERVED0_ALIGN 0 9210 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0_RESERVED0_BITS 14 9211 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0_RESERVED0_SHIFT 17 9212 9213 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_EN_CS0 :: FORCE [16:16] */ 9214 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0_FORCE_MASK 0x00010000 9215 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0_FORCE_ALIGN 0 9216 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0_FORCE_BITS 1 9217 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0_FORCE_SHIFT 16 9218 9219 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_EN_CS0 :: reserved1 [15:13] */ 9220 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0_RESERVED1_MASK 0x0000e000 9221 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0_RESERVED1_ALIGN 0 9222 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0_RESERVED1_BITS 3 9223 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0_RESERVED1_SHIFT 13 9224 9225 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_EN_CS0 :: ADJ_EN [12:12] */ 9226 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0_ADJ_EN_MASK 0x00001000 9227 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0_ADJ_EN_ALIGN 0 9228 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0_ADJ_EN_BITS 1 9229 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0_ADJ_EN_SHIFT 12 9230 9231 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_EN_CS0 :: reserved2 [11:08] */ 9232 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0_RESERVED2_MASK 0x00000f00 9233 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0_RESERVED2_ALIGN 0 9234 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0_RESERVED2_BITS 4 9235 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0_RESERVED2_SHIFT 8 9236 9237 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_EN_CS0 :: VDL_STEP [07:00] */ 9238 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0_VDL_STEP_MASK 0x000000ff 9239 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0_VDL_STEP_ALIGN 0 9240 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0_VDL_STEP_BITS 8 9241 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0_VDL_STEP_SHIFT 0 9242 9243 9244 /**************************************************************************** 9245 * DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_EN_CS1 9246 */ 9247 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_EN_CS1 :: BUSY [31:31] */ 9248 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1_BUSY_MASK 0x80000000 9249 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1_BUSY_ALIGN 0 9250 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1_BUSY_BITS 1 9251 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1_BUSY_SHIFT 31 9252 9253 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_EN_CS1 :: reserved0 [30:17] */ 9254 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1_RESERVED0_MASK 0x7ffe0000 9255 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1_RESERVED0_ALIGN 0 9256 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1_RESERVED0_BITS 14 9257 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1_RESERVED0_SHIFT 17 9258 9259 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_EN_CS1 :: FORCE [16:16] */ 9260 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1_FORCE_MASK 0x00010000 9261 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1_FORCE_ALIGN 0 9262 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1_FORCE_BITS 1 9263 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1_FORCE_SHIFT 16 9264 9265 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_EN_CS1 :: reserved1 [15:13] */ 9266 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1_RESERVED1_MASK 0x0000e000 9267 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1_RESERVED1_ALIGN 0 9268 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1_RESERVED1_BITS 3 9269 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1_RESERVED1_SHIFT 13 9270 9271 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_EN_CS1 :: ADJ_EN [12:12] */ 9272 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1_ADJ_EN_MASK 0x00001000 9273 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1_ADJ_EN_ALIGN 0 9274 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1_ADJ_EN_BITS 1 9275 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1_ADJ_EN_SHIFT 12 9276 9277 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_EN_CS1 :: reserved2 [11:08] */ 9278 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1_RESERVED2_MASK 0x00000f00 9279 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1_RESERVED2_ALIGN 0 9280 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1_RESERVED2_BITS 4 9281 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1_RESERVED2_SHIFT 8 9282 9283 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_EN_CS1 :: VDL_STEP [07:00] */ 9284 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1_VDL_STEP_MASK 0x000000ff 9285 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1_VDL_STEP_ALIGN 0 9286 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1_VDL_STEP_BITS 8 9287 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1_VDL_STEP_SHIFT 0 9288 9289 9290 /**************************************************************************** 9291 * DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CLK_CONTROL 9292 */ 9293 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CLK_CONTROL :: BUSY [31:31] */ 9294 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CLK_CONTROL_BUSY_MASK 0x80000000 9295 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CLK_CONTROL_BUSY_ALIGN 0 9296 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CLK_CONTROL_BUSY_BITS 1 9297 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CLK_CONTROL_BUSY_SHIFT 31 9298 9299 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CLK_CONTROL :: reserved0 [30:17] */ 9300 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CLK_CONTROL_RESERVED0_MASK 0x7ffe0000 9301 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CLK_CONTROL_RESERVED0_ALIGN 0 9302 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CLK_CONTROL_RESERVED0_BITS 14 9303 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CLK_CONTROL_RESERVED0_SHIFT 17 9304 9305 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CLK_CONTROL :: FORCE [16:16] */ 9306 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CLK_CONTROL_FORCE_MASK 0x00010000 9307 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CLK_CONTROL_FORCE_ALIGN 0 9308 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CLK_CONTROL_FORCE_BITS 1 9309 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CLK_CONTROL_FORCE_SHIFT 16 9310 9311 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CLK_CONTROL :: reserved1 [15:13] */ 9312 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CLK_CONTROL_RESERVED1_MASK 0x0000e000 9313 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CLK_CONTROL_RESERVED1_ALIGN 0 9314 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CLK_CONTROL_RESERVED1_BITS 3 9315 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CLK_CONTROL_RESERVED1_SHIFT 13 9316 9317 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CLK_CONTROL :: ADJ_EN [12:12] */ 9318 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CLK_CONTROL_ADJ_EN_MASK 0x00001000 9319 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CLK_CONTROL_ADJ_EN_ALIGN 0 9320 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CLK_CONTROL_ADJ_EN_BITS 1 9321 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CLK_CONTROL_ADJ_EN_SHIFT 12 9322 9323 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CLK_CONTROL :: reserved2 [11:09] */ 9324 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CLK_CONTROL_RESERVED2_MASK 0x00000e00 9325 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CLK_CONTROL_RESERVED2_ALIGN 0 9326 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CLK_CONTROL_RESERVED2_BITS 3 9327 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CLK_CONTROL_RESERVED2_SHIFT 9 9328 9329 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_CLK_CONTROL :: VDL_STEP [08:00] */ 9330 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CLK_CONTROL_VDL_STEP_MASK 0x000001ff 9331 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CLK_CONTROL_VDL_STEP_ALIGN 0 9332 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CLK_CONTROL_VDL_STEP_BITS 9 9333 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_CLK_CONTROL_VDL_STEP_SHIFT 0 9334 9335 9336 /**************************************************************************** 9337 * DDR34_F0_PHY_BYTE_LANE_1 :: VDL_LDE_CONTROL 9338 */ 9339 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_LDE_CONTROL :: BUSY [31:31] */ 9340 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_LDE_CONTROL_BUSY_MASK 0x80000000 9341 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_LDE_CONTROL_BUSY_ALIGN 0 9342 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_LDE_CONTROL_BUSY_BITS 1 9343 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_LDE_CONTROL_BUSY_SHIFT 31 9344 9345 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_LDE_CONTROL :: reserved0 [30:17] */ 9346 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_LDE_CONTROL_RESERVED0_MASK 0x7ffe0000 9347 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_LDE_CONTROL_RESERVED0_ALIGN 0 9348 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_LDE_CONTROL_RESERVED0_BITS 14 9349 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_LDE_CONTROL_RESERVED0_SHIFT 17 9350 9351 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_LDE_CONTROL :: FORCE [16:16] */ 9352 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_LDE_CONTROL_FORCE_MASK 0x00010000 9353 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_LDE_CONTROL_FORCE_ALIGN 0 9354 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_LDE_CONTROL_FORCE_BITS 1 9355 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_LDE_CONTROL_FORCE_SHIFT 16 9356 9357 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_LDE_CONTROL :: reserved1 [15:13] */ 9358 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_LDE_CONTROL_RESERVED1_MASK 0x0000e000 9359 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_LDE_CONTROL_RESERVED1_ALIGN 0 9360 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_LDE_CONTROL_RESERVED1_BITS 3 9361 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_LDE_CONTROL_RESERVED1_SHIFT 13 9362 9363 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_LDE_CONTROL :: ADJ_EN [12:12] */ 9364 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_LDE_CONTROL_ADJ_EN_MASK 0x00001000 9365 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_LDE_CONTROL_ADJ_EN_ALIGN 0 9366 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_LDE_CONTROL_ADJ_EN_BITS 1 9367 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_LDE_CONTROL_ADJ_EN_SHIFT 12 9368 9369 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_LDE_CONTROL :: reserved2 [11:09] */ 9370 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_LDE_CONTROL_RESERVED2_MASK 0x00000e00 9371 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_LDE_CONTROL_RESERVED2_ALIGN 0 9372 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_LDE_CONTROL_RESERVED2_BITS 3 9373 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_LDE_CONTROL_RESERVED2_SHIFT 9 9374 9375 /* DDR34_F0_PHY_BYTE_LANE_1 :: VDL_LDE_CONTROL :: VDL_STEP [08:00] */ 9376 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_LDE_CONTROL_VDL_STEP_MASK 0x000001ff 9377 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_LDE_CONTROL_VDL_STEP_ALIGN 0 9378 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_LDE_CONTROL_VDL_STEP_BITS 9 9379 #define DDR34_F0_PHY_BYTE_LANE_1_VDL_LDE_CONTROL_VDL_STEP_SHIFT 0 9380 9381 9382 /**************************************************************************** 9383 * DDR34_F0_PHY_BYTE_LANE_1 :: RD_EN_DLY_CYC 9384 */ 9385 /* DDR34_F0_PHY_BYTE_LANE_1 :: RD_EN_DLY_CYC :: BUSY [31:31] */ 9386 #define DDR34_F0_PHY_BYTE_LANE_1_RD_EN_DLY_CYC_BUSY_MASK 0x80000000 9387 #define DDR34_F0_PHY_BYTE_LANE_1_RD_EN_DLY_CYC_BUSY_ALIGN 0 9388 #define DDR34_F0_PHY_BYTE_LANE_1_RD_EN_DLY_CYC_BUSY_BITS 1 9389 #define DDR34_F0_PHY_BYTE_LANE_1_RD_EN_DLY_CYC_BUSY_SHIFT 31 9390 9391 /* DDR34_F0_PHY_BYTE_LANE_1 :: RD_EN_DLY_CYC :: reserved0 [30:17] */ 9392 #define DDR34_F0_PHY_BYTE_LANE_1_RD_EN_DLY_CYC_RESERVED0_MASK 0x7ffe0000 9393 #define DDR34_F0_PHY_BYTE_LANE_1_RD_EN_DLY_CYC_RESERVED0_ALIGN 0 9394 #define DDR34_F0_PHY_BYTE_LANE_1_RD_EN_DLY_CYC_RESERVED0_BITS 14 9395 #define DDR34_F0_PHY_BYTE_LANE_1_RD_EN_DLY_CYC_RESERVED0_SHIFT 17 9396 9397 /* DDR34_F0_PHY_BYTE_LANE_1 :: RD_EN_DLY_CYC :: FORCE [16:16] */ 9398 #define DDR34_F0_PHY_BYTE_LANE_1_RD_EN_DLY_CYC_FORCE_MASK 0x00010000 9399 #define DDR34_F0_PHY_BYTE_LANE_1_RD_EN_DLY_CYC_FORCE_ALIGN 0 9400 #define DDR34_F0_PHY_BYTE_LANE_1_RD_EN_DLY_CYC_FORCE_BITS 1 9401 #define DDR34_F0_PHY_BYTE_LANE_1_RD_EN_DLY_CYC_FORCE_SHIFT 16 9402 9403 /* DDR34_F0_PHY_BYTE_LANE_1 :: RD_EN_DLY_CYC :: reserved1 [15:09] */ 9404 #define DDR34_F0_PHY_BYTE_LANE_1_RD_EN_DLY_CYC_RESERVED1_MASK 0x0000fe00 9405 #define DDR34_F0_PHY_BYTE_LANE_1_RD_EN_DLY_CYC_RESERVED1_ALIGN 0 9406 #define DDR34_F0_PHY_BYTE_LANE_1_RD_EN_DLY_CYC_RESERVED1_BITS 7 9407 #define DDR34_F0_PHY_BYTE_LANE_1_RD_EN_DLY_CYC_RESERVED1_SHIFT 9 9408 9409 /* DDR34_F0_PHY_BYTE_LANE_1 :: RD_EN_DLY_CYC :: ENABLE_CS1 [08:08] */ 9410 #define DDR34_F0_PHY_BYTE_LANE_1_RD_EN_DLY_CYC_ENABLE_CS1_MASK 0x00000100 9411 #define DDR34_F0_PHY_BYTE_LANE_1_RD_EN_DLY_CYC_ENABLE_CS1_ALIGN 0 9412 #define DDR34_F0_PHY_BYTE_LANE_1_RD_EN_DLY_CYC_ENABLE_CS1_BITS 1 9413 #define DDR34_F0_PHY_BYTE_LANE_1_RD_EN_DLY_CYC_ENABLE_CS1_SHIFT 8 9414 9415 /* DDR34_F0_PHY_BYTE_LANE_1 :: RD_EN_DLY_CYC :: CS1_CYCLES [07:04] */ 9416 #define DDR34_F0_PHY_BYTE_LANE_1_RD_EN_DLY_CYC_CS1_CYCLES_MASK 0x000000f0 9417 #define DDR34_F0_PHY_BYTE_LANE_1_RD_EN_DLY_CYC_CS1_CYCLES_ALIGN 0 9418 #define DDR34_F0_PHY_BYTE_LANE_1_RD_EN_DLY_CYC_CS1_CYCLES_BITS 4 9419 #define DDR34_F0_PHY_BYTE_LANE_1_RD_EN_DLY_CYC_CS1_CYCLES_SHIFT 4 9420 9421 /* DDR34_F0_PHY_BYTE_LANE_1 :: RD_EN_DLY_CYC :: CS0_CYCLES [03:00] */ 9422 #define DDR34_F0_PHY_BYTE_LANE_1_RD_EN_DLY_CYC_CS0_CYCLES_MASK 0x0000000f 9423 #define DDR34_F0_PHY_BYTE_LANE_1_RD_EN_DLY_CYC_CS0_CYCLES_ALIGN 0 9424 #define DDR34_F0_PHY_BYTE_LANE_1_RD_EN_DLY_CYC_CS0_CYCLES_BITS 4 9425 #define DDR34_F0_PHY_BYTE_LANE_1_RD_EN_DLY_CYC_CS0_CYCLES_SHIFT 0 9426 9427 9428 /**************************************************************************** 9429 * DDR34_F0_PHY_BYTE_LANE_1 :: WR_CHAN_DLY_CYC 9430 */ 9431 /* DDR34_F0_PHY_BYTE_LANE_1 :: WR_CHAN_DLY_CYC :: BUSY [31:31] */ 9432 #define DDR34_F0_PHY_BYTE_LANE_1_WR_CHAN_DLY_CYC_BUSY_MASK 0x80000000 9433 #define DDR34_F0_PHY_BYTE_LANE_1_WR_CHAN_DLY_CYC_BUSY_ALIGN 0 9434 #define DDR34_F0_PHY_BYTE_LANE_1_WR_CHAN_DLY_CYC_BUSY_BITS 1 9435 #define DDR34_F0_PHY_BYTE_LANE_1_WR_CHAN_DLY_CYC_BUSY_SHIFT 31 9436 9437 /* DDR34_F0_PHY_BYTE_LANE_1 :: WR_CHAN_DLY_CYC :: reserved0 [30:17] */ 9438 #define DDR34_F0_PHY_BYTE_LANE_1_WR_CHAN_DLY_CYC_RESERVED0_MASK 0x7ffe0000 9439 #define DDR34_F0_PHY_BYTE_LANE_1_WR_CHAN_DLY_CYC_RESERVED0_ALIGN 0 9440 #define DDR34_F0_PHY_BYTE_LANE_1_WR_CHAN_DLY_CYC_RESERVED0_BITS 14 9441 #define DDR34_F0_PHY_BYTE_LANE_1_WR_CHAN_DLY_CYC_RESERVED0_SHIFT 17 9442 9443 /* DDR34_F0_PHY_BYTE_LANE_1 :: WR_CHAN_DLY_CYC :: FORCE [16:16] */ 9444 #define DDR34_F0_PHY_BYTE_LANE_1_WR_CHAN_DLY_CYC_FORCE_MASK 0x00010000 9445 #define DDR34_F0_PHY_BYTE_LANE_1_WR_CHAN_DLY_CYC_FORCE_ALIGN 0 9446 #define DDR34_F0_PHY_BYTE_LANE_1_WR_CHAN_DLY_CYC_FORCE_BITS 1 9447 #define DDR34_F0_PHY_BYTE_LANE_1_WR_CHAN_DLY_CYC_FORCE_SHIFT 16 9448 9449 /* DDR34_F0_PHY_BYTE_LANE_1 :: WR_CHAN_DLY_CYC :: reserved1 [15:08] */ 9450 #define DDR34_F0_PHY_BYTE_LANE_1_WR_CHAN_DLY_CYC_RESERVED1_MASK 0x0000ff00 9451 #define DDR34_F0_PHY_BYTE_LANE_1_WR_CHAN_DLY_CYC_RESERVED1_ALIGN 0 9452 #define DDR34_F0_PHY_BYTE_LANE_1_WR_CHAN_DLY_CYC_RESERVED1_BITS 8 9453 #define DDR34_F0_PHY_BYTE_LANE_1_WR_CHAN_DLY_CYC_RESERVED1_SHIFT 8 9454 9455 /* DDR34_F0_PHY_BYTE_LANE_1 :: WR_CHAN_DLY_CYC :: DQ_CYCLES [07:04] */ 9456 #define DDR34_F0_PHY_BYTE_LANE_1_WR_CHAN_DLY_CYC_DQ_CYCLES_MASK 0x000000f0 9457 #define DDR34_F0_PHY_BYTE_LANE_1_WR_CHAN_DLY_CYC_DQ_CYCLES_ALIGN 0 9458 #define DDR34_F0_PHY_BYTE_LANE_1_WR_CHAN_DLY_CYC_DQ_CYCLES_BITS 4 9459 #define DDR34_F0_PHY_BYTE_LANE_1_WR_CHAN_DLY_CYC_DQ_CYCLES_SHIFT 4 9460 9461 /* DDR34_F0_PHY_BYTE_LANE_1 :: WR_CHAN_DLY_CYC :: reserved2 [03:03] */ 9462 #define DDR34_F0_PHY_BYTE_LANE_1_WR_CHAN_DLY_CYC_RESERVED2_MASK 0x00000008 9463 #define DDR34_F0_PHY_BYTE_LANE_1_WR_CHAN_DLY_CYC_RESERVED2_ALIGN 0 9464 #define DDR34_F0_PHY_BYTE_LANE_1_WR_CHAN_DLY_CYC_RESERVED2_BITS 1 9465 #define DDR34_F0_PHY_BYTE_LANE_1_WR_CHAN_DLY_CYC_RESERVED2_SHIFT 3 9466 9467 /* DDR34_F0_PHY_BYTE_LANE_1 :: WR_CHAN_DLY_CYC :: CYCLES [02:00] */ 9468 #define DDR34_F0_PHY_BYTE_LANE_1_WR_CHAN_DLY_CYC_CYCLES_MASK 0x00000007 9469 #define DDR34_F0_PHY_BYTE_LANE_1_WR_CHAN_DLY_CYC_CYCLES_ALIGN 0 9470 #define DDR34_F0_PHY_BYTE_LANE_1_WR_CHAN_DLY_CYC_CYCLES_BITS 3 9471 #define DDR34_F0_PHY_BYTE_LANE_1_WR_CHAN_DLY_CYC_CYCLES_SHIFT 0 9472 9473 9474 /**************************************************************************** 9475 * DDR34_F0_PHY_BYTE_LANE_1 :: READ_CONTROL 9476 */ 9477 /* DDR34_F0_PHY_BYTE_LANE_1 :: READ_CONTROL :: reserved0 [31:05] */ 9478 #define DDR34_F0_PHY_BYTE_LANE_1_READ_CONTROL_RESERVED0_MASK 0xffffffe0 9479 #define DDR34_F0_PHY_BYTE_LANE_1_READ_CONTROL_RESERVED0_ALIGN 0 9480 #define DDR34_F0_PHY_BYTE_LANE_1_READ_CONTROL_RESERVED0_BITS 27 9481 #define DDR34_F0_PHY_BYTE_LANE_1_READ_CONTROL_RESERVED0_SHIFT 5 9482 9483 /* DDR34_F0_PHY_BYTE_LANE_1 :: READ_CONTROL :: MODE [04:04] */ 9484 #define DDR34_F0_PHY_BYTE_LANE_1_READ_CONTROL_MODE_MASK 0x00000010 9485 #define DDR34_F0_PHY_BYTE_LANE_1_READ_CONTROL_MODE_ALIGN 0 9486 #define DDR34_F0_PHY_BYTE_LANE_1_READ_CONTROL_MODE_BITS 1 9487 #define DDR34_F0_PHY_BYTE_LANE_1_READ_CONTROL_MODE_SHIFT 4 9488 9489 /* DDR34_F0_PHY_BYTE_LANE_1 :: READ_CONTROL :: RD_EN_MODE [03:03] */ 9490 #define DDR34_F0_PHY_BYTE_LANE_1_READ_CONTROL_RD_EN_MODE_MASK 0x00000008 9491 #define DDR34_F0_PHY_BYTE_LANE_1_READ_CONTROL_RD_EN_MODE_ALIGN 0 9492 #define DDR34_F0_PHY_BYTE_LANE_1_READ_CONTROL_RD_EN_MODE_BITS 1 9493 #define DDR34_F0_PHY_BYTE_LANE_1_READ_CONTROL_RD_EN_MODE_SHIFT 3 9494 9495 /* DDR34_F0_PHY_BYTE_LANE_1 :: READ_CONTROL :: RD_DATA_DLY [02:00] */ 9496 #define DDR34_F0_PHY_BYTE_LANE_1_READ_CONTROL_RD_DATA_DLY_MASK 0x00000007 9497 #define DDR34_F0_PHY_BYTE_LANE_1_READ_CONTROL_RD_DATA_DLY_ALIGN 0 9498 #define DDR34_F0_PHY_BYTE_LANE_1_READ_CONTROL_RD_DATA_DLY_BITS 3 9499 #define DDR34_F0_PHY_BYTE_LANE_1_READ_CONTROL_RD_DATA_DLY_SHIFT 0 9500 9501 9502 /**************************************************************************** 9503 * DDR34_F0_PHY_BYTE_LANE_1 :: READ_FIFO_ADDR 9504 */ 9505 /* DDR34_F0_PHY_BYTE_LANE_1 :: READ_FIFO_ADDR :: reserved0 [31:03] */ 9506 #define DDR34_F0_PHY_BYTE_LANE_1_READ_FIFO_ADDR_RESERVED0_MASK 0xfffffff8 9507 #define DDR34_F0_PHY_BYTE_LANE_1_READ_FIFO_ADDR_RESERVED0_ALIGN 0 9508 #define DDR34_F0_PHY_BYTE_LANE_1_READ_FIFO_ADDR_RESERVED0_BITS 29 9509 #define DDR34_F0_PHY_BYTE_LANE_1_READ_FIFO_ADDR_RESERVED0_SHIFT 3 9510 9511 /* DDR34_F0_PHY_BYTE_LANE_1 :: READ_FIFO_ADDR :: ADDR [02:00] */ 9512 #define DDR34_F0_PHY_BYTE_LANE_1_READ_FIFO_ADDR_ADDR_MASK 0x00000007 9513 #define DDR34_F0_PHY_BYTE_LANE_1_READ_FIFO_ADDR_ADDR_ALIGN 0 9514 #define DDR34_F0_PHY_BYTE_LANE_1_READ_FIFO_ADDR_ADDR_BITS 3 9515 #define DDR34_F0_PHY_BYTE_LANE_1_READ_FIFO_ADDR_ADDR_SHIFT 0 9516 9517 9518 /**************************************************************************** 9519 * DDR34_F0_PHY_BYTE_LANE_1 :: READ_FIFO_DATA 9520 */ 9521 /* DDR34_F0_PHY_BYTE_LANE_1 :: READ_FIFO_DATA :: DATA [31:00] */ 9522 #define DDR34_F0_PHY_BYTE_LANE_1_READ_FIFO_DATA_DATA_MASK 0xffffffff 9523 #define DDR34_F0_PHY_BYTE_LANE_1_READ_FIFO_DATA_DATA_ALIGN 0 9524 #define DDR34_F0_PHY_BYTE_LANE_1_READ_FIFO_DATA_DATA_BITS 32 9525 #define DDR34_F0_PHY_BYTE_LANE_1_READ_FIFO_DATA_DATA_SHIFT 0 9526 9527 9528 /**************************************************************************** 9529 * DDR34_F0_PHY_BYTE_LANE_1 :: READ_FIFO_DM_DBI 9530 */ 9531 /* DDR34_F0_PHY_BYTE_LANE_1 :: READ_FIFO_DM_DBI :: reserved0 [31:04] */ 9532 #define DDR34_F0_PHY_BYTE_LANE_1_READ_FIFO_DM_DBI_RESERVED0_MASK 0xfffffff0 9533 #define DDR34_F0_PHY_BYTE_LANE_1_READ_FIFO_DM_DBI_RESERVED0_ALIGN 0 9534 #define DDR34_F0_PHY_BYTE_LANE_1_READ_FIFO_DM_DBI_RESERVED0_BITS 28 9535 #define DDR34_F0_PHY_BYTE_LANE_1_READ_FIFO_DM_DBI_RESERVED0_SHIFT 4 9536 9537 /* DDR34_F0_PHY_BYTE_LANE_1 :: READ_FIFO_DM_DBI :: DM_DBI [03:00] */ 9538 #define DDR34_F0_PHY_BYTE_LANE_1_READ_FIFO_DM_DBI_DM_DBI_MASK 0x0000000f 9539 #define DDR34_F0_PHY_BYTE_LANE_1_READ_FIFO_DM_DBI_DM_DBI_ALIGN 0 9540 #define DDR34_F0_PHY_BYTE_LANE_1_READ_FIFO_DM_DBI_DM_DBI_BITS 4 9541 #define DDR34_F0_PHY_BYTE_LANE_1_READ_FIFO_DM_DBI_DM_DBI_SHIFT 0 9542 9543 9544 /**************************************************************************** 9545 * DDR34_F0_PHY_BYTE_LANE_1 :: READ_FIFO_STATUS 9546 */ 9547 /* DDR34_F0_PHY_BYTE_LANE_1 :: READ_FIFO_STATUS :: reserved0 [31:02] */ 9548 #define DDR34_F0_PHY_BYTE_LANE_1_READ_FIFO_STATUS_RESERVED0_MASK 0xfffffffc 9549 #define DDR34_F0_PHY_BYTE_LANE_1_READ_FIFO_STATUS_RESERVED0_ALIGN 0 9550 #define DDR34_F0_PHY_BYTE_LANE_1_READ_FIFO_STATUS_RESERVED0_BITS 30 9551 #define DDR34_F0_PHY_BYTE_LANE_1_READ_FIFO_STATUS_RESERVED0_SHIFT 2 9552 9553 /* DDR34_F0_PHY_BYTE_LANE_1 :: READ_FIFO_STATUS :: OVERFLOW [01:01] */ 9554 #define DDR34_F0_PHY_BYTE_LANE_1_READ_FIFO_STATUS_OVERFLOW_MASK 0x00000002 9555 #define DDR34_F0_PHY_BYTE_LANE_1_READ_FIFO_STATUS_OVERFLOW_ALIGN 0 9556 #define DDR34_F0_PHY_BYTE_LANE_1_READ_FIFO_STATUS_OVERFLOW_BITS 1 9557 #define DDR34_F0_PHY_BYTE_LANE_1_READ_FIFO_STATUS_OVERFLOW_SHIFT 1 9558 9559 /* DDR34_F0_PHY_BYTE_LANE_1 :: READ_FIFO_STATUS :: UNDERFLOW [00:00] */ 9560 #define DDR34_F0_PHY_BYTE_LANE_1_READ_FIFO_STATUS_UNDERFLOW_MASK 0x00000001 9561 #define DDR34_F0_PHY_BYTE_LANE_1_READ_FIFO_STATUS_UNDERFLOW_ALIGN 0 9562 #define DDR34_F0_PHY_BYTE_LANE_1_READ_FIFO_STATUS_UNDERFLOW_BITS 1 9563 #define DDR34_F0_PHY_BYTE_LANE_1_READ_FIFO_STATUS_UNDERFLOW_SHIFT 0 9564 9565 9566 /**************************************************************************** 9567 * DDR34_F0_PHY_BYTE_LANE_1 :: READ_FIFO_CLEAR 9568 */ 9569 /* DDR34_F0_PHY_BYTE_LANE_1 :: READ_FIFO_CLEAR :: reserved0 [31:01] */ 9570 #define DDR34_F0_PHY_BYTE_LANE_1_READ_FIFO_CLEAR_RESERVED0_MASK 0xfffffffe 9571 #define DDR34_F0_PHY_BYTE_LANE_1_READ_FIFO_CLEAR_RESERVED0_ALIGN 0 9572 #define DDR34_F0_PHY_BYTE_LANE_1_READ_FIFO_CLEAR_RESERVED0_BITS 31 9573 #define DDR34_F0_PHY_BYTE_LANE_1_READ_FIFO_CLEAR_RESERVED0_SHIFT 1 9574 9575 /* DDR34_F0_PHY_BYTE_LANE_1 :: READ_FIFO_CLEAR :: CLEAR [00:00] */ 9576 #define DDR34_F0_PHY_BYTE_LANE_1_READ_FIFO_CLEAR_CLEAR_MASK 0x00000001 9577 #define DDR34_F0_PHY_BYTE_LANE_1_READ_FIFO_CLEAR_CLEAR_ALIGN 0 9578 #define DDR34_F0_PHY_BYTE_LANE_1_READ_FIFO_CLEAR_CLEAR_BITS 1 9579 #define DDR34_F0_PHY_BYTE_LANE_1_READ_FIFO_CLEAR_CLEAR_SHIFT 0 9580 9581 9582 /**************************************************************************** 9583 * DDR34_F0_PHY_BYTE_LANE_1 :: IDLE_PAD_CONTROL 9584 */ 9585 /* DDR34_F0_PHY_BYTE_LANE_1 :: IDLE_PAD_CONTROL :: IDLE [31:31] */ 9586 #define DDR34_F0_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_IDLE_MASK 0x80000000 9587 #define DDR34_F0_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_IDLE_ALIGN 0 9588 #define DDR34_F0_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_IDLE_BITS 1 9589 #define DDR34_F0_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_IDLE_SHIFT 31 9590 9591 /* DDR34_F0_PHY_BYTE_LANE_1 :: IDLE_PAD_CONTROL :: reserved0 [30:20] */ 9592 #define DDR34_F0_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_RESERVED0_MASK 0x7ff00000 9593 #define DDR34_F0_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_RESERVED0_ALIGN 0 9594 #define DDR34_F0_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_RESERVED0_BITS 11 9595 #define DDR34_F0_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_RESERVED0_SHIFT 20 9596 9597 /* DDR34_F0_PHY_BYTE_LANE_1 :: IDLE_PAD_CONTROL :: AUTO_DQ_RXENB_MODE [19:18] */ 9598 #define DDR34_F0_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_AUTO_DQ_RXENB_MODE_MASK 0x000c0000 9599 #define DDR34_F0_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_AUTO_DQ_RXENB_MODE_ALIGN 0 9600 #define DDR34_F0_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_AUTO_DQ_RXENB_MODE_BITS 2 9601 #define DDR34_F0_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_AUTO_DQ_RXENB_MODE_SHIFT 18 9602 9603 /* DDR34_F0_PHY_BYTE_LANE_1 :: IDLE_PAD_CONTROL :: AUTO_DQ_IDDQ_MODE [17:16] */ 9604 #define DDR34_F0_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_AUTO_DQ_IDDQ_MODE_MASK 0x00030000 9605 #define DDR34_F0_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_AUTO_DQ_IDDQ_MODE_ALIGN 0 9606 #define DDR34_F0_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_AUTO_DQ_IDDQ_MODE_BITS 2 9607 #define DDR34_F0_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_AUTO_DQ_IDDQ_MODE_SHIFT 16 9608 9609 /* DDR34_F0_PHY_BYTE_LANE_1 :: IDLE_PAD_CONTROL :: IO_IDLE_ENABLE [15:04] */ 9610 #define DDR34_F0_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_IO_IDLE_ENABLE_MASK 0x0000fff0 9611 #define DDR34_F0_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_IO_IDLE_ENABLE_ALIGN 0 9612 #define DDR34_F0_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_IO_IDLE_ENABLE_BITS 12 9613 #define DDR34_F0_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_IO_IDLE_ENABLE_SHIFT 4 9614 9615 /* DDR34_F0_PHY_BYTE_LANE_1 :: IDLE_PAD_CONTROL :: RXENB [03:03] */ 9616 #define DDR34_F0_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_RXENB_MASK 0x00000008 9617 #define DDR34_F0_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_RXENB_ALIGN 0 9618 #define DDR34_F0_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_RXENB_BITS 1 9619 #define DDR34_F0_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_RXENB_SHIFT 3 9620 9621 /* DDR34_F0_PHY_BYTE_LANE_1 :: IDLE_PAD_CONTROL :: IDDQ [02:02] */ 9622 #define DDR34_F0_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_IDDQ_MASK 0x00000004 9623 #define DDR34_F0_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_IDDQ_ALIGN 0 9624 #define DDR34_F0_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_IDDQ_BITS 1 9625 #define DDR34_F0_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_IDDQ_SHIFT 2 9626 9627 /* DDR34_F0_PHY_BYTE_LANE_1 :: IDLE_PAD_CONTROL :: DOUT_N [01:01] */ 9628 #define DDR34_F0_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_DOUT_N_MASK 0x00000002 9629 #define DDR34_F0_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_DOUT_N_ALIGN 0 9630 #define DDR34_F0_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_DOUT_N_BITS 1 9631 #define DDR34_F0_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_DOUT_N_SHIFT 1 9632 9633 /* DDR34_F0_PHY_BYTE_LANE_1 :: IDLE_PAD_CONTROL :: DOUT_P [00:00] */ 9634 #define DDR34_F0_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_DOUT_P_MASK 0x00000001 9635 #define DDR34_F0_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_DOUT_P_ALIGN 0 9636 #define DDR34_F0_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_DOUT_P_BITS 1 9637 #define DDR34_F0_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_DOUT_P_SHIFT 0 9638 9639 9640 /**************************************************************************** 9641 * DDR34_F0_PHY_BYTE_LANE_1 :: DRIVE_PAD_CTL 9642 */ 9643 /* DDR34_F0_PHY_BYTE_LANE_1 :: DRIVE_PAD_CTL :: reserved0 [31:20] */ 9644 #define DDR34_F0_PHY_BYTE_LANE_1_DRIVE_PAD_CTL_RESERVED0_MASK 0xfff00000 9645 #define DDR34_F0_PHY_BYTE_LANE_1_DRIVE_PAD_CTL_RESERVED0_ALIGN 0 9646 #define DDR34_F0_PHY_BYTE_LANE_1_DRIVE_PAD_CTL_RESERVED0_BITS 12 9647 #define DDR34_F0_PHY_BYTE_LANE_1_DRIVE_PAD_CTL_RESERVED0_SHIFT 20 9648 9649 /* DDR34_F0_PHY_BYTE_LANE_1 :: DRIVE_PAD_CTL :: BL_PD_TERM_STRENGTH [19:15] */ 9650 #define DDR34_F0_PHY_BYTE_LANE_1_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_MASK 0x000f8000 9651 #define DDR34_F0_PHY_BYTE_LANE_1_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_ALIGN 0 9652 #define DDR34_F0_PHY_BYTE_LANE_1_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_BITS 5 9653 #define DDR34_F0_PHY_BYTE_LANE_1_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_SHIFT 15 9654 9655 /* DDR34_F0_PHY_BYTE_LANE_1 :: DRIVE_PAD_CTL :: BL_ND_TERM_STRENGTH [14:10] */ 9656 #define DDR34_F0_PHY_BYTE_LANE_1_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_MASK 0x00007c00 9657 #define DDR34_F0_PHY_BYTE_LANE_1_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_ALIGN 0 9658 #define DDR34_F0_PHY_BYTE_LANE_1_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_BITS 5 9659 #define DDR34_F0_PHY_BYTE_LANE_1_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_SHIFT 10 9660 9661 /* DDR34_F0_PHY_BYTE_LANE_1 :: DRIVE_PAD_CTL :: BL_PD_STRENGTH [09:05] */ 9662 #define DDR34_F0_PHY_BYTE_LANE_1_DRIVE_PAD_CTL_BL_PD_STRENGTH_MASK 0x000003e0 9663 #define DDR34_F0_PHY_BYTE_LANE_1_DRIVE_PAD_CTL_BL_PD_STRENGTH_ALIGN 0 9664 #define DDR34_F0_PHY_BYTE_LANE_1_DRIVE_PAD_CTL_BL_PD_STRENGTH_BITS 5 9665 #define DDR34_F0_PHY_BYTE_LANE_1_DRIVE_PAD_CTL_BL_PD_STRENGTH_SHIFT 5 9666 9667 /* DDR34_F0_PHY_BYTE_LANE_1 :: DRIVE_PAD_CTL :: BL_ND_STRENGTH [04:00] */ 9668 #define DDR34_F0_PHY_BYTE_LANE_1_DRIVE_PAD_CTL_BL_ND_STRENGTH_MASK 0x0000001f 9669 #define DDR34_F0_PHY_BYTE_LANE_1_DRIVE_PAD_CTL_BL_ND_STRENGTH_ALIGN 0 9670 #define DDR34_F0_PHY_BYTE_LANE_1_DRIVE_PAD_CTL_BL_ND_STRENGTH_BITS 5 9671 #define DDR34_F0_PHY_BYTE_LANE_1_DRIVE_PAD_CTL_BL_ND_STRENGTH_SHIFT 0 9672 9673 9674 /**************************************************************************** 9675 * DDR34_F0_PHY_BYTE_LANE_1 :: DQSP_DRIVE_PAD_CTL 9676 */ 9677 /* DDR34_F0_PHY_BYTE_LANE_1 :: DQSP_DRIVE_PAD_CTL :: reserved0 [31:20] */ 9678 #define DDR34_F0_PHY_BYTE_LANE_1_DQSP_DRIVE_PAD_CTL_RESERVED0_MASK 0xfff00000 9679 #define DDR34_F0_PHY_BYTE_LANE_1_DQSP_DRIVE_PAD_CTL_RESERVED0_ALIGN 0 9680 #define DDR34_F0_PHY_BYTE_LANE_1_DQSP_DRIVE_PAD_CTL_RESERVED0_BITS 12 9681 #define DDR34_F0_PHY_BYTE_LANE_1_DQSP_DRIVE_PAD_CTL_RESERVED0_SHIFT 20 9682 9683 /* DDR34_F0_PHY_BYTE_LANE_1 :: DQSP_DRIVE_PAD_CTL :: BL_PD_TERM_STRENGTH [19:15] */ 9684 #define DDR34_F0_PHY_BYTE_LANE_1_DQSP_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_MASK 0x000f8000 9685 #define DDR34_F0_PHY_BYTE_LANE_1_DQSP_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_ALIGN 0 9686 #define DDR34_F0_PHY_BYTE_LANE_1_DQSP_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_BITS 5 9687 #define DDR34_F0_PHY_BYTE_LANE_1_DQSP_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_SHIFT 15 9688 9689 /* DDR34_F0_PHY_BYTE_LANE_1 :: DQSP_DRIVE_PAD_CTL :: BL_ND_TERM_STRENGTH [14:10] */ 9690 #define DDR34_F0_PHY_BYTE_LANE_1_DQSP_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_MASK 0x00007c00 9691 #define DDR34_F0_PHY_BYTE_LANE_1_DQSP_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_ALIGN 0 9692 #define DDR34_F0_PHY_BYTE_LANE_1_DQSP_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_BITS 5 9693 #define DDR34_F0_PHY_BYTE_LANE_1_DQSP_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_SHIFT 10 9694 9695 /* DDR34_F0_PHY_BYTE_LANE_1 :: DQSP_DRIVE_PAD_CTL :: BL_PD_STRENGTH [09:05] */ 9696 #define DDR34_F0_PHY_BYTE_LANE_1_DQSP_DRIVE_PAD_CTL_BL_PD_STRENGTH_MASK 0x000003e0 9697 #define DDR34_F0_PHY_BYTE_LANE_1_DQSP_DRIVE_PAD_CTL_BL_PD_STRENGTH_ALIGN 0 9698 #define DDR34_F0_PHY_BYTE_LANE_1_DQSP_DRIVE_PAD_CTL_BL_PD_STRENGTH_BITS 5 9699 #define DDR34_F0_PHY_BYTE_LANE_1_DQSP_DRIVE_PAD_CTL_BL_PD_STRENGTH_SHIFT 5 9700 9701 /* DDR34_F0_PHY_BYTE_LANE_1 :: DQSP_DRIVE_PAD_CTL :: BL_ND_STRENGTH [04:00] */ 9702 #define DDR34_F0_PHY_BYTE_LANE_1_DQSP_DRIVE_PAD_CTL_BL_ND_STRENGTH_MASK 0x0000001f 9703 #define DDR34_F0_PHY_BYTE_LANE_1_DQSP_DRIVE_PAD_CTL_BL_ND_STRENGTH_ALIGN 0 9704 #define DDR34_F0_PHY_BYTE_LANE_1_DQSP_DRIVE_PAD_CTL_BL_ND_STRENGTH_BITS 5 9705 #define DDR34_F0_PHY_BYTE_LANE_1_DQSP_DRIVE_PAD_CTL_BL_ND_STRENGTH_SHIFT 0 9706 9707 9708 /**************************************************************************** 9709 * DDR34_F0_PHY_BYTE_LANE_1 :: DQSN_DRIVE_PAD_CTL 9710 */ 9711 /* DDR34_F0_PHY_BYTE_LANE_1 :: DQSN_DRIVE_PAD_CTL :: reserved0 [31:20] */ 9712 #define DDR34_F0_PHY_BYTE_LANE_1_DQSN_DRIVE_PAD_CTL_RESERVED0_MASK 0xfff00000 9713 #define DDR34_F0_PHY_BYTE_LANE_1_DQSN_DRIVE_PAD_CTL_RESERVED0_ALIGN 0 9714 #define DDR34_F0_PHY_BYTE_LANE_1_DQSN_DRIVE_PAD_CTL_RESERVED0_BITS 12 9715 #define DDR34_F0_PHY_BYTE_LANE_1_DQSN_DRIVE_PAD_CTL_RESERVED0_SHIFT 20 9716 9717 /* DDR34_F0_PHY_BYTE_LANE_1 :: DQSN_DRIVE_PAD_CTL :: BL_PD_TERM_STRENGTH [19:15] */ 9718 #define DDR34_F0_PHY_BYTE_LANE_1_DQSN_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_MASK 0x000f8000 9719 #define DDR34_F0_PHY_BYTE_LANE_1_DQSN_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_ALIGN 0 9720 #define DDR34_F0_PHY_BYTE_LANE_1_DQSN_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_BITS 5 9721 #define DDR34_F0_PHY_BYTE_LANE_1_DQSN_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_SHIFT 15 9722 9723 /* DDR34_F0_PHY_BYTE_LANE_1 :: DQSN_DRIVE_PAD_CTL :: BL_ND_TERM_STRENGTH [14:10] */ 9724 #define DDR34_F0_PHY_BYTE_LANE_1_DQSN_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_MASK 0x00007c00 9725 #define DDR34_F0_PHY_BYTE_LANE_1_DQSN_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_ALIGN 0 9726 #define DDR34_F0_PHY_BYTE_LANE_1_DQSN_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_BITS 5 9727 #define DDR34_F0_PHY_BYTE_LANE_1_DQSN_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_SHIFT 10 9728 9729 /* DDR34_F0_PHY_BYTE_LANE_1 :: DQSN_DRIVE_PAD_CTL :: BL_PD_STRENGTH [09:05] */ 9730 #define DDR34_F0_PHY_BYTE_LANE_1_DQSN_DRIVE_PAD_CTL_BL_PD_STRENGTH_MASK 0x000003e0 9731 #define DDR34_F0_PHY_BYTE_LANE_1_DQSN_DRIVE_PAD_CTL_BL_PD_STRENGTH_ALIGN 0 9732 #define DDR34_F0_PHY_BYTE_LANE_1_DQSN_DRIVE_PAD_CTL_BL_PD_STRENGTH_BITS 5 9733 #define DDR34_F0_PHY_BYTE_LANE_1_DQSN_DRIVE_PAD_CTL_BL_PD_STRENGTH_SHIFT 5 9734 9735 /* DDR34_F0_PHY_BYTE_LANE_1 :: DQSN_DRIVE_PAD_CTL :: BL_ND_STRENGTH [04:00] */ 9736 #define DDR34_F0_PHY_BYTE_LANE_1_DQSN_DRIVE_PAD_CTL_BL_ND_STRENGTH_MASK 0x0000001f 9737 #define DDR34_F0_PHY_BYTE_LANE_1_DQSN_DRIVE_PAD_CTL_BL_ND_STRENGTH_ALIGN 0 9738 #define DDR34_F0_PHY_BYTE_LANE_1_DQSN_DRIVE_PAD_CTL_BL_ND_STRENGTH_BITS 5 9739 #define DDR34_F0_PHY_BYTE_LANE_1_DQSN_DRIVE_PAD_CTL_BL_ND_STRENGTH_SHIFT 0 9740 9741 9742 /**************************************************************************** 9743 * DDR34_F0_PHY_BYTE_LANE_1 :: ALERT_DRIVE_PAD_CTL 9744 */ 9745 /* DDR34_F0_PHY_BYTE_LANE_1 :: ALERT_DRIVE_PAD_CTL :: reserved0 [31:20] */ 9746 #define DDR34_F0_PHY_BYTE_LANE_1_ALERT_DRIVE_PAD_CTL_RESERVED0_MASK 0xfff00000 9747 #define DDR34_F0_PHY_BYTE_LANE_1_ALERT_DRIVE_PAD_CTL_RESERVED0_ALIGN 0 9748 #define DDR34_F0_PHY_BYTE_LANE_1_ALERT_DRIVE_PAD_CTL_RESERVED0_BITS 12 9749 #define DDR34_F0_PHY_BYTE_LANE_1_ALERT_DRIVE_PAD_CTL_RESERVED0_SHIFT 20 9750 9751 /* DDR34_F0_PHY_BYTE_LANE_1 :: ALERT_DRIVE_PAD_CTL :: BL_PD_TERM_STRENGTH [19:15] */ 9752 #define DDR34_F0_PHY_BYTE_LANE_1_ALERT_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_MASK 0x000f8000 9753 #define DDR34_F0_PHY_BYTE_LANE_1_ALERT_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_ALIGN 0 9754 #define DDR34_F0_PHY_BYTE_LANE_1_ALERT_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_BITS 5 9755 #define DDR34_F0_PHY_BYTE_LANE_1_ALERT_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_SHIFT 15 9756 9757 /* DDR34_F0_PHY_BYTE_LANE_1 :: ALERT_DRIVE_PAD_CTL :: BL_ND_TERM_STRENGTH [14:10] */ 9758 #define DDR34_F0_PHY_BYTE_LANE_1_ALERT_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_MASK 0x00007c00 9759 #define DDR34_F0_PHY_BYTE_LANE_1_ALERT_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_ALIGN 0 9760 #define DDR34_F0_PHY_BYTE_LANE_1_ALERT_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_BITS 5 9761 #define DDR34_F0_PHY_BYTE_LANE_1_ALERT_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_SHIFT 10 9762 9763 /* DDR34_F0_PHY_BYTE_LANE_1 :: ALERT_DRIVE_PAD_CTL :: BL_PD_STRENGTH [09:05] */ 9764 #define DDR34_F0_PHY_BYTE_LANE_1_ALERT_DRIVE_PAD_CTL_BL_PD_STRENGTH_MASK 0x000003e0 9765 #define DDR34_F0_PHY_BYTE_LANE_1_ALERT_DRIVE_PAD_CTL_BL_PD_STRENGTH_ALIGN 0 9766 #define DDR34_F0_PHY_BYTE_LANE_1_ALERT_DRIVE_PAD_CTL_BL_PD_STRENGTH_BITS 5 9767 #define DDR34_F0_PHY_BYTE_LANE_1_ALERT_DRIVE_PAD_CTL_BL_PD_STRENGTH_SHIFT 5 9768 9769 /* DDR34_F0_PHY_BYTE_LANE_1 :: ALERT_DRIVE_PAD_CTL :: BL_ND_STRENGTH [04:00] */ 9770 #define DDR34_F0_PHY_BYTE_LANE_1_ALERT_DRIVE_PAD_CTL_BL_ND_STRENGTH_MASK 0x0000001f 9771 #define DDR34_F0_PHY_BYTE_LANE_1_ALERT_DRIVE_PAD_CTL_BL_ND_STRENGTH_ALIGN 0 9772 #define DDR34_F0_PHY_BYTE_LANE_1_ALERT_DRIVE_PAD_CTL_BL_ND_STRENGTH_BITS 5 9773 #define DDR34_F0_PHY_BYTE_LANE_1_ALERT_DRIVE_PAD_CTL_BL_ND_STRENGTH_SHIFT 0 9774 9775 9776 /**************************************************************************** 9777 * DDR34_F0_PHY_BYTE_LANE_1 :: RD_EN_DRIVE_PAD_CTL 9778 */ 9779 /* DDR34_F0_PHY_BYTE_LANE_1 :: RD_EN_DRIVE_PAD_CTL :: reserved0 [31:10] */ 9780 #define DDR34_F0_PHY_BYTE_LANE_1_RD_EN_DRIVE_PAD_CTL_RESERVED0_MASK 0xfffffc00 9781 #define DDR34_F0_PHY_BYTE_LANE_1_RD_EN_DRIVE_PAD_CTL_RESERVED0_ALIGN 0 9782 #define DDR34_F0_PHY_BYTE_LANE_1_RD_EN_DRIVE_PAD_CTL_RESERVED0_BITS 22 9783 #define DDR34_F0_PHY_BYTE_LANE_1_RD_EN_DRIVE_PAD_CTL_RESERVED0_SHIFT 10 9784 9785 /* DDR34_F0_PHY_BYTE_LANE_1 :: RD_EN_DRIVE_PAD_CTL :: BL_RD_EN_PD_STRENGTH [09:05] */ 9786 #define DDR34_F0_PHY_BYTE_LANE_1_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_PD_STRENGTH_MASK 0x000003e0 9787 #define DDR34_F0_PHY_BYTE_LANE_1_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_PD_STRENGTH_ALIGN 0 9788 #define DDR34_F0_PHY_BYTE_LANE_1_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_PD_STRENGTH_BITS 5 9789 #define DDR34_F0_PHY_BYTE_LANE_1_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_PD_STRENGTH_SHIFT 5 9790 9791 /* DDR34_F0_PHY_BYTE_LANE_1 :: RD_EN_DRIVE_PAD_CTL :: BL_RD_EN_ND_STRENGTH [04:00] */ 9792 #define DDR34_F0_PHY_BYTE_LANE_1_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_ND_STRENGTH_MASK 0x0000001f 9793 #define DDR34_F0_PHY_BYTE_LANE_1_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_ND_STRENGTH_ALIGN 0 9794 #define DDR34_F0_PHY_BYTE_LANE_1_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_ND_STRENGTH_BITS 5 9795 #define DDR34_F0_PHY_BYTE_LANE_1_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_ND_STRENGTH_SHIFT 0 9796 9797 9798 /**************************************************************************** 9799 * DDR34_F0_PHY_BYTE_LANE_1 :: STATIC_PAD_CTL 9800 */ 9801 /* DDR34_F0_PHY_BYTE_LANE_1 :: STATIC_PAD_CTL :: reserved0 [31:18] */ 9802 #define DDR34_F0_PHY_BYTE_LANE_1_STATIC_PAD_CTL_RESERVED0_MASK 0xfffc0000 9803 #define DDR34_F0_PHY_BYTE_LANE_1_STATIC_PAD_CTL_RESERVED0_ALIGN 0 9804 #define DDR34_F0_PHY_BYTE_LANE_1_STATIC_PAD_CTL_RESERVED0_BITS 14 9805 #define DDR34_F0_PHY_BYTE_LANE_1_STATIC_PAD_CTL_RESERVED0_SHIFT 18 9806 9807 /* DDR34_F0_PHY_BYTE_LANE_1 :: STATIC_PAD_CTL :: DM_INVERT [17:17] */ 9808 #define DDR34_F0_PHY_BYTE_LANE_1_STATIC_PAD_CTL_DM_INVERT_MASK 0x00020000 9809 #define DDR34_F0_PHY_BYTE_LANE_1_STATIC_PAD_CTL_DM_INVERT_ALIGN 0 9810 #define DDR34_F0_PHY_BYTE_LANE_1_STATIC_PAD_CTL_DM_INVERT_BITS 1 9811 #define DDR34_F0_PHY_BYTE_LANE_1_STATIC_PAD_CTL_DM_INVERT_SHIFT 17 9812 9813 /* DDR34_F0_PHY_BYTE_LANE_1 :: STATIC_PAD_CTL :: WDBI_ENABLE [16:16] */ 9814 #define DDR34_F0_PHY_BYTE_LANE_1_STATIC_PAD_CTL_WDBI_ENABLE_MASK 0x00010000 9815 #define DDR34_F0_PHY_BYTE_LANE_1_STATIC_PAD_CTL_WDBI_ENABLE_ALIGN 0 9816 #define DDR34_F0_PHY_BYTE_LANE_1_STATIC_PAD_CTL_WDBI_ENABLE_BITS 1 9817 #define DDR34_F0_PHY_BYTE_LANE_1_STATIC_PAD_CTL_WDBI_ENABLE_SHIFT 16 9818 9819 /* DDR34_F0_PHY_BYTE_LANE_1 :: STATIC_PAD_CTL :: RDBI_ENABLE [15:15] */ 9820 #define DDR34_F0_PHY_BYTE_LANE_1_STATIC_PAD_CTL_RDBI_ENABLE_MASK 0x00008000 9821 #define DDR34_F0_PHY_BYTE_LANE_1_STATIC_PAD_CTL_RDBI_ENABLE_ALIGN 0 9822 #define DDR34_F0_PHY_BYTE_LANE_1_STATIC_PAD_CTL_RDBI_ENABLE_BITS 1 9823 #define DDR34_F0_PHY_BYTE_LANE_1_STATIC_PAD_CTL_RDBI_ENABLE_SHIFT 15 9824 9825 /* DDR34_F0_PHY_BYTE_LANE_1 :: STATIC_PAD_CTL :: DM_MODE [14:14] */ 9826 #define DDR34_F0_PHY_BYTE_LANE_1_STATIC_PAD_CTL_DM_MODE_MASK 0x00004000 9827 #define DDR34_F0_PHY_BYTE_LANE_1_STATIC_PAD_CTL_DM_MODE_ALIGN 0 9828 #define DDR34_F0_PHY_BYTE_LANE_1_STATIC_PAD_CTL_DM_MODE_BITS 1 9829 #define DDR34_F0_PHY_BYTE_LANE_1_STATIC_PAD_CTL_DM_MODE_SHIFT 14 9830 9831 /* DDR34_F0_PHY_BYTE_LANE_1 :: STATIC_PAD_CTL :: reserved1 [13:10] */ 9832 #define DDR34_F0_PHY_BYTE_LANE_1_STATIC_PAD_CTL_RESERVED1_MASK 0x00003c00 9833 #define DDR34_F0_PHY_BYTE_LANE_1_STATIC_PAD_CTL_RESERVED1_ALIGN 0 9834 #define DDR34_F0_PHY_BYTE_LANE_1_STATIC_PAD_CTL_RESERVED1_BITS 4 9835 #define DDR34_F0_PHY_BYTE_LANE_1_STATIC_PAD_CTL_RESERVED1_SHIFT 10 9836 9837 /* DDR34_F0_PHY_BYTE_LANE_1 :: STATIC_PAD_CTL :: DQS_TX_DIS [09:09] */ 9838 #define DDR34_F0_PHY_BYTE_LANE_1_STATIC_PAD_CTL_DQS_TX_DIS_MASK 0x00000200 9839 #define DDR34_F0_PHY_BYTE_LANE_1_STATIC_PAD_CTL_DQS_TX_DIS_ALIGN 0 9840 #define DDR34_F0_PHY_BYTE_LANE_1_STATIC_PAD_CTL_DQS_TX_DIS_BITS 1 9841 #define DDR34_F0_PHY_BYTE_LANE_1_STATIC_PAD_CTL_DQS_TX_DIS_SHIFT 9 9842 9843 /* DDR34_F0_PHY_BYTE_LANE_1 :: STATIC_PAD_CTL :: reserved2 [08:02] */ 9844 #define DDR34_F0_PHY_BYTE_LANE_1_STATIC_PAD_CTL_RESERVED2_MASK 0x000001fc 9845 #define DDR34_F0_PHY_BYTE_LANE_1_STATIC_PAD_CTL_RESERVED2_ALIGN 0 9846 #define DDR34_F0_PHY_BYTE_LANE_1_STATIC_PAD_CTL_RESERVED2_BITS 7 9847 #define DDR34_F0_PHY_BYTE_LANE_1_STATIC_PAD_CTL_RESERVED2_SHIFT 2 9848 9849 /* DDR34_F0_PHY_BYTE_LANE_1 :: STATIC_PAD_CTL :: RX_MODE [01:00] */ 9850 #define DDR34_F0_PHY_BYTE_LANE_1_STATIC_PAD_CTL_RX_MODE_MASK 0x00000003 9851 #define DDR34_F0_PHY_BYTE_LANE_1_STATIC_PAD_CTL_RX_MODE_ALIGN 0 9852 #define DDR34_F0_PHY_BYTE_LANE_1_STATIC_PAD_CTL_RX_MODE_BITS 2 9853 #define DDR34_F0_PHY_BYTE_LANE_1_STATIC_PAD_CTL_RX_MODE_SHIFT 0 9854 9855 9856 /**************************************************************************** 9857 * DDR34_F0_PHY_BYTE_LANE_1 :: WR_PREAMBLE_MODE 9858 */ 9859 /* DDR34_F0_PHY_BYTE_LANE_1 :: WR_PREAMBLE_MODE :: reserved0 [31:21] */ 9860 #define DDR34_F0_PHY_BYTE_LANE_1_WR_PREAMBLE_MODE_RESERVED0_MASK 0xffe00000 9861 #define DDR34_F0_PHY_BYTE_LANE_1_WR_PREAMBLE_MODE_RESERVED0_ALIGN 0 9862 #define DDR34_F0_PHY_BYTE_LANE_1_WR_PREAMBLE_MODE_RESERVED0_BITS 11 9863 #define DDR34_F0_PHY_BYTE_LANE_1_WR_PREAMBLE_MODE_RESERVED0_SHIFT 21 9864 9865 /* DDR34_F0_PHY_BYTE_LANE_1 :: WR_PREAMBLE_MODE :: POSTAM_TERM_BITS [20:19] */ 9866 #define DDR34_F0_PHY_BYTE_LANE_1_WR_PREAMBLE_MODE_POSTAM_TERM_BITS_MASK 0x00180000 9867 #define DDR34_F0_PHY_BYTE_LANE_1_WR_PREAMBLE_MODE_POSTAM_TERM_BITS_ALIGN 0 9868 #define DDR34_F0_PHY_BYTE_LANE_1_WR_PREAMBLE_MODE_POSTAM_TERM_BITS_BITS 2 9869 #define DDR34_F0_PHY_BYTE_LANE_1_WR_PREAMBLE_MODE_POSTAM_TERM_BITS_SHIFT 19 9870 9871 /* DDR34_F0_PHY_BYTE_LANE_1 :: WR_PREAMBLE_MODE :: DM_POSTAM_BITS [18:17] */ 9872 #define DDR34_F0_PHY_BYTE_LANE_1_WR_PREAMBLE_MODE_DM_POSTAM_BITS_MASK 0x00060000 9873 #define DDR34_F0_PHY_BYTE_LANE_1_WR_PREAMBLE_MODE_DM_POSTAM_BITS_ALIGN 0 9874 #define DDR34_F0_PHY_BYTE_LANE_1_WR_PREAMBLE_MODE_DM_POSTAM_BITS_BITS 2 9875 #define DDR34_F0_PHY_BYTE_LANE_1_WR_PREAMBLE_MODE_DM_POSTAM_BITS_SHIFT 17 9876 9877 /* DDR34_F0_PHY_BYTE_LANE_1 :: WR_PREAMBLE_MODE :: DM_PREAM_BITS [16:14] */ 9878 #define DDR34_F0_PHY_BYTE_LANE_1_WR_PREAMBLE_MODE_DM_PREAM_BITS_MASK 0x0001c000 9879 #define DDR34_F0_PHY_BYTE_LANE_1_WR_PREAMBLE_MODE_DM_PREAM_BITS_ALIGN 0 9880 #define DDR34_F0_PHY_BYTE_LANE_1_WR_PREAMBLE_MODE_DM_PREAM_BITS_BITS 3 9881 #define DDR34_F0_PHY_BYTE_LANE_1_WR_PREAMBLE_MODE_DM_PREAM_BITS_SHIFT 14 9882 9883 /* DDR34_F0_PHY_BYTE_LANE_1 :: WR_PREAMBLE_MODE :: DQ_POSTAM_BITS [13:12] */ 9884 #define DDR34_F0_PHY_BYTE_LANE_1_WR_PREAMBLE_MODE_DQ_POSTAM_BITS_MASK 0x00003000 9885 #define DDR34_F0_PHY_BYTE_LANE_1_WR_PREAMBLE_MODE_DQ_POSTAM_BITS_ALIGN 0 9886 #define DDR34_F0_PHY_BYTE_LANE_1_WR_PREAMBLE_MODE_DQ_POSTAM_BITS_BITS 2 9887 #define DDR34_F0_PHY_BYTE_LANE_1_WR_PREAMBLE_MODE_DQ_POSTAM_BITS_SHIFT 12 9888 9889 /* DDR34_F0_PHY_BYTE_LANE_1 :: WR_PREAMBLE_MODE :: DQ_PREAM_BITS [11:09] */ 9890 #define DDR34_F0_PHY_BYTE_LANE_1_WR_PREAMBLE_MODE_DQ_PREAM_BITS_MASK 0x00000e00 9891 #define DDR34_F0_PHY_BYTE_LANE_1_WR_PREAMBLE_MODE_DQ_PREAM_BITS_ALIGN 0 9892 #define DDR34_F0_PHY_BYTE_LANE_1_WR_PREAMBLE_MODE_DQ_PREAM_BITS_BITS 3 9893 #define DDR34_F0_PHY_BYTE_LANE_1_WR_PREAMBLE_MODE_DQ_PREAM_BITS_SHIFT 9 9894 9895 /* DDR34_F0_PHY_BYTE_LANE_1 :: WR_PREAMBLE_MODE :: DQS [08:05] */ 9896 #define DDR34_F0_PHY_BYTE_LANE_1_WR_PREAMBLE_MODE_DQS_MASK 0x000001e0 9897 #define DDR34_F0_PHY_BYTE_LANE_1_WR_PREAMBLE_MODE_DQS_ALIGN 0 9898 #define DDR34_F0_PHY_BYTE_LANE_1_WR_PREAMBLE_MODE_DQS_BITS 4 9899 #define DDR34_F0_PHY_BYTE_LANE_1_WR_PREAMBLE_MODE_DQS_SHIFT 5 9900 9901 /* DDR34_F0_PHY_BYTE_LANE_1 :: WR_PREAMBLE_MODE :: DQS_POSTAM_BITS [04:03] */ 9902 #define DDR34_F0_PHY_BYTE_LANE_1_WR_PREAMBLE_MODE_DQS_POSTAM_BITS_MASK 0x00000018 9903 #define DDR34_F0_PHY_BYTE_LANE_1_WR_PREAMBLE_MODE_DQS_POSTAM_BITS_ALIGN 0 9904 #define DDR34_F0_PHY_BYTE_LANE_1_WR_PREAMBLE_MODE_DQS_POSTAM_BITS_BITS 2 9905 #define DDR34_F0_PHY_BYTE_LANE_1_WR_PREAMBLE_MODE_DQS_POSTAM_BITS_SHIFT 3 9906 9907 /* DDR34_F0_PHY_BYTE_LANE_1 :: WR_PREAMBLE_MODE :: DQS_PREAM_BITS [02:00] */ 9908 #define DDR34_F0_PHY_BYTE_LANE_1_WR_PREAMBLE_MODE_DQS_PREAM_BITS_MASK 0x00000007 9909 #define DDR34_F0_PHY_BYTE_LANE_1_WR_PREAMBLE_MODE_DQS_PREAM_BITS_ALIGN 0 9910 #define DDR34_F0_PHY_BYTE_LANE_1_WR_PREAMBLE_MODE_DQS_PREAM_BITS_BITS 3 9911 #define DDR34_F0_PHY_BYTE_LANE_1_WR_PREAMBLE_MODE_DQS_PREAM_BITS_SHIFT 0 9912 9913 9914 /**************************************************************************** 9915 * DDR34_F0_PHY_BYTE_LANE_1 :: ODT_CONTROL 9916 */ 9917 /* DDR34_F0_PHY_BYTE_LANE_1 :: ODT_CONTROL :: reserved0 [31:10] */ 9918 #define DDR34_F0_PHY_BYTE_LANE_1_ODT_CONTROL_RESERVED0_MASK 0xfffffc00 9919 #define DDR34_F0_PHY_BYTE_LANE_1_ODT_CONTROL_RESERVED0_ALIGN 0 9920 #define DDR34_F0_PHY_BYTE_LANE_1_ODT_CONTROL_RESERVED0_BITS 22 9921 #define DDR34_F0_PHY_BYTE_LANE_1_ODT_CONTROL_RESERVED0_SHIFT 10 9922 9923 /* DDR34_F0_PHY_BYTE_LANE_1 :: ODT_CONTROL :: ODT_ENABLE [09:09] */ 9924 #define DDR34_F0_PHY_BYTE_LANE_1_ODT_CONTROL_ODT_ENABLE_MASK 0x00000200 9925 #define DDR34_F0_PHY_BYTE_LANE_1_ODT_CONTROL_ODT_ENABLE_ALIGN 0 9926 #define DDR34_F0_PHY_BYTE_LANE_1_ODT_CONTROL_ODT_ENABLE_BITS 1 9927 #define DDR34_F0_PHY_BYTE_LANE_1_ODT_CONTROL_ODT_ENABLE_SHIFT 9 9928 9929 /* DDR34_F0_PHY_BYTE_LANE_1 :: ODT_CONTROL :: ODT_DELAY [08:06] */ 9930 #define DDR34_F0_PHY_BYTE_LANE_1_ODT_CONTROL_ODT_DELAY_MASK 0x000001c0 9931 #define DDR34_F0_PHY_BYTE_LANE_1_ODT_CONTROL_ODT_DELAY_ALIGN 0 9932 #define DDR34_F0_PHY_BYTE_LANE_1_ODT_CONTROL_ODT_DELAY_BITS 3 9933 #define DDR34_F0_PHY_BYTE_LANE_1_ODT_CONTROL_ODT_DELAY_SHIFT 6 9934 9935 /* DDR34_F0_PHY_BYTE_LANE_1 :: ODT_CONTROL :: ODT_POST_LENGTH [05:03] */ 9936 #define DDR34_F0_PHY_BYTE_LANE_1_ODT_CONTROL_ODT_POST_LENGTH_MASK 0x00000038 9937 #define DDR34_F0_PHY_BYTE_LANE_1_ODT_CONTROL_ODT_POST_LENGTH_ALIGN 0 9938 #define DDR34_F0_PHY_BYTE_LANE_1_ODT_CONTROL_ODT_POST_LENGTH_BITS 3 9939 #define DDR34_F0_PHY_BYTE_LANE_1_ODT_CONTROL_ODT_POST_LENGTH_SHIFT 3 9940 9941 /* DDR34_F0_PHY_BYTE_LANE_1 :: ODT_CONTROL :: reserved1 [02:02] */ 9942 #define DDR34_F0_PHY_BYTE_LANE_1_ODT_CONTROL_RESERVED1_MASK 0x00000004 9943 #define DDR34_F0_PHY_BYTE_LANE_1_ODT_CONTROL_RESERVED1_ALIGN 0 9944 #define DDR34_F0_PHY_BYTE_LANE_1_ODT_CONTROL_RESERVED1_BITS 1 9945 #define DDR34_F0_PHY_BYTE_LANE_1_ODT_CONTROL_RESERVED1_SHIFT 2 9946 9947 /* DDR34_F0_PHY_BYTE_LANE_1 :: ODT_CONTROL :: ODT_PRE_LENGTH [01:00] */ 9948 #define DDR34_F0_PHY_BYTE_LANE_1_ODT_CONTROL_ODT_PRE_LENGTH_MASK 0x00000003 9949 #define DDR34_F0_PHY_BYTE_LANE_1_ODT_CONTROL_ODT_PRE_LENGTH_ALIGN 0 9950 #define DDR34_F0_PHY_BYTE_LANE_1_ODT_CONTROL_ODT_PRE_LENGTH_BITS 2 9951 #define DDR34_F0_PHY_BYTE_LANE_1_ODT_CONTROL_ODT_PRE_LENGTH_SHIFT 0 9952 9953 9954 /**************************************************************************** 9955 * DDR34_F0_PHY_BYTE_LANE_1 :: CLOCK_ENABLE 9956 */ 9957 /* DDR34_F0_PHY_BYTE_LANE_1 :: CLOCK_ENABLE :: reserved0 [31:03] */ 9958 #define DDR34_F0_PHY_BYTE_LANE_1_CLOCK_ENABLE_RESERVED0_MASK 0xfffffff8 9959 #define DDR34_F0_PHY_BYTE_LANE_1_CLOCK_ENABLE_RESERVED0_ALIGN 0 9960 #define DDR34_F0_PHY_BYTE_LANE_1_CLOCK_ENABLE_RESERVED0_BITS 29 9961 #define DDR34_F0_PHY_BYTE_LANE_1_CLOCK_ENABLE_RESERVED0_SHIFT 3 9962 9963 /* DDR34_F0_PHY_BYTE_LANE_1 :: CLOCK_ENABLE :: TO_MC_CLOCK [02:02] */ 9964 #define DDR34_F0_PHY_BYTE_LANE_1_CLOCK_ENABLE_TO_MC_CLOCK_MASK 0x00000004 9965 #define DDR34_F0_PHY_BYTE_LANE_1_CLOCK_ENABLE_TO_MC_CLOCK_ALIGN 0 9966 #define DDR34_F0_PHY_BYTE_LANE_1_CLOCK_ENABLE_TO_MC_CLOCK_BITS 1 9967 #define DDR34_F0_PHY_BYTE_LANE_1_CLOCK_ENABLE_TO_MC_CLOCK_SHIFT 2 9968 9969 /* DDR34_F0_PHY_BYTE_LANE_1 :: CLOCK_ENABLE :: FROM_MC_CLOCK [01:01] */ 9970 #define DDR34_F0_PHY_BYTE_LANE_1_CLOCK_ENABLE_FROM_MC_CLOCK_MASK 0x00000002 9971 #define DDR34_F0_PHY_BYTE_LANE_1_CLOCK_ENABLE_FROM_MC_CLOCK_ALIGN 0 9972 #define DDR34_F0_PHY_BYTE_LANE_1_CLOCK_ENABLE_FROM_MC_CLOCK_BITS 1 9973 #define DDR34_F0_PHY_BYTE_LANE_1_CLOCK_ENABLE_FROM_MC_CLOCK_SHIFT 1 9974 9975 /* DDR34_F0_PHY_BYTE_LANE_1 :: CLOCK_ENABLE :: BIT_CLOCK [00:00] */ 9976 #define DDR34_F0_PHY_BYTE_LANE_1_CLOCK_ENABLE_BIT_CLOCK_MASK 0x00000001 9977 #define DDR34_F0_PHY_BYTE_LANE_1_CLOCK_ENABLE_BIT_CLOCK_ALIGN 0 9978 #define DDR34_F0_PHY_BYTE_LANE_1_CLOCK_ENABLE_BIT_CLOCK_BITS 1 9979 #define DDR34_F0_PHY_BYTE_LANE_1_CLOCK_ENABLE_BIT_CLOCK_SHIFT 0 9980 9981 9982 /**************************************************************************** 9983 * DDR34_F0_PHY_BYTE_LANE_1 :: CLOCK_IDLE 9984 */ 9985 /* DDR34_F0_PHY_BYTE_LANE_1 :: CLOCK_IDLE :: reserved0 [31:03] */ 9986 #define DDR34_F0_PHY_BYTE_LANE_1_CLOCK_IDLE_RESERVED0_MASK 0xfffffff8 9987 #define DDR34_F0_PHY_BYTE_LANE_1_CLOCK_IDLE_RESERVED0_ALIGN 0 9988 #define DDR34_F0_PHY_BYTE_LANE_1_CLOCK_IDLE_RESERVED0_BITS 29 9989 #define DDR34_F0_PHY_BYTE_LANE_1_CLOCK_IDLE_RESERVED0_SHIFT 3 9990 9991 /* DDR34_F0_PHY_BYTE_LANE_1 :: CLOCK_IDLE :: TO_MC_CLOCK [02:02] */ 9992 #define DDR34_F0_PHY_BYTE_LANE_1_CLOCK_IDLE_TO_MC_CLOCK_MASK 0x00000004 9993 #define DDR34_F0_PHY_BYTE_LANE_1_CLOCK_IDLE_TO_MC_CLOCK_ALIGN 0 9994 #define DDR34_F0_PHY_BYTE_LANE_1_CLOCK_IDLE_TO_MC_CLOCK_BITS 1 9995 #define DDR34_F0_PHY_BYTE_LANE_1_CLOCK_IDLE_TO_MC_CLOCK_SHIFT 2 9996 9997 /* DDR34_F0_PHY_BYTE_LANE_1 :: CLOCK_IDLE :: FROM_MC_CLOCK [01:01] */ 9998 #define DDR34_F0_PHY_BYTE_LANE_1_CLOCK_IDLE_FROM_MC_CLOCK_MASK 0x00000002 9999 #define DDR34_F0_PHY_BYTE_LANE_1_CLOCK_IDLE_FROM_MC_CLOCK_ALIGN 0 10000 #define DDR34_F0_PHY_BYTE_LANE_1_CLOCK_IDLE_FROM_MC_CLOCK_BITS 1 10001 #define DDR34_F0_PHY_BYTE_LANE_1_CLOCK_IDLE_FROM_MC_CLOCK_SHIFT 1 10002 10003 /* DDR34_F0_PHY_BYTE_LANE_1 :: CLOCK_IDLE :: BIT_CLOCK [00:00] */ 10004 #define DDR34_F0_PHY_BYTE_LANE_1_CLOCK_IDLE_BIT_CLOCK_MASK 0x00000001 10005 #define DDR34_F0_PHY_BYTE_LANE_1_CLOCK_IDLE_BIT_CLOCK_ALIGN 0 10006 #define DDR34_F0_PHY_BYTE_LANE_1_CLOCK_IDLE_BIT_CLOCK_BITS 1 10007 #define DDR34_F0_PHY_BYTE_LANE_1_CLOCK_IDLE_BIT_CLOCK_SHIFT 0 10008 10009 10010 /**************************************************************************** 10011 * DDR34_F0_PHY_BYTE_LANE_1 :: BL_SPARE_REG 10012 */ 10013 /* DDR34_F0_PHY_BYTE_LANE_1 :: BL_SPARE_REG :: reserved_for_eco0 [31:00] */ 10014 #define DDR34_F0_PHY_BYTE_LANE_1_BL_SPARE_REG_RESERVED_FOR_ECO0_MASK 0xffffffff 10015 #define DDR34_F0_PHY_BYTE_LANE_1_BL_SPARE_REG_RESERVED_FOR_ECO0_ALIGN 0 10016 #define DDR34_F0_PHY_BYTE_LANE_1_BL_SPARE_REG_RESERVED_FOR_ECO0_BITS 32 10017 #define DDR34_F0_PHY_BYTE_LANE_1_BL_SPARE_REG_RESERVED_FOR_ECO0_SHIFT 0 10018 10019 10020 /**************************************************************************** 10021 * DDR34_F0_PHY_DDR34_F0_PHY_BYTE_LANE_2 10022 */ 10023 /**************************************************************************** 10024 * DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DQS 10025 */ 10026 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DQS :: BUSY [31:31] */ 10027 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_BUSY_MASK 0x80000000 10028 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_BUSY_ALIGN 0 10029 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_BUSY_BITS 1 10030 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_BUSY_SHIFT 31 10031 10032 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DQS :: reserved0 [30:17] */ 10033 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_RESERVED0_MASK 0x7ffe0000 10034 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_RESERVED0_ALIGN 0 10035 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_RESERVED0_BITS 14 10036 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_RESERVED0_SHIFT 17 10037 10038 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DQS :: FORCE [16:16] */ 10039 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_FORCE_MASK 0x00010000 10040 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_FORCE_ALIGN 0 10041 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_FORCE_BITS 1 10042 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_FORCE_SHIFT 16 10043 10044 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DQS :: reserved1 [15:13] */ 10045 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_RESERVED1_MASK 0x0000e000 10046 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_RESERVED1_ALIGN 0 10047 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_RESERVED1_BITS 3 10048 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_RESERVED1_SHIFT 13 10049 10050 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DQS :: ADJ_EN [12:12] */ 10051 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_ADJ_EN_MASK 0x00001000 10052 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_ADJ_EN_ALIGN 0 10053 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_ADJ_EN_BITS 1 10054 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_ADJ_EN_SHIFT 12 10055 10056 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DQS :: reserved2 [11:09] */ 10057 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_RESERVED2_MASK 0x00000e00 10058 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_RESERVED2_ALIGN 0 10059 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_RESERVED2_BITS 3 10060 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_RESERVED2_SHIFT 9 10061 10062 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DQS :: VDL_STEP [08:00] */ 10063 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_VDL_STEP_MASK 0x000001ff 10064 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_VDL_STEP_ALIGN 0 10065 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_VDL_STEP_BITS 9 10066 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_VDL_STEP_SHIFT 0 10067 10068 10069 /**************************************************************************** 10070 * DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DQ0 10071 */ 10072 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DQ0 :: BUSY [31:31] */ 10073 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ0_BUSY_MASK 0x80000000 10074 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ0_BUSY_ALIGN 0 10075 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ0_BUSY_BITS 1 10076 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ0_BUSY_SHIFT 31 10077 10078 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DQ0 :: reserved0 [30:17] */ 10079 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ0_RESERVED0_MASK 0x7ffe0000 10080 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ0_RESERVED0_ALIGN 0 10081 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ0_RESERVED0_BITS 14 10082 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ0_RESERVED0_SHIFT 17 10083 10084 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DQ0 :: FORCE [16:16] */ 10085 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ0_FORCE_MASK 0x00010000 10086 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ0_FORCE_ALIGN 0 10087 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ0_FORCE_BITS 1 10088 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ0_FORCE_SHIFT 16 10089 10090 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DQ0 :: reserved1 [15:13] */ 10091 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ0_RESERVED1_MASK 0x0000e000 10092 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ0_RESERVED1_ALIGN 0 10093 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ0_RESERVED1_BITS 3 10094 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ0_RESERVED1_SHIFT 13 10095 10096 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DQ0 :: ADJ_EN [12:12] */ 10097 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ0_ADJ_EN_MASK 0x00001000 10098 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ0_ADJ_EN_ALIGN 0 10099 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ0_ADJ_EN_BITS 1 10100 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ0_ADJ_EN_SHIFT 12 10101 10102 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DQ0 :: reserved2 [11:09] */ 10103 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ0_RESERVED2_MASK 0x00000e00 10104 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ0_RESERVED2_ALIGN 0 10105 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ0_RESERVED2_BITS 3 10106 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ0_RESERVED2_SHIFT 9 10107 10108 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DQ0 :: VDL_STEP [08:00] */ 10109 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ0_VDL_STEP_MASK 0x000001ff 10110 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ0_VDL_STEP_ALIGN 0 10111 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ0_VDL_STEP_BITS 9 10112 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ0_VDL_STEP_SHIFT 0 10113 10114 10115 /**************************************************************************** 10116 * DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DQ1 10117 */ 10118 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DQ1 :: BUSY [31:31] */ 10119 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ1_BUSY_MASK 0x80000000 10120 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ1_BUSY_ALIGN 0 10121 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ1_BUSY_BITS 1 10122 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ1_BUSY_SHIFT 31 10123 10124 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DQ1 :: reserved0 [30:17] */ 10125 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ1_RESERVED0_MASK 0x7ffe0000 10126 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ1_RESERVED0_ALIGN 0 10127 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ1_RESERVED0_BITS 14 10128 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ1_RESERVED0_SHIFT 17 10129 10130 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DQ1 :: FORCE [16:16] */ 10131 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ1_FORCE_MASK 0x00010000 10132 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ1_FORCE_ALIGN 0 10133 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ1_FORCE_BITS 1 10134 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ1_FORCE_SHIFT 16 10135 10136 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DQ1 :: reserved1 [15:13] */ 10137 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ1_RESERVED1_MASK 0x0000e000 10138 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ1_RESERVED1_ALIGN 0 10139 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ1_RESERVED1_BITS 3 10140 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ1_RESERVED1_SHIFT 13 10141 10142 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DQ1 :: ADJ_EN [12:12] */ 10143 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ1_ADJ_EN_MASK 0x00001000 10144 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ1_ADJ_EN_ALIGN 0 10145 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ1_ADJ_EN_BITS 1 10146 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ1_ADJ_EN_SHIFT 12 10147 10148 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DQ1 :: reserved2 [11:09] */ 10149 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ1_RESERVED2_MASK 0x00000e00 10150 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ1_RESERVED2_ALIGN 0 10151 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ1_RESERVED2_BITS 3 10152 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ1_RESERVED2_SHIFT 9 10153 10154 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DQ1 :: VDL_STEP [08:00] */ 10155 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ1_VDL_STEP_MASK 0x000001ff 10156 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ1_VDL_STEP_ALIGN 0 10157 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ1_VDL_STEP_BITS 9 10158 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ1_VDL_STEP_SHIFT 0 10159 10160 10161 /**************************************************************************** 10162 * DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DQ2 10163 */ 10164 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DQ2 :: BUSY [31:31] */ 10165 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ2_BUSY_MASK 0x80000000 10166 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ2_BUSY_ALIGN 0 10167 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ2_BUSY_BITS 1 10168 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ2_BUSY_SHIFT 31 10169 10170 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DQ2 :: reserved0 [30:17] */ 10171 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ2_RESERVED0_MASK 0x7ffe0000 10172 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ2_RESERVED0_ALIGN 0 10173 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ2_RESERVED0_BITS 14 10174 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ2_RESERVED0_SHIFT 17 10175 10176 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DQ2 :: FORCE [16:16] */ 10177 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ2_FORCE_MASK 0x00010000 10178 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ2_FORCE_ALIGN 0 10179 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ2_FORCE_BITS 1 10180 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ2_FORCE_SHIFT 16 10181 10182 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DQ2 :: reserved1 [15:13] */ 10183 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ2_RESERVED1_MASK 0x0000e000 10184 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ2_RESERVED1_ALIGN 0 10185 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ2_RESERVED1_BITS 3 10186 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ2_RESERVED1_SHIFT 13 10187 10188 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DQ2 :: ADJ_EN [12:12] */ 10189 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ2_ADJ_EN_MASK 0x00001000 10190 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ2_ADJ_EN_ALIGN 0 10191 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ2_ADJ_EN_BITS 1 10192 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ2_ADJ_EN_SHIFT 12 10193 10194 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DQ2 :: reserved2 [11:09] */ 10195 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ2_RESERVED2_MASK 0x00000e00 10196 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ2_RESERVED2_ALIGN 0 10197 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ2_RESERVED2_BITS 3 10198 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ2_RESERVED2_SHIFT 9 10199 10200 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DQ2 :: VDL_STEP [08:00] */ 10201 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ2_VDL_STEP_MASK 0x000001ff 10202 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ2_VDL_STEP_ALIGN 0 10203 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ2_VDL_STEP_BITS 9 10204 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ2_VDL_STEP_SHIFT 0 10205 10206 10207 /**************************************************************************** 10208 * DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DQ3 10209 */ 10210 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DQ3 :: BUSY [31:31] */ 10211 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ3_BUSY_MASK 0x80000000 10212 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ3_BUSY_ALIGN 0 10213 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ3_BUSY_BITS 1 10214 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ3_BUSY_SHIFT 31 10215 10216 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DQ3 :: reserved0 [30:17] */ 10217 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ3_RESERVED0_MASK 0x7ffe0000 10218 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ3_RESERVED0_ALIGN 0 10219 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ3_RESERVED0_BITS 14 10220 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ3_RESERVED0_SHIFT 17 10221 10222 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DQ3 :: FORCE [16:16] */ 10223 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ3_FORCE_MASK 0x00010000 10224 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ3_FORCE_ALIGN 0 10225 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ3_FORCE_BITS 1 10226 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ3_FORCE_SHIFT 16 10227 10228 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DQ3 :: reserved1 [15:13] */ 10229 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ3_RESERVED1_MASK 0x0000e000 10230 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ3_RESERVED1_ALIGN 0 10231 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ3_RESERVED1_BITS 3 10232 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ3_RESERVED1_SHIFT 13 10233 10234 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DQ3 :: ADJ_EN [12:12] */ 10235 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ3_ADJ_EN_MASK 0x00001000 10236 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ3_ADJ_EN_ALIGN 0 10237 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ3_ADJ_EN_BITS 1 10238 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ3_ADJ_EN_SHIFT 12 10239 10240 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DQ3 :: reserved2 [11:09] */ 10241 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ3_RESERVED2_MASK 0x00000e00 10242 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ3_RESERVED2_ALIGN 0 10243 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ3_RESERVED2_BITS 3 10244 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ3_RESERVED2_SHIFT 9 10245 10246 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DQ3 :: VDL_STEP [08:00] */ 10247 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ3_VDL_STEP_MASK 0x000001ff 10248 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ3_VDL_STEP_ALIGN 0 10249 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ3_VDL_STEP_BITS 9 10250 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ3_VDL_STEP_SHIFT 0 10251 10252 10253 /**************************************************************************** 10254 * DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DQ4 10255 */ 10256 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DQ4 :: BUSY [31:31] */ 10257 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ4_BUSY_MASK 0x80000000 10258 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ4_BUSY_ALIGN 0 10259 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ4_BUSY_BITS 1 10260 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ4_BUSY_SHIFT 31 10261 10262 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DQ4 :: reserved0 [30:17] */ 10263 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ4_RESERVED0_MASK 0x7ffe0000 10264 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ4_RESERVED0_ALIGN 0 10265 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ4_RESERVED0_BITS 14 10266 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ4_RESERVED0_SHIFT 17 10267 10268 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DQ4 :: FORCE [16:16] */ 10269 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ4_FORCE_MASK 0x00010000 10270 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ4_FORCE_ALIGN 0 10271 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ4_FORCE_BITS 1 10272 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ4_FORCE_SHIFT 16 10273 10274 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DQ4 :: reserved1 [15:13] */ 10275 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ4_RESERVED1_MASK 0x0000e000 10276 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ4_RESERVED1_ALIGN 0 10277 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ4_RESERVED1_BITS 3 10278 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ4_RESERVED1_SHIFT 13 10279 10280 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DQ4 :: ADJ_EN [12:12] */ 10281 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ4_ADJ_EN_MASK 0x00001000 10282 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ4_ADJ_EN_ALIGN 0 10283 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ4_ADJ_EN_BITS 1 10284 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ4_ADJ_EN_SHIFT 12 10285 10286 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DQ4 :: reserved2 [11:09] */ 10287 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ4_RESERVED2_MASK 0x00000e00 10288 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ4_RESERVED2_ALIGN 0 10289 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ4_RESERVED2_BITS 3 10290 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ4_RESERVED2_SHIFT 9 10291 10292 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DQ4 :: VDL_STEP [08:00] */ 10293 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ4_VDL_STEP_MASK 0x000001ff 10294 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ4_VDL_STEP_ALIGN 0 10295 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ4_VDL_STEP_BITS 9 10296 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ4_VDL_STEP_SHIFT 0 10297 10298 10299 /**************************************************************************** 10300 * DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DQ5 10301 */ 10302 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DQ5 :: BUSY [31:31] */ 10303 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ5_BUSY_MASK 0x80000000 10304 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ5_BUSY_ALIGN 0 10305 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ5_BUSY_BITS 1 10306 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ5_BUSY_SHIFT 31 10307 10308 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DQ5 :: reserved0 [30:17] */ 10309 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ5_RESERVED0_MASK 0x7ffe0000 10310 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ5_RESERVED0_ALIGN 0 10311 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ5_RESERVED0_BITS 14 10312 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ5_RESERVED0_SHIFT 17 10313 10314 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DQ5 :: FORCE [16:16] */ 10315 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ5_FORCE_MASK 0x00010000 10316 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ5_FORCE_ALIGN 0 10317 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ5_FORCE_BITS 1 10318 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ5_FORCE_SHIFT 16 10319 10320 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DQ5 :: reserved1 [15:13] */ 10321 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ5_RESERVED1_MASK 0x0000e000 10322 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ5_RESERVED1_ALIGN 0 10323 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ5_RESERVED1_BITS 3 10324 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ5_RESERVED1_SHIFT 13 10325 10326 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DQ5 :: ADJ_EN [12:12] */ 10327 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ5_ADJ_EN_MASK 0x00001000 10328 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ5_ADJ_EN_ALIGN 0 10329 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ5_ADJ_EN_BITS 1 10330 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ5_ADJ_EN_SHIFT 12 10331 10332 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DQ5 :: reserved2 [11:09] */ 10333 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ5_RESERVED2_MASK 0x00000e00 10334 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ5_RESERVED2_ALIGN 0 10335 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ5_RESERVED2_BITS 3 10336 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ5_RESERVED2_SHIFT 9 10337 10338 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DQ5 :: VDL_STEP [08:00] */ 10339 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ5_VDL_STEP_MASK 0x000001ff 10340 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ5_VDL_STEP_ALIGN 0 10341 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ5_VDL_STEP_BITS 9 10342 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ5_VDL_STEP_SHIFT 0 10343 10344 10345 /**************************************************************************** 10346 * DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DQ6 10347 */ 10348 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DQ6 :: BUSY [31:31] */ 10349 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ6_BUSY_MASK 0x80000000 10350 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ6_BUSY_ALIGN 0 10351 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ6_BUSY_BITS 1 10352 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ6_BUSY_SHIFT 31 10353 10354 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DQ6 :: reserved0 [30:17] */ 10355 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ6_RESERVED0_MASK 0x7ffe0000 10356 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ6_RESERVED0_ALIGN 0 10357 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ6_RESERVED0_BITS 14 10358 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ6_RESERVED0_SHIFT 17 10359 10360 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DQ6 :: FORCE [16:16] */ 10361 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ6_FORCE_MASK 0x00010000 10362 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ6_FORCE_ALIGN 0 10363 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ6_FORCE_BITS 1 10364 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ6_FORCE_SHIFT 16 10365 10366 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DQ6 :: reserved1 [15:13] */ 10367 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ6_RESERVED1_MASK 0x0000e000 10368 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ6_RESERVED1_ALIGN 0 10369 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ6_RESERVED1_BITS 3 10370 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ6_RESERVED1_SHIFT 13 10371 10372 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DQ6 :: ADJ_EN [12:12] */ 10373 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ6_ADJ_EN_MASK 0x00001000 10374 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ6_ADJ_EN_ALIGN 0 10375 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ6_ADJ_EN_BITS 1 10376 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ6_ADJ_EN_SHIFT 12 10377 10378 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DQ6 :: reserved2 [11:09] */ 10379 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ6_RESERVED2_MASK 0x00000e00 10380 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ6_RESERVED2_ALIGN 0 10381 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ6_RESERVED2_BITS 3 10382 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ6_RESERVED2_SHIFT 9 10383 10384 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DQ6 :: VDL_STEP [08:00] */ 10385 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ6_VDL_STEP_MASK 0x000001ff 10386 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ6_VDL_STEP_ALIGN 0 10387 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ6_VDL_STEP_BITS 9 10388 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ6_VDL_STEP_SHIFT 0 10389 10390 10391 /**************************************************************************** 10392 * DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DQ7 10393 */ 10394 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DQ7 :: BUSY [31:31] */ 10395 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ7_BUSY_MASK 0x80000000 10396 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ7_BUSY_ALIGN 0 10397 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ7_BUSY_BITS 1 10398 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ7_BUSY_SHIFT 31 10399 10400 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DQ7 :: reserved0 [30:17] */ 10401 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ7_RESERVED0_MASK 0x7ffe0000 10402 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ7_RESERVED0_ALIGN 0 10403 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ7_RESERVED0_BITS 14 10404 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ7_RESERVED0_SHIFT 17 10405 10406 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DQ7 :: FORCE [16:16] */ 10407 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ7_FORCE_MASK 0x00010000 10408 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ7_FORCE_ALIGN 0 10409 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ7_FORCE_BITS 1 10410 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ7_FORCE_SHIFT 16 10411 10412 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DQ7 :: reserved1 [15:13] */ 10413 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ7_RESERVED1_MASK 0x0000e000 10414 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ7_RESERVED1_ALIGN 0 10415 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ7_RESERVED1_BITS 3 10416 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ7_RESERVED1_SHIFT 13 10417 10418 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DQ7 :: ADJ_EN [12:12] */ 10419 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ7_ADJ_EN_MASK 0x00001000 10420 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ7_ADJ_EN_ALIGN 0 10421 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ7_ADJ_EN_BITS 1 10422 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ7_ADJ_EN_SHIFT 12 10423 10424 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DQ7 :: reserved2 [11:09] */ 10425 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ7_RESERVED2_MASK 0x00000e00 10426 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ7_RESERVED2_ALIGN 0 10427 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ7_RESERVED2_BITS 3 10428 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ7_RESERVED2_SHIFT 9 10429 10430 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DQ7 :: VDL_STEP [08:00] */ 10431 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ7_VDL_STEP_MASK 0x000001ff 10432 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ7_VDL_STEP_ALIGN 0 10433 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ7_VDL_STEP_BITS 9 10434 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ7_VDL_STEP_SHIFT 0 10435 10436 10437 /**************************************************************************** 10438 * DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DM 10439 */ 10440 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DM :: BUSY [31:31] */ 10441 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DM_BUSY_MASK 0x80000000 10442 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DM_BUSY_ALIGN 0 10443 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DM_BUSY_BITS 1 10444 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DM_BUSY_SHIFT 31 10445 10446 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DM :: reserved0 [30:17] */ 10447 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DM_RESERVED0_MASK 0x7ffe0000 10448 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DM_RESERVED0_ALIGN 0 10449 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DM_RESERVED0_BITS 14 10450 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DM_RESERVED0_SHIFT 17 10451 10452 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DM :: FORCE [16:16] */ 10453 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DM_FORCE_MASK 0x00010000 10454 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DM_FORCE_ALIGN 0 10455 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DM_FORCE_BITS 1 10456 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DM_FORCE_SHIFT 16 10457 10458 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DM :: reserved1 [15:13] */ 10459 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DM_RESERVED1_MASK 0x0000e000 10460 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DM_RESERVED1_ALIGN 0 10461 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DM_RESERVED1_BITS 3 10462 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DM_RESERVED1_SHIFT 13 10463 10464 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DM :: ADJ_EN [12:12] */ 10465 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DM_ADJ_EN_MASK 0x00001000 10466 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DM_ADJ_EN_ALIGN 0 10467 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DM_ADJ_EN_BITS 1 10468 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DM_ADJ_EN_SHIFT 12 10469 10470 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DM :: reserved2 [11:09] */ 10471 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DM_RESERVED2_MASK 0x00000e00 10472 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DM_RESERVED2_ALIGN 0 10473 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DM_RESERVED2_BITS 3 10474 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DM_RESERVED2_SHIFT 9 10475 10476 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DM :: VDL_STEP [08:00] */ 10477 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DM_VDL_STEP_MASK 0x000001ff 10478 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DM_VDL_STEP_ALIGN 0 10479 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DM_VDL_STEP_BITS 9 10480 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DM_VDL_STEP_SHIFT 0 10481 10482 10483 /**************************************************************************** 10484 * DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_ALERT 10485 */ 10486 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_ALERT :: BUSY [31:31] */ 10487 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_ALERT_BUSY_MASK 0x80000000 10488 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_ALERT_BUSY_ALIGN 0 10489 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_ALERT_BUSY_BITS 1 10490 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_ALERT_BUSY_SHIFT 31 10491 10492 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_ALERT :: reserved0 [30:17] */ 10493 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_ALERT_RESERVED0_MASK 0x7ffe0000 10494 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_ALERT_RESERVED0_ALIGN 0 10495 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_ALERT_RESERVED0_BITS 14 10496 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_ALERT_RESERVED0_SHIFT 17 10497 10498 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_ALERT :: FORCE [16:16] */ 10499 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_ALERT_FORCE_MASK 0x00010000 10500 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_ALERT_FORCE_ALIGN 0 10501 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_ALERT_FORCE_BITS 1 10502 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_ALERT_FORCE_SHIFT 16 10503 10504 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_ALERT :: reserved1 [15:13] */ 10505 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_ALERT_RESERVED1_MASK 0x0000e000 10506 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_ALERT_RESERVED1_ALIGN 0 10507 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_ALERT_RESERVED1_BITS 3 10508 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_ALERT_RESERVED1_SHIFT 13 10509 10510 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_ALERT :: ADJ_EN [12:12] */ 10511 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_ALERT_ADJ_EN_MASK 0x00001000 10512 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_ALERT_ADJ_EN_ALIGN 0 10513 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_ALERT_ADJ_EN_BITS 1 10514 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_ALERT_ADJ_EN_SHIFT 12 10515 10516 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_ALERT :: reserved2 [11:09] */ 10517 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_ALERT_RESERVED2_MASK 0x00000e00 10518 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_ALERT_RESERVED2_ALIGN 0 10519 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_ALERT_RESERVED2_BITS 3 10520 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_ALERT_RESERVED2_SHIFT 9 10521 10522 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_ALERT :: VDL_STEP [08:00] */ 10523 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_ALERT_VDL_STEP_MASK 0x000001ff 10524 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_ALERT_VDL_STEP_ALIGN 0 10525 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_ALERT_VDL_STEP_BITS 9 10526 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_ALERT_VDL_STEP_SHIFT 0 10527 10528 10529 /**************************************************************************** 10530 * DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQSP 10531 */ 10532 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQSP :: BUSY [31:31] */ 10533 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSP_BUSY_MASK 0x80000000 10534 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSP_BUSY_ALIGN 0 10535 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSP_BUSY_BITS 1 10536 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSP_BUSY_SHIFT 31 10537 10538 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQSP :: reserved0 [30:17] */ 10539 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSP_RESERVED0_MASK 0x7ffe0000 10540 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSP_RESERVED0_ALIGN 0 10541 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSP_RESERVED0_BITS 14 10542 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSP_RESERVED0_SHIFT 17 10543 10544 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQSP :: FORCE [16:16] */ 10545 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSP_FORCE_MASK 0x00010000 10546 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSP_FORCE_ALIGN 0 10547 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSP_FORCE_BITS 1 10548 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSP_FORCE_SHIFT 16 10549 10550 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQSP :: reserved1 [15:13] */ 10551 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSP_RESERVED1_MASK 0x0000e000 10552 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSP_RESERVED1_ALIGN 0 10553 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSP_RESERVED1_BITS 3 10554 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSP_RESERVED1_SHIFT 13 10555 10556 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQSP :: ADJ_EN [12:12] */ 10557 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSP_ADJ_EN_MASK 0x00001000 10558 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSP_ADJ_EN_ALIGN 0 10559 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSP_ADJ_EN_BITS 1 10560 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSP_ADJ_EN_SHIFT 12 10561 10562 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQSP :: reserved2 [11:08] */ 10563 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSP_RESERVED2_MASK 0x00000f00 10564 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSP_RESERVED2_ALIGN 0 10565 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSP_RESERVED2_BITS 4 10566 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSP_RESERVED2_SHIFT 8 10567 10568 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQSP :: VDL_STEP [07:00] */ 10569 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSP_VDL_STEP_MASK 0x000000ff 10570 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSP_VDL_STEP_ALIGN 0 10571 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSP_VDL_STEP_BITS 8 10572 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSP_VDL_STEP_SHIFT 0 10573 10574 10575 /**************************************************************************** 10576 * DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQSN 10577 */ 10578 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQSN :: BUSY [31:31] */ 10579 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSN_BUSY_MASK 0x80000000 10580 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSN_BUSY_ALIGN 0 10581 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSN_BUSY_BITS 1 10582 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSN_BUSY_SHIFT 31 10583 10584 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQSN :: reserved0 [30:17] */ 10585 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSN_RESERVED0_MASK 0x7ffe0000 10586 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSN_RESERVED0_ALIGN 0 10587 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSN_RESERVED0_BITS 14 10588 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSN_RESERVED0_SHIFT 17 10589 10590 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQSN :: FORCE [16:16] */ 10591 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSN_FORCE_MASK 0x00010000 10592 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSN_FORCE_ALIGN 0 10593 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSN_FORCE_BITS 1 10594 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSN_FORCE_SHIFT 16 10595 10596 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQSN :: reserved1 [15:13] */ 10597 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSN_RESERVED1_MASK 0x0000e000 10598 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSN_RESERVED1_ALIGN 0 10599 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSN_RESERVED1_BITS 3 10600 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSN_RESERVED1_SHIFT 13 10601 10602 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQSN :: ADJ_EN [12:12] */ 10603 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSN_ADJ_EN_MASK 0x00001000 10604 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSN_ADJ_EN_ALIGN 0 10605 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSN_ADJ_EN_BITS 1 10606 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSN_ADJ_EN_SHIFT 12 10607 10608 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQSN :: reserved2 [11:08] */ 10609 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSN_RESERVED2_MASK 0x00000f00 10610 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSN_RESERVED2_ALIGN 0 10611 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSN_RESERVED2_BITS 4 10612 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSN_RESERVED2_SHIFT 8 10613 10614 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQSN :: VDL_STEP [07:00] */ 10615 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSN_VDL_STEP_MASK 0x000000ff 10616 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSN_VDL_STEP_ALIGN 0 10617 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSN_VDL_STEP_BITS 8 10618 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSN_VDL_STEP_SHIFT 0 10619 10620 10621 /**************************************************************************** 10622 * DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ0P 10623 */ 10624 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ0P :: BUSY [31:31] */ 10625 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0P_BUSY_MASK 0x80000000 10626 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0P_BUSY_ALIGN 0 10627 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0P_BUSY_BITS 1 10628 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0P_BUSY_SHIFT 31 10629 10630 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ0P :: reserved0 [30:17] */ 10631 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0P_RESERVED0_MASK 0x7ffe0000 10632 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0P_RESERVED0_ALIGN 0 10633 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0P_RESERVED0_BITS 14 10634 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0P_RESERVED0_SHIFT 17 10635 10636 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ0P :: FORCE [16:16] */ 10637 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0P_FORCE_MASK 0x00010000 10638 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0P_FORCE_ALIGN 0 10639 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0P_FORCE_BITS 1 10640 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0P_FORCE_SHIFT 16 10641 10642 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ0P :: reserved1 [15:13] */ 10643 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0P_RESERVED1_MASK 0x0000e000 10644 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0P_RESERVED1_ALIGN 0 10645 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0P_RESERVED1_BITS 3 10646 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0P_RESERVED1_SHIFT 13 10647 10648 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ0P :: ADJ_EN [12:12] */ 10649 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0P_ADJ_EN_MASK 0x00001000 10650 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0P_ADJ_EN_ALIGN 0 10651 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0P_ADJ_EN_BITS 1 10652 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0P_ADJ_EN_SHIFT 12 10653 10654 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ0P :: reserved2 [11:08] */ 10655 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0P_RESERVED2_MASK 0x00000f00 10656 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0P_RESERVED2_ALIGN 0 10657 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0P_RESERVED2_BITS 4 10658 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0P_RESERVED2_SHIFT 8 10659 10660 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ0P :: VDL_STEP [07:00] */ 10661 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0P_VDL_STEP_MASK 0x000000ff 10662 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0P_VDL_STEP_ALIGN 0 10663 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0P_VDL_STEP_BITS 8 10664 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0P_VDL_STEP_SHIFT 0 10665 10666 10667 /**************************************************************************** 10668 * DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ0N 10669 */ 10670 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ0N :: BUSY [31:31] */ 10671 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0N_BUSY_MASK 0x80000000 10672 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0N_BUSY_ALIGN 0 10673 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0N_BUSY_BITS 1 10674 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0N_BUSY_SHIFT 31 10675 10676 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ0N :: reserved0 [30:17] */ 10677 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0N_RESERVED0_MASK 0x7ffe0000 10678 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0N_RESERVED0_ALIGN 0 10679 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0N_RESERVED0_BITS 14 10680 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0N_RESERVED0_SHIFT 17 10681 10682 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ0N :: FORCE [16:16] */ 10683 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0N_FORCE_MASK 0x00010000 10684 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0N_FORCE_ALIGN 0 10685 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0N_FORCE_BITS 1 10686 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0N_FORCE_SHIFT 16 10687 10688 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ0N :: reserved1 [15:13] */ 10689 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0N_RESERVED1_MASK 0x0000e000 10690 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0N_RESERVED1_ALIGN 0 10691 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0N_RESERVED1_BITS 3 10692 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0N_RESERVED1_SHIFT 13 10693 10694 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ0N :: ADJ_EN [12:12] */ 10695 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0N_ADJ_EN_MASK 0x00001000 10696 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0N_ADJ_EN_ALIGN 0 10697 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0N_ADJ_EN_BITS 1 10698 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0N_ADJ_EN_SHIFT 12 10699 10700 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ0N :: reserved2 [11:08] */ 10701 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0N_RESERVED2_MASK 0x00000f00 10702 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0N_RESERVED2_ALIGN 0 10703 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0N_RESERVED2_BITS 4 10704 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0N_RESERVED2_SHIFT 8 10705 10706 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ0N :: VDL_STEP [07:00] */ 10707 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0N_VDL_STEP_MASK 0x000000ff 10708 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0N_VDL_STEP_ALIGN 0 10709 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0N_VDL_STEP_BITS 8 10710 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0N_VDL_STEP_SHIFT 0 10711 10712 10713 /**************************************************************************** 10714 * DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ1P 10715 */ 10716 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ1P :: BUSY [31:31] */ 10717 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1P_BUSY_MASK 0x80000000 10718 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1P_BUSY_ALIGN 0 10719 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1P_BUSY_BITS 1 10720 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1P_BUSY_SHIFT 31 10721 10722 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ1P :: reserved0 [30:17] */ 10723 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1P_RESERVED0_MASK 0x7ffe0000 10724 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1P_RESERVED0_ALIGN 0 10725 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1P_RESERVED0_BITS 14 10726 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1P_RESERVED0_SHIFT 17 10727 10728 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ1P :: FORCE [16:16] */ 10729 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1P_FORCE_MASK 0x00010000 10730 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1P_FORCE_ALIGN 0 10731 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1P_FORCE_BITS 1 10732 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1P_FORCE_SHIFT 16 10733 10734 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ1P :: reserved1 [15:13] */ 10735 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1P_RESERVED1_MASK 0x0000e000 10736 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1P_RESERVED1_ALIGN 0 10737 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1P_RESERVED1_BITS 3 10738 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1P_RESERVED1_SHIFT 13 10739 10740 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ1P :: ADJ_EN [12:12] */ 10741 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1P_ADJ_EN_MASK 0x00001000 10742 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1P_ADJ_EN_ALIGN 0 10743 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1P_ADJ_EN_BITS 1 10744 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1P_ADJ_EN_SHIFT 12 10745 10746 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ1P :: reserved2 [11:08] */ 10747 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1P_RESERVED2_MASK 0x00000f00 10748 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1P_RESERVED2_ALIGN 0 10749 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1P_RESERVED2_BITS 4 10750 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1P_RESERVED2_SHIFT 8 10751 10752 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ1P :: VDL_STEP [07:00] */ 10753 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1P_VDL_STEP_MASK 0x000000ff 10754 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1P_VDL_STEP_ALIGN 0 10755 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1P_VDL_STEP_BITS 8 10756 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1P_VDL_STEP_SHIFT 0 10757 10758 10759 /**************************************************************************** 10760 * DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ1N 10761 */ 10762 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ1N :: BUSY [31:31] */ 10763 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1N_BUSY_MASK 0x80000000 10764 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1N_BUSY_ALIGN 0 10765 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1N_BUSY_BITS 1 10766 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1N_BUSY_SHIFT 31 10767 10768 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ1N :: reserved0 [30:17] */ 10769 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1N_RESERVED0_MASK 0x7ffe0000 10770 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1N_RESERVED0_ALIGN 0 10771 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1N_RESERVED0_BITS 14 10772 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1N_RESERVED0_SHIFT 17 10773 10774 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ1N :: FORCE [16:16] */ 10775 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1N_FORCE_MASK 0x00010000 10776 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1N_FORCE_ALIGN 0 10777 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1N_FORCE_BITS 1 10778 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1N_FORCE_SHIFT 16 10779 10780 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ1N :: reserved1 [15:13] */ 10781 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1N_RESERVED1_MASK 0x0000e000 10782 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1N_RESERVED1_ALIGN 0 10783 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1N_RESERVED1_BITS 3 10784 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1N_RESERVED1_SHIFT 13 10785 10786 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ1N :: ADJ_EN [12:12] */ 10787 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1N_ADJ_EN_MASK 0x00001000 10788 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1N_ADJ_EN_ALIGN 0 10789 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1N_ADJ_EN_BITS 1 10790 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1N_ADJ_EN_SHIFT 12 10791 10792 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ1N :: reserved2 [11:08] */ 10793 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1N_RESERVED2_MASK 0x00000f00 10794 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1N_RESERVED2_ALIGN 0 10795 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1N_RESERVED2_BITS 4 10796 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1N_RESERVED2_SHIFT 8 10797 10798 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ1N :: VDL_STEP [07:00] */ 10799 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1N_VDL_STEP_MASK 0x000000ff 10800 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1N_VDL_STEP_ALIGN 0 10801 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1N_VDL_STEP_BITS 8 10802 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1N_VDL_STEP_SHIFT 0 10803 10804 10805 /**************************************************************************** 10806 * DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ2P 10807 */ 10808 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ2P :: BUSY [31:31] */ 10809 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2P_BUSY_MASK 0x80000000 10810 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2P_BUSY_ALIGN 0 10811 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2P_BUSY_BITS 1 10812 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2P_BUSY_SHIFT 31 10813 10814 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ2P :: reserved0 [30:17] */ 10815 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2P_RESERVED0_MASK 0x7ffe0000 10816 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2P_RESERVED0_ALIGN 0 10817 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2P_RESERVED0_BITS 14 10818 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2P_RESERVED0_SHIFT 17 10819 10820 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ2P :: FORCE [16:16] */ 10821 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2P_FORCE_MASK 0x00010000 10822 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2P_FORCE_ALIGN 0 10823 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2P_FORCE_BITS 1 10824 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2P_FORCE_SHIFT 16 10825 10826 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ2P :: reserved1 [15:13] */ 10827 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2P_RESERVED1_MASK 0x0000e000 10828 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2P_RESERVED1_ALIGN 0 10829 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2P_RESERVED1_BITS 3 10830 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2P_RESERVED1_SHIFT 13 10831 10832 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ2P :: ADJ_EN [12:12] */ 10833 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2P_ADJ_EN_MASK 0x00001000 10834 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2P_ADJ_EN_ALIGN 0 10835 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2P_ADJ_EN_BITS 1 10836 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2P_ADJ_EN_SHIFT 12 10837 10838 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ2P :: reserved2 [11:08] */ 10839 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2P_RESERVED2_MASK 0x00000f00 10840 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2P_RESERVED2_ALIGN 0 10841 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2P_RESERVED2_BITS 4 10842 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2P_RESERVED2_SHIFT 8 10843 10844 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ2P :: VDL_STEP [07:00] */ 10845 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2P_VDL_STEP_MASK 0x000000ff 10846 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2P_VDL_STEP_ALIGN 0 10847 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2P_VDL_STEP_BITS 8 10848 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2P_VDL_STEP_SHIFT 0 10849 10850 10851 /**************************************************************************** 10852 * DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ2N 10853 */ 10854 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ2N :: BUSY [31:31] */ 10855 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2N_BUSY_MASK 0x80000000 10856 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2N_BUSY_ALIGN 0 10857 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2N_BUSY_BITS 1 10858 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2N_BUSY_SHIFT 31 10859 10860 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ2N :: reserved0 [30:17] */ 10861 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2N_RESERVED0_MASK 0x7ffe0000 10862 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2N_RESERVED0_ALIGN 0 10863 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2N_RESERVED0_BITS 14 10864 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2N_RESERVED0_SHIFT 17 10865 10866 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ2N :: FORCE [16:16] */ 10867 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2N_FORCE_MASK 0x00010000 10868 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2N_FORCE_ALIGN 0 10869 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2N_FORCE_BITS 1 10870 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2N_FORCE_SHIFT 16 10871 10872 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ2N :: reserved1 [15:13] */ 10873 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2N_RESERVED1_MASK 0x0000e000 10874 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2N_RESERVED1_ALIGN 0 10875 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2N_RESERVED1_BITS 3 10876 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2N_RESERVED1_SHIFT 13 10877 10878 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ2N :: ADJ_EN [12:12] */ 10879 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2N_ADJ_EN_MASK 0x00001000 10880 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2N_ADJ_EN_ALIGN 0 10881 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2N_ADJ_EN_BITS 1 10882 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2N_ADJ_EN_SHIFT 12 10883 10884 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ2N :: reserved2 [11:08] */ 10885 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2N_RESERVED2_MASK 0x00000f00 10886 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2N_RESERVED2_ALIGN 0 10887 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2N_RESERVED2_BITS 4 10888 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2N_RESERVED2_SHIFT 8 10889 10890 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ2N :: VDL_STEP [07:00] */ 10891 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2N_VDL_STEP_MASK 0x000000ff 10892 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2N_VDL_STEP_ALIGN 0 10893 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2N_VDL_STEP_BITS 8 10894 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2N_VDL_STEP_SHIFT 0 10895 10896 10897 /**************************************************************************** 10898 * DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ3P 10899 */ 10900 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ3P :: BUSY [31:31] */ 10901 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3P_BUSY_MASK 0x80000000 10902 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3P_BUSY_ALIGN 0 10903 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3P_BUSY_BITS 1 10904 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3P_BUSY_SHIFT 31 10905 10906 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ3P :: reserved0 [30:17] */ 10907 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3P_RESERVED0_MASK 0x7ffe0000 10908 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3P_RESERVED0_ALIGN 0 10909 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3P_RESERVED0_BITS 14 10910 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3P_RESERVED0_SHIFT 17 10911 10912 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ3P :: FORCE [16:16] */ 10913 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3P_FORCE_MASK 0x00010000 10914 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3P_FORCE_ALIGN 0 10915 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3P_FORCE_BITS 1 10916 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3P_FORCE_SHIFT 16 10917 10918 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ3P :: reserved1 [15:13] */ 10919 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3P_RESERVED1_MASK 0x0000e000 10920 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3P_RESERVED1_ALIGN 0 10921 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3P_RESERVED1_BITS 3 10922 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3P_RESERVED1_SHIFT 13 10923 10924 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ3P :: ADJ_EN [12:12] */ 10925 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3P_ADJ_EN_MASK 0x00001000 10926 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3P_ADJ_EN_ALIGN 0 10927 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3P_ADJ_EN_BITS 1 10928 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3P_ADJ_EN_SHIFT 12 10929 10930 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ3P :: reserved2 [11:08] */ 10931 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3P_RESERVED2_MASK 0x00000f00 10932 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3P_RESERVED2_ALIGN 0 10933 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3P_RESERVED2_BITS 4 10934 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3P_RESERVED2_SHIFT 8 10935 10936 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ3P :: VDL_STEP [07:00] */ 10937 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3P_VDL_STEP_MASK 0x000000ff 10938 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3P_VDL_STEP_ALIGN 0 10939 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3P_VDL_STEP_BITS 8 10940 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3P_VDL_STEP_SHIFT 0 10941 10942 10943 /**************************************************************************** 10944 * DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ3N 10945 */ 10946 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ3N :: BUSY [31:31] */ 10947 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3N_BUSY_MASK 0x80000000 10948 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3N_BUSY_ALIGN 0 10949 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3N_BUSY_BITS 1 10950 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3N_BUSY_SHIFT 31 10951 10952 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ3N :: reserved0 [30:17] */ 10953 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3N_RESERVED0_MASK 0x7ffe0000 10954 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3N_RESERVED0_ALIGN 0 10955 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3N_RESERVED0_BITS 14 10956 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3N_RESERVED0_SHIFT 17 10957 10958 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ3N :: FORCE [16:16] */ 10959 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3N_FORCE_MASK 0x00010000 10960 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3N_FORCE_ALIGN 0 10961 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3N_FORCE_BITS 1 10962 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3N_FORCE_SHIFT 16 10963 10964 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ3N :: reserved1 [15:13] */ 10965 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3N_RESERVED1_MASK 0x0000e000 10966 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3N_RESERVED1_ALIGN 0 10967 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3N_RESERVED1_BITS 3 10968 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3N_RESERVED1_SHIFT 13 10969 10970 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ3N :: ADJ_EN [12:12] */ 10971 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3N_ADJ_EN_MASK 0x00001000 10972 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3N_ADJ_EN_ALIGN 0 10973 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3N_ADJ_EN_BITS 1 10974 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3N_ADJ_EN_SHIFT 12 10975 10976 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ3N :: reserved2 [11:08] */ 10977 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3N_RESERVED2_MASK 0x00000f00 10978 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3N_RESERVED2_ALIGN 0 10979 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3N_RESERVED2_BITS 4 10980 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3N_RESERVED2_SHIFT 8 10981 10982 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ3N :: VDL_STEP [07:00] */ 10983 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3N_VDL_STEP_MASK 0x000000ff 10984 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3N_VDL_STEP_ALIGN 0 10985 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3N_VDL_STEP_BITS 8 10986 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3N_VDL_STEP_SHIFT 0 10987 10988 10989 /**************************************************************************** 10990 * DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ4P 10991 */ 10992 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ4P :: BUSY [31:31] */ 10993 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4P_BUSY_MASK 0x80000000 10994 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4P_BUSY_ALIGN 0 10995 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4P_BUSY_BITS 1 10996 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4P_BUSY_SHIFT 31 10997 10998 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ4P :: reserved0 [30:17] */ 10999 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4P_RESERVED0_MASK 0x7ffe0000 11000 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4P_RESERVED0_ALIGN 0 11001 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4P_RESERVED0_BITS 14 11002 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4P_RESERVED0_SHIFT 17 11003 11004 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ4P :: FORCE [16:16] */ 11005 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4P_FORCE_MASK 0x00010000 11006 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4P_FORCE_ALIGN 0 11007 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4P_FORCE_BITS 1 11008 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4P_FORCE_SHIFT 16 11009 11010 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ4P :: reserved1 [15:13] */ 11011 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4P_RESERVED1_MASK 0x0000e000 11012 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4P_RESERVED1_ALIGN 0 11013 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4P_RESERVED1_BITS 3 11014 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4P_RESERVED1_SHIFT 13 11015 11016 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ4P :: ADJ_EN [12:12] */ 11017 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4P_ADJ_EN_MASK 0x00001000 11018 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4P_ADJ_EN_ALIGN 0 11019 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4P_ADJ_EN_BITS 1 11020 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4P_ADJ_EN_SHIFT 12 11021 11022 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ4P :: reserved2 [11:08] */ 11023 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4P_RESERVED2_MASK 0x00000f00 11024 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4P_RESERVED2_ALIGN 0 11025 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4P_RESERVED2_BITS 4 11026 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4P_RESERVED2_SHIFT 8 11027 11028 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ4P :: VDL_STEP [07:00] */ 11029 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4P_VDL_STEP_MASK 0x000000ff 11030 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4P_VDL_STEP_ALIGN 0 11031 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4P_VDL_STEP_BITS 8 11032 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4P_VDL_STEP_SHIFT 0 11033 11034 11035 /**************************************************************************** 11036 * DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ4N 11037 */ 11038 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ4N :: BUSY [31:31] */ 11039 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4N_BUSY_MASK 0x80000000 11040 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4N_BUSY_ALIGN 0 11041 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4N_BUSY_BITS 1 11042 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4N_BUSY_SHIFT 31 11043 11044 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ4N :: reserved0 [30:17] */ 11045 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4N_RESERVED0_MASK 0x7ffe0000 11046 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4N_RESERVED0_ALIGN 0 11047 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4N_RESERVED0_BITS 14 11048 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4N_RESERVED0_SHIFT 17 11049 11050 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ4N :: FORCE [16:16] */ 11051 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4N_FORCE_MASK 0x00010000 11052 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4N_FORCE_ALIGN 0 11053 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4N_FORCE_BITS 1 11054 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4N_FORCE_SHIFT 16 11055 11056 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ4N :: reserved1 [15:13] */ 11057 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4N_RESERVED1_MASK 0x0000e000 11058 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4N_RESERVED1_ALIGN 0 11059 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4N_RESERVED1_BITS 3 11060 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4N_RESERVED1_SHIFT 13 11061 11062 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ4N :: ADJ_EN [12:12] */ 11063 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4N_ADJ_EN_MASK 0x00001000 11064 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4N_ADJ_EN_ALIGN 0 11065 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4N_ADJ_EN_BITS 1 11066 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4N_ADJ_EN_SHIFT 12 11067 11068 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ4N :: reserved2 [11:08] */ 11069 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4N_RESERVED2_MASK 0x00000f00 11070 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4N_RESERVED2_ALIGN 0 11071 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4N_RESERVED2_BITS 4 11072 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4N_RESERVED2_SHIFT 8 11073 11074 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ4N :: VDL_STEP [07:00] */ 11075 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4N_VDL_STEP_MASK 0x000000ff 11076 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4N_VDL_STEP_ALIGN 0 11077 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4N_VDL_STEP_BITS 8 11078 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4N_VDL_STEP_SHIFT 0 11079 11080 11081 /**************************************************************************** 11082 * DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ5P 11083 */ 11084 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ5P :: BUSY [31:31] */ 11085 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5P_BUSY_MASK 0x80000000 11086 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5P_BUSY_ALIGN 0 11087 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5P_BUSY_BITS 1 11088 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5P_BUSY_SHIFT 31 11089 11090 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ5P :: reserved0 [30:17] */ 11091 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5P_RESERVED0_MASK 0x7ffe0000 11092 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5P_RESERVED0_ALIGN 0 11093 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5P_RESERVED0_BITS 14 11094 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5P_RESERVED0_SHIFT 17 11095 11096 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ5P :: FORCE [16:16] */ 11097 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5P_FORCE_MASK 0x00010000 11098 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5P_FORCE_ALIGN 0 11099 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5P_FORCE_BITS 1 11100 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5P_FORCE_SHIFT 16 11101 11102 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ5P :: reserved1 [15:13] */ 11103 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5P_RESERVED1_MASK 0x0000e000 11104 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5P_RESERVED1_ALIGN 0 11105 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5P_RESERVED1_BITS 3 11106 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5P_RESERVED1_SHIFT 13 11107 11108 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ5P :: ADJ_EN [12:12] */ 11109 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5P_ADJ_EN_MASK 0x00001000 11110 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5P_ADJ_EN_ALIGN 0 11111 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5P_ADJ_EN_BITS 1 11112 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5P_ADJ_EN_SHIFT 12 11113 11114 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ5P :: reserved2 [11:08] */ 11115 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5P_RESERVED2_MASK 0x00000f00 11116 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5P_RESERVED2_ALIGN 0 11117 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5P_RESERVED2_BITS 4 11118 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5P_RESERVED2_SHIFT 8 11119 11120 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ5P :: VDL_STEP [07:00] */ 11121 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5P_VDL_STEP_MASK 0x000000ff 11122 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5P_VDL_STEP_ALIGN 0 11123 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5P_VDL_STEP_BITS 8 11124 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5P_VDL_STEP_SHIFT 0 11125 11126 11127 /**************************************************************************** 11128 * DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ5N 11129 */ 11130 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ5N :: BUSY [31:31] */ 11131 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5N_BUSY_MASK 0x80000000 11132 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5N_BUSY_ALIGN 0 11133 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5N_BUSY_BITS 1 11134 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5N_BUSY_SHIFT 31 11135 11136 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ5N :: reserved0 [30:17] */ 11137 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5N_RESERVED0_MASK 0x7ffe0000 11138 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5N_RESERVED0_ALIGN 0 11139 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5N_RESERVED0_BITS 14 11140 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5N_RESERVED0_SHIFT 17 11141 11142 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ5N :: FORCE [16:16] */ 11143 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5N_FORCE_MASK 0x00010000 11144 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5N_FORCE_ALIGN 0 11145 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5N_FORCE_BITS 1 11146 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5N_FORCE_SHIFT 16 11147 11148 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ5N :: reserved1 [15:13] */ 11149 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5N_RESERVED1_MASK 0x0000e000 11150 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5N_RESERVED1_ALIGN 0 11151 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5N_RESERVED1_BITS 3 11152 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5N_RESERVED1_SHIFT 13 11153 11154 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ5N :: ADJ_EN [12:12] */ 11155 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5N_ADJ_EN_MASK 0x00001000 11156 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5N_ADJ_EN_ALIGN 0 11157 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5N_ADJ_EN_BITS 1 11158 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5N_ADJ_EN_SHIFT 12 11159 11160 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ5N :: reserved2 [11:08] */ 11161 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5N_RESERVED2_MASK 0x00000f00 11162 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5N_RESERVED2_ALIGN 0 11163 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5N_RESERVED2_BITS 4 11164 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5N_RESERVED2_SHIFT 8 11165 11166 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ5N :: VDL_STEP [07:00] */ 11167 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5N_VDL_STEP_MASK 0x000000ff 11168 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5N_VDL_STEP_ALIGN 0 11169 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5N_VDL_STEP_BITS 8 11170 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5N_VDL_STEP_SHIFT 0 11171 11172 11173 /**************************************************************************** 11174 * DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ6P 11175 */ 11176 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ6P :: BUSY [31:31] */ 11177 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6P_BUSY_MASK 0x80000000 11178 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6P_BUSY_ALIGN 0 11179 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6P_BUSY_BITS 1 11180 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6P_BUSY_SHIFT 31 11181 11182 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ6P :: reserved0 [30:17] */ 11183 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6P_RESERVED0_MASK 0x7ffe0000 11184 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6P_RESERVED0_ALIGN 0 11185 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6P_RESERVED0_BITS 14 11186 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6P_RESERVED0_SHIFT 17 11187 11188 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ6P :: FORCE [16:16] */ 11189 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6P_FORCE_MASK 0x00010000 11190 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6P_FORCE_ALIGN 0 11191 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6P_FORCE_BITS 1 11192 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6P_FORCE_SHIFT 16 11193 11194 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ6P :: reserved1 [15:13] */ 11195 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6P_RESERVED1_MASK 0x0000e000 11196 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6P_RESERVED1_ALIGN 0 11197 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6P_RESERVED1_BITS 3 11198 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6P_RESERVED1_SHIFT 13 11199 11200 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ6P :: ADJ_EN [12:12] */ 11201 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6P_ADJ_EN_MASK 0x00001000 11202 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6P_ADJ_EN_ALIGN 0 11203 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6P_ADJ_EN_BITS 1 11204 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6P_ADJ_EN_SHIFT 12 11205 11206 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ6P :: reserved2 [11:08] */ 11207 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6P_RESERVED2_MASK 0x00000f00 11208 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6P_RESERVED2_ALIGN 0 11209 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6P_RESERVED2_BITS 4 11210 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6P_RESERVED2_SHIFT 8 11211 11212 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ6P :: VDL_STEP [07:00] */ 11213 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6P_VDL_STEP_MASK 0x000000ff 11214 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6P_VDL_STEP_ALIGN 0 11215 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6P_VDL_STEP_BITS 8 11216 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6P_VDL_STEP_SHIFT 0 11217 11218 11219 /**************************************************************************** 11220 * DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ6N 11221 */ 11222 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ6N :: BUSY [31:31] */ 11223 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6N_BUSY_MASK 0x80000000 11224 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6N_BUSY_ALIGN 0 11225 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6N_BUSY_BITS 1 11226 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6N_BUSY_SHIFT 31 11227 11228 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ6N :: reserved0 [30:17] */ 11229 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6N_RESERVED0_MASK 0x7ffe0000 11230 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6N_RESERVED0_ALIGN 0 11231 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6N_RESERVED0_BITS 14 11232 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6N_RESERVED0_SHIFT 17 11233 11234 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ6N :: FORCE [16:16] */ 11235 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6N_FORCE_MASK 0x00010000 11236 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6N_FORCE_ALIGN 0 11237 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6N_FORCE_BITS 1 11238 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6N_FORCE_SHIFT 16 11239 11240 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ6N :: reserved1 [15:13] */ 11241 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6N_RESERVED1_MASK 0x0000e000 11242 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6N_RESERVED1_ALIGN 0 11243 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6N_RESERVED1_BITS 3 11244 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6N_RESERVED1_SHIFT 13 11245 11246 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ6N :: ADJ_EN [12:12] */ 11247 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6N_ADJ_EN_MASK 0x00001000 11248 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6N_ADJ_EN_ALIGN 0 11249 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6N_ADJ_EN_BITS 1 11250 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6N_ADJ_EN_SHIFT 12 11251 11252 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ6N :: reserved2 [11:08] */ 11253 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6N_RESERVED2_MASK 0x00000f00 11254 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6N_RESERVED2_ALIGN 0 11255 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6N_RESERVED2_BITS 4 11256 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6N_RESERVED2_SHIFT 8 11257 11258 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ6N :: VDL_STEP [07:00] */ 11259 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6N_VDL_STEP_MASK 0x000000ff 11260 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6N_VDL_STEP_ALIGN 0 11261 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6N_VDL_STEP_BITS 8 11262 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6N_VDL_STEP_SHIFT 0 11263 11264 11265 /**************************************************************************** 11266 * DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ7P 11267 */ 11268 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ7P :: BUSY [31:31] */ 11269 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7P_BUSY_MASK 0x80000000 11270 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7P_BUSY_ALIGN 0 11271 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7P_BUSY_BITS 1 11272 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7P_BUSY_SHIFT 31 11273 11274 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ7P :: reserved0 [30:17] */ 11275 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7P_RESERVED0_MASK 0x7ffe0000 11276 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7P_RESERVED0_ALIGN 0 11277 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7P_RESERVED0_BITS 14 11278 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7P_RESERVED0_SHIFT 17 11279 11280 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ7P :: FORCE [16:16] */ 11281 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7P_FORCE_MASK 0x00010000 11282 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7P_FORCE_ALIGN 0 11283 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7P_FORCE_BITS 1 11284 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7P_FORCE_SHIFT 16 11285 11286 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ7P :: reserved1 [15:13] */ 11287 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7P_RESERVED1_MASK 0x0000e000 11288 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7P_RESERVED1_ALIGN 0 11289 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7P_RESERVED1_BITS 3 11290 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7P_RESERVED1_SHIFT 13 11291 11292 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ7P :: ADJ_EN [12:12] */ 11293 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7P_ADJ_EN_MASK 0x00001000 11294 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7P_ADJ_EN_ALIGN 0 11295 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7P_ADJ_EN_BITS 1 11296 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7P_ADJ_EN_SHIFT 12 11297 11298 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ7P :: reserved2 [11:08] */ 11299 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7P_RESERVED2_MASK 0x00000f00 11300 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7P_RESERVED2_ALIGN 0 11301 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7P_RESERVED2_BITS 4 11302 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7P_RESERVED2_SHIFT 8 11303 11304 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ7P :: VDL_STEP [07:00] */ 11305 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7P_VDL_STEP_MASK 0x000000ff 11306 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7P_VDL_STEP_ALIGN 0 11307 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7P_VDL_STEP_BITS 8 11308 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7P_VDL_STEP_SHIFT 0 11309 11310 11311 /**************************************************************************** 11312 * DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ7N 11313 */ 11314 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ7N :: BUSY [31:31] */ 11315 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7N_BUSY_MASK 0x80000000 11316 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7N_BUSY_ALIGN 0 11317 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7N_BUSY_BITS 1 11318 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7N_BUSY_SHIFT 31 11319 11320 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ7N :: reserved0 [30:17] */ 11321 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7N_RESERVED0_MASK 0x7ffe0000 11322 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7N_RESERVED0_ALIGN 0 11323 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7N_RESERVED0_BITS 14 11324 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7N_RESERVED0_SHIFT 17 11325 11326 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ7N :: FORCE [16:16] */ 11327 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7N_FORCE_MASK 0x00010000 11328 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7N_FORCE_ALIGN 0 11329 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7N_FORCE_BITS 1 11330 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7N_FORCE_SHIFT 16 11331 11332 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ7N :: reserved1 [15:13] */ 11333 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7N_RESERVED1_MASK 0x0000e000 11334 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7N_RESERVED1_ALIGN 0 11335 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7N_RESERVED1_BITS 3 11336 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7N_RESERVED1_SHIFT 13 11337 11338 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ7N :: ADJ_EN [12:12] */ 11339 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7N_ADJ_EN_MASK 0x00001000 11340 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7N_ADJ_EN_ALIGN 0 11341 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7N_ADJ_EN_BITS 1 11342 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7N_ADJ_EN_SHIFT 12 11343 11344 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ7N :: reserved2 [11:08] */ 11345 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7N_RESERVED2_MASK 0x00000f00 11346 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7N_RESERVED2_ALIGN 0 11347 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7N_RESERVED2_BITS 4 11348 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7N_RESERVED2_SHIFT 8 11349 11350 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ7N :: VDL_STEP [07:00] */ 11351 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7N_VDL_STEP_MASK 0x000000ff 11352 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7N_VDL_STEP_ALIGN 0 11353 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7N_VDL_STEP_BITS 8 11354 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7N_VDL_STEP_SHIFT 0 11355 11356 11357 /**************************************************************************** 11358 * DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DMP 11359 */ 11360 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DMP :: BUSY [31:31] */ 11361 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMP_BUSY_MASK 0x80000000 11362 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMP_BUSY_ALIGN 0 11363 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMP_BUSY_BITS 1 11364 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMP_BUSY_SHIFT 31 11365 11366 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DMP :: reserved0 [30:17] */ 11367 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMP_RESERVED0_MASK 0x7ffe0000 11368 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMP_RESERVED0_ALIGN 0 11369 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMP_RESERVED0_BITS 14 11370 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMP_RESERVED0_SHIFT 17 11371 11372 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DMP :: FORCE [16:16] */ 11373 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMP_FORCE_MASK 0x00010000 11374 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMP_FORCE_ALIGN 0 11375 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMP_FORCE_BITS 1 11376 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMP_FORCE_SHIFT 16 11377 11378 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DMP :: reserved1 [15:13] */ 11379 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMP_RESERVED1_MASK 0x0000e000 11380 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMP_RESERVED1_ALIGN 0 11381 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMP_RESERVED1_BITS 3 11382 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMP_RESERVED1_SHIFT 13 11383 11384 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DMP :: ADJ_EN [12:12] */ 11385 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMP_ADJ_EN_MASK 0x00001000 11386 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMP_ADJ_EN_ALIGN 0 11387 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMP_ADJ_EN_BITS 1 11388 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMP_ADJ_EN_SHIFT 12 11389 11390 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DMP :: reserved2 [11:08] */ 11391 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMP_RESERVED2_MASK 0x00000f00 11392 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMP_RESERVED2_ALIGN 0 11393 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMP_RESERVED2_BITS 4 11394 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMP_RESERVED2_SHIFT 8 11395 11396 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DMP :: VDL_STEP [07:00] */ 11397 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMP_VDL_STEP_MASK 0x000000ff 11398 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMP_VDL_STEP_ALIGN 0 11399 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMP_VDL_STEP_BITS 8 11400 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMP_VDL_STEP_SHIFT 0 11401 11402 11403 /**************************************************************************** 11404 * DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DMN 11405 */ 11406 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DMN :: BUSY [31:31] */ 11407 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMN_BUSY_MASK 0x80000000 11408 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMN_BUSY_ALIGN 0 11409 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMN_BUSY_BITS 1 11410 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMN_BUSY_SHIFT 31 11411 11412 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DMN :: reserved0 [30:17] */ 11413 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMN_RESERVED0_MASK 0x7ffe0000 11414 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMN_RESERVED0_ALIGN 0 11415 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMN_RESERVED0_BITS 14 11416 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMN_RESERVED0_SHIFT 17 11417 11418 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DMN :: FORCE [16:16] */ 11419 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMN_FORCE_MASK 0x00010000 11420 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMN_FORCE_ALIGN 0 11421 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMN_FORCE_BITS 1 11422 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMN_FORCE_SHIFT 16 11423 11424 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DMN :: reserved1 [15:13] */ 11425 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMN_RESERVED1_MASK 0x0000e000 11426 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMN_RESERVED1_ALIGN 0 11427 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMN_RESERVED1_BITS 3 11428 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMN_RESERVED1_SHIFT 13 11429 11430 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DMN :: ADJ_EN [12:12] */ 11431 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMN_ADJ_EN_MASK 0x00001000 11432 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMN_ADJ_EN_ALIGN 0 11433 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMN_ADJ_EN_BITS 1 11434 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMN_ADJ_EN_SHIFT 12 11435 11436 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DMN :: reserved2 [11:08] */ 11437 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMN_RESERVED2_MASK 0x00000f00 11438 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMN_RESERVED2_ALIGN 0 11439 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMN_RESERVED2_BITS 4 11440 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMN_RESERVED2_SHIFT 8 11441 11442 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DMN :: VDL_STEP [07:00] */ 11443 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMN_VDL_STEP_MASK 0x000000ff 11444 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMN_VDL_STEP_ALIGN 0 11445 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMN_VDL_STEP_BITS 8 11446 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMN_VDL_STEP_SHIFT 0 11447 11448 11449 /**************************************************************************** 11450 * DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_EN_CS0 11451 */ 11452 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_EN_CS0 :: BUSY [31:31] */ 11453 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS0_BUSY_MASK 0x80000000 11454 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS0_BUSY_ALIGN 0 11455 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS0_BUSY_BITS 1 11456 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS0_BUSY_SHIFT 31 11457 11458 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_EN_CS0 :: reserved0 [30:17] */ 11459 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS0_RESERVED0_MASK 0x7ffe0000 11460 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS0_RESERVED0_ALIGN 0 11461 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS0_RESERVED0_BITS 14 11462 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS0_RESERVED0_SHIFT 17 11463 11464 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_EN_CS0 :: FORCE [16:16] */ 11465 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS0_FORCE_MASK 0x00010000 11466 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS0_FORCE_ALIGN 0 11467 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS0_FORCE_BITS 1 11468 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS0_FORCE_SHIFT 16 11469 11470 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_EN_CS0 :: reserved1 [15:13] */ 11471 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS0_RESERVED1_MASK 0x0000e000 11472 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS0_RESERVED1_ALIGN 0 11473 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS0_RESERVED1_BITS 3 11474 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS0_RESERVED1_SHIFT 13 11475 11476 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_EN_CS0 :: ADJ_EN [12:12] */ 11477 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS0_ADJ_EN_MASK 0x00001000 11478 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS0_ADJ_EN_ALIGN 0 11479 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS0_ADJ_EN_BITS 1 11480 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS0_ADJ_EN_SHIFT 12 11481 11482 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_EN_CS0 :: reserved2 [11:08] */ 11483 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS0_RESERVED2_MASK 0x00000f00 11484 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS0_RESERVED2_ALIGN 0 11485 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS0_RESERVED2_BITS 4 11486 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS0_RESERVED2_SHIFT 8 11487 11488 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_EN_CS0 :: VDL_STEP [07:00] */ 11489 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS0_VDL_STEP_MASK 0x000000ff 11490 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS0_VDL_STEP_ALIGN 0 11491 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS0_VDL_STEP_BITS 8 11492 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS0_VDL_STEP_SHIFT 0 11493 11494 11495 /**************************************************************************** 11496 * DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_EN_CS1 11497 */ 11498 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_EN_CS1 :: BUSY [31:31] */ 11499 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS1_BUSY_MASK 0x80000000 11500 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS1_BUSY_ALIGN 0 11501 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS1_BUSY_BITS 1 11502 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS1_BUSY_SHIFT 31 11503 11504 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_EN_CS1 :: reserved0 [30:17] */ 11505 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS1_RESERVED0_MASK 0x7ffe0000 11506 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS1_RESERVED0_ALIGN 0 11507 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS1_RESERVED0_BITS 14 11508 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS1_RESERVED0_SHIFT 17 11509 11510 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_EN_CS1 :: FORCE [16:16] */ 11511 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS1_FORCE_MASK 0x00010000 11512 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS1_FORCE_ALIGN 0 11513 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS1_FORCE_BITS 1 11514 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS1_FORCE_SHIFT 16 11515 11516 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_EN_CS1 :: reserved1 [15:13] */ 11517 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS1_RESERVED1_MASK 0x0000e000 11518 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS1_RESERVED1_ALIGN 0 11519 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS1_RESERVED1_BITS 3 11520 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS1_RESERVED1_SHIFT 13 11521 11522 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_EN_CS1 :: ADJ_EN [12:12] */ 11523 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS1_ADJ_EN_MASK 0x00001000 11524 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS1_ADJ_EN_ALIGN 0 11525 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS1_ADJ_EN_BITS 1 11526 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS1_ADJ_EN_SHIFT 12 11527 11528 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_EN_CS1 :: reserved2 [11:08] */ 11529 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS1_RESERVED2_MASK 0x00000f00 11530 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS1_RESERVED2_ALIGN 0 11531 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS1_RESERVED2_BITS 4 11532 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS1_RESERVED2_SHIFT 8 11533 11534 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_EN_CS1 :: VDL_STEP [07:00] */ 11535 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS1_VDL_STEP_MASK 0x000000ff 11536 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS1_VDL_STEP_ALIGN 0 11537 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS1_VDL_STEP_BITS 8 11538 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS1_VDL_STEP_SHIFT 0 11539 11540 11541 /**************************************************************************** 11542 * DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CLK_CONTROL 11543 */ 11544 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CLK_CONTROL :: BUSY [31:31] */ 11545 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CLK_CONTROL_BUSY_MASK 0x80000000 11546 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CLK_CONTROL_BUSY_ALIGN 0 11547 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CLK_CONTROL_BUSY_BITS 1 11548 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CLK_CONTROL_BUSY_SHIFT 31 11549 11550 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CLK_CONTROL :: reserved0 [30:17] */ 11551 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CLK_CONTROL_RESERVED0_MASK 0x7ffe0000 11552 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CLK_CONTROL_RESERVED0_ALIGN 0 11553 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CLK_CONTROL_RESERVED0_BITS 14 11554 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CLK_CONTROL_RESERVED0_SHIFT 17 11555 11556 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CLK_CONTROL :: FORCE [16:16] */ 11557 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CLK_CONTROL_FORCE_MASK 0x00010000 11558 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CLK_CONTROL_FORCE_ALIGN 0 11559 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CLK_CONTROL_FORCE_BITS 1 11560 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CLK_CONTROL_FORCE_SHIFT 16 11561 11562 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CLK_CONTROL :: reserved1 [15:13] */ 11563 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CLK_CONTROL_RESERVED1_MASK 0x0000e000 11564 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CLK_CONTROL_RESERVED1_ALIGN 0 11565 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CLK_CONTROL_RESERVED1_BITS 3 11566 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CLK_CONTROL_RESERVED1_SHIFT 13 11567 11568 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CLK_CONTROL :: ADJ_EN [12:12] */ 11569 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CLK_CONTROL_ADJ_EN_MASK 0x00001000 11570 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CLK_CONTROL_ADJ_EN_ALIGN 0 11571 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CLK_CONTROL_ADJ_EN_BITS 1 11572 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CLK_CONTROL_ADJ_EN_SHIFT 12 11573 11574 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CLK_CONTROL :: reserved2 [11:09] */ 11575 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CLK_CONTROL_RESERVED2_MASK 0x00000e00 11576 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CLK_CONTROL_RESERVED2_ALIGN 0 11577 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CLK_CONTROL_RESERVED2_BITS 3 11578 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CLK_CONTROL_RESERVED2_SHIFT 9 11579 11580 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_CLK_CONTROL :: VDL_STEP [08:00] */ 11581 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CLK_CONTROL_VDL_STEP_MASK 0x000001ff 11582 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CLK_CONTROL_VDL_STEP_ALIGN 0 11583 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CLK_CONTROL_VDL_STEP_BITS 9 11584 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_CLK_CONTROL_VDL_STEP_SHIFT 0 11585 11586 11587 /**************************************************************************** 11588 * DDR34_F0_PHY_BYTE_LANE_2 :: VDL_LDE_CONTROL 11589 */ 11590 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_LDE_CONTROL :: BUSY [31:31] */ 11591 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_LDE_CONTROL_BUSY_MASK 0x80000000 11592 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_LDE_CONTROL_BUSY_ALIGN 0 11593 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_LDE_CONTROL_BUSY_BITS 1 11594 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_LDE_CONTROL_BUSY_SHIFT 31 11595 11596 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_LDE_CONTROL :: reserved0 [30:17] */ 11597 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_LDE_CONTROL_RESERVED0_MASK 0x7ffe0000 11598 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_LDE_CONTROL_RESERVED0_ALIGN 0 11599 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_LDE_CONTROL_RESERVED0_BITS 14 11600 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_LDE_CONTROL_RESERVED0_SHIFT 17 11601 11602 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_LDE_CONTROL :: FORCE [16:16] */ 11603 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_LDE_CONTROL_FORCE_MASK 0x00010000 11604 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_LDE_CONTROL_FORCE_ALIGN 0 11605 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_LDE_CONTROL_FORCE_BITS 1 11606 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_LDE_CONTROL_FORCE_SHIFT 16 11607 11608 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_LDE_CONTROL :: reserved1 [15:13] */ 11609 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_LDE_CONTROL_RESERVED1_MASK 0x0000e000 11610 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_LDE_CONTROL_RESERVED1_ALIGN 0 11611 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_LDE_CONTROL_RESERVED1_BITS 3 11612 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_LDE_CONTROL_RESERVED1_SHIFT 13 11613 11614 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_LDE_CONTROL :: ADJ_EN [12:12] */ 11615 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_LDE_CONTROL_ADJ_EN_MASK 0x00001000 11616 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_LDE_CONTROL_ADJ_EN_ALIGN 0 11617 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_LDE_CONTROL_ADJ_EN_BITS 1 11618 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_LDE_CONTROL_ADJ_EN_SHIFT 12 11619 11620 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_LDE_CONTROL :: reserved2 [11:09] */ 11621 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_LDE_CONTROL_RESERVED2_MASK 0x00000e00 11622 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_LDE_CONTROL_RESERVED2_ALIGN 0 11623 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_LDE_CONTROL_RESERVED2_BITS 3 11624 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_LDE_CONTROL_RESERVED2_SHIFT 9 11625 11626 /* DDR34_F0_PHY_BYTE_LANE_2 :: VDL_LDE_CONTROL :: VDL_STEP [08:00] */ 11627 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_LDE_CONTROL_VDL_STEP_MASK 0x000001ff 11628 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_LDE_CONTROL_VDL_STEP_ALIGN 0 11629 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_LDE_CONTROL_VDL_STEP_BITS 9 11630 #define DDR34_F0_PHY_BYTE_LANE_2_VDL_LDE_CONTROL_VDL_STEP_SHIFT 0 11631 11632 11633 /**************************************************************************** 11634 * DDR34_F0_PHY_BYTE_LANE_2 :: RD_EN_DLY_CYC 11635 */ 11636 /* DDR34_F0_PHY_BYTE_LANE_2 :: RD_EN_DLY_CYC :: BUSY [31:31] */ 11637 #define DDR34_F0_PHY_BYTE_LANE_2_RD_EN_DLY_CYC_BUSY_MASK 0x80000000 11638 #define DDR34_F0_PHY_BYTE_LANE_2_RD_EN_DLY_CYC_BUSY_ALIGN 0 11639 #define DDR34_F0_PHY_BYTE_LANE_2_RD_EN_DLY_CYC_BUSY_BITS 1 11640 #define DDR34_F0_PHY_BYTE_LANE_2_RD_EN_DLY_CYC_BUSY_SHIFT 31 11641 11642 /* DDR34_F0_PHY_BYTE_LANE_2 :: RD_EN_DLY_CYC :: reserved0 [30:17] */ 11643 #define DDR34_F0_PHY_BYTE_LANE_2_RD_EN_DLY_CYC_RESERVED0_MASK 0x7ffe0000 11644 #define DDR34_F0_PHY_BYTE_LANE_2_RD_EN_DLY_CYC_RESERVED0_ALIGN 0 11645 #define DDR34_F0_PHY_BYTE_LANE_2_RD_EN_DLY_CYC_RESERVED0_BITS 14 11646 #define DDR34_F0_PHY_BYTE_LANE_2_RD_EN_DLY_CYC_RESERVED0_SHIFT 17 11647 11648 /* DDR34_F0_PHY_BYTE_LANE_2 :: RD_EN_DLY_CYC :: FORCE [16:16] */ 11649 #define DDR34_F0_PHY_BYTE_LANE_2_RD_EN_DLY_CYC_FORCE_MASK 0x00010000 11650 #define DDR34_F0_PHY_BYTE_LANE_2_RD_EN_DLY_CYC_FORCE_ALIGN 0 11651 #define DDR34_F0_PHY_BYTE_LANE_2_RD_EN_DLY_CYC_FORCE_BITS 1 11652 #define DDR34_F0_PHY_BYTE_LANE_2_RD_EN_DLY_CYC_FORCE_SHIFT 16 11653 11654 /* DDR34_F0_PHY_BYTE_LANE_2 :: RD_EN_DLY_CYC :: reserved1 [15:09] */ 11655 #define DDR34_F0_PHY_BYTE_LANE_2_RD_EN_DLY_CYC_RESERVED1_MASK 0x0000fe00 11656 #define DDR34_F0_PHY_BYTE_LANE_2_RD_EN_DLY_CYC_RESERVED1_ALIGN 0 11657 #define DDR34_F0_PHY_BYTE_LANE_2_RD_EN_DLY_CYC_RESERVED1_BITS 7 11658 #define DDR34_F0_PHY_BYTE_LANE_2_RD_EN_DLY_CYC_RESERVED1_SHIFT 9 11659 11660 /* DDR34_F0_PHY_BYTE_LANE_2 :: RD_EN_DLY_CYC :: ENABLE_CS1 [08:08] */ 11661 #define DDR34_F0_PHY_BYTE_LANE_2_RD_EN_DLY_CYC_ENABLE_CS1_MASK 0x00000100 11662 #define DDR34_F0_PHY_BYTE_LANE_2_RD_EN_DLY_CYC_ENABLE_CS1_ALIGN 0 11663 #define DDR34_F0_PHY_BYTE_LANE_2_RD_EN_DLY_CYC_ENABLE_CS1_BITS 1 11664 #define DDR34_F0_PHY_BYTE_LANE_2_RD_EN_DLY_CYC_ENABLE_CS1_SHIFT 8 11665 11666 /* DDR34_F0_PHY_BYTE_LANE_2 :: RD_EN_DLY_CYC :: CS1_CYCLES [07:04] */ 11667 #define DDR34_F0_PHY_BYTE_LANE_2_RD_EN_DLY_CYC_CS1_CYCLES_MASK 0x000000f0 11668 #define DDR34_F0_PHY_BYTE_LANE_2_RD_EN_DLY_CYC_CS1_CYCLES_ALIGN 0 11669 #define DDR34_F0_PHY_BYTE_LANE_2_RD_EN_DLY_CYC_CS1_CYCLES_BITS 4 11670 #define DDR34_F0_PHY_BYTE_LANE_2_RD_EN_DLY_CYC_CS1_CYCLES_SHIFT 4 11671 11672 /* DDR34_F0_PHY_BYTE_LANE_2 :: RD_EN_DLY_CYC :: CS0_CYCLES [03:00] */ 11673 #define DDR34_F0_PHY_BYTE_LANE_2_RD_EN_DLY_CYC_CS0_CYCLES_MASK 0x0000000f 11674 #define DDR34_F0_PHY_BYTE_LANE_2_RD_EN_DLY_CYC_CS0_CYCLES_ALIGN 0 11675 #define DDR34_F0_PHY_BYTE_LANE_2_RD_EN_DLY_CYC_CS0_CYCLES_BITS 4 11676 #define DDR34_F0_PHY_BYTE_LANE_2_RD_EN_DLY_CYC_CS0_CYCLES_SHIFT 0 11677 11678 11679 /**************************************************************************** 11680 * DDR34_F0_PHY_BYTE_LANE_2 :: WR_CHAN_DLY_CYC 11681 */ 11682 /* DDR34_F0_PHY_BYTE_LANE_2 :: WR_CHAN_DLY_CYC :: BUSY [31:31] */ 11683 #define DDR34_F0_PHY_BYTE_LANE_2_WR_CHAN_DLY_CYC_BUSY_MASK 0x80000000 11684 #define DDR34_F0_PHY_BYTE_LANE_2_WR_CHAN_DLY_CYC_BUSY_ALIGN 0 11685 #define DDR34_F0_PHY_BYTE_LANE_2_WR_CHAN_DLY_CYC_BUSY_BITS 1 11686 #define DDR34_F0_PHY_BYTE_LANE_2_WR_CHAN_DLY_CYC_BUSY_SHIFT 31 11687 11688 /* DDR34_F0_PHY_BYTE_LANE_2 :: WR_CHAN_DLY_CYC :: reserved0 [30:17] */ 11689 #define DDR34_F0_PHY_BYTE_LANE_2_WR_CHAN_DLY_CYC_RESERVED0_MASK 0x7ffe0000 11690 #define DDR34_F0_PHY_BYTE_LANE_2_WR_CHAN_DLY_CYC_RESERVED0_ALIGN 0 11691 #define DDR34_F0_PHY_BYTE_LANE_2_WR_CHAN_DLY_CYC_RESERVED0_BITS 14 11692 #define DDR34_F0_PHY_BYTE_LANE_2_WR_CHAN_DLY_CYC_RESERVED0_SHIFT 17 11693 11694 /* DDR34_F0_PHY_BYTE_LANE_2 :: WR_CHAN_DLY_CYC :: FORCE [16:16] */ 11695 #define DDR34_F0_PHY_BYTE_LANE_2_WR_CHAN_DLY_CYC_FORCE_MASK 0x00010000 11696 #define DDR34_F0_PHY_BYTE_LANE_2_WR_CHAN_DLY_CYC_FORCE_ALIGN 0 11697 #define DDR34_F0_PHY_BYTE_LANE_2_WR_CHAN_DLY_CYC_FORCE_BITS 1 11698 #define DDR34_F0_PHY_BYTE_LANE_2_WR_CHAN_DLY_CYC_FORCE_SHIFT 16 11699 11700 /* DDR34_F0_PHY_BYTE_LANE_2 :: WR_CHAN_DLY_CYC :: reserved1 [15:08] */ 11701 #define DDR34_F0_PHY_BYTE_LANE_2_WR_CHAN_DLY_CYC_RESERVED1_MASK 0x0000ff00 11702 #define DDR34_F0_PHY_BYTE_LANE_2_WR_CHAN_DLY_CYC_RESERVED1_ALIGN 0 11703 #define DDR34_F0_PHY_BYTE_LANE_2_WR_CHAN_DLY_CYC_RESERVED1_BITS 8 11704 #define DDR34_F0_PHY_BYTE_LANE_2_WR_CHAN_DLY_CYC_RESERVED1_SHIFT 8 11705 11706 /* DDR34_F0_PHY_BYTE_LANE_2 :: WR_CHAN_DLY_CYC :: DQ_CYCLES [07:04] */ 11707 #define DDR34_F0_PHY_BYTE_LANE_2_WR_CHAN_DLY_CYC_DQ_CYCLES_MASK 0x000000f0 11708 #define DDR34_F0_PHY_BYTE_LANE_2_WR_CHAN_DLY_CYC_DQ_CYCLES_ALIGN 0 11709 #define DDR34_F0_PHY_BYTE_LANE_2_WR_CHAN_DLY_CYC_DQ_CYCLES_BITS 4 11710 #define DDR34_F0_PHY_BYTE_LANE_2_WR_CHAN_DLY_CYC_DQ_CYCLES_SHIFT 4 11711 11712 /* DDR34_F0_PHY_BYTE_LANE_2 :: WR_CHAN_DLY_CYC :: reserved2 [03:03] */ 11713 #define DDR34_F0_PHY_BYTE_LANE_2_WR_CHAN_DLY_CYC_RESERVED2_MASK 0x00000008 11714 #define DDR34_F0_PHY_BYTE_LANE_2_WR_CHAN_DLY_CYC_RESERVED2_ALIGN 0 11715 #define DDR34_F0_PHY_BYTE_LANE_2_WR_CHAN_DLY_CYC_RESERVED2_BITS 1 11716 #define DDR34_F0_PHY_BYTE_LANE_2_WR_CHAN_DLY_CYC_RESERVED2_SHIFT 3 11717 11718 /* DDR34_F0_PHY_BYTE_LANE_2 :: WR_CHAN_DLY_CYC :: CYCLES [02:00] */ 11719 #define DDR34_F0_PHY_BYTE_LANE_2_WR_CHAN_DLY_CYC_CYCLES_MASK 0x00000007 11720 #define DDR34_F0_PHY_BYTE_LANE_2_WR_CHAN_DLY_CYC_CYCLES_ALIGN 0 11721 #define DDR34_F0_PHY_BYTE_LANE_2_WR_CHAN_DLY_CYC_CYCLES_BITS 3 11722 #define DDR34_F0_PHY_BYTE_LANE_2_WR_CHAN_DLY_CYC_CYCLES_SHIFT 0 11723 11724 11725 /**************************************************************************** 11726 * DDR34_F0_PHY_BYTE_LANE_2 :: READ_CONTROL 11727 */ 11728 /* DDR34_F0_PHY_BYTE_LANE_2 :: READ_CONTROL :: reserved0 [31:05] */ 11729 #define DDR34_F0_PHY_BYTE_LANE_2_READ_CONTROL_RESERVED0_MASK 0xffffffe0 11730 #define DDR34_F0_PHY_BYTE_LANE_2_READ_CONTROL_RESERVED0_ALIGN 0 11731 #define DDR34_F0_PHY_BYTE_LANE_2_READ_CONTROL_RESERVED0_BITS 27 11732 #define DDR34_F0_PHY_BYTE_LANE_2_READ_CONTROL_RESERVED0_SHIFT 5 11733 11734 /* DDR34_F0_PHY_BYTE_LANE_2 :: READ_CONTROL :: MODE [04:04] */ 11735 #define DDR34_F0_PHY_BYTE_LANE_2_READ_CONTROL_MODE_MASK 0x00000010 11736 #define DDR34_F0_PHY_BYTE_LANE_2_READ_CONTROL_MODE_ALIGN 0 11737 #define DDR34_F0_PHY_BYTE_LANE_2_READ_CONTROL_MODE_BITS 1 11738 #define DDR34_F0_PHY_BYTE_LANE_2_READ_CONTROL_MODE_SHIFT 4 11739 11740 /* DDR34_F0_PHY_BYTE_LANE_2 :: READ_CONTROL :: RD_EN_MODE [03:03] */ 11741 #define DDR34_F0_PHY_BYTE_LANE_2_READ_CONTROL_RD_EN_MODE_MASK 0x00000008 11742 #define DDR34_F0_PHY_BYTE_LANE_2_READ_CONTROL_RD_EN_MODE_ALIGN 0 11743 #define DDR34_F0_PHY_BYTE_LANE_2_READ_CONTROL_RD_EN_MODE_BITS 1 11744 #define DDR34_F0_PHY_BYTE_LANE_2_READ_CONTROL_RD_EN_MODE_SHIFT 3 11745 11746 /* DDR34_F0_PHY_BYTE_LANE_2 :: READ_CONTROL :: RD_DATA_DLY [02:00] */ 11747 #define DDR34_F0_PHY_BYTE_LANE_2_READ_CONTROL_RD_DATA_DLY_MASK 0x00000007 11748 #define DDR34_F0_PHY_BYTE_LANE_2_READ_CONTROL_RD_DATA_DLY_ALIGN 0 11749 #define DDR34_F0_PHY_BYTE_LANE_2_READ_CONTROL_RD_DATA_DLY_BITS 3 11750 #define DDR34_F0_PHY_BYTE_LANE_2_READ_CONTROL_RD_DATA_DLY_SHIFT 0 11751 11752 11753 /**************************************************************************** 11754 * DDR34_F0_PHY_BYTE_LANE_2 :: READ_FIFO_ADDR 11755 */ 11756 /* DDR34_F0_PHY_BYTE_LANE_2 :: READ_FIFO_ADDR :: reserved0 [31:03] */ 11757 #define DDR34_F0_PHY_BYTE_LANE_2_READ_FIFO_ADDR_RESERVED0_MASK 0xfffffff8 11758 #define DDR34_F0_PHY_BYTE_LANE_2_READ_FIFO_ADDR_RESERVED0_ALIGN 0 11759 #define DDR34_F0_PHY_BYTE_LANE_2_READ_FIFO_ADDR_RESERVED0_BITS 29 11760 #define DDR34_F0_PHY_BYTE_LANE_2_READ_FIFO_ADDR_RESERVED0_SHIFT 3 11761 11762 /* DDR34_F0_PHY_BYTE_LANE_2 :: READ_FIFO_ADDR :: ADDR [02:00] */ 11763 #define DDR34_F0_PHY_BYTE_LANE_2_READ_FIFO_ADDR_ADDR_MASK 0x00000007 11764 #define DDR34_F0_PHY_BYTE_LANE_2_READ_FIFO_ADDR_ADDR_ALIGN 0 11765 #define DDR34_F0_PHY_BYTE_LANE_2_READ_FIFO_ADDR_ADDR_BITS 3 11766 #define DDR34_F0_PHY_BYTE_LANE_2_READ_FIFO_ADDR_ADDR_SHIFT 0 11767 11768 11769 /**************************************************************************** 11770 * DDR34_F0_PHY_BYTE_LANE_2 :: READ_FIFO_DATA 11771 */ 11772 /* DDR34_F0_PHY_BYTE_LANE_2 :: READ_FIFO_DATA :: DATA [31:00] */ 11773 #define DDR34_F0_PHY_BYTE_LANE_2_READ_FIFO_DATA_DATA_MASK 0xffffffff 11774 #define DDR34_F0_PHY_BYTE_LANE_2_READ_FIFO_DATA_DATA_ALIGN 0 11775 #define DDR34_F0_PHY_BYTE_LANE_2_READ_FIFO_DATA_DATA_BITS 32 11776 #define DDR34_F0_PHY_BYTE_LANE_2_READ_FIFO_DATA_DATA_SHIFT 0 11777 11778 11779 /**************************************************************************** 11780 * DDR34_F0_PHY_BYTE_LANE_2 :: READ_FIFO_DM_DBI 11781 */ 11782 /* DDR34_F0_PHY_BYTE_LANE_2 :: READ_FIFO_DM_DBI :: reserved0 [31:04] */ 11783 #define DDR34_F0_PHY_BYTE_LANE_2_READ_FIFO_DM_DBI_RESERVED0_MASK 0xfffffff0 11784 #define DDR34_F0_PHY_BYTE_LANE_2_READ_FIFO_DM_DBI_RESERVED0_ALIGN 0 11785 #define DDR34_F0_PHY_BYTE_LANE_2_READ_FIFO_DM_DBI_RESERVED0_BITS 28 11786 #define DDR34_F0_PHY_BYTE_LANE_2_READ_FIFO_DM_DBI_RESERVED0_SHIFT 4 11787 11788 /* DDR34_F0_PHY_BYTE_LANE_2 :: READ_FIFO_DM_DBI :: DM_DBI [03:00] */ 11789 #define DDR34_F0_PHY_BYTE_LANE_2_READ_FIFO_DM_DBI_DM_DBI_MASK 0x0000000f 11790 #define DDR34_F0_PHY_BYTE_LANE_2_READ_FIFO_DM_DBI_DM_DBI_ALIGN 0 11791 #define DDR34_F0_PHY_BYTE_LANE_2_READ_FIFO_DM_DBI_DM_DBI_BITS 4 11792 #define DDR34_F0_PHY_BYTE_LANE_2_READ_FIFO_DM_DBI_DM_DBI_SHIFT 0 11793 11794 11795 /**************************************************************************** 11796 * DDR34_F0_PHY_BYTE_LANE_2 :: READ_FIFO_STATUS 11797 */ 11798 /* DDR34_F0_PHY_BYTE_LANE_2 :: READ_FIFO_STATUS :: reserved0 [31:02] */ 11799 #define DDR34_F0_PHY_BYTE_LANE_2_READ_FIFO_STATUS_RESERVED0_MASK 0xfffffffc 11800 #define DDR34_F0_PHY_BYTE_LANE_2_READ_FIFO_STATUS_RESERVED0_ALIGN 0 11801 #define DDR34_F0_PHY_BYTE_LANE_2_READ_FIFO_STATUS_RESERVED0_BITS 30 11802 #define DDR34_F0_PHY_BYTE_LANE_2_READ_FIFO_STATUS_RESERVED0_SHIFT 2 11803 11804 /* DDR34_F0_PHY_BYTE_LANE_2 :: READ_FIFO_STATUS :: OVERFLOW [01:01] */ 11805 #define DDR34_F0_PHY_BYTE_LANE_2_READ_FIFO_STATUS_OVERFLOW_MASK 0x00000002 11806 #define DDR34_F0_PHY_BYTE_LANE_2_READ_FIFO_STATUS_OVERFLOW_ALIGN 0 11807 #define DDR34_F0_PHY_BYTE_LANE_2_READ_FIFO_STATUS_OVERFLOW_BITS 1 11808 #define DDR34_F0_PHY_BYTE_LANE_2_READ_FIFO_STATUS_OVERFLOW_SHIFT 1 11809 11810 /* DDR34_F0_PHY_BYTE_LANE_2 :: READ_FIFO_STATUS :: UNDERFLOW [00:00] */ 11811 #define DDR34_F0_PHY_BYTE_LANE_2_READ_FIFO_STATUS_UNDERFLOW_MASK 0x00000001 11812 #define DDR34_F0_PHY_BYTE_LANE_2_READ_FIFO_STATUS_UNDERFLOW_ALIGN 0 11813 #define DDR34_F0_PHY_BYTE_LANE_2_READ_FIFO_STATUS_UNDERFLOW_BITS 1 11814 #define DDR34_F0_PHY_BYTE_LANE_2_READ_FIFO_STATUS_UNDERFLOW_SHIFT 0 11815 11816 11817 /**************************************************************************** 11818 * DDR34_F0_PHY_BYTE_LANE_2 :: READ_FIFO_CLEAR 11819 */ 11820 /* DDR34_F0_PHY_BYTE_LANE_2 :: READ_FIFO_CLEAR :: reserved0 [31:01] */ 11821 #define DDR34_F0_PHY_BYTE_LANE_2_READ_FIFO_CLEAR_RESERVED0_MASK 0xfffffffe 11822 #define DDR34_F0_PHY_BYTE_LANE_2_READ_FIFO_CLEAR_RESERVED0_ALIGN 0 11823 #define DDR34_F0_PHY_BYTE_LANE_2_READ_FIFO_CLEAR_RESERVED0_BITS 31 11824 #define DDR34_F0_PHY_BYTE_LANE_2_READ_FIFO_CLEAR_RESERVED0_SHIFT 1 11825 11826 /* DDR34_F0_PHY_BYTE_LANE_2 :: READ_FIFO_CLEAR :: CLEAR [00:00] */ 11827 #define DDR34_F0_PHY_BYTE_LANE_2_READ_FIFO_CLEAR_CLEAR_MASK 0x00000001 11828 #define DDR34_F0_PHY_BYTE_LANE_2_READ_FIFO_CLEAR_CLEAR_ALIGN 0 11829 #define DDR34_F0_PHY_BYTE_LANE_2_READ_FIFO_CLEAR_CLEAR_BITS 1 11830 #define DDR34_F0_PHY_BYTE_LANE_2_READ_FIFO_CLEAR_CLEAR_SHIFT 0 11831 11832 11833 /**************************************************************************** 11834 * DDR34_F0_PHY_BYTE_LANE_2 :: IDLE_PAD_CONTROL 11835 */ 11836 /* DDR34_F0_PHY_BYTE_LANE_2 :: IDLE_PAD_CONTROL :: IDLE [31:31] */ 11837 #define DDR34_F0_PHY_BYTE_LANE_2_IDLE_PAD_CONTROL_IDLE_MASK 0x80000000 11838 #define DDR34_F0_PHY_BYTE_LANE_2_IDLE_PAD_CONTROL_IDLE_ALIGN 0 11839 #define DDR34_F0_PHY_BYTE_LANE_2_IDLE_PAD_CONTROL_IDLE_BITS 1 11840 #define DDR34_F0_PHY_BYTE_LANE_2_IDLE_PAD_CONTROL_IDLE_SHIFT 31 11841 11842 /* DDR34_F0_PHY_BYTE_LANE_2 :: IDLE_PAD_CONTROL :: reserved0 [30:20] */ 11843 #define DDR34_F0_PHY_BYTE_LANE_2_IDLE_PAD_CONTROL_RESERVED0_MASK 0x7ff00000 11844 #define DDR34_F0_PHY_BYTE_LANE_2_IDLE_PAD_CONTROL_RESERVED0_ALIGN 0 11845 #define DDR34_F0_PHY_BYTE_LANE_2_IDLE_PAD_CONTROL_RESERVED0_BITS 11 11846 #define DDR34_F0_PHY_BYTE_LANE_2_IDLE_PAD_CONTROL_RESERVED0_SHIFT 20 11847 11848 /* DDR34_F0_PHY_BYTE_LANE_2 :: IDLE_PAD_CONTROL :: AUTO_DQ_RXENB_MODE [19:18] */ 11849 #define DDR34_F0_PHY_BYTE_LANE_2_IDLE_PAD_CONTROL_AUTO_DQ_RXENB_MODE_MASK 0x000c0000 11850 #define DDR34_F0_PHY_BYTE_LANE_2_IDLE_PAD_CONTROL_AUTO_DQ_RXENB_MODE_ALIGN 0 11851 #define DDR34_F0_PHY_BYTE_LANE_2_IDLE_PAD_CONTROL_AUTO_DQ_RXENB_MODE_BITS 2 11852 #define DDR34_F0_PHY_BYTE_LANE_2_IDLE_PAD_CONTROL_AUTO_DQ_RXENB_MODE_SHIFT 18 11853 11854 /* DDR34_F0_PHY_BYTE_LANE_2 :: IDLE_PAD_CONTROL :: AUTO_DQ_IDDQ_MODE [17:16] */ 11855 #define DDR34_F0_PHY_BYTE_LANE_2_IDLE_PAD_CONTROL_AUTO_DQ_IDDQ_MODE_MASK 0x00030000 11856 #define DDR34_F0_PHY_BYTE_LANE_2_IDLE_PAD_CONTROL_AUTO_DQ_IDDQ_MODE_ALIGN 0 11857 #define DDR34_F0_PHY_BYTE_LANE_2_IDLE_PAD_CONTROL_AUTO_DQ_IDDQ_MODE_BITS 2 11858 #define DDR34_F0_PHY_BYTE_LANE_2_IDLE_PAD_CONTROL_AUTO_DQ_IDDQ_MODE_SHIFT 16 11859 11860 /* DDR34_F0_PHY_BYTE_LANE_2 :: IDLE_PAD_CONTROL :: IO_IDLE_ENABLE [15:04] */ 11861 #define DDR34_F0_PHY_BYTE_LANE_2_IDLE_PAD_CONTROL_IO_IDLE_ENABLE_MASK 0x0000fff0 11862 #define DDR34_F0_PHY_BYTE_LANE_2_IDLE_PAD_CONTROL_IO_IDLE_ENABLE_ALIGN 0 11863 #define DDR34_F0_PHY_BYTE_LANE_2_IDLE_PAD_CONTROL_IO_IDLE_ENABLE_BITS 12 11864 #define DDR34_F0_PHY_BYTE_LANE_2_IDLE_PAD_CONTROL_IO_IDLE_ENABLE_SHIFT 4 11865 11866 /* DDR34_F0_PHY_BYTE_LANE_2 :: IDLE_PAD_CONTROL :: RXENB [03:03] */ 11867 #define DDR34_F0_PHY_BYTE_LANE_2_IDLE_PAD_CONTROL_RXENB_MASK 0x00000008 11868 #define DDR34_F0_PHY_BYTE_LANE_2_IDLE_PAD_CONTROL_RXENB_ALIGN 0 11869 #define DDR34_F0_PHY_BYTE_LANE_2_IDLE_PAD_CONTROL_RXENB_BITS 1 11870 #define DDR34_F0_PHY_BYTE_LANE_2_IDLE_PAD_CONTROL_RXENB_SHIFT 3 11871 11872 /* DDR34_F0_PHY_BYTE_LANE_2 :: IDLE_PAD_CONTROL :: IDDQ [02:02] */ 11873 #define DDR34_F0_PHY_BYTE_LANE_2_IDLE_PAD_CONTROL_IDDQ_MASK 0x00000004 11874 #define DDR34_F0_PHY_BYTE_LANE_2_IDLE_PAD_CONTROL_IDDQ_ALIGN 0 11875 #define DDR34_F0_PHY_BYTE_LANE_2_IDLE_PAD_CONTROL_IDDQ_BITS 1 11876 #define DDR34_F0_PHY_BYTE_LANE_2_IDLE_PAD_CONTROL_IDDQ_SHIFT 2 11877 11878 /* DDR34_F0_PHY_BYTE_LANE_2 :: IDLE_PAD_CONTROL :: DOUT_N [01:01] */ 11879 #define DDR34_F0_PHY_BYTE_LANE_2_IDLE_PAD_CONTROL_DOUT_N_MASK 0x00000002 11880 #define DDR34_F0_PHY_BYTE_LANE_2_IDLE_PAD_CONTROL_DOUT_N_ALIGN 0 11881 #define DDR34_F0_PHY_BYTE_LANE_2_IDLE_PAD_CONTROL_DOUT_N_BITS 1 11882 #define DDR34_F0_PHY_BYTE_LANE_2_IDLE_PAD_CONTROL_DOUT_N_SHIFT 1 11883 11884 /* DDR34_F0_PHY_BYTE_LANE_2 :: IDLE_PAD_CONTROL :: DOUT_P [00:00] */ 11885 #define DDR34_F0_PHY_BYTE_LANE_2_IDLE_PAD_CONTROL_DOUT_P_MASK 0x00000001 11886 #define DDR34_F0_PHY_BYTE_LANE_2_IDLE_PAD_CONTROL_DOUT_P_ALIGN 0 11887 #define DDR34_F0_PHY_BYTE_LANE_2_IDLE_PAD_CONTROL_DOUT_P_BITS 1 11888 #define DDR34_F0_PHY_BYTE_LANE_2_IDLE_PAD_CONTROL_DOUT_P_SHIFT 0 11889 11890 11891 /**************************************************************************** 11892 * DDR34_F0_PHY_BYTE_LANE_2 :: DRIVE_PAD_CTL 11893 */ 11894 /* DDR34_F0_PHY_BYTE_LANE_2 :: DRIVE_PAD_CTL :: reserved0 [31:20] */ 11895 #define DDR34_F0_PHY_BYTE_LANE_2_DRIVE_PAD_CTL_RESERVED0_MASK 0xfff00000 11896 #define DDR34_F0_PHY_BYTE_LANE_2_DRIVE_PAD_CTL_RESERVED0_ALIGN 0 11897 #define DDR34_F0_PHY_BYTE_LANE_2_DRIVE_PAD_CTL_RESERVED0_BITS 12 11898 #define DDR34_F0_PHY_BYTE_LANE_2_DRIVE_PAD_CTL_RESERVED0_SHIFT 20 11899 11900 /* DDR34_F0_PHY_BYTE_LANE_2 :: DRIVE_PAD_CTL :: BL_PD_TERM_STRENGTH [19:15] */ 11901 #define DDR34_F0_PHY_BYTE_LANE_2_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_MASK 0x000f8000 11902 #define DDR34_F0_PHY_BYTE_LANE_2_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_ALIGN 0 11903 #define DDR34_F0_PHY_BYTE_LANE_2_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_BITS 5 11904 #define DDR34_F0_PHY_BYTE_LANE_2_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_SHIFT 15 11905 11906 /* DDR34_F0_PHY_BYTE_LANE_2 :: DRIVE_PAD_CTL :: BL_ND_TERM_STRENGTH [14:10] */ 11907 #define DDR34_F0_PHY_BYTE_LANE_2_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_MASK 0x00007c00 11908 #define DDR34_F0_PHY_BYTE_LANE_2_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_ALIGN 0 11909 #define DDR34_F0_PHY_BYTE_LANE_2_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_BITS 5 11910 #define DDR34_F0_PHY_BYTE_LANE_2_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_SHIFT 10 11911 11912 /* DDR34_F0_PHY_BYTE_LANE_2 :: DRIVE_PAD_CTL :: BL_PD_STRENGTH [09:05] */ 11913 #define DDR34_F0_PHY_BYTE_LANE_2_DRIVE_PAD_CTL_BL_PD_STRENGTH_MASK 0x000003e0 11914 #define DDR34_F0_PHY_BYTE_LANE_2_DRIVE_PAD_CTL_BL_PD_STRENGTH_ALIGN 0 11915 #define DDR34_F0_PHY_BYTE_LANE_2_DRIVE_PAD_CTL_BL_PD_STRENGTH_BITS 5 11916 #define DDR34_F0_PHY_BYTE_LANE_2_DRIVE_PAD_CTL_BL_PD_STRENGTH_SHIFT 5 11917 11918 /* DDR34_F0_PHY_BYTE_LANE_2 :: DRIVE_PAD_CTL :: BL_ND_STRENGTH [04:00] */ 11919 #define DDR34_F0_PHY_BYTE_LANE_2_DRIVE_PAD_CTL_BL_ND_STRENGTH_MASK 0x0000001f 11920 #define DDR34_F0_PHY_BYTE_LANE_2_DRIVE_PAD_CTL_BL_ND_STRENGTH_ALIGN 0 11921 #define DDR34_F0_PHY_BYTE_LANE_2_DRIVE_PAD_CTL_BL_ND_STRENGTH_BITS 5 11922 #define DDR34_F0_PHY_BYTE_LANE_2_DRIVE_PAD_CTL_BL_ND_STRENGTH_SHIFT 0 11923 11924 11925 /**************************************************************************** 11926 * DDR34_F0_PHY_BYTE_LANE_2 :: DQSP_DRIVE_PAD_CTL 11927 */ 11928 /* DDR34_F0_PHY_BYTE_LANE_2 :: DQSP_DRIVE_PAD_CTL :: reserved0 [31:20] */ 11929 #define DDR34_F0_PHY_BYTE_LANE_2_DQSP_DRIVE_PAD_CTL_RESERVED0_MASK 0xfff00000 11930 #define DDR34_F0_PHY_BYTE_LANE_2_DQSP_DRIVE_PAD_CTL_RESERVED0_ALIGN 0 11931 #define DDR34_F0_PHY_BYTE_LANE_2_DQSP_DRIVE_PAD_CTL_RESERVED0_BITS 12 11932 #define DDR34_F0_PHY_BYTE_LANE_2_DQSP_DRIVE_PAD_CTL_RESERVED0_SHIFT 20 11933 11934 /* DDR34_F0_PHY_BYTE_LANE_2 :: DQSP_DRIVE_PAD_CTL :: BL_PD_TERM_STRENGTH [19:15] */ 11935 #define DDR34_F0_PHY_BYTE_LANE_2_DQSP_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_MASK 0x000f8000 11936 #define DDR34_F0_PHY_BYTE_LANE_2_DQSP_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_ALIGN 0 11937 #define DDR34_F0_PHY_BYTE_LANE_2_DQSP_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_BITS 5 11938 #define DDR34_F0_PHY_BYTE_LANE_2_DQSP_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_SHIFT 15 11939 11940 /* DDR34_F0_PHY_BYTE_LANE_2 :: DQSP_DRIVE_PAD_CTL :: BL_ND_TERM_STRENGTH [14:10] */ 11941 #define DDR34_F0_PHY_BYTE_LANE_2_DQSP_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_MASK 0x00007c00 11942 #define DDR34_F0_PHY_BYTE_LANE_2_DQSP_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_ALIGN 0 11943 #define DDR34_F0_PHY_BYTE_LANE_2_DQSP_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_BITS 5 11944 #define DDR34_F0_PHY_BYTE_LANE_2_DQSP_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_SHIFT 10 11945 11946 /* DDR34_F0_PHY_BYTE_LANE_2 :: DQSP_DRIVE_PAD_CTL :: BL_PD_STRENGTH [09:05] */ 11947 #define DDR34_F0_PHY_BYTE_LANE_2_DQSP_DRIVE_PAD_CTL_BL_PD_STRENGTH_MASK 0x000003e0 11948 #define DDR34_F0_PHY_BYTE_LANE_2_DQSP_DRIVE_PAD_CTL_BL_PD_STRENGTH_ALIGN 0 11949 #define DDR34_F0_PHY_BYTE_LANE_2_DQSP_DRIVE_PAD_CTL_BL_PD_STRENGTH_BITS 5 11950 #define DDR34_F0_PHY_BYTE_LANE_2_DQSP_DRIVE_PAD_CTL_BL_PD_STRENGTH_SHIFT 5 11951 11952 /* DDR34_F0_PHY_BYTE_LANE_2 :: DQSP_DRIVE_PAD_CTL :: BL_ND_STRENGTH [04:00] */ 11953 #define DDR34_F0_PHY_BYTE_LANE_2_DQSP_DRIVE_PAD_CTL_BL_ND_STRENGTH_MASK 0x0000001f 11954 #define DDR34_F0_PHY_BYTE_LANE_2_DQSP_DRIVE_PAD_CTL_BL_ND_STRENGTH_ALIGN 0 11955 #define DDR34_F0_PHY_BYTE_LANE_2_DQSP_DRIVE_PAD_CTL_BL_ND_STRENGTH_BITS 5 11956 #define DDR34_F0_PHY_BYTE_LANE_2_DQSP_DRIVE_PAD_CTL_BL_ND_STRENGTH_SHIFT 0 11957 11958 11959 /**************************************************************************** 11960 * DDR34_F0_PHY_BYTE_LANE_2 :: DQSN_DRIVE_PAD_CTL 11961 */ 11962 /* DDR34_F0_PHY_BYTE_LANE_2 :: DQSN_DRIVE_PAD_CTL :: reserved0 [31:20] */ 11963 #define DDR34_F0_PHY_BYTE_LANE_2_DQSN_DRIVE_PAD_CTL_RESERVED0_MASK 0xfff00000 11964 #define DDR34_F0_PHY_BYTE_LANE_2_DQSN_DRIVE_PAD_CTL_RESERVED0_ALIGN 0 11965 #define DDR34_F0_PHY_BYTE_LANE_2_DQSN_DRIVE_PAD_CTL_RESERVED0_BITS 12 11966 #define DDR34_F0_PHY_BYTE_LANE_2_DQSN_DRIVE_PAD_CTL_RESERVED0_SHIFT 20 11967 11968 /* DDR34_F0_PHY_BYTE_LANE_2 :: DQSN_DRIVE_PAD_CTL :: BL_PD_TERM_STRENGTH [19:15] */ 11969 #define DDR34_F0_PHY_BYTE_LANE_2_DQSN_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_MASK 0x000f8000 11970 #define DDR34_F0_PHY_BYTE_LANE_2_DQSN_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_ALIGN 0 11971 #define DDR34_F0_PHY_BYTE_LANE_2_DQSN_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_BITS 5 11972 #define DDR34_F0_PHY_BYTE_LANE_2_DQSN_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_SHIFT 15 11973 11974 /* DDR34_F0_PHY_BYTE_LANE_2 :: DQSN_DRIVE_PAD_CTL :: BL_ND_TERM_STRENGTH [14:10] */ 11975 #define DDR34_F0_PHY_BYTE_LANE_2_DQSN_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_MASK 0x00007c00 11976 #define DDR34_F0_PHY_BYTE_LANE_2_DQSN_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_ALIGN 0 11977 #define DDR34_F0_PHY_BYTE_LANE_2_DQSN_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_BITS 5 11978 #define DDR34_F0_PHY_BYTE_LANE_2_DQSN_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_SHIFT 10 11979 11980 /* DDR34_F0_PHY_BYTE_LANE_2 :: DQSN_DRIVE_PAD_CTL :: BL_PD_STRENGTH [09:05] */ 11981 #define DDR34_F0_PHY_BYTE_LANE_2_DQSN_DRIVE_PAD_CTL_BL_PD_STRENGTH_MASK 0x000003e0 11982 #define DDR34_F0_PHY_BYTE_LANE_2_DQSN_DRIVE_PAD_CTL_BL_PD_STRENGTH_ALIGN 0 11983 #define DDR34_F0_PHY_BYTE_LANE_2_DQSN_DRIVE_PAD_CTL_BL_PD_STRENGTH_BITS 5 11984 #define DDR34_F0_PHY_BYTE_LANE_2_DQSN_DRIVE_PAD_CTL_BL_PD_STRENGTH_SHIFT 5 11985 11986 /* DDR34_F0_PHY_BYTE_LANE_2 :: DQSN_DRIVE_PAD_CTL :: BL_ND_STRENGTH [04:00] */ 11987 #define DDR34_F0_PHY_BYTE_LANE_2_DQSN_DRIVE_PAD_CTL_BL_ND_STRENGTH_MASK 0x0000001f 11988 #define DDR34_F0_PHY_BYTE_LANE_2_DQSN_DRIVE_PAD_CTL_BL_ND_STRENGTH_ALIGN 0 11989 #define DDR34_F0_PHY_BYTE_LANE_2_DQSN_DRIVE_PAD_CTL_BL_ND_STRENGTH_BITS 5 11990 #define DDR34_F0_PHY_BYTE_LANE_2_DQSN_DRIVE_PAD_CTL_BL_ND_STRENGTH_SHIFT 0 11991 11992 11993 /**************************************************************************** 11994 * DDR34_F0_PHY_BYTE_LANE_2 :: ALERT_DRIVE_PAD_CTL 11995 */ 11996 /* DDR34_F0_PHY_BYTE_LANE_2 :: ALERT_DRIVE_PAD_CTL :: reserved0 [31:20] */ 11997 #define DDR34_F0_PHY_BYTE_LANE_2_ALERT_DRIVE_PAD_CTL_RESERVED0_MASK 0xfff00000 11998 #define DDR34_F0_PHY_BYTE_LANE_2_ALERT_DRIVE_PAD_CTL_RESERVED0_ALIGN 0 11999 #define DDR34_F0_PHY_BYTE_LANE_2_ALERT_DRIVE_PAD_CTL_RESERVED0_BITS 12 12000 #define DDR34_F0_PHY_BYTE_LANE_2_ALERT_DRIVE_PAD_CTL_RESERVED0_SHIFT 20 12001 12002 /* DDR34_F0_PHY_BYTE_LANE_2 :: ALERT_DRIVE_PAD_CTL :: BL_PD_TERM_STRENGTH [19:15] */ 12003 #define DDR34_F0_PHY_BYTE_LANE_2_ALERT_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_MASK 0x000f8000 12004 #define DDR34_F0_PHY_BYTE_LANE_2_ALERT_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_ALIGN 0 12005 #define DDR34_F0_PHY_BYTE_LANE_2_ALERT_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_BITS 5 12006 #define DDR34_F0_PHY_BYTE_LANE_2_ALERT_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_SHIFT 15 12007 12008 /* DDR34_F0_PHY_BYTE_LANE_2 :: ALERT_DRIVE_PAD_CTL :: BL_ND_TERM_STRENGTH [14:10] */ 12009 #define DDR34_F0_PHY_BYTE_LANE_2_ALERT_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_MASK 0x00007c00 12010 #define DDR34_F0_PHY_BYTE_LANE_2_ALERT_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_ALIGN 0 12011 #define DDR34_F0_PHY_BYTE_LANE_2_ALERT_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_BITS 5 12012 #define DDR34_F0_PHY_BYTE_LANE_2_ALERT_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_SHIFT 10 12013 12014 /* DDR34_F0_PHY_BYTE_LANE_2 :: ALERT_DRIVE_PAD_CTL :: BL_PD_STRENGTH [09:05] */ 12015 #define DDR34_F0_PHY_BYTE_LANE_2_ALERT_DRIVE_PAD_CTL_BL_PD_STRENGTH_MASK 0x000003e0 12016 #define DDR34_F0_PHY_BYTE_LANE_2_ALERT_DRIVE_PAD_CTL_BL_PD_STRENGTH_ALIGN 0 12017 #define DDR34_F0_PHY_BYTE_LANE_2_ALERT_DRIVE_PAD_CTL_BL_PD_STRENGTH_BITS 5 12018 #define DDR34_F0_PHY_BYTE_LANE_2_ALERT_DRIVE_PAD_CTL_BL_PD_STRENGTH_SHIFT 5 12019 12020 /* DDR34_F0_PHY_BYTE_LANE_2 :: ALERT_DRIVE_PAD_CTL :: BL_ND_STRENGTH [04:00] */ 12021 #define DDR34_F0_PHY_BYTE_LANE_2_ALERT_DRIVE_PAD_CTL_BL_ND_STRENGTH_MASK 0x0000001f 12022 #define DDR34_F0_PHY_BYTE_LANE_2_ALERT_DRIVE_PAD_CTL_BL_ND_STRENGTH_ALIGN 0 12023 #define DDR34_F0_PHY_BYTE_LANE_2_ALERT_DRIVE_PAD_CTL_BL_ND_STRENGTH_BITS 5 12024 #define DDR34_F0_PHY_BYTE_LANE_2_ALERT_DRIVE_PAD_CTL_BL_ND_STRENGTH_SHIFT 0 12025 12026 12027 /**************************************************************************** 12028 * DDR34_F0_PHY_BYTE_LANE_2 :: RD_EN_DRIVE_PAD_CTL 12029 */ 12030 /* DDR34_F0_PHY_BYTE_LANE_2 :: RD_EN_DRIVE_PAD_CTL :: reserved0 [31:10] */ 12031 #define DDR34_F0_PHY_BYTE_LANE_2_RD_EN_DRIVE_PAD_CTL_RESERVED0_MASK 0xfffffc00 12032 #define DDR34_F0_PHY_BYTE_LANE_2_RD_EN_DRIVE_PAD_CTL_RESERVED0_ALIGN 0 12033 #define DDR34_F0_PHY_BYTE_LANE_2_RD_EN_DRIVE_PAD_CTL_RESERVED0_BITS 22 12034 #define DDR34_F0_PHY_BYTE_LANE_2_RD_EN_DRIVE_PAD_CTL_RESERVED0_SHIFT 10 12035 12036 /* DDR34_F0_PHY_BYTE_LANE_2 :: RD_EN_DRIVE_PAD_CTL :: BL_RD_EN_PD_STRENGTH [09:05] */ 12037 #define DDR34_F0_PHY_BYTE_LANE_2_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_PD_STRENGTH_MASK 0x000003e0 12038 #define DDR34_F0_PHY_BYTE_LANE_2_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_PD_STRENGTH_ALIGN 0 12039 #define DDR34_F0_PHY_BYTE_LANE_2_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_PD_STRENGTH_BITS 5 12040 #define DDR34_F0_PHY_BYTE_LANE_2_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_PD_STRENGTH_SHIFT 5 12041 12042 /* DDR34_F0_PHY_BYTE_LANE_2 :: RD_EN_DRIVE_PAD_CTL :: BL_RD_EN_ND_STRENGTH [04:00] */ 12043 #define DDR34_F0_PHY_BYTE_LANE_2_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_ND_STRENGTH_MASK 0x0000001f 12044 #define DDR34_F0_PHY_BYTE_LANE_2_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_ND_STRENGTH_ALIGN 0 12045 #define DDR34_F0_PHY_BYTE_LANE_2_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_ND_STRENGTH_BITS 5 12046 #define DDR34_F0_PHY_BYTE_LANE_2_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_ND_STRENGTH_SHIFT 0 12047 12048 12049 /**************************************************************************** 12050 * DDR34_F0_PHY_BYTE_LANE_2 :: STATIC_PAD_CTL 12051 */ 12052 /* DDR34_F0_PHY_BYTE_LANE_2 :: STATIC_PAD_CTL :: reserved0 [31:18] */ 12053 #define DDR34_F0_PHY_BYTE_LANE_2_STATIC_PAD_CTL_RESERVED0_MASK 0xfffc0000 12054 #define DDR34_F0_PHY_BYTE_LANE_2_STATIC_PAD_CTL_RESERVED0_ALIGN 0 12055 #define DDR34_F0_PHY_BYTE_LANE_2_STATIC_PAD_CTL_RESERVED0_BITS 14 12056 #define DDR34_F0_PHY_BYTE_LANE_2_STATIC_PAD_CTL_RESERVED0_SHIFT 18 12057 12058 /* DDR34_F0_PHY_BYTE_LANE_2 :: STATIC_PAD_CTL :: DM_INVERT [17:17] */ 12059 #define DDR34_F0_PHY_BYTE_LANE_2_STATIC_PAD_CTL_DM_INVERT_MASK 0x00020000 12060 #define DDR34_F0_PHY_BYTE_LANE_2_STATIC_PAD_CTL_DM_INVERT_ALIGN 0 12061 #define DDR34_F0_PHY_BYTE_LANE_2_STATIC_PAD_CTL_DM_INVERT_BITS 1 12062 #define DDR34_F0_PHY_BYTE_LANE_2_STATIC_PAD_CTL_DM_INVERT_SHIFT 17 12063 12064 /* DDR34_F0_PHY_BYTE_LANE_2 :: STATIC_PAD_CTL :: WDBI_ENABLE [16:16] */ 12065 #define DDR34_F0_PHY_BYTE_LANE_2_STATIC_PAD_CTL_WDBI_ENABLE_MASK 0x00010000 12066 #define DDR34_F0_PHY_BYTE_LANE_2_STATIC_PAD_CTL_WDBI_ENABLE_ALIGN 0 12067 #define DDR34_F0_PHY_BYTE_LANE_2_STATIC_PAD_CTL_WDBI_ENABLE_BITS 1 12068 #define DDR34_F0_PHY_BYTE_LANE_2_STATIC_PAD_CTL_WDBI_ENABLE_SHIFT 16 12069 12070 /* DDR34_F0_PHY_BYTE_LANE_2 :: STATIC_PAD_CTL :: RDBI_ENABLE [15:15] */ 12071 #define DDR34_F0_PHY_BYTE_LANE_2_STATIC_PAD_CTL_RDBI_ENABLE_MASK 0x00008000 12072 #define DDR34_F0_PHY_BYTE_LANE_2_STATIC_PAD_CTL_RDBI_ENABLE_ALIGN 0 12073 #define DDR34_F0_PHY_BYTE_LANE_2_STATIC_PAD_CTL_RDBI_ENABLE_BITS 1 12074 #define DDR34_F0_PHY_BYTE_LANE_2_STATIC_PAD_CTL_RDBI_ENABLE_SHIFT 15 12075 12076 /* DDR34_F0_PHY_BYTE_LANE_2 :: STATIC_PAD_CTL :: DM_MODE [14:14] */ 12077 #define DDR34_F0_PHY_BYTE_LANE_2_STATIC_PAD_CTL_DM_MODE_MASK 0x00004000 12078 #define DDR34_F0_PHY_BYTE_LANE_2_STATIC_PAD_CTL_DM_MODE_ALIGN 0 12079 #define DDR34_F0_PHY_BYTE_LANE_2_STATIC_PAD_CTL_DM_MODE_BITS 1 12080 #define DDR34_F0_PHY_BYTE_LANE_2_STATIC_PAD_CTL_DM_MODE_SHIFT 14 12081 12082 /* DDR34_F0_PHY_BYTE_LANE_2 :: STATIC_PAD_CTL :: reserved1 [13:10] */ 12083 #define DDR34_F0_PHY_BYTE_LANE_2_STATIC_PAD_CTL_RESERVED1_MASK 0x00003c00 12084 #define DDR34_F0_PHY_BYTE_LANE_2_STATIC_PAD_CTL_RESERVED1_ALIGN 0 12085 #define DDR34_F0_PHY_BYTE_LANE_2_STATIC_PAD_CTL_RESERVED1_BITS 4 12086 #define DDR34_F0_PHY_BYTE_LANE_2_STATIC_PAD_CTL_RESERVED1_SHIFT 10 12087 12088 /* DDR34_F0_PHY_BYTE_LANE_2 :: STATIC_PAD_CTL :: DQS_TX_DIS [09:09] */ 12089 #define DDR34_F0_PHY_BYTE_LANE_2_STATIC_PAD_CTL_DQS_TX_DIS_MASK 0x00000200 12090 #define DDR34_F0_PHY_BYTE_LANE_2_STATIC_PAD_CTL_DQS_TX_DIS_ALIGN 0 12091 #define DDR34_F0_PHY_BYTE_LANE_2_STATIC_PAD_CTL_DQS_TX_DIS_BITS 1 12092 #define DDR34_F0_PHY_BYTE_LANE_2_STATIC_PAD_CTL_DQS_TX_DIS_SHIFT 9 12093 12094 /* DDR34_F0_PHY_BYTE_LANE_2 :: STATIC_PAD_CTL :: reserved2 [08:02] */ 12095 #define DDR34_F0_PHY_BYTE_LANE_2_STATIC_PAD_CTL_RESERVED2_MASK 0x000001fc 12096 #define DDR34_F0_PHY_BYTE_LANE_2_STATIC_PAD_CTL_RESERVED2_ALIGN 0 12097 #define DDR34_F0_PHY_BYTE_LANE_2_STATIC_PAD_CTL_RESERVED2_BITS 7 12098 #define DDR34_F0_PHY_BYTE_LANE_2_STATIC_PAD_CTL_RESERVED2_SHIFT 2 12099 12100 /* DDR34_F0_PHY_BYTE_LANE_2 :: STATIC_PAD_CTL :: RX_MODE [01:00] */ 12101 #define DDR34_F0_PHY_BYTE_LANE_2_STATIC_PAD_CTL_RX_MODE_MASK 0x00000003 12102 #define DDR34_F0_PHY_BYTE_LANE_2_STATIC_PAD_CTL_RX_MODE_ALIGN 0 12103 #define DDR34_F0_PHY_BYTE_LANE_2_STATIC_PAD_CTL_RX_MODE_BITS 2 12104 #define DDR34_F0_PHY_BYTE_LANE_2_STATIC_PAD_CTL_RX_MODE_SHIFT 0 12105 12106 12107 /**************************************************************************** 12108 * DDR34_F0_PHY_BYTE_LANE_2 :: WR_PREAMBLE_MODE 12109 */ 12110 /* DDR34_F0_PHY_BYTE_LANE_2 :: WR_PREAMBLE_MODE :: reserved0 [31:21] */ 12111 #define DDR34_F0_PHY_BYTE_LANE_2_WR_PREAMBLE_MODE_RESERVED0_MASK 0xffe00000 12112 #define DDR34_F0_PHY_BYTE_LANE_2_WR_PREAMBLE_MODE_RESERVED0_ALIGN 0 12113 #define DDR34_F0_PHY_BYTE_LANE_2_WR_PREAMBLE_MODE_RESERVED0_BITS 11 12114 #define DDR34_F0_PHY_BYTE_LANE_2_WR_PREAMBLE_MODE_RESERVED0_SHIFT 21 12115 12116 /* DDR34_F0_PHY_BYTE_LANE_2 :: WR_PREAMBLE_MODE :: POSTAM_TERM_BITS [20:19] */ 12117 #define DDR34_F0_PHY_BYTE_LANE_2_WR_PREAMBLE_MODE_POSTAM_TERM_BITS_MASK 0x00180000 12118 #define DDR34_F0_PHY_BYTE_LANE_2_WR_PREAMBLE_MODE_POSTAM_TERM_BITS_ALIGN 0 12119 #define DDR34_F0_PHY_BYTE_LANE_2_WR_PREAMBLE_MODE_POSTAM_TERM_BITS_BITS 2 12120 #define DDR34_F0_PHY_BYTE_LANE_2_WR_PREAMBLE_MODE_POSTAM_TERM_BITS_SHIFT 19 12121 12122 /* DDR34_F0_PHY_BYTE_LANE_2 :: WR_PREAMBLE_MODE :: DM_POSTAM_BITS [18:17] */ 12123 #define DDR34_F0_PHY_BYTE_LANE_2_WR_PREAMBLE_MODE_DM_POSTAM_BITS_MASK 0x00060000 12124 #define DDR34_F0_PHY_BYTE_LANE_2_WR_PREAMBLE_MODE_DM_POSTAM_BITS_ALIGN 0 12125 #define DDR34_F0_PHY_BYTE_LANE_2_WR_PREAMBLE_MODE_DM_POSTAM_BITS_BITS 2 12126 #define DDR34_F0_PHY_BYTE_LANE_2_WR_PREAMBLE_MODE_DM_POSTAM_BITS_SHIFT 17 12127 12128 /* DDR34_F0_PHY_BYTE_LANE_2 :: WR_PREAMBLE_MODE :: DM_PREAM_BITS [16:14] */ 12129 #define DDR34_F0_PHY_BYTE_LANE_2_WR_PREAMBLE_MODE_DM_PREAM_BITS_MASK 0x0001c000 12130 #define DDR34_F0_PHY_BYTE_LANE_2_WR_PREAMBLE_MODE_DM_PREAM_BITS_ALIGN 0 12131 #define DDR34_F0_PHY_BYTE_LANE_2_WR_PREAMBLE_MODE_DM_PREAM_BITS_BITS 3 12132 #define DDR34_F0_PHY_BYTE_LANE_2_WR_PREAMBLE_MODE_DM_PREAM_BITS_SHIFT 14 12133 12134 /* DDR34_F0_PHY_BYTE_LANE_2 :: WR_PREAMBLE_MODE :: DQ_POSTAM_BITS [13:12] */ 12135 #define DDR34_F0_PHY_BYTE_LANE_2_WR_PREAMBLE_MODE_DQ_POSTAM_BITS_MASK 0x00003000 12136 #define DDR34_F0_PHY_BYTE_LANE_2_WR_PREAMBLE_MODE_DQ_POSTAM_BITS_ALIGN 0 12137 #define DDR34_F0_PHY_BYTE_LANE_2_WR_PREAMBLE_MODE_DQ_POSTAM_BITS_BITS 2 12138 #define DDR34_F0_PHY_BYTE_LANE_2_WR_PREAMBLE_MODE_DQ_POSTAM_BITS_SHIFT 12 12139 12140 /* DDR34_F0_PHY_BYTE_LANE_2 :: WR_PREAMBLE_MODE :: DQ_PREAM_BITS [11:09] */ 12141 #define DDR34_F0_PHY_BYTE_LANE_2_WR_PREAMBLE_MODE_DQ_PREAM_BITS_MASK 0x00000e00 12142 #define DDR34_F0_PHY_BYTE_LANE_2_WR_PREAMBLE_MODE_DQ_PREAM_BITS_ALIGN 0 12143 #define DDR34_F0_PHY_BYTE_LANE_2_WR_PREAMBLE_MODE_DQ_PREAM_BITS_BITS 3 12144 #define DDR34_F0_PHY_BYTE_LANE_2_WR_PREAMBLE_MODE_DQ_PREAM_BITS_SHIFT 9 12145 12146 /* DDR34_F0_PHY_BYTE_LANE_2 :: WR_PREAMBLE_MODE :: DQS [08:05] */ 12147 #define DDR34_F0_PHY_BYTE_LANE_2_WR_PREAMBLE_MODE_DQS_MASK 0x000001e0 12148 #define DDR34_F0_PHY_BYTE_LANE_2_WR_PREAMBLE_MODE_DQS_ALIGN 0 12149 #define DDR34_F0_PHY_BYTE_LANE_2_WR_PREAMBLE_MODE_DQS_BITS 4 12150 #define DDR34_F0_PHY_BYTE_LANE_2_WR_PREAMBLE_MODE_DQS_SHIFT 5 12151 12152 /* DDR34_F0_PHY_BYTE_LANE_2 :: WR_PREAMBLE_MODE :: DQS_POSTAM_BITS [04:03] */ 12153 #define DDR34_F0_PHY_BYTE_LANE_2_WR_PREAMBLE_MODE_DQS_POSTAM_BITS_MASK 0x00000018 12154 #define DDR34_F0_PHY_BYTE_LANE_2_WR_PREAMBLE_MODE_DQS_POSTAM_BITS_ALIGN 0 12155 #define DDR34_F0_PHY_BYTE_LANE_2_WR_PREAMBLE_MODE_DQS_POSTAM_BITS_BITS 2 12156 #define DDR34_F0_PHY_BYTE_LANE_2_WR_PREAMBLE_MODE_DQS_POSTAM_BITS_SHIFT 3 12157 12158 /* DDR34_F0_PHY_BYTE_LANE_2 :: WR_PREAMBLE_MODE :: DQS_PREAM_BITS [02:00] */ 12159 #define DDR34_F0_PHY_BYTE_LANE_2_WR_PREAMBLE_MODE_DQS_PREAM_BITS_MASK 0x00000007 12160 #define DDR34_F0_PHY_BYTE_LANE_2_WR_PREAMBLE_MODE_DQS_PREAM_BITS_ALIGN 0 12161 #define DDR34_F0_PHY_BYTE_LANE_2_WR_PREAMBLE_MODE_DQS_PREAM_BITS_BITS 3 12162 #define DDR34_F0_PHY_BYTE_LANE_2_WR_PREAMBLE_MODE_DQS_PREAM_BITS_SHIFT 0 12163 12164 12165 /**************************************************************************** 12166 * DDR34_F0_PHY_BYTE_LANE_2 :: ODT_CONTROL 12167 */ 12168 /* DDR34_F0_PHY_BYTE_LANE_2 :: ODT_CONTROL :: reserved0 [31:10] */ 12169 #define DDR34_F0_PHY_BYTE_LANE_2_ODT_CONTROL_RESERVED0_MASK 0xfffffc00 12170 #define DDR34_F0_PHY_BYTE_LANE_2_ODT_CONTROL_RESERVED0_ALIGN 0 12171 #define DDR34_F0_PHY_BYTE_LANE_2_ODT_CONTROL_RESERVED0_BITS 22 12172 #define DDR34_F0_PHY_BYTE_LANE_2_ODT_CONTROL_RESERVED0_SHIFT 10 12173 12174 /* DDR34_F0_PHY_BYTE_LANE_2 :: ODT_CONTROL :: ODT_ENABLE [09:09] */ 12175 #define DDR34_F0_PHY_BYTE_LANE_2_ODT_CONTROL_ODT_ENABLE_MASK 0x00000200 12176 #define DDR34_F0_PHY_BYTE_LANE_2_ODT_CONTROL_ODT_ENABLE_ALIGN 0 12177 #define DDR34_F0_PHY_BYTE_LANE_2_ODT_CONTROL_ODT_ENABLE_BITS 1 12178 #define DDR34_F0_PHY_BYTE_LANE_2_ODT_CONTROL_ODT_ENABLE_SHIFT 9 12179 12180 /* DDR34_F0_PHY_BYTE_LANE_2 :: ODT_CONTROL :: ODT_DELAY [08:06] */ 12181 #define DDR34_F0_PHY_BYTE_LANE_2_ODT_CONTROL_ODT_DELAY_MASK 0x000001c0 12182 #define DDR34_F0_PHY_BYTE_LANE_2_ODT_CONTROL_ODT_DELAY_ALIGN 0 12183 #define DDR34_F0_PHY_BYTE_LANE_2_ODT_CONTROL_ODT_DELAY_BITS 3 12184 #define DDR34_F0_PHY_BYTE_LANE_2_ODT_CONTROL_ODT_DELAY_SHIFT 6 12185 12186 /* DDR34_F0_PHY_BYTE_LANE_2 :: ODT_CONTROL :: ODT_POST_LENGTH [05:03] */ 12187 #define DDR34_F0_PHY_BYTE_LANE_2_ODT_CONTROL_ODT_POST_LENGTH_MASK 0x00000038 12188 #define DDR34_F0_PHY_BYTE_LANE_2_ODT_CONTROL_ODT_POST_LENGTH_ALIGN 0 12189 #define DDR34_F0_PHY_BYTE_LANE_2_ODT_CONTROL_ODT_POST_LENGTH_BITS 3 12190 #define DDR34_F0_PHY_BYTE_LANE_2_ODT_CONTROL_ODT_POST_LENGTH_SHIFT 3 12191 12192 /* DDR34_F0_PHY_BYTE_LANE_2 :: ODT_CONTROL :: reserved1 [02:02] */ 12193 #define DDR34_F0_PHY_BYTE_LANE_2_ODT_CONTROL_RESERVED1_MASK 0x00000004 12194 #define DDR34_F0_PHY_BYTE_LANE_2_ODT_CONTROL_RESERVED1_ALIGN 0 12195 #define DDR34_F0_PHY_BYTE_LANE_2_ODT_CONTROL_RESERVED1_BITS 1 12196 #define DDR34_F0_PHY_BYTE_LANE_2_ODT_CONTROL_RESERVED1_SHIFT 2 12197 12198 /* DDR34_F0_PHY_BYTE_LANE_2 :: ODT_CONTROL :: ODT_PRE_LENGTH [01:00] */ 12199 #define DDR34_F0_PHY_BYTE_LANE_2_ODT_CONTROL_ODT_PRE_LENGTH_MASK 0x00000003 12200 #define DDR34_F0_PHY_BYTE_LANE_2_ODT_CONTROL_ODT_PRE_LENGTH_ALIGN 0 12201 #define DDR34_F0_PHY_BYTE_LANE_2_ODT_CONTROL_ODT_PRE_LENGTH_BITS 2 12202 #define DDR34_F0_PHY_BYTE_LANE_2_ODT_CONTROL_ODT_PRE_LENGTH_SHIFT 0 12203 12204 12205 /**************************************************************************** 12206 * DDR34_F0_PHY_BYTE_LANE_2 :: CLOCK_ENABLE 12207 */ 12208 /* DDR34_F0_PHY_BYTE_LANE_2 :: CLOCK_ENABLE :: reserved0 [31:03] */ 12209 #define DDR34_F0_PHY_BYTE_LANE_2_CLOCK_ENABLE_RESERVED0_MASK 0xfffffff8 12210 #define DDR34_F0_PHY_BYTE_LANE_2_CLOCK_ENABLE_RESERVED0_ALIGN 0 12211 #define DDR34_F0_PHY_BYTE_LANE_2_CLOCK_ENABLE_RESERVED0_BITS 29 12212 #define DDR34_F0_PHY_BYTE_LANE_2_CLOCK_ENABLE_RESERVED0_SHIFT 3 12213 12214 /* DDR34_F0_PHY_BYTE_LANE_2 :: CLOCK_ENABLE :: TO_MC_CLOCK [02:02] */ 12215 #define DDR34_F0_PHY_BYTE_LANE_2_CLOCK_ENABLE_TO_MC_CLOCK_MASK 0x00000004 12216 #define DDR34_F0_PHY_BYTE_LANE_2_CLOCK_ENABLE_TO_MC_CLOCK_ALIGN 0 12217 #define DDR34_F0_PHY_BYTE_LANE_2_CLOCK_ENABLE_TO_MC_CLOCK_BITS 1 12218 #define DDR34_F0_PHY_BYTE_LANE_2_CLOCK_ENABLE_TO_MC_CLOCK_SHIFT 2 12219 12220 /* DDR34_F0_PHY_BYTE_LANE_2 :: CLOCK_ENABLE :: FROM_MC_CLOCK [01:01] */ 12221 #define DDR34_F0_PHY_BYTE_LANE_2_CLOCK_ENABLE_FROM_MC_CLOCK_MASK 0x00000002 12222 #define DDR34_F0_PHY_BYTE_LANE_2_CLOCK_ENABLE_FROM_MC_CLOCK_ALIGN 0 12223 #define DDR34_F0_PHY_BYTE_LANE_2_CLOCK_ENABLE_FROM_MC_CLOCK_BITS 1 12224 #define DDR34_F0_PHY_BYTE_LANE_2_CLOCK_ENABLE_FROM_MC_CLOCK_SHIFT 1 12225 12226 /* DDR34_F0_PHY_BYTE_LANE_2 :: CLOCK_ENABLE :: BIT_CLOCK [00:00] */ 12227 #define DDR34_F0_PHY_BYTE_LANE_2_CLOCK_ENABLE_BIT_CLOCK_MASK 0x00000001 12228 #define DDR34_F0_PHY_BYTE_LANE_2_CLOCK_ENABLE_BIT_CLOCK_ALIGN 0 12229 #define DDR34_F0_PHY_BYTE_LANE_2_CLOCK_ENABLE_BIT_CLOCK_BITS 1 12230 #define DDR34_F0_PHY_BYTE_LANE_2_CLOCK_ENABLE_BIT_CLOCK_SHIFT 0 12231 12232 12233 /**************************************************************************** 12234 * DDR34_F0_PHY_BYTE_LANE_2 :: CLOCK_IDLE 12235 */ 12236 /* DDR34_F0_PHY_BYTE_LANE_2 :: CLOCK_IDLE :: reserved0 [31:03] */ 12237 #define DDR34_F0_PHY_BYTE_LANE_2_CLOCK_IDLE_RESERVED0_MASK 0xfffffff8 12238 #define DDR34_F0_PHY_BYTE_LANE_2_CLOCK_IDLE_RESERVED0_ALIGN 0 12239 #define DDR34_F0_PHY_BYTE_LANE_2_CLOCK_IDLE_RESERVED0_BITS 29 12240 #define DDR34_F0_PHY_BYTE_LANE_2_CLOCK_IDLE_RESERVED0_SHIFT 3 12241 12242 /* DDR34_F0_PHY_BYTE_LANE_2 :: CLOCK_IDLE :: TO_MC_CLOCK [02:02] */ 12243 #define DDR34_F0_PHY_BYTE_LANE_2_CLOCK_IDLE_TO_MC_CLOCK_MASK 0x00000004 12244 #define DDR34_F0_PHY_BYTE_LANE_2_CLOCK_IDLE_TO_MC_CLOCK_ALIGN 0 12245 #define DDR34_F0_PHY_BYTE_LANE_2_CLOCK_IDLE_TO_MC_CLOCK_BITS 1 12246 #define DDR34_F0_PHY_BYTE_LANE_2_CLOCK_IDLE_TO_MC_CLOCK_SHIFT 2 12247 12248 /* DDR34_F0_PHY_BYTE_LANE_2 :: CLOCK_IDLE :: FROM_MC_CLOCK [01:01] */ 12249 #define DDR34_F0_PHY_BYTE_LANE_2_CLOCK_IDLE_FROM_MC_CLOCK_MASK 0x00000002 12250 #define DDR34_F0_PHY_BYTE_LANE_2_CLOCK_IDLE_FROM_MC_CLOCK_ALIGN 0 12251 #define DDR34_F0_PHY_BYTE_LANE_2_CLOCK_IDLE_FROM_MC_CLOCK_BITS 1 12252 #define DDR34_F0_PHY_BYTE_LANE_2_CLOCK_IDLE_FROM_MC_CLOCK_SHIFT 1 12253 12254 /* DDR34_F0_PHY_BYTE_LANE_2 :: CLOCK_IDLE :: BIT_CLOCK [00:00] */ 12255 #define DDR34_F0_PHY_BYTE_LANE_2_CLOCK_IDLE_BIT_CLOCK_MASK 0x00000001 12256 #define DDR34_F0_PHY_BYTE_LANE_2_CLOCK_IDLE_BIT_CLOCK_ALIGN 0 12257 #define DDR34_F0_PHY_BYTE_LANE_2_CLOCK_IDLE_BIT_CLOCK_BITS 1 12258 #define DDR34_F0_PHY_BYTE_LANE_2_CLOCK_IDLE_BIT_CLOCK_SHIFT 0 12259 12260 12261 /**************************************************************************** 12262 * DDR34_F0_PHY_BYTE_LANE_2 :: BL_SPARE_REG 12263 */ 12264 /* DDR34_F0_PHY_BYTE_LANE_2 :: BL_SPARE_REG :: reserved_for_eco0 [31:00] */ 12265 #define DDR34_F0_PHY_BYTE_LANE_2_BL_SPARE_REG_RESERVED_FOR_ECO0_MASK 0xffffffff 12266 #define DDR34_F0_PHY_BYTE_LANE_2_BL_SPARE_REG_RESERVED_FOR_ECO0_ALIGN 0 12267 #define DDR34_F0_PHY_BYTE_LANE_2_BL_SPARE_REG_RESERVED_FOR_ECO0_BITS 32 12268 #define DDR34_F0_PHY_BYTE_LANE_2_BL_SPARE_REG_RESERVED_FOR_ECO0_SHIFT 0 12269 12270 12271 /**************************************************************************** 12272 * DDR34_F0_PHY_DDR34_F0_PHY_BYTE_LANE_3 12273 */ 12274 /**************************************************************************** 12275 * DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DQS 12276 */ 12277 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DQS :: BUSY [31:31] */ 12278 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_BUSY_MASK 0x80000000 12279 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_BUSY_ALIGN 0 12280 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_BUSY_BITS 1 12281 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_BUSY_SHIFT 31 12282 12283 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DQS :: reserved0 [30:17] */ 12284 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_RESERVED0_MASK 0x7ffe0000 12285 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_RESERVED0_ALIGN 0 12286 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_RESERVED0_BITS 14 12287 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_RESERVED0_SHIFT 17 12288 12289 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DQS :: FORCE [16:16] */ 12290 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_FORCE_MASK 0x00010000 12291 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_FORCE_ALIGN 0 12292 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_FORCE_BITS 1 12293 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_FORCE_SHIFT 16 12294 12295 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DQS :: reserved1 [15:13] */ 12296 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_RESERVED1_MASK 0x0000e000 12297 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_RESERVED1_ALIGN 0 12298 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_RESERVED1_BITS 3 12299 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_RESERVED1_SHIFT 13 12300 12301 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DQS :: ADJ_EN [12:12] */ 12302 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_ADJ_EN_MASK 0x00001000 12303 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_ADJ_EN_ALIGN 0 12304 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_ADJ_EN_BITS 1 12305 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_ADJ_EN_SHIFT 12 12306 12307 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DQS :: reserved2 [11:09] */ 12308 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_RESERVED2_MASK 0x00000e00 12309 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_RESERVED2_ALIGN 0 12310 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_RESERVED2_BITS 3 12311 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_RESERVED2_SHIFT 9 12312 12313 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DQS :: VDL_STEP [08:00] */ 12314 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_VDL_STEP_MASK 0x000001ff 12315 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_VDL_STEP_ALIGN 0 12316 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_VDL_STEP_BITS 9 12317 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_VDL_STEP_SHIFT 0 12318 12319 12320 /**************************************************************************** 12321 * DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DQ0 12322 */ 12323 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DQ0 :: BUSY [31:31] */ 12324 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ0_BUSY_MASK 0x80000000 12325 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ0_BUSY_ALIGN 0 12326 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ0_BUSY_BITS 1 12327 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ0_BUSY_SHIFT 31 12328 12329 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DQ0 :: reserved0 [30:17] */ 12330 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ0_RESERVED0_MASK 0x7ffe0000 12331 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ0_RESERVED0_ALIGN 0 12332 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ0_RESERVED0_BITS 14 12333 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ0_RESERVED0_SHIFT 17 12334 12335 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DQ0 :: FORCE [16:16] */ 12336 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ0_FORCE_MASK 0x00010000 12337 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ0_FORCE_ALIGN 0 12338 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ0_FORCE_BITS 1 12339 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ0_FORCE_SHIFT 16 12340 12341 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DQ0 :: reserved1 [15:13] */ 12342 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ0_RESERVED1_MASK 0x0000e000 12343 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ0_RESERVED1_ALIGN 0 12344 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ0_RESERVED1_BITS 3 12345 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ0_RESERVED1_SHIFT 13 12346 12347 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DQ0 :: ADJ_EN [12:12] */ 12348 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ0_ADJ_EN_MASK 0x00001000 12349 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ0_ADJ_EN_ALIGN 0 12350 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ0_ADJ_EN_BITS 1 12351 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ0_ADJ_EN_SHIFT 12 12352 12353 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DQ0 :: reserved2 [11:09] */ 12354 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ0_RESERVED2_MASK 0x00000e00 12355 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ0_RESERVED2_ALIGN 0 12356 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ0_RESERVED2_BITS 3 12357 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ0_RESERVED2_SHIFT 9 12358 12359 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DQ0 :: VDL_STEP [08:00] */ 12360 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ0_VDL_STEP_MASK 0x000001ff 12361 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ0_VDL_STEP_ALIGN 0 12362 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ0_VDL_STEP_BITS 9 12363 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ0_VDL_STEP_SHIFT 0 12364 12365 12366 /**************************************************************************** 12367 * DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DQ1 12368 */ 12369 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DQ1 :: BUSY [31:31] */ 12370 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ1_BUSY_MASK 0x80000000 12371 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ1_BUSY_ALIGN 0 12372 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ1_BUSY_BITS 1 12373 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ1_BUSY_SHIFT 31 12374 12375 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DQ1 :: reserved0 [30:17] */ 12376 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ1_RESERVED0_MASK 0x7ffe0000 12377 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ1_RESERVED0_ALIGN 0 12378 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ1_RESERVED0_BITS 14 12379 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ1_RESERVED0_SHIFT 17 12380 12381 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DQ1 :: FORCE [16:16] */ 12382 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ1_FORCE_MASK 0x00010000 12383 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ1_FORCE_ALIGN 0 12384 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ1_FORCE_BITS 1 12385 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ1_FORCE_SHIFT 16 12386 12387 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DQ1 :: reserved1 [15:13] */ 12388 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ1_RESERVED1_MASK 0x0000e000 12389 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ1_RESERVED1_ALIGN 0 12390 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ1_RESERVED1_BITS 3 12391 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ1_RESERVED1_SHIFT 13 12392 12393 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DQ1 :: ADJ_EN [12:12] */ 12394 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ1_ADJ_EN_MASK 0x00001000 12395 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ1_ADJ_EN_ALIGN 0 12396 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ1_ADJ_EN_BITS 1 12397 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ1_ADJ_EN_SHIFT 12 12398 12399 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DQ1 :: reserved2 [11:09] */ 12400 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ1_RESERVED2_MASK 0x00000e00 12401 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ1_RESERVED2_ALIGN 0 12402 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ1_RESERVED2_BITS 3 12403 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ1_RESERVED2_SHIFT 9 12404 12405 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DQ1 :: VDL_STEP [08:00] */ 12406 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ1_VDL_STEP_MASK 0x000001ff 12407 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ1_VDL_STEP_ALIGN 0 12408 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ1_VDL_STEP_BITS 9 12409 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ1_VDL_STEP_SHIFT 0 12410 12411 12412 /**************************************************************************** 12413 * DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DQ2 12414 */ 12415 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DQ2 :: BUSY [31:31] */ 12416 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ2_BUSY_MASK 0x80000000 12417 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ2_BUSY_ALIGN 0 12418 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ2_BUSY_BITS 1 12419 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ2_BUSY_SHIFT 31 12420 12421 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DQ2 :: reserved0 [30:17] */ 12422 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ2_RESERVED0_MASK 0x7ffe0000 12423 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ2_RESERVED0_ALIGN 0 12424 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ2_RESERVED0_BITS 14 12425 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ2_RESERVED0_SHIFT 17 12426 12427 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DQ2 :: FORCE [16:16] */ 12428 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ2_FORCE_MASK 0x00010000 12429 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ2_FORCE_ALIGN 0 12430 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ2_FORCE_BITS 1 12431 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ2_FORCE_SHIFT 16 12432 12433 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DQ2 :: reserved1 [15:13] */ 12434 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ2_RESERVED1_MASK 0x0000e000 12435 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ2_RESERVED1_ALIGN 0 12436 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ2_RESERVED1_BITS 3 12437 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ2_RESERVED1_SHIFT 13 12438 12439 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DQ2 :: ADJ_EN [12:12] */ 12440 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ2_ADJ_EN_MASK 0x00001000 12441 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ2_ADJ_EN_ALIGN 0 12442 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ2_ADJ_EN_BITS 1 12443 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ2_ADJ_EN_SHIFT 12 12444 12445 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DQ2 :: reserved2 [11:09] */ 12446 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ2_RESERVED2_MASK 0x00000e00 12447 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ2_RESERVED2_ALIGN 0 12448 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ2_RESERVED2_BITS 3 12449 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ2_RESERVED2_SHIFT 9 12450 12451 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DQ2 :: VDL_STEP [08:00] */ 12452 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ2_VDL_STEP_MASK 0x000001ff 12453 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ2_VDL_STEP_ALIGN 0 12454 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ2_VDL_STEP_BITS 9 12455 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ2_VDL_STEP_SHIFT 0 12456 12457 12458 /**************************************************************************** 12459 * DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DQ3 12460 */ 12461 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DQ3 :: BUSY [31:31] */ 12462 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ3_BUSY_MASK 0x80000000 12463 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ3_BUSY_ALIGN 0 12464 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ3_BUSY_BITS 1 12465 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ3_BUSY_SHIFT 31 12466 12467 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DQ3 :: reserved0 [30:17] */ 12468 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ3_RESERVED0_MASK 0x7ffe0000 12469 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ3_RESERVED0_ALIGN 0 12470 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ3_RESERVED0_BITS 14 12471 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ3_RESERVED0_SHIFT 17 12472 12473 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DQ3 :: FORCE [16:16] */ 12474 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ3_FORCE_MASK 0x00010000 12475 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ3_FORCE_ALIGN 0 12476 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ3_FORCE_BITS 1 12477 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ3_FORCE_SHIFT 16 12478 12479 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DQ3 :: reserved1 [15:13] */ 12480 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ3_RESERVED1_MASK 0x0000e000 12481 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ3_RESERVED1_ALIGN 0 12482 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ3_RESERVED1_BITS 3 12483 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ3_RESERVED1_SHIFT 13 12484 12485 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DQ3 :: ADJ_EN [12:12] */ 12486 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ3_ADJ_EN_MASK 0x00001000 12487 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ3_ADJ_EN_ALIGN 0 12488 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ3_ADJ_EN_BITS 1 12489 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ3_ADJ_EN_SHIFT 12 12490 12491 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DQ3 :: reserved2 [11:09] */ 12492 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ3_RESERVED2_MASK 0x00000e00 12493 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ3_RESERVED2_ALIGN 0 12494 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ3_RESERVED2_BITS 3 12495 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ3_RESERVED2_SHIFT 9 12496 12497 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DQ3 :: VDL_STEP [08:00] */ 12498 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ3_VDL_STEP_MASK 0x000001ff 12499 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ3_VDL_STEP_ALIGN 0 12500 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ3_VDL_STEP_BITS 9 12501 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ3_VDL_STEP_SHIFT 0 12502 12503 12504 /**************************************************************************** 12505 * DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DQ4 12506 */ 12507 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DQ4 :: BUSY [31:31] */ 12508 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ4_BUSY_MASK 0x80000000 12509 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ4_BUSY_ALIGN 0 12510 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ4_BUSY_BITS 1 12511 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ4_BUSY_SHIFT 31 12512 12513 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DQ4 :: reserved0 [30:17] */ 12514 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ4_RESERVED0_MASK 0x7ffe0000 12515 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ4_RESERVED0_ALIGN 0 12516 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ4_RESERVED0_BITS 14 12517 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ4_RESERVED0_SHIFT 17 12518 12519 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DQ4 :: FORCE [16:16] */ 12520 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ4_FORCE_MASK 0x00010000 12521 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ4_FORCE_ALIGN 0 12522 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ4_FORCE_BITS 1 12523 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ4_FORCE_SHIFT 16 12524 12525 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DQ4 :: reserved1 [15:13] */ 12526 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ4_RESERVED1_MASK 0x0000e000 12527 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ4_RESERVED1_ALIGN 0 12528 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ4_RESERVED1_BITS 3 12529 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ4_RESERVED1_SHIFT 13 12530 12531 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DQ4 :: ADJ_EN [12:12] */ 12532 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ4_ADJ_EN_MASK 0x00001000 12533 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ4_ADJ_EN_ALIGN 0 12534 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ4_ADJ_EN_BITS 1 12535 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ4_ADJ_EN_SHIFT 12 12536 12537 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DQ4 :: reserved2 [11:09] */ 12538 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ4_RESERVED2_MASK 0x00000e00 12539 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ4_RESERVED2_ALIGN 0 12540 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ4_RESERVED2_BITS 3 12541 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ4_RESERVED2_SHIFT 9 12542 12543 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DQ4 :: VDL_STEP [08:00] */ 12544 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ4_VDL_STEP_MASK 0x000001ff 12545 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ4_VDL_STEP_ALIGN 0 12546 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ4_VDL_STEP_BITS 9 12547 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ4_VDL_STEP_SHIFT 0 12548 12549 12550 /**************************************************************************** 12551 * DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DQ5 12552 */ 12553 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DQ5 :: BUSY [31:31] */ 12554 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ5_BUSY_MASK 0x80000000 12555 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ5_BUSY_ALIGN 0 12556 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ5_BUSY_BITS 1 12557 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ5_BUSY_SHIFT 31 12558 12559 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DQ5 :: reserved0 [30:17] */ 12560 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ5_RESERVED0_MASK 0x7ffe0000 12561 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ5_RESERVED0_ALIGN 0 12562 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ5_RESERVED0_BITS 14 12563 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ5_RESERVED0_SHIFT 17 12564 12565 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DQ5 :: FORCE [16:16] */ 12566 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ5_FORCE_MASK 0x00010000 12567 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ5_FORCE_ALIGN 0 12568 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ5_FORCE_BITS 1 12569 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ5_FORCE_SHIFT 16 12570 12571 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DQ5 :: reserved1 [15:13] */ 12572 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ5_RESERVED1_MASK 0x0000e000 12573 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ5_RESERVED1_ALIGN 0 12574 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ5_RESERVED1_BITS 3 12575 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ5_RESERVED1_SHIFT 13 12576 12577 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DQ5 :: ADJ_EN [12:12] */ 12578 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ5_ADJ_EN_MASK 0x00001000 12579 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ5_ADJ_EN_ALIGN 0 12580 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ5_ADJ_EN_BITS 1 12581 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ5_ADJ_EN_SHIFT 12 12582 12583 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DQ5 :: reserved2 [11:09] */ 12584 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ5_RESERVED2_MASK 0x00000e00 12585 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ5_RESERVED2_ALIGN 0 12586 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ5_RESERVED2_BITS 3 12587 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ5_RESERVED2_SHIFT 9 12588 12589 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DQ5 :: VDL_STEP [08:00] */ 12590 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ5_VDL_STEP_MASK 0x000001ff 12591 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ5_VDL_STEP_ALIGN 0 12592 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ5_VDL_STEP_BITS 9 12593 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ5_VDL_STEP_SHIFT 0 12594 12595 12596 /**************************************************************************** 12597 * DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DQ6 12598 */ 12599 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DQ6 :: BUSY [31:31] */ 12600 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ6_BUSY_MASK 0x80000000 12601 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ6_BUSY_ALIGN 0 12602 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ6_BUSY_BITS 1 12603 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ6_BUSY_SHIFT 31 12604 12605 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DQ6 :: reserved0 [30:17] */ 12606 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ6_RESERVED0_MASK 0x7ffe0000 12607 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ6_RESERVED0_ALIGN 0 12608 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ6_RESERVED0_BITS 14 12609 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ6_RESERVED0_SHIFT 17 12610 12611 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DQ6 :: FORCE [16:16] */ 12612 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ6_FORCE_MASK 0x00010000 12613 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ6_FORCE_ALIGN 0 12614 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ6_FORCE_BITS 1 12615 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ6_FORCE_SHIFT 16 12616 12617 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DQ6 :: reserved1 [15:13] */ 12618 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ6_RESERVED1_MASK 0x0000e000 12619 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ6_RESERVED1_ALIGN 0 12620 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ6_RESERVED1_BITS 3 12621 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ6_RESERVED1_SHIFT 13 12622 12623 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DQ6 :: ADJ_EN [12:12] */ 12624 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ6_ADJ_EN_MASK 0x00001000 12625 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ6_ADJ_EN_ALIGN 0 12626 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ6_ADJ_EN_BITS 1 12627 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ6_ADJ_EN_SHIFT 12 12628 12629 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DQ6 :: reserved2 [11:09] */ 12630 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ6_RESERVED2_MASK 0x00000e00 12631 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ6_RESERVED2_ALIGN 0 12632 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ6_RESERVED2_BITS 3 12633 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ6_RESERVED2_SHIFT 9 12634 12635 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DQ6 :: VDL_STEP [08:00] */ 12636 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ6_VDL_STEP_MASK 0x000001ff 12637 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ6_VDL_STEP_ALIGN 0 12638 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ6_VDL_STEP_BITS 9 12639 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ6_VDL_STEP_SHIFT 0 12640 12641 12642 /**************************************************************************** 12643 * DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DQ7 12644 */ 12645 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DQ7 :: BUSY [31:31] */ 12646 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ7_BUSY_MASK 0x80000000 12647 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ7_BUSY_ALIGN 0 12648 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ7_BUSY_BITS 1 12649 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ7_BUSY_SHIFT 31 12650 12651 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DQ7 :: reserved0 [30:17] */ 12652 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ7_RESERVED0_MASK 0x7ffe0000 12653 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ7_RESERVED0_ALIGN 0 12654 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ7_RESERVED0_BITS 14 12655 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ7_RESERVED0_SHIFT 17 12656 12657 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DQ7 :: FORCE [16:16] */ 12658 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ7_FORCE_MASK 0x00010000 12659 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ7_FORCE_ALIGN 0 12660 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ7_FORCE_BITS 1 12661 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ7_FORCE_SHIFT 16 12662 12663 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DQ7 :: reserved1 [15:13] */ 12664 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ7_RESERVED1_MASK 0x0000e000 12665 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ7_RESERVED1_ALIGN 0 12666 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ7_RESERVED1_BITS 3 12667 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ7_RESERVED1_SHIFT 13 12668 12669 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DQ7 :: ADJ_EN [12:12] */ 12670 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ7_ADJ_EN_MASK 0x00001000 12671 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ7_ADJ_EN_ALIGN 0 12672 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ7_ADJ_EN_BITS 1 12673 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ7_ADJ_EN_SHIFT 12 12674 12675 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DQ7 :: reserved2 [11:09] */ 12676 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ7_RESERVED2_MASK 0x00000e00 12677 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ7_RESERVED2_ALIGN 0 12678 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ7_RESERVED2_BITS 3 12679 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ7_RESERVED2_SHIFT 9 12680 12681 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DQ7 :: VDL_STEP [08:00] */ 12682 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ7_VDL_STEP_MASK 0x000001ff 12683 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ7_VDL_STEP_ALIGN 0 12684 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ7_VDL_STEP_BITS 9 12685 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ7_VDL_STEP_SHIFT 0 12686 12687 12688 /**************************************************************************** 12689 * DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DM 12690 */ 12691 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DM :: BUSY [31:31] */ 12692 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DM_BUSY_MASK 0x80000000 12693 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DM_BUSY_ALIGN 0 12694 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DM_BUSY_BITS 1 12695 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DM_BUSY_SHIFT 31 12696 12697 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DM :: reserved0 [30:17] */ 12698 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DM_RESERVED0_MASK 0x7ffe0000 12699 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DM_RESERVED0_ALIGN 0 12700 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DM_RESERVED0_BITS 14 12701 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DM_RESERVED0_SHIFT 17 12702 12703 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DM :: FORCE [16:16] */ 12704 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DM_FORCE_MASK 0x00010000 12705 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DM_FORCE_ALIGN 0 12706 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DM_FORCE_BITS 1 12707 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DM_FORCE_SHIFT 16 12708 12709 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DM :: reserved1 [15:13] */ 12710 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DM_RESERVED1_MASK 0x0000e000 12711 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DM_RESERVED1_ALIGN 0 12712 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DM_RESERVED1_BITS 3 12713 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DM_RESERVED1_SHIFT 13 12714 12715 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DM :: ADJ_EN [12:12] */ 12716 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DM_ADJ_EN_MASK 0x00001000 12717 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DM_ADJ_EN_ALIGN 0 12718 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DM_ADJ_EN_BITS 1 12719 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DM_ADJ_EN_SHIFT 12 12720 12721 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DM :: reserved2 [11:09] */ 12722 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DM_RESERVED2_MASK 0x00000e00 12723 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DM_RESERVED2_ALIGN 0 12724 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DM_RESERVED2_BITS 3 12725 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DM_RESERVED2_SHIFT 9 12726 12727 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DM :: VDL_STEP [08:00] */ 12728 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DM_VDL_STEP_MASK 0x000001ff 12729 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DM_VDL_STEP_ALIGN 0 12730 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DM_VDL_STEP_BITS 9 12731 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DM_VDL_STEP_SHIFT 0 12732 12733 12734 /**************************************************************************** 12735 * DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_ALERT 12736 */ 12737 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_ALERT :: BUSY [31:31] */ 12738 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_ALERT_BUSY_MASK 0x80000000 12739 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_ALERT_BUSY_ALIGN 0 12740 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_ALERT_BUSY_BITS 1 12741 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_ALERT_BUSY_SHIFT 31 12742 12743 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_ALERT :: reserved0 [30:17] */ 12744 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_ALERT_RESERVED0_MASK 0x7ffe0000 12745 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_ALERT_RESERVED0_ALIGN 0 12746 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_ALERT_RESERVED0_BITS 14 12747 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_ALERT_RESERVED0_SHIFT 17 12748 12749 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_ALERT :: FORCE [16:16] */ 12750 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_ALERT_FORCE_MASK 0x00010000 12751 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_ALERT_FORCE_ALIGN 0 12752 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_ALERT_FORCE_BITS 1 12753 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_ALERT_FORCE_SHIFT 16 12754 12755 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_ALERT :: reserved1 [15:13] */ 12756 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_ALERT_RESERVED1_MASK 0x0000e000 12757 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_ALERT_RESERVED1_ALIGN 0 12758 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_ALERT_RESERVED1_BITS 3 12759 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_ALERT_RESERVED1_SHIFT 13 12760 12761 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_ALERT :: ADJ_EN [12:12] */ 12762 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_ALERT_ADJ_EN_MASK 0x00001000 12763 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_ALERT_ADJ_EN_ALIGN 0 12764 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_ALERT_ADJ_EN_BITS 1 12765 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_ALERT_ADJ_EN_SHIFT 12 12766 12767 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_ALERT :: reserved2 [11:09] */ 12768 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_ALERT_RESERVED2_MASK 0x00000e00 12769 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_ALERT_RESERVED2_ALIGN 0 12770 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_ALERT_RESERVED2_BITS 3 12771 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_ALERT_RESERVED2_SHIFT 9 12772 12773 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_ALERT :: VDL_STEP [08:00] */ 12774 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_ALERT_VDL_STEP_MASK 0x000001ff 12775 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_ALERT_VDL_STEP_ALIGN 0 12776 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_ALERT_VDL_STEP_BITS 9 12777 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_ALERT_VDL_STEP_SHIFT 0 12778 12779 12780 /**************************************************************************** 12781 * DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQSP 12782 */ 12783 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQSP :: BUSY [31:31] */ 12784 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSP_BUSY_MASK 0x80000000 12785 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSP_BUSY_ALIGN 0 12786 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSP_BUSY_BITS 1 12787 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSP_BUSY_SHIFT 31 12788 12789 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQSP :: reserved0 [30:17] */ 12790 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSP_RESERVED0_MASK 0x7ffe0000 12791 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSP_RESERVED0_ALIGN 0 12792 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSP_RESERVED0_BITS 14 12793 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSP_RESERVED0_SHIFT 17 12794 12795 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQSP :: FORCE [16:16] */ 12796 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSP_FORCE_MASK 0x00010000 12797 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSP_FORCE_ALIGN 0 12798 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSP_FORCE_BITS 1 12799 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSP_FORCE_SHIFT 16 12800 12801 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQSP :: reserved1 [15:13] */ 12802 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSP_RESERVED1_MASK 0x0000e000 12803 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSP_RESERVED1_ALIGN 0 12804 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSP_RESERVED1_BITS 3 12805 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSP_RESERVED1_SHIFT 13 12806 12807 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQSP :: ADJ_EN [12:12] */ 12808 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSP_ADJ_EN_MASK 0x00001000 12809 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSP_ADJ_EN_ALIGN 0 12810 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSP_ADJ_EN_BITS 1 12811 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSP_ADJ_EN_SHIFT 12 12812 12813 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQSP :: reserved2 [11:08] */ 12814 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSP_RESERVED2_MASK 0x00000f00 12815 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSP_RESERVED2_ALIGN 0 12816 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSP_RESERVED2_BITS 4 12817 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSP_RESERVED2_SHIFT 8 12818 12819 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQSP :: VDL_STEP [07:00] */ 12820 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSP_VDL_STEP_MASK 0x000000ff 12821 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSP_VDL_STEP_ALIGN 0 12822 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSP_VDL_STEP_BITS 8 12823 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSP_VDL_STEP_SHIFT 0 12824 12825 12826 /**************************************************************************** 12827 * DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQSN 12828 */ 12829 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQSN :: BUSY [31:31] */ 12830 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSN_BUSY_MASK 0x80000000 12831 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSN_BUSY_ALIGN 0 12832 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSN_BUSY_BITS 1 12833 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSN_BUSY_SHIFT 31 12834 12835 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQSN :: reserved0 [30:17] */ 12836 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSN_RESERVED0_MASK 0x7ffe0000 12837 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSN_RESERVED0_ALIGN 0 12838 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSN_RESERVED0_BITS 14 12839 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSN_RESERVED0_SHIFT 17 12840 12841 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQSN :: FORCE [16:16] */ 12842 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSN_FORCE_MASK 0x00010000 12843 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSN_FORCE_ALIGN 0 12844 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSN_FORCE_BITS 1 12845 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSN_FORCE_SHIFT 16 12846 12847 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQSN :: reserved1 [15:13] */ 12848 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSN_RESERVED1_MASK 0x0000e000 12849 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSN_RESERVED1_ALIGN 0 12850 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSN_RESERVED1_BITS 3 12851 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSN_RESERVED1_SHIFT 13 12852 12853 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQSN :: ADJ_EN [12:12] */ 12854 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSN_ADJ_EN_MASK 0x00001000 12855 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSN_ADJ_EN_ALIGN 0 12856 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSN_ADJ_EN_BITS 1 12857 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSN_ADJ_EN_SHIFT 12 12858 12859 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQSN :: reserved2 [11:08] */ 12860 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSN_RESERVED2_MASK 0x00000f00 12861 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSN_RESERVED2_ALIGN 0 12862 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSN_RESERVED2_BITS 4 12863 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSN_RESERVED2_SHIFT 8 12864 12865 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQSN :: VDL_STEP [07:00] */ 12866 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSN_VDL_STEP_MASK 0x000000ff 12867 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSN_VDL_STEP_ALIGN 0 12868 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSN_VDL_STEP_BITS 8 12869 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSN_VDL_STEP_SHIFT 0 12870 12871 12872 /**************************************************************************** 12873 * DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ0P 12874 */ 12875 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ0P :: BUSY [31:31] */ 12876 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0P_BUSY_MASK 0x80000000 12877 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0P_BUSY_ALIGN 0 12878 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0P_BUSY_BITS 1 12879 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0P_BUSY_SHIFT 31 12880 12881 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ0P :: reserved0 [30:17] */ 12882 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0P_RESERVED0_MASK 0x7ffe0000 12883 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0P_RESERVED0_ALIGN 0 12884 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0P_RESERVED0_BITS 14 12885 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0P_RESERVED0_SHIFT 17 12886 12887 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ0P :: FORCE [16:16] */ 12888 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0P_FORCE_MASK 0x00010000 12889 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0P_FORCE_ALIGN 0 12890 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0P_FORCE_BITS 1 12891 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0P_FORCE_SHIFT 16 12892 12893 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ0P :: reserved1 [15:13] */ 12894 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0P_RESERVED1_MASK 0x0000e000 12895 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0P_RESERVED1_ALIGN 0 12896 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0P_RESERVED1_BITS 3 12897 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0P_RESERVED1_SHIFT 13 12898 12899 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ0P :: ADJ_EN [12:12] */ 12900 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0P_ADJ_EN_MASK 0x00001000 12901 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0P_ADJ_EN_ALIGN 0 12902 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0P_ADJ_EN_BITS 1 12903 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0P_ADJ_EN_SHIFT 12 12904 12905 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ0P :: reserved2 [11:08] */ 12906 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0P_RESERVED2_MASK 0x00000f00 12907 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0P_RESERVED2_ALIGN 0 12908 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0P_RESERVED2_BITS 4 12909 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0P_RESERVED2_SHIFT 8 12910 12911 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ0P :: VDL_STEP [07:00] */ 12912 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0P_VDL_STEP_MASK 0x000000ff 12913 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0P_VDL_STEP_ALIGN 0 12914 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0P_VDL_STEP_BITS 8 12915 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0P_VDL_STEP_SHIFT 0 12916 12917 12918 /**************************************************************************** 12919 * DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ0N 12920 */ 12921 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ0N :: BUSY [31:31] */ 12922 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0N_BUSY_MASK 0x80000000 12923 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0N_BUSY_ALIGN 0 12924 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0N_BUSY_BITS 1 12925 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0N_BUSY_SHIFT 31 12926 12927 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ0N :: reserved0 [30:17] */ 12928 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0N_RESERVED0_MASK 0x7ffe0000 12929 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0N_RESERVED0_ALIGN 0 12930 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0N_RESERVED0_BITS 14 12931 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0N_RESERVED0_SHIFT 17 12932 12933 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ0N :: FORCE [16:16] */ 12934 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0N_FORCE_MASK 0x00010000 12935 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0N_FORCE_ALIGN 0 12936 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0N_FORCE_BITS 1 12937 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0N_FORCE_SHIFT 16 12938 12939 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ0N :: reserved1 [15:13] */ 12940 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0N_RESERVED1_MASK 0x0000e000 12941 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0N_RESERVED1_ALIGN 0 12942 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0N_RESERVED1_BITS 3 12943 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0N_RESERVED1_SHIFT 13 12944 12945 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ0N :: ADJ_EN [12:12] */ 12946 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0N_ADJ_EN_MASK 0x00001000 12947 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0N_ADJ_EN_ALIGN 0 12948 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0N_ADJ_EN_BITS 1 12949 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0N_ADJ_EN_SHIFT 12 12950 12951 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ0N :: reserved2 [11:08] */ 12952 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0N_RESERVED2_MASK 0x00000f00 12953 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0N_RESERVED2_ALIGN 0 12954 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0N_RESERVED2_BITS 4 12955 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0N_RESERVED2_SHIFT 8 12956 12957 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ0N :: VDL_STEP [07:00] */ 12958 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0N_VDL_STEP_MASK 0x000000ff 12959 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0N_VDL_STEP_ALIGN 0 12960 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0N_VDL_STEP_BITS 8 12961 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0N_VDL_STEP_SHIFT 0 12962 12963 12964 /**************************************************************************** 12965 * DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ1P 12966 */ 12967 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ1P :: BUSY [31:31] */ 12968 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1P_BUSY_MASK 0x80000000 12969 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1P_BUSY_ALIGN 0 12970 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1P_BUSY_BITS 1 12971 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1P_BUSY_SHIFT 31 12972 12973 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ1P :: reserved0 [30:17] */ 12974 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1P_RESERVED0_MASK 0x7ffe0000 12975 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1P_RESERVED0_ALIGN 0 12976 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1P_RESERVED0_BITS 14 12977 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1P_RESERVED0_SHIFT 17 12978 12979 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ1P :: FORCE [16:16] */ 12980 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1P_FORCE_MASK 0x00010000 12981 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1P_FORCE_ALIGN 0 12982 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1P_FORCE_BITS 1 12983 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1P_FORCE_SHIFT 16 12984 12985 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ1P :: reserved1 [15:13] */ 12986 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1P_RESERVED1_MASK 0x0000e000 12987 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1P_RESERVED1_ALIGN 0 12988 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1P_RESERVED1_BITS 3 12989 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1P_RESERVED1_SHIFT 13 12990 12991 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ1P :: ADJ_EN [12:12] */ 12992 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1P_ADJ_EN_MASK 0x00001000 12993 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1P_ADJ_EN_ALIGN 0 12994 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1P_ADJ_EN_BITS 1 12995 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1P_ADJ_EN_SHIFT 12 12996 12997 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ1P :: reserved2 [11:08] */ 12998 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1P_RESERVED2_MASK 0x00000f00 12999 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1P_RESERVED2_ALIGN 0 13000 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1P_RESERVED2_BITS 4 13001 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1P_RESERVED2_SHIFT 8 13002 13003 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ1P :: VDL_STEP [07:00] */ 13004 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1P_VDL_STEP_MASK 0x000000ff 13005 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1P_VDL_STEP_ALIGN 0 13006 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1P_VDL_STEP_BITS 8 13007 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1P_VDL_STEP_SHIFT 0 13008 13009 13010 /**************************************************************************** 13011 * DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ1N 13012 */ 13013 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ1N :: BUSY [31:31] */ 13014 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1N_BUSY_MASK 0x80000000 13015 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1N_BUSY_ALIGN 0 13016 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1N_BUSY_BITS 1 13017 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1N_BUSY_SHIFT 31 13018 13019 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ1N :: reserved0 [30:17] */ 13020 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1N_RESERVED0_MASK 0x7ffe0000 13021 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1N_RESERVED0_ALIGN 0 13022 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1N_RESERVED0_BITS 14 13023 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1N_RESERVED0_SHIFT 17 13024 13025 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ1N :: FORCE [16:16] */ 13026 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1N_FORCE_MASK 0x00010000 13027 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1N_FORCE_ALIGN 0 13028 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1N_FORCE_BITS 1 13029 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1N_FORCE_SHIFT 16 13030 13031 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ1N :: reserved1 [15:13] */ 13032 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1N_RESERVED1_MASK 0x0000e000 13033 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1N_RESERVED1_ALIGN 0 13034 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1N_RESERVED1_BITS 3 13035 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1N_RESERVED1_SHIFT 13 13036 13037 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ1N :: ADJ_EN [12:12] */ 13038 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1N_ADJ_EN_MASK 0x00001000 13039 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1N_ADJ_EN_ALIGN 0 13040 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1N_ADJ_EN_BITS 1 13041 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1N_ADJ_EN_SHIFT 12 13042 13043 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ1N :: reserved2 [11:08] */ 13044 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1N_RESERVED2_MASK 0x00000f00 13045 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1N_RESERVED2_ALIGN 0 13046 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1N_RESERVED2_BITS 4 13047 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1N_RESERVED2_SHIFT 8 13048 13049 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ1N :: VDL_STEP [07:00] */ 13050 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1N_VDL_STEP_MASK 0x000000ff 13051 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1N_VDL_STEP_ALIGN 0 13052 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1N_VDL_STEP_BITS 8 13053 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1N_VDL_STEP_SHIFT 0 13054 13055 13056 /**************************************************************************** 13057 * DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ2P 13058 */ 13059 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ2P :: BUSY [31:31] */ 13060 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2P_BUSY_MASK 0x80000000 13061 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2P_BUSY_ALIGN 0 13062 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2P_BUSY_BITS 1 13063 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2P_BUSY_SHIFT 31 13064 13065 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ2P :: reserved0 [30:17] */ 13066 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2P_RESERVED0_MASK 0x7ffe0000 13067 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2P_RESERVED0_ALIGN 0 13068 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2P_RESERVED0_BITS 14 13069 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2P_RESERVED0_SHIFT 17 13070 13071 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ2P :: FORCE [16:16] */ 13072 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2P_FORCE_MASK 0x00010000 13073 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2P_FORCE_ALIGN 0 13074 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2P_FORCE_BITS 1 13075 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2P_FORCE_SHIFT 16 13076 13077 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ2P :: reserved1 [15:13] */ 13078 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2P_RESERVED1_MASK 0x0000e000 13079 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2P_RESERVED1_ALIGN 0 13080 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2P_RESERVED1_BITS 3 13081 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2P_RESERVED1_SHIFT 13 13082 13083 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ2P :: ADJ_EN [12:12] */ 13084 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2P_ADJ_EN_MASK 0x00001000 13085 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2P_ADJ_EN_ALIGN 0 13086 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2P_ADJ_EN_BITS 1 13087 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2P_ADJ_EN_SHIFT 12 13088 13089 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ2P :: reserved2 [11:08] */ 13090 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2P_RESERVED2_MASK 0x00000f00 13091 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2P_RESERVED2_ALIGN 0 13092 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2P_RESERVED2_BITS 4 13093 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2P_RESERVED2_SHIFT 8 13094 13095 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ2P :: VDL_STEP [07:00] */ 13096 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2P_VDL_STEP_MASK 0x000000ff 13097 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2P_VDL_STEP_ALIGN 0 13098 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2P_VDL_STEP_BITS 8 13099 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2P_VDL_STEP_SHIFT 0 13100 13101 13102 /**************************************************************************** 13103 * DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ2N 13104 */ 13105 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ2N :: BUSY [31:31] */ 13106 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2N_BUSY_MASK 0x80000000 13107 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2N_BUSY_ALIGN 0 13108 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2N_BUSY_BITS 1 13109 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2N_BUSY_SHIFT 31 13110 13111 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ2N :: reserved0 [30:17] */ 13112 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2N_RESERVED0_MASK 0x7ffe0000 13113 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2N_RESERVED0_ALIGN 0 13114 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2N_RESERVED0_BITS 14 13115 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2N_RESERVED0_SHIFT 17 13116 13117 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ2N :: FORCE [16:16] */ 13118 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2N_FORCE_MASK 0x00010000 13119 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2N_FORCE_ALIGN 0 13120 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2N_FORCE_BITS 1 13121 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2N_FORCE_SHIFT 16 13122 13123 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ2N :: reserved1 [15:13] */ 13124 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2N_RESERVED1_MASK 0x0000e000 13125 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2N_RESERVED1_ALIGN 0 13126 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2N_RESERVED1_BITS 3 13127 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2N_RESERVED1_SHIFT 13 13128 13129 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ2N :: ADJ_EN [12:12] */ 13130 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2N_ADJ_EN_MASK 0x00001000 13131 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2N_ADJ_EN_ALIGN 0 13132 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2N_ADJ_EN_BITS 1 13133 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2N_ADJ_EN_SHIFT 12 13134 13135 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ2N :: reserved2 [11:08] */ 13136 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2N_RESERVED2_MASK 0x00000f00 13137 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2N_RESERVED2_ALIGN 0 13138 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2N_RESERVED2_BITS 4 13139 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2N_RESERVED2_SHIFT 8 13140 13141 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ2N :: VDL_STEP [07:00] */ 13142 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2N_VDL_STEP_MASK 0x000000ff 13143 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2N_VDL_STEP_ALIGN 0 13144 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2N_VDL_STEP_BITS 8 13145 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2N_VDL_STEP_SHIFT 0 13146 13147 13148 /**************************************************************************** 13149 * DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ3P 13150 */ 13151 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ3P :: BUSY [31:31] */ 13152 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3P_BUSY_MASK 0x80000000 13153 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3P_BUSY_ALIGN 0 13154 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3P_BUSY_BITS 1 13155 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3P_BUSY_SHIFT 31 13156 13157 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ3P :: reserved0 [30:17] */ 13158 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3P_RESERVED0_MASK 0x7ffe0000 13159 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3P_RESERVED0_ALIGN 0 13160 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3P_RESERVED0_BITS 14 13161 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3P_RESERVED0_SHIFT 17 13162 13163 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ3P :: FORCE [16:16] */ 13164 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3P_FORCE_MASK 0x00010000 13165 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3P_FORCE_ALIGN 0 13166 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3P_FORCE_BITS 1 13167 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3P_FORCE_SHIFT 16 13168 13169 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ3P :: reserved1 [15:13] */ 13170 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3P_RESERVED1_MASK 0x0000e000 13171 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3P_RESERVED1_ALIGN 0 13172 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3P_RESERVED1_BITS 3 13173 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3P_RESERVED1_SHIFT 13 13174 13175 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ3P :: ADJ_EN [12:12] */ 13176 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3P_ADJ_EN_MASK 0x00001000 13177 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3P_ADJ_EN_ALIGN 0 13178 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3P_ADJ_EN_BITS 1 13179 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3P_ADJ_EN_SHIFT 12 13180 13181 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ3P :: reserved2 [11:08] */ 13182 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3P_RESERVED2_MASK 0x00000f00 13183 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3P_RESERVED2_ALIGN 0 13184 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3P_RESERVED2_BITS 4 13185 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3P_RESERVED2_SHIFT 8 13186 13187 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ3P :: VDL_STEP [07:00] */ 13188 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3P_VDL_STEP_MASK 0x000000ff 13189 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3P_VDL_STEP_ALIGN 0 13190 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3P_VDL_STEP_BITS 8 13191 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3P_VDL_STEP_SHIFT 0 13192 13193 13194 /**************************************************************************** 13195 * DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ3N 13196 */ 13197 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ3N :: BUSY [31:31] */ 13198 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3N_BUSY_MASK 0x80000000 13199 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3N_BUSY_ALIGN 0 13200 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3N_BUSY_BITS 1 13201 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3N_BUSY_SHIFT 31 13202 13203 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ3N :: reserved0 [30:17] */ 13204 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3N_RESERVED0_MASK 0x7ffe0000 13205 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3N_RESERVED0_ALIGN 0 13206 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3N_RESERVED0_BITS 14 13207 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3N_RESERVED0_SHIFT 17 13208 13209 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ3N :: FORCE [16:16] */ 13210 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3N_FORCE_MASK 0x00010000 13211 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3N_FORCE_ALIGN 0 13212 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3N_FORCE_BITS 1 13213 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3N_FORCE_SHIFT 16 13214 13215 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ3N :: reserved1 [15:13] */ 13216 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3N_RESERVED1_MASK 0x0000e000 13217 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3N_RESERVED1_ALIGN 0 13218 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3N_RESERVED1_BITS 3 13219 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3N_RESERVED1_SHIFT 13 13220 13221 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ3N :: ADJ_EN [12:12] */ 13222 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3N_ADJ_EN_MASK 0x00001000 13223 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3N_ADJ_EN_ALIGN 0 13224 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3N_ADJ_EN_BITS 1 13225 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3N_ADJ_EN_SHIFT 12 13226 13227 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ3N :: reserved2 [11:08] */ 13228 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3N_RESERVED2_MASK 0x00000f00 13229 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3N_RESERVED2_ALIGN 0 13230 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3N_RESERVED2_BITS 4 13231 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3N_RESERVED2_SHIFT 8 13232 13233 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ3N :: VDL_STEP [07:00] */ 13234 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3N_VDL_STEP_MASK 0x000000ff 13235 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3N_VDL_STEP_ALIGN 0 13236 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3N_VDL_STEP_BITS 8 13237 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3N_VDL_STEP_SHIFT 0 13238 13239 13240 /**************************************************************************** 13241 * DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ4P 13242 */ 13243 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ4P :: BUSY [31:31] */ 13244 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4P_BUSY_MASK 0x80000000 13245 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4P_BUSY_ALIGN 0 13246 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4P_BUSY_BITS 1 13247 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4P_BUSY_SHIFT 31 13248 13249 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ4P :: reserved0 [30:17] */ 13250 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4P_RESERVED0_MASK 0x7ffe0000 13251 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4P_RESERVED0_ALIGN 0 13252 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4P_RESERVED0_BITS 14 13253 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4P_RESERVED0_SHIFT 17 13254 13255 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ4P :: FORCE [16:16] */ 13256 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4P_FORCE_MASK 0x00010000 13257 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4P_FORCE_ALIGN 0 13258 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4P_FORCE_BITS 1 13259 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4P_FORCE_SHIFT 16 13260 13261 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ4P :: reserved1 [15:13] */ 13262 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4P_RESERVED1_MASK 0x0000e000 13263 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4P_RESERVED1_ALIGN 0 13264 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4P_RESERVED1_BITS 3 13265 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4P_RESERVED1_SHIFT 13 13266 13267 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ4P :: ADJ_EN [12:12] */ 13268 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4P_ADJ_EN_MASK 0x00001000 13269 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4P_ADJ_EN_ALIGN 0 13270 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4P_ADJ_EN_BITS 1 13271 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4P_ADJ_EN_SHIFT 12 13272 13273 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ4P :: reserved2 [11:08] */ 13274 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4P_RESERVED2_MASK 0x00000f00 13275 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4P_RESERVED2_ALIGN 0 13276 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4P_RESERVED2_BITS 4 13277 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4P_RESERVED2_SHIFT 8 13278 13279 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ4P :: VDL_STEP [07:00] */ 13280 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4P_VDL_STEP_MASK 0x000000ff 13281 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4P_VDL_STEP_ALIGN 0 13282 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4P_VDL_STEP_BITS 8 13283 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4P_VDL_STEP_SHIFT 0 13284 13285 13286 /**************************************************************************** 13287 * DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ4N 13288 */ 13289 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ4N :: BUSY [31:31] */ 13290 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4N_BUSY_MASK 0x80000000 13291 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4N_BUSY_ALIGN 0 13292 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4N_BUSY_BITS 1 13293 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4N_BUSY_SHIFT 31 13294 13295 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ4N :: reserved0 [30:17] */ 13296 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4N_RESERVED0_MASK 0x7ffe0000 13297 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4N_RESERVED0_ALIGN 0 13298 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4N_RESERVED0_BITS 14 13299 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4N_RESERVED0_SHIFT 17 13300 13301 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ4N :: FORCE [16:16] */ 13302 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4N_FORCE_MASK 0x00010000 13303 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4N_FORCE_ALIGN 0 13304 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4N_FORCE_BITS 1 13305 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4N_FORCE_SHIFT 16 13306 13307 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ4N :: reserved1 [15:13] */ 13308 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4N_RESERVED1_MASK 0x0000e000 13309 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4N_RESERVED1_ALIGN 0 13310 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4N_RESERVED1_BITS 3 13311 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4N_RESERVED1_SHIFT 13 13312 13313 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ4N :: ADJ_EN [12:12] */ 13314 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4N_ADJ_EN_MASK 0x00001000 13315 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4N_ADJ_EN_ALIGN 0 13316 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4N_ADJ_EN_BITS 1 13317 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4N_ADJ_EN_SHIFT 12 13318 13319 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ4N :: reserved2 [11:08] */ 13320 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4N_RESERVED2_MASK 0x00000f00 13321 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4N_RESERVED2_ALIGN 0 13322 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4N_RESERVED2_BITS 4 13323 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4N_RESERVED2_SHIFT 8 13324 13325 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ4N :: VDL_STEP [07:00] */ 13326 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4N_VDL_STEP_MASK 0x000000ff 13327 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4N_VDL_STEP_ALIGN 0 13328 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4N_VDL_STEP_BITS 8 13329 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4N_VDL_STEP_SHIFT 0 13330 13331 13332 /**************************************************************************** 13333 * DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ5P 13334 */ 13335 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ5P :: BUSY [31:31] */ 13336 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5P_BUSY_MASK 0x80000000 13337 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5P_BUSY_ALIGN 0 13338 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5P_BUSY_BITS 1 13339 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5P_BUSY_SHIFT 31 13340 13341 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ5P :: reserved0 [30:17] */ 13342 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5P_RESERVED0_MASK 0x7ffe0000 13343 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5P_RESERVED0_ALIGN 0 13344 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5P_RESERVED0_BITS 14 13345 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5P_RESERVED0_SHIFT 17 13346 13347 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ5P :: FORCE [16:16] */ 13348 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5P_FORCE_MASK 0x00010000 13349 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5P_FORCE_ALIGN 0 13350 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5P_FORCE_BITS 1 13351 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5P_FORCE_SHIFT 16 13352 13353 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ5P :: reserved1 [15:13] */ 13354 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5P_RESERVED1_MASK 0x0000e000 13355 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5P_RESERVED1_ALIGN 0 13356 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5P_RESERVED1_BITS 3 13357 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5P_RESERVED1_SHIFT 13 13358 13359 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ5P :: ADJ_EN [12:12] */ 13360 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5P_ADJ_EN_MASK 0x00001000 13361 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5P_ADJ_EN_ALIGN 0 13362 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5P_ADJ_EN_BITS 1 13363 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5P_ADJ_EN_SHIFT 12 13364 13365 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ5P :: reserved2 [11:08] */ 13366 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5P_RESERVED2_MASK 0x00000f00 13367 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5P_RESERVED2_ALIGN 0 13368 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5P_RESERVED2_BITS 4 13369 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5P_RESERVED2_SHIFT 8 13370 13371 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ5P :: VDL_STEP [07:00] */ 13372 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5P_VDL_STEP_MASK 0x000000ff 13373 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5P_VDL_STEP_ALIGN 0 13374 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5P_VDL_STEP_BITS 8 13375 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5P_VDL_STEP_SHIFT 0 13376 13377 13378 /**************************************************************************** 13379 * DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ5N 13380 */ 13381 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ5N :: BUSY [31:31] */ 13382 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5N_BUSY_MASK 0x80000000 13383 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5N_BUSY_ALIGN 0 13384 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5N_BUSY_BITS 1 13385 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5N_BUSY_SHIFT 31 13386 13387 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ5N :: reserved0 [30:17] */ 13388 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5N_RESERVED0_MASK 0x7ffe0000 13389 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5N_RESERVED0_ALIGN 0 13390 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5N_RESERVED0_BITS 14 13391 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5N_RESERVED0_SHIFT 17 13392 13393 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ5N :: FORCE [16:16] */ 13394 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5N_FORCE_MASK 0x00010000 13395 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5N_FORCE_ALIGN 0 13396 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5N_FORCE_BITS 1 13397 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5N_FORCE_SHIFT 16 13398 13399 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ5N :: reserved1 [15:13] */ 13400 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5N_RESERVED1_MASK 0x0000e000 13401 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5N_RESERVED1_ALIGN 0 13402 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5N_RESERVED1_BITS 3 13403 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5N_RESERVED1_SHIFT 13 13404 13405 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ5N :: ADJ_EN [12:12] */ 13406 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5N_ADJ_EN_MASK 0x00001000 13407 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5N_ADJ_EN_ALIGN 0 13408 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5N_ADJ_EN_BITS 1 13409 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5N_ADJ_EN_SHIFT 12 13410 13411 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ5N :: reserved2 [11:08] */ 13412 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5N_RESERVED2_MASK 0x00000f00 13413 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5N_RESERVED2_ALIGN 0 13414 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5N_RESERVED2_BITS 4 13415 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5N_RESERVED2_SHIFT 8 13416 13417 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ5N :: VDL_STEP [07:00] */ 13418 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5N_VDL_STEP_MASK 0x000000ff 13419 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5N_VDL_STEP_ALIGN 0 13420 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5N_VDL_STEP_BITS 8 13421 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5N_VDL_STEP_SHIFT 0 13422 13423 13424 /**************************************************************************** 13425 * DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ6P 13426 */ 13427 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ6P :: BUSY [31:31] */ 13428 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6P_BUSY_MASK 0x80000000 13429 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6P_BUSY_ALIGN 0 13430 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6P_BUSY_BITS 1 13431 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6P_BUSY_SHIFT 31 13432 13433 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ6P :: reserved0 [30:17] */ 13434 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6P_RESERVED0_MASK 0x7ffe0000 13435 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6P_RESERVED0_ALIGN 0 13436 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6P_RESERVED0_BITS 14 13437 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6P_RESERVED0_SHIFT 17 13438 13439 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ6P :: FORCE [16:16] */ 13440 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6P_FORCE_MASK 0x00010000 13441 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6P_FORCE_ALIGN 0 13442 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6P_FORCE_BITS 1 13443 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6P_FORCE_SHIFT 16 13444 13445 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ6P :: reserved1 [15:13] */ 13446 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6P_RESERVED1_MASK 0x0000e000 13447 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6P_RESERVED1_ALIGN 0 13448 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6P_RESERVED1_BITS 3 13449 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6P_RESERVED1_SHIFT 13 13450 13451 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ6P :: ADJ_EN [12:12] */ 13452 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6P_ADJ_EN_MASK 0x00001000 13453 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6P_ADJ_EN_ALIGN 0 13454 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6P_ADJ_EN_BITS 1 13455 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6P_ADJ_EN_SHIFT 12 13456 13457 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ6P :: reserved2 [11:08] */ 13458 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6P_RESERVED2_MASK 0x00000f00 13459 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6P_RESERVED2_ALIGN 0 13460 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6P_RESERVED2_BITS 4 13461 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6P_RESERVED2_SHIFT 8 13462 13463 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ6P :: VDL_STEP [07:00] */ 13464 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6P_VDL_STEP_MASK 0x000000ff 13465 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6P_VDL_STEP_ALIGN 0 13466 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6P_VDL_STEP_BITS 8 13467 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6P_VDL_STEP_SHIFT 0 13468 13469 13470 /**************************************************************************** 13471 * DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ6N 13472 */ 13473 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ6N :: BUSY [31:31] */ 13474 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6N_BUSY_MASK 0x80000000 13475 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6N_BUSY_ALIGN 0 13476 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6N_BUSY_BITS 1 13477 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6N_BUSY_SHIFT 31 13478 13479 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ6N :: reserved0 [30:17] */ 13480 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6N_RESERVED0_MASK 0x7ffe0000 13481 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6N_RESERVED0_ALIGN 0 13482 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6N_RESERVED0_BITS 14 13483 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6N_RESERVED0_SHIFT 17 13484 13485 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ6N :: FORCE [16:16] */ 13486 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6N_FORCE_MASK 0x00010000 13487 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6N_FORCE_ALIGN 0 13488 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6N_FORCE_BITS 1 13489 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6N_FORCE_SHIFT 16 13490 13491 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ6N :: reserved1 [15:13] */ 13492 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6N_RESERVED1_MASK 0x0000e000 13493 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6N_RESERVED1_ALIGN 0 13494 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6N_RESERVED1_BITS 3 13495 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6N_RESERVED1_SHIFT 13 13496 13497 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ6N :: ADJ_EN [12:12] */ 13498 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6N_ADJ_EN_MASK 0x00001000 13499 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6N_ADJ_EN_ALIGN 0 13500 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6N_ADJ_EN_BITS 1 13501 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6N_ADJ_EN_SHIFT 12 13502 13503 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ6N :: reserved2 [11:08] */ 13504 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6N_RESERVED2_MASK 0x00000f00 13505 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6N_RESERVED2_ALIGN 0 13506 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6N_RESERVED2_BITS 4 13507 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6N_RESERVED2_SHIFT 8 13508 13509 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ6N :: VDL_STEP [07:00] */ 13510 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6N_VDL_STEP_MASK 0x000000ff 13511 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6N_VDL_STEP_ALIGN 0 13512 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6N_VDL_STEP_BITS 8 13513 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6N_VDL_STEP_SHIFT 0 13514 13515 13516 /**************************************************************************** 13517 * DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ7P 13518 */ 13519 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ7P :: BUSY [31:31] */ 13520 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7P_BUSY_MASK 0x80000000 13521 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7P_BUSY_ALIGN 0 13522 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7P_BUSY_BITS 1 13523 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7P_BUSY_SHIFT 31 13524 13525 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ7P :: reserved0 [30:17] */ 13526 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7P_RESERVED0_MASK 0x7ffe0000 13527 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7P_RESERVED0_ALIGN 0 13528 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7P_RESERVED0_BITS 14 13529 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7P_RESERVED0_SHIFT 17 13530 13531 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ7P :: FORCE [16:16] */ 13532 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7P_FORCE_MASK 0x00010000 13533 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7P_FORCE_ALIGN 0 13534 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7P_FORCE_BITS 1 13535 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7P_FORCE_SHIFT 16 13536 13537 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ7P :: reserved1 [15:13] */ 13538 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7P_RESERVED1_MASK 0x0000e000 13539 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7P_RESERVED1_ALIGN 0 13540 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7P_RESERVED1_BITS 3 13541 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7P_RESERVED1_SHIFT 13 13542 13543 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ7P :: ADJ_EN [12:12] */ 13544 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7P_ADJ_EN_MASK 0x00001000 13545 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7P_ADJ_EN_ALIGN 0 13546 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7P_ADJ_EN_BITS 1 13547 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7P_ADJ_EN_SHIFT 12 13548 13549 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ7P :: reserved2 [11:08] */ 13550 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7P_RESERVED2_MASK 0x00000f00 13551 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7P_RESERVED2_ALIGN 0 13552 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7P_RESERVED2_BITS 4 13553 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7P_RESERVED2_SHIFT 8 13554 13555 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ7P :: VDL_STEP [07:00] */ 13556 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7P_VDL_STEP_MASK 0x000000ff 13557 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7P_VDL_STEP_ALIGN 0 13558 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7P_VDL_STEP_BITS 8 13559 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7P_VDL_STEP_SHIFT 0 13560 13561 13562 /**************************************************************************** 13563 * DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ7N 13564 */ 13565 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ7N :: BUSY [31:31] */ 13566 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7N_BUSY_MASK 0x80000000 13567 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7N_BUSY_ALIGN 0 13568 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7N_BUSY_BITS 1 13569 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7N_BUSY_SHIFT 31 13570 13571 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ7N :: reserved0 [30:17] */ 13572 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7N_RESERVED0_MASK 0x7ffe0000 13573 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7N_RESERVED0_ALIGN 0 13574 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7N_RESERVED0_BITS 14 13575 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7N_RESERVED0_SHIFT 17 13576 13577 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ7N :: FORCE [16:16] */ 13578 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7N_FORCE_MASK 0x00010000 13579 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7N_FORCE_ALIGN 0 13580 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7N_FORCE_BITS 1 13581 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7N_FORCE_SHIFT 16 13582 13583 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ7N :: reserved1 [15:13] */ 13584 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7N_RESERVED1_MASK 0x0000e000 13585 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7N_RESERVED1_ALIGN 0 13586 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7N_RESERVED1_BITS 3 13587 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7N_RESERVED1_SHIFT 13 13588 13589 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ7N :: ADJ_EN [12:12] */ 13590 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7N_ADJ_EN_MASK 0x00001000 13591 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7N_ADJ_EN_ALIGN 0 13592 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7N_ADJ_EN_BITS 1 13593 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7N_ADJ_EN_SHIFT 12 13594 13595 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ7N :: reserved2 [11:08] */ 13596 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7N_RESERVED2_MASK 0x00000f00 13597 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7N_RESERVED2_ALIGN 0 13598 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7N_RESERVED2_BITS 4 13599 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7N_RESERVED2_SHIFT 8 13600 13601 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ7N :: VDL_STEP [07:00] */ 13602 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7N_VDL_STEP_MASK 0x000000ff 13603 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7N_VDL_STEP_ALIGN 0 13604 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7N_VDL_STEP_BITS 8 13605 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7N_VDL_STEP_SHIFT 0 13606 13607 13608 /**************************************************************************** 13609 * DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DMP 13610 */ 13611 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DMP :: BUSY [31:31] */ 13612 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMP_BUSY_MASK 0x80000000 13613 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMP_BUSY_ALIGN 0 13614 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMP_BUSY_BITS 1 13615 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMP_BUSY_SHIFT 31 13616 13617 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DMP :: reserved0 [30:17] */ 13618 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMP_RESERVED0_MASK 0x7ffe0000 13619 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMP_RESERVED0_ALIGN 0 13620 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMP_RESERVED0_BITS 14 13621 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMP_RESERVED0_SHIFT 17 13622 13623 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DMP :: FORCE [16:16] */ 13624 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMP_FORCE_MASK 0x00010000 13625 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMP_FORCE_ALIGN 0 13626 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMP_FORCE_BITS 1 13627 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMP_FORCE_SHIFT 16 13628 13629 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DMP :: reserved1 [15:13] */ 13630 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMP_RESERVED1_MASK 0x0000e000 13631 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMP_RESERVED1_ALIGN 0 13632 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMP_RESERVED1_BITS 3 13633 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMP_RESERVED1_SHIFT 13 13634 13635 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DMP :: ADJ_EN [12:12] */ 13636 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMP_ADJ_EN_MASK 0x00001000 13637 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMP_ADJ_EN_ALIGN 0 13638 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMP_ADJ_EN_BITS 1 13639 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMP_ADJ_EN_SHIFT 12 13640 13641 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DMP :: reserved2 [11:08] */ 13642 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMP_RESERVED2_MASK 0x00000f00 13643 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMP_RESERVED2_ALIGN 0 13644 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMP_RESERVED2_BITS 4 13645 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMP_RESERVED2_SHIFT 8 13646 13647 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DMP :: VDL_STEP [07:00] */ 13648 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMP_VDL_STEP_MASK 0x000000ff 13649 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMP_VDL_STEP_ALIGN 0 13650 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMP_VDL_STEP_BITS 8 13651 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMP_VDL_STEP_SHIFT 0 13652 13653 13654 /**************************************************************************** 13655 * DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DMN 13656 */ 13657 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DMN :: BUSY [31:31] */ 13658 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMN_BUSY_MASK 0x80000000 13659 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMN_BUSY_ALIGN 0 13660 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMN_BUSY_BITS 1 13661 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMN_BUSY_SHIFT 31 13662 13663 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DMN :: reserved0 [30:17] */ 13664 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMN_RESERVED0_MASK 0x7ffe0000 13665 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMN_RESERVED0_ALIGN 0 13666 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMN_RESERVED0_BITS 14 13667 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMN_RESERVED0_SHIFT 17 13668 13669 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DMN :: FORCE [16:16] */ 13670 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMN_FORCE_MASK 0x00010000 13671 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMN_FORCE_ALIGN 0 13672 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMN_FORCE_BITS 1 13673 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMN_FORCE_SHIFT 16 13674 13675 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DMN :: reserved1 [15:13] */ 13676 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMN_RESERVED1_MASK 0x0000e000 13677 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMN_RESERVED1_ALIGN 0 13678 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMN_RESERVED1_BITS 3 13679 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMN_RESERVED1_SHIFT 13 13680 13681 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DMN :: ADJ_EN [12:12] */ 13682 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMN_ADJ_EN_MASK 0x00001000 13683 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMN_ADJ_EN_ALIGN 0 13684 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMN_ADJ_EN_BITS 1 13685 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMN_ADJ_EN_SHIFT 12 13686 13687 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DMN :: reserved2 [11:08] */ 13688 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMN_RESERVED2_MASK 0x00000f00 13689 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMN_RESERVED2_ALIGN 0 13690 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMN_RESERVED2_BITS 4 13691 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMN_RESERVED2_SHIFT 8 13692 13693 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DMN :: VDL_STEP [07:00] */ 13694 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMN_VDL_STEP_MASK 0x000000ff 13695 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMN_VDL_STEP_ALIGN 0 13696 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMN_VDL_STEP_BITS 8 13697 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMN_VDL_STEP_SHIFT 0 13698 13699 13700 /**************************************************************************** 13701 * DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_EN_CS0 13702 */ 13703 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_EN_CS0 :: BUSY [31:31] */ 13704 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS0_BUSY_MASK 0x80000000 13705 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS0_BUSY_ALIGN 0 13706 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS0_BUSY_BITS 1 13707 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS0_BUSY_SHIFT 31 13708 13709 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_EN_CS0 :: reserved0 [30:17] */ 13710 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS0_RESERVED0_MASK 0x7ffe0000 13711 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS0_RESERVED0_ALIGN 0 13712 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS0_RESERVED0_BITS 14 13713 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS0_RESERVED0_SHIFT 17 13714 13715 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_EN_CS0 :: FORCE [16:16] */ 13716 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS0_FORCE_MASK 0x00010000 13717 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS0_FORCE_ALIGN 0 13718 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS0_FORCE_BITS 1 13719 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS0_FORCE_SHIFT 16 13720 13721 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_EN_CS0 :: reserved1 [15:13] */ 13722 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS0_RESERVED1_MASK 0x0000e000 13723 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS0_RESERVED1_ALIGN 0 13724 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS0_RESERVED1_BITS 3 13725 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS0_RESERVED1_SHIFT 13 13726 13727 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_EN_CS0 :: ADJ_EN [12:12] */ 13728 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS0_ADJ_EN_MASK 0x00001000 13729 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS0_ADJ_EN_ALIGN 0 13730 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS0_ADJ_EN_BITS 1 13731 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS0_ADJ_EN_SHIFT 12 13732 13733 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_EN_CS0 :: reserved2 [11:08] */ 13734 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS0_RESERVED2_MASK 0x00000f00 13735 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS0_RESERVED2_ALIGN 0 13736 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS0_RESERVED2_BITS 4 13737 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS0_RESERVED2_SHIFT 8 13738 13739 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_EN_CS0 :: VDL_STEP [07:00] */ 13740 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS0_VDL_STEP_MASK 0x000000ff 13741 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS0_VDL_STEP_ALIGN 0 13742 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS0_VDL_STEP_BITS 8 13743 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS0_VDL_STEP_SHIFT 0 13744 13745 13746 /**************************************************************************** 13747 * DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_EN_CS1 13748 */ 13749 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_EN_CS1 :: BUSY [31:31] */ 13750 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS1_BUSY_MASK 0x80000000 13751 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS1_BUSY_ALIGN 0 13752 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS1_BUSY_BITS 1 13753 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS1_BUSY_SHIFT 31 13754 13755 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_EN_CS1 :: reserved0 [30:17] */ 13756 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS1_RESERVED0_MASK 0x7ffe0000 13757 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS1_RESERVED0_ALIGN 0 13758 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS1_RESERVED0_BITS 14 13759 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS1_RESERVED0_SHIFT 17 13760 13761 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_EN_CS1 :: FORCE [16:16] */ 13762 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS1_FORCE_MASK 0x00010000 13763 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS1_FORCE_ALIGN 0 13764 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS1_FORCE_BITS 1 13765 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS1_FORCE_SHIFT 16 13766 13767 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_EN_CS1 :: reserved1 [15:13] */ 13768 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS1_RESERVED1_MASK 0x0000e000 13769 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS1_RESERVED1_ALIGN 0 13770 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS1_RESERVED1_BITS 3 13771 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS1_RESERVED1_SHIFT 13 13772 13773 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_EN_CS1 :: ADJ_EN [12:12] */ 13774 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS1_ADJ_EN_MASK 0x00001000 13775 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS1_ADJ_EN_ALIGN 0 13776 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS1_ADJ_EN_BITS 1 13777 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS1_ADJ_EN_SHIFT 12 13778 13779 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_EN_CS1 :: reserved2 [11:08] */ 13780 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS1_RESERVED2_MASK 0x00000f00 13781 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS1_RESERVED2_ALIGN 0 13782 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS1_RESERVED2_BITS 4 13783 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS1_RESERVED2_SHIFT 8 13784 13785 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_EN_CS1 :: VDL_STEP [07:00] */ 13786 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS1_VDL_STEP_MASK 0x000000ff 13787 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS1_VDL_STEP_ALIGN 0 13788 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS1_VDL_STEP_BITS 8 13789 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS1_VDL_STEP_SHIFT 0 13790 13791 13792 /**************************************************************************** 13793 * DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CLK_CONTROL 13794 */ 13795 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CLK_CONTROL :: BUSY [31:31] */ 13796 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CLK_CONTROL_BUSY_MASK 0x80000000 13797 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CLK_CONTROL_BUSY_ALIGN 0 13798 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CLK_CONTROL_BUSY_BITS 1 13799 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CLK_CONTROL_BUSY_SHIFT 31 13800 13801 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CLK_CONTROL :: reserved0 [30:17] */ 13802 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CLK_CONTROL_RESERVED0_MASK 0x7ffe0000 13803 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CLK_CONTROL_RESERVED0_ALIGN 0 13804 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CLK_CONTROL_RESERVED0_BITS 14 13805 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CLK_CONTROL_RESERVED0_SHIFT 17 13806 13807 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CLK_CONTROL :: FORCE [16:16] */ 13808 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CLK_CONTROL_FORCE_MASK 0x00010000 13809 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CLK_CONTROL_FORCE_ALIGN 0 13810 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CLK_CONTROL_FORCE_BITS 1 13811 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CLK_CONTROL_FORCE_SHIFT 16 13812 13813 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CLK_CONTROL :: reserved1 [15:13] */ 13814 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CLK_CONTROL_RESERVED1_MASK 0x0000e000 13815 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CLK_CONTROL_RESERVED1_ALIGN 0 13816 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CLK_CONTROL_RESERVED1_BITS 3 13817 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CLK_CONTROL_RESERVED1_SHIFT 13 13818 13819 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CLK_CONTROL :: ADJ_EN [12:12] */ 13820 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CLK_CONTROL_ADJ_EN_MASK 0x00001000 13821 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CLK_CONTROL_ADJ_EN_ALIGN 0 13822 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CLK_CONTROL_ADJ_EN_BITS 1 13823 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CLK_CONTROL_ADJ_EN_SHIFT 12 13824 13825 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CLK_CONTROL :: reserved2 [11:09] */ 13826 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CLK_CONTROL_RESERVED2_MASK 0x00000e00 13827 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CLK_CONTROL_RESERVED2_ALIGN 0 13828 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CLK_CONTROL_RESERVED2_BITS 3 13829 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CLK_CONTROL_RESERVED2_SHIFT 9 13830 13831 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_CLK_CONTROL :: VDL_STEP [08:00] */ 13832 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CLK_CONTROL_VDL_STEP_MASK 0x000001ff 13833 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CLK_CONTROL_VDL_STEP_ALIGN 0 13834 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CLK_CONTROL_VDL_STEP_BITS 9 13835 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_CLK_CONTROL_VDL_STEP_SHIFT 0 13836 13837 13838 /**************************************************************************** 13839 * DDR34_F0_PHY_BYTE_LANE_3 :: VDL_LDE_CONTROL 13840 */ 13841 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_LDE_CONTROL :: BUSY [31:31] */ 13842 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_LDE_CONTROL_BUSY_MASK 0x80000000 13843 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_LDE_CONTROL_BUSY_ALIGN 0 13844 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_LDE_CONTROL_BUSY_BITS 1 13845 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_LDE_CONTROL_BUSY_SHIFT 31 13846 13847 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_LDE_CONTROL :: reserved0 [30:17] */ 13848 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_LDE_CONTROL_RESERVED0_MASK 0x7ffe0000 13849 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_LDE_CONTROL_RESERVED0_ALIGN 0 13850 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_LDE_CONTROL_RESERVED0_BITS 14 13851 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_LDE_CONTROL_RESERVED0_SHIFT 17 13852 13853 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_LDE_CONTROL :: FORCE [16:16] */ 13854 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_LDE_CONTROL_FORCE_MASK 0x00010000 13855 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_LDE_CONTROL_FORCE_ALIGN 0 13856 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_LDE_CONTROL_FORCE_BITS 1 13857 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_LDE_CONTROL_FORCE_SHIFT 16 13858 13859 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_LDE_CONTROL :: reserved1 [15:13] */ 13860 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_LDE_CONTROL_RESERVED1_MASK 0x0000e000 13861 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_LDE_CONTROL_RESERVED1_ALIGN 0 13862 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_LDE_CONTROL_RESERVED1_BITS 3 13863 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_LDE_CONTROL_RESERVED1_SHIFT 13 13864 13865 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_LDE_CONTROL :: ADJ_EN [12:12] */ 13866 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_LDE_CONTROL_ADJ_EN_MASK 0x00001000 13867 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_LDE_CONTROL_ADJ_EN_ALIGN 0 13868 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_LDE_CONTROL_ADJ_EN_BITS 1 13869 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_LDE_CONTROL_ADJ_EN_SHIFT 12 13870 13871 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_LDE_CONTROL :: reserved2 [11:09] */ 13872 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_LDE_CONTROL_RESERVED2_MASK 0x00000e00 13873 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_LDE_CONTROL_RESERVED2_ALIGN 0 13874 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_LDE_CONTROL_RESERVED2_BITS 3 13875 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_LDE_CONTROL_RESERVED2_SHIFT 9 13876 13877 /* DDR34_F0_PHY_BYTE_LANE_3 :: VDL_LDE_CONTROL :: VDL_STEP [08:00] */ 13878 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_LDE_CONTROL_VDL_STEP_MASK 0x000001ff 13879 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_LDE_CONTROL_VDL_STEP_ALIGN 0 13880 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_LDE_CONTROL_VDL_STEP_BITS 9 13881 #define DDR34_F0_PHY_BYTE_LANE_3_VDL_LDE_CONTROL_VDL_STEP_SHIFT 0 13882 13883 13884 /**************************************************************************** 13885 * DDR34_F0_PHY_BYTE_LANE_3 :: RD_EN_DLY_CYC 13886 */ 13887 /* DDR34_F0_PHY_BYTE_LANE_3 :: RD_EN_DLY_CYC :: BUSY [31:31] */ 13888 #define DDR34_F0_PHY_BYTE_LANE_3_RD_EN_DLY_CYC_BUSY_MASK 0x80000000 13889 #define DDR34_F0_PHY_BYTE_LANE_3_RD_EN_DLY_CYC_BUSY_ALIGN 0 13890 #define DDR34_F0_PHY_BYTE_LANE_3_RD_EN_DLY_CYC_BUSY_BITS 1 13891 #define DDR34_F0_PHY_BYTE_LANE_3_RD_EN_DLY_CYC_BUSY_SHIFT 31 13892 13893 /* DDR34_F0_PHY_BYTE_LANE_3 :: RD_EN_DLY_CYC :: reserved0 [30:17] */ 13894 #define DDR34_F0_PHY_BYTE_LANE_3_RD_EN_DLY_CYC_RESERVED0_MASK 0x7ffe0000 13895 #define DDR34_F0_PHY_BYTE_LANE_3_RD_EN_DLY_CYC_RESERVED0_ALIGN 0 13896 #define DDR34_F0_PHY_BYTE_LANE_3_RD_EN_DLY_CYC_RESERVED0_BITS 14 13897 #define DDR34_F0_PHY_BYTE_LANE_3_RD_EN_DLY_CYC_RESERVED0_SHIFT 17 13898 13899 /* DDR34_F0_PHY_BYTE_LANE_3 :: RD_EN_DLY_CYC :: FORCE [16:16] */ 13900 #define DDR34_F0_PHY_BYTE_LANE_3_RD_EN_DLY_CYC_FORCE_MASK 0x00010000 13901 #define DDR34_F0_PHY_BYTE_LANE_3_RD_EN_DLY_CYC_FORCE_ALIGN 0 13902 #define DDR34_F0_PHY_BYTE_LANE_3_RD_EN_DLY_CYC_FORCE_BITS 1 13903 #define DDR34_F0_PHY_BYTE_LANE_3_RD_EN_DLY_CYC_FORCE_SHIFT 16 13904 13905 /* DDR34_F0_PHY_BYTE_LANE_3 :: RD_EN_DLY_CYC :: reserved1 [15:09] */ 13906 #define DDR34_F0_PHY_BYTE_LANE_3_RD_EN_DLY_CYC_RESERVED1_MASK 0x0000fe00 13907 #define DDR34_F0_PHY_BYTE_LANE_3_RD_EN_DLY_CYC_RESERVED1_ALIGN 0 13908 #define DDR34_F0_PHY_BYTE_LANE_3_RD_EN_DLY_CYC_RESERVED1_BITS 7 13909 #define DDR34_F0_PHY_BYTE_LANE_3_RD_EN_DLY_CYC_RESERVED1_SHIFT 9 13910 13911 /* DDR34_F0_PHY_BYTE_LANE_3 :: RD_EN_DLY_CYC :: ENABLE_CS1 [08:08] */ 13912 #define DDR34_F0_PHY_BYTE_LANE_3_RD_EN_DLY_CYC_ENABLE_CS1_MASK 0x00000100 13913 #define DDR34_F0_PHY_BYTE_LANE_3_RD_EN_DLY_CYC_ENABLE_CS1_ALIGN 0 13914 #define DDR34_F0_PHY_BYTE_LANE_3_RD_EN_DLY_CYC_ENABLE_CS1_BITS 1 13915 #define DDR34_F0_PHY_BYTE_LANE_3_RD_EN_DLY_CYC_ENABLE_CS1_SHIFT 8 13916 13917 /* DDR34_F0_PHY_BYTE_LANE_3 :: RD_EN_DLY_CYC :: CS1_CYCLES [07:04] */ 13918 #define DDR34_F0_PHY_BYTE_LANE_3_RD_EN_DLY_CYC_CS1_CYCLES_MASK 0x000000f0 13919 #define DDR34_F0_PHY_BYTE_LANE_3_RD_EN_DLY_CYC_CS1_CYCLES_ALIGN 0 13920 #define DDR34_F0_PHY_BYTE_LANE_3_RD_EN_DLY_CYC_CS1_CYCLES_BITS 4 13921 #define DDR34_F0_PHY_BYTE_LANE_3_RD_EN_DLY_CYC_CS1_CYCLES_SHIFT 4 13922 13923 /* DDR34_F0_PHY_BYTE_LANE_3 :: RD_EN_DLY_CYC :: CS0_CYCLES [03:00] */ 13924 #define DDR34_F0_PHY_BYTE_LANE_3_RD_EN_DLY_CYC_CS0_CYCLES_MASK 0x0000000f 13925 #define DDR34_F0_PHY_BYTE_LANE_3_RD_EN_DLY_CYC_CS0_CYCLES_ALIGN 0 13926 #define DDR34_F0_PHY_BYTE_LANE_3_RD_EN_DLY_CYC_CS0_CYCLES_BITS 4 13927 #define DDR34_F0_PHY_BYTE_LANE_3_RD_EN_DLY_CYC_CS0_CYCLES_SHIFT 0 13928 13929 13930 /**************************************************************************** 13931 * DDR34_F0_PHY_BYTE_LANE_3 :: WR_CHAN_DLY_CYC 13932 */ 13933 /* DDR34_F0_PHY_BYTE_LANE_3 :: WR_CHAN_DLY_CYC :: BUSY [31:31] */ 13934 #define DDR34_F0_PHY_BYTE_LANE_3_WR_CHAN_DLY_CYC_BUSY_MASK 0x80000000 13935 #define DDR34_F0_PHY_BYTE_LANE_3_WR_CHAN_DLY_CYC_BUSY_ALIGN 0 13936 #define DDR34_F0_PHY_BYTE_LANE_3_WR_CHAN_DLY_CYC_BUSY_BITS 1 13937 #define DDR34_F0_PHY_BYTE_LANE_3_WR_CHAN_DLY_CYC_BUSY_SHIFT 31 13938 13939 /* DDR34_F0_PHY_BYTE_LANE_3 :: WR_CHAN_DLY_CYC :: reserved0 [30:17] */ 13940 #define DDR34_F0_PHY_BYTE_LANE_3_WR_CHAN_DLY_CYC_RESERVED0_MASK 0x7ffe0000 13941 #define DDR34_F0_PHY_BYTE_LANE_3_WR_CHAN_DLY_CYC_RESERVED0_ALIGN 0 13942 #define DDR34_F0_PHY_BYTE_LANE_3_WR_CHAN_DLY_CYC_RESERVED0_BITS 14 13943 #define DDR34_F0_PHY_BYTE_LANE_3_WR_CHAN_DLY_CYC_RESERVED0_SHIFT 17 13944 13945 /* DDR34_F0_PHY_BYTE_LANE_3 :: WR_CHAN_DLY_CYC :: FORCE [16:16] */ 13946 #define DDR34_F0_PHY_BYTE_LANE_3_WR_CHAN_DLY_CYC_FORCE_MASK 0x00010000 13947 #define DDR34_F0_PHY_BYTE_LANE_3_WR_CHAN_DLY_CYC_FORCE_ALIGN 0 13948 #define DDR34_F0_PHY_BYTE_LANE_3_WR_CHAN_DLY_CYC_FORCE_BITS 1 13949 #define DDR34_F0_PHY_BYTE_LANE_3_WR_CHAN_DLY_CYC_FORCE_SHIFT 16 13950 13951 /* DDR34_F0_PHY_BYTE_LANE_3 :: WR_CHAN_DLY_CYC :: reserved1 [15:08] */ 13952 #define DDR34_F0_PHY_BYTE_LANE_3_WR_CHAN_DLY_CYC_RESERVED1_MASK 0x0000ff00 13953 #define DDR34_F0_PHY_BYTE_LANE_3_WR_CHAN_DLY_CYC_RESERVED1_ALIGN 0 13954 #define DDR34_F0_PHY_BYTE_LANE_3_WR_CHAN_DLY_CYC_RESERVED1_BITS 8 13955 #define DDR34_F0_PHY_BYTE_LANE_3_WR_CHAN_DLY_CYC_RESERVED1_SHIFT 8 13956 13957 /* DDR34_F0_PHY_BYTE_LANE_3 :: WR_CHAN_DLY_CYC :: DQ_CYCLES [07:04] */ 13958 #define DDR34_F0_PHY_BYTE_LANE_3_WR_CHAN_DLY_CYC_DQ_CYCLES_MASK 0x000000f0 13959 #define DDR34_F0_PHY_BYTE_LANE_3_WR_CHAN_DLY_CYC_DQ_CYCLES_ALIGN 0 13960 #define DDR34_F0_PHY_BYTE_LANE_3_WR_CHAN_DLY_CYC_DQ_CYCLES_BITS 4 13961 #define DDR34_F0_PHY_BYTE_LANE_3_WR_CHAN_DLY_CYC_DQ_CYCLES_SHIFT 4 13962 13963 /* DDR34_F0_PHY_BYTE_LANE_3 :: WR_CHAN_DLY_CYC :: reserved2 [03:03] */ 13964 #define DDR34_F0_PHY_BYTE_LANE_3_WR_CHAN_DLY_CYC_RESERVED2_MASK 0x00000008 13965 #define DDR34_F0_PHY_BYTE_LANE_3_WR_CHAN_DLY_CYC_RESERVED2_ALIGN 0 13966 #define DDR34_F0_PHY_BYTE_LANE_3_WR_CHAN_DLY_CYC_RESERVED2_BITS 1 13967 #define DDR34_F0_PHY_BYTE_LANE_3_WR_CHAN_DLY_CYC_RESERVED2_SHIFT 3 13968 13969 /* DDR34_F0_PHY_BYTE_LANE_3 :: WR_CHAN_DLY_CYC :: CYCLES [02:00] */ 13970 #define DDR34_F0_PHY_BYTE_LANE_3_WR_CHAN_DLY_CYC_CYCLES_MASK 0x00000007 13971 #define DDR34_F0_PHY_BYTE_LANE_3_WR_CHAN_DLY_CYC_CYCLES_ALIGN 0 13972 #define DDR34_F0_PHY_BYTE_LANE_3_WR_CHAN_DLY_CYC_CYCLES_BITS 3 13973 #define DDR34_F0_PHY_BYTE_LANE_3_WR_CHAN_DLY_CYC_CYCLES_SHIFT 0 13974 13975 13976 /**************************************************************************** 13977 * DDR34_F0_PHY_BYTE_LANE_3 :: READ_CONTROL 13978 */ 13979 /* DDR34_F0_PHY_BYTE_LANE_3 :: READ_CONTROL :: reserved0 [31:05] */ 13980 #define DDR34_F0_PHY_BYTE_LANE_3_READ_CONTROL_RESERVED0_MASK 0xffffffe0 13981 #define DDR34_F0_PHY_BYTE_LANE_3_READ_CONTROL_RESERVED0_ALIGN 0 13982 #define DDR34_F0_PHY_BYTE_LANE_3_READ_CONTROL_RESERVED0_BITS 27 13983 #define DDR34_F0_PHY_BYTE_LANE_3_READ_CONTROL_RESERVED0_SHIFT 5 13984 13985 /* DDR34_F0_PHY_BYTE_LANE_3 :: READ_CONTROL :: MODE [04:04] */ 13986 #define DDR34_F0_PHY_BYTE_LANE_3_READ_CONTROL_MODE_MASK 0x00000010 13987 #define DDR34_F0_PHY_BYTE_LANE_3_READ_CONTROL_MODE_ALIGN 0 13988 #define DDR34_F0_PHY_BYTE_LANE_3_READ_CONTROL_MODE_BITS 1 13989 #define DDR34_F0_PHY_BYTE_LANE_3_READ_CONTROL_MODE_SHIFT 4 13990 13991 /* DDR34_F0_PHY_BYTE_LANE_3 :: READ_CONTROL :: RD_EN_MODE [03:03] */ 13992 #define DDR34_F0_PHY_BYTE_LANE_3_READ_CONTROL_RD_EN_MODE_MASK 0x00000008 13993 #define DDR34_F0_PHY_BYTE_LANE_3_READ_CONTROL_RD_EN_MODE_ALIGN 0 13994 #define DDR34_F0_PHY_BYTE_LANE_3_READ_CONTROL_RD_EN_MODE_BITS 1 13995 #define DDR34_F0_PHY_BYTE_LANE_3_READ_CONTROL_RD_EN_MODE_SHIFT 3 13996 13997 /* DDR34_F0_PHY_BYTE_LANE_3 :: READ_CONTROL :: RD_DATA_DLY [02:00] */ 13998 #define DDR34_F0_PHY_BYTE_LANE_3_READ_CONTROL_RD_DATA_DLY_MASK 0x00000007 13999 #define DDR34_F0_PHY_BYTE_LANE_3_READ_CONTROL_RD_DATA_DLY_ALIGN 0 14000 #define DDR34_F0_PHY_BYTE_LANE_3_READ_CONTROL_RD_DATA_DLY_BITS 3 14001 #define DDR34_F0_PHY_BYTE_LANE_3_READ_CONTROL_RD_DATA_DLY_SHIFT 0 14002 14003 14004 /**************************************************************************** 14005 * DDR34_F0_PHY_BYTE_LANE_3 :: READ_FIFO_ADDR 14006 */ 14007 /* DDR34_F0_PHY_BYTE_LANE_3 :: READ_FIFO_ADDR :: reserved0 [31:03] */ 14008 #define DDR34_F0_PHY_BYTE_LANE_3_READ_FIFO_ADDR_RESERVED0_MASK 0xfffffff8 14009 #define DDR34_F0_PHY_BYTE_LANE_3_READ_FIFO_ADDR_RESERVED0_ALIGN 0 14010 #define DDR34_F0_PHY_BYTE_LANE_3_READ_FIFO_ADDR_RESERVED0_BITS 29 14011 #define DDR34_F0_PHY_BYTE_LANE_3_READ_FIFO_ADDR_RESERVED0_SHIFT 3 14012 14013 /* DDR34_F0_PHY_BYTE_LANE_3 :: READ_FIFO_ADDR :: ADDR [02:00] */ 14014 #define DDR34_F0_PHY_BYTE_LANE_3_READ_FIFO_ADDR_ADDR_MASK 0x00000007 14015 #define DDR34_F0_PHY_BYTE_LANE_3_READ_FIFO_ADDR_ADDR_ALIGN 0 14016 #define DDR34_F0_PHY_BYTE_LANE_3_READ_FIFO_ADDR_ADDR_BITS 3 14017 #define DDR34_F0_PHY_BYTE_LANE_3_READ_FIFO_ADDR_ADDR_SHIFT 0 14018 14019 14020 /**************************************************************************** 14021 * DDR34_F0_PHY_BYTE_LANE_3 :: READ_FIFO_DATA 14022 */ 14023 /* DDR34_F0_PHY_BYTE_LANE_3 :: READ_FIFO_DATA :: DATA [31:00] */ 14024 #define DDR34_F0_PHY_BYTE_LANE_3_READ_FIFO_DATA_DATA_MASK 0xffffffff 14025 #define DDR34_F0_PHY_BYTE_LANE_3_READ_FIFO_DATA_DATA_ALIGN 0 14026 #define DDR34_F0_PHY_BYTE_LANE_3_READ_FIFO_DATA_DATA_BITS 32 14027 #define DDR34_F0_PHY_BYTE_LANE_3_READ_FIFO_DATA_DATA_SHIFT 0 14028 14029 14030 /**************************************************************************** 14031 * DDR34_F0_PHY_BYTE_LANE_3 :: READ_FIFO_DM_DBI 14032 */ 14033 /* DDR34_F0_PHY_BYTE_LANE_3 :: READ_FIFO_DM_DBI :: reserved0 [31:04] */ 14034 #define DDR34_F0_PHY_BYTE_LANE_3_READ_FIFO_DM_DBI_RESERVED0_MASK 0xfffffff0 14035 #define DDR34_F0_PHY_BYTE_LANE_3_READ_FIFO_DM_DBI_RESERVED0_ALIGN 0 14036 #define DDR34_F0_PHY_BYTE_LANE_3_READ_FIFO_DM_DBI_RESERVED0_BITS 28 14037 #define DDR34_F0_PHY_BYTE_LANE_3_READ_FIFO_DM_DBI_RESERVED0_SHIFT 4 14038 14039 /* DDR34_F0_PHY_BYTE_LANE_3 :: READ_FIFO_DM_DBI :: DM_DBI [03:00] */ 14040 #define DDR34_F0_PHY_BYTE_LANE_3_READ_FIFO_DM_DBI_DM_DBI_MASK 0x0000000f 14041 #define DDR34_F0_PHY_BYTE_LANE_3_READ_FIFO_DM_DBI_DM_DBI_ALIGN 0 14042 #define DDR34_F0_PHY_BYTE_LANE_3_READ_FIFO_DM_DBI_DM_DBI_BITS 4 14043 #define DDR34_F0_PHY_BYTE_LANE_3_READ_FIFO_DM_DBI_DM_DBI_SHIFT 0 14044 14045 14046 /**************************************************************************** 14047 * DDR34_F0_PHY_BYTE_LANE_3 :: READ_FIFO_STATUS 14048 */ 14049 /* DDR34_F0_PHY_BYTE_LANE_3 :: READ_FIFO_STATUS :: reserved0 [31:02] */ 14050 #define DDR34_F0_PHY_BYTE_LANE_3_READ_FIFO_STATUS_RESERVED0_MASK 0xfffffffc 14051 #define DDR34_F0_PHY_BYTE_LANE_3_READ_FIFO_STATUS_RESERVED0_ALIGN 0 14052 #define DDR34_F0_PHY_BYTE_LANE_3_READ_FIFO_STATUS_RESERVED0_BITS 30 14053 #define DDR34_F0_PHY_BYTE_LANE_3_READ_FIFO_STATUS_RESERVED0_SHIFT 2 14054 14055 /* DDR34_F0_PHY_BYTE_LANE_3 :: READ_FIFO_STATUS :: OVERFLOW [01:01] */ 14056 #define DDR34_F0_PHY_BYTE_LANE_3_READ_FIFO_STATUS_OVERFLOW_MASK 0x00000002 14057 #define DDR34_F0_PHY_BYTE_LANE_3_READ_FIFO_STATUS_OVERFLOW_ALIGN 0 14058 #define DDR34_F0_PHY_BYTE_LANE_3_READ_FIFO_STATUS_OVERFLOW_BITS 1 14059 #define DDR34_F0_PHY_BYTE_LANE_3_READ_FIFO_STATUS_OVERFLOW_SHIFT 1 14060 14061 /* DDR34_F0_PHY_BYTE_LANE_3 :: READ_FIFO_STATUS :: UNDERFLOW [00:00] */ 14062 #define DDR34_F0_PHY_BYTE_LANE_3_READ_FIFO_STATUS_UNDERFLOW_MASK 0x00000001 14063 #define DDR34_F0_PHY_BYTE_LANE_3_READ_FIFO_STATUS_UNDERFLOW_ALIGN 0 14064 #define DDR34_F0_PHY_BYTE_LANE_3_READ_FIFO_STATUS_UNDERFLOW_BITS 1 14065 #define DDR34_F0_PHY_BYTE_LANE_3_READ_FIFO_STATUS_UNDERFLOW_SHIFT 0 14066 14067 14068 /**************************************************************************** 14069 * DDR34_F0_PHY_BYTE_LANE_3 :: READ_FIFO_CLEAR 14070 */ 14071 /* DDR34_F0_PHY_BYTE_LANE_3 :: READ_FIFO_CLEAR :: reserved0 [31:01] */ 14072 #define DDR34_F0_PHY_BYTE_LANE_3_READ_FIFO_CLEAR_RESERVED0_MASK 0xfffffffe 14073 #define DDR34_F0_PHY_BYTE_LANE_3_READ_FIFO_CLEAR_RESERVED0_ALIGN 0 14074 #define DDR34_F0_PHY_BYTE_LANE_3_READ_FIFO_CLEAR_RESERVED0_BITS 31 14075 #define DDR34_F0_PHY_BYTE_LANE_3_READ_FIFO_CLEAR_RESERVED0_SHIFT 1 14076 14077 /* DDR34_F0_PHY_BYTE_LANE_3 :: READ_FIFO_CLEAR :: CLEAR [00:00] */ 14078 #define DDR34_F0_PHY_BYTE_LANE_3_READ_FIFO_CLEAR_CLEAR_MASK 0x00000001 14079 #define DDR34_F0_PHY_BYTE_LANE_3_READ_FIFO_CLEAR_CLEAR_ALIGN 0 14080 #define DDR34_F0_PHY_BYTE_LANE_3_READ_FIFO_CLEAR_CLEAR_BITS 1 14081 #define DDR34_F0_PHY_BYTE_LANE_3_READ_FIFO_CLEAR_CLEAR_SHIFT 0 14082 14083 14084 /**************************************************************************** 14085 * DDR34_F0_PHY_BYTE_LANE_3 :: IDLE_PAD_CONTROL 14086 */ 14087 /* DDR34_F0_PHY_BYTE_LANE_3 :: IDLE_PAD_CONTROL :: IDLE [31:31] */ 14088 #define DDR34_F0_PHY_BYTE_LANE_3_IDLE_PAD_CONTROL_IDLE_MASK 0x80000000 14089 #define DDR34_F0_PHY_BYTE_LANE_3_IDLE_PAD_CONTROL_IDLE_ALIGN 0 14090 #define DDR34_F0_PHY_BYTE_LANE_3_IDLE_PAD_CONTROL_IDLE_BITS 1 14091 #define DDR34_F0_PHY_BYTE_LANE_3_IDLE_PAD_CONTROL_IDLE_SHIFT 31 14092 14093 /* DDR34_F0_PHY_BYTE_LANE_3 :: IDLE_PAD_CONTROL :: reserved0 [30:20] */ 14094 #define DDR34_F0_PHY_BYTE_LANE_3_IDLE_PAD_CONTROL_RESERVED0_MASK 0x7ff00000 14095 #define DDR34_F0_PHY_BYTE_LANE_3_IDLE_PAD_CONTROL_RESERVED0_ALIGN 0 14096 #define DDR34_F0_PHY_BYTE_LANE_3_IDLE_PAD_CONTROL_RESERVED0_BITS 11 14097 #define DDR34_F0_PHY_BYTE_LANE_3_IDLE_PAD_CONTROL_RESERVED0_SHIFT 20 14098 14099 /* DDR34_F0_PHY_BYTE_LANE_3 :: IDLE_PAD_CONTROL :: AUTO_DQ_RXENB_MODE [19:18] */ 14100 #define DDR34_F0_PHY_BYTE_LANE_3_IDLE_PAD_CONTROL_AUTO_DQ_RXENB_MODE_MASK 0x000c0000 14101 #define DDR34_F0_PHY_BYTE_LANE_3_IDLE_PAD_CONTROL_AUTO_DQ_RXENB_MODE_ALIGN 0 14102 #define DDR34_F0_PHY_BYTE_LANE_3_IDLE_PAD_CONTROL_AUTO_DQ_RXENB_MODE_BITS 2 14103 #define DDR34_F0_PHY_BYTE_LANE_3_IDLE_PAD_CONTROL_AUTO_DQ_RXENB_MODE_SHIFT 18 14104 14105 /* DDR34_F0_PHY_BYTE_LANE_3 :: IDLE_PAD_CONTROL :: AUTO_DQ_IDDQ_MODE [17:16] */ 14106 #define DDR34_F0_PHY_BYTE_LANE_3_IDLE_PAD_CONTROL_AUTO_DQ_IDDQ_MODE_MASK 0x00030000 14107 #define DDR34_F0_PHY_BYTE_LANE_3_IDLE_PAD_CONTROL_AUTO_DQ_IDDQ_MODE_ALIGN 0 14108 #define DDR34_F0_PHY_BYTE_LANE_3_IDLE_PAD_CONTROL_AUTO_DQ_IDDQ_MODE_BITS 2 14109 #define DDR34_F0_PHY_BYTE_LANE_3_IDLE_PAD_CONTROL_AUTO_DQ_IDDQ_MODE_SHIFT 16 14110 14111 /* DDR34_F0_PHY_BYTE_LANE_3 :: IDLE_PAD_CONTROL :: IO_IDLE_ENABLE [15:04] */ 14112 #define DDR34_F0_PHY_BYTE_LANE_3_IDLE_PAD_CONTROL_IO_IDLE_ENABLE_MASK 0x0000fff0 14113 #define DDR34_F0_PHY_BYTE_LANE_3_IDLE_PAD_CONTROL_IO_IDLE_ENABLE_ALIGN 0 14114 #define DDR34_F0_PHY_BYTE_LANE_3_IDLE_PAD_CONTROL_IO_IDLE_ENABLE_BITS 12 14115 #define DDR34_F0_PHY_BYTE_LANE_3_IDLE_PAD_CONTROL_IO_IDLE_ENABLE_SHIFT 4 14116 14117 /* DDR34_F0_PHY_BYTE_LANE_3 :: IDLE_PAD_CONTROL :: RXENB [03:03] */ 14118 #define DDR34_F0_PHY_BYTE_LANE_3_IDLE_PAD_CONTROL_RXENB_MASK 0x00000008 14119 #define DDR34_F0_PHY_BYTE_LANE_3_IDLE_PAD_CONTROL_RXENB_ALIGN 0 14120 #define DDR34_F0_PHY_BYTE_LANE_3_IDLE_PAD_CONTROL_RXENB_BITS 1 14121 #define DDR34_F0_PHY_BYTE_LANE_3_IDLE_PAD_CONTROL_RXENB_SHIFT 3 14122 14123 /* DDR34_F0_PHY_BYTE_LANE_3 :: IDLE_PAD_CONTROL :: IDDQ [02:02] */ 14124 #define DDR34_F0_PHY_BYTE_LANE_3_IDLE_PAD_CONTROL_IDDQ_MASK 0x00000004 14125 #define DDR34_F0_PHY_BYTE_LANE_3_IDLE_PAD_CONTROL_IDDQ_ALIGN 0 14126 #define DDR34_F0_PHY_BYTE_LANE_3_IDLE_PAD_CONTROL_IDDQ_BITS 1 14127 #define DDR34_F0_PHY_BYTE_LANE_3_IDLE_PAD_CONTROL_IDDQ_SHIFT 2 14128 14129 /* DDR34_F0_PHY_BYTE_LANE_3 :: IDLE_PAD_CONTROL :: DOUT_N [01:01] */ 14130 #define DDR34_F0_PHY_BYTE_LANE_3_IDLE_PAD_CONTROL_DOUT_N_MASK 0x00000002 14131 #define DDR34_F0_PHY_BYTE_LANE_3_IDLE_PAD_CONTROL_DOUT_N_ALIGN 0 14132 #define DDR34_F0_PHY_BYTE_LANE_3_IDLE_PAD_CONTROL_DOUT_N_BITS 1 14133 #define DDR34_F0_PHY_BYTE_LANE_3_IDLE_PAD_CONTROL_DOUT_N_SHIFT 1 14134 14135 /* DDR34_F0_PHY_BYTE_LANE_3 :: IDLE_PAD_CONTROL :: DOUT_P [00:00] */ 14136 #define DDR34_F0_PHY_BYTE_LANE_3_IDLE_PAD_CONTROL_DOUT_P_MASK 0x00000001 14137 #define DDR34_F0_PHY_BYTE_LANE_3_IDLE_PAD_CONTROL_DOUT_P_ALIGN 0 14138 #define DDR34_F0_PHY_BYTE_LANE_3_IDLE_PAD_CONTROL_DOUT_P_BITS 1 14139 #define DDR34_F0_PHY_BYTE_LANE_3_IDLE_PAD_CONTROL_DOUT_P_SHIFT 0 14140 14141 14142 /**************************************************************************** 14143 * DDR34_F0_PHY_BYTE_LANE_3 :: DRIVE_PAD_CTL 14144 */ 14145 /* DDR34_F0_PHY_BYTE_LANE_3 :: DRIVE_PAD_CTL :: reserved0 [31:20] */ 14146 #define DDR34_F0_PHY_BYTE_LANE_3_DRIVE_PAD_CTL_RESERVED0_MASK 0xfff00000 14147 #define DDR34_F0_PHY_BYTE_LANE_3_DRIVE_PAD_CTL_RESERVED0_ALIGN 0 14148 #define DDR34_F0_PHY_BYTE_LANE_3_DRIVE_PAD_CTL_RESERVED0_BITS 12 14149 #define DDR34_F0_PHY_BYTE_LANE_3_DRIVE_PAD_CTL_RESERVED0_SHIFT 20 14150 14151 /* DDR34_F0_PHY_BYTE_LANE_3 :: DRIVE_PAD_CTL :: BL_PD_TERM_STRENGTH [19:15] */ 14152 #define DDR34_F0_PHY_BYTE_LANE_3_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_MASK 0x000f8000 14153 #define DDR34_F0_PHY_BYTE_LANE_3_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_ALIGN 0 14154 #define DDR34_F0_PHY_BYTE_LANE_3_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_BITS 5 14155 #define DDR34_F0_PHY_BYTE_LANE_3_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_SHIFT 15 14156 14157 /* DDR34_F0_PHY_BYTE_LANE_3 :: DRIVE_PAD_CTL :: BL_ND_TERM_STRENGTH [14:10] */ 14158 #define DDR34_F0_PHY_BYTE_LANE_3_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_MASK 0x00007c00 14159 #define DDR34_F0_PHY_BYTE_LANE_3_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_ALIGN 0 14160 #define DDR34_F0_PHY_BYTE_LANE_3_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_BITS 5 14161 #define DDR34_F0_PHY_BYTE_LANE_3_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_SHIFT 10 14162 14163 /* DDR34_F0_PHY_BYTE_LANE_3 :: DRIVE_PAD_CTL :: BL_PD_STRENGTH [09:05] */ 14164 #define DDR34_F0_PHY_BYTE_LANE_3_DRIVE_PAD_CTL_BL_PD_STRENGTH_MASK 0x000003e0 14165 #define DDR34_F0_PHY_BYTE_LANE_3_DRIVE_PAD_CTL_BL_PD_STRENGTH_ALIGN 0 14166 #define DDR34_F0_PHY_BYTE_LANE_3_DRIVE_PAD_CTL_BL_PD_STRENGTH_BITS 5 14167 #define DDR34_F0_PHY_BYTE_LANE_3_DRIVE_PAD_CTL_BL_PD_STRENGTH_SHIFT 5 14168 14169 /* DDR34_F0_PHY_BYTE_LANE_3 :: DRIVE_PAD_CTL :: BL_ND_STRENGTH [04:00] */ 14170 #define DDR34_F0_PHY_BYTE_LANE_3_DRIVE_PAD_CTL_BL_ND_STRENGTH_MASK 0x0000001f 14171 #define DDR34_F0_PHY_BYTE_LANE_3_DRIVE_PAD_CTL_BL_ND_STRENGTH_ALIGN 0 14172 #define DDR34_F0_PHY_BYTE_LANE_3_DRIVE_PAD_CTL_BL_ND_STRENGTH_BITS 5 14173 #define DDR34_F0_PHY_BYTE_LANE_3_DRIVE_PAD_CTL_BL_ND_STRENGTH_SHIFT 0 14174 14175 14176 /**************************************************************************** 14177 * DDR34_F0_PHY_BYTE_LANE_3 :: DQSP_DRIVE_PAD_CTL 14178 */ 14179 /* DDR34_F0_PHY_BYTE_LANE_3 :: DQSP_DRIVE_PAD_CTL :: reserved0 [31:20] */ 14180 #define DDR34_F0_PHY_BYTE_LANE_3_DQSP_DRIVE_PAD_CTL_RESERVED0_MASK 0xfff00000 14181 #define DDR34_F0_PHY_BYTE_LANE_3_DQSP_DRIVE_PAD_CTL_RESERVED0_ALIGN 0 14182 #define DDR34_F0_PHY_BYTE_LANE_3_DQSP_DRIVE_PAD_CTL_RESERVED0_BITS 12 14183 #define DDR34_F0_PHY_BYTE_LANE_3_DQSP_DRIVE_PAD_CTL_RESERVED0_SHIFT 20 14184 14185 /* DDR34_F0_PHY_BYTE_LANE_3 :: DQSP_DRIVE_PAD_CTL :: BL_PD_TERM_STRENGTH [19:15] */ 14186 #define DDR34_F0_PHY_BYTE_LANE_3_DQSP_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_MASK 0x000f8000 14187 #define DDR34_F0_PHY_BYTE_LANE_3_DQSP_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_ALIGN 0 14188 #define DDR34_F0_PHY_BYTE_LANE_3_DQSP_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_BITS 5 14189 #define DDR34_F0_PHY_BYTE_LANE_3_DQSP_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_SHIFT 15 14190 14191 /* DDR34_F0_PHY_BYTE_LANE_3 :: DQSP_DRIVE_PAD_CTL :: BL_ND_TERM_STRENGTH [14:10] */ 14192 #define DDR34_F0_PHY_BYTE_LANE_3_DQSP_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_MASK 0x00007c00 14193 #define DDR34_F0_PHY_BYTE_LANE_3_DQSP_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_ALIGN 0 14194 #define DDR34_F0_PHY_BYTE_LANE_3_DQSP_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_BITS 5 14195 #define DDR34_F0_PHY_BYTE_LANE_3_DQSP_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_SHIFT 10 14196 14197 /* DDR34_F0_PHY_BYTE_LANE_3 :: DQSP_DRIVE_PAD_CTL :: BL_PD_STRENGTH [09:05] */ 14198 #define DDR34_F0_PHY_BYTE_LANE_3_DQSP_DRIVE_PAD_CTL_BL_PD_STRENGTH_MASK 0x000003e0 14199 #define DDR34_F0_PHY_BYTE_LANE_3_DQSP_DRIVE_PAD_CTL_BL_PD_STRENGTH_ALIGN 0 14200 #define DDR34_F0_PHY_BYTE_LANE_3_DQSP_DRIVE_PAD_CTL_BL_PD_STRENGTH_BITS 5 14201 #define DDR34_F0_PHY_BYTE_LANE_3_DQSP_DRIVE_PAD_CTL_BL_PD_STRENGTH_SHIFT 5 14202 14203 /* DDR34_F0_PHY_BYTE_LANE_3 :: DQSP_DRIVE_PAD_CTL :: BL_ND_STRENGTH [04:00] */ 14204 #define DDR34_F0_PHY_BYTE_LANE_3_DQSP_DRIVE_PAD_CTL_BL_ND_STRENGTH_MASK 0x0000001f 14205 #define DDR34_F0_PHY_BYTE_LANE_3_DQSP_DRIVE_PAD_CTL_BL_ND_STRENGTH_ALIGN 0 14206 #define DDR34_F0_PHY_BYTE_LANE_3_DQSP_DRIVE_PAD_CTL_BL_ND_STRENGTH_BITS 5 14207 #define DDR34_F0_PHY_BYTE_LANE_3_DQSP_DRIVE_PAD_CTL_BL_ND_STRENGTH_SHIFT 0 14208 14209 14210 /**************************************************************************** 14211 * DDR34_F0_PHY_BYTE_LANE_3 :: DQSN_DRIVE_PAD_CTL 14212 */ 14213 /* DDR34_F0_PHY_BYTE_LANE_3 :: DQSN_DRIVE_PAD_CTL :: reserved0 [31:20] */ 14214 #define DDR34_F0_PHY_BYTE_LANE_3_DQSN_DRIVE_PAD_CTL_RESERVED0_MASK 0xfff00000 14215 #define DDR34_F0_PHY_BYTE_LANE_3_DQSN_DRIVE_PAD_CTL_RESERVED0_ALIGN 0 14216 #define DDR34_F0_PHY_BYTE_LANE_3_DQSN_DRIVE_PAD_CTL_RESERVED0_BITS 12 14217 #define DDR34_F0_PHY_BYTE_LANE_3_DQSN_DRIVE_PAD_CTL_RESERVED0_SHIFT 20 14218 14219 /* DDR34_F0_PHY_BYTE_LANE_3 :: DQSN_DRIVE_PAD_CTL :: BL_PD_TERM_STRENGTH [19:15] */ 14220 #define DDR34_F0_PHY_BYTE_LANE_3_DQSN_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_MASK 0x000f8000 14221 #define DDR34_F0_PHY_BYTE_LANE_3_DQSN_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_ALIGN 0 14222 #define DDR34_F0_PHY_BYTE_LANE_3_DQSN_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_BITS 5 14223 #define DDR34_F0_PHY_BYTE_LANE_3_DQSN_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_SHIFT 15 14224 14225 /* DDR34_F0_PHY_BYTE_LANE_3 :: DQSN_DRIVE_PAD_CTL :: BL_ND_TERM_STRENGTH [14:10] */ 14226 #define DDR34_F0_PHY_BYTE_LANE_3_DQSN_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_MASK 0x00007c00 14227 #define DDR34_F0_PHY_BYTE_LANE_3_DQSN_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_ALIGN 0 14228 #define DDR34_F0_PHY_BYTE_LANE_3_DQSN_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_BITS 5 14229 #define DDR34_F0_PHY_BYTE_LANE_3_DQSN_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_SHIFT 10 14230 14231 /* DDR34_F0_PHY_BYTE_LANE_3 :: DQSN_DRIVE_PAD_CTL :: BL_PD_STRENGTH [09:05] */ 14232 #define DDR34_F0_PHY_BYTE_LANE_3_DQSN_DRIVE_PAD_CTL_BL_PD_STRENGTH_MASK 0x000003e0 14233 #define DDR34_F0_PHY_BYTE_LANE_3_DQSN_DRIVE_PAD_CTL_BL_PD_STRENGTH_ALIGN 0 14234 #define DDR34_F0_PHY_BYTE_LANE_3_DQSN_DRIVE_PAD_CTL_BL_PD_STRENGTH_BITS 5 14235 #define DDR34_F0_PHY_BYTE_LANE_3_DQSN_DRIVE_PAD_CTL_BL_PD_STRENGTH_SHIFT 5 14236 14237 /* DDR34_F0_PHY_BYTE_LANE_3 :: DQSN_DRIVE_PAD_CTL :: BL_ND_STRENGTH [04:00] */ 14238 #define DDR34_F0_PHY_BYTE_LANE_3_DQSN_DRIVE_PAD_CTL_BL_ND_STRENGTH_MASK 0x0000001f 14239 #define DDR34_F0_PHY_BYTE_LANE_3_DQSN_DRIVE_PAD_CTL_BL_ND_STRENGTH_ALIGN 0 14240 #define DDR34_F0_PHY_BYTE_LANE_3_DQSN_DRIVE_PAD_CTL_BL_ND_STRENGTH_BITS 5 14241 #define DDR34_F0_PHY_BYTE_LANE_3_DQSN_DRIVE_PAD_CTL_BL_ND_STRENGTH_SHIFT 0 14242 14243 14244 /**************************************************************************** 14245 * DDR34_F0_PHY_BYTE_LANE_3 :: ALERT_DRIVE_PAD_CTL 14246 */ 14247 /* DDR34_F0_PHY_BYTE_LANE_3 :: ALERT_DRIVE_PAD_CTL :: reserved0 [31:20] */ 14248 #define DDR34_F0_PHY_BYTE_LANE_3_ALERT_DRIVE_PAD_CTL_RESERVED0_MASK 0xfff00000 14249 #define DDR34_F0_PHY_BYTE_LANE_3_ALERT_DRIVE_PAD_CTL_RESERVED0_ALIGN 0 14250 #define DDR34_F0_PHY_BYTE_LANE_3_ALERT_DRIVE_PAD_CTL_RESERVED0_BITS 12 14251 #define DDR34_F0_PHY_BYTE_LANE_3_ALERT_DRIVE_PAD_CTL_RESERVED0_SHIFT 20 14252 14253 /* DDR34_F0_PHY_BYTE_LANE_3 :: ALERT_DRIVE_PAD_CTL :: BL_PD_TERM_STRENGTH [19:15] */ 14254 #define DDR34_F0_PHY_BYTE_LANE_3_ALERT_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_MASK 0x000f8000 14255 #define DDR34_F0_PHY_BYTE_LANE_3_ALERT_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_ALIGN 0 14256 #define DDR34_F0_PHY_BYTE_LANE_3_ALERT_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_BITS 5 14257 #define DDR34_F0_PHY_BYTE_LANE_3_ALERT_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_SHIFT 15 14258 14259 /* DDR34_F0_PHY_BYTE_LANE_3 :: ALERT_DRIVE_PAD_CTL :: BL_ND_TERM_STRENGTH [14:10] */ 14260 #define DDR34_F0_PHY_BYTE_LANE_3_ALERT_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_MASK 0x00007c00 14261 #define DDR34_F0_PHY_BYTE_LANE_3_ALERT_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_ALIGN 0 14262 #define DDR34_F0_PHY_BYTE_LANE_3_ALERT_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_BITS 5 14263 #define DDR34_F0_PHY_BYTE_LANE_3_ALERT_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_SHIFT 10 14264 14265 /* DDR34_F0_PHY_BYTE_LANE_3 :: ALERT_DRIVE_PAD_CTL :: BL_PD_STRENGTH [09:05] */ 14266 #define DDR34_F0_PHY_BYTE_LANE_3_ALERT_DRIVE_PAD_CTL_BL_PD_STRENGTH_MASK 0x000003e0 14267 #define DDR34_F0_PHY_BYTE_LANE_3_ALERT_DRIVE_PAD_CTL_BL_PD_STRENGTH_ALIGN 0 14268 #define DDR34_F0_PHY_BYTE_LANE_3_ALERT_DRIVE_PAD_CTL_BL_PD_STRENGTH_BITS 5 14269 #define DDR34_F0_PHY_BYTE_LANE_3_ALERT_DRIVE_PAD_CTL_BL_PD_STRENGTH_SHIFT 5 14270 14271 /* DDR34_F0_PHY_BYTE_LANE_3 :: ALERT_DRIVE_PAD_CTL :: BL_ND_STRENGTH [04:00] */ 14272 #define DDR34_F0_PHY_BYTE_LANE_3_ALERT_DRIVE_PAD_CTL_BL_ND_STRENGTH_MASK 0x0000001f 14273 #define DDR34_F0_PHY_BYTE_LANE_3_ALERT_DRIVE_PAD_CTL_BL_ND_STRENGTH_ALIGN 0 14274 #define DDR34_F0_PHY_BYTE_LANE_3_ALERT_DRIVE_PAD_CTL_BL_ND_STRENGTH_BITS 5 14275 #define DDR34_F0_PHY_BYTE_LANE_3_ALERT_DRIVE_PAD_CTL_BL_ND_STRENGTH_SHIFT 0 14276 14277 14278 /**************************************************************************** 14279 * DDR34_F0_PHY_BYTE_LANE_3 :: RD_EN_DRIVE_PAD_CTL 14280 */ 14281 /* DDR34_F0_PHY_BYTE_LANE_3 :: RD_EN_DRIVE_PAD_CTL :: reserved0 [31:10] */ 14282 #define DDR34_F0_PHY_BYTE_LANE_3_RD_EN_DRIVE_PAD_CTL_RESERVED0_MASK 0xfffffc00 14283 #define DDR34_F0_PHY_BYTE_LANE_3_RD_EN_DRIVE_PAD_CTL_RESERVED0_ALIGN 0 14284 #define DDR34_F0_PHY_BYTE_LANE_3_RD_EN_DRIVE_PAD_CTL_RESERVED0_BITS 22 14285 #define DDR34_F0_PHY_BYTE_LANE_3_RD_EN_DRIVE_PAD_CTL_RESERVED0_SHIFT 10 14286 14287 /* DDR34_F0_PHY_BYTE_LANE_3 :: RD_EN_DRIVE_PAD_CTL :: BL_RD_EN_PD_STRENGTH [09:05] */ 14288 #define DDR34_F0_PHY_BYTE_LANE_3_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_PD_STRENGTH_MASK 0x000003e0 14289 #define DDR34_F0_PHY_BYTE_LANE_3_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_PD_STRENGTH_ALIGN 0 14290 #define DDR34_F0_PHY_BYTE_LANE_3_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_PD_STRENGTH_BITS 5 14291 #define DDR34_F0_PHY_BYTE_LANE_3_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_PD_STRENGTH_SHIFT 5 14292 14293 /* DDR34_F0_PHY_BYTE_LANE_3 :: RD_EN_DRIVE_PAD_CTL :: BL_RD_EN_ND_STRENGTH [04:00] */ 14294 #define DDR34_F0_PHY_BYTE_LANE_3_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_ND_STRENGTH_MASK 0x0000001f 14295 #define DDR34_F0_PHY_BYTE_LANE_3_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_ND_STRENGTH_ALIGN 0 14296 #define DDR34_F0_PHY_BYTE_LANE_3_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_ND_STRENGTH_BITS 5 14297 #define DDR34_F0_PHY_BYTE_LANE_3_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_ND_STRENGTH_SHIFT 0 14298 14299 14300 /**************************************************************************** 14301 * DDR34_F0_PHY_BYTE_LANE_3 :: STATIC_PAD_CTL 14302 */ 14303 /* DDR34_F0_PHY_BYTE_LANE_3 :: STATIC_PAD_CTL :: reserved0 [31:18] */ 14304 #define DDR34_F0_PHY_BYTE_LANE_3_STATIC_PAD_CTL_RESERVED0_MASK 0xfffc0000 14305 #define DDR34_F0_PHY_BYTE_LANE_3_STATIC_PAD_CTL_RESERVED0_ALIGN 0 14306 #define DDR34_F0_PHY_BYTE_LANE_3_STATIC_PAD_CTL_RESERVED0_BITS 14 14307 #define DDR34_F0_PHY_BYTE_LANE_3_STATIC_PAD_CTL_RESERVED0_SHIFT 18 14308 14309 /* DDR34_F0_PHY_BYTE_LANE_3 :: STATIC_PAD_CTL :: DM_INVERT [17:17] */ 14310 #define DDR34_F0_PHY_BYTE_LANE_3_STATIC_PAD_CTL_DM_INVERT_MASK 0x00020000 14311 #define DDR34_F0_PHY_BYTE_LANE_3_STATIC_PAD_CTL_DM_INVERT_ALIGN 0 14312 #define DDR34_F0_PHY_BYTE_LANE_3_STATIC_PAD_CTL_DM_INVERT_BITS 1 14313 #define DDR34_F0_PHY_BYTE_LANE_3_STATIC_PAD_CTL_DM_INVERT_SHIFT 17 14314 14315 /* DDR34_F0_PHY_BYTE_LANE_3 :: STATIC_PAD_CTL :: WDBI_ENABLE [16:16] */ 14316 #define DDR34_F0_PHY_BYTE_LANE_3_STATIC_PAD_CTL_WDBI_ENABLE_MASK 0x00010000 14317 #define DDR34_F0_PHY_BYTE_LANE_3_STATIC_PAD_CTL_WDBI_ENABLE_ALIGN 0 14318 #define DDR34_F0_PHY_BYTE_LANE_3_STATIC_PAD_CTL_WDBI_ENABLE_BITS 1 14319 #define DDR34_F0_PHY_BYTE_LANE_3_STATIC_PAD_CTL_WDBI_ENABLE_SHIFT 16 14320 14321 /* DDR34_F0_PHY_BYTE_LANE_3 :: STATIC_PAD_CTL :: RDBI_ENABLE [15:15] */ 14322 #define DDR34_F0_PHY_BYTE_LANE_3_STATIC_PAD_CTL_RDBI_ENABLE_MASK 0x00008000 14323 #define DDR34_F0_PHY_BYTE_LANE_3_STATIC_PAD_CTL_RDBI_ENABLE_ALIGN 0 14324 #define DDR34_F0_PHY_BYTE_LANE_3_STATIC_PAD_CTL_RDBI_ENABLE_BITS 1 14325 #define DDR34_F0_PHY_BYTE_LANE_3_STATIC_PAD_CTL_RDBI_ENABLE_SHIFT 15 14326 14327 /* DDR34_F0_PHY_BYTE_LANE_3 :: STATIC_PAD_CTL :: DM_MODE [14:14] */ 14328 #define DDR34_F0_PHY_BYTE_LANE_3_STATIC_PAD_CTL_DM_MODE_MASK 0x00004000 14329 #define DDR34_F0_PHY_BYTE_LANE_3_STATIC_PAD_CTL_DM_MODE_ALIGN 0 14330 #define DDR34_F0_PHY_BYTE_LANE_3_STATIC_PAD_CTL_DM_MODE_BITS 1 14331 #define DDR34_F0_PHY_BYTE_LANE_3_STATIC_PAD_CTL_DM_MODE_SHIFT 14 14332 14333 /* DDR34_F0_PHY_BYTE_LANE_3 :: STATIC_PAD_CTL :: reserved1 [13:10] */ 14334 #define DDR34_F0_PHY_BYTE_LANE_3_STATIC_PAD_CTL_RESERVED1_MASK 0x00003c00 14335 #define DDR34_F0_PHY_BYTE_LANE_3_STATIC_PAD_CTL_RESERVED1_ALIGN 0 14336 #define DDR34_F0_PHY_BYTE_LANE_3_STATIC_PAD_CTL_RESERVED1_BITS 4 14337 #define DDR34_F0_PHY_BYTE_LANE_3_STATIC_PAD_CTL_RESERVED1_SHIFT 10 14338 14339 /* DDR34_F0_PHY_BYTE_LANE_3 :: STATIC_PAD_CTL :: DQS_TX_DIS [09:09] */ 14340 #define DDR34_F0_PHY_BYTE_LANE_3_STATIC_PAD_CTL_DQS_TX_DIS_MASK 0x00000200 14341 #define DDR34_F0_PHY_BYTE_LANE_3_STATIC_PAD_CTL_DQS_TX_DIS_ALIGN 0 14342 #define DDR34_F0_PHY_BYTE_LANE_3_STATIC_PAD_CTL_DQS_TX_DIS_BITS 1 14343 #define DDR34_F0_PHY_BYTE_LANE_3_STATIC_PAD_CTL_DQS_TX_DIS_SHIFT 9 14344 14345 /* DDR34_F0_PHY_BYTE_LANE_3 :: STATIC_PAD_CTL :: reserved2 [08:02] */ 14346 #define DDR34_F0_PHY_BYTE_LANE_3_STATIC_PAD_CTL_RESERVED2_MASK 0x000001fc 14347 #define DDR34_F0_PHY_BYTE_LANE_3_STATIC_PAD_CTL_RESERVED2_ALIGN 0 14348 #define DDR34_F0_PHY_BYTE_LANE_3_STATIC_PAD_CTL_RESERVED2_BITS 7 14349 #define DDR34_F0_PHY_BYTE_LANE_3_STATIC_PAD_CTL_RESERVED2_SHIFT 2 14350 14351 /* DDR34_F0_PHY_BYTE_LANE_3 :: STATIC_PAD_CTL :: RX_MODE [01:00] */ 14352 #define DDR34_F0_PHY_BYTE_LANE_3_STATIC_PAD_CTL_RX_MODE_MASK 0x00000003 14353 #define DDR34_F0_PHY_BYTE_LANE_3_STATIC_PAD_CTL_RX_MODE_ALIGN 0 14354 #define DDR34_F0_PHY_BYTE_LANE_3_STATIC_PAD_CTL_RX_MODE_BITS 2 14355 #define DDR34_F0_PHY_BYTE_LANE_3_STATIC_PAD_CTL_RX_MODE_SHIFT 0 14356 14357 14358 /**************************************************************************** 14359 * DDR34_F0_PHY_BYTE_LANE_3 :: WR_PREAMBLE_MODE 14360 */ 14361 /* DDR34_F0_PHY_BYTE_LANE_3 :: WR_PREAMBLE_MODE :: reserved0 [31:21] */ 14362 #define DDR34_F0_PHY_BYTE_LANE_3_WR_PREAMBLE_MODE_RESERVED0_MASK 0xffe00000 14363 #define DDR34_F0_PHY_BYTE_LANE_3_WR_PREAMBLE_MODE_RESERVED0_ALIGN 0 14364 #define DDR34_F0_PHY_BYTE_LANE_3_WR_PREAMBLE_MODE_RESERVED0_BITS 11 14365 #define DDR34_F0_PHY_BYTE_LANE_3_WR_PREAMBLE_MODE_RESERVED0_SHIFT 21 14366 14367 /* DDR34_F0_PHY_BYTE_LANE_3 :: WR_PREAMBLE_MODE :: POSTAM_TERM_BITS [20:19] */ 14368 #define DDR34_F0_PHY_BYTE_LANE_3_WR_PREAMBLE_MODE_POSTAM_TERM_BITS_MASK 0x00180000 14369 #define DDR34_F0_PHY_BYTE_LANE_3_WR_PREAMBLE_MODE_POSTAM_TERM_BITS_ALIGN 0 14370 #define DDR34_F0_PHY_BYTE_LANE_3_WR_PREAMBLE_MODE_POSTAM_TERM_BITS_BITS 2 14371 #define DDR34_F0_PHY_BYTE_LANE_3_WR_PREAMBLE_MODE_POSTAM_TERM_BITS_SHIFT 19 14372 14373 /* DDR34_F0_PHY_BYTE_LANE_3 :: WR_PREAMBLE_MODE :: DM_POSTAM_BITS [18:17] */ 14374 #define DDR34_F0_PHY_BYTE_LANE_3_WR_PREAMBLE_MODE_DM_POSTAM_BITS_MASK 0x00060000 14375 #define DDR34_F0_PHY_BYTE_LANE_3_WR_PREAMBLE_MODE_DM_POSTAM_BITS_ALIGN 0 14376 #define DDR34_F0_PHY_BYTE_LANE_3_WR_PREAMBLE_MODE_DM_POSTAM_BITS_BITS 2 14377 #define DDR34_F0_PHY_BYTE_LANE_3_WR_PREAMBLE_MODE_DM_POSTAM_BITS_SHIFT 17 14378 14379 /* DDR34_F0_PHY_BYTE_LANE_3 :: WR_PREAMBLE_MODE :: DM_PREAM_BITS [16:14] */ 14380 #define DDR34_F0_PHY_BYTE_LANE_3_WR_PREAMBLE_MODE_DM_PREAM_BITS_MASK 0x0001c000 14381 #define DDR34_F0_PHY_BYTE_LANE_3_WR_PREAMBLE_MODE_DM_PREAM_BITS_ALIGN 0 14382 #define DDR34_F0_PHY_BYTE_LANE_3_WR_PREAMBLE_MODE_DM_PREAM_BITS_BITS 3 14383 #define DDR34_F0_PHY_BYTE_LANE_3_WR_PREAMBLE_MODE_DM_PREAM_BITS_SHIFT 14 14384 14385 /* DDR34_F0_PHY_BYTE_LANE_3 :: WR_PREAMBLE_MODE :: DQ_POSTAM_BITS [13:12] */ 14386 #define DDR34_F0_PHY_BYTE_LANE_3_WR_PREAMBLE_MODE_DQ_POSTAM_BITS_MASK 0x00003000 14387 #define DDR34_F0_PHY_BYTE_LANE_3_WR_PREAMBLE_MODE_DQ_POSTAM_BITS_ALIGN 0 14388 #define DDR34_F0_PHY_BYTE_LANE_3_WR_PREAMBLE_MODE_DQ_POSTAM_BITS_BITS 2 14389 #define DDR34_F0_PHY_BYTE_LANE_3_WR_PREAMBLE_MODE_DQ_POSTAM_BITS_SHIFT 12 14390 14391 /* DDR34_F0_PHY_BYTE_LANE_3 :: WR_PREAMBLE_MODE :: DQ_PREAM_BITS [11:09] */ 14392 #define DDR34_F0_PHY_BYTE_LANE_3_WR_PREAMBLE_MODE_DQ_PREAM_BITS_MASK 0x00000e00 14393 #define DDR34_F0_PHY_BYTE_LANE_3_WR_PREAMBLE_MODE_DQ_PREAM_BITS_ALIGN 0 14394 #define DDR34_F0_PHY_BYTE_LANE_3_WR_PREAMBLE_MODE_DQ_PREAM_BITS_BITS 3 14395 #define DDR34_F0_PHY_BYTE_LANE_3_WR_PREAMBLE_MODE_DQ_PREAM_BITS_SHIFT 9 14396 14397 /* DDR34_F0_PHY_BYTE_LANE_3 :: WR_PREAMBLE_MODE :: DQS [08:05] */ 14398 #define DDR34_F0_PHY_BYTE_LANE_3_WR_PREAMBLE_MODE_DQS_MASK 0x000001e0 14399 #define DDR34_F0_PHY_BYTE_LANE_3_WR_PREAMBLE_MODE_DQS_ALIGN 0 14400 #define DDR34_F0_PHY_BYTE_LANE_3_WR_PREAMBLE_MODE_DQS_BITS 4 14401 #define DDR34_F0_PHY_BYTE_LANE_3_WR_PREAMBLE_MODE_DQS_SHIFT 5 14402 14403 /* DDR34_F0_PHY_BYTE_LANE_3 :: WR_PREAMBLE_MODE :: DQS_POSTAM_BITS [04:03] */ 14404 #define DDR34_F0_PHY_BYTE_LANE_3_WR_PREAMBLE_MODE_DQS_POSTAM_BITS_MASK 0x00000018 14405 #define DDR34_F0_PHY_BYTE_LANE_3_WR_PREAMBLE_MODE_DQS_POSTAM_BITS_ALIGN 0 14406 #define DDR34_F0_PHY_BYTE_LANE_3_WR_PREAMBLE_MODE_DQS_POSTAM_BITS_BITS 2 14407 #define DDR34_F0_PHY_BYTE_LANE_3_WR_PREAMBLE_MODE_DQS_POSTAM_BITS_SHIFT 3 14408 14409 /* DDR34_F0_PHY_BYTE_LANE_3 :: WR_PREAMBLE_MODE :: DQS_PREAM_BITS [02:00] */ 14410 #define DDR34_F0_PHY_BYTE_LANE_3_WR_PREAMBLE_MODE_DQS_PREAM_BITS_MASK 0x00000007 14411 #define DDR34_F0_PHY_BYTE_LANE_3_WR_PREAMBLE_MODE_DQS_PREAM_BITS_ALIGN 0 14412 #define DDR34_F0_PHY_BYTE_LANE_3_WR_PREAMBLE_MODE_DQS_PREAM_BITS_BITS 3 14413 #define DDR34_F0_PHY_BYTE_LANE_3_WR_PREAMBLE_MODE_DQS_PREAM_BITS_SHIFT 0 14414 14415 14416 /**************************************************************************** 14417 * DDR34_F0_PHY_BYTE_LANE_3 :: ODT_CONTROL 14418 */ 14419 /* DDR34_F0_PHY_BYTE_LANE_3 :: ODT_CONTROL :: reserved0 [31:10] */ 14420 #define DDR34_F0_PHY_BYTE_LANE_3_ODT_CONTROL_RESERVED0_MASK 0xfffffc00 14421 #define DDR34_F0_PHY_BYTE_LANE_3_ODT_CONTROL_RESERVED0_ALIGN 0 14422 #define DDR34_F0_PHY_BYTE_LANE_3_ODT_CONTROL_RESERVED0_BITS 22 14423 #define DDR34_F0_PHY_BYTE_LANE_3_ODT_CONTROL_RESERVED0_SHIFT 10 14424 14425 /* DDR34_F0_PHY_BYTE_LANE_3 :: ODT_CONTROL :: ODT_ENABLE [09:09] */ 14426 #define DDR34_F0_PHY_BYTE_LANE_3_ODT_CONTROL_ODT_ENABLE_MASK 0x00000200 14427 #define DDR34_F0_PHY_BYTE_LANE_3_ODT_CONTROL_ODT_ENABLE_ALIGN 0 14428 #define DDR34_F0_PHY_BYTE_LANE_3_ODT_CONTROL_ODT_ENABLE_BITS 1 14429 #define DDR34_F0_PHY_BYTE_LANE_3_ODT_CONTROL_ODT_ENABLE_SHIFT 9 14430 14431 /* DDR34_F0_PHY_BYTE_LANE_3 :: ODT_CONTROL :: ODT_DELAY [08:06] */ 14432 #define DDR34_F0_PHY_BYTE_LANE_3_ODT_CONTROL_ODT_DELAY_MASK 0x000001c0 14433 #define DDR34_F0_PHY_BYTE_LANE_3_ODT_CONTROL_ODT_DELAY_ALIGN 0 14434 #define DDR34_F0_PHY_BYTE_LANE_3_ODT_CONTROL_ODT_DELAY_BITS 3 14435 #define DDR34_F0_PHY_BYTE_LANE_3_ODT_CONTROL_ODT_DELAY_SHIFT 6 14436 14437 /* DDR34_F0_PHY_BYTE_LANE_3 :: ODT_CONTROL :: ODT_POST_LENGTH [05:03] */ 14438 #define DDR34_F0_PHY_BYTE_LANE_3_ODT_CONTROL_ODT_POST_LENGTH_MASK 0x00000038 14439 #define DDR34_F0_PHY_BYTE_LANE_3_ODT_CONTROL_ODT_POST_LENGTH_ALIGN 0 14440 #define DDR34_F0_PHY_BYTE_LANE_3_ODT_CONTROL_ODT_POST_LENGTH_BITS 3 14441 #define DDR34_F0_PHY_BYTE_LANE_3_ODT_CONTROL_ODT_POST_LENGTH_SHIFT 3 14442 14443 /* DDR34_F0_PHY_BYTE_LANE_3 :: ODT_CONTROL :: reserved1 [02:02] */ 14444 #define DDR34_F0_PHY_BYTE_LANE_3_ODT_CONTROL_RESERVED1_MASK 0x00000004 14445 #define DDR34_F0_PHY_BYTE_LANE_3_ODT_CONTROL_RESERVED1_ALIGN 0 14446 #define DDR34_F0_PHY_BYTE_LANE_3_ODT_CONTROL_RESERVED1_BITS 1 14447 #define DDR34_F0_PHY_BYTE_LANE_3_ODT_CONTROL_RESERVED1_SHIFT 2 14448 14449 /* DDR34_F0_PHY_BYTE_LANE_3 :: ODT_CONTROL :: ODT_PRE_LENGTH [01:00] */ 14450 #define DDR34_F0_PHY_BYTE_LANE_3_ODT_CONTROL_ODT_PRE_LENGTH_MASK 0x00000003 14451 #define DDR34_F0_PHY_BYTE_LANE_3_ODT_CONTROL_ODT_PRE_LENGTH_ALIGN 0 14452 #define DDR34_F0_PHY_BYTE_LANE_3_ODT_CONTROL_ODT_PRE_LENGTH_BITS 2 14453 #define DDR34_F0_PHY_BYTE_LANE_3_ODT_CONTROL_ODT_PRE_LENGTH_SHIFT 0 14454 14455 14456 /**************************************************************************** 14457 * DDR34_F0_PHY_BYTE_LANE_3 :: CLOCK_ENABLE 14458 */ 14459 /* DDR34_F0_PHY_BYTE_LANE_3 :: CLOCK_ENABLE :: reserved0 [31:03] */ 14460 #define DDR34_F0_PHY_BYTE_LANE_3_CLOCK_ENABLE_RESERVED0_MASK 0xfffffff8 14461 #define DDR34_F0_PHY_BYTE_LANE_3_CLOCK_ENABLE_RESERVED0_ALIGN 0 14462 #define DDR34_F0_PHY_BYTE_LANE_3_CLOCK_ENABLE_RESERVED0_BITS 29 14463 #define DDR34_F0_PHY_BYTE_LANE_3_CLOCK_ENABLE_RESERVED0_SHIFT 3 14464 14465 /* DDR34_F0_PHY_BYTE_LANE_3 :: CLOCK_ENABLE :: TO_MC_CLOCK [02:02] */ 14466 #define DDR34_F0_PHY_BYTE_LANE_3_CLOCK_ENABLE_TO_MC_CLOCK_MASK 0x00000004 14467 #define DDR34_F0_PHY_BYTE_LANE_3_CLOCK_ENABLE_TO_MC_CLOCK_ALIGN 0 14468 #define DDR34_F0_PHY_BYTE_LANE_3_CLOCK_ENABLE_TO_MC_CLOCK_BITS 1 14469 #define DDR34_F0_PHY_BYTE_LANE_3_CLOCK_ENABLE_TO_MC_CLOCK_SHIFT 2 14470 14471 /* DDR34_F0_PHY_BYTE_LANE_3 :: CLOCK_ENABLE :: FROM_MC_CLOCK [01:01] */ 14472 #define DDR34_F0_PHY_BYTE_LANE_3_CLOCK_ENABLE_FROM_MC_CLOCK_MASK 0x00000002 14473 #define DDR34_F0_PHY_BYTE_LANE_3_CLOCK_ENABLE_FROM_MC_CLOCK_ALIGN 0 14474 #define DDR34_F0_PHY_BYTE_LANE_3_CLOCK_ENABLE_FROM_MC_CLOCK_BITS 1 14475 #define DDR34_F0_PHY_BYTE_LANE_3_CLOCK_ENABLE_FROM_MC_CLOCK_SHIFT 1 14476 14477 /* DDR34_F0_PHY_BYTE_LANE_3 :: CLOCK_ENABLE :: BIT_CLOCK [00:00] */ 14478 #define DDR34_F0_PHY_BYTE_LANE_3_CLOCK_ENABLE_BIT_CLOCK_MASK 0x00000001 14479 #define DDR34_F0_PHY_BYTE_LANE_3_CLOCK_ENABLE_BIT_CLOCK_ALIGN 0 14480 #define DDR34_F0_PHY_BYTE_LANE_3_CLOCK_ENABLE_BIT_CLOCK_BITS 1 14481 #define DDR34_F0_PHY_BYTE_LANE_3_CLOCK_ENABLE_BIT_CLOCK_SHIFT 0 14482 14483 14484 /**************************************************************************** 14485 * DDR34_F0_PHY_BYTE_LANE_3 :: CLOCK_IDLE 14486 */ 14487 /* DDR34_F0_PHY_BYTE_LANE_3 :: CLOCK_IDLE :: reserved0 [31:03] */ 14488 #define DDR34_F0_PHY_BYTE_LANE_3_CLOCK_IDLE_RESERVED0_MASK 0xfffffff8 14489 #define DDR34_F0_PHY_BYTE_LANE_3_CLOCK_IDLE_RESERVED0_ALIGN 0 14490 #define DDR34_F0_PHY_BYTE_LANE_3_CLOCK_IDLE_RESERVED0_BITS 29 14491 #define DDR34_F0_PHY_BYTE_LANE_3_CLOCK_IDLE_RESERVED0_SHIFT 3 14492 14493 /* DDR34_F0_PHY_BYTE_LANE_3 :: CLOCK_IDLE :: TO_MC_CLOCK [02:02] */ 14494 #define DDR34_F0_PHY_BYTE_LANE_3_CLOCK_IDLE_TO_MC_CLOCK_MASK 0x00000004 14495 #define DDR34_F0_PHY_BYTE_LANE_3_CLOCK_IDLE_TO_MC_CLOCK_ALIGN 0 14496 #define DDR34_F0_PHY_BYTE_LANE_3_CLOCK_IDLE_TO_MC_CLOCK_BITS 1 14497 #define DDR34_F0_PHY_BYTE_LANE_3_CLOCK_IDLE_TO_MC_CLOCK_SHIFT 2 14498 14499 /* DDR34_F0_PHY_BYTE_LANE_3 :: CLOCK_IDLE :: FROM_MC_CLOCK [01:01] */ 14500 #define DDR34_F0_PHY_BYTE_LANE_3_CLOCK_IDLE_FROM_MC_CLOCK_MASK 0x00000002 14501 #define DDR34_F0_PHY_BYTE_LANE_3_CLOCK_IDLE_FROM_MC_CLOCK_ALIGN 0 14502 #define DDR34_F0_PHY_BYTE_LANE_3_CLOCK_IDLE_FROM_MC_CLOCK_BITS 1 14503 #define DDR34_F0_PHY_BYTE_LANE_3_CLOCK_IDLE_FROM_MC_CLOCK_SHIFT 1 14504 14505 /* DDR34_F0_PHY_BYTE_LANE_3 :: CLOCK_IDLE :: BIT_CLOCK [00:00] */ 14506 #define DDR34_F0_PHY_BYTE_LANE_3_CLOCK_IDLE_BIT_CLOCK_MASK 0x00000001 14507 #define DDR34_F0_PHY_BYTE_LANE_3_CLOCK_IDLE_BIT_CLOCK_ALIGN 0 14508 #define DDR34_F0_PHY_BYTE_LANE_3_CLOCK_IDLE_BIT_CLOCK_BITS 1 14509 #define DDR34_F0_PHY_BYTE_LANE_3_CLOCK_IDLE_BIT_CLOCK_SHIFT 0 14510 14511 14512 /**************************************************************************** 14513 * DDR34_F0_PHY_BYTE_LANE_3 :: BL_SPARE_REG 14514 */ 14515 /* DDR34_F0_PHY_BYTE_LANE_3 :: BL_SPARE_REG :: reserved_for_eco0 [31:00] */ 14516 #define DDR34_F0_PHY_BYTE_LANE_3_BL_SPARE_REG_RESERVED_FOR_ECO0_MASK 0xffffffff 14517 #define DDR34_F0_PHY_BYTE_LANE_3_BL_SPARE_REG_RESERVED_FOR_ECO0_ALIGN 0 14518 #define DDR34_F0_PHY_BYTE_LANE_3_BL_SPARE_REG_RESERVED_FOR_ECO0_BITS 32 14519 #define DDR34_F0_PHY_BYTE_LANE_3_BL_SPARE_REG_RESERVED_FOR_ECO0_SHIFT 0 14520 14521 14522 /**************************************************************************** 14523 * Datatype Definitions. 14524 */ 14525 #endif /* #ifndef DDR34_F0_PHY_H__ */ 14526 14527 /* End of File */ 14528