phy_and28_e0.h (1046091B)
1 /* 2 * 3 * 4 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 5 * 6 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 7 * 8 * THIS SOFTWARE MAY ONLY BE USED SUBJECT TO AN EXECUTED SOFTWARE LICENSE 9 * AGREEMENT BETWEEN THE USER AND BROADCOM. YOU HAVE NO RIGHT TO USE OR 10 * EXPLOIT THIS MATERIAL EXCEPT SUBJECT TO THE TERMS OF SUCH AN AGREEMENT. 11 * 12 * $brcm_Workfile: $ 13 * $brcm_Revision: $ 14 * $brcm_Date: $ 15 * 16 * Module Description: 17 * DO NOT EDIT THIS FILE DIRECTLY 18 * 19 * This module was generated magically with RDB from a source description 20 * file. You must edit the source file for changes to be made to this file. 21 * 22 * 23 * Date: Generated on Fri Jan 4 14:25:17 2013 24 * MD5 Checksum 6d4da9060fffdb8b37e48b100cf7a630 25 * 26 * Compiled with: RDB Utility combo_header.pl 27 * RDB Parser 3.0 28 * unknown unknown 29 * Perl Interpreter 5.008008 30 * Operating System linux 31 * 32 * Spec Versions: DDR34_PHY_ADDR_CTL 04 33 * DDR34_PHY_BYTE_LANE 04 34 * 35 * RDB Files: /projects/DDR34_2/E0/work/ebleich/phy_7145_tahiti/design/ddr34_phy/ddr_lp_phy_32_fc_28hpm_h/rdb/ddr34_phy_top_standalone.rdb 36 * /projects/DDR34_2/E0/work/ebleich/phy_7145_tahiti/design/ddr34_phy/ddr_lp_phy_32_fc_28hpm_h/rdb/ddr34_phy_top_blockdef.rdb 37 * /projects/DDR34_2/E0/work/ebleich/phy_7145_tahiti/design/ddr34_phy/ddr_lp_phy_32_fc_28hpm_h/rdb/ddr34_phy_addr_ctl.rdb 38 * /projects/DDR34_2/E0/work/ebleich/phy_7145_tahiti/design/ddr34_phy/ddr_lp_phy_32_fc_28hpm_h/rdb/ddr34_phy_regtypes.rdb 39 * /projects/DDR34_2/E0/work/ebleich/phy_7145_tahiti/design/ddr34_phy/ddr_lp_phy_32_fc_28hpm_h/rdb/ddr34_phy_byte_lane.rdb 40 * /projects/DDR34_2/E0/work/ebleich/phy_7145_tahiti/design/ddr34_phy/ddr_lp_phy_32_fc_28hpm_h/rdb/ddr34_phy_regtypes.rdb 41 * /projects/DDR34_2/E0/work/ebleich/phy_7145_tahiti/design/ddr34_phy/ddr_lp_phy_32_fc_28hpm_h/rdb/ddr34_phy_byte_lane_regtypes.rdb 42 * 43 * Revision History: 44 * 45 * $brcm_Log: $ 46 */ 47 48 #ifndef DDR34_E0_PHY_H__ 49 #define DDR34_E0_PHY_H__ 50 51 /** 52 * m = memory, c = core, r = register, f = field, d = data. 53 */ 54 #if !defined(GET_FIELD) && !defined(SET_FIELD) 55 #define BRCM_ALIGN(c,r,f) c##_##r##_##f##_ALIGN 56 #define BRCM_BITS(c,r,f) c##_##r##_##f##_BITS 57 #define BRCM_MASK(c,r,f) c##_##r##_##f##_MASK 58 #define BRCM_SHIFT(c,r,f) c##_##r##_##f##_SHIFT 59 60 #define GET_FIELD(m,c,r,f) \ 61 ((((m) & BRCM_MASK(c,r,f)) >> BRCM_SHIFT(c,r,f)) << BRCM_ALIGN(c,r,f)) 62 63 #define SET_FIELD(m,c,r,f,d) \ 64 ((m) = (((m) & ~BRCM_MASK(c,r,f)) | ((((d) >> BRCM_ALIGN(c,r,f)) << \ 65 BRCM_SHIFT(c,r,f)) & BRCM_MASK(c,r,f))) \ 66 ) 67 68 #define SET_TYPE_FIELD(m,c,r,f,d) SET_FIELD(m,c,r,f,c##_##d) 69 #define SET_NAME_FIELD(m,c,r,f,d) SET_FIELD(m,c,r,f,c##_##r##_##f##_##d) 70 #define SET_VALUE_FIELD(m,c,r,f,d) SET_FIELD(m,c,r,f,d) 71 72 #endif /* GET & SET */ 73 74 /*************************************************************************** 75 *DDR34_E0_PHY_CONTROL_REGS - DDR34 CORE DDR34 Address/Comand control registers 76 */ 77 #define DDR34_E0_PHY_CONTROL_REGS_REVISION 0x00000000 /* Address & Control revision register */ 78 #define DDR34_E0_PHY_CONTROL_REGS_PLL_STATUS 0x00000004 /* PHY PLL status register */ 79 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONFIG 0x00000008 /* PHY PLL configuration register */ 80 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONTROL1 0x0000000c /* PHY PLL control register */ 81 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONTROL2 0x00000010 /* PHY PLL control register */ 82 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONTROL3 0x00000014 /* PHY PLL control register */ 83 #define DDR34_E0_PHY_CONTROL_REGS_PLL_DIVIDERS 0x00000018 /* PHY PLL integer divider register */ 84 #define DDR34_E0_PHY_CONTROL_REGS_PLL_FRAC_DIVIDER 0x0000001c /* PHY PLL fractional divider register */ 85 #define DDR34_E0_PHY_CONTROL_REGS_PLL_SS_CONTROL 0x00000020 /* PHY PLL spread spectrum control register */ 86 #define DDR34_E0_PHY_CONTROL_REGS_PLL_SS_LIMIT 0x00000024 /* PHY PLL spread spectrum limit register */ 87 #define DDR34_E0_PHY_CONTROL_REGS_AUX_CONTROL 0x00000028 /* Aux Control register */ 88 #define DDR34_E0_PHY_CONTROL_REGS_IDLE_PAD_CONTROL 0x0000002c /* Idle mode pad control register */ 89 #define DDR34_E0_PHY_CONTROL_REGS_IDLE_PAD_ENABLE0 0x00000030 /* Idle mode pad enable register */ 90 #define DDR34_E0_PHY_CONTROL_REGS_IDLE_PAD_ENABLE1 0x00000034 /* Idle mode pad enable register */ 91 #define DDR34_E0_PHY_CONTROL_REGS_DRIVE_PAD_CTL 0x00000038 /* PVT Compensation control register */ 92 #define DDR34_E0_PHY_CONTROL_REGS_STATIC_PAD_CTL 0x0000003c /* pad rx and tx characteristics control register */ 93 #define DDR34_E0_PHY_CONTROL_REGS_DRAM_CONFIG 0x00000040 /* DRAM configuration register */ 94 #define DDR34_E0_PHY_CONTROL_REGS_DRAM_TIMING1 0x00000044 /* DRAM timing register #1 */ 95 #define DDR34_E0_PHY_CONTROL_REGS_DRAM_TIMING2 0x00000048 /* DRAM timing register #2 */ 96 #define DDR34_E0_PHY_CONTROL_REGS_DRAM_TIMING3 0x0000004c /* DRAM timing register #3 */ 97 #define DDR34_E0_PHY_CONTROL_REGS_DRAM_TIMING4 0x00000050 /* DRAM timing register #4 */ 98 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CALIBRATE 0x00000060 /* PHY VDL calibration control register */ 99 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CALIB_STATUS1 0x00000064 /* PHY VDL calibration status register #1 */ 100 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CALIB_STATUS2 0x00000068 /* PHY VDL calibration status register #2 */ 101 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_CONTROL 0x0000006c /* PHY VDL delay monitoring control register */ 102 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_REF 0x00000070 /* PHY VDL delay monitoring reference register */ 103 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_STATUS 0x00000074 /* PHY VDL delay monitoring status register */ 104 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDE 0x00000078 /* PHY VDL delay monitoring override register */ 105 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_OUT_CONTROL 0x0000007c /* PHY VDL delay monitoring output control register */ 106 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS 0x00000080 /* PHY VDL delay monitoring output status register */ 107 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_CLEAR 0x00000084 /* PHY VDL delay monitoring output status clear register */ 108 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD00 0x00000090 /* DDR interface signal AD[00] VDL control register */ 109 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD01 0x00000094 /* DDR interface signal AD[01] VDL control register */ 110 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD02 0x00000098 /* DDR interface signal AD[02] VDL control register */ 111 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD03 0x0000009c /* DDR interface signal AD[03] VDL control register */ 112 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD04 0x000000a0 /* DDR interface signal AD[04] VDL control register */ 113 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD05 0x000000a4 /* DDR interface signal AD[05] VDL control register */ 114 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD06 0x000000a8 /* DDR interface signal AD[06] VDL control register */ 115 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD07 0x000000ac /* DDR interface signal AD[07] VDL control register */ 116 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD08 0x000000b0 /* DDR interface signal AD[08] VDL control register */ 117 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD09 0x000000b4 /* DDR interface signal AD[09] VDL control register */ 118 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD10 0x000000b8 /* DDR interface signal AD[10] VDL control register */ 119 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD11 0x000000bc /* DDR interface signal AD[11] VDL control register */ 120 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD12 0x000000c0 /* DDR interface signal AD[12] VDL control register */ 121 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD13 0x000000c4 /* DDR interface signal AD[13] VDL control register */ 122 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD14 0x000000c8 /* DDR interface signal AD[14] VDL control register */ 123 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD15 0x000000cc /* DDR interface signal AD[15] VDL control register */ 124 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_BA0 0x000000d0 /* DDR interface signal BA[0] VDL control register */ 125 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_BA1 0x000000d4 /* DDR interface signal BA[1] VDL control register */ 126 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_BA2 0x000000d8 /* DDR interface signal BA[2] VDL control register */ 127 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AUX0 0x000000dc /* DDR interface signal AUX[0] VDL control register */ 128 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AUX1 0x000000e0 /* DDR interface signal AUX[1] VDL control register */ 129 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AUX2 0x000000e4 /* DDR interface signal AUX[2] VDL control register */ 130 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_CS0 0x000000e8 /* DDR interface signal CS0 VDL control register */ 131 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_CS1 0x000000ec /* DDR interface signal CS1 VDL control register */ 132 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_PAR 0x000000f0 /* DDR interface signal PAR VDL control register */ 133 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_RAS_N 0x000000f4 /* DDR interface signal RAS_N VDL control register */ 134 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_CAS_N 0x000000f8 /* DDR interface signal CAS_N VDL control register */ 135 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_CKE 0x000000fc /* DDR interface signal CKE0 VDL control register */ 136 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_RST_N 0x00000100 /* DDR interface signal RST_N VDL control register */ 137 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_ODT 0x00000104 /* DDR interface signal ODT0 VDL control register */ 138 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_WE_N 0x00000108 /* DDR interface signal WE_N VDL control register */ 139 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_P 0x0000010c /* DDR interface signal DDR_CK-P VDL control register */ 140 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_N 0x00000110 /* DDR interface signal DDR_CK-N VDL control register */ 141 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CLK_CONTROL 0x00000114 /* DDR interface signal Write Leveling CLK VDL control register */ 142 #define DDR34_E0_PHY_CONTROL_REGS_VDL_LDE_CONTROL 0x00000118 /* DDR interface signal Write Leveling Capture Enable VDL control register */ 143 #define DDR34_E0_PHY_CONTROL_REGS_REFRESH 0x00000130 /* Refresh engine controller */ 144 #define DDR34_E0_PHY_CONTROL_REGS_UPDATE_VDL 0x00000134 /* Update VDL control register */ 145 #define DDR34_E0_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1 0x00000138 /* Update VDL snoop control register #1 */ 146 #define DDR34_E0_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2 0x0000013c /* Update VDL snoop control register #2 */ 147 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG1 0x00000140 /* DRAM Command Register #1 */ 148 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_AUX_REG1 0x00000144 /* DRAM AUX_N Command Register #1 */ 149 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG2 0x00000148 /* DRAM Command Register #2 */ 150 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_AUX_REG2 0x0000014c /* DRAM AUX_N Command Register #2 */ 151 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG3 0x00000150 /* DRAM Command Register #3 */ 152 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_AUX_REG3 0x00000154 /* DRAM AUX_N Command Register #3 */ 153 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG4 0x00000158 /* DRAM Command Register #4 */ 154 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_AUX_REG4 0x0000015c /* DRAM AUX_N Command Register #4 */ 155 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG_TIMER 0x00000160 /* DRAM Command Timer Register */ 156 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG0 0x00000164 /* DDR3/DDR4/GDDR5 Mode Register 0 and LPDDR Mode Register 1 */ 157 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG1 0x00000168 /* DDR3/DDR4/GDDR5 Mode Register 1 and LPDDR Mode Register 2 */ 158 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG2 0x0000016c /* DDR3/DDR4/GDDR5 Mode Register 2 and LPDDR Mode Register 3 */ 159 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG3 0x00000170 /* DDR3/DDR4/GDDR5 Mode Register 3 and LPDDR Mode Register 9 */ 160 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG4 0x00000174 /* DDR4/GDDR5 Mode Register 4 and LPDDR Mode Register 10 */ 161 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG5 0x00000178 /* DDR4/GDDR5 Mode Register 5 and LPDDR Mode Register 16 */ 162 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG6 0x0000017c /* DDR4/GDDR5 Mode Register 6 and LPDDR Mode Register 17 */ 163 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG7 0x00000180 /* DDR4/GDDR5 Mode Register 7 and LPDDR Mode Register 41 */ 164 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG8 0x00000184 /* GDDR5 Mode Register 8 and LPDDR Mode Register 42 */ 165 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG15 0x00000188 /* GDDR5 Mode Register 15 and LPDDR Mode Register 48 */ 166 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG63 0x0000018c /* LPDDR Mode Register 63 */ 167 #define DDR34_E0_PHY_CONTROL_REGS_ALERT_CLEAR 0x00000190 /* DDR4 Alert status clear register */ 168 #define DDR34_E0_PHY_CONTROL_REGS_ALERT_STATUS 0x00000194 /* DDR4 Alert status register */ 169 #define DDR34_E0_PHY_CONTROL_REGS_CA_PARITY 0x00000198 /* DDR4 CA parity control register */ 170 #define DDR34_E0_PHY_CONTROL_REGS_CA_PLAYBACK_CONTROL 0x0000019c /* GDDR5 CA playback control register */ 171 #define DDR34_E0_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS0 0x000001a0 /* LPDDR3 and GDDR5 CA playback status register0 (for BL0 and BL1) */ 172 #define DDR34_E0_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS1 0x000001a4 /* LPDDR3 and GDDR5 CA playback status register1 (for BL2 and BL3) */ 173 #define DDR34_E0_PHY_CONTROL_REGS_WRITE_LEVELING_CONTROL 0x000001ac /* Write leveling control register */ 174 #define DDR34_E0_PHY_CONTROL_REGS_WRITE_LEVELING_STATUS 0x000001b0 /* Write leveling status register */ 175 #define DDR34_E0_PHY_CONTROL_REGS_READ_ENABLE_CONTROL 0x000001b4 /* Read enable test cycle control register */ 176 #define DDR34_E0_PHY_CONTROL_REGS_READ_ENABLE_STATUS 0x000001b8 /* Read enable test cycle status register */ 177 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_LFSR_SEED 0x000001c0 /* Traffic generator seed register */ 178 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_ADDRESS1 0x000001c4 /* Traffic generator address register #1 */ 179 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_ADDRESS2 0x000001c8 /* Traffic generator address register #2 */ 180 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL 0x000001cc /* Traffic generator control register */ 181 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_DATA_CONTROL 0x000001d0 /* Traffic generator data control register */ 182 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_MASK 0x000001d4 /* Traffic generator DQ mask register */ 183 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_ECC_DQ_MASK 0x000001d8 /* Traffic generator ECC DQ mask register */ 184 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_STATUS 0x000001dc /* Traffic generator status register */ 185 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUS 0x000001e0 /* Traffic generator DQ status register */ 186 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_ECC_STATUS 0x000001e4 /* Traffic generator ECC DQ status register */ 187 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_ERR_CNT_CONTROL 0x000001e8 /* Traffic generator error count control register */ 188 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_ERR_CNT_STATUS 0x000001ec /* Traffic generator error count status register */ 189 #define DDR34_E0_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL 0x000001f0 /* Virtual VTT Control and Status register */ 190 #define DDR34_E0_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS 0x000001f4 /* Virtual VTT Control and Status register */ 191 #define DDR34_E0_PHY_CONTROL_REGS_VIRTUAL_VTT_CONNECTIONS 0x000001f8 /* Virtual VTT Connections register */ 192 #define DDR34_E0_PHY_CONTROL_REGS_VIRTUAL_VTT_OVERRIDE 0x000001fc /* Virtual VTT Override register */ 193 #define DDR34_E0_PHY_CONTROL_REGS_VREF_DAC_CONTROL 0x00000200 /* VREF DAC Control register */ 194 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_CNTRL 0x00000204 /* PhyBist Control Register */ 195 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_SEED 0x00000208 /* PhyBist Seed Register */ 196 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_STATUS 0x0000020c /* PhyBist General Status Register */ 197 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_CTL_STATUS 0x00000210 /* PhyBist Per-Bit Control Pad Status Register */ 198 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_BL0_STATUS 0x00000214 /* PhyBist Byte Lane #0 Status Register */ 199 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_BL1_STATUS 0x00000218 /* PhyBist Byte Lane #1 Status Register */ 200 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_BL2_STATUS 0x0000021c /* PhyBist Byte Lane #2 Status Register */ 201 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_BL3_STATUS 0x00000220 /* PhyBist Byte Lane #3 Status Register */ 202 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_BL4_STATUS 0x00000224 /* PhyBist Byte Lane #4 (ECC) Status Register */ 203 #define DDR34_E0_PHY_CONTROL_REGS_STANDBY_CONTROL 0x00000230 /* Standby Control register */ 204 #define DDR34_E0_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE 0x00000234 /* Freeze-on-error enable register */ 205 #define DDR34_E0_PHY_CONTROL_REGS_DEBUG_MUX_CONTROL 0x00000238 /* Debug Mux Control register */ 206 #define DDR34_E0_PHY_CONTROL_REGS_DFI_CNTRL 0x0000023c /* DFI Interface Ownership Control register */ 207 #define DDR34_E0_PHY_CONTROL_REGS_WRITE_ODT_CNTRL 0x00000240 /* Write ODT Control register */ 208 #define DDR34_E0_PHY_CONTROL_REGS_ABI_PAR_CNTRL 0x00000244 /* ABI and PAR Control register */ 209 #define DDR34_E0_PHY_CONTROL_REGS_ZQ_CAL 0x00000248 /* ZQ Calibration Control register */ 210 #define DDR34_E0_PHY_CONTROL_REGS_AC_SPARE_REG 0x0000011c /* Address and Control Spare register */ 211 212 /*************************************************************************** 213 *DDR34_E0_PHY_BYTE_LANE_0 - DDR34 CORE DDR34 Byte Lane #0 control registers 214 */ 215 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_P 0x00000400 /* Write channel DQS-P VDL control register */ 216 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_N 0x00000404 /* Write channel DQS-N VDL control register */ 217 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0 0x00000408 /* Write channel DQ0 VDL control register */ 218 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1 0x0000040c /* Write channel DQ1 VDL control register */ 219 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2 0x00000410 /* Write channel DQ2 VDL control register */ 220 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3 0x00000414 /* Write channel DQ3 VDL control register */ 221 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4 0x00000418 /* Write channel DQ4 VDL control register */ 222 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5 0x0000041c /* Write channel DQ5 VDL control register */ 223 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6 0x00000420 /* Write channel DQ6 VDL control register */ 224 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7 0x00000424 /* Write channel DQ7 VDL control register */ 225 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DM 0x00000428 /* Write channel DM VDL control register */ 226 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_EDC 0x0000042c /* Write channel EDC VDL control register */ 227 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSP 0x00000430 /* Read channel DQSP VDL control register */ 228 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSN 0x00000434 /* Read channel DQSP VDL control register */ 229 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0P 0x00000438 /* Read channel DQ0-P VDL control register */ 230 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0N 0x0000043c /* Read channel DQ0-N VDL control register */ 231 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1P 0x00000440 /* Read channel DQ1-P VDL control register */ 232 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1N 0x00000444 /* Read channel DQ1-N VDL control register */ 233 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2P 0x00000448 /* Read channel DQ2-P VDL control register */ 234 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2N 0x0000044c /* Read channel DQ2-N VDL control register */ 235 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3P 0x00000450 /* Read channel DQ3-P VDL control register */ 236 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3N 0x00000454 /* Read channel DQ3-N VDL control register */ 237 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4P 0x00000458 /* Read channel DQ4-P VDL control register */ 238 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4N 0x0000045c /* Read channel DQ4-N VDL control register */ 239 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5P 0x00000460 /* Read channel DQ5-P VDL control register */ 240 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5N 0x00000464 /* Read channel DQ5-N VDL control register */ 241 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6P 0x00000468 /* Read channel DQ6-P VDL control register */ 242 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6N 0x0000046c /* Read channel DQ6-N VDL control register */ 243 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7P 0x00000470 /* Read channel DQ7-P VDL control register */ 244 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7N 0x00000474 /* Read channel DQ7-N VDL control register */ 245 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMP 0x00000478 /* Read channel DM-P VDL control register */ 246 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMN 0x0000047c /* Read channel DM-N VDL control register */ 247 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCP 0x00000480 /* Read channel EDC-P VDL control register */ 248 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCN 0x00000484 /* Read channel EDC-N VDL control register */ 249 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0 0x00000488 /* Read channel CS_N[0] read enable VDL control register */ 250 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1 0x0000048c /* Read channel CS_N[1] read enable VDL control register */ 251 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CLK_CONTROL 0x00000490 /* DDR interface signal Write Leveling CLK VDL control register */ 252 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_LDE_CONTROL 0x00000494 /* DDR interface signal Write Leveling Capture Enable VDL control register */ 253 #define DDR34_E0_PHY_BYTE_LANE_0_RD_EN_DLY_CYC 0x000004a0 /* Read enable bit-clock cycle delay control register */ 254 #define DDR34_E0_PHY_BYTE_LANE_0_WR_CHAN_DLY_CYC 0x000004a4 /* Write leveling bit-clock cycle delay control register */ 255 #define DDR34_E0_PHY_BYTE_LANE_0_READ_CONTROL 0x000004b0 /* Read channel datapath control register */ 256 #define DDR34_E0_PHY_BYTE_LANE_0_READ_FIFO_ADDR 0x000004b4 /* Read fifo addresss pointer register */ 257 #define DDR34_E0_PHY_BYTE_LANE_0_READ_FIFO_DATA 0x000004b8 /* Read fifo data register */ 258 #define DDR34_E0_PHY_BYTE_LANE_0_READ_FIFO_DM_DBI 0x000004bc /* Read fifo dm/dbi register */ 259 #define DDR34_E0_PHY_BYTE_LANE_0_READ_FIFO_STATUS 0x000004c0 /* Read fifo status register */ 260 #define DDR34_E0_PHY_BYTE_LANE_0_READ_FIFO_CLEAR 0x000004c4 /* Read fifo status clear register */ 261 #define DDR34_E0_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL 0x000004c8 /* Idle mode SSTL pad control register */ 262 #define DDR34_E0_PHY_BYTE_LANE_0_DRIVE_PAD_CTL 0x000004cc /* SSTL pad drive characteristics control register */ 263 #define DDR34_E0_PHY_BYTE_LANE_0_RD_EN_DRIVE_PAD_CTL 0x000004d0 /* SSTL read enable pad drive characteristics control register */ 264 #define DDR34_E0_PHY_BYTE_LANE_0_STATIC_PAD_CTL 0x000004d4 /* pad rx and tx characteristics control register */ 265 #define DDR34_E0_PHY_BYTE_LANE_0_WR_PREAMBLE_MODE 0x000004d8 /* Write cycle preamble control register */ 266 #define DDR34_E0_PHY_BYTE_LANE_0_ODT_CONTROL 0x000004e0 /* Read channel ODT control register */ 267 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_DPD_CONTROL 0x000004f0 /* GDDR5M EDC digital phase detector control register */ 268 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_DPD_STATUS 0x000004f4 /* GDDR5M EDC digital phase detector status register */ 269 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_DPD_OUT_CONTROL 0x000004f8 /* GDDR5M EDC digital phase detector output signal control register */ 270 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_DPD_OUT_STATUS 0x000004fc /* GDDR5M EDC digital phase detector output signal status register */ 271 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_DPD_OUT_STATUS_CLEAR 0x00000500 /* GDDR5M EDC digital phase detector output signal status clear register */ 272 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_CRC_CONTROL 0x00000504 /* GDDR5M EDC signal path CRC control register */ 273 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_CRC_STATUS 0x00000508 /* GDDR5M EDC signal path CRC status register */ 274 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_CRC_COUNT 0x0000050c /* GDDR5M EDC signal path CRC counter register */ 275 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_CRC_STATUS_CLEAR 0x00000510 /* GDDR5M EDC signal path CRC counter register */ 276 #define DDR34_E0_PHY_BYTE_LANE_0_BL_SPARE_REG 0x00000514 /* Byte-Lane Spare register */ 277 278 /*************************************************************************** 279 *DDR34_E0_PHY_BYTE_LANE_1 - DDR34 CORE DDR34 Byte Lane #1 control registers 280 */ 281 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_P 0x00000600 /* Write channel DQS-P VDL control register */ 282 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_N 0x00000604 /* Write channel DQS-N VDL control register */ 283 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0 0x00000608 /* Write channel DQ0 VDL control register */ 284 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1 0x0000060c /* Write channel DQ1 VDL control register */ 285 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2 0x00000610 /* Write channel DQ2 VDL control register */ 286 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3 0x00000614 /* Write channel DQ3 VDL control register */ 287 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4 0x00000618 /* Write channel DQ4 VDL control register */ 288 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5 0x0000061c /* Write channel DQ5 VDL control register */ 289 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6 0x00000620 /* Write channel DQ6 VDL control register */ 290 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7 0x00000624 /* Write channel DQ7 VDL control register */ 291 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DM 0x00000628 /* Write channel DM VDL control register */ 292 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_EDC 0x0000062c /* Write channel EDC VDL control register */ 293 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSP 0x00000630 /* Read channel DQSP VDL control register */ 294 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSN 0x00000634 /* Read channel DQSP VDL control register */ 295 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0P 0x00000638 /* Read channel DQ0-P VDL control register */ 296 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0N 0x0000063c /* Read channel DQ0-N VDL control register */ 297 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1P 0x00000640 /* Read channel DQ1-P VDL control register */ 298 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1N 0x00000644 /* Read channel DQ1-N VDL control register */ 299 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2P 0x00000648 /* Read channel DQ2-P VDL control register */ 300 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2N 0x0000064c /* Read channel DQ2-N VDL control register */ 301 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3P 0x00000650 /* Read channel DQ3-P VDL control register */ 302 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3N 0x00000654 /* Read channel DQ3-N VDL control register */ 303 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4P 0x00000658 /* Read channel DQ4-P VDL control register */ 304 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4N 0x0000065c /* Read channel DQ4-N VDL control register */ 305 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5P 0x00000660 /* Read channel DQ5-P VDL control register */ 306 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5N 0x00000664 /* Read channel DQ5-N VDL control register */ 307 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6P 0x00000668 /* Read channel DQ6-P VDL control register */ 308 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6N 0x0000066c /* Read channel DQ6-N VDL control register */ 309 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7P 0x00000670 /* Read channel DQ7-P VDL control register */ 310 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7N 0x00000674 /* Read channel DQ7-N VDL control register */ 311 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMP 0x00000678 /* Read channel DM-P VDL control register */ 312 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMN 0x0000067c /* Read channel DM-N VDL control register */ 313 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCP 0x00000680 /* Read channel EDC-P VDL control register */ 314 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCN 0x00000684 /* Read channel EDC-N VDL control register */ 315 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0 0x00000688 /* Read channel CS_N[0] read enable VDL control register */ 316 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1 0x0000068c /* Read channel CS_N[1] read enable VDL control register */ 317 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CLK_CONTROL 0x00000690 /* DDR interface signal Write Leveling CLK VDL control register */ 318 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_LDE_CONTROL 0x00000694 /* DDR interface signal Write Leveling Capture Enable VDL control register */ 319 #define DDR34_E0_PHY_BYTE_LANE_1_RD_EN_DLY_CYC 0x000006a0 /* Read enable bit-clock cycle delay control register */ 320 #define DDR34_E0_PHY_BYTE_LANE_1_WR_CHAN_DLY_CYC 0x000006a4 /* Write leveling bit-clock cycle delay control register */ 321 #define DDR34_E0_PHY_BYTE_LANE_1_READ_CONTROL 0x000006b0 /* Read channel datapath control register */ 322 #define DDR34_E0_PHY_BYTE_LANE_1_READ_FIFO_ADDR 0x000006b4 /* Read fifo addresss pointer register */ 323 #define DDR34_E0_PHY_BYTE_LANE_1_READ_FIFO_DATA 0x000006b8 /* Read fifo data register */ 324 #define DDR34_E0_PHY_BYTE_LANE_1_READ_FIFO_DM_DBI 0x000006bc /* Read fifo dm/dbi register */ 325 #define DDR34_E0_PHY_BYTE_LANE_1_READ_FIFO_STATUS 0x000006c0 /* Read fifo status register */ 326 #define DDR34_E0_PHY_BYTE_LANE_1_READ_FIFO_CLEAR 0x000006c4 /* Read fifo status clear register */ 327 #define DDR34_E0_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL 0x000006c8 /* Idle mode SSTL pad control register */ 328 #define DDR34_E0_PHY_BYTE_LANE_1_DRIVE_PAD_CTL 0x000006cc /* SSTL pad drive characteristics control register */ 329 #define DDR34_E0_PHY_BYTE_LANE_1_RD_EN_DRIVE_PAD_CTL 0x000006d0 /* SSTL read enable pad drive characteristics control register */ 330 #define DDR34_E0_PHY_BYTE_LANE_1_STATIC_PAD_CTL 0x000006d4 /* pad rx and tx characteristics control register */ 331 #define DDR34_E0_PHY_BYTE_LANE_1_WR_PREAMBLE_MODE 0x000006d8 /* Write cycle preamble control register */ 332 #define DDR34_E0_PHY_BYTE_LANE_1_ODT_CONTROL 0x000006e0 /* Read channel ODT control register */ 333 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_DPD_CONTROL 0x000006f0 /* GDDR5M EDC digital phase detector control register */ 334 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_DPD_STATUS 0x000006f4 /* GDDR5M EDC digital phase detector status register */ 335 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_DPD_OUT_CONTROL 0x000006f8 /* GDDR5M EDC digital phase detector output signal control register */ 336 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_DPD_OUT_STATUS 0x000006fc /* GDDR5M EDC digital phase detector output signal status register */ 337 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_DPD_OUT_STATUS_CLEAR 0x00000700 /* GDDR5M EDC digital phase detector output signal status clear register */ 338 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_CRC_CONTROL 0x00000704 /* GDDR5M EDC signal path CRC control register */ 339 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_CRC_STATUS 0x00000708 /* GDDR5M EDC signal path CRC status register */ 340 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_CRC_COUNT 0x0000070c /* GDDR5M EDC signal path CRC counter register */ 341 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_CRC_STATUS_CLEAR 0x00000710 /* GDDR5M EDC signal path CRC counter register */ 342 #define DDR34_E0_PHY_BYTE_LANE_1_BL_SPARE_REG 0x00000714 /* Byte-Lane Spare register */ 343 344 /*************************************************************************** 345 *DDR34_E0_PHY_BYTE_LANE_2 - DDR34 CORE DDR34 Byte Lane #2 control registers 346 */ 347 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_P 0x00000800 /* Write channel DQS-P VDL control register */ 348 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_N 0x00000804 /* Write channel DQS-N VDL control register */ 349 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ0 0x00000808 /* Write channel DQ0 VDL control register */ 350 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ1 0x0000080c /* Write channel DQ1 VDL control register */ 351 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ2 0x00000810 /* Write channel DQ2 VDL control register */ 352 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ3 0x00000814 /* Write channel DQ3 VDL control register */ 353 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ4 0x00000818 /* Write channel DQ4 VDL control register */ 354 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ5 0x0000081c /* Write channel DQ5 VDL control register */ 355 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ6 0x00000820 /* Write channel DQ6 VDL control register */ 356 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ7 0x00000824 /* Write channel DQ7 VDL control register */ 357 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DM 0x00000828 /* Write channel DM VDL control register */ 358 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_EDC 0x0000082c /* Write channel EDC VDL control register */ 359 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSP 0x00000830 /* Read channel DQSP VDL control register */ 360 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSN 0x00000834 /* Read channel DQSP VDL control register */ 361 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0P 0x00000838 /* Read channel DQ0-P VDL control register */ 362 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0N 0x0000083c /* Read channel DQ0-N VDL control register */ 363 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1P 0x00000840 /* Read channel DQ1-P VDL control register */ 364 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1N 0x00000844 /* Read channel DQ1-N VDL control register */ 365 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2P 0x00000848 /* Read channel DQ2-P VDL control register */ 366 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2N 0x0000084c /* Read channel DQ2-N VDL control register */ 367 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3P 0x00000850 /* Read channel DQ3-P VDL control register */ 368 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3N 0x00000854 /* Read channel DQ3-N VDL control register */ 369 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4P 0x00000858 /* Read channel DQ4-P VDL control register */ 370 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4N 0x0000085c /* Read channel DQ4-N VDL control register */ 371 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5P 0x00000860 /* Read channel DQ5-P VDL control register */ 372 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5N 0x00000864 /* Read channel DQ5-N VDL control register */ 373 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6P 0x00000868 /* Read channel DQ6-P VDL control register */ 374 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6N 0x0000086c /* Read channel DQ6-N VDL control register */ 375 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7P 0x00000870 /* Read channel DQ7-P VDL control register */ 376 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7N 0x00000874 /* Read channel DQ7-N VDL control register */ 377 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMP 0x00000878 /* Read channel DM-P VDL control register */ 378 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMN 0x0000087c /* Read channel DM-N VDL control register */ 379 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EDCP 0x00000880 /* Read channel EDC-P VDL control register */ 380 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EDCN 0x00000884 /* Read channel EDC-N VDL control register */ 381 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS0 0x00000888 /* Read channel CS_N[0] read enable VDL control register */ 382 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS1 0x0000088c /* Read channel CS_N[1] read enable VDL control register */ 383 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CLK_CONTROL 0x00000890 /* DDR interface signal Write Leveling CLK VDL control register */ 384 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_LDE_CONTROL 0x00000894 /* DDR interface signal Write Leveling Capture Enable VDL control register */ 385 #define DDR34_E0_PHY_BYTE_LANE_2_RD_EN_DLY_CYC 0x000008a0 /* Read enable bit-clock cycle delay control register */ 386 #define DDR34_E0_PHY_BYTE_LANE_2_WR_CHAN_DLY_CYC 0x000008a4 /* Write leveling bit-clock cycle delay control register */ 387 #define DDR34_E0_PHY_BYTE_LANE_2_READ_CONTROL 0x000008b0 /* Read channel datapath control register */ 388 #define DDR34_E0_PHY_BYTE_LANE_2_READ_FIFO_ADDR 0x000008b4 /* Read fifo addresss pointer register */ 389 #define DDR34_E0_PHY_BYTE_LANE_2_READ_FIFO_DATA 0x000008b8 /* Read fifo data register */ 390 #define DDR34_E0_PHY_BYTE_LANE_2_READ_FIFO_DM_DBI 0x000008bc /* Read fifo dm/dbi register */ 391 #define DDR34_E0_PHY_BYTE_LANE_2_READ_FIFO_STATUS 0x000008c0 /* Read fifo status register */ 392 #define DDR34_E0_PHY_BYTE_LANE_2_READ_FIFO_CLEAR 0x000008c4 /* Read fifo status clear register */ 393 #define DDR34_E0_PHY_BYTE_LANE_2_IDLE_PAD_CONTROL 0x000008c8 /* Idle mode SSTL pad control register */ 394 #define DDR34_E0_PHY_BYTE_LANE_2_DRIVE_PAD_CTL 0x000008cc /* SSTL pad drive characteristics control register */ 395 #define DDR34_E0_PHY_BYTE_LANE_2_RD_EN_DRIVE_PAD_CTL 0x000008d0 /* SSTL read enable pad drive characteristics control register */ 396 #define DDR34_E0_PHY_BYTE_LANE_2_STATIC_PAD_CTL 0x000008d4 /* pad rx and tx characteristics control register */ 397 #define DDR34_E0_PHY_BYTE_LANE_2_WR_PREAMBLE_MODE 0x000008d8 /* Write cycle preamble control register */ 398 #define DDR34_E0_PHY_BYTE_LANE_2_ODT_CONTROL 0x000008e0 /* Read channel ODT control register */ 399 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_DPD_CONTROL 0x000008f0 /* GDDR5M EDC digital phase detector control register */ 400 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_DPD_STATUS 0x000008f4 /* GDDR5M EDC digital phase detector status register */ 401 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_DPD_OUT_CONTROL 0x000008f8 /* GDDR5M EDC digital phase detector output signal control register */ 402 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_DPD_OUT_STATUS 0x000008fc /* GDDR5M EDC digital phase detector output signal status register */ 403 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_DPD_OUT_STATUS_CLEAR 0x00000900 /* GDDR5M EDC digital phase detector output signal status clear register */ 404 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_CRC_CONTROL 0x00000904 /* GDDR5M EDC signal path CRC control register */ 405 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_CRC_STATUS 0x00000908 /* GDDR5M EDC signal path CRC status register */ 406 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_CRC_COUNT 0x0000090c /* GDDR5M EDC signal path CRC counter register */ 407 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_CRC_STATUS_CLEAR 0x00000910 /* GDDR5M EDC signal path CRC counter register */ 408 #define DDR34_E0_PHY_BYTE_LANE_2_BL_SPARE_REG 0x00000914 /* Byte-Lane Spare register */ 409 410 /*************************************************************************** 411 *DDR34_E0_PHY_BYTE_LANE_3 - DDR34 CORE DDR34 Byte Lane #3 control registers 412 */ 413 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_P 0x00000a00 /* Write channel DQS-P VDL control register */ 414 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_N 0x00000a04 /* Write channel DQS-N VDL control register */ 415 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ0 0x00000a08 /* Write channel DQ0 VDL control register */ 416 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ1 0x00000a0c /* Write channel DQ1 VDL control register */ 417 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ2 0x00000a10 /* Write channel DQ2 VDL control register */ 418 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ3 0x00000a14 /* Write channel DQ3 VDL control register */ 419 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ4 0x00000a18 /* Write channel DQ4 VDL control register */ 420 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ5 0x00000a1c /* Write channel DQ5 VDL control register */ 421 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ6 0x00000a20 /* Write channel DQ6 VDL control register */ 422 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ7 0x00000a24 /* Write channel DQ7 VDL control register */ 423 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DM 0x00000a28 /* Write channel DM VDL control register */ 424 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_EDC 0x00000a2c /* Write channel EDC VDL control register */ 425 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSP 0x00000a30 /* Read channel DQSP VDL control register */ 426 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSN 0x00000a34 /* Read channel DQSP VDL control register */ 427 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0P 0x00000a38 /* Read channel DQ0-P VDL control register */ 428 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0N 0x00000a3c /* Read channel DQ0-N VDL control register */ 429 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1P 0x00000a40 /* Read channel DQ1-P VDL control register */ 430 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1N 0x00000a44 /* Read channel DQ1-N VDL control register */ 431 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2P 0x00000a48 /* Read channel DQ2-P VDL control register */ 432 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2N 0x00000a4c /* Read channel DQ2-N VDL control register */ 433 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3P 0x00000a50 /* Read channel DQ3-P VDL control register */ 434 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3N 0x00000a54 /* Read channel DQ3-N VDL control register */ 435 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4P 0x00000a58 /* Read channel DQ4-P VDL control register */ 436 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4N 0x00000a5c /* Read channel DQ4-N VDL control register */ 437 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5P 0x00000a60 /* Read channel DQ5-P VDL control register */ 438 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5N 0x00000a64 /* Read channel DQ5-N VDL control register */ 439 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6P 0x00000a68 /* Read channel DQ6-P VDL control register */ 440 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6N 0x00000a6c /* Read channel DQ6-N VDL control register */ 441 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7P 0x00000a70 /* Read channel DQ7-P VDL control register */ 442 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7N 0x00000a74 /* Read channel DQ7-N VDL control register */ 443 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMP 0x00000a78 /* Read channel DM-P VDL control register */ 444 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMN 0x00000a7c /* Read channel DM-N VDL control register */ 445 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EDCP 0x00000a80 /* Read channel EDC-P VDL control register */ 446 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EDCN 0x00000a84 /* Read channel EDC-N VDL control register */ 447 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS0 0x00000a88 /* Read channel CS_N[0] read enable VDL control register */ 448 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS1 0x00000a8c /* Read channel CS_N[1] read enable VDL control register */ 449 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CLK_CONTROL 0x00000a90 /* DDR interface signal Write Leveling CLK VDL control register */ 450 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_LDE_CONTROL 0x00000a94 /* DDR interface signal Write Leveling Capture Enable VDL control register */ 451 #define DDR34_E0_PHY_BYTE_LANE_3_RD_EN_DLY_CYC 0x00000aa0 /* Read enable bit-clock cycle delay control register */ 452 #define DDR34_E0_PHY_BYTE_LANE_3_WR_CHAN_DLY_CYC 0x00000aa4 /* Write leveling bit-clock cycle delay control register */ 453 #define DDR34_E0_PHY_BYTE_LANE_3_READ_CONTROL 0x00000ab0 /* Read channel datapath control register */ 454 #define DDR34_E0_PHY_BYTE_LANE_3_READ_FIFO_ADDR 0x00000ab4 /* Read fifo addresss pointer register */ 455 #define DDR34_E0_PHY_BYTE_LANE_3_READ_FIFO_DATA 0x00000ab8 /* Read fifo data register */ 456 #define DDR34_E0_PHY_BYTE_LANE_3_READ_FIFO_DM_DBI 0x00000abc /* Read fifo dm/dbi register */ 457 #define DDR34_E0_PHY_BYTE_LANE_3_READ_FIFO_STATUS 0x00000ac0 /* Read fifo status register */ 458 #define DDR34_E0_PHY_BYTE_LANE_3_READ_FIFO_CLEAR 0x00000ac4 /* Read fifo status clear register */ 459 #define DDR34_E0_PHY_BYTE_LANE_3_IDLE_PAD_CONTROL 0x00000ac8 /* Idle mode SSTL pad control register */ 460 #define DDR34_E0_PHY_BYTE_LANE_3_DRIVE_PAD_CTL 0x00000acc /* SSTL pad drive characteristics control register */ 461 #define DDR34_E0_PHY_BYTE_LANE_3_RD_EN_DRIVE_PAD_CTL 0x00000ad0 /* SSTL read enable pad drive characteristics control register */ 462 #define DDR34_E0_PHY_BYTE_LANE_3_STATIC_PAD_CTL 0x00000ad4 /* pad rx and tx characteristics control register */ 463 #define DDR34_E0_PHY_BYTE_LANE_3_WR_PREAMBLE_MODE 0x00000ad8 /* Write cycle preamble control register */ 464 #define DDR34_E0_PHY_BYTE_LANE_3_ODT_CONTROL 0x00000ae0 /* Read channel ODT control register */ 465 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_DPD_CONTROL 0x00000af0 /* GDDR5M EDC digital phase detector control register */ 466 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_DPD_STATUS 0x00000af4 /* GDDR5M EDC digital phase detector status register */ 467 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_DPD_OUT_CONTROL 0x00000af8 /* GDDR5M EDC digital phase detector output signal control register */ 468 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_DPD_OUT_STATUS 0x00000afc /* GDDR5M EDC digital phase detector output signal status register */ 469 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_DPD_OUT_STATUS_CLEAR 0x00000b00 /* GDDR5M EDC digital phase detector output signal status clear register */ 470 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_CRC_CONTROL 0x00000b04 /* GDDR5M EDC signal path CRC control register */ 471 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_CRC_STATUS 0x00000b08 /* GDDR5M EDC signal path CRC status register */ 472 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_CRC_COUNT 0x00000b0c /* GDDR5M EDC signal path CRC counter register */ 473 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_CRC_STATUS_CLEAR 0x00000b10 /* GDDR5M EDC signal path CRC counter register */ 474 #define DDR34_E0_PHY_BYTE_LANE_3_BL_SPARE_REG 0x00000b14 /* Byte-Lane Spare register */ 475 476 /*************************************************************************** 477 *REVISION - Address & Control revision register 478 */ 479 /* DDR34_E0_PHY_CONTROL_REGS :: REVISION :: reserved0 [31:25] */ 480 #define DDR34_E0_PHY_CONTROL_REGS_REVISION_RESERVED0_MASK 0xfe000000 481 #define DDR34_E0_PHY_CONTROL_REGS_REVISION_RESERVED0_ALIGN 0 482 #define DDR34_E0_PHY_CONTROL_REGS_REVISION_RESERVED0_BITS 7 483 #define DDR34_E0_PHY_CONTROL_REGS_REVISION_RESERVED0_SHIFT 25 484 485 /* DDR34_E0_PHY_CONTROL_REGS :: REVISION :: PERFORMANCE [24:23] */ 486 #define DDR34_E0_PHY_CONTROL_REGS_REVISION_PERFORMANCE_MASK 0x01800000 487 #define DDR34_E0_PHY_CONTROL_REGS_REVISION_PERFORMANCE_ALIGN 0 488 #define DDR34_E0_PHY_CONTROL_REGS_REVISION_PERFORMANCE_BITS 2 489 #define DDR34_E0_PHY_CONTROL_REGS_REVISION_PERFORMANCE_SHIFT 23 490 491 /* DDR34_E0_PHY_CONTROL_REGS :: REVISION :: TECHNOLOGY [22:20] */ 492 #define DDR34_E0_PHY_CONTROL_REGS_REVISION_TECHNOLOGY_MASK 0x00700000 493 #define DDR34_E0_PHY_CONTROL_REGS_REVISION_TECHNOLOGY_ALIGN 0 494 #define DDR34_E0_PHY_CONTROL_REGS_REVISION_TECHNOLOGY_BITS 3 495 #define DDR34_E0_PHY_CONTROL_REGS_REVISION_TECHNOLOGY_SHIFT 20 496 497 /* DDR34_E0_PHY_CONTROL_REGS :: REVISION :: WB [19:19] */ 498 #define DDR34_E0_PHY_CONTROL_REGS_REVISION_WB_MASK 0x00080000 499 #define DDR34_E0_PHY_CONTROL_REGS_REVISION_WB_ALIGN 0 500 #define DDR34_E0_PHY_CONTROL_REGS_REVISION_WB_BITS 1 501 #define DDR34_E0_PHY_CONTROL_REGS_REVISION_WB_SHIFT 19 502 503 /* DDR34_E0_PHY_CONTROL_REGS :: REVISION :: BITS [18:16] */ 504 #define DDR34_E0_PHY_CONTROL_REGS_REVISION_BITS_MASK 0x00070000 505 #define DDR34_E0_PHY_CONTROL_REGS_REVISION_BITS_ALIGN 0 506 #define DDR34_E0_PHY_CONTROL_REGS_REVISION_BITS_BITS 3 507 #define DDR34_E0_PHY_CONTROL_REGS_REVISION_BITS_SHIFT 16 508 509 /* DDR34_E0_PHY_CONTROL_REGS :: REVISION :: MAJOR [15:08] */ 510 #define DDR34_E0_PHY_CONTROL_REGS_REVISION_MAJOR_MASK 0x0000ff00 511 #define DDR34_E0_PHY_CONTROL_REGS_REVISION_MAJOR_ALIGN 0 512 #define DDR34_E0_PHY_CONTROL_REGS_REVISION_MAJOR_BITS 8 513 #define DDR34_E0_PHY_CONTROL_REGS_REVISION_MAJOR_SHIFT 8 514 #define DDR34_E0_PHY_CONTROL_REGS_REVISION_MAJOR_DEFAULT 0x000000e0 515 516 /* DDR34_E0_PHY_CONTROL_REGS :: REVISION :: MINOR [07:00] */ 517 #define DDR34_E0_PHY_CONTROL_REGS_REVISION_MINOR_MASK 0x000000ff 518 #define DDR34_E0_PHY_CONTROL_REGS_REVISION_MINOR_ALIGN 0 519 #define DDR34_E0_PHY_CONTROL_REGS_REVISION_MINOR_BITS 8 520 #define DDR34_E0_PHY_CONTROL_REGS_REVISION_MINOR_SHIFT 0 521 #define DDR34_E0_PHY_CONTROL_REGS_REVISION_MINOR_DEFAULT 0x00000001 522 523 /*************************************************************************** 524 *PLL_STATUS - PHY PLL status register 525 */ 526 /* DDR34_E0_PHY_CONTROL_REGS :: PLL_STATUS :: reserved0 [31:17] */ 527 #define DDR34_E0_PHY_CONTROL_REGS_PLL_STATUS_RESERVED0_MASK 0xfffe0000 528 #define DDR34_E0_PHY_CONTROL_REGS_PLL_STATUS_RESERVED0_ALIGN 0 529 #define DDR34_E0_PHY_CONTROL_REGS_PLL_STATUS_RESERVED0_BITS 15 530 #define DDR34_E0_PHY_CONTROL_REGS_PLL_STATUS_RESERVED0_SHIFT 17 531 532 /* DDR34_E0_PHY_CONTROL_REGS :: PLL_STATUS :: LOCK_LOST [16:16] */ 533 #define DDR34_E0_PHY_CONTROL_REGS_PLL_STATUS_LOCK_LOST_MASK 0x00010000 534 #define DDR34_E0_PHY_CONTROL_REGS_PLL_STATUS_LOCK_LOST_ALIGN 0 535 #define DDR34_E0_PHY_CONTROL_REGS_PLL_STATUS_LOCK_LOST_BITS 1 536 #define DDR34_E0_PHY_CONTROL_REGS_PLL_STATUS_LOCK_LOST_SHIFT 16 537 538 /* DDR34_E0_PHY_CONTROL_REGS :: PLL_STATUS :: CLOCKING_8X [15:15] */ 539 #define DDR34_E0_PHY_CONTROL_REGS_PLL_STATUS_CLOCKING_8X_MASK 0x00008000 540 #define DDR34_E0_PHY_CONTROL_REGS_PLL_STATUS_CLOCKING_8X_ALIGN 0 541 #define DDR34_E0_PHY_CONTROL_REGS_PLL_STATUS_CLOCKING_8X_BITS 1 542 #define DDR34_E0_PHY_CONTROL_REGS_PLL_STATUS_CLOCKING_8X_SHIFT 15 543 544 /* DDR34_E0_PHY_CONTROL_REGS :: PLL_STATUS :: CLOCKING_4X [14:14] */ 545 #define DDR34_E0_PHY_CONTROL_REGS_PLL_STATUS_CLOCKING_4X_MASK 0x00004000 546 #define DDR34_E0_PHY_CONTROL_REGS_PLL_STATUS_CLOCKING_4X_ALIGN 0 547 #define DDR34_E0_PHY_CONTROL_REGS_PLL_STATUS_CLOCKING_4X_BITS 1 548 #define DDR34_E0_PHY_CONTROL_REGS_PLL_STATUS_CLOCKING_4X_SHIFT 14 549 550 /* DDR34_E0_PHY_CONTROL_REGS :: PLL_STATUS :: CLOCKING_2X [13:13] */ 551 #define DDR34_E0_PHY_CONTROL_REGS_PLL_STATUS_CLOCKING_2X_MASK 0x00002000 552 #define DDR34_E0_PHY_CONTROL_REGS_PLL_STATUS_CLOCKING_2X_ALIGN 0 553 #define DDR34_E0_PHY_CONTROL_REGS_PLL_STATUS_CLOCKING_2X_BITS 1 554 #define DDR34_E0_PHY_CONTROL_REGS_PLL_STATUS_CLOCKING_2X_SHIFT 13 555 556 /* DDR34_E0_PHY_CONTROL_REGS :: PLL_STATUS :: STATUS [12:01] */ 557 #define DDR34_E0_PHY_CONTROL_REGS_PLL_STATUS_STATUS_MASK 0x00001ffe 558 #define DDR34_E0_PHY_CONTROL_REGS_PLL_STATUS_STATUS_ALIGN 0 559 #define DDR34_E0_PHY_CONTROL_REGS_PLL_STATUS_STATUS_BITS 12 560 #define DDR34_E0_PHY_CONTROL_REGS_PLL_STATUS_STATUS_SHIFT 1 561 562 /* DDR34_E0_PHY_CONTROL_REGS :: PLL_STATUS :: LOCK [00:00] */ 563 #define DDR34_E0_PHY_CONTROL_REGS_PLL_STATUS_LOCK_MASK 0x00000001 564 #define DDR34_E0_PHY_CONTROL_REGS_PLL_STATUS_LOCK_ALIGN 0 565 #define DDR34_E0_PHY_CONTROL_REGS_PLL_STATUS_LOCK_BITS 1 566 #define DDR34_E0_PHY_CONTROL_REGS_PLL_STATUS_LOCK_SHIFT 0 567 568 /*************************************************************************** 569 *PLL_CONFIG - PHY PLL configuration register 570 */ 571 /* DDR34_E0_PHY_CONTROL_REGS :: PLL_CONFIG :: reserved0 [31:28] */ 572 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONFIG_RESERVED0_MASK 0xf0000000 573 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONFIG_RESERVED0_ALIGN 0 574 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONFIG_RESERVED0_BITS 4 575 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONFIG_RESERVED0_SHIFT 28 576 577 /* DDR34_E0_PHY_CONTROL_REGS :: PLL_CONFIG :: reserved_for_eco1 [27:27] */ 578 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONFIG_RESERVED_for_eco1_MASK 0x08000000 579 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONFIG_RESERVED_for_eco1_ALIGN 0 580 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONFIG_RESERVED_for_eco1_BITS 1 581 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONFIG_RESERVED_for_eco1_SHIFT 27 582 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONFIG_RESERVED_for_eco1_DEFAULT 0x00000000 583 584 /* DDR34_E0_PHY_CONTROL_REGS :: PLL_CONFIG :: CK_LDO_REF_CTRL [26:25] */ 585 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONFIG_CK_LDO_REF_CTRL_MASK 0x06000000 586 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONFIG_CK_LDO_REF_CTRL_ALIGN 0 587 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONFIG_CK_LDO_REF_CTRL_BITS 2 588 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONFIG_CK_LDO_REF_CTRL_SHIFT 25 589 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONFIG_CK_LDO_REF_CTRL_DEFAULT 0x00000001 590 591 /* DDR34_E0_PHY_CONTROL_REGS :: PLL_CONFIG :: CK_LDO_BIAS [24:23] */ 592 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONFIG_CK_LDO_BIAS_MASK 0x01800000 593 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONFIG_CK_LDO_BIAS_ALIGN 0 594 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONFIG_CK_LDO_BIAS_BITS 2 595 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONFIG_CK_LDO_BIAS_SHIFT 23 596 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONFIG_CK_LDO_BIAS_DEFAULT 0x00000003 597 598 /* DDR34_E0_PHY_CONTROL_REGS :: PLL_CONFIG :: PLL_LDO_REF_SEL [22:22] */ 599 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONFIG_PLL_LDO_REF_SEL_MASK 0x00400000 600 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONFIG_PLL_LDO_REF_SEL_ALIGN 0 601 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONFIG_PLL_LDO_REF_SEL_BITS 1 602 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONFIG_PLL_LDO_REF_SEL_SHIFT 22 603 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONFIG_PLL_LDO_REF_SEL_DEFAULT 0x00000000 604 605 /* DDR34_E0_PHY_CONTROL_REGS :: PLL_CONFIG :: PLL_LDO_REF_CTRL [21:20] */ 606 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONFIG_PLL_LDO_REF_CTRL_MASK 0x00300000 607 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONFIG_PLL_LDO_REF_CTRL_ALIGN 0 608 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONFIG_PLL_LDO_REF_CTRL_BITS 2 609 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONFIG_PLL_LDO_REF_CTRL_SHIFT 20 610 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONFIG_PLL_LDO_REF_CTRL_DEFAULT 0x00000001 611 612 /* DDR34_E0_PHY_CONTROL_REGS :: PLL_CONFIG :: PLL_LDO_BIAS [19:18] */ 613 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONFIG_PLL_LDO_BIAS_MASK 0x000c0000 614 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONFIG_PLL_LDO_BIAS_ALIGN 0 615 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONFIG_PLL_LDO_BIAS_BITS 2 616 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONFIG_PLL_LDO_BIAS_SHIFT 18 617 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONFIG_PLL_LDO_BIAS_DEFAULT 0x00000003 618 619 /* DDR34_E0_PHY_CONTROL_REGS :: PLL_CONFIG :: HOLD [17:17] */ 620 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONFIG_HOLD_MASK 0x00020000 621 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONFIG_HOLD_ALIGN 0 622 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONFIG_HOLD_BITS 1 623 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONFIG_HOLD_SHIFT 17 624 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONFIG_HOLD_DEFAULT 0x00000000 625 626 /* DDR34_E0_PHY_CONTROL_REGS :: PLL_CONFIG :: ENABLE [16:16] */ 627 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONFIG_ENABLE_MASK 0x00010000 628 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONFIG_ENABLE_ALIGN 0 629 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONFIG_ENABLE_BITS 1 630 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONFIG_ENABLE_SHIFT 16 631 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONFIG_ENABLE_DEFAULT 0x00000001 632 633 /* DDR34_E0_PHY_CONTROL_REGS :: PLL_CONFIG :: reserved2 [15:14] */ 634 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONFIG_RESERVED2_MASK 0x0000c000 635 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONFIG_RESERVED2_ALIGN 0 636 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONFIG_RESERVED2_BITS 2 637 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONFIG_RESERVED2_SHIFT 14 638 639 /* DDR34_E0_PHY_CONTROL_REGS :: PLL_CONFIG :: FB_OFFSET [13:08] */ 640 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONFIG_FB_OFFSET_MASK 0x00003f00 641 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONFIG_FB_OFFSET_ALIGN 0 642 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONFIG_FB_OFFSET_BITS 6 643 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONFIG_FB_OFFSET_SHIFT 8 644 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONFIG_FB_OFFSET_DEFAULT 0x00000000 645 646 /* DDR34_E0_PHY_CONTROL_REGS :: PLL_CONFIG :: reserved3 [07:05] */ 647 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONFIG_RESERVED3_MASK 0x000000e0 648 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONFIG_RESERVED3_ALIGN 0 649 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONFIG_RESERVED3_BITS 3 650 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONFIG_RESERVED3_SHIFT 5 651 652 /* DDR34_E0_PHY_CONTROL_REGS :: PLL_CONFIG :: RESET_POST_DIV [04:04] */ 653 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONFIG_RESET_POST_DIV_MASK 0x00000010 654 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONFIG_RESET_POST_DIV_ALIGN 0 655 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONFIG_RESET_POST_DIV_BITS 1 656 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONFIG_RESET_POST_DIV_SHIFT 4 657 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONFIG_RESET_POST_DIV_DEFAULT 0x00000000 658 659 /* DDR34_E0_PHY_CONTROL_REGS :: PLL_CONFIG :: reserved4 [03:02] */ 660 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONFIG_RESERVED4_MASK 0x0000000c 661 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONFIG_RESERVED4_ALIGN 0 662 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONFIG_RESERVED4_BITS 2 663 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONFIG_RESERVED4_SHIFT 2 664 665 /* DDR34_E0_PHY_CONTROL_REGS :: PLL_CONFIG :: RESET [01:01] */ 666 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONFIG_RESET_MASK 0x00000002 667 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONFIG_RESET_ALIGN 0 668 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONFIG_RESET_BITS 1 669 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONFIG_RESET_SHIFT 1 670 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONFIG_RESET_DEFAULT 0x00000000 671 672 /* DDR34_E0_PHY_CONTROL_REGS :: PLL_CONFIG :: PWRDN [00:00] */ 673 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONFIG_PWRDN_MASK 0x00000001 674 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONFIG_PWRDN_ALIGN 0 675 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONFIG_PWRDN_BITS 1 676 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONFIG_PWRDN_SHIFT 0 677 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONFIG_PWRDN_DEFAULT 0x00000000 678 679 /*************************************************************************** 680 *PLL_CONTROL1 - PHY PLL control register 681 */ 682 /* DDR34_E0_PHY_CONTROL_REGS :: PLL_CONTROL1 :: reserved0 [31:10] */ 683 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONTROL1_RESERVED0_MASK 0xfffffc00 684 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONTROL1_RESERVED0_ALIGN 0 685 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONTROL1_RESERVED0_BITS 22 686 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONTROL1_RESERVED0_SHIFT 10 687 688 /* DDR34_E0_PHY_CONTROL_REGS :: PLL_CONTROL1 :: I_KP [09:06] */ 689 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONTROL1_I_KP_MASK 0x000003c0 690 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONTROL1_I_KP_ALIGN 0 691 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONTROL1_I_KP_BITS 4 692 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONTROL1_I_KP_SHIFT 6 693 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONTROL1_I_KP_DEFAULT 0x00000005 694 695 /* DDR34_E0_PHY_CONTROL_REGS :: PLL_CONTROL1 :: I_KI [05:03] */ 696 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONTROL1_I_KI_MASK 0x00000038 697 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONTROL1_I_KI_ALIGN 0 698 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONTROL1_I_KI_BITS 3 699 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONTROL1_I_KI_SHIFT 3 700 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONTROL1_I_KI_DEFAULT 0x00000002 701 702 /* DDR34_E0_PHY_CONTROL_REGS :: PLL_CONTROL1 :: I_KA [02:00] */ 703 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONTROL1_I_KA_MASK 0x00000007 704 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONTROL1_I_KA_ALIGN 0 705 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONTROL1_I_KA_BITS 3 706 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONTROL1_I_KA_SHIFT 0 707 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONTROL1_I_KA_DEFAULT 0x00000000 708 709 /*************************************************************************** 710 *PLL_CONTROL2 - PHY PLL control register 711 */ 712 /* DDR34_E0_PHY_CONTROL_REGS :: PLL_CONTROL2 :: VCO_RANGE [31:30] */ 713 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONTROL2_VCO_RANGE_MASK 0xc0000000 714 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONTROL2_VCO_RANGE_ALIGN 0 715 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONTROL2_VCO_RANGE_BITS 2 716 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONTROL2_VCO_RANGE_SHIFT 30 717 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONTROL2_VCO_RANGE_DEFAULT 0x00000000 718 719 /* DDR34_E0_PHY_CONTROL_REGS :: PLL_CONTROL2 :: UNUSED2 [29:29] */ 720 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONTROL2_UNUSED2_MASK 0x20000000 721 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONTROL2_UNUSED2_ALIGN 0 722 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONTROL2_UNUSED2_BITS 1 723 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONTROL2_UNUSED2_SHIFT 29 724 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONTROL2_UNUSED2_DEFAULT 0x00000000 725 726 /* DDR34_E0_PHY_CONTROL_REGS :: PLL_CONTROL2 :: NDIV_RELOCK [28:28] */ 727 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONTROL2_NDIV_RELOCK_MASK 0x10000000 728 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONTROL2_NDIV_RELOCK_ALIGN 0 729 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONTROL2_NDIV_RELOCK_BITS 1 730 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONTROL2_NDIV_RELOCK_SHIFT 28 731 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONTROL2_NDIV_RELOCK_DEFAULT 0x00000001 732 733 /* DDR34_E0_PHY_CONTROL_REGS :: PLL_CONTROL2 :: FAST_LOCK [27:27] */ 734 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONTROL2_FAST_LOCK_MASK 0x08000000 735 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONTROL2_FAST_LOCK_ALIGN 0 736 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONTROL2_FAST_LOCK_BITS 1 737 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONTROL2_FAST_LOCK_SHIFT 27 738 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONTROL2_FAST_LOCK_DEFAULT 0x00000001 739 740 /* DDR34_E0_PHY_CONTROL_REGS :: PLL_CONTROL2 :: VCO_FB_DIV2 [26:26] */ 741 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONTROL2_VCO_FB_DIV2_MASK 0x04000000 742 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONTROL2_VCO_FB_DIV2_ALIGN 0 743 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONTROL2_VCO_FB_DIV2_BITS 1 744 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONTROL2_VCO_FB_DIV2_SHIFT 26 745 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONTROL2_VCO_FB_DIV2_DEFAULT 0x00000000 746 747 /* DDR34_E0_PHY_CONTROL_REGS :: PLL_CONTROL2 :: POST_CTRL_RESETB [25:24] */ 748 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONTROL2_POST_CTRL_RESETB_MASK 0x03000000 749 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONTROL2_POST_CTRL_RESETB_ALIGN 0 750 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONTROL2_POST_CTRL_RESETB_BITS 2 751 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONTROL2_POST_CTRL_RESETB_SHIFT 24 752 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONTROL2_POST_CTRL_RESETB_DEFAULT 0x00000000 753 754 /* DDR34_E0_PHY_CONTROL_REGS :: PLL_CONTROL2 :: PWM_RATE [23:22] */ 755 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONTROL2_PWM_RATE_MASK 0x00c00000 756 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONTROL2_PWM_RATE_ALIGN 0 757 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONTROL2_PWM_RATE_BITS 2 758 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONTROL2_PWM_RATE_SHIFT 22 759 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONTROL2_PWM_RATE_DEFAULT 0x00000000 760 761 /* DDR34_E0_PHY_CONTROL_REGS :: PLL_CONTROL2 :: STAT_MODE [21:20] */ 762 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONTROL2_STAT_MODE_MASK 0x00300000 763 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONTROL2_STAT_MODE_ALIGN 0 764 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONTROL2_STAT_MODE_BITS 2 765 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONTROL2_STAT_MODE_SHIFT 20 766 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONTROL2_STAT_MODE_DEFAULT 0x00000000 767 768 /* DDR34_E0_PHY_CONTROL_REGS :: PLL_CONTROL2 :: UNUSED1 [19:18] */ 769 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONTROL2_UNUSED1_MASK 0x000c0000 770 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONTROL2_UNUSED1_ALIGN 0 771 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONTROL2_UNUSED1_BITS 2 772 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONTROL2_UNUSED1_SHIFT 18 773 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONTROL2_UNUSED1_DEFAULT 0x00000000 774 775 /* DDR34_E0_PHY_CONTROL_REGS :: PLL_CONTROL2 :: STAT_UPDATE [17:17] */ 776 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONTROL2_STAT_UPDATE_MASK 0x00020000 777 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONTROL2_STAT_UPDATE_ALIGN 0 778 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONTROL2_STAT_UPDATE_BITS 1 779 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONTROL2_STAT_UPDATE_SHIFT 17 780 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONTROL2_STAT_UPDATE_DEFAULT 0x00000000 781 782 /* DDR34_E0_PHY_CONTROL_REGS :: PLL_CONTROL2 :: STAT_SELECT [16:14] */ 783 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONTROL2_STAT_SELECT_MASK 0x0001c000 784 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONTROL2_STAT_SELECT_ALIGN 0 785 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONTROL2_STAT_SELECT_BITS 3 786 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONTROL2_STAT_SELECT_SHIFT 14 787 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONTROL2_STAT_SELECT_DEFAULT 0x00000000 788 789 /* DDR34_E0_PHY_CONTROL_REGS :: PLL_CONTROL2 :: STAT_RESET [13:13] */ 790 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONTROL2_STAT_RESET_MASK 0x00002000 791 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONTROL2_STAT_RESET_ALIGN 0 792 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONTROL2_STAT_RESET_BITS 1 793 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONTROL2_STAT_RESET_SHIFT 13 794 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONTROL2_STAT_RESET_DEFAULT 0x00000000 795 796 /* DDR34_E0_PHY_CONTROL_REGS :: PLL_CONTROL2 :: DCO_CTRL_BYPASS_ENABLE [12:12] */ 797 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONTROL2_DCO_CTRL_BYPASS_ENABLE_MASK 0x00001000 798 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONTROL2_DCO_CTRL_BYPASS_ENABLE_ALIGN 0 799 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONTROL2_DCO_CTRL_BYPASS_ENABLE_BITS 1 800 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONTROL2_DCO_CTRL_BYPASS_ENABLE_SHIFT 12 801 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONTROL2_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000 802 803 /* DDR34_E0_PHY_CONTROL_REGS :: PLL_CONTROL2 :: DCO_CTRL_BYPASS [11:00] */ 804 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONTROL2_DCO_CTRL_BYPASS_MASK 0x00000fff 805 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONTROL2_DCO_CTRL_BYPASS_ALIGN 0 806 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONTROL2_DCO_CTRL_BYPASS_BITS 12 807 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONTROL2_DCO_CTRL_BYPASS_SHIFT 0 808 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONTROL2_DCO_CTRL_BYPASS_DEFAULT 0x00000000 809 810 /*************************************************************************** 811 *PLL_CONTROL3 - PHY PLL control register 812 */ 813 /* DDR34_E0_PHY_CONTROL_REGS :: PLL_CONTROL3 :: PLL_CONTROL [31:00] */ 814 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONTROL3_PLL_CONTROL_MASK 0xffffffff 815 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONTROL3_PLL_CONTROL_ALIGN 0 816 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONTROL3_PLL_CONTROL_BITS 32 817 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONTROL3_PLL_CONTROL_SHIFT 0 818 #define DDR34_E0_PHY_CONTROL_REGS_PLL_CONTROL3_PLL_CONTROL_DEFAULT 0x00000000 819 820 /*************************************************************************** 821 *PLL_DIVIDERS - PHY PLL integer divider register 822 */ 823 /* DDR34_E0_PHY_CONTROL_REGS :: PLL_DIVIDERS :: reserved0 [31:28] */ 824 #define DDR34_E0_PHY_CONTROL_REGS_PLL_DIVIDERS_RESERVED0_MASK 0xf0000000 825 #define DDR34_E0_PHY_CONTROL_REGS_PLL_DIVIDERS_RESERVED0_ALIGN 0 826 #define DDR34_E0_PHY_CONTROL_REGS_PLL_DIVIDERS_RESERVED0_BITS 4 827 #define DDR34_E0_PHY_CONTROL_REGS_PLL_DIVIDERS_RESERVED0_SHIFT 28 828 829 /* DDR34_E0_PHY_CONTROL_REGS :: PLL_DIVIDERS :: MDIV [27:20] */ 830 #define DDR34_E0_PHY_CONTROL_REGS_PLL_DIVIDERS_MDIV_MASK 0x0ff00000 831 #define DDR34_E0_PHY_CONTROL_REGS_PLL_DIVIDERS_MDIV_ALIGN 0 832 #define DDR34_E0_PHY_CONTROL_REGS_PLL_DIVIDERS_MDIV_BITS 8 833 #define DDR34_E0_PHY_CONTROL_REGS_PLL_DIVIDERS_MDIV_SHIFT 20 834 #define DDR34_E0_PHY_CONTROL_REGS_PLL_DIVIDERS_MDIV_DEFAULT 0x00000001 835 836 /* DDR34_E0_PHY_CONTROL_REGS :: PLL_DIVIDERS :: reserved1 [19:16] */ 837 #define DDR34_E0_PHY_CONTROL_REGS_PLL_DIVIDERS_RESERVED1_MASK 0x000f0000 838 #define DDR34_E0_PHY_CONTROL_REGS_PLL_DIVIDERS_RESERVED1_ALIGN 0 839 #define DDR34_E0_PHY_CONTROL_REGS_PLL_DIVIDERS_RESERVED1_BITS 4 840 #define DDR34_E0_PHY_CONTROL_REGS_PLL_DIVIDERS_RESERVED1_SHIFT 16 841 842 /* DDR34_E0_PHY_CONTROL_REGS :: PLL_DIVIDERS :: PDIV [15:12] */ 843 #define DDR34_E0_PHY_CONTROL_REGS_PLL_DIVIDERS_PDIV_MASK 0x0000f000 844 #define DDR34_E0_PHY_CONTROL_REGS_PLL_DIVIDERS_PDIV_ALIGN 0 845 #define DDR34_E0_PHY_CONTROL_REGS_PLL_DIVIDERS_PDIV_BITS 4 846 #define DDR34_E0_PHY_CONTROL_REGS_PLL_DIVIDERS_PDIV_SHIFT 12 847 #define DDR34_E0_PHY_CONTROL_REGS_PLL_DIVIDERS_PDIV_DEFAULT 0x00000001 848 849 /* DDR34_E0_PHY_CONTROL_REGS :: PLL_DIVIDERS :: reserved2 [11:10] */ 850 #define DDR34_E0_PHY_CONTROL_REGS_PLL_DIVIDERS_RESERVED2_MASK 0x00000c00 851 #define DDR34_E0_PHY_CONTROL_REGS_PLL_DIVIDERS_RESERVED2_ALIGN 0 852 #define DDR34_E0_PHY_CONTROL_REGS_PLL_DIVIDERS_RESERVED2_BITS 2 853 #define DDR34_E0_PHY_CONTROL_REGS_PLL_DIVIDERS_RESERVED2_SHIFT 10 854 855 /* DDR34_E0_PHY_CONTROL_REGS :: PLL_DIVIDERS :: NDIV_INT [09:00] */ 856 #define DDR34_E0_PHY_CONTROL_REGS_PLL_DIVIDERS_NDIV_INT_MASK 0x000003ff 857 #define DDR34_E0_PHY_CONTROL_REGS_PLL_DIVIDERS_NDIV_INT_ALIGN 0 858 #define DDR34_E0_PHY_CONTROL_REGS_PLL_DIVIDERS_NDIV_INT_BITS 10 859 #define DDR34_E0_PHY_CONTROL_REGS_PLL_DIVIDERS_NDIV_INT_SHIFT 0 860 #define DDR34_E0_PHY_CONTROL_REGS_PLL_DIVIDERS_NDIV_INT_DEFAULT 0x00000020 861 862 /*************************************************************************** 863 *PLL_FRAC_DIVIDER - PHY PLL fractional divider register 864 */ 865 /* DDR34_E0_PHY_CONTROL_REGS :: PLL_FRAC_DIVIDER :: reserved0 [31:20] */ 866 #define DDR34_E0_PHY_CONTROL_REGS_PLL_FRAC_DIVIDER_RESERVED0_MASK 0xfff00000 867 #define DDR34_E0_PHY_CONTROL_REGS_PLL_FRAC_DIVIDER_RESERVED0_ALIGN 0 868 #define DDR34_E0_PHY_CONTROL_REGS_PLL_FRAC_DIVIDER_RESERVED0_BITS 12 869 #define DDR34_E0_PHY_CONTROL_REGS_PLL_FRAC_DIVIDER_RESERVED0_SHIFT 20 870 871 /* DDR34_E0_PHY_CONTROL_REGS :: PLL_FRAC_DIVIDER :: NDIV_FRAC [19:00] */ 872 #define DDR34_E0_PHY_CONTROL_REGS_PLL_FRAC_DIVIDER_NDIV_FRAC_MASK 0x000fffff 873 #define DDR34_E0_PHY_CONTROL_REGS_PLL_FRAC_DIVIDER_NDIV_FRAC_ALIGN 0 874 #define DDR34_E0_PHY_CONTROL_REGS_PLL_FRAC_DIVIDER_NDIV_FRAC_BITS 20 875 #define DDR34_E0_PHY_CONTROL_REGS_PLL_FRAC_DIVIDER_NDIV_FRAC_SHIFT 0 876 #define DDR34_E0_PHY_CONTROL_REGS_PLL_FRAC_DIVIDER_NDIV_FRAC_DEFAULT 0x00000000 877 878 /*************************************************************************** 879 *PLL_SS_CONTROL - PHY PLL spread spectrum control register 880 */ 881 /* DDR34_E0_PHY_CONTROL_REGS :: PLL_SS_CONTROL :: reserved0 [31:20] */ 882 #define DDR34_E0_PHY_CONTROL_REGS_PLL_SS_CONTROL_RESERVED0_MASK 0xfff00000 883 #define DDR34_E0_PHY_CONTROL_REGS_PLL_SS_CONTROL_RESERVED0_ALIGN 0 884 #define DDR34_E0_PHY_CONTROL_REGS_PLL_SS_CONTROL_RESERVED0_BITS 12 885 #define DDR34_E0_PHY_CONTROL_REGS_PLL_SS_CONTROL_RESERVED0_SHIFT 20 886 887 /* DDR34_E0_PHY_CONTROL_REGS :: PLL_SS_CONTROL :: SSC_STEP [19:04] */ 888 #define DDR34_E0_PHY_CONTROL_REGS_PLL_SS_CONTROL_SSC_STEP_MASK 0x000ffff0 889 #define DDR34_E0_PHY_CONTROL_REGS_PLL_SS_CONTROL_SSC_STEP_ALIGN 0 890 #define DDR34_E0_PHY_CONTROL_REGS_PLL_SS_CONTROL_SSC_STEP_BITS 16 891 #define DDR34_E0_PHY_CONTROL_REGS_PLL_SS_CONTROL_SSC_STEP_SHIFT 4 892 #define DDR34_E0_PHY_CONTROL_REGS_PLL_SS_CONTROL_SSC_STEP_DEFAULT 0x00000000 893 894 /* DDR34_E0_PHY_CONTROL_REGS :: PLL_SS_CONTROL :: reserved1 [03:01] */ 895 #define DDR34_E0_PHY_CONTROL_REGS_PLL_SS_CONTROL_RESERVED1_MASK 0x0000000e 896 #define DDR34_E0_PHY_CONTROL_REGS_PLL_SS_CONTROL_RESERVED1_ALIGN 0 897 #define DDR34_E0_PHY_CONTROL_REGS_PLL_SS_CONTROL_RESERVED1_BITS 3 898 #define DDR34_E0_PHY_CONTROL_REGS_PLL_SS_CONTROL_RESERVED1_SHIFT 1 899 900 /* DDR34_E0_PHY_CONTROL_REGS :: PLL_SS_CONTROL :: SSC_MODE [00:00] */ 901 #define DDR34_E0_PHY_CONTROL_REGS_PLL_SS_CONTROL_SSC_MODE_MASK 0x00000001 902 #define DDR34_E0_PHY_CONTROL_REGS_PLL_SS_CONTROL_SSC_MODE_ALIGN 0 903 #define DDR34_E0_PHY_CONTROL_REGS_PLL_SS_CONTROL_SSC_MODE_BITS 1 904 #define DDR34_E0_PHY_CONTROL_REGS_PLL_SS_CONTROL_SSC_MODE_SHIFT 0 905 #define DDR34_E0_PHY_CONTROL_REGS_PLL_SS_CONTROL_SSC_MODE_DEFAULT 0x00000000 906 907 /*************************************************************************** 908 *PLL_SS_LIMIT - PHY PLL spread spectrum limit register 909 */ 910 /* DDR34_E0_PHY_CONTROL_REGS :: PLL_SS_LIMIT :: reserved0 [31:26] */ 911 #define DDR34_E0_PHY_CONTROL_REGS_PLL_SS_LIMIT_RESERVED0_MASK 0xfc000000 912 #define DDR34_E0_PHY_CONTROL_REGS_PLL_SS_LIMIT_RESERVED0_ALIGN 0 913 #define DDR34_E0_PHY_CONTROL_REGS_PLL_SS_LIMIT_RESERVED0_BITS 6 914 #define DDR34_E0_PHY_CONTROL_REGS_PLL_SS_LIMIT_RESERVED0_SHIFT 26 915 916 /* DDR34_E0_PHY_CONTROL_REGS :: PLL_SS_LIMIT :: SSC_LIMIT [25:04] */ 917 #define DDR34_E0_PHY_CONTROL_REGS_PLL_SS_LIMIT_SSC_LIMIT_MASK 0x03fffff0 918 #define DDR34_E0_PHY_CONTROL_REGS_PLL_SS_LIMIT_SSC_LIMIT_ALIGN 0 919 #define DDR34_E0_PHY_CONTROL_REGS_PLL_SS_LIMIT_SSC_LIMIT_BITS 22 920 #define DDR34_E0_PHY_CONTROL_REGS_PLL_SS_LIMIT_SSC_LIMIT_SHIFT 4 921 #define DDR34_E0_PHY_CONTROL_REGS_PLL_SS_LIMIT_SSC_LIMIT_DEFAULT 0x00000000 922 923 /* DDR34_E0_PHY_CONTROL_REGS :: PLL_SS_LIMIT :: reserved1 [03:00] */ 924 #define DDR34_E0_PHY_CONTROL_REGS_PLL_SS_LIMIT_RESERVED1_MASK 0x0000000f 925 #define DDR34_E0_PHY_CONTROL_REGS_PLL_SS_LIMIT_RESERVED1_ALIGN 0 926 #define DDR34_E0_PHY_CONTROL_REGS_PLL_SS_LIMIT_RESERVED1_BITS 4 927 #define DDR34_E0_PHY_CONTROL_REGS_PLL_SS_LIMIT_RESERVED1_SHIFT 0 928 929 /*************************************************************************** 930 *AUX_CONTROL - Aux Control register 931 */ 932 /* DDR34_E0_PHY_CONTROL_REGS :: AUX_CONTROL :: reserved0 [31:21] */ 933 #define DDR34_E0_PHY_CONTROL_REGS_AUX_CONTROL_RESERVED0_MASK 0xffe00000 934 #define DDR34_E0_PHY_CONTROL_REGS_AUX_CONTROL_RESERVED0_ALIGN 0 935 #define DDR34_E0_PHY_CONTROL_REGS_AUX_CONTROL_RESERVED0_BITS 11 936 #define DDR34_E0_PHY_CONTROL_REGS_AUX_CONTROL_RESERVED0_SHIFT 21 937 938 /* DDR34_E0_PHY_CONTROL_REGS :: AUX_CONTROL :: IS_ODT [20:16] */ 939 #define DDR34_E0_PHY_CONTROL_REGS_AUX_CONTROL_IS_ODT_MASK 0x001f0000 940 #define DDR34_E0_PHY_CONTROL_REGS_AUX_CONTROL_IS_ODT_ALIGN 0 941 #define DDR34_E0_PHY_CONTROL_REGS_AUX_CONTROL_IS_ODT_BITS 5 942 #define DDR34_E0_PHY_CONTROL_REGS_AUX_CONTROL_IS_ODT_SHIFT 16 943 #define DDR34_E0_PHY_CONTROL_REGS_AUX_CONTROL_IS_ODT_DEFAULT 0x00000000 944 945 /* DDR34_E0_PHY_CONTROL_REGS :: AUX_CONTROL :: reserved1 [15:13] */ 946 #define DDR34_E0_PHY_CONTROL_REGS_AUX_CONTROL_RESERVED1_MASK 0x0000e000 947 #define DDR34_E0_PHY_CONTROL_REGS_AUX_CONTROL_RESERVED1_ALIGN 0 948 #define DDR34_E0_PHY_CONTROL_REGS_AUX_CONTROL_RESERVED1_BITS 3 949 #define DDR34_E0_PHY_CONTROL_REGS_AUX_CONTROL_RESERVED1_SHIFT 13 950 951 /* DDR34_E0_PHY_CONTROL_REGS :: AUX_CONTROL :: IS_CS [12:08] */ 952 #define DDR34_E0_PHY_CONTROL_REGS_AUX_CONTROL_IS_CS_MASK 0x00001f00 953 #define DDR34_E0_PHY_CONTROL_REGS_AUX_CONTROL_IS_CS_ALIGN 0 954 #define DDR34_E0_PHY_CONTROL_REGS_AUX_CONTROL_IS_CS_BITS 5 955 #define DDR34_E0_PHY_CONTROL_REGS_AUX_CONTROL_IS_CS_SHIFT 8 956 #define DDR34_E0_PHY_CONTROL_REGS_AUX_CONTROL_IS_CS_DEFAULT 0x00000000 957 958 /* DDR34_E0_PHY_CONTROL_REGS :: AUX_CONTROL :: reserved2 [07:05] */ 959 #define DDR34_E0_PHY_CONTROL_REGS_AUX_CONTROL_RESERVED2_MASK 0x000000e0 960 #define DDR34_E0_PHY_CONTROL_REGS_AUX_CONTROL_RESERVED2_ALIGN 0 961 #define DDR34_E0_PHY_CONTROL_REGS_AUX_CONTROL_RESERVED2_BITS 3 962 #define DDR34_E0_PHY_CONTROL_REGS_AUX_CONTROL_RESERVED2_SHIFT 5 963 964 /* DDR34_E0_PHY_CONTROL_REGS :: AUX_CONTROL :: IS_AD [04:00] */ 965 #define DDR34_E0_PHY_CONTROL_REGS_AUX_CONTROL_IS_AD_MASK 0x0000001f 966 #define DDR34_E0_PHY_CONTROL_REGS_AUX_CONTROL_IS_AD_ALIGN 0 967 #define DDR34_E0_PHY_CONTROL_REGS_AUX_CONTROL_IS_AD_BITS 5 968 #define DDR34_E0_PHY_CONTROL_REGS_AUX_CONTROL_IS_AD_SHIFT 0 969 #define DDR34_E0_PHY_CONTROL_REGS_AUX_CONTROL_IS_AD_DEFAULT 0x00000000 970 971 /*************************************************************************** 972 *IDLE_PAD_CONTROL - Idle mode pad control register 973 */ 974 /* DDR34_E0_PHY_CONTROL_REGS :: IDLE_PAD_CONTROL :: IDLE [31:31] */ 975 #define DDR34_E0_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_IDLE_MASK 0x80000000 976 #define DDR34_E0_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_IDLE_ALIGN 0 977 #define DDR34_E0_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_IDLE_BITS 1 978 #define DDR34_E0_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_IDLE_SHIFT 31 979 #define DDR34_E0_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_IDLE_DEFAULT 0x00000000 980 981 /* DDR34_E0_PHY_CONTROL_REGS :: IDLE_PAD_CONTROL :: DIB_MODE [30:30] */ 982 #define DDR34_E0_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_DIB_MODE_MASK 0x40000000 983 #define DDR34_E0_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_DIB_MODE_ALIGN 0 984 #define DDR34_E0_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_DIB_MODE_BITS 1 985 #define DDR34_E0_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_DIB_MODE_SHIFT 30 986 #define DDR34_E0_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_DIB_MODE_DEFAULT 0x00000000 987 988 /* DDR34_E0_PHY_CONTROL_REGS :: IDLE_PAD_CONTROL :: reserved0 [29:04] */ 989 #define DDR34_E0_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_RESERVED0_MASK 0x3ffffff0 990 #define DDR34_E0_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_RESERVED0_ALIGN 0 991 #define DDR34_E0_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_RESERVED0_BITS 26 992 #define DDR34_E0_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_RESERVED0_SHIFT 4 993 994 /* DDR34_E0_PHY_CONTROL_REGS :: IDLE_PAD_CONTROL :: RXENB [03:03] */ 995 #define DDR34_E0_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_RXENB_MASK 0x00000008 996 #define DDR34_E0_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_RXENB_ALIGN 0 997 #define DDR34_E0_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_RXENB_BITS 1 998 #define DDR34_E0_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_RXENB_SHIFT 3 999 #define DDR34_E0_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_RXENB_DEFAULT 0x00000001 1000 1001 /* DDR34_E0_PHY_CONTROL_REGS :: IDLE_PAD_CONTROL :: IDDQ [02:02] */ 1002 #define DDR34_E0_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_IDDQ_MASK 0x00000004 1003 #define DDR34_E0_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_IDDQ_ALIGN 0 1004 #define DDR34_E0_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_IDDQ_BITS 1 1005 #define DDR34_E0_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_IDDQ_SHIFT 2 1006 #define DDR34_E0_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_IDDQ_DEFAULT 0x00000000 1007 1008 /* DDR34_E0_PHY_CONTROL_REGS :: IDLE_PAD_CONTROL :: DOUT_N [01:01] */ 1009 #define DDR34_E0_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_DOUT_N_MASK 0x00000002 1010 #define DDR34_E0_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_DOUT_N_ALIGN 0 1011 #define DDR34_E0_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_DOUT_N_BITS 1 1012 #define DDR34_E0_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_DOUT_N_SHIFT 1 1013 #define DDR34_E0_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_DOUT_N_DEFAULT 0x00000001 1014 1015 /* DDR34_E0_PHY_CONTROL_REGS :: IDLE_PAD_CONTROL :: DOUT_P [00:00] */ 1016 #define DDR34_E0_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_DOUT_P_MASK 0x00000001 1017 #define DDR34_E0_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_DOUT_P_ALIGN 0 1018 #define DDR34_E0_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_DOUT_P_BITS 1 1019 #define DDR34_E0_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_DOUT_P_SHIFT 0 1020 #define DDR34_E0_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_DOUT_P_DEFAULT 0x00000000 1021 1022 /*************************************************************************** 1023 *IDLE_PAD_ENABLE0 - Idle mode pad enable register 1024 */ 1025 /* DDR34_E0_PHY_CONTROL_REGS :: IDLE_PAD_ENABLE0 :: reserved0 [31:11] */ 1026 #define DDR34_E0_PHY_CONTROL_REGS_IDLE_PAD_ENABLE0_RESERVED0_MASK 0xfffff800 1027 #define DDR34_E0_PHY_CONTROL_REGS_IDLE_PAD_ENABLE0_RESERVED0_ALIGN 0 1028 #define DDR34_E0_PHY_CONTROL_REGS_IDLE_PAD_ENABLE0_RESERVED0_BITS 21 1029 #define DDR34_E0_PHY_CONTROL_REGS_IDLE_PAD_ENABLE0_RESERVED0_SHIFT 11 1030 1031 /* DDR34_E0_PHY_CONTROL_REGS :: IDLE_PAD_ENABLE0 :: IO_IDLE_ENABLE [10:00] */ 1032 #define DDR34_E0_PHY_CONTROL_REGS_IDLE_PAD_ENABLE0_IO_IDLE_ENABLE_MASK 0x000007ff 1033 #define DDR34_E0_PHY_CONTROL_REGS_IDLE_PAD_ENABLE0_IO_IDLE_ENABLE_ALIGN 0 1034 #define DDR34_E0_PHY_CONTROL_REGS_IDLE_PAD_ENABLE0_IO_IDLE_ENABLE_BITS 11 1035 #define DDR34_E0_PHY_CONTROL_REGS_IDLE_PAD_ENABLE0_IO_IDLE_ENABLE_SHIFT 0 1036 #define DDR34_E0_PHY_CONTROL_REGS_IDLE_PAD_ENABLE0_IO_IDLE_ENABLE_DEFAULT 0x00000000 1037 1038 /*************************************************************************** 1039 *IDLE_PAD_ENABLE1 - Idle mode pad enable register 1040 */ 1041 /* DDR34_E0_PHY_CONTROL_REGS :: IDLE_PAD_ENABLE1 :: reserved0 [31:22] */ 1042 #define DDR34_E0_PHY_CONTROL_REGS_IDLE_PAD_ENABLE1_RESERVED0_MASK 0xffc00000 1043 #define DDR34_E0_PHY_CONTROL_REGS_IDLE_PAD_ENABLE1_RESERVED0_ALIGN 0 1044 #define DDR34_E0_PHY_CONTROL_REGS_IDLE_PAD_ENABLE1_RESERVED0_BITS 10 1045 #define DDR34_E0_PHY_CONTROL_REGS_IDLE_PAD_ENABLE1_RESERVED0_SHIFT 22 1046 1047 /* DDR34_E0_PHY_CONTROL_REGS :: IDLE_PAD_ENABLE1 :: IO_IDLE_ENABLE [21:00] */ 1048 #define DDR34_E0_PHY_CONTROL_REGS_IDLE_PAD_ENABLE1_IO_IDLE_ENABLE_MASK 0x003fffff 1049 #define DDR34_E0_PHY_CONTROL_REGS_IDLE_PAD_ENABLE1_IO_IDLE_ENABLE_ALIGN 0 1050 #define DDR34_E0_PHY_CONTROL_REGS_IDLE_PAD_ENABLE1_IO_IDLE_ENABLE_BITS 22 1051 #define DDR34_E0_PHY_CONTROL_REGS_IDLE_PAD_ENABLE1_IO_IDLE_ENABLE_SHIFT 0 1052 #define DDR34_E0_PHY_CONTROL_REGS_IDLE_PAD_ENABLE1_IO_IDLE_ENABLE_DEFAULT 0x00000000 1053 1054 /*************************************************************************** 1055 *DRIVE_PAD_CTL - PVT Compensation control register 1056 */ 1057 /* DDR34_E0_PHY_CONTROL_REGS :: DRIVE_PAD_CTL :: reserved0 [31:30] */ 1058 #define DDR34_E0_PHY_CONTROL_REGS_DRIVE_PAD_CTL_RESERVED0_MASK 0xc0000000 1059 #define DDR34_E0_PHY_CONTROL_REGS_DRIVE_PAD_CTL_RESERVED0_ALIGN 0 1060 #define DDR34_E0_PHY_CONTROL_REGS_DRIVE_PAD_CTL_RESERVED0_BITS 2 1061 #define DDR34_E0_PHY_CONTROL_REGS_DRIVE_PAD_CTL_RESERVED0_SHIFT 30 1062 1063 /* DDR34_E0_PHY_CONTROL_REGS :: DRIVE_PAD_CTL :: ADDR_CTL_PD_IDLE_STRENGTH [29:25] */ 1064 #define DDR34_E0_PHY_CONTROL_REGS_DRIVE_PAD_CTL_ADDR_CTL_PD_IDLE_STRENGTH_MASK 0x3e000000 1065 #define DDR34_E0_PHY_CONTROL_REGS_DRIVE_PAD_CTL_ADDR_CTL_PD_IDLE_STRENGTH_ALIGN 0 1066 #define DDR34_E0_PHY_CONTROL_REGS_DRIVE_PAD_CTL_ADDR_CTL_PD_IDLE_STRENGTH_BITS 5 1067 #define DDR34_E0_PHY_CONTROL_REGS_DRIVE_PAD_CTL_ADDR_CTL_PD_IDLE_STRENGTH_SHIFT 25 1068 #define DDR34_E0_PHY_CONTROL_REGS_DRIVE_PAD_CTL_ADDR_CTL_PD_IDLE_STRENGTH_DEFAULT 0x0000001f 1069 1070 /* DDR34_E0_PHY_CONTROL_REGS :: DRIVE_PAD_CTL :: ADDR_CTL_ND_IDLE_STRENGTH [24:20] */ 1071 #define DDR34_E0_PHY_CONTROL_REGS_DRIVE_PAD_CTL_ADDR_CTL_ND_IDLE_STRENGTH_MASK 0x01f00000 1072 #define DDR34_E0_PHY_CONTROL_REGS_DRIVE_PAD_CTL_ADDR_CTL_ND_IDLE_STRENGTH_ALIGN 0 1073 #define DDR34_E0_PHY_CONTROL_REGS_DRIVE_PAD_CTL_ADDR_CTL_ND_IDLE_STRENGTH_BITS 5 1074 #define DDR34_E0_PHY_CONTROL_REGS_DRIVE_PAD_CTL_ADDR_CTL_ND_IDLE_STRENGTH_SHIFT 20 1075 #define DDR34_E0_PHY_CONTROL_REGS_DRIVE_PAD_CTL_ADDR_CTL_ND_IDLE_STRENGTH_DEFAULT 0x0000001f 1076 1077 /* DDR34_E0_PHY_CONTROL_REGS :: DRIVE_PAD_CTL :: ADDR_CTL_PD_TERM_STRENGTH [19:15] */ 1078 #define DDR34_E0_PHY_CONTROL_REGS_DRIVE_PAD_CTL_ADDR_CTL_PD_TERM_STRENGTH_MASK 0x000f8000 1079 #define DDR34_E0_PHY_CONTROL_REGS_DRIVE_PAD_CTL_ADDR_CTL_PD_TERM_STRENGTH_ALIGN 0 1080 #define DDR34_E0_PHY_CONTROL_REGS_DRIVE_PAD_CTL_ADDR_CTL_PD_TERM_STRENGTH_BITS 5 1081 #define DDR34_E0_PHY_CONTROL_REGS_DRIVE_PAD_CTL_ADDR_CTL_PD_TERM_STRENGTH_SHIFT 15 1082 #define DDR34_E0_PHY_CONTROL_REGS_DRIVE_PAD_CTL_ADDR_CTL_PD_TERM_STRENGTH_DEFAULT 0x00000006 1083 1084 /* DDR34_E0_PHY_CONTROL_REGS :: DRIVE_PAD_CTL :: ADDR_CTL_ND_TERM_STRENGTH [14:10] */ 1085 #define DDR34_E0_PHY_CONTROL_REGS_DRIVE_PAD_CTL_ADDR_CTL_ND_TERM_STRENGTH_MASK 0x00007c00 1086 #define DDR34_E0_PHY_CONTROL_REGS_DRIVE_PAD_CTL_ADDR_CTL_ND_TERM_STRENGTH_ALIGN 0 1087 #define DDR34_E0_PHY_CONTROL_REGS_DRIVE_PAD_CTL_ADDR_CTL_ND_TERM_STRENGTH_BITS 5 1088 #define DDR34_E0_PHY_CONTROL_REGS_DRIVE_PAD_CTL_ADDR_CTL_ND_TERM_STRENGTH_SHIFT 10 1089 #define DDR34_E0_PHY_CONTROL_REGS_DRIVE_PAD_CTL_ADDR_CTL_ND_TERM_STRENGTH_DEFAULT 0x00000006 1090 1091 /* DDR34_E0_PHY_CONTROL_REGS :: DRIVE_PAD_CTL :: ADDR_CTL_PD_STRENGTH [09:05] */ 1092 #define DDR34_E0_PHY_CONTROL_REGS_DRIVE_PAD_CTL_ADDR_CTL_PD_STRENGTH_MASK 0x000003e0 1093 #define DDR34_E0_PHY_CONTROL_REGS_DRIVE_PAD_CTL_ADDR_CTL_PD_STRENGTH_ALIGN 0 1094 #define DDR34_E0_PHY_CONTROL_REGS_DRIVE_PAD_CTL_ADDR_CTL_PD_STRENGTH_BITS 5 1095 #define DDR34_E0_PHY_CONTROL_REGS_DRIVE_PAD_CTL_ADDR_CTL_PD_STRENGTH_SHIFT 5 1096 #define DDR34_E0_PHY_CONTROL_REGS_DRIVE_PAD_CTL_ADDR_CTL_PD_STRENGTH_DEFAULT 0x0000001f 1097 1098 /* DDR34_E0_PHY_CONTROL_REGS :: DRIVE_PAD_CTL :: ADDR_CTL_ND_STRENGTH [04:00] */ 1099 #define DDR34_E0_PHY_CONTROL_REGS_DRIVE_PAD_CTL_ADDR_CTL_ND_STRENGTH_MASK 0x0000001f 1100 #define DDR34_E0_PHY_CONTROL_REGS_DRIVE_PAD_CTL_ADDR_CTL_ND_STRENGTH_ALIGN 0 1101 #define DDR34_E0_PHY_CONTROL_REGS_DRIVE_PAD_CTL_ADDR_CTL_ND_STRENGTH_BITS 5 1102 #define DDR34_E0_PHY_CONTROL_REGS_DRIVE_PAD_CTL_ADDR_CTL_ND_STRENGTH_SHIFT 0 1103 #define DDR34_E0_PHY_CONTROL_REGS_DRIVE_PAD_CTL_ADDR_CTL_ND_STRENGTH_DEFAULT 0x0000001f 1104 1105 /*************************************************************************** 1106 *STATIC_PAD_CTL - pad rx and tx characteristics control register 1107 */ 1108 /* DDR34_E0_PHY_CONTROL_REGS :: STATIC_PAD_CTL :: reserved0 [31:28] */ 1109 #define DDR34_E0_PHY_CONTROL_REGS_STATIC_PAD_CTL_RESERVED0_MASK 0xf0000000 1110 #define DDR34_E0_PHY_CONTROL_REGS_STATIC_PAD_CTL_RESERVED0_ALIGN 0 1111 #define DDR34_E0_PHY_CONTROL_REGS_STATIC_PAD_CTL_RESERVED0_BITS 4 1112 #define DDR34_E0_PHY_CONTROL_REGS_STATIC_PAD_CTL_RESERVED0_SHIFT 28 1113 1114 /* DDR34_E0_PHY_CONTROL_REGS :: STATIC_PAD_CTL :: AUTO_OEB [27:27] */ 1115 #define DDR34_E0_PHY_CONTROL_REGS_STATIC_PAD_CTL_AUTO_OEB_MASK 0x08000000 1116 #define DDR34_E0_PHY_CONTROL_REGS_STATIC_PAD_CTL_AUTO_OEB_ALIGN 0 1117 #define DDR34_E0_PHY_CONTROL_REGS_STATIC_PAD_CTL_AUTO_OEB_BITS 1 1118 #define DDR34_E0_PHY_CONTROL_REGS_STATIC_PAD_CTL_AUTO_OEB_SHIFT 27 1119 #define DDR34_E0_PHY_CONTROL_REGS_STATIC_PAD_CTL_AUTO_OEB_DEFAULT 0x00000000 1120 1121 /* DDR34_E0_PHY_CONTROL_REGS :: STATIC_PAD_CTL :: IDDQ_GDDR5 [26:26] */ 1122 #define DDR34_E0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_GDDR5_MASK 0x04000000 1123 #define DDR34_E0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_GDDR5_ALIGN 0 1124 #define DDR34_E0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_GDDR5_BITS 1 1125 #define DDR34_E0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_GDDR5_SHIFT 26 1126 #define DDR34_E0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_GDDR5_DEFAULT 0x00000000 1127 1128 /* DDR34_E0_PHY_CONTROL_REGS :: STATIC_PAD_CTL :: IDDQ_LPDDR [25:25] */ 1129 #define DDR34_E0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_LPDDR_MASK 0x02000000 1130 #define DDR34_E0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_LPDDR_ALIGN 0 1131 #define DDR34_E0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_LPDDR_BITS 1 1132 #define DDR34_E0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_LPDDR_SHIFT 25 1133 #define DDR34_E0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_LPDDR_DEFAULT 0x00000000 1134 1135 /* DDR34_E0_PHY_CONTROL_REGS :: STATIC_PAD_CTL :: IDDQ_CLK1 [24:24] */ 1136 #define DDR34_E0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_CLK1_MASK 0x01000000 1137 #define DDR34_E0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_CLK1_ALIGN 0 1138 #define DDR34_E0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_CLK1_BITS 1 1139 #define DDR34_E0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_CLK1_SHIFT 24 1140 #define DDR34_E0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_CLK1_DEFAULT 0x00000000 1141 1142 /* DDR34_E0_PHY_CONTROL_REGS :: STATIC_PAD_CTL :: IDDQ_CLK0 [23:23] */ 1143 #define DDR34_E0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_CLK0_MASK 0x00800000 1144 #define DDR34_E0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_CLK0_ALIGN 0 1145 #define DDR34_E0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_CLK0_BITS 1 1146 #define DDR34_E0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_CLK0_SHIFT 23 1147 #define DDR34_E0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_CLK0_DEFAULT 0x00000000 1148 1149 /* DDR34_E0_PHY_CONTROL_REGS :: STATIC_PAD_CTL :: IDDQ_ODT [22:22] */ 1150 #define DDR34_E0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_ODT_MASK 0x00400000 1151 #define DDR34_E0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_ODT_ALIGN 0 1152 #define DDR34_E0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_ODT_BITS 1 1153 #define DDR34_E0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_ODT_SHIFT 22 1154 #define DDR34_E0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_ODT_DEFAULT 0x00000000 1155 1156 /* DDR34_E0_PHY_CONTROL_REGS :: STATIC_PAD_CTL :: IDDQ_PAR [21:21] */ 1157 #define DDR34_E0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_PAR_MASK 0x00200000 1158 #define DDR34_E0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_PAR_ALIGN 0 1159 #define DDR34_E0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_PAR_BITS 1 1160 #define DDR34_E0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_PAR_SHIFT 21 1161 #define DDR34_E0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_PAR_DEFAULT 0x00000000 1162 1163 /* DDR34_E0_PHY_CONTROL_REGS :: STATIC_PAD_CTL :: IDDQ_BA [20:20] */ 1164 #define DDR34_E0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_BA_MASK 0x00100000 1165 #define DDR34_E0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_BA_ALIGN 0 1166 #define DDR34_E0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_BA_BITS 1 1167 #define DDR34_E0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_BA_SHIFT 20 1168 #define DDR34_E0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_BA_DEFAULT 0x00000000 1169 1170 /* DDR34_E0_PHY_CONTROL_REGS :: STATIC_PAD_CTL :: IDDQ_AUX2 [19:19] */ 1171 #define DDR34_E0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_AUX2_MASK 0x00080000 1172 #define DDR34_E0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_AUX2_ALIGN 0 1173 #define DDR34_E0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_AUX2_BITS 1 1174 #define DDR34_E0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_AUX2_SHIFT 19 1175 #define DDR34_E0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_AUX2_DEFAULT 0x00000000 1176 1177 /* DDR34_E0_PHY_CONTROL_REGS :: STATIC_PAD_CTL :: IDDQ_AUX1 [18:18] */ 1178 #define DDR34_E0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_AUX1_MASK 0x00040000 1179 #define DDR34_E0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_AUX1_ALIGN 0 1180 #define DDR34_E0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_AUX1_BITS 1 1181 #define DDR34_E0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_AUX1_SHIFT 18 1182 #define DDR34_E0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_AUX1_DEFAULT 0x00000000 1183 1184 /* DDR34_E0_PHY_CONTROL_REGS :: STATIC_PAD_CTL :: IDDQ_AUX0 [17:17] */ 1185 #define DDR34_E0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_AUX0_MASK 0x00020000 1186 #define DDR34_E0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_AUX0_ALIGN 0 1187 #define DDR34_E0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_AUX0_BITS 1 1188 #define DDR34_E0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_AUX0_SHIFT 17 1189 #define DDR34_E0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_AUX0_DEFAULT 0x00000000 1190 1191 /* DDR34_E0_PHY_CONTROL_REGS :: STATIC_PAD_CTL :: IDDQ_CS1 [16:16] */ 1192 #define DDR34_E0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_CS1_MASK 0x00010000 1193 #define DDR34_E0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_CS1_ALIGN 0 1194 #define DDR34_E0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_CS1_BITS 1 1195 #define DDR34_E0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_CS1_SHIFT 16 1196 #define DDR34_E0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_CS1_DEFAULT 0x00000000 1197 1198 /* DDR34_E0_PHY_CONTROL_REGS :: STATIC_PAD_CTL :: IDDQ_A15 [15:15] */ 1199 #define DDR34_E0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_A15_MASK 0x00008000 1200 #define DDR34_E0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_A15_ALIGN 0 1201 #define DDR34_E0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_A15_BITS 1 1202 #define DDR34_E0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_A15_SHIFT 15 1203 #define DDR34_E0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_A15_DEFAULT 0x00000000 1204 1205 /* DDR34_E0_PHY_CONTROL_REGS :: STATIC_PAD_CTL :: IDDQ_A14 [14:14] */ 1206 #define DDR34_E0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_A14_MASK 0x00004000 1207 #define DDR34_E0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_A14_ALIGN 0 1208 #define DDR34_E0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_A14_BITS 1 1209 #define DDR34_E0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_A14_SHIFT 14 1210 #define DDR34_E0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_A14_DEFAULT 0x00000000 1211 1212 /* DDR34_E0_PHY_CONTROL_REGS :: STATIC_PAD_CTL :: IDDQ_A13 [13:13] */ 1213 #define DDR34_E0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_A13_MASK 0x00002000 1214 #define DDR34_E0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_A13_ALIGN 0 1215 #define DDR34_E0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_A13_BITS 1 1216 #define DDR34_E0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_A13_SHIFT 13 1217 #define DDR34_E0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_A13_DEFAULT 0x00000000 1218 1219 /* DDR34_E0_PHY_CONTROL_REGS :: STATIC_PAD_CTL :: IDDQ_A12 [12:12] */ 1220 #define DDR34_E0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_A12_MASK 0x00001000 1221 #define DDR34_E0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_A12_ALIGN 0 1222 #define DDR34_E0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_A12_BITS 1 1223 #define DDR34_E0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_A12_SHIFT 12 1224 #define DDR34_E0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_A12_DEFAULT 0x00000000 1225 1226 /* DDR34_E0_PHY_CONTROL_REGS :: STATIC_PAD_CTL :: IDDQ_A11 [11:11] */ 1227 #define DDR34_E0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_A11_MASK 0x00000800 1228 #define DDR34_E0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_A11_ALIGN 0 1229 #define DDR34_E0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_A11_BITS 1 1230 #define DDR34_E0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_A11_SHIFT 11 1231 #define DDR34_E0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_A11_DEFAULT 0x00000000 1232 1233 /* DDR34_E0_PHY_CONTROL_REGS :: STATIC_PAD_CTL :: IDDQ_A10 [10:10] */ 1234 #define DDR34_E0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_A10_MASK 0x00000400 1235 #define DDR34_E0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_A10_ALIGN 0 1236 #define DDR34_E0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_A10_BITS 1 1237 #define DDR34_E0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_A10_SHIFT 10 1238 #define DDR34_E0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_A10_DEFAULT 0x00000000 1239 1240 /* DDR34_E0_PHY_CONTROL_REGS :: STATIC_PAD_CTL :: IDDQ_A09 [09:09] */ 1241 #define DDR34_E0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_A09_MASK 0x00000200 1242 #define DDR34_E0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_A09_ALIGN 0 1243 #define DDR34_E0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_A09_BITS 1 1244 #define DDR34_E0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_A09_SHIFT 9 1245 #define DDR34_E0_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_A09_DEFAULT 0x00000000 1246 1247 /* DDR34_E0_PHY_CONTROL_REGS :: STATIC_PAD_CTL :: reserved1 [08:02] */ 1248 #define DDR34_E0_PHY_CONTROL_REGS_STATIC_PAD_CTL_RESERVED1_MASK 0x000001fc 1249 #define DDR34_E0_PHY_CONTROL_REGS_STATIC_PAD_CTL_RESERVED1_ALIGN 0 1250 #define DDR34_E0_PHY_CONTROL_REGS_STATIC_PAD_CTL_RESERVED1_BITS 7 1251 #define DDR34_E0_PHY_CONTROL_REGS_STATIC_PAD_CTL_RESERVED1_SHIFT 2 1252 1253 /* DDR34_E0_PHY_CONTROL_REGS :: STATIC_PAD_CTL :: RX_MODE [01:00] */ 1254 #define DDR34_E0_PHY_CONTROL_REGS_STATIC_PAD_CTL_RX_MODE_MASK 0x00000003 1255 #define DDR34_E0_PHY_CONTROL_REGS_STATIC_PAD_CTL_RX_MODE_ALIGN 0 1256 #define DDR34_E0_PHY_CONTROL_REGS_STATIC_PAD_CTL_RX_MODE_BITS 2 1257 #define DDR34_E0_PHY_CONTROL_REGS_STATIC_PAD_CTL_RX_MODE_SHIFT 0 1258 #define DDR34_E0_PHY_CONTROL_REGS_STATIC_PAD_CTL_RX_MODE_DEFAULT 0x00000000 1259 1260 /*************************************************************************** 1261 *DRAM_CONFIG - DRAM configuration register 1262 */ 1263 /* DDR34_E0_PHY_CONTROL_REGS :: DRAM_CONFIG :: INIT_MODE [31:31] */ 1264 #define DDR34_E0_PHY_CONTROL_REGS_DRAM_CONFIG_INIT_MODE_MASK 0x80000000 1265 #define DDR34_E0_PHY_CONTROL_REGS_DRAM_CONFIG_INIT_MODE_ALIGN 0 1266 #define DDR34_E0_PHY_CONTROL_REGS_DRAM_CONFIG_INIT_MODE_BITS 1 1267 #define DDR34_E0_PHY_CONTROL_REGS_DRAM_CONFIG_INIT_MODE_SHIFT 31 1268 #define DDR34_E0_PHY_CONTROL_REGS_DRAM_CONFIG_INIT_MODE_DEFAULT 0x00000000 1269 1270 /* DDR34_E0_PHY_CONTROL_REGS :: DRAM_CONFIG :: reserved0 [30:28] */ 1271 #define DDR34_E0_PHY_CONTROL_REGS_DRAM_CONFIG_RESERVED0_MASK 0x70000000 1272 #define DDR34_E0_PHY_CONTROL_REGS_DRAM_CONFIG_RESERVED0_ALIGN 0 1273 #define DDR34_E0_PHY_CONTROL_REGS_DRAM_CONFIG_RESERVED0_BITS 3 1274 #define DDR34_E0_PHY_CONTROL_REGS_DRAM_CONFIG_RESERVED0_SHIFT 28 1275 1276 /* DDR34_E0_PHY_CONTROL_REGS :: DRAM_CONFIG :: ECC_ENABLED [27:27] */ 1277 #define DDR34_E0_PHY_CONTROL_REGS_DRAM_CONFIG_ECC_ENABLED_MASK 0x08000000 1278 #define DDR34_E0_PHY_CONTROL_REGS_DRAM_CONFIG_ECC_ENABLED_ALIGN 0 1279 #define DDR34_E0_PHY_CONTROL_REGS_DRAM_CONFIG_ECC_ENABLED_BITS 1 1280 #define DDR34_E0_PHY_CONTROL_REGS_DRAM_CONFIG_ECC_ENABLED_SHIFT 27 1281 #define DDR34_E0_PHY_CONTROL_REGS_DRAM_CONFIG_ECC_ENABLED_DEFAULT 0x00000000 1282 1283 /* DDR34_E0_PHY_CONTROL_REGS :: DRAM_CONFIG :: SPLIT_DQ_BUS [26:26] */ 1284 #define DDR34_E0_PHY_CONTROL_REGS_DRAM_CONFIG_SPLIT_DQ_BUS_MASK 0x04000000 1285 #define DDR34_E0_PHY_CONTROL_REGS_DRAM_CONFIG_SPLIT_DQ_BUS_ALIGN 0 1286 #define DDR34_E0_PHY_CONTROL_REGS_DRAM_CONFIG_SPLIT_DQ_BUS_BITS 1 1287 #define DDR34_E0_PHY_CONTROL_REGS_DRAM_CONFIG_SPLIT_DQ_BUS_SHIFT 26 1288 #define DDR34_E0_PHY_CONTROL_REGS_DRAM_CONFIG_SPLIT_DQ_BUS_DEFAULT 0x00000000 1289 1290 /* DDR34_E0_PHY_CONTROL_REGS :: DRAM_CONFIG :: BUS16 [25:25] */ 1291 #define DDR34_E0_PHY_CONTROL_REGS_DRAM_CONFIG_BUS16_MASK 0x02000000 1292 #define DDR34_E0_PHY_CONTROL_REGS_DRAM_CONFIG_BUS16_ALIGN 0 1293 #define DDR34_E0_PHY_CONTROL_REGS_DRAM_CONFIG_BUS16_BITS 1 1294 #define DDR34_E0_PHY_CONTROL_REGS_DRAM_CONFIG_BUS16_SHIFT 25 1295 #define DDR34_E0_PHY_CONTROL_REGS_DRAM_CONFIG_BUS16_DEFAULT 0x00000000 1296 1297 /* DDR34_E0_PHY_CONTROL_REGS :: DRAM_CONFIG :: BUS8 [24:24] */ 1298 #define DDR34_E0_PHY_CONTROL_REGS_DRAM_CONFIG_BUS8_MASK 0x01000000 1299 #define DDR34_E0_PHY_CONTROL_REGS_DRAM_CONFIG_BUS8_ALIGN 0 1300 #define DDR34_E0_PHY_CONTROL_REGS_DRAM_CONFIG_BUS8_BITS 1 1301 #define DDR34_E0_PHY_CONTROL_REGS_DRAM_CONFIG_BUS8_SHIFT 24 1302 #define DDR34_E0_PHY_CONTROL_REGS_DRAM_CONFIG_BUS8_DEFAULT 0x00000000 1303 1304 /* DDR34_E0_PHY_CONTROL_REGS :: DRAM_CONFIG :: reserved1 [23:16] */ 1305 #define DDR34_E0_PHY_CONTROL_REGS_DRAM_CONFIG_RESERVED1_MASK 0x00ff0000 1306 #define DDR34_E0_PHY_CONTROL_REGS_DRAM_CONFIG_RESERVED1_ALIGN 0 1307 #define DDR34_E0_PHY_CONTROL_REGS_DRAM_CONFIG_RESERVED1_BITS 8 1308 #define DDR34_E0_PHY_CONTROL_REGS_DRAM_CONFIG_RESERVED1_SHIFT 16 1309 1310 /* DDR34_E0_PHY_CONTROL_REGS :: DRAM_CONFIG :: EDC_MODE [15:15] */ 1311 #define DDR34_E0_PHY_CONTROL_REGS_DRAM_CONFIG_EDC_MODE_MASK 0x00008000 1312 #define DDR34_E0_PHY_CONTROL_REGS_DRAM_CONFIG_EDC_MODE_ALIGN 0 1313 #define DDR34_E0_PHY_CONTROL_REGS_DRAM_CONFIG_EDC_MODE_BITS 1 1314 #define DDR34_E0_PHY_CONTROL_REGS_DRAM_CONFIG_EDC_MODE_SHIFT 15 1315 #define DDR34_E0_PHY_CONTROL_REGS_DRAM_CONFIG_EDC_MODE_DEFAULT 0x00000000 1316 1317 /* DDR34_E0_PHY_CONTROL_REGS :: DRAM_CONFIG :: RDQS_MODE [14:14] */ 1318 #define DDR34_E0_PHY_CONTROL_REGS_DRAM_CONFIG_RDQS_MODE_MASK 0x00004000 1319 #define DDR34_E0_PHY_CONTROL_REGS_DRAM_CONFIG_RDQS_MODE_ALIGN 0 1320 #define DDR34_E0_PHY_CONTROL_REGS_DRAM_CONFIG_RDQS_MODE_BITS 1 1321 #define DDR34_E0_PHY_CONTROL_REGS_DRAM_CONFIG_RDQS_MODE_SHIFT 14 1322 #define DDR34_E0_PHY_CONTROL_REGS_DRAM_CONFIG_RDQS_MODE_DEFAULT 0x00000000 1323 1324 /* DDR34_E0_PHY_CONTROL_REGS :: DRAM_CONFIG :: GROUP_BITS [13:12] */ 1325 #define DDR34_E0_PHY_CONTROL_REGS_DRAM_CONFIG_GROUP_BITS_MASK 0x00003000 1326 #define DDR34_E0_PHY_CONTROL_REGS_DRAM_CONFIG_GROUP_BITS_ALIGN 0 1327 #define DDR34_E0_PHY_CONTROL_REGS_DRAM_CONFIG_GROUP_BITS_BITS 2 1328 #define DDR34_E0_PHY_CONTROL_REGS_DRAM_CONFIG_GROUP_BITS_SHIFT 12 1329 #define DDR34_E0_PHY_CONTROL_REGS_DRAM_CONFIG_GROUP_BITS_DEFAULT 0x00000000 1330 1331 /* DDR34_E0_PHY_CONTROL_REGS :: DRAM_CONFIG :: BANK_BITS [11:10] */ 1332 #define DDR34_E0_PHY_CONTROL_REGS_DRAM_CONFIG_BANK_BITS_MASK 0x00000c00 1333 #define DDR34_E0_PHY_CONTROL_REGS_DRAM_CONFIG_BANK_BITS_ALIGN 0 1334 #define DDR34_E0_PHY_CONTROL_REGS_DRAM_CONFIG_BANK_BITS_BITS 2 1335 #define DDR34_E0_PHY_CONTROL_REGS_DRAM_CONFIG_BANK_BITS_SHIFT 10 1336 #define DDR34_E0_PHY_CONTROL_REGS_DRAM_CONFIG_BANK_BITS_DEFAULT 0x00000000 1337 1338 /* DDR34_E0_PHY_CONTROL_REGS :: DRAM_CONFIG :: COL_BITS [09:08] */ 1339 #define DDR34_E0_PHY_CONTROL_REGS_DRAM_CONFIG_COL_BITS_MASK 0x00000300 1340 #define DDR34_E0_PHY_CONTROL_REGS_DRAM_CONFIG_COL_BITS_ALIGN 0 1341 #define DDR34_E0_PHY_CONTROL_REGS_DRAM_CONFIG_COL_BITS_BITS 2 1342 #define DDR34_E0_PHY_CONTROL_REGS_DRAM_CONFIG_COL_BITS_SHIFT 8 1343 #define DDR34_E0_PHY_CONTROL_REGS_DRAM_CONFIG_COL_BITS_DEFAULT 0x00000000 1344 1345 /* DDR34_E0_PHY_CONTROL_REGS :: DRAM_CONFIG :: ROW_BITS [07:04] */ 1346 #define DDR34_E0_PHY_CONTROL_REGS_DRAM_CONFIG_ROW_BITS_MASK 0x000000f0 1347 #define DDR34_E0_PHY_CONTROL_REGS_DRAM_CONFIG_ROW_BITS_ALIGN 0 1348 #define DDR34_E0_PHY_CONTROL_REGS_DRAM_CONFIG_ROW_BITS_BITS 4 1349 #define DDR34_E0_PHY_CONTROL_REGS_DRAM_CONFIG_ROW_BITS_SHIFT 4 1350 #define DDR34_E0_PHY_CONTROL_REGS_DRAM_CONFIG_ROW_BITS_DEFAULT 0x00000000 1351 1352 /* DDR34_E0_PHY_CONTROL_REGS :: DRAM_CONFIG :: DRAM_TYPE [03:00] */ 1353 #define DDR34_E0_PHY_CONTROL_REGS_DRAM_CONFIG_DRAM_TYPE_MASK 0x0000000f 1354 #define DDR34_E0_PHY_CONTROL_REGS_DRAM_CONFIG_DRAM_TYPE_ALIGN 0 1355 #define DDR34_E0_PHY_CONTROL_REGS_DRAM_CONFIG_DRAM_TYPE_BITS 4 1356 #define DDR34_E0_PHY_CONTROL_REGS_DRAM_CONFIG_DRAM_TYPE_SHIFT 0 1357 #define DDR34_E0_PHY_CONTROL_REGS_DRAM_CONFIG_DRAM_TYPE_DEFAULT 0x00000000 1358 1359 /*************************************************************************** 1360 *DRAM_TIMING1 - DRAM timing register #1 1361 */ 1362 /* DDR34_E0_PHY_CONTROL_REGS :: DRAM_TIMING1 :: TRAS [31:24] */ 1363 #define DDR34_E0_PHY_CONTROL_REGS_DRAM_TIMING1_TRAS_MASK 0xff000000 1364 #define DDR34_E0_PHY_CONTROL_REGS_DRAM_TIMING1_TRAS_ALIGN 0 1365 #define DDR34_E0_PHY_CONTROL_REGS_DRAM_TIMING1_TRAS_BITS 8 1366 #define DDR34_E0_PHY_CONTROL_REGS_DRAM_TIMING1_TRAS_SHIFT 24 1367 #define DDR34_E0_PHY_CONTROL_REGS_DRAM_TIMING1_TRAS_DEFAULT 0x00000000 1368 1369 /* DDR34_E0_PHY_CONTROL_REGS :: DRAM_TIMING1 :: TRRD [23:16] */ 1370 #define DDR34_E0_PHY_CONTROL_REGS_DRAM_TIMING1_TRRD_MASK 0x00ff0000 1371 #define DDR34_E0_PHY_CONTROL_REGS_DRAM_TIMING1_TRRD_ALIGN 0 1372 #define DDR34_E0_PHY_CONTROL_REGS_DRAM_TIMING1_TRRD_BITS 8 1373 #define DDR34_E0_PHY_CONTROL_REGS_DRAM_TIMING1_TRRD_SHIFT 16 1374 #define DDR34_E0_PHY_CONTROL_REGS_DRAM_TIMING1_TRRD_DEFAULT 0x00000000 1375 1376 /* DDR34_E0_PHY_CONTROL_REGS :: DRAM_TIMING1 :: TRP [15:08] */ 1377 #define DDR34_E0_PHY_CONTROL_REGS_DRAM_TIMING1_TRP_MASK 0x0000ff00 1378 #define DDR34_E0_PHY_CONTROL_REGS_DRAM_TIMING1_TRP_ALIGN 0 1379 #define DDR34_E0_PHY_CONTROL_REGS_DRAM_TIMING1_TRP_BITS 8 1380 #define DDR34_E0_PHY_CONTROL_REGS_DRAM_TIMING1_TRP_SHIFT 8 1381 #define DDR34_E0_PHY_CONTROL_REGS_DRAM_TIMING1_TRP_DEFAULT 0x00000000 1382 1383 /* DDR34_E0_PHY_CONTROL_REGS :: DRAM_TIMING1 :: TRCD [07:00] */ 1384 #define DDR34_E0_PHY_CONTROL_REGS_DRAM_TIMING1_TRCD_MASK 0x000000ff 1385 #define DDR34_E0_PHY_CONTROL_REGS_DRAM_TIMING1_TRCD_ALIGN 0 1386 #define DDR34_E0_PHY_CONTROL_REGS_DRAM_TIMING1_TRCD_BITS 8 1387 #define DDR34_E0_PHY_CONTROL_REGS_DRAM_TIMING1_TRCD_SHIFT 0 1388 #define DDR34_E0_PHY_CONTROL_REGS_DRAM_TIMING1_TRCD_DEFAULT 0x00000000 1389 1390 /*************************************************************************** 1391 *DRAM_TIMING2 - DRAM timing register #2 1392 */ 1393 /* DDR34_E0_PHY_CONTROL_REGS :: DRAM_TIMING2 :: TRTP [31:24] */ 1394 #define DDR34_E0_PHY_CONTROL_REGS_DRAM_TIMING2_TRTP_MASK 0xff000000 1395 #define DDR34_E0_PHY_CONTROL_REGS_DRAM_TIMING2_TRTP_ALIGN 0 1396 #define DDR34_E0_PHY_CONTROL_REGS_DRAM_TIMING2_TRTP_BITS 8 1397 #define DDR34_E0_PHY_CONTROL_REGS_DRAM_TIMING2_TRTP_SHIFT 24 1398 #define DDR34_E0_PHY_CONTROL_REGS_DRAM_TIMING2_TRTP_DEFAULT 0x00000000 1399 1400 /* DDR34_E0_PHY_CONTROL_REGS :: DRAM_TIMING2 :: TWR [23:16] */ 1401 #define DDR34_E0_PHY_CONTROL_REGS_DRAM_TIMING2_TWR_MASK 0x00ff0000 1402 #define DDR34_E0_PHY_CONTROL_REGS_DRAM_TIMING2_TWR_ALIGN 0 1403 #define DDR34_E0_PHY_CONTROL_REGS_DRAM_TIMING2_TWR_BITS 8 1404 #define DDR34_E0_PHY_CONTROL_REGS_DRAM_TIMING2_TWR_SHIFT 16 1405 #define DDR34_E0_PHY_CONTROL_REGS_DRAM_TIMING2_TWR_DEFAULT 0x00000000 1406 1407 /* DDR34_E0_PHY_CONTROL_REGS :: DRAM_TIMING2 :: TCWL [15:08] */ 1408 #define DDR34_E0_PHY_CONTROL_REGS_DRAM_TIMING2_TCWL_MASK 0x0000ff00 1409 #define DDR34_E0_PHY_CONTROL_REGS_DRAM_TIMING2_TCWL_ALIGN 0 1410 #define DDR34_E0_PHY_CONTROL_REGS_DRAM_TIMING2_TCWL_BITS 8 1411 #define DDR34_E0_PHY_CONTROL_REGS_DRAM_TIMING2_TCWL_SHIFT 8 1412 #define DDR34_E0_PHY_CONTROL_REGS_DRAM_TIMING2_TCWL_DEFAULT 0x00000000 1413 1414 /* DDR34_E0_PHY_CONTROL_REGS :: DRAM_TIMING2 :: TCAS [07:00] */ 1415 #define DDR34_E0_PHY_CONTROL_REGS_DRAM_TIMING2_TCAS_MASK 0x000000ff 1416 #define DDR34_E0_PHY_CONTROL_REGS_DRAM_TIMING2_TCAS_ALIGN 0 1417 #define DDR34_E0_PHY_CONTROL_REGS_DRAM_TIMING2_TCAS_BITS 8 1418 #define DDR34_E0_PHY_CONTROL_REGS_DRAM_TIMING2_TCAS_SHIFT 0 1419 #define DDR34_E0_PHY_CONTROL_REGS_DRAM_TIMING2_TCAS_DEFAULT 0x00000000 1420 1421 /*************************************************************************** 1422 *DRAM_TIMING3 - DRAM timing register #3 1423 */ 1424 /* DDR34_E0_PHY_CONTROL_REGS :: DRAM_TIMING3 :: reserved0 [31:24] */ 1425 #define DDR34_E0_PHY_CONTROL_REGS_DRAM_TIMING3_RESERVED0_MASK 0xff000000 1426 #define DDR34_E0_PHY_CONTROL_REGS_DRAM_TIMING3_RESERVED0_ALIGN 0 1427 #define DDR34_E0_PHY_CONTROL_REGS_DRAM_TIMING3_RESERVED0_BITS 8 1428 #define DDR34_E0_PHY_CONTROL_REGS_DRAM_TIMING3_RESERVED0_SHIFT 24 1429 1430 /* DDR34_E0_PHY_CONTROL_REGS :: DRAM_TIMING3 :: TCAL [23:20] */ 1431 #define DDR34_E0_PHY_CONTROL_REGS_DRAM_TIMING3_TCAL_MASK 0x00f00000 1432 #define DDR34_E0_PHY_CONTROL_REGS_DRAM_TIMING3_TCAL_ALIGN 0 1433 #define DDR34_E0_PHY_CONTROL_REGS_DRAM_TIMING3_TCAL_BITS 4 1434 #define DDR34_E0_PHY_CONTROL_REGS_DRAM_TIMING3_TCAL_SHIFT 20 1435 #define DDR34_E0_PHY_CONTROL_REGS_DRAM_TIMING3_TCAL_DEFAULT 0x00000000 1436 1437 /* DDR34_E0_PHY_CONTROL_REGS :: DRAM_TIMING3 :: TRTW [19:16] */ 1438 #define DDR34_E0_PHY_CONTROL_REGS_DRAM_TIMING3_TRTW_MASK 0x000f0000 1439 #define DDR34_E0_PHY_CONTROL_REGS_DRAM_TIMING3_TRTW_ALIGN 0 1440 #define DDR34_E0_PHY_CONTROL_REGS_DRAM_TIMING3_TRTW_BITS 4 1441 #define DDR34_E0_PHY_CONTROL_REGS_DRAM_TIMING3_TRTW_SHIFT 16 1442 #define DDR34_E0_PHY_CONTROL_REGS_DRAM_TIMING3_TRTW_DEFAULT 0x00000004 1443 1444 /* DDR34_E0_PHY_CONTROL_REGS :: DRAM_TIMING3 :: TWTR [15:12] */ 1445 #define DDR34_E0_PHY_CONTROL_REGS_DRAM_TIMING3_TWTR_MASK 0x0000f000 1446 #define DDR34_E0_PHY_CONTROL_REGS_DRAM_TIMING3_TWTR_ALIGN 0 1447 #define DDR34_E0_PHY_CONTROL_REGS_DRAM_TIMING3_TWTR_BITS 4 1448 #define DDR34_E0_PHY_CONTROL_REGS_DRAM_TIMING3_TWTR_SHIFT 12 1449 #define DDR34_E0_PHY_CONTROL_REGS_DRAM_TIMING3_TWTR_DEFAULT 0x00000000 1450 1451 /* DDR34_E0_PHY_CONTROL_REGS :: DRAM_TIMING3 :: TRFC [11:00] */ 1452 #define DDR34_E0_PHY_CONTROL_REGS_DRAM_TIMING3_TRFC_MASK 0x00000fff 1453 #define DDR34_E0_PHY_CONTROL_REGS_DRAM_TIMING3_TRFC_ALIGN 0 1454 #define DDR34_E0_PHY_CONTROL_REGS_DRAM_TIMING3_TRFC_BITS 12 1455 #define DDR34_E0_PHY_CONTROL_REGS_DRAM_TIMING3_TRFC_SHIFT 0 1456 #define DDR34_E0_PHY_CONTROL_REGS_DRAM_TIMING3_TRFC_DEFAULT 0x00000000 1457 1458 /*************************************************************************** 1459 *DRAM_TIMING4 - DRAM timing register #4 1460 */ 1461 /* DDR34_E0_PHY_CONTROL_REGS :: DRAM_TIMING4 :: temp [31:00] */ 1462 #define DDR34_E0_PHY_CONTROL_REGS_DRAM_TIMING4_temp_MASK 0xffffffff 1463 #define DDR34_E0_PHY_CONTROL_REGS_DRAM_TIMING4_temp_ALIGN 0 1464 #define DDR34_E0_PHY_CONTROL_REGS_DRAM_TIMING4_temp_BITS 32 1465 #define DDR34_E0_PHY_CONTROL_REGS_DRAM_TIMING4_temp_SHIFT 0 1466 #define DDR34_E0_PHY_CONTROL_REGS_DRAM_TIMING4_temp_DEFAULT 0x00000000 1467 1468 /*************************************************************************** 1469 *VDL_CALIBRATE - PHY VDL calibration control register 1470 */ 1471 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CALIBRATE :: reserved0 [31:09] */ 1472 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CALIBRATE_RESERVED0_MASK 0xfffffe00 1473 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CALIBRATE_RESERVED0_ALIGN 0 1474 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CALIBRATE_RESERVED0_BITS 23 1475 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CALIBRATE_RESERVED0_SHIFT 9 1476 1477 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CALIBRATE :: reserved_for_padding1 [08:06] */ 1478 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CALIBRATE_RESERVED_for_padding1_MASK 0x000001c0 1479 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CALIBRATE_RESERVED_for_padding1_ALIGN 0 1480 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CALIBRATE_RESERVED_for_padding1_BITS 3 1481 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CALIBRATE_RESERVED_for_padding1_SHIFT 6 1482 1483 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CALIBRATE :: HALF_STEPS [05:05] */ 1484 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CALIBRATE_HALF_STEPS_MASK 0x00000020 1485 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CALIBRATE_HALF_STEPS_ALIGN 0 1486 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CALIBRATE_HALF_STEPS_BITS 1 1487 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CALIBRATE_HALF_STEPS_SHIFT 5 1488 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CALIBRATE_HALF_STEPS_DEFAULT 0x00000000 1489 1490 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CALIBRATE :: UPDATE_FAST [04:04] */ 1491 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CALIBRATE_UPDATE_FAST_MASK 0x00000010 1492 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CALIBRATE_UPDATE_FAST_ALIGN 0 1493 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CALIBRATE_UPDATE_FAST_BITS 1 1494 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CALIBRATE_UPDATE_FAST_SHIFT 4 1495 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CALIBRATE_UPDATE_FAST_DEFAULT 0x00000000 1496 1497 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CALIBRATE :: UPDATE_REGS [03:03] */ 1498 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CALIBRATE_UPDATE_REGS_MASK 0x00000008 1499 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CALIBRATE_UPDATE_REGS_ALIGN 0 1500 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CALIBRATE_UPDATE_REGS_BITS 1 1501 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CALIBRATE_UPDATE_REGS_SHIFT 3 1502 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CALIBRATE_UPDATE_REGS_DEFAULT 0x00000000 1503 1504 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CALIBRATE :: CALIB_FTM2 [02:02] */ 1505 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CALIBRATE_CALIB_FTM2_MASK 0x00000004 1506 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CALIBRATE_CALIB_FTM2_ALIGN 0 1507 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CALIBRATE_CALIB_FTM2_BITS 1 1508 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CALIBRATE_CALIB_FTM2_SHIFT 2 1509 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CALIBRATE_CALIB_FTM2_DEFAULT 0x00000000 1510 1511 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CALIBRATE :: CALIB_PHYBIST [01:01] */ 1512 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CALIBRATE_CALIB_PHYBIST_MASK 0x00000002 1513 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CALIBRATE_CALIB_PHYBIST_ALIGN 0 1514 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CALIBRATE_CALIB_PHYBIST_BITS 1 1515 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CALIBRATE_CALIB_PHYBIST_SHIFT 1 1516 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CALIBRATE_CALIB_PHYBIST_DEFAULT 0x00000000 1517 1518 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CALIBRATE :: CALIB_ONCE [00:00] */ 1519 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CALIBRATE_CALIB_ONCE_MASK 0x00000001 1520 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CALIBRATE_CALIB_ONCE_ALIGN 0 1521 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CALIBRATE_CALIB_ONCE_BITS 1 1522 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CALIBRATE_CALIB_ONCE_SHIFT 0 1523 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CALIBRATE_CALIB_ONCE_DEFAULT 0x00000000 1524 1525 /*************************************************************************** 1526 *VDL_CALIB_STATUS1 - PHY VDL calibration status register #1 1527 */ 1528 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CALIB_STATUS1 :: reserved0 [31:18] */ 1529 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_RESERVED0_MASK 0xfffc0000 1530 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_RESERVED0_ALIGN 0 1531 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_RESERVED0_BITS 14 1532 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_RESERVED0_SHIFT 18 1533 1534 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CALIB_STATUS1 :: CALIB_TOTAL_STEPS [17:08] */ 1535 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_CALIB_TOTAL_STEPS_MASK 0x0003ff00 1536 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_CALIB_TOTAL_STEPS_ALIGN 0 1537 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_CALIB_TOTAL_STEPS_BITS 10 1538 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_CALIB_TOTAL_STEPS_SHIFT 8 1539 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_CALIB_TOTAL_STEPS_DEFAULT 0x00000000 1540 1541 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CALIB_STATUS1 :: reserved1 [07:06] */ 1542 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_RESERVED1_MASK 0x000000c0 1543 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_RESERVED1_ALIGN 0 1544 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_RESERVED1_BITS 2 1545 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_RESERVED1_SHIFT 6 1546 1547 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CALIB_STATUS1 :: CALIB_BUS_ERROR [05:05] */ 1548 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_CALIB_BUS_ERROR_MASK 0x00000020 1549 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_CALIB_BUS_ERROR_ALIGN 0 1550 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_CALIB_BUS_ERROR_BITS 1 1551 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_CALIB_BUS_ERROR_SHIFT 5 1552 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_CALIB_BUS_ERROR_DEFAULT 0x00000000 1553 1554 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CALIB_STATUS1 :: CALIB_REGS_DONE [04:04] */ 1555 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_CALIB_REGS_DONE_MASK 0x00000010 1556 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_CALIB_REGS_DONE_ALIGN 0 1557 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_CALIB_REGS_DONE_BITS 1 1558 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_CALIB_REGS_DONE_SHIFT 4 1559 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_CALIB_REGS_DONE_DEFAULT 0x00000000 1560 1561 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CALIB_STATUS1 :: CALIB_LOCK_6B [03:03] */ 1562 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_CALIB_LOCK_6B_MASK 0x00000008 1563 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_CALIB_LOCK_6B_ALIGN 0 1564 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_CALIB_LOCK_6B_BITS 1 1565 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_CALIB_LOCK_6B_SHIFT 3 1566 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_CALIB_LOCK_6B_DEFAULT 0x00000000 1567 1568 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CALIB_STATUS1 :: CALIB_LOCK_4B [02:02] */ 1569 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_CALIB_LOCK_4B_MASK 0x00000004 1570 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_CALIB_LOCK_4B_ALIGN 0 1571 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_CALIB_LOCK_4B_BITS 1 1572 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_CALIB_LOCK_4B_SHIFT 2 1573 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_CALIB_LOCK_4B_DEFAULT 0x00000000 1574 1575 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CALIB_STATUS1 :: CALIB_LOCK_2B [01:01] */ 1576 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_CALIB_LOCK_2B_MASK 0x00000002 1577 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_CALIB_LOCK_2B_ALIGN 0 1578 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_CALIB_LOCK_2B_BITS 1 1579 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_CALIB_LOCK_2B_SHIFT 1 1580 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_CALIB_LOCK_2B_DEFAULT 0x00000000 1581 1582 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CALIB_STATUS1 :: CALIB_IDLE [00:00] */ 1583 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_CALIB_IDLE_MASK 0x00000001 1584 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_CALIB_IDLE_ALIGN 0 1585 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_CALIB_IDLE_BITS 1 1586 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_CALIB_IDLE_SHIFT 0 1587 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_CALIB_IDLE_DEFAULT 0x00000001 1588 1589 /*************************************************************************** 1590 *VDL_CALIB_STATUS2 - PHY VDL calibration status register #2 1591 */ 1592 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CALIB_STATUS2 :: reserved0 [31:22] */ 1593 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CALIB_STATUS2_RESERVED0_MASK 0xffc00000 1594 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CALIB_STATUS2_RESERVED0_ALIGN 0 1595 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CALIB_STATUS2_RESERVED0_BITS 10 1596 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CALIB_STATUS2_RESERVED0_SHIFT 22 1597 1598 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CALIB_STATUS2 :: CALIB_4B_STEPS [21:12] */ 1599 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CALIB_STATUS2_CALIB_4B_STEPS_MASK 0x003ff000 1600 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CALIB_STATUS2_CALIB_4B_STEPS_ALIGN 0 1601 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CALIB_STATUS2_CALIB_4B_STEPS_BITS 10 1602 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CALIB_STATUS2_CALIB_4B_STEPS_SHIFT 12 1603 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CALIB_STATUS2_CALIB_4B_STEPS_DEFAULT 0x00000000 1604 1605 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CALIB_STATUS2 :: reserved1 [11:10] */ 1606 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CALIB_STATUS2_RESERVED1_MASK 0x00000c00 1607 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CALIB_STATUS2_RESERVED1_ALIGN 0 1608 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CALIB_STATUS2_RESERVED1_BITS 2 1609 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CALIB_STATUS2_RESERVED1_SHIFT 10 1610 1611 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CALIB_STATUS2 :: CALIB_2B_STEPS [09:00] */ 1612 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CALIB_STATUS2_CALIB_2B_STEPS_MASK 0x000003ff 1613 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CALIB_STATUS2_CALIB_2B_STEPS_ALIGN 0 1614 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CALIB_STATUS2_CALIB_2B_STEPS_BITS 10 1615 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CALIB_STATUS2_CALIB_2B_STEPS_SHIFT 0 1616 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CALIB_STATUS2_CALIB_2B_STEPS_DEFAULT 0x00000000 1617 1618 /*************************************************************************** 1619 *VDL_MONITOR_CONTROL - PHY VDL delay monitoring control register 1620 */ 1621 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_MONITOR_CONTROL :: reserved0 [31:22] */ 1622 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_CONTROL_RESERVED0_MASK 0xffc00000 1623 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_CONTROL_RESERVED0_ALIGN 0 1624 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_CONTROL_RESERVED0_BITS 10 1625 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_CONTROL_RESERVED0_SHIFT 22 1626 1627 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_MONITOR_CONTROL :: INTERVAL [21:08] */ 1628 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_CONTROL_INTERVAL_MASK 0x003fff00 1629 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_CONTROL_INTERVAL_ALIGN 0 1630 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_CONTROL_INTERVAL_BITS 14 1631 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_CONTROL_INTERVAL_SHIFT 8 1632 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_CONTROL_INTERVAL_DEFAULT 0x00000000 1633 1634 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_MONITOR_CONTROL :: reserved1 [07:04] */ 1635 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_CONTROL_RESERVED1_MASK 0x000000f0 1636 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_CONTROL_RESERVED1_ALIGN 0 1637 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_CONTROL_RESERVED1_BITS 4 1638 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_CONTROL_RESERVED1_SHIFT 4 1639 1640 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_MONITOR_CONTROL :: UPDATE [03:03] */ 1641 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_CONTROL_UPDATE_MASK 0x00000008 1642 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_CONTROL_UPDATE_ALIGN 0 1643 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_CONTROL_UPDATE_BITS 1 1644 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_CONTROL_UPDATE_SHIFT 3 1645 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_CONTROL_UPDATE_DEFAULT 0x00000000 1646 1647 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_MONITOR_CONTROL :: FORCE [02:02] */ 1648 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_CONTROL_FORCE_MASK 0x00000004 1649 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_CONTROL_FORCE_ALIGN 0 1650 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_CONTROL_FORCE_BITS 1 1651 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_CONTROL_FORCE_SHIFT 2 1652 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_CONTROL_FORCE_DEFAULT 0x00000000 1653 1654 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_MONITOR_CONTROL :: DATA_RATE [01:01] */ 1655 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_CONTROL_DATA_RATE_MASK 0x00000002 1656 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_CONTROL_DATA_RATE_ALIGN 0 1657 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_CONTROL_DATA_RATE_BITS 1 1658 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_CONTROL_DATA_RATE_SHIFT 1 1659 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_CONTROL_DATA_RATE_DEFAULT 0x00000000 1660 1661 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_MONITOR_CONTROL :: ENABLE [00:00] */ 1662 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_CONTROL_ENABLE_MASK 0x00000001 1663 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_CONTROL_ENABLE_ALIGN 0 1664 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_CONTROL_ENABLE_BITS 1 1665 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_CONTROL_ENABLE_SHIFT 0 1666 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_CONTROL_ENABLE_DEFAULT 0x00000000 1667 1668 /*************************************************************************** 1669 *VDL_MONITOR_REF - PHY VDL delay monitoring reference register 1670 */ 1671 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_MONITOR_REF :: reserved0 [31:22] */ 1672 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_REF_RESERVED0_MASK 0xffc00000 1673 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_REF_RESERVED0_ALIGN 0 1674 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_REF_RESERVED0_BITS 10 1675 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_REF_RESERVED0_SHIFT 22 1676 1677 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_MONITOR_REF :: MONITOR_4B_STEPS [21:12] */ 1678 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_REF_MONITOR_4B_STEPS_MASK 0x003ff000 1679 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_REF_MONITOR_4B_STEPS_ALIGN 0 1680 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_REF_MONITOR_4B_STEPS_BITS 10 1681 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_REF_MONITOR_4B_STEPS_SHIFT 12 1682 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_REF_MONITOR_4B_STEPS_DEFAULT 0x00000000 1683 1684 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_MONITOR_REF :: reserved1 [11:10] */ 1685 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_REF_RESERVED1_MASK 0x00000c00 1686 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_REF_RESERVED1_ALIGN 0 1687 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_REF_RESERVED1_BITS 2 1688 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_REF_RESERVED1_SHIFT 10 1689 1690 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_MONITOR_REF :: MONITOR_2B_STEPS [09:00] */ 1691 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_REF_MONITOR_2B_STEPS_MASK 0x000003ff 1692 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_REF_MONITOR_2B_STEPS_ALIGN 0 1693 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_REF_MONITOR_2B_STEPS_BITS 10 1694 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_REF_MONITOR_2B_STEPS_SHIFT 0 1695 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_REF_MONITOR_2B_STEPS_DEFAULT 0x00000000 1696 1697 /*************************************************************************** 1698 *VDL_MONITOR_STATUS - PHY VDL delay monitoring status register 1699 */ 1700 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_MONITOR_STATUS :: reserved0 [31:29] */ 1701 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_STATUS_RESERVED0_MASK 0xe0000000 1702 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_STATUS_RESERVED0_ALIGN 0 1703 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_STATUS_RESERVED0_BITS 3 1704 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_STATUS_RESERVED0_SHIFT 29 1705 1706 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_MONITOR_STATUS :: MONITOR_BUS_ERROR [28:28] */ 1707 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_STATUS_MONITOR_BUS_ERROR_MASK 0x10000000 1708 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_STATUS_MONITOR_BUS_ERROR_ALIGN 0 1709 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_STATUS_MONITOR_BUS_ERROR_BITS 1 1710 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_STATUS_MONITOR_BUS_ERROR_SHIFT 28 1711 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_STATUS_MONITOR_BUS_ERROR_DEFAULT 0x00000000 1712 1713 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_MONITOR_STATUS :: reserved1 [27:25] */ 1714 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_STATUS_RESERVED1_MASK 0x0e000000 1715 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_STATUS_RESERVED1_ALIGN 0 1716 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_STATUS_RESERVED1_BITS 3 1717 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_STATUS_RESERVED1_SHIFT 25 1718 1719 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_MONITOR_STATUS :: MONITOR_ADJ [24:20] */ 1720 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_STATUS_MONITOR_ADJ_MASK 0x01f00000 1721 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_STATUS_MONITOR_ADJ_ALIGN 0 1722 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_STATUS_MONITOR_ADJ_BITS 5 1723 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_STATUS_MONITOR_ADJ_SHIFT 20 1724 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_STATUS_MONITOR_ADJ_DEFAULT 0x00000000 1725 1726 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_MONITOR_STATUS :: MONITOR_CHANGE [19:12] */ 1727 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_STATUS_MONITOR_CHANGE_MASK 0x000ff000 1728 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_STATUS_MONITOR_CHANGE_ALIGN 0 1729 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_STATUS_MONITOR_CHANGE_BITS 8 1730 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_STATUS_MONITOR_CHANGE_SHIFT 12 1731 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_STATUS_MONITOR_CHANGE_DEFAULT 0x00000000 1732 1733 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_MONITOR_STATUS :: reserved2 [11:10] */ 1734 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_STATUS_RESERVED2_MASK 0x00000c00 1735 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_STATUS_RESERVED2_ALIGN 0 1736 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_STATUS_RESERVED2_BITS 2 1737 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_STATUS_RESERVED2_SHIFT 10 1738 1739 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_MONITOR_STATUS :: MONITOR_TOTAL [09:00] */ 1740 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_STATUS_MONITOR_TOTAL_MASK 0x000003ff 1741 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_STATUS_MONITOR_TOTAL_ALIGN 0 1742 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_STATUS_MONITOR_TOTAL_BITS 10 1743 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_STATUS_MONITOR_TOTAL_SHIFT 0 1744 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_STATUS_MONITOR_TOTAL_DEFAULT 0x00000000 1745 1746 /*************************************************************************** 1747 *VDL_MONITOR_OVERRIDE - PHY VDL delay monitoring override register 1748 */ 1749 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_MONITOR_OVERRIDE :: BUSY [31:31] */ 1750 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDE_BUSY_MASK 0x80000000 1751 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDE_BUSY_ALIGN 0 1752 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDE_BUSY_BITS 1 1753 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDE_BUSY_SHIFT 31 1754 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDE_BUSY_DEFAULT 0x00000000 1755 1756 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_MONITOR_OVERRIDE :: reserved0 [30:17] */ 1757 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDE_RESERVED0_MASK 0x7ffe0000 1758 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDE_RESERVED0_ALIGN 0 1759 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDE_RESERVED0_BITS 14 1760 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDE_RESERVED0_SHIFT 17 1761 1762 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_MONITOR_OVERRIDE :: FORCE [16:16] */ 1763 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDE_FORCE_MASK 0x00010000 1764 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDE_FORCE_ALIGN 0 1765 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDE_FORCE_BITS 1 1766 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDE_FORCE_SHIFT 16 1767 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDE_FORCE_DEFAULT 0x00000000 1768 1769 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_MONITOR_OVERRIDE :: reserved1 [15:09] */ 1770 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDE_RESERVED1_MASK 0x0000fe00 1771 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDE_RESERVED1_ALIGN 0 1772 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDE_RESERVED1_BITS 7 1773 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDE_RESERVED1_SHIFT 9 1774 1775 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_MONITOR_OVERRIDE :: ADJ [08:04] */ 1776 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDE_ADJ_MASK 0x000001f0 1777 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDE_ADJ_ALIGN 0 1778 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDE_ADJ_BITS 5 1779 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDE_ADJ_SHIFT 4 1780 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDE_ADJ_DEFAULT 0x00000000 1781 1782 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_MONITOR_OVERRIDE :: reserved2 [03:01] */ 1783 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDE_RESERVED2_MASK 0x0000000e 1784 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDE_RESERVED2_ALIGN 0 1785 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDE_RESERVED2_BITS 3 1786 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDE_RESERVED2_SHIFT 1 1787 1788 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_MONITOR_OVERRIDE :: ENABLE [00:00] */ 1789 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDE_ENABLE_MASK 0x00000001 1790 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDE_ENABLE_ALIGN 0 1791 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDE_ENABLE_BITS 1 1792 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDE_ENABLE_SHIFT 0 1793 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDE_ENABLE_DEFAULT 0x00000000 1794 1795 /*************************************************************************** 1796 *VDL_MONITOR_OUT_CONTROL - PHY VDL delay monitoring output control register 1797 */ 1798 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_MONITOR_OUT_CONTROL :: reserved0 [31:20] */ 1799 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_OUT_CONTROL_RESERVED0_MASK 0xfff00000 1800 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_OUT_CONTROL_RESERVED0_ALIGN 0 1801 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_OUT_CONTROL_RESERVED0_BITS 12 1802 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_OUT_CONTROL_RESERVED0_SHIFT 20 1803 1804 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_MONITOR_OUT_CONTROL :: LOWER_LIMIT [19:12] */ 1805 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_OUT_CONTROL_LOWER_LIMIT_MASK 0x000ff000 1806 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_OUT_CONTROL_LOWER_LIMIT_ALIGN 0 1807 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_OUT_CONTROL_LOWER_LIMIT_BITS 8 1808 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_OUT_CONTROL_LOWER_LIMIT_SHIFT 12 1809 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_OUT_CONTROL_LOWER_LIMIT_DEFAULT 0x00000000 1810 1811 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_MONITOR_OUT_CONTROL :: UPPER_LIMIT [11:04] */ 1812 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_OUT_CONTROL_UPPER_LIMIT_MASK 0x00000ff0 1813 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_OUT_CONTROL_UPPER_LIMIT_ALIGN 0 1814 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_OUT_CONTROL_UPPER_LIMIT_BITS 8 1815 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_OUT_CONTROL_UPPER_LIMIT_SHIFT 4 1816 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_OUT_CONTROL_UPPER_LIMIT_DEFAULT 0x00000000 1817 1818 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_MONITOR_OUT_CONTROL :: reserved1 [03:01] */ 1819 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_OUT_CONTROL_RESERVED1_MASK 0x0000000e 1820 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_OUT_CONTROL_RESERVED1_ALIGN 0 1821 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_OUT_CONTROL_RESERVED1_BITS 3 1822 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_OUT_CONTROL_RESERVED1_SHIFT 1 1823 1824 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_MONITOR_OUT_CONTROL :: ENABLE [00:00] */ 1825 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_OUT_CONTROL_ENABLE_MASK 0x00000001 1826 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_OUT_CONTROL_ENABLE_ALIGN 0 1827 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_OUT_CONTROL_ENABLE_BITS 1 1828 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_OUT_CONTROL_ENABLE_SHIFT 0 1829 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_OUT_CONTROL_ENABLE_DEFAULT 0x00000000 1830 1831 /*************************************************************************** 1832 *VDL_MONITOR_OUT_STATUS - PHY VDL delay monitoring output status register 1833 */ 1834 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_MONITOR_OUT_STATUS :: reserved0 [31:24] */ 1835 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_RESERVED0_MASK 0xff000000 1836 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_RESERVED0_ALIGN 0 1837 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_RESERVED0_BITS 8 1838 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_RESERVED0_SHIFT 24 1839 1840 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_MONITOR_OUT_STATUS :: MONITOR_CHANGE [23:16] */ 1841 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_MONITOR_CHANGE_MASK 0x00ff0000 1842 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_MONITOR_CHANGE_ALIGN 0 1843 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_MONITOR_CHANGE_BITS 8 1844 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_MONITOR_CHANGE_SHIFT 16 1845 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_MONITOR_CHANGE_DEFAULT 0x00000000 1846 1847 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_MONITOR_OUT_STATUS :: reserved1 [15:14] */ 1848 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_RESERVED1_MASK 0x0000c000 1849 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_RESERVED1_ALIGN 0 1850 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_RESERVED1_BITS 2 1851 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_RESERVED1_SHIFT 14 1852 1853 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_MONITOR_OUT_STATUS :: MONITOR_TOTAL [13:04] */ 1854 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_MONITOR_TOTAL_MASK 0x00003ff0 1855 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_MONITOR_TOTAL_ALIGN 0 1856 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_MONITOR_TOTAL_BITS 10 1857 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_MONITOR_TOTAL_SHIFT 4 1858 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_MONITOR_TOTAL_DEFAULT 0x00000000 1859 1860 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_MONITOR_OUT_STATUS :: reserved2 [03:01] */ 1861 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_RESERVED2_MASK 0x0000000e 1862 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_RESERVED2_ALIGN 0 1863 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_RESERVED2_BITS 3 1864 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_RESERVED2_SHIFT 1 1865 1866 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_MONITOR_OUT_STATUS :: VALID [00:00] */ 1867 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_VALID_MASK 0x00000001 1868 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_VALID_ALIGN 0 1869 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_VALID_BITS 1 1870 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_VALID_SHIFT 0 1871 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_VALID_DEFAULT 0x00000000 1872 1873 /*************************************************************************** 1874 *VDL_MONITOR_OUT_STATUS_CLEAR - PHY VDL delay monitoring output status clear register 1875 */ 1876 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_MONITOR_OUT_STATUS_CLEAR :: reserved0 [31:01] */ 1877 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_CLEAR_RESERVED0_MASK 0xfffffffe 1878 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_CLEAR_RESERVED0_ALIGN 0 1879 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_CLEAR_RESERVED0_BITS 31 1880 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_CLEAR_RESERVED0_SHIFT 1 1881 1882 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_MONITOR_OUT_STATUS_CLEAR :: CLEAR [00:00] */ 1883 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_CLEAR_CLEAR_MASK 0x00000001 1884 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_CLEAR_CLEAR_ALIGN 0 1885 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_CLEAR_CLEAR_BITS 1 1886 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_CLEAR_CLEAR_SHIFT 0 1887 #define DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_CLEAR_CLEAR_DEFAULT 0x00000000 1888 1889 /*************************************************************************** 1890 *VDL_CONTROL_AD00 - DDR interface signal AD[00] VDL control register 1891 */ 1892 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_AD00 :: BUSY [31:31] */ 1893 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD00_BUSY_MASK 0x80000000 1894 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD00_BUSY_ALIGN 0 1895 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD00_BUSY_BITS 1 1896 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD00_BUSY_SHIFT 31 1897 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD00_BUSY_DEFAULT 0x00000000 1898 1899 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_AD00 :: reserved0 [30:17] */ 1900 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD00_RESERVED0_MASK 0x7ffe0000 1901 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD00_RESERVED0_ALIGN 0 1902 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD00_RESERVED0_BITS 14 1903 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD00_RESERVED0_SHIFT 17 1904 1905 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_AD00 :: FORCE [16:16] */ 1906 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD00_FORCE_MASK 0x00010000 1907 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD00_FORCE_ALIGN 0 1908 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD00_FORCE_BITS 1 1909 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD00_FORCE_SHIFT 16 1910 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD00_FORCE_DEFAULT 0x00000000 1911 1912 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_AD00 :: reserved1 [15:13] */ 1913 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD00_RESERVED1_MASK 0x0000e000 1914 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD00_RESERVED1_ALIGN 0 1915 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD00_RESERVED1_BITS 3 1916 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD00_RESERVED1_SHIFT 13 1917 1918 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_AD00 :: ADJ_EN [12:12] */ 1919 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD00_ADJ_EN_MASK 0x00001000 1920 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD00_ADJ_EN_ALIGN 0 1921 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD00_ADJ_EN_BITS 1 1922 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD00_ADJ_EN_SHIFT 12 1923 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD00_ADJ_EN_DEFAULT 0x00000000 1924 1925 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_AD00 :: reserved2 [11:09] */ 1926 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD00_RESERVED2_MASK 0x00000e00 1927 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD00_RESERVED2_ALIGN 0 1928 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD00_RESERVED2_BITS 3 1929 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD00_RESERVED2_SHIFT 9 1930 1931 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_AD00 :: VDL_STEP [08:00] */ 1932 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD00_VDL_STEP_MASK 0x000001ff 1933 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD00_VDL_STEP_ALIGN 0 1934 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD00_VDL_STEP_BITS 9 1935 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD00_VDL_STEP_SHIFT 0 1936 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD00_VDL_STEP_DEFAULT 0x00000000 1937 1938 /*************************************************************************** 1939 *VDL_CONTROL_AD01 - DDR interface signal AD[01] VDL control register 1940 */ 1941 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_AD01 :: BUSY [31:31] */ 1942 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD01_BUSY_MASK 0x80000000 1943 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD01_BUSY_ALIGN 0 1944 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD01_BUSY_BITS 1 1945 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD01_BUSY_SHIFT 31 1946 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD01_BUSY_DEFAULT 0x00000000 1947 1948 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_AD01 :: reserved0 [30:17] */ 1949 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD01_RESERVED0_MASK 0x7ffe0000 1950 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD01_RESERVED0_ALIGN 0 1951 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD01_RESERVED0_BITS 14 1952 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD01_RESERVED0_SHIFT 17 1953 1954 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_AD01 :: FORCE [16:16] */ 1955 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD01_FORCE_MASK 0x00010000 1956 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD01_FORCE_ALIGN 0 1957 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD01_FORCE_BITS 1 1958 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD01_FORCE_SHIFT 16 1959 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD01_FORCE_DEFAULT 0x00000000 1960 1961 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_AD01 :: reserved1 [15:13] */ 1962 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD01_RESERVED1_MASK 0x0000e000 1963 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD01_RESERVED1_ALIGN 0 1964 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD01_RESERVED1_BITS 3 1965 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD01_RESERVED1_SHIFT 13 1966 1967 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_AD01 :: ADJ_EN [12:12] */ 1968 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD01_ADJ_EN_MASK 0x00001000 1969 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD01_ADJ_EN_ALIGN 0 1970 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD01_ADJ_EN_BITS 1 1971 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD01_ADJ_EN_SHIFT 12 1972 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD01_ADJ_EN_DEFAULT 0x00000000 1973 1974 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_AD01 :: reserved2 [11:09] */ 1975 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD01_RESERVED2_MASK 0x00000e00 1976 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD01_RESERVED2_ALIGN 0 1977 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD01_RESERVED2_BITS 3 1978 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD01_RESERVED2_SHIFT 9 1979 1980 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_AD01 :: VDL_STEP [08:00] */ 1981 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD01_VDL_STEP_MASK 0x000001ff 1982 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD01_VDL_STEP_ALIGN 0 1983 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD01_VDL_STEP_BITS 9 1984 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD01_VDL_STEP_SHIFT 0 1985 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD01_VDL_STEP_DEFAULT 0x00000000 1986 1987 /*************************************************************************** 1988 *VDL_CONTROL_AD02 - DDR interface signal AD[02] VDL control register 1989 */ 1990 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_AD02 :: BUSY [31:31] */ 1991 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD02_BUSY_MASK 0x80000000 1992 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD02_BUSY_ALIGN 0 1993 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD02_BUSY_BITS 1 1994 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD02_BUSY_SHIFT 31 1995 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD02_BUSY_DEFAULT 0x00000000 1996 1997 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_AD02 :: reserved0 [30:17] */ 1998 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD02_RESERVED0_MASK 0x7ffe0000 1999 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD02_RESERVED0_ALIGN 0 2000 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD02_RESERVED0_BITS 14 2001 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD02_RESERVED0_SHIFT 17 2002 2003 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_AD02 :: FORCE [16:16] */ 2004 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD02_FORCE_MASK 0x00010000 2005 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD02_FORCE_ALIGN 0 2006 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD02_FORCE_BITS 1 2007 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD02_FORCE_SHIFT 16 2008 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD02_FORCE_DEFAULT 0x00000000 2009 2010 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_AD02 :: reserved1 [15:13] */ 2011 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD02_RESERVED1_MASK 0x0000e000 2012 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD02_RESERVED1_ALIGN 0 2013 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD02_RESERVED1_BITS 3 2014 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD02_RESERVED1_SHIFT 13 2015 2016 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_AD02 :: ADJ_EN [12:12] */ 2017 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD02_ADJ_EN_MASK 0x00001000 2018 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD02_ADJ_EN_ALIGN 0 2019 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD02_ADJ_EN_BITS 1 2020 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD02_ADJ_EN_SHIFT 12 2021 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD02_ADJ_EN_DEFAULT 0x00000000 2022 2023 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_AD02 :: reserved2 [11:09] */ 2024 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD02_RESERVED2_MASK 0x00000e00 2025 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD02_RESERVED2_ALIGN 0 2026 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD02_RESERVED2_BITS 3 2027 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD02_RESERVED2_SHIFT 9 2028 2029 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_AD02 :: VDL_STEP [08:00] */ 2030 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD02_VDL_STEP_MASK 0x000001ff 2031 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD02_VDL_STEP_ALIGN 0 2032 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD02_VDL_STEP_BITS 9 2033 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD02_VDL_STEP_SHIFT 0 2034 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD02_VDL_STEP_DEFAULT 0x00000000 2035 2036 /*************************************************************************** 2037 *VDL_CONTROL_AD03 - DDR interface signal AD[03] VDL control register 2038 */ 2039 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_AD03 :: BUSY [31:31] */ 2040 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD03_BUSY_MASK 0x80000000 2041 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD03_BUSY_ALIGN 0 2042 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD03_BUSY_BITS 1 2043 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD03_BUSY_SHIFT 31 2044 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD03_BUSY_DEFAULT 0x00000000 2045 2046 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_AD03 :: reserved0 [30:17] */ 2047 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD03_RESERVED0_MASK 0x7ffe0000 2048 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD03_RESERVED0_ALIGN 0 2049 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD03_RESERVED0_BITS 14 2050 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD03_RESERVED0_SHIFT 17 2051 2052 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_AD03 :: FORCE [16:16] */ 2053 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD03_FORCE_MASK 0x00010000 2054 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD03_FORCE_ALIGN 0 2055 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD03_FORCE_BITS 1 2056 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD03_FORCE_SHIFT 16 2057 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD03_FORCE_DEFAULT 0x00000000 2058 2059 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_AD03 :: reserved1 [15:13] */ 2060 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD03_RESERVED1_MASK 0x0000e000 2061 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD03_RESERVED1_ALIGN 0 2062 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD03_RESERVED1_BITS 3 2063 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD03_RESERVED1_SHIFT 13 2064 2065 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_AD03 :: ADJ_EN [12:12] */ 2066 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD03_ADJ_EN_MASK 0x00001000 2067 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD03_ADJ_EN_ALIGN 0 2068 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD03_ADJ_EN_BITS 1 2069 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD03_ADJ_EN_SHIFT 12 2070 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD03_ADJ_EN_DEFAULT 0x00000000 2071 2072 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_AD03 :: reserved2 [11:09] */ 2073 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD03_RESERVED2_MASK 0x00000e00 2074 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD03_RESERVED2_ALIGN 0 2075 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD03_RESERVED2_BITS 3 2076 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD03_RESERVED2_SHIFT 9 2077 2078 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_AD03 :: VDL_STEP [08:00] */ 2079 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD03_VDL_STEP_MASK 0x000001ff 2080 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD03_VDL_STEP_ALIGN 0 2081 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD03_VDL_STEP_BITS 9 2082 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD03_VDL_STEP_SHIFT 0 2083 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD03_VDL_STEP_DEFAULT 0x00000000 2084 2085 /*************************************************************************** 2086 *VDL_CONTROL_AD04 - DDR interface signal AD[04] VDL control register 2087 */ 2088 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_AD04 :: BUSY [31:31] */ 2089 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD04_BUSY_MASK 0x80000000 2090 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD04_BUSY_ALIGN 0 2091 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD04_BUSY_BITS 1 2092 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD04_BUSY_SHIFT 31 2093 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD04_BUSY_DEFAULT 0x00000000 2094 2095 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_AD04 :: reserved0 [30:17] */ 2096 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD04_RESERVED0_MASK 0x7ffe0000 2097 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD04_RESERVED0_ALIGN 0 2098 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD04_RESERVED0_BITS 14 2099 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD04_RESERVED0_SHIFT 17 2100 2101 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_AD04 :: FORCE [16:16] */ 2102 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD04_FORCE_MASK 0x00010000 2103 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD04_FORCE_ALIGN 0 2104 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD04_FORCE_BITS 1 2105 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD04_FORCE_SHIFT 16 2106 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD04_FORCE_DEFAULT 0x00000000 2107 2108 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_AD04 :: reserved1 [15:13] */ 2109 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD04_RESERVED1_MASK 0x0000e000 2110 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD04_RESERVED1_ALIGN 0 2111 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD04_RESERVED1_BITS 3 2112 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD04_RESERVED1_SHIFT 13 2113 2114 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_AD04 :: ADJ_EN [12:12] */ 2115 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD04_ADJ_EN_MASK 0x00001000 2116 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD04_ADJ_EN_ALIGN 0 2117 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD04_ADJ_EN_BITS 1 2118 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD04_ADJ_EN_SHIFT 12 2119 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD04_ADJ_EN_DEFAULT 0x00000000 2120 2121 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_AD04 :: reserved2 [11:09] */ 2122 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD04_RESERVED2_MASK 0x00000e00 2123 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD04_RESERVED2_ALIGN 0 2124 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD04_RESERVED2_BITS 3 2125 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD04_RESERVED2_SHIFT 9 2126 2127 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_AD04 :: VDL_STEP [08:00] */ 2128 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD04_VDL_STEP_MASK 0x000001ff 2129 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD04_VDL_STEP_ALIGN 0 2130 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD04_VDL_STEP_BITS 9 2131 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD04_VDL_STEP_SHIFT 0 2132 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD04_VDL_STEP_DEFAULT 0x00000000 2133 2134 /*************************************************************************** 2135 *VDL_CONTROL_AD05 - DDR interface signal AD[05] VDL control register 2136 */ 2137 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_AD05 :: BUSY [31:31] */ 2138 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD05_BUSY_MASK 0x80000000 2139 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD05_BUSY_ALIGN 0 2140 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD05_BUSY_BITS 1 2141 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD05_BUSY_SHIFT 31 2142 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD05_BUSY_DEFAULT 0x00000000 2143 2144 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_AD05 :: reserved0 [30:17] */ 2145 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD05_RESERVED0_MASK 0x7ffe0000 2146 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD05_RESERVED0_ALIGN 0 2147 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD05_RESERVED0_BITS 14 2148 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD05_RESERVED0_SHIFT 17 2149 2150 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_AD05 :: FORCE [16:16] */ 2151 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD05_FORCE_MASK 0x00010000 2152 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD05_FORCE_ALIGN 0 2153 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD05_FORCE_BITS 1 2154 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD05_FORCE_SHIFT 16 2155 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD05_FORCE_DEFAULT 0x00000000 2156 2157 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_AD05 :: reserved1 [15:13] */ 2158 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD05_RESERVED1_MASK 0x0000e000 2159 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD05_RESERVED1_ALIGN 0 2160 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD05_RESERVED1_BITS 3 2161 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD05_RESERVED1_SHIFT 13 2162 2163 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_AD05 :: ADJ_EN [12:12] */ 2164 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD05_ADJ_EN_MASK 0x00001000 2165 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD05_ADJ_EN_ALIGN 0 2166 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD05_ADJ_EN_BITS 1 2167 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD05_ADJ_EN_SHIFT 12 2168 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD05_ADJ_EN_DEFAULT 0x00000000 2169 2170 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_AD05 :: reserved2 [11:09] */ 2171 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD05_RESERVED2_MASK 0x00000e00 2172 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD05_RESERVED2_ALIGN 0 2173 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD05_RESERVED2_BITS 3 2174 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD05_RESERVED2_SHIFT 9 2175 2176 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_AD05 :: VDL_STEP [08:00] */ 2177 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD05_VDL_STEP_MASK 0x000001ff 2178 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD05_VDL_STEP_ALIGN 0 2179 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD05_VDL_STEP_BITS 9 2180 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD05_VDL_STEP_SHIFT 0 2181 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD05_VDL_STEP_DEFAULT 0x00000000 2182 2183 /*************************************************************************** 2184 *VDL_CONTROL_AD06 - DDR interface signal AD[06] VDL control register 2185 */ 2186 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_AD06 :: BUSY [31:31] */ 2187 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD06_BUSY_MASK 0x80000000 2188 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD06_BUSY_ALIGN 0 2189 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD06_BUSY_BITS 1 2190 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD06_BUSY_SHIFT 31 2191 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD06_BUSY_DEFAULT 0x00000000 2192 2193 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_AD06 :: reserved0 [30:17] */ 2194 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD06_RESERVED0_MASK 0x7ffe0000 2195 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD06_RESERVED0_ALIGN 0 2196 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD06_RESERVED0_BITS 14 2197 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD06_RESERVED0_SHIFT 17 2198 2199 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_AD06 :: FORCE [16:16] */ 2200 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD06_FORCE_MASK 0x00010000 2201 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD06_FORCE_ALIGN 0 2202 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD06_FORCE_BITS 1 2203 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD06_FORCE_SHIFT 16 2204 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD06_FORCE_DEFAULT 0x00000000 2205 2206 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_AD06 :: reserved1 [15:13] */ 2207 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD06_RESERVED1_MASK 0x0000e000 2208 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD06_RESERVED1_ALIGN 0 2209 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD06_RESERVED1_BITS 3 2210 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD06_RESERVED1_SHIFT 13 2211 2212 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_AD06 :: ADJ_EN [12:12] */ 2213 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD06_ADJ_EN_MASK 0x00001000 2214 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD06_ADJ_EN_ALIGN 0 2215 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD06_ADJ_EN_BITS 1 2216 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD06_ADJ_EN_SHIFT 12 2217 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD06_ADJ_EN_DEFAULT 0x00000000 2218 2219 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_AD06 :: reserved2 [11:09] */ 2220 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD06_RESERVED2_MASK 0x00000e00 2221 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD06_RESERVED2_ALIGN 0 2222 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD06_RESERVED2_BITS 3 2223 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD06_RESERVED2_SHIFT 9 2224 2225 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_AD06 :: VDL_STEP [08:00] */ 2226 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD06_VDL_STEP_MASK 0x000001ff 2227 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD06_VDL_STEP_ALIGN 0 2228 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD06_VDL_STEP_BITS 9 2229 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD06_VDL_STEP_SHIFT 0 2230 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD06_VDL_STEP_DEFAULT 0x00000000 2231 2232 /*************************************************************************** 2233 *VDL_CONTROL_AD07 - DDR interface signal AD[07] VDL control register 2234 */ 2235 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_AD07 :: BUSY [31:31] */ 2236 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD07_BUSY_MASK 0x80000000 2237 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD07_BUSY_ALIGN 0 2238 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD07_BUSY_BITS 1 2239 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD07_BUSY_SHIFT 31 2240 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD07_BUSY_DEFAULT 0x00000000 2241 2242 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_AD07 :: reserved0 [30:17] */ 2243 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD07_RESERVED0_MASK 0x7ffe0000 2244 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD07_RESERVED0_ALIGN 0 2245 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD07_RESERVED0_BITS 14 2246 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD07_RESERVED0_SHIFT 17 2247 2248 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_AD07 :: FORCE [16:16] */ 2249 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD07_FORCE_MASK 0x00010000 2250 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD07_FORCE_ALIGN 0 2251 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD07_FORCE_BITS 1 2252 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD07_FORCE_SHIFT 16 2253 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD07_FORCE_DEFAULT 0x00000000 2254 2255 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_AD07 :: reserved1 [15:13] */ 2256 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD07_RESERVED1_MASK 0x0000e000 2257 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD07_RESERVED1_ALIGN 0 2258 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD07_RESERVED1_BITS 3 2259 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD07_RESERVED1_SHIFT 13 2260 2261 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_AD07 :: ADJ_EN [12:12] */ 2262 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD07_ADJ_EN_MASK 0x00001000 2263 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD07_ADJ_EN_ALIGN 0 2264 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD07_ADJ_EN_BITS 1 2265 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD07_ADJ_EN_SHIFT 12 2266 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD07_ADJ_EN_DEFAULT 0x00000000 2267 2268 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_AD07 :: reserved2 [11:09] */ 2269 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD07_RESERVED2_MASK 0x00000e00 2270 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD07_RESERVED2_ALIGN 0 2271 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD07_RESERVED2_BITS 3 2272 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD07_RESERVED2_SHIFT 9 2273 2274 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_AD07 :: VDL_STEP [08:00] */ 2275 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD07_VDL_STEP_MASK 0x000001ff 2276 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD07_VDL_STEP_ALIGN 0 2277 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD07_VDL_STEP_BITS 9 2278 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD07_VDL_STEP_SHIFT 0 2279 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD07_VDL_STEP_DEFAULT 0x00000000 2280 2281 /*************************************************************************** 2282 *VDL_CONTROL_AD08 - DDR interface signal AD[08] VDL control register 2283 */ 2284 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_AD08 :: BUSY [31:31] */ 2285 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD08_BUSY_MASK 0x80000000 2286 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD08_BUSY_ALIGN 0 2287 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD08_BUSY_BITS 1 2288 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD08_BUSY_SHIFT 31 2289 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD08_BUSY_DEFAULT 0x00000000 2290 2291 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_AD08 :: reserved0 [30:17] */ 2292 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD08_RESERVED0_MASK 0x7ffe0000 2293 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD08_RESERVED0_ALIGN 0 2294 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD08_RESERVED0_BITS 14 2295 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD08_RESERVED0_SHIFT 17 2296 2297 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_AD08 :: FORCE [16:16] */ 2298 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD08_FORCE_MASK 0x00010000 2299 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD08_FORCE_ALIGN 0 2300 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD08_FORCE_BITS 1 2301 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD08_FORCE_SHIFT 16 2302 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD08_FORCE_DEFAULT 0x00000000 2303 2304 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_AD08 :: reserved1 [15:13] */ 2305 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD08_RESERVED1_MASK 0x0000e000 2306 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD08_RESERVED1_ALIGN 0 2307 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD08_RESERVED1_BITS 3 2308 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD08_RESERVED1_SHIFT 13 2309 2310 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_AD08 :: ADJ_EN [12:12] */ 2311 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD08_ADJ_EN_MASK 0x00001000 2312 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD08_ADJ_EN_ALIGN 0 2313 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD08_ADJ_EN_BITS 1 2314 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD08_ADJ_EN_SHIFT 12 2315 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD08_ADJ_EN_DEFAULT 0x00000000 2316 2317 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_AD08 :: reserved2 [11:09] */ 2318 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD08_RESERVED2_MASK 0x00000e00 2319 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD08_RESERVED2_ALIGN 0 2320 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD08_RESERVED2_BITS 3 2321 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD08_RESERVED2_SHIFT 9 2322 2323 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_AD08 :: VDL_STEP [08:00] */ 2324 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD08_VDL_STEP_MASK 0x000001ff 2325 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD08_VDL_STEP_ALIGN 0 2326 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD08_VDL_STEP_BITS 9 2327 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD08_VDL_STEP_SHIFT 0 2328 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD08_VDL_STEP_DEFAULT 0x00000000 2329 2330 /*************************************************************************** 2331 *VDL_CONTROL_AD09 - DDR interface signal AD[09] VDL control register 2332 */ 2333 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_AD09 :: BUSY [31:31] */ 2334 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD09_BUSY_MASK 0x80000000 2335 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD09_BUSY_ALIGN 0 2336 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD09_BUSY_BITS 1 2337 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD09_BUSY_SHIFT 31 2338 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD09_BUSY_DEFAULT 0x00000000 2339 2340 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_AD09 :: reserved0 [30:17] */ 2341 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD09_RESERVED0_MASK 0x7ffe0000 2342 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD09_RESERVED0_ALIGN 0 2343 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD09_RESERVED0_BITS 14 2344 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD09_RESERVED0_SHIFT 17 2345 2346 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_AD09 :: FORCE [16:16] */ 2347 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD09_FORCE_MASK 0x00010000 2348 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD09_FORCE_ALIGN 0 2349 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD09_FORCE_BITS 1 2350 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD09_FORCE_SHIFT 16 2351 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD09_FORCE_DEFAULT 0x00000000 2352 2353 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_AD09 :: reserved1 [15:13] */ 2354 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD09_RESERVED1_MASK 0x0000e000 2355 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD09_RESERVED1_ALIGN 0 2356 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD09_RESERVED1_BITS 3 2357 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD09_RESERVED1_SHIFT 13 2358 2359 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_AD09 :: ADJ_EN [12:12] */ 2360 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD09_ADJ_EN_MASK 0x00001000 2361 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD09_ADJ_EN_ALIGN 0 2362 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD09_ADJ_EN_BITS 1 2363 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD09_ADJ_EN_SHIFT 12 2364 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD09_ADJ_EN_DEFAULT 0x00000000 2365 2366 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_AD09 :: reserved2 [11:09] */ 2367 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD09_RESERVED2_MASK 0x00000e00 2368 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD09_RESERVED2_ALIGN 0 2369 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD09_RESERVED2_BITS 3 2370 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD09_RESERVED2_SHIFT 9 2371 2372 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_AD09 :: VDL_STEP [08:00] */ 2373 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD09_VDL_STEP_MASK 0x000001ff 2374 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD09_VDL_STEP_ALIGN 0 2375 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD09_VDL_STEP_BITS 9 2376 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD09_VDL_STEP_SHIFT 0 2377 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD09_VDL_STEP_DEFAULT 0x00000000 2378 2379 /*************************************************************************** 2380 *VDL_CONTROL_AD10 - DDR interface signal AD[10] VDL control register 2381 */ 2382 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_AD10 :: BUSY [31:31] */ 2383 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD10_BUSY_MASK 0x80000000 2384 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD10_BUSY_ALIGN 0 2385 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD10_BUSY_BITS 1 2386 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD10_BUSY_SHIFT 31 2387 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD10_BUSY_DEFAULT 0x00000000 2388 2389 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_AD10 :: reserved0 [30:17] */ 2390 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD10_RESERVED0_MASK 0x7ffe0000 2391 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD10_RESERVED0_ALIGN 0 2392 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD10_RESERVED0_BITS 14 2393 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD10_RESERVED0_SHIFT 17 2394 2395 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_AD10 :: FORCE [16:16] */ 2396 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD10_FORCE_MASK 0x00010000 2397 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD10_FORCE_ALIGN 0 2398 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD10_FORCE_BITS 1 2399 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD10_FORCE_SHIFT 16 2400 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD10_FORCE_DEFAULT 0x00000000 2401 2402 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_AD10 :: reserved1 [15:13] */ 2403 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD10_RESERVED1_MASK 0x0000e000 2404 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD10_RESERVED1_ALIGN 0 2405 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD10_RESERVED1_BITS 3 2406 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD10_RESERVED1_SHIFT 13 2407 2408 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_AD10 :: ADJ_EN [12:12] */ 2409 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD10_ADJ_EN_MASK 0x00001000 2410 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD10_ADJ_EN_ALIGN 0 2411 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD10_ADJ_EN_BITS 1 2412 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD10_ADJ_EN_SHIFT 12 2413 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD10_ADJ_EN_DEFAULT 0x00000000 2414 2415 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_AD10 :: reserved2 [11:09] */ 2416 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD10_RESERVED2_MASK 0x00000e00 2417 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD10_RESERVED2_ALIGN 0 2418 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD10_RESERVED2_BITS 3 2419 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD10_RESERVED2_SHIFT 9 2420 2421 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_AD10 :: VDL_STEP [08:00] */ 2422 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD10_VDL_STEP_MASK 0x000001ff 2423 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD10_VDL_STEP_ALIGN 0 2424 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD10_VDL_STEP_BITS 9 2425 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD10_VDL_STEP_SHIFT 0 2426 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD10_VDL_STEP_DEFAULT 0x00000000 2427 2428 /*************************************************************************** 2429 *VDL_CONTROL_AD11 - DDR interface signal AD[11] VDL control register 2430 */ 2431 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_AD11 :: BUSY [31:31] */ 2432 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD11_BUSY_MASK 0x80000000 2433 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD11_BUSY_ALIGN 0 2434 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD11_BUSY_BITS 1 2435 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD11_BUSY_SHIFT 31 2436 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD11_BUSY_DEFAULT 0x00000000 2437 2438 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_AD11 :: reserved0 [30:17] */ 2439 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD11_RESERVED0_MASK 0x7ffe0000 2440 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD11_RESERVED0_ALIGN 0 2441 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD11_RESERVED0_BITS 14 2442 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD11_RESERVED0_SHIFT 17 2443 2444 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_AD11 :: FORCE [16:16] */ 2445 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD11_FORCE_MASK 0x00010000 2446 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD11_FORCE_ALIGN 0 2447 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD11_FORCE_BITS 1 2448 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD11_FORCE_SHIFT 16 2449 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD11_FORCE_DEFAULT 0x00000000 2450 2451 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_AD11 :: reserved1 [15:13] */ 2452 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD11_RESERVED1_MASK 0x0000e000 2453 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD11_RESERVED1_ALIGN 0 2454 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD11_RESERVED1_BITS 3 2455 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD11_RESERVED1_SHIFT 13 2456 2457 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_AD11 :: ADJ_EN [12:12] */ 2458 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD11_ADJ_EN_MASK 0x00001000 2459 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD11_ADJ_EN_ALIGN 0 2460 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD11_ADJ_EN_BITS 1 2461 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD11_ADJ_EN_SHIFT 12 2462 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD11_ADJ_EN_DEFAULT 0x00000000 2463 2464 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_AD11 :: reserved2 [11:09] */ 2465 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD11_RESERVED2_MASK 0x00000e00 2466 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD11_RESERVED2_ALIGN 0 2467 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD11_RESERVED2_BITS 3 2468 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD11_RESERVED2_SHIFT 9 2469 2470 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_AD11 :: VDL_STEP [08:00] */ 2471 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD11_VDL_STEP_MASK 0x000001ff 2472 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD11_VDL_STEP_ALIGN 0 2473 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD11_VDL_STEP_BITS 9 2474 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD11_VDL_STEP_SHIFT 0 2475 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD11_VDL_STEP_DEFAULT 0x00000000 2476 2477 /*************************************************************************** 2478 *VDL_CONTROL_AD12 - DDR interface signal AD[12] VDL control register 2479 */ 2480 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_AD12 :: BUSY [31:31] */ 2481 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD12_BUSY_MASK 0x80000000 2482 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD12_BUSY_ALIGN 0 2483 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD12_BUSY_BITS 1 2484 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD12_BUSY_SHIFT 31 2485 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD12_BUSY_DEFAULT 0x00000000 2486 2487 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_AD12 :: reserved0 [30:17] */ 2488 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD12_RESERVED0_MASK 0x7ffe0000 2489 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD12_RESERVED0_ALIGN 0 2490 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD12_RESERVED0_BITS 14 2491 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD12_RESERVED0_SHIFT 17 2492 2493 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_AD12 :: FORCE [16:16] */ 2494 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD12_FORCE_MASK 0x00010000 2495 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD12_FORCE_ALIGN 0 2496 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD12_FORCE_BITS 1 2497 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD12_FORCE_SHIFT 16 2498 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD12_FORCE_DEFAULT 0x00000000 2499 2500 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_AD12 :: reserved1 [15:13] */ 2501 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD12_RESERVED1_MASK 0x0000e000 2502 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD12_RESERVED1_ALIGN 0 2503 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD12_RESERVED1_BITS 3 2504 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD12_RESERVED1_SHIFT 13 2505 2506 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_AD12 :: ADJ_EN [12:12] */ 2507 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD12_ADJ_EN_MASK 0x00001000 2508 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD12_ADJ_EN_ALIGN 0 2509 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD12_ADJ_EN_BITS 1 2510 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD12_ADJ_EN_SHIFT 12 2511 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD12_ADJ_EN_DEFAULT 0x00000000 2512 2513 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_AD12 :: reserved2 [11:09] */ 2514 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD12_RESERVED2_MASK 0x00000e00 2515 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD12_RESERVED2_ALIGN 0 2516 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD12_RESERVED2_BITS 3 2517 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD12_RESERVED2_SHIFT 9 2518 2519 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_AD12 :: VDL_STEP [08:00] */ 2520 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD12_VDL_STEP_MASK 0x000001ff 2521 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD12_VDL_STEP_ALIGN 0 2522 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD12_VDL_STEP_BITS 9 2523 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD12_VDL_STEP_SHIFT 0 2524 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD12_VDL_STEP_DEFAULT 0x00000000 2525 2526 /*************************************************************************** 2527 *VDL_CONTROL_AD13 - DDR interface signal AD[13] VDL control register 2528 */ 2529 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_AD13 :: BUSY [31:31] */ 2530 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD13_BUSY_MASK 0x80000000 2531 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD13_BUSY_ALIGN 0 2532 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD13_BUSY_BITS 1 2533 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD13_BUSY_SHIFT 31 2534 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD13_BUSY_DEFAULT 0x00000000 2535 2536 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_AD13 :: reserved0 [30:17] */ 2537 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD13_RESERVED0_MASK 0x7ffe0000 2538 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD13_RESERVED0_ALIGN 0 2539 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD13_RESERVED0_BITS 14 2540 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD13_RESERVED0_SHIFT 17 2541 2542 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_AD13 :: FORCE [16:16] */ 2543 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD13_FORCE_MASK 0x00010000 2544 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD13_FORCE_ALIGN 0 2545 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD13_FORCE_BITS 1 2546 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD13_FORCE_SHIFT 16 2547 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD13_FORCE_DEFAULT 0x00000000 2548 2549 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_AD13 :: reserved1 [15:13] */ 2550 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD13_RESERVED1_MASK 0x0000e000 2551 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD13_RESERVED1_ALIGN 0 2552 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD13_RESERVED1_BITS 3 2553 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD13_RESERVED1_SHIFT 13 2554 2555 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_AD13 :: ADJ_EN [12:12] */ 2556 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD13_ADJ_EN_MASK 0x00001000 2557 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD13_ADJ_EN_ALIGN 0 2558 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD13_ADJ_EN_BITS 1 2559 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD13_ADJ_EN_SHIFT 12 2560 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD13_ADJ_EN_DEFAULT 0x00000000 2561 2562 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_AD13 :: reserved2 [11:09] */ 2563 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD13_RESERVED2_MASK 0x00000e00 2564 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD13_RESERVED2_ALIGN 0 2565 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD13_RESERVED2_BITS 3 2566 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD13_RESERVED2_SHIFT 9 2567 2568 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_AD13 :: VDL_STEP [08:00] */ 2569 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD13_VDL_STEP_MASK 0x000001ff 2570 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD13_VDL_STEP_ALIGN 0 2571 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD13_VDL_STEP_BITS 9 2572 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD13_VDL_STEP_SHIFT 0 2573 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD13_VDL_STEP_DEFAULT 0x00000000 2574 2575 /*************************************************************************** 2576 *VDL_CONTROL_AD14 - DDR interface signal AD[14] VDL control register 2577 */ 2578 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_AD14 :: BUSY [31:31] */ 2579 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD14_BUSY_MASK 0x80000000 2580 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD14_BUSY_ALIGN 0 2581 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD14_BUSY_BITS 1 2582 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD14_BUSY_SHIFT 31 2583 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD14_BUSY_DEFAULT 0x00000000 2584 2585 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_AD14 :: reserved0 [30:17] */ 2586 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD14_RESERVED0_MASK 0x7ffe0000 2587 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD14_RESERVED0_ALIGN 0 2588 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD14_RESERVED0_BITS 14 2589 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD14_RESERVED0_SHIFT 17 2590 2591 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_AD14 :: FORCE [16:16] */ 2592 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD14_FORCE_MASK 0x00010000 2593 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD14_FORCE_ALIGN 0 2594 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD14_FORCE_BITS 1 2595 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD14_FORCE_SHIFT 16 2596 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD14_FORCE_DEFAULT 0x00000000 2597 2598 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_AD14 :: reserved1 [15:13] */ 2599 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD14_RESERVED1_MASK 0x0000e000 2600 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD14_RESERVED1_ALIGN 0 2601 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD14_RESERVED1_BITS 3 2602 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD14_RESERVED1_SHIFT 13 2603 2604 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_AD14 :: ADJ_EN [12:12] */ 2605 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD14_ADJ_EN_MASK 0x00001000 2606 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD14_ADJ_EN_ALIGN 0 2607 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD14_ADJ_EN_BITS 1 2608 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD14_ADJ_EN_SHIFT 12 2609 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD14_ADJ_EN_DEFAULT 0x00000000 2610 2611 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_AD14 :: reserved2 [11:09] */ 2612 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD14_RESERVED2_MASK 0x00000e00 2613 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD14_RESERVED2_ALIGN 0 2614 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD14_RESERVED2_BITS 3 2615 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD14_RESERVED2_SHIFT 9 2616 2617 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_AD14 :: VDL_STEP [08:00] */ 2618 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD14_VDL_STEP_MASK 0x000001ff 2619 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD14_VDL_STEP_ALIGN 0 2620 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD14_VDL_STEP_BITS 9 2621 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD14_VDL_STEP_SHIFT 0 2622 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD14_VDL_STEP_DEFAULT 0x00000000 2623 2624 /*************************************************************************** 2625 *VDL_CONTROL_AD15 - DDR interface signal AD[15] VDL control register 2626 */ 2627 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_AD15 :: BUSY [31:31] */ 2628 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD15_BUSY_MASK 0x80000000 2629 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD15_BUSY_ALIGN 0 2630 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD15_BUSY_BITS 1 2631 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD15_BUSY_SHIFT 31 2632 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD15_BUSY_DEFAULT 0x00000000 2633 2634 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_AD15 :: reserved0 [30:17] */ 2635 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD15_RESERVED0_MASK 0x7ffe0000 2636 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD15_RESERVED0_ALIGN 0 2637 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD15_RESERVED0_BITS 14 2638 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD15_RESERVED0_SHIFT 17 2639 2640 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_AD15 :: FORCE [16:16] */ 2641 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD15_FORCE_MASK 0x00010000 2642 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD15_FORCE_ALIGN 0 2643 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD15_FORCE_BITS 1 2644 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD15_FORCE_SHIFT 16 2645 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD15_FORCE_DEFAULT 0x00000000 2646 2647 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_AD15 :: reserved1 [15:13] */ 2648 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD15_RESERVED1_MASK 0x0000e000 2649 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD15_RESERVED1_ALIGN 0 2650 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD15_RESERVED1_BITS 3 2651 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD15_RESERVED1_SHIFT 13 2652 2653 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_AD15 :: ADJ_EN [12:12] */ 2654 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD15_ADJ_EN_MASK 0x00001000 2655 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD15_ADJ_EN_ALIGN 0 2656 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD15_ADJ_EN_BITS 1 2657 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD15_ADJ_EN_SHIFT 12 2658 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD15_ADJ_EN_DEFAULT 0x00000000 2659 2660 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_AD15 :: reserved2 [11:09] */ 2661 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD15_RESERVED2_MASK 0x00000e00 2662 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD15_RESERVED2_ALIGN 0 2663 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD15_RESERVED2_BITS 3 2664 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD15_RESERVED2_SHIFT 9 2665 2666 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_AD15 :: VDL_STEP [08:00] */ 2667 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD15_VDL_STEP_MASK 0x000001ff 2668 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD15_VDL_STEP_ALIGN 0 2669 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD15_VDL_STEP_BITS 9 2670 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD15_VDL_STEP_SHIFT 0 2671 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD15_VDL_STEP_DEFAULT 0x00000000 2672 2673 /*************************************************************************** 2674 *VDL_CONTROL_BA0 - DDR interface signal BA[0] VDL control register 2675 */ 2676 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_BA0 :: BUSY [31:31] */ 2677 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_BA0_BUSY_MASK 0x80000000 2678 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_BA0_BUSY_ALIGN 0 2679 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_BA0_BUSY_BITS 1 2680 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_BA0_BUSY_SHIFT 31 2681 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_BA0_BUSY_DEFAULT 0x00000000 2682 2683 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_BA0 :: reserved0 [30:17] */ 2684 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_BA0_RESERVED0_MASK 0x7ffe0000 2685 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_BA0_RESERVED0_ALIGN 0 2686 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_BA0_RESERVED0_BITS 14 2687 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_BA0_RESERVED0_SHIFT 17 2688 2689 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_BA0 :: FORCE [16:16] */ 2690 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_BA0_FORCE_MASK 0x00010000 2691 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_BA0_FORCE_ALIGN 0 2692 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_BA0_FORCE_BITS 1 2693 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_BA0_FORCE_SHIFT 16 2694 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_BA0_FORCE_DEFAULT 0x00000000 2695 2696 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_BA0 :: reserved1 [15:13] */ 2697 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_BA0_RESERVED1_MASK 0x0000e000 2698 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_BA0_RESERVED1_ALIGN 0 2699 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_BA0_RESERVED1_BITS 3 2700 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_BA0_RESERVED1_SHIFT 13 2701 2702 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_BA0 :: ADJ_EN [12:12] */ 2703 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_BA0_ADJ_EN_MASK 0x00001000 2704 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_BA0_ADJ_EN_ALIGN 0 2705 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_BA0_ADJ_EN_BITS 1 2706 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_BA0_ADJ_EN_SHIFT 12 2707 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_BA0_ADJ_EN_DEFAULT 0x00000000 2708 2709 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_BA0 :: reserved2 [11:09] */ 2710 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_BA0_RESERVED2_MASK 0x00000e00 2711 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_BA0_RESERVED2_ALIGN 0 2712 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_BA0_RESERVED2_BITS 3 2713 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_BA0_RESERVED2_SHIFT 9 2714 2715 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_BA0 :: VDL_STEP [08:00] */ 2716 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_BA0_VDL_STEP_MASK 0x000001ff 2717 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_BA0_VDL_STEP_ALIGN 0 2718 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_BA0_VDL_STEP_BITS 9 2719 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_BA0_VDL_STEP_SHIFT 0 2720 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_BA0_VDL_STEP_DEFAULT 0x00000000 2721 2722 /*************************************************************************** 2723 *VDL_CONTROL_BA1 - DDR interface signal BA[1] VDL control register 2724 */ 2725 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_BA1 :: BUSY [31:31] */ 2726 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_BA1_BUSY_MASK 0x80000000 2727 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_BA1_BUSY_ALIGN 0 2728 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_BA1_BUSY_BITS 1 2729 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_BA1_BUSY_SHIFT 31 2730 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_BA1_BUSY_DEFAULT 0x00000000 2731 2732 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_BA1 :: reserved0 [30:17] */ 2733 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_BA1_RESERVED0_MASK 0x7ffe0000 2734 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_BA1_RESERVED0_ALIGN 0 2735 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_BA1_RESERVED0_BITS 14 2736 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_BA1_RESERVED0_SHIFT 17 2737 2738 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_BA1 :: FORCE [16:16] */ 2739 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_BA1_FORCE_MASK 0x00010000 2740 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_BA1_FORCE_ALIGN 0 2741 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_BA1_FORCE_BITS 1 2742 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_BA1_FORCE_SHIFT 16 2743 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_BA1_FORCE_DEFAULT 0x00000000 2744 2745 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_BA1 :: reserved1 [15:13] */ 2746 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_BA1_RESERVED1_MASK 0x0000e000 2747 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_BA1_RESERVED1_ALIGN 0 2748 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_BA1_RESERVED1_BITS 3 2749 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_BA1_RESERVED1_SHIFT 13 2750 2751 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_BA1 :: ADJ_EN [12:12] */ 2752 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_BA1_ADJ_EN_MASK 0x00001000 2753 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_BA1_ADJ_EN_ALIGN 0 2754 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_BA1_ADJ_EN_BITS 1 2755 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_BA1_ADJ_EN_SHIFT 12 2756 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_BA1_ADJ_EN_DEFAULT 0x00000000 2757 2758 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_BA1 :: reserved2 [11:09] */ 2759 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_BA1_RESERVED2_MASK 0x00000e00 2760 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_BA1_RESERVED2_ALIGN 0 2761 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_BA1_RESERVED2_BITS 3 2762 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_BA1_RESERVED2_SHIFT 9 2763 2764 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_BA1 :: VDL_STEP [08:00] */ 2765 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_BA1_VDL_STEP_MASK 0x000001ff 2766 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_BA1_VDL_STEP_ALIGN 0 2767 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_BA1_VDL_STEP_BITS 9 2768 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_BA1_VDL_STEP_SHIFT 0 2769 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_BA1_VDL_STEP_DEFAULT 0x00000000 2770 2771 /*************************************************************************** 2772 *VDL_CONTROL_BA2 - DDR interface signal BA[2] VDL control register 2773 */ 2774 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_BA2 :: BUSY [31:31] */ 2775 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_BA2_BUSY_MASK 0x80000000 2776 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_BA2_BUSY_ALIGN 0 2777 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_BA2_BUSY_BITS 1 2778 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_BA2_BUSY_SHIFT 31 2779 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_BA2_BUSY_DEFAULT 0x00000000 2780 2781 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_BA2 :: reserved0 [30:17] */ 2782 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_BA2_RESERVED0_MASK 0x7ffe0000 2783 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_BA2_RESERVED0_ALIGN 0 2784 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_BA2_RESERVED0_BITS 14 2785 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_BA2_RESERVED0_SHIFT 17 2786 2787 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_BA2 :: FORCE [16:16] */ 2788 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_BA2_FORCE_MASK 0x00010000 2789 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_BA2_FORCE_ALIGN 0 2790 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_BA2_FORCE_BITS 1 2791 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_BA2_FORCE_SHIFT 16 2792 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_BA2_FORCE_DEFAULT 0x00000000 2793 2794 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_BA2 :: reserved1 [15:13] */ 2795 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_BA2_RESERVED1_MASK 0x0000e000 2796 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_BA2_RESERVED1_ALIGN 0 2797 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_BA2_RESERVED1_BITS 3 2798 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_BA2_RESERVED1_SHIFT 13 2799 2800 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_BA2 :: ADJ_EN [12:12] */ 2801 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_BA2_ADJ_EN_MASK 0x00001000 2802 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_BA2_ADJ_EN_ALIGN 0 2803 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_BA2_ADJ_EN_BITS 1 2804 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_BA2_ADJ_EN_SHIFT 12 2805 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_BA2_ADJ_EN_DEFAULT 0x00000000 2806 2807 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_BA2 :: reserved2 [11:09] */ 2808 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_BA2_RESERVED2_MASK 0x00000e00 2809 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_BA2_RESERVED2_ALIGN 0 2810 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_BA2_RESERVED2_BITS 3 2811 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_BA2_RESERVED2_SHIFT 9 2812 2813 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_BA2 :: VDL_STEP [08:00] */ 2814 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_BA2_VDL_STEP_MASK 0x000001ff 2815 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_BA2_VDL_STEP_ALIGN 0 2816 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_BA2_VDL_STEP_BITS 9 2817 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_BA2_VDL_STEP_SHIFT 0 2818 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_BA2_VDL_STEP_DEFAULT 0x00000000 2819 2820 /*************************************************************************** 2821 *VDL_CONTROL_AUX0 - DDR interface signal AUX[0] VDL control register 2822 */ 2823 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_AUX0 :: BUSY [31:31] */ 2824 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AUX0_BUSY_MASK 0x80000000 2825 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AUX0_BUSY_ALIGN 0 2826 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AUX0_BUSY_BITS 1 2827 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AUX0_BUSY_SHIFT 31 2828 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AUX0_BUSY_DEFAULT 0x00000000 2829 2830 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_AUX0 :: reserved0 [30:17] */ 2831 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AUX0_RESERVED0_MASK 0x7ffe0000 2832 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AUX0_RESERVED0_ALIGN 0 2833 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AUX0_RESERVED0_BITS 14 2834 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AUX0_RESERVED0_SHIFT 17 2835 2836 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_AUX0 :: FORCE [16:16] */ 2837 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AUX0_FORCE_MASK 0x00010000 2838 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AUX0_FORCE_ALIGN 0 2839 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AUX0_FORCE_BITS 1 2840 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AUX0_FORCE_SHIFT 16 2841 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AUX0_FORCE_DEFAULT 0x00000000 2842 2843 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_AUX0 :: reserved1 [15:13] */ 2844 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AUX0_RESERVED1_MASK 0x0000e000 2845 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AUX0_RESERVED1_ALIGN 0 2846 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AUX0_RESERVED1_BITS 3 2847 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AUX0_RESERVED1_SHIFT 13 2848 2849 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_AUX0 :: ADJ_EN [12:12] */ 2850 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AUX0_ADJ_EN_MASK 0x00001000 2851 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AUX0_ADJ_EN_ALIGN 0 2852 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AUX0_ADJ_EN_BITS 1 2853 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AUX0_ADJ_EN_SHIFT 12 2854 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AUX0_ADJ_EN_DEFAULT 0x00000000 2855 2856 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_AUX0 :: reserved2 [11:09] */ 2857 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AUX0_RESERVED2_MASK 0x00000e00 2858 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AUX0_RESERVED2_ALIGN 0 2859 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AUX0_RESERVED2_BITS 3 2860 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AUX0_RESERVED2_SHIFT 9 2861 2862 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_AUX0 :: VDL_STEP [08:00] */ 2863 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AUX0_VDL_STEP_MASK 0x000001ff 2864 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AUX0_VDL_STEP_ALIGN 0 2865 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AUX0_VDL_STEP_BITS 9 2866 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AUX0_VDL_STEP_SHIFT 0 2867 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AUX0_VDL_STEP_DEFAULT 0x00000000 2868 2869 /*************************************************************************** 2870 *VDL_CONTROL_AUX1 - DDR interface signal AUX[1] VDL control register 2871 */ 2872 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_AUX1 :: BUSY [31:31] */ 2873 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AUX1_BUSY_MASK 0x80000000 2874 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AUX1_BUSY_ALIGN 0 2875 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AUX1_BUSY_BITS 1 2876 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AUX1_BUSY_SHIFT 31 2877 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AUX1_BUSY_DEFAULT 0x00000000 2878 2879 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_AUX1 :: reserved0 [30:17] */ 2880 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AUX1_RESERVED0_MASK 0x7ffe0000 2881 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AUX1_RESERVED0_ALIGN 0 2882 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AUX1_RESERVED0_BITS 14 2883 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AUX1_RESERVED0_SHIFT 17 2884 2885 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_AUX1 :: FORCE [16:16] */ 2886 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AUX1_FORCE_MASK 0x00010000 2887 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AUX1_FORCE_ALIGN 0 2888 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AUX1_FORCE_BITS 1 2889 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AUX1_FORCE_SHIFT 16 2890 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AUX1_FORCE_DEFAULT 0x00000000 2891 2892 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_AUX1 :: reserved1 [15:13] */ 2893 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AUX1_RESERVED1_MASK 0x0000e000 2894 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AUX1_RESERVED1_ALIGN 0 2895 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AUX1_RESERVED1_BITS 3 2896 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AUX1_RESERVED1_SHIFT 13 2897 2898 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_AUX1 :: ADJ_EN [12:12] */ 2899 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AUX1_ADJ_EN_MASK 0x00001000 2900 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AUX1_ADJ_EN_ALIGN 0 2901 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AUX1_ADJ_EN_BITS 1 2902 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AUX1_ADJ_EN_SHIFT 12 2903 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AUX1_ADJ_EN_DEFAULT 0x00000000 2904 2905 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_AUX1 :: reserved2 [11:09] */ 2906 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AUX1_RESERVED2_MASK 0x00000e00 2907 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AUX1_RESERVED2_ALIGN 0 2908 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AUX1_RESERVED2_BITS 3 2909 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AUX1_RESERVED2_SHIFT 9 2910 2911 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_AUX1 :: VDL_STEP [08:00] */ 2912 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AUX1_VDL_STEP_MASK 0x000001ff 2913 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AUX1_VDL_STEP_ALIGN 0 2914 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AUX1_VDL_STEP_BITS 9 2915 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AUX1_VDL_STEP_SHIFT 0 2916 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AUX1_VDL_STEP_DEFAULT 0x00000000 2917 2918 /*************************************************************************** 2919 *VDL_CONTROL_AUX2 - DDR interface signal AUX[2] VDL control register 2920 */ 2921 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_AUX2 :: BUSY [31:31] */ 2922 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AUX2_BUSY_MASK 0x80000000 2923 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AUX2_BUSY_ALIGN 0 2924 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AUX2_BUSY_BITS 1 2925 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AUX2_BUSY_SHIFT 31 2926 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AUX2_BUSY_DEFAULT 0x00000000 2927 2928 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_AUX2 :: reserved0 [30:17] */ 2929 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AUX2_RESERVED0_MASK 0x7ffe0000 2930 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AUX2_RESERVED0_ALIGN 0 2931 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AUX2_RESERVED0_BITS 14 2932 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AUX2_RESERVED0_SHIFT 17 2933 2934 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_AUX2 :: FORCE [16:16] */ 2935 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AUX2_FORCE_MASK 0x00010000 2936 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AUX2_FORCE_ALIGN 0 2937 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AUX2_FORCE_BITS 1 2938 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AUX2_FORCE_SHIFT 16 2939 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AUX2_FORCE_DEFAULT 0x00000000 2940 2941 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_AUX2 :: reserved1 [15:13] */ 2942 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AUX2_RESERVED1_MASK 0x0000e000 2943 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AUX2_RESERVED1_ALIGN 0 2944 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AUX2_RESERVED1_BITS 3 2945 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AUX2_RESERVED1_SHIFT 13 2946 2947 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_AUX2 :: ADJ_EN [12:12] */ 2948 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AUX2_ADJ_EN_MASK 0x00001000 2949 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AUX2_ADJ_EN_ALIGN 0 2950 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AUX2_ADJ_EN_BITS 1 2951 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AUX2_ADJ_EN_SHIFT 12 2952 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AUX2_ADJ_EN_DEFAULT 0x00000000 2953 2954 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_AUX2 :: reserved2 [11:09] */ 2955 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AUX2_RESERVED2_MASK 0x00000e00 2956 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AUX2_RESERVED2_ALIGN 0 2957 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AUX2_RESERVED2_BITS 3 2958 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AUX2_RESERVED2_SHIFT 9 2959 2960 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_AUX2 :: VDL_STEP [08:00] */ 2961 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AUX2_VDL_STEP_MASK 0x000001ff 2962 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AUX2_VDL_STEP_ALIGN 0 2963 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AUX2_VDL_STEP_BITS 9 2964 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AUX2_VDL_STEP_SHIFT 0 2965 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AUX2_VDL_STEP_DEFAULT 0x00000000 2966 2967 /*************************************************************************** 2968 *VDL_CONTROL_CS0 - DDR interface signal CS0 VDL control register 2969 */ 2970 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_CS0 :: BUSY [31:31] */ 2971 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_CS0_BUSY_MASK 0x80000000 2972 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_CS0_BUSY_ALIGN 0 2973 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_CS0_BUSY_BITS 1 2974 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_CS0_BUSY_SHIFT 31 2975 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_CS0_BUSY_DEFAULT 0x00000000 2976 2977 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_CS0 :: reserved0 [30:17] */ 2978 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_CS0_RESERVED0_MASK 0x7ffe0000 2979 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_CS0_RESERVED0_ALIGN 0 2980 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_CS0_RESERVED0_BITS 14 2981 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_CS0_RESERVED0_SHIFT 17 2982 2983 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_CS0 :: FORCE [16:16] */ 2984 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_CS0_FORCE_MASK 0x00010000 2985 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_CS0_FORCE_ALIGN 0 2986 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_CS0_FORCE_BITS 1 2987 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_CS0_FORCE_SHIFT 16 2988 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_CS0_FORCE_DEFAULT 0x00000000 2989 2990 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_CS0 :: reserved1 [15:13] */ 2991 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_CS0_RESERVED1_MASK 0x0000e000 2992 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_CS0_RESERVED1_ALIGN 0 2993 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_CS0_RESERVED1_BITS 3 2994 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_CS0_RESERVED1_SHIFT 13 2995 2996 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_CS0 :: ADJ_EN [12:12] */ 2997 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_CS0_ADJ_EN_MASK 0x00001000 2998 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_CS0_ADJ_EN_ALIGN 0 2999 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_CS0_ADJ_EN_BITS 1 3000 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_CS0_ADJ_EN_SHIFT 12 3001 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_CS0_ADJ_EN_DEFAULT 0x00000000 3002 3003 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_CS0 :: reserved2 [11:09] */ 3004 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_CS0_RESERVED2_MASK 0x00000e00 3005 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_CS0_RESERVED2_ALIGN 0 3006 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_CS0_RESERVED2_BITS 3 3007 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_CS0_RESERVED2_SHIFT 9 3008 3009 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_CS0 :: VDL_STEP [08:00] */ 3010 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_CS0_VDL_STEP_MASK 0x000001ff 3011 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_CS0_VDL_STEP_ALIGN 0 3012 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_CS0_VDL_STEP_BITS 9 3013 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_CS0_VDL_STEP_SHIFT 0 3014 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_CS0_VDL_STEP_DEFAULT 0x00000000 3015 3016 /*************************************************************************** 3017 *VDL_CONTROL_CS1 - DDR interface signal CS1 VDL control register 3018 */ 3019 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_CS1 :: BUSY [31:31] */ 3020 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_CS1_BUSY_MASK 0x80000000 3021 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_CS1_BUSY_ALIGN 0 3022 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_CS1_BUSY_BITS 1 3023 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_CS1_BUSY_SHIFT 31 3024 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_CS1_BUSY_DEFAULT 0x00000000 3025 3026 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_CS1 :: reserved0 [30:17] */ 3027 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_CS1_RESERVED0_MASK 0x7ffe0000 3028 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_CS1_RESERVED0_ALIGN 0 3029 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_CS1_RESERVED0_BITS 14 3030 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_CS1_RESERVED0_SHIFT 17 3031 3032 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_CS1 :: FORCE [16:16] */ 3033 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_CS1_FORCE_MASK 0x00010000 3034 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_CS1_FORCE_ALIGN 0 3035 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_CS1_FORCE_BITS 1 3036 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_CS1_FORCE_SHIFT 16 3037 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_CS1_FORCE_DEFAULT 0x00000000 3038 3039 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_CS1 :: reserved1 [15:13] */ 3040 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_CS1_RESERVED1_MASK 0x0000e000 3041 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_CS1_RESERVED1_ALIGN 0 3042 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_CS1_RESERVED1_BITS 3 3043 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_CS1_RESERVED1_SHIFT 13 3044 3045 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_CS1 :: ADJ_EN [12:12] */ 3046 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_CS1_ADJ_EN_MASK 0x00001000 3047 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_CS1_ADJ_EN_ALIGN 0 3048 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_CS1_ADJ_EN_BITS 1 3049 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_CS1_ADJ_EN_SHIFT 12 3050 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_CS1_ADJ_EN_DEFAULT 0x00000000 3051 3052 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_CS1 :: reserved2 [11:09] */ 3053 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_CS1_RESERVED2_MASK 0x00000e00 3054 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_CS1_RESERVED2_ALIGN 0 3055 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_CS1_RESERVED2_BITS 3 3056 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_CS1_RESERVED2_SHIFT 9 3057 3058 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_CS1 :: VDL_STEP [08:00] */ 3059 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_CS1_VDL_STEP_MASK 0x000001ff 3060 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_CS1_VDL_STEP_ALIGN 0 3061 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_CS1_VDL_STEP_BITS 9 3062 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_CS1_VDL_STEP_SHIFT 0 3063 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_CS1_VDL_STEP_DEFAULT 0x00000000 3064 3065 /*************************************************************************** 3066 *VDL_CONTROL_PAR - DDR interface signal PAR VDL control register 3067 */ 3068 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_PAR :: BUSY [31:31] */ 3069 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_PAR_BUSY_MASK 0x80000000 3070 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_PAR_BUSY_ALIGN 0 3071 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_PAR_BUSY_BITS 1 3072 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_PAR_BUSY_SHIFT 31 3073 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_PAR_BUSY_DEFAULT 0x00000000 3074 3075 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_PAR :: reserved0 [30:17] */ 3076 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_PAR_RESERVED0_MASK 0x7ffe0000 3077 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_PAR_RESERVED0_ALIGN 0 3078 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_PAR_RESERVED0_BITS 14 3079 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_PAR_RESERVED0_SHIFT 17 3080 3081 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_PAR :: FORCE [16:16] */ 3082 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_PAR_FORCE_MASK 0x00010000 3083 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_PAR_FORCE_ALIGN 0 3084 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_PAR_FORCE_BITS 1 3085 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_PAR_FORCE_SHIFT 16 3086 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_PAR_FORCE_DEFAULT 0x00000000 3087 3088 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_PAR :: reserved1 [15:13] */ 3089 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_PAR_RESERVED1_MASK 0x0000e000 3090 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_PAR_RESERVED1_ALIGN 0 3091 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_PAR_RESERVED1_BITS 3 3092 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_PAR_RESERVED1_SHIFT 13 3093 3094 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_PAR :: ADJ_EN [12:12] */ 3095 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_PAR_ADJ_EN_MASK 0x00001000 3096 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_PAR_ADJ_EN_ALIGN 0 3097 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_PAR_ADJ_EN_BITS 1 3098 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_PAR_ADJ_EN_SHIFT 12 3099 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_PAR_ADJ_EN_DEFAULT 0x00000000 3100 3101 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_PAR :: reserved2 [11:09] */ 3102 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_PAR_RESERVED2_MASK 0x00000e00 3103 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_PAR_RESERVED2_ALIGN 0 3104 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_PAR_RESERVED2_BITS 3 3105 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_PAR_RESERVED2_SHIFT 9 3106 3107 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_PAR :: VDL_STEP [08:00] */ 3108 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_PAR_VDL_STEP_MASK 0x000001ff 3109 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_PAR_VDL_STEP_ALIGN 0 3110 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_PAR_VDL_STEP_BITS 9 3111 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_PAR_VDL_STEP_SHIFT 0 3112 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_PAR_VDL_STEP_DEFAULT 0x00000000 3113 3114 /*************************************************************************** 3115 *VDL_CONTROL_RAS_N - DDR interface signal RAS_N VDL control register 3116 */ 3117 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_RAS_N :: BUSY [31:31] */ 3118 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_RAS_N_BUSY_MASK 0x80000000 3119 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_RAS_N_BUSY_ALIGN 0 3120 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_RAS_N_BUSY_BITS 1 3121 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_RAS_N_BUSY_SHIFT 31 3122 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_RAS_N_BUSY_DEFAULT 0x00000000 3123 3124 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_RAS_N :: reserved0 [30:17] */ 3125 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_RAS_N_RESERVED0_MASK 0x7ffe0000 3126 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_RAS_N_RESERVED0_ALIGN 0 3127 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_RAS_N_RESERVED0_BITS 14 3128 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_RAS_N_RESERVED0_SHIFT 17 3129 3130 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_RAS_N :: FORCE [16:16] */ 3131 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_RAS_N_FORCE_MASK 0x00010000 3132 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_RAS_N_FORCE_ALIGN 0 3133 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_RAS_N_FORCE_BITS 1 3134 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_RAS_N_FORCE_SHIFT 16 3135 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_RAS_N_FORCE_DEFAULT 0x00000000 3136 3137 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_RAS_N :: reserved1 [15:13] */ 3138 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_RAS_N_RESERVED1_MASK 0x0000e000 3139 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_RAS_N_RESERVED1_ALIGN 0 3140 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_RAS_N_RESERVED1_BITS 3 3141 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_RAS_N_RESERVED1_SHIFT 13 3142 3143 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_RAS_N :: ADJ_EN [12:12] */ 3144 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_RAS_N_ADJ_EN_MASK 0x00001000 3145 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_RAS_N_ADJ_EN_ALIGN 0 3146 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_RAS_N_ADJ_EN_BITS 1 3147 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_RAS_N_ADJ_EN_SHIFT 12 3148 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_RAS_N_ADJ_EN_DEFAULT 0x00000000 3149 3150 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_RAS_N :: reserved2 [11:09] */ 3151 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_RAS_N_RESERVED2_MASK 0x00000e00 3152 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_RAS_N_RESERVED2_ALIGN 0 3153 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_RAS_N_RESERVED2_BITS 3 3154 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_RAS_N_RESERVED2_SHIFT 9 3155 3156 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_RAS_N :: VDL_STEP [08:00] */ 3157 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_RAS_N_VDL_STEP_MASK 0x000001ff 3158 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_RAS_N_VDL_STEP_ALIGN 0 3159 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_RAS_N_VDL_STEP_BITS 9 3160 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_RAS_N_VDL_STEP_SHIFT 0 3161 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_RAS_N_VDL_STEP_DEFAULT 0x00000000 3162 3163 /*************************************************************************** 3164 *VDL_CONTROL_CAS_N - DDR interface signal CAS_N VDL control register 3165 */ 3166 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_CAS_N :: BUSY [31:31] */ 3167 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_CAS_N_BUSY_MASK 0x80000000 3168 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_CAS_N_BUSY_ALIGN 0 3169 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_CAS_N_BUSY_BITS 1 3170 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_CAS_N_BUSY_SHIFT 31 3171 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_CAS_N_BUSY_DEFAULT 0x00000000 3172 3173 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_CAS_N :: reserved0 [30:17] */ 3174 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_CAS_N_RESERVED0_MASK 0x7ffe0000 3175 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_CAS_N_RESERVED0_ALIGN 0 3176 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_CAS_N_RESERVED0_BITS 14 3177 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_CAS_N_RESERVED0_SHIFT 17 3178 3179 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_CAS_N :: FORCE [16:16] */ 3180 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_CAS_N_FORCE_MASK 0x00010000 3181 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_CAS_N_FORCE_ALIGN 0 3182 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_CAS_N_FORCE_BITS 1 3183 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_CAS_N_FORCE_SHIFT 16 3184 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_CAS_N_FORCE_DEFAULT 0x00000000 3185 3186 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_CAS_N :: reserved1 [15:13] */ 3187 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_CAS_N_RESERVED1_MASK 0x0000e000 3188 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_CAS_N_RESERVED1_ALIGN 0 3189 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_CAS_N_RESERVED1_BITS 3 3190 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_CAS_N_RESERVED1_SHIFT 13 3191 3192 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_CAS_N :: ADJ_EN [12:12] */ 3193 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_CAS_N_ADJ_EN_MASK 0x00001000 3194 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_CAS_N_ADJ_EN_ALIGN 0 3195 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_CAS_N_ADJ_EN_BITS 1 3196 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_CAS_N_ADJ_EN_SHIFT 12 3197 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_CAS_N_ADJ_EN_DEFAULT 0x00000000 3198 3199 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_CAS_N :: reserved2 [11:09] */ 3200 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_CAS_N_RESERVED2_MASK 0x00000e00 3201 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_CAS_N_RESERVED2_ALIGN 0 3202 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_CAS_N_RESERVED2_BITS 3 3203 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_CAS_N_RESERVED2_SHIFT 9 3204 3205 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_CAS_N :: VDL_STEP [08:00] */ 3206 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_CAS_N_VDL_STEP_MASK 0x000001ff 3207 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_CAS_N_VDL_STEP_ALIGN 0 3208 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_CAS_N_VDL_STEP_BITS 9 3209 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_CAS_N_VDL_STEP_SHIFT 0 3210 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_CAS_N_VDL_STEP_DEFAULT 0x00000000 3211 3212 /*************************************************************************** 3213 *VDL_CONTROL_CKE - DDR interface signal CKE0 VDL control register 3214 */ 3215 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_CKE :: BUSY [31:31] */ 3216 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_CKE_BUSY_MASK 0x80000000 3217 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_CKE_BUSY_ALIGN 0 3218 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_CKE_BUSY_BITS 1 3219 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_CKE_BUSY_SHIFT 31 3220 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_CKE_BUSY_DEFAULT 0x00000000 3221 3222 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_CKE :: reserved0 [30:17] */ 3223 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_CKE_RESERVED0_MASK 0x7ffe0000 3224 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_CKE_RESERVED0_ALIGN 0 3225 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_CKE_RESERVED0_BITS 14 3226 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_CKE_RESERVED0_SHIFT 17 3227 3228 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_CKE :: FORCE [16:16] */ 3229 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_CKE_FORCE_MASK 0x00010000 3230 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_CKE_FORCE_ALIGN 0 3231 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_CKE_FORCE_BITS 1 3232 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_CKE_FORCE_SHIFT 16 3233 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_CKE_FORCE_DEFAULT 0x00000000 3234 3235 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_CKE :: reserved1 [15:13] */ 3236 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_CKE_RESERVED1_MASK 0x0000e000 3237 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_CKE_RESERVED1_ALIGN 0 3238 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_CKE_RESERVED1_BITS 3 3239 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_CKE_RESERVED1_SHIFT 13 3240 3241 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_CKE :: ADJ_EN [12:12] */ 3242 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_CKE_ADJ_EN_MASK 0x00001000 3243 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_CKE_ADJ_EN_ALIGN 0 3244 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_CKE_ADJ_EN_BITS 1 3245 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_CKE_ADJ_EN_SHIFT 12 3246 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_CKE_ADJ_EN_DEFAULT 0x00000000 3247 3248 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_CKE :: reserved2 [11:09] */ 3249 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_CKE_RESERVED2_MASK 0x00000e00 3250 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_CKE_RESERVED2_ALIGN 0 3251 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_CKE_RESERVED2_BITS 3 3252 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_CKE_RESERVED2_SHIFT 9 3253 3254 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_CKE :: VDL_STEP [08:00] */ 3255 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_CKE_VDL_STEP_MASK 0x000001ff 3256 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_CKE_VDL_STEP_ALIGN 0 3257 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_CKE_VDL_STEP_BITS 9 3258 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_CKE_VDL_STEP_SHIFT 0 3259 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_CKE_VDL_STEP_DEFAULT 0x00000000 3260 3261 /*************************************************************************** 3262 *VDL_CONTROL_RST_N - DDR interface signal RST_N VDL control register 3263 */ 3264 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_RST_N :: BUSY [31:31] */ 3265 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_RST_N_BUSY_MASK 0x80000000 3266 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_RST_N_BUSY_ALIGN 0 3267 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_RST_N_BUSY_BITS 1 3268 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_RST_N_BUSY_SHIFT 31 3269 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_RST_N_BUSY_DEFAULT 0x00000000 3270 3271 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_RST_N :: reserved0 [30:17] */ 3272 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_RST_N_RESERVED0_MASK 0x7ffe0000 3273 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_RST_N_RESERVED0_ALIGN 0 3274 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_RST_N_RESERVED0_BITS 14 3275 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_RST_N_RESERVED0_SHIFT 17 3276 3277 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_RST_N :: FORCE [16:16] */ 3278 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_RST_N_FORCE_MASK 0x00010000 3279 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_RST_N_FORCE_ALIGN 0 3280 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_RST_N_FORCE_BITS 1 3281 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_RST_N_FORCE_SHIFT 16 3282 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_RST_N_FORCE_DEFAULT 0x00000000 3283 3284 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_RST_N :: reserved1 [15:13] */ 3285 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_RST_N_RESERVED1_MASK 0x0000e000 3286 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_RST_N_RESERVED1_ALIGN 0 3287 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_RST_N_RESERVED1_BITS 3 3288 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_RST_N_RESERVED1_SHIFT 13 3289 3290 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_RST_N :: ADJ_EN [12:12] */ 3291 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_RST_N_ADJ_EN_MASK 0x00001000 3292 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_RST_N_ADJ_EN_ALIGN 0 3293 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_RST_N_ADJ_EN_BITS 1 3294 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_RST_N_ADJ_EN_SHIFT 12 3295 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_RST_N_ADJ_EN_DEFAULT 0x00000000 3296 3297 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_RST_N :: reserved2 [11:09] */ 3298 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_RST_N_RESERVED2_MASK 0x00000e00 3299 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_RST_N_RESERVED2_ALIGN 0 3300 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_RST_N_RESERVED2_BITS 3 3301 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_RST_N_RESERVED2_SHIFT 9 3302 3303 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_RST_N :: VDL_STEP [08:00] */ 3304 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_RST_N_VDL_STEP_MASK 0x000001ff 3305 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_RST_N_VDL_STEP_ALIGN 0 3306 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_RST_N_VDL_STEP_BITS 9 3307 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_RST_N_VDL_STEP_SHIFT 0 3308 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_RST_N_VDL_STEP_DEFAULT 0x00000000 3309 3310 /*************************************************************************** 3311 *VDL_CONTROL_ODT - DDR interface signal ODT0 VDL control register 3312 */ 3313 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_ODT :: BUSY [31:31] */ 3314 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_ODT_BUSY_MASK 0x80000000 3315 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_ODT_BUSY_ALIGN 0 3316 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_ODT_BUSY_BITS 1 3317 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_ODT_BUSY_SHIFT 31 3318 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_ODT_BUSY_DEFAULT 0x00000000 3319 3320 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_ODT :: reserved0 [30:17] */ 3321 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_ODT_RESERVED0_MASK 0x7ffe0000 3322 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_ODT_RESERVED0_ALIGN 0 3323 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_ODT_RESERVED0_BITS 14 3324 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_ODT_RESERVED0_SHIFT 17 3325 3326 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_ODT :: FORCE [16:16] */ 3327 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_ODT_FORCE_MASK 0x00010000 3328 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_ODT_FORCE_ALIGN 0 3329 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_ODT_FORCE_BITS 1 3330 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_ODT_FORCE_SHIFT 16 3331 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_ODT_FORCE_DEFAULT 0x00000000 3332 3333 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_ODT :: reserved1 [15:13] */ 3334 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_ODT_RESERVED1_MASK 0x0000e000 3335 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_ODT_RESERVED1_ALIGN 0 3336 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_ODT_RESERVED1_BITS 3 3337 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_ODT_RESERVED1_SHIFT 13 3338 3339 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_ODT :: ADJ_EN [12:12] */ 3340 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_ODT_ADJ_EN_MASK 0x00001000 3341 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_ODT_ADJ_EN_ALIGN 0 3342 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_ODT_ADJ_EN_BITS 1 3343 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_ODT_ADJ_EN_SHIFT 12 3344 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_ODT_ADJ_EN_DEFAULT 0x00000000 3345 3346 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_ODT :: reserved2 [11:09] */ 3347 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_ODT_RESERVED2_MASK 0x00000e00 3348 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_ODT_RESERVED2_ALIGN 0 3349 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_ODT_RESERVED2_BITS 3 3350 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_ODT_RESERVED2_SHIFT 9 3351 3352 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_ODT :: VDL_STEP [08:00] */ 3353 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_ODT_VDL_STEP_MASK 0x000001ff 3354 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_ODT_VDL_STEP_ALIGN 0 3355 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_ODT_VDL_STEP_BITS 9 3356 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_ODT_VDL_STEP_SHIFT 0 3357 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_ODT_VDL_STEP_DEFAULT 0x00000000 3358 3359 /*************************************************************************** 3360 *VDL_CONTROL_WE_N - DDR interface signal WE_N VDL control register 3361 */ 3362 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_WE_N :: BUSY [31:31] */ 3363 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_WE_N_BUSY_MASK 0x80000000 3364 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_WE_N_BUSY_ALIGN 0 3365 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_WE_N_BUSY_BITS 1 3366 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_WE_N_BUSY_SHIFT 31 3367 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_WE_N_BUSY_DEFAULT 0x00000000 3368 3369 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_WE_N :: reserved0 [30:17] */ 3370 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_WE_N_RESERVED0_MASK 0x7ffe0000 3371 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_WE_N_RESERVED0_ALIGN 0 3372 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_WE_N_RESERVED0_BITS 14 3373 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_WE_N_RESERVED0_SHIFT 17 3374 3375 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_WE_N :: FORCE [16:16] */ 3376 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_WE_N_FORCE_MASK 0x00010000 3377 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_WE_N_FORCE_ALIGN 0 3378 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_WE_N_FORCE_BITS 1 3379 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_WE_N_FORCE_SHIFT 16 3380 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_WE_N_FORCE_DEFAULT 0x00000000 3381 3382 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_WE_N :: reserved1 [15:13] */ 3383 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_WE_N_RESERVED1_MASK 0x0000e000 3384 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_WE_N_RESERVED1_ALIGN 0 3385 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_WE_N_RESERVED1_BITS 3 3386 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_WE_N_RESERVED1_SHIFT 13 3387 3388 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_WE_N :: ADJ_EN [12:12] */ 3389 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_WE_N_ADJ_EN_MASK 0x00001000 3390 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_WE_N_ADJ_EN_ALIGN 0 3391 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_WE_N_ADJ_EN_BITS 1 3392 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_WE_N_ADJ_EN_SHIFT 12 3393 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_WE_N_ADJ_EN_DEFAULT 0x00000000 3394 3395 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_WE_N :: reserved2 [11:09] */ 3396 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_WE_N_RESERVED2_MASK 0x00000e00 3397 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_WE_N_RESERVED2_ALIGN 0 3398 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_WE_N_RESERVED2_BITS 3 3399 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_WE_N_RESERVED2_SHIFT 9 3400 3401 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_WE_N :: VDL_STEP [08:00] */ 3402 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_WE_N_VDL_STEP_MASK 0x000001ff 3403 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_WE_N_VDL_STEP_ALIGN 0 3404 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_WE_N_VDL_STEP_BITS 9 3405 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_WE_N_VDL_STEP_SHIFT 0 3406 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_WE_N_VDL_STEP_DEFAULT 0x00000000 3407 3408 /*************************************************************************** 3409 *VDL_CONTROL_DDR_CK_P - DDR interface signal DDR_CK-P VDL control register 3410 */ 3411 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_DDR_CK_P :: BUSY [31:31] */ 3412 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_P_BUSY_MASK 0x80000000 3413 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_P_BUSY_ALIGN 0 3414 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_P_BUSY_BITS 1 3415 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_P_BUSY_SHIFT 31 3416 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_P_BUSY_DEFAULT 0x00000000 3417 3418 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_DDR_CK_P :: reserved0 [30:17] */ 3419 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_P_RESERVED0_MASK 0x7ffe0000 3420 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_P_RESERVED0_ALIGN 0 3421 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_P_RESERVED0_BITS 14 3422 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_P_RESERVED0_SHIFT 17 3423 3424 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_DDR_CK_P :: FORCE [16:16] */ 3425 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_P_FORCE_MASK 0x00010000 3426 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_P_FORCE_ALIGN 0 3427 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_P_FORCE_BITS 1 3428 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_P_FORCE_SHIFT 16 3429 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_P_FORCE_DEFAULT 0x00000000 3430 3431 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_DDR_CK_P :: reserved1 [15:13] */ 3432 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_P_RESERVED1_MASK 0x0000e000 3433 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_P_RESERVED1_ALIGN 0 3434 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_P_RESERVED1_BITS 3 3435 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_P_RESERVED1_SHIFT 13 3436 3437 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_DDR_CK_P :: ADJ_EN [12:12] */ 3438 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_P_ADJ_EN_MASK 0x00001000 3439 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_P_ADJ_EN_ALIGN 0 3440 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_P_ADJ_EN_BITS 1 3441 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_P_ADJ_EN_SHIFT 12 3442 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_P_ADJ_EN_DEFAULT 0x00000000 3443 3444 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_DDR_CK_P :: reserved2 [11:09] */ 3445 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_P_RESERVED2_MASK 0x00000e00 3446 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_P_RESERVED2_ALIGN 0 3447 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_P_RESERVED2_BITS 3 3448 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_P_RESERVED2_SHIFT 9 3449 3450 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_DDR_CK_P :: VDL_STEP [08:00] */ 3451 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_P_VDL_STEP_MASK 0x000001ff 3452 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_P_VDL_STEP_ALIGN 0 3453 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_P_VDL_STEP_BITS 9 3454 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_P_VDL_STEP_SHIFT 0 3455 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_P_VDL_STEP_DEFAULT 0x00000000 3456 3457 /*************************************************************************** 3458 *VDL_CONTROL_DDR_CK_N - DDR interface signal DDR_CK-N VDL control register 3459 */ 3460 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_DDR_CK_N :: BUSY [31:31] */ 3461 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_N_BUSY_MASK 0x80000000 3462 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_N_BUSY_ALIGN 0 3463 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_N_BUSY_BITS 1 3464 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_N_BUSY_SHIFT 31 3465 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_N_BUSY_DEFAULT 0x00000000 3466 3467 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_DDR_CK_N :: reserved0 [30:17] */ 3468 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_N_RESERVED0_MASK 0x7ffe0000 3469 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_N_RESERVED0_ALIGN 0 3470 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_N_RESERVED0_BITS 14 3471 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_N_RESERVED0_SHIFT 17 3472 3473 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_DDR_CK_N :: FORCE [16:16] */ 3474 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_N_FORCE_MASK 0x00010000 3475 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_N_FORCE_ALIGN 0 3476 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_N_FORCE_BITS 1 3477 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_N_FORCE_SHIFT 16 3478 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_N_FORCE_DEFAULT 0x00000000 3479 3480 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_DDR_CK_N :: reserved1 [15:13] */ 3481 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_N_RESERVED1_MASK 0x0000e000 3482 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_N_RESERVED1_ALIGN 0 3483 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_N_RESERVED1_BITS 3 3484 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_N_RESERVED1_SHIFT 13 3485 3486 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_DDR_CK_N :: ADJ_EN [12:12] */ 3487 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_N_ADJ_EN_MASK 0x00001000 3488 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_N_ADJ_EN_ALIGN 0 3489 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_N_ADJ_EN_BITS 1 3490 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_N_ADJ_EN_SHIFT 12 3491 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_N_ADJ_EN_DEFAULT 0x00000000 3492 3493 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_DDR_CK_N :: reserved2 [11:09] */ 3494 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_N_RESERVED2_MASK 0x00000e00 3495 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_N_RESERVED2_ALIGN 0 3496 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_N_RESERVED2_BITS 3 3497 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_N_RESERVED2_SHIFT 9 3498 3499 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CONTROL_DDR_CK_N :: VDL_STEP [08:00] */ 3500 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_N_VDL_STEP_MASK 0x000001ff 3501 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_N_VDL_STEP_ALIGN 0 3502 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_N_VDL_STEP_BITS 9 3503 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_N_VDL_STEP_SHIFT 0 3504 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_N_VDL_STEP_DEFAULT 0x00000000 3505 3506 /*************************************************************************** 3507 *VDL_CLK_CONTROL - DDR interface signal Write Leveling CLK VDL control register 3508 */ 3509 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CLK_CONTROL :: BUSY [31:31] */ 3510 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CLK_CONTROL_BUSY_MASK 0x80000000 3511 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CLK_CONTROL_BUSY_ALIGN 0 3512 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CLK_CONTROL_BUSY_BITS 1 3513 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CLK_CONTROL_BUSY_SHIFT 31 3514 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CLK_CONTROL_BUSY_DEFAULT 0x00000000 3515 3516 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CLK_CONTROL :: reserved0 [30:17] */ 3517 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CLK_CONTROL_RESERVED0_MASK 0x7ffe0000 3518 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CLK_CONTROL_RESERVED0_ALIGN 0 3519 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CLK_CONTROL_RESERVED0_BITS 14 3520 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CLK_CONTROL_RESERVED0_SHIFT 17 3521 3522 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CLK_CONTROL :: FORCE [16:16] */ 3523 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CLK_CONTROL_FORCE_MASK 0x00010000 3524 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CLK_CONTROL_FORCE_ALIGN 0 3525 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CLK_CONTROL_FORCE_BITS 1 3526 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CLK_CONTROL_FORCE_SHIFT 16 3527 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CLK_CONTROL_FORCE_DEFAULT 0x00000000 3528 3529 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CLK_CONTROL :: reserved1 [15:13] */ 3530 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CLK_CONTROL_RESERVED1_MASK 0x0000e000 3531 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CLK_CONTROL_RESERVED1_ALIGN 0 3532 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CLK_CONTROL_RESERVED1_BITS 3 3533 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CLK_CONTROL_RESERVED1_SHIFT 13 3534 3535 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CLK_CONTROL :: ADJ_EN [12:12] */ 3536 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CLK_CONTROL_ADJ_EN_MASK 0x00001000 3537 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CLK_CONTROL_ADJ_EN_ALIGN 0 3538 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CLK_CONTROL_ADJ_EN_BITS 1 3539 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CLK_CONTROL_ADJ_EN_SHIFT 12 3540 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CLK_CONTROL_ADJ_EN_DEFAULT 0x00000000 3541 3542 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CLK_CONTROL :: reserved2 [11:09] */ 3543 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CLK_CONTROL_RESERVED2_MASK 0x00000e00 3544 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CLK_CONTROL_RESERVED2_ALIGN 0 3545 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CLK_CONTROL_RESERVED2_BITS 3 3546 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CLK_CONTROL_RESERVED2_SHIFT 9 3547 3548 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_CLK_CONTROL :: VDL_STEP [08:00] */ 3549 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CLK_CONTROL_VDL_STEP_MASK 0x000001ff 3550 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CLK_CONTROL_VDL_STEP_ALIGN 0 3551 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CLK_CONTROL_VDL_STEP_BITS 9 3552 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CLK_CONTROL_VDL_STEP_SHIFT 0 3553 #define DDR34_E0_PHY_CONTROL_REGS_VDL_CLK_CONTROL_VDL_STEP_DEFAULT 0x00000000 3554 3555 /*************************************************************************** 3556 *VDL_LDE_CONTROL - DDR interface signal Write Leveling Capture Enable VDL control register 3557 */ 3558 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_LDE_CONTROL :: BUSY [31:31] */ 3559 #define DDR34_E0_PHY_CONTROL_REGS_VDL_LDE_CONTROL_BUSY_MASK 0x80000000 3560 #define DDR34_E0_PHY_CONTROL_REGS_VDL_LDE_CONTROL_BUSY_ALIGN 0 3561 #define DDR34_E0_PHY_CONTROL_REGS_VDL_LDE_CONTROL_BUSY_BITS 1 3562 #define DDR34_E0_PHY_CONTROL_REGS_VDL_LDE_CONTROL_BUSY_SHIFT 31 3563 #define DDR34_E0_PHY_CONTROL_REGS_VDL_LDE_CONTROL_BUSY_DEFAULT 0x00000000 3564 3565 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_LDE_CONTROL :: reserved0 [30:17] */ 3566 #define DDR34_E0_PHY_CONTROL_REGS_VDL_LDE_CONTROL_RESERVED0_MASK 0x7ffe0000 3567 #define DDR34_E0_PHY_CONTROL_REGS_VDL_LDE_CONTROL_RESERVED0_ALIGN 0 3568 #define DDR34_E0_PHY_CONTROL_REGS_VDL_LDE_CONTROL_RESERVED0_BITS 14 3569 #define DDR34_E0_PHY_CONTROL_REGS_VDL_LDE_CONTROL_RESERVED0_SHIFT 17 3570 3571 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_LDE_CONTROL :: FORCE [16:16] */ 3572 #define DDR34_E0_PHY_CONTROL_REGS_VDL_LDE_CONTROL_FORCE_MASK 0x00010000 3573 #define DDR34_E0_PHY_CONTROL_REGS_VDL_LDE_CONTROL_FORCE_ALIGN 0 3574 #define DDR34_E0_PHY_CONTROL_REGS_VDL_LDE_CONTROL_FORCE_BITS 1 3575 #define DDR34_E0_PHY_CONTROL_REGS_VDL_LDE_CONTROL_FORCE_SHIFT 16 3576 #define DDR34_E0_PHY_CONTROL_REGS_VDL_LDE_CONTROL_FORCE_DEFAULT 0x00000000 3577 3578 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_LDE_CONTROL :: reserved1 [15:13] */ 3579 #define DDR34_E0_PHY_CONTROL_REGS_VDL_LDE_CONTROL_RESERVED1_MASK 0x0000e000 3580 #define DDR34_E0_PHY_CONTROL_REGS_VDL_LDE_CONTROL_RESERVED1_ALIGN 0 3581 #define DDR34_E0_PHY_CONTROL_REGS_VDL_LDE_CONTROL_RESERVED1_BITS 3 3582 #define DDR34_E0_PHY_CONTROL_REGS_VDL_LDE_CONTROL_RESERVED1_SHIFT 13 3583 3584 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_LDE_CONTROL :: ADJ_EN [12:12] */ 3585 #define DDR34_E0_PHY_CONTROL_REGS_VDL_LDE_CONTROL_ADJ_EN_MASK 0x00001000 3586 #define DDR34_E0_PHY_CONTROL_REGS_VDL_LDE_CONTROL_ADJ_EN_ALIGN 0 3587 #define DDR34_E0_PHY_CONTROL_REGS_VDL_LDE_CONTROL_ADJ_EN_BITS 1 3588 #define DDR34_E0_PHY_CONTROL_REGS_VDL_LDE_CONTROL_ADJ_EN_SHIFT 12 3589 #define DDR34_E0_PHY_CONTROL_REGS_VDL_LDE_CONTROL_ADJ_EN_DEFAULT 0x00000000 3590 3591 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_LDE_CONTROL :: reserved2 [11:09] */ 3592 #define DDR34_E0_PHY_CONTROL_REGS_VDL_LDE_CONTROL_RESERVED2_MASK 0x00000e00 3593 #define DDR34_E0_PHY_CONTROL_REGS_VDL_LDE_CONTROL_RESERVED2_ALIGN 0 3594 #define DDR34_E0_PHY_CONTROL_REGS_VDL_LDE_CONTROL_RESERVED2_BITS 3 3595 #define DDR34_E0_PHY_CONTROL_REGS_VDL_LDE_CONTROL_RESERVED2_SHIFT 9 3596 3597 /* DDR34_E0_PHY_CONTROL_REGS :: VDL_LDE_CONTROL :: VDL_STEP [08:00] */ 3598 #define DDR34_E0_PHY_CONTROL_REGS_VDL_LDE_CONTROL_VDL_STEP_MASK 0x000001ff 3599 #define DDR34_E0_PHY_CONTROL_REGS_VDL_LDE_CONTROL_VDL_STEP_ALIGN 0 3600 #define DDR34_E0_PHY_CONTROL_REGS_VDL_LDE_CONTROL_VDL_STEP_BITS 9 3601 #define DDR34_E0_PHY_CONTROL_REGS_VDL_LDE_CONTROL_VDL_STEP_SHIFT 0 3602 #define DDR34_E0_PHY_CONTROL_REGS_VDL_LDE_CONTROL_VDL_STEP_DEFAULT 0x00000000 3603 3604 /*************************************************************************** 3605 *REFRESH - Refresh engine controller 3606 */ 3607 /* DDR34_E0_PHY_CONTROL_REGS :: REFRESH :: reserved0 [31:17] */ 3608 #define DDR34_E0_PHY_CONTROL_REGS_REFRESH_RESERVED0_MASK 0xfffe0000 3609 #define DDR34_E0_PHY_CONTROL_REGS_REFRESH_RESERVED0_ALIGN 0 3610 #define DDR34_E0_PHY_CONTROL_REGS_REFRESH_RESERVED0_BITS 15 3611 #define DDR34_E0_PHY_CONTROL_REGS_REFRESH_RESERVED0_SHIFT 17 3612 3613 /* DDR34_E0_PHY_CONTROL_REGS :: REFRESH :: ENABLE [16:16] */ 3614 #define DDR34_E0_PHY_CONTROL_REGS_REFRESH_ENABLE_MASK 0x00010000 3615 #define DDR34_E0_PHY_CONTROL_REGS_REFRESH_ENABLE_ALIGN 0 3616 #define DDR34_E0_PHY_CONTROL_REGS_REFRESH_ENABLE_BITS 1 3617 #define DDR34_E0_PHY_CONTROL_REGS_REFRESH_ENABLE_SHIFT 16 3618 #define DDR34_E0_PHY_CONTROL_REGS_REFRESH_ENABLE_DEFAULT 0x00000000 3619 3620 /* DDR34_E0_PHY_CONTROL_REGS :: REFRESH :: PERIOD [15:00] */ 3621 #define DDR34_E0_PHY_CONTROL_REGS_REFRESH_PERIOD_MASK 0x0000ffff 3622 #define DDR34_E0_PHY_CONTROL_REGS_REFRESH_PERIOD_ALIGN 0 3623 #define DDR34_E0_PHY_CONTROL_REGS_REFRESH_PERIOD_BITS 16 3624 #define DDR34_E0_PHY_CONTROL_REGS_REFRESH_PERIOD_SHIFT 0 3625 #define DDR34_E0_PHY_CONTROL_REGS_REFRESH_PERIOD_DEFAULT 0x00000000 3626 3627 /*************************************************************************** 3628 *UPDATE_VDL - Update VDL control register 3629 */ 3630 /* DDR34_E0_PHY_CONTROL_REGS :: UPDATE_VDL :: reserved0 [31:06] */ 3631 #define DDR34_E0_PHY_CONTROL_REGS_UPDATE_VDL_RESERVED0_MASK 0xffffffc0 3632 #define DDR34_E0_PHY_CONTROL_REGS_UPDATE_VDL_RESERVED0_ALIGN 0 3633 #define DDR34_E0_PHY_CONTROL_REGS_UPDATE_VDL_RESERVED0_BITS 26 3634 #define DDR34_E0_PHY_CONTROL_REGS_UPDATE_VDL_RESERVED0_SHIFT 6 3635 3636 /* DDR34_E0_PHY_CONTROL_REGS :: UPDATE_VDL :: MODE [05:04] */ 3637 #define DDR34_E0_PHY_CONTROL_REGS_UPDATE_VDL_MODE_MASK 0x00000030 3638 #define DDR34_E0_PHY_CONTROL_REGS_UPDATE_VDL_MODE_ALIGN 0 3639 #define DDR34_E0_PHY_CONTROL_REGS_UPDATE_VDL_MODE_BITS 2 3640 #define DDR34_E0_PHY_CONTROL_REGS_UPDATE_VDL_MODE_SHIFT 4 3641 #define DDR34_E0_PHY_CONTROL_REGS_UPDATE_VDL_MODE_DEFAULT 0x00000000 3642 3643 /* DDR34_E0_PHY_CONTROL_REGS :: UPDATE_VDL :: reserved1 [03:02] */ 3644 #define DDR34_E0_PHY_CONTROL_REGS_UPDATE_VDL_RESERVED1_MASK 0x0000000c 3645 #define DDR34_E0_PHY_CONTROL_REGS_UPDATE_VDL_RESERVED1_ALIGN 0 3646 #define DDR34_E0_PHY_CONTROL_REGS_UPDATE_VDL_RESERVED1_BITS 2 3647 #define DDR34_E0_PHY_CONTROL_REGS_UPDATE_VDL_RESERVED1_SHIFT 2 3648 3649 /* DDR34_E0_PHY_CONTROL_REGS :: UPDATE_VDL :: DISABLE_INPUT [01:01] */ 3650 #define DDR34_E0_PHY_CONTROL_REGS_UPDATE_VDL_DISABLE_INPUT_MASK 0x00000002 3651 #define DDR34_E0_PHY_CONTROL_REGS_UPDATE_VDL_DISABLE_INPUT_ALIGN 0 3652 #define DDR34_E0_PHY_CONTROL_REGS_UPDATE_VDL_DISABLE_INPUT_BITS 1 3653 #define DDR34_E0_PHY_CONTROL_REGS_UPDATE_VDL_DISABLE_INPUT_SHIFT 1 3654 #define DDR34_E0_PHY_CONTROL_REGS_UPDATE_VDL_DISABLE_INPUT_DEFAULT 0x00000000 3655 3656 /* DDR34_E0_PHY_CONTROL_REGS :: UPDATE_VDL :: ENABLE [00:00] */ 3657 #define DDR34_E0_PHY_CONTROL_REGS_UPDATE_VDL_ENABLE_MASK 0x00000001 3658 #define DDR34_E0_PHY_CONTROL_REGS_UPDATE_VDL_ENABLE_ALIGN 0 3659 #define DDR34_E0_PHY_CONTROL_REGS_UPDATE_VDL_ENABLE_BITS 1 3660 #define DDR34_E0_PHY_CONTROL_REGS_UPDATE_VDL_ENABLE_SHIFT 0 3661 #define DDR34_E0_PHY_CONTROL_REGS_UPDATE_VDL_ENABLE_DEFAULT 0x00000000 3662 3663 /*************************************************************************** 3664 *UPDATE_VDL_SNOOP1 - Update VDL snoop control register #1 3665 */ 3666 /* DDR34_E0_PHY_CONTROL_REGS :: UPDATE_VDL_SNOOP1 :: reserved0 [31:30] */ 3667 #define DDR34_E0_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1_RESERVED0_MASK 0xc0000000 3668 #define DDR34_E0_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1_RESERVED0_ALIGN 0 3669 #define DDR34_E0_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1_RESERVED0_BITS 2 3670 #define DDR34_E0_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1_RESERVED0_SHIFT 30 3671 3672 /* DDR34_E0_PHY_CONTROL_REGS :: UPDATE_VDL_SNOOP1 :: MODE [29:28] */ 3673 #define DDR34_E0_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1_MODE_MASK 0x30000000 3674 #define DDR34_E0_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1_MODE_ALIGN 0 3675 #define DDR34_E0_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1_MODE_BITS 2 3676 #define DDR34_E0_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1_MODE_SHIFT 28 3677 #define DDR34_E0_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1_MODE_DEFAULT 0x00000000 3678 3679 /* DDR34_E0_PHY_CONTROL_REGS :: UPDATE_VDL_SNOOP1 :: reserved1 [27:27] */ 3680 #define DDR34_E0_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1_RESERVED1_MASK 0x08000000 3681 #define DDR34_E0_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1_RESERVED1_ALIGN 0 3682 #define DDR34_E0_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1_RESERVED1_BITS 1 3683 #define DDR34_E0_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1_RESERVED1_SHIFT 27 3684 3685 /* DDR34_E0_PHY_CONTROL_REGS :: UPDATE_VDL_SNOOP1 :: MASK [26:16] */ 3686 #define DDR34_E0_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1_MASK_MASK 0x07ff0000 3687 #define DDR34_E0_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1_MASK_ALIGN 0 3688 #define DDR34_E0_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1_MASK_BITS 11 3689 #define DDR34_E0_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1_MASK_SHIFT 16 3690 #define DDR34_E0_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1_MASK_DEFAULT 0x00000000 3691 3692 /* DDR34_E0_PHY_CONTROL_REGS :: UPDATE_VDL_SNOOP1 :: reserved2 [15:15] */ 3693 #define DDR34_E0_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1_RESERVED2_MASK 0x00008000 3694 #define DDR34_E0_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1_RESERVED2_ALIGN 0 3695 #define DDR34_E0_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1_RESERVED2_BITS 1 3696 #define DDR34_E0_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1_RESERVED2_SHIFT 15 3697 3698 /* DDR34_E0_PHY_CONTROL_REGS :: UPDATE_VDL_SNOOP1 :: CMD [14:04] */ 3699 #define DDR34_E0_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1_CMD_MASK 0x00007ff0 3700 #define DDR34_E0_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1_CMD_ALIGN 0 3701 #define DDR34_E0_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1_CMD_BITS 11 3702 #define DDR34_E0_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1_CMD_SHIFT 4 3703 #define DDR34_E0_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1_CMD_DEFAULT 0x00000000 3704 3705 /* DDR34_E0_PHY_CONTROL_REGS :: UPDATE_VDL_SNOOP1 :: reserved3 [03:01] */ 3706 #define DDR34_E0_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1_RESERVED3_MASK 0x0000000e 3707 #define DDR34_E0_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1_RESERVED3_ALIGN 0 3708 #define DDR34_E0_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1_RESERVED3_BITS 3 3709 #define DDR34_E0_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1_RESERVED3_SHIFT 1 3710 3711 /* DDR34_E0_PHY_CONTROL_REGS :: UPDATE_VDL_SNOOP1 :: ENABLE [00:00] */ 3712 #define DDR34_E0_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1_ENABLE_MASK 0x00000001 3713 #define DDR34_E0_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1_ENABLE_ALIGN 0 3714 #define DDR34_E0_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1_ENABLE_BITS 1 3715 #define DDR34_E0_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1_ENABLE_SHIFT 0 3716 #define DDR34_E0_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1_ENABLE_DEFAULT 0x00000000 3717 3718 /*************************************************************************** 3719 *UPDATE_VDL_SNOOP2 - Update VDL snoop control register #2 3720 */ 3721 /* DDR34_E0_PHY_CONTROL_REGS :: UPDATE_VDL_SNOOP2 :: reserved0 [31:30] */ 3722 #define DDR34_E0_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2_RESERVED0_MASK 0xc0000000 3723 #define DDR34_E0_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2_RESERVED0_ALIGN 0 3724 #define DDR34_E0_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2_RESERVED0_BITS 2 3725 #define DDR34_E0_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2_RESERVED0_SHIFT 30 3726 3727 /* DDR34_E0_PHY_CONTROL_REGS :: UPDATE_VDL_SNOOP2 :: MODE [29:28] */ 3728 #define DDR34_E0_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2_MODE_MASK 0x30000000 3729 #define DDR34_E0_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2_MODE_ALIGN 0 3730 #define DDR34_E0_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2_MODE_BITS 2 3731 #define DDR34_E0_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2_MODE_SHIFT 28 3732 #define DDR34_E0_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2_MODE_DEFAULT 0x00000000 3733 3734 /* DDR34_E0_PHY_CONTROL_REGS :: UPDATE_VDL_SNOOP2 :: reserved1 [27:27] */ 3735 #define DDR34_E0_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2_RESERVED1_MASK 0x08000000 3736 #define DDR34_E0_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2_RESERVED1_ALIGN 0 3737 #define DDR34_E0_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2_RESERVED1_BITS 1 3738 #define DDR34_E0_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2_RESERVED1_SHIFT 27 3739 3740 /* DDR34_E0_PHY_CONTROL_REGS :: UPDATE_VDL_SNOOP2 :: MASK [26:16] */ 3741 #define DDR34_E0_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2_MASK_MASK 0x07ff0000 3742 #define DDR34_E0_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2_MASK_ALIGN 0 3743 #define DDR34_E0_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2_MASK_BITS 11 3744 #define DDR34_E0_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2_MASK_SHIFT 16 3745 #define DDR34_E0_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2_MASK_DEFAULT 0x00000000 3746 3747 /* DDR34_E0_PHY_CONTROL_REGS :: UPDATE_VDL_SNOOP2 :: reserved2 [15:15] */ 3748 #define DDR34_E0_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2_RESERVED2_MASK 0x00008000 3749 #define DDR34_E0_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2_RESERVED2_ALIGN 0 3750 #define DDR34_E0_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2_RESERVED2_BITS 1 3751 #define DDR34_E0_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2_RESERVED2_SHIFT 15 3752 3753 /* DDR34_E0_PHY_CONTROL_REGS :: UPDATE_VDL_SNOOP2 :: CMD [14:04] */ 3754 #define DDR34_E0_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2_CMD_MASK 0x00007ff0 3755 #define DDR34_E0_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2_CMD_ALIGN 0 3756 #define DDR34_E0_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2_CMD_BITS 11 3757 #define DDR34_E0_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2_CMD_SHIFT 4 3758 #define DDR34_E0_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2_CMD_DEFAULT 0x00000000 3759 3760 /* DDR34_E0_PHY_CONTROL_REGS :: UPDATE_VDL_SNOOP2 :: reserved3 [03:01] */ 3761 #define DDR34_E0_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2_RESERVED3_MASK 0x0000000e 3762 #define DDR34_E0_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2_RESERVED3_ALIGN 0 3763 #define DDR34_E0_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2_RESERVED3_BITS 3 3764 #define DDR34_E0_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2_RESERVED3_SHIFT 1 3765 3766 /* DDR34_E0_PHY_CONTROL_REGS :: UPDATE_VDL_SNOOP2 :: ENABLE [00:00] */ 3767 #define DDR34_E0_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2_ENABLE_MASK 0x00000001 3768 #define DDR34_E0_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2_ENABLE_ALIGN 0 3769 #define DDR34_E0_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2_ENABLE_BITS 1 3770 #define DDR34_E0_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2_ENABLE_SHIFT 0 3771 #define DDR34_E0_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2_ENABLE_DEFAULT 0x00000000 3772 3773 /*************************************************************************** 3774 *COMMAND_REG1 - DRAM Command Register #1 3775 */ 3776 /* DDR34_E0_PHY_CONTROL_REGS :: COMMAND_REG1 :: MCP [31:31] */ 3777 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG1_MCP_MASK 0x80000000 3778 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG1_MCP_ALIGN 0 3779 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG1_MCP_BITS 1 3780 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG1_MCP_SHIFT 31 3781 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG1_MCP_DEFAULT 0x00000000 3782 3783 /* DDR34_E0_PHY_CONTROL_REGS :: COMMAND_REG1 :: CS [30:29] */ 3784 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG1_CS_MASK 0x60000000 3785 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG1_CS_ALIGN 0 3786 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG1_CS_BITS 2 3787 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG1_CS_SHIFT 29 3788 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG1_CS_DEFAULT 0x00000000 3789 3790 /* DDR34_E0_PHY_CONTROL_REGS :: COMMAND_REG1 :: AUX [28:24] */ 3791 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG1_AUX_MASK 0x1f000000 3792 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG1_AUX_ALIGN 0 3793 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG1_AUX_BITS 5 3794 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG1_AUX_SHIFT 24 3795 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG1_AUX_DEFAULT 0x00000000 3796 3797 /* DDR34_E0_PHY_CONTROL_REGS :: COMMAND_REG1 :: ACT [23:23] */ 3798 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG1_ACT_MASK 0x00800000 3799 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG1_ACT_ALIGN 0 3800 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG1_ACT_BITS 1 3801 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG1_ACT_SHIFT 23 3802 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG1_ACT_DEFAULT 0x00000000 3803 3804 /* DDR34_E0_PHY_CONTROL_REGS :: COMMAND_REG1 :: WE [22:22] */ 3805 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG1_WE_MASK 0x00400000 3806 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG1_WE_ALIGN 0 3807 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG1_WE_BITS 1 3808 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG1_WE_SHIFT 22 3809 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG1_WE_DEFAULT 0x00000000 3810 3811 /* DDR34_E0_PHY_CONTROL_REGS :: COMMAND_REG1 :: CAS [21:21] */ 3812 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG1_CAS_MASK 0x00200000 3813 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG1_CAS_ALIGN 0 3814 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG1_CAS_BITS 1 3815 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG1_CAS_SHIFT 21 3816 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG1_CAS_DEFAULT 0x00000000 3817 3818 /* DDR34_E0_PHY_CONTROL_REGS :: COMMAND_REG1 :: RAS [20:20] */ 3819 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG1_RAS_MASK 0x00100000 3820 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG1_RAS_ALIGN 0 3821 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG1_RAS_BITS 1 3822 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG1_RAS_SHIFT 20 3823 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG1_RAS_DEFAULT 0x00000000 3824 3825 /* DDR34_E0_PHY_CONTROL_REGS :: COMMAND_REG1 :: BA [19:16] */ 3826 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG1_BA_MASK 0x000f0000 3827 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG1_BA_ALIGN 0 3828 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG1_BA_BITS 4 3829 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG1_BA_SHIFT 16 3830 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG1_BA_DEFAULT 0x00000000 3831 3832 /* DDR34_E0_PHY_CONTROL_REGS :: COMMAND_REG1 :: AD [15:00] */ 3833 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG1_AD_MASK 0x0000ffff 3834 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG1_AD_ALIGN 0 3835 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG1_AD_BITS 16 3836 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG1_AD_SHIFT 0 3837 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG1_AD_DEFAULT 0x00000000 3838 3839 /*************************************************************************** 3840 *COMMAND_AUX_REG1 - DRAM AUX_N Command Register #1 3841 */ 3842 /* DDR34_E0_PHY_CONTROL_REGS :: COMMAND_AUX_REG1 :: reserved0 [31:05] */ 3843 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_AUX_REG1_RESERVED0_MASK 0xffffffe0 3844 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_AUX_REG1_RESERVED0_ALIGN 0 3845 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_AUX_REG1_RESERVED0_BITS 27 3846 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_AUX_REG1_RESERVED0_SHIFT 5 3847 3848 /* DDR34_E0_PHY_CONTROL_REGS :: COMMAND_AUX_REG1 :: AUX [04:00] */ 3849 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_AUX_REG1_AUX_MASK 0x0000001f 3850 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_AUX_REG1_AUX_ALIGN 0 3851 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_AUX_REG1_AUX_BITS 5 3852 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_AUX_REG1_AUX_SHIFT 0 3853 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_AUX_REG1_AUX_DEFAULT 0x00000000 3854 3855 /*************************************************************************** 3856 *COMMAND_REG2 - DRAM Command Register #2 3857 */ 3858 /* DDR34_E0_PHY_CONTROL_REGS :: COMMAND_REG2 :: MCP [31:31] */ 3859 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG2_MCP_MASK 0x80000000 3860 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG2_MCP_ALIGN 0 3861 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG2_MCP_BITS 1 3862 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG2_MCP_SHIFT 31 3863 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG2_MCP_DEFAULT 0x00000000 3864 3865 /* DDR34_E0_PHY_CONTROL_REGS :: COMMAND_REG2 :: CS [30:29] */ 3866 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG2_CS_MASK 0x60000000 3867 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG2_CS_ALIGN 0 3868 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG2_CS_BITS 2 3869 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG2_CS_SHIFT 29 3870 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG2_CS_DEFAULT 0x00000000 3871 3872 /* DDR34_E0_PHY_CONTROL_REGS :: COMMAND_REG2 :: AUX [28:24] */ 3873 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG2_AUX_MASK 0x1f000000 3874 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG2_AUX_ALIGN 0 3875 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG2_AUX_BITS 5 3876 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG2_AUX_SHIFT 24 3877 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG2_AUX_DEFAULT 0x00000000 3878 3879 /* DDR34_E0_PHY_CONTROL_REGS :: COMMAND_REG2 :: ACT [23:23] */ 3880 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG2_ACT_MASK 0x00800000 3881 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG2_ACT_ALIGN 0 3882 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG2_ACT_BITS 1 3883 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG2_ACT_SHIFT 23 3884 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG2_ACT_DEFAULT 0x00000000 3885 3886 /* DDR34_E0_PHY_CONTROL_REGS :: COMMAND_REG2 :: WE [22:22] */ 3887 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG2_WE_MASK 0x00400000 3888 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG2_WE_ALIGN 0 3889 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG2_WE_BITS 1 3890 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG2_WE_SHIFT 22 3891 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG2_WE_DEFAULT 0x00000000 3892 3893 /* DDR34_E0_PHY_CONTROL_REGS :: COMMAND_REG2 :: CAS [21:21] */ 3894 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG2_CAS_MASK 0x00200000 3895 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG2_CAS_ALIGN 0 3896 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG2_CAS_BITS 1 3897 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG2_CAS_SHIFT 21 3898 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG2_CAS_DEFAULT 0x00000000 3899 3900 /* DDR34_E0_PHY_CONTROL_REGS :: COMMAND_REG2 :: RAS [20:20] */ 3901 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG2_RAS_MASK 0x00100000 3902 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG2_RAS_ALIGN 0 3903 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG2_RAS_BITS 1 3904 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG2_RAS_SHIFT 20 3905 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG2_RAS_DEFAULT 0x00000000 3906 3907 /* DDR34_E0_PHY_CONTROL_REGS :: COMMAND_REG2 :: BA [19:16] */ 3908 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG2_BA_MASK 0x000f0000 3909 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG2_BA_ALIGN 0 3910 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG2_BA_BITS 4 3911 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG2_BA_SHIFT 16 3912 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG2_BA_DEFAULT 0x00000000 3913 3914 /* DDR34_E0_PHY_CONTROL_REGS :: COMMAND_REG2 :: AD [15:00] */ 3915 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG2_AD_MASK 0x0000ffff 3916 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG2_AD_ALIGN 0 3917 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG2_AD_BITS 16 3918 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG2_AD_SHIFT 0 3919 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG2_AD_DEFAULT 0x00000000 3920 3921 /*************************************************************************** 3922 *COMMAND_AUX_REG2 - DRAM AUX_N Command Register #2 3923 */ 3924 /* DDR34_E0_PHY_CONTROL_REGS :: COMMAND_AUX_REG2 :: reserved0 [31:05] */ 3925 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_AUX_REG2_RESERVED0_MASK 0xffffffe0 3926 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_AUX_REG2_RESERVED0_ALIGN 0 3927 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_AUX_REG2_RESERVED0_BITS 27 3928 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_AUX_REG2_RESERVED0_SHIFT 5 3929 3930 /* DDR34_E0_PHY_CONTROL_REGS :: COMMAND_AUX_REG2 :: AUX [04:00] */ 3931 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_AUX_REG2_AUX_MASK 0x0000001f 3932 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_AUX_REG2_AUX_ALIGN 0 3933 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_AUX_REG2_AUX_BITS 5 3934 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_AUX_REG2_AUX_SHIFT 0 3935 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_AUX_REG2_AUX_DEFAULT 0x00000000 3936 3937 /*************************************************************************** 3938 *COMMAND_REG3 - DRAM Command Register #3 3939 */ 3940 /* DDR34_E0_PHY_CONTROL_REGS :: COMMAND_REG3 :: MCP [31:31] */ 3941 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG3_MCP_MASK 0x80000000 3942 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG3_MCP_ALIGN 0 3943 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG3_MCP_BITS 1 3944 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG3_MCP_SHIFT 31 3945 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG3_MCP_DEFAULT 0x00000000 3946 3947 /* DDR34_E0_PHY_CONTROL_REGS :: COMMAND_REG3 :: CS [30:29] */ 3948 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG3_CS_MASK 0x60000000 3949 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG3_CS_ALIGN 0 3950 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG3_CS_BITS 2 3951 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG3_CS_SHIFT 29 3952 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG3_CS_DEFAULT 0x00000000 3953 3954 /* DDR34_E0_PHY_CONTROL_REGS :: COMMAND_REG3 :: AUX [28:24] */ 3955 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG3_AUX_MASK 0x1f000000 3956 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG3_AUX_ALIGN 0 3957 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG3_AUX_BITS 5 3958 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG3_AUX_SHIFT 24 3959 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG3_AUX_DEFAULT 0x00000000 3960 3961 /* DDR34_E0_PHY_CONTROL_REGS :: COMMAND_REG3 :: ACT [23:23] */ 3962 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG3_ACT_MASK 0x00800000 3963 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG3_ACT_ALIGN 0 3964 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG3_ACT_BITS 1 3965 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG3_ACT_SHIFT 23 3966 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG3_ACT_DEFAULT 0x00000000 3967 3968 /* DDR34_E0_PHY_CONTROL_REGS :: COMMAND_REG3 :: WE [22:22] */ 3969 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG3_WE_MASK 0x00400000 3970 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG3_WE_ALIGN 0 3971 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG3_WE_BITS 1 3972 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG3_WE_SHIFT 22 3973 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG3_WE_DEFAULT 0x00000000 3974 3975 /* DDR34_E0_PHY_CONTROL_REGS :: COMMAND_REG3 :: CAS [21:21] */ 3976 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG3_CAS_MASK 0x00200000 3977 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG3_CAS_ALIGN 0 3978 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG3_CAS_BITS 1 3979 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG3_CAS_SHIFT 21 3980 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG3_CAS_DEFAULT 0x00000000 3981 3982 /* DDR34_E0_PHY_CONTROL_REGS :: COMMAND_REG3 :: RAS [20:20] */ 3983 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG3_RAS_MASK 0x00100000 3984 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG3_RAS_ALIGN 0 3985 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG3_RAS_BITS 1 3986 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG3_RAS_SHIFT 20 3987 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG3_RAS_DEFAULT 0x00000000 3988 3989 /* DDR34_E0_PHY_CONTROL_REGS :: COMMAND_REG3 :: BA [19:16] */ 3990 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG3_BA_MASK 0x000f0000 3991 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG3_BA_ALIGN 0 3992 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG3_BA_BITS 4 3993 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG3_BA_SHIFT 16 3994 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG3_BA_DEFAULT 0x00000000 3995 3996 /* DDR34_E0_PHY_CONTROL_REGS :: COMMAND_REG3 :: AD [15:00] */ 3997 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG3_AD_MASK 0x0000ffff 3998 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG3_AD_ALIGN 0 3999 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG3_AD_BITS 16 4000 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG3_AD_SHIFT 0 4001 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG3_AD_DEFAULT 0x00000000 4002 4003 /*************************************************************************** 4004 *COMMAND_AUX_REG3 - DRAM AUX_N Command Register #3 4005 */ 4006 /* DDR34_E0_PHY_CONTROL_REGS :: COMMAND_AUX_REG3 :: reserved0 [31:05] */ 4007 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_AUX_REG3_RESERVED0_MASK 0xffffffe0 4008 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_AUX_REG3_RESERVED0_ALIGN 0 4009 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_AUX_REG3_RESERVED0_BITS 27 4010 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_AUX_REG3_RESERVED0_SHIFT 5 4011 4012 /* DDR34_E0_PHY_CONTROL_REGS :: COMMAND_AUX_REG3 :: AUX [04:00] */ 4013 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_AUX_REG3_AUX_MASK 0x0000001f 4014 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_AUX_REG3_AUX_ALIGN 0 4015 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_AUX_REG3_AUX_BITS 5 4016 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_AUX_REG3_AUX_SHIFT 0 4017 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_AUX_REG3_AUX_DEFAULT 0x00000000 4018 4019 /*************************************************************************** 4020 *COMMAND_REG4 - DRAM Command Register #4 4021 */ 4022 /* DDR34_E0_PHY_CONTROL_REGS :: COMMAND_REG4 :: MCP [31:31] */ 4023 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG4_MCP_MASK 0x80000000 4024 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG4_MCP_ALIGN 0 4025 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG4_MCP_BITS 1 4026 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG4_MCP_SHIFT 31 4027 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG4_MCP_DEFAULT 0x00000000 4028 4029 /* DDR34_E0_PHY_CONTROL_REGS :: COMMAND_REG4 :: CS [30:29] */ 4030 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG4_CS_MASK 0x60000000 4031 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG4_CS_ALIGN 0 4032 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG4_CS_BITS 2 4033 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG4_CS_SHIFT 29 4034 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG4_CS_DEFAULT 0x00000000 4035 4036 /* DDR34_E0_PHY_CONTROL_REGS :: COMMAND_REG4 :: AUX [28:24] */ 4037 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG4_AUX_MASK 0x1f000000 4038 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG4_AUX_ALIGN 0 4039 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG4_AUX_BITS 5 4040 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG4_AUX_SHIFT 24 4041 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG4_AUX_DEFAULT 0x00000000 4042 4043 /* DDR34_E0_PHY_CONTROL_REGS :: COMMAND_REG4 :: ACT [23:23] */ 4044 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG4_ACT_MASK 0x00800000 4045 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG4_ACT_ALIGN 0 4046 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG4_ACT_BITS 1 4047 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG4_ACT_SHIFT 23 4048 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG4_ACT_DEFAULT 0x00000000 4049 4050 /* DDR34_E0_PHY_CONTROL_REGS :: COMMAND_REG4 :: WE [22:22] */ 4051 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG4_WE_MASK 0x00400000 4052 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG4_WE_ALIGN 0 4053 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG4_WE_BITS 1 4054 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG4_WE_SHIFT 22 4055 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG4_WE_DEFAULT 0x00000000 4056 4057 /* DDR34_E0_PHY_CONTROL_REGS :: COMMAND_REG4 :: CAS [21:21] */ 4058 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG4_CAS_MASK 0x00200000 4059 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG4_CAS_ALIGN 0 4060 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG4_CAS_BITS 1 4061 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG4_CAS_SHIFT 21 4062 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG4_CAS_DEFAULT 0x00000000 4063 4064 /* DDR34_E0_PHY_CONTROL_REGS :: COMMAND_REG4 :: RAS [20:20] */ 4065 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG4_RAS_MASK 0x00100000 4066 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG4_RAS_ALIGN 0 4067 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG4_RAS_BITS 1 4068 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG4_RAS_SHIFT 20 4069 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG4_RAS_DEFAULT 0x00000000 4070 4071 /* DDR34_E0_PHY_CONTROL_REGS :: COMMAND_REG4 :: BA [19:16] */ 4072 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG4_BA_MASK 0x000f0000 4073 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG4_BA_ALIGN 0 4074 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG4_BA_BITS 4 4075 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG4_BA_SHIFT 16 4076 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG4_BA_DEFAULT 0x00000000 4077 4078 /* DDR34_E0_PHY_CONTROL_REGS :: COMMAND_REG4 :: AD [15:00] */ 4079 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG4_AD_MASK 0x0000ffff 4080 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG4_AD_ALIGN 0 4081 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG4_AD_BITS 16 4082 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG4_AD_SHIFT 0 4083 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG4_AD_DEFAULT 0x00000000 4084 4085 /*************************************************************************** 4086 *COMMAND_AUX_REG4 - DRAM AUX_N Command Register #4 4087 */ 4088 /* DDR34_E0_PHY_CONTROL_REGS :: COMMAND_AUX_REG4 :: reserved0 [31:05] */ 4089 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_AUX_REG4_RESERVED0_MASK 0xffffffe0 4090 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_AUX_REG4_RESERVED0_ALIGN 0 4091 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_AUX_REG4_RESERVED0_BITS 27 4092 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_AUX_REG4_RESERVED0_SHIFT 5 4093 4094 /* DDR34_E0_PHY_CONTROL_REGS :: COMMAND_AUX_REG4 :: AUX [04:00] */ 4095 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_AUX_REG4_AUX_MASK 0x0000001f 4096 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_AUX_REG4_AUX_ALIGN 0 4097 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_AUX_REG4_AUX_BITS 5 4098 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_AUX_REG4_AUX_SHIFT 0 4099 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_AUX_REG4_AUX_DEFAULT 0x00000000 4100 4101 /*************************************************************************** 4102 *COMMAND_REG_TIMER - DRAM Command Timer Register 4103 */ 4104 /* DDR34_E0_PHY_CONTROL_REGS :: COMMAND_REG_TIMER :: reserved0 [31:16] */ 4105 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG_TIMER_RESERVED0_MASK 0xffff0000 4106 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG_TIMER_RESERVED0_ALIGN 0 4107 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG_TIMER_RESERVED0_BITS 16 4108 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG_TIMER_RESERVED0_SHIFT 16 4109 4110 /* DDR34_E0_PHY_CONTROL_REGS :: COMMAND_REG_TIMER :: INIT_VAL [15:08] */ 4111 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG_TIMER_INIT_VAL_MASK 0x0000ff00 4112 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG_TIMER_INIT_VAL_ALIGN 0 4113 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG_TIMER_INIT_VAL_BITS 8 4114 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG_TIMER_INIT_VAL_SHIFT 8 4115 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG_TIMER_INIT_VAL_DEFAULT 0x0000000f 4116 4117 /* DDR34_E0_PHY_CONTROL_REGS :: COMMAND_REG_TIMER :: COUNT [07:00] */ 4118 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG_TIMER_COUNT_MASK 0x000000ff 4119 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG_TIMER_COUNT_ALIGN 0 4120 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG_TIMER_COUNT_BITS 8 4121 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG_TIMER_COUNT_SHIFT 0 4122 #define DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG_TIMER_COUNT_DEFAULT 0x00000000 4123 4124 /*************************************************************************** 4125 *MODE_REG0 - DDR3/DDR4/GDDR5 Mode Register 0 and LPDDR Mode Register 1 4126 */ 4127 /* DDR34_E0_PHY_CONTROL_REGS :: MODE_REG0 :: reserved0 [31:17] */ 4128 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG0_RESERVED0_MASK 0xfffe0000 4129 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG0_RESERVED0_ALIGN 0 4130 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG0_RESERVED0_BITS 15 4131 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG0_RESERVED0_SHIFT 17 4132 4133 /* DDR34_E0_PHY_CONTROL_REGS :: MODE_REG0 :: VALID [16:16] */ 4134 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG0_VALID_MASK 0x00010000 4135 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG0_VALID_ALIGN 0 4136 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG0_VALID_BITS 1 4137 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG0_VALID_SHIFT 16 4138 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG0_VALID_DEFAULT 0x00000000 4139 4140 /* DDR34_E0_PHY_CONTROL_REGS :: MODE_REG0 :: AD [15:00] */ 4141 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG0_AD_MASK 0x0000ffff 4142 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG0_AD_ALIGN 0 4143 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG0_AD_BITS 16 4144 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG0_AD_SHIFT 0 4145 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG0_AD_DEFAULT 0x00000000 4146 4147 /*************************************************************************** 4148 *MODE_REG1 - DDR3/DDR4/GDDR5 Mode Register 1 and LPDDR Mode Register 2 4149 */ 4150 /* DDR34_E0_PHY_CONTROL_REGS :: MODE_REG1 :: reserved0 [31:17] */ 4151 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG1_RESERVED0_MASK 0xfffe0000 4152 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG1_RESERVED0_ALIGN 0 4153 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG1_RESERVED0_BITS 15 4154 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG1_RESERVED0_SHIFT 17 4155 4156 /* DDR34_E0_PHY_CONTROL_REGS :: MODE_REG1 :: VALID [16:16] */ 4157 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG1_VALID_MASK 0x00010000 4158 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG1_VALID_ALIGN 0 4159 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG1_VALID_BITS 1 4160 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG1_VALID_SHIFT 16 4161 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG1_VALID_DEFAULT 0x00000000 4162 4163 /* DDR34_E0_PHY_CONTROL_REGS :: MODE_REG1 :: AD [15:00] */ 4164 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG1_AD_MASK 0x0000ffff 4165 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG1_AD_ALIGN 0 4166 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG1_AD_BITS 16 4167 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG1_AD_SHIFT 0 4168 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG1_AD_DEFAULT 0x00000000 4169 4170 /*************************************************************************** 4171 *MODE_REG2 - DDR3/DDR4/GDDR5 Mode Register 2 and LPDDR Mode Register 3 4172 */ 4173 /* DDR34_E0_PHY_CONTROL_REGS :: MODE_REG2 :: reserved0 [31:17] */ 4174 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG2_RESERVED0_MASK 0xfffe0000 4175 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG2_RESERVED0_ALIGN 0 4176 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG2_RESERVED0_BITS 15 4177 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG2_RESERVED0_SHIFT 17 4178 4179 /* DDR34_E0_PHY_CONTROL_REGS :: MODE_REG2 :: VALID [16:16] */ 4180 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG2_VALID_MASK 0x00010000 4181 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG2_VALID_ALIGN 0 4182 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG2_VALID_BITS 1 4183 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG2_VALID_SHIFT 16 4184 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG2_VALID_DEFAULT 0x00000000 4185 4186 /* DDR34_E0_PHY_CONTROL_REGS :: MODE_REG2 :: AD [15:00] */ 4187 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG2_AD_MASK 0x0000ffff 4188 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG2_AD_ALIGN 0 4189 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG2_AD_BITS 16 4190 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG2_AD_SHIFT 0 4191 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG2_AD_DEFAULT 0x00000000 4192 4193 /*************************************************************************** 4194 *MODE_REG3 - DDR3/DDR4/GDDR5 Mode Register 3 and LPDDR Mode Register 9 4195 */ 4196 /* DDR34_E0_PHY_CONTROL_REGS :: MODE_REG3 :: reserved0 [31:17] */ 4197 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG3_RESERVED0_MASK 0xfffe0000 4198 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG3_RESERVED0_ALIGN 0 4199 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG3_RESERVED0_BITS 15 4200 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG3_RESERVED0_SHIFT 17 4201 4202 /* DDR34_E0_PHY_CONTROL_REGS :: MODE_REG3 :: VALID [16:16] */ 4203 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG3_VALID_MASK 0x00010000 4204 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG3_VALID_ALIGN 0 4205 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG3_VALID_BITS 1 4206 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG3_VALID_SHIFT 16 4207 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG3_VALID_DEFAULT 0x00000000 4208 4209 /* DDR34_E0_PHY_CONTROL_REGS :: MODE_REG3 :: AD [15:00] */ 4210 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG3_AD_MASK 0x0000ffff 4211 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG3_AD_ALIGN 0 4212 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG3_AD_BITS 16 4213 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG3_AD_SHIFT 0 4214 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG3_AD_DEFAULT 0x00000000 4215 4216 /*************************************************************************** 4217 *MODE_REG4 - DDR4/GDDR5 Mode Register 4 and LPDDR Mode Register 10 4218 */ 4219 /* DDR34_E0_PHY_CONTROL_REGS :: MODE_REG4 :: reserved0 [31:17] */ 4220 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG4_RESERVED0_MASK 0xfffe0000 4221 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG4_RESERVED0_ALIGN 0 4222 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG4_RESERVED0_BITS 15 4223 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG4_RESERVED0_SHIFT 17 4224 4225 /* DDR34_E0_PHY_CONTROL_REGS :: MODE_REG4 :: VALID [16:16] */ 4226 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG4_VALID_MASK 0x00010000 4227 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG4_VALID_ALIGN 0 4228 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG4_VALID_BITS 1 4229 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG4_VALID_SHIFT 16 4230 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG4_VALID_DEFAULT 0x00000000 4231 4232 /* DDR34_E0_PHY_CONTROL_REGS :: MODE_REG4 :: AD [15:00] */ 4233 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG4_AD_MASK 0x0000ffff 4234 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG4_AD_ALIGN 0 4235 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG4_AD_BITS 16 4236 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG4_AD_SHIFT 0 4237 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG4_AD_DEFAULT 0x00000000 4238 4239 /*************************************************************************** 4240 *MODE_REG5 - DDR4/GDDR5 Mode Register 5 and LPDDR Mode Register 16 4241 */ 4242 /* DDR34_E0_PHY_CONTROL_REGS :: MODE_REG5 :: reserved0 [31:17] */ 4243 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG5_RESERVED0_MASK 0xfffe0000 4244 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG5_RESERVED0_ALIGN 0 4245 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG5_RESERVED0_BITS 15 4246 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG5_RESERVED0_SHIFT 17 4247 4248 /* DDR34_E0_PHY_CONTROL_REGS :: MODE_REG5 :: VALID [16:16] */ 4249 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG5_VALID_MASK 0x00010000 4250 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG5_VALID_ALIGN 0 4251 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG5_VALID_BITS 1 4252 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG5_VALID_SHIFT 16 4253 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG5_VALID_DEFAULT 0x00000000 4254 4255 /* DDR34_E0_PHY_CONTROL_REGS :: MODE_REG5 :: AD [15:00] */ 4256 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG5_AD_MASK 0x0000ffff 4257 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG5_AD_ALIGN 0 4258 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG5_AD_BITS 16 4259 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG5_AD_SHIFT 0 4260 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG5_AD_DEFAULT 0x00000000 4261 4262 /*************************************************************************** 4263 *MODE_REG6 - DDR4/GDDR5 Mode Register 6 and LPDDR Mode Register 17 4264 */ 4265 /* DDR34_E0_PHY_CONTROL_REGS :: MODE_REG6 :: reserved0 [31:17] */ 4266 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG6_RESERVED0_MASK 0xfffe0000 4267 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG6_RESERVED0_ALIGN 0 4268 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG6_RESERVED0_BITS 15 4269 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG6_RESERVED0_SHIFT 17 4270 4271 /* DDR34_E0_PHY_CONTROL_REGS :: MODE_REG6 :: VALID [16:16] */ 4272 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG6_VALID_MASK 0x00010000 4273 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG6_VALID_ALIGN 0 4274 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG6_VALID_BITS 1 4275 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG6_VALID_SHIFT 16 4276 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG6_VALID_DEFAULT 0x00000000 4277 4278 /* DDR34_E0_PHY_CONTROL_REGS :: MODE_REG6 :: AD [15:00] */ 4279 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG6_AD_MASK 0x0000ffff 4280 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG6_AD_ALIGN 0 4281 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG6_AD_BITS 16 4282 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG6_AD_SHIFT 0 4283 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG6_AD_DEFAULT 0x00000000 4284 4285 /*************************************************************************** 4286 *MODE_REG7 - DDR4/GDDR5 Mode Register 7 and LPDDR Mode Register 41 4287 */ 4288 /* DDR34_E0_PHY_CONTROL_REGS :: MODE_REG7 :: reserved0 [31:17] */ 4289 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG7_RESERVED0_MASK 0xfffe0000 4290 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG7_RESERVED0_ALIGN 0 4291 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG7_RESERVED0_BITS 15 4292 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG7_RESERVED0_SHIFT 17 4293 4294 /* DDR34_E0_PHY_CONTROL_REGS :: MODE_REG7 :: VALID [16:16] */ 4295 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG7_VALID_MASK 0x00010000 4296 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG7_VALID_ALIGN 0 4297 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG7_VALID_BITS 1 4298 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG7_VALID_SHIFT 16 4299 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG7_VALID_DEFAULT 0x00000000 4300 4301 /* DDR34_E0_PHY_CONTROL_REGS :: MODE_REG7 :: AD [15:00] */ 4302 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG7_AD_MASK 0x0000ffff 4303 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG7_AD_ALIGN 0 4304 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG7_AD_BITS 16 4305 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG7_AD_SHIFT 0 4306 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG7_AD_DEFAULT 0x00000000 4307 4308 /*************************************************************************** 4309 *MODE_REG8 - GDDR5 Mode Register 8 and LPDDR Mode Register 42 4310 */ 4311 /* DDR34_E0_PHY_CONTROL_REGS :: MODE_REG8 :: reserved0 [31:17] */ 4312 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG8_RESERVED0_MASK 0xfffe0000 4313 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG8_RESERVED0_ALIGN 0 4314 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG8_RESERVED0_BITS 15 4315 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG8_RESERVED0_SHIFT 17 4316 4317 /* DDR34_E0_PHY_CONTROL_REGS :: MODE_REG8 :: VALID [16:16] */ 4318 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG8_VALID_MASK 0x00010000 4319 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG8_VALID_ALIGN 0 4320 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG8_VALID_BITS 1 4321 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG8_VALID_SHIFT 16 4322 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG8_VALID_DEFAULT 0x00000000 4323 4324 /* DDR34_E0_PHY_CONTROL_REGS :: MODE_REG8 :: AD [15:00] */ 4325 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG8_AD_MASK 0x0000ffff 4326 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG8_AD_ALIGN 0 4327 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG8_AD_BITS 16 4328 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG8_AD_SHIFT 0 4329 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG8_AD_DEFAULT 0x00000000 4330 4331 /*************************************************************************** 4332 *MODE_REG15 - GDDR5 Mode Register 15 and LPDDR Mode Register 48 4333 */ 4334 /* DDR34_E0_PHY_CONTROL_REGS :: MODE_REG15 :: reserved0 [31:17] */ 4335 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG15_RESERVED0_MASK 0xfffe0000 4336 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG15_RESERVED0_ALIGN 0 4337 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG15_RESERVED0_BITS 15 4338 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG15_RESERVED0_SHIFT 17 4339 4340 /* DDR34_E0_PHY_CONTROL_REGS :: MODE_REG15 :: VALID [16:16] */ 4341 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG15_VALID_MASK 0x00010000 4342 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG15_VALID_ALIGN 0 4343 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG15_VALID_BITS 1 4344 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG15_VALID_SHIFT 16 4345 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG15_VALID_DEFAULT 0x00000000 4346 4347 /* DDR34_E0_PHY_CONTROL_REGS :: MODE_REG15 :: AD [15:00] */ 4348 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG15_AD_MASK 0x0000ffff 4349 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG15_AD_ALIGN 0 4350 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG15_AD_BITS 16 4351 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG15_AD_SHIFT 0 4352 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG15_AD_DEFAULT 0x00000000 4353 4354 /*************************************************************************** 4355 *MODE_REG63 - LPDDR Mode Register 63 4356 */ 4357 /* DDR34_E0_PHY_CONTROL_REGS :: MODE_REG63 :: reserved0 [31:17] */ 4358 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG63_RESERVED0_MASK 0xfffe0000 4359 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG63_RESERVED0_ALIGN 0 4360 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG63_RESERVED0_BITS 15 4361 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG63_RESERVED0_SHIFT 17 4362 4363 /* DDR34_E0_PHY_CONTROL_REGS :: MODE_REG63 :: VALID [16:16] */ 4364 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG63_VALID_MASK 0x00010000 4365 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG63_VALID_ALIGN 0 4366 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG63_VALID_BITS 1 4367 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG63_VALID_SHIFT 16 4368 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG63_VALID_DEFAULT 0x00000000 4369 4370 /* DDR34_E0_PHY_CONTROL_REGS :: MODE_REG63 :: AD [15:00] */ 4371 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG63_AD_MASK 0x0000ffff 4372 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG63_AD_ALIGN 0 4373 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG63_AD_BITS 16 4374 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG63_AD_SHIFT 0 4375 #define DDR34_E0_PHY_CONTROL_REGS_MODE_REG63_AD_DEFAULT 0x00000000 4376 4377 /*************************************************************************** 4378 *ALERT_CLEAR - DDR4 Alert status clear register 4379 */ 4380 /* DDR34_E0_PHY_CONTROL_REGS :: ALERT_CLEAR :: reserved0 [31:01] */ 4381 #define DDR34_E0_PHY_CONTROL_REGS_ALERT_CLEAR_RESERVED0_MASK 0xfffffffe 4382 #define DDR34_E0_PHY_CONTROL_REGS_ALERT_CLEAR_RESERVED0_ALIGN 0 4383 #define DDR34_E0_PHY_CONTROL_REGS_ALERT_CLEAR_RESERVED0_BITS 31 4384 #define DDR34_E0_PHY_CONTROL_REGS_ALERT_CLEAR_RESERVED0_SHIFT 1 4385 4386 /* DDR34_E0_PHY_CONTROL_REGS :: ALERT_CLEAR :: CLEAR [00:00] */ 4387 #define DDR34_E0_PHY_CONTROL_REGS_ALERT_CLEAR_CLEAR_MASK 0x00000001 4388 #define DDR34_E0_PHY_CONTROL_REGS_ALERT_CLEAR_CLEAR_ALIGN 0 4389 #define DDR34_E0_PHY_CONTROL_REGS_ALERT_CLEAR_CLEAR_BITS 1 4390 #define DDR34_E0_PHY_CONTROL_REGS_ALERT_CLEAR_CLEAR_SHIFT 0 4391 #define DDR34_E0_PHY_CONTROL_REGS_ALERT_CLEAR_CLEAR_DEFAULT 0x00000000 4392 4393 /*************************************************************************** 4394 *ALERT_STATUS - DDR4 Alert status register 4395 */ 4396 /* DDR34_E0_PHY_CONTROL_REGS :: ALERT_STATUS :: reserved0 [31:01] */ 4397 #define DDR34_E0_PHY_CONTROL_REGS_ALERT_STATUS_RESERVED0_MASK 0xfffffffe 4398 #define DDR34_E0_PHY_CONTROL_REGS_ALERT_STATUS_RESERVED0_ALIGN 0 4399 #define DDR34_E0_PHY_CONTROL_REGS_ALERT_STATUS_RESERVED0_BITS 31 4400 #define DDR34_E0_PHY_CONTROL_REGS_ALERT_STATUS_RESERVED0_SHIFT 1 4401 4402 /* DDR34_E0_PHY_CONTROL_REGS :: ALERT_STATUS :: STATUS [00:00] */ 4403 #define DDR34_E0_PHY_CONTROL_REGS_ALERT_STATUS_STATUS_MASK 0x00000001 4404 #define DDR34_E0_PHY_CONTROL_REGS_ALERT_STATUS_STATUS_ALIGN 0 4405 #define DDR34_E0_PHY_CONTROL_REGS_ALERT_STATUS_STATUS_BITS 1 4406 #define DDR34_E0_PHY_CONTROL_REGS_ALERT_STATUS_STATUS_SHIFT 0 4407 #define DDR34_E0_PHY_CONTROL_REGS_ALERT_STATUS_STATUS_DEFAULT 0x00000000 4408 4409 /*************************************************************************** 4410 *CA_PARITY - DDR4 CA parity control register 4411 */ 4412 /* DDR34_E0_PHY_CONTROL_REGS :: CA_PARITY :: reserved0 [31:02] */ 4413 #define DDR34_E0_PHY_CONTROL_REGS_CA_PARITY_RESERVED0_MASK 0xfffffffc 4414 #define DDR34_E0_PHY_CONTROL_REGS_CA_PARITY_RESERVED0_ALIGN 0 4415 #define DDR34_E0_PHY_CONTROL_REGS_CA_PARITY_RESERVED0_BITS 30 4416 #define DDR34_E0_PHY_CONTROL_REGS_CA_PARITY_RESERVED0_SHIFT 2 4417 4418 /* DDR34_E0_PHY_CONTROL_REGS :: CA_PARITY :: ERROR [01:01] */ 4419 #define DDR34_E0_PHY_CONTROL_REGS_CA_PARITY_ERROR_MASK 0x00000002 4420 #define DDR34_E0_PHY_CONTROL_REGS_CA_PARITY_ERROR_ALIGN 0 4421 #define DDR34_E0_PHY_CONTROL_REGS_CA_PARITY_ERROR_BITS 1 4422 #define DDR34_E0_PHY_CONTROL_REGS_CA_PARITY_ERROR_SHIFT 1 4423 #define DDR34_E0_PHY_CONTROL_REGS_CA_PARITY_ERROR_DEFAULT 0x00000000 4424 4425 /* DDR34_E0_PHY_CONTROL_REGS :: CA_PARITY :: ENABLE [00:00] */ 4426 #define DDR34_E0_PHY_CONTROL_REGS_CA_PARITY_ENABLE_MASK 0x00000001 4427 #define DDR34_E0_PHY_CONTROL_REGS_CA_PARITY_ENABLE_ALIGN 0 4428 #define DDR34_E0_PHY_CONTROL_REGS_CA_PARITY_ENABLE_BITS 1 4429 #define DDR34_E0_PHY_CONTROL_REGS_CA_PARITY_ENABLE_SHIFT 0 4430 #define DDR34_E0_PHY_CONTROL_REGS_CA_PARITY_ENABLE_DEFAULT 0x00000000 4431 4432 /*************************************************************************** 4433 *CA_PLAYBACK_CONTROL - GDDR5 CA playback control register 4434 */ 4435 /* DDR34_E0_PHY_CONTROL_REGS :: CA_PLAYBACK_CONTROL :: reserved0 [31:12] */ 4436 #define DDR34_E0_PHY_CONTROL_REGS_CA_PLAYBACK_CONTROL_RESERVED0_MASK 0xfffff000 4437 #define DDR34_E0_PHY_CONTROL_REGS_CA_PLAYBACK_CONTROL_RESERVED0_ALIGN 0 4438 #define DDR34_E0_PHY_CONTROL_REGS_CA_PLAYBACK_CONTROL_RESERVED0_BITS 20 4439 #define DDR34_E0_PHY_CONTROL_REGS_CA_PLAYBACK_CONTROL_RESERVED0_SHIFT 12 4440 4441 /* DDR34_E0_PHY_CONTROL_REGS :: CA_PLAYBACK_CONTROL :: COUNT [11:04] */ 4442 #define DDR34_E0_PHY_CONTROL_REGS_CA_PLAYBACK_CONTROL_COUNT_MASK 0x00000ff0 4443 #define DDR34_E0_PHY_CONTROL_REGS_CA_PLAYBACK_CONTROL_COUNT_ALIGN 0 4444 #define DDR34_E0_PHY_CONTROL_REGS_CA_PLAYBACK_CONTROL_COUNT_BITS 8 4445 #define DDR34_E0_PHY_CONTROL_REGS_CA_PLAYBACK_CONTROL_COUNT_SHIFT 4 4446 #define DDR34_E0_PHY_CONTROL_REGS_CA_PLAYBACK_CONTROL_COUNT_DEFAULT 0x00000000 4447 4448 /* DDR34_E0_PHY_CONTROL_REGS :: CA_PLAYBACK_CONTROL :: reserved1 [03:01] */ 4449 #define DDR34_E0_PHY_CONTROL_REGS_CA_PLAYBACK_CONTROL_RESERVED1_MASK 0x0000000e 4450 #define DDR34_E0_PHY_CONTROL_REGS_CA_PLAYBACK_CONTROL_RESERVED1_ALIGN 0 4451 #define DDR34_E0_PHY_CONTROL_REGS_CA_PLAYBACK_CONTROL_RESERVED1_BITS 3 4452 #define DDR34_E0_PHY_CONTROL_REGS_CA_PLAYBACK_CONTROL_RESERVED1_SHIFT 1 4453 4454 /* DDR34_E0_PHY_CONTROL_REGS :: CA_PLAYBACK_CONTROL :: SAMPLE [00:00] */ 4455 #define DDR34_E0_PHY_CONTROL_REGS_CA_PLAYBACK_CONTROL_SAMPLE_MASK 0x00000001 4456 #define DDR34_E0_PHY_CONTROL_REGS_CA_PLAYBACK_CONTROL_SAMPLE_ALIGN 0 4457 #define DDR34_E0_PHY_CONTROL_REGS_CA_PLAYBACK_CONTROL_SAMPLE_BITS 1 4458 #define DDR34_E0_PHY_CONTROL_REGS_CA_PLAYBACK_CONTROL_SAMPLE_SHIFT 0 4459 #define DDR34_E0_PHY_CONTROL_REGS_CA_PLAYBACK_CONTROL_SAMPLE_DEFAULT 0x00000000 4460 4461 /*************************************************************************** 4462 *CA_PLAYBACK_STATUS0 - LPDDR3 and GDDR5 CA playback status register0 (for BL0 and BL1) 4463 */ 4464 /* DDR34_E0_PHY_CONTROL_REGS :: CA_PLAYBACK_STATUS0 :: VALID [31:31] */ 4465 #define DDR34_E0_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS0_VALID_MASK 0x80000000 4466 #define DDR34_E0_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS0_VALID_ALIGN 0 4467 #define DDR34_E0_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS0_VALID_BITS 1 4468 #define DDR34_E0_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS0_VALID_SHIFT 31 4469 #define DDR34_E0_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS0_VALID_DEFAULT 0x00000000 4470 4471 /* DDR34_E0_PHY_CONTROL_REGS :: CA_PLAYBACK_STATUS0 :: reserved0 [30:26] */ 4472 #define DDR34_E0_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS0_RESERVED0_MASK 0x7c000000 4473 #define DDR34_E0_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS0_RESERVED0_ALIGN 0 4474 #define DDR34_E0_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS0_RESERVED0_BITS 5 4475 #define DDR34_E0_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS0_RESERVED0_SHIFT 26 4476 4477 /* DDR34_E0_PHY_CONTROL_REGS :: CA_PLAYBACK_STATUS0 :: DATA1 [25:16] */ 4478 #define DDR34_E0_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS0_DATA1_MASK 0x03ff0000 4479 #define DDR34_E0_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS0_DATA1_ALIGN 0 4480 #define DDR34_E0_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS0_DATA1_BITS 10 4481 #define DDR34_E0_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS0_DATA1_SHIFT 16 4482 #define DDR34_E0_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS0_DATA1_DEFAULT 0x00000000 4483 4484 /* DDR34_E0_PHY_CONTROL_REGS :: CA_PLAYBACK_STATUS0 :: reserved1 [15:10] */ 4485 #define DDR34_E0_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS0_RESERVED1_MASK 0x0000fc00 4486 #define DDR34_E0_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS0_RESERVED1_ALIGN 0 4487 #define DDR34_E0_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS0_RESERVED1_BITS 6 4488 #define DDR34_E0_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS0_RESERVED1_SHIFT 10 4489 4490 /* DDR34_E0_PHY_CONTROL_REGS :: CA_PLAYBACK_STATUS0 :: DATA0 [09:00] */ 4491 #define DDR34_E0_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS0_DATA0_MASK 0x000003ff 4492 #define DDR34_E0_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS0_DATA0_ALIGN 0 4493 #define DDR34_E0_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS0_DATA0_BITS 10 4494 #define DDR34_E0_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS0_DATA0_SHIFT 0 4495 #define DDR34_E0_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS0_DATA0_DEFAULT 0x00000000 4496 4497 /*************************************************************************** 4498 *CA_PLAYBACK_STATUS1 - LPDDR3 and GDDR5 CA playback status register1 (for BL2 and BL3) 4499 */ 4500 /* DDR34_E0_PHY_CONTROL_REGS :: CA_PLAYBACK_STATUS1 :: VALID [31:31] */ 4501 #define DDR34_E0_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS1_VALID_MASK 0x80000000 4502 #define DDR34_E0_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS1_VALID_ALIGN 0 4503 #define DDR34_E0_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS1_VALID_BITS 1 4504 #define DDR34_E0_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS1_VALID_SHIFT 31 4505 #define DDR34_E0_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS1_VALID_DEFAULT 0x00000000 4506 4507 /* DDR34_E0_PHY_CONTROL_REGS :: CA_PLAYBACK_STATUS1 :: reserved0 [30:26] */ 4508 #define DDR34_E0_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS1_RESERVED0_MASK 0x7c000000 4509 #define DDR34_E0_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS1_RESERVED0_ALIGN 0 4510 #define DDR34_E0_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS1_RESERVED0_BITS 5 4511 #define DDR34_E0_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS1_RESERVED0_SHIFT 26 4512 4513 /* DDR34_E0_PHY_CONTROL_REGS :: CA_PLAYBACK_STATUS1 :: DATA1 [25:16] */ 4514 #define DDR34_E0_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS1_DATA1_MASK 0x03ff0000 4515 #define DDR34_E0_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS1_DATA1_ALIGN 0 4516 #define DDR34_E0_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS1_DATA1_BITS 10 4517 #define DDR34_E0_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS1_DATA1_SHIFT 16 4518 #define DDR34_E0_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS1_DATA1_DEFAULT 0x00000000 4519 4520 /* DDR34_E0_PHY_CONTROL_REGS :: CA_PLAYBACK_STATUS1 :: reserved1 [15:10] */ 4521 #define DDR34_E0_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS1_RESERVED1_MASK 0x0000fc00 4522 #define DDR34_E0_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS1_RESERVED1_ALIGN 0 4523 #define DDR34_E0_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS1_RESERVED1_BITS 6 4524 #define DDR34_E0_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS1_RESERVED1_SHIFT 10 4525 4526 /* DDR34_E0_PHY_CONTROL_REGS :: CA_PLAYBACK_STATUS1 :: DATA0 [09:00] */ 4527 #define DDR34_E0_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS1_DATA0_MASK 0x000003ff 4528 #define DDR34_E0_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS1_DATA0_ALIGN 0 4529 #define DDR34_E0_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS1_DATA0_BITS 10 4530 #define DDR34_E0_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS1_DATA0_SHIFT 0 4531 #define DDR34_E0_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS1_DATA0_DEFAULT 0x00000000 4532 4533 /*************************************************************************** 4534 *WRITE_LEVELING_CONTROL - Write leveling control register 4535 */ 4536 /* DDR34_E0_PHY_CONTROL_REGS :: WRITE_LEVELING_CONTROL :: reserved0 [31:16] */ 4537 #define DDR34_E0_PHY_CONTROL_REGS_WRITE_LEVELING_CONTROL_RESERVED0_MASK 0xffff0000 4538 #define DDR34_E0_PHY_CONTROL_REGS_WRITE_LEVELING_CONTROL_RESERVED0_ALIGN 0 4539 #define DDR34_E0_PHY_CONTROL_REGS_WRITE_LEVELING_CONTROL_RESERVED0_BITS 16 4540 #define DDR34_E0_PHY_CONTROL_REGS_WRITE_LEVELING_CONTROL_RESERVED0_SHIFT 16 4541 4542 /* DDR34_E0_PHY_CONTROL_REGS :: WRITE_LEVELING_CONTROL :: COUNT [15:08] */ 4543 #define DDR34_E0_PHY_CONTROL_REGS_WRITE_LEVELING_CONTROL_COUNT_MASK 0x0000ff00 4544 #define DDR34_E0_PHY_CONTROL_REGS_WRITE_LEVELING_CONTROL_COUNT_ALIGN 0 4545 #define DDR34_E0_PHY_CONTROL_REGS_WRITE_LEVELING_CONTROL_COUNT_BITS 8 4546 #define DDR34_E0_PHY_CONTROL_REGS_WRITE_LEVELING_CONTROL_COUNT_SHIFT 8 4547 #define DDR34_E0_PHY_CONTROL_REGS_WRITE_LEVELING_CONTROL_COUNT_DEFAULT 0x0000000f 4548 4549 /* DDR34_E0_PHY_CONTROL_REGS :: WRITE_LEVELING_CONTROL :: reserved1 [07:03] */ 4550 #define DDR34_E0_PHY_CONTROL_REGS_WRITE_LEVELING_CONTROL_RESERVED1_MASK 0x000000f8 4551 #define DDR34_E0_PHY_CONTROL_REGS_WRITE_LEVELING_CONTROL_RESERVED1_ALIGN 0 4552 #define DDR34_E0_PHY_CONTROL_REGS_WRITE_LEVELING_CONTROL_RESERVED1_BITS 5 4553 #define DDR34_E0_PHY_CONTROL_REGS_WRITE_LEVELING_CONTROL_RESERVED1_SHIFT 3 4554 4555 /* DDR34_E0_PHY_CONTROL_REGS :: WRITE_LEVELING_CONTROL :: SAMPLE [02:02] */ 4556 #define DDR34_E0_PHY_CONTROL_REGS_WRITE_LEVELING_CONTROL_SAMPLE_MASK 0x00000004 4557 #define DDR34_E0_PHY_CONTROL_REGS_WRITE_LEVELING_CONTROL_SAMPLE_ALIGN 0 4558 #define DDR34_E0_PHY_CONTROL_REGS_WRITE_LEVELING_CONTROL_SAMPLE_BITS 1 4559 #define DDR34_E0_PHY_CONTROL_REGS_WRITE_LEVELING_CONTROL_SAMPLE_SHIFT 2 4560 #define DDR34_E0_PHY_CONTROL_REGS_WRITE_LEVELING_CONTROL_SAMPLE_DEFAULT 0x00000000 4561 4562 /* DDR34_E0_PHY_CONTROL_REGS :: WRITE_LEVELING_CONTROL :: CONTINUOUS [01:01] */ 4563 #define DDR34_E0_PHY_CONTROL_REGS_WRITE_LEVELING_CONTROL_CONTINUOUS_MASK 0x00000002 4564 #define DDR34_E0_PHY_CONTROL_REGS_WRITE_LEVELING_CONTROL_CONTINUOUS_ALIGN 0 4565 #define DDR34_E0_PHY_CONTROL_REGS_WRITE_LEVELING_CONTROL_CONTINUOUS_BITS 1 4566 #define DDR34_E0_PHY_CONTROL_REGS_WRITE_LEVELING_CONTROL_CONTINUOUS_SHIFT 1 4567 #define DDR34_E0_PHY_CONTROL_REGS_WRITE_LEVELING_CONTROL_CONTINUOUS_DEFAULT 0x00000000 4568 4569 /* DDR34_E0_PHY_CONTROL_REGS :: WRITE_LEVELING_CONTROL :: ENABLE [00:00] */ 4570 #define DDR34_E0_PHY_CONTROL_REGS_WRITE_LEVELING_CONTROL_ENABLE_MASK 0x00000001 4571 #define DDR34_E0_PHY_CONTROL_REGS_WRITE_LEVELING_CONTROL_ENABLE_ALIGN 0 4572 #define DDR34_E0_PHY_CONTROL_REGS_WRITE_LEVELING_CONTROL_ENABLE_BITS 1 4573 #define DDR34_E0_PHY_CONTROL_REGS_WRITE_LEVELING_CONTROL_ENABLE_SHIFT 0 4574 #define DDR34_E0_PHY_CONTROL_REGS_WRITE_LEVELING_CONTROL_ENABLE_DEFAULT 0x00000000 4575 4576 /*************************************************************************** 4577 *WRITE_LEVELING_STATUS - Write leveling status register 4578 */ 4579 /* DDR34_E0_PHY_CONTROL_REGS :: WRITE_LEVELING_STATUS :: reserved0 [31:14] */ 4580 #define DDR34_E0_PHY_CONTROL_REGS_WRITE_LEVELING_STATUS_RESERVED0_MASK 0xffffc000 4581 #define DDR34_E0_PHY_CONTROL_REGS_WRITE_LEVELING_STATUS_RESERVED0_ALIGN 0 4582 #define DDR34_E0_PHY_CONTROL_REGS_WRITE_LEVELING_STATUS_RESERVED0_BITS 18 4583 #define DDR34_E0_PHY_CONTROL_REGS_WRITE_LEVELING_STATUS_RESERVED0_SHIFT 14 4584 4585 /* DDR34_E0_PHY_CONTROL_REGS :: WRITE_LEVELING_STATUS :: EDC [13:09] */ 4586 #define DDR34_E0_PHY_CONTROL_REGS_WRITE_LEVELING_STATUS_EDC_MASK 0x00003e00 4587 #define DDR34_E0_PHY_CONTROL_REGS_WRITE_LEVELING_STATUS_EDC_ALIGN 0 4588 #define DDR34_E0_PHY_CONTROL_REGS_WRITE_LEVELING_STATUS_EDC_BITS 5 4589 #define DDR34_E0_PHY_CONTROL_REGS_WRITE_LEVELING_STATUS_EDC_SHIFT 9 4590 #define DDR34_E0_PHY_CONTROL_REGS_WRITE_LEVELING_STATUS_EDC_DEFAULT 0x00000000 4591 4592 /* DDR34_E0_PHY_CONTROL_REGS :: WRITE_LEVELING_STATUS :: STATUS [08:04] */ 4593 #define DDR34_E0_PHY_CONTROL_REGS_WRITE_LEVELING_STATUS_STATUS_MASK 0x000001f0 4594 #define DDR34_E0_PHY_CONTROL_REGS_WRITE_LEVELING_STATUS_STATUS_ALIGN 0 4595 #define DDR34_E0_PHY_CONTROL_REGS_WRITE_LEVELING_STATUS_STATUS_BITS 5 4596 #define DDR34_E0_PHY_CONTROL_REGS_WRITE_LEVELING_STATUS_STATUS_SHIFT 4 4597 #define DDR34_E0_PHY_CONTROL_REGS_WRITE_LEVELING_STATUS_STATUS_DEFAULT 0x00000000 4598 4599 /* DDR34_E0_PHY_CONTROL_REGS :: WRITE_LEVELING_STATUS :: reserved1 [03:01] */ 4600 #define DDR34_E0_PHY_CONTROL_REGS_WRITE_LEVELING_STATUS_RESERVED1_MASK 0x0000000e 4601 #define DDR34_E0_PHY_CONTROL_REGS_WRITE_LEVELING_STATUS_RESERVED1_ALIGN 0 4602 #define DDR34_E0_PHY_CONTROL_REGS_WRITE_LEVELING_STATUS_RESERVED1_BITS 3 4603 #define DDR34_E0_PHY_CONTROL_REGS_WRITE_LEVELING_STATUS_RESERVED1_SHIFT 1 4604 4605 /* DDR34_E0_PHY_CONTROL_REGS :: WRITE_LEVELING_STATUS :: VALID [00:00] */ 4606 #define DDR34_E0_PHY_CONTROL_REGS_WRITE_LEVELING_STATUS_VALID_MASK 0x00000001 4607 #define DDR34_E0_PHY_CONTROL_REGS_WRITE_LEVELING_STATUS_VALID_ALIGN 0 4608 #define DDR34_E0_PHY_CONTROL_REGS_WRITE_LEVELING_STATUS_VALID_BITS 1 4609 #define DDR34_E0_PHY_CONTROL_REGS_WRITE_LEVELING_STATUS_VALID_SHIFT 0 4610 #define DDR34_E0_PHY_CONTROL_REGS_WRITE_LEVELING_STATUS_VALID_DEFAULT 0x00000000 4611 4612 /*************************************************************************** 4613 *READ_ENABLE_CONTROL - Read enable test cycle control register 4614 */ 4615 /* DDR34_E0_PHY_CONTROL_REGS :: READ_ENABLE_CONTROL :: reserved0 [31:13] */ 4616 #define DDR34_E0_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_RESERVED0_MASK 0xffffe000 4617 #define DDR34_E0_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_RESERVED0_ALIGN 0 4618 #define DDR34_E0_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_RESERVED0_BITS 19 4619 #define DDR34_E0_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_RESERVED0_SHIFT 13 4620 4621 /* DDR34_E0_PHY_CONTROL_REGS :: READ_ENABLE_CONTROL :: TEST_CYCLE [12:12] */ 4622 #define DDR34_E0_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_TEST_CYCLE_MASK 0x00001000 4623 #define DDR34_E0_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_TEST_CYCLE_ALIGN 0 4624 #define DDR34_E0_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_TEST_CYCLE_BITS 1 4625 #define DDR34_E0_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_TEST_CYCLE_SHIFT 12 4626 #define DDR34_E0_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_TEST_CYCLE_DEFAULT 0x00000000 4627 4628 /* DDR34_E0_PHY_CONTROL_REGS :: READ_ENABLE_CONTROL :: SELECT [11:08] */ 4629 #define DDR34_E0_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_SELECT_MASK 0x00000f00 4630 #define DDR34_E0_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_SELECT_ALIGN 0 4631 #define DDR34_E0_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_SELECT_BITS 4 4632 #define DDR34_E0_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_SELECT_SHIFT 8 4633 #define DDR34_E0_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_SELECT_DEFAULT 0x00000000 4634 4635 /* DDR34_E0_PHY_CONTROL_REGS :: READ_ENABLE_CONTROL :: reserved1 [07:06] */ 4636 #define DDR34_E0_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_RESERVED1_MASK 0x000000c0 4637 #define DDR34_E0_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_RESERVED1_ALIGN 0 4638 #define DDR34_E0_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_RESERVED1_BITS 2 4639 #define DDR34_E0_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_RESERVED1_SHIFT 6 4640 4641 /* DDR34_E0_PHY_CONTROL_REGS :: READ_ENABLE_CONTROL :: CS_N [05:04] */ 4642 #define DDR34_E0_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_CS_N_MASK 0x00000030 4643 #define DDR34_E0_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_CS_N_ALIGN 0 4644 #define DDR34_E0_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_CS_N_BITS 2 4645 #define DDR34_E0_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_CS_N_SHIFT 4 4646 #define DDR34_E0_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_CS_N_DEFAULT 0x00000000 4647 4648 /* DDR34_E0_PHY_CONTROL_REGS :: READ_ENABLE_CONTROL :: EDC_DATA [03:03] */ 4649 #define DDR34_E0_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_EDC_DATA_MASK 0x00000008 4650 #define DDR34_E0_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_EDC_DATA_ALIGN 0 4651 #define DDR34_E0_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_EDC_DATA_BITS 1 4652 #define DDR34_E0_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_EDC_DATA_SHIFT 3 4653 #define DDR34_E0_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_EDC_DATA_DEFAULT 0x00000000 4654 4655 /* DDR34_E0_PHY_CONTROL_REGS :: READ_ENABLE_CONTROL :: EDC_PHASE [02:02] */ 4656 #define DDR34_E0_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_EDC_PHASE_MASK 0x00000004 4657 #define DDR34_E0_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_EDC_PHASE_ALIGN 0 4658 #define DDR34_E0_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_EDC_PHASE_BITS 1 4659 #define DDR34_E0_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_EDC_PHASE_SHIFT 2 4660 #define DDR34_E0_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_EDC_PHASE_DEFAULT 0x00000000 4661 4662 /* DDR34_E0_PHY_CONTROL_REGS :: READ_ENABLE_CONTROL :: DQS [01:01] */ 4663 #define DDR34_E0_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_DQS_MASK 0x00000002 4664 #define DDR34_E0_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_DQS_ALIGN 0 4665 #define DDR34_E0_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_DQS_BITS 1 4666 #define DDR34_E0_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_DQS_SHIFT 1 4667 #define DDR34_E0_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_DQS_DEFAULT 0x00000000 4668 4669 /* DDR34_E0_PHY_CONTROL_REGS :: READ_ENABLE_CONTROL :: ENABLE [00:00] */ 4670 #define DDR34_E0_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_ENABLE_MASK 0x00000001 4671 #define DDR34_E0_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_ENABLE_ALIGN 0 4672 #define DDR34_E0_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_ENABLE_BITS 1 4673 #define DDR34_E0_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_ENABLE_SHIFT 0 4674 #define DDR34_E0_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_ENABLE_DEFAULT 0x00000000 4675 4676 /*************************************************************************** 4677 *READ_ENABLE_STATUS - Read enable test cycle status register 4678 */ 4679 /* DDR34_E0_PHY_CONTROL_REGS :: READ_ENABLE_STATUS :: reserved0 [31:20] */ 4680 #define DDR34_E0_PHY_CONTROL_REGS_READ_ENABLE_STATUS_RESERVED0_MASK 0xfff00000 4681 #define DDR34_E0_PHY_CONTROL_REGS_READ_ENABLE_STATUS_RESERVED0_ALIGN 0 4682 #define DDR34_E0_PHY_CONTROL_REGS_READ_ENABLE_STATUS_RESERVED0_BITS 12 4683 #define DDR34_E0_PHY_CONTROL_REGS_READ_ENABLE_STATUS_RESERVED0_SHIFT 20 4684 4685 /* DDR34_E0_PHY_CONTROL_REGS :: READ_ENABLE_STATUS :: DATA [19:12] */ 4686 #define DDR34_E0_PHY_CONTROL_REGS_READ_ENABLE_STATUS_DATA_MASK 0x000ff000 4687 #define DDR34_E0_PHY_CONTROL_REGS_READ_ENABLE_STATUS_DATA_ALIGN 0 4688 #define DDR34_E0_PHY_CONTROL_REGS_READ_ENABLE_STATUS_DATA_BITS 8 4689 #define DDR34_E0_PHY_CONTROL_REGS_READ_ENABLE_STATUS_DATA_SHIFT 12 4690 #define DDR34_E0_PHY_CONTROL_REGS_READ_ENABLE_STATUS_DATA_DEFAULT 0x00000000 4691 4692 /* DDR34_E0_PHY_CONTROL_REGS :: READ_ENABLE_STATUS :: reserved1 [11:09] */ 4693 #define DDR34_E0_PHY_CONTROL_REGS_READ_ENABLE_STATUS_RESERVED1_MASK 0x00000e00 4694 #define DDR34_E0_PHY_CONTROL_REGS_READ_ENABLE_STATUS_RESERVED1_ALIGN 0 4695 #define DDR34_E0_PHY_CONTROL_REGS_READ_ENABLE_STATUS_RESERVED1_BITS 3 4696 #define DDR34_E0_PHY_CONTROL_REGS_READ_ENABLE_STATUS_RESERVED1_SHIFT 9 4697 4698 /* DDR34_E0_PHY_CONTROL_REGS :: READ_ENABLE_STATUS :: BL4_STATUS [08:08] */ 4699 #define DDR34_E0_PHY_CONTROL_REGS_READ_ENABLE_STATUS_BL4_STATUS_MASK 0x00000100 4700 #define DDR34_E0_PHY_CONTROL_REGS_READ_ENABLE_STATUS_BL4_STATUS_ALIGN 0 4701 #define DDR34_E0_PHY_CONTROL_REGS_READ_ENABLE_STATUS_BL4_STATUS_BITS 1 4702 #define DDR34_E0_PHY_CONTROL_REGS_READ_ENABLE_STATUS_BL4_STATUS_SHIFT 8 4703 #define DDR34_E0_PHY_CONTROL_REGS_READ_ENABLE_STATUS_BL4_STATUS_DEFAULT 0x00000000 4704 4705 /* DDR34_E0_PHY_CONTROL_REGS :: READ_ENABLE_STATUS :: BL3_STATUS [07:07] */ 4706 #define DDR34_E0_PHY_CONTROL_REGS_READ_ENABLE_STATUS_BL3_STATUS_MASK 0x00000080 4707 #define DDR34_E0_PHY_CONTROL_REGS_READ_ENABLE_STATUS_BL3_STATUS_ALIGN 0 4708 #define DDR34_E0_PHY_CONTROL_REGS_READ_ENABLE_STATUS_BL3_STATUS_BITS 1 4709 #define DDR34_E0_PHY_CONTROL_REGS_READ_ENABLE_STATUS_BL3_STATUS_SHIFT 7 4710 #define DDR34_E0_PHY_CONTROL_REGS_READ_ENABLE_STATUS_BL3_STATUS_DEFAULT 0x00000000 4711 4712 /* DDR34_E0_PHY_CONTROL_REGS :: READ_ENABLE_STATUS :: BL2_STATUS [06:06] */ 4713 #define DDR34_E0_PHY_CONTROL_REGS_READ_ENABLE_STATUS_BL2_STATUS_MASK 0x00000040 4714 #define DDR34_E0_PHY_CONTROL_REGS_READ_ENABLE_STATUS_BL2_STATUS_ALIGN 0 4715 #define DDR34_E0_PHY_CONTROL_REGS_READ_ENABLE_STATUS_BL2_STATUS_BITS 1 4716 #define DDR34_E0_PHY_CONTROL_REGS_READ_ENABLE_STATUS_BL2_STATUS_SHIFT 6 4717 #define DDR34_E0_PHY_CONTROL_REGS_READ_ENABLE_STATUS_BL2_STATUS_DEFAULT 0x00000000 4718 4719 /* DDR34_E0_PHY_CONTROL_REGS :: READ_ENABLE_STATUS :: BL1_STATUS [05:05] */ 4720 #define DDR34_E0_PHY_CONTROL_REGS_READ_ENABLE_STATUS_BL1_STATUS_MASK 0x00000020 4721 #define DDR34_E0_PHY_CONTROL_REGS_READ_ENABLE_STATUS_BL1_STATUS_ALIGN 0 4722 #define DDR34_E0_PHY_CONTROL_REGS_READ_ENABLE_STATUS_BL1_STATUS_BITS 1 4723 #define DDR34_E0_PHY_CONTROL_REGS_READ_ENABLE_STATUS_BL1_STATUS_SHIFT 5 4724 #define DDR34_E0_PHY_CONTROL_REGS_READ_ENABLE_STATUS_BL1_STATUS_DEFAULT 0x00000000 4725 4726 /* DDR34_E0_PHY_CONTROL_REGS :: READ_ENABLE_STATUS :: BL0_STATUS [04:04] */ 4727 #define DDR34_E0_PHY_CONTROL_REGS_READ_ENABLE_STATUS_BL0_STATUS_MASK 0x00000010 4728 #define DDR34_E0_PHY_CONTROL_REGS_READ_ENABLE_STATUS_BL0_STATUS_ALIGN 0 4729 #define DDR34_E0_PHY_CONTROL_REGS_READ_ENABLE_STATUS_BL0_STATUS_BITS 1 4730 #define DDR34_E0_PHY_CONTROL_REGS_READ_ENABLE_STATUS_BL0_STATUS_SHIFT 4 4731 #define DDR34_E0_PHY_CONTROL_REGS_READ_ENABLE_STATUS_BL0_STATUS_DEFAULT 0x00000000 4732 4733 /* DDR34_E0_PHY_CONTROL_REGS :: READ_ENABLE_STATUS :: reserved2 [03:01] */ 4734 #define DDR34_E0_PHY_CONTROL_REGS_READ_ENABLE_STATUS_RESERVED2_MASK 0x0000000e 4735 #define DDR34_E0_PHY_CONTROL_REGS_READ_ENABLE_STATUS_RESERVED2_ALIGN 0 4736 #define DDR34_E0_PHY_CONTROL_REGS_READ_ENABLE_STATUS_RESERVED2_BITS 3 4737 #define DDR34_E0_PHY_CONTROL_REGS_READ_ENABLE_STATUS_RESERVED2_SHIFT 1 4738 4739 /* DDR34_E0_PHY_CONTROL_REGS :: READ_ENABLE_STATUS :: VALID [00:00] */ 4740 #define DDR34_E0_PHY_CONTROL_REGS_READ_ENABLE_STATUS_VALID_MASK 0x00000001 4741 #define DDR34_E0_PHY_CONTROL_REGS_READ_ENABLE_STATUS_VALID_ALIGN 0 4742 #define DDR34_E0_PHY_CONTROL_REGS_READ_ENABLE_STATUS_VALID_BITS 1 4743 #define DDR34_E0_PHY_CONTROL_REGS_READ_ENABLE_STATUS_VALID_SHIFT 0 4744 #define DDR34_E0_PHY_CONTROL_REGS_READ_ENABLE_STATUS_VALID_DEFAULT 0x00000000 4745 4746 /*************************************************************************** 4747 *TRAFFIC_GEN_LFSR_SEED - Traffic generator seed register 4748 */ 4749 /* DDR34_E0_PHY_CONTROL_REGS :: TRAFFIC_GEN_LFSR_SEED :: SEED [31:00] */ 4750 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_LFSR_SEED_SEED_MASK 0xffffffff 4751 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_LFSR_SEED_SEED_ALIGN 0 4752 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_LFSR_SEED_SEED_BITS 32 4753 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_LFSR_SEED_SEED_SHIFT 0 4754 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_LFSR_SEED_SEED_DEFAULT 0xba5eba11 4755 4756 /*************************************************************************** 4757 *TRAFFIC_GEN_ADDRESS1 - Traffic generator address register #1 4758 */ 4759 /* DDR34_E0_PHY_CONTROL_REGS :: TRAFFIC_GEN_ADDRESS1 :: reserved0 [31:20] */ 4760 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_ADDRESS1_RESERVED0_MASK 0xfff00000 4761 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_ADDRESS1_RESERVED0_ALIGN 0 4762 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_ADDRESS1_RESERVED0_BITS 12 4763 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_ADDRESS1_RESERVED0_SHIFT 20 4764 4765 /* DDR34_E0_PHY_CONTROL_REGS :: TRAFFIC_GEN_ADDRESS1 :: BANK [19:16] */ 4766 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_ADDRESS1_BANK_MASK 0x000f0000 4767 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_ADDRESS1_BANK_ALIGN 0 4768 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_ADDRESS1_BANK_BITS 4 4769 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_ADDRESS1_BANK_SHIFT 16 4770 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_ADDRESS1_BANK_DEFAULT 0x00000000 4771 4772 /* DDR34_E0_PHY_CONTROL_REGS :: TRAFFIC_GEN_ADDRESS1 :: ROW [15:00] */ 4773 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_ADDRESS1_ROW_MASK 0x0000ffff 4774 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_ADDRESS1_ROW_ALIGN 0 4775 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_ADDRESS1_ROW_BITS 16 4776 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_ADDRESS1_ROW_SHIFT 0 4777 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_ADDRESS1_ROW_DEFAULT 0x00000000 4778 4779 /*************************************************************************** 4780 *TRAFFIC_GEN_ADDRESS2 - Traffic generator address register #2 4781 */ 4782 /* DDR34_E0_PHY_CONTROL_REGS :: TRAFFIC_GEN_ADDRESS2 :: reserved0 [31:20] */ 4783 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_ADDRESS2_RESERVED0_MASK 0xfff00000 4784 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_ADDRESS2_RESERVED0_ALIGN 0 4785 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_ADDRESS2_RESERVED0_BITS 12 4786 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_ADDRESS2_RESERVED0_SHIFT 20 4787 4788 /* DDR34_E0_PHY_CONTROL_REGS :: TRAFFIC_GEN_ADDRESS2 :: BANK [19:16] */ 4789 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_ADDRESS2_BANK_MASK 0x000f0000 4790 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_ADDRESS2_BANK_ALIGN 0 4791 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_ADDRESS2_BANK_BITS 4 4792 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_ADDRESS2_BANK_SHIFT 16 4793 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_ADDRESS2_BANK_DEFAULT 0x00000000 4794 4795 /* DDR34_E0_PHY_CONTROL_REGS :: TRAFFIC_GEN_ADDRESS2 :: ROW [15:00] */ 4796 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_ADDRESS2_ROW_MASK 0x0000ffff 4797 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_ADDRESS2_ROW_ALIGN 0 4798 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_ADDRESS2_ROW_BITS 16 4799 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_ADDRESS2_ROW_SHIFT 0 4800 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_ADDRESS2_ROW_DEFAULT 0x00000000 4801 4802 /*************************************************************************** 4803 *TRAFFIC_GEN_CONTROL - Traffic generator control register 4804 */ 4805 /* DDR34_E0_PHY_CONTROL_REGS :: TRAFFIC_GEN_CONTROL :: reserved0 [31:13] */ 4806 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_RESERVED0_MASK 0xffffe000 4807 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_RESERVED0_ALIGN 0 4808 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_RESERVED0_BITS 19 4809 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_RESERVED0_SHIFT 13 4810 4811 /* DDR34_E0_PHY_CONTROL_REGS :: TRAFFIC_GEN_CONTROL :: DIAG_WRO [12:12] */ 4812 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_DIAG_WRO_MASK 0x00001000 4813 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_DIAG_WRO_ALIGN 0 4814 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_DIAG_WRO_BITS 1 4815 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_DIAG_WRO_SHIFT 12 4816 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_DIAG_WRO_DEFAULT 0x00000000 4817 4818 /* DDR34_E0_PHY_CONTROL_REGS :: TRAFFIC_GEN_CONTROL :: DIAG_WRO_RD [11:11] */ 4819 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_DIAG_WRO_RD_MASK 0x00000800 4820 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_DIAG_WRO_RD_ALIGN 0 4821 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_DIAG_WRO_RD_BITS 1 4822 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_DIAG_WRO_RD_SHIFT 11 4823 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_DIAG_WRO_RD_DEFAULT 0x00000000 4824 4825 /* DDR34_E0_PHY_CONTROL_REGS :: TRAFFIC_GEN_CONTROL :: DIAG_WR_RD [10:10] */ 4826 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_DIAG_WR_RD_MASK 0x00000400 4827 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_DIAG_WR_RD_ALIGN 0 4828 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_DIAG_WR_RD_BITS 1 4829 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_DIAG_WR_RD_SHIFT 10 4830 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_DIAG_WR_RD_DEFAULT 0x00000000 4831 4832 /* DDR34_E0_PHY_CONTROL_REGS :: TRAFFIC_GEN_CONTROL :: WR_NOISE [09:09] */ 4833 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_WR_NOISE_MASK 0x00000200 4834 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_WR_NOISE_ALIGN 0 4835 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_WR_NOISE_BITS 1 4836 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_WR_NOISE_SHIFT 9 4837 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_WR_NOISE_DEFAULT 0x00000000 4838 4839 /* DDR34_E0_PHY_CONTROL_REGS :: TRAFFIC_GEN_CONTROL :: RD_NOISE [08:08] */ 4840 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_RD_NOISE_MASK 0x00000100 4841 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_RD_NOISE_ALIGN 0 4842 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_RD_NOISE_BITS 1 4843 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_RD_NOISE_SHIFT 8 4844 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_RD_NOISE_DEFAULT 0x00000000 4845 4846 /* DDR34_E0_PHY_CONTROL_REGS :: TRAFFIC_GEN_CONTROL :: CLEAR_DRAM [07:07] */ 4847 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_CLEAR_DRAM_MASK 0x00000080 4848 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_CLEAR_DRAM_ALIGN 0 4849 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_CLEAR_DRAM_BITS 1 4850 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_CLEAR_DRAM_SHIFT 7 4851 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_CLEAR_DRAM_DEFAULT 0x00000000 4852 4853 /* DDR34_E0_PHY_CONTROL_REGS :: TRAFFIC_GEN_CONTROL :: MASK_DM [06:06] */ 4854 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_MASK_DM_MASK 0x00000040 4855 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_MASK_DM_ALIGN 0 4856 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_MASK_DM_BITS 1 4857 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_MASK_DM_SHIFT 6 4858 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_MASK_DM_DEFAULT 0x00000000 4859 4860 /* DDR34_E0_PHY_CONTROL_REGS :: TRAFFIC_GEN_CONTROL :: INIT_LFSR [05:05] */ 4861 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_INIT_LFSR_MASK 0x00000020 4862 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_INIT_LFSR_ALIGN 0 4863 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_INIT_LFSR_BITS 1 4864 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_INIT_LFSR_SHIFT 5 4865 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_INIT_LFSR_DEFAULT 0x00000000 4866 4867 /* DDR34_E0_PHY_CONTROL_REGS :: TRAFFIC_GEN_CONTROL :: FIFO [04:04] */ 4868 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_FIFO_MASK 0x00000010 4869 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_FIFO_ALIGN 0 4870 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_FIFO_BITS 1 4871 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_FIFO_SHIFT 4 4872 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_FIFO_DEFAULT 0x00000000 4873 4874 /* DDR34_E0_PHY_CONTROL_REGS :: TRAFFIC_GEN_CONTROL :: MPR [03:03] */ 4875 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_MPR_MASK 0x00000008 4876 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_MPR_ALIGN 0 4877 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_MPR_BITS 1 4878 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_MPR_SHIFT 3 4879 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_MPR_DEFAULT 0x00000000 4880 4881 /* DDR34_E0_PHY_CONTROL_REGS :: TRAFFIC_GEN_CONTROL :: RD_WR [02:02] */ 4882 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_RD_WR_MASK 0x00000004 4883 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_RD_WR_ALIGN 0 4884 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_RD_WR_BITS 1 4885 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_RD_WR_SHIFT 2 4886 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_RD_WR_DEFAULT 0x00000000 4887 4888 /* DDR34_E0_PHY_CONTROL_REGS :: TRAFFIC_GEN_CONTROL :: RD_EN [01:01] */ 4889 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_RD_EN_MASK 0x00000002 4890 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_RD_EN_ALIGN 0 4891 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_RD_EN_BITS 1 4892 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_RD_EN_SHIFT 1 4893 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_RD_EN_DEFAULT 0x00000000 4894 4895 /* DDR34_E0_PHY_CONTROL_REGS :: TRAFFIC_GEN_CONTROL :: ENABLE [00:00] */ 4896 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_ENABLE_MASK 0x00000001 4897 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_ENABLE_ALIGN 0 4898 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_ENABLE_BITS 1 4899 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_ENABLE_SHIFT 0 4900 4901 /*************************************************************************** 4902 *TRAFFIC_GEN_DATA_CONTROL - Traffic generator data control register 4903 */ 4904 /* DDR34_E0_PHY_CONTROL_REGS :: TRAFFIC_GEN_DATA_CONTROL :: reserved0 [31:22] */ 4905 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_DATA_CONTROL_RESERVED0_MASK 0xffc00000 4906 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_DATA_CONTROL_RESERVED0_ALIGN 0 4907 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_DATA_CONTROL_RESERVED0_BITS 10 4908 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_DATA_CONTROL_RESERVED0_SHIFT 22 4909 4910 /* DDR34_E0_PHY_CONTROL_REGS :: TRAFFIC_GEN_DATA_CONTROL :: PATTERN [21:20] */ 4911 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_DATA_CONTROL_PATTERN_MASK 0x00300000 4912 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_DATA_CONTROL_PATTERN_ALIGN 0 4913 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_DATA_CONTROL_PATTERN_BITS 2 4914 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_DATA_CONTROL_PATTERN_SHIFT 20 4915 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_DATA_CONTROL_PATTERN_DEFAULT 0x00000000 4916 4917 /* DDR34_E0_PHY_CONTROL_REGS :: TRAFFIC_GEN_DATA_CONTROL :: LENGTH [19:00] */ 4918 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_DATA_CONTROL_LENGTH_MASK 0x000fffff 4919 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_DATA_CONTROL_LENGTH_ALIGN 0 4920 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_DATA_CONTROL_LENGTH_BITS 20 4921 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_DATA_CONTROL_LENGTH_SHIFT 0 4922 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_DATA_CONTROL_LENGTH_DEFAULT 0x00000000 4923 4924 /*************************************************************************** 4925 *TRAFFIC_GEN_DQ_MASK - Traffic generator DQ mask register 4926 */ 4927 /* DDR34_E0_PHY_CONTROL_REGS :: TRAFFIC_GEN_DQ_MASK :: MASK [31:00] */ 4928 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_MASK_MASK_MASK 0xffffffff 4929 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_MASK_MASK_ALIGN 0 4930 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_MASK_MASK_BITS 32 4931 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_MASK_MASK_SHIFT 0 4932 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_MASK_MASK_DEFAULT 0x00000000 4933 4934 /*************************************************************************** 4935 *TRAFFIC_GEN_ECC_DQ_MASK - Traffic generator ECC DQ mask register 4936 */ 4937 /* DDR34_E0_PHY_CONTROL_REGS :: TRAFFIC_GEN_ECC_DQ_MASK :: reserved0 [31:04] */ 4938 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_ECC_DQ_MASK_RESERVED0_MASK 0xfffffff0 4939 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_ECC_DQ_MASK_RESERVED0_ALIGN 0 4940 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_ECC_DQ_MASK_RESERVED0_BITS 28 4941 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_ECC_DQ_MASK_RESERVED0_SHIFT 4 4942 4943 /* DDR34_E0_PHY_CONTROL_REGS :: TRAFFIC_GEN_ECC_DQ_MASK :: MASK [03:00] */ 4944 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_ECC_DQ_MASK_MASK_MASK 0x0000000f 4945 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_ECC_DQ_MASK_MASK_ALIGN 0 4946 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_ECC_DQ_MASK_MASK_BITS 4 4947 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_ECC_DQ_MASK_MASK_SHIFT 0 4948 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_ECC_DQ_MASK_MASK_DEFAULT 0x00000000 4949 4950 /*************************************************************************** 4951 *TRAFFIC_GEN_STATUS - Traffic generator status register 4952 */ 4953 /* DDR34_E0_PHY_CONTROL_REGS :: TRAFFIC_GEN_STATUS :: reserved0 [31:01] */ 4954 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_STATUS_RESERVED0_MASK 0xfffffffe 4955 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_STATUS_RESERVED0_ALIGN 0 4956 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_STATUS_RESERVED0_BITS 31 4957 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_STATUS_RESERVED0_SHIFT 1 4958 4959 /* DDR34_E0_PHY_CONTROL_REGS :: TRAFFIC_GEN_STATUS :: BUSY [00:00] */ 4960 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_STATUS_BUSY_MASK 0x00000001 4961 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_STATUS_BUSY_ALIGN 0 4962 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_STATUS_BUSY_BITS 1 4963 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_STATUS_BUSY_SHIFT 0 4964 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_STATUS_BUSY_DEFAULT 0x00000000 4965 4966 /*************************************************************************** 4967 *TRAFFIC_GEN_DQ_STATUS - Traffic generator DQ status register 4968 */ 4969 /* DDR34_E0_PHY_CONTROL_REGS :: TRAFFIC_GEN_DQ_STATUS :: STATUS [31:00] */ 4970 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUS_STATUS_MASK 0xffffffff 4971 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUS_STATUS_ALIGN 0 4972 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUS_STATUS_BITS 32 4973 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUS_STATUS_SHIFT 0 4974 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUS_STATUS_DEFAULT 0x00000000 4975 4976 /*************************************************************************** 4977 *TRAFFIC_GEN_ECC_STATUS - Traffic generator ECC DQ status register 4978 */ 4979 /* DDR34_E0_PHY_CONTROL_REGS :: TRAFFIC_GEN_ECC_STATUS :: reserved0 [31:04] */ 4980 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_ECC_STATUS_RESERVED0_MASK 0xfffffff0 4981 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_ECC_STATUS_RESERVED0_ALIGN 0 4982 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_ECC_STATUS_RESERVED0_BITS 28 4983 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_ECC_STATUS_RESERVED0_SHIFT 4 4984 4985 /* DDR34_E0_PHY_CONTROL_REGS :: TRAFFIC_GEN_ECC_STATUS :: STATUS [03:00] */ 4986 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_ECC_STATUS_STATUS_MASK 0x0000000f 4987 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_ECC_STATUS_STATUS_ALIGN 0 4988 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_ECC_STATUS_STATUS_BITS 4 4989 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_ECC_STATUS_STATUS_SHIFT 0 4990 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_ECC_STATUS_STATUS_DEFAULT 0x00000000 4991 4992 /*************************************************************************** 4993 *TRAFFIC_GEN_ERR_CNT_CONTROL - Traffic generator error count control register 4994 */ 4995 /* DDR34_E0_PHY_CONTROL_REGS :: TRAFFIC_GEN_ERR_CNT_CONTROL :: reserved0 [31:09] */ 4996 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_ERR_CNT_CONTROL_RESERVED0_MASK 0xfffffe00 4997 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_ERR_CNT_CONTROL_RESERVED0_ALIGN 0 4998 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_ERR_CNT_CONTROL_RESERVED0_BITS 23 4999 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_ERR_CNT_CONTROL_RESERVED0_SHIFT 9 5000 5001 /* DDR34_E0_PHY_CONTROL_REGS :: TRAFFIC_GEN_ERR_CNT_CONTROL :: DQ_SEL [08:04] */ 5002 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_ERR_CNT_CONTROL_DQ_SEL_MASK 0x000001f0 5003 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_ERR_CNT_CONTROL_DQ_SEL_ALIGN 0 5004 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_ERR_CNT_CONTROL_DQ_SEL_BITS 5 5005 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_ERR_CNT_CONTROL_DQ_SEL_SHIFT 4 5006 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_ERR_CNT_CONTROL_DQ_SEL_DEFAULT 0x00000000 5007 5008 /* DDR34_E0_PHY_CONTROL_REGS :: TRAFFIC_GEN_ERR_CNT_CONTROL :: reserved1 [03:02] */ 5009 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_ERR_CNT_CONTROL_RESERVED1_MASK 0x0000000c 5010 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_ERR_CNT_CONTROL_RESERVED1_ALIGN 0 5011 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_ERR_CNT_CONTROL_RESERVED1_BITS 2 5012 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_ERR_CNT_CONTROL_RESERVED1_SHIFT 2 5013 5014 /* DDR34_E0_PHY_CONTROL_REGS :: TRAFFIC_GEN_ERR_CNT_CONTROL :: CLEAR [01:01] */ 5015 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_ERR_CNT_CONTROL_CLEAR_MASK 0x00000002 5016 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_ERR_CNT_CONTROL_CLEAR_ALIGN 0 5017 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_ERR_CNT_CONTROL_CLEAR_BITS 1 5018 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_ERR_CNT_CONTROL_CLEAR_SHIFT 1 5019 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_ERR_CNT_CONTROL_CLEAR_DEFAULT 0x00000000 5020 5021 /* DDR34_E0_PHY_CONTROL_REGS :: TRAFFIC_GEN_ERR_CNT_CONTROL :: ENABLE [00:00] */ 5022 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_ERR_CNT_CONTROL_ENABLE_MASK 0x00000001 5023 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_ERR_CNT_CONTROL_ENABLE_ALIGN 0 5024 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_ERR_CNT_CONTROL_ENABLE_BITS 1 5025 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_ERR_CNT_CONTROL_ENABLE_SHIFT 0 5026 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_ERR_CNT_CONTROL_ENABLE_DEFAULT 0x00000000 5027 5028 /*************************************************************************** 5029 *TRAFFIC_GEN_ERR_CNT_STATUS - Traffic generator error count status register 5030 */ 5031 /* DDR34_E0_PHY_CONTROL_REGS :: TRAFFIC_GEN_ERR_CNT_STATUS :: reserved0 [31:16] */ 5032 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_ERR_CNT_STATUS_RESERVED0_MASK 0xffff0000 5033 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_ERR_CNT_STATUS_RESERVED0_ALIGN 0 5034 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_ERR_CNT_STATUS_RESERVED0_BITS 16 5035 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_ERR_CNT_STATUS_RESERVED0_SHIFT 16 5036 5037 /* DDR34_E0_PHY_CONTROL_REGS :: TRAFFIC_GEN_ERR_CNT_STATUS :: COUNT [15:00] */ 5038 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_ERR_CNT_STATUS_COUNT_MASK 0x0000ffff 5039 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_ERR_CNT_STATUS_COUNT_ALIGN 0 5040 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_ERR_CNT_STATUS_COUNT_BITS 16 5041 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_ERR_CNT_STATUS_COUNT_SHIFT 0 5042 #define DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_ERR_CNT_STATUS_COUNT_DEFAULT 0x00000000 5043 5044 /*************************************************************************** 5045 *VIRTUAL_VTT_CONTROL - Virtual VTT Control and Status register 5046 */ 5047 /* DDR34_E0_PHY_CONTROL_REGS :: VIRTUAL_VTT_CONTROL :: reserved0 [31:12] */ 5048 #define DDR34_E0_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_RESERVED0_MASK 0xfffff000 5049 #define DDR34_E0_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_RESERVED0_ALIGN 0 5050 #define DDR34_E0_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_RESERVED0_BITS 20 5051 #define DDR34_E0_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_RESERVED0_SHIFT 12 5052 5053 /* DDR34_E0_PHY_CONTROL_REGS :: VIRTUAL_VTT_CONTROL :: reserved_for_eco1 [11:08] */ 5054 #define DDR34_E0_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_RESERVED_for_eco1_MASK 0x00000f00 5055 #define DDR34_E0_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_RESERVED_for_eco1_ALIGN 0 5056 #define DDR34_E0_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_RESERVED_for_eco1_BITS 4 5057 #define DDR34_E0_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_RESERVED_for_eco1_SHIFT 8 5058 #define DDR34_E0_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_RESERVED_for_eco1_DEFAULT 0x00000000 5059 5060 /* DDR34_E0_PHY_CONTROL_REGS :: VIRTUAL_VTT_CONTROL :: MAX_NOISE [07:07] */ 5061 #define DDR34_E0_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_MAX_NOISE_MASK 0x00000080 5062 #define DDR34_E0_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_MAX_NOISE_ALIGN 0 5063 #define DDR34_E0_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_MAX_NOISE_BITS 1 5064 #define DDR34_E0_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_MAX_NOISE_SHIFT 7 5065 #define DDR34_E0_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_MAX_NOISE_DEFAULT 0x00000000 5066 5067 /* DDR34_E0_PHY_CONTROL_REGS :: VIRTUAL_VTT_CONTROL :: LOW_NOISE [06:06] */ 5068 #define DDR34_E0_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_LOW_NOISE_MASK 0x00000040 5069 #define DDR34_E0_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_LOW_NOISE_ALIGN 0 5070 #define DDR34_E0_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_LOW_NOISE_BITS 1 5071 #define DDR34_E0_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_LOW_NOISE_SHIFT 6 5072 #define DDR34_E0_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_LOW_NOISE_DEFAULT 0x00000000 5073 5074 /* DDR34_E0_PHY_CONTROL_REGS :: VIRTUAL_VTT_CONTROL :: LOW_VTT [05:05] */ 5075 #define DDR34_E0_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_LOW_VTT_MASK 0x00000020 5076 #define DDR34_E0_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_LOW_VTT_ALIGN 0 5077 #define DDR34_E0_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_LOW_VTT_BITS 1 5078 #define DDR34_E0_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_LOW_VTT_SHIFT 5 5079 #define DDR34_E0_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_LOW_VTT_DEFAULT 0x00000000 5080 5081 /* DDR34_E0_PHY_CONTROL_REGS :: VIRTUAL_VTT_CONTROL :: HIGH_VTT [04:04] */ 5082 #define DDR34_E0_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_HIGH_VTT_MASK 0x00000010 5083 #define DDR34_E0_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_HIGH_VTT_ALIGN 0 5084 #define DDR34_E0_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_HIGH_VTT_BITS 1 5085 #define DDR34_E0_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_HIGH_VTT_SHIFT 4 5086 #define DDR34_E0_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_HIGH_VTT_DEFAULT 0x00000000 5087 5088 /* DDR34_E0_PHY_CONTROL_REGS :: VIRTUAL_VTT_CONTROL :: ERROR_RESET [03:03] */ 5089 #define DDR34_E0_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_ERROR_RESET_MASK 0x00000008 5090 #define DDR34_E0_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_ERROR_RESET_ALIGN 0 5091 #define DDR34_E0_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_ERROR_RESET_BITS 1 5092 #define DDR34_E0_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_ERROR_RESET_SHIFT 3 5093 #define DDR34_E0_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_ERROR_RESET_DEFAULT 0x00000000 5094 5095 /* DDR34_E0_PHY_CONTROL_REGS :: VIRTUAL_VTT_CONTROL :: ENABLE_CTL_IDLE [02:02] */ 5096 #define DDR34_E0_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_ENABLE_CTL_IDLE_MASK 0x00000004 5097 #define DDR34_E0_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_ENABLE_CTL_IDLE_ALIGN 0 5098 #define DDR34_E0_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_ENABLE_CTL_IDLE_BITS 1 5099 #define DDR34_E0_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_ENABLE_CTL_IDLE_SHIFT 2 5100 #define DDR34_E0_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_ENABLE_CTL_IDLE_DEFAULT 0x00000000 5101 5102 /* DDR34_E0_PHY_CONTROL_REGS :: VIRTUAL_VTT_CONTROL :: ENABLE_CS_IDLE [01:01] */ 5103 #define DDR34_E0_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_ENABLE_CS_IDLE_MASK 0x00000002 5104 #define DDR34_E0_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_ENABLE_CS_IDLE_ALIGN 0 5105 #define DDR34_E0_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_ENABLE_CS_IDLE_BITS 1 5106 #define DDR34_E0_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_ENABLE_CS_IDLE_SHIFT 1 5107 #define DDR34_E0_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_ENABLE_CS_IDLE_DEFAULT 0x00000000 5108 5109 /* DDR34_E0_PHY_CONTROL_REGS :: VIRTUAL_VTT_CONTROL :: ENABLE_CKE_IDLE [00:00] */ 5110 #define DDR34_E0_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_ENABLE_CKE_IDLE_MASK 0x00000001 5111 #define DDR34_E0_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_ENABLE_CKE_IDLE_ALIGN 0 5112 #define DDR34_E0_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_ENABLE_CKE_IDLE_BITS 1 5113 #define DDR34_E0_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_ENABLE_CKE_IDLE_SHIFT 0 5114 #define DDR34_E0_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_ENABLE_CKE_IDLE_DEFAULT 0x00000000 5115 5116 /*************************************************************************** 5117 *VIRTUAL_VTT_STATUS - Virtual VTT Control and Status register 5118 */ 5119 /* DDR34_E0_PHY_CONTROL_REGS :: VIRTUAL_VTT_STATUS :: reserved0 [31:19] */ 5120 #define DDR34_E0_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS_RESERVED0_MASK 0xfff80000 5121 #define DDR34_E0_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS_RESERVED0_ALIGN 0 5122 #define DDR34_E0_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS_RESERVED0_BITS 13 5123 #define DDR34_E0_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS_RESERVED0_SHIFT 19 5124 5125 /* DDR34_E0_PHY_CONTROL_REGS :: VIRTUAL_VTT_STATUS :: ERROR [18:03] */ 5126 #define DDR34_E0_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS_ERROR_MASK 0x0007fff8 5127 #define DDR34_E0_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS_ERROR_ALIGN 0 5128 #define DDR34_E0_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS_ERROR_BITS 16 5129 #define DDR34_E0_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS_ERROR_SHIFT 3 5130 #define DDR34_E0_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS_ERROR_DEFAULT 0x00000000 5131 5132 /* DDR34_E0_PHY_CONTROL_REGS :: VIRTUAL_VTT_STATUS :: ERROR_LOW [02:02] */ 5133 #define DDR34_E0_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS_ERROR_LOW_MASK 0x00000004 5134 #define DDR34_E0_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS_ERROR_LOW_ALIGN 0 5135 #define DDR34_E0_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS_ERROR_LOW_BITS 1 5136 #define DDR34_E0_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS_ERROR_LOW_SHIFT 2 5137 #define DDR34_E0_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS_ERROR_LOW_DEFAULT 0x00000000 5138 5139 /* DDR34_E0_PHY_CONTROL_REGS :: VIRTUAL_VTT_STATUS :: ERROR_HIGH [01:01] */ 5140 #define DDR34_E0_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS_ERROR_HIGH_MASK 0x00000002 5141 #define DDR34_E0_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS_ERROR_HIGH_ALIGN 0 5142 #define DDR34_E0_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS_ERROR_HIGH_BITS 1 5143 #define DDR34_E0_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS_ERROR_HIGH_SHIFT 1 5144 #define DDR34_E0_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS_ERROR_HIGH_DEFAULT 0x00000000 5145 5146 /* DDR34_E0_PHY_CONTROL_REGS :: VIRTUAL_VTT_STATUS :: READY [00:00] */ 5147 #define DDR34_E0_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS_READY_MASK 0x00000001 5148 #define DDR34_E0_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS_READY_ALIGN 0 5149 #define DDR34_E0_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS_READY_BITS 1 5150 #define DDR34_E0_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS_READY_SHIFT 0 5151 #define DDR34_E0_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS_READY_DEFAULT 0x00000000 5152 5153 /*************************************************************************** 5154 *VIRTUAL_VTT_CONNECTIONS - Virtual VTT Connections register 5155 */ 5156 /* DDR34_E0_PHY_CONTROL_REGS :: VIRTUAL_VTT_CONNECTIONS :: reserved0 [31:31] */ 5157 #define DDR34_E0_PHY_CONTROL_REGS_VIRTUAL_VTT_CONNECTIONS_RESERVED0_MASK 0x80000000 5158 #define DDR34_E0_PHY_CONTROL_REGS_VIRTUAL_VTT_CONNECTIONS_RESERVED0_ALIGN 0 5159 #define DDR34_E0_PHY_CONTROL_REGS_VIRTUAL_VTT_CONNECTIONS_RESERVED0_BITS 1 5160 #define DDR34_E0_PHY_CONTROL_REGS_VIRTUAL_VTT_CONNECTIONS_RESERVED0_SHIFT 31 5161 5162 /* DDR34_E0_PHY_CONTROL_REGS :: VIRTUAL_VTT_CONNECTIONS :: MASK [30:00] */ 5163 #define DDR34_E0_PHY_CONTROL_REGS_VIRTUAL_VTT_CONNECTIONS_MASK_MASK 0x7fffffff 5164 #define DDR34_E0_PHY_CONTROL_REGS_VIRTUAL_VTT_CONNECTIONS_MASK_ALIGN 0 5165 #define DDR34_E0_PHY_CONTROL_REGS_VIRTUAL_VTT_CONNECTIONS_MASK_BITS 31 5166 #define DDR34_E0_PHY_CONTROL_REGS_VIRTUAL_VTT_CONNECTIONS_MASK_SHIFT 0 5167 #define DDR34_E0_PHY_CONTROL_REGS_VIRTUAL_VTT_CONNECTIONS_MASK_DEFAULT 0x1fffffff 5168 5169 /*************************************************************************** 5170 *VIRTUAL_VTT_OVERRIDE - Virtual VTT Override register 5171 */ 5172 /* DDR34_E0_PHY_CONTROL_REGS :: VIRTUAL_VTT_OVERRIDE :: reserved0 [31:31] */ 5173 #define DDR34_E0_PHY_CONTROL_REGS_VIRTUAL_VTT_OVERRIDE_RESERVED0_MASK 0x80000000 5174 #define DDR34_E0_PHY_CONTROL_REGS_VIRTUAL_VTT_OVERRIDE_RESERVED0_ALIGN 0 5175 #define DDR34_E0_PHY_CONTROL_REGS_VIRTUAL_VTT_OVERRIDE_RESERVED0_BITS 1 5176 #define DDR34_E0_PHY_CONTROL_REGS_VIRTUAL_VTT_OVERRIDE_RESERVED0_SHIFT 31 5177 5178 /* DDR34_E0_PHY_CONTROL_REGS :: VIRTUAL_VTT_OVERRIDE :: MASK [30:00] */ 5179 #define DDR34_E0_PHY_CONTROL_REGS_VIRTUAL_VTT_OVERRIDE_MASK_MASK 0x7fffffff 5180 #define DDR34_E0_PHY_CONTROL_REGS_VIRTUAL_VTT_OVERRIDE_MASK_ALIGN 0 5181 #define DDR34_E0_PHY_CONTROL_REGS_VIRTUAL_VTT_OVERRIDE_MASK_BITS 31 5182 #define DDR34_E0_PHY_CONTROL_REGS_VIRTUAL_VTT_OVERRIDE_MASK_SHIFT 0 5183 #define DDR34_E0_PHY_CONTROL_REGS_VIRTUAL_VTT_OVERRIDE_MASK_DEFAULT 0x0000ffff 5184 5185 /*************************************************************************** 5186 *VREF_DAC_CONTROL - VREF DAC Control register 5187 */ 5188 /* DDR34_E0_PHY_CONTROL_REGS :: VREF_DAC_CONTROL :: reserved0 [31:20] */ 5189 #define DDR34_E0_PHY_CONTROL_REGS_VREF_DAC_CONTROL_RESERVED0_MASK 0xfff00000 5190 #define DDR34_E0_PHY_CONTROL_REGS_VREF_DAC_CONTROL_RESERVED0_ALIGN 0 5191 #define DDR34_E0_PHY_CONTROL_REGS_VREF_DAC_CONTROL_RESERVED0_BITS 12 5192 #define DDR34_E0_PHY_CONTROL_REGS_VREF_DAC_CONTROL_RESERVED0_SHIFT 20 5193 5194 /* DDR34_E0_PHY_CONTROL_REGS :: VREF_DAC_CONTROL :: AUX_GT_INT [19:19] */ 5195 #define DDR34_E0_PHY_CONTROL_REGS_VREF_DAC_CONTROL_AUX_GT_INT_MASK 0x00080000 5196 #define DDR34_E0_PHY_CONTROL_REGS_VREF_DAC_CONTROL_AUX_GT_INT_ALIGN 0 5197 #define DDR34_E0_PHY_CONTROL_REGS_VREF_DAC_CONTROL_AUX_GT_INT_BITS 1 5198 #define DDR34_E0_PHY_CONTROL_REGS_VREF_DAC_CONTROL_AUX_GT_INT_SHIFT 19 5199 #define DDR34_E0_PHY_CONTROL_REGS_VREF_DAC_CONTROL_AUX_GT_INT_DEFAULT 0x00000000 5200 5201 /* DDR34_E0_PHY_CONTROL_REGS :: VREF_DAC_CONTROL :: TESTOUT_MUX_CTL [18:17] */ 5202 #define DDR34_E0_PHY_CONTROL_REGS_VREF_DAC_CONTROL_TESTOUT_MUX_CTL_MASK 0x00060000 5203 #define DDR34_E0_PHY_CONTROL_REGS_VREF_DAC_CONTROL_TESTOUT_MUX_CTL_ALIGN 0 5204 #define DDR34_E0_PHY_CONTROL_REGS_VREF_DAC_CONTROL_TESTOUT_MUX_CTL_BITS 2 5205 #define DDR34_E0_PHY_CONTROL_REGS_VREF_DAC_CONTROL_TESTOUT_MUX_CTL_SHIFT 17 5206 #define DDR34_E0_PHY_CONTROL_REGS_VREF_DAC_CONTROL_TESTOUT_MUX_CTL_DEFAULT 0x00000000 5207 5208 /* DDR34_E0_PHY_CONTROL_REGS :: VREF_DAC_CONTROL :: TEST [16:16] */ 5209 #define DDR34_E0_PHY_CONTROL_REGS_VREF_DAC_CONTROL_TEST_MASK 0x00010000 5210 #define DDR34_E0_PHY_CONTROL_REGS_VREF_DAC_CONTROL_TEST_ALIGN 0 5211 #define DDR34_E0_PHY_CONTROL_REGS_VREF_DAC_CONTROL_TEST_BITS 1 5212 #define DDR34_E0_PHY_CONTROL_REGS_VREF_DAC_CONTROL_TEST_SHIFT 16 5213 #define DDR34_E0_PHY_CONTROL_REGS_VREF_DAC_CONTROL_TEST_DEFAULT 0x00000000 5214 5215 /* DDR34_E0_PHY_CONTROL_REGS :: VREF_DAC_CONTROL :: PDN3 [15:15] */ 5216 #define DDR34_E0_PHY_CONTROL_REGS_VREF_DAC_CONTROL_PDN3_MASK 0x00008000 5217 #define DDR34_E0_PHY_CONTROL_REGS_VREF_DAC_CONTROL_PDN3_ALIGN 0 5218 #define DDR34_E0_PHY_CONTROL_REGS_VREF_DAC_CONTROL_PDN3_BITS 1 5219 #define DDR34_E0_PHY_CONTROL_REGS_VREF_DAC_CONTROL_PDN3_SHIFT 15 5220 #define DDR34_E0_PHY_CONTROL_REGS_VREF_DAC_CONTROL_PDN3_DEFAULT 0x00000001 5221 5222 /* DDR34_E0_PHY_CONTROL_REGS :: VREF_DAC_CONTROL :: PDN2 [14:14] */ 5223 #define DDR34_E0_PHY_CONTROL_REGS_VREF_DAC_CONTROL_PDN2_MASK 0x00004000 5224 #define DDR34_E0_PHY_CONTROL_REGS_VREF_DAC_CONTROL_PDN2_ALIGN 0 5225 #define DDR34_E0_PHY_CONTROL_REGS_VREF_DAC_CONTROL_PDN2_BITS 1 5226 #define DDR34_E0_PHY_CONTROL_REGS_VREF_DAC_CONTROL_PDN2_SHIFT 14 5227 #define DDR34_E0_PHY_CONTROL_REGS_VREF_DAC_CONTROL_PDN2_DEFAULT 0x00000001 5228 5229 /* DDR34_E0_PHY_CONTROL_REGS :: VREF_DAC_CONTROL :: PDN1 [13:13] */ 5230 #define DDR34_E0_PHY_CONTROL_REGS_VREF_DAC_CONTROL_PDN1_MASK 0x00002000 5231 #define DDR34_E0_PHY_CONTROL_REGS_VREF_DAC_CONTROL_PDN1_ALIGN 0 5232 #define DDR34_E0_PHY_CONTROL_REGS_VREF_DAC_CONTROL_PDN1_BITS 1 5233 #define DDR34_E0_PHY_CONTROL_REGS_VREF_DAC_CONTROL_PDN1_SHIFT 13 5234 #define DDR34_E0_PHY_CONTROL_REGS_VREF_DAC_CONTROL_PDN1_DEFAULT 0x00000001 5235 5236 /* DDR34_E0_PHY_CONTROL_REGS :: VREF_DAC_CONTROL :: PDN0 [12:12] */ 5237 #define DDR34_E0_PHY_CONTROL_REGS_VREF_DAC_CONTROL_PDN0_MASK 0x00001000 5238 #define DDR34_E0_PHY_CONTROL_REGS_VREF_DAC_CONTROL_PDN0_ALIGN 0 5239 #define DDR34_E0_PHY_CONTROL_REGS_VREF_DAC_CONTROL_PDN0_BITS 1 5240 #define DDR34_E0_PHY_CONTROL_REGS_VREF_DAC_CONTROL_PDN0_SHIFT 12 5241 #define DDR34_E0_PHY_CONTROL_REGS_VREF_DAC_CONTROL_PDN0_DEFAULT 0x00000001 5242 5243 /* DDR34_E0_PHY_CONTROL_REGS :: VREF_DAC_CONTROL :: DAC1 [11:06] */ 5244 #define DDR34_E0_PHY_CONTROL_REGS_VREF_DAC_CONTROL_DAC1_MASK 0x00000fc0 5245 #define DDR34_E0_PHY_CONTROL_REGS_VREF_DAC_CONTROL_DAC1_ALIGN 0 5246 #define DDR34_E0_PHY_CONTROL_REGS_VREF_DAC_CONTROL_DAC1_BITS 6 5247 #define DDR34_E0_PHY_CONTROL_REGS_VREF_DAC_CONTROL_DAC1_SHIFT 6 5248 #define DDR34_E0_PHY_CONTROL_REGS_VREF_DAC_CONTROL_DAC1_DEFAULT 0x00000020 5249 5250 /* DDR34_E0_PHY_CONTROL_REGS :: VREF_DAC_CONTROL :: DAC0 [05:00] */ 5251 #define DDR34_E0_PHY_CONTROL_REGS_VREF_DAC_CONTROL_DAC0_MASK 0x0000003f 5252 #define DDR34_E0_PHY_CONTROL_REGS_VREF_DAC_CONTROL_DAC0_ALIGN 0 5253 #define DDR34_E0_PHY_CONTROL_REGS_VREF_DAC_CONTROL_DAC0_BITS 6 5254 #define DDR34_E0_PHY_CONTROL_REGS_VREF_DAC_CONTROL_DAC0_SHIFT 0 5255 #define DDR34_E0_PHY_CONTROL_REGS_VREF_DAC_CONTROL_DAC0_DEFAULT 0x00000020 5256 5257 /*************************************************************************** 5258 *PHYBIST_CNTRL - PhyBist Control Register 5259 */ 5260 /* DDR34_E0_PHY_CONTROL_REGS :: PHYBIST_CNTRL :: reserved0 [31:30] */ 5261 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_CNTRL_RESERVED0_MASK 0xc0000000 5262 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_CNTRL_RESERVED0_ALIGN 0 5263 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_CNTRL_RESERVED0_BITS 2 5264 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_CNTRL_RESERVED0_SHIFT 30 5265 5266 /* DDR34_E0_PHY_CONTROL_REGS :: PHYBIST_CNTRL :: CLK_PAD_ENB [29:28] */ 5267 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_CNTRL_CLK_PAD_ENB_MASK 0x30000000 5268 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_CNTRL_CLK_PAD_ENB_ALIGN 0 5269 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_CNTRL_CLK_PAD_ENB_BITS 2 5270 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_CNTRL_CLK_PAD_ENB_SHIFT 28 5271 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_CNTRL_CLK_PAD_ENB_DEFAULT 0x00000002 5272 5273 /* DDR34_E0_PHY_CONTROL_REGS :: PHYBIST_CNTRL :: reserved1 [27:27] */ 5274 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_CNTRL_RESERVED1_MASK 0x08000000 5275 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_CNTRL_RESERVED1_ALIGN 0 5276 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_CNTRL_RESERVED1_BITS 1 5277 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_CNTRL_RESERVED1_SHIFT 27 5278 5279 /* DDR34_E0_PHY_CONTROL_REGS :: PHYBIST_CNTRL :: FORCE_DQ_ERROR_SEL [26:24] */ 5280 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_CNTRL_FORCE_DQ_ERROR_SEL_MASK 0x07000000 5281 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_CNTRL_FORCE_DQ_ERROR_SEL_ALIGN 0 5282 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_CNTRL_FORCE_DQ_ERROR_SEL_BITS 3 5283 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_CNTRL_FORCE_DQ_ERROR_SEL_SHIFT 24 5284 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_CNTRL_FORCE_DQ_ERROR_SEL_DEFAULT 0x00000000 5285 5286 /* DDR34_E0_PHY_CONTROL_REGS :: PHYBIST_CNTRL :: reserved2 [23:23] */ 5287 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_CNTRL_RESERVED2_MASK 0x00800000 5288 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_CNTRL_RESERVED2_ALIGN 0 5289 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_CNTRL_RESERVED2_BITS 1 5290 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_CNTRL_RESERVED2_SHIFT 23 5291 5292 /* DDR34_E0_PHY_CONTROL_REGS :: PHYBIST_CNTRL :: FORCE_BL_ERROR_SEL [22:20] */ 5293 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_CNTRL_FORCE_BL_ERROR_SEL_MASK 0x00700000 5294 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_CNTRL_FORCE_BL_ERROR_SEL_ALIGN 0 5295 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_CNTRL_FORCE_BL_ERROR_SEL_BITS 3 5296 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_CNTRL_FORCE_BL_ERROR_SEL_SHIFT 20 5297 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_CNTRL_FORCE_BL_ERROR_SEL_DEFAULT 0x00000000 5298 5299 /* DDR34_E0_PHY_CONTROL_REGS :: PHYBIST_CNTRL :: reserved3 [19:17] */ 5300 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_CNTRL_RESERVED3_MASK 0x000e0000 5301 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_CNTRL_RESERVED3_ALIGN 0 5302 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_CNTRL_RESERVED3_BITS 3 5303 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_CNTRL_RESERVED3_SHIFT 17 5304 5305 /* DDR34_E0_PHY_CONTROL_REGS :: PHYBIST_CNTRL :: FORCE_CTL_ERROR_SEL [16:12] */ 5306 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_CNTRL_FORCE_CTL_ERROR_SEL_MASK 0x0001f000 5307 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_CNTRL_FORCE_CTL_ERROR_SEL_ALIGN 0 5308 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_CNTRL_FORCE_CTL_ERROR_SEL_BITS 5 5309 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_CNTRL_FORCE_CTL_ERROR_SEL_SHIFT 12 5310 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_CNTRL_FORCE_CTL_ERROR_SEL_DEFAULT 0x00000000 5311 5312 /* DDR34_E0_PHY_CONTROL_REGS :: PHYBIST_CNTRL :: reserved4 [11:10] */ 5313 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_CNTRL_RESERVED4_MASK 0x00000c00 5314 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_CNTRL_RESERVED4_ALIGN 0 5315 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_CNTRL_RESERVED4_BITS 2 5316 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_CNTRL_RESERVED4_SHIFT 10 5317 5318 /* DDR34_E0_PHY_CONTROL_REGS :: PHYBIST_CNTRL :: FORCE_DAT_ERROR [09:09] */ 5319 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_CNTRL_FORCE_DAT_ERROR_MASK 0x00000200 5320 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_CNTRL_FORCE_DAT_ERROR_ALIGN 0 5321 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_CNTRL_FORCE_DAT_ERROR_BITS 1 5322 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_CNTRL_FORCE_DAT_ERROR_SHIFT 9 5323 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_CNTRL_FORCE_DAT_ERROR_DEFAULT 0x00000000 5324 5325 /* DDR34_E0_PHY_CONTROL_REGS :: PHYBIST_CNTRL :: FORCE_CTL_ERROR [08:08] */ 5326 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_CNTRL_FORCE_CTL_ERROR_MASK 0x00000100 5327 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_CNTRL_FORCE_CTL_ERROR_ALIGN 0 5328 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_CNTRL_FORCE_CTL_ERROR_BITS 1 5329 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_CNTRL_FORCE_CTL_ERROR_SHIFT 8 5330 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_CNTRL_FORCE_CTL_ERROR_DEFAULT 0x00000000 5331 5332 /* DDR34_E0_PHY_CONTROL_REGS :: PHYBIST_CNTRL :: SSO [07:06] */ 5333 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_CNTRL_SSO_MASK 0x000000c0 5334 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_CNTRL_SSO_ALIGN 0 5335 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_CNTRL_SSO_BITS 2 5336 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_CNTRL_SSO_SHIFT 6 5337 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_CNTRL_SSO_DEFAULT 0x00000000 5338 5339 /* DDR34_E0_PHY_CONTROL_REGS :: PHYBIST_CNTRL :: LENGTH [05:04] */ 5340 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_CNTRL_LENGTH_MASK 0x00000030 5341 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_CNTRL_LENGTH_ALIGN 0 5342 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_CNTRL_LENGTH_BITS 2 5343 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_CNTRL_LENGTH_SHIFT 4 5344 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_CNTRL_LENGTH_DEFAULT 0x00000000 5345 5346 /* DDR34_E0_PHY_CONTROL_REGS :: PHYBIST_CNTRL :: MODE [03:01] */ 5347 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_CNTRL_MODE_MASK 0x0000000e 5348 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_CNTRL_MODE_ALIGN 0 5349 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_CNTRL_MODE_BITS 3 5350 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_CNTRL_MODE_SHIFT 1 5351 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_CNTRL_MODE_DEFAULT 0x00000000 5352 5353 /* DDR34_E0_PHY_CONTROL_REGS :: PHYBIST_CNTRL :: ENABLE [00:00] */ 5354 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_CNTRL_ENABLE_MASK 0x00000001 5355 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_CNTRL_ENABLE_ALIGN 0 5356 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_CNTRL_ENABLE_BITS 1 5357 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_CNTRL_ENABLE_SHIFT 0 5358 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_CNTRL_ENABLE_DEFAULT 0x00000000 5359 5360 /*************************************************************************** 5361 *PHYBIST_SEED - PhyBist Seed Register 5362 */ 5363 /* DDR34_E0_PHY_CONTROL_REGS :: PHYBIST_SEED :: SEED [31:00] */ 5364 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_SEED_SEED_MASK 0xffffffff 5365 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_SEED_SEED_ALIGN 0 5366 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_SEED_SEED_BITS 32 5367 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_SEED_SEED_SHIFT 0 5368 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_SEED_SEED_DEFAULT 0xba5eba11 5369 5370 /*************************************************************************** 5371 *PHYBIST_STATUS - PhyBist General Status Register 5372 */ 5373 /* DDR34_E0_PHY_CONTROL_REGS :: PHYBIST_STATUS :: reserved0 [31:04] */ 5374 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_STATUS_RESERVED0_MASK 0xfffffff0 5375 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_STATUS_RESERVED0_ALIGN 0 5376 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_STATUS_RESERVED0_BITS 28 5377 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_STATUS_RESERVED0_SHIFT 4 5378 5379 /* DDR34_E0_PHY_CONTROL_REGS :: PHYBIST_STATUS :: DAT_PASS [03:03] */ 5380 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_STATUS_DAT_PASS_MASK 0x00000008 5381 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_STATUS_DAT_PASS_ALIGN 0 5382 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_STATUS_DAT_PASS_BITS 1 5383 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_STATUS_DAT_PASS_SHIFT 3 5384 5385 /* DDR34_E0_PHY_CONTROL_REGS :: PHYBIST_STATUS :: CTL_PASS [02:02] */ 5386 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_STATUS_CTL_PASS_MASK 0x00000004 5387 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_STATUS_CTL_PASS_ALIGN 0 5388 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_STATUS_CTL_PASS_BITS 1 5389 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_STATUS_CTL_PASS_SHIFT 2 5390 5391 /* DDR34_E0_PHY_CONTROL_REGS :: PHYBIST_STATUS :: DAT_DONE [01:01] */ 5392 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_STATUS_DAT_DONE_MASK 0x00000002 5393 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_STATUS_DAT_DONE_ALIGN 0 5394 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_STATUS_DAT_DONE_BITS 1 5395 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_STATUS_DAT_DONE_SHIFT 1 5396 5397 /* DDR34_E0_PHY_CONTROL_REGS :: PHYBIST_STATUS :: CTL_DONE [00:00] */ 5398 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_STATUS_CTL_DONE_MASK 0x00000001 5399 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_STATUS_CTL_DONE_ALIGN 0 5400 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_STATUS_CTL_DONE_BITS 1 5401 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_STATUS_CTL_DONE_SHIFT 0 5402 5403 /*************************************************************************** 5404 *PHYBIST_CTL_STATUS - PhyBist Per-Bit Control Pad Status Register 5405 */ 5406 /* DDR34_E0_PHY_CONTROL_REGS :: PHYBIST_CTL_STATUS :: reserved0 [31:31] */ 5407 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_CTL_STATUS_RESERVED0_MASK 0x80000000 5408 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_CTL_STATUS_RESERVED0_ALIGN 0 5409 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_CTL_STATUS_RESERVED0_BITS 1 5410 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_CTL_STATUS_RESERVED0_SHIFT 31 5411 5412 /* DDR34_E0_PHY_CONTROL_REGS :: PHYBIST_CTL_STATUS :: CTL_ERRORS [30:00] */ 5413 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_CTL_STATUS_CTL_ERRORS_MASK 0x7fffffff 5414 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_CTL_STATUS_CTL_ERRORS_ALIGN 0 5415 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_CTL_STATUS_CTL_ERRORS_BITS 31 5416 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_CTL_STATUS_CTL_ERRORS_SHIFT 0 5417 5418 /*************************************************************************** 5419 *PHYBIST_BL0_STATUS - PhyBist Byte Lane #0 Status Register 5420 */ 5421 /* DDR34_E0_PHY_CONTROL_REGS :: PHYBIST_BL0_STATUS :: reserved0 [31:10] */ 5422 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_BL0_STATUS_RESERVED0_MASK 0xfffffc00 5423 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_BL0_STATUS_RESERVED0_ALIGN 0 5424 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_BL0_STATUS_RESERVED0_BITS 22 5425 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_BL0_STATUS_RESERVED0_SHIFT 10 5426 5427 /* DDR34_E0_PHY_CONTROL_REGS :: PHYBIST_BL0_STATUS :: EDC [09:09] */ 5428 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_BL0_STATUS_EDC_MASK 0x00000200 5429 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_BL0_STATUS_EDC_ALIGN 0 5430 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_BL0_STATUS_EDC_BITS 1 5431 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_BL0_STATUS_EDC_SHIFT 9 5432 5433 /* DDR34_E0_PHY_CONTROL_REGS :: PHYBIST_BL0_STATUS :: DM [08:08] */ 5434 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_BL0_STATUS_DM_MASK 0x00000100 5435 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_BL0_STATUS_DM_ALIGN 0 5436 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_BL0_STATUS_DM_BITS 1 5437 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_BL0_STATUS_DM_SHIFT 8 5438 5439 /* DDR34_E0_PHY_CONTROL_REGS :: PHYBIST_BL0_STATUS :: DQ [07:00] */ 5440 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_BL0_STATUS_DQ_MASK 0x000000ff 5441 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_BL0_STATUS_DQ_ALIGN 0 5442 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_BL0_STATUS_DQ_BITS 8 5443 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_BL0_STATUS_DQ_SHIFT 0 5444 5445 /*************************************************************************** 5446 *PHYBIST_BL1_STATUS - PhyBist Byte Lane #1 Status Register 5447 */ 5448 /* DDR34_E0_PHY_CONTROL_REGS :: PHYBIST_BL1_STATUS :: reserved0 [31:10] */ 5449 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_BL1_STATUS_RESERVED0_MASK 0xfffffc00 5450 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_BL1_STATUS_RESERVED0_ALIGN 0 5451 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_BL1_STATUS_RESERVED0_BITS 22 5452 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_BL1_STATUS_RESERVED0_SHIFT 10 5453 5454 /* DDR34_E0_PHY_CONTROL_REGS :: PHYBIST_BL1_STATUS :: EDC [09:09] */ 5455 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_BL1_STATUS_EDC_MASK 0x00000200 5456 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_BL1_STATUS_EDC_ALIGN 0 5457 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_BL1_STATUS_EDC_BITS 1 5458 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_BL1_STATUS_EDC_SHIFT 9 5459 5460 /* DDR34_E0_PHY_CONTROL_REGS :: PHYBIST_BL1_STATUS :: DM [08:08] */ 5461 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_BL1_STATUS_DM_MASK 0x00000100 5462 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_BL1_STATUS_DM_ALIGN 0 5463 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_BL1_STATUS_DM_BITS 1 5464 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_BL1_STATUS_DM_SHIFT 8 5465 5466 /* DDR34_E0_PHY_CONTROL_REGS :: PHYBIST_BL1_STATUS :: DQ [07:00] */ 5467 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_BL1_STATUS_DQ_MASK 0x000000ff 5468 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_BL1_STATUS_DQ_ALIGN 0 5469 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_BL1_STATUS_DQ_BITS 8 5470 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_BL1_STATUS_DQ_SHIFT 0 5471 5472 /*************************************************************************** 5473 *PHYBIST_BL2_STATUS - PhyBist Byte Lane #2 Status Register 5474 */ 5475 /* DDR34_E0_PHY_CONTROL_REGS :: PHYBIST_BL2_STATUS :: reserved0 [31:10] */ 5476 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_BL2_STATUS_RESERVED0_MASK 0xfffffc00 5477 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_BL2_STATUS_RESERVED0_ALIGN 0 5478 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_BL2_STATUS_RESERVED0_BITS 22 5479 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_BL2_STATUS_RESERVED0_SHIFT 10 5480 5481 /* DDR34_E0_PHY_CONTROL_REGS :: PHYBIST_BL2_STATUS :: EDC [09:09] */ 5482 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_BL2_STATUS_EDC_MASK 0x00000200 5483 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_BL2_STATUS_EDC_ALIGN 0 5484 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_BL2_STATUS_EDC_BITS 1 5485 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_BL2_STATUS_EDC_SHIFT 9 5486 5487 /* DDR34_E0_PHY_CONTROL_REGS :: PHYBIST_BL2_STATUS :: DM [08:08] */ 5488 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_BL2_STATUS_DM_MASK 0x00000100 5489 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_BL2_STATUS_DM_ALIGN 0 5490 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_BL2_STATUS_DM_BITS 1 5491 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_BL2_STATUS_DM_SHIFT 8 5492 5493 /* DDR34_E0_PHY_CONTROL_REGS :: PHYBIST_BL2_STATUS :: DQ [07:00] */ 5494 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_BL2_STATUS_DQ_MASK 0x000000ff 5495 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_BL2_STATUS_DQ_ALIGN 0 5496 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_BL2_STATUS_DQ_BITS 8 5497 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_BL2_STATUS_DQ_SHIFT 0 5498 5499 /*************************************************************************** 5500 *PHYBIST_BL3_STATUS - PhyBist Byte Lane #3 Status Register 5501 */ 5502 /* DDR34_E0_PHY_CONTROL_REGS :: PHYBIST_BL3_STATUS :: reserved0 [31:10] */ 5503 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_BL3_STATUS_RESERVED0_MASK 0xfffffc00 5504 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_BL3_STATUS_RESERVED0_ALIGN 0 5505 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_BL3_STATUS_RESERVED0_BITS 22 5506 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_BL3_STATUS_RESERVED0_SHIFT 10 5507 5508 /* DDR34_E0_PHY_CONTROL_REGS :: PHYBIST_BL3_STATUS :: EDC [09:09] */ 5509 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_BL3_STATUS_EDC_MASK 0x00000200 5510 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_BL3_STATUS_EDC_ALIGN 0 5511 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_BL3_STATUS_EDC_BITS 1 5512 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_BL3_STATUS_EDC_SHIFT 9 5513 5514 /* DDR34_E0_PHY_CONTROL_REGS :: PHYBIST_BL3_STATUS :: DM [08:08] */ 5515 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_BL3_STATUS_DM_MASK 0x00000100 5516 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_BL3_STATUS_DM_ALIGN 0 5517 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_BL3_STATUS_DM_BITS 1 5518 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_BL3_STATUS_DM_SHIFT 8 5519 5520 /* DDR34_E0_PHY_CONTROL_REGS :: PHYBIST_BL3_STATUS :: DQ [07:00] */ 5521 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_BL3_STATUS_DQ_MASK 0x000000ff 5522 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_BL3_STATUS_DQ_ALIGN 0 5523 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_BL3_STATUS_DQ_BITS 8 5524 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_BL3_STATUS_DQ_SHIFT 0 5525 5526 /*************************************************************************** 5527 *PHYBIST_BL4_STATUS - PhyBist Byte Lane #4 (ECC) Status Register 5528 */ 5529 /* DDR34_E0_PHY_CONTROL_REGS :: PHYBIST_BL4_STATUS :: reserved0 [31:10] */ 5530 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_BL4_STATUS_RESERVED0_MASK 0xfffffc00 5531 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_BL4_STATUS_RESERVED0_ALIGN 0 5532 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_BL4_STATUS_RESERVED0_BITS 22 5533 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_BL4_STATUS_RESERVED0_SHIFT 10 5534 5535 /* DDR34_E0_PHY_CONTROL_REGS :: PHYBIST_BL4_STATUS :: EDC [09:09] */ 5536 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_BL4_STATUS_EDC_MASK 0x00000200 5537 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_BL4_STATUS_EDC_ALIGN 0 5538 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_BL4_STATUS_EDC_BITS 1 5539 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_BL4_STATUS_EDC_SHIFT 9 5540 5541 /* DDR34_E0_PHY_CONTROL_REGS :: PHYBIST_BL4_STATUS :: DM [08:08] */ 5542 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_BL4_STATUS_DM_MASK 0x00000100 5543 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_BL4_STATUS_DM_ALIGN 0 5544 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_BL4_STATUS_DM_BITS 1 5545 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_BL4_STATUS_DM_SHIFT 8 5546 5547 /* DDR34_E0_PHY_CONTROL_REGS :: PHYBIST_BL4_STATUS :: DQ [07:00] */ 5548 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_BL4_STATUS_DQ_MASK 0x000000ff 5549 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_BL4_STATUS_DQ_ALIGN 0 5550 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_BL4_STATUS_DQ_BITS 8 5551 #define DDR34_E0_PHY_CONTROL_REGS_PHYBIST_BL4_STATUS_DQ_SHIFT 0 5552 5553 /*************************************************************************** 5554 *STANDBY_CONTROL - Standby Control register 5555 */ 5556 /* DDR34_E0_PHY_CONTROL_REGS :: STANDBY_CONTROL :: reserved0 [31:23] */ 5557 #define DDR34_E0_PHY_CONTROL_REGS_STANDBY_CONTROL_RESERVED0_MASK 0xff800000 5558 #define DDR34_E0_PHY_CONTROL_REGS_STANDBY_CONTROL_RESERVED0_ALIGN 0 5559 #define DDR34_E0_PHY_CONTROL_REGS_STANDBY_CONTROL_RESERVED0_BITS 9 5560 #define DDR34_E0_PHY_CONTROL_REGS_STANDBY_CONTROL_RESERVED0_SHIFT 23 5561 5562 /* DDR34_E0_PHY_CONTROL_REGS :: STANDBY_CONTROL :: STANDBY_READY [22:22] */ 5563 #define DDR34_E0_PHY_CONTROL_REGS_STANDBY_CONTROL_STANDBY_READY_MASK 0x00400000 5564 #define DDR34_E0_PHY_CONTROL_REGS_STANDBY_CONTROL_STANDBY_READY_ALIGN 0 5565 #define DDR34_E0_PHY_CONTROL_REGS_STANDBY_CONTROL_STANDBY_READY_BITS 1 5566 #define DDR34_E0_PHY_CONTROL_REGS_STANDBY_CONTROL_STANDBY_READY_SHIFT 22 5567 #define DDR34_E0_PHY_CONTROL_REGS_STANDBY_CONTROL_STANDBY_READY_DEFAULT 0x00000000 5568 5569 /* DDR34_E0_PHY_CONTROL_REGS :: STANDBY_CONTROL :: STANDBY_EXIT_PIN_EN [21:21] */ 5570 #define DDR34_E0_PHY_CONTROL_REGS_STANDBY_CONTROL_STANDBY_EXIT_PIN_EN_MASK 0x00200000 5571 #define DDR34_E0_PHY_CONTROL_REGS_STANDBY_CONTROL_STANDBY_EXIT_PIN_EN_ALIGN 0 5572 #define DDR34_E0_PHY_CONTROL_REGS_STANDBY_CONTROL_STANDBY_EXIT_PIN_EN_BITS 1 5573 #define DDR34_E0_PHY_CONTROL_REGS_STANDBY_CONTROL_STANDBY_EXIT_PIN_EN_SHIFT 21 5574 #define DDR34_E0_PHY_CONTROL_REGS_STANDBY_CONTROL_STANDBY_EXIT_PIN_EN_DEFAULT 0x00000000 5575 5576 /* DDR34_E0_PHY_CONTROL_REGS :: STANDBY_CONTROL :: STANDBY_ACTIVE [20:20] */ 5577 #define DDR34_E0_PHY_CONTROL_REGS_STANDBY_CONTROL_STANDBY_ACTIVE_MASK 0x00100000 5578 #define DDR34_E0_PHY_CONTROL_REGS_STANDBY_CONTROL_STANDBY_ACTIVE_ALIGN 0 5579 #define DDR34_E0_PHY_CONTROL_REGS_STANDBY_CONTROL_STANDBY_ACTIVE_BITS 1 5580 #define DDR34_E0_PHY_CONTROL_REGS_STANDBY_CONTROL_STANDBY_ACTIVE_SHIFT 20 5581 #define DDR34_E0_PHY_CONTROL_REGS_STANDBY_CONTROL_STANDBY_ACTIVE_DEFAULT 0x00000000 5582 5583 /* DDR34_E0_PHY_CONTROL_REGS :: STANDBY_CONTROL :: ARMED [19:19] */ 5584 #define DDR34_E0_PHY_CONTROL_REGS_STANDBY_CONTROL_ARMED_MASK 0x00080000 5585 #define DDR34_E0_PHY_CONTROL_REGS_STANDBY_CONTROL_ARMED_ALIGN 0 5586 #define DDR34_E0_PHY_CONTROL_REGS_STANDBY_CONTROL_ARMED_BITS 1 5587 #define DDR34_E0_PHY_CONTROL_REGS_STANDBY_CONTROL_ARMED_SHIFT 19 5588 #define DDR34_E0_PHY_CONTROL_REGS_STANDBY_CONTROL_ARMED_DEFAULT 0x00000000 5589 5590 /* DDR34_E0_PHY_CONTROL_REGS :: STANDBY_CONTROL :: WARMSTART [18:18] */ 5591 #define DDR34_E0_PHY_CONTROL_REGS_STANDBY_CONTROL_WARMSTART_MASK 0x00040000 5592 #define DDR34_E0_PHY_CONTROL_REGS_STANDBY_CONTROL_WARMSTART_ALIGN 0 5593 #define DDR34_E0_PHY_CONTROL_REGS_STANDBY_CONTROL_WARMSTART_BITS 1 5594 #define DDR34_E0_PHY_CONTROL_REGS_STANDBY_CONTROL_WARMSTART_SHIFT 18 5595 #define DDR34_E0_PHY_CONTROL_REGS_STANDBY_CONTROL_WARMSTART_DEFAULT 0x00000000 5596 5597 /* DDR34_E0_PHY_CONTROL_REGS :: STANDBY_CONTROL :: PWRDOWN_LDO_BIAS [17:16] */ 5598 #define DDR34_E0_PHY_CONTROL_REGS_STANDBY_CONTROL_PWRDOWN_LDO_BIAS_MASK 0x00030000 5599 #define DDR34_E0_PHY_CONTROL_REGS_STANDBY_CONTROL_PWRDOWN_LDO_BIAS_ALIGN 0 5600 #define DDR34_E0_PHY_CONTROL_REGS_STANDBY_CONTROL_PWRDOWN_LDO_BIAS_BITS 2 5601 #define DDR34_E0_PHY_CONTROL_REGS_STANDBY_CONTROL_PWRDOWN_LDO_BIAS_SHIFT 16 5602 #define DDR34_E0_PHY_CONTROL_REGS_STANDBY_CONTROL_PWRDOWN_LDO_BIAS_DEFAULT 0x00000000 5603 5604 /* DDR34_E0_PHY_CONTROL_REGS :: STANDBY_CONTROL :: PWRDOWN_LDO_VOLTS [15:14] */ 5605 #define DDR34_E0_PHY_CONTROL_REGS_STANDBY_CONTROL_PWRDOWN_LDO_VOLTS_MASK 0x0000c000 5606 #define DDR34_E0_PHY_CONTROL_REGS_STANDBY_CONTROL_PWRDOWN_LDO_VOLTS_ALIGN 0 5607 #define DDR34_E0_PHY_CONTROL_REGS_STANDBY_CONTROL_PWRDOWN_LDO_VOLTS_BITS 2 5608 #define DDR34_E0_PHY_CONTROL_REGS_STANDBY_CONTROL_PWRDOWN_LDO_VOLTS_SHIFT 14 5609 #define DDR34_E0_PHY_CONTROL_REGS_STANDBY_CONTROL_PWRDOWN_LDO_VOLTS_DEFAULT 0x00000000 5610 5611 /* DDR34_E0_PHY_CONTROL_REGS :: STANDBY_CONTROL :: PWRDOWN_SKIP_MRS [13:13] */ 5612 #define DDR34_E0_PHY_CONTROL_REGS_STANDBY_CONTROL_PWRDOWN_SKIP_MRS_MASK 0x00002000 5613 #define DDR34_E0_PHY_CONTROL_REGS_STANDBY_CONTROL_PWRDOWN_SKIP_MRS_ALIGN 0 5614 #define DDR34_E0_PHY_CONTROL_REGS_STANDBY_CONTROL_PWRDOWN_SKIP_MRS_BITS 1 5615 #define DDR34_E0_PHY_CONTROL_REGS_STANDBY_CONTROL_PWRDOWN_SKIP_MRS_SHIFT 13 5616 #define DDR34_E0_PHY_CONTROL_REGS_STANDBY_CONTROL_PWRDOWN_SKIP_MRS_DEFAULT 0x00000000 5617 5618 /* DDR34_E0_PHY_CONTROL_REGS :: STANDBY_CONTROL :: PWRDOWN_RST_N [12:12] */ 5619 #define DDR34_E0_PHY_CONTROL_REGS_STANDBY_CONTROL_PWRDOWN_RST_N_MASK 0x00001000 5620 #define DDR34_E0_PHY_CONTROL_REGS_STANDBY_CONTROL_PWRDOWN_RST_N_ALIGN 0 5621 #define DDR34_E0_PHY_CONTROL_REGS_STANDBY_CONTROL_PWRDOWN_RST_N_BITS 1 5622 #define DDR34_E0_PHY_CONTROL_REGS_STANDBY_CONTROL_PWRDOWN_RST_N_SHIFT 12 5623 #define DDR34_E0_PHY_CONTROL_REGS_STANDBY_CONTROL_PWRDOWN_RST_N_DEFAULT 0x00000000 5624 5625 /* DDR34_E0_PHY_CONTROL_REGS :: STANDBY_CONTROL :: PWRDOWN_CKE [11:11] */ 5626 #define DDR34_E0_PHY_CONTROL_REGS_STANDBY_CONTROL_PWRDOWN_CKE_MASK 0x00000800 5627 #define DDR34_E0_PHY_CONTROL_REGS_STANDBY_CONTROL_PWRDOWN_CKE_ALIGN 0 5628 #define DDR34_E0_PHY_CONTROL_REGS_STANDBY_CONTROL_PWRDOWN_CKE_BITS 1 5629 #define DDR34_E0_PHY_CONTROL_REGS_STANDBY_CONTROL_PWRDOWN_CKE_SHIFT 11 5630 #define DDR34_E0_PHY_CONTROL_REGS_STANDBY_CONTROL_PWRDOWN_CKE_DEFAULT 0x00000000 5631 5632 /* DDR34_E0_PHY_CONTROL_REGS :: STANDBY_CONTROL :: LDO_BIAS [10:09] */ 5633 #define DDR34_E0_PHY_CONTROL_REGS_STANDBY_CONTROL_LDO_BIAS_MASK 0x00000600 5634 #define DDR34_E0_PHY_CONTROL_REGS_STANDBY_CONTROL_LDO_BIAS_ALIGN 0 5635 #define DDR34_E0_PHY_CONTROL_REGS_STANDBY_CONTROL_LDO_BIAS_BITS 2 5636 #define DDR34_E0_PHY_CONTROL_REGS_STANDBY_CONTROL_LDO_BIAS_SHIFT 9 5637 #define DDR34_E0_PHY_CONTROL_REGS_STANDBY_CONTROL_LDO_BIAS_DEFAULT 0x00000003 5638 5639 /* DDR34_E0_PHY_CONTROL_REGS :: STANDBY_CONTROL :: LDO_VOLTS [08:07] */ 5640 #define DDR34_E0_PHY_CONTROL_REGS_STANDBY_CONTROL_LDO_VOLTS_MASK 0x00000180 5641 #define DDR34_E0_PHY_CONTROL_REGS_STANDBY_CONTROL_LDO_VOLTS_ALIGN 0 5642 #define DDR34_E0_PHY_CONTROL_REGS_STANDBY_CONTROL_LDO_VOLTS_BITS 2 5643 #define DDR34_E0_PHY_CONTROL_REGS_STANDBY_CONTROL_LDO_VOLTS_SHIFT 7 5644 #define DDR34_E0_PHY_CONTROL_REGS_STANDBY_CONTROL_LDO_VOLTS_DEFAULT 0x00000003 5645 5646 /* DDR34_E0_PHY_CONTROL_REGS :: STANDBY_CONTROL :: SKIP_MRS [06:06] */ 5647 #define DDR34_E0_PHY_CONTROL_REGS_STANDBY_CONTROL_SKIP_MRS_MASK 0x00000040 5648 #define DDR34_E0_PHY_CONTROL_REGS_STANDBY_CONTROL_SKIP_MRS_ALIGN 0 5649 #define DDR34_E0_PHY_CONTROL_REGS_STANDBY_CONTROL_SKIP_MRS_BITS 1 5650 #define DDR34_E0_PHY_CONTROL_REGS_STANDBY_CONTROL_SKIP_MRS_SHIFT 6 5651 #define DDR34_E0_PHY_CONTROL_REGS_STANDBY_CONTROL_SKIP_MRS_DEFAULT 0x00000000 5652 5653 /* DDR34_E0_PHY_CONTROL_REGS :: STANDBY_CONTROL :: RST_N [05:05] */ 5654 #define DDR34_E0_PHY_CONTROL_REGS_STANDBY_CONTROL_RST_N_MASK 0x00000020 5655 #define DDR34_E0_PHY_CONTROL_REGS_STANDBY_CONTROL_RST_N_ALIGN 0 5656 #define DDR34_E0_PHY_CONTROL_REGS_STANDBY_CONTROL_RST_N_BITS 1 5657 #define DDR34_E0_PHY_CONTROL_REGS_STANDBY_CONTROL_RST_N_SHIFT 5 5658 #define DDR34_E0_PHY_CONTROL_REGS_STANDBY_CONTROL_RST_N_DEFAULT 0x00000000 5659 5660 /* DDR34_E0_PHY_CONTROL_REGS :: STANDBY_CONTROL :: CKE [04:04] */ 5661 #define DDR34_E0_PHY_CONTROL_REGS_STANDBY_CONTROL_CKE_MASK 0x00000010 5662 #define DDR34_E0_PHY_CONTROL_REGS_STANDBY_CONTROL_CKE_ALIGN 0 5663 #define DDR34_E0_PHY_CONTROL_REGS_STANDBY_CONTROL_CKE_BITS 1 5664 #define DDR34_E0_PHY_CONTROL_REGS_STANDBY_CONTROL_CKE_SHIFT 4 5665 #define DDR34_E0_PHY_CONTROL_REGS_STANDBY_CONTROL_CKE_DEFAULT 0x00000000 5666 5667 /* DDR34_E0_PHY_CONTROL_REGS :: STANDBY_CONTROL :: STANDBY [03:00] */ 5668 #define DDR34_E0_PHY_CONTROL_REGS_STANDBY_CONTROL_STANDBY_MASK 0x0000000f 5669 #define DDR34_E0_PHY_CONTROL_REGS_STANDBY_CONTROL_STANDBY_ALIGN 0 5670 #define DDR34_E0_PHY_CONTROL_REGS_STANDBY_CONTROL_STANDBY_BITS 4 5671 #define DDR34_E0_PHY_CONTROL_REGS_STANDBY_CONTROL_STANDBY_SHIFT 0 5672 #define DDR34_E0_PHY_CONTROL_REGS_STANDBY_CONTROL_STANDBY_DEFAULT 0x00000000 5673 5674 /*************************************************************************** 5675 *DEBUG_FREEZE_ENABLE - Freeze-on-error enable register 5676 */ 5677 /* DDR34_E0_PHY_CONTROL_REGS :: DEBUG_FREEZE_ENABLE :: reserved0 [31:05] */ 5678 #define DDR34_E0_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE_RESERVED0_MASK 0xffffffe0 5679 #define DDR34_E0_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE_RESERVED0_ALIGN 0 5680 #define DDR34_E0_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE_RESERVED0_BITS 27 5681 #define DDR34_E0_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE_RESERVED0_SHIFT 5 5682 5683 /* DDR34_E0_PHY_CONTROL_REGS :: DEBUG_FREEZE_ENABLE :: WLECC [04:04] */ 5684 #define DDR34_E0_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE_WLECC_MASK 0x00000010 5685 #define DDR34_E0_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE_WLECC_ALIGN 0 5686 #define DDR34_E0_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE_WLECC_BITS 1 5687 #define DDR34_E0_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE_WLECC_SHIFT 4 5688 #define DDR34_E0_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE_WLECC_DEFAULT 0x00000000 5689 5690 /* DDR34_E0_PHY_CONTROL_REGS :: DEBUG_FREEZE_ENABLE :: WL1_BL1 [03:03] */ 5691 #define DDR34_E0_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE_WL1_BL1_MASK 0x00000008 5692 #define DDR34_E0_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE_WL1_BL1_ALIGN 0 5693 #define DDR34_E0_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE_WL1_BL1_BITS 1 5694 #define DDR34_E0_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE_WL1_BL1_SHIFT 3 5695 #define DDR34_E0_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE_WL1_BL1_DEFAULT 0x00000000 5696 5697 /* DDR34_E0_PHY_CONTROL_REGS :: DEBUG_FREEZE_ENABLE :: WL1_BL0 [02:02] */ 5698 #define DDR34_E0_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE_WL1_BL0_MASK 0x00000004 5699 #define DDR34_E0_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE_WL1_BL0_ALIGN 0 5700 #define DDR34_E0_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE_WL1_BL0_BITS 1 5701 #define DDR34_E0_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE_WL1_BL0_SHIFT 2 5702 #define DDR34_E0_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE_WL1_BL0_DEFAULT 0x00000000 5703 5704 /* DDR34_E0_PHY_CONTROL_REGS :: DEBUG_FREEZE_ENABLE :: WL0_BL1 [01:01] */ 5705 #define DDR34_E0_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE_WL0_BL1_MASK 0x00000002 5706 #define DDR34_E0_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE_WL0_BL1_ALIGN 0 5707 #define DDR34_E0_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE_WL0_BL1_BITS 1 5708 #define DDR34_E0_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE_WL0_BL1_SHIFT 1 5709 #define DDR34_E0_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE_WL0_BL1_DEFAULT 0x00000000 5710 5711 /* DDR34_E0_PHY_CONTROL_REGS :: DEBUG_FREEZE_ENABLE :: WL0_BL0 [00:00] */ 5712 #define DDR34_E0_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE_WL0_BL0_MASK 0x00000001 5713 #define DDR34_E0_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE_WL0_BL0_ALIGN 0 5714 #define DDR34_E0_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE_WL0_BL0_BITS 1 5715 #define DDR34_E0_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE_WL0_BL0_SHIFT 0 5716 #define DDR34_E0_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE_WL0_BL0_DEFAULT 0x00000000 5717 5718 /*************************************************************************** 5719 *DEBUG_MUX_CONTROL - Debug Mux Control register 5720 */ 5721 /* DDR34_E0_PHY_CONTROL_REGS :: DEBUG_MUX_CONTROL :: reserved0 [31:11] */ 5722 #define DDR34_E0_PHY_CONTROL_REGS_DEBUG_MUX_CONTROL_RESERVED0_MASK 0xfffff800 5723 #define DDR34_E0_PHY_CONTROL_REGS_DEBUG_MUX_CONTROL_RESERVED0_ALIGN 0 5724 #define DDR34_E0_PHY_CONTROL_REGS_DEBUG_MUX_CONTROL_RESERVED0_BITS 21 5725 #define DDR34_E0_PHY_CONTROL_REGS_DEBUG_MUX_CONTROL_RESERVED0_SHIFT 11 5726 5727 /* DDR34_E0_PHY_CONTROL_REGS :: DEBUG_MUX_CONTROL :: BYTE_SEL [10:08] */ 5728 #define DDR34_E0_PHY_CONTROL_REGS_DEBUG_MUX_CONTROL_BYTE_SEL_MASK 0x00000700 5729 #define DDR34_E0_PHY_CONTROL_REGS_DEBUG_MUX_CONTROL_BYTE_SEL_ALIGN 0 5730 #define DDR34_E0_PHY_CONTROL_REGS_DEBUG_MUX_CONTROL_BYTE_SEL_BITS 3 5731 #define DDR34_E0_PHY_CONTROL_REGS_DEBUG_MUX_CONTROL_BYTE_SEL_SHIFT 8 5732 #define DDR34_E0_PHY_CONTROL_REGS_DEBUG_MUX_CONTROL_BYTE_SEL_DEFAULT 0x00000000 5733 5734 /* DDR34_E0_PHY_CONTROL_REGS :: DEBUG_MUX_CONTROL :: reserved1 [07:06] */ 5735 #define DDR34_E0_PHY_CONTROL_REGS_DEBUG_MUX_CONTROL_RESERVED1_MASK 0x000000c0 5736 #define DDR34_E0_PHY_CONTROL_REGS_DEBUG_MUX_CONTROL_RESERVED1_ALIGN 0 5737 #define DDR34_E0_PHY_CONTROL_REGS_DEBUG_MUX_CONTROL_RESERVED1_BITS 2 5738 #define DDR34_E0_PHY_CONTROL_REGS_DEBUG_MUX_CONTROL_RESERVED1_SHIFT 6 5739 5740 /* DDR34_E0_PHY_CONTROL_REGS :: DEBUG_MUX_CONTROL :: PHASE_SEL [05:04] */ 5741 #define DDR34_E0_PHY_CONTROL_REGS_DEBUG_MUX_CONTROL_PHASE_SEL_MASK 0x00000030 5742 #define DDR34_E0_PHY_CONTROL_REGS_DEBUG_MUX_CONTROL_PHASE_SEL_ALIGN 0 5743 #define DDR34_E0_PHY_CONTROL_REGS_DEBUG_MUX_CONTROL_PHASE_SEL_BITS 2 5744 #define DDR34_E0_PHY_CONTROL_REGS_DEBUG_MUX_CONTROL_PHASE_SEL_SHIFT 4 5745 #define DDR34_E0_PHY_CONTROL_REGS_DEBUG_MUX_CONTROL_PHASE_SEL_DEFAULT 0x00000000 5746 5747 /* DDR34_E0_PHY_CONTROL_REGS :: DEBUG_MUX_CONTROL :: SOURCE_SEL [03:00] */ 5748 #define DDR34_E0_PHY_CONTROL_REGS_DEBUG_MUX_CONTROL_SOURCE_SEL_MASK 0x0000000f 5749 #define DDR34_E0_PHY_CONTROL_REGS_DEBUG_MUX_CONTROL_SOURCE_SEL_ALIGN 0 5750 #define DDR34_E0_PHY_CONTROL_REGS_DEBUG_MUX_CONTROL_SOURCE_SEL_BITS 4 5751 #define DDR34_E0_PHY_CONTROL_REGS_DEBUG_MUX_CONTROL_SOURCE_SEL_SHIFT 0 5752 #define DDR34_E0_PHY_CONTROL_REGS_DEBUG_MUX_CONTROL_SOURCE_SEL_DEFAULT 0x00000000 5753 5754 /*************************************************************************** 5755 *DFI_CNTRL - DFI Interface Ownership Control register 5756 */ 5757 /* DDR34_E0_PHY_CONTROL_REGS :: DFI_CNTRL :: reserved0 [31:07] */ 5758 #define DDR34_E0_PHY_CONTROL_REGS_DFI_CNTRL_RESERVED0_MASK 0xffffff80 5759 #define DDR34_E0_PHY_CONTROL_REGS_DFI_CNTRL_RESERVED0_ALIGN 0 5760 #define DDR34_E0_PHY_CONTROL_REGS_DFI_CNTRL_RESERVED0_BITS 25 5761 #define DDR34_E0_PHY_CONTROL_REGS_DFI_CNTRL_RESERVED0_SHIFT 7 5762 5763 /* DDR34_E0_PHY_CONTROL_REGS :: DFI_CNTRL :: DFI_CS1 [06:06] */ 5764 #define DDR34_E0_PHY_CONTROL_REGS_DFI_CNTRL_DFI_CS1_MASK 0x00000040 5765 #define DDR34_E0_PHY_CONTROL_REGS_DFI_CNTRL_DFI_CS1_ALIGN 0 5766 #define DDR34_E0_PHY_CONTROL_REGS_DFI_CNTRL_DFI_CS1_BITS 1 5767 #define DDR34_E0_PHY_CONTROL_REGS_DFI_CNTRL_DFI_CS1_SHIFT 6 5768 #define DDR34_E0_PHY_CONTROL_REGS_DFI_CNTRL_DFI_CS1_DEFAULT 0x00000001 5769 5770 /* DDR34_E0_PHY_CONTROL_REGS :: DFI_CNTRL :: DFI_CS0 [05:05] */ 5771 #define DDR34_E0_PHY_CONTROL_REGS_DFI_CNTRL_DFI_CS0_MASK 0x00000020 5772 #define DDR34_E0_PHY_CONTROL_REGS_DFI_CNTRL_DFI_CS0_ALIGN 0 5773 #define DDR34_E0_PHY_CONTROL_REGS_DFI_CNTRL_DFI_CS0_BITS 1 5774 #define DDR34_E0_PHY_CONTROL_REGS_DFI_CNTRL_DFI_CS0_SHIFT 5 5775 #define DDR34_E0_PHY_CONTROL_REGS_DFI_CNTRL_DFI_CS0_DEFAULT 0x00000001 5776 5777 /* DDR34_E0_PHY_CONTROL_REGS :: DFI_CNTRL :: DFI_RST_N [04:04] */ 5778 #define DDR34_E0_PHY_CONTROL_REGS_DFI_CNTRL_DFI_RST_N_MASK 0x00000010 5779 #define DDR34_E0_PHY_CONTROL_REGS_DFI_CNTRL_DFI_RST_N_ALIGN 0 5780 #define DDR34_E0_PHY_CONTROL_REGS_DFI_CNTRL_DFI_RST_N_BITS 1 5781 #define DDR34_E0_PHY_CONTROL_REGS_DFI_CNTRL_DFI_RST_N_SHIFT 4 5782 #define DDR34_E0_PHY_CONTROL_REGS_DFI_CNTRL_DFI_RST_N_DEFAULT 0x00000001 5783 5784 /* DDR34_E0_PHY_CONTROL_REGS :: DFI_CNTRL :: DFI_CKE [03:03] */ 5785 #define DDR34_E0_PHY_CONTROL_REGS_DFI_CNTRL_DFI_CKE_MASK 0x00000008 5786 #define DDR34_E0_PHY_CONTROL_REGS_DFI_CNTRL_DFI_CKE_ALIGN 0 5787 #define DDR34_E0_PHY_CONTROL_REGS_DFI_CNTRL_DFI_CKE_BITS 1 5788 #define DDR34_E0_PHY_CONTROL_REGS_DFI_CNTRL_DFI_CKE_SHIFT 3 5789 #define DDR34_E0_PHY_CONTROL_REGS_DFI_CNTRL_DFI_CKE_DEFAULT 0x00000000 5790 5791 /* DDR34_E0_PHY_CONTROL_REGS :: DFI_CNTRL :: ACK_ENABLE [02:02] */ 5792 #define DDR34_E0_PHY_CONTROL_REGS_DFI_CNTRL_ACK_ENABLE_MASK 0x00000004 5793 #define DDR34_E0_PHY_CONTROL_REGS_DFI_CNTRL_ACK_ENABLE_ALIGN 0 5794 #define DDR34_E0_PHY_CONTROL_REGS_DFI_CNTRL_ACK_ENABLE_BITS 1 5795 #define DDR34_E0_PHY_CONTROL_REGS_DFI_CNTRL_ACK_ENABLE_SHIFT 2 5796 #define DDR34_E0_PHY_CONTROL_REGS_DFI_CNTRL_ACK_ENABLE_DEFAULT 0x00000000 5797 5798 /* DDR34_E0_PHY_CONTROL_REGS :: DFI_CNTRL :: ACK_STATUS [01:01] */ 5799 #define DDR34_E0_PHY_CONTROL_REGS_DFI_CNTRL_ACK_STATUS_MASK 0x00000002 5800 #define DDR34_E0_PHY_CONTROL_REGS_DFI_CNTRL_ACK_STATUS_ALIGN 0 5801 #define DDR34_E0_PHY_CONTROL_REGS_DFI_CNTRL_ACK_STATUS_BITS 1 5802 #define DDR34_E0_PHY_CONTROL_REGS_DFI_CNTRL_ACK_STATUS_SHIFT 1 5803 #define DDR34_E0_PHY_CONTROL_REGS_DFI_CNTRL_ACK_STATUS_DEFAULT 0x00000000 5804 5805 /* DDR34_E0_PHY_CONTROL_REGS :: DFI_CNTRL :: ASSERT_REQ [00:00] */ 5806 #define DDR34_E0_PHY_CONTROL_REGS_DFI_CNTRL_ASSERT_REQ_MASK 0x00000001 5807 #define DDR34_E0_PHY_CONTROL_REGS_DFI_CNTRL_ASSERT_REQ_ALIGN 0 5808 #define DDR34_E0_PHY_CONTROL_REGS_DFI_CNTRL_ASSERT_REQ_BITS 1 5809 #define DDR34_E0_PHY_CONTROL_REGS_DFI_CNTRL_ASSERT_REQ_SHIFT 0 5810 #define DDR34_E0_PHY_CONTROL_REGS_DFI_CNTRL_ASSERT_REQ_DEFAULT 0x00000001 5811 5812 /*************************************************************************** 5813 *WRITE_ODT_CNTRL - Write ODT Control register 5814 */ 5815 /* DDR34_E0_PHY_CONTROL_REGS :: WRITE_ODT_CNTRL :: reserved0 [31:13] */ 5816 #define DDR34_E0_PHY_CONTROL_REGS_WRITE_ODT_CNTRL_RESERVED0_MASK 0xffffe000 5817 #define DDR34_E0_PHY_CONTROL_REGS_WRITE_ODT_CNTRL_RESERVED0_ALIGN 0 5818 #define DDR34_E0_PHY_CONTROL_REGS_WRITE_ODT_CNTRL_RESERVED0_BITS 19 5819 #define DDR34_E0_PHY_CONTROL_REGS_WRITE_ODT_CNTRL_RESERVED0_SHIFT 13 5820 5821 /* DDR34_E0_PHY_CONTROL_REGS :: WRITE_ODT_CNTRL :: ODT_FORCE_VALUE [12:12] */ 5822 #define DDR34_E0_PHY_CONTROL_REGS_WRITE_ODT_CNTRL_ODT_FORCE_VALUE_MASK 0x00001000 5823 #define DDR34_E0_PHY_CONTROL_REGS_WRITE_ODT_CNTRL_ODT_FORCE_VALUE_ALIGN 0 5824 #define DDR34_E0_PHY_CONTROL_REGS_WRITE_ODT_CNTRL_ODT_FORCE_VALUE_BITS 1 5825 #define DDR34_E0_PHY_CONTROL_REGS_WRITE_ODT_CNTRL_ODT_FORCE_VALUE_SHIFT 12 5826 #define DDR34_E0_PHY_CONTROL_REGS_WRITE_ODT_CNTRL_ODT_FORCE_VALUE_DEFAULT 0x00000000 5827 5828 /* DDR34_E0_PHY_CONTROL_REGS :: WRITE_ODT_CNTRL :: ODT_FORCE [11:11] */ 5829 #define DDR34_E0_PHY_CONTROL_REGS_WRITE_ODT_CNTRL_ODT_FORCE_MASK 0x00000800 5830 #define DDR34_E0_PHY_CONTROL_REGS_WRITE_ODT_CNTRL_ODT_FORCE_ALIGN 0 5831 #define DDR34_E0_PHY_CONTROL_REGS_WRITE_ODT_CNTRL_ODT_FORCE_BITS 1 5832 #define DDR34_E0_PHY_CONTROL_REGS_WRITE_ODT_CNTRL_ODT_FORCE_SHIFT 11 5833 #define DDR34_E0_PHY_CONTROL_REGS_WRITE_ODT_CNTRL_ODT_FORCE_DEFAULT 0x00000001 5834 5835 /* DDR34_E0_PHY_CONTROL_REGS :: WRITE_ODT_CNTRL :: ODT_ENABLE [10:10] */ 5836 #define DDR34_E0_PHY_CONTROL_REGS_WRITE_ODT_CNTRL_ODT_ENABLE_MASK 0x00000400 5837 #define DDR34_E0_PHY_CONTROL_REGS_WRITE_ODT_CNTRL_ODT_ENABLE_ALIGN 0 5838 #define DDR34_E0_PHY_CONTROL_REGS_WRITE_ODT_CNTRL_ODT_ENABLE_BITS 1 5839 #define DDR34_E0_PHY_CONTROL_REGS_WRITE_ODT_CNTRL_ODT_ENABLE_SHIFT 10 5840 #define DDR34_E0_PHY_CONTROL_REGS_WRITE_ODT_CNTRL_ODT_ENABLE_DEFAULT 0x00000000 5841 5842 /* DDR34_E0_PHY_CONTROL_REGS :: WRITE_ODT_CNTRL :: ODT_LENGTH [09:06] */ 5843 #define DDR34_E0_PHY_CONTROL_REGS_WRITE_ODT_CNTRL_ODT_LENGTH_MASK 0x000003c0 5844 #define DDR34_E0_PHY_CONTROL_REGS_WRITE_ODT_CNTRL_ODT_LENGTH_ALIGN 0 5845 #define DDR34_E0_PHY_CONTROL_REGS_WRITE_ODT_CNTRL_ODT_LENGTH_BITS 4 5846 #define DDR34_E0_PHY_CONTROL_REGS_WRITE_ODT_CNTRL_ODT_LENGTH_SHIFT 6 5847 #define DDR34_E0_PHY_CONTROL_REGS_WRITE_ODT_CNTRL_ODT_LENGTH_DEFAULT 0x00000004 5848 5849 /* DDR34_E0_PHY_CONTROL_REGS :: WRITE_ODT_CNTRL :: ODT_DELAY [05:00] */ 5850 #define DDR34_E0_PHY_CONTROL_REGS_WRITE_ODT_CNTRL_ODT_DELAY_MASK 0x0000003f 5851 #define DDR34_E0_PHY_CONTROL_REGS_WRITE_ODT_CNTRL_ODT_DELAY_ALIGN 0 5852 #define DDR34_E0_PHY_CONTROL_REGS_WRITE_ODT_CNTRL_ODT_DELAY_BITS 6 5853 #define DDR34_E0_PHY_CONTROL_REGS_WRITE_ODT_CNTRL_ODT_DELAY_SHIFT 0 5854 #define DDR34_E0_PHY_CONTROL_REGS_WRITE_ODT_CNTRL_ODT_DELAY_DEFAULT 0x00000010 5855 5856 /*************************************************************************** 5857 *ABI_PAR_CNTRL - ABI and PAR Control register 5858 */ 5859 /* DDR34_E0_PHY_CONTROL_REGS :: ABI_PAR_CNTRL :: reserved0 [31:04] */ 5860 #define DDR34_E0_PHY_CONTROL_REGS_ABI_PAR_CNTRL_RESERVED0_MASK 0xfffffff0 5861 #define DDR34_E0_PHY_CONTROL_REGS_ABI_PAR_CNTRL_RESERVED0_ALIGN 0 5862 #define DDR34_E0_PHY_CONTROL_REGS_ABI_PAR_CNTRL_RESERVED0_BITS 28 5863 #define DDR34_E0_PHY_CONTROL_REGS_ABI_PAR_CNTRL_RESERVED0_SHIFT 4 5864 5865 /* DDR34_E0_PHY_CONTROL_REGS :: ABI_PAR_CNTRL :: PAR_INCLUDE_AUX [03:03] */ 5866 #define DDR34_E0_PHY_CONTROL_REGS_ABI_PAR_CNTRL_PAR_INCLUDE_AUX_MASK 0x00000008 5867 #define DDR34_E0_PHY_CONTROL_REGS_ABI_PAR_CNTRL_PAR_INCLUDE_AUX_ALIGN 0 5868 #define DDR34_E0_PHY_CONTROL_REGS_ABI_PAR_CNTRL_PAR_INCLUDE_AUX_BITS 1 5869 #define DDR34_E0_PHY_CONTROL_REGS_ABI_PAR_CNTRL_PAR_INCLUDE_AUX_SHIFT 3 5870 #define DDR34_E0_PHY_CONTROL_REGS_ABI_PAR_CNTRL_PAR_INCLUDE_AUX_DEFAULT 0x00000000 5871 5872 /* DDR34_E0_PHY_CONTROL_REGS :: ABI_PAR_CNTRL :: PAR_ENABLE [02:02] */ 5873 #define DDR34_E0_PHY_CONTROL_REGS_ABI_PAR_CNTRL_PAR_ENABLE_MASK 0x00000004 5874 #define DDR34_E0_PHY_CONTROL_REGS_ABI_PAR_CNTRL_PAR_ENABLE_ALIGN 0 5875 #define DDR34_E0_PHY_CONTROL_REGS_ABI_PAR_CNTRL_PAR_ENABLE_BITS 1 5876 #define DDR34_E0_PHY_CONTROL_REGS_ABI_PAR_CNTRL_PAR_ENABLE_SHIFT 2 5877 #define DDR34_E0_PHY_CONTROL_REGS_ABI_PAR_CNTRL_PAR_ENABLE_DEFAULT 0x00000000 5878 5879 /* DDR34_E0_PHY_CONTROL_REGS :: ABI_PAR_CNTRL :: ABI_INCLUDE_AUX [01:01] */ 5880 #define DDR34_E0_PHY_CONTROL_REGS_ABI_PAR_CNTRL_ABI_INCLUDE_AUX_MASK 0x00000002 5881 #define DDR34_E0_PHY_CONTROL_REGS_ABI_PAR_CNTRL_ABI_INCLUDE_AUX_ALIGN 0 5882 #define DDR34_E0_PHY_CONTROL_REGS_ABI_PAR_CNTRL_ABI_INCLUDE_AUX_BITS 1 5883 #define DDR34_E0_PHY_CONTROL_REGS_ABI_PAR_CNTRL_ABI_INCLUDE_AUX_SHIFT 1 5884 #define DDR34_E0_PHY_CONTROL_REGS_ABI_PAR_CNTRL_ABI_INCLUDE_AUX_DEFAULT 0x00000000 5885 5886 /* DDR34_E0_PHY_CONTROL_REGS :: ABI_PAR_CNTRL :: ABI_ENABLE [00:00] */ 5887 #define DDR34_E0_PHY_CONTROL_REGS_ABI_PAR_CNTRL_ABI_ENABLE_MASK 0x00000001 5888 #define DDR34_E0_PHY_CONTROL_REGS_ABI_PAR_CNTRL_ABI_ENABLE_ALIGN 0 5889 #define DDR34_E0_PHY_CONTROL_REGS_ABI_PAR_CNTRL_ABI_ENABLE_BITS 1 5890 #define DDR34_E0_PHY_CONTROL_REGS_ABI_PAR_CNTRL_ABI_ENABLE_SHIFT 0 5891 #define DDR34_E0_PHY_CONTROL_REGS_ABI_PAR_CNTRL_ABI_ENABLE_DEFAULT 0x00000000 5892 5893 /*************************************************************************** 5894 *ZQ_CAL - ZQ Calibration Control register 5895 */ 5896 /* DDR34_E0_PHY_CONTROL_REGS :: ZQ_CAL :: reserved0 [31:20] */ 5897 #define DDR34_E0_PHY_CONTROL_REGS_ZQ_CAL_RESERVED0_MASK 0xfff00000 5898 #define DDR34_E0_PHY_CONTROL_REGS_ZQ_CAL_RESERVED0_ALIGN 0 5899 #define DDR34_E0_PHY_CONTROL_REGS_ZQ_CAL_RESERVED0_BITS 12 5900 #define DDR34_E0_PHY_CONTROL_REGS_ZQ_CAL_RESERVED0_SHIFT 20 5901 5902 /* DDR34_E0_PHY_CONTROL_REGS :: ZQ_CAL :: ZQ_PCOMP_STATUS [19:19] */ 5903 #define DDR34_E0_PHY_CONTROL_REGS_ZQ_CAL_ZQ_PCOMP_STATUS_MASK 0x00080000 5904 #define DDR34_E0_PHY_CONTROL_REGS_ZQ_CAL_ZQ_PCOMP_STATUS_ALIGN 0 5905 #define DDR34_E0_PHY_CONTROL_REGS_ZQ_CAL_ZQ_PCOMP_STATUS_BITS 1 5906 #define DDR34_E0_PHY_CONTROL_REGS_ZQ_CAL_ZQ_PCOMP_STATUS_SHIFT 19 5907 #define DDR34_E0_PHY_CONTROL_REGS_ZQ_CAL_ZQ_PCOMP_STATUS_DEFAULT 0x00000000 5908 5909 /* DDR34_E0_PHY_CONTROL_REGS :: ZQ_CAL :: ZQ_NCOMP_STATUS [18:18] */ 5910 #define DDR34_E0_PHY_CONTROL_REGS_ZQ_CAL_ZQ_NCOMP_STATUS_MASK 0x00040000 5911 #define DDR34_E0_PHY_CONTROL_REGS_ZQ_CAL_ZQ_NCOMP_STATUS_ALIGN 0 5912 #define DDR34_E0_PHY_CONTROL_REGS_ZQ_CAL_ZQ_NCOMP_STATUS_BITS 1 5913 #define DDR34_E0_PHY_CONTROL_REGS_ZQ_CAL_ZQ_NCOMP_STATUS_SHIFT 18 5914 #define DDR34_E0_PHY_CONTROL_REGS_ZQ_CAL_ZQ_NCOMP_STATUS_DEFAULT 0x00000000 5915 5916 /* DDR34_E0_PHY_CONTROL_REGS :: ZQ_CAL :: ZQ_IDDQ [17:17] */ 5917 #define DDR34_E0_PHY_CONTROL_REGS_ZQ_CAL_ZQ_IDDQ_MASK 0x00020000 5918 #define DDR34_E0_PHY_CONTROL_REGS_ZQ_CAL_ZQ_IDDQ_ALIGN 0 5919 #define DDR34_E0_PHY_CONTROL_REGS_ZQ_CAL_ZQ_IDDQ_BITS 1 5920 #define DDR34_E0_PHY_CONTROL_REGS_ZQ_CAL_ZQ_IDDQ_SHIFT 17 5921 #define DDR34_E0_PHY_CONTROL_REGS_ZQ_CAL_ZQ_IDDQ_DEFAULT 0x00000001 5922 5923 /* DDR34_E0_PHY_CONTROL_REGS :: ZQ_CAL :: ZQ_DRIVE_P [16:12] */ 5924 #define DDR34_E0_PHY_CONTROL_REGS_ZQ_CAL_ZQ_DRIVE_P_MASK 0x0001f000 5925 #define DDR34_E0_PHY_CONTROL_REGS_ZQ_CAL_ZQ_DRIVE_P_ALIGN 0 5926 #define DDR34_E0_PHY_CONTROL_REGS_ZQ_CAL_ZQ_DRIVE_P_BITS 5 5927 #define DDR34_E0_PHY_CONTROL_REGS_ZQ_CAL_ZQ_DRIVE_P_SHIFT 12 5928 #define DDR34_E0_PHY_CONTROL_REGS_ZQ_CAL_ZQ_DRIVE_P_DEFAULT 0x00000000 5929 5930 /* DDR34_E0_PHY_CONTROL_REGS :: ZQ_CAL :: ZQ_DRIVE_N [11:07] */ 5931 #define DDR34_E0_PHY_CONTROL_REGS_ZQ_CAL_ZQ_DRIVE_N_MASK 0x00000f80 5932 #define DDR34_E0_PHY_CONTROL_REGS_ZQ_CAL_ZQ_DRIVE_N_ALIGN 0 5933 #define DDR34_E0_PHY_CONTROL_REGS_ZQ_CAL_ZQ_DRIVE_N_BITS 5 5934 #define DDR34_E0_PHY_CONTROL_REGS_ZQ_CAL_ZQ_DRIVE_N_SHIFT 7 5935 #define DDR34_E0_PHY_CONTROL_REGS_ZQ_CAL_ZQ_DRIVE_N_DEFAULT 0x00000000 5936 5937 /* DDR34_E0_PHY_CONTROL_REGS :: ZQ_CAL :: reserved_for_padding1 [06:02] */ 5938 #define DDR34_E0_PHY_CONTROL_REGS_ZQ_CAL_RESERVED_for_padding1_MASK 0x0000007c 5939 #define DDR34_E0_PHY_CONTROL_REGS_ZQ_CAL_RESERVED_for_padding1_ALIGN 0 5940 #define DDR34_E0_PHY_CONTROL_REGS_ZQ_CAL_RESERVED_for_padding1_BITS 5 5941 #define DDR34_E0_PHY_CONTROL_REGS_ZQ_CAL_RESERVED_for_padding1_SHIFT 2 5942 5943 /* DDR34_E0_PHY_CONTROL_REGS :: ZQ_CAL :: ZQ_PCOMP_ENB [01:01] */ 5944 #define DDR34_E0_PHY_CONTROL_REGS_ZQ_CAL_ZQ_PCOMP_ENB_MASK 0x00000002 5945 #define DDR34_E0_PHY_CONTROL_REGS_ZQ_CAL_ZQ_PCOMP_ENB_ALIGN 0 5946 #define DDR34_E0_PHY_CONTROL_REGS_ZQ_CAL_ZQ_PCOMP_ENB_BITS 1 5947 #define DDR34_E0_PHY_CONTROL_REGS_ZQ_CAL_ZQ_PCOMP_ENB_SHIFT 1 5948 #define DDR34_E0_PHY_CONTROL_REGS_ZQ_CAL_ZQ_PCOMP_ENB_DEFAULT 0x00000001 5949 5950 /* DDR34_E0_PHY_CONTROL_REGS :: ZQ_CAL :: ZQ_NCOMP_ENB [00:00] */ 5951 #define DDR34_E0_PHY_CONTROL_REGS_ZQ_CAL_ZQ_NCOMP_ENB_MASK 0x00000001 5952 #define DDR34_E0_PHY_CONTROL_REGS_ZQ_CAL_ZQ_NCOMP_ENB_ALIGN 0 5953 #define DDR34_E0_PHY_CONTROL_REGS_ZQ_CAL_ZQ_NCOMP_ENB_BITS 1 5954 #define DDR34_E0_PHY_CONTROL_REGS_ZQ_CAL_ZQ_NCOMP_ENB_SHIFT 0 5955 #define DDR34_E0_PHY_CONTROL_REGS_ZQ_CAL_ZQ_NCOMP_ENB_DEFAULT 0x00000001 5956 5957 /*************************************************************************** 5958 *AC_SPARE_REG - Address and Control Spare register 5959 */ 5960 /* DDR34_E0_PHY_CONTROL_REGS :: AC_SPARE_REG :: reserved_for_eco0 [31:00] */ 5961 #define DDR34_E0_PHY_CONTROL_REGS_AC_SPARE_REG_RESERVED_for_eco0_MASK 0xffffffff 5962 #define DDR34_E0_PHY_CONTROL_REGS_AC_SPARE_REG_RESERVED_for_eco0_ALIGN 0 5963 #define DDR34_E0_PHY_CONTROL_REGS_AC_SPARE_REG_RESERVED_for_eco0_BITS 32 5964 #define DDR34_E0_PHY_CONTROL_REGS_AC_SPARE_REG_RESERVED_for_eco0_SHIFT 0 5965 #define DDR34_E0_PHY_CONTROL_REGS_AC_SPARE_REG_RESERVED_for_eco0_DEFAULT 0x00000000 5966 5967 /*************************************************************************** 5968 *VDL_CONTROL_WR_DQS_P - Write channel DQS-P VDL control register 5969 */ 5970 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQS_P :: BUSY [31:31] */ 5971 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_P_BUSY_MASK 0x80000000 5972 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_P_BUSY_ALIGN 0 5973 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_P_BUSY_BITS 1 5974 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_P_BUSY_SHIFT 31 5975 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_P_BUSY_DEFAULT 0x00000000 5976 5977 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQS_P :: reserved0 [30:17] */ 5978 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_P_RESERVED0_MASK 0x7ffe0000 5979 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_P_RESERVED0_ALIGN 0 5980 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_P_RESERVED0_BITS 14 5981 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_P_RESERVED0_SHIFT 17 5982 5983 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQS_P :: FORCE [16:16] */ 5984 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_P_FORCE_MASK 0x00010000 5985 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_P_FORCE_ALIGN 0 5986 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_P_FORCE_BITS 1 5987 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_P_FORCE_SHIFT 16 5988 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_P_FORCE_DEFAULT 0x00000000 5989 5990 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQS_P :: reserved1 [15:13] */ 5991 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_P_RESERVED1_MASK 0x0000e000 5992 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_P_RESERVED1_ALIGN 0 5993 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_P_RESERVED1_BITS 3 5994 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_P_RESERVED1_SHIFT 13 5995 5996 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQS_P :: ADJ_EN [12:12] */ 5997 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_P_ADJ_EN_MASK 0x00001000 5998 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_P_ADJ_EN_ALIGN 0 5999 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_P_ADJ_EN_BITS 1 6000 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_P_ADJ_EN_SHIFT 12 6001 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_P_ADJ_EN_DEFAULT 0x00000000 6002 6003 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQS_P :: reserved2 [11:09] */ 6004 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_P_RESERVED2_MASK 0x00000e00 6005 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_P_RESERVED2_ALIGN 0 6006 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_P_RESERVED2_BITS 3 6007 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_P_RESERVED2_SHIFT 9 6008 6009 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQS_P :: VDL_STEP [08:00] */ 6010 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_P_VDL_STEP_MASK 0x000001ff 6011 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_P_VDL_STEP_ALIGN 0 6012 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_P_VDL_STEP_BITS 9 6013 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_P_VDL_STEP_SHIFT 0 6014 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_P_VDL_STEP_DEFAULT 0x00000000 6015 6016 /*************************************************************************** 6017 *VDL_CONTROL_WR_DQS_N - Write channel DQS-N VDL control register 6018 */ 6019 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQS_N :: BUSY [31:31] */ 6020 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_N_BUSY_MASK 0x80000000 6021 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_N_BUSY_ALIGN 0 6022 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_N_BUSY_BITS 1 6023 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_N_BUSY_SHIFT 31 6024 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_N_BUSY_DEFAULT 0x00000000 6025 6026 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQS_N :: reserved0 [30:17] */ 6027 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_N_RESERVED0_MASK 0x7ffe0000 6028 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_N_RESERVED0_ALIGN 0 6029 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_N_RESERVED0_BITS 14 6030 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_N_RESERVED0_SHIFT 17 6031 6032 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQS_N :: FORCE [16:16] */ 6033 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_N_FORCE_MASK 0x00010000 6034 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_N_FORCE_ALIGN 0 6035 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_N_FORCE_BITS 1 6036 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_N_FORCE_SHIFT 16 6037 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_N_FORCE_DEFAULT 0x00000000 6038 6039 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQS_N :: reserved1 [15:13] */ 6040 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_N_RESERVED1_MASK 0x0000e000 6041 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_N_RESERVED1_ALIGN 0 6042 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_N_RESERVED1_BITS 3 6043 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_N_RESERVED1_SHIFT 13 6044 6045 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQS_N :: ADJ_EN [12:12] */ 6046 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_N_ADJ_EN_MASK 0x00001000 6047 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_N_ADJ_EN_ALIGN 0 6048 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_N_ADJ_EN_BITS 1 6049 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_N_ADJ_EN_SHIFT 12 6050 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_N_ADJ_EN_DEFAULT 0x00000000 6051 6052 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQS_N :: reserved2 [11:09] */ 6053 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_N_RESERVED2_MASK 0x00000e00 6054 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_N_RESERVED2_ALIGN 0 6055 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_N_RESERVED2_BITS 3 6056 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_N_RESERVED2_SHIFT 9 6057 6058 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQS_N :: VDL_STEP [08:00] */ 6059 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_N_VDL_STEP_MASK 0x000001ff 6060 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_N_VDL_STEP_ALIGN 0 6061 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_N_VDL_STEP_BITS 9 6062 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_N_VDL_STEP_SHIFT 0 6063 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_N_VDL_STEP_DEFAULT 0x00000000 6064 6065 /*************************************************************************** 6066 *VDL_CONTROL_WR_DQ0 - Write channel DQ0 VDL control register 6067 */ 6068 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ0 :: BUSY [31:31] */ 6069 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0_BUSY_MASK 0x80000000 6070 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0_BUSY_ALIGN 0 6071 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0_BUSY_BITS 1 6072 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0_BUSY_SHIFT 31 6073 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0_BUSY_DEFAULT 0x00000000 6074 6075 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ0 :: reserved0 [30:17] */ 6076 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0_RESERVED0_MASK 0x7ffe0000 6077 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0_RESERVED0_ALIGN 0 6078 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0_RESERVED0_BITS 14 6079 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0_RESERVED0_SHIFT 17 6080 6081 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ0 :: FORCE [16:16] */ 6082 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0_FORCE_MASK 0x00010000 6083 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0_FORCE_ALIGN 0 6084 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0_FORCE_BITS 1 6085 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0_FORCE_SHIFT 16 6086 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0_FORCE_DEFAULT 0x00000000 6087 6088 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ0 :: reserved1 [15:13] */ 6089 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0_RESERVED1_MASK 0x0000e000 6090 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0_RESERVED1_ALIGN 0 6091 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0_RESERVED1_BITS 3 6092 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0_RESERVED1_SHIFT 13 6093 6094 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ0 :: ADJ_EN [12:12] */ 6095 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0_ADJ_EN_MASK 0x00001000 6096 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0_ADJ_EN_ALIGN 0 6097 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0_ADJ_EN_BITS 1 6098 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0_ADJ_EN_SHIFT 12 6099 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0_ADJ_EN_DEFAULT 0x00000000 6100 6101 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ0 :: reserved2 [11:09] */ 6102 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0_RESERVED2_MASK 0x00000e00 6103 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0_RESERVED2_ALIGN 0 6104 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0_RESERVED2_BITS 3 6105 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0_RESERVED2_SHIFT 9 6106 6107 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ0 :: VDL_STEP [08:00] */ 6108 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0_VDL_STEP_MASK 0x000001ff 6109 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0_VDL_STEP_ALIGN 0 6110 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0_VDL_STEP_BITS 9 6111 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0_VDL_STEP_SHIFT 0 6112 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0_VDL_STEP_DEFAULT 0x00000000 6113 6114 /*************************************************************************** 6115 *VDL_CONTROL_WR_DQ1 - Write channel DQ1 VDL control register 6116 */ 6117 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ1 :: BUSY [31:31] */ 6118 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1_BUSY_MASK 0x80000000 6119 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1_BUSY_ALIGN 0 6120 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1_BUSY_BITS 1 6121 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1_BUSY_SHIFT 31 6122 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1_BUSY_DEFAULT 0x00000000 6123 6124 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ1 :: reserved0 [30:17] */ 6125 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1_RESERVED0_MASK 0x7ffe0000 6126 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1_RESERVED0_ALIGN 0 6127 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1_RESERVED0_BITS 14 6128 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1_RESERVED0_SHIFT 17 6129 6130 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ1 :: FORCE [16:16] */ 6131 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1_FORCE_MASK 0x00010000 6132 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1_FORCE_ALIGN 0 6133 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1_FORCE_BITS 1 6134 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1_FORCE_SHIFT 16 6135 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1_FORCE_DEFAULT 0x00000000 6136 6137 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ1 :: reserved1 [15:13] */ 6138 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1_RESERVED1_MASK 0x0000e000 6139 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1_RESERVED1_ALIGN 0 6140 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1_RESERVED1_BITS 3 6141 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1_RESERVED1_SHIFT 13 6142 6143 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ1 :: ADJ_EN [12:12] */ 6144 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1_ADJ_EN_MASK 0x00001000 6145 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1_ADJ_EN_ALIGN 0 6146 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1_ADJ_EN_BITS 1 6147 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1_ADJ_EN_SHIFT 12 6148 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1_ADJ_EN_DEFAULT 0x00000000 6149 6150 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ1 :: reserved2 [11:09] */ 6151 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1_RESERVED2_MASK 0x00000e00 6152 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1_RESERVED2_ALIGN 0 6153 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1_RESERVED2_BITS 3 6154 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1_RESERVED2_SHIFT 9 6155 6156 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ1 :: VDL_STEP [08:00] */ 6157 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1_VDL_STEP_MASK 0x000001ff 6158 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1_VDL_STEP_ALIGN 0 6159 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1_VDL_STEP_BITS 9 6160 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1_VDL_STEP_SHIFT 0 6161 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1_VDL_STEP_DEFAULT 0x00000000 6162 6163 /*************************************************************************** 6164 *VDL_CONTROL_WR_DQ2 - Write channel DQ2 VDL control register 6165 */ 6166 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ2 :: BUSY [31:31] */ 6167 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2_BUSY_MASK 0x80000000 6168 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2_BUSY_ALIGN 0 6169 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2_BUSY_BITS 1 6170 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2_BUSY_SHIFT 31 6171 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2_BUSY_DEFAULT 0x00000000 6172 6173 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ2 :: reserved0 [30:17] */ 6174 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2_RESERVED0_MASK 0x7ffe0000 6175 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2_RESERVED0_ALIGN 0 6176 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2_RESERVED0_BITS 14 6177 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2_RESERVED0_SHIFT 17 6178 6179 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ2 :: FORCE [16:16] */ 6180 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2_FORCE_MASK 0x00010000 6181 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2_FORCE_ALIGN 0 6182 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2_FORCE_BITS 1 6183 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2_FORCE_SHIFT 16 6184 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2_FORCE_DEFAULT 0x00000000 6185 6186 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ2 :: reserved1 [15:13] */ 6187 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2_RESERVED1_MASK 0x0000e000 6188 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2_RESERVED1_ALIGN 0 6189 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2_RESERVED1_BITS 3 6190 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2_RESERVED1_SHIFT 13 6191 6192 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ2 :: ADJ_EN [12:12] */ 6193 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2_ADJ_EN_MASK 0x00001000 6194 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2_ADJ_EN_ALIGN 0 6195 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2_ADJ_EN_BITS 1 6196 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2_ADJ_EN_SHIFT 12 6197 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2_ADJ_EN_DEFAULT 0x00000000 6198 6199 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ2 :: reserved2 [11:09] */ 6200 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2_RESERVED2_MASK 0x00000e00 6201 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2_RESERVED2_ALIGN 0 6202 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2_RESERVED2_BITS 3 6203 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2_RESERVED2_SHIFT 9 6204 6205 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ2 :: VDL_STEP [08:00] */ 6206 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2_VDL_STEP_MASK 0x000001ff 6207 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2_VDL_STEP_ALIGN 0 6208 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2_VDL_STEP_BITS 9 6209 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2_VDL_STEP_SHIFT 0 6210 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2_VDL_STEP_DEFAULT 0x00000000 6211 6212 /*************************************************************************** 6213 *VDL_CONTROL_WR_DQ3 - Write channel DQ3 VDL control register 6214 */ 6215 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ3 :: BUSY [31:31] */ 6216 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3_BUSY_MASK 0x80000000 6217 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3_BUSY_ALIGN 0 6218 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3_BUSY_BITS 1 6219 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3_BUSY_SHIFT 31 6220 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3_BUSY_DEFAULT 0x00000000 6221 6222 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ3 :: reserved0 [30:17] */ 6223 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3_RESERVED0_MASK 0x7ffe0000 6224 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3_RESERVED0_ALIGN 0 6225 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3_RESERVED0_BITS 14 6226 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3_RESERVED0_SHIFT 17 6227 6228 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ3 :: FORCE [16:16] */ 6229 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3_FORCE_MASK 0x00010000 6230 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3_FORCE_ALIGN 0 6231 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3_FORCE_BITS 1 6232 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3_FORCE_SHIFT 16 6233 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3_FORCE_DEFAULT 0x00000000 6234 6235 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ3 :: reserved1 [15:13] */ 6236 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3_RESERVED1_MASK 0x0000e000 6237 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3_RESERVED1_ALIGN 0 6238 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3_RESERVED1_BITS 3 6239 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3_RESERVED1_SHIFT 13 6240 6241 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ3 :: ADJ_EN [12:12] */ 6242 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3_ADJ_EN_MASK 0x00001000 6243 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3_ADJ_EN_ALIGN 0 6244 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3_ADJ_EN_BITS 1 6245 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3_ADJ_EN_SHIFT 12 6246 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3_ADJ_EN_DEFAULT 0x00000000 6247 6248 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ3 :: reserved2 [11:09] */ 6249 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3_RESERVED2_MASK 0x00000e00 6250 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3_RESERVED2_ALIGN 0 6251 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3_RESERVED2_BITS 3 6252 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3_RESERVED2_SHIFT 9 6253 6254 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ3 :: VDL_STEP [08:00] */ 6255 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3_VDL_STEP_MASK 0x000001ff 6256 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3_VDL_STEP_ALIGN 0 6257 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3_VDL_STEP_BITS 9 6258 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3_VDL_STEP_SHIFT 0 6259 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3_VDL_STEP_DEFAULT 0x00000000 6260 6261 /*************************************************************************** 6262 *VDL_CONTROL_WR_DQ4 - Write channel DQ4 VDL control register 6263 */ 6264 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ4 :: BUSY [31:31] */ 6265 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4_BUSY_MASK 0x80000000 6266 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4_BUSY_ALIGN 0 6267 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4_BUSY_BITS 1 6268 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4_BUSY_SHIFT 31 6269 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4_BUSY_DEFAULT 0x00000000 6270 6271 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ4 :: reserved0 [30:17] */ 6272 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4_RESERVED0_MASK 0x7ffe0000 6273 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4_RESERVED0_ALIGN 0 6274 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4_RESERVED0_BITS 14 6275 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4_RESERVED0_SHIFT 17 6276 6277 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ4 :: FORCE [16:16] */ 6278 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4_FORCE_MASK 0x00010000 6279 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4_FORCE_ALIGN 0 6280 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4_FORCE_BITS 1 6281 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4_FORCE_SHIFT 16 6282 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4_FORCE_DEFAULT 0x00000000 6283 6284 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ4 :: reserved1 [15:13] */ 6285 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4_RESERVED1_MASK 0x0000e000 6286 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4_RESERVED1_ALIGN 0 6287 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4_RESERVED1_BITS 3 6288 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4_RESERVED1_SHIFT 13 6289 6290 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ4 :: ADJ_EN [12:12] */ 6291 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4_ADJ_EN_MASK 0x00001000 6292 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4_ADJ_EN_ALIGN 0 6293 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4_ADJ_EN_BITS 1 6294 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4_ADJ_EN_SHIFT 12 6295 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4_ADJ_EN_DEFAULT 0x00000000 6296 6297 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ4 :: reserved2 [11:09] */ 6298 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4_RESERVED2_MASK 0x00000e00 6299 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4_RESERVED2_ALIGN 0 6300 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4_RESERVED2_BITS 3 6301 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4_RESERVED2_SHIFT 9 6302 6303 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ4 :: VDL_STEP [08:00] */ 6304 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4_VDL_STEP_MASK 0x000001ff 6305 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4_VDL_STEP_ALIGN 0 6306 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4_VDL_STEP_BITS 9 6307 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4_VDL_STEP_SHIFT 0 6308 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4_VDL_STEP_DEFAULT 0x00000000 6309 6310 /*************************************************************************** 6311 *VDL_CONTROL_WR_DQ5 - Write channel DQ5 VDL control register 6312 */ 6313 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ5 :: BUSY [31:31] */ 6314 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5_BUSY_MASK 0x80000000 6315 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5_BUSY_ALIGN 0 6316 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5_BUSY_BITS 1 6317 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5_BUSY_SHIFT 31 6318 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5_BUSY_DEFAULT 0x00000000 6319 6320 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ5 :: reserved0 [30:17] */ 6321 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5_RESERVED0_MASK 0x7ffe0000 6322 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5_RESERVED0_ALIGN 0 6323 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5_RESERVED0_BITS 14 6324 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5_RESERVED0_SHIFT 17 6325 6326 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ5 :: FORCE [16:16] */ 6327 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5_FORCE_MASK 0x00010000 6328 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5_FORCE_ALIGN 0 6329 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5_FORCE_BITS 1 6330 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5_FORCE_SHIFT 16 6331 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5_FORCE_DEFAULT 0x00000000 6332 6333 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ5 :: reserved1 [15:13] */ 6334 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5_RESERVED1_MASK 0x0000e000 6335 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5_RESERVED1_ALIGN 0 6336 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5_RESERVED1_BITS 3 6337 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5_RESERVED1_SHIFT 13 6338 6339 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ5 :: ADJ_EN [12:12] */ 6340 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5_ADJ_EN_MASK 0x00001000 6341 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5_ADJ_EN_ALIGN 0 6342 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5_ADJ_EN_BITS 1 6343 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5_ADJ_EN_SHIFT 12 6344 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5_ADJ_EN_DEFAULT 0x00000000 6345 6346 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ5 :: reserved2 [11:09] */ 6347 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5_RESERVED2_MASK 0x00000e00 6348 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5_RESERVED2_ALIGN 0 6349 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5_RESERVED2_BITS 3 6350 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5_RESERVED2_SHIFT 9 6351 6352 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ5 :: VDL_STEP [08:00] */ 6353 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5_VDL_STEP_MASK 0x000001ff 6354 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5_VDL_STEP_ALIGN 0 6355 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5_VDL_STEP_BITS 9 6356 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5_VDL_STEP_SHIFT 0 6357 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5_VDL_STEP_DEFAULT 0x00000000 6358 6359 /*************************************************************************** 6360 *VDL_CONTROL_WR_DQ6 - Write channel DQ6 VDL control register 6361 */ 6362 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ6 :: BUSY [31:31] */ 6363 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6_BUSY_MASK 0x80000000 6364 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6_BUSY_ALIGN 0 6365 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6_BUSY_BITS 1 6366 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6_BUSY_SHIFT 31 6367 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6_BUSY_DEFAULT 0x00000000 6368 6369 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ6 :: reserved0 [30:17] */ 6370 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6_RESERVED0_MASK 0x7ffe0000 6371 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6_RESERVED0_ALIGN 0 6372 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6_RESERVED0_BITS 14 6373 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6_RESERVED0_SHIFT 17 6374 6375 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ6 :: FORCE [16:16] */ 6376 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6_FORCE_MASK 0x00010000 6377 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6_FORCE_ALIGN 0 6378 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6_FORCE_BITS 1 6379 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6_FORCE_SHIFT 16 6380 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6_FORCE_DEFAULT 0x00000000 6381 6382 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ6 :: reserved1 [15:13] */ 6383 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6_RESERVED1_MASK 0x0000e000 6384 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6_RESERVED1_ALIGN 0 6385 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6_RESERVED1_BITS 3 6386 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6_RESERVED1_SHIFT 13 6387 6388 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ6 :: ADJ_EN [12:12] */ 6389 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6_ADJ_EN_MASK 0x00001000 6390 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6_ADJ_EN_ALIGN 0 6391 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6_ADJ_EN_BITS 1 6392 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6_ADJ_EN_SHIFT 12 6393 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6_ADJ_EN_DEFAULT 0x00000000 6394 6395 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ6 :: reserved2 [11:09] */ 6396 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6_RESERVED2_MASK 0x00000e00 6397 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6_RESERVED2_ALIGN 0 6398 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6_RESERVED2_BITS 3 6399 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6_RESERVED2_SHIFT 9 6400 6401 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ6 :: VDL_STEP [08:00] */ 6402 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6_VDL_STEP_MASK 0x000001ff 6403 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6_VDL_STEP_ALIGN 0 6404 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6_VDL_STEP_BITS 9 6405 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6_VDL_STEP_SHIFT 0 6406 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6_VDL_STEP_DEFAULT 0x00000000 6407 6408 /*************************************************************************** 6409 *VDL_CONTROL_WR_DQ7 - Write channel DQ7 VDL control register 6410 */ 6411 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ7 :: BUSY [31:31] */ 6412 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7_BUSY_MASK 0x80000000 6413 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7_BUSY_ALIGN 0 6414 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7_BUSY_BITS 1 6415 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7_BUSY_SHIFT 31 6416 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7_BUSY_DEFAULT 0x00000000 6417 6418 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ7 :: reserved0 [30:17] */ 6419 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7_RESERVED0_MASK 0x7ffe0000 6420 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7_RESERVED0_ALIGN 0 6421 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7_RESERVED0_BITS 14 6422 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7_RESERVED0_SHIFT 17 6423 6424 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ7 :: FORCE [16:16] */ 6425 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7_FORCE_MASK 0x00010000 6426 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7_FORCE_ALIGN 0 6427 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7_FORCE_BITS 1 6428 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7_FORCE_SHIFT 16 6429 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7_FORCE_DEFAULT 0x00000000 6430 6431 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ7 :: reserved1 [15:13] */ 6432 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7_RESERVED1_MASK 0x0000e000 6433 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7_RESERVED1_ALIGN 0 6434 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7_RESERVED1_BITS 3 6435 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7_RESERVED1_SHIFT 13 6436 6437 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ7 :: ADJ_EN [12:12] */ 6438 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7_ADJ_EN_MASK 0x00001000 6439 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7_ADJ_EN_ALIGN 0 6440 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7_ADJ_EN_BITS 1 6441 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7_ADJ_EN_SHIFT 12 6442 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7_ADJ_EN_DEFAULT 0x00000000 6443 6444 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ7 :: reserved2 [11:09] */ 6445 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7_RESERVED2_MASK 0x00000e00 6446 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7_RESERVED2_ALIGN 0 6447 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7_RESERVED2_BITS 3 6448 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7_RESERVED2_SHIFT 9 6449 6450 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ7 :: VDL_STEP [08:00] */ 6451 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7_VDL_STEP_MASK 0x000001ff 6452 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7_VDL_STEP_ALIGN 0 6453 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7_VDL_STEP_BITS 9 6454 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7_VDL_STEP_SHIFT 0 6455 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7_VDL_STEP_DEFAULT 0x00000000 6456 6457 /*************************************************************************** 6458 *VDL_CONTROL_WR_DM - Write channel DM VDL control register 6459 */ 6460 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DM :: BUSY [31:31] */ 6461 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DM_BUSY_MASK 0x80000000 6462 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DM_BUSY_ALIGN 0 6463 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DM_BUSY_BITS 1 6464 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DM_BUSY_SHIFT 31 6465 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DM_BUSY_DEFAULT 0x00000000 6466 6467 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DM :: reserved0 [30:17] */ 6468 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DM_RESERVED0_MASK 0x7ffe0000 6469 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DM_RESERVED0_ALIGN 0 6470 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DM_RESERVED0_BITS 14 6471 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DM_RESERVED0_SHIFT 17 6472 6473 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DM :: FORCE [16:16] */ 6474 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DM_FORCE_MASK 0x00010000 6475 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DM_FORCE_ALIGN 0 6476 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DM_FORCE_BITS 1 6477 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DM_FORCE_SHIFT 16 6478 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DM_FORCE_DEFAULT 0x00000000 6479 6480 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DM :: reserved1 [15:13] */ 6481 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DM_RESERVED1_MASK 0x0000e000 6482 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DM_RESERVED1_ALIGN 0 6483 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DM_RESERVED1_BITS 3 6484 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DM_RESERVED1_SHIFT 13 6485 6486 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DM :: ADJ_EN [12:12] */ 6487 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DM_ADJ_EN_MASK 0x00001000 6488 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DM_ADJ_EN_ALIGN 0 6489 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DM_ADJ_EN_BITS 1 6490 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DM_ADJ_EN_SHIFT 12 6491 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DM_ADJ_EN_DEFAULT 0x00000000 6492 6493 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DM :: reserved2 [11:09] */ 6494 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DM_RESERVED2_MASK 0x00000e00 6495 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DM_RESERVED2_ALIGN 0 6496 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DM_RESERVED2_BITS 3 6497 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DM_RESERVED2_SHIFT 9 6498 6499 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DM :: VDL_STEP [08:00] */ 6500 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DM_VDL_STEP_MASK 0x000001ff 6501 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DM_VDL_STEP_ALIGN 0 6502 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DM_VDL_STEP_BITS 9 6503 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DM_VDL_STEP_SHIFT 0 6504 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DM_VDL_STEP_DEFAULT 0x00000000 6505 6506 /*************************************************************************** 6507 *VDL_CONTROL_WR_EDC - Write channel EDC VDL control register 6508 */ 6509 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_EDC :: BUSY [31:31] */ 6510 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_EDC_BUSY_MASK 0x80000000 6511 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_EDC_BUSY_ALIGN 0 6512 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_EDC_BUSY_BITS 1 6513 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_EDC_BUSY_SHIFT 31 6514 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_EDC_BUSY_DEFAULT 0x00000000 6515 6516 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_EDC :: reserved0 [30:17] */ 6517 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_EDC_RESERVED0_MASK 0x7ffe0000 6518 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_EDC_RESERVED0_ALIGN 0 6519 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_EDC_RESERVED0_BITS 14 6520 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_EDC_RESERVED0_SHIFT 17 6521 6522 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_EDC :: FORCE [16:16] */ 6523 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_EDC_FORCE_MASK 0x00010000 6524 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_EDC_FORCE_ALIGN 0 6525 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_EDC_FORCE_BITS 1 6526 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_EDC_FORCE_SHIFT 16 6527 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_EDC_FORCE_DEFAULT 0x00000000 6528 6529 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_EDC :: reserved1 [15:13] */ 6530 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_EDC_RESERVED1_MASK 0x0000e000 6531 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_EDC_RESERVED1_ALIGN 0 6532 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_EDC_RESERVED1_BITS 3 6533 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_EDC_RESERVED1_SHIFT 13 6534 6535 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_EDC :: ADJ_EN [12:12] */ 6536 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_EDC_ADJ_EN_MASK 0x00001000 6537 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_EDC_ADJ_EN_ALIGN 0 6538 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_EDC_ADJ_EN_BITS 1 6539 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_EDC_ADJ_EN_SHIFT 12 6540 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_EDC_ADJ_EN_DEFAULT 0x00000000 6541 6542 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_EDC :: reserved2 [11:09] */ 6543 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_EDC_RESERVED2_MASK 0x00000e00 6544 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_EDC_RESERVED2_ALIGN 0 6545 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_EDC_RESERVED2_BITS 3 6546 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_EDC_RESERVED2_SHIFT 9 6547 6548 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_EDC :: VDL_STEP [08:00] */ 6549 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_EDC_VDL_STEP_MASK 0x000001ff 6550 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_EDC_VDL_STEP_ALIGN 0 6551 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_EDC_VDL_STEP_BITS 9 6552 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_EDC_VDL_STEP_SHIFT 0 6553 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_EDC_VDL_STEP_DEFAULT 0x00000000 6554 6555 /*************************************************************************** 6556 *VDL_CONTROL_RD_DQSP - Read channel DQSP VDL control register 6557 */ 6558 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQSP :: BUSY [31:31] */ 6559 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSP_BUSY_MASK 0x80000000 6560 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSP_BUSY_ALIGN 0 6561 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSP_BUSY_BITS 1 6562 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSP_BUSY_SHIFT 31 6563 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSP_BUSY_DEFAULT 0x00000000 6564 6565 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQSP :: reserved0 [30:17] */ 6566 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSP_RESERVED0_MASK 0x7ffe0000 6567 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSP_RESERVED0_ALIGN 0 6568 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSP_RESERVED0_BITS 14 6569 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSP_RESERVED0_SHIFT 17 6570 6571 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQSP :: FORCE [16:16] */ 6572 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSP_FORCE_MASK 0x00010000 6573 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSP_FORCE_ALIGN 0 6574 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSP_FORCE_BITS 1 6575 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSP_FORCE_SHIFT 16 6576 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSP_FORCE_DEFAULT 0x00000000 6577 6578 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQSP :: reserved1 [15:13] */ 6579 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSP_RESERVED1_MASK 0x0000e000 6580 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSP_RESERVED1_ALIGN 0 6581 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSP_RESERVED1_BITS 3 6582 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSP_RESERVED1_SHIFT 13 6583 6584 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQSP :: ADJ_EN [12:12] */ 6585 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSP_ADJ_EN_MASK 0x00001000 6586 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSP_ADJ_EN_ALIGN 0 6587 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSP_ADJ_EN_BITS 1 6588 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSP_ADJ_EN_SHIFT 12 6589 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSP_ADJ_EN_DEFAULT 0x00000000 6590 6591 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQSP :: reserved2 [11:08] */ 6592 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSP_RESERVED2_MASK 0x00000f00 6593 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSP_RESERVED2_ALIGN 0 6594 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSP_RESERVED2_BITS 4 6595 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSP_RESERVED2_SHIFT 8 6596 6597 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQSP :: VDL_STEP [07:00] */ 6598 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSP_VDL_STEP_MASK 0x000000ff 6599 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSP_VDL_STEP_ALIGN 0 6600 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSP_VDL_STEP_BITS 8 6601 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSP_VDL_STEP_SHIFT 0 6602 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSP_VDL_STEP_DEFAULT 0x00000000 6603 6604 /*************************************************************************** 6605 *VDL_CONTROL_RD_DQSN - Read channel DQSP VDL control register 6606 */ 6607 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQSN :: BUSY [31:31] */ 6608 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSN_BUSY_MASK 0x80000000 6609 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSN_BUSY_ALIGN 0 6610 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSN_BUSY_BITS 1 6611 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSN_BUSY_SHIFT 31 6612 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSN_BUSY_DEFAULT 0x00000000 6613 6614 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQSN :: reserved0 [30:17] */ 6615 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSN_RESERVED0_MASK 0x7ffe0000 6616 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSN_RESERVED0_ALIGN 0 6617 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSN_RESERVED0_BITS 14 6618 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSN_RESERVED0_SHIFT 17 6619 6620 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQSN :: FORCE [16:16] */ 6621 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSN_FORCE_MASK 0x00010000 6622 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSN_FORCE_ALIGN 0 6623 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSN_FORCE_BITS 1 6624 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSN_FORCE_SHIFT 16 6625 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSN_FORCE_DEFAULT 0x00000000 6626 6627 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQSN :: reserved1 [15:13] */ 6628 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSN_RESERVED1_MASK 0x0000e000 6629 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSN_RESERVED1_ALIGN 0 6630 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSN_RESERVED1_BITS 3 6631 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSN_RESERVED1_SHIFT 13 6632 6633 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQSN :: ADJ_EN [12:12] */ 6634 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSN_ADJ_EN_MASK 0x00001000 6635 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSN_ADJ_EN_ALIGN 0 6636 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSN_ADJ_EN_BITS 1 6637 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSN_ADJ_EN_SHIFT 12 6638 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSN_ADJ_EN_DEFAULT 0x00000000 6639 6640 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQSN :: reserved2 [11:08] */ 6641 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSN_RESERVED2_MASK 0x00000f00 6642 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSN_RESERVED2_ALIGN 0 6643 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSN_RESERVED2_BITS 4 6644 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSN_RESERVED2_SHIFT 8 6645 6646 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQSN :: VDL_STEP [07:00] */ 6647 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSN_VDL_STEP_MASK 0x000000ff 6648 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSN_VDL_STEP_ALIGN 0 6649 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSN_VDL_STEP_BITS 8 6650 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSN_VDL_STEP_SHIFT 0 6651 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSN_VDL_STEP_DEFAULT 0x00000000 6652 6653 /*************************************************************************** 6654 *VDL_CONTROL_RD_DQ0P - Read channel DQ0-P VDL control register 6655 */ 6656 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ0P :: BUSY [31:31] */ 6657 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0P_BUSY_MASK 0x80000000 6658 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0P_BUSY_ALIGN 0 6659 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0P_BUSY_BITS 1 6660 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0P_BUSY_SHIFT 31 6661 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0P_BUSY_DEFAULT 0x00000000 6662 6663 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ0P :: reserved0 [30:17] */ 6664 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0P_RESERVED0_MASK 0x7ffe0000 6665 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0P_RESERVED0_ALIGN 0 6666 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0P_RESERVED0_BITS 14 6667 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0P_RESERVED0_SHIFT 17 6668 6669 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ0P :: FORCE [16:16] */ 6670 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0P_FORCE_MASK 0x00010000 6671 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0P_FORCE_ALIGN 0 6672 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0P_FORCE_BITS 1 6673 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0P_FORCE_SHIFT 16 6674 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0P_FORCE_DEFAULT 0x00000000 6675 6676 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ0P :: reserved1 [15:13] */ 6677 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0P_RESERVED1_MASK 0x0000e000 6678 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0P_RESERVED1_ALIGN 0 6679 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0P_RESERVED1_BITS 3 6680 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0P_RESERVED1_SHIFT 13 6681 6682 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ0P :: ADJ_EN [12:12] */ 6683 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0P_ADJ_EN_MASK 0x00001000 6684 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0P_ADJ_EN_ALIGN 0 6685 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0P_ADJ_EN_BITS 1 6686 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0P_ADJ_EN_SHIFT 12 6687 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0P_ADJ_EN_DEFAULT 0x00000000 6688 6689 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ0P :: reserved2 [11:08] */ 6690 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0P_RESERVED2_MASK 0x00000f00 6691 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0P_RESERVED2_ALIGN 0 6692 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0P_RESERVED2_BITS 4 6693 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0P_RESERVED2_SHIFT 8 6694 6695 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ0P :: VDL_STEP [07:00] */ 6696 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0P_VDL_STEP_MASK 0x000000ff 6697 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0P_VDL_STEP_ALIGN 0 6698 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0P_VDL_STEP_BITS 8 6699 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0P_VDL_STEP_SHIFT 0 6700 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0P_VDL_STEP_DEFAULT 0x00000000 6701 6702 /*************************************************************************** 6703 *VDL_CONTROL_RD_DQ0N - Read channel DQ0-N VDL control register 6704 */ 6705 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ0N :: BUSY [31:31] */ 6706 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0N_BUSY_MASK 0x80000000 6707 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0N_BUSY_ALIGN 0 6708 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0N_BUSY_BITS 1 6709 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0N_BUSY_SHIFT 31 6710 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0N_BUSY_DEFAULT 0x00000000 6711 6712 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ0N :: reserved0 [30:17] */ 6713 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0N_RESERVED0_MASK 0x7ffe0000 6714 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0N_RESERVED0_ALIGN 0 6715 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0N_RESERVED0_BITS 14 6716 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0N_RESERVED0_SHIFT 17 6717 6718 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ0N :: FORCE [16:16] */ 6719 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0N_FORCE_MASK 0x00010000 6720 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0N_FORCE_ALIGN 0 6721 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0N_FORCE_BITS 1 6722 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0N_FORCE_SHIFT 16 6723 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0N_FORCE_DEFAULT 0x00000000 6724 6725 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ0N :: reserved1 [15:13] */ 6726 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0N_RESERVED1_MASK 0x0000e000 6727 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0N_RESERVED1_ALIGN 0 6728 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0N_RESERVED1_BITS 3 6729 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0N_RESERVED1_SHIFT 13 6730 6731 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ0N :: ADJ_EN [12:12] */ 6732 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0N_ADJ_EN_MASK 0x00001000 6733 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0N_ADJ_EN_ALIGN 0 6734 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0N_ADJ_EN_BITS 1 6735 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0N_ADJ_EN_SHIFT 12 6736 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0N_ADJ_EN_DEFAULT 0x00000000 6737 6738 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ0N :: reserved2 [11:08] */ 6739 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0N_RESERVED2_MASK 0x00000f00 6740 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0N_RESERVED2_ALIGN 0 6741 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0N_RESERVED2_BITS 4 6742 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0N_RESERVED2_SHIFT 8 6743 6744 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ0N :: VDL_STEP [07:00] */ 6745 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0N_VDL_STEP_MASK 0x000000ff 6746 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0N_VDL_STEP_ALIGN 0 6747 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0N_VDL_STEP_BITS 8 6748 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0N_VDL_STEP_SHIFT 0 6749 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0N_VDL_STEP_DEFAULT 0x00000000 6750 6751 /*************************************************************************** 6752 *VDL_CONTROL_RD_DQ1P - Read channel DQ1-P VDL control register 6753 */ 6754 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ1P :: BUSY [31:31] */ 6755 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1P_BUSY_MASK 0x80000000 6756 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1P_BUSY_ALIGN 0 6757 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1P_BUSY_BITS 1 6758 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1P_BUSY_SHIFT 31 6759 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1P_BUSY_DEFAULT 0x00000000 6760 6761 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ1P :: reserved0 [30:17] */ 6762 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1P_RESERVED0_MASK 0x7ffe0000 6763 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1P_RESERVED0_ALIGN 0 6764 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1P_RESERVED0_BITS 14 6765 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1P_RESERVED0_SHIFT 17 6766 6767 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ1P :: FORCE [16:16] */ 6768 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1P_FORCE_MASK 0x00010000 6769 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1P_FORCE_ALIGN 0 6770 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1P_FORCE_BITS 1 6771 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1P_FORCE_SHIFT 16 6772 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1P_FORCE_DEFAULT 0x00000000 6773 6774 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ1P :: reserved1 [15:13] */ 6775 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1P_RESERVED1_MASK 0x0000e000 6776 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1P_RESERVED1_ALIGN 0 6777 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1P_RESERVED1_BITS 3 6778 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1P_RESERVED1_SHIFT 13 6779 6780 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ1P :: ADJ_EN [12:12] */ 6781 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1P_ADJ_EN_MASK 0x00001000 6782 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1P_ADJ_EN_ALIGN 0 6783 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1P_ADJ_EN_BITS 1 6784 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1P_ADJ_EN_SHIFT 12 6785 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1P_ADJ_EN_DEFAULT 0x00000000 6786 6787 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ1P :: reserved2 [11:08] */ 6788 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1P_RESERVED2_MASK 0x00000f00 6789 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1P_RESERVED2_ALIGN 0 6790 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1P_RESERVED2_BITS 4 6791 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1P_RESERVED2_SHIFT 8 6792 6793 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ1P :: VDL_STEP [07:00] */ 6794 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1P_VDL_STEP_MASK 0x000000ff 6795 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1P_VDL_STEP_ALIGN 0 6796 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1P_VDL_STEP_BITS 8 6797 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1P_VDL_STEP_SHIFT 0 6798 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1P_VDL_STEP_DEFAULT 0x00000000 6799 6800 /*************************************************************************** 6801 *VDL_CONTROL_RD_DQ1N - Read channel DQ1-N VDL control register 6802 */ 6803 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ1N :: BUSY [31:31] */ 6804 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1N_BUSY_MASK 0x80000000 6805 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1N_BUSY_ALIGN 0 6806 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1N_BUSY_BITS 1 6807 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1N_BUSY_SHIFT 31 6808 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1N_BUSY_DEFAULT 0x00000000 6809 6810 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ1N :: reserved0 [30:17] */ 6811 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1N_RESERVED0_MASK 0x7ffe0000 6812 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1N_RESERVED0_ALIGN 0 6813 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1N_RESERVED0_BITS 14 6814 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1N_RESERVED0_SHIFT 17 6815 6816 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ1N :: FORCE [16:16] */ 6817 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1N_FORCE_MASK 0x00010000 6818 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1N_FORCE_ALIGN 0 6819 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1N_FORCE_BITS 1 6820 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1N_FORCE_SHIFT 16 6821 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1N_FORCE_DEFAULT 0x00000000 6822 6823 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ1N :: reserved1 [15:13] */ 6824 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1N_RESERVED1_MASK 0x0000e000 6825 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1N_RESERVED1_ALIGN 0 6826 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1N_RESERVED1_BITS 3 6827 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1N_RESERVED1_SHIFT 13 6828 6829 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ1N :: ADJ_EN [12:12] */ 6830 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1N_ADJ_EN_MASK 0x00001000 6831 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1N_ADJ_EN_ALIGN 0 6832 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1N_ADJ_EN_BITS 1 6833 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1N_ADJ_EN_SHIFT 12 6834 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1N_ADJ_EN_DEFAULT 0x00000000 6835 6836 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ1N :: reserved2 [11:08] */ 6837 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1N_RESERVED2_MASK 0x00000f00 6838 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1N_RESERVED2_ALIGN 0 6839 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1N_RESERVED2_BITS 4 6840 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1N_RESERVED2_SHIFT 8 6841 6842 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ1N :: VDL_STEP [07:00] */ 6843 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1N_VDL_STEP_MASK 0x000000ff 6844 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1N_VDL_STEP_ALIGN 0 6845 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1N_VDL_STEP_BITS 8 6846 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1N_VDL_STEP_SHIFT 0 6847 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1N_VDL_STEP_DEFAULT 0x00000000 6848 6849 /*************************************************************************** 6850 *VDL_CONTROL_RD_DQ2P - Read channel DQ2-P VDL control register 6851 */ 6852 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ2P :: BUSY [31:31] */ 6853 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2P_BUSY_MASK 0x80000000 6854 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2P_BUSY_ALIGN 0 6855 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2P_BUSY_BITS 1 6856 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2P_BUSY_SHIFT 31 6857 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2P_BUSY_DEFAULT 0x00000000 6858 6859 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ2P :: reserved0 [30:17] */ 6860 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2P_RESERVED0_MASK 0x7ffe0000 6861 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2P_RESERVED0_ALIGN 0 6862 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2P_RESERVED0_BITS 14 6863 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2P_RESERVED0_SHIFT 17 6864 6865 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ2P :: FORCE [16:16] */ 6866 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2P_FORCE_MASK 0x00010000 6867 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2P_FORCE_ALIGN 0 6868 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2P_FORCE_BITS 1 6869 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2P_FORCE_SHIFT 16 6870 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2P_FORCE_DEFAULT 0x00000000 6871 6872 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ2P :: reserved1 [15:13] */ 6873 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2P_RESERVED1_MASK 0x0000e000 6874 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2P_RESERVED1_ALIGN 0 6875 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2P_RESERVED1_BITS 3 6876 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2P_RESERVED1_SHIFT 13 6877 6878 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ2P :: ADJ_EN [12:12] */ 6879 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2P_ADJ_EN_MASK 0x00001000 6880 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2P_ADJ_EN_ALIGN 0 6881 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2P_ADJ_EN_BITS 1 6882 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2P_ADJ_EN_SHIFT 12 6883 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2P_ADJ_EN_DEFAULT 0x00000000 6884 6885 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ2P :: reserved2 [11:08] */ 6886 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2P_RESERVED2_MASK 0x00000f00 6887 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2P_RESERVED2_ALIGN 0 6888 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2P_RESERVED2_BITS 4 6889 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2P_RESERVED2_SHIFT 8 6890 6891 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ2P :: VDL_STEP [07:00] */ 6892 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2P_VDL_STEP_MASK 0x000000ff 6893 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2P_VDL_STEP_ALIGN 0 6894 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2P_VDL_STEP_BITS 8 6895 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2P_VDL_STEP_SHIFT 0 6896 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2P_VDL_STEP_DEFAULT 0x00000000 6897 6898 /*************************************************************************** 6899 *VDL_CONTROL_RD_DQ2N - Read channel DQ2-N VDL control register 6900 */ 6901 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ2N :: BUSY [31:31] */ 6902 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2N_BUSY_MASK 0x80000000 6903 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2N_BUSY_ALIGN 0 6904 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2N_BUSY_BITS 1 6905 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2N_BUSY_SHIFT 31 6906 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2N_BUSY_DEFAULT 0x00000000 6907 6908 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ2N :: reserved0 [30:17] */ 6909 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2N_RESERVED0_MASK 0x7ffe0000 6910 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2N_RESERVED0_ALIGN 0 6911 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2N_RESERVED0_BITS 14 6912 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2N_RESERVED0_SHIFT 17 6913 6914 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ2N :: FORCE [16:16] */ 6915 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2N_FORCE_MASK 0x00010000 6916 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2N_FORCE_ALIGN 0 6917 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2N_FORCE_BITS 1 6918 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2N_FORCE_SHIFT 16 6919 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2N_FORCE_DEFAULT 0x00000000 6920 6921 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ2N :: reserved1 [15:13] */ 6922 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2N_RESERVED1_MASK 0x0000e000 6923 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2N_RESERVED1_ALIGN 0 6924 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2N_RESERVED1_BITS 3 6925 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2N_RESERVED1_SHIFT 13 6926 6927 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ2N :: ADJ_EN [12:12] */ 6928 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2N_ADJ_EN_MASK 0x00001000 6929 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2N_ADJ_EN_ALIGN 0 6930 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2N_ADJ_EN_BITS 1 6931 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2N_ADJ_EN_SHIFT 12 6932 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2N_ADJ_EN_DEFAULT 0x00000000 6933 6934 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ2N :: reserved2 [11:08] */ 6935 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2N_RESERVED2_MASK 0x00000f00 6936 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2N_RESERVED2_ALIGN 0 6937 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2N_RESERVED2_BITS 4 6938 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2N_RESERVED2_SHIFT 8 6939 6940 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ2N :: VDL_STEP [07:00] */ 6941 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2N_VDL_STEP_MASK 0x000000ff 6942 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2N_VDL_STEP_ALIGN 0 6943 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2N_VDL_STEP_BITS 8 6944 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2N_VDL_STEP_SHIFT 0 6945 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2N_VDL_STEP_DEFAULT 0x00000000 6946 6947 /*************************************************************************** 6948 *VDL_CONTROL_RD_DQ3P - Read channel DQ3-P VDL control register 6949 */ 6950 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ3P :: BUSY [31:31] */ 6951 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3P_BUSY_MASK 0x80000000 6952 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3P_BUSY_ALIGN 0 6953 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3P_BUSY_BITS 1 6954 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3P_BUSY_SHIFT 31 6955 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3P_BUSY_DEFAULT 0x00000000 6956 6957 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ3P :: reserved0 [30:17] */ 6958 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3P_RESERVED0_MASK 0x7ffe0000 6959 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3P_RESERVED0_ALIGN 0 6960 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3P_RESERVED0_BITS 14 6961 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3P_RESERVED0_SHIFT 17 6962 6963 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ3P :: FORCE [16:16] */ 6964 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3P_FORCE_MASK 0x00010000 6965 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3P_FORCE_ALIGN 0 6966 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3P_FORCE_BITS 1 6967 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3P_FORCE_SHIFT 16 6968 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3P_FORCE_DEFAULT 0x00000000 6969 6970 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ3P :: reserved1 [15:13] */ 6971 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3P_RESERVED1_MASK 0x0000e000 6972 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3P_RESERVED1_ALIGN 0 6973 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3P_RESERVED1_BITS 3 6974 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3P_RESERVED1_SHIFT 13 6975 6976 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ3P :: ADJ_EN [12:12] */ 6977 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3P_ADJ_EN_MASK 0x00001000 6978 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3P_ADJ_EN_ALIGN 0 6979 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3P_ADJ_EN_BITS 1 6980 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3P_ADJ_EN_SHIFT 12 6981 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3P_ADJ_EN_DEFAULT 0x00000000 6982 6983 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ3P :: reserved2 [11:08] */ 6984 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3P_RESERVED2_MASK 0x00000f00 6985 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3P_RESERVED2_ALIGN 0 6986 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3P_RESERVED2_BITS 4 6987 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3P_RESERVED2_SHIFT 8 6988 6989 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ3P :: VDL_STEP [07:00] */ 6990 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3P_VDL_STEP_MASK 0x000000ff 6991 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3P_VDL_STEP_ALIGN 0 6992 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3P_VDL_STEP_BITS 8 6993 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3P_VDL_STEP_SHIFT 0 6994 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3P_VDL_STEP_DEFAULT 0x00000000 6995 6996 /*************************************************************************** 6997 *VDL_CONTROL_RD_DQ3N - Read channel DQ3-N VDL control register 6998 */ 6999 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ3N :: BUSY [31:31] */ 7000 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3N_BUSY_MASK 0x80000000 7001 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3N_BUSY_ALIGN 0 7002 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3N_BUSY_BITS 1 7003 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3N_BUSY_SHIFT 31 7004 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3N_BUSY_DEFAULT 0x00000000 7005 7006 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ3N :: reserved0 [30:17] */ 7007 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3N_RESERVED0_MASK 0x7ffe0000 7008 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3N_RESERVED0_ALIGN 0 7009 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3N_RESERVED0_BITS 14 7010 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3N_RESERVED0_SHIFT 17 7011 7012 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ3N :: FORCE [16:16] */ 7013 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3N_FORCE_MASK 0x00010000 7014 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3N_FORCE_ALIGN 0 7015 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3N_FORCE_BITS 1 7016 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3N_FORCE_SHIFT 16 7017 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3N_FORCE_DEFAULT 0x00000000 7018 7019 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ3N :: reserved1 [15:13] */ 7020 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3N_RESERVED1_MASK 0x0000e000 7021 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3N_RESERVED1_ALIGN 0 7022 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3N_RESERVED1_BITS 3 7023 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3N_RESERVED1_SHIFT 13 7024 7025 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ3N :: ADJ_EN [12:12] */ 7026 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3N_ADJ_EN_MASK 0x00001000 7027 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3N_ADJ_EN_ALIGN 0 7028 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3N_ADJ_EN_BITS 1 7029 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3N_ADJ_EN_SHIFT 12 7030 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3N_ADJ_EN_DEFAULT 0x00000000 7031 7032 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ3N :: reserved2 [11:08] */ 7033 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3N_RESERVED2_MASK 0x00000f00 7034 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3N_RESERVED2_ALIGN 0 7035 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3N_RESERVED2_BITS 4 7036 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3N_RESERVED2_SHIFT 8 7037 7038 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ3N :: VDL_STEP [07:00] */ 7039 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3N_VDL_STEP_MASK 0x000000ff 7040 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3N_VDL_STEP_ALIGN 0 7041 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3N_VDL_STEP_BITS 8 7042 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3N_VDL_STEP_SHIFT 0 7043 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3N_VDL_STEP_DEFAULT 0x00000000 7044 7045 /*************************************************************************** 7046 *VDL_CONTROL_RD_DQ4P - Read channel DQ4-P VDL control register 7047 */ 7048 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ4P :: BUSY [31:31] */ 7049 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4P_BUSY_MASK 0x80000000 7050 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4P_BUSY_ALIGN 0 7051 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4P_BUSY_BITS 1 7052 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4P_BUSY_SHIFT 31 7053 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4P_BUSY_DEFAULT 0x00000000 7054 7055 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ4P :: reserved0 [30:17] */ 7056 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4P_RESERVED0_MASK 0x7ffe0000 7057 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4P_RESERVED0_ALIGN 0 7058 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4P_RESERVED0_BITS 14 7059 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4P_RESERVED0_SHIFT 17 7060 7061 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ4P :: FORCE [16:16] */ 7062 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4P_FORCE_MASK 0x00010000 7063 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4P_FORCE_ALIGN 0 7064 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4P_FORCE_BITS 1 7065 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4P_FORCE_SHIFT 16 7066 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4P_FORCE_DEFAULT 0x00000000 7067 7068 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ4P :: reserved1 [15:13] */ 7069 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4P_RESERVED1_MASK 0x0000e000 7070 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4P_RESERVED1_ALIGN 0 7071 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4P_RESERVED1_BITS 3 7072 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4P_RESERVED1_SHIFT 13 7073 7074 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ4P :: ADJ_EN [12:12] */ 7075 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4P_ADJ_EN_MASK 0x00001000 7076 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4P_ADJ_EN_ALIGN 0 7077 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4P_ADJ_EN_BITS 1 7078 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4P_ADJ_EN_SHIFT 12 7079 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4P_ADJ_EN_DEFAULT 0x00000000 7080 7081 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ4P :: reserved2 [11:08] */ 7082 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4P_RESERVED2_MASK 0x00000f00 7083 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4P_RESERVED2_ALIGN 0 7084 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4P_RESERVED2_BITS 4 7085 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4P_RESERVED2_SHIFT 8 7086 7087 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ4P :: VDL_STEP [07:00] */ 7088 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4P_VDL_STEP_MASK 0x000000ff 7089 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4P_VDL_STEP_ALIGN 0 7090 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4P_VDL_STEP_BITS 8 7091 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4P_VDL_STEP_SHIFT 0 7092 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4P_VDL_STEP_DEFAULT 0x00000000 7093 7094 /*************************************************************************** 7095 *VDL_CONTROL_RD_DQ4N - Read channel DQ4-N VDL control register 7096 */ 7097 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ4N :: BUSY [31:31] */ 7098 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4N_BUSY_MASK 0x80000000 7099 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4N_BUSY_ALIGN 0 7100 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4N_BUSY_BITS 1 7101 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4N_BUSY_SHIFT 31 7102 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4N_BUSY_DEFAULT 0x00000000 7103 7104 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ4N :: reserved0 [30:17] */ 7105 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4N_RESERVED0_MASK 0x7ffe0000 7106 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4N_RESERVED0_ALIGN 0 7107 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4N_RESERVED0_BITS 14 7108 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4N_RESERVED0_SHIFT 17 7109 7110 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ4N :: FORCE [16:16] */ 7111 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4N_FORCE_MASK 0x00010000 7112 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4N_FORCE_ALIGN 0 7113 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4N_FORCE_BITS 1 7114 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4N_FORCE_SHIFT 16 7115 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4N_FORCE_DEFAULT 0x00000000 7116 7117 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ4N :: reserved1 [15:13] */ 7118 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4N_RESERVED1_MASK 0x0000e000 7119 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4N_RESERVED1_ALIGN 0 7120 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4N_RESERVED1_BITS 3 7121 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4N_RESERVED1_SHIFT 13 7122 7123 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ4N :: ADJ_EN [12:12] */ 7124 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4N_ADJ_EN_MASK 0x00001000 7125 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4N_ADJ_EN_ALIGN 0 7126 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4N_ADJ_EN_BITS 1 7127 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4N_ADJ_EN_SHIFT 12 7128 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4N_ADJ_EN_DEFAULT 0x00000000 7129 7130 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ4N :: reserved2 [11:08] */ 7131 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4N_RESERVED2_MASK 0x00000f00 7132 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4N_RESERVED2_ALIGN 0 7133 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4N_RESERVED2_BITS 4 7134 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4N_RESERVED2_SHIFT 8 7135 7136 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ4N :: VDL_STEP [07:00] */ 7137 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4N_VDL_STEP_MASK 0x000000ff 7138 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4N_VDL_STEP_ALIGN 0 7139 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4N_VDL_STEP_BITS 8 7140 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4N_VDL_STEP_SHIFT 0 7141 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4N_VDL_STEP_DEFAULT 0x00000000 7142 7143 /*************************************************************************** 7144 *VDL_CONTROL_RD_DQ5P - Read channel DQ5-P VDL control register 7145 */ 7146 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ5P :: BUSY [31:31] */ 7147 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5P_BUSY_MASK 0x80000000 7148 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5P_BUSY_ALIGN 0 7149 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5P_BUSY_BITS 1 7150 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5P_BUSY_SHIFT 31 7151 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5P_BUSY_DEFAULT 0x00000000 7152 7153 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ5P :: reserved0 [30:17] */ 7154 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5P_RESERVED0_MASK 0x7ffe0000 7155 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5P_RESERVED0_ALIGN 0 7156 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5P_RESERVED0_BITS 14 7157 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5P_RESERVED0_SHIFT 17 7158 7159 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ5P :: FORCE [16:16] */ 7160 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5P_FORCE_MASK 0x00010000 7161 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5P_FORCE_ALIGN 0 7162 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5P_FORCE_BITS 1 7163 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5P_FORCE_SHIFT 16 7164 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5P_FORCE_DEFAULT 0x00000000 7165 7166 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ5P :: reserved1 [15:13] */ 7167 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5P_RESERVED1_MASK 0x0000e000 7168 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5P_RESERVED1_ALIGN 0 7169 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5P_RESERVED1_BITS 3 7170 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5P_RESERVED1_SHIFT 13 7171 7172 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ5P :: ADJ_EN [12:12] */ 7173 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5P_ADJ_EN_MASK 0x00001000 7174 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5P_ADJ_EN_ALIGN 0 7175 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5P_ADJ_EN_BITS 1 7176 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5P_ADJ_EN_SHIFT 12 7177 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5P_ADJ_EN_DEFAULT 0x00000000 7178 7179 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ5P :: reserved2 [11:08] */ 7180 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5P_RESERVED2_MASK 0x00000f00 7181 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5P_RESERVED2_ALIGN 0 7182 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5P_RESERVED2_BITS 4 7183 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5P_RESERVED2_SHIFT 8 7184 7185 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ5P :: VDL_STEP [07:00] */ 7186 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5P_VDL_STEP_MASK 0x000000ff 7187 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5P_VDL_STEP_ALIGN 0 7188 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5P_VDL_STEP_BITS 8 7189 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5P_VDL_STEP_SHIFT 0 7190 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5P_VDL_STEP_DEFAULT 0x00000000 7191 7192 /*************************************************************************** 7193 *VDL_CONTROL_RD_DQ5N - Read channel DQ5-N VDL control register 7194 */ 7195 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ5N :: BUSY [31:31] */ 7196 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5N_BUSY_MASK 0x80000000 7197 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5N_BUSY_ALIGN 0 7198 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5N_BUSY_BITS 1 7199 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5N_BUSY_SHIFT 31 7200 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5N_BUSY_DEFAULT 0x00000000 7201 7202 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ5N :: reserved0 [30:17] */ 7203 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5N_RESERVED0_MASK 0x7ffe0000 7204 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5N_RESERVED0_ALIGN 0 7205 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5N_RESERVED0_BITS 14 7206 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5N_RESERVED0_SHIFT 17 7207 7208 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ5N :: FORCE [16:16] */ 7209 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5N_FORCE_MASK 0x00010000 7210 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5N_FORCE_ALIGN 0 7211 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5N_FORCE_BITS 1 7212 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5N_FORCE_SHIFT 16 7213 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5N_FORCE_DEFAULT 0x00000000 7214 7215 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ5N :: reserved1 [15:13] */ 7216 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5N_RESERVED1_MASK 0x0000e000 7217 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5N_RESERVED1_ALIGN 0 7218 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5N_RESERVED1_BITS 3 7219 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5N_RESERVED1_SHIFT 13 7220 7221 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ5N :: ADJ_EN [12:12] */ 7222 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5N_ADJ_EN_MASK 0x00001000 7223 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5N_ADJ_EN_ALIGN 0 7224 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5N_ADJ_EN_BITS 1 7225 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5N_ADJ_EN_SHIFT 12 7226 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5N_ADJ_EN_DEFAULT 0x00000000 7227 7228 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ5N :: reserved2 [11:08] */ 7229 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5N_RESERVED2_MASK 0x00000f00 7230 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5N_RESERVED2_ALIGN 0 7231 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5N_RESERVED2_BITS 4 7232 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5N_RESERVED2_SHIFT 8 7233 7234 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ5N :: VDL_STEP [07:00] */ 7235 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5N_VDL_STEP_MASK 0x000000ff 7236 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5N_VDL_STEP_ALIGN 0 7237 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5N_VDL_STEP_BITS 8 7238 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5N_VDL_STEP_SHIFT 0 7239 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5N_VDL_STEP_DEFAULT 0x00000000 7240 7241 /*************************************************************************** 7242 *VDL_CONTROL_RD_DQ6P - Read channel DQ6-P VDL control register 7243 */ 7244 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ6P :: BUSY [31:31] */ 7245 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6P_BUSY_MASK 0x80000000 7246 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6P_BUSY_ALIGN 0 7247 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6P_BUSY_BITS 1 7248 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6P_BUSY_SHIFT 31 7249 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6P_BUSY_DEFAULT 0x00000000 7250 7251 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ6P :: reserved0 [30:17] */ 7252 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6P_RESERVED0_MASK 0x7ffe0000 7253 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6P_RESERVED0_ALIGN 0 7254 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6P_RESERVED0_BITS 14 7255 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6P_RESERVED0_SHIFT 17 7256 7257 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ6P :: FORCE [16:16] */ 7258 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6P_FORCE_MASK 0x00010000 7259 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6P_FORCE_ALIGN 0 7260 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6P_FORCE_BITS 1 7261 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6P_FORCE_SHIFT 16 7262 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6P_FORCE_DEFAULT 0x00000000 7263 7264 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ6P :: reserved1 [15:13] */ 7265 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6P_RESERVED1_MASK 0x0000e000 7266 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6P_RESERVED1_ALIGN 0 7267 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6P_RESERVED1_BITS 3 7268 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6P_RESERVED1_SHIFT 13 7269 7270 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ6P :: ADJ_EN [12:12] */ 7271 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6P_ADJ_EN_MASK 0x00001000 7272 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6P_ADJ_EN_ALIGN 0 7273 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6P_ADJ_EN_BITS 1 7274 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6P_ADJ_EN_SHIFT 12 7275 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6P_ADJ_EN_DEFAULT 0x00000000 7276 7277 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ6P :: reserved2 [11:08] */ 7278 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6P_RESERVED2_MASK 0x00000f00 7279 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6P_RESERVED2_ALIGN 0 7280 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6P_RESERVED2_BITS 4 7281 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6P_RESERVED2_SHIFT 8 7282 7283 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ6P :: VDL_STEP [07:00] */ 7284 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6P_VDL_STEP_MASK 0x000000ff 7285 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6P_VDL_STEP_ALIGN 0 7286 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6P_VDL_STEP_BITS 8 7287 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6P_VDL_STEP_SHIFT 0 7288 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6P_VDL_STEP_DEFAULT 0x00000000 7289 7290 /*************************************************************************** 7291 *VDL_CONTROL_RD_DQ6N - Read channel DQ6-N VDL control register 7292 */ 7293 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ6N :: BUSY [31:31] */ 7294 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6N_BUSY_MASK 0x80000000 7295 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6N_BUSY_ALIGN 0 7296 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6N_BUSY_BITS 1 7297 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6N_BUSY_SHIFT 31 7298 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6N_BUSY_DEFAULT 0x00000000 7299 7300 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ6N :: reserved0 [30:17] */ 7301 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6N_RESERVED0_MASK 0x7ffe0000 7302 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6N_RESERVED0_ALIGN 0 7303 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6N_RESERVED0_BITS 14 7304 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6N_RESERVED0_SHIFT 17 7305 7306 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ6N :: FORCE [16:16] */ 7307 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6N_FORCE_MASK 0x00010000 7308 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6N_FORCE_ALIGN 0 7309 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6N_FORCE_BITS 1 7310 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6N_FORCE_SHIFT 16 7311 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6N_FORCE_DEFAULT 0x00000000 7312 7313 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ6N :: reserved1 [15:13] */ 7314 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6N_RESERVED1_MASK 0x0000e000 7315 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6N_RESERVED1_ALIGN 0 7316 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6N_RESERVED1_BITS 3 7317 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6N_RESERVED1_SHIFT 13 7318 7319 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ6N :: ADJ_EN [12:12] */ 7320 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6N_ADJ_EN_MASK 0x00001000 7321 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6N_ADJ_EN_ALIGN 0 7322 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6N_ADJ_EN_BITS 1 7323 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6N_ADJ_EN_SHIFT 12 7324 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6N_ADJ_EN_DEFAULT 0x00000000 7325 7326 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ6N :: reserved2 [11:08] */ 7327 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6N_RESERVED2_MASK 0x00000f00 7328 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6N_RESERVED2_ALIGN 0 7329 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6N_RESERVED2_BITS 4 7330 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6N_RESERVED2_SHIFT 8 7331 7332 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ6N :: VDL_STEP [07:00] */ 7333 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6N_VDL_STEP_MASK 0x000000ff 7334 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6N_VDL_STEP_ALIGN 0 7335 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6N_VDL_STEP_BITS 8 7336 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6N_VDL_STEP_SHIFT 0 7337 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6N_VDL_STEP_DEFAULT 0x00000000 7338 7339 /*************************************************************************** 7340 *VDL_CONTROL_RD_DQ7P - Read channel DQ7-P VDL control register 7341 */ 7342 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ7P :: BUSY [31:31] */ 7343 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7P_BUSY_MASK 0x80000000 7344 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7P_BUSY_ALIGN 0 7345 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7P_BUSY_BITS 1 7346 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7P_BUSY_SHIFT 31 7347 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7P_BUSY_DEFAULT 0x00000000 7348 7349 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ7P :: reserved0 [30:17] */ 7350 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7P_RESERVED0_MASK 0x7ffe0000 7351 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7P_RESERVED0_ALIGN 0 7352 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7P_RESERVED0_BITS 14 7353 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7P_RESERVED0_SHIFT 17 7354 7355 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ7P :: FORCE [16:16] */ 7356 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7P_FORCE_MASK 0x00010000 7357 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7P_FORCE_ALIGN 0 7358 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7P_FORCE_BITS 1 7359 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7P_FORCE_SHIFT 16 7360 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7P_FORCE_DEFAULT 0x00000000 7361 7362 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ7P :: reserved1 [15:13] */ 7363 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7P_RESERVED1_MASK 0x0000e000 7364 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7P_RESERVED1_ALIGN 0 7365 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7P_RESERVED1_BITS 3 7366 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7P_RESERVED1_SHIFT 13 7367 7368 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ7P :: ADJ_EN [12:12] */ 7369 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7P_ADJ_EN_MASK 0x00001000 7370 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7P_ADJ_EN_ALIGN 0 7371 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7P_ADJ_EN_BITS 1 7372 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7P_ADJ_EN_SHIFT 12 7373 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7P_ADJ_EN_DEFAULT 0x00000000 7374 7375 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ7P :: reserved2 [11:08] */ 7376 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7P_RESERVED2_MASK 0x00000f00 7377 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7P_RESERVED2_ALIGN 0 7378 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7P_RESERVED2_BITS 4 7379 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7P_RESERVED2_SHIFT 8 7380 7381 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ7P :: VDL_STEP [07:00] */ 7382 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7P_VDL_STEP_MASK 0x000000ff 7383 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7P_VDL_STEP_ALIGN 0 7384 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7P_VDL_STEP_BITS 8 7385 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7P_VDL_STEP_SHIFT 0 7386 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7P_VDL_STEP_DEFAULT 0x00000000 7387 7388 /*************************************************************************** 7389 *VDL_CONTROL_RD_DQ7N - Read channel DQ7-N VDL control register 7390 */ 7391 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ7N :: BUSY [31:31] */ 7392 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7N_BUSY_MASK 0x80000000 7393 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7N_BUSY_ALIGN 0 7394 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7N_BUSY_BITS 1 7395 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7N_BUSY_SHIFT 31 7396 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7N_BUSY_DEFAULT 0x00000000 7397 7398 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ7N :: reserved0 [30:17] */ 7399 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7N_RESERVED0_MASK 0x7ffe0000 7400 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7N_RESERVED0_ALIGN 0 7401 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7N_RESERVED0_BITS 14 7402 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7N_RESERVED0_SHIFT 17 7403 7404 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ7N :: FORCE [16:16] */ 7405 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7N_FORCE_MASK 0x00010000 7406 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7N_FORCE_ALIGN 0 7407 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7N_FORCE_BITS 1 7408 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7N_FORCE_SHIFT 16 7409 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7N_FORCE_DEFAULT 0x00000000 7410 7411 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ7N :: reserved1 [15:13] */ 7412 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7N_RESERVED1_MASK 0x0000e000 7413 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7N_RESERVED1_ALIGN 0 7414 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7N_RESERVED1_BITS 3 7415 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7N_RESERVED1_SHIFT 13 7416 7417 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ7N :: ADJ_EN [12:12] */ 7418 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7N_ADJ_EN_MASK 0x00001000 7419 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7N_ADJ_EN_ALIGN 0 7420 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7N_ADJ_EN_BITS 1 7421 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7N_ADJ_EN_SHIFT 12 7422 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7N_ADJ_EN_DEFAULT 0x00000000 7423 7424 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ7N :: reserved2 [11:08] */ 7425 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7N_RESERVED2_MASK 0x00000f00 7426 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7N_RESERVED2_ALIGN 0 7427 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7N_RESERVED2_BITS 4 7428 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7N_RESERVED2_SHIFT 8 7429 7430 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ7N :: VDL_STEP [07:00] */ 7431 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7N_VDL_STEP_MASK 0x000000ff 7432 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7N_VDL_STEP_ALIGN 0 7433 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7N_VDL_STEP_BITS 8 7434 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7N_VDL_STEP_SHIFT 0 7435 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7N_VDL_STEP_DEFAULT 0x00000000 7436 7437 /*************************************************************************** 7438 *VDL_CONTROL_RD_DMP - Read channel DM-P VDL control register 7439 */ 7440 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DMP :: BUSY [31:31] */ 7441 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMP_BUSY_MASK 0x80000000 7442 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMP_BUSY_ALIGN 0 7443 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMP_BUSY_BITS 1 7444 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMP_BUSY_SHIFT 31 7445 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMP_BUSY_DEFAULT 0x00000000 7446 7447 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DMP :: reserved0 [30:17] */ 7448 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMP_RESERVED0_MASK 0x7ffe0000 7449 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMP_RESERVED0_ALIGN 0 7450 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMP_RESERVED0_BITS 14 7451 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMP_RESERVED0_SHIFT 17 7452 7453 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DMP :: FORCE [16:16] */ 7454 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMP_FORCE_MASK 0x00010000 7455 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMP_FORCE_ALIGN 0 7456 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMP_FORCE_BITS 1 7457 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMP_FORCE_SHIFT 16 7458 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMP_FORCE_DEFAULT 0x00000000 7459 7460 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DMP :: reserved1 [15:13] */ 7461 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMP_RESERVED1_MASK 0x0000e000 7462 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMP_RESERVED1_ALIGN 0 7463 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMP_RESERVED1_BITS 3 7464 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMP_RESERVED1_SHIFT 13 7465 7466 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DMP :: ADJ_EN [12:12] */ 7467 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMP_ADJ_EN_MASK 0x00001000 7468 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMP_ADJ_EN_ALIGN 0 7469 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMP_ADJ_EN_BITS 1 7470 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMP_ADJ_EN_SHIFT 12 7471 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMP_ADJ_EN_DEFAULT 0x00000000 7472 7473 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DMP :: reserved2 [11:08] */ 7474 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMP_RESERVED2_MASK 0x00000f00 7475 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMP_RESERVED2_ALIGN 0 7476 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMP_RESERVED2_BITS 4 7477 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMP_RESERVED2_SHIFT 8 7478 7479 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DMP :: VDL_STEP [07:00] */ 7480 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMP_VDL_STEP_MASK 0x000000ff 7481 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMP_VDL_STEP_ALIGN 0 7482 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMP_VDL_STEP_BITS 8 7483 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMP_VDL_STEP_SHIFT 0 7484 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMP_VDL_STEP_DEFAULT 0x00000000 7485 7486 /*************************************************************************** 7487 *VDL_CONTROL_RD_DMN - Read channel DM-N VDL control register 7488 */ 7489 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DMN :: BUSY [31:31] */ 7490 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMN_BUSY_MASK 0x80000000 7491 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMN_BUSY_ALIGN 0 7492 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMN_BUSY_BITS 1 7493 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMN_BUSY_SHIFT 31 7494 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMN_BUSY_DEFAULT 0x00000000 7495 7496 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DMN :: reserved0 [30:17] */ 7497 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMN_RESERVED0_MASK 0x7ffe0000 7498 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMN_RESERVED0_ALIGN 0 7499 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMN_RESERVED0_BITS 14 7500 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMN_RESERVED0_SHIFT 17 7501 7502 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DMN :: FORCE [16:16] */ 7503 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMN_FORCE_MASK 0x00010000 7504 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMN_FORCE_ALIGN 0 7505 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMN_FORCE_BITS 1 7506 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMN_FORCE_SHIFT 16 7507 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMN_FORCE_DEFAULT 0x00000000 7508 7509 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DMN :: reserved1 [15:13] */ 7510 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMN_RESERVED1_MASK 0x0000e000 7511 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMN_RESERVED1_ALIGN 0 7512 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMN_RESERVED1_BITS 3 7513 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMN_RESERVED1_SHIFT 13 7514 7515 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DMN :: ADJ_EN [12:12] */ 7516 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMN_ADJ_EN_MASK 0x00001000 7517 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMN_ADJ_EN_ALIGN 0 7518 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMN_ADJ_EN_BITS 1 7519 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMN_ADJ_EN_SHIFT 12 7520 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMN_ADJ_EN_DEFAULT 0x00000000 7521 7522 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DMN :: reserved2 [11:08] */ 7523 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMN_RESERVED2_MASK 0x00000f00 7524 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMN_RESERVED2_ALIGN 0 7525 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMN_RESERVED2_BITS 4 7526 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMN_RESERVED2_SHIFT 8 7527 7528 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DMN :: VDL_STEP [07:00] */ 7529 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMN_VDL_STEP_MASK 0x000000ff 7530 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMN_VDL_STEP_ALIGN 0 7531 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMN_VDL_STEP_BITS 8 7532 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMN_VDL_STEP_SHIFT 0 7533 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMN_VDL_STEP_DEFAULT 0x00000000 7534 7535 /*************************************************************************** 7536 *VDL_CONTROL_RD_EDCP - Read channel EDC-P VDL control register 7537 */ 7538 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_EDCP :: BUSY [31:31] */ 7539 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCP_BUSY_MASK 0x80000000 7540 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCP_BUSY_ALIGN 0 7541 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCP_BUSY_BITS 1 7542 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCP_BUSY_SHIFT 31 7543 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCP_BUSY_DEFAULT 0x00000000 7544 7545 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_EDCP :: reserved0 [30:17] */ 7546 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCP_RESERVED0_MASK 0x7ffe0000 7547 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCP_RESERVED0_ALIGN 0 7548 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCP_RESERVED0_BITS 14 7549 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCP_RESERVED0_SHIFT 17 7550 7551 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_EDCP :: FORCE [16:16] */ 7552 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCP_FORCE_MASK 0x00010000 7553 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCP_FORCE_ALIGN 0 7554 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCP_FORCE_BITS 1 7555 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCP_FORCE_SHIFT 16 7556 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCP_FORCE_DEFAULT 0x00000000 7557 7558 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_EDCP :: reserved1 [15:13] */ 7559 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCP_RESERVED1_MASK 0x0000e000 7560 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCP_RESERVED1_ALIGN 0 7561 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCP_RESERVED1_BITS 3 7562 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCP_RESERVED1_SHIFT 13 7563 7564 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_EDCP :: ADJ_EN [12:12] */ 7565 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCP_ADJ_EN_MASK 0x00001000 7566 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCP_ADJ_EN_ALIGN 0 7567 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCP_ADJ_EN_BITS 1 7568 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCP_ADJ_EN_SHIFT 12 7569 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCP_ADJ_EN_DEFAULT 0x00000000 7570 7571 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_EDCP :: reserved2 [11:08] */ 7572 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCP_RESERVED2_MASK 0x00000f00 7573 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCP_RESERVED2_ALIGN 0 7574 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCP_RESERVED2_BITS 4 7575 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCP_RESERVED2_SHIFT 8 7576 7577 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_EDCP :: VDL_STEP [07:00] */ 7578 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCP_VDL_STEP_MASK 0x000000ff 7579 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCP_VDL_STEP_ALIGN 0 7580 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCP_VDL_STEP_BITS 8 7581 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCP_VDL_STEP_SHIFT 0 7582 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCP_VDL_STEP_DEFAULT 0x00000000 7583 7584 /*************************************************************************** 7585 *VDL_CONTROL_RD_EDCN - Read channel EDC-N VDL control register 7586 */ 7587 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_EDCN :: BUSY [31:31] */ 7588 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCN_BUSY_MASK 0x80000000 7589 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCN_BUSY_ALIGN 0 7590 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCN_BUSY_BITS 1 7591 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCN_BUSY_SHIFT 31 7592 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCN_BUSY_DEFAULT 0x00000000 7593 7594 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_EDCN :: reserved0 [30:17] */ 7595 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCN_RESERVED0_MASK 0x7ffe0000 7596 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCN_RESERVED0_ALIGN 0 7597 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCN_RESERVED0_BITS 14 7598 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCN_RESERVED0_SHIFT 17 7599 7600 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_EDCN :: FORCE [16:16] */ 7601 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCN_FORCE_MASK 0x00010000 7602 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCN_FORCE_ALIGN 0 7603 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCN_FORCE_BITS 1 7604 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCN_FORCE_SHIFT 16 7605 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCN_FORCE_DEFAULT 0x00000000 7606 7607 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_EDCN :: reserved1 [15:13] */ 7608 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCN_RESERVED1_MASK 0x0000e000 7609 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCN_RESERVED1_ALIGN 0 7610 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCN_RESERVED1_BITS 3 7611 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCN_RESERVED1_SHIFT 13 7612 7613 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_EDCN :: ADJ_EN [12:12] */ 7614 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCN_ADJ_EN_MASK 0x00001000 7615 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCN_ADJ_EN_ALIGN 0 7616 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCN_ADJ_EN_BITS 1 7617 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCN_ADJ_EN_SHIFT 12 7618 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCN_ADJ_EN_DEFAULT 0x00000000 7619 7620 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_EDCN :: reserved2 [11:08] */ 7621 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCN_RESERVED2_MASK 0x00000f00 7622 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCN_RESERVED2_ALIGN 0 7623 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCN_RESERVED2_BITS 4 7624 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCN_RESERVED2_SHIFT 8 7625 7626 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_EDCN :: VDL_STEP [07:00] */ 7627 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCN_VDL_STEP_MASK 0x000000ff 7628 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCN_VDL_STEP_ALIGN 0 7629 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCN_VDL_STEP_BITS 8 7630 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCN_VDL_STEP_SHIFT 0 7631 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCN_VDL_STEP_DEFAULT 0x00000000 7632 7633 /*************************************************************************** 7634 *VDL_CONTROL_RD_EN_CS0 - Read channel CS_N[0] read enable VDL control register 7635 */ 7636 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_EN_CS0 :: BUSY [31:31] */ 7637 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0_BUSY_MASK 0x80000000 7638 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0_BUSY_ALIGN 0 7639 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0_BUSY_BITS 1 7640 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0_BUSY_SHIFT 31 7641 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0_BUSY_DEFAULT 0x00000000 7642 7643 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_EN_CS0 :: reserved0 [30:17] */ 7644 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0_RESERVED0_MASK 0x7ffe0000 7645 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0_RESERVED0_ALIGN 0 7646 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0_RESERVED0_BITS 14 7647 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0_RESERVED0_SHIFT 17 7648 7649 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_EN_CS0 :: FORCE [16:16] */ 7650 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0_FORCE_MASK 0x00010000 7651 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0_FORCE_ALIGN 0 7652 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0_FORCE_BITS 1 7653 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0_FORCE_SHIFT 16 7654 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0_FORCE_DEFAULT 0x00000000 7655 7656 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_EN_CS0 :: reserved1 [15:13] */ 7657 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0_RESERVED1_MASK 0x0000e000 7658 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0_RESERVED1_ALIGN 0 7659 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0_RESERVED1_BITS 3 7660 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0_RESERVED1_SHIFT 13 7661 7662 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_EN_CS0 :: ADJ_EN [12:12] */ 7663 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0_ADJ_EN_MASK 0x00001000 7664 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0_ADJ_EN_ALIGN 0 7665 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0_ADJ_EN_BITS 1 7666 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0_ADJ_EN_SHIFT 12 7667 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0_ADJ_EN_DEFAULT 0x00000000 7668 7669 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_EN_CS0 :: reserved2 [11:08] */ 7670 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0_RESERVED2_MASK 0x00000f00 7671 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0_RESERVED2_ALIGN 0 7672 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0_RESERVED2_BITS 4 7673 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0_RESERVED2_SHIFT 8 7674 7675 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_EN_CS0 :: VDL_STEP [07:00] */ 7676 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0_VDL_STEP_MASK 0x000000ff 7677 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0_VDL_STEP_ALIGN 0 7678 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0_VDL_STEP_BITS 8 7679 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0_VDL_STEP_SHIFT 0 7680 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0_VDL_STEP_DEFAULT 0x00000000 7681 7682 /*************************************************************************** 7683 *VDL_CONTROL_RD_EN_CS1 - Read channel CS_N[1] read enable VDL control register 7684 */ 7685 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_EN_CS1 :: BUSY [31:31] */ 7686 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1_BUSY_MASK 0x80000000 7687 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1_BUSY_ALIGN 0 7688 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1_BUSY_BITS 1 7689 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1_BUSY_SHIFT 31 7690 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1_BUSY_DEFAULT 0x00000000 7691 7692 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_EN_CS1 :: reserved0 [30:17] */ 7693 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1_RESERVED0_MASK 0x7ffe0000 7694 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1_RESERVED0_ALIGN 0 7695 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1_RESERVED0_BITS 14 7696 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1_RESERVED0_SHIFT 17 7697 7698 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_EN_CS1 :: FORCE [16:16] */ 7699 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1_FORCE_MASK 0x00010000 7700 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1_FORCE_ALIGN 0 7701 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1_FORCE_BITS 1 7702 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1_FORCE_SHIFT 16 7703 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1_FORCE_DEFAULT 0x00000000 7704 7705 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_EN_CS1 :: reserved1 [15:13] */ 7706 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1_RESERVED1_MASK 0x0000e000 7707 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1_RESERVED1_ALIGN 0 7708 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1_RESERVED1_BITS 3 7709 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1_RESERVED1_SHIFT 13 7710 7711 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_EN_CS1 :: ADJ_EN [12:12] */ 7712 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1_ADJ_EN_MASK 0x00001000 7713 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1_ADJ_EN_ALIGN 0 7714 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1_ADJ_EN_BITS 1 7715 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1_ADJ_EN_SHIFT 12 7716 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1_ADJ_EN_DEFAULT 0x00000000 7717 7718 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_EN_CS1 :: reserved2 [11:08] */ 7719 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1_RESERVED2_MASK 0x00000f00 7720 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1_RESERVED2_ALIGN 0 7721 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1_RESERVED2_BITS 4 7722 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1_RESERVED2_SHIFT 8 7723 7724 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_EN_CS1 :: VDL_STEP [07:00] */ 7725 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1_VDL_STEP_MASK 0x000000ff 7726 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1_VDL_STEP_ALIGN 0 7727 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1_VDL_STEP_BITS 8 7728 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1_VDL_STEP_SHIFT 0 7729 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1_VDL_STEP_DEFAULT 0x00000000 7730 7731 /*************************************************************************** 7732 *VDL_CLK_CONTROL - DDR interface signal Write Leveling CLK VDL control register 7733 */ 7734 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CLK_CONTROL :: BUSY [31:31] */ 7735 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CLK_CONTROL_BUSY_MASK 0x80000000 7736 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CLK_CONTROL_BUSY_ALIGN 0 7737 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CLK_CONTROL_BUSY_BITS 1 7738 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CLK_CONTROL_BUSY_SHIFT 31 7739 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CLK_CONTROL_BUSY_DEFAULT 0x00000000 7740 7741 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CLK_CONTROL :: reserved0 [30:17] */ 7742 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CLK_CONTROL_RESERVED0_MASK 0x7ffe0000 7743 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CLK_CONTROL_RESERVED0_ALIGN 0 7744 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CLK_CONTROL_RESERVED0_BITS 14 7745 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CLK_CONTROL_RESERVED0_SHIFT 17 7746 7747 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CLK_CONTROL :: FORCE [16:16] */ 7748 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CLK_CONTROL_FORCE_MASK 0x00010000 7749 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CLK_CONTROL_FORCE_ALIGN 0 7750 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CLK_CONTROL_FORCE_BITS 1 7751 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CLK_CONTROL_FORCE_SHIFT 16 7752 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CLK_CONTROL_FORCE_DEFAULT 0x00000000 7753 7754 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CLK_CONTROL :: reserved1 [15:13] */ 7755 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CLK_CONTROL_RESERVED1_MASK 0x0000e000 7756 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CLK_CONTROL_RESERVED1_ALIGN 0 7757 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CLK_CONTROL_RESERVED1_BITS 3 7758 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CLK_CONTROL_RESERVED1_SHIFT 13 7759 7760 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CLK_CONTROL :: ADJ_EN [12:12] */ 7761 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CLK_CONTROL_ADJ_EN_MASK 0x00001000 7762 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CLK_CONTROL_ADJ_EN_ALIGN 0 7763 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CLK_CONTROL_ADJ_EN_BITS 1 7764 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CLK_CONTROL_ADJ_EN_SHIFT 12 7765 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CLK_CONTROL_ADJ_EN_DEFAULT 0x00000000 7766 7767 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CLK_CONTROL :: reserved2 [11:09] */ 7768 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CLK_CONTROL_RESERVED2_MASK 0x00000e00 7769 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CLK_CONTROL_RESERVED2_ALIGN 0 7770 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CLK_CONTROL_RESERVED2_BITS 3 7771 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CLK_CONTROL_RESERVED2_SHIFT 9 7772 7773 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_CLK_CONTROL :: VDL_STEP [08:00] */ 7774 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CLK_CONTROL_VDL_STEP_MASK 0x000001ff 7775 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CLK_CONTROL_VDL_STEP_ALIGN 0 7776 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CLK_CONTROL_VDL_STEP_BITS 9 7777 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CLK_CONTROL_VDL_STEP_SHIFT 0 7778 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_CLK_CONTROL_VDL_STEP_DEFAULT 0x00000000 7779 7780 /*************************************************************************** 7781 *VDL_LDE_CONTROL - DDR interface signal Write Leveling Capture Enable VDL control register 7782 */ 7783 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_LDE_CONTROL :: BUSY [31:31] */ 7784 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_LDE_CONTROL_BUSY_MASK 0x80000000 7785 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_LDE_CONTROL_BUSY_ALIGN 0 7786 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_LDE_CONTROL_BUSY_BITS 1 7787 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_LDE_CONTROL_BUSY_SHIFT 31 7788 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_LDE_CONTROL_BUSY_DEFAULT 0x00000000 7789 7790 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_LDE_CONTROL :: reserved0 [30:17] */ 7791 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_LDE_CONTROL_RESERVED0_MASK 0x7ffe0000 7792 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_LDE_CONTROL_RESERVED0_ALIGN 0 7793 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_LDE_CONTROL_RESERVED0_BITS 14 7794 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_LDE_CONTROL_RESERVED0_SHIFT 17 7795 7796 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_LDE_CONTROL :: FORCE [16:16] */ 7797 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_LDE_CONTROL_FORCE_MASK 0x00010000 7798 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_LDE_CONTROL_FORCE_ALIGN 0 7799 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_LDE_CONTROL_FORCE_BITS 1 7800 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_LDE_CONTROL_FORCE_SHIFT 16 7801 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_LDE_CONTROL_FORCE_DEFAULT 0x00000000 7802 7803 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_LDE_CONTROL :: reserved1 [15:13] */ 7804 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_LDE_CONTROL_RESERVED1_MASK 0x0000e000 7805 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_LDE_CONTROL_RESERVED1_ALIGN 0 7806 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_LDE_CONTROL_RESERVED1_BITS 3 7807 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_LDE_CONTROL_RESERVED1_SHIFT 13 7808 7809 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_LDE_CONTROL :: ADJ_EN [12:12] */ 7810 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_LDE_CONTROL_ADJ_EN_MASK 0x00001000 7811 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_LDE_CONTROL_ADJ_EN_ALIGN 0 7812 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_LDE_CONTROL_ADJ_EN_BITS 1 7813 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_LDE_CONTROL_ADJ_EN_SHIFT 12 7814 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_LDE_CONTROL_ADJ_EN_DEFAULT 0x00000000 7815 7816 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_LDE_CONTROL :: reserved2 [11:09] */ 7817 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_LDE_CONTROL_RESERVED2_MASK 0x00000e00 7818 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_LDE_CONTROL_RESERVED2_ALIGN 0 7819 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_LDE_CONTROL_RESERVED2_BITS 3 7820 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_LDE_CONTROL_RESERVED2_SHIFT 9 7821 7822 /* DDR34_E0_PHY_BYTE_LANE_0 :: VDL_LDE_CONTROL :: VDL_STEP [08:00] */ 7823 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_LDE_CONTROL_VDL_STEP_MASK 0x000001ff 7824 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_LDE_CONTROL_VDL_STEP_ALIGN 0 7825 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_LDE_CONTROL_VDL_STEP_BITS 9 7826 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_LDE_CONTROL_VDL_STEP_SHIFT 0 7827 #define DDR34_E0_PHY_BYTE_LANE_0_VDL_LDE_CONTROL_VDL_STEP_DEFAULT 0x00000000 7828 7829 /*************************************************************************** 7830 *RD_EN_DLY_CYC - Read enable bit-clock cycle delay control register 7831 */ 7832 /* DDR34_E0_PHY_BYTE_LANE_0 :: RD_EN_DLY_CYC :: BUSY [31:31] */ 7833 #define DDR34_E0_PHY_BYTE_LANE_0_RD_EN_DLY_CYC_BUSY_MASK 0x80000000 7834 #define DDR34_E0_PHY_BYTE_LANE_0_RD_EN_DLY_CYC_BUSY_ALIGN 0 7835 #define DDR34_E0_PHY_BYTE_LANE_0_RD_EN_DLY_CYC_BUSY_BITS 1 7836 #define DDR34_E0_PHY_BYTE_LANE_0_RD_EN_DLY_CYC_BUSY_SHIFT 31 7837 #define DDR34_E0_PHY_BYTE_LANE_0_RD_EN_DLY_CYC_BUSY_DEFAULT 0x00000000 7838 7839 /* DDR34_E0_PHY_BYTE_LANE_0 :: RD_EN_DLY_CYC :: reserved0 [30:17] */ 7840 #define DDR34_E0_PHY_BYTE_LANE_0_RD_EN_DLY_CYC_RESERVED0_MASK 0x7ffe0000 7841 #define DDR34_E0_PHY_BYTE_LANE_0_RD_EN_DLY_CYC_RESERVED0_ALIGN 0 7842 #define DDR34_E0_PHY_BYTE_LANE_0_RD_EN_DLY_CYC_RESERVED0_BITS 14 7843 #define DDR34_E0_PHY_BYTE_LANE_0_RD_EN_DLY_CYC_RESERVED0_SHIFT 17 7844 7845 /* DDR34_E0_PHY_BYTE_LANE_0 :: RD_EN_DLY_CYC :: FORCE [16:16] */ 7846 #define DDR34_E0_PHY_BYTE_LANE_0_RD_EN_DLY_CYC_FORCE_MASK 0x00010000 7847 #define DDR34_E0_PHY_BYTE_LANE_0_RD_EN_DLY_CYC_FORCE_ALIGN 0 7848 #define DDR34_E0_PHY_BYTE_LANE_0_RD_EN_DLY_CYC_FORCE_BITS 1 7849 #define DDR34_E0_PHY_BYTE_LANE_0_RD_EN_DLY_CYC_FORCE_SHIFT 16 7850 #define DDR34_E0_PHY_BYTE_LANE_0_RD_EN_DLY_CYC_FORCE_DEFAULT 0x00000000 7851 7852 /* DDR34_E0_PHY_BYTE_LANE_0 :: RD_EN_DLY_CYC :: reserved1 [15:08] */ 7853 #define DDR34_E0_PHY_BYTE_LANE_0_RD_EN_DLY_CYC_RESERVED1_MASK 0x0000ff00 7854 #define DDR34_E0_PHY_BYTE_LANE_0_RD_EN_DLY_CYC_RESERVED1_ALIGN 0 7855 #define DDR34_E0_PHY_BYTE_LANE_0_RD_EN_DLY_CYC_RESERVED1_BITS 8 7856 #define DDR34_E0_PHY_BYTE_LANE_0_RD_EN_DLY_CYC_RESERVED1_SHIFT 8 7857 7858 /* DDR34_E0_PHY_BYTE_LANE_0 :: RD_EN_DLY_CYC :: CS1_CYCLES [07:04] */ 7859 #define DDR34_E0_PHY_BYTE_LANE_0_RD_EN_DLY_CYC_CS1_CYCLES_MASK 0x000000f0 7860 #define DDR34_E0_PHY_BYTE_LANE_0_RD_EN_DLY_CYC_CS1_CYCLES_ALIGN 0 7861 #define DDR34_E0_PHY_BYTE_LANE_0_RD_EN_DLY_CYC_CS1_CYCLES_BITS 4 7862 #define DDR34_E0_PHY_BYTE_LANE_0_RD_EN_DLY_CYC_CS1_CYCLES_SHIFT 4 7863 #define DDR34_E0_PHY_BYTE_LANE_0_RD_EN_DLY_CYC_CS1_CYCLES_DEFAULT 0x00000000 7864 7865 /* DDR34_E0_PHY_BYTE_LANE_0 :: RD_EN_DLY_CYC :: CS0_CYCLES [03:00] */ 7866 #define DDR34_E0_PHY_BYTE_LANE_0_RD_EN_DLY_CYC_CS0_CYCLES_MASK 0x0000000f 7867 #define DDR34_E0_PHY_BYTE_LANE_0_RD_EN_DLY_CYC_CS0_CYCLES_ALIGN 0 7868 #define DDR34_E0_PHY_BYTE_LANE_0_RD_EN_DLY_CYC_CS0_CYCLES_BITS 4 7869 #define DDR34_E0_PHY_BYTE_LANE_0_RD_EN_DLY_CYC_CS0_CYCLES_SHIFT 0 7870 #define DDR34_E0_PHY_BYTE_LANE_0_RD_EN_DLY_CYC_CS0_CYCLES_DEFAULT 0x00000000 7871 7872 /*************************************************************************** 7873 *WR_CHAN_DLY_CYC - Write leveling bit-clock cycle delay control register 7874 */ 7875 /* DDR34_E0_PHY_BYTE_LANE_0 :: WR_CHAN_DLY_CYC :: BUSY [31:31] */ 7876 #define DDR34_E0_PHY_BYTE_LANE_0_WR_CHAN_DLY_CYC_BUSY_MASK 0x80000000 7877 #define DDR34_E0_PHY_BYTE_LANE_0_WR_CHAN_DLY_CYC_BUSY_ALIGN 0 7878 #define DDR34_E0_PHY_BYTE_LANE_0_WR_CHAN_DLY_CYC_BUSY_BITS 1 7879 #define DDR34_E0_PHY_BYTE_LANE_0_WR_CHAN_DLY_CYC_BUSY_SHIFT 31 7880 #define DDR34_E0_PHY_BYTE_LANE_0_WR_CHAN_DLY_CYC_BUSY_DEFAULT 0x00000000 7881 7882 /* DDR34_E0_PHY_BYTE_LANE_0 :: WR_CHAN_DLY_CYC :: reserved0 [30:17] */ 7883 #define DDR34_E0_PHY_BYTE_LANE_0_WR_CHAN_DLY_CYC_RESERVED0_MASK 0x7ffe0000 7884 #define DDR34_E0_PHY_BYTE_LANE_0_WR_CHAN_DLY_CYC_RESERVED0_ALIGN 0 7885 #define DDR34_E0_PHY_BYTE_LANE_0_WR_CHAN_DLY_CYC_RESERVED0_BITS 14 7886 #define DDR34_E0_PHY_BYTE_LANE_0_WR_CHAN_DLY_CYC_RESERVED0_SHIFT 17 7887 7888 /* DDR34_E0_PHY_BYTE_LANE_0 :: WR_CHAN_DLY_CYC :: FORCE [16:16] */ 7889 #define DDR34_E0_PHY_BYTE_LANE_0_WR_CHAN_DLY_CYC_FORCE_MASK 0x00010000 7890 #define DDR34_E0_PHY_BYTE_LANE_0_WR_CHAN_DLY_CYC_FORCE_ALIGN 0 7891 #define DDR34_E0_PHY_BYTE_LANE_0_WR_CHAN_DLY_CYC_FORCE_BITS 1 7892 #define DDR34_E0_PHY_BYTE_LANE_0_WR_CHAN_DLY_CYC_FORCE_SHIFT 16 7893 #define DDR34_E0_PHY_BYTE_LANE_0_WR_CHAN_DLY_CYC_FORCE_DEFAULT 0x00000000 7894 7895 /* DDR34_E0_PHY_BYTE_LANE_0 :: WR_CHAN_DLY_CYC :: reserved1 [15:03] */ 7896 #define DDR34_E0_PHY_BYTE_LANE_0_WR_CHAN_DLY_CYC_RESERVED1_MASK 0x0000fff8 7897 #define DDR34_E0_PHY_BYTE_LANE_0_WR_CHAN_DLY_CYC_RESERVED1_ALIGN 0 7898 #define DDR34_E0_PHY_BYTE_LANE_0_WR_CHAN_DLY_CYC_RESERVED1_BITS 13 7899 #define DDR34_E0_PHY_BYTE_LANE_0_WR_CHAN_DLY_CYC_RESERVED1_SHIFT 3 7900 7901 /* DDR34_E0_PHY_BYTE_LANE_0 :: WR_CHAN_DLY_CYC :: CYCLES [02:00] */ 7902 #define DDR34_E0_PHY_BYTE_LANE_0_WR_CHAN_DLY_CYC_CYCLES_MASK 0x00000007 7903 #define DDR34_E0_PHY_BYTE_LANE_0_WR_CHAN_DLY_CYC_CYCLES_ALIGN 0 7904 #define DDR34_E0_PHY_BYTE_LANE_0_WR_CHAN_DLY_CYC_CYCLES_BITS 3 7905 #define DDR34_E0_PHY_BYTE_LANE_0_WR_CHAN_DLY_CYC_CYCLES_SHIFT 0 7906 #define DDR34_E0_PHY_BYTE_LANE_0_WR_CHAN_DLY_CYC_CYCLES_DEFAULT 0x00000000 7907 7908 /*************************************************************************** 7909 *READ_CONTROL - Read channel datapath control register 7910 */ 7911 /* DDR34_E0_PHY_BYTE_LANE_0 :: READ_CONTROL :: reserved0 [31:05] */ 7912 #define DDR34_E0_PHY_BYTE_LANE_0_READ_CONTROL_RESERVED0_MASK 0xffffffe0 7913 #define DDR34_E0_PHY_BYTE_LANE_0_READ_CONTROL_RESERVED0_ALIGN 0 7914 #define DDR34_E0_PHY_BYTE_LANE_0_READ_CONTROL_RESERVED0_BITS 27 7915 #define DDR34_E0_PHY_BYTE_LANE_0_READ_CONTROL_RESERVED0_SHIFT 5 7916 7917 /* DDR34_E0_PHY_BYTE_LANE_0 :: READ_CONTROL :: MODE [04:04] */ 7918 #define DDR34_E0_PHY_BYTE_LANE_0_READ_CONTROL_MODE_MASK 0x00000010 7919 #define DDR34_E0_PHY_BYTE_LANE_0_READ_CONTROL_MODE_ALIGN 0 7920 #define DDR34_E0_PHY_BYTE_LANE_0_READ_CONTROL_MODE_BITS 1 7921 #define DDR34_E0_PHY_BYTE_LANE_0_READ_CONTROL_MODE_SHIFT 4 7922 #define DDR34_E0_PHY_BYTE_LANE_0_READ_CONTROL_MODE_DEFAULT 0x00000001 7923 7924 /* DDR34_E0_PHY_BYTE_LANE_0 :: READ_CONTROL :: reserved1 [03:03] */ 7925 #define DDR34_E0_PHY_BYTE_LANE_0_READ_CONTROL_RESERVED1_MASK 0x00000008 7926 #define DDR34_E0_PHY_BYTE_LANE_0_READ_CONTROL_RESERVED1_ALIGN 0 7927 #define DDR34_E0_PHY_BYTE_LANE_0_READ_CONTROL_RESERVED1_BITS 1 7928 #define DDR34_E0_PHY_BYTE_LANE_0_READ_CONTROL_RESERVED1_SHIFT 3 7929 7930 /* DDR34_E0_PHY_BYTE_LANE_0 :: READ_CONTROL :: RD_DATA_DLY [02:00] */ 7931 #define DDR34_E0_PHY_BYTE_LANE_0_READ_CONTROL_RD_DATA_DLY_MASK 0x00000007 7932 #define DDR34_E0_PHY_BYTE_LANE_0_READ_CONTROL_RD_DATA_DLY_ALIGN 0 7933 #define DDR34_E0_PHY_BYTE_LANE_0_READ_CONTROL_RD_DATA_DLY_BITS 3 7934 #define DDR34_E0_PHY_BYTE_LANE_0_READ_CONTROL_RD_DATA_DLY_SHIFT 0 7935 #define DDR34_E0_PHY_BYTE_LANE_0_READ_CONTROL_RD_DATA_DLY_DEFAULT 0x00000007 7936 7937 /*************************************************************************** 7938 *READ_FIFO_ADDR - Read fifo addresss pointer register 7939 */ 7940 /* DDR34_E0_PHY_BYTE_LANE_0 :: READ_FIFO_ADDR :: reserved0 [31:03] */ 7941 #define DDR34_E0_PHY_BYTE_LANE_0_READ_FIFO_ADDR_RESERVED0_MASK 0xfffffff8 7942 #define DDR34_E0_PHY_BYTE_LANE_0_READ_FIFO_ADDR_RESERVED0_ALIGN 0 7943 #define DDR34_E0_PHY_BYTE_LANE_0_READ_FIFO_ADDR_RESERVED0_BITS 29 7944 #define DDR34_E0_PHY_BYTE_LANE_0_READ_FIFO_ADDR_RESERVED0_SHIFT 3 7945 7946 /* DDR34_E0_PHY_BYTE_LANE_0 :: READ_FIFO_ADDR :: ADDR [02:00] */ 7947 #define DDR34_E0_PHY_BYTE_LANE_0_READ_FIFO_ADDR_ADDR_MASK 0x00000007 7948 #define DDR34_E0_PHY_BYTE_LANE_0_READ_FIFO_ADDR_ADDR_ALIGN 0 7949 #define DDR34_E0_PHY_BYTE_LANE_0_READ_FIFO_ADDR_ADDR_BITS 3 7950 #define DDR34_E0_PHY_BYTE_LANE_0_READ_FIFO_ADDR_ADDR_SHIFT 0 7951 #define DDR34_E0_PHY_BYTE_LANE_0_READ_FIFO_ADDR_ADDR_DEFAULT 0x00000000 7952 7953 /*************************************************************************** 7954 *READ_FIFO_DATA - Read fifo data register 7955 */ 7956 /* DDR34_E0_PHY_BYTE_LANE_0 :: READ_FIFO_DATA :: DATA [31:00] */ 7957 #define DDR34_E0_PHY_BYTE_LANE_0_READ_FIFO_DATA_DATA_MASK 0xffffffff 7958 #define DDR34_E0_PHY_BYTE_LANE_0_READ_FIFO_DATA_DATA_ALIGN 0 7959 #define DDR34_E0_PHY_BYTE_LANE_0_READ_FIFO_DATA_DATA_BITS 32 7960 #define DDR34_E0_PHY_BYTE_LANE_0_READ_FIFO_DATA_DATA_SHIFT 0 7961 7962 /*************************************************************************** 7963 *READ_FIFO_DM_DBI - Read fifo dm/dbi register 7964 */ 7965 /* DDR34_E0_PHY_BYTE_LANE_0 :: READ_FIFO_DM_DBI :: reserved0 [31:04] */ 7966 #define DDR34_E0_PHY_BYTE_LANE_0_READ_FIFO_DM_DBI_RESERVED0_MASK 0xfffffff0 7967 #define DDR34_E0_PHY_BYTE_LANE_0_READ_FIFO_DM_DBI_RESERVED0_ALIGN 0 7968 #define DDR34_E0_PHY_BYTE_LANE_0_READ_FIFO_DM_DBI_RESERVED0_BITS 28 7969 #define DDR34_E0_PHY_BYTE_LANE_0_READ_FIFO_DM_DBI_RESERVED0_SHIFT 4 7970 7971 /* DDR34_E0_PHY_BYTE_LANE_0 :: READ_FIFO_DM_DBI :: DM_DBI [03:00] */ 7972 #define DDR34_E0_PHY_BYTE_LANE_0_READ_FIFO_DM_DBI_DM_DBI_MASK 0x0000000f 7973 #define DDR34_E0_PHY_BYTE_LANE_0_READ_FIFO_DM_DBI_DM_DBI_ALIGN 0 7974 #define DDR34_E0_PHY_BYTE_LANE_0_READ_FIFO_DM_DBI_DM_DBI_BITS 4 7975 #define DDR34_E0_PHY_BYTE_LANE_0_READ_FIFO_DM_DBI_DM_DBI_SHIFT 0 7976 7977 /*************************************************************************** 7978 *READ_FIFO_STATUS - Read fifo status register 7979 */ 7980 /* DDR34_E0_PHY_BYTE_LANE_0 :: READ_FIFO_STATUS :: reserved0 [31:02] */ 7981 #define DDR34_E0_PHY_BYTE_LANE_0_READ_FIFO_STATUS_RESERVED0_MASK 0xfffffffc 7982 #define DDR34_E0_PHY_BYTE_LANE_0_READ_FIFO_STATUS_RESERVED0_ALIGN 0 7983 #define DDR34_E0_PHY_BYTE_LANE_0_READ_FIFO_STATUS_RESERVED0_BITS 30 7984 #define DDR34_E0_PHY_BYTE_LANE_0_READ_FIFO_STATUS_RESERVED0_SHIFT 2 7985 7986 /* DDR34_E0_PHY_BYTE_LANE_0 :: READ_FIFO_STATUS :: OVERFLOW [01:01] */ 7987 #define DDR34_E0_PHY_BYTE_LANE_0_READ_FIFO_STATUS_OVERFLOW_MASK 0x00000002 7988 #define DDR34_E0_PHY_BYTE_LANE_0_READ_FIFO_STATUS_OVERFLOW_ALIGN 0 7989 #define DDR34_E0_PHY_BYTE_LANE_0_READ_FIFO_STATUS_OVERFLOW_BITS 1 7990 #define DDR34_E0_PHY_BYTE_LANE_0_READ_FIFO_STATUS_OVERFLOW_SHIFT 1 7991 #define DDR34_E0_PHY_BYTE_LANE_0_READ_FIFO_STATUS_OVERFLOW_DEFAULT 0x00000000 7992 7993 /* DDR34_E0_PHY_BYTE_LANE_0 :: READ_FIFO_STATUS :: UNDERFLOW [00:00] */ 7994 #define DDR34_E0_PHY_BYTE_LANE_0_READ_FIFO_STATUS_UNDERFLOW_MASK 0x00000001 7995 #define DDR34_E0_PHY_BYTE_LANE_0_READ_FIFO_STATUS_UNDERFLOW_ALIGN 0 7996 #define DDR34_E0_PHY_BYTE_LANE_0_READ_FIFO_STATUS_UNDERFLOW_BITS 1 7997 #define DDR34_E0_PHY_BYTE_LANE_0_READ_FIFO_STATUS_UNDERFLOW_SHIFT 0 7998 #define DDR34_E0_PHY_BYTE_LANE_0_READ_FIFO_STATUS_UNDERFLOW_DEFAULT 0x00000000 7999 8000 /*************************************************************************** 8001 *READ_FIFO_CLEAR - Read fifo status clear register 8002 */ 8003 /* DDR34_E0_PHY_BYTE_LANE_0 :: READ_FIFO_CLEAR :: reserved0 [31:01] */ 8004 #define DDR34_E0_PHY_BYTE_LANE_0_READ_FIFO_CLEAR_RESERVED0_MASK 0xfffffffe 8005 #define DDR34_E0_PHY_BYTE_LANE_0_READ_FIFO_CLEAR_RESERVED0_ALIGN 0 8006 #define DDR34_E0_PHY_BYTE_LANE_0_READ_FIFO_CLEAR_RESERVED0_BITS 31 8007 #define DDR34_E0_PHY_BYTE_LANE_0_READ_FIFO_CLEAR_RESERVED0_SHIFT 1 8008 8009 /* DDR34_E0_PHY_BYTE_LANE_0 :: READ_FIFO_CLEAR :: CLEAR [00:00] */ 8010 #define DDR34_E0_PHY_BYTE_LANE_0_READ_FIFO_CLEAR_CLEAR_MASK 0x00000001 8011 #define DDR34_E0_PHY_BYTE_LANE_0_READ_FIFO_CLEAR_CLEAR_ALIGN 0 8012 #define DDR34_E0_PHY_BYTE_LANE_0_READ_FIFO_CLEAR_CLEAR_BITS 1 8013 #define DDR34_E0_PHY_BYTE_LANE_0_READ_FIFO_CLEAR_CLEAR_SHIFT 0 8014 #define DDR34_E0_PHY_BYTE_LANE_0_READ_FIFO_CLEAR_CLEAR_DEFAULT 0x00000000 8015 8016 /*************************************************************************** 8017 *IDLE_PAD_CONTROL - Idle mode SSTL pad control register 8018 */ 8019 /* DDR34_E0_PHY_BYTE_LANE_0 :: IDLE_PAD_CONTROL :: IDLE [31:31] */ 8020 #define DDR34_E0_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_IDLE_MASK 0x80000000 8021 #define DDR34_E0_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_IDLE_ALIGN 0 8022 #define DDR34_E0_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_IDLE_BITS 1 8023 #define DDR34_E0_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_IDLE_SHIFT 31 8024 #define DDR34_E0_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_IDLE_DEFAULT 0x00000000 8025 8026 /* DDR34_E0_PHY_BYTE_LANE_0 :: IDLE_PAD_CONTROL :: reserved0 [30:20] */ 8027 #define DDR34_E0_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_RESERVED0_MASK 0x7ff00000 8028 #define DDR34_E0_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_RESERVED0_ALIGN 0 8029 #define DDR34_E0_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_RESERVED0_BITS 11 8030 #define DDR34_E0_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_RESERVED0_SHIFT 20 8031 8032 /* DDR34_E0_PHY_BYTE_LANE_0 :: IDLE_PAD_CONTROL :: AUTO_DQ_RXENB_MODE [19:18] */ 8033 #define DDR34_E0_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_AUTO_DQ_RXENB_MODE_MASK 0x000c0000 8034 #define DDR34_E0_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_AUTO_DQ_RXENB_MODE_ALIGN 0 8035 #define DDR34_E0_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_AUTO_DQ_RXENB_MODE_BITS 2 8036 #define DDR34_E0_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_AUTO_DQ_RXENB_MODE_SHIFT 18 8037 #define DDR34_E0_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_AUTO_DQ_RXENB_MODE_DEFAULT 0x00000001 8038 8039 /* DDR34_E0_PHY_BYTE_LANE_0 :: IDLE_PAD_CONTROL :: AUTO_DQ_IDDQ_MODE [17:16] */ 8040 #define DDR34_E0_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_AUTO_DQ_IDDQ_MODE_MASK 0x00030000 8041 #define DDR34_E0_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_AUTO_DQ_IDDQ_MODE_ALIGN 0 8042 #define DDR34_E0_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_AUTO_DQ_IDDQ_MODE_BITS 2 8043 #define DDR34_E0_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_AUTO_DQ_IDDQ_MODE_SHIFT 16 8044 #define DDR34_E0_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_AUTO_DQ_IDDQ_MODE_DEFAULT 0x00000001 8045 8046 /* DDR34_E0_PHY_BYTE_LANE_0 :: IDLE_PAD_CONTROL :: reserved_for_padding1 [15:15] */ 8047 #define DDR34_E0_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_RESERVED_for_padding1_MASK 0x00008000 8048 #define DDR34_E0_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_RESERVED_for_padding1_ALIGN 0 8049 #define DDR34_E0_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_RESERVED_for_padding1_BITS 1 8050 #define DDR34_E0_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_RESERVED_for_padding1_SHIFT 15 8051 8052 /* DDR34_E0_PHY_BYTE_LANE_0 :: IDLE_PAD_CONTROL :: IO_IDLE_ENABLE [14:04] */ 8053 #define DDR34_E0_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_IO_IDLE_ENABLE_MASK 0x00007ff0 8054 #define DDR34_E0_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_IO_IDLE_ENABLE_ALIGN 0 8055 #define DDR34_E0_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_IO_IDLE_ENABLE_BITS 11 8056 #define DDR34_E0_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_IO_IDLE_ENABLE_SHIFT 4 8057 #define DDR34_E0_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_IO_IDLE_ENABLE_DEFAULT 0x00000000 8058 8059 /* DDR34_E0_PHY_BYTE_LANE_0 :: IDLE_PAD_CONTROL :: RXENB [03:03] */ 8060 #define DDR34_E0_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_RXENB_MASK 0x00000008 8061 #define DDR34_E0_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_RXENB_ALIGN 0 8062 #define DDR34_E0_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_RXENB_BITS 1 8063 #define DDR34_E0_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_RXENB_SHIFT 3 8064 #define DDR34_E0_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_RXENB_DEFAULT 0x00000001 8065 8066 /* DDR34_E0_PHY_BYTE_LANE_0 :: IDLE_PAD_CONTROL :: IDDQ [02:02] */ 8067 #define DDR34_E0_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_IDDQ_MASK 0x00000004 8068 #define DDR34_E0_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_IDDQ_ALIGN 0 8069 #define DDR34_E0_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_IDDQ_BITS 1 8070 #define DDR34_E0_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_IDDQ_SHIFT 2 8071 #define DDR34_E0_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_IDDQ_DEFAULT 0x00000000 8072 8073 /* DDR34_E0_PHY_BYTE_LANE_0 :: IDLE_PAD_CONTROL :: DOUT_N [01:01] */ 8074 #define DDR34_E0_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_DOUT_N_MASK 0x00000002 8075 #define DDR34_E0_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_DOUT_N_ALIGN 0 8076 #define DDR34_E0_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_DOUT_N_BITS 1 8077 #define DDR34_E0_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_DOUT_N_SHIFT 1 8078 #define DDR34_E0_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_DOUT_N_DEFAULT 0x00000001 8079 8080 /* DDR34_E0_PHY_BYTE_LANE_0 :: IDLE_PAD_CONTROL :: DOUT_P [00:00] */ 8081 #define DDR34_E0_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_DOUT_P_MASK 0x00000001 8082 #define DDR34_E0_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_DOUT_P_ALIGN 0 8083 #define DDR34_E0_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_DOUT_P_BITS 1 8084 #define DDR34_E0_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_DOUT_P_SHIFT 0 8085 #define DDR34_E0_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_DOUT_P_DEFAULT 0x00000000 8086 8087 /*************************************************************************** 8088 *DRIVE_PAD_CTL - SSTL pad drive characteristics control register 8089 */ 8090 /* DDR34_E0_PHY_BYTE_LANE_0 :: DRIVE_PAD_CTL :: reserved0 [31:30] */ 8091 #define DDR34_E0_PHY_BYTE_LANE_0_DRIVE_PAD_CTL_RESERVED0_MASK 0xc0000000 8092 #define DDR34_E0_PHY_BYTE_LANE_0_DRIVE_PAD_CTL_RESERVED0_ALIGN 0 8093 #define DDR34_E0_PHY_BYTE_LANE_0_DRIVE_PAD_CTL_RESERVED0_BITS 2 8094 #define DDR34_E0_PHY_BYTE_LANE_0_DRIVE_PAD_CTL_RESERVED0_SHIFT 30 8095 8096 /* DDR34_E0_PHY_BYTE_LANE_0 :: DRIVE_PAD_CTL :: BL_PD_IDLE_STRENGTH [29:25] */ 8097 #define DDR34_E0_PHY_BYTE_LANE_0_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_MASK 0x3e000000 8098 #define DDR34_E0_PHY_BYTE_LANE_0_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_ALIGN 0 8099 #define DDR34_E0_PHY_BYTE_LANE_0_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_BITS 5 8100 #define DDR34_E0_PHY_BYTE_LANE_0_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_SHIFT 25 8101 #define DDR34_E0_PHY_BYTE_LANE_0_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_DEFAULT 0x0000001f 8102 8103 /* DDR34_E0_PHY_BYTE_LANE_0 :: DRIVE_PAD_CTL :: BL_ND_IDLE_STRENGTH [24:20] */ 8104 #define DDR34_E0_PHY_BYTE_LANE_0_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_MASK 0x01f00000 8105 #define DDR34_E0_PHY_BYTE_LANE_0_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_ALIGN 0 8106 #define DDR34_E0_PHY_BYTE_LANE_0_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_BITS 5 8107 #define DDR34_E0_PHY_BYTE_LANE_0_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_SHIFT 20 8108 #define DDR34_E0_PHY_BYTE_LANE_0_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_DEFAULT 0x0000001f 8109 8110 /* DDR34_E0_PHY_BYTE_LANE_0 :: DRIVE_PAD_CTL :: BL_PD_TERM_STRENGTH [19:15] */ 8111 #define DDR34_E0_PHY_BYTE_LANE_0_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_MASK 0x000f8000 8112 #define DDR34_E0_PHY_BYTE_LANE_0_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_ALIGN 0 8113 #define DDR34_E0_PHY_BYTE_LANE_0_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_BITS 5 8114 #define DDR34_E0_PHY_BYTE_LANE_0_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_SHIFT 15 8115 #define DDR34_E0_PHY_BYTE_LANE_0_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_DEFAULT 0x00000006 8116 8117 /* DDR34_E0_PHY_BYTE_LANE_0 :: DRIVE_PAD_CTL :: BL_ND_TERM_STRENGTH [14:10] */ 8118 #define DDR34_E0_PHY_BYTE_LANE_0_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_MASK 0x00007c00 8119 #define DDR34_E0_PHY_BYTE_LANE_0_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_ALIGN 0 8120 #define DDR34_E0_PHY_BYTE_LANE_0_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_BITS 5 8121 #define DDR34_E0_PHY_BYTE_LANE_0_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_SHIFT 10 8122 #define DDR34_E0_PHY_BYTE_LANE_0_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_DEFAULT 0x00000006 8123 8124 /* DDR34_E0_PHY_BYTE_LANE_0 :: DRIVE_PAD_CTL :: BL_PD_STRENGTH [09:05] */ 8125 #define DDR34_E0_PHY_BYTE_LANE_0_DRIVE_PAD_CTL_BL_PD_STRENGTH_MASK 0x000003e0 8126 #define DDR34_E0_PHY_BYTE_LANE_0_DRIVE_PAD_CTL_BL_PD_STRENGTH_ALIGN 0 8127 #define DDR34_E0_PHY_BYTE_LANE_0_DRIVE_PAD_CTL_BL_PD_STRENGTH_BITS 5 8128 #define DDR34_E0_PHY_BYTE_LANE_0_DRIVE_PAD_CTL_BL_PD_STRENGTH_SHIFT 5 8129 #define DDR34_E0_PHY_BYTE_LANE_0_DRIVE_PAD_CTL_BL_PD_STRENGTH_DEFAULT 0x0000001f 8130 8131 /* DDR34_E0_PHY_BYTE_LANE_0 :: DRIVE_PAD_CTL :: BL_ND_STRENGTH [04:00] */ 8132 #define DDR34_E0_PHY_BYTE_LANE_0_DRIVE_PAD_CTL_BL_ND_STRENGTH_MASK 0x0000001f 8133 #define DDR34_E0_PHY_BYTE_LANE_0_DRIVE_PAD_CTL_BL_ND_STRENGTH_ALIGN 0 8134 #define DDR34_E0_PHY_BYTE_LANE_0_DRIVE_PAD_CTL_BL_ND_STRENGTH_BITS 5 8135 #define DDR34_E0_PHY_BYTE_LANE_0_DRIVE_PAD_CTL_BL_ND_STRENGTH_SHIFT 0 8136 #define DDR34_E0_PHY_BYTE_LANE_0_DRIVE_PAD_CTL_BL_ND_STRENGTH_DEFAULT 0x0000001f 8137 8138 /*************************************************************************** 8139 *RD_EN_DRIVE_PAD_CTL - SSTL read enable pad drive characteristics control register 8140 */ 8141 /* DDR34_E0_PHY_BYTE_LANE_0 :: RD_EN_DRIVE_PAD_CTL :: reserved0 [31:20] */ 8142 #define DDR34_E0_PHY_BYTE_LANE_0_RD_EN_DRIVE_PAD_CTL_RESERVED0_MASK 0xfff00000 8143 #define DDR34_E0_PHY_BYTE_LANE_0_RD_EN_DRIVE_PAD_CTL_RESERVED0_ALIGN 0 8144 #define DDR34_E0_PHY_BYTE_LANE_0_RD_EN_DRIVE_PAD_CTL_RESERVED0_BITS 12 8145 #define DDR34_E0_PHY_BYTE_LANE_0_RD_EN_DRIVE_PAD_CTL_RESERVED0_SHIFT 20 8146 8147 /* DDR34_E0_PHY_BYTE_LANE_0 :: RD_EN_DRIVE_PAD_CTL :: EDC_RD_EN_PD_STRENGTH [19:15] */ 8148 #define DDR34_E0_PHY_BYTE_LANE_0_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_PD_STRENGTH_MASK 0x000f8000 8149 #define DDR34_E0_PHY_BYTE_LANE_0_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_PD_STRENGTH_ALIGN 0 8150 #define DDR34_E0_PHY_BYTE_LANE_0_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_PD_STRENGTH_BITS 5 8151 #define DDR34_E0_PHY_BYTE_LANE_0_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_PD_STRENGTH_SHIFT 15 8152 #define DDR34_E0_PHY_BYTE_LANE_0_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_PD_STRENGTH_DEFAULT 0x0000001f 8153 8154 /* DDR34_E0_PHY_BYTE_LANE_0 :: RD_EN_DRIVE_PAD_CTL :: EDC_RD_EN_ND_STRENGTH [14:10] */ 8155 #define DDR34_E0_PHY_BYTE_LANE_0_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_ND_STRENGTH_MASK 0x00007c00 8156 #define DDR34_E0_PHY_BYTE_LANE_0_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_ND_STRENGTH_ALIGN 0 8157 #define DDR34_E0_PHY_BYTE_LANE_0_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_ND_STRENGTH_BITS 5 8158 #define DDR34_E0_PHY_BYTE_LANE_0_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_ND_STRENGTH_SHIFT 10 8159 #define DDR34_E0_PHY_BYTE_LANE_0_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_ND_STRENGTH_DEFAULT 0x0000001f 8160 8161 /* DDR34_E0_PHY_BYTE_LANE_0 :: RD_EN_DRIVE_PAD_CTL :: BL_RD_EN_PD_STRENGTH [09:05] */ 8162 #define DDR34_E0_PHY_BYTE_LANE_0_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_PD_STRENGTH_MASK 0x000003e0 8163 #define DDR34_E0_PHY_BYTE_LANE_0_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_PD_STRENGTH_ALIGN 0 8164 #define DDR34_E0_PHY_BYTE_LANE_0_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_PD_STRENGTH_BITS 5 8165 #define DDR34_E0_PHY_BYTE_LANE_0_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_PD_STRENGTH_SHIFT 5 8166 #define DDR34_E0_PHY_BYTE_LANE_0_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_PD_STRENGTH_DEFAULT 0x0000001f 8167 8168 /* DDR34_E0_PHY_BYTE_LANE_0 :: RD_EN_DRIVE_PAD_CTL :: BL_RD_EN_ND_STRENGTH [04:00] */ 8169 #define DDR34_E0_PHY_BYTE_LANE_0_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_ND_STRENGTH_MASK 0x0000001f 8170 #define DDR34_E0_PHY_BYTE_LANE_0_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_ND_STRENGTH_ALIGN 0 8171 #define DDR34_E0_PHY_BYTE_LANE_0_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_ND_STRENGTH_BITS 5 8172 #define DDR34_E0_PHY_BYTE_LANE_0_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_ND_STRENGTH_SHIFT 0 8173 #define DDR34_E0_PHY_BYTE_LANE_0_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_ND_STRENGTH_DEFAULT 0x0000001f 8174 8175 /*************************************************************************** 8176 *STATIC_PAD_CTL - pad rx and tx characteristics control register 8177 */ 8178 /* DDR34_E0_PHY_BYTE_LANE_0 :: STATIC_PAD_CTL :: reserved0 [31:21] */ 8179 #define DDR34_E0_PHY_BYTE_LANE_0_STATIC_PAD_CTL_RESERVED0_MASK 0xffe00000 8180 #define DDR34_E0_PHY_BYTE_LANE_0_STATIC_PAD_CTL_RESERVED0_ALIGN 0 8181 #define DDR34_E0_PHY_BYTE_LANE_0_STATIC_PAD_CTL_RESERVED0_BITS 11 8182 #define DDR34_E0_PHY_BYTE_LANE_0_STATIC_PAD_CTL_RESERVED0_SHIFT 21 8183 8184 /* DDR34_E0_PHY_BYTE_LANE_0 :: STATIC_PAD_CTL :: DQS_MODE [20:20] */ 8185 #define DDR34_E0_PHY_BYTE_LANE_0_STATIC_PAD_CTL_DQS_MODE_MASK 0x00100000 8186 #define DDR34_E0_PHY_BYTE_LANE_0_STATIC_PAD_CTL_DQS_MODE_ALIGN 0 8187 #define DDR34_E0_PHY_BYTE_LANE_0_STATIC_PAD_CTL_DQS_MODE_BITS 1 8188 #define DDR34_E0_PHY_BYTE_LANE_0_STATIC_PAD_CTL_DQS_MODE_SHIFT 20 8189 #define DDR34_E0_PHY_BYTE_LANE_0_STATIC_PAD_CTL_DQS_MODE_DEFAULT 0x00000000 8190 8191 /* DDR34_E0_PHY_BYTE_LANE_0 :: STATIC_PAD_CTL :: reserved1 [19:18] */ 8192 #define DDR34_E0_PHY_BYTE_LANE_0_STATIC_PAD_CTL_RESERVED1_MASK 0x000c0000 8193 #define DDR34_E0_PHY_BYTE_LANE_0_STATIC_PAD_CTL_RESERVED1_ALIGN 0 8194 #define DDR34_E0_PHY_BYTE_LANE_0_STATIC_PAD_CTL_RESERVED1_BITS 2 8195 #define DDR34_E0_PHY_BYTE_LANE_0_STATIC_PAD_CTL_RESERVED1_SHIFT 18 8196 8197 /* DDR34_E0_PHY_BYTE_LANE_0 :: STATIC_PAD_CTL :: EDC_MODE [17:16] */ 8198 #define DDR34_E0_PHY_BYTE_LANE_0_STATIC_PAD_CTL_EDC_MODE_MASK 0x00030000 8199 #define DDR34_E0_PHY_BYTE_LANE_0_STATIC_PAD_CTL_EDC_MODE_ALIGN 0 8200 #define DDR34_E0_PHY_BYTE_LANE_0_STATIC_PAD_CTL_EDC_MODE_BITS 2 8201 #define DDR34_E0_PHY_BYTE_LANE_0_STATIC_PAD_CTL_EDC_MODE_SHIFT 16 8202 #define DDR34_E0_PHY_BYTE_LANE_0_STATIC_PAD_CTL_EDC_MODE_DEFAULT 0x00000000 8203 8204 /* DDR34_E0_PHY_BYTE_LANE_0 :: STATIC_PAD_CTL :: reserved2 [15:15] */ 8205 #define DDR34_E0_PHY_BYTE_LANE_0_STATIC_PAD_CTL_RESERVED2_MASK 0x00008000 8206 #define DDR34_E0_PHY_BYTE_LANE_0_STATIC_PAD_CTL_RESERVED2_ALIGN 0 8207 #define DDR34_E0_PHY_BYTE_LANE_0_STATIC_PAD_CTL_RESERVED2_BITS 1 8208 #define DDR34_E0_PHY_BYTE_LANE_0_STATIC_PAD_CTL_RESERVED2_SHIFT 15 8209 8210 /* DDR34_E0_PHY_BYTE_LANE_0 :: STATIC_PAD_CTL :: WDBI_ENABLE [14:14] */ 8211 #define DDR34_E0_PHY_BYTE_LANE_0_STATIC_PAD_CTL_WDBI_ENABLE_MASK 0x00004000 8212 #define DDR34_E0_PHY_BYTE_LANE_0_STATIC_PAD_CTL_WDBI_ENABLE_ALIGN 0 8213 #define DDR34_E0_PHY_BYTE_LANE_0_STATIC_PAD_CTL_WDBI_ENABLE_BITS 1 8214 #define DDR34_E0_PHY_BYTE_LANE_0_STATIC_PAD_CTL_WDBI_ENABLE_SHIFT 14 8215 #define DDR34_E0_PHY_BYTE_LANE_0_STATIC_PAD_CTL_WDBI_ENABLE_DEFAULT 0x00000000 8216 8217 /* DDR34_E0_PHY_BYTE_LANE_0 :: STATIC_PAD_CTL :: RDBI_ENABLE [13:13] */ 8218 #define DDR34_E0_PHY_BYTE_LANE_0_STATIC_PAD_CTL_RDBI_ENABLE_MASK 0x00002000 8219 #define DDR34_E0_PHY_BYTE_LANE_0_STATIC_PAD_CTL_RDBI_ENABLE_ALIGN 0 8220 #define DDR34_E0_PHY_BYTE_LANE_0_STATIC_PAD_CTL_RDBI_ENABLE_BITS 1 8221 #define DDR34_E0_PHY_BYTE_LANE_0_STATIC_PAD_CTL_RDBI_ENABLE_SHIFT 13 8222 #define DDR34_E0_PHY_BYTE_LANE_0_STATIC_PAD_CTL_RDBI_ENABLE_DEFAULT 0x00000000 8223 8224 /* DDR34_E0_PHY_BYTE_LANE_0 :: STATIC_PAD_CTL :: DM_MODE [12:12] */ 8225 #define DDR34_E0_PHY_BYTE_LANE_0_STATIC_PAD_CTL_DM_MODE_MASK 0x00001000 8226 #define DDR34_E0_PHY_BYTE_LANE_0_STATIC_PAD_CTL_DM_MODE_ALIGN 0 8227 #define DDR34_E0_PHY_BYTE_LANE_0_STATIC_PAD_CTL_DM_MODE_BITS 1 8228 #define DDR34_E0_PHY_BYTE_LANE_0_STATIC_PAD_CTL_DM_MODE_SHIFT 12 8229 #define DDR34_E0_PHY_BYTE_LANE_0_STATIC_PAD_CTL_DM_MODE_DEFAULT 0x00000000 8230 8231 /* DDR34_E0_PHY_BYTE_LANE_0 :: STATIC_PAD_CTL :: reserved3 [11:10] */ 8232 #define DDR34_E0_PHY_BYTE_LANE_0_STATIC_PAD_CTL_RESERVED3_MASK 0x00000c00 8233 #define DDR34_E0_PHY_BYTE_LANE_0_STATIC_PAD_CTL_RESERVED3_ALIGN 0 8234 #define DDR34_E0_PHY_BYTE_LANE_0_STATIC_PAD_CTL_RESERVED3_BITS 2 8235 #define DDR34_E0_PHY_BYTE_LANE_0_STATIC_PAD_CTL_RESERVED3_SHIFT 10 8236 8237 /* DDR34_E0_PHY_BYTE_LANE_0 :: STATIC_PAD_CTL :: DQS_TX_DIS [09:09] */ 8238 #define DDR34_E0_PHY_BYTE_LANE_0_STATIC_PAD_CTL_DQS_TX_DIS_MASK 0x00000200 8239 #define DDR34_E0_PHY_BYTE_LANE_0_STATIC_PAD_CTL_DQS_TX_DIS_ALIGN 0 8240 #define DDR34_E0_PHY_BYTE_LANE_0_STATIC_PAD_CTL_DQS_TX_DIS_BITS 1 8241 #define DDR34_E0_PHY_BYTE_LANE_0_STATIC_PAD_CTL_DQS_TX_DIS_SHIFT 9 8242 #define DDR34_E0_PHY_BYTE_LANE_0_STATIC_PAD_CTL_DQS_TX_DIS_DEFAULT 0x00000000 8243 8244 /* DDR34_E0_PHY_BYTE_LANE_0 :: STATIC_PAD_CTL :: reserved4 [08:02] */ 8245 #define DDR34_E0_PHY_BYTE_LANE_0_STATIC_PAD_CTL_RESERVED4_MASK 0x000001fc 8246 #define DDR34_E0_PHY_BYTE_LANE_0_STATIC_PAD_CTL_RESERVED4_ALIGN 0 8247 #define DDR34_E0_PHY_BYTE_LANE_0_STATIC_PAD_CTL_RESERVED4_BITS 7 8248 #define DDR34_E0_PHY_BYTE_LANE_0_STATIC_PAD_CTL_RESERVED4_SHIFT 2 8249 8250 /* DDR34_E0_PHY_BYTE_LANE_0 :: STATIC_PAD_CTL :: RX_MODE [01:00] */ 8251 #define DDR34_E0_PHY_BYTE_LANE_0_STATIC_PAD_CTL_RX_MODE_MASK 0x00000003 8252 #define DDR34_E0_PHY_BYTE_LANE_0_STATIC_PAD_CTL_RX_MODE_ALIGN 0 8253 #define DDR34_E0_PHY_BYTE_LANE_0_STATIC_PAD_CTL_RX_MODE_BITS 2 8254 #define DDR34_E0_PHY_BYTE_LANE_0_STATIC_PAD_CTL_RX_MODE_SHIFT 0 8255 #define DDR34_E0_PHY_BYTE_LANE_0_STATIC_PAD_CTL_RX_MODE_DEFAULT 0x00000000 8256 8257 /*************************************************************************** 8258 *WR_PREAMBLE_MODE - Write cycle preamble control register 8259 */ 8260 /* DDR34_E0_PHY_BYTE_LANE_0 :: WR_PREAMBLE_MODE :: reserved0 [31:16] */ 8261 #define DDR34_E0_PHY_BYTE_LANE_0_WR_PREAMBLE_MODE_RESERVED0_MASK 0xffff0000 8262 #define DDR34_E0_PHY_BYTE_LANE_0_WR_PREAMBLE_MODE_RESERVED0_ALIGN 0 8263 #define DDR34_E0_PHY_BYTE_LANE_0_WR_PREAMBLE_MODE_RESERVED0_BITS 16 8264 #define DDR34_E0_PHY_BYTE_LANE_0_WR_PREAMBLE_MODE_RESERVED0_SHIFT 16 8265 8266 /* DDR34_E0_PHY_BYTE_LANE_0 :: WR_PREAMBLE_MODE :: DQ_POSTAM_BITS [15:14] */ 8267 #define DDR34_E0_PHY_BYTE_LANE_0_WR_PREAMBLE_MODE_DQ_POSTAM_BITS_MASK 0x0000c000 8268 #define DDR34_E0_PHY_BYTE_LANE_0_WR_PREAMBLE_MODE_DQ_POSTAM_BITS_ALIGN 0 8269 #define DDR34_E0_PHY_BYTE_LANE_0_WR_PREAMBLE_MODE_DQ_POSTAM_BITS_BITS 2 8270 #define DDR34_E0_PHY_BYTE_LANE_0_WR_PREAMBLE_MODE_DQ_POSTAM_BITS_SHIFT 14 8271 #define DDR34_E0_PHY_BYTE_LANE_0_WR_PREAMBLE_MODE_DQ_POSTAM_BITS_DEFAULT 0x00000000 8272 8273 /* DDR34_E0_PHY_BYTE_LANE_0 :: WR_PREAMBLE_MODE :: DQ_PREAM_BITS [13:12] */ 8274 #define DDR34_E0_PHY_BYTE_LANE_0_WR_PREAMBLE_MODE_DQ_PREAM_BITS_MASK 0x00003000 8275 #define DDR34_E0_PHY_BYTE_LANE_0_WR_PREAMBLE_MODE_DQ_PREAM_BITS_ALIGN 0 8276 #define DDR34_E0_PHY_BYTE_LANE_0_WR_PREAMBLE_MODE_DQ_PREAM_BITS_BITS 2 8277 #define DDR34_E0_PHY_BYTE_LANE_0_WR_PREAMBLE_MODE_DQ_PREAM_BITS_SHIFT 12 8278 #define DDR34_E0_PHY_BYTE_LANE_0_WR_PREAMBLE_MODE_DQ_PREAM_BITS_DEFAULT 0x00000000 8279 8280 /* DDR34_E0_PHY_BYTE_LANE_0 :: WR_PREAMBLE_MODE :: DQS [11:08] */ 8281 #define DDR34_E0_PHY_BYTE_LANE_0_WR_PREAMBLE_MODE_DQS_MASK 0x00000f00 8282 #define DDR34_E0_PHY_BYTE_LANE_0_WR_PREAMBLE_MODE_DQS_ALIGN 0 8283 #define DDR34_E0_PHY_BYTE_LANE_0_WR_PREAMBLE_MODE_DQS_BITS 4 8284 #define DDR34_E0_PHY_BYTE_LANE_0_WR_PREAMBLE_MODE_DQS_SHIFT 8 8285 #define DDR34_E0_PHY_BYTE_LANE_0_WR_PREAMBLE_MODE_DQS_DEFAULT 0x0000000e 8286 8287 /* DDR34_E0_PHY_BYTE_LANE_0 :: WR_PREAMBLE_MODE :: reserved1 [07:05] */ 8288 #define DDR34_E0_PHY_BYTE_LANE_0_WR_PREAMBLE_MODE_RESERVED1_MASK 0x000000e0 8289 #define DDR34_E0_PHY_BYTE_LANE_0_WR_PREAMBLE_MODE_RESERVED1_ALIGN 0 8290 #define DDR34_E0_PHY_BYTE_LANE_0_WR_PREAMBLE_MODE_RESERVED1_BITS 3 8291 #define DDR34_E0_PHY_BYTE_LANE_0_WR_PREAMBLE_MODE_RESERVED1_SHIFT 5 8292 8293 /* DDR34_E0_PHY_BYTE_LANE_0 :: WR_PREAMBLE_MODE :: DQS_POSTAM_BITS [04:03] */ 8294 #define DDR34_E0_PHY_BYTE_LANE_0_WR_PREAMBLE_MODE_DQS_POSTAM_BITS_MASK 0x00000018 8295 #define DDR34_E0_PHY_BYTE_LANE_0_WR_PREAMBLE_MODE_DQS_POSTAM_BITS_ALIGN 0 8296 #define DDR34_E0_PHY_BYTE_LANE_0_WR_PREAMBLE_MODE_DQS_POSTAM_BITS_BITS 2 8297 #define DDR34_E0_PHY_BYTE_LANE_0_WR_PREAMBLE_MODE_DQS_POSTAM_BITS_SHIFT 3 8298 #define DDR34_E0_PHY_BYTE_LANE_0_WR_PREAMBLE_MODE_DQS_POSTAM_BITS_DEFAULT 0x00000000 8299 8300 /* DDR34_E0_PHY_BYTE_LANE_0 :: WR_PREAMBLE_MODE :: DQS_PREAM_BITS [02:00] */ 8301 #define DDR34_E0_PHY_BYTE_LANE_0_WR_PREAMBLE_MODE_DQS_PREAM_BITS_MASK 0x00000007 8302 #define DDR34_E0_PHY_BYTE_LANE_0_WR_PREAMBLE_MODE_DQS_PREAM_BITS_ALIGN 0 8303 #define DDR34_E0_PHY_BYTE_LANE_0_WR_PREAMBLE_MODE_DQS_PREAM_BITS_BITS 3 8304 #define DDR34_E0_PHY_BYTE_LANE_0_WR_PREAMBLE_MODE_DQS_PREAM_BITS_SHIFT 0 8305 #define DDR34_E0_PHY_BYTE_LANE_0_WR_PREAMBLE_MODE_DQS_PREAM_BITS_DEFAULT 0x00000002 8306 8307 /*************************************************************************** 8308 *ODT_CONTROL - Read channel ODT control register 8309 */ 8310 /* DDR34_E0_PHY_BYTE_LANE_0 :: ODT_CONTROL :: reserved_for_padding0 [31:31] */ 8311 #define DDR34_E0_PHY_BYTE_LANE_0_ODT_CONTROL_RESERVED_for_padding0_MASK 0x80000000 8312 #define DDR34_E0_PHY_BYTE_LANE_0_ODT_CONTROL_RESERVED_for_padding0_ALIGN 0 8313 #define DDR34_E0_PHY_BYTE_LANE_0_ODT_CONTROL_RESERVED_for_padding0_BITS 1 8314 #define DDR34_E0_PHY_BYTE_LANE_0_ODT_CONTROL_RESERVED_for_padding0_SHIFT 31 8315 8316 /* DDR34_E0_PHY_BYTE_LANE_0 :: ODT_CONTROL :: reserved1 [30:10] */ 8317 #define DDR34_E0_PHY_BYTE_LANE_0_ODT_CONTROL_RESERVED1_MASK 0x7ffffc00 8318 #define DDR34_E0_PHY_BYTE_LANE_0_ODT_CONTROL_RESERVED1_ALIGN 0 8319 #define DDR34_E0_PHY_BYTE_LANE_0_ODT_CONTROL_RESERVED1_BITS 21 8320 #define DDR34_E0_PHY_BYTE_LANE_0_ODT_CONTROL_RESERVED1_SHIFT 10 8321 8322 /* DDR34_E0_PHY_BYTE_LANE_0 :: ODT_CONTROL :: ODT_ENABLE [09:09] */ 8323 #define DDR34_E0_PHY_BYTE_LANE_0_ODT_CONTROL_ODT_ENABLE_MASK 0x00000200 8324 #define DDR34_E0_PHY_BYTE_LANE_0_ODT_CONTROL_ODT_ENABLE_ALIGN 0 8325 #define DDR34_E0_PHY_BYTE_LANE_0_ODT_CONTROL_ODT_ENABLE_BITS 1 8326 #define DDR34_E0_PHY_BYTE_LANE_0_ODT_CONTROL_ODT_ENABLE_SHIFT 9 8327 #define DDR34_E0_PHY_BYTE_LANE_0_ODT_CONTROL_ODT_ENABLE_DEFAULT 0x00000001 8328 8329 /* DDR34_E0_PHY_BYTE_LANE_0 :: ODT_CONTROL :: ODT_DELAY [08:06] */ 8330 #define DDR34_E0_PHY_BYTE_LANE_0_ODT_CONTROL_ODT_DELAY_MASK 0x000001c0 8331 #define DDR34_E0_PHY_BYTE_LANE_0_ODT_CONTROL_ODT_DELAY_ALIGN 0 8332 #define DDR34_E0_PHY_BYTE_LANE_0_ODT_CONTROL_ODT_DELAY_BITS 3 8333 #define DDR34_E0_PHY_BYTE_LANE_0_ODT_CONTROL_ODT_DELAY_SHIFT 6 8334 #define DDR34_E0_PHY_BYTE_LANE_0_ODT_CONTROL_ODT_DELAY_DEFAULT 0x00000000 8335 8336 /* DDR34_E0_PHY_BYTE_LANE_0 :: ODT_CONTROL :: ODT_POST_LENGTH [05:03] */ 8337 #define DDR34_E0_PHY_BYTE_LANE_0_ODT_CONTROL_ODT_POST_LENGTH_MASK 0x00000038 8338 #define DDR34_E0_PHY_BYTE_LANE_0_ODT_CONTROL_ODT_POST_LENGTH_ALIGN 0 8339 #define DDR34_E0_PHY_BYTE_LANE_0_ODT_CONTROL_ODT_POST_LENGTH_BITS 3 8340 #define DDR34_E0_PHY_BYTE_LANE_0_ODT_CONTROL_ODT_POST_LENGTH_SHIFT 3 8341 #define DDR34_E0_PHY_BYTE_LANE_0_ODT_CONTROL_ODT_POST_LENGTH_DEFAULT 0x00000001 8342 8343 /* DDR34_E0_PHY_BYTE_LANE_0 :: ODT_CONTROL :: ODT_PRE_LENGTH [02:00] */ 8344 #define DDR34_E0_PHY_BYTE_LANE_0_ODT_CONTROL_ODT_PRE_LENGTH_MASK 0x00000007 8345 #define DDR34_E0_PHY_BYTE_LANE_0_ODT_CONTROL_ODT_PRE_LENGTH_ALIGN 0 8346 #define DDR34_E0_PHY_BYTE_LANE_0_ODT_CONTROL_ODT_PRE_LENGTH_BITS 3 8347 #define DDR34_E0_PHY_BYTE_LANE_0_ODT_CONTROL_ODT_PRE_LENGTH_SHIFT 0 8348 #define DDR34_E0_PHY_BYTE_LANE_0_ODT_CONTROL_ODT_PRE_LENGTH_DEFAULT 0x00000003 8349 8350 /*************************************************************************** 8351 *EDC_DPD_CONTROL - GDDR5M EDC digital phase detector control register 8352 */ 8353 /* DDR34_E0_PHY_BYTE_LANE_0 :: EDC_DPD_CONTROL :: reserved0 [31:06] */ 8354 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_DPD_CONTROL_RESERVED0_MASK 0xffffffc0 8355 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_DPD_CONTROL_RESERVED0_ALIGN 0 8356 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_DPD_CONTROL_RESERVED0_BITS 26 8357 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_DPD_CONTROL_RESERVED0_SHIFT 6 8358 8359 /* DDR34_E0_PHY_BYTE_LANE_0 :: EDC_DPD_CONTROL :: DQS_PHASE_OVERRIDE_VALUE [05:05] */ 8360 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_VALUE_MASK 0x00000020 8361 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_VALUE_ALIGN 0 8362 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_VALUE_BITS 1 8363 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_VALUE_SHIFT 5 8364 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_VALUE_DEFAULT 0x00000000 8365 8366 /* DDR34_E0_PHY_BYTE_LANE_0 :: EDC_DPD_CONTROL :: DQS_PHASE_OVERRIDE_ENABLE [04:04] */ 8367 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_ENABLE_MASK 0x00000010 8368 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_ENABLE_ALIGN 0 8369 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_ENABLE_BITS 1 8370 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_ENABLE_SHIFT 4 8371 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_ENABLE_DEFAULT 0x00000000 8372 8373 /* DDR34_E0_PHY_BYTE_LANE_0 :: EDC_DPD_CONTROL :: SET_ADJ_EN [03:03] */ 8374 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_DPD_CONTROL_SET_ADJ_EN_MASK 0x00000008 8375 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_DPD_CONTROL_SET_ADJ_EN_ALIGN 0 8376 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_DPD_CONTROL_SET_ADJ_EN_BITS 1 8377 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_DPD_CONTROL_SET_ADJ_EN_SHIFT 3 8378 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_DPD_CONTROL_SET_ADJ_EN_DEFAULT 0x00000000 8379 8380 /* DDR34_E0_PHY_BYTE_LANE_0 :: EDC_DPD_CONTROL :: UPDATE [02:02] */ 8381 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_DPD_CONTROL_UPDATE_MASK 0x00000004 8382 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_DPD_CONTROL_UPDATE_ALIGN 0 8383 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_DPD_CONTROL_UPDATE_BITS 1 8384 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_DPD_CONTROL_UPDATE_SHIFT 2 8385 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_DPD_CONTROL_UPDATE_DEFAULT 0x00000000 8386 8387 /* DDR34_E0_PHY_BYTE_LANE_0 :: EDC_DPD_CONTROL :: MONITOR [01:01] */ 8388 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_DPD_CONTROL_MONITOR_MASK 0x00000002 8389 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_DPD_CONTROL_MONITOR_ALIGN 0 8390 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_DPD_CONTROL_MONITOR_BITS 1 8391 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_DPD_CONTROL_MONITOR_SHIFT 1 8392 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_DPD_CONTROL_MONITOR_DEFAULT 0x00000000 8393 8394 /* DDR34_E0_PHY_BYTE_LANE_0 :: EDC_DPD_CONTROL :: INIT [00:00] */ 8395 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_DPD_CONTROL_INIT_MASK 0x00000001 8396 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_DPD_CONTROL_INIT_ALIGN 0 8397 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_DPD_CONTROL_INIT_BITS 1 8398 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_DPD_CONTROL_INIT_SHIFT 0 8399 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_DPD_CONTROL_INIT_DEFAULT 0x00000000 8400 8401 /*************************************************************************** 8402 *EDC_DPD_STATUS - GDDR5M EDC digital phase detector status register 8403 */ 8404 /* DDR34_E0_PHY_BYTE_LANE_0 :: EDC_DPD_STATUS :: reserved0 [31:25] */ 8405 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_DPD_STATUS_RESERVED0_MASK 0xfe000000 8406 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_DPD_STATUS_RESERVED0_ALIGN 0 8407 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_DPD_STATUS_RESERVED0_BITS 7 8408 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_DPD_STATUS_RESERVED0_SHIFT 25 8409 8410 /* DDR34_E0_PHY_BYTE_LANE_0 :: EDC_DPD_STATUS :: CURRENT_DQS_PHASE [24:24] */ 8411 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_DPD_STATUS_CURRENT_DQS_PHASE_MASK 0x01000000 8412 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_DPD_STATUS_CURRENT_DQS_PHASE_ALIGN 0 8413 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_DPD_STATUS_CURRENT_DQS_PHASE_BITS 1 8414 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_DPD_STATUS_CURRENT_DQS_PHASE_SHIFT 24 8415 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_DPD_STATUS_CURRENT_DQS_PHASE_DEFAULT 0x00000000 8416 8417 /* DDR34_E0_PHY_BYTE_LANE_0 :: EDC_DPD_STATUS :: CURRENT_VDL_SETTING [23:16] */ 8418 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_DPD_STATUS_CURRENT_VDL_SETTING_MASK 0x00ff0000 8419 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_DPD_STATUS_CURRENT_VDL_SETTING_ALIGN 0 8420 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_DPD_STATUS_CURRENT_VDL_SETTING_BITS 8 8421 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_DPD_STATUS_CURRENT_VDL_SETTING_SHIFT 16 8422 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_DPD_STATUS_CURRENT_VDL_SETTING_DEFAULT 0x00000000 8423 8424 /* DDR34_E0_PHY_BYTE_LANE_0 :: EDC_DPD_STATUS :: reserved1 [15:13] */ 8425 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_DPD_STATUS_RESERVED1_MASK 0x0000e000 8426 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_DPD_STATUS_RESERVED1_ALIGN 0 8427 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_DPD_STATUS_RESERVED1_BITS 3 8428 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_DPD_STATUS_RESERVED1_SHIFT 13 8429 8430 /* DDR34_E0_PHY_BYTE_LANE_0 :: EDC_DPD_STATUS :: INIT_DQS_PHASE [12:12] */ 8431 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_DPD_STATUS_INIT_DQS_PHASE_MASK 0x00001000 8432 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_DPD_STATUS_INIT_DQS_PHASE_ALIGN 0 8433 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_DPD_STATUS_INIT_DQS_PHASE_BITS 1 8434 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_DPD_STATUS_INIT_DQS_PHASE_SHIFT 12 8435 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_DPD_STATUS_INIT_DQS_PHASE_DEFAULT 0x00000000 8436 8437 /* DDR34_E0_PHY_BYTE_LANE_0 :: EDC_DPD_STATUS :: INIT_VDL_SETTING [11:04] */ 8438 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_DPD_STATUS_INIT_VDL_SETTING_MASK 0x00000ff0 8439 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_DPD_STATUS_INIT_VDL_SETTING_ALIGN 0 8440 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_DPD_STATUS_INIT_VDL_SETTING_BITS 8 8441 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_DPD_STATUS_INIT_VDL_SETTING_SHIFT 4 8442 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_DPD_STATUS_INIT_VDL_SETTING_DEFAULT 0x00000000 8443 8444 /* DDR34_E0_PHY_BYTE_LANE_0 :: EDC_DPD_STATUS :: EDGE_ERROR [03:03] */ 8445 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_DPD_STATUS_EDGE_ERROR_MASK 0x00000008 8446 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_DPD_STATUS_EDGE_ERROR_ALIGN 0 8447 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_DPD_STATUS_EDGE_ERROR_BITS 1 8448 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_DPD_STATUS_EDGE_ERROR_SHIFT 3 8449 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_DPD_STATUS_EDGE_ERROR_DEFAULT 0x00000000 8450 8451 /* DDR34_E0_PHY_BYTE_LANE_0 :: EDC_DPD_STATUS :: MONITOR_BUSY [02:02] */ 8452 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_DPD_STATUS_MONITOR_BUSY_MASK 0x00000004 8453 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_DPD_STATUS_MONITOR_BUSY_ALIGN 0 8454 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_DPD_STATUS_MONITOR_BUSY_BITS 1 8455 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_DPD_STATUS_MONITOR_BUSY_SHIFT 2 8456 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_DPD_STATUS_MONITOR_BUSY_DEFAULT 0x00000000 8457 8458 /* DDR34_E0_PHY_BYTE_LANE_0 :: EDC_DPD_STATUS :: INIT_BUSY [01:01] */ 8459 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_DPD_STATUS_INIT_BUSY_MASK 0x00000002 8460 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_DPD_STATUS_INIT_BUSY_ALIGN 0 8461 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_DPD_STATUS_INIT_BUSY_BITS 1 8462 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_DPD_STATUS_INIT_BUSY_SHIFT 1 8463 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_DPD_STATUS_INIT_BUSY_DEFAULT 0x00000000 8464 8465 /* DDR34_E0_PHY_BYTE_LANE_0 :: EDC_DPD_STATUS :: INIT_DONE [00:00] */ 8466 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_DPD_STATUS_INIT_DONE_MASK 0x00000001 8467 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_DPD_STATUS_INIT_DONE_ALIGN 0 8468 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_DPD_STATUS_INIT_DONE_BITS 1 8469 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_DPD_STATUS_INIT_DONE_SHIFT 0 8470 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_DPD_STATUS_INIT_DONE_DEFAULT 0x00000000 8471 8472 /*************************************************************************** 8473 *EDC_DPD_OUT_CONTROL - GDDR5M EDC digital phase detector output signal control register 8474 */ 8475 /* DDR34_E0_PHY_BYTE_LANE_0 :: EDC_DPD_OUT_CONTROL :: reserved0 [31:20] */ 8476 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_DPD_OUT_CONTROL_RESERVED0_MASK 0xfff00000 8477 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_DPD_OUT_CONTROL_RESERVED0_ALIGN 0 8478 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_DPD_OUT_CONTROL_RESERVED0_BITS 12 8479 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_DPD_OUT_CONTROL_RESERVED0_SHIFT 20 8480 8481 /* DDR34_E0_PHY_BYTE_LANE_0 :: EDC_DPD_OUT_CONTROL :: LOWER_LIMIT [19:12] */ 8482 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_DPD_OUT_CONTROL_LOWER_LIMIT_MASK 0x000ff000 8483 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_DPD_OUT_CONTROL_LOWER_LIMIT_ALIGN 0 8484 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_DPD_OUT_CONTROL_LOWER_LIMIT_BITS 8 8485 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_DPD_OUT_CONTROL_LOWER_LIMIT_SHIFT 12 8486 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_DPD_OUT_CONTROL_LOWER_LIMIT_DEFAULT 0x00000000 8487 8488 /* DDR34_E0_PHY_BYTE_LANE_0 :: EDC_DPD_OUT_CONTROL :: UPPER_LIMIT [11:04] */ 8489 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_DPD_OUT_CONTROL_UPPER_LIMIT_MASK 0x00000ff0 8490 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_DPD_OUT_CONTROL_UPPER_LIMIT_ALIGN 0 8491 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_DPD_OUT_CONTROL_UPPER_LIMIT_BITS 8 8492 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_DPD_OUT_CONTROL_UPPER_LIMIT_SHIFT 4 8493 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_DPD_OUT_CONTROL_UPPER_LIMIT_DEFAULT 0x00000000 8494 8495 /* DDR34_E0_PHY_BYTE_LANE_0 :: EDC_DPD_OUT_CONTROL :: reserved1 [03:01] */ 8496 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_DPD_OUT_CONTROL_RESERVED1_MASK 0x0000000e 8497 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_DPD_OUT_CONTROL_RESERVED1_ALIGN 0 8498 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_DPD_OUT_CONTROL_RESERVED1_BITS 3 8499 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_DPD_OUT_CONTROL_RESERVED1_SHIFT 1 8500 8501 /* DDR34_E0_PHY_BYTE_LANE_0 :: EDC_DPD_OUT_CONTROL :: ENABLE [00:00] */ 8502 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_DPD_OUT_CONTROL_ENABLE_MASK 0x00000001 8503 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_DPD_OUT_CONTROL_ENABLE_ALIGN 0 8504 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_DPD_OUT_CONTROL_ENABLE_BITS 1 8505 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_DPD_OUT_CONTROL_ENABLE_SHIFT 0 8506 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_DPD_OUT_CONTROL_ENABLE_DEFAULT 0x00000000 8507 8508 /*************************************************************************** 8509 *EDC_DPD_OUT_STATUS - GDDR5M EDC digital phase detector output signal status register 8510 */ 8511 /* DDR34_E0_PHY_BYTE_LANE_0 :: EDC_DPD_OUT_STATUS :: reserved0 [31:12] */ 8512 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_DPD_OUT_STATUS_RESERVED0_MASK 0xfffff000 8513 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_DPD_OUT_STATUS_RESERVED0_ALIGN 0 8514 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_DPD_OUT_STATUS_RESERVED0_BITS 20 8515 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_DPD_OUT_STATUS_RESERVED0_SHIFT 12 8516 8517 /* DDR34_E0_PHY_BYTE_LANE_0 :: EDC_DPD_OUT_STATUS :: VDL_SETTING [11:04] */ 8518 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_DPD_OUT_STATUS_VDL_SETTING_MASK 0x00000ff0 8519 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_DPD_OUT_STATUS_VDL_SETTING_ALIGN 0 8520 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_DPD_OUT_STATUS_VDL_SETTING_BITS 8 8521 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_DPD_OUT_STATUS_VDL_SETTING_SHIFT 4 8522 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_DPD_OUT_STATUS_VDL_SETTING_DEFAULT 0x00000000 8523 8524 /* DDR34_E0_PHY_BYTE_LANE_0 :: EDC_DPD_OUT_STATUS :: reserved1 [03:01] */ 8525 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_DPD_OUT_STATUS_RESERVED1_MASK 0x0000000e 8526 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_DPD_OUT_STATUS_RESERVED1_ALIGN 0 8527 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_DPD_OUT_STATUS_RESERVED1_BITS 3 8528 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_DPD_OUT_STATUS_RESERVED1_SHIFT 1 8529 8530 /* DDR34_E0_PHY_BYTE_LANE_0 :: EDC_DPD_OUT_STATUS :: VALID [00:00] */ 8531 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_DPD_OUT_STATUS_VALID_MASK 0x00000001 8532 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_DPD_OUT_STATUS_VALID_ALIGN 0 8533 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_DPD_OUT_STATUS_VALID_BITS 1 8534 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_DPD_OUT_STATUS_VALID_SHIFT 0 8535 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_DPD_OUT_STATUS_VALID_DEFAULT 0x00000000 8536 8537 /*************************************************************************** 8538 *EDC_DPD_OUT_STATUS_CLEAR - GDDR5M EDC digital phase detector output signal status clear register 8539 */ 8540 /* DDR34_E0_PHY_BYTE_LANE_0 :: EDC_DPD_OUT_STATUS_CLEAR :: reserved0 [31:01] */ 8541 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_DPD_OUT_STATUS_CLEAR_RESERVED0_MASK 0xfffffffe 8542 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_DPD_OUT_STATUS_CLEAR_RESERVED0_ALIGN 0 8543 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_DPD_OUT_STATUS_CLEAR_RESERVED0_BITS 31 8544 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_DPD_OUT_STATUS_CLEAR_RESERVED0_SHIFT 1 8545 8546 /* DDR34_E0_PHY_BYTE_LANE_0 :: EDC_DPD_OUT_STATUS_CLEAR :: CLEAR [00:00] */ 8547 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_DPD_OUT_STATUS_CLEAR_CLEAR_MASK 0x00000001 8548 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_DPD_OUT_STATUS_CLEAR_CLEAR_ALIGN 0 8549 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_DPD_OUT_STATUS_CLEAR_CLEAR_BITS 1 8550 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_DPD_OUT_STATUS_CLEAR_CLEAR_SHIFT 0 8551 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_DPD_OUT_STATUS_CLEAR_CLEAR_DEFAULT 0x00000000 8552 8553 /*************************************************************************** 8554 *EDC_CRC_CONTROL - GDDR5M EDC signal path CRC control register 8555 */ 8556 /* DDR34_E0_PHY_BYTE_LANE_0 :: EDC_CRC_CONTROL :: BUSY [31:31] */ 8557 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_CRC_CONTROL_BUSY_MASK 0x80000000 8558 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_CRC_CONTROL_BUSY_ALIGN 0 8559 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_CRC_CONTROL_BUSY_BITS 1 8560 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_CRC_CONTROL_BUSY_SHIFT 31 8561 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_CRC_CONTROL_BUSY_DEFAULT 0x00000000 8562 8563 /* DDR34_E0_PHY_BYTE_LANE_0 :: EDC_CRC_CONTROL :: reserved0 [30:17] */ 8564 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_CRC_CONTROL_RESERVED0_MASK 0x7ffe0000 8565 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_CRC_CONTROL_RESERVED0_ALIGN 0 8566 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_CRC_CONTROL_RESERVED0_BITS 14 8567 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_CRC_CONTROL_RESERVED0_SHIFT 17 8568 8569 /* DDR34_E0_PHY_BYTE_LANE_0 :: EDC_CRC_CONTROL :: FORCE [16:16] */ 8570 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_CRC_CONTROL_FORCE_MASK 0x00010000 8571 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_CRC_CONTROL_FORCE_ALIGN 0 8572 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_CRC_CONTROL_FORCE_BITS 1 8573 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_CRC_CONTROL_FORCE_SHIFT 16 8574 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_CRC_CONTROL_FORCE_DEFAULT 0x00000000 8575 8576 /* DDR34_E0_PHY_BYTE_LANE_0 :: EDC_CRC_CONTROL :: reserved1 [15:11] */ 8577 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_CRC_CONTROL_RESERVED1_MASK 0x0000f800 8578 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_CRC_CONTROL_RESERVED1_ALIGN 0 8579 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_CRC_CONTROL_RESERVED1_BITS 5 8580 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_CRC_CONTROL_RESERVED1_SHIFT 11 8581 8582 /* DDR34_E0_PHY_BYTE_LANE_0 :: EDC_CRC_CONTROL :: CRCWL [10:08] */ 8583 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_CRC_CONTROL_CRCWL_MASK 0x00000700 8584 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_CRC_CONTROL_CRCWL_ALIGN 0 8585 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_CRC_CONTROL_CRCWL_BITS 3 8586 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_CRC_CONTROL_CRCWL_SHIFT 8 8587 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_CRC_CONTROL_CRCWL_DEFAULT 0x00000000 8588 8589 /* DDR34_E0_PHY_BYTE_LANE_0 :: EDC_CRC_CONTROL :: reserved2 [07:06] */ 8590 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_CRC_CONTROL_RESERVED2_MASK 0x000000c0 8591 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_CRC_CONTROL_RESERVED2_ALIGN 0 8592 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_CRC_CONTROL_RESERVED2_BITS 2 8593 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_CRC_CONTROL_RESERVED2_SHIFT 6 8594 8595 /* DDR34_E0_PHY_BYTE_LANE_0 :: EDC_CRC_CONTROL :: CRCRL [05:04] */ 8596 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_CRC_CONTROL_CRCRL_MASK 0x00000030 8597 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_CRC_CONTROL_CRCRL_ALIGN 0 8598 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_CRC_CONTROL_CRCRL_BITS 2 8599 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_CRC_CONTROL_CRCRL_SHIFT 4 8600 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_CRC_CONTROL_CRCRL_DEFAULT 0x00000000 8601 8602 /* DDR34_E0_PHY_BYTE_LANE_0 :: EDC_CRC_CONTROL :: reserved3 [03:03] */ 8603 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_CRC_CONTROL_RESERVED3_MASK 0x00000008 8604 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_CRC_CONTROL_RESERVED3_ALIGN 0 8605 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_CRC_CONTROL_RESERVED3_BITS 1 8606 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_CRC_CONTROL_RESERVED3_SHIFT 3 8607 8608 /* DDR34_E0_PHY_BYTE_LANE_0 :: EDC_CRC_CONTROL :: COUNT_MODE [02:02] */ 8609 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_CRC_CONTROL_COUNT_MODE_MASK 0x00000004 8610 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_CRC_CONTROL_COUNT_MODE_ALIGN 0 8611 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_CRC_CONTROL_COUNT_MODE_BITS 1 8612 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_CRC_CONTROL_COUNT_MODE_SHIFT 2 8613 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_CRC_CONTROL_COUNT_MODE_DEFAULT 0x00000000 8614 8615 /* DDR34_E0_PHY_BYTE_LANE_0 :: EDC_CRC_CONTROL :: ENABLE_WR [01:01] */ 8616 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_CRC_CONTROL_ENABLE_WR_MASK 0x00000002 8617 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_CRC_CONTROL_ENABLE_WR_ALIGN 0 8618 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_CRC_CONTROL_ENABLE_WR_BITS 1 8619 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_CRC_CONTROL_ENABLE_WR_SHIFT 1 8620 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_CRC_CONTROL_ENABLE_WR_DEFAULT 0x00000000 8621 8622 /* DDR34_E0_PHY_BYTE_LANE_0 :: EDC_CRC_CONTROL :: ENABLE_RD [00:00] */ 8623 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_CRC_CONTROL_ENABLE_RD_MASK 0x00000001 8624 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_CRC_CONTROL_ENABLE_RD_ALIGN 0 8625 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_CRC_CONTROL_ENABLE_RD_BITS 1 8626 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_CRC_CONTROL_ENABLE_RD_SHIFT 0 8627 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_CRC_CONTROL_ENABLE_RD_DEFAULT 0x00000000 8628 8629 /*************************************************************************** 8630 *EDC_CRC_STATUS - GDDR5M EDC signal path CRC status register 8631 */ 8632 /* DDR34_E0_PHY_BYTE_LANE_0 :: EDC_CRC_STATUS :: reserved0 [31:04] */ 8633 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_CRC_STATUS_RESERVED0_MASK 0xfffffff0 8634 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_CRC_STATUS_RESERVED0_ALIGN 0 8635 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_CRC_STATUS_RESERVED0_BITS 28 8636 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_CRC_STATUS_RESERVED0_SHIFT 4 8637 8638 /* DDR34_E0_PHY_BYTE_LANE_0 :: EDC_CRC_STATUS :: WR_FAIL [03:03] */ 8639 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_CRC_STATUS_WR_FAIL_MASK 0x00000008 8640 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_CRC_STATUS_WR_FAIL_ALIGN 0 8641 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_CRC_STATUS_WR_FAIL_BITS 1 8642 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_CRC_STATUS_WR_FAIL_SHIFT 3 8643 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_CRC_STATUS_WR_FAIL_DEFAULT 0x00000000 8644 8645 /* DDR34_E0_PHY_BYTE_LANE_0 :: EDC_CRC_STATUS :: WR_PASS [02:02] */ 8646 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_CRC_STATUS_WR_PASS_MASK 0x00000004 8647 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_CRC_STATUS_WR_PASS_ALIGN 0 8648 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_CRC_STATUS_WR_PASS_BITS 1 8649 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_CRC_STATUS_WR_PASS_SHIFT 2 8650 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_CRC_STATUS_WR_PASS_DEFAULT 0x00000000 8651 8652 /* DDR34_E0_PHY_BYTE_LANE_0 :: EDC_CRC_STATUS :: RD_FAIL [01:01] */ 8653 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_CRC_STATUS_RD_FAIL_MASK 0x00000002 8654 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_CRC_STATUS_RD_FAIL_ALIGN 0 8655 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_CRC_STATUS_RD_FAIL_BITS 1 8656 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_CRC_STATUS_RD_FAIL_SHIFT 1 8657 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_CRC_STATUS_RD_FAIL_DEFAULT 0x00000000 8658 8659 /* DDR34_E0_PHY_BYTE_LANE_0 :: EDC_CRC_STATUS :: RD_PASS [00:00] */ 8660 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_CRC_STATUS_RD_PASS_MASK 0x00000001 8661 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_CRC_STATUS_RD_PASS_ALIGN 0 8662 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_CRC_STATUS_RD_PASS_BITS 1 8663 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_CRC_STATUS_RD_PASS_SHIFT 0 8664 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_CRC_STATUS_RD_PASS_DEFAULT 0x00000000 8665 8666 /*************************************************************************** 8667 *EDC_CRC_COUNT - GDDR5M EDC signal path CRC counter register 8668 */ 8669 /* DDR34_E0_PHY_BYTE_LANE_0 :: EDC_CRC_COUNT :: reserved0 [31:28] */ 8670 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_CRC_COUNT_RESERVED0_MASK 0xf0000000 8671 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_CRC_COUNT_RESERVED0_ALIGN 0 8672 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_CRC_COUNT_RESERVED0_BITS 4 8673 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_CRC_COUNT_RESERVED0_SHIFT 28 8674 8675 /* DDR34_E0_PHY_BYTE_LANE_0 :: EDC_CRC_COUNT :: WR_COUNT [27:16] */ 8676 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_CRC_COUNT_WR_COUNT_MASK 0x0fff0000 8677 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_CRC_COUNT_WR_COUNT_ALIGN 0 8678 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_CRC_COUNT_WR_COUNT_BITS 12 8679 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_CRC_COUNT_WR_COUNT_SHIFT 16 8680 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_CRC_COUNT_WR_COUNT_DEFAULT 0x00000000 8681 8682 /* DDR34_E0_PHY_BYTE_LANE_0 :: EDC_CRC_COUNT :: reserved1 [15:12] */ 8683 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_CRC_COUNT_RESERVED1_MASK 0x0000f000 8684 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_CRC_COUNT_RESERVED1_ALIGN 0 8685 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_CRC_COUNT_RESERVED1_BITS 4 8686 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_CRC_COUNT_RESERVED1_SHIFT 12 8687 8688 /* DDR34_E0_PHY_BYTE_LANE_0 :: EDC_CRC_COUNT :: RD_COUNT [11:00] */ 8689 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_CRC_COUNT_RD_COUNT_MASK 0x00000fff 8690 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_CRC_COUNT_RD_COUNT_ALIGN 0 8691 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_CRC_COUNT_RD_COUNT_BITS 12 8692 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_CRC_COUNT_RD_COUNT_SHIFT 0 8693 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_CRC_COUNT_RD_COUNT_DEFAULT 0x00000000 8694 8695 /*************************************************************************** 8696 *EDC_CRC_STATUS_CLEAR - GDDR5M EDC signal path CRC counter register 8697 */ 8698 /* DDR34_E0_PHY_BYTE_LANE_0 :: EDC_CRC_STATUS_CLEAR :: reserved0 [31:01] */ 8699 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_CRC_STATUS_CLEAR_RESERVED0_MASK 0xfffffffe 8700 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_CRC_STATUS_CLEAR_RESERVED0_ALIGN 0 8701 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_CRC_STATUS_CLEAR_RESERVED0_BITS 31 8702 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_CRC_STATUS_CLEAR_RESERVED0_SHIFT 1 8703 8704 /* DDR34_E0_PHY_BYTE_LANE_0 :: EDC_CRC_STATUS_CLEAR :: CLEAR [00:00] */ 8705 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_CRC_STATUS_CLEAR_CLEAR_MASK 0x00000001 8706 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_CRC_STATUS_CLEAR_CLEAR_ALIGN 0 8707 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_CRC_STATUS_CLEAR_CLEAR_BITS 1 8708 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_CRC_STATUS_CLEAR_CLEAR_SHIFT 0 8709 #define DDR34_E0_PHY_BYTE_LANE_0_EDC_CRC_STATUS_CLEAR_CLEAR_DEFAULT 0x00000000 8710 8711 /*************************************************************************** 8712 *BL_SPARE_REG - Byte-Lane Spare register 8713 */ 8714 /* DDR34_E0_PHY_BYTE_LANE_0 :: BL_SPARE_REG :: reserved_for_eco0 [31:00] */ 8715 #define DDR34_E0_PHY_BYTE_LANE_0_BL_SPARE_REG_RESERVED_for_eco0_MASK 0xffffffff 8716 #define DDR34_E0_PHY_BYTE_LANE_0_BL_SPARE_REG_RESERVED_for_eco0_ALIGN 0 8717 #define DDR34_E0_PHY_BYTE_LANE_0_BL_SPARE_REG_RESERVED_for_eco0_BITS 32 8718 #define DDR34_E0_PHY_BYTE_LANE_0_BL_SPARE_REG_RESERVED_for_eco0_SHIFT 0 8719 #define DDR34_E0_PHY_BYTE_LANE_0_BL_SPARE_REG_RESERVED_for_eco0_DEFAULT 0x00000000 8720 8721 /*************************************************************************** 8722 *VDL_CONTROL_WR_DQS_P - Write channel DQS-P VDL control register 8723 */ 8724 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQS_P :: BUSY [31:31] */ 8725 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_P_BUSY_MASK 0x80000000 8726 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_P_BUSY_ALIGN 0 8727 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_P_BUSY_BITS 1 8728 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_P_BUSY_SHIFT 31 8729 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_P_BUSY_DEFAULT 0x00000000 8730 8731 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQS_P :: reserved0 [30:17] */ 8732 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_P_RESERVED0_MASK 0x7ffe0000 8733 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_P_RESERVED0_ALIGN 0 8734 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_P_RESERVED0_BITS 14 8735 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_P_RESERVED0_SHIFT 17 8736 8737 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQS_P :: FORCE [16:16] */ 8738 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_P_FORCE_MASK 0x00010000 8739 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_P_FORCE_ALIGN 0 8740 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_P_FORCE_BITS 1 8741 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_P_FORCE_SHIFT 16 8742 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_P_FORCE_DEFAULT 0x00000000 8743 8744 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQS_P :: reserved1 [15:13] */ 8745 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_P_RESERVED1_MASK 0x0000e000 8746 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_P_RESERVED1_ALIGN 0 8747 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_P_RESERVED1_BITS 3 8748 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_P_RESERVED1_SHIFT 13 8749 8750 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQS_P :: ADJ_EN [12:12] */ 8751 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_P_ADJ_EN_MASK 0x00001000 8752 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_P_ADJ_EN_ALIGN 0 8753 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_P_ADJ_EN_BITS 1 8754 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_P_ADJ_EN_SHIFT 12 8755 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_P_ADJ_EN_DEFAULT 0x00000000 8756 8757 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQS_P :: reserved2 [11:09] */ 8758 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_P_RESERVED2_MASK 0x00000e00 8759 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_P_RESERVED2_ALIGN 0 8760 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_P_RESERVED2_BITS 3 8761 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_P_RESERVED2_SHIFT 9 8762 8763 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQS_P :: VDL_STEP [08:00] */ 8764 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_P_VDL_STEP_MASK 0x000001ff 8765 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_P_VDL_STEP_ALIGN 0 8766 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_P_VDL_STEP_BITS 9 8767 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_P_VDL_STEP_SHIFT 0 8768 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_P_VDL_STEP_DEFAULT 0x00000000 8769 8770 /*************************************************************************** 8771 *VDL_CONTROL_WR_DQS_N - Write channel DQS-N VDL control register 8772 */ 8773 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQS_N :: BUSY [31:31] */ 8774 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_N_BUSY_MASK 0x80000000 8775 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_N_BUSY_ALIGN 0 8776 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_N_BUSY_BITS 1 8777 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_N_BUSY_SHIFT 31 8778 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_N_BUSY_DEFAULT 0x00000000 8779 8780 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQS_N :: reserved0 [30:17] */ 8781 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_N_RESERVED0_MASK 0x7ffe0000 8782 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_N_RESERVED0_ALIGN 0 8783 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_N_RESERVED0_BITS 14 8784 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_N_RESERVED0_SHIFT 17 8785 8786 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQS_N :: FORCE [16:16] */ 8787 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_N_FORCE_MASK 0x00010000 8788 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_N_FORCE_ALIGN 0 8789 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_N_FORCE_BITS 1 8790 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_N_FORCE_SHIFT 16 8791 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_N_FORCE_DEFAULT 0x00000000 8792 8793 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQS_N :: reserved1 [15:13] */ 8794 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_N_RESERVED1_MASK 0x0000e000 8795 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_N_RESERVED1_ALIGN 0 8796 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_N_RESERVED1_BITS 3 8797 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_N_RESERVED1_SHIFT 13 8798 8799 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQS_N :: ADJ_EN [12:12] */ 8800 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_N_ADJ_EN_MASK 0x00001000 8801 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_N_ADJ_EN_ALIGN 0 8802 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_N_ADJ_EN_BITS 1 8803 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_N_ADJ_EN_SHIFT 12 8804 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_N_ADJ_EN_DEFAULT 0x00000000 8805 8806 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQS_N :: reserved2 [11:09] */ 8807 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_N_RESERVED2_MASK 0x00000e00 8808 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_N_RESERVED2_ALIGN 0 8809 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_N_RESERVED2_BITS 3 8810 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_N_RESERVED2_SHIFT 9 8811 8812 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQS_N :: VDL_STEP [08:00] */ 8813 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_N_VDL_STEP_MASK 0x000001ff 8814 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_N_VDL_STEP_ALIGN 0 8815 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_N_VDL_STEP_BITS 9 8816 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_N_VDL_STEP_SHIFT 0 8817 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_N_VDL_STEP_DEFAULT 0x00000000 8818 8819 /*************************************************************************** 8820 *VDL_CONTROL_WR_DQ0 - Write channel DQ0 VDL control register 8821 */ 8822 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ0 :: BUSY [31:31] */ 8823 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0_BUSY_MASK 0x80000000 8824 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0_BUSY_ALIGN 0 8825 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0_BUSY_BITS 1 8826 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0_BUSY_SHIFT 31 8827 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0_BUSY_DEFAULT 0x00000000 8828 8829 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ0 :: reserved0 [30:17] */ 8830 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0_RESERVED0_MASK 0x7ffe0000 8831 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0_RESERVED0_ALIGN 0 8832 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0_RESERVED0_BITS 14 8833 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0_RESERVED0_SHIFT 17 8834 8835 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ0 :: FORCE [16:16] */ 8836 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0_FORCE_MASK 0x00010000 8837 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0_FORCE_ALIGN 0 8838 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0_FORCE_BITS 1 8839 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0_FORCE_SHIFT 16 8840 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0_FORCE_DEFAULT 0x00000000 8841 8842 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ0 :: reserved1 [15:13] */ 8843 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0_RESERVED1_MASK 0x0000e000 8844 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0_RESERVED1_ALIGN 0 8845 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0_RESERVED1_BITS 3 8846 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0_RESERVED1_SHIFT 13 8847 8848 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ0 :: ADJ_EN [12:12] */ 8849 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0_ADJ_EN_MASK 0x00001000 8850 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0_ADJ_EN_ALIGN 0 8851 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0_ADJ_EN_BITS 1 8852 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0_ADJ_EN_SHIFT 12 8853 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0_ADJ_EN_DEFAULT 0x00000000 8854 8855 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ0 :: reserved2 [11:09] */ 8856 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0_RESERVED2_MASK 0x00000e00 8857 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0_RESERVED2_ALIGN 0 8858 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0_RESERVED2_BITS 3 8859 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0_RESERVED2_SHIFT 9 8860 8861 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ0 :: VDL_STEP [08:00] */ 8862 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0_VDL_STEP_MASK 0x000001ff 8863 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0_VDL_STEP_ALIGN 0 8864 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0_VDL_STEP_BITS 9 8865 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0_VDL_STEP_SHIFT 0 8866 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0_VDL_STEP_DEFAULT 0x00000000 8867 8868 /*************************************************************************** 8869 *VDL_CONTROL_WR_DQ1 - Write channel DQ1 VDL control register 8870 */ 8871 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ1 :: BUSY [31:31] */ 8872 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1_BUSY_MASK 0x80000000 8873 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1_BUSY_ALIGN 0 8874 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1_BUSY_BITS 1 8875 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1_BUSY_SHIFT 31 8876 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1_BUSY_DEFAULT 0x00000000 8877 8878 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ1 :: reserved0 [30:17] */ 8879 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1_RESERVED0_MASK 0x7ffe0000 8880 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1_RESERVED0_ALIGN 0 8881 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1_RESERVED0_BITS 14 8882 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1_RESERVED0_SHIFT 17 8883 8884 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ1 :: FORCE [16:16] */ 8885 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1_FORCE_MASK 0x00010000 8886 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1_FORCE_ALIGN 0 8887 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1_FORCE_BITS 1 8888 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1_FORCE_SHIFT 16 8889 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1_FORCE_DEFAULT 0x00000000 8890 8891 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ1 :: reserved1 [15:13] */ 8892 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1_RESERVED1_MASK 0x0000e000 8893 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1_RESERVED1_ALIGN 0 8894 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1_RESERVED1_BITS 3 8895 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1_RESERVED1_SHIFT 13 8896 8897 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ1 :: ADJ_EN [12:12] */ 8898 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1_ADJ_EN_MASK 0x00001000 8899 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1_ADJ_EN_ALIGN 0 8900 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1_ADJ_EN_BITS 1 8901 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1_ADJ_EN_SHIFT 12 8902 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1_ADJ_EN_DEFAULT 0x00000000 8903 8904 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ1 :: reserved2 [11:09] */ 8905 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1_RESERVED2_MASK 0x00000e00 8906 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1_RESERVED2_ALIGN 0 8907 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1_RESERVED2_BITS 3 8908 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1_RESERVED2_SHIFT 9 8909 8910 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ1 :: VDL_STEP [08:00] */ 8911 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1_VDL_STEP_MASK 0x000001ff 8912 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1_VDL_STEP_ALIGN 0 8913 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1_VDL_STEP_BITS 9 8914 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1_VDL_STEP_SHIFT 0 8915 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1_VDL_STEP_DEFAULT 0x00000000 8916 8917 /*************************************************************************** 8918 *VDL_CONTROL_WR_DQ2 - Write channel DQ2 VDL control register 8919 */ 8920 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ2 :: BUSY [31:31] */ 8921 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2_BUSY_MASK 0x80000000 8922 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2_BUSY_ALIGN 0 8923 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2_BUSY_BITS 1 8924 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2_BUSY_SHIFT 31 8925 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2_BUSY_DEFAULT 0x00000000 8926 8927 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ2 :: reserved0 [30:17] */ 8928 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2_RESERVED0_MASK 0x7ffe0000 8929 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2_RESERVED0_ALIGN 0 8930 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2_RESERVED0_BITS 14 8931 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2_RESERVED0_SHIFT 17 8932 8933 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ2 :: FORCE [16:16] */ 8934 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2_FORCE_MASK 0x00010000 8935 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2_FORCE_ALIGN 0 8936 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2_FORCE_BITS 1 8937 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2_FORCE_SHIFT 16 8938 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2_FORCE_DEFAULT 0x00000000 8939 8940 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ2 :: reserved1 [15:13] */ 8941 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2_RESERVED1_MASK 0x0000e000 8942 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2_RESERVED1_ALIGN 0 8943 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2_RESERVED1_BITS 3 8944 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2_RESERVED1_SHIFT 13 8945 8946 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ2 :: ADJ_EN [12:12] */ 8947 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2_ADJ_EN_MASK 0x00001000 8948 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2_ADJ_EN_ALIGN 0 8949 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2_ADJ_EN_BITS 1 8950 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2_ADJ_EN_SHIFT 12 8951 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2_ADJ_EN_DEFAULT 0x00000000 8952 8953 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ2 :: reserved2 [11:09] */ 8954 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2_RESERVED2_MASK 0x00000e00 8955 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2_RESERVED2_ALIGN 0 8956 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2_RESERVED2_BITS 3 8957 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2_RESERVED2_SHIFT 9 8958 8959 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ2 :: VDL_STEP [08:00] */ 8960 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2_VDL_STEP_MASK 0x000001ff 8961 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2_VDL_STEP_ALIGN 0 8962 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2_VDL_STEP_BITS 9 8963 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2_VDL_STEP_SHIFT 0 8964 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2_VDL_STEP_DEFAULT 0x00000000 8965 8966 /*************************************************************************** 8967 *VDL_CONTROL_WR_DQ3 - Write channel DQ3 VDL control register 8968 */ 8969 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ3 :: BUSY [31:31] */ 8970 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3_BUSY_MASK 0x80000000 8971 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3_BUSY_ALIGN 0 8972 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3_BUSY_BITS 1 8973 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3_BUSY_SHIFT 31 8974 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3_BUSY_DEFAULT 0x00000000 8975 8976 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ3 :: reserved0 [30:17] */ 8977 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3_RESERVED0_MASK 0x7ffe0000 8978 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3_RESERVED0_ALIGN 0 8979 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3_RESERVED0_BITS 14 8980 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3_RESERVED0_SHIFT 17 8981 8982 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ3 :: FORCE [16:16] */ 8983 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3_FORCE_MASK 0x00010000 8984 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3_FORCE_ALIGN 0 8985 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3_FORCE_BITS 1 8986 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3_FORCE_SHIFT 16 8987 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3_FORCE_DEFAULT 0x00000000 8988 8989 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ3 :: reserved1 [15:13] */ 8990 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3_RESERVED1_MASK 0x0000e000 8991 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3_RESERVED1_ALIGN 0 8992 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3_RESERVED1_BITS 3 8993 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3_RESERVED1_SHIFT 13 8994 8995 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ3 :: ADJ_EN [12:12] */ 8996 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3_ADJ_EN_MASK 0x00001000 8997 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3_ADJ_EN_ALIGN 0 8998 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3_ADJ_EN_BITS 1 8999 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3_ADJ_EN_SHIFT 12 9000 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3_ADJ_EN_DEFAULT 0x00000000 9001 9002 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ3 :: reserved2 [11:09] */ 9003 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3_RESERVED2_MASK 0x00000e00 9004 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3_RESERVED2_ALIGN 0 9005 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3_RESERVED2_BITS 3 9006 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3_RESERVED2_SHIFT 9 9007 9008 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ3 :: VDL_STEP [08:00] */ 9009 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3_VDL_STEP_MASK 0x000001ff 9010 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3_VDL_STEP_ALIGN 0 9011 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3_VDL_STEP_BITS 9 9012 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3_VDL_STEP_SHIFT 0 9013 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3_VDL_STEP_DEFAULT 0x00000000 9014 9015 /*************************************************************************** 9016 *VDL_CONTROL_WR_DQ4 - Write channel DQ4 VDL control register 9017 */ 9018 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ4 :: BUSY [31:31] */ 9019 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4_BUSY_MASK 0x80000000 9020 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4_BUSY_ALIGN 0 9021 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4_BUSY_BITS 1 9022 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4_BUSY_SHIFT 31 9023 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4_BUSY_DEFAULT 0x00000000 9024 9025 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ4 :: reserved0 [30:17] */ 9026 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4_RESERVED0_MASK 0x7ffe0000 9027 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4_RESERVED0_ALIGN 0 9028 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4_RESERVED0_BITS 14 9029 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4_RESERVED0_SHIFT 17 9030 9031 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ4 :: FORCE [16:16] */ 9032 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4_FORCE_MASK 0x00010000 9033 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4_FORCE_ALIGN 0 9034 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4_FORCE_BITS 1 9035 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4_FORCE_SHIFT 16 9036 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4_FORCE_DEFAULT 0x00000000 9037 9038 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ4 :: reserved1 [15:13] */ 9039 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4_RESERVED1_MASK 0x0000e000 9040 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4_RESERVED1_ALIGN 0 9041 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4_RESERVED1_BITS 3 9042 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4_RESERVED1_SHIFT 13 9043 9044 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ4 :: ADJ_EN [12:12] */ 9045 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4_ADJ_EN_MASK 0x00001000 9046 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4_ADJ_EN_ALIGN 0 9047 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4_ADJ_EN_BITS 1 9048 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4_ADJ_EN_SHIFT 12 9049 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4_ADJ_EN_DEFAULT 0x00000000 9050 9051 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ4 :: reserved2 [11:09] */ 9052 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4_RESERVED2_MASK 0x00000e00 9053 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4_RESERVED2_ALIGN 0 9054 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4_RESERVED2_BITS 3 9055 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4_RESERVED2_SHIFT 9 9056 9057 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ4 :: VDL_STEP [08:00] */ 9058 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4_VDL_STEP_MASK 0x000001ff 9059 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4_VDL_STEP_ALIGN 0 9060 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4_VDL_STEP_BITS 9 9061 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4_VDL_STEP_SHIFT 0 9062 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4_VDL_STEP_DEFAULT 0x00000000 9063 9064 /*************************************************************************** 9065 *VDL_CONTROL_WR_DQ5 - Write channel DQ5 VDL control register 9066 */ 9067 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ5 :: BUSY [31:31] */ 9068 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5_BUSY_MASK 0x80000000 9069 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5_BUSY_ALIGN 0 9070 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5_BUSY_BITS 1 9071 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5_BUSY_SHIFT 31 9072 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5_BUSY_DEFAULT 0x00000000 9073 9074 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ5 :: reserved0 [30:17] */ 9075 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5_RESERVED0_MASK 0x7ffe0000 9076 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5_RESERVED0_ALIGN 0 9077 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5_RESERVED0_BITS 14 9078 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5_RESERVED0_SHIFT 17 9079 9080 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ5 :: FORCE [16:16] */ 9081 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5_FORCE_MASK 0x00010000 9082 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5_FORCE_ALIGN 0 9083 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5_FORCE_BITS 1 9084 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5_FORCE_SHIFT 16 9085 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5_FORCE_DEFAULT 0x00000000 9086 9087 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ5 :: reserved1 [15:13] */ 9088 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5_RESERVED1_MASK 0x0000e000 9089 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5_RESERVED1_ALIGN 0 9090 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5_RESERVED1_BITS 3 9091 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5_RESERVED1_SHIFT 13 9092 9093 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ5 :: ADJ_EN [12:12] */ 9094 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5_ADJ_EN_MASK 0x00001000 9095 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5_ADJ_EN_ALIGN 0 9096 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5_ADJ_EN_BITS 1 9097 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5_ADJ_EN_SHIFT 12 9098 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5_ADJ_EN_DEFAULT 0x00000000 9099 9100 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ5 :: reserved2 [11:09] */ 9101 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5_RESERVED2_MASK 0x00000e00 9102 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5_RESERVED2_ALIGN 0 9103 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5_RESERVED2_BITS 3 9104 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5_RESERVED2_SHIFT 9 9105 9106 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ5 :: VDL_STEP [08:00] */ 9107 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5_VDL_STEP_MASK 0x000001ff 9108 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5_VDL_STEP_ALIGN 0 9109 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5_VDL_STEP_BITS 9 9110 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5_VDL_STEP_SHIFT 0 9111 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5_VDL_STEP_DEFAULT 0x00000000 9112 9113 /*************************************************************************** 9114 *VDL_CONTROL_WR_DQ6 - Write channel DQ6 VDL control register 9115 */ 9116 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ6 :: BUSY [31:31] */ 9117 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6_BUSY_MASK 0x80000000 9118 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6_BUSY_ALIGN 0 9119 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6_BUSY_BITS 1 9120 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6_BUSY_SHIFT 31 9121 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6_BUSY_DEFAULT 0x00000000 9122 9123 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ6 :: reserved0 [30:17] */ 9124 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6_RESERVED0_MASK 0x7ffe0000 9125 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6_RESERVED0_ALIGN 0 9126 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6_RESERVED0_BITS 14 9127 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6_RESERVED0_SHIFT 17 9128 9129 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ6 :: FORCE [16:16] */ 9130 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6_FORCE_MASK 0x00010000 9131 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6_FORCE_ALIGN 0 9132 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6_FORCE_BITS 1 9133 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6_FORCE_SHIFT 16 9134 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6_FORCE_DEFAULT 0x00000000 9135 9136 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ6 :: reserved1 [15:13] */ 9137 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6_RESERVED1_MASK 0x0000e000 9138 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6_RESERVED1_ALIGN 0 9139 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6_RESERVED1_BITS 3 9140 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6_RESERVED1_SHIFT 13 9141 9142 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ6 :: ADJ_EN [12:12] */ 9143 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6_ADJ_EN_MASK 0x00001000 9144 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6_ADJ_EN_ALIGN 0 9145 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6_ADJ_EN_BITS 1 9146 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6_ADJ_EN_SHIFT 12 9147 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6_ADJ_EN_DEFAULT 0x00000000 9148 9149 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ6 :: reserved2 [11:09] */ 9150 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6_RESERVED2_MASK 0x00000e00 9151 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6_RESERVED2_ALIGN 0 9152 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6_RESERVED2_BITS 3 9153 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6_RESERVED2_SHIFT 9 9154 9155 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ6 :: VDL_STEP [08:00] */ 9156 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6_VDL_STEP_MASK 0x000001ff 9157 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6_VDL_STEP_ALIGN 0 9158 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6_VDL_STEP_BITS 9 9159 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6_VDL_STEP_SHIFT 0 9160 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6_VDL_STEP_DEFAULT 0x00000000 9161 9162 /*************************************************************************** 9163 *VDL_CONTROL_WR_DQ7 - Write channel DQ7 VDL control register 9164 */ 9165 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ7 :: BUSY [31:31] */ 9166 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7_BUSY_MASK 0x80000000 9167 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7_BUSY_ALIGN 0 9168 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7_BUSY_BITS 1 9169 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7_BUSY_SHIFT 31 9170 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7_BUSY_DEFAULT 0x00000000 9171 9172 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ7 :: reserved0 [30:17] */ 9173 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7_RESERVED0_MASK 0x7ffe0000 9174 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7_RESERVED0_ALIGN 0 9175 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7_RESERVED0_BITS 14 9176 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7_RESERVED0_SHIFT 17 9177 9178 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ7 :: FORCE [16:16] */ 9179 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7_FORCE_MASK 0x00010000 9180 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7_FORCE_ALIGN 0 9181 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7_FORCE_BITS 1 9182 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7_FORCE_SHIFT 16 9183 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7_FORCE_DEFAULT 0x00000000 9184 9185 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ7 :: reserved1 [15:13] */ 9186 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7_RESERVED1_MASK 0x0000e000 9187 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7_RESERVED1_ALIGN 0 9188 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7_RESERVED1_BITS 3 9189 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7_RESERVED1_SHIFT 13 9190 9191 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ7 :: ADJ_EN [12:12] */ 9192 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7_ADJ_EN_MASK 0x00001000 9193 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7_ADJ_EN_ALIGN 0 9194 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7_ADJ_EN_BITS 1 9195 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7_ADJ_EN_SHIFT 12 9196 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7_ADJ_EN_DEFAULT 0x00000000 9197 9198 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ7 :: reserved2 [11:09] */ 9199 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7_RESERVED2_MASK 0x00000e00 9200 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7_RESERVED2_ALIGN 0 9201 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7_RESERVED2_BITS 3 9202 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7_RESERVED2_SHIFT 9 9203 9204 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ7 :: VDL_STEP [08:00] */ 9205 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7_VDL_STEP_MASK 0x000001ff 9206 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7_VDL_STEP_ALIGN 0 9207 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7_VDL_STEP_BITS 9 9208 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7_VDL_STEP_SHIFT 0 9209 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7_VDL_STEP_DEFAULT 0x00000000 9210 9211 /*************************************************************************** 9212 *VDL_CONTROL_WR_DM - Write channel DM VDL control register 9213 */ 9214 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DM :: BUSY [31:31] */ 9215 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DM_BUSY_MASK 0x80000000 9216 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DM_BUSY_ALIGN 0 9217 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DM_BUSY_BITS 1 9218 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DM_BUSY_SHIFT 31 9219 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DM_BUSY_DEFAULT 0x00000000 9220 9221 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DM :: reserved0 [30:17] */ 9222 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DM_RESERVED0_MASK 0x7ffe0000 9223 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DM_RESERVED0_ALIGN 0 9224 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DM_RESERVED0_BITS 14 9225 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DM_RESERVED0_SHIFT 17 9226 9227 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DM :: FORCE [16:16] */ 9228 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DM_FORCE_MASK 0x00010000 9229 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DM_FORCE_ALIGN 0 9230 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DM_FORCE_BITS 1 9231 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DM_FORCE_SHIFT 16 9232 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DM_FORCE_DEFAULT 0x00000000 9233 9234 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DM :: reserved1 [15:13] */ 9235 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DM_RESERVED1_MASK 0x0000e000 9236 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DM_RESERVED1_ALIGN 0 9237 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DM_RESERVED1_BITS 3 9238 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DM_RESERVED1_SHIFT 13 9239 9240 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DM :: ADJ_EN [12:12] */ 9241 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DM_ADJ_EN_MASK 0x00001000 9242 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DM_ADJ_EN_ALIGN 0 9243 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DM_ADJ_EN_BITS 1 9244 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DM_ADJ_EN_SHIFT 12 9245 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DM_ADJ_EN_DEFAULT 0x00000000 9246 9247 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DM :: reserved2 [11:09] */ 9248 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DM_RESERVED2_MASK 0x00000e00 9249 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DM_RESERVED2_ALIGN 0 9250 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DM_RESERVED2_BITS 3 9251 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DM_RESERVED2_SHIFT 9 9252 9253 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DM :: VDL_STEP [08:00] */ 9254 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DM_VDL_STEP_MASK 0x000001ff 9255 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DM_VDL_STEP_ALIGN 0 9256 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DM_VDL_STEP_BITS 9 9257 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DM_VDL_STEP_SHIFT 0 9258 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DM_VDL_STEP_DEFAULT 0x00000000 9259 9260 /*************************************************************************** 9261 *VDL_CONTROL_WR_EDC - Write channel EDC VDL control register 9262 */ 9263 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_EDC :: BUSY [31:31] */ 9264 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_EDC_BUSY_MASK 0x80000000 9265 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_EDC_BUSY_ALIGN 0 9266 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_EDC_BUSY_BITS 1 9267 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_EDC_BUSY_SHIFT 31 9268 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_EDC_BUSY_DEFAULT 0x00000000 9269 9270 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_EDC :: reserved0 [30:17] */ 9271 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_EDC_RESERVED0_MASK 0x7ffe0000 9272 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_EDC_RESERVED0_ALIGN 0 9273 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_EDC_RESERVED0_BITS 14 9274 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_EDC_RESERVED0_SHIFT 17 9275 9276 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_EDC :: FORCE [16:16] */ 9277 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_EDC_FORCE_MASK 0x00010000 9278 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_EDC_FORCE_ALIGN 0 9279 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_EDC_FORCE_BITS 1 9280 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_EDC_FORCE_SHIFT 16 9281 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_EDC_FORCE_DEFAULT 0x00000000 9282 9283 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_EDC :: reserved1 [15:13] */ 9284 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_EDC_RESERVED1_MASK 0x0000e000 9285 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_EDC_RESERVED1_ALIGN 0 9286 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_EDC_RESERVED1_BITS 3 9287 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_EDC_RESERVED1_SHIFT 13 9288 9289 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_EDC :: ADJ_EN [12:12] */ 9290 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_EDC_ADJ_EN_MASK 0x00001000 9291 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_EDC_ADJ_EN_ALIGN 0 9292 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_EDC_ADJ_EN_BITS 1 9293 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_EDC_ADJ_EN_SHIFT 12 9294 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_EDC_ADJ_EN_DEFAULT 0x00000000 9295 9296 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_EDC :: reserved2 [11:09] */ 9297 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_EDC_RESERVED2_MASK 0x00000e00 9298 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_EDC_RESERVED2_ALIGN 0 9299 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_EDC_RESERVED2_BITS 3 9300 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_EDC_RESERVED2_SHIFT 9 9301 9302 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_EDC :: VDL_STEP [08:00] */ 9303 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_EDC_VDL_STEP_MASK 0x000001ff 9304 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_EDC_VDL_STEP_ALIGN 0 9305 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_EDC_VDL_STEP_BITS 9 9306 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_EDC_VDL_STEP_SHIFT 0 9307 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_EDC_VDL_STEP_DEFAULT 0x00000000 9308 9309 /*************************************************************************** 9310 *VDL_CONTROL_RD_DQSP - Read channel DQSP VDL control register 9311 */ 9312 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQSP :: BUSY [31:31] */ 9313 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSP_BUSY_MASK 0x80000000 9314 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSP_BUSY_ALIGN 0 9315 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSP_BUSY_BITS 1 9316 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSP_BUSY_SHIFT 31 9317 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSP_BUSY_DEFAULT 0x00000000 9318 9319 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQSP :: reserved0 [30:17] */ 9320 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSP_RESERVED0_MASK 0x7ffe0000 9321 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSP_RESERVED0_ALIGN 0 9322 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSP_RESERVED0_BITS 14 9323 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSP_RESERVED0_SHIFT 17 9324 9325 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQSP :: FORCE [16:16] */ 9326 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSP_FORCE_MASK 0x00010000 9327 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSP_FORCE_ALIGN 0 9328 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSP_FORCE_BITS 1 9329 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSP_FORCE_SHIFT 16 9330 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSP_FORCE_DEFAULT 0x00000000 9331 9332 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQSP :: reserved1 [15:13] */ 9333 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSP_RESERVED1_MASK 0x0000e000 9334 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSP_RESERVED1_ALIGN 0 9335 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSP_RESERVED1_BITS 3 9336 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSP_RESERVED1_SHIFT 13 9337 9338 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQSP :: ADJ_EN [12:12] */ 9339 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSP_ADJ_EN_MASK 0x00001000 9340 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSP_ADJ_EN_ALIGN 0 9341 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSP_ADJ_EN_BITS 1 9342 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSP_ADJ_EN_SHIFT 12 9343 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSP_ADJ_EN_DEFAULT 0x00000000 9344 9345 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQSP :: reserved2 [11:08] */ 9346 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSP_RESERVED2_MASK 0x00000f00 9347 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSP_RESERVED2_ALIGN 0 9348 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSP_RESERVED2_BITS 4 9349 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSP_RESERVED2_SHIFT 8 9350 9351 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQSP :: VDL_STEP [07:00] */ 9352 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSP_VDL_STEP_MASK 0x000000ff 9353 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSP_VDL_STEP_ALIGN 0 9354 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSP_VDL_STEP_BITS 8 9355 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSP_VDL_STEP_SHIFT 0 9356 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSP_VDL_STEP_DEFAULT 0x00000000 9357 9358 /*************************************************************************** 9359 *VDL_CONTROL_RD_DQSN - Read channel DQSP VDL control register 9360 */ 9361 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQSN :: BUSY [31:31] */ 9362 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSN_BUSY_MASK 0x80000000 9363 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSN_BUSY_ALIGN 0 9364 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSN_BUSY_BITS 1 9365 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSN_BUSY_SHIFT 31 9366 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSN_BUSY_DEFAULT 0x00000000 9367 9368 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQSN :: reserved0 [30:17] */ 9369 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSN_RESERVED0_MASK 0x7ffe0000 9370 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSN_RESERVED0_ALIGN 0 9371 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSN_RESERVED0_BITS 14 9372 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSN_RESERVED0_SHIFT 17 9373 9374 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQSN :: FORCE [16:16] */ 9375 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSN_FORCE_MASK 0x00010000 9376 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSN_FORCE_ALIGN 0 9377 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSN_FORCE_BITS 1 9378 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSN_FORCE_SHIFT 16 9379 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSN_FORCE_DEFAULT 0x00000000 9380 9381 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQSN :: reserved1 [15:13] */ 9382 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSN_RESERVED1_MASK 0x0000e000 9383 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSN_RESERVED1_ALIGN 0 9384 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSN_RESERVED1_BITS 3 9385 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSN_RESERVED1_SHIFT 13 9386 9387 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQSN :: ADJ_EN [12:12] */ 9388 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSN_ADJ_EN_MASK 0x00001000 9389 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSN_ADJ_EN_ALIGN 0 9390 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSN_ADJ_EN_BITS 1 9391 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSN_ADJ_EN_SHIFT 12 9392 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSN_ADJ_EN_DEFAULT 0x00000000 9393 9394 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQSN :: reserved2 [11:08] */ 9395 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSN_RESERVED2_MASK 0x00000f00 9396 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSN_RESERVED2_ALIGN 0 9397 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSN_RESERVED2_BITS 4 9398 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSN_RESERVED2_SHIFT 8 9399 9400 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQSN :: VDL_STEP [07:00] */ 9401 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSN_VDL_STEP_MASK 0x000000ff 9402 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSN_VDL_STEP_ALIGN 0 9403 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSN_VDL_STEP_BITS 8 9404 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSN_VDL_STEP_SHIFT 0 9405 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSN_VDL_STEP_DEFAULT 0x00000000 9406 9407 /*************************************************************************** 9408 *VDL_CONTROL_RD_DQ0P - Read channel DQ0-P VDL control register 9409 */ 9410 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ0P :: BUSY [31:31] */ 9411 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0P_BUSY_MASK 0x80000000 9412 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0P_BUSY_ALIGN 0 9413 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0P_BUSY_BITS 1 9414 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0P_BUSY_SHIFT 31 9415 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0P_BUSY_DEFAULT 0x00000000 9416 9417 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ0P :: reserved0 [30:17] */ 9418 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0P_RESERVED0_MASK 0x7ffe0000 9419 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0P_RESERVED0_ALIGN 0 9420 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0P_RESERVED0_BITS 14 9421 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0P_RESERVED0_SHIFT 17 9422 9423 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ0P :: FORCE [16:16] */ 9424 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0P_FORCE_MASK 0x00010000 9425 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0P_FORCE_ALIGN 0 9426 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0P_FORCE_BITS 1 9427 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0P_FORCE_SHIFT 16 9428 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0P_FORCE_DEFAULT 0x00000000 9429 9430 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ0P :: reserved1 [15:13] */ 9431 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0P_RESERVED1_MASK 0x0000e000 9432 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0P_RESERVED1_ALIGN 0 9433 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0P_RESERVED1_BITS 3 9434 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0P_RESERVED1_SHIFT 13 9435 9436 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ0P :: ADJ_EN [12:12] */ 9437 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0P_ADJ_EN_MASK 0x00001000 9438 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0P_ADJ_EN_ALIGN 0 9439 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0P_ADJ_EN_BITS 1 9440 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0P_ADJ_EN_SHIFT 12 9441 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0P_ADJ_EN_DEFAULT 0x00000000 9442 9443 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ0P :: reserved2 [11:08] */ 9444 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0P_RESERVED2_MASK 0x00000f00 9445 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0P_RESERVED2_ALIGN 0 9446 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0P_RESERVED2_BITS 4 9447 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0P_RESERVED2_SHIFT 8 9448 9449 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ0P :: VDL_STEP [07:00] */ 9450 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0P_VDL_STEP_MASK 0x000000ff 9451 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0P_VDL_STEP_ALIGN 0 9452 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0P_VDL_STEP_BITS 8 9453 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0P_VDL_STEP_SHIFT 0 9454 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0P_VDL_STEP_DEFAULT 0x00000000 9455 9456 /*************************************************************************** 9457 *VDL_CONTROL_RD_DQ0N - Read channel DQ0-N VDL control register 9458 */ 9459 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ0N :: BUSY [31:31] */ 9460 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0N_BUSY_MASK 0x80000000 9461 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0N_BUSY_ALIGN 0 9462 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0N_BUSY_BITS 1 9463 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0N_BUSY_SHIFT 31 9464 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0N_BUSY_DEFAULT 0x00000000 9465 9466 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ0N :: reserved0 [30:17] */ 9467 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0N_RESERVED0_MASK 0x7ffe0000 9468 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0N_RESERVED0_ALIGN 0 9469 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0N_RESERVED0_BITS 14 9470 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0N_RESERVED0_SHIFT 17 9471 9472 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ0N :: FORCE [16:16] */ 9473 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0N_FORCE_MASK 0x00010000 9474 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0N_FORCE_ALIGN 0 9475 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0N_FORCE_BITS 1 9476 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0N_FORCE_SHIFT 16 9477 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0N_FORCE_DEFAULT 0x00000000 9478 9479 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ0N :: reserved1 [15:13] */ 9480 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0N_RESERVED1_MASK 0x0000e000 9481 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0N_RESERVED1_ALIGN 0 9482 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0N_RESERVED1_BITS 3 9483 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0N_RESERVED1_SHIFT 13 9484 9485 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ0N :: ADJ_EN [12:12] */ 9486 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0N_ADJ_EN_MASK 0x00001000 9487 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0N_ADJ_EN_ALIGN 0 9488 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0N_ADJ_EN_BITS 1 9489 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0N_ADJ_EN_SHIFT 12 9490 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0N_ADJ_EN_DEFAULT 0x00000000 9491 9492 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ0N :: reserved2 [11:08] */ 9493 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0N_RESERVED2_MASK 0x00000f00 9494 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0N_RESERVED2_ALIGN 0 9495 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0N_RESERVED2_BITS 4 9496 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0N_RESERVED2_SHIFT 8 9497 9498 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ0N :: VDL_STEP [07:00] */ 9499 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0N_VDL_STEP_MASK 0x000000ff 9500 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0N_VDL_STEP_ALIGN 0 9501 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0N_VDL_STEP_BITS 8 9502 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0N_VDL_STEP_SHIFT 0 9503 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0N_VDL_STEP_DEFAULT 0x00000000 9504 9505 /*************************************************************************** 9506 *VDL_CONTROL_RD_DQ1P - Read channel DQ1-P VDL control register 9507 */ 9508 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ1P :: BUSY [31:31] */ 9509 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1P_BUSY_MASK 0x80000000 9510 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1P_BUSY_ALIGN 0 9511 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1P_BUSY_BITS 1 9512 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1P_BUSY_SHIFT 31 9513 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1P_BUSY_DEFAULT 0x00000000 9514 9515 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ1P :: reserved0 [30:17] */ 9516 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1P_RESERVED0_MASK 0x7ffe0000 9517 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1P_RESERVED0_ALIGN 0 9518 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1P_RESERVED0_BITS 14 9519 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1P_RESERVED0_SHIFT 17 9520 9521 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ1P :: FORCE [16:16] */ 9522 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1P_FORCE_MASK 0x00010000 9523 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1P_FORCE_ALIGN 0 9524 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1P_FORCE_BITS 1 9525 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1P_FORCE_SHIFT 16 9526 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1P_FORCE_DEFAULT 0x00000000 9527 9528 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ1P :: reserved1 [15:13] */ 9529 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1P_RESERVED1_MASK 0x0000e000 9530 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1P_RESERVED1_ALIGN 0 9531 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1P_RESERVED1_BITS 3 9532 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1P_RESERVED1_SHIFT 13 9533 9534 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ1P :: ADJ_EN [12:12] */ 9535 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1P_ADJ_EN_MASK 0x00001000 9536 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1P_ADJ_EN_ALIGN 0 9537 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1P_ADJ_EN_BITS 1 9538 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1P_ADJ_EN_SHIFT 12 9539 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1P_ADJ_EN_DEFAULT 0x00000000 9540 9541 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ1P :: reserved2 [11:08] */ 9542 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1P_RESERVED2_MASK 0x00000f00 9543 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1P_RESERVED2_ALIGN 0 9544 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1P_RESERVED2_BITS 4 9545 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1P_RESERVED2_SHIFT 8 9546 9547 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ1P :: VDL_STEP [07:00] */ 9548 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1P_VDL_STEP_MASK 0x000000ff 9549 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1P_VDL_STEP_ALIGN 0 9550 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1P_VDL_STEP_BITS 8 9551 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1P_VDL_STEP_SHIFT 0 9552 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1P_VDL_STEP_DEFAULT 0x00000000 9553 9554 /*************************************************************************** 9555 *VDL_CONTROL_RD_DQ1N - Read channel DQ1-N VDL control register 9556 */ 9557 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ1N :: BUSY [31:31] */ 9558 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1N_BUSY_MASK 0x80000000 9559 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1N_BUSY_ALIGN 0 9560 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1N_BUSY_BITS 1 9561 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1N_BUSY_SHIFT 31 9562 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1N_BUSY_DEFAULT 0x00000000 9563 9564 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ1N :: reserved0 [30:17] */ 9565 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1N_RESERVED0_MASK 0x7ffe0000 9566 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1N_RESERVED0_ALIGN 0 9567 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1N_RESERVED0_BITS 14 9568 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1N_RESERVED0_SHIFT 17 9569 9570 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ1N :: FORCE [16:16] */ 9571 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1N_FORCE_MASK 0x00010000 9572 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1N_FORCE_ALIGN 0 9573 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1N_FORCE_BITS 1 9574 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1N_FORCE_SHIFT 16 9575 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1N_FORCE_DEFAULT 0x00000000 9576 9577 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ1N :: reserved1 [15:13] */ 9578 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1N_RESERVED1_MASK 0x0000e000 9579 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1N_RESERVED1_ALIGN 0 9580 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1N_RESERVED1_BITS 3 9581 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1N_RESERVED1_SHIFT 13 9582 9583 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ1N :: ADJ_EN [12:12] */ 9584 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1N_ADJ_EN_MASK 0x00001000 9585 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1N_ADJ_EN_ALIGN 0 9586 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1N_ADJ_EN_BITS 1 9587 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1N_ADJ_EN_SHIFT 12 9588 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1N_ADJ_EN_DEFAULT 0x00000000 9589 9590 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ1N :: reserved2 [11:08] */ 9591 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1N_RESERVED2_MASK 0x00000f00 9592 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1N_RESERVED2_ALIGN 0 9593 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1N_RESERVED2_BITS 4 9594 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1N_RESERVED2_SHIFT 8 9595 9596 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ1N :: VDL_STEP [07:00] */ 9597 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1N_VDL_STEP_MASK 0x000000ff 9598 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1N_VDL_STEP_ALIGN 0 9599 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1N_VDL_STEP_BITS 8 9600 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1N_VDL_STEP_SHIFT 0 9601 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1N_VDL_STEP_DEFAULT 0x00000000 9602 9603 /*************************************************************************** 9604 *VDL_CONTROL_RD_DQ2P - Read channel DQ2-P VDL control register 9605 */ 9606 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ2P :: BUSY [31:31] */ 9607 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2P_BUSY_MASK 0x80000000 9608 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2P_BUSY_ALIGN 0 9609 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2P_BUSY_BITS 1 9610 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2P_BUSY_SHIFT 31 9611 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2P_BUSY_DEFAULT 0x00000000 9612 9613 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ2P :: reserved0 [30:17] */ 9614 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2P_RESERVED0_MASK 0x7ffe0000 9615 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2P_RESERVED0_ALIGN 0 9616 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2P_RESERVED0_BITS 14 9617 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2P_RESERVED0_SHIFT 17 9618 9619 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ2P :: FORCE [16:16] */ 9620 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2P_FORCE_MASK 0x00010000 9621 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2P_FORCE_ALIGN 0 9622 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2P_FORCE_BITS 1 9623 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2P_FORCE_SHIFT 16 9624 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2P_FORCE_DEFAULT 0x00000000 9625 9626 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ2P :: reserved1 [15:13] */ 9627 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2P_RESERVED1_MASK 0x0000e000 9628 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2P_RESERVED1_ALIGN 0 9629 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2P_RESERVED1_BITS 3 9630 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2P_RESERVED1_SHIFT 13 9631 9632 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ2P :: ADJ_EN [12:12] */ 9633 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2P_ADJ_EN_MASK 0x00001000 9634 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2P_ADJ_EN_ALIGN 0 9635 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2P_ADJ_EN_BITS 1 9636 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2P_ADJ_EN_SHIFT 12 9637 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2P_ADJ_EN_DEFAULT 0x00000000 9638 9639 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ2P :: reserved2 [11:08] */ 9640 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2P_RESERVED2_MASK 0x00000f00 9641 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2P_RESERVED2_ALIGN 0 9642 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2P_RESERVED2_BITS 4 9643 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2P_RESERVED2_SHIFT 8 9644 9645 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ2P :: VDL_STEP [07:00] */ 9646 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2P_VDL_STEP_MASK 0x000000ff 9647 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2P_VDL_STEP_ALIGN 0 9648 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2P_VDL_STEP_BITS 8 9649 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2P_VDL_STEP_SHIFT 0 9650 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2P_VDL_STEP_DEFAULT 0x00000000 9651 9652 /*************************************************************************** 9653 *VDL_CONTROL_RD_DQ2N - Read channel DQ2-N VDL control register 9654 */ 9655 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ2N :: BUSY [31:31] */ 9656 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2N_BUSY_MASK 0x80000000 9657 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2N_BUSY_ALIGN 0 9658 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2N_BUSY_BITS 1 9659 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2N_BUSY_SHIFT 31 9660 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2N_BUSY_DEFAULT 0x00000000 9661 9662 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ2N :: reserved0 [30:17] */ 9663 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2N_RESERVED0_MASK 0x7ffe0000 9664 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2N_RESERVED0_ALIGN 0 9665 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2N_RESERVED0_BITS 14 9666 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2N_RESERVED0_SHIFT 17 9667 9668 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ2N :: FORCE [16:16] */ 9669 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2N_FORCE_MASK 0x00010000 9670 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2N_FORCE_ALIGN 0 9671 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2N_FORCE_BITS 1 9672 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2N_FORCE_SHIFT 16 9673 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2N_FORCE_DEFAULT 0x00000000 9674 9675 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ2N :: reserved1 [15:13] */ 9676 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2N_RESERVED1_MASK 0x0000e000 9677 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2N_RESERVED1_ALIGN 0 9678 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2N_RESERVED1_BITS 3 9679 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2N_RESERVED1_SHIFT 13 9680 9681 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ2N :: ADJ_EN [12:12] */ 9682 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2N_ADJ_EN_MASK 0x00001000 9683 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2N_ADJ_EN_ALIGN 0 9684 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2N_ADJ_EN_BITS 1 9685 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2N_ADJ_EN_SHIFT 12 9686 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2N_ADJ_EN_DEFAULT 0x00000000 9687 9688 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ2N :: reserved2 [11:08] */ 9689 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2N_RESERVED2_MASK 0x00000f00 9690 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2N_RESERVED2_ALIGN 0 9691 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2N_RESERVED2_BITS 4 9692 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2N_RESERVED2_SHIFT 8 9693 9694 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ2N :: VDL_STEP [07:00] */ 9695 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2N_VDL_STEP_MASK 0x000000ff 9696 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2N_VDL_STEP_ALIGN 0 9697 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2N_VDL_STEP_BITS 8 9698 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2N_VDL_STEP_SHIFT 0 9699 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2N_VDL_STEP_DEFAULT 0x00000000 9700 9701 /*************************************************************************** 9702 *VDL_CONTROL_RD_DQ3P - Read channel DQ3-P VDL control register 9703 */ 9704 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ3P :: BUSY [31:31] */ 9705 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3P_BUSY_MASK 0x80000000 9706 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3P_BUSY_ALIGN 0 9707 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3P_BUSY_BITS 1 9708 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3P_BUSY_SHIFT 31 9709 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3P_BUSY_DEFAULT 0x00000000 9710 9711 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ3P :: reserved0 [30:17] */ 9712 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3P_RESERVED0_MASK 0x7ffe0000 9713 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3P_RESERVED0_ALIGN 0 9714 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3P_RESERVED0_BITS 14 9715 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3P_RESERVED0_SHIFT 17 9716 9717 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ3P :: FORCE [16:16] */ 9718 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3P_FORCE_MASK 0x00010000 9719 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3P_FORCE_ALIGN 0 9720 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3P_FORCE_BITS 1 9721 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3P_FORCE_SHIFT 16 9722 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3P_FORCE_DEFAULT 0x00000000 9723 9724 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ3P :: reserved1 [15:13] */ 9725 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3P_RESERVED1_MASK 0x0000e000 9726 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3P_RESERVED1_ALIGN 0 9727 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3P_RESERVED1_BITS 3 9728 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3P_RESERVED1_SHIFT 13 9729 9730 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ3P :: ADJ_EN [12:12] */ 9731 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3P_ADJ_EN_MASK 0x00001000 9732 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3P_ADJ_EN_ALIGN 0 9733 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3P_ADJ_EN_BITS 1 9734 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3P_ADJ_EN_SHIFT 12 9735 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3P_ADJ_EN_DEFAULT 0x00000000 9736 9737 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ3P :: reserved2 [11:08] */ 9738 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3P_RESERVED2_MASK 0x00000f00 9739 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3P_RESERVED2_ALIGN 0 9740 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3P_RESERVED2_BITS 4 9741 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3P_RESERVED2_SHIFT 8 9742 9743 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ3P :: VDL_STEP [07:00] */ 9744 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3P_VDL_STEP_MASK 0x000000ff 9745 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3P_VDL_STEP_ALIGN 0 9746 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3P_VDL_STEP_BITS 8 9747 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3P_VDL_STEP_SHIFT 0 9748 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3P_VDL_STEP_DEFAULT 0x00000000 9749 9750 /*************************************************************************** 9751 *VDL_CONTROL_RD_DQ3N - Read channel DQ3-N VDL control register 9752 */ 9753 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ3N :: BUSY [31:31] */ 9754 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3N_BUSY_MASK 0x80000000 9755 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3N_BUSY_ALIGN 0 9756 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3N_BUSY_BITS 1 9757 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3N_BUSY_SHIFT 31 9758 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3N_BUSY_DEFAULT 0x00000000 9759 9760 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ3N :: reserved0 [30:17] */ 9761 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3N_RESERVED0_MASK 0x7ffe0000 9762 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3N_RESERVED0_ALIGN 0 9763 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3N_RESERVED0_BITS 14 9764 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3N_RESERVED0_SHIFT 17 9765 9766 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ3N :: FORCE [16:16] */ 9767 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3N_FORCE_MASK 0x00010000 9768 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3N_FORCE_ALIGN 0 9769 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3N_FORCE_BITS 1 9770 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3N_FORCE_SHIFT 16 9771 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3N_FORCE_DEFAULT 0x00000000 9772 9773 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ3N :: reserved1 [15:13] */ 9774 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3N_RESERVED1_MASK 0x0000e000 9775 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3N_RESERVED1_ALIGN 0 9776 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3N_RESERVED1_BITS 3 9777 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3N_RESERVED1_SHIFT 13 9778 9779 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ3N :: ADJ_EN [12:12] */ 9780 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3N_ADJ_EN_MASK 0x00001000 9781 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3N_ADJ_EN_ALIGN 0 9782 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3N_ADJ_EN_BITS 1 9783 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3N_ADJ_EN_SHIFT 12 9784 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3N_ADJ_EN_DEFAULT 0x00000000 9785 9786 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ3N :: reserved2 [11:08] */ 9787 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3N_RESERVED2_MASK 0x00000f00 9788 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3N_RESERVED2_ALIGN 0 9789 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3N_RESERVED2_BITS 4 9790 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3N_RESERVED2_SHIFT 8 9791 9792 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ3N :: VDL_STEP [07:00] */ 9793 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3N_VDL_STEP_MASK 0x000000ff 9794 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3N_VDL_STEP_ALIGN 0 9795 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3N_VDL_STEP_BITS 8 9796 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3N_VDL_STEP_SHIFT 0 9797 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3N_VDL_STEP_DEFAULT 0x00000000 9798 9799 /*************************************************************************** 9800 *VDL_CONTROL_RD_DQ4P - Read channel DQ4-P VDL control register 9801 */ 9802 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ4P :: BUSY [31:31] */ 9803 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4P_BUSY_MASK 0x80000000 9804 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4P_BUSY_ALIGN 0 9805 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4P_BUSY_BITS 1 9806 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4P_BUSY_SHIFT 31 9807 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4P_BUSY_DEFAULT 0x00000000 9808 9809 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ4P :: reserved0 [30:17] */ 9810 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4P_RESERVED0_MASK 0x7ffe0000 9811 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4P_RESERVED0_ALIGN 0 9812 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4P_RESERVED0_BITS 14 9813 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4P_RESERVED0_SHIFT 17 9814 9815 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ4P :: FORCE [16:16] */ 9816 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4P_FORCE_MASK 0x00010000 9817 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4P_FORCE_ALIGN 0 9818 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4P_FORCE_BITS 1 9819 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4P_FORCE_SHIFT 16 9820 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4P_FORCE_DEFAULT 0x00000000 9821 9822 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ4P :: reserved1 [15:13] */ 9823 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4P_RESERVED1_MASK 0x0000e000 9824 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4P_RESERVED1_ALIGN 0 9825 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4P_RESERVED1_BITS 3 9826 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4P_RESERVED1_SHIFT 13 9827 9828 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ4P :: ADJ_EN [12:12] */ 9829 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4P_ADJ_EN_MASK 0x00001000 9830 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4P_ADJ_EN_ALIGN 0 9831 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4P_ADJ_EN_BITS 1 9832 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4P_ADJ_EN_SHIFT 12 9833 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4P_ADJ_EN_DEFAULT 0x00000000 9834 9835 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ4P :: reserved2 [11:08] */ 9836 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4P_RESERVED2_MASK 0x00000f00 9837 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4P_RESERVED2_ALIGN 0 9838 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4P_RESERVED2_BITS 4 9839 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4P_RESERVED2_SHIFT 8 9840 9841 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ4P :: VDL_STEP [07:00] */ 9842 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4P_VDL_STEP_MASK 0x000000ff 9843 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4P_VDL_STEP_ALIGN 0 9844 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4P_VDL_STEP_BITS 8 9845 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4P_VDL_STEP_SHIFT 0 9846 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4P_VDL_STEP_DEFAULT 0x00000000 9847 9848 /*************************************************************************** 9849 *VDL_CONTROL_RD_DQ4N - Read channel DQ4-N VDL control register 9850 */ 9851 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ4N :: BUSY [31:31] */ 9852 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4N_BUSY_MASK 0x80000000 9853 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4N_BUSY_ALIGN 0 9854 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4N_BUSY_BITS 1 9855 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4N_BUSY_SHIFT 31 9856 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4N_BUSY_DEFAULT 0x00000000 9857 9858 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ4N :: reserved0 [30:17] */ 9859 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4N_RESERVED0_MASK 0x7ffe0000 9860 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4N_RESERVED0_ALIGN 0 9861 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4N_RESERVED0_BITS 14 9862 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4N_RESERVED0_SHIFT 17 9863 9864 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ4N :: FORCE [16:16] */ 9865 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4N_FORCE_MASK 0x00010000 9866 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4N_FORCE_ALIGN 0 9867 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4N_FORCE_BITS 1 9868 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4N_FORCE_SHIFT 16 9869 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4N_FORCE_DEFAULT 0x00000000 9870 9871 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ4N :: reserved1 [15:13] */ 9872 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4N_RESERVED1_MASK 0x0000e000 9873 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4N_RESERVED1_ALIGN 0 9874 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4N_RESERVED1_BITS 3 9875 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4N_RESERVED1_SHIFT 13 9876 9877 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ4N :: ADJ_EN [12:12] */ 9878 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4N_ADJ_EN_MASK 0x00001000 9879 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4N_ADJ_EN_ALIGN 0 9880 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4N_ADJ_EN_BITS 1 9881 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4N_ADJ_EN_SHIFT 12 9882 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4N_ADJ_EN_DEFAULT 0x00000000 9883 9884 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ4N :: reserved2 [11:08] */ 9885 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4N_RESERVED2_MASK 0x00000f00 9886 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4N_RESERVED2_ALIGN 0 9887 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4N_RESERVED2_BITS 4 9888 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4N_RESERVED2_SHIFT 8 9889 9890 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ4N :: VDL_STEP [07:00] */ 9891 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4N_VDL_STEP_MASK 0x000000ff 9892 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4N_VDL_STEP_ALIGN 0 9893 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4N_VDL_STEP_BITS 8 9894 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4N_VDL_STEP_SHIFT 0 9895 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4N_VDL_STEP_DEFAULT 0x00000000 9896 9897 /*************************************************************************** 9898 *VDL_CONTROL_RD_DQ5P - Read channel DQ5-P VDL control register 9899 */ 9900 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ5P :: BUSY [31:31] */ 9901 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5P_BUSY_MASK 0x80000000 9902 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5P_BUSY_ALIGN 0 9903 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5P_BUSY_BITS 1 9904 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5P_BUSY_SHIFT 31 9905 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5P_BUSY_DEFAULT 0x00000000 9906 9907 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ5P :: reserved0 [30:17] */ 9908 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5P_RESERVED0_MASK 0x7ffe0000 9909 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5P_RESERVED0_ALIGN 0 9910 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5P_RESERVED0_BITS 14 9911 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5P_RESERVED0_SHIFT 17 9912 9913 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ5P :: FORCE [16:16] */ 9914 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5P_FORCE_MASK 0x00010000 9915 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5P_FORCE_ALIGN 0 9916 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5P_FORCE_BITS 1 9917 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5P_FORCE_SHIFT 16 9918 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5P_FORCE_DEFAULT 0x00000000 9919 9920 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ5P :: reserved1 [15:13] */ 9921 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5P_RESERVED1_MASK 0x0000e000 9922 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5P_RESERVED1_ALIGN 0 9923 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5P_RESERVED1_BITS 3 9924 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5P_RESERVED1_SHIFT 13 9925 9926 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ5P :: ADJ_EN [12:12] */ 9927 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5P_ADJ_EN_MASK 0x00001000 9928 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5P_ADJ_EN_ALIGN 0 9929 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5P_ADJ_EN_BITS 1 9930 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5P_ADJ_EN_SHIFT 12 9931 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5P_ADJ_EN_DEFAULT 0x00000000 9932 9933 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ5P :: reserved2 [11:08] */ 9934 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5P_RESERVED2_MASK 0x00000f00 9935 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5P_RESERVED2_ALIGN 0 9936 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5P_RESERVED2_BITS 4 9937 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5P_RESERVED2_SHIFT 8 9938 9939 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ5P :: VDL_STEP [07:00] */ 9940 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5P_VDL_STEP_MASK 0x000000ff 9941 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5P_VDL_STEP_ALIGN 0 9942 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5P_VDL_STEP_BITS 8 9943 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5P_VDL_STEP_SHIFT 0 9944 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5P_VDL_STEP_DEFAULT 0x00000000 9945 9946 /*************************************************************************** 9947 *VDL_CONTROL_RD_DQ5N - Read channel DQ5-N VDL control register 9948 */ 9949 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ5N :: BUSY [31:31] */ 9950 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5N_BUSY_MASK 0x80000000 9951 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5N_BUSY_ALIGN 0 9952 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5N_BUSY_BITS 1 9953 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5N_BUSY_SHIFT 31 9954 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5N_BUSY_DEFAULT 0x00000000 9955 9956 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ5N :: reserved0 [30:17] */ 9957 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5N_RESERVED0_MASK 0x7ffe0000 9958 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5N_RESERVED0_ALIGN 0 9959 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5N_RESERVED0_BITS 14 9960 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5N_RESERVED0_SHIFT 17 9961 9962 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ5N :: FORCE [16:16] */ 9963 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5N_FORCE_MASK 0x00010000 9964 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5N_FORCE_ALIGN 0 9965 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5N_FORCE_BITS 1 9966 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5N_FORCE_SHIFT 16 9967 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5N_FORCE_DEFAULT 0x00000000 9968 9969 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ5N :: reserved1 [15:13] */ 9970 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5N_RESERVED1_MASK 0x0000e000 9971 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5N_RESERVED1_ALIGN 0 9972 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5N_RESERVED1_BITS 3 9973 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5N_RESERVED1_SHIFT 13 9974 9975 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ5N :: ADJ_EN [12:12] */ 9976 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5N_ADJ_EN_MASK 0x00001000 9977 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5N_ADJ_EN_ALIGN 0 9978 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5N_ADJ_EN_BITS 1 9979 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5N_ADJ_EN_SHIFT 12 9980 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5N_ADJ_EN_DEFAULT 0x00000000 9981 9982 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ5N :: reserved2 [11:08] */ 9983 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5N_RESERVED2_MASK 0x00000f00 9984 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5N_RESERVED2_ALIGN 0 9985 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5N_RESERVED2_BITS 4 9986 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5N_RESERVED2_SHIFT 8 9987 9988 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ5N :: VDL_STEP [07:00] */ 9989 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5N_VDL_STEP_MASK 0x000000ff 9990 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5N_VDL_STEP_ALIGN 0 9991 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5N_VDL_STEP_BITS 8 9992 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5N_VDL_STEP_SHIFT 0 9993 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5N_VDL_STEP_DEFAULT 0x00000000 9994 9995 /*************************************************************************** 9996 *VDL_CONTROL_RD_DQ6P - Read channel DQ6-P VDL control register 9997 */ 9998 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ6P :: BUSY [31:31] */ 9999 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6P_BUSY_MASK 0x80000000 10000 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6P_BUSY_ALIGN 0 10001 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6P_BUSY_BITS 1 10002 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6P_BUSY_SHIFT 31 10003 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6P_BUSY_DEFAULT 0x00000000 10004 10005 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ6P :: reserved0 [30:17] */ 10006 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6P_RESERVED0_MASK 0x7ffe0000 10007 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6P_RESERVED0_ALIGN 0 10008 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6P_RESERVED0_BITS 14 10009 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6P_RESERVED0_SHIFT 17 10010 10011 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ6P :: FORCE [16:16] */ 10012 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6P_FORCE_MASK 0x00010000 10013 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6P_FORCE_ALIGN 0 10014 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6P_FORCE_BITS 1 10015 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6P_FORCE_SHIFT 16 10016 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6P_FORCE_DEFAULT 0x00000000 10017 10018 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ6P :: reserved1 [15:13] */ 10019 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6P_RESERVED1_MASK 0x0000e000 10020 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6P_RESERVED1_ALIGN 0 10021 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6P_RESERVED1_BITS 3 10022 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6P_RESERVED1_SHIFT 13 10023 10024 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ6P :: ADJ_EN [12:12] */ 10025 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6P_ADJ_EN_MASK 0x00001000 10026 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6P_ADJ_EN_ALIGN 0 10027 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6P_ADJ_EN_BITS 1 10028 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6P_ADJ_EN_SHIFT 12 10029 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6P_ADJ_EN_DEFAULT 0x00000000 10030 10031 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ6P :: reserved2 [11:08] */ 10032 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6P_RESERVED2_MASK 0x00000f00 10033 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6P_RESERVED2_ALIGN 0 10034 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6P_RESERVED2_BITS 4 10035 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6P_RESERVED2_SHIFT 8 10036 10037 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ6P :: VDL_STEP [07:00] */ 10038 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6P_VDL_STEP_MASK 0x000000ff 10039 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6P_VDL_STEP_ALIGN 0 10040 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6P_VDL_STEP_BITS 8 10041 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6P_VDL_STEP_SHIFT 0 10042 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6P_VDL_STEP_DEFAULT 0x00000000 10043 10044 /*************************************************************************** 10045 *VDL_CONTROL_RD_DQ6N - Read channel DQ6-N VDL control register 10046 */ 10047 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ6N :: BUSY [31:31] */ 10048 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6N_BUSY_MASK 0x80000000 10049 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6N_BUSY_ALIGN 0 10050 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6N_BUSY_BITS 1 10051 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6N_BUSY_SHIFT 31 10052 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6N_BUSY_DEFAULT 0x00000000 10053 10054 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ6N :: reserved0 [30:17] */ 10055 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6N_RESERVED0_MASK 0x7ffe0000 10056 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6N_RESERVED0_ALIGN 0 10057 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6N_RESERVED0_BITS 14 10058 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6N_RESERVED0_SHIFT 17 10059 10060 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ6N :: FORCE [16:16] */ 10061 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6N_FORCE_MASK 0x00010000 10062 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6N_FORCE_ALIGN 0 10063 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6N_FORCE_BITS 1 10064 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6N_FORCE_SHIFT 16 10065 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6N_FORCE_DEFAULT 0x00000000 10066 10067 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ6N :: reserved1 [15:13] */ 10068 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6N_RESERVED1_MASK 0x0000e000 10069 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6N_RESERVED1_ALIGN 0 10070 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6N_RESERVED1_BITS 3 10071 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6N_RESERVED1_SHIFT 13 10072 10073 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ6N :: ADJ_EN [12:12] */ 10074 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6N_ADJ_EN_MASK 0x00001000 10075 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6N_ADJ_EN_ALIGN 0 10076 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6N_ADJ_EN_BITS 1 10077 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6N_ADJ_EN_SHIFT 12 10078 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6N_ADJ_EN_DEFAULT 0x00000000 10079 10080 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ6N :: reserved2 [11:08] */ 10081 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6N_RESERVED2_MASK 0x00000f00 10082 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6N_RESERVED2_ALIGN 0 10083 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6N_RESERVED2_BITS 4 10084 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6N_RESERVED2_SHIFT 8 10085 10086 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ6N :: VDL_STEP [07:00] */ 10087 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6N_VDL_STEP_MASK 0x000000ff 10088 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6N_VDL_STEP_ALIGN 0 10089 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6N_VDL_STEP_BITS 8 10090 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6N_VDL_STEP_SHIFT 0 10091 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6N_VDL_STEP_DEFAULT 0x00000000 10092 10093 /*************************************************************************** 10094 *VDL_CONTROL_RD_DQ7P - Read channel DQ7-P VDL control register 10095 */ 10096 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ7P :: BUSY [31:31] */ 10097 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7P_BUSY_MASK 0x80000000 10098 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7P_BUSY_ALIGN 0 10099 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7P_BUSY_BITS 1 10100 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7P_BUSY_SHIFT 31 10101 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7P_BUSY_DEFAULT 0x00000000 10102 10103 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ7P :: reserved0 [30:17] */ 10104 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7P_RESERVED0_MASK 0x7ffe0000 10105 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7P_RESERVED0_ALIGN 0 10106 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7P_RESERVED0_BITS 14 10107 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7P_RESERVED0_SHIFT 17 10108 10109 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ7P :: FORCE [16:16] */ 10110 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7P_FORCE_MASK 0x00010000 10111 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7P_FORCE_ALIGN 0 10112 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7P_FORCE_BITS 1 10113 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7P_FORCE_SHIFT 16 10114 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7P_FORCE_DEFAULT 0x00000000 10115 10116 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ7P :: reserved1 [15:13] */ 10117 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7P_RESERVED1_MASK 0x0000e000 10118 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7P_RESERVED1_ALIGN 0 10119 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7P_RESERVED1_BITS 3 10120 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7P_RESERVED1_SHIFT 13 10121 10122 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ7P :: ADJ_EN [12:12] */ 10123 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7P_ADJ_EN_MASK 0x00001000 10124 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7P_ADJ_EN_ALIGN 0 10125 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7P_ADJ_EN_BITS 1 10126 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7P_ADJ_EN_SHIFT 12 10127 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7P_ADJ_EN_DEFAULT 0x00000000 10128 10129 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ7P :: reserved2 [11:08] */ 10130 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7P_RESERVED2_MASK 0x00000f00 10131 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7P_RESERVED2_ALIGN 0 10132 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7P_RESERVED2_BITS 4 10133 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7P_RESERVED2_SHIFT 8 10134 10135 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ7P :: VDL_STEP [07:00] */ 10136 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7P_VDL_STEP_MASK 0x000000ff 10137 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7P_VDL_STEP_ALIGN 0 10138 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7P_VDL_STEP_BITS 8 10139 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7P_VDL_STEP_SHIFT 0 10140 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7P_VDL_STEP_DEFAULT 0x00000000 10141 10142 /*************************************************************************** 10143 *VDL_CONTROL_RD_DQ7N - Read channel DQ7-N VDL control register 10144 */ 10145 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ7N :: BUSY [31:31] */ 10146 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7N_BUSY_MASK 0x80000000 10147 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7N_BUSY_ALIGN 0 10148 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7N_BUSY_BITS 1 10149 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7N_BUSY_SHIFT 31 10150 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7N_BUSY_DEFAULT 0x00000000 10151 10152 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ7N :: reserved0 [30:17] */ 10153 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7N_RESERVED0_MASK 0x7ffe0000 10154 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7N_RESERVED0_ALIGN 0 10155 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7N_RESERVED0_BITS 14 10156 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7N_RESERVED0_SHIFT 17 10157 10158 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ7N :: FORCE [16:16] */ 10159 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7N_FORCE_MASK 0x00010000 10160 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7N_FORCE_ALIGN 0 10161 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7N_FORCE_BITS 1 10162 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7N_FORCE_SHIFT 16 10163 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7N_FORCE_DEFAULT 0x00000000 10164 10165 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ7N :: reserved1 [15:13] */ 10166 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7N_RESERVED1_MASK 0x0000e000 10167 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7N_RESERVED1_ALIGN 0 10168 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7N_RESERVED1_BITS 3 10169 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7N_RESERVED1_SHIFT 13 10170 10171 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ7N :: ADJ_EN [12:12] */ 10172 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7N_ADJ_EN_MASK 0x00001000 10173 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7N_ADJ_EN_ALIGN 0 10174 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7N_ADJ_EN_BITS 1 10175 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7N_ADJ_EN_SHIFT 12 10176 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7N_ADJ_EN_DEFAULT 0x00000000 10177 10178 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ7N :: reserved2 [11:08] */ 10179 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7N_RESERVED2_MASK 0x00000f00 10180 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7N_RESERVED2_ALIGN 0 10181 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7N_RESERVED2_BITS 4 10182 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7N_RESERVED2_SHIFT 8 10183 10184 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ7N :: VDL_STEP [07:00] */ 10185 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7N_VDL_STEP_MASK 0x000000ff 10186 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7N_VDL_STEP_ALIGN 0 10187 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7N_VDL_STEP_BITS 8 10188 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7N_VDL_STEP_SHIFT 0 10189 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7N_VDL_STEP_DEFAULT 0x00000000 10190 10191 /*************************************************************************** 10192 *VDL_CONTROL_RD_DMP - Read channel DM-P VDL control register 10193 */ 10194 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DMP :: BUSY [31:31] */ 10195 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMP_BUSY_MASK 0x80000000 10196 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMP_BUSY_ALIGN 0 10197 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMP_BUSY_BITS 1 10198 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMP_BUSY_SHIFT 31 10199 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMP_BUSY_DEFAULT 0x00000000 10200 10201 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DMP :: reserved0 [30:17] */ 10202 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMP_RESERVED0_MASK 0x7ffe0000 10203 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMP_RESERVED0_ALIGN 0 10204 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMP_RESERVED0_BITS 14 10205 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMP_RESERVED0_SHIFT 17 10206 10207 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DMP :: FORCE [16:16] */ 10208 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMP_FORCE_MASK 0x00010000 10209 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMP_FORCE_ALIGN 0 10210 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMP_FORCE_BITS 1 10211 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMP_FORCE_SHIFT 16 10212 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMP_FORCE_DEFAULT 0x00000000 10213 10214 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DMP :: reserved1 [15:13] */ 10215 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMP_RESERVED1_MASK 0x0000e000 10216 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMP_RESERVED1_ALIGN 0 10217 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMP_RESERVED1_BITS 3 10218 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMP_RESERVED1_SHIFT 13 10219 10220 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DMP :: ADJ_EN [12:12] */ 10221 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMP_ADJ_EN_MASK 0x00001000 10222 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMP_ADJ_EN_ALIGN 0 10223 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMP_ADJ_EN_BITS 1 10224 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMP_ADJ_EN_SHIFT 12 10225 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMP_ADJ_EN_DEFAULT 0x00000000 10226 10227 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DMP :: reserved2 [11:08] */ 10228 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMP_RESERVED2_MASK 0x00000f00 10229 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMP_RESERVED2_ALIGN 0 10230 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMP_RESERVED2_BITS 4 10231 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMP_RESERVED2_SHIFT 8 10232 10233 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DMP :: VDL_STEP [07:00] */ 10234 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMP_VDL_STEP_MASK 0x000000ff 10235 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMP_VDL_STEP_ALIGN 0 10236 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMP_VDL_STEP_BITS 8 10237 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMP_VDL_STEP_SHIFT 0 10238 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMP_VDL_STEP_DEFAULT 0x00000000 10239 10240 /*************************************************************************** 10241 *VDL_CONTROL_RD_DMN - Read channel DM-N VDL control register 10242 */ 10243 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DMN :: BUSY [31:31] */ 10244 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMN_BUSY_MASK 0x80000000 10245 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMN_BUSY_ALIGN 0 10246 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMN_BUSY_BITS 1 10247 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMN_BUSY_SHIFT 31 10248 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMN_BUSY_DEFAULT 0x00000000 10249 10250 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DMN :: reserved0 [30:17] */ 10251 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMN_RESERVED0_MASK 0x7ffe0000 10252 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMN_RESERVED0_ALIGN 0 10253 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMN_RESERVED0_BITS 14 10254 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMN_RESERVED0_SHIFT 17 10255 10256 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DMN :: FORCE [16:16] */ 10257 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMN_FORCE_MASK 0x00010000 10258 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMN_FORCE_ALIGN 0 10259 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMN_FORCE_BITS 1 10260 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMN_FORCE_SHIFT 16 10261 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMN_FORCE_DEFAULT 0x00000000 10262 10263 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DMN :: reserved1 [15:13] */ 10264 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMN_RESERVED1_MASK 0x0000e000 10265 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMN_RESERVED1_ALIGN 0 10266 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMN_RESERVED1_BITS 3 10267 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMN_RESERVED1_SHIFT 13 10268 10269 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DMN :: ADJ_EN [12:12] */ 10270 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMN_ADJ_EN_MASK 0x00001000 10271 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMN_ADJ_EN_ALIGN 0 10272 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMN_ADJ_EN_BITS 1 10273 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMN_ADJ_EN_SHIFT 12 10274 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMN_ADJ_EN_DEFAULT 0x00000000 10275 10276 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DMN :: reserved2 [11:08] */ 10277 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMN_RESERVED2_MASK 0x00000f00 10278 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMN_RESERVED2_ALIGN 0 10279 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMN_RESERVED2_BITS 4 10280 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMN_RESERVED2_SHIFT 8 10281 10282 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DMN :: VDL_STEP [07:00] */ 10283 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMN_VDL_STEP_MASK 0x000000ff 10284 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMN_VDL_STEP_ALIGN 0 10285 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMN_VDL_STEP_BITS 8 10286 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMN_VDL_STEP_SHIFT 0 10287 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMN_VDL_STEP_DEFAULT 0x00000000 10288 10289 /*************************************************************************** 10290 *VDL_CONTROL_RD_EDCP - Read channel EDC-P VDL control register 10291 */ 10292 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_EDCP :: BUSY [31:31] */ 10293 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCP_BUSY_MASK 0x80000000 10294 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCP_BUSY_ALIGN 0 10295 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCP_BUSY_BITS 1 10296 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCP_BUSY_SHIFT 31 10297 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCP_BUSY_DEFAULT 0x00000000 10298 10299 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_EDCP :: reserved0 [30:17] */ 10300 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCP_RESERVED0_MASK 0x7ffe0000 10301 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCP_RESERVED0_ALIGN 0 10302 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCP_RESERVED0_BITS 14 10303 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCP_RESERVED0_SHIFT 17 10304 10305 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_EDCP :: FORCE [16:16] */ 10306 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCP_FORCE_MASK 0x00010000 10307 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCP_FORCE_ALIGN 0 10308 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCP_FORCE_BITS 1 10309 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCP_FORCE_SHIFT 16 10310 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCP_FORCE_DEFAULT 0x00000000 10311 10312 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_EDCP :: reserved1 [15:13] */ 10313 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCP_RESERVED1_MASK 0x0000e000 10314 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCP_RESERVED1_ALIGN 0 10315 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCP_RESERVED1_BITS 3 10316 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCP_RESERVED1_SHIFT 13 10317 10318 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_EDCP :: ADJ_EN [12:12] */ 10319 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCP_ADJ_EN_MASK 0x00001000 10320 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCP_ADJ_EN_ALIGN 0 10321 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCP_ADJ_EN_BITS 1 10322 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCP_ADJ_EN_SHIFT 12 10323 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCP_ADJ_EN_DEFAULT 0x00000000 10324 10325 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_EDCP :: reserved2 [11:08] */ 10326 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCP_RESERVED2_MASK 0x00000f00 10327 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCP_RESERVED2_ALIGN 0 10328 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCP_RESERVED2_BITS 4 10329 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCP_RESERVED2_SHIFT 8 10330 10331 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_EDCP :: VDL_STEP [07:00] */ 10332 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCP_VDL_STEP_MASK 0x000000ff 10333 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCP_VDL_STEP_ALIGN 0 10334 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCP_VDL_STEP_BITS 8 10335 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCP_VDL_STEP_SHIFT 0 10336 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCP_VDL_STEP_DEFAULT 0x00000000 10337 10338 /*************************************************************************** 10339 *VDL_CONTROL_RD_EDCN - Read channel EDC-N VDL control register 10340 */ 10341 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_EDCN :: BUSY [31:31] */ 10342 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCN_BUSY_MASK 0x80000000 10343 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCN_BUSY_ALIGN 0 10344 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCN_BUSY_BITS 1 10345 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCN_BUSY_SHIFT 31 10346 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCN_BUSY_DEFAULT 0x00000000 10347 10348 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_EDCN :: reserved0 [30:17] */ 10349 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCN_RESERVED0_MASK 0x7ffe0000 10350 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCN_RESERVED0_ALIGN 0 10351 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCN_RESERVED0_BITS 14 10352 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCN_RESERVED0_SHIFT 17 10353 10354 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_EDCN :: FORCE [16:16] */ 10355 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCN_FORCE_MASK 0x00010000 10356 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCN_FORCE_ALIGN 0 10357 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCN_FORCE_BITS 1 10358 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCN_FORCE_SHIFT 16 10359 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCN_FORCE_DEFAULT 0x00000000 10360 10361 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_EDCN :: reserved1 [15:13] */ 10362 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCN_RESERVED1_MASK 0x0000e000 10363 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCN_RESERVED1_ALIGN 0 10364 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCN_RESERVED1_BITS 3 10365 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCN_RESERVED1_SHIFT 13 10366 10367 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_EDCN :: ADJ_EN [12:12] */ 10368 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCN_ADJ_EN_MASK 0x00001000 10369 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCN_ADJ_EN_ALIGN 0 10370 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCN_ADJ_EN_BITS 1 10371 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCN_ADJ_EN_SHIFT 12 10372 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCN_ADJ_EN_DEFAULT 0x00000000 10373 10374 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_EDCN :: reserved2 [11:08] */ 10375 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCN_RESERVED2_MASK 0x00000f00 10376 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCN_RESERVED2_ALIGN 0 10377 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCN_RESERVED2_BITS 4 10378 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCN_RESERVED2_SHIFT 8 10379 10380 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_EDCN :: VDL_STEP [07:00] */ 10381 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCN_VDL_STEP_MASK 0x000000ff 10382 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCN_VDL_STEP_ALIGN 0 10383 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCN_VDL_STEP_BITS 8 10384 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCN_VDL_STEP_SHIFT 0 10385 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCN_VDL_STEP_DEFAULT 0x00000000 10386 10387 /*************************************************************************** 10388 *VDL_CONTROL_RD_EN_CS0 - Read channel CS_N[0] read enable VDL control register 10389 */ 10390 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_EN_CS0 :: BUSY [31:31] */ 10391 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0_BUSY_MASK 0x80000000 10392 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0_BUSY_ALIGN 0 10393 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0_BUSY_BITS 1 10394 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0_BUSY_SHIFT 31 10395 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0_BUSY_DEFAULT 0x00000000 10396 10397 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_EN_CS0 :: reserved0 [30:17] */ 10398 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0_RESERVED0_MASK 0x7ffe0000 10399 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0_RESERVED0_ALIGN 0 10400 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0_RESERVED0_BITS 14 10401 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0_RESERVED0_SHIFT 17 10402 10403 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_EN_CS0 :: FORCE [16:16] */ 10404 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0_FORCE_MASK 0x00010000 10405 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0_FORCE_ALIGN 0 10406 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0_FORCE_BITS 1 10407 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0_FORCE_SHIFT 16 10408 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0_FORCE_DEFAULT 0x00000000 10409 10410 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_EN_CS0 :: reserved1 [15:13] */ 10411 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0_RESERVED1_MASK 0x0000e000 10412 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0_RESERVED1_ALIGN 0 10413 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0_RESERVED1_BITS 3 10414 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0_RESERVED1_SHIFT 13 10415 10416 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_EN_CS0 :: ADJ_EN [12:12] */ 10417 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0_ADJ_EN_MASK 0x00001000 10418 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0_ADJ_EN_ALIGN 0 10419 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0_ADJ_EN_BITS 1 10420 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0_ADJ_EN_SHIFT 12 10421 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0_ADJ_EN_DEFAULT 0x00000000 10422 10423 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_EN_CS0 :: reserved2 [11:08] */ 10424 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0_RESERVED2_MASK 0x00000f00 10425 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0_RESERVED2_ALIGN 0 10426 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0_RESERVED2_BITS 4 10427 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0_RESERVED2_SHIFT 8 10428 10429 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_EN_CS0 :: VDL_STEP [07:00] */ 10430 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0_VDL_STEP_MASK 0x000000ff 10431 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0_VDL_STEP_ALIGN 0 10432 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0_VDL_STEP_BITS 8 10433 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0_VDL_STEP_SHIFT 0 10434 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0_VDL_STEP_DEFAULT 0x00000000 10435 10436 /*************************************************************************** 10437 *VDL_CONTROL_RD_EN_CS1 - Read channel CS_N[1] read enable VDL control register 10438 */ 10439 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_EN_CS1 :: BUSY [31:31] */ 10440 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1_BUSY_MASK 0x80000000 10441 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1_BUSY_ALIGN 0 10442 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1_BUSY_BITS 1 10443 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1_BUSY_SHIFT 31 10444 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1_BUSY_DEFAULT 0x00000000 10445 10446 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_EN_CS1 :: reserved0 [30:17] */ 10447 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1_RESERVED0_MASK 0x7ffe0000 10448 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1_RESERVED0_ALIGN 0 10449 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1_RESERVED0_BITS 14 10450 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1_RESERVED0_SHIFT 17 10451 10452 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_EN_CS1 :: FORCE [16:16] */ 10453 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1_FORCE_MASK 0x00010000 10454 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1_FORCE_ALIGN 0 10455 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1_FORCE_BITS 1 10456 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1_FORCE_SHIFT 16 10457 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1_FORCE_DEFAULT 0x00000000 10458 10459 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_EN_CS1 :: reserved1 [15:13] */ 10460 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1_RESERVED1_MASK 0x0000e000 10461 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1_RESERVED1_ALIGN 0 10462 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1_RESERVED1_BITS 3 10463 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1_RESERVED1_SHIFT 13 10464 10465 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_EN_CS1 :: ADJ_EN [12:12] */ 10466 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1_ADJ_EN_MASK 0x00001000 10467 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1_ADJ_EN_ALIGN 0 10468 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1_ADJ_EN_BITS 1 10469 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1_ADJ_EN_SHIFT 12 10470 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1_ADJ_EN_DEFAULT 0x00000000 10471 10472 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_EN_CS1 :: reserved2 [11:08] */ 10473 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1_RESERVED2_MASK 0x00000f00 10474 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1_RESERVED2_ALIGN 0 10475 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1_RESERVED2_BITS 4 10476 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1_RESERVED2_SHIFT 8 10477 10478 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_EN_CS1 :: VDL_STEP [07:00] */ 10479 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1_VDL_STEP_MASK 0x000000ff 10480 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1_VDL_STEP_ALIGN 0 10481 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1_VDL_STEP_BITS 8 10482 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1_VDL_STEP_SHIFT 0 10483 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1_VDL_STEP_DEFAULT 0x00000000 10484 10485 /*************************************************************************** 10486 *VDL_CLK_CONTROL - DDR interface signal Write Leveling CLK VDL control register 10487 */ 10488 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CLK_CONTROL :: BUSY [31:31] */ 10489 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CLK_CONTROL_BUSY_MASK 0x80000000 10490 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CLK_CONTROL_BUSY_ALIGN 0 10491 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CLK_CONTROL_BUSY_BITS 1 10492 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CLK_CONTROL_BUSY_SHIFT 31 10493 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CLK_CONTROL_BUSY_DEFAULT 0x00000000 10494 10495 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CLK_CONTROL :: reserved0 [30:17] */ 10496 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CLK_CONTROL_RESERVED0_MASK 0x7ffe0000 10497 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CLK_CONTROL_RESERVED0_ALIGN 0 10498 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CLK_CONTROL_RESERVED0_BITS 14 10499 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CLK_CONTROL_RESERVED0_SHIFT 17 10500 10501 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CLK_CONTROL :: FORCE [16:16] */ 10502 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CLK_CONTROL_FORCE_MASK 0x00010000 10503 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CLK_CONTROL_FORCE_ALIGN 0 10504 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CLK_CONTROL_FORCE_BITS 1 10505 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CLK_CONTROL_FORCE_SHIFT 16 10506 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CLK_CONTROL_FORCE_DEFAULT 0x00000000 10507 10508 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CLK_CONTROL :: reserved1 [15:13] */ 10509 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CLK_CONTROL_RESERVED1_MASK 0x0000e000 10510 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CLK_CONTROL_RESERVED1_ALIGN 0 10511 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CLK_CONTROL_RESERVED1_BITS 3 10512 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CLK_CONTROL_RESERVED1_SHIFT 13 10513 10514 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CLK_CONTROL :: ADJ_EN [12:12] */ 10515 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CLK_CONTROL_ADJ_EN_MASK 0x00001000 10516 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CLK_CONTROL_ADJ_EN_ALIGN 0 10517 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CLK_CONTROL_ADJ_EN_BITS 1 10518 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CLK_CONTROL_ADJ_EN_SHIFT 12 10519 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CLK_CONTROL_ADJ_EN_DEFAULT 0x00000000 10520 10521 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CLK_CONTROL :: reserved2 [11:09] */ 10522 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CLK_CONTROL_RESERVED2_MASK 0x00000e00 10523 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CLK_CONTROL_RESERVED2_ALIGN 0 10524 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CLK_CONTROL_RESERVED2_BITS 3 10525 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CLK_CONTROL_RESERVED2_SHIFT 9 10526 10527 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_CLK_CONTROL :: VDL_STEP [08:00] */ 10528 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CLK_CONTROL_VDL_STEP_MASK 0x000001ff 10529 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CLK_CONTROL_VDL_STEP_ALIGN 0 10530 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CLK_CONTROL_VDL_STEP_BITS 9 10531 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CLK_CONTROL_VDL_STEP_SHIFT 0 10532 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_CLK_CONTROL_VDL_STEP_DEFAULT 0x00000000 10533 10534 /*************************************************************************** 10535 *VDL_LDE_CONTROL - DDR interface signal Write Leveling Capture Enable VDL control register 10536 */ 10537 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_LDE_CONTROL :: BUSY [31:31] */ 10538 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_LDE_CONTROL_BUSY_MASK 0x80000000 10539 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_LDE_CONTROL_BUSY_ALIGN 0 10540 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_LDE_CONTROL_BUSY_BITS 1 10541 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_LDE_CONTROL_BUSY_SHIFT 31 10542 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_LDE_CONTROL_BUSY_DEFAULT 0x00000000 10543 10544 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_LDE_CONTROL :: reserved0 [30:17] */ 10545 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_LDE_CONTROL_RESERVED0_MASK 0x7ffe0000 10546 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_LDE_CONTROL_RESERVED0_ALIGN 0 10547 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_LDE_CONTROL_RESERVED0_BITS 14 10548 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_LDE_CONTROL_RESERVED0_SHIFT 17 10549 10550 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_LDE_CONTROL :: FORCE [16:16] */ 10551 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_LDE_CONTROL_FORCE_MASK 0x00010000 10552 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_LDE_CONTROL_FORCE_ALIGN 0 10553 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_LDE_CONTROL_FORCE_BITS 1 10554 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_LDE_CONTROL_FORCE_SHIFT 16 10555 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_LDE_CONTROL_FORCE_DEFAULT 0x00000000 10556 10557 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_LDE_CONTROL :: reserved1 [15:13] */ 10558 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_LDE_CONTROL_RESERVED1_MASK 0x0000e000 10559 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_LDE_CONTROL_RESERVED1_ALIGN 0 10560 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_LDE_CONTROL_RESERVED1_BITS 3 10561 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_LDE_CONTROL_RESERVED1_SHIFT 13 10562 10563 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_LDE_CONTROL :: ADJ_EN [12:12] */ 10564 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_LDE_CONTROL_ADJ_EN_MASK 0x00001000 10565 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_LDE_CONTROL_ADJ_EN_ALIGN 0 10566 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_LDE_CONTROL_ADJ_EN_BITS 1 10567 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_LDE_CONTROL_ADJ_EN_SHIFT 12 10568 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_LDE_CONTROL_ADJ_EN_DEFAULT 0x00000000 10569 10570 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_LDE_CONTROL :: reserved2 [11:09] */ 10571 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_LDE_CONTROL_RESERVED2_MASK 0x00000e00 10572 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_LDE_CONTROL_RESERVED2_ALIGN 0 10573 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_LDE_CONTROL_RESERVED2_BITS 3 10574 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_LDE_CONTROL_RESERVED2_SHIFT 9 10575 10576 /* DDR34_E0_PHY_BYTE_LANE_1 :: VDL_LDE_CONTROL :: VDL_STEP [08:00] */ 10577 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_LDE_CONTROL_VDL_STEP_MASK 0x000001ff 10578 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_LDE_CONTROL_VDL_STEP_ALIGN 0 10579 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_LDE_CONTROL_VDL_STEP_BITS 9 10580 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_LDE_CONTROL_VDL_STEP_SHIFT 0 10581 #define DDR34_E0_PHY_BYTE_LANE_1_VDL_LDE_CONTROL_VDL_STEP_DEFAULT 0x00000000 10582 10583 /*************************************************************************** 10584 *RD_EN_DLY_CYC - Read enable bit-clock cycle delay control register 10585 */ 10586 /* DDR34_E0_PHY_BYTE_LANE_1 :: RD_EN_DLY_CYC :: BUSY [31:31] */ 10587 #define DDR34_E0_PHY_BYTE_LANE_1_RD_EN_DLY_CYC_BUSY_MASK 0x80000000 10588 #define DDR34_E0_PHY_BYTE_LANE_1_RD_EN_DLY_CYC_BUSY_ALIGN 0 10589 #define DDR34_E0_PHY_BYTE_LANE_1_RD_EN_DLY_CYC_BUSY_BITS 1 10590 #define DDR34_E0_PHY_BYTE_LANE_1_RD_EN_DLY_CYC_BUSY_SHIFT 31 10591 #define DDR34_E0_PHY_BYTE_LANE_1_RD_EN_DLY_CYC_BUSY_DEFAULT 0x00000000 10592 10593 /* DDR34_E0_PHY_BYTE_LANE_1 :: RD_EN_DLY_CYC :: reserved0 [30:17] */ 10594 #define DDR34_E0_PHY_BYTE_LANE_1_RD_EN_DLY_CYC_RESERVED0_MASK 0x7ffe0000 10595 #define DDR34_E0_PHY_BYTE_LANE_1_RD_EN_DLY_CYC_RESERVED0_ALIGN 0 10596 #define DDR34_E0_PHY_BYTE_LANE_1_RD_EN_DLY_CYC_RESERVED0_BITS 14 10597 #define DDR34_E0_PHY_BYTE_LANE_1_RD_EN_DLY_CYC_RESERVED0_SHIFT 17 10598 10599 /* DDR34_E0_PHY_BYTE_LANE_1 :: RD_EN_DLY_CYC :: FORCE [16:16] */ 10600 #define DDR34_E0_PHY_BYTE_LANE_1_RD_EN_DLY_CYC_FORCE_MASK 0x00010000 10601 #define DDR34_E0_PHY_BYTE_LANE_1_RD_EN_DLY_CYC_FORCE_ALIGN 0 10602 #define DDR34_E0_PHY_BYTE_LANE_1_RD_EN_DLY_CYC_FORCE_BITS 1 10603 #define DDR34_E0_PHY_BYTE_LANE_1_RD_EN_DLY_CYC_FORCE_SHIFT 16 10604 #define DDR34_E0_PHY_BYTE_LANE_1_RD_EN_DLY_CYC_FORCE_DEFAULT 0x00000000 10605 10606 /* DDR34_E0_PHY_BYTE_LANE_1 :: RD_EN_DLY_CYC :: reserved1 [15:08] */ 10607 #define DDR34_E0_PHY_BYTE_LANE_1_RD_EN_DLY_CYC_RESERVED1_MASK 0x0000ff00 10608 #define DDR34_E0_PHY_BYTE_LANE_1_RD_EN_DLY_CYC_RESERVED1_ALIGN 0 10609 #define DDR34_E0_PHY_BYTE_LANE_1_RD_EN_DLY_CYC_RESERVED1_BITS 8 10610 #define DDR34_E0_PHY_BYTE_LANE_1_RD_EN_DLY_CYC_RESERVED1_SHIFT 8 10611 10612 /* DDR34_E0_PHY_BYTE_LANE_1 :: RD_EN_DLY_CYC :: CS1_CYCLES [07:04] */ 10613 #define DDR34_E0_PHY_BYTE_LANE_1_RD_EN_DLY_CYC_CS1_CYCLES_MASK 0x000000f0 10614 #define DDR34_E0_PHY_BYTE_LANE_1_RD_EN_DLY_CYC_CS1_CYCLES_ALIGN 0 10615 #define DDR34_E0_PHY_BYTE_LANE_1_RD_EN_DLY_CYC_CS1_CYCLES_BITS 4 10616 #define DDR34_E0_PHY_BYTE_LANE_1_RD_EN_DLY_CYC_CS1_CYCLES_SHIFT 4 10617 #define DDR34_E0_PHY_BYTE_LANE_1_RD_EN_DLY_CYC_CS1_CYCLES_DEFAULT 0x00000000 10618 10619 /* DDR34_E0_PHY_BYTE_LANE_1 :: RD_EN_DLY_CYC :: CS0_CYCLES [03:00] */ 10620 #define DDR34_E0_PHY_BYTE_LANE_1_RD_EN_DLY_CYC_CS0_CYCLES_MASK 0x0000000f 10621 #define DDR34_E0_PHY_BYTE_LANE_1_RD_EN_DLY_CYC_CS0_CYCLES_ALIGN 0 10622 #define DDR34_E0_PHY_BYTE_LANE_1_RD_EN_DLY_CYC_CS0_CYCLES_BITS 4 10623 #define DDR34_E0_PHY_BYTE_LANE_1_RD_EN_DLY_CYC_CS0_CYCLES_SHIFT 0 10624 #define DDR34_E0_PHY_BYTE_LANE_1_RD_EN_DLY_CYC_CS0_CYCLES_DEFAULT 0x00000000 10625 10626 /*************************************************************************** 10627 *WR_CHAN_DLY_CYC - Write leveling bit-clock cycle delay control register 10628 */ 10629 /* DDR34_E0_PHY_BYTE_LANE_1 :: WR_CHAN_DLY_CYC :: BUSY [31:31] */ 10630 #define DDR34_E0_PHY_BYTE_LANE_1_WR_CHAN_DLY_CYC_BUSY_MASK 0x80000000 10631 #define DDR34_E0_PHY_BYTE_LANE_1_WR_CHAN_DLY_CYC_BUSY_ALIGN 0 10632 #define DDR34_E0_PHY_BYTE_LANE_1_WR_CHAN_DLY_CYC_BUSY_BITS 1 10633 #define DDR34_E0_PHY_BYTE_LANE_1_WR_CHAN_DLY_CYC_BUSY_SHIFT 31 10634 #define DDR34_E0_PHY_BYTE_LANE_1_WR_CHAN_DLY_CYC_BUSY_DEFAULT 0x00000000 10635 10636 /* DDR34_E0_PHY_BYTE_LANE_1 :: WR_CHAN_DLY_CYC :: reserved0 [30:17] */ 10637 #define DDR34_E0_PHY_BYTE_LANE_1_WR_CHAN_DLY_CYC_RESERVED0_MASK 0x7ffe0000 10638 #define DDR34_E0_PHY_BYTE_LANE_1_WR_CHAN_DLY_CYC_RESERVED0_ALIGN 0 10639 #define DDR34_E0_PHY_BYTE_LANE_1_WR_CHAN_DLY_CYC_RESERVED0_BITS 14 10640 #define DDR34_E0_PHY_BYTE_LANE_1_WR_CHAN_DLY_CYC_RESERVED0_SHIFT 17 10641 10642 /* DDR34_E0_PHY_BYTE_LANE_1 :: WR_CHAN_DLY_CYC :: FORCE [16:16] */ 10643 #define DDR34_E0_PHY_BYTE_LANE_1_WR_CHAN_DLY_CYC_FORCE_MASK 0x00010000 10644 #define DDR34_E0_PHY_BYTE_LANE_1_WR_CHAN_DLY_CYC_FORCE_ALIGN 0 10645 #define DDR34_E0_PHY_BYTE_LANE_1_WR_CHAN_DLY_CYC_FORCE_BITS 1 10646 #define DDR34_E0_PHY_BYTE_LANE_1_WR_CHAN_DLY_CYC_FORCE_SHIFT 16 10647 #define DDR34_E0_PHY_BYTE_LANE_1_WR_CHAN_DLY_CYC_FORCE_DEFAULT 0x00000000 10648 10649 /* DDR34_E0_PHY_BYTE_LANE_1 :: WR_CHAN_DLY_CYC :: reserved1 [15:03] */ 10650 #define DDR34_E0_PHY_BYTE_LANE_1_WR_CHAN_DLY_CYC_RESERVED1_MASK 0x0000fff8 10651 #define DDR34_E0_PHY_BYTE_LANE_1_WR_CHAN_DLY_CYC_RESERVED1_ALIGN 0 10652 #define DDR34_E0_PHY_BYTE_LANE_1_WR_CHAN_DLY_CYC_RESERVED1_BITS 13 10653 #define DDR34_E0_PHY_BYTE_LANE_1_WR_CHAN_DLY_CYC_RESERVED1_SHIFT 3 10654 10655 /* DDR34_E0_PHY_BYTE_LANE_1 :: WR_CHAN_DLY_CYC :: CYCLES [02:00] */ 10656 #define DDR34_E0_PHY_BYTE_LANE_1_WR_CHAN_DLY_CYC_CYCLES_MASK 0x00000007 10657 #define DDR34_E0_PHY_BYTE_LANE_1_WR_CHAN_DLY_CYC_CYCLES_ALIGN 0 10658 #define DDR34_E0_PHY_BYTE_LANE_1_WR_CHAN_DLY_CYC_CYCLES_BITS 3 10659 #define DDR34_E0_PHY_BYTE_LANE_1_WR_CHAN_DLY_CYC_CYCLES_SHIFT 0 10660 #define DDR34_E0_PHY_BYTE_LANE_1_WR_CHAN_DLY_CYC_CYCLES_DEFAULT 0x00000000 10661 10662 /*************************************************************************** 10663 *READ_CONTROL - Read channel datapath control register 10664 */ 10665 /* DDR34_E0_PHY_BYTE_LANE_1 :: READ_CONTROL :: reserved0 [31:05] */ 10666 #define DDR34_E0_PHY_BYTE_LANE_1_READ_CONTROL_RESERVED0_MASK 0xffffffe0 10667 #define DDR34_E0_PHY_BYTE_LANE_1_READ_CONTROL_RESERVED0_ALIGN 0 10668 #define DDR34_E0_PHY_BYTE_LANE_1_READ_CONTROL_RESERVED0_BITS 27 10669 #define DDR34_E0_PHY_BYTE_LANE_1_READ_CONTROL_RESERVED0_SHIFT 5 10670 10671 /* DDR34_E0_PHY_BYTE_LANE_1 :: READ_CONTROL :: MODE [04:04] */ 10672 #define DDR34_E0_PHY_BYTE_LANE_1_READ_CONTROL_MODE_MASK 0x00000010 10673 #define DDR34_E0_PHY_BYTE_LANE_1_READ_CONTROL_MODE_ALIGN 0 10674 #define DDR34_E0_PHY_BYTE_LANE_1_READ_CONTROL_MODE_BITS 1 10675 #define DDR34_E0_PHY_BYTE_LANE_1_READ_CONTROL_MODE_SHIFT 4 10676 #define DDR34_E0_PHY_BYTE_LANE_1_READ_CONTROL_MODE_DEFAULT 0x00000001 10677 10678 /* DDR34_E0_PHY_BYTE_LANE_1 :: READ_CONTROL :: reserved1 [03:03] */ 10679 #define DDR34_E0_PHY_BYTE_LANE_1_READ_CONTROL_RESERVED1_MASK 0x00000008 10680 #define DDR34_E0_PHY_BYTE_LANE_1_READ_CONTROL_RESERVED1_ALIGN 0 10681 #define DDR34_E0_PHY_BYTE_LANE_1_READ_CONTROL_RESERVED1_BITS 1 10682 #define DDR34_E0_PHY_BYTE_LANE_1_READ_CONTROL_RESERVED1_SHIFT 3 10683 10684 /* DDR34_E0_PHY_BYTE_LANE_1 :: READ_CONTROL :: RD_DATA_DLY [02:00] */ 10685 #define DDR34_E0_PHY_BYTE_LANE_1_READ_CONTROL_RD_DATA_DLY_MASK 0x00000007 10686 #define DDR34_E0_PHY_BYTE_LANE_1_READ_CONTROL_RD_DATA_DLY_ALIGN 0 10687 #define DDR34_E0_PHY_BYTE_LANE_1_READ_CONTROL_RD_DATA_DLY_BITS 3 10688 #define DDR34_E0_PHY_BYTE_LANE_1_READ_CONTROL_RD_DATA_DLY_SHIFT 0 10689 #define DDR34_E0_PHY_BYTE_LANE_1_READ_CONTROL_RD_DATA_DLY_DEFAULT 0x00000007 10690 10691 /*************************************************************************** 10692 *READ_FIFO_ADDR - Read fifo addresss pointer register 10693 */ 10694 /* DDR34_E0_PHY_BYTE_LANE_1 :: READ_FIFO_ADDR :: reserved0 [31:03] */ 10695 #define DDR34_E0_PHY_BYTE_LANE_1_READ_FIFO_ADDR_RESERVED0_MASK 0xfffffff8 10696 #define DDR34_E0_PHY_BYTE_LANE_1_READ_FIFO_ADDR_RESERVED0_ALIGN 0 10697 #define DDR34_E0_PHY_BYTE_LANE_1_READ_FIFO_ADDR_RESERVED0_BITS 29 10698 #define DDR34_E0_PHY_BYTE_LANE_1_READ_FIFO_ADDR_RESERVED0_SHIFT 3 10699 10700 /* DDR34_E0_PHY_BYTE_LANE_1 :: READ_FIFO_ADDR :: ADDR [02:00] */ 10701 #define DDR34_E0_PHY_BYTE_LANE_1_READ_FIFO_ADDR_ADDR_MASK 0x00000007 10702 #define DDR34_E0_PHY_BYTE_LANE_1_READ_FIFO_ADDR_ADDR_ALIGN 0 10703 #define DDR34_E0_PHY_BYTE_LANE_1_READ_FIFO_ADDR_ADDR_BITS 3 10704 #define DDR34_E0_PHY_BYTE_LANE_1_READ_FIFO_ADDR_ADDR_SHIFT 0 10705 #define DDR34_E0_PHY_BYTE_LANE_1_READ_FIFO_ADDR_ADDR_DEFAULT 0x00000000 10706 10707 /*************************************************************************** 10708 *READ_FIFO_DATA - Read fifo data register 10709 */ 10710 /* DDR34_E0_PHY_BYTE_LANE_1 :: READ_FIFO_DATA :: DATA [31:00] */ 10711 #define DDR34_E0_PHY_BYTE_LANE_1_READ_FIFO_DATA_DATA_MASK 0xffffffff 10712 #define DDR34_E0_PHY_BYTE_LANE_1_READ_FIFO_DATA_DATA_ALIGN 0 10713 #define DDR34_E0_PHY_BYTE_LANE_1_READ_FIFO_DATA_DATA_BITS 32 10714 #define DDR34_E0_PHY_BYTE_LANE_1_READ_FIFO_DATA_DATA_SHIFT 0 10715 10716 /*************************************************************************** 10717 *READ_FIFO_DM_DBI - Read fifo dm/dbi register 10718 */ 10719 /* DDR34_E0_PHY_BYTE_LANE_1 :: READ_FIFO_DM_DBI :: reserved0 [31:04] */ 10720 #define DDR34_E0_PHY_BYTE_LANE_1_READ_FIFO_DM_DBI_RESERVED0_MASK 0xfffffff0 10721 #define DDR34_E0_PHY_BYTE_LANE_1_READ_FIFO_DM_DBI_RESERVED0_ALIGN 0 10722 #define DDR34_E0_PHY_BYTE_LANE_1_READ_FIFO_DM_DBI_RESERVED0_BITS 28 10723 #define DDR34_E0_PHY_BYTE_LANE_1_READ_FIFO_DM_DBI_RESERVED0_SHIFT 4 10724 10725 /* DDR34_E0_PHY_BYTE_LANE_1 :: READ_FIFO_DM_DBI :: DM_DBI [03:00] */ 10726 #define DDR34_E0_PHY_BYTE_LANE_1_READ_FIFO_DM_DBI_DM_DBI_MASK 0x0000000f 10727 #define DDR34_E0_PHY_BYTE_LANE_1_READ_FIFO_DM_DBI_DM_DBI_ALIGN 0 10728 #define DDR34_E0_PHY_BYTE_LANE_1_READ_FIFO_DM_DBI_DM_DBI_BITS 4 10729 #define DDR34_E0_PHY_BYTE_LANE_1_READ_FIFO_DM_DBI_DM_DBI_SHIFT 0 10730 10731 /*************************************************************************** 10732 *READ_FIFO_STATUS - Read fifo status register 10733 */ 10734 /* DDR34_E0_PHY_BYTE_LANE_1 :: READ_FIFO_STATUS :: reserved0 [31:02] */ 10735 #define DDR34_E0_PHY_BYTE_LANE_1_READ_FIFO_STATUS_RESERVED0_MASK 0xfffffffc 10736 #define DDR34_E0_PHY_BYTE_LANE_1_READ_FIFO_STATUS_RESERVED0_ALIGN 0 10737 #define DDR34_E0_PHY_BYTE_LANE_1_READ_FIFO_STATUS_RESERVED0_BITS 30 10738 #define DDR34_E0_PHY_BYTE_LANE_1_READ_FIFO_STATUS_RESERVED0_SHIFT 2 10739 10740 /* DDR34_E0_PHY_BYTE_LANE_1 :: READ_FIFO_STATUS :: OVERFLOW [01:01] */ 10741 #define DDR34_E0_PHY_BYTE_LANE_1_READ_FIFO_STATUS_OVERFLOW_MASK 0x00000002 10742 #define DDR34_E0_PHY_BYTE_LANE_1_READ_FIFO_STATUS_OVERFLOW_ALIGN 0 10743 #define DDR34_E0_PHY_BYTE_LANE_1_READ_FIFO_STATUS_OVERFLOW_BITS 1 10744 #define DDR34_E0_PHY_BYTE_LANE_1_READ_FIFO_STATUS_OVERFLOW_SHIFT 1 10745 #define DDR34_E0_PHY_BYTE_LANE_1_READ_FIFO_STATUS_OVERFLOW_DEFAULT 0x00000000 10746 10747 /* DDR34_E0_PHY_BYTE_LANE_1 :: READ_FIFO_STATUS :: UNDERFLOW [00:00] */ 10748 #define DDR34_E0_PHY_BYTE_LANE_1_READ_FIFO_STATUS_UNDERFLOW_MASK 0x00000001 10749 #define DDR34_E0_PHY_BYTE_LANE_1_READ_FIFO_STATUS_UNDERFLOW_ALIGN 0 10750 #define DDR34_E0_PHY_BYTE_LANE_1_READ_FIFO_STATUS_UNDERFLOW_BITS 1 10751 #define DDR34_E0_PHY_BYTE_LANE_1_READ_FIFO_STATUS_UNDERFLOW_SHIFT 0 10752 #define DDR34_E0_PHY_BYTE_LANE_1_READ_FIFO_STATUS_UNDERFLOW_DEFAULT 0x00000000 10753 10754 /*************************************************************************** 10755 *READ_FIFO_CLEAR - Read fifo status clear register 10756 */ 10757 /* DDR34_E0_PHY_BYTE_LANE_1 :: READ_FIFO_CLEAR :: reserved0 [31:01] */ 10758 #define DDR34_E0_PHY_BYTE_LANE_1_READ_FIFO_CLEAR_RESERVED0_MASK 0xfffffffe 10759 #define DDR34_E0_PHY_BYTE_LANE_1_READ_FIFO_CLEAR_RESERVED0_ALIGN 0 10760 #define DDR34_E0_PHY_BYTE_LANE_1_READ_FIFO_CLEAR_RESERVED0_BITS 31 10761 #define DDR34_E0_PHY_BYTE_LANE_1_READ_FIFO_CLEAR_RESERVED0_SHIFT 1 10762 10763 /* DDR34_E0_PHY_BYTE_LANE_1 :: READ_FIFO_CLEAR :: CLEAR [00:00] */ 10764 #define DDR34_E0_PHY_BYTE_LANE_1_READ_FIFO_CLEAR_CLEAR_MASK 0x00000001 10765 #define DDR34_E0_PHY_BYTE_LANE_1_READ_FIFO_CLEAR_CLEAR_ALIGN 0 10766 #define DDR34_E0_PHY_BYTE_LANE_1_READ_FIFO_CLEAR_CLEAR_BITS 1 10767 #define DDR34_E0_PHY_BYTE_LANE_1_READ_FIFO_CLEAR_CLEAR_SHIFT 0 10768 #define DDR34_E0_PHY_BYTE_LANE_1_READ_FIFO_CLEAR_CLEAR_DEFAULT 0x00000000 10769 10770 /*************************************************************************** 10771 *IDLE_PAD_CONTROL - Idle mode SSTL pad control register 10772 */ 10773 /* DDR34_E0_PHY_BYTE_LANE_1 :: IDLE_PAD_CONTROL :: IDLE [31:31] */ 10774 #define DDR34_E0_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_IDLE_MASK 0x80000000 10775 #define DDR34_E0_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_IDLE_ALIGN 0 10776 #define DDR34_E0_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_IDLE_BITS 1 10777 #define DDR34_E0_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_IDLE_SHIFT 31 10778 #define DDR34_E0_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_IDLE_DEFAULT 0x00000000 10779 10780 /* DDR34_E0_PHY_BYTE_LANE_1 :: IDLE_PAD_CONTROL :: reserved0 [30:20] */ 10781 #define DDR34_E0_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_RESERVED0_MASK 0x7ff00000 10782 #define DDR34_E0_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_RESERVED0_ALIGN 0 10783 #define DDR34_E0_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_RESERVED0_BITS 11 10784 #define DDR34_E0_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_RESERVED0_SHIFT 20 10785 10786 /* DDR34_E0_PHY_BYTE_LANE_1 :: IDLE_PAD_CONTROL :: AUTO_DQ_RXENB_MODE [19:18] */ 10787 #define DDR34_E0_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_AUTO_DQ_RXENB_MODE_MASK 0x000c0000 10788 #define DDR34_E0_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_AUTO_DQ_RXENB_MODE_ALIGN 0 10789 #define DDR34_E0_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_AUTO_DQ_RXENB_MODE_BITS 2 10790 #define DDR34_E0_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_AUTO_DQ_RXENB_MODE_SHIFT 18 10791 #define DDR34_E0_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_AUTO_DQ_RXENB_MODE_DEFAULT 0x00000001 10792 10793 /* DDR34_E0_PHY_BYTE_LANE_1 :: IDLE_PAD_CONTROL :: AUTO_DQ_IDDQ_MODE [17:16] */ 10794 #define DDR34_E0_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_AUTO_DQ_IDDQ_MODE_MASK 0x00030000 10795 #define DDR34_E0_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_AUTO_DQ_IDDQ_MODE_ALIGN 0 10796 #define DDR34_E0_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_AUTO_DQ_IDDQ_MODE_BITS 2 10797 #define DDR34_E0_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_AUTO_DQ_IDDQ_MODE_SHIFT 16 10798 #define DDR34_E0_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_AUTO_DQ_IDDQ_MODE_DEFAULT 0x00000001 10799 10800 /* DDR34_E0_PHY_BYTE_LANE_1 :: IDLE_PAD_CONTROL :: reserved_for_padding1 [15:15] */ 10801 #define DDR34_E0_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_RESERVED_for_padding1_MASK 0x00008000 10802 #define DDR34_E0_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_RESERVED_for_padding1_ALIGN 0 10803 #define DDR34_E0_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_RESERVED_for_padding1_BITS 1 10804 #define DDR34_E0_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_RESERVED_for_padding1_SHIFT 15 10805 10806 /* DDR34_E0_PHY_BYTE_LANE_1 :: IDLE_PAD_CONTROL :: IO_IDLE_ENABLE [14:04] */ 10807 #define DDR34_E0_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_IO_IDLE_ENABLE_MASK 0x00007ff0 10808 #define DDR34_E0_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_IO_IDLE_ENABLE_ALIGN 0 10809 #define DDR34_E0_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_IO_IDLE_ENABLE_BITS 11 10810 #define DDR34_E0_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_IO_IDLE_ENABLE_SHIFT 4 10811 #define DDR34_E0_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_IO_IDLE_ENABLE_DEFAULT 0x00000000 10812 10813 /* DDR34_E0_PHY_BYTE_LANE_1 :: IDLE_PAD_CONTROL :: RXENB [03:03] */ 10814 #define DDR34_E0_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_RXENB_MASK 0x00000008 10815 #define DDR34_E0_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_RXENB_ALIGN 0 10816 #define DDR34_E0_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_RXENB_BITS 1 10817 #define DDR34_E0_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_RXENB_SHIFT 3 10818 #define DDR34_E0_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_RXENB_DEFAULT 0x00000001 10819 10820 /* DDR34_E0_PHY_BYTE_LANE_1 :: IDLE_PAD_CONTROL :: IDDQ [02:02] */ 10821 #define DDR34_E0_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_IDDQ_MASK 0x00000004 10822 #define DDR34_E0_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_IDDQ_ALIGN 0 10823 #define DDR34_E0_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_IDDQ_BITS 1 10824 #define DDR34_E0_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_IDDQ_SHIFT 2 10825 #define DDR34_E0_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_IDDQ_DEFAULT 0x00000000 10826 10827 /* DDR34_E0_PHY_BYTE_LANE_1 :: IDLE_PAD_CONTROL :: DOUT_N [01:01] */ 10828 #define DDR34_E0_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_DOUT_N_MASK 0x00000002 10829 #define DDR34_E0_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_DOUT_N_ALIGN 0 10830 #define DDR34_E0_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_DOUT_N_BITS 1 10831 #define DDR34_E0_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_DOUT_N_SHIFT 1 10832 #define DDR34_E0_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_DOUT_N_DEFAULT 0x00000001 10833 10834 /* DDR34_E0_PHY_BYTE_LANE_1 :: IDLE_PAD_CONTROL :: DOUT_P [00:00] */ 10835 #define DDR34_E0_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_DOUT_P_MASK 0x00000001 10836 #define DDR34_E0_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_DOUT_P_ALIGN 0 10837 #define DDR34_E0_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_DOUT_P_BITS 1 10838 #define DDR34_E0_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_DOUT_P_SHIFT 0 10839 #define DDR34_E0_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_DOUT_P_DEFAULT 0x00000000 10840 10841 /*************************************************************************** 10842 *DRIVE_PAD_CTL - SSTL pad drive characteristics control register 10843 */ 10844 /* DDR34_E0_PHY_BYTE_LANE_1 :: DRIVE_PAD_CTL :: reserved0 [31:30] */ 10845 #define DDR34_E0_PHY_BYTE_LANE_1_DRIVE_PAD_CTL_RESERVED0_MASK 0xc0000000 10846 #define DDR34_E0_PHY_BYTE_LANE_1_DRIVE_PAD_CTL_RESERVED0_ALIGN 0 10847 #define DDR34_E0_PHY_BYTE_LANE_1_DRIVE_PAD_CTL_RESERVED0_BITS 2 10848 #define DDR34_E0_PHY_BYTE_LANE_1_DRIVE_PAD_CTL_RESERVED0_SHIFT 30 10849 10850 /* DDR34_E0_PHY_BYTE_LANE_1 :: DRIVE_PAD_CTL :: BL_PD_IDLE_STRENGTH [29:25] */ 10851 #define DDR34_E0_PHY_BYTE_LANE_1_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_MASK 0x3e000000 10852 #define DDR34_E0_PHY_BYTE_LANE_1_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_ALIGN 0 10853 #define DDR34_E0_PHY_BYTE_LANE_1_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_BITS 5 10854 #define DDR34_E0_PHY_BYTE_LANE_1_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_SHIFT 25 10855 #define DDR34_E0_PHY_BYTE_LANE_1_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_DEFAULT 0x0000001f 10856 10857 /* DDR34_E0_PHY_BYTE_LANE_1 :: DRIVE_PAD_CTL :: BL_ND_IDLE_STRENGTH [24:20] */ 10858 #define DDR34_E0_PHY_BYTE_LANE_1_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_MASK 0x01f00000 10859 #define DDR34_E0_PHY_BYTE_LANE_1_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_ALIGN 0 10860 #define DDR34_E0_PHY_BYTE_LANE_1_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_BITS 5 10861 #define DDR34_E0_PHY_BYTE_LANE_1_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_SHIFT 20 10862 #define DDR34_E0_PHY_BYTE_LANE_1_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_DEFAULT 0x0000001f 10863 10864 /* DDR34_E0_PHY_BYTE_LANE_1 :: DRIVE_PAD_CTL :: BL_PD_TERM_STRENGTH [19:15] */ 10865 #define DDR34_E0_PHY_BYTE_LANE_1_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_MASK 0x000f8000 10866 #define DDR34_E0_PHY_BYTE_LANE_1_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_ALIGN 0 10867 #define DDR34_E0_PHY_BYTE_LANE_1_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_BITS 5 10868 #define DDR34_E0_PHY_BYTE_LANE_1_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_SHIFT 15 10869 #define DDR34_E0_PHY_BYTE_LANE_1_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_DEFAULT 0x00000006 10870 10871 /* DDR34_E0_PHY_BYTE_LANE_1 :: DRIVE_PAD_CTL :: BL_ND_TERM_STRENGTH [14:10] */ 10872 #define DDR34_E0_PHY_BYTE_LANE_1_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_MASK 0x00007c00 10873 #define DDR34_E0_PHY_BYTE_LANE_1_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_ALIGN 0 10874 #define DDR34_E0_PHY_BYTE_LANE_1_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_BITS 5 10875 #define DDR34_E0_PHY_BYTE_LANE_1_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_SHIFT 10 10876 #define DDR34_E0_PHY_BYTE_LANE_1_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_DEFAULT 0x00000006 10877 10878 /* DDR34_E0_PHY_BYTE_LANE_1 :: DRIVE_PAD_CTL :: BL_PD_STRENGTH [09:05] */ 10879 #define DDR34_E0_PHY_BYTE_LANE_1_DRIVE_PAD_CTL_BL_PD_STRENGTH_MASK 0x000003e0 10880 #define DDR34_E0_PHY_BYTE_LANE_1_DRIVE_PAD_CTL_BL_PD_STRENGTH_ALIGN 0 10881 #define DDR34_E0_PHY_BYTE_LANE_1_DRIVE_PAD_CTL_BL_PD_STRENGTH_BITS 5 10882 #define DDR34_E0_PHY_BYTE_LANE_1_DRIVE_PAD_CTL_BL_PD_STRENGTH_SHIFT 5 10883 #define DDR34_E0_PHY_BYTE_LANE_1_DRIVE_PAD_CTL_BL_PD_STRENGTH_DEFAULT 0x0000001f 10884 10885 /* DDR34_E0_PHY_BYTE_LANE_1 :: DRIVE_PAD_CTL :: BL_ND_STRENGTH [04:00] */ 10886 #define DDR34_E0_PHY_BYTE_LANE_1_DRIVE_PAD_CTL_BL_ND_STRENGTH_MASK 0x0000001f 10887 #define DDR34_E0_PHY_BYTE_LANE_1_DRIVE_PAD_CTL_BL_ND_STRENGTH_ALIGN 0 10888 #define DDR34_E0_PHY_BYTE_LANE_1_DRIVE_PAD_CTL_BL_ND_STRENGTH_BITS 5 10889 #define DDR34_E0_PHY_BYTE_LANE_1_DRIVE_PAD_CTL_BL_ND_STRENGTH_SHIFT 0 10890 #define DDR34_E0_PHY_BYTE_LANE_1_DRIVE_PAD_CTL_BL_ND_STRENGTH_DEFAULT 0x0000001f 10891 10892 /*************************************************************************** 10893 *RD_EN_DRIVE_PAD_CTL - SSTL read enable pad drive characteristics control register 10894 */ 10895 /* DDR34_E0_PHY_BYTE_LANE_1 :: RD_EN_DRIVE_PAD_CTL :: reserved0 [31:20] */ 10896 #define DDR34_E0_PHY_BYTE_LANE_1_RD_EN_DRIVE_PAD_CTL_RESERVED0_MASK 0xfff00000 10897 #define DDR34_E0_PHY_BYTE_LANE_1_RD_EN_DRIVE_PAD_CTL_RESERVED0_ALIGN 0 10898 #define DDR34_E0_PHY_BYTE_LANE_1_RD_EN_DRIVE_PAD_CTL_RESERVED0_BITS 12 10899 #define DDR34_E0_PHY_BYTE_LANE_1_RD_EN_DRIVE_PAD_CTL_RESERVED0_SHIFT 20 10900 10901 /* DDR34_E0_PHY_BYTE_LANE_1 :: RD_EN_DRIVE_PAD_CTL :: EDC_RD_EN_PD_STRENGTH [19:15] */ 10902 #define DDR34_E0_PHY_BYTE_LANE_1_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_PD_STRENGTH_MASK 0x000f8000 10903 #define DDR34_E0_PHY_BYTE_LANE_1_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_PD_STRENGTH_ALIGN 0 10904 #define DDR34_E0_PHY_BYTE_LANE_1_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_PD_STRENGTH_BITS 5 10905 #define DDR34_E0_PHY_BYTE_LANE_1_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_PD_STRENGTH_SHIFT 15 10906 #define DDR34_E0_PHY_BYTE_LANE_1_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_PD_STRENGTH_DEFAULT 0x0000001f 10907 10908 /* DDR34_E0_PHY_BYTE_LANE_1 :: RD_EN_DRIVE_PAD_CTL :: EDC_RD_EN_ND_STRENGTH [14:10] */ 10909 #define DDR34_E0_PHY_BYTE_LANE_1_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_ND_STRENGTH_MASK 0x00007c00 10910 #define DDR34_E0_PHY_BYTE_LANE_1_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_ND_STRENGTH_ALIGN 0 10911 #define DDR34_E0_PHY_BYTE_LANE_1_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_ND_STRENGTH_BITS 5 10912 #define DDR34_E0_PHY_BYTE_LANE_1_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_ND_STRENGTH_SHIFT 10 10913 #define DDR34_E0_PHY_BYTE_LANE_1_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_ND_STRENGTH_DEFAULT 0x0000001f 10914 10915 /* DDR34_E0_PHY_BYTE_LANE_1 :: RD_EN_DRIVE_PAD_CTL :: BL_RD_EN_PD_STRENGTH [09:05] */ 10916 #define DDR34_E0_PHY_BYTE_LANE_1_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_PD_STRENGTH_MASK 0x000003e0 10917 #define DDR34_E0_PHY_BYTE_LANE_1_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_PD_STRENGTH_ALIGN 0 10918 #define DDR34_E0_PHY_BYTE_LANE_1_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_PD_STRENGTH_BITS 5 10919 #define DDR34_E0_PHY_BYTE_LANE_1_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_PD_STRENGTH_SHIFT 5 10920 #define DDR34_E0_PHY_BYTE_LANE_1_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_PD_STRENGTH_DEFAULT 0x0000001f 10921 10922 /* DDR34_E0_PHY_BYTE_LANE_1 :: RD_EN_DRIVE_PAD_CTL :: BL_RD_EN_ND_STRENGTH [04:00] */ 10923 #define DDR34_E0_PHY_BYTE_LANE_1_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_ND_STRENGTH_MASK 0x0000001f 10924 #define DDR34_E0_PHY_BYTE_LANE_1_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_ND_STRENGTH_ALIGN 0 10925 #define DDR34_E0_PHY_BYTE_LANE_1_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_ND_STRENGTH_BITS 5 10926 #define DDR34_E0_PHY_BYTE_LANE_1_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_ND_STRENGTH_SHIFT 0 10927 #define DDR34_E0_PHY_BYTE_LANE_1_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_ND_STRENGTH_DEFAULT 0x0000001f 10928 10929 /*************************************************************************** 10930 *STATIC_PAD_CTL - pad rx and tx characteristics control register 10931 */ 10932 /* DDR34_E0_PHY_BYTE_LANE_1 :: STATIC_PAD_CTL :: reserved0 [31:21] */ 10933 #define DDR34_E0_PHY_BYTE_LANE_1_STATIC_PAD_CTL_RESERVED0_MASK 0xffe00000 10934 #define DDR34_E0_PHY_BYTE_LANE_1_STATIC_PAD_CTL_RESERVED0_ALIGN 0 10935 #define DDR34_E0_PHY_BYTE_LANE_1_STATIC_PAD_CTL_RESERVED0_BITS 11 10936 #define DDR34_E0_PHY_BYTE_LANE_1_STATIC_PAD_CTL_RESERVED0_SHIFT 21 10937 10938 /* DDR34_E0_PHY_BYTE_LANE_1 :: STATIC_PAD_CTL :: DQS_MODE [20:20] */ 10939 #define DDR34_E0_PHY_BYTE_LANE_1_STATIC_PAD_CTL_DQS_MODE_MASK 0x00100000 10940 #define DDR34_E0_PHY_BYTE_LANE_1_STATIC_PAD_CTL_DQS_MODE_ALIGN 0 10941 #define DDR34_E0_PHY_BYTE_LANE_1_STATIC_PAD_CTL_DQS_MODE_BITS 1 10942 #define DDR34_E0_PHY_BYTE_LANE_1_STATIC_PAD_CTL_DQS_MODE_SHIFT 20 10943 #define DDR34_E0_PHY_BYTE_LANE_1_STATIC_PAD_CTL_DQS_MODE_DEFAULT 0x00000000 10944 10945 /* DDR34_E0_PHY_BYTE_LANE_1 :: STATIC_PAD_CTL :: reserved1 [19:18] */ 10946 #define DDR34_E0_PHY_BYTE_LANE_1_STATIC_PAD_CTL_RESERVED1_MASK 0x000c0000 10947 #define DDR34_E0_PHY_BYTE_LANE_1_STATIC_PAD_CTL_RESERVED1_ALIGN 0 10948 #define DDR34_E0_PHY_BYTE_LANE_1_STATIC_PAD_CTL_RESERVED1_BITS 2 10949 #define DDR34_E0_PHY_BYTE_LANE_1_STATIC_PAD_CTL_RESERVED1_SHIFT 18 10950 10951 /* DDR34_E0_PHY_BYTE_LANE_1 :: STATIC_PAD_CTL :: EDC_MODE [17:16] */ 10952 #define DDR34_E0_PHY_BYTE_LANE_1_STATIC_PAD_CTL_EDC_MODE_MASK 0x00030000 10953 #define DDR34_E0_PHY_BYTE_LANE_1_STATIC_PAD_CTL_EDC_MODE_ALIGN 0 10954 #define DDR34_E0_PHY_BYTE_LANE_1_STATIC_PAD_CTL_EDC_MODE_BITS 2 10955 #define DDR34_E0_PHY_BYTE_LANE_1_STATIC_PAD_CTL_EDC_MODE_SHIFT 16 10956 #define DDR34_E0_PHY_BYTE_LANE_1_STATIC_PAD_CTL_EDC_MODE_DEFAULT 0x00000000 10957 10958 /* DDR34_E0_PHY_BYTE_LANE_1 :: STATIC_PAD_CTL :: reserved2 [15:15] */ 10959 #define DDR34_E0_PHY_BYTE_LANE_1_STATIC_PAD_CTL_RESERVED2_MASK 0x00008000 10960 #define DDR34_E0_PHY_BYTE_LANE_1_STATIC_PAD_CTL_RESERVED2_ALIGN 0 10961 #define DDR34_E0_PHY_BYTE_LANE_1_STATIC_PAD_CTL_RESERVED2_BITS 1 10962 #define DDR34_E0_PHY_BYTE_LANE_1_STATIC_PAD_CTL_RESERVED2_SHIFT 15 10963 10964 /* DDR34_E0_PHY_BYTE_LANE_1 :: STATIC_PAD_CTL :: WDBI_ENABLE [14:14] */ 10965 #define DDR34_E0_PHY_BYTE_LANE_1_STATIC_PAD_CTL_WDBI_ENABLE_MASK 0x00004000 10966 #define DDR34_E0_PHY_BYTE_LANE_1_STATIC_PAD_CTL_WDBI_ENABLE_ALIGN 0 10967 #define DDR34_E0_PHY_BYTE_LANE_1_STATIC_PAD_CTL_WDBI_ENABLE_BITS 1 10968 #define DDR34_E0_PHY_BYTE_LANE_1_STATIC_PAD_CTL_WDBI_ENABLE_SHIFT 14 10969 #define DDR34_E0_PHY_BYTE_LANE_1_STATIC_PAD_CTL_WDBI_ENABLE_DEFAULT 0x00000000 10970 10971 /* DDR34_E0_PHY_BYTE_LANE_1 :: STATIC_PAD_CTL :: RDBI_ENABLE [13:13] */ 10972 #define DDR34_E0_PHY_BYTE_LANE_1_STATIC_PAD_CTL_RDBI_ENABLE_MASK 0x00002000 10973 #define DDR34_E0_PHY_BYTE_LANE_1_STATIC_PAD_CTL_RDBI_ENABLE_ALIGN 0 10974 #define DDR34_E0_PHY_BYTE_LANE_1_STATIC_PAD_CTL_RDBI_ENABLE_BITS 1 10975 #define DDR34_E0_PHY_BYTE_LANE_1_STATIC_PAD_CTL_RDBI_ENABLE_SHIFT 13 10976 #define DDR34_E0_PHY_BYTE_LANE_1_STATIC_PAD_CTL_RDBI_ENABLE_DEFAULT 0x00000000 10977 10978 /* DDR34_E0_PHY_BYTE_LANE_1 :: STATIC_PAD_CTL :: DM_MODE [12:12] */ 10979 #define DDR34_E0_PHY_BYTE_LANE_1_STATIC_PAD_CTL_DM_MODE_MASK 0x00001000 10980 #define DDR34_E0_PHY_BYTE_LANE_1_STATIC_PAD_CTL_DM_MODE_ALIGN 0 10981 #define DDR34_E0_PHY_BYTE_LANE_1_STATIC_PAD_CTL_DM_MODE_BITS 1 10982 #define DDR34_E0_PHY_BYTE_LANE_1_STATIC_PAD_CTL_DM_MODE_SHIFT 12 10983 #define DDR34_E0_PHY_BYTE_LANE_1_STATIC_PAD_CTL_DM_MODE_DEFAULT 0x00000000 10984 10985 /* DDR34_E0_PHY_BYTE_LANE_1 :: STATIC_PAD_CTL :: reserved3 [11:10] */ 10986 #define DDR34_E0_PHY_BYTE_LANE_1_STATIC_PAD_CTL_RESERVED3_MASK 0x00000c00 10987 #define DDR34_E0_PHY_BYTE_LANE_1_STATIC_PAD_CTL_RESERVED3_ALIGN 0 10988 #define DDR34_E0_PHY_BYTE_LANE_1_STATIC_PAD_CTL_RESERVED3_BITS 2 10989 #define DDR34_E0_PHY_BYTE_LANE_1_STATIC_PAD_CTL_RESERVED3_SHIFT 10 10990 10991 /* DDR34_E0_PHY_BYTE_LANE_1 :: STATIC_PAD_CTL :: DQS_TX_DIS [09:09] */ 10992 #define DDR34_E0_PHY_BYTE_LANE_1_STATIC_PAD_CTL_DQS_TX_DIS_MASK 0x00000200 10993 #define DDR34_E0_PHY_BYTE_LANE_1_STATIC_PAD_CTL_DQS_TX_DIS_ALIGN 0 10994 #define DDR34_E0_PHY_BYTE_LANE_1_STATIC_PAD_CTL_DQS_TX_DIS_BITS 1 10995 #define DDR34_E0_PHY_BYTE_LANE_1_STATIC_PAD_CTL_DQS_TX_DIS_SHIFT 9 10996 #define DDR34_E0_PHY_BYTE_LANE_1_STATIC_PAD_CTL_DQS_TX_DIS_DEFAULT 0x00000000 10997 10998 /* DDR34_E0_PHY_BYTE_LANE_1 :: STATIC_PAD_CTL :: reserved4 [08:02] */ 10999 #define DDR34_E0_PHY_BYTE_LANE_1_STATIC_PAD_CTL_RESERVED4_MASK 0x000001fc 11000 #define DDR34_E0_PHY_BYTE_LANE_1_STATIC_PAD_CTL_RESERVED4_ALIGN 0 11001 #define DDR34_E0_PHY_BYTE_LANE_1_STATIC_PAD_CTL_RESERVED4_BITS 7 11002 #define DDR34_E0_PHY_BYTE_LANE_1_STATIC_PAD_CTL_RESERVED4_SHIFT 2 11003 11004 /* DDR34_E0_PHY_BYTE_LANE_1 :: STATIC_PAD_CTL :: RX_MODE [01:00] */ 11005 #define DDR34_E0_PHY_BYTE_LANE_1_STATIC_PAD_CTL_RX_MODE_MASK 0x00000003 11006 #define DDR34_E0_PHY_BYTE_LANE_1_STATIC_PAD_CTL_RX_MODE_ALIGN 0 11007 #define DDR34_E0_PHY_BYTE_LANE_1_STATIC_PAD_CTL_RX_MODE_BITS 2 11008 #define DDR34_E0_PHY_BYTE_LANE_1_STATIC_PAD_CTL_RX_MODE_SHIFT 0 11009 #define DDR34_E0_PHY_BYTE_LANE_1_STATIC_PAD_CTL_RX_MODE_DEFAULT 0x00000000 11010 11011 /*************************************************************************** 11012 *WR_PREAMBLE_MODE - Write cycle preamble control register 11013 */ 11014 /* DDR34_E0_PHY_BYTE_LANE_1 :: WR_PREAMBLE_MODE :: reserved0 [31:16] */ 11015 #define DDR34_E0_PHY_BYTE_LANE_1_WR_PREAMBLE_MODE_RESERVED0_MASK 0xffff0000 11016 #define DDR34_E0_PHY_BYTE_LANE_1_WR_PREAMBLE_MODE_RESERVED0_ALIGN 0 11017 #define DDR34_E0_PHY_BYTE_LANE_1_WR_PREAMBLE_MODE_RESERVED0_BITS 16 11018 #define DDR34_E0_PHY_BYTE_LANE_1_WR_PREAMBLE_MODE_RESERVED0_SHIFT 16 11019 11020 /* DDR34_E0_PHY_BYTE_LANE_1 :: WR_PREAMBLE_MODE :: DQ_POSTAM_BITS [15:14] */ 11021 #define DDR34_E0_PHY_BYTE_LANE_1_WR_PREAMBLE_MODE_DQ_POSTAM_BITS_MASK 0x0000c000 11022 #define DDR34_E0_PHY_BYTE_LANE_1_WR_PREAMBLE_MODE_DQ_POSTAM_BITS_ALIGN 0 11023 #define DDR34_E0_PHY_BYTE_LANE_1_WR_PREAMBLE_MODE_DQ_POSTAM_BITS_BITS 2 11024 #define DDR34_E0_PHY_BYTE_LANE_1_WR_PREAMBLE_MODE_DQ_POSTAM_BITS_SHIFT 14 11025 #define DDR34_E0_PHY_BYTE_LANE_1_WR_PREAMBLE_MODE_DQ_POSTAM_BITS_DEFAULT 0x00000000 11026 11027 /* DDR34_E0_PHY_BYTE_LANE_1 :: WR_PREAMBLE_MODE :: DQ_PREAM_BITS [13:12] */ 11028 #define DDR34_E0_PHY_BYTE_LANE_1_WR_PREAMBLE_MODE_DQ_PREAM_BITS_MASK 0x00003000 11029 #define DDR34_E0_PHY_BYTE_LANE_1_WR_PREAMBLE_MODE_DQ_PREAM_BITS_ALIGN 0 11030 #define DDR34_E0_PHY_BYTE_LANE_1_WR_PREAMBLE_MODE_DQ_PREAM_BITS_BITS 2 11031 #define DDR34_E0_PHY_BYTE_LANE_1_WR_PREAMBLE_MODE_DQ_PREAM_BITS_SHIFT 12 11032 #define DDR34_E0_PHY_BYTE_LANE_1_WR_PREAMBLE_MODE_DQ_PREAM_BITS_DEFAULT 0x00000000 11033 11034 /* DDR34_E0_PHY_BYTE_LANE_1 :: WR_PREAMBLE_MODE :: DQS [11:08] */ 11035 #define DDR34_E0_PHY_BYTE_LANE_1_WR_PREAMBLE_MODE_DQS_MASK 0x00000f00 11036 #define DDR34_E0_PHY_BYTE_LANE_1_WR_PREAMBLE_MODE_DQS_ALIGN 0 11037 #define DDR34_E0_PHY_BYTE_LANE_1_WR_PREAMBLE_MODE_DQS_BITS 4 11038 #define DDR34_E0_PHY_BYTE_LANE_1_WR_PREAMBLE_MODE_DQS_SHIFT 8 11039 #define DDR34_E0_PHY_BYTE_LANE_1_WR_PREAMBLE_MODE_DQS_DEFAULT 0x0000000e 11040 11041 /* DDR34_E0_PHY_BYTE_LANE_1 :: WR_PREAMBLE_MODE :: reserved1 [07:05] */ 11042 #define DDR34_E0_PHY_BYTE_LANE_1_WR_PREAMBLE_MODE_RESERVED1_MASK 0x000000e0 11043 #define DDR34_E0_PHY_BYTE_LANE_1_WR_PREAMBLE_MODE_RESERVED1_ALIGN 0 11044 #define DDR34_E0_PHY_BYTE_LANE_1_WR_PREAMBLE_MODE_RESERVED1_BITS 3 11045 #define DDR34_E0_PHY_BYTE_LANE_1_WR_PREAMBLE_MODE_RESERVED1_SHIFT 5 11046 11047 /* DDR34_E0_PHY_BYTE_LANE_1 :: WR_PREAMBLE_MODE :: DQS_POSTAM_BITS [04:03] */ 11048 #define DDR34_E0_PHY_BYTE_LANE_1_WR_PREAMBLE_MODE_DQS_POSTAM_BITS_MASK 0x00000018 11049 #define DDR34_E0_PHY_BYTE_LANE_1_WR_PREAMBLE_MODE_DQS_POSTAM_BITS_ALIGN 0 11050 #define DDR34_E0_PHY_BYTE_LANE_1_WR_PREAMBLE_MODE_DQS_POSTAM_BITS_BITS 2 11051 #define DDR34_E0_PHY_BYTE_LANE_1_WR_PREAMBLE_MODE_DQS_POSTAM_BITS_SHIFT 3 11052 #define DDR34_E0_PHY_BYTE_LANE_1_WR_PREAMBLE_MODE_DQS_POSTAM_BITS_DEFAULT 0x00000000 11053 11054 /* DDR34_E0_PHY_BYTE_LANE_1 :: WR_PREAMBLE_MODE :: DQS_PREAM_BITS [02:00] */ 11055 #define DDR34_E0_PHY_BYTE_LANE_1_WR_PREAMBLE_MODE_DQS_PREAM_BITS_MASK 0x00000007 11056 #define DDR34_E0_PHY_BYTE_LANE_1_WR_PREAMBLE_MODE_DQS_PREAM_BITS_ALIGN 0 11057 #define DDR34_E0_PHY_BYTE_LANE_1_WR_PREAMBLE_MODE_DQS_PREAM_BITS_BITS 3 11058 #define DDR34_E0_PHY_BYTE_LANE_1_WR_PREAMBLE_MODE_DQS_PREAM_BITS_SHIFT 0 11059 #define DDR34_E0_PHY_BYTE_LANE_1_WR_PREAMBLE_MODE_DQS_PREAM_BITS_DEFAULT 0x00000002 11060 11061 /*************************************************************************** 11062 *ODT_CONTROL - Read channel ODT control register 11063 */ 11064 /* DDR34_E0_PHY_BYTE_LANE_1 :: ODT_CONTROL :: reserved_for_padding0 [31:31] */ 11065 #define DDR34_E0_PHY_BYTE_LANE_1_ODT_CONTROL_RESERVED_for_padding0_MASK 0x80000000 11066 #define DDR34_E0_PHY_BYTE_LANE_1_ODT_CONTROL_RESERVED_for_padding0_ALIGN 0 11067 #define DDR34_E0_PHY_BYTE_LANE_1_ODT_CONTROL_RESERVED_for_padding0_BITS 1 11068 #define DDR34_E0_PHY_BYTE_LANE_1_ODT_CONTROL_RESERVED_for_padding0_SHIFT 31 11069 11070 /* DDR34_E0_PHY_BYTE_LANE_1 :: ODT_CONTROL :: reserved1 [30:10] */ 11071 #define DDR34_E0_PHY_BYTE_LANE_1_ODT_CONTROL_RESERVED1_MASK 0x7ffffc00 11072 #define DDR34_E0_PHY_BYTE_LANE_1_ODT_CONTROL_RESERVED1_ALIGN 0 11073 #define DDR34_E0_PHY_BYTE_LANE_1_ODT_CONTROL_RESERVED1_BITS 21 11074 #define DDR34_E0_PHY_BYTE_LANE_1_ODT_CONTROL_RESERVED1_SHIFT 10 11075 11076 /* DDR34_E0_PHY_BYTE_LANE_1 :: ODT_CONTROL :: ODT_ENABLE [09:09] */ 11077 #define DDR34_E0_PHY_BYTE_LANE_1_ODT_CONTROL_ODT_ENABLE_MASK 0x00000200 11078 #define DDR34_E0_PHY_BYTE_LANE_1_ODT_CONTROL_ODT_ENABLE_ALIGN 0 11079 #define DDR34_E0_PHY_BYTE_LANE_1_ODT_CONTROL_ODT_ENABLE_BITS 1 11080 #define DDR34_E0_PHY_BYTE_LANE_1_ODT_CONTROL_ODT_ENABLE_SHIFT 9 11081 #define DDR34_E0_PHY_BYTE_LANE_1_ODT_CONTROL_ODT_ENABLE_DEFAULT 0x00000001 11082 11083 /* DDR34_E0_PHY_BYTE_LANE_1 :: ODT_CONTROL :: ODT_DELAY [08:06] */ 11084 #define DDR34_E0_PHY_BYTE_LANE_1_ODT_CONTROL_ODT_DELAY_MASK 0x000001c0 11085 #define DDR34_E0_PHY_BYTE_LANE_1_ODT_CONTROL_ODT_DELAY_ALIGN 0 11086 #define DDR34_E0_PHY_BYTE_LANE_1_ODT_CONTROL_ODT_DELAY_BITS 3 11087 #define DDR34_E0_PHY_BYTE_LANE_1_ODT_CONTROL_ODT_DELAY_SHIFT 6 11088 #define DDR34_E0_PHY_BYTE_LANE_1_ODT_CONTROL_ODT_DELAY_DEFAULT 0x00000000 11089 11090 /* DDR34_E0_PHY_BYTE_LANE_1 :: ODT_CONTROL :: ODT_POST_LENGTH [05:03] */ 11091 #define DDR34_E0_PHY_BYTE_LANE_1_ODT_CONTROL_ODT_POST_LENGTH_MASK 0x00000038 11092 #define DDR34_E0_PHY_BYTE_LANE_1_ODT_CONTROL_ODT_POST_LENGTH_ALIGN 0 11093 #define DDR34_E0_PHY_BYTE_LANE_1_ODT_CONTROL_ODT_POST_LENGTH_BITS 3 11094 #define DDR34_E0_PHY_BYTE_LANE_1_ODT_CONTROL_ODT_POST_LENGTH_SHIFT 3 11095 #define DDR34_E0_PHY_BYTE_LANE_1_ODT_CONTROL_ODT_POST_LENGTH_DEFAULT 0x00000001 11096 11097 /* DDR34_E0_PHY_BYTE_LANE_1 :: ODT_CONTROL :: ODT_PRE_LENGTH [02:00] */ 11098 #define DDR34_E0_PHY_BYTE_LANE_1_ODT_CONTROL_ODT_PRE_LENGTH_MASK 0x00000007 11099 #define DDR34_E0_PHY_BYTE_LANE_1_ODT_CONTROL_ODT_PRE_LENGTH_ALIGN 0 11100 #define DDR34_E0_PHY_BYTE_LANE_1_ODT_CONTROL_ODT_PRE_LENGTH_BITS 3 11101 #define DDR34_E0_PHY_BYTE_LANE_1_ODT_CONTROL_ODT_PRE_LENGTH_SHIFT 0 11102 #define DDR34_E0_PHY_BYTE_LANE_1_ODT_CONTROL_ODT_PRE_LENGTH_DEFAULT 0x00000003 11103 11104 /*************************************************************************** 11105 *EDC_DPD_CONTROL - GDDR5M EDC digital phase detector control register 11106 */ 11107 /* DDR34_E0_PHY_BYTE_LANE_1 :: EDC_DPD_CONTROL :: reserved0 [31:06] */ 11108 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_DPD_CONTROL_RESERVED0_MASK 0xffffffc0 11109 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_DPD_CONTROL_RESERVED0_ALIGN 0 11110 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_DPD_CONTROL_RESERVED0_BITS 26 11111 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_DPD_CONTROL_RESERVED0_SHIFT 6 11112 11113 /* DDR34_E0_PHY_BYTE_LANE_1 :: EDC_DPD_CONTROL :: DQS_PHASE_OVERRIDE_VALUE [05:05] */ 11114 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_VALUE_MASK 0x00000020 11115 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_VALUE_ALIGN 0 11116 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_VALUE_BITS 1 11117 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_VALUE_SHIFT 5 11118 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_VALUE_DEFAULT 0x00000000 11119 11120 /* DDR34_E0_PHY_BYTE_LANE_1 :: EDC_DPD_CONTROL :: DQS_PHASE_OVERRIDE_ENABLE [04:04] */ 11121 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_ENABLE_MASK 0x00000010 11122 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_ENABLE_ALIGN 0 11123 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_ENABLE_BITS 1 11124 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_ENABLE_SHIFT 4 11125 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_ENABLE_DEFAULT 0x00000000 11126 11127 /* DDR34_E0_PHY_BYTE_LANE_1 :: EDC_DPD_CONTROL :: SET_ADJ_EN [03:03] */ 11128 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_DPD_CONTROL_SET_ADJ_EN_MASK 0x00000008 11129 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_DPD_CONTROL_SET_ADJ_EN_ALIGN 0 11130 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_DPD_CONTROL_SET_ADJ_EN_BITS 1 11131 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_DPD_CONTROL_SET_ADJ_EN_SHIFT 3 11132 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_DPD_CONTROL_SET_ADJ_EN_DEFAULT 0x00000000 11133 11134 /* DDR34_E0_PHY_BYTE_LANE_1 :: EDC_DPD_CONTROL :: UPDATE [02:02] */ 11135 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_DPD_CONTROL_UPDATE_MASK 0x00000004 11136 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_DPD_CONTROL_UPDATE_ALIGN 0 11137 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_DPD_CONTROL_UPDATE_BITS 1 11138 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_DPD_CONTROL_UPDATE_SHIFT 2 11139 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_DPD_CONTROL_UPDATE_DEFAULT 0x00000000 11140 11141 /* DDR34_E0_PHY_BYTE_LANE_1 :: EDC_DPD_CONTROL :: MONITOR [01:01] */ 11142 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_DPD_CONTROL_MONITOR_MASK 0x00000002 11143 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_DPD_CONTROL_MONITOR_ALIGN 0 11144 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_DPD_CONTROL_MONITOR_BITS 1 11145 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_DPD_CONTROL_MONITOR_SHIFT 1 11146 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_DPD_CONTROL_MONITOR_DEFAULT 0x00000000 11147 11148 /* DDR34_E0_PHY_BYTE_LANE_1 :: EDC_DPD_CONTROL :: INIT [00:00] */ 11149 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_DPD_CONTROL_INIT_MASK 0x00000001 11150 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_DPD_CONTROL_INIT_ALIGN 0 11151 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_DPD_CONTROL_INIT_BITS 1 11152 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_DPD_CONTROL_INIT_SHIFT 0 11153 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_DPD_CONTROL_INIT_DEFAULT 0x00000000 11154 11155 /*************************************************************************** 11156 *EDC_DPD_STATUS - GDDR5M EDC digital phase detector status register 11157 */ 11158 /* DDR34_E0_PHY_BYTE_LANE_1 :: EDC_DPD_STATUS :: reserved0 [31:25] */ 11159 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_DPD_STATUS_RESERVED0_MASK 0xfe000000 11160 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_DPD_STATUS_RESERVED0_ALIGN 0 11161 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_DPD_STATUS_RESERVED0_BITS 7 11162 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_DPD_STATUS_RESERVED0_SHIFT 25 11163 11164 /* DDR34_E0_PHY_BYTE_LANE_1 :: EDC_DPD_STATUS :: CURRENT_DQS_PHASE [24:24] */ 11165 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_DPD_STATUS_CURRENT_DQS_PHASE_MASK 0x01000000 11166 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_DPD_STATUS_CURRENT_DQS_PHASE_ALIGN 0 11167 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_DPD_STATUS_CURRENT_DQS_PHASE_BITS 1 11168 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_DPD_STATUS_CURRENT_DQS_PHASE_SHIFT 24 11169 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_DPD_STATUS_CURRENT_DQS_PHASE_DEFAULT 0x00000000 11170 11171 /* DDR34_E0_PHY_BYTE_LANE_1 :: EDC_DPD_STATUS :: CURRENT_VDL_SETTING [23:16] */ 11172 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_DPD_STATUS_CURRENT_VDL_SETTING_MASK 0x00ff0000 11173 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_DPD_STATUS_CURRENT_VDL_SETTING_ALIGN 0 11174 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_DPD_STATUS_CURRENT_VDL_SETTING_BITS 8 11175 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_DPD_STATUS_CURRENT_VDL_SETTING_SHIFT 16 11176 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_DPD_STATUS_CURRENT_VDL_SETTING_DEFAULT 0x00000000 11177 11178 /* DDR34_E0_PHY_BYTE_LANE_1 :: EDC_DPD_STATUS :: reserved1 [15:13] */ 11179 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_DPD_STATUS_RESERVED1_MASK 0x0000e000 11180 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_DPD_STATUS_RESERVED1_ALIGN 0 11181 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_DPD_STATUS_RESERVED1_BITS 3 11182 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_DPD_STATUS_RESERVED1_SHIFT 13 11183 11184 /* DDR34_E0_PHY_BYTE_LANE_1 :: EDC_DPD_STATUS :: INIT_DQS_PHASE [12:12] */ 11185 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_DPD_STATUS_INIT_DQS_PHASE_MASK 0x00001000 11186 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_DPD_STATUS_INIT_DQS_PHASE_ALIGN 0 11187 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_DPD_STATUS_INIT_DQS_PHASE_BITS 1 11188 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_DPD_STATUS_INIT_DQS_PHASE_SHIFT 12 11189 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_DPD_STATUS_INIT_DQS_PHASE_DEFAULT 0x00000000 11190 11191 /* DDR34_E0_PHY_BYTE_LANE_1 :: EDC_DPD_STATUS :: INIT_VDL_SETTING [11:04] */ 11192 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_DPD_STATUS_INIT_VDL_SETTING_MASK 0x00000ff0 11193 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_DPD_STATUS_INIT_VDL_SETTING_ALIGN 0 11194 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_DPD_STATUS_INIT_VDL_SETTING_BITS 8 11195 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_DPD_STATUS_INIT_VDL_SETTING_SHIFT 4 11196 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_DPD_STATUS_INIT_VDL_SETTING_DEFAULT 0x00000000 11197 11198 /* DDR34_E0_PHY_BYTE_LANE_1 :: EDC_DPD_STATUS :: EDGE_ERROR [03:03] */ 11199 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_DPD_STATUS_EDGE_ERROR_MASK 0x00000008 11200 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_DPD_STATUS_EDGE_ERROR_ALIGN 0 11201 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_DPD_STATUS_EDGE_ERROR_BITS 1 11202 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_DPD_STATUS_EDGE_ERROR_SHIFT 3 11203 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_DPD_STATUS_EDGE_ERROR_DEFAULT 0x00000000 11204 11205 /* DDR34_E0_PHY_BYTE_LANE_1 :: EDC_DPD_STATUS :: MONITOR_BUSY [02:02] */ 11206 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_DPD_STATUS_MONITOR_BUSY_MASK 0x00000004 11207 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_DPD_STATUS_MONITOR_BUSY_ALIGN 0 11208 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_DPD_STATUS_MONITOR_BUSY_BITS 1 11209 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_DPD_STATUS_MONITOR_BUSY_SHIFT 2 11210 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_DPD_STATUS_MONITOR_BUSY_DEFAULT 0x00000000 11211 11212 /* DDR34_E0_PHY_BYTE_LANE_1 :: EDC_DPD_STATUS :: INIT_BUSY [01:01] */ 11213 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_DPD_STATUS_INIT_BUSY_MASK 0x00000002 11214 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_DPD_STATUS_INIT_BUSY_ALIGN 0 11215 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_DPD_STATUS_INIT_BUSY_BITS 1 11216 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_DPD_STATUS_INIT_BUSY_SHIFT 1 11217 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_DPD_STATUS_INIT_BUSY_DEFAULT 0x00000000 11218 11219 /* DDR34_E0_PHY_BYTE_LANE_1 :: EDC_DPD_STATUS :: INIT_DONE [00:00] */ 11220 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_DPD_STATUS_INIT_DONE_MASK 0x00000001 11221 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_DPD_STATUS_INIT_DONE_ALIGN 0 11222 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_DPD_STATUS_INIT_DONE_BITS 1 11223 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_DPD_STATUS_INIT_DONE_SHIFT 0 11224 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_DPD_STATUS_INIT_DONE_DEFAULT 0x00000000 11225 11226 /*************************************************************************** 11227 *EDC_DPD_OUT_CONTROL - GDDR5M EDC digital phase detector output signal control register 11228 */ 11229 /* DDR34_E0_PHY_BYTE_LANE_1 :: EDC_DPD_OUT_CONTROL :: reserved0 [31:20] */ 11230 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_DPD_OUT_CONTROL_RESERVED0_MASK 0xfff00000 11231 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_DPD_OUT_CONTROL_RESERVED0_ALIGN 0 11232 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_DPD_OUT_CONTROL_RESERVED0_BITS 12 11233 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_DPD_OUT_CONTROL_RESERVED0_SHIFT 20 11234 11235 /* DDR34_E0_PHY_BYTE_LANE_1 :: EDC_DPD_OUT_CONTROL :: LOWER_LIMIT [19:12] */ 11236 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_DPD_OUT_CONTROL_LOWER_LIMIT_MASK 0x000ff000 11237 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_DPD_OUT_CONTROL_LOWER_LIMIT_ALIGN 0 11238 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_DPD_OUT_CONTROL_LOWER_LIMIT_BITS 8 11239 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_DPD_OUT_CONTROL_LOWER_LIMIT_SHIFT 12 11240 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_DPD_OUT_CONTROL_LOWER_LIMIT_DEFAULT 0x00000000 11241 11242 /* DDR34_E0_PHY_BYTE_LANE_1 :: EDC_DPD_OUT_CONTROL :: UPPER_LIMIT [11:04] */ 11243 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_DPD_OUT_CONTROL_UPPER_LIMIT_MASK 0x00000ff0 11244 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_DPD_OUT_CONTROL_UPPER_LIMIT_ALIGN 0 11245 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_DPD_OUT_CONTROL_UPPER_LIMIT_BITS 8 11246 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_DPD_OUT_CONTROL_UPPER_LIMIT_SHIFT 4 11247 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_DPD_OUT_CONTROL_UPPER_LIMIT_DEFAULT 0x00000000 11248 11249 /* DDR34_E0_PHY_BYTE_LANE_1 :: EDC_DPD_OUT_CONTROL :: reserved1 [03:01] */ 11250 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_DPD_OUT_CONTROL_RESERVED1_MASK 0x0000000e 11251 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_DPD_OUT_CONTROL_RESERVED1_ALIGN 0 11252 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_DPD_OUT_CONTROL_RESERVED1_BITS 3 11253 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_DPD_OUT_CONTROL_RESERVED1_SHIFT 1 11254 11255 /* DDR34_E0_PHY_BYTE_LANE_1 :: EDC_DPD_OUT_CONTROL :: ENABLE [00:00] */ 11256 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_DPD_OUT_CONTROL_ENABLE_MASK 0x00000001 11257 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_DPD_OUT_CONTROL_ENABLE_ALIGN 0 11258 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_DPD_OUT_CONTROL_ENABLE_BITS 1 11259 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_DPD_OUT_CONTROL_ENABLE_SHIFT 0 11260 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_DPD_OUT_CONTROL_ENABLE_DEFAULT 0x00000000 11261 11262 /*************************************************************************** 11263 *EDC_DPD_OUT_STATUS - GDDR5M EDC digital phase detector output signal status register 11264 */ 11265 /* DDR34_E0_PHY_BYTE_LANE_1 :: EDC_DPD_OUT_STATUS :: reserved0 [31:12] */ 11266 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_DPD_OUT_STATUS_RESERVED0_MASK 0xfffff000 11267 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_DPD_OUT_STATUS_RESERVED0_ALIGN 0 11268 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_DPD_OUT_STATUS_RESERVED0_BITS 20 11269 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_DPD_OUT_STATUS_RESERVED0_SHIFT 12 11270 11271 /* DDR34_E0_PHY_BYTE_LANE_1 :: EDC_DPD_OUT_STATUS :: VDL_SETTING [11:04] */ 11272 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_DPD_OUT_STATUS_VDL_SETTING_MASK 0x00000ff0 11273 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_DPD_OUT_STATUS_VDL_SETTING_ALIGN 0 11274 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_DPD_OUT_STATUS_VDL_SETTING_BITS 8 11275 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_DPD_OUT_STATUS_VDL_SETTING_SHIFT 4 11276 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_DPD_OUT_STATUS_VDL_SETTING_DEFAULT 0x00000000 11277 11278 /* DDR34_E0_PHY_BYTE_LANE_1 :: EDC_DPD_OUT_STATUS :: reserved1 [03:01] */ 11279 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_DPD_OUT_STATUS_RESERVED1_MASK 0x0000000e 11280 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_DPD_OUT_STATUS_RESERVED1_ALIGN 0 11281 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_DPD_OUT_STATUS_RESERVED1_BITS 3 11282 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_DPD_OUT_STATUS_RESERVED1_SHIFT 1 11283 11284 /* DDR34_E0_PHY_BYTE_LANE_1 :: EDC_DPD_OUT_STATUS :: VALID [00:00] */ 11285 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_DPD_OUT_STATUS_VALID_MASK 0x00000001 11286 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_DPD_OUT_STATUS_VALID_ALIGN 0 11287 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_DPD_OUT_STATUS_VALID_BITS 1 11288 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_DPD_OUT_STATUS_VALID_SHIFT 0 11289 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_DPD_OUT_STATUS_VALID_DEFAULT 0x00000000 11290 11291 /*************************************************************************** 11292 *EDC_DPD_OUT_STATUS_CLEAR - GDDR5M EDC digital phase detector output signal status clear register 11293 */ 11294 /* DDR34_E0_PHY_BYTE_LANE_1 :: EDC_DPD_OUT_STATUS_CLEAR :: reserved0 [31:01] */ 11295 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_DPD_OUT_STATUS_CLEAR_RESERVED0_MASK 0xfffffffe 11296 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_DPD_OUT_STATUS_CLEAR_RESERVED0_ALIGN 0 11297 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_DPD_OUT_STATUS_CLEAR_RESERVED0_BITS 31 11298 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_DPD_OUT_STATUS_CLEAR_RESERVED0_SHIFT 1 11299 11300 /* DDR34_E0_PHY_BYTE_LANE_1 :: EDC_DPD_OUT_STATUS_CLEAR :: CLEAR [00:00] */ 11301 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_DPD_OUT_STATUS_CLEAR_CLEAR_MASK 0x00000001 11302 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_DPD_OUT_STATUS_CLEAR_CLEAR_ALIGN 0 11303 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_DPD_OUT_STATUS_CLEAR_CLEAR_BITS 1 11304 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_DPD_OUT_STATUS_CLEAR_CLEAR_SHIFT 0 11305 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_DPD_OUT_STATUS_CLEAR_CLEAR_DEFAULT 0x00000000 11306 11307 /*************************************************************************** 11308 *EDC_CRC_CONTROL - GDDR5M EDC signal path CRC control register 11309 */ 11310 /* DDR34_E0_PHY_BYTE_LANE_1 :: EDC_CRC_CONTROL :: BUSY [31:31] */ 11311 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_CRC_CONTROL_BUSY_MASK 0x80000000 11312 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_CRC_CONTROL_BUSY_ALIGN 0 11313 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_CRC_CONTROL_BUSY_BITS 1 11314 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_CRC_CONTROL_BUSY_SHIFT 31 11315 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_CRC_CONTROL_BUSY_DEFAULT 0x00000000 11316 11317 /* DDR34_E0_PHY_BYTE_LANE_1 :: EDC_CRC_CONTROL :: reserved0 [30:17] */ 11318 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_CRC_CONTROL_RESERVED0_MASK 0x7ffe0000 11319 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_CRC_CONTROL_RESERVED0_ALIGN 0 11320 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_CRC_CONTROL_RESERVED0_BITS 14 11321 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_CRC_CONTROL_RESERVED0_SHIFT 17 11322 11323 /* DDR34_E0_PHY_BYTE_LANE_1 :: EDC_CRC_CONTROL :: FORCE [16:16] */ 11324 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_CRC_CONTROL_FORCE_MASK 0x00010000 11325 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_CRC_CONTROL_FORCE_ALIGN 0 11326 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_CRC_CONTROL_FORCE_BITS 1 11327 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_CRC_CONTROL_FORCE_SHIFT 16 11328 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_CRC_CONTROL_FORCE_DEFAULT 0x00000000 11329 11330 /* DDR34_E0_PHY_BYTE_LANE_1 :: EDC_CRC_CONTROL :: reserved1 [15:11] */ 11331 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_CRC_CONTROL_RESERVED1_MASK 0x0000f800 11332 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_CRC_CONTROL_RESERVED1_ALIGN 0 11333 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_CRC_CONTROL_RESERVED1_BITS 5 11334 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_CRC_CONTROL_RESERVED1_SHIFT 11 11335 11336 /* DDR34_E0_PHY_BYTE_LANE_1 :: EDC_CRC_CONTROL :: CRCWL [10:08] */ 11337 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_CRC_CONTROL_CRCWL_MASK 0x00000700 11338 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_CRC_CONTROL_CRCWL_ALIGN 0 11339 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_CRC_CONTROL_CRCWL_BITS 3 11340 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_CRC_CONTROL_CRCWL_SHIFT 8 11341 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_CRC_CONTROL_CRCWL_DEFAULT 0x00000000 11342 11343 /* DDR34_E0_PHY_BYTE_LANE_1 :: EDC_CRC_CONTROL :: reserved2 [07:06] */ 11344 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_CRC_CONTROL_RESERVED2_MASK 0x000000c0 11345 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_CRC_CONTROL_RESERVED2_ALIGN 0 11346 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_CRC_CONTROL_RESERVED2_BITS 2 11347 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_CRC_CONTROL_RESERVED2_SHIFT 6 11348 11349 /* DDR34_E0_PHY_BYTE_LANE_1 :: EDC_CRC_CONTROL :: CRCRL [05:04] */ 11350 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_CRC_CONTROL_CRCRL_MASK 0x00000030 11351 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_CRC_CONTROL_CRCRL_ALIGN 0 11352 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_CRC_CONTROL_CRCRL_BITS 2 11353 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_CRC_CONTROL_CRCRL_SHIFT 4 11354 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_CRC_CONTROL_CRCRL_DEFAULT 0x00000000 11355 11356 /* DDR34_E0_PHY_BYTE_LANE_1 :: EDC_CRC_CONTROL :: reserved3 [03:03] */ 11357 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_CRC_CONTROL_RESERVED3_MASK 0x00000008 11358 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_CRC_CONTROL_RESERVED3_ALIGN 0 11359 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_CRC_CONTROL_RESERVED3_BITS 1 11360 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_CRC_CONTROL_RESERVED3_SHIFT 3 11361 11362 /* DDR34_E0_PHY_BYTE_LANE_1 :: EDC_CRC_CONTROL :: COUNT_MODE [02:02] */ 11363 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_CRC_CONTROL_COUNT_MODE_MASK 0x00000004 11364 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_CRC_CONTROL_COUNT_MODE_ALIGN 0 11365 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_CRC_CONTROL_COUNT_MODE_BITS 1 11366 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_CRC_CONTROL_COUNT_MODE_SHIFT 2 11367 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_CRC_CONTROL_COUNT_MODE_DEFAULT 0x00000000 11368 11369 /* DDR34_E0_PHY_BYTE_LANE_1 :: EDC_CRC_CONTROL :: ENABLE_WR [01:01] */ 11370 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_CRC_CONTROL_ENABLE_WR_MASK 0x00000002 11371 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_CRC_CONTROL_ENABLE_WR_ALIGN 0 11372 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_CRC_CONTROL_ENABLE_WR_BITS 1 11373 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_CRC_CONTROL_ENABLE_WR_SHIFT 1 11374 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_CRC_CONTROL_ENABLE_WR_DEFAULT 0x00000000 11375 11376 /* DDR34_E0_PHY_BYTE_LANE_1 :: EDC_CRC_CONTROL :: ENABLE_RD [00:00] */ 11377 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_CRC_CONTROL_ENABLE_RD_MASK 0x00000001 11378 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_CRC_CONTROL_ENABLE_RD_ALIGN 0 11379 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_CRC_CONTROL_ENABLE_RD_BITS 1 11380 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_CRC_CONTROL_ENABLE_RD_SHIFT 0 11381 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_CRC_CONTROL_ENABLE_RD_DEFAULT 0x00000000 11382 11383 /*************************************************************************** 11384 *EDC_CRC_STATUS - GDDR5M EDC signal path CRC status register 11385 */ 11386 /* DDR34_E0_PHY_BYTE_LANE_1 :: EDC_CRC_STATUS :: reserved0 [31:04] */ 11387 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_CRC_STATUS_RESERVED0_MASK 0xfffffff0 11388 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_CRC_STATUS_RESERVED0_ALIGN 0 11389 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_CRC_STATUS_RESERVED0_BITS 28 11390 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_CRC_STATUS_RESERVED0_SHIFT 4 11391 11392 /* DDR34_E0_PHY_BYTE_LANE_1 :: EDC_CRC_STATUS :: WR_FAIL [03:03] */ 11393 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_CRC_STATUS_WR_FAIL_MASK 0x00000008 11394 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_CRC_STATUS_WR_FAIL_ALIGN 0 11395 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_CRC_STATUS_WR_FAIL_BITS 1 11396 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_CRC_STATUS_WR_FAIL_SHIFT 3 11397 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_CRC_STATUS_WR_FAIL_DEFAULT 0x00000000 11398 11399 /* DDR34_E0_PHY_BYTE_LANE_1 :: EDC_CRC_STATUS :: WR_PASS [02:02] */ 11400 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_CRC_STATUS_WR_PASS_MASK 0x00000004 11401 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_CRC_STATUS_WR_PASS_ALIGN 0 11402 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_CRC_STATUS_WR_PASS_BITS 1 11403 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_CRC_STATUS_WR_PASS_SHIFT 2 11404 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_CRC_STATUS_WR_PASS_DEFAULT 0x00000000 11405 11406 /* DDR34_E0_PHY_BYTE_LANE_1 :: EDC_CRC_STATUS :: RD_FAIL [01:01] */ 11407 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_CRC_STATUS_RD_FAIL_MASK 0x00000002 11408 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_CRC_STATUS_RD_FAIL_ALIGN 0 11409 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_CRC_STATUS_RD_FAIL_BITS 1 11410 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_CRC_STATUS_RD_FAIL_SHIFT 1 11411 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_CRC_STATUS_RD_FAIL_DEFAULT 0x00000000 11412 11413 /* DDR34_E0_PHY_BYTE_LANE_1 :: EDC_CRC_STATUS :: RD_PASS [00:00] */ 11414 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_CRC_STATUS_RD_PASS_MASK 0x00000001 11415 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_CRC_STATUS_RD_PASS_ALIGN 0 11416 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_CRC_STATUS_RD_PASS_BITS 1 11417 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_CRC_STATUS_RD_PASS_SHIFT 0 11418 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_CRC_STATUS_RD_PASS_DEFAULT 0x00000000 11419 11420 /*************************************************************************** 11421 *EDC_CRC_COUNT - GDDR5M EDC signal path CRC counter register 11422 */ 11423 /* DDR34_E0_PHY_BYTE_LANE_1 :: EDC_CRC_COUNT :: reserved0 [31:28] */ 11424 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_CRC_COUNT_RESERVED0_MASK 0xf0000000 11425 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_CRC_COUNT_RESERVED0_ALIGN 0 11426 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_CRC_COUNT_RESERVED0_BITS 4 11427 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_CRC_COUNT_RESERVED0_SHIFT 28 11428 11429 /* DDR34_E0_PHY_BYTE_LANE_1 :: EDC_CRC_COUNT :: WR_COUNT [27:16] */ 11430 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_CRC_COUNT_WR_COUNT_MASK 0x0fff0000 11431 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_CRC_COUNT_WR_COUNT_ALIGN 0 11432 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_CRC_COUNT_WR_COUNT_BITS 12 11433 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_CRC_COUNT_WR_COUNT_SHIFT 16 11434 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_CRC_COUNT_WR_COUNT_DEFAULT 0x00000000 11435 11436 /* DDR34_E0_PHY_BYTE_LANE_1 :: EDC_CRC_COUNT :: reserved1 [15:12] */ 11437 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_CRC_COUNT_RESERVED1_MASK 0x0000f000 11438 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_CRC_COUNT_RESERVED1_ALIGN 0 11439 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_CRC_COUNT_RESERVED1_BITS 4 11440 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_CRC_COUNT_RESERVED1_SHIFT 12 11441 11442 /* DDR34_E0_PHY_BYTE_LANE_1 :: EDC_CRC_COUNT :: RD_COUNT [11:00] */ 11443 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_CRC_COUNT_RD_COUNT_MASK 0x00000fff 11444 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_CRC_COUNT_RD_COUNT_ALIGN 0 11445 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_CRC_COUNT_RD_COUNT_BITS 12 11446 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_CRC_COUNT_RD_COUNT_SHIFT 0 11447 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_CRC_COUNT_RD_COUNT_DEFAULT 0x00000000 11448 11449 /*************************************************************************** 11450 *EDC_CRC_STATUS_CLEAR - GDDR5M EDC signal path CRC counter register 11451 */ 11452 /* DDR34_E0_PHY_BYTE_LANE_1 :: EDC_CRC_STATUS_CLEAR :: reserved0 [31:01] */ 11453 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_CRC_STATUS_CLEAR_RESERVED0_MASK 0xfffffffe 11454 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_CRC_STATUS_CLEAR_RESERVED0_ALIGN 0 11455 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_CRC_STATUS_CLEAR_RESERVED0_BITS 31 11456 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_CRC_STATUS_CLEAR_RESERVED0_SHIFT 1 11457 11458 /* DDR34_E0_PHY_BYTE_LANE_1 :: EDC_CRC_STATUS_CLEAR :: CLEAR [00:00] */ 11459 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_CRC_STATUS_CLEAR_CLEAR_MASK 0x00000001 11460 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_CRC_STATUS_CLEAR_CLEAR_ALIGN 0 11461 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_CRC_STATUS_CLEAR_CLEAR_BITS 1 11462 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_CRC_STATUS_CLEAR_CLEAR_SHIFT 0 11463 #define DDR34_E0_PHY_BYTE_LANE_1_EDC_CRC_STATUS_CLEAR_CLEAR_DEFAULT 0x00000000 11464 11465 /*************************************************************************** 11466 *BL_SPARE_REG - Byte-Lane Spare register 11467 */ 11468 /* DDR34_E0_PHY_BYTE_LANE_1 :: BL_SPARE_REG :: reserved_for_eco0 [31:00] */ 11469 #define DDR34_E0_PHY_BYTE_LANE_1_BL_SPARE_REG_RESERVED_for_eco0_MASK 0xffffffff 11470 #define DDR34_E0_PHY_BYTE_LANE_1_BL_SPARE_REG_RESERVED_for_eco0_ALIGN 0 11471 #define DDR34_E0_PHY_BYTE_LANE_1_BL_SPARE_REG_RESERVED_for_eco0_BITS 32 11472 #define DDR34_E0_PHY_BYTE_LANE_1_BL_SPARE_REG_RESERVED_for_eco0_SHIFT 0 11473 #define DDR34_E0_PHY_BYTE_LANE_1_BL_SPARE_REG_RESERVED_for_eco0_DEFAULT 0x00000000 11474 11475 /*************************************************************************** 11476 *VDL_CONTROL_WR_DQS_P - Write channel DQS-P VDL control register 11477 */ 11478 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DQS_P :: BUSY [31:31] */ 11479 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_P_BUSY_MASK 0x80000000 11480 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_P_BUSY_ALIGN 0 11481 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_P_BUSY_BITS 1 11482 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_P_BUSY_SHIFT 31 11483 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_P_BUSY_DEFAULT 0x00000000 11484 11485 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DQS_P :: reserved0 [30:17] */ 11486 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_P_RESERVED0_MASK 0x7ffe0000 11487 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_P_RESERVED0_ALIGN 0 11488 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_P_RESERVED0_BITS 14 11489 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_P_RESERVED0_SHIFT 17 11490 11491 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DQS_P :: FORCE [16:16] */ 11492 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_P_FORCE_MASK 0x00010000 11493 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_P_FORCE_ALIGN 0 11494 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_P_FORCE_BITS 1 11495 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_P_FORCE_SHIFT 16 11496 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_P_FORCE_DEFAULT 0x00000000 11497 11498 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DQS_P :: reserved1 [15:13] */ 11499 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_P_RESERVED1_MASK 0x0000e000 11500 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_P_RESERVED1_ALIGN 0 11501 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_P_RESERVED1_BITS 3 11502 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_P_RESERVED1_SHIFT 13 11503 11504 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DQS_P :: ADJ_EN [12:12] */ 11505 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_P_ADJ_EN_MASK 0x00001000 11506 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_P_ADJ_EN_ALIGN 0 11507 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_P_ADJ_EN_BITS 1 11508 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_P_ADJ_EN_SHIFT 12 11509 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_P_ADJ_EN_DEFAULT 0x00000000 11510 11511 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DQS_P :: reserved2 [11:09] */ 11512 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_P_RESERVED2_MASK 0x00000e00 11513 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_P_RESERVED2_ALIGN 0 11514 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_P_RESERVED2_BITS 3 11515 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_P_RESERVED2_SHIFT 9 11516 11517 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DQS_P :: VDL_STEP [08:00] */ 11518 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_P_VDL_STEP_MASK 0x000001ff 11519 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_P_VDL_STEP_ALIGN 0 11520 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_P_VDL_STEP_BITS 9 11521 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_P_VDL_STEP_SHIFT 0 11522 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_P_VDL_STEP_DEFAULT 0x00000000 11523 11524 /*************************************************************************** 11525 *VDL_CONTROL_WR_DQS_N - Write channel DQS-N VDL control register 11526 */ 11527 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DQS_N :: BUSY [31:31] */ 11528 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_N_BUSY_MASK 0x80000000 11529 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_N_BUSY_ALIGN 0 11530 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_N_BUSY_BITS 1 11531 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_N_BUSY_SHIFT 31 11532 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_N_BUSY_DEFAULT 0x00000000 11533 11534 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DQS_N :: reserved0 [30:17] */ 11535 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_N_RESERVED0_MASK 0x7ffe0000 11536 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_N_RESERVED0_ALIGN 0 11537 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_N_RESERVED0_BITS 14 11538 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_N_RESERVED0_SHIFT 17 11539 11540 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DQS_N :: FORCE [16:16] */ 11541 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_N_FORCE_MASK 0x00010000 11542 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_N_FORCE_ALIGN 0 11543 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_N_FORCE_BITS 1 11544 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_N_FORCE_SHIFT 16 11545 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_N_FORCE_DEFAULT 0x00000000 11546 11547 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DQS_N :: reserved1 [15:13] */ 11548 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_N_RESERVED1_MASK 0x0000e000 11549 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_N_RESERVED1_ALIGN 0 11550 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_N_RESERVED1_BITS 3 11551 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_N_RESERVED1_SHIFT 13 11552 11553 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DQS_N :: ADJ_EN [12:12] */ 11554 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_N_ADJ_EN_MASK 0x00001000 11555 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_N_ADJ_EN_ALIGN 0 11556 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_N_ADJ_EN_BITS 1 11557 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_N_ADJ_EN_SHIFT 12 11558 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_N_ADJ_EN_DEFAULT 0x00000000 11559 11560 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DQS_N :: reserved2 [11:09] */ 11561 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_N_RESERVED2_MASK 0x00000e00 11562 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_N_RESERVED2_ALIGN 0 11563 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_N_RESERVED2_BITS 3 11564 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_N_RESERVED2_SHIFT 9 11565 11566 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DQS_N :: VDL_STEP [08:00] */ 11567 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_N_VDL_STEP_MASK 0x000001ff 11568 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_N_VDL_STEP_ALIGN 0 11569 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_N_VDL_STEP_BITS 9 11570 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_N_VDL_STEP_SHIFT 0 11571 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_N_VDL_STEP_DEFAULT 0x00000000 11572 11573 /*************************************************************************** 11574 *VDL_CONTROL_WR_DQ0 - Write channel DQ0 VDL control register 11575 */ 11576 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DQ0 :: BUSY [31:31] */ 11577 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ0_BUSY_MASK 0x80000000 11578 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ0_BUSY_ALIGN 0 11579 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ0_BUSY_BITS 1 11580 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ0_BUSY_SHIFT 31 11581 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ0_BUSY_DEFAULT 0x00000000 11582 11583 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DQ0 :: reserved0 [30:17] */ 11584 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ0_RESERVED0_MASK 0x7ffe0000 11585 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ0_RESERVED0_ALIGN 0 11586 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ0_RESERVED0_BITS 14 11587 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ0_RESERVED0_SHIFT 17 11588 11589 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DQ0 :: FORCE [16:16] */ 11590 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ0_FORCE_MASK 0x00010000 11591 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ0_FORCE_ALIGN 0 11592 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ0_FORCE_BITS 1 11593 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ0_FORCE_SHIFT 16 11594 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ0_FORCE_DEFAULT 0x00000000 11595 11596 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DQ0 :: reserved1 [15:13] */ 11597 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ0_RESERVED1_MASK 0x0000e000 11598 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ0_RESERVED1_ALIGN 0 11599 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ0_RESERVED1_BITS 3 11600 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ0_RESERVED1_SHIFT 13 11601 11602 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DQ0 :: ADJ_EN [12:12] */ 11603 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ0_ADJ_EN_MASK 0x00001000 11604 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ0_ADJ_EN_ALIGN 0 11605 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ0_ADJ_EN_BITS 1 11606 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ0_ADJ_EN_SHIFT 12 11607 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ0_ADJ_EN_DEFAULT 0x00000000 11608 11609 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DQ0 :: reserved2 [11:09] */ 11610 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ0_RESERVED2_MASK 0x00000e00 11611 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ0_RESERVED2_ALIGN 0 11612 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ0_RESERVED2_BITS 3 11613 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ0_RESERVED2_SHIFT 9 11614 11615 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DQ0 :: VDL_STEP [08:00] */ 11616 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ0_VDL_STEP_MASK 0x000001ff 11617 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ0_VDL_STEP_ALIGN 0 11618 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ0_VDL_STEP_BITS 9 11619 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ0_VDL_STEP_SHIFT 0 11620 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ0_VDL_STEP_DEFAULT 0x00000000 11621 11622 /*************************************************************************** 11623 *VDL_CONTROL_WR_DQ1 - Write channel DQ1 VDL control register 11624 */ 11625 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DQ1 :: BUSY [31:31] */ 11626 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ1_BUSY_MASK 0x80000000 11627 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ1_BUSY_ALIGN 0 11628 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ1_BUSY_BITS 1 11629 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ1_BUSY_SHIFT 31 11630 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ1_BUSY_DEFAULT 0x00000000 11631 11632 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DQ1 :: reserved0 [30:17] */ 11633 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ1_RESERVED0_MASK 0x7ffe0000 11634 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ1_RESERVED0_ALIGN 0 11635 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ1_RESERVED0_BITS 14 11636 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ1_RESERVED0_SHIFT 17 11637 11638 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DQ1 :: FORCE [16:16] */ 11639 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ1_FORCE_MASK 0x00010000 11640 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ1_FORCE_ALIGN 0 11641 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ1_FORCE_BITS 1 11642 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ1_FORCE_SHIFT 16 11643 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ1_FORCE_DEFAULT 0x00000000 11644 11645 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DQ1 :: reserved1 [15:13] */ 11646 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ1_RESERVED1_MASK 0x0000e000 11647 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ1_RESERVED1_ALIGN 0 11648 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ1_RESERVED1_BITS 3 11649 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ1_RESERVED1_SHIFT 13 11650 11651 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DQ1 :: ADJ_EN [12:12] */ 11652 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ1_ADJ_EN_MASK 0x00001000 11653 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ1_ADJ_EN_ALIGN 0 11654 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ1_ADJ_EN_BITS 1 11655 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ1_ADJ_EN_SHIFT 12 11656 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ1_ADJ_EN_DEFAULT 0x00000000 11657 11658 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DQ1 :: reserved2 [11:09] */ 11659 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ1_RESERVED2_MASK 0x00000e00 11660 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ1_RESERVED2_ALIGN 0 11661 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ1_RESERVED2_BITS 3 11662 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ1_RESERVED2_SHIFT 9 11663 11664 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DQ1 :: VDL_STEP [08:00] */ 11665 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ1_VDL_STEP_MASK 0x000001ff 11666 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ1_VDL_STEP_ALIGN 0 11667 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ1_VDL_STEP_BITS 9 11668 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ1_VDL_STEP_SHIFT 0 11669 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ1_VDL_STEP_DEFAULT 0x00000000 11670 11671 /*************************************************************************** 11672 *VDL_CONTROL_WR_DQ2 - Write channel DQ2 VDL control register 11673 */ 11674 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DQ2 :: BUSY [31:31] */ 11675 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ2_BUSY_MASK 0x80000000 11676 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ2_BUSY_ALIGN 0 11677 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ2_BUSY_BITS 1 11678 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ2_BUSY_SHIFT 31 11679 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ2_BUSY_DEFAULT 0x00000000 11680 11681 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DQ2 :: reserved0 [30:17] */ 11682 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ2_RESERVED0_MASK 0x7ffe0000 11683 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ2_RESERVED0_ALIGN 0 11684 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ2_RESERVED0_BITS 14 11685 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ2_RESERVED0_SHIFT 17 11686 11687 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DQ2 :: FORCE [16:16] */ 11688 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ2_FORCE_MASK 0x00010000 11689 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ2_FORCE_ALIGN 0 11690 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ2_FORCE_BITS 1 11691 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ2_FORCE_SHIFT 16 11692 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ2_FORCE_DEFAULT 0x00000000 11693 11694 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DQ2 :: reserved1 [15:13] */ 11695 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ2_RESERVED1_MASK 0x0000e000 11696 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ2_RESERVED1_ALIGN 0 11697 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ2_RESERVED1_BITS 3 11698 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ2_RESERVED1_SHIFT 13 11699 11700 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DQ2 :: ADJ_EN [12:12] */ 11701 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ2_ADJ_EN_MASK 0x00001000 11702 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ2_ADJ_EN_ALIGN 0 11703 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ2_ADJ_EN_BITS 1 11704 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ2_ADJ_EN_SHIFT 12 11705 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ2_ADJ_EN_DEFAULT 0x00000000 11706 11707 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DQ2 :: reserved2 [11:09] */ 11708 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ2_RESERVED2_MASK 0x00000e00 11709 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ2_RESERVED2_ALIGN 0 11710 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ2_RESERVED2_BITS 3 11711 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ2_RESERVED2_SHIFT 9 11712 11713 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DQ2 :: VDL_STEP [08:00] */ 11714 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ2_VDL_STEP_MASK 0x000001ff 11715 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ2_VDL_STEP_ALIGN 0 11716 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ2_VDL_STEP_BITS 9 11717 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ2_VDL_STEP_SHIFT 0 11718 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ2_VDL_STEP_DEFAULT 0x00000000 11719 11720 /*************************************************************************** 11721 *VDL_CONTROL_WR_DQ3 - Write channel DQ3 VDL control register 11722 */ 11723 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DQ3 :: BUSY [31:31] */ 11724 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ3_BUSY_MASK 0x80000000 11725 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ3_BUSY_ALIGN 0 11726 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ3_BUSY_BITS 1 11727 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ3_BUSY_SHIFT 31 11728 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ3_BUSY_DEFAULT 0x00000000 11729 11730 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DQ3 :: reserved0 [30:17] */ 11731 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ3_RESERVED0_MASK 0x7ffe0000 11732 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ3_RESERVED0_ALIGN 0 11733 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ3_RESERVED0_BITS 14 11734 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ3_RESERVED0_SHIFT 17 11735 11736 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DQ3 :: FORCE [16:16] */ 11737 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ3_FORCE_MASK 0x00010000 11738 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ3_FORCE_ALIGN 0 11739 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ3_FORCE_BITS 1 11740 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ3_FORCE_SHIFT 16 11741 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ3_FORCE_DEFAULT 0x00000000 11742 11743 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DQ3 :: reserved1 [15:13] */ 11744 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ3_RESERVED1_MASK 0x0000e000 11745 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ3_RESERVED1_ALIGN 0 11746 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ3_RESERVED1_BITS 3 11747 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ3_RESERVED1_SHIFT 13 11748 11749 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DQ3 :: ADJ_EN [12:12] */ 11750 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ3_ADJ_EN_MASK 0x00001000 11751 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ3_ADJ_EN_ALIGN 0 11752 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ3_ADJ_EN_BITS 1 11753 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ3_ADJ_EN_SHIFT 12 11754 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ3_ADJ_EN_DEFAULT 0x00000000 11755 11756 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DQ3 :: reserved2 [11:09] */ 11757 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ3_RESERVED2_MASK 0x00000e00 11758 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ3_RESERVED2_ALIGN 0 11759 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ3_RESERVED2_BITS 3 11760 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ3_RESERVED2_SHIFT 9 11761 11762 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DQ3 :: VDL_STEP [08:00] */ 11763 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ3_VDL_STEP_MASK 0x000001ff 11764 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ3_VDL_STEP_ALIGN 0 11765 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ3_VDL_STEP_BITS 9 11766 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ3_VDL_STEP_SHIFT 0 11767 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ3_VDL_STEP_DEFAULT 0x00000000 11768 11769 /*************************************************************************** 11770 *VDL_CONTROL_WR_DQ4 - Write channel DQ4 VDL control register 11771 */ 11772 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DQ4 :: BUSY [31:31] */ 11773 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ4_BUSY_MASK 0x80000000 11774 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ4_BUSY_ALIGN 0 11775 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ4_BUSY_BITS 1 11776 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ4_BUSY_SHIFT 31 11777 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ4_BUSY_DEFAULT 0x00000000 11778 11779 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DQ4 :: reserved0 [30:17] */ 11780 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ4_RESERVED0_MASK 0x7ffe0000 11781 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ4_RESERVED0_ALIGN 0 11782 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ4_RESERVED0_BITS 14 11783 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ4_RESERVED0_SHIFT 17 11784 11785 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DQ4 :: FORCE [16:16] */ 11786 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ4_FORCE_MASK 0x00010000 11787 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ4_FORCE_ALIGN 0 11788 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ4_FORCE_BITS 1 11789 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ4_FORCE_SHIFT 16 11790 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ4_FORCE_DEFAULT 0x00000000 11791 11792 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DQ4 :: reserved1 [15:13] */ 11793 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ4_RESERVED1_MASK 0x0000e000 11794 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ4_RESERVED1_ALIGN 0 11795 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ4_RESERVED1_BITS 3 11796 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ4_RESERVED1_SHIFT 13 11797 11798 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DQ4 :: ADJ_EN [12:12] */ 11799 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ4_ADJ_EN_MASK 0x00001000 11800 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ4_ADJ_EN_ALIGN 0 11801 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ4_ADJ_EN_BITS 1 11802 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ4_ADJ_EN_SHIFT 12 11803 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ4_ADJ_EN_DEFAULT 0x00000000 11804 11805 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DQ4 :: reserved2 [11:09] */ 11806 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ4_RESERVED2_MASK 0x00000e00 11807 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ4_RESERVED2_ALIGN 0 11808 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ4_RESERVED2_BITS 3 11809 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ4_RESERVED2_SHIFT 9 11810 11811 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DQ4 :: VDL_STEP [08:00] */ 11812 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ4_VDL_STEP_MASK 0x000001ff 11813 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ4_VDL_STEP_ALIGN 0 11814 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ4_VDL_STEP_BITS 9 11815 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ4_VDL_STEP_SHIFT 0 11816 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ4_VDL_STEP_DEFAULT 0x00000000 11817 11818 /*************************************************************************** 11819 *VDL_CONTROL_WR_DQ5 - Write channel DQ5 VDL control register 11820 */ 11821 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DQ5 :: BUSY [31:31] */ 11822 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ5_BUSY_MASK 0x80000000 11823 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ5_BUSY_ALIGN 0 11824 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ5_BUSY_BITS 1 11825 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ5_BUSY_SHIFT 31 11826 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ5_BUSY_DEFAULT 0x00000000 11827 11828 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DQ5 :: reserved0 [30:17] */ 11829 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ5_RESERVED0_MASK 0x7ffe0000 11830 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ5_RESERVED0_ALIGN 0 11831 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ5_RESERVED0_BITS 14 11832 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ5_RESERVED0_SHIFT 17 11833 11834 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DQ5 :: FORCE [16:16] */ 11835 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ5_FORCE_MASK 0x00010000 11836 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ5_FORCE_ALIGN 0 11837 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ5_FORCE_BITS 1 11838 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ5_FORCE_SHIFT 16 11839 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ5_FORCE_DEFAULT 0x00000000 11840 11841 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DQ5 :: reserved1 [15:13] */ 11842 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ5_RESERVED1_MASK 0x0000e000 11843 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ5_RESERVED1_ALIGN 0 11844 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ5_RESERVED1_BITS 3 11845 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ5_RESERVED1_SHIFT 13 11846 11847 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DQ5 :: ADJ_EN [12:12] */ 11848 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ5_ADJ_EN_MASK 0x00001000 11849 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ5_ADJ_EN_ALIGN 0 11850 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ5_ADJ_EN_BITS 1 11851 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ5_ADJ_EN_SHIFT 12 11852 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ5_ADJ_EN_DEFAULT 0x00000000 11853 11854 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DQ5 :: reserved2 [11:09] */ 11855 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ5_RESERVED2_MASK 0x00000e00 11856 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ5_RESERVED2_ALIGN 0 11857 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ5_RESERVED2_BITS 3 11858 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ5_RESERVED2_SHIFT 9 11859 11860 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DQ5 :: VDL_STEP [08:00] */ 11861 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ5_VDL_STEP_MASK 0x000001ff 11862 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ5_VDL_STEP_ALIGN 0 11863 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ5_VDL_STEP_BITS 9 11864 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ5_VDL_STEP_SHIFT 0 11865 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ5_VDL_STEP_DEFAULT 0x00000000 11866 11867 /*************************************************************************** 11868 *VDL_CONTROL_WR_DQ6 - Write channel DQ6 VDL control register 11869 */ 11870 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DQ6 :: BUSY [31:31] */ 11871 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ6_BUSY_MASK 0x80000000 11872 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ6_BUSY_ALIGN 0 11873 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ6_BUSY_BITS 1 11874 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ6_BUSY_SHIFT 31 11875 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ6_BUSY_DEFAULT 0x00000000 11876 11877 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DQ6 :: reserved0 [30:17] */ 11878 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ6_RESERVED0_MASK 0x7ffe0000 11879 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ6_RESERVED0_ALIGN 0 11880 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ6_RESERVED0_BITS 14 11881 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ6_RESERVED0_SHIFT 17 11882 11883 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DQ6 :: FORCE [16:16] */ 11884 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ6_FORCE_MASK 0x00010000 11885 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ6_FORCE_ALIGN 0 11886 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ6_FORCE_BITS 1 11887 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ6_FORCE_SHIFT 16 11888 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ6_FORCE_DEFAULT 0x00000000 11889 11890 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DQ6 :: reserved1 [15:13] */ 11891 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ6_RESERVED1_MASK 0x0000e000 11892 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ6_RESERVED1_ALIGN 0 11893 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ6_RESERVED1_BITS 3 11894 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ6_RESERVED1_SHIFT 13 11895 11896 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DQ6 :: ADJ_EN [12:12] */ 11897 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ6_ADJ_EN_MASK 0x00001000 11898 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ6_ADJ_EN_ALIGN 0 11899 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ6_ADJ_EN_BITS 1 11900 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ6_ADJ_EN_SHIFT 12 11901 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ6_ADJ_EN_DEFAULT 0x00000000 11902 11903 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DQ6 :: reserved2 [11:09] */ 11904 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ6_RESERVED2_MASK 0x00000e00 11905 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ6_RESERVED2_ALIGN 0 11906 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ6_RESERVED2_BITS 3 11907 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ6_RESERVED2_SHIFT 9 11908 11909 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DQ6 :: VDL_STEP [08:00] */ 11910 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ6_VDL_STEP_MASK 0x000001ff 11911 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ6_VDL_STEP_ALIGN 0 11912 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ6_VDL_STEP_BITS 9 11913 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ6_VDL_STEP_SHIFT 0 11914 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ6_VDL_STEP_DEFAULT 0x00000000 11915 11916 /*************************************************************************** 11917 *VDL_CONTROL_WR_DQ7 - Write channel DQ7 VDL control register 11918 */ 11919 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DQ7 :: BUSY [31:31] */ 11920 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ7_BUSY_MASK 0x80000000 11921 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ7_BUSY_ALIGN 0 11922 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ7_BUSY_BITS 1 11923 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ7_BUSY_SHIFT 31 11924 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ7_BUSY_DEFAULT 0x00000000 11925 11926 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DQ7 :: reserved0 [30:17] */ 11927 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ7_RESERVED0_MASK 0x7ffe0000 11928 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ7_RESERVED0_ALIGN 0 11929 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ7_RESERVED0_BITS 14 11930 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ7_RESERVED0_SHIFT 17 11931 11932 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DQ7 :: FORCE [16:16] */ 11933 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ7_FORCE_MASK 0x00010000 11934 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ7_FORCE_ALIGN 0 11935 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ7_FORCE_BITS 1 11936 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ7_FORCE_SHIFT 16 11937 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ7_FORCE_DEFAULT 0x00000000 11938 11939 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DQ7 :: reserved1 [15:13] */ 11940 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ7_RESERVED1_MASK 0x0000e000 11941 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ7_RESERVED1_ALIGN 0 11942 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ7_RESERVED1_BITS 3 11943 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ7_RESERVED1_SHIFT 13 11944 11945 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DQ7 :: ADJ_EN [12:12] */ 11946 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ7_ADJ_EN_MASK 0x00001000 11947 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ7_ADJ_EN_ALIGN 0 11948 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ7_ADJ_EN_BITS 1 11949 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ7_ADJ_EN_SHIFT 12 11950 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ7_ADJ_EN_DEFAULT 0x00000000 11951 11952 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DQ7 :: reserved2 [11:09] */ 11953 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ7_RESERVED2_MASK 0x00000e00 11954 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ7_RESERVED2_ALIGN 0 11955 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ7_RESERVED2_BITS 3 11956 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ7_RESERVED2_SHIFT 9 11957 11958 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DQ7 :: VDL_STEP [08:00] */ 11959 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ7_VDL_STEP_MASK 0x000001ff 11960 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ7_VDL_STEP_ALIGN 0 11961 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ7_VDL_STEP_BITS 9 11962 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ7_VDL_STEP_SHIFT 0 11963 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ7_VDL_STEP_DEFAULT 0x00000000 11964 11965 /*************************************************************************** 11966 *VDL_CONTROL_WR_DM - Write channel DM VDL control register 11967 */ 11968 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DM :: BUSY [31:31] */ 11969 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DM_BUSY_MASK 0x80000000 11970 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DM_BUSY_ALIGN 0 11971 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DM_BUSY_BITS 1 11972 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DM_BUSY_SHIFT 31 11973 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DM_BUSY_DEFAULT 0x00000000 11974 11975 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DM :: reserved0 [30:17] */ 11976 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DM_RESERVED0_MASK 0x7ffe0000 11977 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DM_RESERVED0_ALIGN 0 11978 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DM_RESERVED0_BITS 14 11979 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DM_RESERVED0_SHIFT 17 11980 11981 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DM :: FORCE [16:16] */ 11982 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DM_FORCE_MASK 0x00010000 11983 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DM_FORCE_ALIGN 0 11984 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DM_FORCE_BITS 1 11985 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DM_FORCE_SHIFT 16 11986 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DM_FORCE_DEFAULT 0x00000000 11987 11988 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DM :: reserved1 [15:13] */ 11989 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DM_RESERVED1_MASK 0x0000e000 11990 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DM_RESERVED1_ALIGN 0 11991 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DM_RESERVED1_BITS 3 11992 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DM_RESERVED1_SHIFT 13 11993 11994 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DM :: ADJ_EN [12:12] */ 11995 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DM_ADJ_EN_MASK 0x00001000 11996 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DM_ADJ_EN_ALIGN 0 11997 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DM_ADJ_EN_BITS 1 11998 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DM_ADJ_EN_SHIFT 12 11999 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DM_ADJ_EN_DEFAULT 0x00000000 12000 12001 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DM :: reserved2 [11:09] */ 12002 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DM_RESERVED2_MASK 0x00000e00 12003 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DM_RESERVED2_ALIGN 0 12004 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DM_RESERVED2_BITS 3 12005 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DM_RESERVED2_SHIFT 9 12006 12007 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_DM :: VDL_STEP [08:00] */ 12008 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DM_VDL_STEP_MASK 0x000001ff 12009 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DM_VDL_STEP_ALIGN 0 12010 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DM_VDL_STEP_BITS 9 12011 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DM_VDL_STEP_SHIFT 0 12012 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DM_VDL_STEP_DEFAULT 0x00000000 12013 12014 /*************************************************************************** 12015 *VDL_CONTROL_WR_EDC - Write channel EDC VDL control register 12016 */ 12017 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_EDC :: BUSY [31:31] */ 12018 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_EDC_BUSY_MASK 0x80000000 12019 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_EDC_BUSY_ALIGN 0 12020 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_EDC_BUSY_BITS 1 12021 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_EDC_BUSY_SHIFT 31 12022 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_EDC_BUSY_DEFAULT 0x00000000 12023 12024 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_EDC :: reserved0 [30:17] */ 12025 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_EDC_RESERVED0_MASK 0x7ffe0000 12026 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_EDC_RESERVED0_ALIGN 0 12027 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_EDC_RESERVED0_BITS 14 12028 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_EDC_RESERVED0_SHIFT 17 12029 12030 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_EDC :: FORCE [16:16] */ 12031 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_EDC_FORCE_MASK 0x00010000 12032 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_EDC_FORCE_ALIGN 0 12033 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_EDC_FORCE_BITS 1 12034 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_EDC_FORCE_SHIFT 16 12035 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_EDC_FORCE_DEFAULT 0x00000000 12036 12037 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_EDC :: reserved1 [15:13] */ 12038 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_EDC_RESERVED1_MASK 0x0000e000 12039 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_EDC_RESERVED1_ALIGN 0 12040 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_EDC_RESERVED1_BITS 3 12041 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_EDC_RESERVED1_SHIFT 13 12042 12043 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_EDC :: ADJ_EN [12:12] */ 12044 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_EDC_ADJ_EN_MASK 0x00001000 12045 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_EDC_ADJ_EN_ALIGN 0 12046 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_EDC_ADJ_EN_BITS 1 12047 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_EDC_ADJ_EN_SHIFT 12 12048 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_EDC_ADJ_EN_DEFAULT 0x00000000 12049 12050 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_EDC :: reserved2 [11:09] */ 12051 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_EDC_RESERVED2_MASK 0x00000e00 12052 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_EDC_RESERVED2_ALIGN 0 12053 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_EDC_RESERVED2_BITS 3 12054 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_EDC_RESERVED2_SHIFT 9 12055 12056 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_WR_EDC :: VDL_STEP [08:00] */ 12057 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_EDC_VDL_STEP_MASK 0x000001ff 12058 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_EDC_VDL_STEP_ALIGN 0 12059 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_EDC_VDL_STEP_BITS 9 12060 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_EDC_VDL_STEP_SHIFT 0 12061 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_EDC_VDL_STEP_DEFAULT 0x00000000 12062 12063 /*************************************************************************** 12064 *VDL_CONTROL_RD_DQSP - Read channel DQSP VDL control register 12065 */ 12066 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQSP :: BUSY [31:31] */ 12067 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSP_BUSY_MASK 0x80000000 12068 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSP_BUSY_ALIGN 0 12069 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSP_BUSY_BITS 1 12070 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSP_BUSY_SHIFT 31 12071 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSP_BUSY_DEFAULT 0x00000000 12072 12073 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQSP :: reserved0 [30:17] */ 12074 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSP_RESERVED0_MASK 0x7ffe0000 12075 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSP_RESERVED0_ALIGN 0 12076 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSP_RESERVED0_BITS 14 12077 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSP_RESERVED0_SHIFT 17 12078 12079 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQSP :: FORCE [16:16] */ 12080 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSP_FORCE_MASK 0x00010000 12081 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSP_FORCE_ALIGN 0 12082 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSP_FORCE_BITS 1 12083 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSP_FORCE_SHIFT 16 12084 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSP_FORCE_DEFAULT 0x00000000 12085 12086 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQSP :: reserved1 [15:13] */ 12087 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSP_RESERVED1_MASK 0x0000e000 12088 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSP_RESERVED1_ALIGN 0 12089 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSP_RESERVED1_BITS 3 12090 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSP_RESERVED1_SHIFT 13 12091 12092 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQSP :: ADJ_EN [12:12] */ 12093 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSP_ADJ_EN_MASK 0x00001000 12094 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSP_ADJ_EN_ALIGN 0 12095 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSP_ADJ_EN_BITS 1 12096 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSP_ADJ_EN_SHIFT 12 12097 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSP_ADJ_EN_DEFAULT 0x00000000 12098 12099 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQSP :: reserved2 [11:08] */ 12100 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSP_RESERVED2_MASK 0x00000f00 12101 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSP_RESERVED2_ALIGN 0 12102 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSP_RESERVED2_BITS 4 12103 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSP_RESERVED2_SHIFT 8 12104 12105 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQSP :: VDL_STEP [07:00] */ 12106 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSP_VDL_STEP_MASK 0x000000ff 12107 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSP_VDL_STEP_ALIGN 0 12108 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSP_VDL_STEP_BITS 8 12109 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSP_VDL_STEP_SHIFT 0 12110 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSP_VDL_STEP_DEFAULT 0x00000000 12111 12112 /*************************************************************************** 12113 *VDL_CONTROL_RD_DQSN - Read channel DQSP VDL control register 12114 */ 12115 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQSN :: BUSY [31:31] */ 12116 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSN_BUSY_MASK 0x80000000 12117 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSN_BUSY_ALIGN 0 12118 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSN_BUSY_BITS 1 12119 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSN_BUSY_SHIFT 31 12120 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSN_BUSY_DEFAULT 0x00000000 12121 12122 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQSN :: reserved0 [30:17] */ 12123 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSN_RESERVED0_MASK 0x7ffe0000 12124 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSN_RESERVED0_ALIGN 0 12125 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSN_RESERVED0_BITS 14 12126 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSN_RESERVED0_SHIFT 17 12127 12128 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQSN :: FORCE [16:16] */ 12129 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSN_FORCE_MASK 0x00010000 12130 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSN_FORCE_ALIGN 0 12131 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSN_FORCE_BITS 1 12132 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSN_FORCE_SHIFT 16 12133 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSN_FORCE_DEFAULT 0x00000000 12134 12135 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQSN :: reserved1 [15:13] */ 12136 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSN_RESERVED1_MASK 0x0000e000 12137 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSN_RESERVED1_ALIGN 0 12138 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSN_RESERVED1_BITS 3 12139 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSN_RESERVED1_SHIFT 13 12140 12141 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQSN :: ADJ_EN [12:12] */ 12142 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSN_ADJ_EN_MASK 0x00001000 12143 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSN_ADJ_EN_ALIGN 0 12144 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSN_ADJ_EN_BITS 1 12145 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSN_ADJ_EN_SHIFT 12 12146 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSN_ADJ_EN_DEFAULT 0x00000000 12147 12148 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQSN :: reserved2 [11:08] */ 12149 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSN_RESERVED2_MASK 0x00000f00 12150 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSN_RESERVED2_ALIGN 0 12151 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSN_RESERVED2_BITS 4 12152 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSN_RESERVED2_SHIFT 8 12153 12154 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQSN :: VDL_STEP [07:00] */ 12155 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSN_VDL_STEP_MASK 0x000000ff 12156 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSN_VDL_STEP_ALIGN 0 12157 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSN_VDL_STEP_BITS 8 12158 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSN_VDL_STEP_SHIFT 0 12159 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSN_VDL_STEP_DEFAULT 0x00000000 12160 12161 /*************************************************************************** 12162 *VDL_CONTROL_RD_DQ0P - Read channel DQ0-P VDL control register 12163 */ 12164 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ0P :: BUSY [31:31] */ 12165 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0P_BUSY_MASK 0x80000000 12166 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0P_BUSY_ALIGN 0 12167 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0P_BUSY_BITS 1 12168 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0P_BUSY_SHIFT 31 12169 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0P_BUSY_DEFAULT 0x00000000 12170 12171 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ0P :: reserved0 [30:17] */ 12172 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0P_RESERVED0_MASK 0x7ffe0000 12173 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0P_RESERVED0_ALIGN 0 12174 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0P_RESERVED0_BITS 14 12175 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0P_RESERVED0_SHIFT 17 12176 12177 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ0P :: FORCE [16:16] */ 12178 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0P_FORCE_MASK 0x00010000 12179 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0P_FORCE_ALIGN 0 12180 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0P_FORCE_BITS 1 12181 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0P_FORCE_SHIFT 16 12182 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0P_FORCE_DEFAULT 0x00000000 12183 12184 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ0P :: reserved1 [15:13] */ 12185 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0P_RESERVED1_MASK 0x0000e000 12186 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0P_RESERVED1_ALIGN 0 12187 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0P_RESERVED1_BITS 3 12188 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0P_RESERVED1_SHIFT 13 12189 12190 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ0P :: ADJ_EN [12:12] */ 12191 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0P_ADJ_EN_MASK 0x00001000 12192 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0P_ADJ_EN_ALIGN 0 12193 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0P_ADJ_EN_BITS 1 12194 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0P_ADJ_EN_SHIFT 12 12195 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0P_ADJ_EN_DEFAULT 0x00000000 12196 12197 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ0P :: reserved2 [11:08] */ 12198 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0P_RESERVED2_MASK 0x00000f00 12199 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0P_RESERVED2_ALIGN 0 12200 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0P_RESERVED2_BITS 4 12201 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0P_RESERVED2_SHIFT 8 12202 12203 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ0P :: VDL_STEP [07:00] */ 12204 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0P_VDL_STEP_MASK 0x000000ff 12205 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0P_VDL_STEP_ALIGN 0 12206 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0P_VDL_STEP_BITS 8 12207 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0P_VDL_STEP_SHIFT 0 12208 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0P_VDL_STEP_DEFAULT 0x00000000 12209 12210 /*************************************************************************** 12211 *VDL_CONTROL_RD_DQ0N - Read channel DQ0-N VDL control register 12212 */ 12213 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ0N :: BUSY [31:31] */ 12214 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0N_BUSY_MASK 0x80000000 12215 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0N_BUSY_ALIGN 0 12216 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0N_BUSY_BITS 1 12217 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0N_BUSY_SHIFT 31 12218 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0N_BUSY_DEFAULT 0x00000000 12219 12220 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ0N :: reserved0 [30:17] */ 12221 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0N_RESERVED0_MASK 0x7ffe0000 12222 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0N_RESERVED0_ALIGN 0 12223 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0N_RESERVED0_BITS 14 12224 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0N_RESERVED0_SHIFT 17 12225 12226 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ0N :: FORCE [16:16] */ 12227 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0N_FORCE_MASK 0x00010000 12228 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0N_FORCE_ALIGN 0 12229 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0N_FORCE_BITS 1 12230 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0N_FORCE_SHIFT 16 12231 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0N_FORCE_DEFAULT 0x00000000 12232 12233 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ0N :: reserved1 [15:13] */ 12234 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0N_RESERVED1_MASK 0x0000e000 12235 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0N_RESERVED1_ALIGN 0 12236 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0N_RESERVED1_BITS 3 12237 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0N_RESERVED1_SHIFT 13 12238 12239 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ0N :: ADJ_EN [12:12] */ 12240 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0N_ADJ_EN_MASK 0x00001000 12241 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0N_ADJ_EN_ALIGN 0 12242 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0N_ADJ_EN_BITS 1 12243 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0N_ADJ_EN_SHIFT 12 12244 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0N_ADJ_EN_DEFAULT 0x00000000 12245 12246 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ0N :: reserved2 [11:08] */ 12247 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0N_RESERVED2_MASK 0x00000f00 12248 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0N_RESERVED2_ALIGN 0 12249 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0N_RESERVED2_BITS 4 12250 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0N_RESERVED2_SHIFT 8 12251 12252 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ0N :: VDL_STEP [07:00] */ 12253 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0N_VDL_STEP_MASK 0x000000ff 12254 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0N_VDL_STEP_ALIGN 0 12255 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0N_VDL_STEP_BITS 8 12256 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0N_VDL_STEP_SHIFT 0 12257 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0N_VDL_STEP_DEFAULT 0x00000000 12258 12259 /*************************************************************************** 12260 *VDL_CONTROL_RD_DQ1P - Read channel DQ1-P VDL control register 12261 */ 12262 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ1P :: BUSY [31:31] */ 12263 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1P_BUSY_MASK 0x80000000 12264 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1P_BUSY_ALIGN 0 12265 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1P_BUSY_BITS 1 12266 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1P_BUSY_SHIFT 31 12267 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1P_BUSY_DEFAULT 0x00000000 12268 12269 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ1P :: reserved0 [30:17] */ 12270 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1P_RESERVED0_MASK 0x7ffe0000 12271 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1P_RESERVED0_ALIGN 0 12272 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1P_RESERVED0_BITS 14 12273 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1P_RESERVED0_SHIFT 17 12274 12275 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ1P :: FORCE [16:16] */ 12276 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1P_FORCE_MASK 0x00010000 12277 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1P_FORCE_ALIGN 0 12278 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1P_FORCE_BITS 1 12279 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1P_FORCE_SHIFT 16 12280 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1P_FORCE_DEFAULT 0x00000000 12281 12282 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ1P :: reserved1 [15:13] */ 12283 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1P_RESERVED1_MASK 0x0000e000 12284 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1P_RESERVED1_ALIGN 0 12285 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1P_RESERVED1_BITS 3 12286 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1P_RESERVED1_SHIFT 13 12287 12288 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ1P :: ADJ_EN [12:12] */ 12289 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1P_ADJ_EN_MASK 0x00001000 12290 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1P_ADJ_EN_ALIGN 0 12291 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1P_ADJ_EN_BITS 1 12292 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1P_ADJ_EN_SHIFT 12 12293 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1P_ADJ_EN_DEFAULT 0x00000000 12294 12295 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ1P :: reserved2 [11:08] */ 12296 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1P_RESERVED2_MASK 0x00000f00 12297 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1P_RESERVED2_ALIGN 0 12298 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1P_RESERVED2_BITS 4 12299 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1P_RESERVED2_SHIFT 8 12300 12301 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ1P :: VDL_STEP [07:00] */ 12302 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1P_VDL_STEP_MASK 0x000000ff 12303 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1P_VDL_STEP_ALIGN 0 12304 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1P_VDL_STEP_BITS 8 12305 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1P_VDL_STEP_SHIFT 0 12306 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1P_VDL_STEP_DEFAULT 0x00000000 12307 12308 /*************************************************************************** 12309 *VDL_CONTROL_RD_DQ1N - Read channel DQ1-N VDL control register 12310 */ 12311 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ1N :: BUSY [31:31] */ 12312 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1N_BUSY_MASK 0x80000000 12313 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1N_BUSY_ALIGN 0 12314 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1N_BUSY_BITS 1 12315 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1N_BUSY_SHIFT 31 12316 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1N_BUSY_DEFAULT 0x00000000 12317 12318 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ1N :: reserved0 [30:17] */ 12319 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1N_RESERVED0_MASK 0x7ffe0000 12320 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1N_RESERVED0_ALIGN 0 12321 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1N_RESERVED0_BITS 14 12322 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1N_RESERVED0_SHIFT 17 12323 12324 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ1N :: FORCE [16:16] */ 12325 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1N_FORCE_MASK 0x00010000 12326 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1N_FORCE_ALIGN 0 12327 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1N_FORCE_BITS 1 12328 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1N_FORCE_SHIFT 16 12329 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1N_FORCE_DEFAULT 0x00000000 12330 12331 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ1N :: reserved1 [15:13] */ 12332 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1N_RESERVED1_MASK 0x0000e000 12333 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1N_RESERVED1_ALIGN 0 12334 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1N_RESERVED1_BITS 3 12335 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1N_RESERVED1_SHIFT 13 12336 12337 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ1N :: ADJ_EN [12:12] */ 12338 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1N_ADJ_EN_MASK 0x00001000 12339 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1N_ADJ_EN_ALIGN 0 12340 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1N_ADJ_EN_BITS 1 12341 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1N_ADJ_EN_SHIFT 12 12342 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1N_ADJ_EN_DEFAULT 0x00000000 12343 12344 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ1N :: reserved2 [11:08] */ 12345 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1N_RESERVED2_MASK 0x00000f00 12346 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1N_RESERVED2_ALIGN 0 12347 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1N_RESERVED2_BITS 4 12348 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1N_RESERVED2_SHIFT 8 12349 12350 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ1N :: VDL_STEP [07:00] */ 12351 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1N_VDL_STEP_MASK 0x000000ff 12352 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1N_VDL_STEP_ALIGN 0 12353 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1N_VDL_STEP_BITS 8 12354 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1N_VDL_STEP_SHIFT 0 12355 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1N_VDL_STEP_DEFAULT 0x00000000 12356 12357 /*************************************************************************** 12358 *VDL_CONTROL_RD_DQ2P - Read channel DQ2-P VDL control register 12359 */ 12360 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ2P :: BUSY [31:31] */ 12361 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2P_BUSY_MASK 0x80000000 12362 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2P_BUSY_ALIGN 0 12363 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2P_BUSY_BITS 1 12364 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2P_BUSY_SHIFT 31 12365 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2P_BUSY_DEFAULT 0x00000000 12366 12367 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ2P :: reserved0 [30:17] */ 12368 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2P_RESERVED0_MASK 0x7ffe0000 12369 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2P_RESERVED0_ALIGN 0 12370 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2P_RESERVED0_BITS 14 12371 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2P_RESERVED0_SHIFT 17 12372 12373 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ2P :: FORCE [16:16] */ 12374 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2P_FORCE_MASK 0x00010000 12375 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2P_FORCE_ALIGN 0 12376 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2P_FORCE_BITS 1 12377 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2P_FORCE_SHIFT 16 12378 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2P_FORCE_DEFAULT 0x00000000 12379 12380 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ2P :: reserved1 [15:13] */ 12381 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2P_RESERVED1_MASK 0x0000e000 12382 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2P_RESERVED1_ALIGN 0 12383 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2P_RESERVED1_BITS 3 12384 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2P_RESERVED1_SHIFT 13 12385 12386 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ2P :: ADJ_EN [12:12] */ 12387 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2P_ADJ_EN_MASK 0x00001000 12388 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2P_ADJ_EN_ALIGN 0 12389 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2P_ADJ_EN_BITS 1 12390 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2P_ADJ_EN_SHIFT 12 12391 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2P_ADJ_EN_DEFAULT 0x00000000 12392 12393 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ2P :: reserved2 [11:08] */ 12394 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2P_RESERVED2_MASK 0x00000f00 12395 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2P_RESERVED2_ALIGN 0 12396 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2P_RESERVED2_BITS 4 12397 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2P_RESERVED2_SHIFT 8 12398 12399 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ2P :: VDL_STEP [07:00] */ 12400 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2P_VDL_STEP_MASK 0x000000ff 12401 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2P_VDL_STEP_ALIGN 0 12402 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2P_VDL_STEP_BITS 8 12403 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2P_VDL_STEP_SHIFT 0 12404 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2P_VDL_STEP_DEFAULT 0x00000000 12405 12406 /*************************************************************************** 12407 *VDL_CONTROL_RD_DQ2N - Read channel DQ2-N VDL control register 12408 */ 12409 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ2N :: BUSY [31:31] */ 12410 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2N_BUSY_MASK 0x80000000 12411 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2N_BUSY_ALIGN 0 12412 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2N_BUSY_BITS 1 12413 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2N_BUSY_SHIFT 31 12414 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2N_BUSY_DEFAULT 0x00000000 12415 12416 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ2N :: reserved0 [30:17] */ 12417 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2N_RESERVED0_MASK 0x7ffe0000 12418 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2N_RESERVED0_ALIGN 0 12419 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2N_RESERVED0_BITS 14 12420 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2N_RESERVED0_SHIFT 17 12421 12422 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ2N :: FORCE [16:16] */ 12423 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2N_FORCE_MASK 0x00010000 12424 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2N_FORCE_ALIGN 0 12425 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2N_FORCE_BITS 1 12426 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2N_FORCE_SHIFT 16 12427 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2N_FORCE_DEFAULT 0x00000000 12428 12429 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ2N :: reserved1 [15:13] */ 12430 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2N_RESERVED1_MASK 0x0000e000 12431 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2N_RESERVED1_ALIGN 0 12432 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2N_RESERVED1_BITS 3 12433 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2N_RESERVED1_SHIFT 13 12434 12435 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ2N :: ADJ_EN [12:12] */ 12436 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2N_ADJ_EN_MASK 0x00001000 12437 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2N_ADJ_EN_ALIGN 0 12438 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2N_ADJ_EN_BITS 1 12439 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2N_ADJ_EN_SHIFT 12 12440 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2N_ADJ_EN_DEFAULT 0x00000000 12441 12442 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ2N :: reserved2 [11:08] */ 12443 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2N_RESERVED2_MASK 0x00000f00 12444 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2N_RESERVED2_ALIGN 0 12445 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2N_RESERVED2_BITS 4 12446 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2N_RESERVED2_SHIFT 8 12447 12448 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ2N :: VDL_STEP [07:00] */ 12449 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2N_VDL_STEP_MASK 0x000000ff 12450 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2N_VDL_STEP_ALIGN 0 12451 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2N_VDL_STEP_BITS 8 12452 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2N_VDL_STEP_SHIFT 0 12453 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2N_VDL_STEP_DEFAULT 0x00000000 12454 12455 /*************************************************************************** 12456 *VDL_CONTROL_RD_DQ3P - Read channel DQ3-P VDL control register 12457 */ 12458 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ3P :: BUSY [31:31] */ 12459 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3P_BUSY_MASK 0x80000000 12460 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3P_BUSY_ALIGN 0 12461 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3P_BUSY_BITS 1 12462 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3P_BUSY_SHIFT 31 12463 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3P_BUSY_DEFAULT 0x00000000 12464 12465 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ3P :: reserved0 [30:17] */ 12466 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3P_RESERVED0_MASK 0x7ffe0000 12467 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3P_RESERVED0_ALIGN 0 12468 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3P_RESERVED0_BITS 14 12469 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3P_RESERVED0_SHIFT 17 12470 12471 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ3P :: FORCE [16:16] */ 12472 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3P_FORCE_MASK 0x00010000 12473 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3P_FORCE_ALIGN 0 12474 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3P_FORCE_BITS 1 12475 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3P_FORCE_SHIFT 16 12476 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3P_FORCE_DEFAULT 0x00000000 12477 12478 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ3P :: reserved1 [15:13] */ 12479 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3P_RESERVED1_MASK 0x0000e000 12480 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3P_RESERVED1_ALIGN 0 12481 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3P_RESERVED1_BITS 3 12482 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3P_RESERVED1_SHIFT 13 12483 12484 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ3P :: ADJ_EN [12:12] */ 12485 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3P_ADJ_EN_MASK 0x00001000 12486 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3P_ADJ_EN_ALIGN 0 12487 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3P_ADJ_EN_BITS 1 12488 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3P_ADJ_EN_SHIFT 12 12489 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3P_ADJ_EN_DEFAULT 0x00000000 12490 12491 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ3P :: reserved2 [11:08] */ 12492 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3P_RESERVED2_MASK 0x00000f00 12493 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3P_RESERVED2_ALIGN 0 12494 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3P_RESERVED2_BITS 4 12495 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3P_RESERVED2_SHIFT 8 12496 12497 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ3P :: VDL_STEP [07:00] */ 12498 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3P_VDL_STEP_MASK 0x000000ff 12499 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3P_VDL_STEP_ALIGN 0 12500 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3P_VDL_STEP_BITS 8 12501 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3P_VDL_STEP_SHIFT 0 12502 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3P_VDL_STEP_DEFAULT 0x00000000 12503 12504 /*************************************************************************** 12505 *VDL_CONTROL_RD_DQ3N - Read channel DQ3-N VDL control register 12506 */ 12507 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ3N :: BUSY [31:31] */ 12508 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3N_BUSY_MASK 0x80000000 12509 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3N_BUSY_ALIGN 0 12510 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3N_BUSY_BITS 1 12511 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3N_BUSY_SHIFT 31 12512 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3N_BUSY_DEFAULT 0x00000000 12513 12514 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ3N :: reserved0 [30:17] */ 12515 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3N_RESERVED0_MASK 0x7ffe0000 12516 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3N_RESERVED0_ALIGN 0 12517 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3N_RESERVED0_BITS 14 12518 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3N_RESERVED0_SHIFT 17 12519 12520 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ3N :: FORCE [16:16] */ 12521 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3N_FORCE_MASK 0x00010000 12522 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3N_FORCE_ALIGN 0 12523 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3N_FORCE_BITS 1 12524 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3N_FORCE_SHIFT 16 12525 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3N_FORCE_DEFAULT 0x00000000 12526 12527 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ3N :: reserved1 [15:13] */ 12528 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3N_RESERVED1_MASK 0x0000e000 12529 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3N_RESERVED1_ALIGN 0 12530 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3N_RESERVED1_BITS 3 12531 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3N_RESERVED1_SHIFT 13 12532 12533 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ3N :: ADJ_EN [12:12] */ 12534 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3N_ADJ_EN_MASK 0x00001000 12535 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3N_ADJ_EN_ALIGN 0 12536 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3N_ADJ_EN_BITS 1 12537 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3N_ADJ_EN_SHIFT 12 12538 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3N_ADJ_EN_DEFAULT 0x00000000 12539 12540 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ3N :: reserved2 [11:08] */ 12541 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3N_RESERVED2_MASK 0x00000f00 12542 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3N_RESERVED2_ALIGN 0 12543 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3N_RESERVED2_BITS 4 12544 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3N_RESERVED2_SHIFT 8 12545 12546 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ3N :: VDL_STEP [07:00] */ 12547 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3N_VDL_STEP_MASK 0x000000ff 12548 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3N_VDL_STEP_ALIGN 0 12549 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3N_VDL_STEP_BITS 8 12550 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3N_VDL_STEP_SHIFT 0 12551 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3N_VDL_STEP_DEFAULT 0x00000000 12552 12553 /*************************************************************************** 12554 *VDL_CONTROL_RD_DQ4P - Read channel DQ4-P VDL control register 12555 */ 12556 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ4P :: BUSY [31:31] */ 12557 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4P_BUSY_MASK 0x80000000 12558 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4P_BUSY_ALIGN 0 12559 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4P_BUSY_BITS 1 12560 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4P_BUSY_SHIFT 31 12561 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4P_BUSY_DEFAULT 0x00000000 12562 12563 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ4P :: reserved0 [30:17] */ 12564 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4P_RESERVED0_MASK 0x7ffe0000 12565 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4P_RESERVED0_ALIGN 0 12566 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4P_RESERVED0_BITS 14 12567 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4P_RESERVED0_SHIFT 17 12568 12569 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ4P :: FORCE [16:16] */ 12570 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4P_FORCE_MASK 0x00010000 12571 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4P_FORCE_ALIGN 0 12572 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4P_FORCE_BITS 1 12573 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4P_FORCE_SHIFT 16 12574 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4P_FORCE_DEFAULT 0x00000000 12575 12576 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ4P :: reserved1 [15:13] */ 12577 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4P_RESERVED1_MASK 0x0000e000 12578 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4P_RESERVED1_ALIGN 0 12579 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4P_RESERVED1_BITS 3 12580 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4P_RESERVED1_SHIFT 13 12581 12582 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ4P :: ADJ_EN [12:12] */ 12583 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4P_ADJ_EN_MASK 0x00001000 12584 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4P_ADJ_EN_ALIGN 0 12585 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4P_ADJ_EN_BITS 1 12586 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4P_ADJ_EN_SHIFT 12 12587 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4P_ADJ_EN_DEFAULT 0x00000000 12588 12589 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ4P :: reserved2 [11:08] */ 12590 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4P_RESERVED2_MASK 0x00000f00 12591 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4P_RESERVED2_ALIGN 0 12592 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4P_RESERVED2_BITS 4 12593 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4P_RESERVED2_SHIFT 8 12594 12595 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ4P :: VDL_STEP [07:00] */ 12596 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4P_VDL_STEP_MASK 0x000000ff 12597 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4P_VDL_STEP_ALIGN 0 12598 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4P_VDL_STEP_BITS 8 12599 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4P_VDL_STEP_SHIFT 0 12600 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4P_VDL_STEP_DEFAULT 0x00000000 12601 12602 /*************************************************************************** 12603 *VDL_CONTROL_RD_DQ4N - Read channel DQ4-N VDL control register 12604 */ 12605 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ4N :: BUSY [31:31] */ 12606 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4N_BUSY_MASK 0x80000000 12607 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4N_BUSY_ALIGN 0 12608 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4N_BUSY_BITS 1 12609 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4N_BUSY_SHIFT 31 12610 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4N_BUSY_DEFAULT 0x00000000 12611 12612 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ4N :: reserved0 [30:17] */ 12613 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4N_RESERVED0_MASK 0x7ffe0000 12614 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4N_RESERVED0_ALIGN 0 12615 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4N_RESERVED0_BITS 14 12616 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4N_RESERVED0_SHIFT 17 12617 12618 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ4N :: FORCE [16:16] */ 12619 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4N_FORCE_MASK 0x00010000 12620 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4N_FORCE_ALIGN 0 12621 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4N_FORCE_BITS 1 12622 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4N_FORCE_SHIFT 16 12623 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4N_FORCE_DEFAULT 0x00000000 12624 12625 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ4N :: reserved1 [15:13] */ 12626 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4N_RESERVED1_MASK 0x0000e000 12627 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4N_RESERVED1_ALIGN 0 12628 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4N_RESERVED1_BITS 3 12629 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4N_RESERVED1_SHIFT 13 12630 12631 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ4N :: ADJ_EN [12:12] */ 12632 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4N_ADJ_EN_MASK 0x00001000 12633 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4N_ADJ_EN_ALIGN 0 12634 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4N_ADJ_EN_BITS 1 12635 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4N_ADJ_EN_SHIFT 12 12636 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4N_ADJ_EN_DEFAULT 0x00000000 12637 12638 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ4N :: reserved2 [11:08] */ 12639 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4N_RESERVED2_MASK 0x00000f00 12640 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4N_RESERVED2_ALIGN 0 12641 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4N_RESERVED2_BITS 4 12642 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4N_RESERVED2_SHIFT 8 12643 12644 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ4N :: VDL_STEP [07:00] */ 12645 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4N_VDL_STEP_MASK 0x000000ff 12646 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4N_VDL_STEP_ALIGN 0 12647 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4N_VDL_STEP_BITS 8 12648 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4N_VDL_STEP_SHIFT 0 12649 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4N_VDL_STEP_DEFAULT 0x00000000 12650 12651 /*************************************************************************** 12652 *VDL_CONTROL_RD_DQ5P - Read channel DQ5-P VDL control register 12653 */ 12654 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ5P :: BUSY [31:31] */ 12655 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5P_BUSY_MASK 0x80000000 12656 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5P_BUSY_ALIGN 0 12657 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5P_BUSY_BITS 1 12658 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5P_BUSY_SHIFT 31 12659 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5P_BUSY_DEFAULT 0x00000000 12660 12661 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ5P :: reserved0 [30:17] */ 12662 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5P_RESERVED0_MASK 0x7ffe0000 12663 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5P_RESERVED0_ALIGN 0 12664 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5P_RESERVED0_BITS 14 12665 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5P_RESERVED0_SHIFT 17 12666 12667 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ5P :: FORCE [16:16] */ 12668 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5P_FORCE_MASK 0x00010000 12669 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5P_FORCE_ALIGN 0 12670 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5P_FORCE_BITS 1 12671 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5P_FORCE_SHIFT 16 12672 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5P_FORCE_DEFAULT 0x00000000 12673 12674 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ5P :: reserved1 [15:13] */ 12675 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5P_RESERVED1_MASK 0x0000e000 12676 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5P_RESERVED1_ALIGN 0 12677 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5P_RESERVED1_BITS 3 12678 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5P_RESERVED1_SHIFT 13 12679 12680 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ5P :: ADJ_EN [12:12] */ 12681 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5P_ADJ_EN_MASK 0x00001000 12682 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5P_ADJ_EN_ALIGN 0 12683 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5P_ADJ_EN_BITS 1 12684 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5P_ADJ_EN_SHIFT 12 12685 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5P_ADJ_EN_DEFAULT 0x00000000 12686 12687 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ5P :: reserved2 [11:08] */ 12688 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5P_RESERVED2_MASK 0x00000f00 12689 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5P_RESERVED2_ALIGN 0 12690 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5P_RESERVED2_BITS 4 12691 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5P_RESERVED2_SHIFT 8 12692 12693 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ5P :: VDL_STEP [07:00] */ 12694 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5P_VDL_STEP_MASK 0x000000ff 12695 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5P_VDL_STEP_ALIGN 0 12696 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5P_VDL_STEP_BITS 8 12697 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5P_VDL_STEP_SHIFT 0 12698 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5P_VDL_STEP_DEFAULT 0x00000000 12699 12700 /*************************************************************************** 12701 *VDL_CONTROL_RD_DQ5N - Read channel DQ5-N VDL control register 12702 */ 12703 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ5N :: BUSY [31:31] */ 12704 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5N_BUSY_MASK 0x80000000 12705 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5N_BUSY_ALIGN 0 12706 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5N_BUSY_BITS 1 12707 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5N_BUSY_SHIFT 31 12708 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5N_BUSY_DEFAULT 0x00000000 12709 12710 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ5N :: reserved0 [30:17] */ 12711 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5N_RESERVED0_MASK 0x7ffe0000 12712 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5N_RESERVED0_ALIGN 0 12713 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5N_RESERVED0_BITS 14 12714 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5N_RESERVED0_SHIFT 17 12715 12716 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ5N :: FORCE [16:16] */ 12717 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5N_FORCE_MASK 0x00010000 12718 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5N_FORCE_ALIGN 0 12719 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5N_FORCE_BITS 1 12720 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5N_FORCE_SHIFT 16 12721 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5N_FORCE_DEFAULT 0x00000000 12722 12723 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ5N :: reserved1 [15:13] */ 12724 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5N_RESERVED1_MASK 0x0000e000 12725 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5N_RESERVED1_ALIGN 0 12726 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5N_RESERVED1_BITS 3 12727 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5N_RESERVED1_SHIFT 13 12728 12729 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ5N :: ADJ_EN [12:12] */ 12730 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5N_ADJ_EN_MASK 0x00001000 12731 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5N_ADJ_EN_ALIGN 0 12732 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5N_ADJ_EN_BITS 1 12733 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5N_ADJ_EN_SHIFT 12 12734 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5N_ADJ_EN_DEFAULT 0x00000000 12735 12736 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ5N :: reserved2 [11:08] */ 12737 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5N_RESERVED2_MASK 0x00000f00 12738 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5N_RESERVED2_ALIGN 0 12739 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5N_RESERVED2_BITS 4 12740 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5N_RESERVED2_SHIFT 8 12741 12742 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ5N :: VDL_STEP [07:00] */ 12743 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5N_VDL_STEP_MASK 0x000000ff 12744 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5N_VDL_STEP_ALIGN 0 12745 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5N_VDL_STEP_BITS 8 12746 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5N_VDL_STEP_SHIFT 0 12747 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5N_VDL_STEP_DEFAULT 0x00000000 12748 12749 /*************************************************************************** 12750 *VDL_CONTROL_RD_DQ6P - Read channel DQ6-P VDL control register 12751 */ 12752 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ6P :: BUSY [31:31] */ 12753 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6P_BUSY_MASK 0x80000000 12754 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6P_BUSY_ALIGN 0 12755 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6P_BUSY_BITS 1 12756 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6P_BUSY_SHIFT 31 12757 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6P_BUSY_DEFAULT 0x00000000 12758 12759 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ6P :: reserved0 [30:17] */ 12760 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6P_RESERVED0_MASK 0x7ffe0000 12761 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6P_RESERVED0_ALIGN 0 12762 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6P_RESERVED0_BITS 14 12763 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6P_RESERVED0_SHIFT 17 12764 12765 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ6P :: FORCE [16:16] */ 12766 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6P_FORCE_MASK 0x00010000 12767 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6P_FORCE_ALIGN 0 12768 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6P_FORCE_BITS 1 12769 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6P_FORCE_SHIFT 16 12770 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6P_FORCE_DEFAULT 0x00000000 12771 12772 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ6P :: reserved1 [15:13] */ 12773 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6P_RESERVED1_MASK 0x0000e000 12774 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6P_RESERVED1_ALIGN 0 12775 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6P_RESERVED1_BITS 3 12776 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6P_RESERVED1_SHIFT 13 12777 12778 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ6P :: ADJ_EN [12:12] */ 12779 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6P_ADJ_EN_MASK 0x00001000 12780 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6P_ADJ_EN_ALIGN 0 12781 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6P_ADJ_EN_BITS 1 12782 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6P_ADJ_EN_SHIFT 12 12783 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6P_ADJ_EN_DEFAULT 0x00000000 12784 12785 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ6P :: reserved2 [11:08] */ 12786 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6P_RESERVED2_MASK 0x00000f00 12787 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6P_RESERVED2_ALIGN 0 12788 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6P_RESERVED2_BITS 4 12789 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6P_RESERVED2_SHIFT 8 12790 12791 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ6P :: VDL_STEP [07:00] */ 12792 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6P_VDL_STEP_MASK 0x000000ff 12793 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6P_VDL_STEP_ALIGN 0 12794 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6P_VDL_STEP_BITS 8 12795 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6P_VDL_STEP_SHIFT 0 12796 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6P_VDL_STEP_DEFAULT 0x00000000 12797 12798 /*************************************************************************** 12799 *VDL_CONTROL_RD_DQ6N - Read channel DQ6-N VDL control register 12800 */ 12801 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ6N :: BUSY [31:31] */ 12802 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6N_BUSY_MASK 0x80000000 12803 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6N_BUSY_ALIGN 0 12804 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6N_BUSY_BITS 1 12805 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6N_BUSY_SHIFT 31 12806 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6N_BUSY_DEFAULT 0x00000000 12807 12808 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ6N :: reserved0 [30:17] */ 12809 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6N_RESERVED0_MASK 0x7ffe0000 12810 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6N_RESERVED0_ALIGN 0 12811 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6N_RESERVED0_BITS 14 12812 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6N_RESERVED0_SHIFT 17 12813 12814 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ6N :: FORCE [16:16] */ 12815 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6N_FORCE_MASK 0x00010000 12816 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6N_FORCE_ALIGN 0 12817 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6N_FORCE_BITS 1 12818 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6N_FORCE_SHIFT 16 12819 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6N_FORCE_DEFAULT 0x00000000 12820 12821 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ6N :: reserved1 [15:13] */ 12822 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6N_RESERVED1_MASK 0x0000e000 12823 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6N_RESERVED1_ALIGN 0 12824 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6N_RESERVED1_BITS 3 12825 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6N_RESERVED1_SHIFT 13 12826 12827 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ6N :: ADJ_EN [12:12] */ 12828 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6N_ADJ_EN_MASK 0x00001000 12829 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6N_ADJ_EN_ALIGN 0 12830 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6N_ADJ_EN_BITS 1 12831 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6N_ADJ_EN_SHIFT 12 12832 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6N_ADJ_EN_DEFAULT 0x00000000 12833 12834 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ6N :: reserved2 [11:08] */ 12835 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6N_RESERVED2_MASK 0x00000f00 12836 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6N_RESERVED2_ALIGN 0 12837 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6N_RESERVED2_BITS 4 12838 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6N_RESERVED2_SHIFT 8 12839 12840 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ6N :: VDL_STEP [07:00] */ 12841 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6N_VDL_STEP_MASK 0x000000ff 12842 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6N_VDL_STEP_ALIGN 0 12843 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6N_VDL_STEP_BITS 8 12844 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6N_VDL_STEP_SHIFT 0 12845 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6N_VDL_STEP_DEFAULT 0x00000000 12846 12847 /*************************************************************************** 12848 *VDL_CONTROL_RD_DQ7P - Read channel DQ7-P VDL control register 12849 */ 12850 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ7P :: BUSY [31:31] */ 12851 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7P_BUSY_MASK 0x80000000 12852 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7P_BUSY_ALIGN 0 12853 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7P_BUSY_BITS 1 12854 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7P_BUSY_SHIFT 31 12855 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7P_BUSY_DEFAULT 0x00000000 12856 12857 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ7P :: reserved0 [30:17] */ 12858 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7P_RESERVED0_MASK 0x7ffe0000 12859 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7P_RESERVED0_ALIGN 0 12860 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7P_RESERVED0_BITS 14 12861 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7P_RESERVED0_SHIFT 17 12862 12863 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ7P :: FORCE [16:16] */ 12864 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7P_FORCE_MASK 0x00010000 12865 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7P_FORCE_ALIGN 0 12866 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7P_FORCE_BITS 1 12867 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7P_FORCE_SHIFT 16 12868 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7P_FORCE_DEFAULT 0x00000000 12869 12870 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ7P :: reserved1 [15:13] */ 12871 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7P_RESERVED1_MASK 0x0000e000 12872 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7P_RESERVED1_ALIGN 0 12873 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7P_RESERVED1_BITS 3 12874 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7P_RESERVED1_SHIFT 13 12875 12876 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ7P :: ADJ_EN [12:12] */ 12877 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7P_ADJ_EN_MASK 0x00001000 12878 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7P_ADJ_EN_ALIGN 0 12879 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7P_ADJ_EN_BITS 1 12880 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7P_ADJ_EN_SHIFT 12 12881 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7P_ADJ_EN_DEFAULT 0x00000000 12882 12883 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ7P :: reserved2 [11:08] */ 12884 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7P_RESERVED2_MASK 0x00000f00 12885 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7P_RESERVED2_ALIGN 0 12886 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7P_RESERVED2_BITS 4 12887 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7P_RESERVED2_SHIFT 8 12888 12889 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ7P :: VDL_STEP [07:00] */ 12890 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7P_VDL_STEP_MASK 0x000000ff 12891 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7P_VDL_STEP_ALIGN 0 12892 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7P_VDL_STEP_BITS 8 12893 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7P_VDL_STEP_SHIFT 0 12894 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7P_VDL_STEP_DEFAULT 0x00000000 12895 12896 /*************************************************************************** 12897 *VDL_CONTROL_RD_DQ7N - Read channel DQ7-N VDL control register 12898 */ 12899 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ7N :: BUSY [31:31] */ 12900 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7N_BUSY_MASK 0x80000000 12901 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7N_BUSY_ALIGN 0 12902 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7N_BUSY_BITS 1 12903 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7N_BUSY_SHIFT 31 12904 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7N_BUSY_DEFAULT 0x00000000 12905 12906 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ7N :: reserved0 [30:17] */ 12907 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7N_RESERVED0_MASK 0x7ffe0000 12908 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7N_RESERVED0_ALIGN 0 12909 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7N_RESERVED0_BITS 14 12910 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7N_RESERVED0_SHIFT 17 12911 12912 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ7N :: FORCE [16:16] */ 12913 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7N_FORCE_MASK 0x00010000 12914 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7N_FORCE_ALIGN 0 12915 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7N_FORCE_BITS 1 12916 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7N_FORCE_SHIFT 16 12917 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7N_FORCE_DEFAULT 0x00000000 12918 12919 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ7N :: reserved1 [15:13] */ 12920 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7N_RESERVED1_MASK 0x0000e000 12921 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7N_RESERVED1_ALIGN 0 12922 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7N_RESERVED1_BITS 3 12923 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7N_RESERVED1_SHIFT 13 12924 12925 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ7N :: ADJ_EN [12:12] */ 12926 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7N_ADJ_EN_MASK 0x00001000 12927 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7N_ADJ_EN_ALIGN 0 12928 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7N_ADJ_EN_BITS 1 12929 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7N_ADJ_EN_SHIFT 12 12930 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7N_ADJ_EN_DEFAULT 0x00000000 12931 12932 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ7N :: reserved2 [11:08] */ 12933 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7N_RESERVED2_MASK 0x00000f00 12934 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7N_RESERVED2_ALIGN 0 12935 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7N_RESERVED2_BITS 4 12936 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7N_RESERVED2_SHIFT 8 12937 12938 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DQ7N :: VDL_STEP [07:00] */ 12939 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7N_VDL_STEP_MASK 0x000000ff 12940 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7N_VDL_STEP_ALIGN 0 12941 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7N_VDL_STEP_BITS 8 12942 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7N_VDL_STEP_SHIFT 0 12943 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7N_VDL_STEP_DEFAULT 0x00000000 12944 12945 /*************************************************************************** 12946 *VDL_CONTROL_RD_DMP - Read channel DM-P VDL control register 12947 */ 12948 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DMP :: BUSY [31:31] */ 12949 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMP_BUSY_MASK 0x80000000 12950 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMP_BUSY_ALIGN 0 12951 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMP_BUSY_BITS 1 12952 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMP_BUSY_SHIFT 31 12953 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMP_BUSY_DEFAULT 0x00000000 12954 12955 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DMP :: reserved0 [30:17] */ 12956 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMP_RESERVED0_MASK 0x7ffe0000 12957 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMP_RESERVED0_ALIGN 0 12958 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMP_RESERVED0_BITS 14 12959 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMP_RESERVED0_SHIFT 17 12960 12961 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DMP :: FORCE [16:16] */ 12962 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMP_FORCE_MASK 0x00010000 12963 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMP_FORCE_ALIGN 0 12964 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMP_FORCE_BITS 1 12965 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMP_FORCE_SHIFT 16 12966 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMP_FORCE_DEFAULT 0x00000000 12967 12968 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DMP :: reserved1 [15:13] */ 12969 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMP_RESERVED1_MASK 0x0000e000 12970 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMP_RESERVED1_ALIGN 0 12971 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMP_RESERVED1_BITS 3 12972 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMP_RESERVED1_SHIFT 13 12973 12974 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DMP :: ADJ_EN [12:12] */ 12975 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMP_ADJ_EN_MASK 0x00001000 12976 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMP_ADJ_EN_ALIGN 0 12977 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMP_ADJ_EN_BITS 1 12978 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMP_ADJ_EN_SHIFT 12 12979 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMP_ADJ_EN_DEFAULT 0x00000000 12980 12981 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DMP :: reserved2 [11:08] */ 12982 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMP_RESERVED2_MASK 0x00000f00 12983 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMP_RESERVED2_ALIGN 0 12984 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMP_RESERVED2_BITS 4 12985 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMP_RESERVED2_SHIFT 8 12986 12987 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DMP :: VDL_STEP [07:00] */ 12988 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMP_VDL_STEP_MASK 0x000000ff 12989 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMP_VDL_STEP_ALIGN 0 12990 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMP_VDL_STEP_BITS 8 12991 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMP_VDL_STEP_SHIFT 0 12992 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMP_VDL_STEP_DEFAULT 0x00000000 12993 12994 /*************************************************************************** 12995 *VDL_CONTROL_RD_DMN - Read channel DM-N VDL control register 12996 */ 12997 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DMN :: BUSY [31:31] */ 12998 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMN_BUSY_MASK 0x80000000 12999 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMN_BUSY_ALIGN 0 13000 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMN_BUSY_BITS 1 13001 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMN_BUSY_SHIFT 31 13002 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMN_BUSY_DEFAULT 0x00000000 13003 13004 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DMN :: reserved0 [30:17] */ 13005 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMN_RESERVED0_MASK 0x7ffe0000 13006 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMN_RESERVED0_ALIGN 0 13007 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMN_RESERVED0_BITS 14 13008 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMN_RESERVED0_SHIFT 17 13009 13010 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DMN :: FORCE [16:16] */ 13011 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMN_FORCE_MASK 0x00010000 13012 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMN_FORCE_ALIGN 0 13013 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMN_FORCE_BITS 1 13014 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMN_FORCE_SHIFT 16 13015 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMN_FORCE_DEFAULT 0x00000000 13016 13017 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DMN :: reserved1 [15:13] */ 13018 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMN_RESERVED1_MASK 0x0000e000 13019 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMN_RESERVED1_ALIGN 0 13020 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMN_RESERVED1_BITS 3 13021 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMN_RESERVED1_SHIFT 13 13022 13023 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DMN :: ADJ_EN [12:12] */ 13024 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMN_ADJ_EN_MASK 0x00001000 13025 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMN_ADJ_EN_ALIGN 0 13026 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMN_ADJ_EN_BITS 1 13027 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMN_ADJ_EN_SHIFT 12 13028 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMN_ADJ_EN_DEFAULT 0x00000000 13029 13030 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DMN :: reserved2 [11:08] */ 13031 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMN_RESERVED2_MASK 0x00000f00 13032 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMN_RESERVED2_ALIGN 0 13033 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMN_RESERVED2_BITS 4 13034 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMN_RESERVED2_SHIFT 8 13035 13036 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_DMN :: VDL_STEP [07:00] */ 13037 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMN_VDL_STEP_MASK 0x000000ff 13038 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMN_VDL_STEP_ALIGN 0 13039 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMN_VDL_STEP_BITS 8 13040 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMN_VDL_STEP_SHIFT 0 13041 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMN_VDL_STEP_DEFAULT 0x00000000 13042 13043 /*************************************************************************** 13044 *VDL_CONTROL_RD_EDCP - Read channel EDC-P VDL control register 13045 */ 13046 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_EDCP :: BUSY [31:31] */ 13047 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EDCP_BUSY_MASK 0x80000000 13048 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EDCP_BUSY_ALIGN 0 13049 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EDCP_BUSY_BITS 1 13050 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EDCP_BUSY_SHIFT 31 13051 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EDCP_BUSY_DEFAULT 0x00000000 13052 13053 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_EDCP :: reserved0 [30:17] */ 13054 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EDCP_RESERVED0_MASK 0x7ffe0000 13055 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EDCP_RESERVED0_ALIGN 0 13056 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EDCP_RESERVED0_BITS 14 13057 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EDCP_RESERVED0_SHIFT 17 13058 13059 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_EDCP :: FORCE [16:16] */ 13060 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EDCP_FORCE_MASK 0x00010000 13061 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EDCP_FORCE_ALIGN 0 13062 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EDCP_FORCE_BITS 1 13063 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EDCP_FORCE_SHIFT 16 13064 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EDCP_FORCE_DEFAULT 0x00000000 13065 13066 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_EDCP :: reserved1 [15:13] */ 13067 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EDCP_RESERVED1_MASK 0x0000e000 13068 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EDCP_RESERVED1_ALIGN 0 13069 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EDCP_RESERVED1_BITS 3 13070 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EDCP_RESERVED1_SHIFT 13 13071 13072 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_EDCP :: ADJ_EN [12:12] */ 13073 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EDCP_ADJ_EN_MASK 0x00001000 13074 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EDCP_ADJ_EN_ALIGN 0 13075 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EDCP_ADJ_EN_BITS 1 13076 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EDCP_ADJ_EN_SHIFT 12 13077 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EDCP_ADJ_EN_DEFAULT 0x00000000 13078 13079 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_EDCP :: reserved2 [11:08] */ 13080 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EDCP_RESERVED2_MASK 0x00000f00 13081 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EDCP_RESERVED2_ALIGN 0 13082 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EDCP_RESERVED2_BITS 4 13083 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EDCP_RESERVED2_SHIFT 8 13084 13085 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_EDCP :: VDL_STEP [07:00] */ 13086 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EDCP_VDL_STEP_MASK 0x000000ff 13087 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EDCP_VDL_STEP_ALIGN 0 13088 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EDCP_VDL_STEP_BITS 8 13089 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EDCP_VDL_STEP_SHIFT 0 13090 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EDCP_VDL_STEP_DEFAULT 0x00000000 13091 13092 /*************************************************************************** 13093 *VDL_CONTROL_RD_EDCN - Read channel EDC-N VDL control register 13094 */ 13095 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_EDCN :: BUSY [31:31] */ 13096 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EDCN_BUSY_MASK 0x80000000 13097 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EDCN_BUSY_ALIGN 0 13098 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EDCN_BUSY_BITS 1 13099 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EDCN_BUSY_SHIFT 31 13100 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EDCN_BUSY_DEFAULT 0x00000000 13101 13102 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_EDCN :: reserved0 [30:17] */ 13103 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EDCN_RESERVED0_MASK 0x7ffe0000 13104 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EDCN_RESERVED0_ALIGN 0 13105 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EDCN_RESERVED0_BITS 14 13106 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EDCN_RESERVED0_SHIFT 17 13107 13108 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_EDCN :: FORCE [16:16] */ 13109 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EDCN_FORCE_MASK 0x00010000 13110 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EDCN_FORCE_ALIGN 0 13111 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EDCN_FORCE_BITS 1 13112 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EDCN_FORCE_SHIFT 16 13113 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EDCN_FORCE_DEFAULT 0x00000000 13114 13115 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_EDCN :: reserved1 [15:13] */ 13116 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EDCN_RESERVED1_MASK 0x0000e000 13117 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EDCN_RESERVED1_ALIGN 0 13118 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EDCN_RESERVED1_BITS 3 13119 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EDCN_RESERVED1_SHIFT 13 13120 13121 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_EDCN :: ADJ_EN [12:12] */ 13122 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EDCN_ADJ_EN_MASK 0x00001000 13123 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EDCN_ADJ_EN_ALIGN 0 13124 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EDCN_ADJ_EN_BITS 1 13125 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EDCN_ADJ_EN_SHIFT 12 13126 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EDCN_ADJ_EN_DEFAULT 0x00000000 13127 13128 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_EDCN :: reserved2 [11:08] */ 13129 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EDCN_RESERVED2_MASK 0x00000f00 13130 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EDCN_RESERVED2_ALIGN 0 13131 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EDCN_RESERVED2_BITS 4 13132 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EDCN_RESERVED2_SHIFT 8 13133 13134 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_EDCN :: VDL_STEP [07:00] */ 13135 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EDCN_VDL_STEP_MASK 0x000000ff 13136 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EDCN_VDL_STEP_ALIGN 0 13137 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EDCN_VDL_STEP_BITS 8 13138 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EDCN_VDL_STEP_SHIFT 0 13139 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EDCN_VDL_STEP_DEFAULT 0x00000000 13140 13141 /*************************************************************************** 13142 *VDL_CONTROL_RD_EN_CS0 - Read channel CS_N[0] read enable VDL control register 13143 */ 13144 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_EN_CS0 :: BUSY [31:31] */ 13145 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS0_BUSY_MASK 0x80000000 13146 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS0_BUSY_ALIGN 0 13147 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS0_BUSY_BITS 1 13148 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS0_BUSY_SHIFT 31 13149 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS0_BUSY_DEFAULT 0x00000000 13150 13151 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_EN_CS0 :: reserved0 [30:17] */ 13152 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS0_RESERVED0_MASK 0x7ffe0000 13153 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS0_RESERVED0_ALIGN 0 13154 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS0_RESERVED0_BITS 14 13155 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS0_RESERVED0_SHIFT 17 13156 13157 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_EN_CS0 :: FORCE [16:16] */ 13158 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS0_FORCE_MASK 0x00010000 13159 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS0_FORCE_ALIGN 0 13160 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS0_FORCE_BITS 1 13161 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS0_FORCE_SHIFT 16 13162 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS0_FORCE_DEFAULT 0x00000000 13163 13164 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_EN_CS0 :: reserved1 [15:13] */ 13165 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS0_RESERVED1_MASK 0x0000e000 13166 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS0_RESERVED1_ALIGN 0 13167 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS0_RESERVED1_BITS 3 13168 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS0_RESERVED1_SHIFT 13 13169 13170 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_EN_CS0 :: ADJ_EN [12:12] */ 13171 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS0_ADJ_EN_MASK 0x00001000 13172 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS0_ADJ_EN_ALIGN 0 13173 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS0_ADJ_EN_BITS 1 13174 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS0_ADJ_EN_SHIFT 12 13175 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS0_ADJ_EN_DEFAULT 0x00000000 13176 13177 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_EN_CS0 :: reserved2 [11:08] */ 13178 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS0_RESERVED2_MASK 0x00000f00 13179 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS0_RESERVED2_ALIGN 0 13180 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS0_RESERVED2_BITS 4 13181 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS0_RESERVED2_SHIFT 8 13182 13183 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_EN_CS0 :: VDL_STEP [07:00] */ 13184 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS0_VDL_STEP_MASK 0x000000ff 13185 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS0_VDL_STEP_ALIGN 0 13186 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS0_VDL_STEP_BITS 8 13187 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS0_VDL_STEP_SHIFT 0 13188 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS0_VDL_STEP_DEFAULT 0x00000000 13189 13190 /*************************************************************************** 13191 *VDL_CONTROL_RD_EN_CS1 - Read channel CS_N[1] read enable VDL control register 13192 */ 13193 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_EN_CS1 :: BUSY [31:31] */ 13194 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS1_BUSY_MASK 0x80000000 13195 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS1_BUSY_ALIGN 0 13196 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS1_BUSY_BITS 1 13197 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS1_BUSY_SHIFT 31 13198 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS1_BUSY_DEFAULT 0x00000000 13199 13200 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_EN_CS1 :: reserved0 [30:17] */ 13201 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS1_RESERVED0_MASK 0x7ffe0000 13202 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS1_RESERVED0_ALIGN 0 13203 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS1_RESERVED0_BITS 14 13204 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS1_RESERVED0_SHIFT 17 13205 13206 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_EN_CS1 :: FORCE [16:16] */ 13207 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS1_FORCE_MASK 0x00010000 13208 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS1_FORCE_ALIGN 0 13209 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS1_FORCE_BITS 1 13210 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS1_FORCE_SHIFT 16 13211 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS1_FORCE_DEFAULT 0x00000000 13212 13213 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_EN_CS1 :: reserved1 [15:13] */ 13214 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS1_RESERVED1_MASK 0x0000e000 13215 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS1_RESERVED1_ALIGN 0 13216 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS1_RESERVED1_BITS 3 13217 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS1_RESERVED1_SHIFT 13 13218 13219 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_EN_CS1 :: ADJ_EN [12:12] */ 13220 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS1_ADJ_EN_MASK 0x00001000 13221 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS1_ADJ_EN_ALIGN 0 13222 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS1_ADJ_EN_BITS 1 13223 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS1_ADJ_EN_SHIFT 12 13224 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS1_ADJ_EN_DEFAULT 0x00000000 13225 13226 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_EN_CS1 :: reserved2 [11:08] */ 13227 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS1_RESERVED2_MASK 0x00000f00 13228 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS1_RESERVED2_ALIGN 0 13229 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS1_RESERVED2_BITS 4 13230 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS1_RESERVED2_SHIFT 8 13231 13232 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CONTROL_RD_EN_CS1 :: VDL_STEP [07:00] */ 13233 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS1_VDL_STEP_MASK 0x000000ff 13234 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS1_VDL_STEP_ALIGN 0 13235 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS1_VDL_STEP_BITS 8 13236 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS1_VDL_STEP_SHIFT 0 13237 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS1_VDL_STEP_DEFAULT 0x00000000 13238 13239 /*************************************************************************** 13240 *VDL_CLK_CONTROL - DDR interface signal Write Leveling CLK VDL control register 13241 */ 13242 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CLK_CONTROL :: BUSY [31:31] */ 13243 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CLK_CONTROL_BUSY_MASK 0x80000000 13244 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CLK_CONTROL_BUSY_ALIGN 0 13245 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CLK_CONTROL_BUSY_BITS 1 13246 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CLK_CONTROL_BUSY_SHIFT 31 13247 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CLK_CONTROL_BUSY_DEFAULT 0x00000000 13248 13249 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CLK_CONTROL :: reserved0 [30:17] */ 13250 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CLK_CONTROL_RESERVED0_MASK 0x7ffe0000 13251 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CLK_CONTROL_RESERVED0_ALIGN 0 13252 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CLK_CONTROL_RESERVED0_BITS 14 13253 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CLK_CONTROL_RESERVED0_SHIFT 17 13254 13255 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CLK_CONTROL :: FORCE [16:16] */ 13256 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CLK_CONTROL_FORCE_MASK 0x00010000 13257 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CLK_CONTROL_FORCE_ALIGN 0 13258 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CLK_CONTROL_FORCE_BITS 1 13259 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CLK_CONTROL_FORCE_SHIFT 16 13260 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CLK_CONTROL_FORCE_DEFAULT 0x00000000 13261 13262 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CLK_CONTROL :: reserved1 [15:13] */ 13263 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CLK_CONTROL_RESERVED1_MASK 0x0000e000 13264 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CLK_CONTROL_RESERVED1_ALIGN 0 13265 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CLK_CONTROL_RESERVED1_BITS 3 13266 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CLK_CONTROL_RESERVED1_SHIFT 13 13267 13268 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CLK_CONTROL :: ADJ_EN [12:12] */ 13269 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CLK_CONTROL_ADJ_EN_MASK 0x00001000 13270 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CLK_CONTROL_ADJ_EN_ALIGN 0 13271 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CLK_CONTROL_ADJ_EN_BITS 1 13272 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CLK_CONTROL_ADJ_EN_SHIFT 12 13273 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CLK_CONTROL_ADJ_EN_DEFAULT 0x00000000 13274 13275 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CLK_CONTROL :: reserved2 [11:09] */ 13276 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CLK_CONTROL_RESERVED2_MASK 0x00000e00 13277 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CLK_CONTROL_RESERVED2_ALIGN 0 13278 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CLK_CONTROL_RESERVED2_BITS 3 13279 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CLK_CONTROL_RESERVED2_SHIFT 9 13280 13281 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_CLK_CONTROL :: VDL_STEP [08:00] */ 13282 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CLK_CONTROL_VDL_STEP_MASK 0x000001ff 13283 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CLK_CONTROL_VDL_STEP_ALIGN 0 13284 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CLK_CONTROL_VDL_STEP_BITS 9 13285 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CLK_CONTROL_VDL_STEP_SHIFT 0 13286 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_CLK_CONTROL_VDL_STEP_DEFAULT 0x00000000 13287 13288 /*************************************************************************** 13289 *VDL_LDE_CONTROL - DDR interface signal Write Leveling Capture Enable VDL control register 13290 */ 13291 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_LDE_CONTROL :: BUSY [31:31] */ 13292 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_LDE_CONTROL_BUSY_MASK 0x80000000 13293 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_LDE_CONTROL_BUSY_ALIGN 0 13294 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_LDE_CONTROL_BUSY_BITS 1 13295 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_LDE_CONTROL_BUSY_SHIFT 31 13296 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_LDE_CONTROL_BUSY_DEFAULT 0x00000000 13297 13298 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_LDE_CONTROL :: reserved0 [30:17] */ 13299 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_LDE_CONTROL_RESERVED0_MASK 0x7ffe0000 13300 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_LDE_CONTROL_RESERVED0_ALIGN 0 13301 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_LDE_CONTROL_RESERVED0_BITS 14 13302 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_LDE_CONTROL_RESERVED0_SHIFT 17 13303 13304 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_LDE_CONTROL :: FORCE [16:16] */ 13305 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_LDE_CONTROL_FORCE_MASK 0x00010000 13306 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_LDE_CONTROL_FORCE_ALIGN 0 13307 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_LDE_CONTROL_FORCE_BITS 1 13308 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_LDE_CONTROL_FORCE_SHIFT 16 13309 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_LDE_CONTROL_FORCE_DEFAULT 0x00000000 13310 13311 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_LDE_CONTROL :: reserved1 [15:13] */ 13312 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_LDE_CONTROL_RESERVED1_MASK 0x0000e000 13313 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_LDE_CONTROL_RESERVED1_ALIGN 0 13314 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_LDE_CONTROL_RESERVED1_BITS 3 13315 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_LDE_CONTROL_RESERVED1_SHIFT 13 13316 13317 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_LDE_CONTROL :: ADJ_EN [12:12] */ 13318 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_LDE_CONTROL_ADJ_EN_MASK 0x00001000 13319 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_LDE_CONTROL_ADJ_EN_ALIGN 0 13320 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_LDE_CONTROL_ADJ_EN_BITS 1 13321 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_LDE_CONTROL_ADJ_EN_SHIFT 12 13322 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_LDE_CONTROL_ADJ_EN_DEFAULT 0x00000000 13323 13324 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_LDE_CONTROL :: reserved2 [11:09] */ 13325 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_LDE_CONTROL_RESERVED2_MASK 0x00000e00 13326 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_LDE_CONTROL_RESERVED2_ALIGN 0 13327 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_LDE_CONTROL_RESERVED2_BITS 3 13328 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_LDE_CONTROL_RESERVED2_SHIFT 9 13329 13330 /* DDR34_E0_PHY_BYTE_LANE_2 :: VDL_LDE_CONTROL :: VDL_STEP [08:00] */ 13331 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_LDE_CONTROL_VDL_STEP_MASK 0x000001ff 13332 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_LDE_CONTROL_VDL_STEP_ALIGN 0 13333 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_LDE_CONTROL_VDL_STEP_BITS 9 13334 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_LDE_CONTROL_VDL_STEP_SHIFT 0 13335 #define DDR34_E0_PHY_BYTE_LANE_2_VDL_LDE_CONTROL_VDL_STEP_DEFAULT 0x00000000 13336 13337 /*************************************************************************** 13338 *RD_EN_DLY_CYC - Read enable bit-clock cycle delay control register 13339 */ 13340 /* DDR34_E0_PHY_BYTE_LANE_2 :: RD_EN_DLY_CYC :: BUSY [31:31] */ 13341 #define DDR34_E0_PHY_BYTE_LANE_2_RD_EN_DLY_CYC_BUSY_MASK 0x80000000 13342 #define DDR34_E0_PHY_BYTE_LANE_2_RD_EN_DLY_CYC_BUSY_ALIGN 0 13343 #define DDR34_E0_PHY_BYTE_LANE_2_RD_EN_DLY_CYC_BUSY_BITS 1 13344 #define DDR34_E0_PHY_BYTE_LANE_2_RD_EN_DLY_CYC_BUSY_SHIFT 31 13345 #define DDR34_E0_PHY_BYTE_LANE_2_RD_EN_DLY_CYC_BUSY_DEFAULT 0x00000000 13346 13347 /* DDR34_E0_PHY_BYTE_LANE_2 :: RD_EN_DLY_CYC :: reserved0 [30:17] */ 13348 #define DDR34_E0_PHY_BYTE_LANE_2_RD_EN_DLY_CYC_RESERVED0_MASK 0x7ffe0000 13349 #define DDR34_E0_PHY_BYTE_LANE_2_RD_EN_DLY_CYC_RESERVED0_ALIGN 0 13350 #define DDR34_E0_PHY_BYTE_LANE_2_RD_EN_DLY_CYC_RESERVED0_BITS 14 13351 #define DDR34_E0_PHY_BYTE_LANE_2_RD_EN_DLY_CYC_RESERVED0_SHIFT 17 13352 13353 /* DDR34_E0_PHY_BYTE_LANE_2 :: RD_EN_DLY_CYC :: FORCE [16:16] */ 13354 #define DDR34_E0_PHY_BYTE_LANE_2_RD_EN_DLY_CYC_FORCE_MASK 0x00010000 13355 #define DDR34_E0_PHY_BYTE_LANE_2_RD_EN_DLY_CYC_FORCE_ALIGN 0 13356 #define DDR34_E0_PHY_BYTE_LANE_2_RD_EN_DLY_CYC_FORCE_BITS 1 13357 #define DDR34_E0_PHY_BYTE_LANE_2_RD_EN_DLY_CYC_FORCE_SHIFT 16 13358 #define DDR34_E0_PHY_BYTE_LANE_2_RD_EN_DLY_CYC_FORCE_DEFAULT 0x00000000 13359 13360 /* DDR34_E0_PHY_BYTE_LANE_2 :: RD_EN_DLY_CYC :: reserved1 [15:08] */ 13361 #define DDR34_E0_PHY_BYTE_LANE_2_RD_EN_DLY_CYC_RESERVED1_MASK 0x0000ff00 13362 #define DDR34_E0_PHY_BYTE_LANE_2_RD_EN_DLY_CYC_RESERVED1_ALIGN 0 13363 #define DDR34_E0_PHY_BYTE_LANE_2_RD_EN_DLY_CYC_RESERVED1_BITS 8 13364 #define DDR34_E0_PHY_BYTE_LANE_2_RD_EN_DLY_CYC_RESERVED1_SHIFT 8 13365 13366 /* DDR34_E0_PHY_BYTE_LANE_2 :: RD_EN_DLY_CYC :: CS1_CYCLES [07:04] */ 13367 #define DDR34_E0_PHY_BYTE_LANE_2_RD_EN_DLY_CYC_CS1_CYCLES_MASK 0x000000f0 13368 #define DDR34_E0_PHY_BYTE_LANE_2_RD_EN_DLY_CYC_CS1_CYCLES_ALIGN 0 13369 #define DDR34_E0_PHY_BYTE_LANE_2_RD_EN_DLY_CYC_CS1_CYCLES_BITS 4 13370 #define DDR34_E0_PHY_BYTE_LANE_2_RD_EN_DLY_CYC_CS1_CYCLES_SHIFT 4 13371 #define DDR34_E0_PHY_BYTE_LANE_2_RD_EN_DLY_CYC_CS1_CYCLES_DEFAULT 0x00000000 13372 13373 /* DDR34_E0_PHY_BYTE_LANE_2 :: RD_EN_DLY_CYC :: CS0_CYCLES [03:00] */ 13374 #define DDR34_E0_PHY_BYTE_LANE_2_RD_EN_DLY_CYC_CS0_CYCLES_MASK 0x0000000f 13375 #define DDR34_E0_PHY_BYTE_LANE_2_RD_EN_DLY_CYC_CS0_CYCLES_ALIGN 0 13376 #define DDR34_E0_PHY_BYTE_LANE_2_RD_EN_DLY_CYC_CS0_CYCLES_BITS 4 13377 #define DDR34_E0_PHY_BYTE_LANE_2_RD_EN_DLY_CYC_CS0_CYCLES_SHIFT 0 13378 #define DDR34_E0_PHY_BYTE_LANE_2_RD_EN_DLY_CYC_CS0_CYCLES_DEFAULT 0x00000000 13379 13380 /*************************************************************************** 13381 *WR_CHAN_DLY_CYC - Write leveling bit-clock cycle delay control register 13382 */ 13383 /* DDR34_E0_PHY_BYTE_LANE_2 :: WR_CHAN_DLY_CYC :: BUSY [31:31] */ 13384 #define DDR34_E0_PHY_BYTE_LANE_2_WR_CHAN_DLY_CYC_BUSY_MASK 0x80000000 13385 #define DDR34_E0_PHY_BYTE_LANE_2_WR_CHAN_DLY_CYC_BUSY_ALIGN 0 13386 #define DDR34_E0_PHY_BYTE_LANE_2_WR_CHAN_DLY_CYC_BUSY_BITS 1 13387 #define DDR34_E0_PHY_BYTE_LANE_2_WR_CHAN_DLY_CYC_BUSY_SHIFT 31 13388 #define DDR34_E0_PHY_BYTE_LANE_2_WR_CHAN_DLY_CYC_BUSY_DEFAULT 0x00000000 13389 13390 /* DDR34_E0_PHY_BYTE_LANE_2 :: WR_CHAN_DLY_CYC :: reserved0 [30:17] */ 13391 #define DDR34_E0_PHY_BYTE_LANE_2_WR_CHAN_DLY_CYC_RESERVED0_MASK 0x7ffe0000 13392 #define DDR34_E0_PHY_BYTE_LANE_2_WR_CHAN_DLY_CYC_RESERVED0_ALIGN 0 13393 #define DDR34_E0_PHY_BYTE_LANE_2_WR_CHAN_DLY_CYC_RESERVED0_BITS 14 13394 #define DDR34_E0_PHY_BYTE_LANE_2_WR_CHAN_DLY_CYC_RESERVED0_SHIFT 17 13395 13396 /* DDR34_E0_PHY_BYTE_LANE_2 :: WR_CHAN_DLY_CYC :: FORCE [16:16] */ 13397 #define DDR34_E0_PHY_BYTE_LANE_2_WR_CHAN_DLY_CYC_FORCE_MASK 0x00010000 13398 #define DDR34_E0_PHY_BYTE_LANE_2_WR_CHAN_DLY_CYC_FORCE_ALIGN 0 13399 #define DDR34_E0_PHY_BYTE_LANE_2_WR_CHAN_DLY_CYC_FORCE_BITS 1 13400 #define DDR34_E0_PHY_BYTE_LANE_2_WR_CHAN_DLY_CYC_FORCE_SHIFT 16 13401 #define DDR34_E0_PHY_BYTE_LANE_2_WR_CHAN_DLY_CYC_FORCE_DEFAULT 0x00000000 13402 13403 /* DDR34_E0_PHY_BYTE_LANE_2 :: WR_CHAN_DLY_CYC :: reserved1 [15:03] */ 13404 #define DDR34_E0_PHY_BYTE_LANE_2_WR_CHAN_DLY_CYC_RESERVED1_MASK 0x0000fff8 13405 #define DDR34_E0_PHY_BYTE_LANE_2_WR_CHAN_DLY_CYC_RESERVED1_ALIGN 0 13406 #define DDR34_E0_PHY_BYTE_LANE_2_WR_CHAN_DLY_CYC_RESERVED1_BITS 13 13407 #define DDR34_E0_PHY_BYTE_LANE_2_WR_CHAN_DLY_CYC_RESERVED1_SHIFT 3 13408 13409 /* DDR34_E0_PHY_BYTE_LANE_2 :: WR_CHAN_DLY_CYC :: CYCLES [02:00] */ 13410 #define DDR34_E0_PHY_BYTE_LANE_2_WR_CHAN_DLY_CYC_CYCLES_MASK 0x00000007 13411 #define DDR34_E0_PHY_BYTE_LANE_2_WR_CHAN_DLY_CYC_CYCLES_ALIGN 0 13412 #define DDR34_E0_PHY_BYTE_LANE_2_WR_CHAN_DLY_CYC_CYCLES_BITS 3 13413 #define DDR34_E0_PHY_BYTE_LANE_2_WR_CHAN_DLY_CYC_CYCLES_SHIFT 0 13414 #define DDR34_E0_PHY_BYTE_LANE_2_WR_CHAN_DLY_CYC_CYCLES_DEFAULT 0x00000000 13415 13416 /*************************************************************************** 13417 *READ_CONTROL - Read channel datapath control register 13418 */ 13419 /* DDR34_E0_PHY_BYTE_LANE_2 :: READ_CONTROL :: reserved0 [31:05] */ 13420 #define DDR34_E0_PHY_BYTE_LANE_2_READ_CONTROL_RESERVED0_MASK 0xffffffe0 13421 #define DDR34_E0_PHY_BYTE_LANE_2_READ_CONTROL_RESERVED0_ALIGN 0 13422 #define DDR34_E0_PHY_BYTE_LANE_2_READ_CONTROL_RESERVED0_BITS 27 13423 #define DDR34_E0_PHY_BYTE_LANE_2_READ_CONTROL_RESERVED0_SHIFT 5 13424 13425 /* DDR34_E0_PHY_BYTE_LANE_2 :: READ_CONTROL :: MODE [04:04] */ 13426 #define DDR34_E0_PHY_BYTE_LANE_2_READ_CONTROL_MODE_MASK 0x00000010 13427 #define DDR34_E0_PHY_BYTE_LANE_2_READ_CONTROL_MODE_ALIGN 0 13428 #define DDR34_E0_PHY_BYTE_LANE_2_READ_CONTROL_MODE_BITS 1 13429 #define DDR34_E0_PHY_BYTE_LANE_2_READ_CONTROL_MODE_SHIFT 4 13430 #define DDR34_E0_PHY_BYTE_LANE_2_READ_CONTROL_MODE_DEFAULT 0x00000001 13431 13432 /* DDR34_E0_PHY_BYTE_LANE_2 :: READ_CONTROL :: reserved1 [03:03] */ 13433 #define DDR34_E0_PHY_BYTE_LANE_2_READ_CONTROL_RESERVED1_MASK 0x00000008 13434 #define DDR34_E0_PHY_BYTE_LANE_2_READ_CONTROL_RESERVED1_ALIGN 0 13435 #define DDR34_E0_PHY_BYTE_LANE_2_READ_CONTROL_RESERVED1_BITS 1 13436 #define DDR34_E0_PHY_BYTE_LANE_2_READ_CONTROL_RESERVED1_SHIFT 3 13437 13438 /* DDR34_E0_PHY_BYTE_LANE_2 :: READ_CONTROL :: RD_DATA_DLY [02:00] */ 13439 #define DDR34_E0_PHY_BYTE_LANE_2_READ_CONTROL_RD_DATA_DLY_MASK 0x00000007 13440 #define DDR34_E0_PHY_BYTE_LANE_2_READ_CONTROL_RD_DATA_DLY_ALIGN 0 13441 #define DDR34_E0_PHY_BYTE_LANE_2_READ_CONTROL_RD_DATA_DLY_BITS 3 13442 #define DDR34_E0_PHY_BYTE_LANE_2_READ_CONTROL_RD_DATA_DLY_SHIFT 0 13443 #define DDR34_E0_PHY_BYTE_LANE_2_READ_CONTROL_RD_DATA_DLY_DEFAULT 0x00000007 13444 13445 /*************************************************************************** 13446 *READ_FIFO_ADDR - Read fifo addresss pointer register 13447 */ 13448 /* DDR34_E0_PHY_BYTE_LANE_2 :: READ_FIFO_ADDR :: reserved0 [31:03] */ 13449 #define DDR34_E0_PHY_BYTE_LANE_2_READ_FIFO_ADDR_RESERVED0_MASK 0xfffffff8 13450 #define DDR34_E0_PHY_BYTE_LANE_2_READ_FIFO_ADDR_RESERVED0_ALIGN 0 13451 #define DDR34_E0_PHY_BYTE_LANE_2_READ_FIFO_ADDR_RESERVED0_BITS 29 13452 #define DDR34_E0_PHY_BYTE_LANE_2_READ_FIFO_ADDR_RESERVED0_SHIFT 3 13453 13454 /* DDR34_E0_PHY_BYTE_LANE_2 :: READ_FIFO_ADDR :: ADDR [02:00] */ 13455 #define DDR34_E0_PHY_BYTE_LANE_2_READ_FIFO_ADDR_ADDR_MASK 0x00000007 13456 #define DDR34_E0_PHY_BYTE_LANE_2_READ_FIFO_ADDR_ADDR_ALIGN 0 13457 #define DDR34_E0_PHY_BYTE_LANE_2_READ_FIFO_ADDR_ADDR_BITS 3 13458 #define DDR34_E0_PHY_BYTE_LANE_2_READ_FIFO_ADDR_ADDR_SHIFT 0 13459 #define DDR34_E0_PHY_BYTE_LANE_2_READ_FIFO_ADDR_ADDR_DEFAULT 0x00000000 13460 13461 /*************************************************************************** 13462 *READ_FIFO_DATA - Read fifo data register 13463 */ 13464 /* DDR34_E0_PHY_BYTE_LANE_2 :: READ_FIFO_DATA :: DATA [31:00] */ 13465 #define DDR34_E0_PHY_BYTE_LANE_2_READ_FIFO_DATA_DATA_MASK 0xffffffff 13466 #define DDR34_E0_PHY_BYTE_LANE_2_READ_FIFO_DATA_DATA_ALIGN 0 13467 #define DDR34_E0_PHY_BYTE_LANE_2_READ_FIFO_DATA_DATA_BITS 32 13468 #define DDR34_E0_PHY_BYTE_LANE_2_READ_FIFO_DATA_DATA_SHIFT 0 13469 13470 /*************************************************************************** 13471 *READ_FIFO_DM_DBI - Read fifo dm/dbi register 13472 */ 13473 /* DDR34_E0_PHY_BYTE_LANE_2 :: READ_FIFO_DM_DBI :: reserved0 [31:04] */ 13474 #define DDR34_E0_PHY_BYTE_LANE_2_READ_FIFO_DM_DBI_RESERVED0_MASK 0xfffffff0 13475 #define DDR34_E0_PHY_BYTE_LANE_2_READ_FIFO_DM_DBI_RESERVED0_ALIGN 0 13476 #define DDR34_E0_PHY_BYTE_LANE_2_READ_FIFO_DM_DBI_RESERVED0_BITS 28 13477 #define DDR34_E0_PHY_BYTE_LANE_2_READ_FIFO_DM_DBI_RESERVED0_SHIFT 4 13478 13479 /* DDR34_E0_PHY_BYTE_LANE_2 :: READ_FIFO_DM_DBI :: DM_DBI [03:00] */ 13480 #define DDR34_E0_PHY_BYTE_LANE_2_READ_FIFO_DM_DBI_DM_DBI_MASK 0x0000000f 13481 #define DDR34_E0_PHY_BYTE_LANE_2_READ_FIFO_DM_DBI_DM_DBI_ALIGN 0 13482 #define DDR34_E0_PHY_BYTE_LANE_2_READ_FIFO_DM_DBI_DM_DBI_BITS 4 13483 #define DDR34_E0_PHY_BYTE_LANE_2_READ_FIFO_DM_DBI_DM_DBI_SHIFT 0 13484 13485 /*************************************************************************** 13486 *READ_FIFO_STATUS - Read fifo status register 13487 */ 13488 /* DDR34_E0_PHY_BYTE_LANE_2 :: READ_FIFO_STATUS :: reserved0 [31:02] */ 13489 #define DDR34_E0_PHY_BYTE_LANE_2_READ_FIFO_STATUS_RESERVED0_MASK 0xfffffffc 13490 #define DDR34_E0_PHY_BYTE_LANE_2_READ_FIFO_STATUS_RESERVED0_ALIGN 0 13491 #define DDR34_E0_PHY_BYTE_LANE_2_READ_FIFO_STATUS_RESERVED0_BITS 30 13492 #define DDR34_E0_PHY_BYTE_LANE_2_READ_FIFO_STATUS_RESERVED0_SHIFT 2 13493 13494 /* DDR34_E0_PHY_BYTE_LANE_2 :: READ_FIFO_STATUS :: OVERFLOW [01:01] */ 13495 #define DDR34_E0_PHY_BYTE_LANE_2_READ_FIFO_STATUS_OVERFLOW_MASK 0x00000002 13496 #define DDR34_E0_PHY_BYTE_LANE_2_READ_FIFO_STATUS_OVERFLOW_ALIGN 0 13497 #define DDR34_E0_PHY_BYTE_LANE_2_READ_FIFO_STATUS_OVERFLOW_BITS 1 13498 #define DDR34_E0_PHY_BYTE_LANE_2_READ_FIFO_STATUS_OVERFLOW_SHIFT 1 13499 #define DDR34_E0_PHY_BYTE_LANE_2_READ_FIFO_STATUS_OVERFLOW_DEFAULT 0x00000000 13500 13501 /* DDR34_E0_PHY_BYTE_LANE_2 :: READ_FIFO_STATUS :: UNDERFLOW [00:00] */ 13502 #define DDR34_E0_PHY_BYTE_LANE_2_READ_FIFO_STATUS_UNDERFLOW_MASK 0x00000001 13503 #define DDR34_E0_PHY_BYTE_LANE_2_READ_FIFO_STATUS_UNDERFLOW_ALIGN 0 13504 #define DDR34_E0_PHY_BYTE_LANE_2_READ_FIFO_STATUS_UNDERFLOW_BITS 1 13505 #define DDR34_E0_PHY_BYTE_LANE_2_READ_FIFO_STATUS_UNDERFLOW_SHIFT 0 13506 #define DDR34_E0_PHY_BYTE_LANE_2_READ_FIFO_STATUS_UNDERFLOW_DEFAULT 0x00000000 13507 13508 /*************************************************************************** 13509 *READ_FIFO_CLEAR - Read fifo status clear register 13510 */ 13511 /* DDR34_E0_PHY_BYTE_LANE_2 :: READ_FIFO_CLEAR :: reserved0 [31:01] */ 13512 #define DDR34_E0_PHY_BYTE_LANE_2_READ_FIFO_CLEAR_RESERVED0_MASK 0xfffffffe 13513 #define DDR34_E0_PHY_BYTE_LANE_2_READ_FIFO_CLEAR_RESERVED0_ALIGN 0 13514 #define DDR34_E0_PHY_BYTE_LANE_2_READ_FIFO_CLEAR_RESERVED0_BITS 31 13515 #define DDR34_E0_PHY_BYTE_LANE_2_READ_FIFO_CLEAR_RESERVED0_SHIFT 1 13516 13517 /* DDR34_E0_PHY_BYTE_LANE_2 :: READ_FIFO_CLEAR :: CLEAR [00:00] */ 13518 #define DDR34_E0_PHY_BYTE_LANE_2_READ_FIFO_CLEAR_CLEAR_MASK 0x00000001 13519 #define DDR34_E0_PHY_BYTE_LANE_2_READ_FIFO_CLEAR_CLEAR_ALIGN 0 13520 #define DDR34_E0_PHY_BYTE_LANE_2_READ_FIFO_CLEAR_CLEAR_BITS 1 13521 #define DDR34_E0_PHY_BYTE_LANE_2_READ_FIFO_CLEAR_CLEAR_SHIFT 0 13522 #define DDR34_E0_PHY_BYTE_LANE_2_READ_FIFO_CLEAR_CLEAR_DEFAULT 0x00000000 13523 13524 /*************************************************************************** 13525 *IDLE_PAD_CONTROL - Idle mode SSTL pad control register 13526 */ 13527 /* DDR34_E0_PHY_BYTE_LANE_2 :: IDLE_PAD_CONTROL :: IDLE [31:31] */ 13528 #define DDR34_E0_PHY_BYTE_LANE_2_IDLE_PAD_CONTROL_IDLE_MASK 0x80000000 13529 #define DDR34_E0_PHY_BYTE_LANE_2_IDLE_PAD_CONTROL_IDLE_ALIGN 0 13530 #define DDR34_E0_PHY_BYTE_LANE_2_IDLE_PAD_CONTROL_IDLE_BITS 1 13531 #define DDR34_E0_PHY_BYTE_LANE_2_IDLE_PAD_CONTROL_IDLE_SHIFT 31 13532 #define DDR34_E0_PHY_BYTE_LANE_2_IDLE_PAD_CONTROL_IDLE_DEFAULT 0x00000000 13533 13534 /* DDR34_E0_PHY_BYTE_LANE_2 :: IDLE_PAD_CONTROL :: reserved0 [30:20] */ 13535 #define DDR34_E0_PHY_BYTE_LANE_2_IDLE_PAD_CONTROL_RESERVED0_MASK 0x7ff00000 13536 #define DDR34_E0_PHY_BYTE_LANE_2_IDLE_PAD_CONTROL_RESERVED0_ALIGN 0 13537 #define DDR34_E0_PHY_BYTE_LANE_2_IDLE_PAD_CONTROL_RESERVED0_BITS 11 13538 #define DDR34_E0_PHY_BYTE_LANE_2_IDLE_PAD_CONTROL_RESERVED0_SHIFT 20 13539 13540 /* DDR34_E0_PHY_BYTE_LANE_2 :: IDLE_PAD_CONTROL :: AUTO_DQ_RXENB_MODE [19:18] */ 13541 #define DDR34_E0_PHY_BYTE_LANE_2_IDLE_PAD_CONTROL_AUTO_DQ_RXENB_MODE_MASK 0x000c0000 13542 #define DDR34_E0_PHY_BYTE_LANE_2_IDLE_PAD_CONTROL_AUTO_DQ_RXENB_MODE_ALIGN 0 13543 #define DDR34_E0_PHY_BYTE_LANE_2_IDLE_PAD_CONTROL_AUTO_DQ_RXENB_MODE_BITS 2 13544 #define DDR34_E0_PHY_BYTE_LANE_2_IDLE_PAD_CONTROL_AUTO_DQ_RXENB_MODE_SHIFT 18 13545 #define DDR34_E0_PHY_BYTE_LANE_2_IDLE_PAD_CONTROL_AUTO_DQ_RXENB_MODE_DEFAULT 0x00000001 13546 13547 /* DDR34_E0_PHY_BYTE_LANE_2 :: IDLE_PAD_CONTROL :: AUTO_DQ_IDDQ_MODE [17:16] */ 13548 #define DDR34_E0_PHY_BYTE_LANE_2_IDLE_PAD_CONTROL_AUTO_DQ_IDDQ_MODE_MASK 0x00030000 13549 #define DDR34_E0_PHY_BYTE_LANE_2_IDLE_PAD_CONTROL_AUTO_DQ_IDDQ_MODE_ALIGN 0 13550 #define DDR34_E0_PHY_BYTE_LANE_2_IDLE_PAD_CONTROL_AUTO_DQ_IDDQ_MODE_BITS 2 13551 #define DDR34_E0_PHY_BYTE_LANE_2_IDLE_PAD_CONTROL_AUTO_DQ_IDDQ_MODE_SHIFT 16 13552 #define DDR34_E0_PHY_BYTE_LANE_2_IDLE_PAD_CONTROL_AUTO_DQ_IDDQ_MODE_DEFAULT 0x00000001 13553 13554 /* DDR34_E0_PHY_BYTE_LANE_2 :: IDLE_PAD_CONTROL :: reserved_for_padding1 [15:15] */ 13555 #define DDR34_E0_PHY_BYTE_LANE_2_IDLE_PAD_CONTROL_RESERVED_for_padding1_MASK 0x00008000 13556 #define DDR34_E0_PHY_BYTE_LANE_2_IDLE_PAD_CONTROL_RESERVED_for_padding1_ALIGN 0 13557 #define DDR34_E0_PHY_BYTE_LANE_2_IDLE_PAD_CONTROL_RESERVED_for_padding1_BITS 1 13558 #define DDR34_E0_PHY_BYTE_LANE_2_IDLE_PAD_CONTROL_RESERVED_for_padding1_SHIFT 15 13559 13560 /* DDR34_E0_PHY_BYTE_LANE_2 :: IDLE_PAD_CONTROL :: IO_IDLE_ENABLE [14:04] */ 13561 #define DDR34_E0_PHY_BYTE_LANE_2_IDLE_PAD_CONTROL_IO_IDLE_ENABLE_MASK 0x00007ff0 13562 #define DDR34_E0_PHY_BYTE_LANE_2_IDLE_PAD_CONTROL_IO_IDLE_ENABLE_ALIGN 0 13563 #define DDR34_E0_PHY_BYTE_LANE_2_IDLE_PAD_CONTROL_IO_IDLE_ENABLE_BITS 11 13564 #define DDR34_E0_PHY_BYTE_LANE_2_IDLE_PAD_CONTROL_IO_IDLE_ENABLE_SHIFT 4 13565 #define DDR34_E0_PHY_BYTE_LANE_2_IDLE_PAD_CONTROL_IO_IDLE_ENABLE_DEFAULT 0x00000000 13566 13567 /* DDR34_E0_PHY_BYTE_LANE_2 :: IDLE_PAD_CONTROL :: RXENB [03:03] */ 13568 #define DDR34_E0_PHY_BYTE_LANE_2_IDLE_PAD_CONTROL_RXENB_MASK 0x00000008 13569 #define DDR34_E0_PHY_BYTE_LANE_2_IDLE_PAD_CONTROL_RXENB_ALIGN 0 13570 #define DDR34_E0_PHY_BYTE_LANE_2_IDLE_PAD_CONTROL_RXENB_BITS 1 13571 #define DDR34_E0_PHY_BYTE_LANE_2_IDLE_PAD_CONTROL_RXENB_SHIFT 3 13572 #define DDR34_E0_PHY_BYTE_LANE_2_IDLE_PAD_CONTROL_RXENB_DEFAULT 0x00000001 13573 13574 /* DDR34_E0_PHY_BYTE_LANE_2 :: IDLE_PAD_CONTROL :: IDDQ [02:02] */ 13575 #define DDR34_E0_PHY_BYTE_LANE_2_IDLE_PAD_CONTROL_IDDQ_MASK 0x00000004 13576 #define DDR34_E0_PHY_BYTE_LANE_2_IDLE_PAD_CONTROL_IDDQ_ALIGN 0 13577 #define DDR34_E0_PHY_BYTE_LANE_2_IDLE_PAD_CONTROL_IDDQ_BITS 1 13578 #define DDR34_E0_PHY_BYTE_LANE_2_IDLE_PAD_CONTROL_IDDQ_SHIFT 2 13579 #define DDR34_E0_PHY_BYTE_LANE_2_IDLE_PAD_CONTROL_IDDQ_DEFAULT 0x00000000 13580 13581 /* DDR34_E0_PHY_BYTE_LANE_2 :: IDLE_PAD_CONTROL :: DOUT_N [01:01] */ 13582 #define DDR34_E0_PHY_BYTE_LANE_2_IDLE_PAD_CONTROL_DOUT_N_MASK 0x00000002 13583 #define DDR34_E0_PHY_BYTE_LANE_2_IDLE_PAD_CONTROL_DOUT_N_ALIGN 0 13584 #define DDR34_E0_PHY_BYTE_LANE_2_IDLE_PAD_CONTROL_DOUT_N_BITS 1 13585 #define DDR34_E0_PHY_BYTE_LANE_2_IDLE_PAD_CONTROL_DOUT_N_SHIFT 1 13586 #define DDR34_E0_PHY_BYTE_LANE_2_IDLE_PAD_CONTROL_DOUT_N_DEFAULT 0x00000001 13587 13588 /* DDR34_E0_PHY_BYTE_LANE_2 :: IDLE_PAD_CONTROL :: DOUT_P [00:00] */ 13589 #define DDR34_E0_PHY_BYTE_LANE_2_IDLE_PAD_CONTROL_DOUT_P_MASK 0x00000001 13590 #define DDR34_E0_PHY_BYTE_LANE_2_IDLE_PAD_CONTROL_DOUT_P_ALIGN 0 13591 #define DDR34_E0_PHY_BYTE_LANE_2_IDLE_PAD_CONTROL_DOUT_P_BITS 1 13592 #define DDR34_E0_PHY_BYTE_LANE_2_IDLE_PAD_CONTROL_DOUT_P_SHIFT 0 13593 #define DDR34_E0_PHY_BYTE_LANE_2_IDLE_PAD_CONTROL_DOUT_P_DEFAULT 0x00000000 13594 13595 /*************************************************************************** 13596 *DRIVE_PAD_CTL - SSTL pad drive characteristics control register 13597 */ 13598 /* DDR34_E0_PHY_BYTE_LANE_2 :: DRIVE_PAD_CTL :: reserved0 [31:30] */ 13599 #define DDR34_E0_PHY_BYTE_LANE_2_DRIVE_PAD_CTL_RESERVED0_MASK 0xc0000000 13600 #define DDR34_E0_PHY_BYTE_LANE_2_DRIVE_PAD_CTL_RESERVED0_ALIGN 0 13601 #define DDR34_E0_PHY_BYTE_LANE_2_DRIVE_PAD_CTL_RESERVED0_BITS 2 13602 #define DDR34_E0_PHY_BYTE_LANE_2_DRIVE_PAD_CTL_RESERVED0_SHIFT 30 13603 13604 /* DDR34_E0_PHY_BYTE_LANE_2 :: DRIVE_PAD_CTL :: BL_PD_IDLE_STRENGTH [29:25] */ 13605 #define DDR34_E0_PHY_BYTE_LANE_2_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_MASK 0x3e000000 13606 #define DDR34_E0_PHY_BYTE_LANE_2_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_ALIGN 0 13607 #define DDR34_E0_PHY_BYTE_LANE_2_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_BITS 5 13608 #define DDR34_E0_PHY_BYTE_LANE_2_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_SHIFT 25 13609 #define DDR34_E0_PHY_BYTE_LANE_2_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_DEFAULT 0x0000001f 13610 13611 /* DDR34_E0_PHY_BYTE_LANE_2 :: DRIVE_PAD_CTL :: BL_ND_IDLE_STRENGTH [24:20] */ 13612 #define DDR34_E0_PHY_BYTE_LANE_2_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_MASK 0x01f00000 13613 #define DDR34_E0_PHY_BYTE_LANE_2_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_ALIGN 0 13614 #define DDR34_E0_PHY_BYTE_LANE_2_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_BITS 5 13615 #define DDR34_E0_PHY_BYTE_LANE_2_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_SHIFT 20 13616 #define DDR34_E0_PHY_BYTE_LANE_2_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_DEFAULT 0x0000001f 13617 13618 /* DDR34_E0_PHY_BYTE_LANE_2 :: DRIVE_PAD_CTL :: BL_PD_TERM_STRENGTH [19:15] */ 13619 #define DDR34_E0_PHY_BYTE_LANE_2_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_MASK 0x000f8000 13620 #define DDR34_E0_PHY_BYTE_LANE_2_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_ALIGN 0 13621 #define DDR34_E0_PHY_BYTE_LANE_2_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_BITS 5 13622 #define DDR34_E0_PHY_BYTE_LANE_2_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_SHIFT 15 13623 #define DDR34_E0_PHY_BYTE_LANE_2_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_DEFAULT 0x00000006 13624 13625 /* DDR34_E0_PHY_BYTE_LANE_2 :: DRIVE_PAD_CTL :: BL_ND_TERM_STRENGTH [14:10] */ 13626 #define DDR34_E0_PHY_BYTE_LANE_2_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_MASK 0x00007c00 13627 #define DDR34_E0_PHY_BYTE_LANE_2_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_ALIGN 0 13628 #define DDR34_E0_PHY_BYTE_LANE_2_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_BITS 5 13629 #define DDR34_E0_PHY_BYTE_LANE_2_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_SHIFT 10 13630 #define DDR34_E0_PHY_BYTE_LANE_2_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_DEFAULT 0x00000006 13631 13632 /* DDR34_E0_PHY_BYTE_LANE_2 :: DRIVE_PAD_CTL :: BL_PD_STRENGTH [09:05] */ 13633 #define DDR34_E0_PHY_BYTE_LANE_2_DRIVE_PAD_CTL_BL_PD_STRENGTH_MASK 0x000003e0 13634 #define DDR34_E0_PHY_BYTE_LANE_2_DRIVE_PAD_CTL_BL_PD_STRENGTH_ALIGN 0 13635 #define DDR34_E0_PHY_BYTE_LANE_2_DRIVE_PAD_CTL_BL_PD_STRENGTH_BITS 5 13636 #define DDR34_E0_PHY_BYTE_LANE_2_DRIVE_PAD_CTL_BL_PD_STRENGTH_SHIFT 5 13637 #define DDR34_E0_PHY_BYTE_LANE_2_DRIVE_PAD_CTL_BL_PD_STRENGTH_DEFAULT 0x0000001f 13638 13639 /* DDR34_E0_PHY_BYTE_LANE_2 :: DRIVE_PAD_CTL :: BL_ND_STRENGTH [04:00] */ 13640 #define DDR34_E0_PHY_BYTE_LANE_2_DRIVE_PAD_CTL_BL_ND_STRENGTH_MASK 0x0000001f 13641 #define DDR34_E0_PHY_BYTE_LANE_2_DRIVE_PAD_CTL_BL_ND_STRENGTH_ALIGN 0 13642 #define DDR34_E0_PHY_BYTE_LANE_2_DRIVE_PAD_CTL_BL_ND_STRENGTH_BITS 5 13643 #define DDR34_E0_PHY_BYTE_LANE_2_DRIVE_PAD_CTL_BL_ND_STRENGTH_SHIFT 0 13644 #define DDR34_E0_PHY_BYTE_LANE_2_DRIVE_PAD_CTL_BL_ND_STRENGTH_DEFAULT 0x0000001f 13645 13646 /*************************************************************************** 13647 *RD_EN_DRIVE_PAD_CTL - SSTL read enable pad drive characteristics control register 13648 */ 13649 /* DDR34_E0_PHY_BYTE_LANE_2 :: RD_EN_DRIVE_PAD_CTL :: reserved0 [31:20] */ 13650 #define DDR34_E0_PHY_BYTE_LANE_2_RD_EN_DRIVE_PAD_CTL_RESERVED0_MASK 0xfff00000 13651 #define DDR34_E0_PHY_BYTE_LANE_2_RD_EN_DRIVE_PAD_CTL_RESERVED0_ALIGN 0 13652 #define DDR34_E0_PHY_BYTE_LANE_2_RD_EN_DRIVE_PAD_CTL_RESERVED0_BITS 12 13653 #define DDR34_E0_PHY_BYTE_LANE_2_RD_EN_DRIVE_PAD_CTL_RESERVED0_SHIFT 20 13654 13655 /* DDR34_E0_PHY_BYTE_LANE_2 :: RD_EN_DRIVE_PAD_CTL :: EDC_RD_EN_PD_STRENGTH [19:15] */ 13656 #define DDR34_E0_PHY_BYTE_LANE_2_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_PD_STRENGTH_MASK 0x000f8000 13657 #define DDR34_E0_PHY_BYTE_LANE_2_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_PD_STRENGTH_ALIGN 0 13658 #define DDR34_E0_PHY_BYTE_LANE_2_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_PD_STRENGTH_BITS 5 13659 #define DDR34_E0_PHY_BYTE_LANE_2_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_PD_STRENGTH_SHIFT 15 13660 #define DDR34_E0_PHY_BYTE_LANE_2_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_PD_STRENGTH_DEFAULT 0x0000001f 13661 13662 /* DDR34_E0_PHY_BYTE_LANE_2 :: RD_EN_DRIVE_PAD_CTL :: EDC_RD_EN_ND_STRENGTH [14:10] */ 13663 #define DDR34_E0_PHY_BYTE_LANE_2_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_ND_STRENGTH_MASK 0x00007c00 13664 #define DDR34_E0_PHY_BYTE_LANE_2_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_ND_STRENGTH_ALIGN 0 13665 #define DDR34_E0_PHY_BYTE_LANE_2_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_ND_STRENGTH_BITS 5 13666 #define DDR34_E0_PHY_BYTE_LANE_2_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_ND_STRENGTH_SHIFT 10 13667 #define DDR34_E0_PHY_BYTE_LANE_2_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_ND_STRENGTH_DEFAULT 0x0000001f 13668 13669 /* DDR34_E0_PHY_BYTE_LANE_2 :: RD_EN_DRIVE_PAD_CTL :: BL_RD_EN_PD_STRENGTH [09:05] */ 13670 #define DDR34_E0_PHY_BYTE_LANE_2_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_PD_STRENGTH_MASK 0x000003e0 13671 #define DDR34_E0_PHY_BYTE_LANE_2_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_PD_STRENGTH_ALIGN 0 13672 #define DDR34_E0_PHY_BYTE_LANE_2_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_PD_STRENGTH_BITS 5 13673 #define DDR34_E0_PHY_BYTE_LANE_2_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_PD_STRENGTH_SHIFT 5 13674 #define DDR34_E0_PHY_BYTE_LANE_2_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_PD_STRENGTH_DEFAULT 0x0000001f 13675 13676 /* DDR34_E0_PHY_BYTE_LANE_2 :: RD_EN_DRIVE_PAD_CTL :: BL_RD_EN_ND_STRENGTH [04:00] */ 13677 #define DDR34_E0_PHY_BYTE_LANE_2_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_ND_STRENGTH_MASK 0x0000001f 13678 #define DDR34_E0_PHY_BYTE_LANE_2_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_ND_STRENGTH_ALIGN 0 13679 #define DDR34_E0_PHY_BYTE_LANE_2_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_ND_STRENGTH_BITS 5 13680 #define DDR34_E0_PHY_BYTE_LANE_2_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_ND_STRENGTH_SHIFT 0 13681 #define DDR34_E0_PHY_BYTE_LANE_2_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_ND_STRENGTH_DEFAULT 0x0000001f 13682 13683 /*************************************************************************** 13684 *STATIC_PAD_CTL - pad rx and tx characteristics control register 13685 */ 13686 /* DDR34_E0_PHY_BYTE_LANE_2 :: STATIC_PAD_CTL :: reserved0 [31:21] */ 13687 #define DDR34_E0_PHY_BYTE_LANE_2_STATIC_PAD_CTL_RESERVED0_MASK 0xffe00000 13688 #define DDR34_E0_PHY_BYTE_LANE_2_STATIC_PAD_CTL_RESERVED0_ALIGN 0 13689 #define DDR34_E0_PHY_BYTE_LANE_2_STATIC_PAD_CTL_RESERVED0_BITS 11 13690 #define DDR34_E0_PHY_BYTE_LANE_2_STATIC_PAD_CTL_RESERVED0_SHIFT 21 13691 13692 /* DDR34_E0_PHY_BYTE_LANE_2 :: STATIC_PAD_CTL :: DQS_MODE [20:20] */ 13693 #define DDR34_E0_PHY_BYTE_LANE_2_STATIC_PAD_CTL_DQS_MODE_MASK 0x00100000 13694 #define DDR34_E0_PHY_BYTE_LANE_2_STATIC_PAD_CTL_DQS_MODE_ALIGN 0 13695 #define DDR34_E0_PHY_BYTE_LANE_2_STATIC_PAD_CTL_DQS_MODE_BITS 1 13696 #define DDR34_E0_PHY_BYTE_LANE_2_STATIC_PAD_CTL_DQS_MODE_SHIFT 20 13697 #define DDR34_E0_PHY_BYTE_LANE_2_STATIC_PAD_CTL_DQS_MODE_DEFAULT 0x00000000 13698 13699 /* DDR34_E0_PHY_BYTE_LANE_2 :: STATIC_PAD_CTL :: reserved1 [19:18] */ 13700 #define DDR34_E0_PHY_BYTE_LANE_2_STATIC_PAD_CTL_RESERVED1_MASK 0x000c0000 13701 #define DDR34_E0_PHY_BYTE_LANE_2_STATIC_PAD_CTL_RESERVED1_ALIGN 0 13702 #define DDR34_E0_PHY_BYTE_LANE_2_STATIC_PAD_CTL_RESERVED1_BITS 2 13703 #define DDR34_E0_PHY_BYTE_LANE_2_STATIC_PAD_CTL_RESERVED1_SHIFT 18 13704 13705 /* DDR34_E0_PHY_BYTE_LANE_2 :: STATIC_PAD_CTL :: EDC_MODE [17:16] */ 13706 #define DDR34_E0_PHY_BYTE_LANE_2_STATIC_PAD_CTL_EDC_MODE_MASK 0x00030000 13707 #define DDR34_E0_PHY_BYTE_LANE_2_STATIC_PAD_CTL_EDC_MODE_ALIGN 0 13708 #define DDR34_E0_PHY_BYTE_LANE_2_STATIC_PAD_CTL_EDC_MODE_BITS 2 13709 #define DDR34_E0_PHY_BYTE_LANE_2_STATIC_PAD_CTL_EDC_MODE_SHIFT 16 13710 #define DDR34_E0_PHY_BYTE_LANE_2_STATIC_PAD_CTL_EDC_MODE_DEFAULT 0x00000000 13711 13712 /* DDR34_E0_PHY_BYTE_LANE_2 :: STATIC_PAD_CTL :: reserved2 [15:15] */ 13713 #define DDR34_E0_PHY_BYTE_LANE_2_STATIC_PAD_CTL_RESERVED2_MASK 0x00008000 13714 #define DDR34_E0_PHY_BYTE_LANE_2_STATIC_PAD_CTL_RESERVED2_ALIGN 0 13715 #define DDR34_E0_PHY_BYTE_LANE_2_STATIC_PAD_CTL_RESERVED2_BITS 1 13716 #define DDR34_E0_PHY_BYTE_LANE_2_STATIC_PAD_CTL_RESERVED2_SHIFT 15 13717 13718 /* DDR34_E0_PHY_BYTE_LANE_2 :: STATIC_PAD_CTL :: WDBI_ENABLE [14:14] */ 13719 #define DDR34_E0_PHY_BYTE_LANE_2_STATIC_PAD_CTL_WDBI_ENABLE_MASK 0x00004000 13720 #define DDR34_E0_PHY_BYTE_LANE_2_STATIC_PAD_CTL_WDBI_ENABLE_ALIGN 0 13721 #define DDR34_E0_PHY_BYTE_LANE_2_STATIC_PAD_CTL_WDBI_ENABLE_BITS 1 13722 #define DDR34_E0_PHY_BYTE_LANE_2_STATIC_PAD_CTL_WDBI_ENABLE_SHIFT 14 13723 #define DDR34_E0_PHY_BYTE_LANE_2_STATIC_PAD_CTL_WDBI_ENABLE_DEFAULT 0x00000000 13724 13725 /* DDR34_E0_PHY_BYTE_LANE_2 :: STATIC_PAD_CTL :: RDBI_ENABLE [13:13] */ 13726 #define DDR34_E0_PHY_BYTE_LANE_2_STATIC_PAD_CTL_RDBI_ENABLE_MASK 0x00002000 13727 #define DDR34_E0_PHY_BYTE_LANE_2_STATIC_PAD_CTL_RDBI_ENABLE_ALIGN 0 13728 #define DDR34_E0_PHY_BYTE_LANE_2_STATIC_PAD_CTL_RDBI_ENABLE_BITS 1 13729 #define DDR34_E0_PHY_BYTE_LANE_2_STATIC_PAD_CTL_RDBI_ENABLE_SHIFT 13 13730 #define DDR34_E0_PHY_BYTE_LANE_2_STATIC_PAD_CTL_RDBI_ENABLE_DEFAULT 0x00000000 13731 13732 /* DDR34_E0_PHY_BYTE_LANE_2 :: STATIC_PAD_CTL :: DM_MODE [12:12] */ 13733 #define DDR34_E0_PHY_BYTE_LANE_2_STATIC_PAD_CTL_DM_MODE_MASK 0x00001000 13734 #define DDR34_E0_PHY_BYTE_LANE_2_STATIC_PAD_CTL_DM_MODE_ALIGN 0 13735 #define DDR34_E0_PHY_BYTE_LANE_2_STATIC_PAD_CTL_DM_MODE_BITS 1 13736 #define DDR34_E0_PHY_BYTE_LANE_2_STATIC_PAD_CTL_DM_MODE_SHIFT 12 13737 #define DDR34_E0_PHY_BYTE_LANE_2_STATIC_PAD_CTL_DM_MODE_DEFAULT 0x00000000 13738 13739 /* DDR34_E0_PHY_BYTE_LANE_2 :: STATIC_PAD_CTL :: reserved3 [11:10] */ 13740 #define DDR34_E0_PHY_BYTE_LANE_2_STATIC_PAD_CTL_RESERVED3_MASK 0x00000c00 13741 #define DDR34_E0_PHY_BYTE_LANE_2_STATIC_PAD_CTL_RESERVED3_ALIGN 0 13742 #define DDR34_E0_PHY_BYTE_LANE_2_STATIC_PAD_CTL_RESERVED3_BITS 2 13743 #define DDR34_E0_PHY_BYTE_LANE_2_STATIC_PAD_CTL_RESERVED3_SHIFT 10 13744 13745 /* DDR34_E0_PHY_BYTE_LANE_2 :: STATIC_PAD_CTL :: DQS_TX_DIS [09:09] */ 13746 #define DDR34_E0_PHY_BYTE_LANE_2_STATIC_PAD_CTL_DQS_TX_DIS_MASK 0x00000200 13747 #define DDR34_E0_PHY_BYTE_LANE_2_STATIC_PAD_CTL_DQS_TX_DIS_ALIGN 0 13748 #define DDR34_E0_PHY_BYTE_LANE_2_STATIC_PAD_CTL_DQS_TX_DIS_BITS 1 13749 #define DDR34_E0_PHY_BYTE_LANE_2_STATIC_PAD_CTL_DQS_TX_DIS_SHIFT 9 13750 #define DDR34_E0_PHY_BYTE_LANE_2_STATIC_PAD_CTL_DQS_TX_DIS_DEFAULT 0x00000000 13751 13752 /* DDR34_E0_PHY_BYTE_LANE_2 :: STATIC_PAD_CTL :: reserved4 [08:02] */ 13753 #define DDR34_E0_PHY_BYTE_LANE_2_STATIC_PAD_CTL_RESERVED4_MASK 0x000001fc 13754 #define DDR34_E0_PHY_BYTE_LANE_2_STATIC_PAD_CTL_RESERVED4_ALIGN 0 13755 #define DDR34_E0_PHY_BYTE_LANE_2_STATIC_PAD_CTL_RESERVED4_BITS 7 13756 #define DDR34_E0_PHY_BYTE_LANE_2_STATIC_PAD_CTL_RESERVED4_SHIFT 2 13757 13758 /* DDR34_E0_PHY_BYTE_LANE_2 :: STATIC_PAD_CTL :: RX_MODE [01:00] */ 13759 #define DDR34_E0_PHY_BYTE_LANE_2_STATIC_PAD_CTL_RX_MODE_MASK 0x00000003 13760 #define DDR34_E0_PHY_BYTE_LANE_2_STATIC_PAD_CTL_RX_MODE_ALIGN 0 13761 #define DDR34_E0_PHY_BYTE_LANE_2_STATIC_PAD_CTL_RX_MODE_BITS 2 13762 #define DDR34_E0_PHY_BYTE_LANE_2_STATIC_PAD_CTL_RX_MODE_SHIFT 0 13763 #define DDR34_E0_PHY_BYTE_LANE_2_STATIC_PAD_CTL_RX_MODE_DEFAULT 0x00000000 13764 13765 /*************************************************************************** 13766 *WR_PREAMBLE_MODE - Write cycle preamble control register 13767 */ 13768 /* DDR34_E0_PHY_BYTE_LANE_2 :: WR_PREAMBLE_MODE :: reserved0 [31:16] */ 13769 #define DDR34_E0_PHY_BYTE_LANE_2_WR_PREAMBLE_MODE_RESERVED0_MASK 0xffff0000 13770 #define DDR34_E0_PHY_BYTE_LANE_2_WR_PREAMBLE_MODE_RESERVED0_ALIGN 0 13771 #define DDR34_E0_PHY_BYTE_LANE_2_WR_PREAMBLE_MODE_RESERVED0_BITS 16 13772 #define DDR34_E0_PHY_BYTE_LANE_2_WR_PREAMBLE_MODE_RESERVED0_SHIFT 16 13773 13774 /* DDR34_E0_PHY_BYTE_LANE_2 :: WR_PREAMBLE_MODE :: DQ_POSTAM_BITS [15:14] */ 13775 #define DDR34_E0_PHY_BYTE_LANE_2_WR_PREAMBLE_MODE_DQ_POSTAM_BITS_MASK 0x0000c000 13776 #define DDR34_E0_PHY_BYTE_LANE_2_WR_PREAMBLE_MODE_DQ_POSTAM_BITS_ALIGN 0 13777 #define DDR34_E0_PHY_BYTE_LANE_2_WR_PREAMBLE_MODE_DQ_POSTAM_BITS_BITS 2 13778 #define DDR34_E0_PHY_BYTE_LANE_2_WR_PREAMBLE_MODE_DQ_POSTAM_BITS_SHIFT 14 13779 #define DDR34_E0_PHY_BYTE_LANE_2_WR_PREAMBLE_MODE_DQ_POSTAM_BITS_DEFAULT 0x00000000 13780 13781 /* DDR34_E0_PHY_BYTE_LANE_2 :: WR_PREAMBLE_MODE :: DQ_PREAM_BITS [13:12] */ 13782 #define DDR34_E0_PHY_BYTE_LANE_2_WR_PREAMBLE_MODE_DQ_PREAM_BITS_MASK 0x00003000 13783 #define DDR34_E0_PHY_BYTE_LANE_2_WR_PREAMBLE_MODE_DQ_PREAM_BITS_ALIGN 0 13784 #define DDR34_E0_PHY_BYTE_LANE_2_WR_PREAMBLE_MODE_DQ_PREAM_BITS_BITS 2 13785 #define DDR34_E0_PHY_BYTE_LANE_2_WR_PREAMBLE_MODE_DQ_PREAM_BITS_SHIFT 12 13786 #define DDR34_E0_PHY_BYTE_LANE_2_WR_PREAMBLE_MODE_DQ_PREAM_BITS_DEFAULT 0x00000000 13787 13788 /* DDR34_E0_PHY_BYTE_LANE_2 :: WR_PREAMBLE_MODE :: DQS [11:08] */ 13789 #define DDR34_E0_PHY_BYTE_LANE_2_WR_PREAMBLE_MODE_DQS_MASK 0x00000f00 13790 #define DDR34_E0_PHY_BYTE_LANE_2_WR_PREAMBLE_MODE_DQS_ALIGN 0 13791 #define DDR34_E0_PHY_BYTE_LANE_2_WR_PREAMBLE_MODE_DQS_BITS 4 13792 #define DDR34_E0_PHY_BYTE_LANE_2_WR_PREAMBLE_MODE_DQS_SHIFT 8 13793 #define DDR34_E0_PHY_BYTE_LANE_2_WR_PREAMBLE_MODE_DQS_DEFAULT 0x0000000e 13794 13795 /* DDR34_E0_PHY_BYTE_LANE_2 :: WR_PREAMBLE_MODE :: reserved1 [07:05] */ 13796 #define DDR34_E0_PHY_BYTE_LANE_2_WR_PREAMBLE_MODE_RESERVED1_MASK 0x000000e0 13797 #define DDR34_E0_PHY_BYTE_LANE_2_WR_PREAMBLE_MODE_RESERVED1_ALIGN 0 13798 #define DDR34_E0_PHY_BYTE_LANE_2_WR_PREAMBLE_MODE_RESERVED1_BITS 3 13799 #define DDR34_E0_PHY_BYTE_LANE_2_WR_PREAMBLE_MODE_RESERVED1_SHIFT 5 13800 13801 /* DDR34_E0_PHY_BYTE_LANE_2 :: WR_PREAMBLE_MODE :: DQS_POSTAM_BITS [04:03] */ 13802 #define DDR34_E0_PHY_BYTE_LANE_2_WR_PREAMBLE_MODE_DQS_POSTAM_BITS_MASK 0x00000018 13803 #define DDR34_E0_PHY_BYTE_LANE_2_WR_PREAMBLE_MODE_DQS_POSTAM_BITS_ALIGN 0 13804 #define DDR34_E0_PHY_BYTE_LANE_2_WR_PREAMBLE_MODE_DQS_POSTAM_BITS_BITS 2 13805 #define DDR34_E0_PHY_BYTE_LANE_2_WR_PREAMBLE_MODE_DQS_POSTAM_BITS_SHIFT 3 13806 #define DDR34_E0_PHY_BYTE_LANE_2_WR_PREAMBLE_MODE_DQS_POSTAM_BITS_DEFAULT 0x00000000 13807 13808 /* DDR34_E0_PHY_BYTE_LANE_2 :: WR_PREAMBLE_MODE :: DQS_PREAM_BITS [02:00] */ 13809 #define DDR34_E0_PHY_BYTE_LANE_2_WR_PREAMBLE_MODE_DQS_PREAM_BITS_MASK 0x00000007 13810 #define DDR34_E0_PHY_BYTE_LANE_2_WR_PREAMBLE_MODE_DQS_PREAM_BITS_ALIGN 0 13811 #define DDR34_E0_PHY_BYTE_LANE_2_WR_PREAMBLE_MODE_DQS_PREAM_BITS_BITS 3 13812 #define DDR34_E0_PHY_BYTE_LANE_2_WR_PREAMBLE_MODE_DQS_PREAM_BITS_SHIFT 0 13813 #define DDR34_E0_PHY_BYTE_LANE_2_WR_PREAMBLE_MODE_DQS_PREAM_BITS_DEFAULT 0x00000002 13814 13815 /*************************************************************************** 13816 *ODT_CONTROL - Read channel ODT control register 13817 */ 13818 /* DDR34_E0_PHY_BYTE_LANE_2 :: ODT_CONTROL :: reserved_for_padding0 [31:31] */ 13819 #define DDR34_E0_PHY_BYTE_LANE_2_ODT_CONTROL_RESERVED_for_padding0_MASK 0x80000000 13820 #define DDR34_E0_PHY_BYTE_LANE_2_ODT_CONTROL_RESERVED_for_padding0_ALIGN 0 13821 #define DDR34_E0_PHY_BYTE_LANE_2_ODT_CONTROL_RESERVED_for_padding0_BITS 1 13822 #define DDR34_E0_PHY_BYTE_LANE_2_ODT_CONTROL_RESERVED_for_padding0_SHIFT 31 13823 13824 /* DDR34_E0_PHY_BYTE_LANE_2 :: ODT_CONTROL :: reserved1 [30:10] */ 13825 #define DDR34_E0_PHY_BYTE_LANE_2_ODT_CONTROL_RESERVED1_MASK 0x7ffffc00 13826 #define DDR34_E0_PHY_BYTE_LANE_2_ODT_CONTROL_RESERVED1_ALIGN 0 13827 #define DDR34_E0_PHY_BYTE_LANE_2_ODT_CONTROL_RESERVED1_BITS 21 13828 #define DDR34_E0_PHY_BYTE_LANE_2_ODT_CONTROL_RESERVED1_SHIFT 10 13829 13830 /* DDR34_E0_PHY_BYTE_LANE_2 :: ODT_CONTROL :: ODT_ENABLE [09:09] */ 13831 #define DDR34_E0_PHY_BYTE_LANE_2_ODT_CONTROL_ODT_ENABLE_MASK 0x00000200 13832 #define DDR34_E0_PHY_BYTE_LANE_2_ODT_CONTROL_ODT_ENABLE_ALIGN 0 13833 #define DDR34_E0_PHY_BYTE_LANE_2_ODT_CONTROL_ODT_ENABLE_BITS 1 13834 #define DDR34_E0_PHY_BYTE_LANE_2_ODT_CONTROL_ODT_ENABLE_SHIFT 9 13835 #define DDR34_E0_PHY_BYTE_LANE_2_ODT_CONTROL_ODT_ENABLE_DEFAULT 0x00000001 13836 13837 /* DDR34_E0_PHY_BYTE_LANE_2 :: ODT_CONTROL :: ODT_DELAY [08:06] */ 13838 #define DDR34_E0_PHY_BYTE_LANE_2_ODT_CONTROL_ODT_DELAY_MASK 0x000001c0 13839 #define DDR34_E0_PHY_BYTE_LANE_2_ODT_CONTROL_ODT_DELAY_ALIGN 0 13840 #define DDR34_E0_PHY_BYTE_LANE_2_ODT_CONTROL_ODT_DELAY_BITS 3 13841 #define DDR34_E0_PHY_BYTE_LANE_2_ODT_CONTROL_ODT_DELAY_SHIFT 6 13842 #define DDR34_E0_PHY_BYTE_LANE_2_ODT_CONTROL_ODT_DELAY_DEFAULT 0x00000000 13843 13844 /* DDR34_E0_PHY_BYTE_LANE_2 :: ODT_CONTROL :: ODT_POST_LENGTH [05:03] */ 13845 #define DDR34_E0_PHY_BYTE_LANE_2_ODT_CONTROL_ODT_POST_LENGTH_MASK 0x00000038 13846 #define DDR34_E0_PHY_BYTE_LANE_2_ODT_CONTROL_ODT_POST_LENGTH_ALIGN 0 13847 #define DDR34_E0_PHY_BYTE_LANE_2_ODT_CONTROL_ODT_POST_LENGTH_BITS 3 13848 #define DDR34_E0_PHY_BYTE_LANE_2_ODT_CONTROL_ODT_POST_LENGTH_SHIFT 3 13849 #define DDR34_E0_PHY_BYTE_LANE_2_ODT_CONTROL_ODT_POST_LENGTH_DEFAULT 0x00000001 13850 13851 /* DDR34_E0_PHY_BYTE_LANE_2 :: ODT_CONTROL :: ODT_PRE_LENGTH [02:00] */ 13852 #define DDR34_E0_PHY_BYTE_LANE_2_ODT_CONTROL_ODT_PRE_LENGTH_MASK 0x00000007 13853 #define DDR34_E0_PHY_BYTE_LANE_2_ODT_CONTROL_ODT_PRE_LENGTH_ALIGN 0 13854 #define DDR34_E0_PHY_BYTE_LANE_2_ODT_CONTROL_ODT_PRE_LENGTH_BITS 3 13855 #define DDR34_E0_PHY_BYTE_LANE_2_ODT_CONTROL_ODT_PRE_LENGTH_SHIFT 0 13856 #define DDR34_E0_PHY_BYTE_LANE_2_ODT_CONTROL_ODT_PRE_LENGTH_DEFAULT 0x00000003 13857 13858 /*************************************************************************** 13859 *EDC_DPD_CONTROL - GDDR5M EDC digital phase detector control register 13860 */ 13861 /* DDR34_E0_PHY_BYTE_LANE_2 :: EDC_DPD_CONTROL :: reserved0 [31:06] */ 13862 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_DPD_CONTROL_RESERVED0_MASK 0xffffffc0 13863 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_DPD_CONTROL_RESERVED0_ALIGN 0 13864 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_DPD_CONTROL_RESERVED0_BITS 26 13865 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_DPD_CONTROL_RESERVED0_SHIFT 6 13866 13867 /* DDR34_E0_PHY_BYTE_LANE_2 :: EDC_DPD_CONTROL :: DQS_PHASE_OVERRIDE_VALUE [05:05] */ 13868 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_VALUE_MASK 0x00000020 13869 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_VALUE_ALIGN 0 13870 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_VALUE_BITS 1 13871 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_VALUE_SHIFT 5 13872 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_VALUE_DEFAULT 0x00000000 13873 13874 /* DDR34_E0_PHY_BYTE_LANE_2 :: EDC_DPD_CONTROL :: DQS_PHASE_OVERRIDE_ENABLE [04:04] */ 13875 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_ENABLE_MASK 0x00000010 13876 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_ENABLE_ALIGN 0 13877 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_ENABLE_BITS 1 13878 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_ENABLE_SHIFT 4 13879 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_ENABLE_DEFAULT 0x00000000 13880 13881 /* DDR34_E0_PHY_BYTE_LANE_2 :: EDC_DPD_CONTROL :: SET_ADJ_EN [03:03] */ 13882 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_DPD_CONTROL_SET_ADJ_EN_MASK 0x00000008 13883 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_DPD_CONTROL_SET_ADJ_EN_ALIGN 0 13884 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_DPD_CONTROL_SET_ADJ_EN_BITS 1 13885 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_DPD_CONTROL_SET_ADJ_EN_SHIFT 3 13886 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_DPD_CONTROL_SET_ADJ_EN_DEFAULT 0x00000000 13887 13888 /* DDR34_E0_PHY_BYTE_LANE_2 :: EDC_DPD_CONTROL :: UPDATE [02:02] */ 13889 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_DPD_CONTROL_UPDATE_MASK 0x00000004 13890 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_DPD_CONTROL_UPDATE_ALIGN 0 13891 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_DPD_CONTROL_UPDATE_BITS 1 13892 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_DPD_CONTROL_UPDATE_SHIFT 2 13893 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_DPD_CONTROL_UPDATE_DEFAULT 0x00000000 13894 13895 /* DDR34_E0_PHY_BYTE_LANE_2 :: EDC_DPD_CONTROL :: MONITOR [01:01] */ 13896 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_DPD_CONTROL_MONITOR_MASK 0x00000002 13897 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_DPD_CONTROL_MONITOR_ALIGN 0 13898 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_DPD_CONTROL_MONITOR_BITS 1 13899 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_DPD_CONTROL_MONITOR_SHIFT 1 13900 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_DPD_CONTROL_MONITOR_DEFAULT 0x00000000 13901 13902 /* DDR34_E0_PHY_BYTE_LANE_2 :: EDC_DPD_CONTROL :: INIT [00:00] */ 13903 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_DPD_CONTROL_INIT_MASK 0x00000001 13904 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_DPD_CONTROL_INIT_ALIGN 0 13905 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_DPD_CONTROL_INIT_BITS 1 13906 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_DPD_CONTROL_INIT_SHIFT 0 13907 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_DPD_CONTROL_INIT_DEFAULT 0x00000000 13908 13909 /*************************************************************************** 13910 *EDC_DPD_STATUS - GDDR5M EDC digital phase detector status register 13911 */ 13912 /* DDR34_E0_PHY_BYTE_LANE_2 :: EDC_DPD_STATUS :: reserved0 [31:25] */ 13913 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_DPD_STATUS_RESERVED0_MASK 0xfe000000 13914 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_DPD_STATUS_RESERVED0_ALIGN 0 13915 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_DPD_STATUS_RESERVED0_BITS 7 13916 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_DPD_STATUS_RESERVED0_SHIFT 25 13917 13918 /* DDR34_E0_PHY_BYTE_LANE_2 :: EDC_DPD_STATUS :: CURRENT_DQS_PHASE [24:24] */ 13919 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_DPD_STATUS_CURRENT_DQS_PHASE_MASK 0x01000000 13920 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_DPD_STATUS_CURRENT_DQS_PHASE_ALIGN 0 13921 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_DPD_STATUS_CURRENT_DQS_PHASE_BITS 1 13922 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_DPD_STATUS_CURRENT_DQS_PHASE_SHIFT 24 13923 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_DPD_STATUS_CURRENT_DQS_PHASE_DEFAULT 0x00000000 13924 13925 /* DDR34_E0_PHY_BYTE_LANE_2 :: EDC_DPD_STATUS :: CURRENT_VDL_SETTING [23:16] */ 13926 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_DPD_STATUS_CURRENT_VDL_SETTING_MASK 0x00ff0000 13927 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_DPD_STATUS_CURRENT_VDL_SETTING_ALIGN 0 13928 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_DPD_STATUS_CURRENT_VDL_SETTING_BITS 8 13929 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_DPD_STATUS_CURRENT_VDL_SETTING_SHIFT 16 13930 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_DPD_STATUS_CURRENT_VDL_SETTING_DEFAULT 0x00000000 13931 13932 /* DDR34_E0_PHY_BYTE_LANE_2 :: EDC_DPD_STATUS :: reserved1 [15:13] */ 13933 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_DPD_STATUS_RESERVED1_MASK 0x0000e000 13934 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_DPD_STATUS_RESERVED1_ALIGN 0 13935 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_DPD_STATUS_RESERVED1_BITS 3 13936 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_DPD_STATUS_RESERVED1_SHIFT 13 13937 13938 /* DDR34_E0_PHY_BYTE_LANE_2 :: EDC_DPD_STATUS :: INIT_DQS_PHASE [12:12] */ 13939 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_DPD_STATUS_INIT_DQS_PHASE_MASK 0x00001000 13940 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_DPD_STATUS_INIT_DQS_PHASE_ALIGN 0 13941 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_DPD_STATUS_INIT_DQS_PHASE_BITS 1 13942 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_DPD_STATUS_INIT_DQS_PHASE_SHIFT 12 13943 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_DPD_STATUS_INIT_DQS_PHASE_DEFAULT 0x00000000 13944 13945 /* DDR34_E0_PHY_BYTE_LANE_2 :: EDC_DPD_STATUS :: INIT_VDL_SETTING [11:04] */ 13946 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_DPD_STATUS_INIT_VDL_SETTING_MASK 0x00000ff0 13947 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_DPD_STATUS_INIT_VDL_SETTING_ALIGN 0 13948 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_DPD_STATUS_INIT_VDL_SETTING_BITS 8 13949 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_DPD_STATUS_INIT_VDL_SETTING_SHIFT 4 13950 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_DPD_STATUS_INIT_VDL_SETTING_DEFAULT 0x00000000 13951 13952 /* DDR34_E0_PHY_BYTE_LANE_2 :: EDC_DPD_STATUS :: EDGE_ERROR [03:03] */ 13953 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_DPD_STATUS_EDGE_ERROR_MASK 0x00000008 13954 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_DPD_STATUS_EDGE_ERROR_ALIGN 0 13955 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_DPD_STATUS_EDGE_ERROR_BITS 1 13956 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_DPD_STATUS_EDGE_ERROR_SHIFT 3 13957 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_DPD_STATUS_EDGE_ERROR_DEFAULT 0x00000000 13958 13959 /* DDR34_E0_PHY_BYTE_LANE_2 :: EDC_DPD_STATUS :: MONITOR_BUSY [02:02] */ 13960 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_DPD_STATUS_MONITOR_BUSY_MASK 0x00000004 13961 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_DPD_STATUS_MONITOR_BUSY_ALIGN 0 13962 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_DPD_STATUS_MONITOR_BUSY_BITS 1 13963 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_DPD_STATUS_MONITOR_BUSY_SHIFT 2 13964 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_DPD_STATUS_MONITOR_BUSY_DEFAULT 0x00000000 13965 13966 /* DDR34_E0_PHY_BYTE_LANE_2 :: EDC_DPD_STATUS :: INIT_BUSY [01:01] */ 13967 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_DPD_STATUS_INIT_BUSY_MASK 0x00000002 13968 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_DPD_STATUS_INIT_BUSY_ALIGN 0 13969 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_DPD_STATUS_INIT_BUSY_BITS 1 13970 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_DPD_STATUS_INIT_BUSY_SHIFT 1 13971 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_DPD_STATUS_INIT_BUSY_DEFAULT 0x00000000 13972 13973 /* DDR34_E0_PHY_BYTE_LANE_2 :: EDC_DPD_STATUS :: INIT_DONE [00:00] */ 13974 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_DPD_STATUS_INIT_DONE_MASK 0x00000001 13975 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_DPD_STATUS_INIT_DONE_ALIGN 0 13976 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_DPD_STATUS_INIT_DONE_BITS 1 13977 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_DPD_STATUS_INIT_DONE_SHIFT 0 13978 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_DPD_STATUS_INIT_DONE_DEFAULT 0x00000000 13979 13980 /*************************************************************************** 13981 *EDC_DPD_OUT_CONTROL - GDDR5M EDC digital phase detector output signal control register 13982 */ 13983 /* DDR34_E0_PHY_BYTE_LANE_2 :: EDC_DPD_OUT_CONTROL :: reserved0 [31:20] */ 13984 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_DPD_OUT_CONTROL_RESERVED0_MASK 0xfff00000 13985 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_DPD_OUT_CONTROL_RESERVED0_ALIGN 0 13986 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_DPD_OUT_CONTROL_RESERVED0_BITS 12 13987 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_DPD_OUT_CONTROL_RESERVED0_SHIFT 20 13988 13989 /* DDR34_E0_PHY_BYTE_LANE_2 :: EDC_DPD_OUT_CONTROL :: LOWER_LIMIT [19:12] */ 13990 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_DPD_OUT_CONTROL_LOWER_LIMIT_MASK 0x000ff000 13991 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_DPD_OUT_CONTROL_LOWER_LIMIT_ALIGN 0 13992 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_DPD_OUT_CONTROL_LOWER_LIMIT_BITS 8 13993 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_DPD_OUT_CONTROL_LOWER_LIMIT_SHIFT 12 13994 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_DPD_OUT_CONTROL_LOWER_LIMIT_DEFAULT 0x00000000 13995 13996 /* DDR34_E0_PHY_BYTE_LANE_2 :: EDC_DPD_OUT_CONTROL :: UPPER_LIMIT [11:04] */ 13997 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_DPD_OUT_CONTROL_UPPER_LIMIT_MASK 0x00000ff0 13998 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_DPD_OUT_CONTROL_UPPER_LIMIT_ALIGN 0 13999 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_DPD_OUT_CONTROL_UPPER_LIMIT_BITS 8 14000 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_DPD_OUT_CONTROL_UPPER_LIMIT_SHIFT 4 14001 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_DPD_OUT_CONTROL_UPPER_LIMIT_DEFAULT 0x00000000 14002 14003 /* DDR34_E0_PHY_BYTE_LANE_2 :: EDC_DPD_OUT_CONTROL :: reserved1 [03:01] */ 14004 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_DPD_OUT_CONTROL_RESERVED1_MASK 0x0000000e 14005 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_DPD_OUT_CONTROL_RESERVED1_ALIGN 0 14006 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_DPD_OUT_CONTROL_RESERVED1_BITS 3 14007 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_DPD_OUT_CONTROL_RESERVED1_SHIFT 1 14008 14009 /* DDR34_E0_PHY_BYTE_LANE_2 :: EDC_DPD_OUT_CONTROL :: ENABLE [00:00] */ 14010 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_DPD_OUT_CONTROL_ENABLE_MASK 0x00000001 14011 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_DPD_OUT_CONTROL_ENABLE_ALIGN 0 14012 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_DPD_OUT_CONTROL_ENABLE_BITS 1 14013 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_DPD_OUT_CONTROL_ENABLE_SHIFT 0 14014 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_DPD_OUT_CONTROL_ENABLE_DEFAULT 0x00000000 14015 14016 /*************************************************************************** 14017 *EDC_DPD_OUT_STATUS - GDDR5M EDC digital phase detector output signal status register 14018 */ 14019 /* DDR34_E0_PHY_BYTE_LANE_2 :: EDC_DPD_OUT_STATUS :: reserved0 [31:12] */ 14020 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_DPD_OUT_STATUS_RESERVED0_MASK 0xfffff000 14021 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_DPD_OUT_STATUS_RESERVED0_ALIGN 0 14022 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_DPD_OUT_STATUS_RESERVED0_BITS 20 14023 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_DPD_OUT_STATUS_RESERVED0_SHIFT 12 14024 14025 /* DDR34_E0_PHY_BYTE_LANE_2 :: EDC_DPD_OUT_STATUS :: VDL_SETTING [11:04] */ 14026 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_DPD_OUT_STATUS_VDL_SETTING_MASK 0x00000ff0 14027 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_DPD_OUT_STATUS_VDL_SETTING_ALIGN 0 14028 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_DPD_OUT_STATUS_VDL_SETTING_BITS 8 14029 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_DPD_OUT_STATUS_VDL_SETTING_SHIFT 4 14030 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_DPD_OUT_STATUS_VDL_SETTING_DEFAULT 0x00000000 14031 14032 /* DDR34_E0_PHY_BYTE_LANE_2 :: EDC_DPD_OUT_STATUS :: reserved1 [03:01] */ 14033 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_DPD_OUT_STATUS_RESERVED1_MASK 0x0000000e 14034 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_DPD_OUT_STATUS_RESERVED1_ALIGN 0 14035 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_DPD_OUT_STATUS_RESERVED1_BITS 3 14036 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_DPD_OUT_STATUS_RESERVED1_SHIFT 1 14037 14038 /* DDR34_E0_PHY_BYTE_LANE_2 :: EDC_DPD_OUT_STATUS :: VALID [00:00] */ 14039 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_DPD_OUT_STATUS_VALID_MASK 0x00000001 14040 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_DPD_OUT_STATUS_VALID_ALIGN 0 14041 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_DPD_OUT_STATUS_VALID_BITS 1 14042 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_DPD_OUT_STATUS_VALID_SHIFT 0 14043 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_DPD_OUT_STATUS_VALID_DEFAULT 0x00000000 14044 14045 /*************************************************************************** 14046 *EDC_DPD_OUT_STATUS_CLEAR - GDDR5M EDC digital phase detector output signal status clear register 14047 */ 14048 /* DDR34_E0_PHY_BYTE_LANE_2 :: EDC_DPD_OUT_STATUS_CLEAR :: reserved0 [31:01] */ 14049 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_DPD_OUT_STATUS_CLEAR_RESERVED0_MASK 0xfffffffe 14050 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_DPD_OUT_STATUS_CLEAR_RESERVED0_ALIGN 0 14051 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_DPD_OUT_STATUS_CLEAR_RESERVED0_BITS 31 14052 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_DPD_OUT_STATUS_CLEAR_RESERVED0_SHIFT 1 14053 14054 /* DDR34_E0_PHY_BYTE_LANE_2 :: EDC_DPD_OUT_STATUS_CLEAR :: CLEAR [00:00] */ 14055 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_DPD_OUT_STATUS_CLEAR_CLEAR_MASK 0x00000001 14056 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_DPD_OUT_STATUS_CLEAR_CLEAR_ALIGN 0 14057 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_DPD_OUT_STATUS_CLEAR_CLEAR_BITS 1 14058 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_DPD_OUT_STATUS_CLEAR_CLEAR_SHIFT 0 14059 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_DPD_OUT_STATUS_CLEAR_CLEAR_DEFAULT 0x00000000 14060 14061 /*************************************************************************** 14062 *EDC_CRC_CONTROL - GDDR5M EDC signal path CRC control register 14063 */ 14064 /* DDR34_E0_PHY_BYTE_LANE_2 :: EDC_CRC_CONTROL :: BUSY [31:31] */ 14065 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_CRC_CONTROL_BUSY_MASK 0x80000000 14066 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_CRC_CONTROL_BUSY_ALIGN 0 14067 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_CRC_CONTROL_BUSY_BITS 1 14068 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_CRC_CONTROL_BUSY_SHIFT 31 14069 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_CRC_CONTROL_BUSY_DEFAULT 0x00000000 14070 14071 /* DDR34_E0_PHY_BYTE_LANE_2 :: EDC_CRC_CONTROL :: reserved0 [30:17] */ 14072 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_CRC_CONTROL_RESERVED0_MASK 0x7ffe0000 14073 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_CRC_CONTROL_RESERVED0_ALIGN 0 14074 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_CRC_CONTROL_RESERVED0_BITS 14 14075 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_CRC_CONTROL_RESERVED0_SHIFT 17 14076 14077 /* DDR34_E0_PHY_BYTE_LANE_2 :: EDC_CRC_CONTROL :: FORCE [16:16] */ 14078 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_CRC_CONTROL_FORCE_MASK 0x00010000 14079 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_CRC_CONTROL_FORCE_ALIGN 0 14080 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_CRC_CONTROL_FORCE_BITS 1 14081 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_CRC_CONTROL_FORCE_SHIFT 16 14082 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_CRC_CONTROL_FORCE_DEFAULT 0x00000000 14083 14084 /* DDR34_E0_PHY_BYTE_LANE_2 :: EDC_CRC_CONTROL :: reserved1 [15:11] */ 14085 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_CRC_CONTROL_RESERVED1_MASK 0x0000f800 14086 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_CRC_CONTROL_RESERVED1_ALIGN 0 14087 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_CRC_CONTROL_RESERVED1_BITS 5 14088 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_CRC_CONTROL_RESERVED1_SHIFT 11 14089 14090 /* DDR34_E0_PHY_BYTE_LANE_2 :: EDC_CRC_CONTROL :: CRCWL [10:08] */ 14091 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_CRC_CONTROL_CRCWL_MASK 0x00000700 14092 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_CRC_CONTROL_CRCWL_ALIGN 0 14093 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_CRC_CONTROL_CRCWL_BITS 3 14094 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_CRC_CONTROL_CRCWL_SHIFT 8 14095 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_CRC_CONTROL_CRCWL_DEFAULT 0x00000000 14096 14097 /* DDR34_E0_PHY_BYTE_LANE_2 :: EDC_CRC_CONTROL :: reserved2 [07:06] */ 14098 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_CRC_CONTROL_RESERVED2_MASK 0x000000c0 14099 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_CRC_CONTROL_RESERVED2_ALIGN 0 14100 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_CRC_CONTROL_RESERVED2_BITS 2 14101 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_CRC_CONTROL_RESERVED2_SHIFT 6 14102 14103 /* DDR34_E0_PHY_BYTE_LANE_2 :: EDC_CRC_CONTROL :: CRCRL [05:04] */ 14104 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_CRC_CONTROL_CRCRL_MASK 0x00000030 14105 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_CRC_CONTROL_CRCRL_ALIGN 0 14106 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_CRC_CONTROL_CRCRL_BITS 2 14107 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_CRC_CONTROL_CRCRL_SHIFT 4 14108 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_CRC_CONTROL_CRCRL_DEFAULT 0x00000000 14109 14110 /* DDR34_E0_PHY_BYTE_LANE_2 :: EDC_CRC_CONTROL :: reserved3 [03:03] */ 14111 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_CRC_CONTROL_RESERVED3_MASK 0x00000008 14112 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_CRC_CONTROL_RESERVED3_ALIGN 0 14113 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_CRC_CONTROL_RESERVED3_BITS 1 14114 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_CRC_CONTROL_RESERVED3_SHIFT 3 14115 14116 /* DDR34_E0_PHY_BYTE_LANE_2 :: EDC_CRC_CONTROL :: COUNT_MODE [02:02] */ 14117 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_CRC_CONTROL_COUNT_MODE_MASK 0x00000004 14118 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_CRC_CONTROL_COUNT_MODE_ALIGN 0 14119 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_CRC_CONTROL_COUNT_MODE_BITS 1 14120 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_CRC_CONTROL_COUNT_MODE_SHIFT 2 14121 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_CRC_CONTROL_COUNT_MODE_DEFAULT 0x00000000 14122 14123 /* DDR34_E0_PHY_BYTE_LANE_2 :: EDC_CRC_CONTROL :: ENABLE_WR [01:01] */ 14124 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_CRC_CONTROL_ENABLE_WR_MASK 0x00000002 14125 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_CRC_CONTROL_ENABLE_WR_ALIGN 0 14126 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_CRC_CONTROL_ENABLE_WR_BITS 1 14127 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_CRC_CONTROL_ENABLE_WR_SHIFT 1 14128 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_CRC_CONTROL_ENABLE_WR_DEFAULT 0x00000000 14129 14130 /* DDR34_E0_PHY_BYTE_LANE_2 :: EDC_CRC_CONTROL :: ENABLE_RD [00:00] */ 14131 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_CRC_CONTROL_ENABLE_RD_MASK 0x00000001 14132 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_CRC_CONTROL_ENABLE_RD_ALIGN 0 14133 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_CRC_CONTROL_ENABLE_RD_BITS 1 14134 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_CRC_CONTROL_ENABLE_RD_SHIFT 0 14135 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_CRC_CONTROL_ENABLE_RD_DEFAULT 0x00000000 14136 14137 /*************************************************************************** 14138 *EDC_CRC_STATUS - GDDR5M EDC signal path CRC status register 14139 */ 14140 /* DDR34_E0_PHY_BYTE_LANE_2 :: EDC_CRC_STATUS :: reserved0 [31:04] */ 14141 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_CRC_STATUS_RESERVED0_MASK 0xfffffff0 14142 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_CRC_STATUS_RESERVED0_ALIGN 0 14143 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_CRC_STATUS_RESERVED0_BITS 28 14144 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_CRC_STATUS_RESERVED0_SHIFT 4 14145 14146 /* DDR34_E0_PHY_BYTE_LANE_2 :: EDC_CRC_STATUS :: WR_FAIL [03:03] */ 14147 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_CRC_STATUS_WR_FAIL_MASK 0x00000008 14148 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_CRC_STATUS_WR_FAIL_ALIGN 0 14149 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_CRC_STATUS_WR_FAIL_BITS 1 14150 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_CRC_STATUS_WR_FAIL_SHIFT 3 14151 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_CRC_STATUS_WR_FAIL_DEFAULT 0x00000000 14152 14153 /* DDR34_E0_PHY_BYTE_LANE_2 :: EDC_CRC_STATUS :: WR_PASS [02:02] */ 14154 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_CRC_STATUS_WR_PASS_MASK 0x00000004 14155 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_CRC_STATUS_WR_PASS_ALIGN 0 14156 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_CRC_STATUS_WR_PASS_BITS 1 14157 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_CRC_STATUS_WR_PASS_SHIFT 2 14158 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_CRC_STATUS_WR_PASS_DEFAULT 0x00000000 14159 14160 /* DDR34_E0_PHY_BYTE_LANE_2 :: EDC_CRC_STATUS :: RD_FAIL [01:01] */ 14161 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_CRC_STATUS_RD_FAIL_MASK 0x00000002 14162 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_CRC_STATUS_RD_FAIL_ALIGN 0 14163 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_CRC_STATUS_RD_FAIL_BITS 1 14164 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_CRC_STATUS_RD_FAIL_SHIFT 1 14165 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_CRC_STATUS_RD_FAIL_DEFAULT 0x00000000 14166 14167 /* DDR34_E0_PHY_BYTE_LANE_2 :: EDC_CRC_STATUS :: RD_PASS [00:00] */ 14168 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_CRC_STATUS_RD_PASS_MASK 0x00000001 14169 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_CRC_STATUS_RD_PASS_ALIGN 0 14170 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_CRC_STATUS_RD_PASS_BITS 1 14171 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_CRC_STATUS_RD_PASS_SHIFT 0 14172 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_CRC_STATUS_RD_PASS_DEFAULT 0x00000000 14173 14174 /*************************************************************************** 14175 *EDC_CRC_COUNT - GDDR5M EDC signal path CRC counter register 14176 */ 14177 /* DDR34_E0_PHY_BYTE_LANE_2 :: EDC_CRC_COUNT :: reserved0 [31:28] */ 14178 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_CRC_COUNT_RESERVED0_MASK 0xf0000000 14179 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_CRC_COUNT_RESERVED0_ALIGN 0 14180 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_CRC_COUNT_RESERVED0_BITS 4 14181 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_CRC_COUNT_RESERVED0_SHIFT 28 14182 14183 /* DDR34_E0_PHY_BYTE_LANE_2 :: EDC_CRC_COUNT :: WR_COUNT [27:16] */ 14184 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_CRC_COUNT_WR_COUNT_MASK 0x0fff0000 14185 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_CRC_COUNT_WR_COUNT_ALIGN 0 14186 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_CRC_COUNT_WR_COUNT_BITS 12 14187 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_CRC_COUNT_WR_COUNT_SHIFT 16 14188 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_CRC_COUNT_WR_COUNT_DEFAULT 0x00000000 14189 14190 /* DDR34_E0_PHY_BYTE_LANE_2 :: EDC_CRC_COUNT :: reserved1 [15:12] */ 14191 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_CRC_COUNT_RESERVED1_MASK 0x0000f000 14192 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_CRC_COUNT_RESERVED1_ALIGN 0 14193 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_CRC_COUNT_RESERVED1_BITS 4 14194 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_CRC_COUNT_RESERVED1_SHIFT 12 14195 14196 /* DDR34_E0_PHY_BYTE_LANE_2 :: EDC_CRC_COUNT :: RD_COUNT [11:00] */ 14197 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_CRC_COUNT_RD_COUNT_MASK 0x00000fff 14198 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_CRC_COUNT_RD_COUNT_ALIGN 0 14199 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_CRC_COUNT_RD_COUNT_BITS 12 14200 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_CRC_COUNT_RD_COUNT_SHIFT 0 14201 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_CRC_COUNT_RD_COUNT_DEFAULT 0x00000000 14202 14203 /*************************************************************************** 14204 *EDC_CRC_STATUS_CLEAR - GDDR5M EDC signal path CRC counter register 14205 */ 14206 /* DDR34_E0_PHY_BYTE_LANE_2 :: EDC_CRC_STATUS_CLEAR :: reserved0 [31:01] */ 14207 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_CRC_STATUS_CLEAR_RESERVED0_MASK 0xfffffffe 14208 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_CRC_STATUS_CLEAR_RESERVED0_ALIGN 0 14209 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_CRC_STATUS_CLEAR_RESERVED0_BITS 31 14210 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_CRC_STATUS_CLEAR_RESERVED0_SHIFT 1 14211 14212 /* DDR34_E0_PHY_BYTE_LANE_2 :: EDC_CRC_STATUS_CLEAR :: CLEAR [00:00] */ 14213 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_CRC_STATUS_CLEAR_CLEAR_MASK 0x00000001 14214 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_CRC_STATUS_CLEAR_CLEAR_ALIGN 0 14215 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_CRC_STATUS_CLEAR_CLEAR_BITS 1 14216 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_CRC_STATUS_CLEAR_CLEAR_SHIFT 0 14217 #define DDR34_E0_PHY_BYTE_LANE_2_EDC_CRC_STATUS_CLEAR_CLEAR_DEFAULT 0x00000000 14218 14219 /*************************************************************************** 14220 *BL_SPARE_REG - Byte-Lane Spare register 14221 */ 14222 /* DDR34_E0_PHY_BYTE_LANE_2 :: BL_SPARE_REG :: reserved_for_eco0 [31:00] */ 14223 #define DDR34_E0_PHY_BYTE_LANE_2_BL_SPARE_REG_RESERVED_for_eco0_MASK 0xffffffff 14224 #define DDR34_E0_PHY_BYTE_LANE_2_BL_SPARE_REG_RESERVED_for_eco0_ALIGN 0 14225 #define DDR34_E0_PHY_BYTE_LANE_2_BL_SPARE_REG_RESERVED_for_eco0_BITS 32 14226 #define DDR34_E0_PHY_BYTE_LANE_2_BL_SPARE_REG_RESERVED_for_eco0_SHIFT 0 14227 #define DDR34_E0_PHY_BYTE_LANE_2_BL_SPARE_REG_RESERVED_for_eco0_DEFAULT 0x00000000 14228 14229 /*************************************************************************** 14230 *VDL_CONTROL_WR_DQS_P - Write channel DQS-P VDL control register 14231 */ 14232 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DQS_P :: BUSY [31:31] */ 14233 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_P_BUSY_MASK 0x80000000 14234 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_P_BUSY_ALIGN 0 14235 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_P_BUSY_BITS 1 14236 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_P_BUSY_SHIFT 31 14237 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_P_BUSY_DEFAULT 0x00000000 14238 14239 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DQS_P :: reserved0 [30:17] */ 14240 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_P_RESERVED0_MASK 0x7ffe0000 14241 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_P_RESERVED0_ALIGN 0 14242 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_P_RESERVED0_BITS 14 14243 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_P_RESERVED0_SHIFT 17 14244 14245 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DQS_P :: FORCE [16:16] */ 14246 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_P_FORCE_MASK 0x00010000 14247 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_P_FORCE_ALIGN 0 14248 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_P_FORCE_BITS 1 14249 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_P_FORCE_SHIFT 16 14250 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_P_FORCE_DEFAULT 0x00000000 14251 14252 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DQS_P :: reserved1 [15:13] */ 14253 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_P_RESERVED1_MASK 0x0000e000 14254 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_P_RESERVED1_ALIGN 0 14255 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_P_RESERVED1_BITS 3 14256 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_P_RESERVED1_SHIFT 13 14257 14258 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DQS_P :: ADJ_EN [12:12] */ 14259 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_P_ADJ_EN_MASK 0x00001000 14260 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_P_ADJ_EN_ALIGN 0 14261 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_P_ADJ_EN_BITS 1 14262 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_P_ADJ_EN_SHIFT 12 14263 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_P_ADJ_EN_DEFAULT 0x00000000 14264 14265 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DQS_P :: reserved2 [11:09] */ 14266 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_P_RESERVED2_MASK 0x00000e00 14267 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_P_RESERVED2_ALIGN 0 14268 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_P_RESERVED2_BITS 3 14269 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_P_RESERVED2_SHIFT 9 14270 14271 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DQS_P :: VDL_STEP [08:00] */ 14272 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_P_VDL_STEP_MASK 0x000001ff 14273 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_P_VDL_STEP_ALIGN 0 14274 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_P_VDL_STEP_BITS 9 14275 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_P_VDL_STEP_SHIFT 0 14276 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_P_VDL_STEP_DEFAULT 0x00000000 14277 14278 /*************************************************************************** 14279 *VDL_CONTROL_WR_DQS_N - Write channel DQS-N VDL control register 14280 */ 14281 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DQS_N :: BUSY [31:31] */ 14282 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_N_BUSY_MASK 0x80000000 14283 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_N_BUSY_ALIGN 0 14284 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_N_BUSY_BITS 1 14285 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_N_BUSY_SHIFT 31 14286 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_N_BUSY_DEFAULT 0x00000000 14287 14288 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DQS_N :: reserved0 [30:17] */ 14289 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_N_RESERVED0_MASK 0x7ffe0000 14290 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_N_RESERVED0_ALIGN 0 14291 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_N_RESERVED0_BITS 14 14292 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_N_RESERVED0_SHIFT 17 14293 14294 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DQS_N :: FORCE [16:16] */ 14295 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_N_FORCE_MASK 0x00010000 14296 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_N_FORCE_ALIGN 0 14297 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_N_FORCE_BITS 1 14298 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_N_FORCE_SHIFT 16 14299 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_N_FORCE_DEFAULT 0x00000000 14300 14301 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DQS_N :: reserved1 [15:13] */ 14302 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_N_RESERVED1_MASK 0x0000e000 14303 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_N_RESERVED1_ALIGN 0 14304 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_N_RESERVED1_BITS 3 14305 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_N_RESERVED1_SHIFT 13 14306 14307 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DQS_N :: ADJ_EN [12:12] */ 14308 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_N_ADJ_EN_MASK 0x00001000 14309 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_N_ADJ_EN_ALIGN 0 14310 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_N_ADJ_EN_BITS 1 14311 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_N_ADJ_EN_SHIFT 12 14312 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_N_ADJ_EN_DEFAULT 0x00000000 14313 14314 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DQS_N :: reserved2 [11:09] */ 14315 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_N_RESERVED2_MASK 0x00000e00 14316 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_N_RESERVED2_ALIGN 0 14317 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_N_RESERVED2_BITS 3 14318 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_N_RESERVED2_SHIFT 9 14319 14320 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DQS_N :: VDL_STEP [08:00] */ 14321 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_N_VDL_STEP_MASK 0x000001ff 14322 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_N_VDL_STEP_ALIGN 0 14323 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_N_VDL_STEP_BITS 9 14324 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_N_VDL_STEP_SHIFT 0 14325 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_N_VDL_STEP_DEFAULT 0x00000000 14326 14327 /*************************************************************************** 14328 *VDL_CONTROL_WR_DQ0 - Write channel DQ0 VDL control register 14329 */ 14330 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DQ0 :: BUSY [31:31] */ 14331 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ0_BUSY_MASK 0x80000000 14332 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ0_BUSY_ALIGN 0 14333 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ0_BUSY_BITS 1 14334 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ0_BUSY_SHIFT 31 14335 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ0_BUSY_DEFAULT 0x00000000 14336 14337 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DQ0 :: reserved0 [30:17] */ 14338 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ0_RESERVED0_MASK 0x7ffe0000 14339 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ0_RESERVED0_ALIGN 0 14340 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ0_RESERVED0_BITS 14 14341 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ0_RESERVED0_SHIFT 17 14342 14343 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DQ0 :: FORCE [16:16] */ 14344 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ0_FORCE_MASK 0x00010000 14345 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ0_FORCE_ALIGN 0 14346 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ0_FORCE_BITS 1 14347 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ0_FORCE_SHIFT 16 14348 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ0_FORCE_DEFAULT 0x00000000 14349 14350 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DQ0 :: reserved1 [15:13] */ 14351 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ0_RESERVED1_MASK 0x0000e000 14352 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ0_RESERVED1_ALIGN 0 14353 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ0_RESERVED1_BITS 3 14354 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ0_RESERVED1_SHIFT 13 14355 14356 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DQ0 :: ADJ_EN [12:12] */ 14357 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ0_ADJ_EN_MASK 0x00001000 14358 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ0_ADJ_EN_ALIGN 0 14359 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ0_ADJ_EN_BITS 1 14360 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ0_ADJ_EN_SHIFT 12 14361 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ0_ADJ_EN_DEFAULT 0x00000000 14362 14363 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DQ0 :: reserved2 [11:09] */ 14364 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ0_RESERVED2_MASK 0x00000e00 14365 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ0_RESERVED2_ALIGN 0 14366 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ0_RESERVED2_BITS 3 14367 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ0_RESERVED2_SHIFT 9 14368 14369 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DQ0 :: VDL_STEP [08:00] */ 14370 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ0_VDL_STEP_MASK 0x000001ff 14371 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ0_VDL_STEP_ALIGN 0 14372 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ0_VDL_STEP_BITS 9 14373 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ0_VDL_STEP_SHIFT 0 14374 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ0_VDL_STEP_DEFAULT 0x00000000 14375 14376 /*************************************************************************** 14377 *VDL_CONTROL_WR_DQ1 - Write channel DQ1 VDL control register 14378 */ 14379 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DQ1 :: BUSY [31:31] */ 14380 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ1_BUSY_MASK 0x80000000 14381 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ1_BUSY_ALIGN 0 14382 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ1_BUSY_BITS 1 14383 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ1_BUSY_SHIFT 31 14384 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ1_BUSY_DEFAULT 0x00000000 14385 14386 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DQ1 :: reserved0 [30:17] */ 14387 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ1_RESERVED0_MASK 0x7ffe0000 14388 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ1_RESERVED0_ALIGN 0 14389 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ1_RESERVED0_BITS 14 14390 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ1_RESERVED0_SHIFT 17 14391 14392 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DQ1 :: FORCE [16:16] */ 14393 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ1_FORCE_MASK 0x00010000 14394 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ1_FORCE_ALIGN 0 14395 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ1_FORCE_BITS 1 14396 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ1_FORCE_SHIFT 16 14397 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ1_FORCE_DEFAULT 0x00000000 14398 14399 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DQ1 :: reserved1 [15:13] */ 14400 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ1_RESERVED1_MASK 0x0000e000 14401 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ1_RESERVED1_ALIGN 0 14402 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ1_RESERVED1_BITS 3 14403 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ1_RESERVED1_SHIFT 13 14404 14405 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DQ1 :: ADJ_EN [12:12] */ 14406 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ1_ADJ_EN_MASK 0x00001000 14407 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ1_ADJ_EN_ALIGN 0 14408 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ1_ADJ_EN_BITS 1 14409 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ1_ADJ_EN_SHIFT 12 14410 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ1_ADJ_EN_DEFAULT 0x00000000 14411 14412 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DQ1 :: reserved2 [11:09] */ 14413 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ1_RESERVED2_MASK 0x00000e00 14414 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ1_RESERVED2_ALIGN 0 14415 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ1_RESERVED2_BITS 3 14416 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ1_RESERVED2_SHIFT 9 14417 14418 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DQ1 :: VDL_STEP [08:00] */ 14419 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ1_VDL_STEP_MASK 0x000001ff 14420 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ1_VDL_STEP_ALIGN 0 14421 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ1_VDL_STEP_BITS 9 14422 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ1_VDL_STEP_SHIFT 0 14423 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ1_VDL_STEP_DEFAULT 0x00000000 14424 14425 /*************************************************************************** 14426 *VDL_CONTROL_WR_DQ2 - Write channel DQ2 VDL control register 14427 */ 14428 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DQ2 :: BUSY [31:31] */ 14429 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ2_BUSY_MASK 0x80000000 14430 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ2_BUSY_ALIGN 0 14431 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ2_BUSY_BITS 1 14432 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ2_BUSY_SHIFT 31 14433 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ2_BUSY_DEFAULT 0x00000000 14434 14435 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DQ2 :: reserved0 [30:17] */ 14436 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ2_RESERVED0_MASK 0x7ffe0000 14437 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ2_RESERVED0_ALIGN 0 14438 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ2_RESERVED0_BITS 14 14439 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ2_RESERVED0_SHIFT 17 14440 14441 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DQ2 :: FORCE [16:16] */ 14442 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ2_FORCE_MASK 0x00010000 14443 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ2_FORCE_ALIGN 0 14444 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ2_FORCE_BITS 1 14445 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ2_FORCE_SHIFT 16 14446 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ2_FORCE_DEFAULT 0x00000000 14447 14448 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DQ2 :: reserved1 [15:13] */ 14449 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ2_RESERVED1_MASK 0x0000e000 14450 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ2_RESERVED1_ALIGN 0 14451 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ2_RESERVED1_BITS 3 14452 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ2_RESERVED1_SHIFT 13 14453 14454 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DQ2 :: ADJ_EN [12:12] */ 14455 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ2_ADJ_EN_MASK 0x00001000 14456 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ2_ADJ_EN_ALIGN 0 14457 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ2_ADJ_EN_BITS 1 14458 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ2_ADJ_EN_SHIFT 12 14459 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ2_ADJ_EN_DEFAULT 0x00000000 14460 14461 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DQ2 :: reserved2 [11:09] */ 14462 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ2_RESERVED2_MASK 0x00000e00 14463 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ2_RESERVED2_ALIGN 0 14464 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ2_RESERVED2_BITS 3 14465 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ2_RESERVED2_SHIFT 9 14466 14467 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DQ2 :: VDL_STEP [08:00] */ 14468 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ2_VDL_STEP_MASK 0x000001ff 14469 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ2_VDL_STEP_ALIGN 0 14470 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ2_VDL_STEP_BITS 9 14471 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ2_VDL_STEP_SHIFT 0 14472 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ2_VDL_STEP_DEFAULT 0x00000000 14473 14474 /*************************************************************************** 14475 *VDL_CONTROL_WR_DQ3 - Write channel DQ3 VDL control register 14476 */ 14477 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DQ3 :: BUSY [31:31] */ 14478 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ3_BUSY_MASK 0x80000000 14479 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ3_BUSY_ALIGN 0 14480 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ3_BUSY_BITS 1 14481 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ3_BUSY_SHIFT 31 14482 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ3_BUSY_DEFAULT 0x00000000 14483 14484 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DQ3 :: reserved0 [30:17] */ 14485 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ3_RESERVED0_MASK 0x7ffe0000 14486 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ3_RESERVED0_ALIGN 0 14487 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ3_RESERVED0_BITS 14 14488 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ3_RESERVED0_SHIFT 17 14489 14490 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DQ3 :: FORCE [16:16] */ 14491 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ3_FORCE_MASK 0x00010000 14492 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ3_FORCE_ALIGN 0 14493 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ3_FORCE_BITS 1 14494 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ3_FORCE_SHIFT 16 14495 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ3_FORCE_DEFAULT 0x00000000 14496 14497 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DQ3 :: reserved1 [15:13] */ 14498 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ3_RESERVED1_MASK 0x0000e000 14499 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ3_RESERVED1_ALIGN 0 14500 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ3_RESERVED1_BITS 3 14501 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ3_RESERVED1_SHIFT 13 14502 14503 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DQ3 :: ADJ_EN [12:12] */ 14504 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ3_ADJ_EN_MASK 0x00001000 14505 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ3_ADJ_EN_ALIGN 0 14506 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ3_ADJ_EN_BITS 1 14507 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ3_ADJ_EN_SHIFT 12 14508 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ3_ADJ_EN_DEFAULT 0x00000000 14509 14510 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DQ3 :: reserved2 [11:09] */ 14511 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ3_RESERVED2_MASK 0x00000e00 14512 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ3_RESERVED2_ALIGN 0 14513 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ3_RESERVED2_BITS 3 14514 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ3_RESERVED2_SHIFT 9 14515 14516 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DQ3 :: VDL_STEP [08:00] */ 14517 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ3_VDL_STEP_MASK 0x000001ff 14518 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ3_VDL_STEP_ALIGN 0 14519 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ3_VDL_STEP_BITS 9 14520 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ3_VDL_STEP_SHIFT 0 14521 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ3_VDL_STEP_DEFAULT 0x00000000 14522 14523 /*************************************************************************** 14524 *VDL_CONTROL_WR_DQ4 - Write channel DQ4 VDL control register 14525 */ 14526 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DQ4 :: BUSY [31:31] */ 14527 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ4_BUSY_MASK 0x80000000 14528 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ4_BUSY_ALIGN 0 14529 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ4_BUSY_BITS 1 14530 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ4_BUSY_SHIFT 31 14531 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ4_BUSY_DEFAULT 0x00000000 14532 14533 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DQ4 :: reserved0 [30:17] */ 14534 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ4_RESERVED0_MASK 0x7ffe0000 14535 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ4_RESERVED0_ALIGN 0 14536 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ4_RESERVED0_BITS 14 14537 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ4_RESERVED0_SHIFT 17 14538 14539 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DQ4 :: FORCE [16:16] */ 14540 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ4_FORCE_MASK 0x00010000 14541 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ4_FORCE_ALIGN 0 14542 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ4_FORCE_BITS 1 14543 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ4_FORCE_SHIFT 16 14544 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ4_FORCE_DEFAULT 0x00000000 14545 14546 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DQ4 :: reserved1 [15:13] */ 14547 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ4_RESERVED1_MASK 0x0000e000 14548 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ4_RESERVED1_ALIGN 0 14549 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ4_RESERVED1_BITS 3 14550 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ4_RESERVED1_SHIFT 13 14551 14552 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DQ4 :: ADJ_EN [12:12] */ 14553 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ4_ADJ_EN_MASK 0x00001000 14554 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ4_ADJ_EN_ALIGN 0 14555 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ4_ADJ_EN_BITS 1 14556 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ4_ADJ_EN_SHIFT 12 14557 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ4_ADJ_EN_DEFAULT 0x00000000 14558 14559 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DQ4 :: reserved2 [11:09] */ 14560 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ4_RESERVED2_MASK 0x00000e00 14561 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ4_RESERVED2_ALIGN 0 14562 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ4_RESERVED2_BITS 3 14563 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ4_RESERVED2_SHIFT 9 14564 14565 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DQ4 :: VDL_STEP [08:00] */ 14566 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ4_VDL_STEP_MASK 0x000001ff 14567 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ4_VDL_STEP_ALIGN 0 14568 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ4_VDL_STEP_BITS 9 14569 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ4_VDL_STEP_SHIFT 0 14570 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ4_VDL_STEP_DEFAULT 0x00000000 14571 14572 /*************************************************************************** 14573 *VDL_CONTROL_WR_DQ5 - Write channel DQ5 VDL control register 14574 */ 14575 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DQ5 :: BUSY [31:31] */ 14576 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ5_BUSY_MASK 0x80000000 14577 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ5_BUSY_ALIGN 0 14578 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ5_BUSY_BITS 1 14579 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ5_BUSY_SHIFT 31 14580 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ5_BUSY_DEFAULT 0x00000000 14581 14582 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DQ5 :: reserved0 [30:17] */ 14583 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ5_RESERVED0_MASK 0x7ffe0000 14584 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ5_RESERVED0_ALIGN 0 14585 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ5_RESERVED0_BITS 14 14586 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ5_RESERVED0_SHIFT 17 14587 14588 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DQ5 :: FORCE [16:16] */ 14589 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ5_FORCE_MASK 0x00010000 14590 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ5_FORCE_ALIGN 0 14591 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ5_FORCE_BITS 1 14592 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ5_FORCE_SHIFT 16 14593 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ5_FORCE_DEFAULT 0x00000000 14594 14595 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DQ5 :: reserved1 [15:13] */ 14596 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ5_RESERVED1_MASK 0x0000e000 14597 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ5_RESERVED1_ALIGN 0 14598 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ5_RESERVED1_BITS 3 14599 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ5_RESERVED1_SHIFT 13 14600 14601 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DQ5 :: ADJ_EN [12:12] */ 14602 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ5_ADJ_EN_MASK 0x00001000 14603 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ5_ADJ_EN_ALIGN 0 14604 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ5_ADJ_EN_BITS 1 14605 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ5_ADJ_EN_SHIFT 12 14606 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ5_ADJ_EN_DEFAULT 0x00000000 14607 14608 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DQ5 :: reserved2 [11:09] */ 14609 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ5_RESERVED2_MASK 0x00000e00 14610 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ5_RESERVED2_ALIGN 0 14611 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ5_RESERVED2_BITS 3 14612 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ5_RESERVED2_SHIFT 9 14613 14614 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DQ5 :: VDL_STEP [08:00] */ 14615 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ5_VDL_STEP_MASK 0x000001ff 14616 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ5_VDL_STEP_ALIGN 0 14617 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ5_VDL_STEP_BITS 9 14618 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ5_VDL_STEP_SHIFT 0 14619 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ5_VDL_STEP_DEFAULT 0x00000000 14620 14621 /*************************************************************************** 14622 *VDL_CONTROL_WR_DQ6 - Write channel DQ6 VDL control register 14623 */ 14624 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DQ6 :: BUSY [31:31] */ 14625 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ6_BUSY_MASK 0x80000000 14626 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ6_BUSY_ALIGN 0 14627 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ6_BUSY_BITS 1 14628 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ6_BUSY_SHIFT 31 14629 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ6_BUSY_DEFAULT 0x00000000 14630 14631 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DQ6 :: reserved0 [30:17] */ 14632 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ6_RESERVED0_MASK 0x7ffe0000 14633 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ6_RESERVED0_ALIGN 0 14634 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ6_RESERVED0_BITS 14 14635 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ6_RESERVED0_SHIFT 17 14636 14637 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DQ6 :: FORCE [16:16] */ 14638 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ6_FORCE_MASK 0x00010000 14639 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ6_FORCE_ALIGN 0 14640 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ6_FORCE_BITS 1 14641 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ6_FORCE_SHIFT 16 14642 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ6_FORCE_DEFAULT 0x00000000 14643 14644 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DQ6 :: reserved1 [15:13] */ 14645 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ6_RESERVED1_MASK 0x0000e000 14646 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ6_RESERVED1_ALIGN 0 14647 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ6_RESERVED1_BITS 3 14648 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ6_RESERVED1_SHIFT 13 14649 14650 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DQ6 :: ADJ_EN [12:12] */ 14651 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ6_ADJ_EN_MASK 0x00001000 14652 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ6_ADJ_EN_ALIGN 0 14653 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ6_ADJ_EN_BITS 1 14654 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ6_ADJ_EN_SHIFT 12 14655 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ6_ADJ_EN_DEFAULT 0x00000000 14656 14657 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DQ6 :: reserved2 [11:09] */ 14658 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ6_RESERVED2_MASK 0x00000e00 14659 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ6_RESERVED2_ALIGN 0 14660 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ6_RESERVED2_BITS 3 14661 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ6_RESERVED2_SHIFT 9 14662 14663 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DQ6 :: VDL_STEP [08:00] */ 14664 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ6_VDL_STEP_MASK 0x000001ff 14665 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ6_VDL_STEP_ALIGN 0 14666 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ6_VDL_STEP_BITS 9 14667 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ6_VDL_STEP_SHIFT 0 14668 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ6_VDL_STEP_DEFAULT 0x00000000 14669 14670 /*************************************************************************** 14671 *VDL_CONTROL_WR_DQ7 - Write channel DQ7 VDL control register 14672 */ 14673 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DQ7 :: BUSY [31:31] */ 14674 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ7_BUSY_MASK 0x80000000 14675 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ7_BUSY_ALIGN 0 14676 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ7_BUSY_BITS 1 14677 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ7_BUSY_SHIFT 31 14678 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ7_BUSY_DEFAULT 0x00000000 14679 14680 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DQ7 :: reserved0 [30:17] */ 14681 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ7_RESERVED0_MASK 0x7ffe0000 14682 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ7_RESERVED0_ALIGN 0 14683 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ7_RESERVED0_BITS 14 14684 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ7_RESERVED0_SHIFT 17 14685 14686 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DQ7 :: FORCE [16:16] */ 14687 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ7_FORCE_MASK 0x00010000 14688 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ7_FORCE_ALIGN 0 14689 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ7_FORCE_BITS 1 14690 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ7_FORCE_SHIFT 16 14691 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ7_FORCE_DEFAULT 0x00000000 14692 14693 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DQ7 :: reserved1 [15:13] */ 14694 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ7_RESERVED1_MASK 0x0000e000 14695 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ7_RESERVED1_ALIGN 0 14696 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ7_RESERVED1_BITS 3 14697 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ7_RESERVED1_SHIFT 13 14698 14699 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DQ7 :: ADJ_EN [12:12] */ 14700 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ7_ADJ_EN_MASK 0x00001000 14701 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ7_ADJ_EN_ALIGN 0 14702 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ7_ADJ_EN_BITS 1 14703 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ7_ADJ_EN_SHIFT 12 14704 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ7_ADJ_EN_DEFAULT 0x00000000 14705 14706 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DQ7 :: reserved2 [11:09] */ 14707 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ7_RESERVED2_MASK 0x00000e00 14708 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ7_RESERVED2_ALIGN 0 14709 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ7_RESERVED2_BITS 3 14710 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ7_RESERVED2_SHIFT 9 14711 14712 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DQ7 :: VDL_STEP [08:00] */ 14713 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ7_VDL_STEP_MASK 0x000001ff 14714 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ7_VDL_STEP_ALIGN 0 14715 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ7_VDL_STEP_BITS 9 14716 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ7_VDL_STEP_SHIFT 0 14717 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ7_VDL_STEP_DEFAULT 0x00000000 14718 14719 /*************************************************************************** 14720 *VDL_CONTROL_WR_DM - Write channel DM VDL control register 14721 */ 14722 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DM :: BUSY [31:31] */ 14723 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DM_BUSY_MASK 0x80000000 14724 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DM_BUSY_ALIGN 0 14725 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DM_BUSY_BITS 1 14726 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DM_BUSY_SHIFT 31 14727 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DM_BUSY_DEFAULT 0x00000000 14728 14729 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DM :: reserved0 [30:17] */ 14730 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DM_RESERVED0_MASK 0x7ffe0000 14731 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DM_RESERVED0_ALIGN 0 14732 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DM_RESERVED0_BITS 14 14733 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DM_RESERVED0_SHIFT 17 14734 14735 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DM :: FORCE [16:16] */ 14736 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DM_FORCE_MASK 0x00010000 14737 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DM_FORCE_ALIGN 0 14738 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DM_FORCE_BITS 1 14739 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DM_FORCE_SHIFT 16 14740 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DM_FORCE_DEFAULT 0x00000000 14741 14742 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DM :: reserved1 [15:13] */ 14743 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DM_RESERVED1_MASK 0x0000e000 14744 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DM_RESERVED1_ALIGN 0 14745 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DM_RESERVED1_BITS 3 14746 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DM_RESERVED1_SHIFT 13 14747 14748 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DM :: ADJ_EN [12:12] */ 14749 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DM_ADJ_EN_MASK 0x00001000 14750 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DM_ADJ_EN_ALIGN 0 14751 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DM_ADJ_EN_BITS 1 14752 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DM_ADJ_EN_SHIFT 12 14753 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DM_ADJ_EN_DEFAULT 0x00000000 14754 14755 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DM :: reserved2 [11:09] */ 14756 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DM_RESERVED2_MASK 0x00000e00 14757 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DM_RESERVED2_ALIGN 0 14758 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DM_RESERVED2_BITS 3 14759 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DM_RESERVED2_SHIFT 9 14760 14761 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_DM :: VDL_STEP [08:00] */ 14762 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DM_VDL_STEP_MASK 0x000001ff 14763 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DM_VDL_STEP_ALIGN 0 14764 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DM_VDL_STEP_BITS 9 14765 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DM_VDL_STEP_SHIFT 0 14766 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DM_VDL_STEP_DEFAULT 0x00000000 14767 14768 /*************************************************************************** 14769 *VDL_CONTROL_WR_EDC - Write channel EDC VDL control register 14770 */ 14771 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_EDC :: BUSY [31:31] */ 14772 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_EDC_BUSY_MASK 0x80000000 14773 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_EDC_BUSY_ALIGN 0 14774 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_EDC_BUSY_BITS 1 14775 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_EDC_BUSY_SHIFT 31 14776 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_EDC_BUSY_DEFAULT 0x00000000 14777 14778 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_EDC :: reserved0 [30:17] */ 14779 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_EDC_RESERVED0_MASK 0x7ffe0000 14780 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_EDC_RESERVED0_ALIGN 0 14781 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_EDC_RESERVED0_BITS 14 14782 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_EDC_RESERVED0_SHIFT 17 14783 14784 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_EDC :: FORCE [16:16] */ 14785 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_EDC_FORCE_MASK 0x00010000 14786 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_EDC_FORCE_ALIGN 0 14787 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_EDC_FORCE_BITS 1 14788 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_EDC_FORCE_SHIFT 16 14789 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_EDC_FORCE_DEFAULT 0x00000000 14790 14791 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_EDC :: reserved1 [15:13] */ 14792 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_EDC_RESERVED1_MASK 0x0000e000 14793 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_EDC_RESERVED1_ALIGN 0 14794 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_EDC_RESERVED1_BITS 3 14795 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_EDC_RESERVED1_SHIFT 13 14796 14797 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_EDC :: ADJ_EN [12:12] */ 14798 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_EDC_ADJ_EN_MASK 0x00001000 14799 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_EDC_ADJ_EN_ALIGN 0 14800 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_EDC_ADJ_EN_BITS 1 14801 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_EDC_ADJ_EN_SHIFT 12 14802 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_EDC_ADJ_EN_DEFAULT 0x00000000 14803 14804 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_EDC :: reserved2 [11:09] */ 14805 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_EDC_RESERVED2_MASK 0x00000e00 14806 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_EDC_RESERVED2_ALIGN 0 14807 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_EDC_RESERVED2_BITS 3 14808 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_EDC_RESERVED2_SHIFT 9 14809 14810 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_WR_EDC :: VDL_STEP [08:00] */ 14811 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_EDC_VDL_STEP_MASK 0x000001ff 14812 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_EDC_VDL_STEP_ALIGN 0 14813 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_EDC_VDL_STEP_BITS 9 14814 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_EDC_VDL_STEP_SHIFT 0 14815 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_EDC_VDL_STEP_DEFAULT 0x00000000 14816 14817 /*************************************************************************** 14818 *VDL_CONTROL_RD_DQSP - Read channel DQSP VDL control register 14819 */ 14820 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQSP :: BUSY [31:31] */ 14821 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSP_BUSY_MASK 0x80000000 14822 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSP_BUSY_ALIGN 0 14823 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSP_BUSY_BITS 1 14824 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSP_BUSY_SHIFT 31 14825 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSP_BUSY_DEFAULT 0x00000000 14826 14827 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQSP :: reserved0 [30:17] */ 14828 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSP_RESERVED0_MASK 0x7ffe0000 14829 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSP_RESERVED0_ALIGN 0 14830 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSP_RESERVED0_BITS 14 14831 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSP_RESERVED0_SHIFT 17 14832 14833 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQSP :: FORCE [16:16] */ 14834 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSP_FORCE_MASK 0x00010000 14835 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSP_FORCE_ALIGN 0 14836 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSP_FORCE_BITS 1 14837 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSP_FORCE_SHIFT 16 14838 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSP_FORCE_DEFAULT 0x00000000 14839 14840 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQSP :: reserved1 [15:13] */ 14841 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSP_RESERVED1_MASK 0x0000e000 14842 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSP_RESERVED1_ALIGN 0 14843 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSP_RESERVED1_BITS 3 14844 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSP_RESERVED1_SHIFT 13 14845 14846 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQSP :: ADJ_EN [12:12] */ 14847 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSP_ADJ_EN_MASK 0x00001000 14848 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSP_ADJ_EN_ALIGN 0 14849 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSP_ADJ_EN_BITS 1 14850 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSP_ADJ_EN_SHIFT 12 14851 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSP_ADJ_EN_DEFAULT 0x00000000 14852 14853 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQSP :: reserved2 [11:08] */ 14854 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSP_RESERVED2_MASK 0x00000f00 14855 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSP_RESERVED2_ALIGN 0 14856 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSP_RESERVED2_BITS 4 14857 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSP_RESERVED2_SHIFT 8 14858 14859 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQSP :: VDL_STEP [07:00] */ 14860 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSP_VDL_STEP_MASK 0x000000ff 14861 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSP_VDL_STEP_ALIGN 0 14862 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSP_VDL_STEP_BITS 8 14863 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSP_VDL_STEP_SHIFT 0 14864 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSP_VDL_STEP_DEFAULT 0x00000000 14865 14866 /*************************************************************************** 14867 *VDL_CONTROL_RD_DQSN - Read channel DQSP VDL control register 14868 */ 14869 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQSN :: BUSY [31:31] */ 14870 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSN_BUSY_MASK 0x80000000 14871 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSN_BUSY_ALIGN 0 14872 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSN_BUSY_BITS 1 14873 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSN_BUSY_SHIFT 31 14874 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSN_BUSY_DEFAULT 0x00000000 14875 14876 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQSN :: reserved0 [30:17] */ 14877 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSN_RESERVED0_MASK 0x7ffe0000 14878 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSN_RESERVED0_ALIGN 0 14879 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSN_RESERVED0_BITS 14 14880 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSN_RESERVED0_SHIFT 17 14881 14882 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQSN :: FORCE [16:16] */ 14883 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSN_FORCE_MASK 0x00010000 14884 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSN_FORCE_ALIGN 0 14885 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSN_FORCE_BITS 1 14886 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSN_FORCE_SHIFT 16 14887 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSN_FORCE_DEFAULT 0x00000000 14888 14889 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQSN :: reserved1 [15:13] */ 14890 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSN_RESERVED1_MASK 0x0000e000 14891 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSN_RESERVED1_ALIGN 0 14892 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSN_RESERVED1_BITS 3 14893 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSN_RESERVED1_SHIFT 13 14894 14895 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQSN :: ADJ_EN [12:12] */ 14896 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSN_ADJ_EN_MASK 0x00001000 14897 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSN_ADJ_EN_ALIGN 0 14898 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSN_ADJ_EN_BITS 1 14899 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSN_ADJ_EN_SHIFT 12 14900 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSN_ADJ_EN_DEFAULT 0x00000000 14901 14902 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQSN :: reserved2 [11:08] */ 14903 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSN_RESERVED2_MASK 0x00000f00 14904 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSN_RESERVED2_ALIGN 0 14905 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSN_RESERVED2_BITS 4 14906 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSN_RESERVED2_SHIFT 8 14907 14908 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQSN :: VDL_STEP [07:00] */ 14909 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSN_VDL_STEP_MASK 0x000000ff 14910 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSN_VDL_STEP_ALIGN 0 14911 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSN_VDL_STEP_BITS 8 14912 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSN_VDL_STEP_SHIFT 0 14913 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSN_VDL_STEP_DEFAULT 0x00000000 14914 14915 /*************************************************************************** 14916 *VDL_CONTROL_RD_DQ0P - Read channel DQ0-P VDL control register 14917 */ 14918 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ0P :: BUSY [31:31] */ 14919 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0P_BUSY_MASK 0x80000000 14920 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0P_BUSY_ALIGN 0 14921 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0P_BUSY_BITS 1 14922 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0P_BUSY_SHIFT 31 14923 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0P_BUSY_DEFAULT 0x00000000 14924 14925 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ0P :: reserved0 [30:17] */ 14926 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0P_RESERVED0_MASK 0x7ffe0000 14927 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0P_RESERVED0_ALIGN 0 14928 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0P_RESERVED0_BITS 14 14929 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0P_RESERVED0_SHIFT 17 14930 14931 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ0P :: FORCE [16:16] */ 14932 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0P_FORCE_MASK 0x00010000 14933 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0P_FORCE_ALIGN 0 14934 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0P_FORCE_BITS 1 14935 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0P_FORCE_SHIFT 16 14936 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0P_FORCE_DEFAULT 0x00000000 14937 14938 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ0P :: reserved1 [15:13] */ 14939 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0P_RESERVED1_MASK 0x0000e000 14940 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0P_RESERVED1_ALIGN 0 14941 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0P_RESERVED1_BITS 3 14942 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0P_RESERVED1_SHIFT 13 14943 14944 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ0P :: ADJ_EN [12:12] */ 14945 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0P_ADJ_EN_MASK 0x00001000 14946 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0P_ADJ_EN_ALIGN 0 14947 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0P_ADJ_EN_BITS 1 14948 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0P_ADJ_EN_SHIFT 12 14949 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0P_ADJ_EN_DEFAULT 0x00000000 14950 14951 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ0P :: reserved2 [11:08] */ 14952 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0P_RESERVED2_MASK 0x00000f00 14953 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0P_RESERVED2_ALIGN 0 14954 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0P_RESERVED2_BITS 4 14955 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0P_RESERVED2_SHIFT 8 14956 14957 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ0P :: VDL_STEP [07:00] */ 14958 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0P_VDL_STEP_MASK 0x000000ff 14959 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0P_VDL_STEP_ALIGN 0 14960 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0P_VDL_STEP_BITS 8 14961 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0P_VDL_STEP_SHIFT 0 14962 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0P_VDL_STEP_DEFAULT 0x00000000 14963 14964 /*************************************************************************** 14965 *VDL_CONTROL_RD_DQ0N - Read channel DQ0-N VDL control register 14966 */ 14967 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ0N :: BUSY [31:31] */ 14968 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0N_BUSY_MASK 0x80000000 14969 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0N_BUSY_ALIGN 0 14970 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0N_BUSY_BITS 1 14971 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0N_BUSY_SHIFT 31 14972 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0N_BUSY_DEFAULT 0x00000000 14973 14974 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ0N :: reserved0 [30:17] */ 14975 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0N_RESERVED0_MASK 0x7ffe0000 14976 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0N_RESERVED0_ALIGN 0 14977 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0N_RESERVED0_BITS 14 14978 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0N_RESERVED0_SHIFT 17 14979 14980 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ0N :: FORCE [16:16] */ 14981 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0N_FORCE_MASK 0x00010000 14982 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0N_FORCE_ALIGN 0 14983 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0N_FORCE_BITS 1 14984 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0N_FORCE_SHIFT 16 14985 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0N_FORCE_DEFAULT 0x00000000 14986 14987 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ0N :: reserved1 [15:13] */ 14988 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0N_RESERVED1_MASK 0x0000e000 14989 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0N_RESERVED1_ALIGN 0 14990 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0N_RESERVED1_BITS 3 14991 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0N_RESERVED1_SHIFT 13 14992 14993 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ0N :: ADJ_EN [12:12] */ 14994 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0N_ADJ_EN_MASK 0x00001000 14995 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0N_ADJ_EN_ALIGN 0 14996 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0N_ADJ_EN_BITS 1 14997 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0N_ADJ_EN_SHIFT 12 14998 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0N_ADJ_EN_DEFAULT 0x00000000 14999 15000 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ0N :: reserved2 [11:08] */ 15001 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0N_RESERVED2_MASK 0x00000f00 15002 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0N_RESERVED2_ALIGN 0 15003 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0N_RESERVED2_BITS 4 15004 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0N_RESERVED2_SHIFT 8 15005 15006 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ0N :: VDL_STEP [07:00] */ 15007 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0N_VDL_STEP_MASK 0x000000ff 15008 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0N_VDL_STEP_ALIGN 0 15009 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0N_VDL_STEP_BITS 8 15010 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0N_VDL_STEP_SHIFT 0 15011 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0N_VDL_STEP_DEFAULT 0x00000000 15012 15013 /*************************************************************************** 15014 *VDL_CONTROL_RD_DQ1P - Read channel DQ1-P VDL control register 15015 */ 15016 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ1P :: BUSY [31:31] */ 15017 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1P_BUSY_MASK 0x80000000 15018 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1P_BUSY_ALIGN 0 15019 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1P_BUSY_BITS 1 15020 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1P_BUSY_SHIFT 31 15021 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1P_BUSY_DEFAULT 0x00000000 15022 15023 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ1P :: reserved0 [30:17] */ 15024 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1P_RESERVED0_MASK 0x7ffe0000 15025 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1P_RESERVED0_ALIGN 0 15026 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1P_RESERVED0_BITS 14 15027 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1P_RESERVED0_SHIFT 17 15028 15029 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ1P :: FORCE [16:16] */ 15030 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1P_FORCE_MASK 0x00010000 15031 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1P_FORCE_ALIGN 0 15032 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1P_FORCE_BITS 1 15033 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1P_FORCE_SHIFT 16 15034 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1P_FORCE_DEFAULT 0x00000000 15035 15036 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ1P :: reserved1 [15:13] */ 15037 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1P_RESERVED1_MASK 0x0000e000 15038 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1P_RESERVED1_ALIGN 0 15039 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1P_RESERVED1_BITS 3 15040 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1P_RESERVED1_SHIFT 13 15041 15042 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ1P :: ADJ_EN [12:12] */ 15043 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1P_ADJ_EN_MASK 0x00001000 15044 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1P_ADJ_EN_ALIGN 0 15045 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1P_ADJ_EN_BITS 1 15046 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1P_ADJ_EN_SHIFT 12 15047 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1P_ADJ_EN_DEFAULT 0x00000000 15048 15049 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ1P :: reserved2 [11:08] */ 15050 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1P_RESERVED2_MASK 0x00000f00 15051 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1P_RESERVED2_ALIGN 0 15052 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1P_RESERVED2_BITS 4 15053 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1P_RESERVED2_SHIFT 8 15054 15055 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ1P :: VDL_STEP [07:00] */ 15056 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1P_VDL_STEP_MASK 0x000000ff 15057 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1P_VDL_STEP_ALIGN 0 15058 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1P_VDL_STEP_BITS 8 15059 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1P_VDL_STEP_SHIFT 0 15060 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1P_VDL_STEP_DEFAULT 0x00000000 15061 15062 /*************************************************************************** 15063 *VDL_CONTROL_RD_DQ1N - Read channel DQ1-N VDL control register 15064 */ 15065 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ1N :: BUSY [31:31] */ 15066 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1N_BUSY_MASK 0x80000000 15067 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1N_BUSY_ALIGN 0 15068 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1N_BUSY_BITS 1 15069 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1N_BUSY_SHIFT 31 15070 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1N_BUSY_DEFAULT 0x00000000 15071 15072 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ1N :: reserved0 [30:17] */ 15073 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1N_RESERVED0_MASK 0x7ffe0000 15074 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1N_RESERVED0_ALIGN 0 15075 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1N_RESERVED0_BITS 14 15076 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1N_RESERVED0_SHIFT 17 15077 15078 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ1N :: FORCE [16:16] */ 15079 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1N_FORCE_MASK 0x00010000 15080 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1N_FORCE_ALIGN 0 15081 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1N_FORCE_BITS 1 15082 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1N_FORCE_SHIFT 16 15083 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1N_FORCE_DEFAULT 0x00000000 15084 15085 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ1N :: reserved1 [15:13] */ 15086 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1N_RESERVED1_MASK 0x0000e000 15087 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1N_RESERVED1_ALIGN 0 15088 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1N_RESERVED1_BITS 3 15089 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1N_RESERVED1_SHIFT 13 15090 15091 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ1N :: ADJ_EN [12:12] */ 15092 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1N_ADJ_EN_MASK 0x00001000 15093 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1N_ADJ_EN_ALIGN 0 15094 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1N_ADJ_EN_BITS 1 15095 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1N_ADJ_EN_SHIFT 12 15096 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1N_ADJ_EN_DEFAULT 0x00000000 15097 15098 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ1N :: reserved2 [11:08] */ 15099 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1N_RESERVED2_MASK 0x00000f00 15100 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1N_RESERVED2_ALIGN 0 15101 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1N_RESERVED2_BITS 4 15102 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1N_RESERVED2_SHIFT 8 15103 15104 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ1N :: VDL_STEP [07:00] */ 15105 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1N_VDL_STEP_MASK 0x000000ff 15106 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1N_VDL_STEP_ALIGN 0 15107 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1N_VDL_STEP_BITS 8 15108 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1N_VDL_STEP_SHIFT 0 15109 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1N_VDL_STEP_DEFAULT 0x00000000 15110 15111 /*************************************************************************** 15112 *VDL_CONTROL_RD_DQ2P - Read channel DQ2-P VDL control register 15113 */ 15114 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ2P :: BUSY [31:31] */ 15115 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2P_BUSY_MASK 0x80000000 15116 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2P_BUSY_ALIGN 0 15117 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2P_BUSY_BITS 1 15118 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2P_BUSY_SHIFT 31 15119 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2P_BUSY_DEFAULT 0x00000000 15120 15121 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ2P :: reserved0 [30:17] */ 15122 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2P_RESERVED0_MASK 0x7ffe0000 15123 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2P_RESERVED0_ALIGN 0 15124 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2P_RESERVED0_BITS 14 15125 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2P_RESERVED0_SHIFT 17 15126 15127 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ2P :: FORCE [16:16] */ 15128 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2P_FORCE_MASK 0x00010000 15129 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2P_FORCE_ALIGN 0 15130 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2P_FORCE_BITS 1 15131 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2P_FORCE_SHIFT 16 15132 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2P_FORCE_DEFAULT 0x00000000 15133 15134 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ2P :: reserved1 [15:13] */ 15135 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2P_RESERVED1_MASK 0x0000e000 15136 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2P_RESERVED1_ALIGN 0 15137 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2P_RESERVED1_BITS 3 15138 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2P_RESERVED1_SHIFT 13 15139 15140 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ2P :: ADJ_EN [12:12] */ 15141 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2P_ADJ_EN_MASK 0x00001000 15142 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2P_ADJ_EN_ALIGN 0 15143 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2P_ADJ_EN_BITS 1 15144 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2P_ADJ_EN_SHIFT 12 15145 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2P_ADJ_EN_DEFAULT 0x00000000 15146 15147 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ2P :: reserved2 [11:08] */ 15148 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2P_RESERVED2_MASK 0x00000f00 15149 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2P_RESERVED2_ALIGN 0 15150 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2P_RESERVED2_BITS 4 15151 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2P_RESERVED2_SHIFT 8 15152 15153 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ2P :: VDL_STEP [07:00] */ 15154 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2P_VDL_STEP_MASK 0x000000ff 15155 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2P_VDL_STEP_ALIGN 0 15156 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2P_VDL_STEP_BITS 8 15157 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2P_VDL_STEP_SHIFT 0 15158 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2P_VDL_STEP_DEFAULT 0x00000000 15159 15160 /*************************************************************************** 15161 *VDL_CONTROL_RD_DQ2N - Read channel DQ2-N VDL control register 15162 */ 15163 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ2N :: BUSY [31:31] */ 15164 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2N_BUSY_MASK 0x80000000 15165 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2N_BUSY_ALIGN 0 15166 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2N_BUSY_BITS 1 15167 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2N_BUSY_SHIFT 31 15168 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2N_BUSY_DEFAULT 0x00000000 15169 15170 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ2N :: reserved0 [30:17] */ 15171 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2N_RESERVED0_MASK 0x7ffe0000 15172 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2N_RESERVED0_ALIGN 0 15173 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2N_RESERVED0_BITS 14 15174 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2N_RESERVED0_SHIFT 17 15175 15176 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ2N :: FORCE [16:16] */ 15177 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2N_FORCE_MASK 0x00010000 15178 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2N_FORCE_ALIGN 0 15179 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2N_FORCE_BITS 1 15180 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2N_FORCE_SHIFT 16 15181 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2N_FORCE_DEFAULT 0x00000000 15182 15183 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ2N :: reserved1 [15:13] */ 15184 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2N_RESERVED1_MASK 0x0000e000 15185 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2N_RESERVED1_ALIGN 0 15186 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2N_RESERVED1_BITS 3 15187 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2N_RESERVED1_SHIFT 13 15188 15189 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ2N :: ADJ_EN [12:12] */ 15190 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2N_ADJ_EN_MASK 0x00001000 15191 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2N_ADJ_EN_ALIGN 0 15192 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2N_ADJ_EN_BITS 1 15193 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2N_ADJ_EN_SHIFT 12 15194 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2N_ADJ_EN_DEFAULT 0x00000000 15195 15196 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ2N :: reserved2 [11:08] */ 15197 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2N_RESERVED2_MASK 0x00000f00 15198 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2N_RESERVED2_ALIGN 0 15199 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2N_RESERVED2_BITS 4 15200 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2N_RESERVED2_SHIFT 8 15201 15202 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ2N :: VDL_STEP [07:00] */ 15203 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2N_VDL_STEP_MASK 0x000000ff 15204 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2N_VDL_STEP_ALIGN 0 15205 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2N_VDL_STEP_BITS 8 15206 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2N_VDL_STEP_SHIFT 0 15207 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2N_VDL_STEP_DEFAULT 0x00000000 15208 15209 /*************************************************************************** 15210 *VDL_CONTROL_RD_DQ3P - Read channel DQ3-P VDL control register 15211 */ 15212 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ3P :: BUSY [31:31] */ 15213 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3P_BUSY_MASK 0x80000000 15214 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3P_BUSY_ALIGN 0 15215 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3P_BUSY_BITS 1 15216 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3P_BUSY_SHIFT 31 15217 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3P_BUSY_DEFAULT 0x00000000 15218 15219 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ3P :: reserved0 [30:17] */ 15220 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3P_RESERVED0_MASK 0x7ffe0000 15221 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3P_RESERVED0_ALIGN 0 15222 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3P_RESERVED0_BITS 14 15223 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3P_RESERVED0_SHIFT 17 15224 15225 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ3P :: FORCE [16:16] */ 15226 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3P_FORCE_MASK 0x00010000 15227 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3P_FORCE_ALIGN 0 15228 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3P_FORCE_BITS 1 15229 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3P_FORCE_SHIFT 16 15230 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3P_FORCE_DEFAULT 0x00000000 15231 15232 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ3P :: reserved1 [15:13] */ 15233 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3P_RESERVED1_MASK 0x0000e000 15234 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3P_RESERVED1_ALIGN 0 15235 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3P_RESERVED1_BITS 3 15236 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3P_RESERVED1_SHIFT 13 15237 15238 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ3P :: ADJ_EN [12:12] */ 15239 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3P_ADJ_EN_MASK 0x00001000 15240 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3P_ADJ_EN_ALIGN 0 15241 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3P_ADJ_EN_BITS 1 15242 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3P_ADJ_EN_SHIFT 12 15243 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3P_ADJ_EN_DEFAULT 0x00000000 15244 15245 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ3P :: reserved2 [11:08] */ 15246 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3P_RESERVED2_MASK 0x00000f00 15247 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3P_RESERVED2_ALIGN 0 15248 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3P_RESERVED2_BITS 4 15249 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3P_RESERVED2_SHIFT 8 15250 15251 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ3P :: VDL_STEP [07:00] */ 15252 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3P_VDL_STEP_MASK 0x000000ff 15253 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3P_VDL_STEP_ALIGN 0 15254 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3P_VDL_STEP_BITS 8 15255 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3P_VDL_STEP_SHIFT 0 15256 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3P_VDL_STEP_DEFAULT 0x00000000 15257 15258 /*************************************************************************** 15259 *VDL_CONTROL_RD_DQ3N - Read channel DQ3-N VDL control register 15260 */ 15261 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ3N :: BUSY [31:31] */ 15262 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3N_BUSY_MASK 0x80000000 15263 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3N_BUSY_ALIGN 0 15264 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3N_BUSY_BITS 1 15265 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3N_BUSY_SHIFT 31 15266 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3N_BUSY_DEFAULT 0x00000000 15267 15268 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ3N :: reserved0 [30:17] */ 15269 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3N_RESERVED0_MASK 0x7ffe0000 15270 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3N_RESERVED0_ALIGN 0 15271 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3N_RESERVED0_BITS 14 15272 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3N_RESERVED0_SHIFT 17 15273 15274 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ3N :: FORCE [16:16] */ 15275 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3N_FORCE_MASK 0x00010000 15276 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3N_FORCE_ALIGN 0 15277 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3N_FORCE_BITS 1 15278 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3N_FORCE_SHIFT 16 15279 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3N_FORCE_DEFAULT 0x00000000 15280 15281 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ3N :: reserved1 [15:13] */ 15282 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3N_RESERVED1_MASK 0x0000e000 15283 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3N_RESERVED1_ALIGN 0 15284 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3N_RESERVED1_BITS 3 15285 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3N_RESERVED1_SHIFT 13 15286 15287 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ3N :: ADJ_EN [12:12] */ 15288 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3N_ADJ_EN_MASK 0x00001000 15289 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3N_ADJ_EN_ALIGN 0 15290 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3N_ADJ_EN_BITS 1 15291 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3N_ADJ_EN_SHIFT 12 15292 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3N_ADJ_EN_DEFAULT 0x00000000 15293 15294 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ3N :: reserved2 [11:08] */ 15295 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3N_RESERVED2_MASK 0x00000f00 15296 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3N_RESERVED2_ALIGN 0 15297 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3N_RESERVED2_BITS 4 15298 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3N_RESERVED2_SHIFT 8 15299 15300 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ3N :: VDL_STEP [07:00] */ 15301 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3N_VDL_STEP_MASK 0x000000ff 15302 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3N_VDL_STEP_ALIGN 0 15303 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3N_VDL_STEP_BITS 8 15304 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3N_VDL_STEP_SHIFT 0 15305 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3N_VDL_STEP_DEFAULT 0x00000000 15306 15307 /*************************************************************************** 15308 *VDL_CONTROL_RD_DQ4P - Read channel DQ4-P VDL control register 15309 */ 15310 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ4P :: BUSY [31:31] */ 15311 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4P_BUSY_MASK 0x80000000 15312 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4P_BUSY_ALIGN 0 15313 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4P_BUSY_BITS 1 15314 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4P_BUSY_SHIFT 31 15315 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4P_BUSY_DEFAULT 0x00000000 15316 15317 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ4P :: reserved0 [30:17] */ 15318 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4P_RESERVED0_MASK 0x7ffe0000 15319 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4P_RESERVED0_ALIGN 0 15320 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4P_RESERVED0_BITS 14 15321 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4P_RESERVED0_SHIFT 17 15322 15323 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ4P :: FORCE [16:16] */ 15324 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4P_FORCE_MASK 0x00010000 15325 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4P_FORCE_ALIGN 0 15326 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4P_FORCE_BITS 1 15327 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4P_FORCE_SHIFT 16 15328 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4P_FORCE_DEFAULT 0x00000000 15329 15330 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ4P :: reserved1 [15:13] */ 15331 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4P_RESERVED1_MASK 0x0000e000 15332 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4P_RESERVED1_ALIGN 0 15333 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4P_RESERVED1_BITS 3 15334 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4P_RESERVED1_SHIFT 13 15335 15336 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ4P :: ADJ_EN [12:12] */ 15337 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4P_ADJ_EN_MASK 0x00001000 15338 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4P_ADJ_EN_ALIGN 0 15339 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4P_ADJ_EN_BITS 1 15340 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4P_ADJ_EN_SHIFT 12 15341 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4P_ADJ_EN_DEFAULT 0x00000000 15342 15343 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ4P :: reserved2 [11:08] */ 15344 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4P_RESERVED2_MASK 0x00000f00 15345 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4P_RESERVED2_ALIGN 0 15346 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4P_RESERVED2_BITS 4 15347 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4P_RESERVED2_SHIFT 8 15348 15349 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ4P :: VDL_STEP [07:00] */ 15350 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4P_VDL_STEP_MASK 0x000000ff 15351 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4P_VDL_STEP_ALIGN 0 15352 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4P_VDL_STEP_BITS 8 15353 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4P_VDL_STEP_SHIFT 0 15354 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4P_VDL_STEP_DEFAULT 0x00000000 15355 15356 /*************************************************************************** 15357 *VDL_CONTROL_RD_DQ4N - Read channel DQ4-N VDL control register 15358 */ 15359 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ4N :: BUSY [31:31] */ 15360 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4N_BUSY_MASK 0x80000000 15361 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4N_BUSY_ALIGN 0 15362 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4N_BUSY_BITS 1 15363 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4N_BUSY_SHIFT 31 15364 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4N_BUSY_DEFAULT 0x00000000 15365 15366 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ4N :: reserved0 [30:17] */ 15367 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4N_RESERVED0_MASK 0x7ffe0000 15368 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4N_RESERVED0_ALIGN 0 15369 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4N_RESERVED0_BITS 14 15370 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4N_RESERVED0_SHIFT 17 15371 15372 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ4N :: FORCE [16:16] */ 15373 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4N_FORCE_MASK 0x00010000 15374 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4N_FORCE_ALIGN 0 15375 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4N_FORCE_BITS 1 15376 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4N_FORCE_SHIFT 16 15377 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4N_FORCE_DEFAULT 0x00000000 15378 15379 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ4N :: reserved1 [15:13] */ 15380 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4N_RESERVED1_MASK 0x0000e000 15381 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4N_RESERVED1_ALIGN 0 15382 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4N_RESERVED1_BITS 3 15383 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4N_RESERVED1_SHIFT 13 15384 15385 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ4N :: ADJ_EN [12:12] */ 15386 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4N_ADJ_EN_MASK 0x00001000 15387 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4N_ADJ_EN_ALIGN 0 15388 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4N_ADJ_EN_BITS 1 15389 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4N_ADJ_EN_SHIFT 12 15390 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4N_ADJ_EN_DEFAULT 0x00000000 15391 15392 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ4N :: reserved2 [11:08] */ 15393 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4N_RESERVED2_MASK 0x00000f00 15394 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4N_RESERVED2_ALIGN 0 15395 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4N_RESERVED2_BITS 4 15396 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4N_RESERVED2_SHIFT 8 15397 15398 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ4N :: VDL_STEP [07:00] */ 15399 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4N_VDL_STEP_MASK 0x000000ff 15400 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4N_VDL_STEP_ALIGN 0 15401 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4N_VDL_STEP_BITS 8 15402 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4N_VDL_STEP_SHIFT 0 15403 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4N_VDL_STEP_DEFAULT 0x00000000 15404 15405 /*************************************************************************** 15406 *VDL_CONTROL_RD_DQ5P - Read channel DQ5-P VDL control register 15407 */ 15408 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ5P :: BUSY [31:31] */ 15409 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5P_BUSY_MASK 0x80000000 15410 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5P_BUSY_ALIGN 0 15411 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5P_BUSY_BITS 1 15412 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5P_BUSY_SHIFT 31 15413 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5P_BUSY_DEFAULT 0x00000000 15414 15415 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ5P :: reserved0 [30:17] */ 15416 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5P_RESERVED0_MASK 0x7ffe0000 15417 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5P_RESERVED0_ALIGN 0 15418 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5P_RESERVED0_BITS 14 15419 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5P_RESERVED0_SHIFT 17 15420 15421 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ5P :: FORCE [16:16] */ 15422 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5P_FORCE_MASK 0x00010000 15423 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5P_FORCE_ALIGN 0 15424 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5P_FORCE_BITS 1 15425 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5P_FORCE_SHIFT 16 15426 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5P_FORCE_DEFAULT 0x00000000 15427 15428 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ5P :: reserved1 [15:13] */ 15429 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5P_RESERVED1_MASK 0x0000e000 15430 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5P_RESERVED1_ALIGN 0 15431 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5P_RESERVED1_BITS 3 15432 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5P_RESERVED1_SHIFT 13 15433 15434 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ5P :: ADJ_EN [12:12] */ 15435 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5P_ADJ_EN_MASK 0x00001000 15436 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5P_ADJ_EN_ALIGN 0 15437 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5P_ADJ_EN_BITS 1 15438 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5P_ADJ_EN_SHIFT 12 15439 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5P_ADJ_EN_DEFAULT 0x00000000 15440 15441 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ5P :: reserved2 [11:08] */ 15442 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5P_RESERVED2_MASK 0x00000f00 15443 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5P_RESERVED2_ALIGN 0 15444 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5P_RESERVED2_BITS 4 15445 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5P_RESERVED2_SHIFT 8 15446 15447 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ5P :: VDL_STEP [07:00] */ 15448 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5P_VDL_STEP_MASK 0x000000ff 15449 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5P_VDL_STEP_ALIGN 0 15450 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5P_VDL_STEP_BITS 8 15451 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5P_VDL_STEP_SHIFT 0 15452 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5P_VDL_STEP_DEFAULT 0x00000000 15453 15454 /*************************************************************************** 15455 *VDL_CONTROL_RD_DQ5N - Read channel DQ5-N VDL control register 15456 */ 15457 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ5N :: BUSY [31:31] */ 15458 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5N_BUSY_MASK 0x80000000 15459 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5N_BUSY_ALIGN 0 15460 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5N_BUSY_BITS 1 15461 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5N_BUSY_SHIFT 31 15462 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5N_BUSY_DEFAULT 0x00000000 15463 15464 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ5N :: reserved0 [30:17] */ 15465 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5N_RESERVED0_MASK 0x7ffe0000 15466 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5N_RESERVED0_ALIGN 0 15467 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5N_RESERVED0_BITS 14 15468 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5N_RESERVED0_SHIFT 17 15469 15470 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ5N :: FORCE [16:16] */ 15471 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5N_FORCE_MASK 0x00010000 15472 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5N_FORCE_ALIGN 0 15473 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5N_FORCE_BITS 1 15474 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5N_FORCE_SHIFT 16 15475 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5N_FORCE_DEFAULT 0x00000000 15476 15477 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ5N :: reserved1 [15:13] */ 15478 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5N_RESERVED1_MASK 0x0000e000 15479 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5N_RESERVED1_ALIGN 0 15480 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5N_RESERVED1_BITS 3 15481 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5N_RESERVED1_SHIFT 13 15482 15483 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ5N :: ADJ_EN [12:12] */ 15484 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5N_ADJ_EN_MASK 0x00001000 15485 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5N_ADJ_EN_ALIGN 0 15486 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5N_ADJ_EN_BITS 1 15487 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5N_ADJ_EN_SHIFT 12 15488 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5N_ADJ_EN_DEFAULT 0x00000000 15489 15490 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ5N :: reserved2 [11:08] */ 15491 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5N_RESERVED2_MASK 0x00000f00 15492 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5N_RESERVED2_ALIGN 0 15493 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5N_RESERVED2_BITS 4 15494 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5N_RESERVED2_SHIFT 8 15495 15496 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ5N :: VDL_STEP [07:00] */ 15497 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5N_VDL_STEP_MASK 0x000000ff 15498 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5N_VDL_STEP_ALIGN 0 15499 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5N_VDL_STEP_BITS 8 15500 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5N_VDL_STEP_SHIFT 0 15501 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5N_VDL_STEP_DEFAULT 0x00000000 15502 15503 /*************************************************************************** 15504 *VDL_CONTROL_RD_DQ6P - Read channel DQ6-P VDL control register 15505 */ 15506 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ6P :: BUSY [31:31] */ 15507 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6P_BUSY_MASK 0x80000000 15508 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6P_BUSY_ALIGN 0 15509 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6P_BUSY_BITS 1 15510 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6P_BUSY_SHIFT 31 15511 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6P_BUSY_DEFAULT 0x00000000 15512 15513 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ6P :: reserved0 [30:17] */ 15514 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6P_RESERVED0_MASK 0x7ffe0000 15515 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6P_RESERVED0_ALIGN 0 15516 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6P_RESERVED0_BITS 14 15517 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6P_RESERVED0_SHIFT 17 15518 15519 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ6P :: FORCE [16:16] */ 15520 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6P_FORCE_MASK 0x00010000 15521 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6P_FORCE_ALIGN 0 15522 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6P_FORCE_BITS 1 15523 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6P_FORCE_SHIFT 16 15524 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6P_FORCE_DEFAULT 0x00000000 15525 15526 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ6P :: reserved1 [15:13] */ 15527 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6P_RESERVED1_MASK 0x0000e000 15528 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6P_RESERVED1_ALIGN 0 15529 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6P_RESERVED1_BITS 3 15530 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6P_RESERVED1_SHIFT 13 15531 15532 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ6P :: ADJ_EN [12:12] */ 15533 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6P_ADJ_EN_MASK 0x00001000 15534 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6P_ADJ_EN_ALIGN 0 15535 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6P_ADJ_EN_BITS 1 15536 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6P_ADJ_EN_SHIFT 12 15537 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6P_ADJ_EN_DEFAULT 0x00000000 15538 15539 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ6P :: reserved2 [11:08] */ 15540 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6P_RESERVED2_MASK 0x00000f00 15541 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6P_RESERVED2_ALIGN 0 15542 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6P_RESERVED2_BITS 4 15543 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6P_RESERVED2_SHIFT 8 15544 15545 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ6P :: VDL_STEP [07:00] */ 15546 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6P_VDL_STEP_MASK 0x000000ff 15547 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6P_VDL_STEP_ALIGN 0 15548 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6P_VDL_STEP_BITS 8 15549 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6P_VDL_STEP_SHIFT 0 15550 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6P_VDL_STEP_DEFAULT 0x00000000 15551 15552 /*************************************************************************** 15553 *VDL_CONTROL_RD_DQ6N - Read channel DQ6-N VDL control register 15554 */ 15555 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ6N :: BUSY [31:31] */ 15556 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6N_BUSY_MASK 0x80000000 15557 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6N_BUSY_ALIGN 0 15558 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6N_BUSY_BITS 1 15559 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6N_BUSY_SHIFT 31 15560 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6N_BUSY_DEFAULT 0x00000000 15561 15562 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ6N :: reserved0 [30:17] */ 15563 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6N_RESERVED0_MASK 0x7ffe0000 15564 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6N_RESERVED0_ALIGN 0 15565 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6N_RESERVED0_BITS 14 15566 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6N_RESERVED0_SHIFT 17 15567 15568 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ6N :: FORCE [16:16] */ 15569 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6N_FORCE_MASK 0x00010000 15570 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6N_FORCE_ALIGN 0 15571 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6N_FORCE_BITS 1 15572 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6N_FORCE_SHIFT 16 15573 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6N_FORCE_DEFAULT 0x00000000 15574 15575 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ6N :: reserved1 [15:13] */ 15576 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6N_RESERVED1_MASK 0x0000e000 15577 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6N_RESERVED1_ALIGN 0 15578 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6N_RESERVED1_BITS 3 15579 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6N_RESERVED1_SHIFT 13 15580 15581 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ6N :: ADJ_EN [12:12] */ 15582 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6N_ADJ_EN_MASK 0x00001000 15583 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6N_ADJ_EN_ALIGN 0 15584 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6N_ADJ_EN_BITS 1 15585 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6N_ADJ_EN_SHIFT 12 15586 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6N_ADJ_EN_DEFAULT 0x00000000 15587 15588 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ6N :: reserved2 [11:08] */ 15589 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6N_RESERVED2_MASK 0x00000f00 15590 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6N_RESERVED2_ALIGN 0 15591 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6N_RESERVED2_BITS 4 15592 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6N_RESERVED2_SHIFT 8 15593 15594 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ6N :: VDL_STEP [07:00] */ 15595 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6N_VDL_STEP_MASK 0x000000ff 15596 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6N_VDL_STEP_ALIGN 0 15597 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6N_VDL_STEP_BITS 8 15598 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6N_VDL_STEP_SHIFT 0 15599 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6N_VDL_STEP_DEFAULT 0x00000000 15600 15601 /*************************************************************************** 15602 *VDL_CONTROL_RD_DQ7P - Read channel DQ7-P VDL control register 15603 */ 15604 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ7P :: BUSY [31:31] */ 15605 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7P_BUSY_MASK 0x80000000 15606 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7P_BUSY_ALIGN 0 15607 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7P_BUSY_BITS 1 15608 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7P_BUSY_SHIFT 31 15609 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7P_BUSY_DEFAULT 0x00000000 15610 15611 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ7P :: reserved0 [30:17] */ 15612 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7P_RESERVED0_MASK 0x7ffe0000 15613 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7P_RESERVED0_ALIGN 0 15614 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7P_RESERVED0_BITS 14 15615 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7P_RESERVED0_SHIFT 17 15616 15617 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ7P :: FORCE [16:16] */ 15618 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7P_FORCE_MASK 0x00010000 15619 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7P_FORCE_ALIGN 0 15620 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7P_FORCE_BITS 1 15621 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7P_FORCE_SHIFT 16 15622 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7P_FORCE_DEFAULT 0x00000000 15623 15624 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ7P :: reserved1 [15:13] */ 15625 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7P_RESERVED1_MASK 0x0000e000 15626 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7P_RESERVED1_ALIGN 0 15627 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7P_RESERVED1_BITS 3 15628 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7P_RESERVED1_SHIFT 13 15629 15630 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ7P :: ADJ_EN [12:12] */ 15631 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7P_ADJ_EN_MASK 0x00001000 15632 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7P_ADJ_EN_ALIGN 0 15633 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7P_ADJ_EN_BITS 1 15634 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7P_ADJ_EN_SHIFT 12 15635 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7P_ADJ_EN_DEFAULT 0x00000000 15636 15637 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ7P :: reserved2 [11:08] */ 15638 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7P_RESERVED2_MASK 0x00000f00 15639 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7P_RESERVED2_ALIGN 0 15640 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7P_RESERVED2_BITS 4 15641 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7P_RESERVED2_SHIFT 8 15642 15643 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ7P :: VDL_STEP [07:00] */ 15644 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7P_VDL_STEP_MASK 0x000000ff 15645 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7P_VDL_STEP_ALIGN 0 15646 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7P_VDL_STEP_BITS 8 15647 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7P_VDL_STEP_SHIFT 0 15648 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7P_VDL_STEP_DEFAULT 0x00000000 15649 15650 /*************************************************************************** 15651 *VDL_CONTROL_RD_DQ7N - Read channel DQ7-N VDL control register 15652 */ 15653 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ7N :: BUSY [31:31] */ 15654 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7N_BUSY_MASK 0x80000000 15655 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7N_BUSY_ALIGN 0 15656 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7N_BUSY_BITS 1 15657 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7N_BUSY_SHIFT 31 15658 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7N_BUSY_DEFAULT 0x00000000 15659 15660 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ7N :: reserved0 [30:17] */ 15661 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7N_RESERVED0_MASK 0x7ffe0000 15662 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7N_RESERVED0_ALIGN 0 15663 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7N_RESERVED0_BITS 14 15664 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7N_RESERVED0_SHIFT 17 15665 15666 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ7N :: FORCE [16:16] */ 15667 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7N_FORCE_MASK 0x00010000 15668 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7N_FORCE_ALIGN 0 15669 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7N_FORCE_BITS 1 15670 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7N_FORCE_SHIFT 16 15671 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7N_FORCE_DEFAULT 0x00000000 15672 15673 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ7N :: reserved1 [15:13] */ 15674 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7N_RESERVED1_MASK 0x0000e000 15675 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7N_RESERVED1_ALIGN 0 15676 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7N_RESERVED1_BITS 3 15677 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7N_RESERVED1_SHIFT 13 15678 15679 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ7N :: ADJ_EN [12:12] */ 15680 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7N_ADJ_EN_MASK 0x00001000 15681 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7N_ADJ_EN_ALIGN 0 15682 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7N_ADJ_EN_BITS 1 15683 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7N_ADJ_EN_SHIFT 12 15684 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7N_ADJ_EN_DEFAULT 0x00000000 15685 15686 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ7N :: reserved2 [11:08] */ 15687 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7N_RESERVED2_MASK 0x00000f00 15688 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7N_RESERVED2_ALIGN 0 15689 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7N_RESERVED2_BITS 4 15690 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7N_RESERVED2_SHIFT 8 15691 15692 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DQ7N :: VDL_STEP [07:00] */ 15693 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7N_VDL_STEP_MASK 0x000000ff 15694 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7N_VDL_STEP_ALIGN 0 15695 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7N_VDL_STEP_BITS 8 15696 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7N_VDL_STEP_SHIFT 0 15697 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7N_VDL_STEP_DEFAULT 0x00000000 15698 15699 /*************************************************************************** 15700 *VDL_CONTROL_RD_DMP - Read channel DM-P VDL control register 15701 */ 15702 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DMP :: BUSY [31:31] */ 15703 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMP_BUSY_MASK 0x80000000 15704 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMP_BUSY_ALIGN 0 15705 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMP_BUSY_BITS 1 15706 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMP_BUSY_SHIFT 31 15707 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMP_BUSY_DEFAULT 0x00000000 15708 15709 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DMP :: reserved0 [30:17] */ 15710 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMP_RESERVED0_MASK 0x7ffe0000 15711 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMP_RESERVED0_ALIGN 0 15712 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMP_RESERVED0_BITS 14 15713 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMP_RESERVED0_SHIFT 17 15714 15715 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DMP :: FORCE [16:16] */ 15716 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMP_FORCE_MASK 0x00010000 15717 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMP_FORCE_ALIGN 0 15718 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMP_FORCE_BITS 1 15719 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMP_FORCE_SHIFT 16 15720 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMP_FORCE_DEFAULT 0x00000000 15721 15722 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DMP :: reserved1 [15:13] */ 15723 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMP_RESERVED1_MASK 0x0000e000 15724 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMP_RESERVED1_ALIGN 0 15725 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMP_RESERVED1_BITS 3 15726 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMP_RESERVED1_SHIFT 13 15727 15728 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DMP :: ADJ_EN [12:12] */ 15729 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMP_ADJ_EN_MASK 0x00001000 15730 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMP_ADJ_EN_ALIGN 0 15731 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMP_ADJ_EN_BITS 1 15732 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMP_ADJ_EN_SHIFT 12 15733 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMP_ADJ_EN_DEFAULT 0x00000000 15734 15735 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DMP :: reserved2 [11:08] */ 15736 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMP_RESERVED2_MASK 0x00000f00 15737 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMP_RESERVED2_ALIGN 0 15738 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMP_RESERVED2_BITS 4 15739 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMP_RESERVED2_SHIFT 8 15740 15741 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DMP :: VDL_STEP [07:00] */ 15742 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMP_VDL_STEP_MASK 0x000000ff 15743 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMP_VDL_STEP_ALIGN 0 15744 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMP_VDL_STEP_BITS 8 15745 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMP_VDL_STEP_SHIFT 0 15746 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMP_VDL_STEP_DEFAULT 0x00000000 15747 15748 /*************************************************************************** 15749 *VDL_CONTROL_RD_DMN - Read channel DM-N VDL control register 15750 */ 15751 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DMN :: BUSY [31:31] */ 15752 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMN_BUSY_MASK 0x80000000 15753 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMN_BUSY_ALIGN 0 15754 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMN_BUSY_BITS 1 15755 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMN_BUSY_SHIFT 31 15756 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMN_BUSY_DEFAULT 0x00000000 15757 15758 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DMN :: reserved0 [30:17] */ 15759 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMN_RESERVED0_MASK 0x7ffe0000 15760 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMN_RESERVED0_ALIGN 0 15761 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMN_RESERVED0_BITS 14 15762 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMN_RESERVED0_SHIFT 17 15763 15764 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DMN :: FORCE [16:16] */ 15765 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMN_FORCE_MASK 0x00010000 15766 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMN_FORCE_ALIGN 0 15767 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMN_FORCE_BITS 1 15768 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMN_FORCE_SHIFT 16 15769 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMN_FORCE_DEFAULT 0x00000000 15770 15771 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DMN :: reserved1 [15:13] */ 15772 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMN_RESERVED1_MASK 0x0000e000 15773 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMN_RESERVED1_ALIGN 0 15774 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMN_RESERVED1_BITS 3 15775 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMN_RESERVED1_SHIFT 13 15776 15777 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DMN :: ADJ_EN [12:12] */ 15778 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMN_ADJ_EN_MASK 0x00001000 15779 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMN_ADJ_EN_ALIGN 0 15780 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMN_ADJ_EN_BITS 1 15781 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMN_ADJ_EN_SHIFT 12 15782 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMN_ADJ_EN_DEFAULT 0x00000000 15783 15784 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DMN :: reserved2 [11:08] */ 15785 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMN_RESERVED2_MASK 0x00000f00 15786 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMN_RESERVED2_ALIGN 0 15787 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMN_RESERVED2_BITS 4 15788 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMN_RESERVED2_SHIFT 8 15789 15790 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_DMN :: VDL_STEP [07:00] */ 15791 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMN_VDL_STEP_MASK 0x000000ff 15792 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMN_VDL_STEP_ALIGN 0 15793 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMN_VDL_STEP_BITS 8 15794 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMN_VDL_STEP_SHIFT 0 15795 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMN_VDL_STEP_DEFAULT 0x00000000 15796 15797 /*************************************************************************** 15798 *VDL_CONTROL_RD_EDCP - Read channel EDC-P VDL control register 15799 */ 15800 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_EDCP :: BUSY [31:31] */ 15801 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EDCP_BUSY_MASK 0x80000000 15802 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EDCP_BUSY_ALIGN 0 15803 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EDCP_BUSY_BITS 1 15804 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EDCP_BUSY_SHIFT 31 15805 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EDCP_BUSY_DEFAULT 0x00000000 15806 15807 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_EDCP :: reserved0 [30:17] */ 15808 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EDCP_RESERVED0_MASK 0x7ffe0000 15809 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EDCP_RESERVED0_ALIGN 0 15810 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EDCP_RESERVED0_BITS 14 15811 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EDCP_RESERVED0_SHIFT 17 15812 15813 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_EDCP :: FORCE [16:16] */ 15814 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EDCP_FORCE_MASK 0x00010000 15815 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EDCP_FORCE_ALIGN 0 15816 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EDCP_FORCE_BITS 1 15817 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EDCP_FORCE_SHIFT 16 15818 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EDCP_FORCE_DEFAULT 0x00000000 15819 15820 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_EDCP :: reserved1 [15:13] */ 15821 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EDCP_RESERVED1_MASK 0x0000e000 15822 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EDCP_RESERVED1_ALIGN 0 15823 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EDCP_RESERVED1_BITS 3 15824 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EDCP_RESERVED1_SHIFT 13 15825 15826 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_EDCP :: ADJ_EN [12:12] */ 15827 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EDCP_ADJ_EN_MASK 0x00001000 15828 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EDCP_ADJ_EN_ALIGN 0 15829 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EDCP_ADJ_EN_BITS 1 15830 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EDCP_ADJ_EN_SHIFT 12 15831 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EDCP_ADJ_EN_DEFAULT 0x00000000 15832 15833 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_EDCP :: reserved2 [11:08] */ 15834 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EDCP_RESERVED2_MASK 0x00000f00 15835 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EDCP_RESERVED2_ALIGN 0 15836 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EDCP_RESERVED2_BITS 4 15837 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EDCP_RESERVED2_SHIFT 8 15838 15839 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_EDCP :: VDL_STEP [07:00] */ 15840 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EDCP_VDL_STEP_MASK 0x000000ff 15841 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EDCP_VDL_STEP_ALIGN 0 15842 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EDCP_VDL_STEP_BITS 8 15843 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EDCP_VDL_STEP_SHIFT 0 15844 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EDCP_VDL_STEP_DEFAULT 0x00000000 15845 15846 /*************************************************************************** 15847 *VDL_CONTROL_RD_EDCN - Read channel EDC-N VDL control register 15848 */ 15849 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_EDCN :: BUSY [31:31] */ 15850 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EDCN_BUSY_MASK 0x80000000 15851 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EDCN_BUSY_ALIGN 0 15852 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EDCN_BUSY_BITS 1 15853 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EDCN_BUSY_SHIFT 31 15854 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EDCN_BUSY_DEFAULT 0x00000000 15855 15856 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_EDCN :: reserved0 [30:17] */ 15857 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EDCN_RESERVED0_MASK 0x7ffe0000 15858 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EDCN_RESERVED0_ALIGN 0 15859 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EDCN_RESERVED0_BITS 14 15860 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EDCN_RESERVED0_SHIFT 17 15861 15862 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_EDCN :: FORCE [16:16] */ 15863 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EDCN_FORCE_MASK 0x00010000 15864 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EDCN_FORCE_ALIGN 0 15865 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EDCN_FORCE_BITS 1 15866 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EDCN_FORCE_SHIFT 16 15867 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EDCN_FORCE_DEFAULT 0x00000000 15868 15869 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_EDCN :: reserved1 [15:13] */ 15870 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EDCN_RESERVED1_MASK 0x0000e000 15871 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EDCN_RESERVED1_ALIGN 0 15872 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EDCN_RESERVED1_BITS 3 15873 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EDCN_RESERVED1_SHIFT 13 15874 15875 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_EDCN :: ADJ_EN [12:12] */ 15876 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EDCN_ADJ_EN_MASK 0x00001000 15877 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EDCN_ADJ_EN_ALIGN 0 15878 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EDCN_ADJ_EN_BITS 1 15879 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EDCN_ADJ_EN_SHIFT 12 15880 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EDCN_ADJ_EN_DEFAULT 0x00000000 15881 15882 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_EDCN :: reserved2 [11:08] */ 15883 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EDCN_RESERVED2_MASK 0x00000f00 15884 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EDCN_RESERVED2_ALIGN 0 15885 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EDCN_RESERVED2_BITS 4 15886 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EDCN_RESERVED2_SHIFT 8 15887 15888 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_EDCN :: VDL_STEP [07:00] */ 15889 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EDCN_VDL_STEP_MASK 0x000000ff 15890 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EDCN_VDL_STEP_ALIGN 0 15891 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EDCN_VDL_STEP_BITS 8 15892 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EDCN_VDL_STEP_SHIFT 0 15893 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EDCN_VDL_STEP_DEFAULT 0x00000000 15894 15895 /*************************************************************************** 15896 *VDL_CONTROL_RD_EN_CS0 - Read channel CS_N[0] read enable VDL control register 15897 */ 15898 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_EN_CS0 :: BUSY [31:31] */ 15899 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS0_BUSY_MASK 0x80000000 15900 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS0_BUSY_ALIGN 0 15901 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS0_BUSY_BITS 1 15902 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS0_BUSY_SHIFT 31 15903 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS0_BUSY_DEFAULT 0x00000000 15904 15905 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_EN_CS0 :: reserved0 [30:17] */ 15906 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS0_RESERVED0_MASK 0x7ffe0000 15907 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS0_RESERVED0_ALIGN 0 15908 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS0_RESERVED0_BITS 14 15909 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS0_RESERVED0_SHIFT 17 15910 15911 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_EN_CS0 :: FORCE [16:16] */ 15912 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS0_FORCE_MASK 0x00010000 15913 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS0_FORCE_ALIGN 0 15914 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS0_FORCE_BITS 1 15915 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS0_FORCE_SHIFT 16 15916 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS0_FORCE_DEFAULT 0x00000000 15917 15918 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_EN_CS0 :: reserved1 [15:13] */ 15919 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS0_RESERVED1_MASK 0x0000e000 15920 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS0_RESERVED1_ALIGN 0 15921 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS0_RESERVED1_BITS 3 15922 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS0_RESERVED1_SHIFT 13 15923 15924 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_EN_CS0 :: ADJ_EN [12:12] */ 15925 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS0_ADJ_EN_MASK 0x00001000 15926 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS0_ADJ_EN_ALIGN 0 15927 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS0_ADJ_EN_BITS 1 15928 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS0_ADJ_EN_SHIFT 12 15929 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS0_ADJ_EN_DEFAULT 0x00000000 15930 15931 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_EN_CS0 :: reserved2 [11:08] */ 15932 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS0_RESERVED2_MASK 0x00000f00 15933 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS0_RESERVED2_ALIGN 0 15934 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS0_RESERVED2_BITS 4 15935 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS0_RESERVED2_SHIFT 8 15936 15937 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_EN_CS0 :: VDL_STEP [07:00] */ 15938 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS0_VDL_STEP_MASK 0x000000ff 15939 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS0_VDL_STEP_ALIGN 0 15940 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS0_VDL_STEP_BITS 8 15941 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS0_VDL_STEP_SHIFT 0 15942 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS0_VDL_STEP_DEFAULT 0x00000000 15943 15944 /*************************************************************************** 15945 *VDL_CONTROL_RD_EN_CS1 - Read channel CS_N[1] read enable VDL control register 15946 */ 15947 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_EN_CS1 :: BUSY [31:31] */ 15948 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS1_BUSY_MASK 0x80000000 15949 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS1_BUSY_ALIGN 0 15950 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS1_BUSY_BITS 1 15951 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS1_BUSY_SHIFT 31 15952 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS1_BUSY_DEFAULT 0x00000000 15953 15954 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_EN_CS1 :: reserved0 [30:17] */ 15955 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS1_RESERVED0_MASK 0x7ffe0000 15956 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS1_RESERVED0_ALIGN 0 15957 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS1_RESERVED0_BITS 14 15958 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS1_RESERVED0_SHIFT 17 15959 15960 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_EN_CS1 :: FORCE [16:16] */ 15961 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS1_FORCE_MASK 0x00010000 15962 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS1_FORCE_ALIGN 0 15963 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS1_FORCE_BITS 1 15964 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS1_FORCE_SHIFT 16 15965 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS1_FORCE_DEFAULT 0x00000000 15966 15967 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_EN_CS1 :: reserved1 [15:13] */ 15968 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS1_RESERVED1_MASK 0x0000e000 15969 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS1_RESERVED1_ALIGN 0 15970 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS1_RESERVED1_BITS 3 15971 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS1_RESERVED1_SHIFT 13 15972 15973 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_EN_CS1 :: ADJ_EN [12:12] */ 15974 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS1_ADJ_EN_MASK 0x00001000 15975 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS1_ADJ_EN_ALIGN 0 15976 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS1_ADJ_EN_BITS 1 15977 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS1_ADJ_EN_SHIFT 12 15978 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS1_ADJ_EN_DEFAULT 0x00000000 15979 15980 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_EN_CS1 :: reserved2 [11:08] */ 15981 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS1_RESERVED2_MASK 0x00000f00 15982 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS1_RESERVED2_ALIGN 0 15983 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS1_RESERVED2_BITS 4 15984 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS1_RESERVED2_SHIFT 8 15985 15986 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CONTROL_RD_EN_CS1 :: VDL_STEP [07:00] */ 15987 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS1_VDL_STEP_MASK 0x000000ff 15988 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS1_VDL_STEP_ALIGN 0 15989 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS1_VDL_STEP_BITS 8 15990 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS1_VDL_STEP_SHIFT 0 15991 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS1_VDL_STEP_DEFAULT 0x00000000 15992 15993 /*************************************************************************** 15994 *VDL_CLK_CONTROL - DDR interface signal Write Leveling CLK VDL control register 15995 */ 15996 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CLK_CONTROL :: BUSY [31:31] */ 15997 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CLK_CONTROL_BUSY_MASK 0x80000000 15998 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CLK_CONTROL_BUSY_ALIGN 0 15999 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CLK_CONTROL_BUSY_BITS 1 16000 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CLK_CONTROL_BUSY_SHIFT 31 16001 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CLK_CONTROL_BUSY_DEFAULT 0x00000000 16002 16003 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CLK_CONTROL :: reserved0 [30:17] */ 16004 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CLK_CONTROL_RESERVED0_MASK 0x7ffe0000 16005 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CLK_CONTROL_RESERVED0_ALIGN 0 16006 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CLK_CONTROL_RESERVED0_BITS 14 16007 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CLK_CONTROL_RESERVED0_SHIFT 17 16008 16009 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CLK_CONTROL :: FORCE [16:16] */ 16010 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CLK_CONTROL_FORCE_MASK 0x00010000 16011 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CLK_CONTROL_FORCE_ALIGN 0 16012 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CLK_CONTROL_FORCE_BITS 1 16013 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CLK_CONTROL_FORCE_SHIFT 16 16014 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CLK_CONTROL_FORCE_DEFAULT 0x00000000 16015 16016 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CLK_CONTROL :: reserved1 [15:13] */ 16017 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CLK_CONTROL_RESERVED1_MASK 0x0000e000 16018 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CLK_CONTROL_RESERVED1_ALIGN 0 16019 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CLK_CONTROL_RESERVED1_BITS 3 16020 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CLK_CONTROL_RESERVED1_SHIFT 13 16021 16022 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CLK_CONTROL :: ADJ_EN [12:12] */ 16023 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CLK_CONTROL_ADJ_EN_MASK 0x00001000 16024 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CLK_CONTROL_ADJ_EN_ALIGN 0 16025 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CLK_CONTROL_ADJ_EN_BITS 1 16026 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CLK_CONTROL_ADJ_EN_SHIFT 12 16027 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CLK_CONTROL_ADJ_EN_DEFAULT 0x00000000 16028 16029 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CLK_CONTROL :: reserved2 [11:09] */ 16030 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CLK_CONTROL_RESERVED2_MASK 0x00000e00 16031 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CLK_CONTROL_RESERVED2_ALIGN 0 16032 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CLK_CONTROL_RESERVED2_BITS 3 16033 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CLK_CONTROL_RESERVED2_SHIFT 9 16034 16035 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_CLK_CONTROL :: VDL_STEP [08:00] */ 16036 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CLK_CONTROL_VDL_STEP_MASK 0x000001ff 16037 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CLK_CONTROL_VDL_STEP_ALIGN 0 16038 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CLK_CONTROL_VDL_STEP_BITS 9 16039 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CLK_CONTROL_VDL_STEP_SHIFT 0 16040 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_CLK_CONTROL_VDL_STEP_DEFAULT 0x00000000 16041 16042 /*************************************************************************** 16043 *VDL_LDE_CONTROL - DDR interface signal Write Leveling Capture Enable VDL control register 16044 */ 16045 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_LDE_CONTROL :: BUSY [31:31] */ 16046 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_LDE_CONTROL_BUSY_MASK 0x80000000 16047 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_LDE_CONTROL_BUSY_ALIGN 0 16048 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_LDE_CONTROL_BUSY_BITS 1 16049 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_LDE_CONTROL_BUSY_SHIFT 31 16050 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_LDE_CONTROL_BUSY_DEFAULT 0x00000000 16051 16052 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_LDE_CONTROL :: reserved0 [30:17] */ 16053 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_LDE_CONTROL_RESERVED0_MASK 0x7ffe0000 16054 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_LDE_CONTROL_RESERVED0_ALIGN 0 16055 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_LDE_CONTROL_RESERVED0_BITS 14 16056 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_LDE_CONTROL_RESERVED0_SHIFT 17 16057 16058 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_LDE_CONTROL :: FORCE [16:16] */ 16059 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_LDE_CONTROL_FORCE_MASK 0x00010000 16060 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_LDE_CONTROL_FORCE_ALIGN 0 16061 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_LDE_CONTROL_FORCE_BITS 1 16062 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_LDE_CONTROL_FORCE_SHIFT 16 16063 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_LDE_CONTROL_FORCE_DEFAULT 0x00000000 16064 16065 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_LDE_CONTROL :: reserved1 [15:13] */ 16066 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_LDE_CONTROL_RESERVED1_MASK 0x0000e000 16067 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_LDE_CONTROL_RESERVED1_ALIGN 0 16068 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_LDE_CONTROL_RESERVED1_BITS 3 16069 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_LDE_CONTROL_RESERVED1_SHIFT 13 16070 16071 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_LDE_CONTROL :: ADJ_EN [12:12] */ 16072 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_LDE_CONTROL_ADJ_EN_MASK 0x00001000 16073 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_LDE_CONTROL_ADJ_EN_ALIGN 0 16074 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_LDE_CONTROL_ADJ_EN_BITS 1 16075 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_LDE_CONTROL_ADJ_EN_SHIFT 12 16076 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_LDE_CONTROL_ADJ_EN_DEFAULT 0x00000000 16077 16078 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_LDE_CONTROL :: reserved2 [11:09] */ 16079 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_LDE_CONTROL_RESERVED2_MASK 0x00000e00 16080 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_LDE_CONTROL_RESERVED2_ALIGN 0 16081 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_LDE_CONTROL_RESERVED2_BITS 3 16082 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_LDE_CONTROL_RESERVED2_SHIFT 9 16083 16084 /* DDR34_E0_PHY_BYTE_LANE_3 :: VDL_LDE_CONTROL :: VDL_STEP [08:00] */ 16085 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_LDE_CONTROL_VDL_STEP_MASK 0x000001ff 16086 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_LDE_CONTROL_VDL_STEP_ALIGN 0 16087 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_LDE_CONTROL_VDL_STEP_BITS 9 16088 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_LDE_CONTROL_VDL_STEP_SHIFT 0 16089 #define DDR34_E0_PHY_BYTE_LANE_3_VDL_LDE_CONTROL_VDL_STEP_DEFAULT 0x00000000 16090 16091 /*************************************************************************** 16092 *RD_EN_DLY_CYC - Read enable bit-clock cycle delay control register 16093 */ 16094 /* DDR34_E0_PHY_BYTE_LANE_3 :: RD_EN_DLY_CYC :: BUSY [31:31] */ 16095 #define DDR34_E0_PHY_BYTE_LANE_3_RD_EN_DLY_CYC_BUSY_MASK 0x80000000 16096 #define DDR34_E0_PHY_BYTE_LANE_3_RD_EN_DLY_CYC_BUSY_ALIGN 0 16097 #define DDR34_E0_PHY_BYTE_LANE_3_RD_EN_DLY_CYC_BUSY_BITS 1 16098 #define DDR34_E0_PHY_BYTE_LANE_3_RD_EN_DLY_CYC_BUSY_SHIFT 31 16099 #define DDR34_E0_PHY_BYTE_LANE_3_RD_EN_DLY_CYC_BUSY_DEFAULT 0x00000000 16100 16101 /* DDR34_E0_PHY_BYTE_LANE_3 :: RD_EN_DLY_CYC :: reserved0 [30:17] */ 16102 #define DDR34_E0_PHY_BYTE_LANE_3_RD_EN_DLY_CYC_RESERVED0_MASK 0x7ffe0000 16103 #define DDR34_E0_PHY_BYTE_LANE_3_RD_EN_DLY_CYC_RESERVED0_ALIGN 0 16104 #define DDR34_E0_PHY_BYTE_LANE_3_RD_EN_DLY_CYC_RESERVED0_BITS 14 16105 #define DDR34_E0_PHY_BYTE_LANE_3_RD_EN_DLY_CYC_RESERVED0_SHIFT 17 16106 16107 /* DDR34_E0_PHY_BYTE_LANE_3 :: RD_EN_DLY_CYC :: FORCE [16:16] */ 16108 #define DDR34_E0_PHY_BYTE_LANE_3_RD_EN_DLY_CYC_FORCE_MASK 0x00010000 16109 #define DDR34_E0_PHY_BYTE_LANE_3_RD_EN_DLY_CYC_FORCE_ALIGN 0 16110 #define DDR34_E0_PHY_BYTE_LANE_3_RD_EN_DLY_CYC_FORCE_BITS 1 16111 #define DDR34_E0_PHY_BYTE_LANE_3_RD_EN_DLY_CYC_FORCE_SHIFT 16 16112 #define DDR34_E0_PHY_BYTE_LANE_3_RD_EN_DLY_CYC_FORCE_DEFAULT 0x00000000 16113 16114 /* DDR34_E0_PHY_BYTE_LANE_3 :: RD_EN_DLY_CYC :: reserved1 [15:08] */ 16115 #define DDR34_E0_PHY_BYTE_LANE_3_RD_EN_DLY_CYC_RESERVED1_MASK 0x0000ff00 16116 #define DDR34_E0_PHY_BYTE_LANE_3_RD_EN_DLY_CYC_RESERVED1_ALIGN 0 16117 #define DDR34_E0_PHY_BYTE_LANE_3_RD_EN_DLY_CYC_RESERVED1_BITS 8 16118 #define DDR34_E0_PHY_BYTE_LANE_3_RD_EN_DLY_CYC_RESERVED1_SHIFT 8 16119 16120 /* DDR34_E0_PHY_BYTE_LANE_3 :: RD_EN_DLY_CYC :: CS1_CYCLES [07:04] */ 16121 #define DDR34_E0_PHY_BYTE_LANE_3_RD_EN_DLY_CYC_CS1_CYCLES_MASK 0x000000f0 16122 #define DDR34_E0_PHY_BYTE_LANE_3_RD_EN_DLY_CYC_CS1_CYCLES_ALIGN 0 16123 #define DDR34_E0_PHY_BYTE_LANE_3_RD_EN_DLY_CYC_CS1_CYCLES_BITS 4 16124 #define DDR34_E0_PHY_BYTE_LANE_3_RD_EN_DLY_CYC_CS1_CYCLES_SHIFT 4 16125 #define DDR34_E0_PHY_BYTE_LANE_3_RD_EN_DLY_CYC_CS1_CYCLES_DEFAULT 0x00000000 16126 16127 /* DDR34_E0_PHY_BYTE_LANE_3 :: RD_EN_DLY_CYC :: CS0_CYCLES [03:00] */ 16128 #define DDR34_E0_PHY_BYTE_LANE_3_RD_EN_DLY_CYC_CS0_CYCLES_MASK 0x0000000f 16129 #define DDR34_E0_PHY_BYTE_LANE_3_RD_EN_DLY_CYC_CS0_CYCLES_ALIGN 0 16130 #define DDR34_E0_PHY_BYTE_LANE_3_RD_EN_DLY_CYC_CS0_CYCLES_BITS 4 16131 #define DDR34_E0_PHY_BYTE_LANE_3_RD_EN_DLY_CYC_CS0_CYCLES_SHIFT 0 16132 #define DDR34_E0_PHY_BYTE_LANE_3_RD_EN_DLY_CYC_CS0_CYCLES_DEFAULT 0x00000000 16133 16134 /*************************************************************************** 16135 *WR_CHAN_DLY_CYC - Write leveling bit-clock cycle delay control register 16136 */ 16137 /* DDR34_E0_PHY_BYTE_LANE_3 :: WR_CHAN_DLY_CYC :: BUSY [31:31] */ 16138 #define DDR34_E0_PHY_BYTE_LANE_3_WR_CHAN_DLY_CYC_BUSY_MASK 0x80000000 16139 #define DDR34_E0_PHY_BYTE_LANE_3_WR_CHAN_DLY_CYC_BUSY_ALIGN 0 16140 #define DDR34_E0_PHY_BYTE_LANE_3_WR_CHAN_DLY_CYC_BUSY_BITS 1 16141 #define DDR34_E0_PHY_BYTE_LANE_3_WR_CHAN_DLY_CYC_BUSY_SHIFT 31 16142 #define DDR34_E0_PHY_BYTE_LANE_3_WR_CHAN_DLY_CYC_BUSY_DEFAULT 0x00000000 16143 16144 /* DDR34_E0_PHY_BYTE_LANE_3 :: WR_CHAN_DLY_CYC :: reserved0 [30:17] */ 16145 #define DDR34_E0_PHY_BYTE_LANE_3_WR_CHAN_DLY_CYC_RESERVED0_MASK 0x7ffe0000 16146 #define DDR34_E0_PHY_BYTE_LANE_3_WR_CHAN_DLY_CYC_RESERVED0_ALIGN 0 16147 #define DDR34_E0_PHY_BYTE_LANE_3_WR_CHAN_DLY_CYC_RESERVED0_BITS 14 16148 #define DDR34_E0_PHY_BYTE_LANE_3_WR_CHAN_DLY_CYC_RESERVED0_SHIFT 17 16149 16150 /* DDR34_E0_PHY_BYTE_LANE_3 :: WR_CHAN_DLY_CYC :: FORCE [16:16] */ 16151 #define DDR34_E0_PHY_BYTE_LANE_3_WR_CHAN_DLY_CYC_FORCE_MASK 0x00010000 16152 #define DDR34_E0_PHY_BYTE_LANE_3_WR_CHAN_DLY_CYC_FORCE_ALIGN 0 16153 #define DDR34_E0_PHY_BYTE_LANE_3_WR_CHAN_DLY_CYC_FORCE_BITS 1 16154 #define DDR34_E0_PHY_BYTE_LANE_3_WR_CHAN_DLY_CYC_FORCE_SHIFT 16 16155 #define DDR34_E0_PHY_BYTE_LANE_3_WR_CHAN_DLY_CYC_FORCE_DEFAULT 0x00000000 16156 16157 /* DDR34_E0_PHY_BYTE_LANE_3 :: WR_CHAN_DLY_CYC :: reserved1 [15:03] */ 16158 #define DDR34_E0_PHY_BYTE_LANE_3_WR_CHAN_DLY_CYC_RESERVED1_MASK 0x0000fff8 16159 #define DDR34_E0_PHY_BYTE_LANE_3_WR_CHAN_DLY_CYC_RESERVED1_ALIGN 0 16160 #define DDR34_E0_PHY_BYTE_LANE_3_WR_CHAN_DLY_CYC_RESERVED1_BITS 13 16161 #define DDR34_E0_PHY_BYTE_LANE_3_WR_CHAN_DLY_CYC_RESERVED1_SHIFT 3 16162 16163 /* DDR34_E0_PHY_BYTE_LANE_3 :: WR_CHAN_DLY_CYC :: CYCLES [02:00] */ 16164 #define DDR34_E0_PHY_BYTE_LANE_3_WR_CHAN_DLY_CYC_CYCLES_MASK 0x00000007 16165 #define DDR34_E0_PHY_BYTE_LANE_3_WR_CHAN_DLY_CYC_CYCLES_ALIGN 0 16166 #define DDR34_E0_PHY_BYTE_LANE_3_WR_CHAN_DLY_CYC_CYCLES_BITS 3 16167 #define DDR34_E0_PHY_BYTE_LANE_3_WR_CHAN_DLY_CYC_CYCLES_SHIFT 0 16168 #define DDR34_E0_PHY_BYTE_LANE_3_WR_CHAN_DLY_CYC_CYCLES_DEFAULT 0x00000000 16169 16170 /*************************************************************************** 16171 *READ_CONTROL - Read channel datapath control register 16172 */ 16173 /* DDR34_E0_PHY_BYTE_LANE_3 :: READ_CONTROL :: reserved0 [31:05] */ 16174 #define DDR34_E0_PHY_BYTE_LANE_3_READ_CONTROL_RESERVED0_MASK 0xffffffe0 16175 #define DDR34_E0_PHY_BYTE_LANE_3_READ_CONTROL_RESERVED0_ALIGN 0 16176 #define DDR34_E0_PHY_BYTE_LANE_3_READ_CONTROL_RESERVED0_BITS 27 16177 #define DDR34_E0_PHY_BYTE_LANE_3_READ_CONTROL_RESERVED0_SHIFT 5 16178 16179 /* DDR34_E0_PHY_BYTE_LANE_3 :: READ_CONTROL :: MODE [04:04] */ 16180 #define DDR34_E0_PHY_BYTE_LANE_3_READ_CONTROL_MODE_MASK 0x00000010 16181 #define DDR34_E0_PHY_BYTE_LANE_3_READ_CONTROL_MODE_ALIGN 0 16182 #define DDR34_E0_PHY_BYTE_LANE_3_READ_CONTROL_MODE_BITS 1 16183 #define DDR34_E0_PHY_BYTE_LANE_3_READ_CONTROL_MODE_SHIFT 4 16184 #define DDR34_E0_PHY_BYTE_LANE_3_READ_CONTROL_MODE_DEFAULT 0x00000001 16185 16186 /* DDR34_E0_PHY_BYTE_LANE_3 :: READ_CONTROL :: reserved1 [03:03] */ 16187 #define DDR34_E0_PHY_BYTE_LANE_3_READ_CONTROL_RESERVED1_MASK 0x00000008 16188 #define DDR34_E0_PHY_BYTE_LANE_3_READ_CONTROL_RESERVED1_ALIGN 0 16189 #define DDR34_E0_PHY_BYTE_LANE_3_READ_CONTROL_RESERVED1_BITS 1 16190 #define DDR34_E0_PHY_BYTE_LANE_3_READ_CONTROL_RESERVED1_SHIFT 3 16191 16192 /* DDR34_E0_PHY_BYTE_LANE_3 :: READ_CONTROL :: RD_DATA_DLY [02:00] */ 16193 #define DDR34_E0_PHY_BYTE_LANE_3_READ_CONTROL_RD_DATA_DLY_MASK 0x00000007 16194 #define DDR34_E0_PHY_BYTE_LANE_3_READ_CONTROL_RD_DATA_DLY_ALIGN 0 16195 #define DDR34_E0_PHY_BYTE_LANE_3_READ_CONTROL_RD_DATA_DLY_BITS 3 16196 #define DDR34_E0_PHY_BYTE_LANE_3_READ_CONTROL_RD_DATA_DLY_SHIFT 0 16197 #define DDR34_E0_PHY_BYTE_LANE_3_READ_CONTROL_RD_DATA_DLY_DEFAULT 0x00000007 16198 16199 /*************************************************************************** 16200 *READ_FIFO_ADDR - Read fifo addresss pointer register 16201 */ 16202 /* DDR34_E0_PHY_BYTE_LANE_3 :: READ_FIFO_ADDR :: reserved0 [31:03] */ 16203 #define DDR34_E0_PHY_BYTE_LANE_3_READ_FIFO_ADDR_RESERVED0_MASK 0xfffffff8 16204 #define DDR34_E0_PHY_BYTE_LANE_3_READ_FIFO_ADDR_RESERVED0_ALIGN 0 16205 #define DDR34_E0_PHY_BYTE_LANE_3_READ_FIFO_ADDR_RESERVED0_BITS 29 16206 #define DDR34_E0_PHY_BYTE_LANE_3_READ_FIFO_ADDR_RESERVED0_SHIFT 3 16207 16208 /* DDR34_E0_PHY_BYTE_LANE_3 :: READ_FIFO_ADDR :: ADDR [02:00] */ 16209 #define DDR34_E0_PHY_BYTE_LANE_3_READ_FIFO_ADDR_ADDR_MASK 0x00000007 16210 #define DDR34_E0_PHY_BYTE_LANE_3_READ_FIFO_ADDR_ADDR_ALIGN 0 16211 #define DDR34_E0_PHY_BYTE_LANE_3_READ_FIFO_ADDR_ADDR_BITS 3 16212 #define DDR34_E0_PHY_BYTE_LANE_3_READ_FIFO_ADDR_ADDR_SHIFT 0 16213 #define DDR34_E0_PHY_BYTE_LANE_3_READ_FIFO_ADDR_ADDR_DEFAULT 0x00000000 16214 16215 /*************************************************************************** 16216 *READ_FIFO_DATA - Read fifo data register 16217 */ 16218 /* DDR34_E0_PHY_BYTE_LANE_3 :: READ_FIFO_DATA :: DATA [31:00] */ 16219 #define DDR34_E0_PHY_BYTE_LANE_3_READ_FIFO_DATA_DATA_MASK 0xffffffff 16220 #define DDR34_E0_PHY_BYTE_LANE_3_READ_FIFO_DATA_DATA_ALIGN 0 16221 #define DDR34_E0_PHY_BYTE_LANE_3_READ_FIFO_DATA_DATA_BITS 32 16222 #define DDR34_E0_PHY_BYTE_LANE_3_READ_FIFO_DATA_DATA_SHIFT 0 16223 16224 /*************************************************************************** 16225 *READ_FIFO_DM_DBI - Read fifo dm/dbi register 16226 */ 16227 /* DDR34_E0_PHY_BYTE_LANE_3 :: READ_FIFO_DM_DBI :: reserved0 [31:04] */ 16228 #define DDR34_E0_PHY_BYTE_LANE_3_READ_FIFO_DM_DBI_RESERVED0_MASK 0xfffffff0 16229 #define DDR34_E0_PHY_BYTE_LANE_3_READ_FIFO_DM_DBI_RESERVED0_ALIGN 0 16230 #define DDR34_E0_PHY_BYTE_LANE_3_READ_FIFO_DM_DBI_RESERVED0_BITS 28 16231 #define DDR34_E0_PHY_BYTE_LANE_3_READ_FIFO_DM_DBI_RESERVED0_SHIFT 4 16232 16233 /* DDR34_E0_PHY_BYTE_LANE_3 :: READ_FIFO_DM_DBI :: DM_DBI [03:00] */ 16234 #define DDR34_E0_PHY_BYTE_LANE_3_READ_FIFO_DM_DBI_DM_DBI_MASK 0x0000000f 16235 #define DDR34_E0_PHY_BYTE_LANE_3_READ_FIFO_DM_DBI_DM_DBI_ALIGN 0 16236 #define DDR34_E0_PHY_BYTE_LANE_3_READ_FIFO_DM_DBI_DM_DBI_BITS 4 16237 #define DDR34_E0_PHY_BYTE_LANE_3_READ_FIFO_DM_DBI_DM_DBI_SHIFT 0 16238 16239 /*************************************************************************** 16240 *READ_FIFO_STATUS - Read fifo status register 16241 */ 16242 /* DDR34_E0_PHY_BYTE_LANE_3 :: READ_FIFO_STATUS :: reserved0 [31:02] */ 16243 #define DDR34_E0_PHY_BYTE_LANE_3_READ_FIFO_STATUS_RESERVED0_MASK 0xfffffffc 16244 #define DDR34_E0_PHY_BYTE_LANE_3_READ_FIFO_STATUS_RESERVED0_ALIGN 0 16245 #define DDR34_E0_PHY_BYTE_LANE_3_READ_FIFO_STATUS_RESERVED0_BITS 30 16246 #define DDR34_E0_PHY_BYTE_LANE_3_READ_FIFO_STATUS_RESERVED0_SHIFT 2 16247 16248 /* DDR34_E0_PHY_BYTE_LANE_3 :: READ_FIFO_STATUS :: OVERFLOW [01:01] */ 16249 #define DDR34_E0_PHY_BYTE_LANE_3_READ_FIFO_STATUS_OVERFLOW_MASK 0x00000002 16250 #define DDR34_E0_PHY_BYTE_LANE_3_READ_FIFO_STATUS_OVERFLOW_ALIGN 0 16251 #define DDR34_E0_PHY_BYTE_LANE_3_READ_FIFO_STATUS_OVERFLOW_BITS 1 16252 #define DDR34_E0_PHY_BYTE_LANE_3_READ_FIFO_STATUS_OVERFLOW_SHIFT 1 16253 #define DDR34_E0_PHY_BYTE_LANE_3_READ_FIFO_STATUS_OVERFLOW_DEFAULT 0x00000000 16254 16255 /* DDR34_E0_PHY_BYTE_LANE_3 :: READ_FIFO_STATUS :: UNDERFLOW [00:00] */ 16256 #define DDR34_E0_PHY_BYTE_LANE_3_READ_FIFO_STATUS_UNDERFLOW_MASK 0x00000001 16257 #define DDR34_E0_PHY_BYTE_LANE_3_READ_FIFO_STATUS_UNDERFLOW_ALIGN 0 16258 #define DDR34_E0_PHY_BYTE_LANE_3_READ_FIFO_STATUS_UNDERFLOW_BITS 1 16259 #define DDR34_E0_PHY_BYTE_LANE_3_READ_FIFO_STATUS_UNDERFLOW_SHIFT 0 16260 #define DDR34_E0_PHY_BYTE_LANE_3_READ_FIFO_STATUS_UNDERFLOW_DEFAULT 0x00000000 16261 16262 /*************************************************************************** 16263 *READ_FIFO_CLEAR - Read fifo status clear register 16264 */ 16265 /* DDR34_E0_PHY_BYTE_LANE_3 :: READ_FIFO_CLEAR :: reserved0 [31:01] */ 16266 #define DDR34_E0_PHY_BYTE_LANE_3_READ_FIFO_CLEAR_RESERVED0_MASK 0xfffffffe 16267 #define DDR34_E0_PHY_BYTE_LANE_3_READ_FIFO_CLEAR_RESERVED0_ALIGN 0 16268 #define DDR34_E0_PHY_BYTE_LANE_3_READ_FIFO_CLEAR_RESERVED0_BITS 31 16269 #define DDR34_E0_PHY_BYTE_LANE_3_READ_FIFO_CLEAR_RESERVED0_SHIFT 1 16270 16271 /* DDR34_E0_PHY_BYTE_LANE_3 :: READ_FIFO_CLEAR :: CLEAR [00:00] */ 16272 #define DDR34_E0_PHY_BYTE_LANE_3_READ_FIFO_CLEAR_CLEAR_MASK 0x00000001 16273 #define DDR34_E0_PHY_BYTE_LANE_3_READ_FIFO_CLEAR_CLEAR_ALIGN 0 16274 #define DDR34_E0_PHY_BYTE_LANE_3_READ_FIFO_CLEAR_CLEAR_BITS 1 16275 #define DDR34_E0_PHY_BYTE_LANE_3_READ_FIFO_CLEAR_CLEAR_SHIFT 0 16276 #define DDR34_E0_PHY_BYTE_LANE_3_READ_FIFO_CLEAR_CLEAR_DEFAULT 0x00000000 16277 16278 /*************************************************************************** 16279 *IDLE_PAD_CONTROL - Idle mode SSTL pad control register 16280 */ 16281 /* DDR34_E0_PHY_BYTE_LANE_3 :: IDLE_PAD_CONTROL :: IDLE [31:31] */ 16282 #define DDR34_E0_PHY_BYTE_LANE_3_IDLE_PAD_CONTROL_IDLE_MASK 0x80000000 16283 #define DDR34_E0_PHY_BYTE_LANE_3_IDLE_PAD_CONTROL_IDLE_ALIGN 0 16284 #define DDR34_E0_PHY_BYTE_LANE_3_IDLE_PAD_CONTROL_IDLE_BITS 1 16285 #define DDR34_E0_PHY_BYTE_LANE_3_IDLE_PAD_CONTROL_IDLE_SHIFT 31 16286 #define DDR34_E0_PHY_BYTE_LANE_3_IDLE_PAD_CONTROL_IDLE_DEFAULT 0x00000000 16287 16288 /* DDR34_E0_PHY_BYTE_LANE_3 :: IDLE_PAD_CONTROL :: reserved0 [30:20] */ 16289 #define DDR34_E0_PHY_BYTE_LANE_3_IDLE_PAD_CONTROL_RESERVED0_MASK 0x7ff00000 16290 #define DDR34_E0_PHY_BYTE_LANE_3_IDLE_PAD_CONTROL_RESERVED0_ALIGN 0 16291 #define DDR34_E0_PHY_BYTE_LANE_3_IDLE_PAD_CONTROL_RESERVED0_BITS 11 16292 #define DDR34_E0_PHY_BYTE_LANE_3_IDLE_PAD_CONTROL_RESERVED0_SHIFT 20 16293 16294 /* DDR34_E0_PHY_BYTE_LANE_3 :: IDLE_PAD_CONTROL :: AUTO_DQ_RXENB_MODE [19:18] */ 16295 #define DDR34_E0_PHY_BYTE_LANE_3_IDLE_PAD_CONTROL_AUTO_DQ_RXENB_MODE_MASK 0x000c0000 16296 #define DDR34_E0_PHY_BYTE_LANE_3_IDLE_PAD_CONTROL_AUTO_DQ_RXENB_MODE_ALIGN 0 16297 #define DDR34_E0_PHY_BYTE_LANE_3_IDLE_PAD_CONTROL_AUTO_DQ_RXENB_MODE_BITS 2 16298 #define DDR34_E0_PHY_BYTE_LANE_3_IDLE_PAD_CONTROL_AUTO_DQ_RXENB_MODE_SHIFT 18 16299 #define DDR34_E0_PHY_BYTE_LANE_3_IDLE_PAD_CONTROL_AUTO_DQ_RXENB_MODE_DEFAULT 0x00000001 16300 16301 /* DDR34_E0_PHY_BYTE_LANE_3 :: IDLE_PAD_CONTROL :: AUTO_DQ_IDDQ_MODE [17:16] */ 16302 #define DDR34_E0_PHY_BYTE_LANE_3_IDLE_PAD_CONTROL_AUTO_DQ_IDDQ_MODE_MASK 0x00030000 16303 #define DDR34_E0_PHY_BYTE_LANE_3_IDLE_PAD_CONTROL_AUTO_DQ_IDDQ_MODE_ALIGN 0 16304 #define DDR34_E0_PHY_BYTE_LANE_3_IDLE_PAD_CONTROL_AUTO_DQ_IDDQ_MODE_BITS 2 16305 #define DDR34_E0_PHY_BYTE_LANE_3_IDLE_PAD_CONTROL_AUTO_DQ_IDDQ_MODE_SHIFT 16 16306 #define DDR34_E0_PHY_BYTE_LANE_3_IDLE_PAD_CONTROL_AUTO_DQ_IDDQ_MODE_DEFAULT 0x00000001 16307 16308 /* DDR34_E0_PHY_BYTE_LANE_3 :: IDLE_PAD_CONTROL :: reserved_for_padding1 [15:15] */ 16309 #define DDR34_E0_PHY_BYTE_LANE_3_IDLE_PAD_CONTROL_RESERVED_for_padding1_MASK 0x00008000 16310 #define DDR34_E0_PHY_BYTE_LANE_3_IDLE_PAD_CONTROL_RESERVED_for_padding1_ALIGN 0 16311 #define DDR34_E0_PHY_BYTE_LANE_3_IDLE_PAD_CONTROL_RESERVED_for_padding1_BITS 1 16312 #define DDR34_E0_PHY_BYTE_LANE_3_IDLE_PAD_CONTROL_RESERVED_for_padding1_SHIFT 15 16313 16314 /* DDR34_E0_PHY_BYTE_LANE_3 :: IDLE_PAD_CONTROL :: IO_IDLE_ENABLE [14:04] */ 16315 #define DDR34_E0_PHY_BYTE_LANE_3_IDLE_PAD_CONTROL_IO_IDLE_ENABLE_MASK 0x00007ff0 16316 #define DDR34_E0_PHY_BYTE_LANE_3_IDLE_PAD_CONTROL_IO_IDLE_ENABLE_ALIGN 0 16317 #define DDR34_E0_PHY_BYTE_LANE_3_IDLE_PAD_CONTROL_IO_IDLE_ENABLE_BITS 11 16318 #define DDR34_E0_PHY_BYTE_LANE_3_IDLE_PAD_CONTROL_IO_IDLE_ENABLE_SHIFT 4 16319 #define DDR34_E0_PHY_BYTE_LANE_3_IDLE_PAD_CONTROL_IO_IDLE_ENABLE_DEFAULT 0x00000000 16320 16321 /* DDR34_E0_PHY_BYTE_LANE_3 :: IDLE_PAD_CONTROL :: RXENB [03:03] */ 16322 #define DDR34_E0_PHY_BYTE_LANE_3_IDLE_PAD_CONTROL_RXENB_MASK 0x00000008 16323 #define DDR34_E0_PHY_BYTE_LANE_3_IDLE_PAD_CONTROL_RXENB_ALIGN 0 16324 #define DDR34_E0_PHY_BYTE_LANE_3_IDLE_PAD_CONTROL_RXENB_BITS 1 16325 #define DDR34_E0_PHY_BYTE_LANE_3_IDLE_PAD_CONTROL_RXENB_SHIFT 3 16326 #define DDR34_E0_PHY_BYTE_LANE_3_IDLE_PAD_CONTROL_RXENB_DEFAULT 0x00000001 16327 16328 /* DDR34_E0_PHY_BYTE_LANE_3 :: IDLE_PAD_CONTROL :: IDDQ [02:02] */ 16329 #define DDR34_E0_PHY_BYTE_LANE_3_IDLE_PAD_CONTROL_IDDQ_MASK 0x00000004 16330 #define DDR34_E0_PHY_BYTE_LANE_3_IDLE_PAD_CONTROL_IDDQ_ALIGN 0 16331 #define DDR34_E0_PHY_BYTE_LANE_3_IDLE_PAD_CONTROL_IDDQ_BITS 1 16332 #define DDR34_E0_PHY_BYTE_LANE_3_IDLE_PAD_CONTROL_IDDQ_SHIFT 2 16333 #define DDR34_E0_PHY_BYTE_LANE_3_IDLE_PAD_CONTROL_IDDQ_DEFAULT 0x00000000 16334 16335 /* DDR34_E0_PHY_BYTE_LANE_3 :: IDLE_PAD_CONTROL :: DOUT_N [01:01] */ 16336 #define DDR34_E0_PHY_BYTE_LANE_3_IDLE_PAD_CONTROL_DOUT_N_MASK 0x00000002 16337 #define DDR34_E0_PHY_BYTE_LANE_3_IDLE_PAD_CONTROL_DOUT_N_ALIGN 0 16338 #define DDR34_E0_PHY_BYTE_LANE_3_IDLE_PAD_CONTROL_DOUT_N_BITS 1 16339 #define DDR34_E0_PHY_BYTE_LANE_3_IDLE_PAD_CONTROL_DOUT_N_SHIFT 1 16340 #define DDR34_E0_PHY_BYTE_LANE_3_IDLE_PAD_CONTROL_DOUT_N_DEFAULT 0x00000001 16341 16342 /* DDR34_E0_PHY_BYTE_LANE_3 :: IDLE_PAD_CONTROL :: DOUT_P [00:00] */ 16343 #define DDR34_E0_PHY_BYTE_LANE_3_IDLE_PAD_CONTROL_DOUT_P_MASK 0x00000001 16344 #define DDR34_E0_PHY_BYTE_LANE_3_IDLE_PAD_CONTROL_DOUT_P_ALIGN 0 16345 #define DDR34_E0_PHY_BYTE_LANE_3_IDLE_PAD_CONTROL_DOUT_P_BITS 1 16346 #define DDR34_E0_PHY_BYTE_LANE_3_IDLE_PAD_CONTROL_DOUT_P_SHIFT 0 16347 #define DDR34_E0_PHY_BYTE_LANE_3_IDLE_PAD_CONTROL_DOUT_P_DEFAULT 0x00000000 16348 16349 /*************************************************************************** 16350 *DRIVE_PAD_CTL - SSTL pad drive characteristics control register 16351 */ 16352 /* DDR34_E0_PHY_BYTE_LANE_3 :: DRIVE_PAD_CTL :: reserved0 [31:30] */ 16353 #define DDR34_E0_PHY_BYTE_LANE_3_DRIVE_PAD_CTL_RESERVED0_MASK 0xc0000000 16354 #define DDR34_E0_PHY_BYTE_LANE_3_DRIVE_PAD_CTL_RESERVED0_ALIGN 0 16355 #define DDR34_E0_PHY_BYTE_LANE_3_DRIVE_PAD_CTL_RESERVED0_BITS 2 16356 #define DDR34_E0_PHY_BYTE_LANE_3_DRIVE_PAD_CTL_RESERVED0_SHIFT 30 16357 16358 /* DDR34_E0_PHY_BYTE_LANE_3 :: DRIVE_PAD_CTL :: BL_PD_IDLE_STRENGTH [29:25] */ 16359 #define DDR34_E0_PHY_BYTE_LANE_3_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_MASK 0x3e000000 16360 #define DDR34_E0_PHY_BYTE_LANE_3_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_ALIGN 0 16361 #define DDR34_E0_PHY_BYTE_LANE_3_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_BITS 5 16362 #define DDR34_E0_PHY_BYTE_LANE_3_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_SHIFT 25 16363 #define DDR34_E0_PHY_BYTE_LANE_3_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_DEFAULT 0x0000001f 16364 16365 /* DDR34_E0_PHY_BYTE_LANE_3 :: DRIVE_PAD_CTL :: BL_ND_IDLE_STRENGTH [24:20] */ 16366 #define DDR34_E0_PHY_BYTE_LANE_3_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_MASK 0x01f00000 16367 #define DDR34_E0_PHY_BYTE_LANE_3_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_ALIGN 0 16368 #define DDR34_E0_PHY_BYTE_LANE_3_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_BITS 5 16369 #define DDR34_E0_PHY_BYTE_LANE_3_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_SHIFT 20 16370 #define DDR34_E0_PHY_BYTE_LANE_3_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_DEFAULT 0x0000001f 16371 16372 /* DDR34_E0_PHY_BYTE_LANE_3 :: DRIVE_PAD_CTL :: BL_PD_TERM_STRENGTH [19:15] */ 16373 #define DDR34_E0_PHY_BYTE_LANE_3_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_MASK 0x000f8000 16374 #define DDR34_E0_PHY_BYTE_LANE_3_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_ALIGN 0 16375 #define DDR34_E0_PHY_BYTE_LANE_3_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_BITS 5 16376 #define DDR34_E0_PHY_BYTE_LANE_3_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_SHIFT 15 16377 #define DDR34_E0_PHY_BYTE_LANE_3_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_DEFAULT 0x00000006 16378 16379 /* DDR34_E0_PHY_BYTE_LANE_3 :: DRIVE_PAD_CTL :: BL_ND_TERM_STRENGTH [14:10] */ 16380 #define DDR34_E0_PHY_BYTE_LANE_3_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_MASK 0x00007c00 16381 #define DDR34_E0_PHY_BYTE_LANE_3_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_ALIGN 0 16382 #define DDR34_E0_PHY_BYTE_LANE_3_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_BITS 5 16383 #define DDR34_E0_PHY_BYTE_LANE_3_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_SHIFT 10 16384 #define DDR34_E0_PHY_BYTE_LANE_3_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_DEFAULT 0x00000006 16385 16386 /* DDR34_E0_PHY_BYTE_LANE_3 :: DRIVE_PAD_CTL :: BL_PD_STRENGTH [09:05] */ 16387 #define DDR34_E0_PHY_BYTE_LANE_3_DRIVE_PAD_CTL_BL_PD_STRENGTH_MASK 0x000003e0 16388 #define DDR34_E0_PHY_BYTE_LANE_3_DRIVE_PAD_CTL_BL_PD_STRENGTH_ALIGN 0 16389 #define DDR34_E0_PHY_BYTE_LANE_3_DRIVE_PAD_CTL_BL_PD_STRENGTH_BITS 5 16390 #define DDR34_E0_PHY_BYTE_LANE_3_DRIVE_PAD_CTL_BL_PD_STRENGTH_SHIFT 5 16391 #define DDR34_E0_PHY_BYTE_LANE_3_DRIVE_PAD_CTL_BL_PD_STRENGTH_DEFAULT 0x0000001f 16392 16393 /* DDR34_E0_PHY_BYTE_LANE_3 :: DRIVE_PAD_CTL :: BL_ND_STRENGTH [04:00] */ 16394 #define DDR34_E0_PHY_BYTE_LANE_3_DRIVE_PAD_CTL_BL_ND_STRENGTH_MASK 0x0000001f 16395 #define DDR34_E0_PHY_BYTE_LANE_3_DRIVE_PAD_CTL_BL_ND_STRENGTH_ALIGN 0 16396 #define DDR34_E0_PHY_BYTE_LANE_3_DRIVE_PAD_CTL_BL_ND_STRENGTH_BITS 5 16397 #define DDR34_E0_PHY_BYTE_LANE_3_DRIVE_PAD_CTL_BL_ND_STRENGTH_SHIFT 0 16398 #define DDR34_E0_PHY_BYTE_LANE_3_DRIVE_PAD_CTL_BL_ND_STRENGTH_DEFAULT 0x0000001f 16399 16400 /*************************************************************************** 16401 *RD_EN_DRIVE_PAD_CTL - SSTL read enable pad drive characteristics control register 16402 */ 16403 /* DDR34_E0_PHY_BYTE_LANE_3 :: RD_EN_DRIVE_PAD_CTL :: reserved0 [31:20] */ 16404 #define DDR34_E0_PHY_BYTE_LANE_3_RD_EN_DRIVE_PAD_CTL_RESERVED0_MASK 0xfff00000 16405 #define DDR34_E0_PHY_BYTE_LANE_3_RD_EN_DRIVE_PAD_CTL_RESERVED0_ALIGN 0 16406 #define DDR34_E0_PHY_BYTE_LANE_3_RD_EN_DRIVE_PAD_CTL_RESERVED0_BITS 12 16407 #define DDR34_E0_PHY_BYTE_LANE_3_RD_EN_DRIVE_PAD_CTL_RESERVED0_SHIFT 20 16408 16409 /* DDR34_E0_PHY_BYTE_LANE_3 :: RD_EN_DRIVE_PAD_CTL :: EDC_RD_EN_PD_STRENGTH [19:15] */ 16410 #define DDR34_E0_PHY_BYTE_LANE_3_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_PD_STRENGTH_MASK 0x000f8000 16411 #define DDR34_E0_PHY_BYTE_LANE_3_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_PD_STRENGTH_ALIGN 0 16412 #define DDR34_E0_PHY_BYTE_LANE_3_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_PD_STRENGTH_BITS 5 16413 #define DDR34_E0_PHY_BYTE_LANE_3_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_PD_STRENGTH_SHIFT 15 16414 #define DDR34_E0_PHY_BYTE_LANE_3_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_PD_STRENGTH_DEFAULT 0x0000001f 16415 16416 /* DDR34_E0_PHY_BYTE_LANE_3 :: RD_EN_DRIVE_PAD_CTL :: EDC_RD_EN_ND_STRENGTH [14:10] */ 16417 #define DDR34_E0_PHY_BYTE_LANE_3_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_ND_STRENGTH_MASK 0x00007c00 16418 #define DDR34_E0_PHY_BYTE_LANE_3_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_ND_STRENGTH_ALIGN 0 16419 #define DDR34_E0_PHY_BYTE_LANE_3_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_ND_STRENGTH_BITS 5 16420 #define DDR34_E0_PHY_BYTE_LANE_3_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_ND_STRENGTH_SHIFT 10 16421 #define DDR34_E0_PHY_BYTE_LANE_3_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_ND_STRENGTH_DEFAULT 0x0000001f 16422 16423 /* DDR34_E0_PHY_BYTE_LANE_3 :: RD_EN_DRIVE_PAD_CTL :: BL_RD_EN_PD_STRENGTH [09:05] */ 16424 #define DDR34_E0_PHY_BYTE_LANE_3_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_PD_STRENGTH_MASK 0x000003e0 16425 #define DDR34_E0_PHY_BYTE_LANE_3_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_PD_STRENGTH_ALIGN 0 16426 #define DDR34_E0_PHY_BYTE_LANE_3_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_PD_STRENGTH_BITS 5 16427 #define DDR34_E0_PHY_BYTE_LANE_3_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_PD_STRENGTH_SHIFT 5 16428 #define DDR34_E0_PHY_BYTE_LANE_3_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_PD_STRENGTH_DEFAULT 0x0000001f 16429 16430 /* DDR34_E0_PHY_BYTE_LANE_3 :: RD_EN_DRIVE_PAD_CTL :: BL_RD_EN_ND_STRENGTH [04:00] */ 16431 #define DDR34_E0_PHY_BYTE_LANE_3_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_ND_STRENGTH_MASK 0x0000001f 16432 #define DDR34_E0_PHY_BYTE_LANE_3_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_ND_STRENGTH_ALIGN 0 16433 #define DDR34_E0_PHY_BYTE_LANE_3_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_ND_STRENGTH_BITS 5 16434 #define DDR34_E0_PHY_BYTE_LANE_3_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_ND_STRENGTH_SHIFT 0 16435 #define DDR34_E0_PHY_BYTE_LANE_3_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_ND_STRENGTH_DEFAULT 0x0000001f 16436 16437 /*************************************************************************** 16438 *STATIC_PAD_CTL - pad rx and tx characteristics control register 16439 */ 16440 /* DDR34_E0_PHY_BYTE_LANE_3 :: STATIC_PAD_CTL :: reserved0 [31:21] */ 16441 #define DDR34_E0_PHY_BYTE_LANE_3_STATIC_PAD_CTL_RESERVED0_MASK 0xffe00000 16442 #define DDR34_E0_PHY_BYTE_LANE_3_STATIC_PAD_CTL_RESERVED0_ALIGN 0 16443 #define DDR34_E0_PHY_BYTE_LANE_3_STATIC_PAD_CTL_RESERVED0_BITS 11 16444 #define DDR34_E0_PHY_BYTE_LANE_3_STATIC_PAD_CTL_RESERVED0_SHIFT 21 16445 16446 /* DDR34_E0_PHY_BYTE_LANE_3 :: STATIC_PAD_CTL :: DQS_MODE [20:20] */ 16447 #define DDR34_E0_PHY_BYTE_LANE_3_STATIC_PAD_CTL_DQS_MODE_MASK 0x00100000 16448 #define DDR34_E0_PHY_BYTE_LANE_3_STATIC_PAD_CTL_DQS_MODE_ALIGN 0 16449 #define DDR34_E0_PHY_BYTE_LANE_3_STATIC_PAD_CTL_DQS_MODE_BITS 1 16450 #define DDR34_E0_PHY_BYTE_LANE_3_STATIC_PAD_CTL_DQS_MODE_SHIFT 20 16451 #define DDR34_E0_PHY_BYTE_LANE_3_STATIC_PAD_CTL_DQS_MODE_DEFAULT 0x00000000 16452 16453 /* DDR34_E0_PHY_BYTE_LANE_3 :: STATIC_PAD_CTL :: reserved1 [19:18] */ 16454 #define DDR34_E0_PHY_BYTE_LANE_3_STATIC_PAD_CTL_RESERVED1_MASK 0x000c0000 16455 #define DDR34_E0_PHY_BYTE_LANE_3_STATIC_PAD_CTL_RESERVED1_ALIGN 0 16456 #define DDR34_E0_PHY_BYTE_LANE_3_STATIC_PAD_CTL_RESERVED1_BITS 2 16457 #define DDR34_E0_PHY_BYTE_LANE_3_STATIC_PAD_CTL_RESERVED1_SHIFT 18 16458 16459 /* DDR34_E0_PHY_BYTE_LANE_3 :: STATIC_PAD_CTL :: EDC_MODE [17:16] */ 16460 #define DDR34_E0_PHY_BYTE_LANE_3_STATIC_PAD_CTL_EDC_MODE_MASK 0x00030000 16461 #define DDR34_E0_PHY_BYTE_LANE_3_STATIC_PAD_CTL_EDC_MODE_ALIGN 0 16462 #define DDR34_E0_PHY_BYTE_LANE_3_STATIC_PAD_CTL_EDC_MODE_BITS 2 16463 #define DDR34_E0_PHY_BYTE_LANE_3_STATIC_PAD_CTL_EDC_MODE_SHIFT 16 16464 #define DDR34_E0_PHY_BYTE_LANE_3_STATIC_PAD_CTL_EDC_MODE_DEFAULT 0x00000000 16465 16466 /* DDR34_E0_PHY_BYTE_LANE_3 :: STATIC_PAD_CTL :: reserved2 [15:15] */ 16467 #define DDR34_E0_PHY_BYTE_LANE_3_STATIC_PAD_CTL_RESERVED2_MASK 0x00008000 16468 #define DDR34_E0_PHY_BYTE_LANE_3_STATIC_PAD_CTL_RESERVED2_ALIGN 0 16469 #define DDR34_E0_PHY_BYTE_LANE_3_STATIC_PAD_CTL_RESERVED2_BITS 1 16470 #define DDR34_E0_PHY_BYTE_LANE_3_STATIC_PAD_CTL_RESERVED2_SHIFT 15 16471 16472 /* DDR34_E0_PHY_BYTE_LANE_3 :: STATIC_PAD_CTL :: WDBI_ENABLE [14:14] */ 16473 #define DDR34_E0_PHY_BYTE_LANE_3_STATIC_PAD_CTL_WDBI_ENABLE_MASK 0x00004000 16474 #define DDR34_E0_PHY_BYTE_LANE_3_STATIC_PAD_CTL_WDBI_ENABLE_ALIGN 0 16475 #define DDR34_E0_PHY_BYTE_LANE_3_STATIC_PAD_CTL_WDBI_ENABLE_BITS 1 16476 #define DDR34_E0_PHY_BYTE_LANE_3_STATIC_PAD_CTL_WDBI_ENABLE_SHIFT 14 16477 #define DDR34_E0_PHY_BYTE_LANE_3_STATIC_PAD_CTL_WDBI_ENABLE_DEFAULT 0x00000000 16478 16479 /* DDR34_E0_PHY_BYTE_LANE_3 :: STATIC_PAD_CTL :: RDBI_ENABLE [13:13] */ 16480 #define DDR34_E0_PHY_BYTE_LANE_3_STATIC_PAD_CTL_RDBI_ENABLE_MASK 0x00002000 16481 #define DDR34_E0_PHY_BYTE_LANE_3_STATIC_PAD_CTL_RDBI_ENABLE_ALIGN 0 16482 #define DDR34_E0_PHY_BYTE_LANE_3_STATIC_PAD_CTL_RDBI_ENABLE_BITS 1 16483 #define DDR34_E0_PHY_BYTE_LANE_3_STATIC_PAD_CTL_RDBI_ENABLE_SHIFT 13 16484 #define DDR34_E0_PHY_BYTE_LANE_3_STATIC_PAD_CTL_RDBI_ENABLE_DEFAULT 0x00000000 16485 16486 /* DDR34_E0_PHY_BYTE_LANE_3 :: STATIC_PAD_CTL :: DM_MODE [12:12] */ 16487 #define DDR34_E0_PHY_BYTE_LANE_3_STATIC_PAD_CTL_DM_MODE_MASK 0x00001000 16488 #define DDR34_E0_PHY_BYTE_LANE_3_STATIC_PAD_CTL_DM_MODE_ALIGN 0 16489 #define DDR34_E0_PHY_BYTE_LANE_3_STATIC_PAD_CTL_DM_MODE_BITS 1 16490 #define DDR34_E0_PHY_BYTE_LANE_3_STATIC_PAD_CTL_DM_MODE_SHIFT 12 16491 #define DDR34_E0_PHY_BYTE_LANE_3_STATIC_PAD_CTL_DM_MODE_DEFAULT 0x00000000 16492 16493 /* DDR34_E0_PHY_BYTE_LANE_3 :: STATIC_PAD_CTL :: reserved3 [11:10] */ 16494 #define DDR34_E0_PHY_BYTE_LANE_3_STATIC_PAD_CTL_RESERVED3_MASK 0x00000c00 16495 #define DDR34_E0_PHY_BYTE_LANE_3_STATIC_PAD_CTL_RESERVED3_ALIGN 0 16496 #define DDR34_E0_PHY_BYTE_LANE_3_STATIC_PAD_CTL_RESERVED3_BITS 2 16497 #define DDR34_E0_PHY_BYTE_LANE_3_STATIC_PAD_CTL_RESERVED3_SHIFT 10 16498 16499 /* DDR34_E0_PHY_BYTE_LANE_3 :: STATIC_PAD_CTL :: DQS_TX_DIS [09:09] */ 16500 #define DDR34_E0_PHY_BYTE_LANE_3_STATIC_PAD_CTL_DQS_TX_DIS_MASK 0x00000200 16501 #define DDR34_E0_PHY_BYTE_LANE_3_STATIC_PAD_CTL_DQS_TX_DIS_ALIGN 0 16502 #define DDR34_E0_PHY_BYTE_LANE_3_STATIC_PAD_CTL_DQS_TX_DIS_BITS 1 16503 #define DDR34_E0_PHY_BYTE_LANE_3_STATIC_PAD_CTL_DQS_TX_DIS_SHIFT 9 16504 #define DDR34_E0_PHY_BYTE_LANE_3_STATIC_PAD_CTL_DQS_TX_DIS_DEFAULT 0x00000000 16505 16506 /* DDR34_E0_PHY_BYTE_LANE_3 :: STATIC_PAD_CTL :: reserved4 [08:02] */ 16507 #define DDR34_E0_PHY_BYTE_LANE_3_STATIC_PAD_CTL_RESERVED4_MASK 0x000001fc 16508 #define DDR34_E0_PHY_BYTE_LANE_3_STATIC_PAD_CTL_RESERVED4_ALIGN 0 16509 #define DDR34_E0_PHY_BYTE_LANE_3_STATIC_PAD_CTL_RESERVED4_BITS 7 16510 #define DDR34_E0_PHY_BYTE_LANE_3_STATIC_PAD_CTL_RESERVED4_SHIFT 2 16511 16512 /* DDR34_E0_PHY_BYTE_LANE_3 :: STATIC_PAD_CTL :: RX_MODE [01:00] */ 16513 #define DDR34_E0_PHY_BYTE_LANE_3_STATIC_PAD_CTL_RX_MODE_MASK 0x00000003 16514 #define DDR34_E0_PHY_BYTE_LANE_3_STATIC_PAD_CTL_RX_MODE_ALIGN 0 16515 #define DDR34_E0_PHY_BYTE_LANE_3_STATIC_PAD_CTL_RX_MODE_BITS 2 16516 #define DDR34_E0_PHY_BYTE_LANE_3_STATIC_PAD_CTL_RX_MODE_SHIFT 0 16517 #define DDR34_E0_PHY_BYTE_LANE_3_STATIC_PAD_CTL_RX_MODE_DEFAULT 0x00000000 16518 16519 /*************************************************************************** 16520 *WR_PREAMBLE_MODE - Write cycle preamble control register 16521 */ 16522 /* DDR34_E0_PHY_BYTE_LANE_3 :: WR_PREAMBLE_MODE :: reserved0 [31:16] */ 16523 #define DDR34_E0_PHY_BYTE_LANE_3_WR_PREAMBLE_MODE_RESERVED0_MASK 0xffff0000 16524 #define DDR34_E0_PHY_BYTE_LANE_3_WR_PREAMBLE_MODE_RESERVED0_ALIGN 0 16525 #define DDR34_E0_PHY_BYTE_LANE_3_WR_PREAMBLE_MODE_RESERVED0_BITS 16 16526 #define DDR34_E0_PHY_BYTE_LANE_3_WR_PREAMBLE_MODE_RESERVED0_SHIFT 16 16527 16528 /* DDR34_E0_PHY_BYTE_LANE_3 :: WR_PREAMBLE_MODE :: DQ_POSTAM_BITS [15:14] */ 16529 #define DDR34_E0_PHY_BYTE_LANE_3_WR_PREAMBLE_MODE_DQ_POSTAM_BITS_MASK 0x0000c000 16530 #define DDR34_E0_PHY_BYTE_LANE_3_WR_PREAMBLE_MODE_DQ_POSTAM_BITS_ALIGN 0 16531 #define DDR34_E0_PHY_BYTE_LANE_3_WR_PREAMBLE_MODE_DQ_POSTAM_BITS_BITS 2 16532 #define DDR34_E0_PHY_BYTE_LANE_3_WR_PREAMBLE_MODE_DQ_POSTAM_BITS_SHIFT 14 16533 #define DDR34_E0_PHY_BYTE_LANE_3_WR_PREAMBLE_MODE_DQ_POSTAM_BITS_DEFAULT 0x00000000 16534 16535 /* DDR34_E0_PHY_BYTE_LANE_3 :: WR_PREAMBLE_MODE :: DQ_PREAM_BITS [13:12] */ 16536 #define DDR34_E0_PHY_BYTE_LANE_3_WR_PREAMBLE_MODE_DQ_PREAM_BITS_MASK 0x00003000 16537 #define DDR34_E0_PHY_BYTE_LANE_3_WR_PREAMBLE_MODE_DQ_PREAM_BITS_ALIGN 0 16538 #define DDR34_E0_PHY_BYTE_LANE_3_WR_PREAMBLE_MODE_DQ_PREAM_BITS_BITS 2 16539 #define DDR34_E0_PHY_BYTE_LANE_3_WR_PREAMBLE_MODE_DQ_PREAM_BITS_SHIFT 12 16540 #define DDR34_E0_PHY_BYTE_LANE_3_WR_PREAMBLE_MODE_DQ_PREAM_BITS_DEFAULT 0x00000000 16541 16542 /* DDR34_E0_PHY_BYTE_LANE_3 :: WR_PREAMBLE_MODE :: DQS [11:08] */ 16543 #define DDR34_E0_PHY_BYTE_LANE_3_WR_PREAMBLE_MODE_DQS_MASK 0x00000f00 16544 #define DDR34_E0_PHY_BYTE_LANE_3_WR_PREAMBLE_MODE_DQS_ALIGN 0 16545 #define DDR34_E0_PHY_BYTE_LANE_3_WR_PREAMBLE_MODE_DQS_BITS 4 16546 #define DDR34_E0_PHY_BYTE_LANE_3_WR_PREAMBLE_MODE_DQS_SHIFT 8 16547 #define DDR34_E0_PHY_BYTE_LANE_3_WR_PREAMBLE_MODE_DQS_DEFAULT 0x0000000e 16548 16549 /* DDR34_E0_PHY_BYTE_LANE_3 :: WR_PREAMBLE_MODE :: reserved1 [07:05] */ 16550 #define DDR34_E0_PHY_BYTE_LANE_3_WR_PREAMBLE_MODE_RESERVED1_MASK 0x000000e0 16551 #define DDR34_E0_PHY_BYTE_LANE_3_WR_PREAMBLE_MODE_RESERVED1_ALIGN 0 16552 #define DDR34_E0_PHY_BYTE_LANE_3_WR_PREAMBLE_MODE_RESERVED1_BITS 3 16553 #define DDR34_E0_PHY_BYTE_LANE_3_WR_PREAMBLE_MODE_RESERVED1_SHIFT 5 16554 16555 /* DDR34_E0_PHY_BYTE_LANE_3 :: WR_PREAMBLE_MODE :: DQS_POSTAM_BITS [04:03] */ 16556 #define DDR34_E0_PHY_BYTE_LANE_3_WR_PREAMBLE_MODE_DQS_POSTAM_BITS_MASK 0x00000018 16557 #define DDR34_E0_PHY_BYTE_LANE_3_WR_PREAMBLE_MODE_DQS_POSTAM_BITS_ALIGN 0 16558 #define DDR34_E0_PHY_BYTE_LANE_3_WR_PREAMBLE_MODE_DQS_POSTAM_BITS_BITS 2 16559 #define DDR34_E0_PHY_BYTE_LANE_3_WR_PREAMBLE_MODE_DQS_POSTAM_BITS_SHIFT 3 16560 #define DDR34_E0_PHY_BYTE_LANE_3_WR_PREAMBLE_MODE_DQS_POSTAM_BITS_DEFAULT 0x00000000 16561 16562 /* DDR34_E0_PHY_BYTE_LANE_3 :: WR_PREAMBLE_MODE :: DQS_PREAM_BITS [02:00] */ 16563 #define DDR34_E0_PHY_BYTE_LANE_3_WR_PREAMBLE_MODE_DQS_PREAM_BITS_MASK 0x00000007 16564 #define DDR34_E0_PHY_BYTE_LANE_3_WR_PREAMBLE_MODE_DQS_PREAM_BITS_ALIGN 0 16565 #define DDR34_E0_PHY_BYTE_LANE_3_WR_PREAMBLE_MODE_DQS_PREAM_BITS_BITS 3 16566 #define DDR34_E0_PHY_BYTE_LANE_3_WR_PREAMBLE_MODE_DQS_PREAM_BITS_SHIFT 0 16567 #define DDR34_E0_PHY_BYTE_LANE_3_WR_PREAMBLE_MODE_DQS_PREAM_BITS_DEFAULT 0x00000002 16568 16569 /*************************************************************************** 16570 *ODT_CONTROL - Read channel ODT control register 16571 */ 16572 /* DDR34_E0_PHY_BYTE_LANE_3 :: ODT_CONTROL :: reserved_for_padding0 [31:31] */ 16573 #define DDR34_E0_PHY_BYTE_LANE_3_ODT_CONTROL_RESERVED_for_padding0_MASK 0x80000000 16574 #define DDR34_E0_PHY_BYTE_LANE_3_ODT_CONTROL_RESERVED_for_padding0_ALIGN 0 16575 #define DDR34_E0_PHY_BYTE_LANE_3_ODT_CONTROL_RESERVED_for_padding0_BITS 1 16576 #define DDR34_E0_PHY_BYTE_LANE_3_ODT_CONTROL_RESERVED_for_padding0_SHIFT 31 16577 16578 /* DDR34_E0_PHY_BYTE_LANE_3 :: ODT_CONTROL :: reserved1 [30:10] */ 16579 #define DDR34_E0_PHY_BYTE_LANE_3_ODT_CONTROL_RESERVED1_MASK 0x7ffffc00 16580 #define DDR34_E0_PHY_BYTE_LANE_3_ODT_CONTROL_RESERVED1_ALIGN 0 16581 #define DDR34_E0_PHY_BYTE_LANE_3_ODT_CONTROL_RESERVED1_BITS 21 16582 #define DDR34_E0_PHY_BYTE_LANE_3_ODT_CONTROL_RESERVED1_SHIFT 10 16583 16584 /* DDR34_E0_PHY_BYTE_LANE_3 :: ODT_CONTROL :: ODT_ENABLE [09:09] */ 16585 #define DDR34_E0_PHY_BYTE_LANE_3_ODT_CONTROL_ODT_ENABLE_MASK 0x00000200 16586 #define DDR34_E0_PHY_BYTE_LANE_3_ODT_CONTROL_ODT_ENABLE_ALIGN 0 16587 #define DDR34_E0_PHY_BYTE_LANE_3_ODT_CONTROL_ODT_ENABLE_BITS 1 16588 #define DDR34_E0_PHY_BYTE_LANE_3_ODT_CONTROL_ODT_ENABLE_SHIFT 9 16589 #define DDR34_E0_PHY_BYTE_LANE_3_ODT_CONTROL_ODT_ENABLE_DEFAULT 0x00000001 16590 16591 /* DDR34_E0_PHY_BYTE_LANE_3 :: ODT_CONTROL :: ODT_DELAY [08:06] */ 16592 #define DDR34_E0_PHY_BYTE_LANE_3_ODT_CONTROL_ODT_DELAY_MASK 0x000001c0 16593 #define DDR34_E0_PHY_BYTE_LANE_3_ODT_CONTROL_ODT_DELAY_ALIGN 0 16594 #define DDR34_E0_PHY_BYTE_LANE_3_ODT_CONTROL_ODT_DELAY_BITS 3 16595 #define DDR34_E0_PHY_BYTE_LANE_3_ODT_CONTROL_ODT_DELAY_SHIFT 6 16596 #define DDR34_E0_PHY_BYTE_LANE_3_ODT_CONTROL_ODT_DELAY_DEFAULT 0x00000000 16597 16598 /* DDR34_E0_PHY_BYTE_LANE_3 :: ODT_CONTROL :: ODT_POST_LENGTH [05:03] */ 16599 #define DDR34_E0_PHY_BYTE_LANE_3_ODT_CONTROL_ODT_POST_LENGTH_MASK 0x00000038 16600 #define DDR34_E0_PHY_BYTE_LANE_3_ODT_CONTROL_ODT_POST_LENGTH_ALIGN 0 16601 #define DDR34_E0_PHY_BYTE_LANE_3_ODT_CONTROL_ODT_POST_LENGTH_BITS 3 16602 #define DDR34_E0_PHY_BYTE_LANE_3_ODT_CONTROL_ODT_POST_LENGTH_SHIFT 3 16603 #define DDR34_E0_PHY_BYTE_LANE_3_ODT_CONTROL_ODT_POST_LENGTH_DEFAULT 0x00000001 16604 16605 /* DDR34_E0_PHY_BYTE_LANE_3 :: ODT_CONTROL :: ODT_PRE_LENGTH [02:00] */ 16606 #define DDR34_E0_PHY_BYTE_LANE_3_ODT_CONTROL_ODT_PRE_LENGTH_MASK 0x00000007 16607 #define DDR34_E0_PHY_BYTE_LANE_3_ODT_CONTROL_ODT_PRE_LENGTH_ALIGN 0 16608 #define DDR34_E0_PHY_BYTE_LANE_3_ODT_CONTROL_ODT_PRE_LENGTH_BITS 3 16609 #define DDR34_E0_PHY_BYTE_LANE_3_ODT_CONTROL_ODT_PRE_LENGTH_SHIFT 0 16610 #define DDR34_E0_PHY_BYTE_LANE_3_ODT_CONTROL_ODT_PRE_LENGTH_DEFAULT 0x00000003 16611 16612 /*************************************************************************** 16613 *EDC_DPD_CONTROL - GDDR5M EDC digital phase detector control register 16614 */ 16615 /* DDR34_E0_PHY_BYTE_LANE_3 :: EDC_DPD_CONTROL :: reserved0 [31:06] */ 16616 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_DPD_CONTROL_RESERVED0_MASK 0xffffffc0 16617 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_DPD_CONTROL_RESERVED0_ALIGN 0 16618 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_DPD_CONTROL_RESERVED0_BITS 26 16619 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_DPD_CONTROL_RESERVED0_SHIFT 6 16620 16621 /* DDR34_E0_PHY_BYTE_LANE_3 :: EDC_DPD_CONTROL :: DQS_PHASE_OVERRIDE_VALUE [05:05] */ 16622 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_VALUE_MASK 0x00000020 16623 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_VALUE_ALIGN 0 16624 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_VALUE_BITS 1 16625 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_VALUE_SHIFT 5 16626 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_VALUE_DEFAULT 0x00000000 16627 16628 /* DDR34_E0_PHY_BYTE_LANE_3 :: EDC_DPD_CONTROL :: DQS_PHASE_OVERRIDE_ENABLE [04:04] */ 16629 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_ENABLE_MASK 0x00000010 16630 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_ENABLE_ALIGN 0 16631 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_ENABLE_BITS 1 16632 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_ENABLE_SHIFT 4 16633 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_ENABLE_DEFAULT 0x00000000 16634 16635 /* DDR34_E0_PHY_BYTE_LANE_3 :: EDC_DPD_CONTROL :: SET_ADJ_EN [03:03] */ 16636 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_DPD_CONTROL_SET_ADJ_EN_MASK 0x00000008 16637 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_DPD_CONTROL_SET_ADJ_EN_ALIGN 0 16638 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_DPD_CONTROL_SET_ADJ_EN_BITS 1 16639 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_DPD_CONTROL_SET_ADJ_EN_SHIFT 3 16640 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_DPD_CONTROL_SET_ADJ_EN_DEFAULT 0x00000000 16641 16642 /* DDR34_E0_PHY_BYTE_LANE_3 :: EDC_DPD_CONTROL :: UPDATE [02:02] */ 16643 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_DPD_CONTROL_UPDATE_MASK 0x00000004 16644 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_DPD_CONTROL_UPDATE_ALIGN 0 16645 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_DPD_CONTROL_UPDATE_BITS 1 16646 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_DPD_CONTROL_UPDATE_SHIFT 2 16647 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_DPD_CONTROL_UPDATE_DEFAULT 0x00000000 16648 16649 /* DDR34_E0_PHY_BYTE_LANE_3 :: EDC_DPD_CONTROL :: MONITOR [01:01] */ 16650 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_DPD_CONTROL_MONITOR_MASK 0x00000002 16651 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_DPD_CONTROL_MONITOR_ALIGN 0 16652 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_DPD_CONTROL_MONITOR_BITS 1 16653 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_DPD_CONTROL_MONITOR_SHIFT 1 16654 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_DPD_CONTROL_MONITOR_DEFAULT 0x00000000 16655 16656 /* DDR34_E0_PHY_BYTE_LANE_3 :: EDC_DPD_CONTROL :: INIT [00:00] */ 16657 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_DPD_CONTROL_INIT_MASK 0x00000001 16658 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_DPD_CONTROL_INIT_ALIGN 0 16659 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_DPD_CONTROL_INIT_BITS 1 16660 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_DPD_CONTROL_INIT_SHIFT 0 16661 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_DPD_CONTROL_INIT_DEFAULT 0x00000000 16662 16663 /*************************************************************************** 16664 *EDC_DPD_STATUS - GDDR5M EDC digital phase detector status register 16665 */ 16666 /* DDR34_E0_PHY_BYTE_LANE_3 :: EDC_DPD_STATUS :: reserved0 [31:25] */ 16667 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_DPD_STATUS_RESERVED0_MASK 0xfe000000 16668 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_DPD_STATUS_RESERVED0_ALIGN 0 16669 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_DPD_STATUS_RESERVED0_BITS 7 16670 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_DPD_STATUS_RESERVED0_SHIFT 25 16671 16672 /* DDR34_E0_PHY_BYTE_LANE_3 :: EDC_DPD_STATUS :: CURRENT_DQS_PHASE [24:24] */ 16673 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_DPD_STATUS_CURRENT_DQS_PHASE_MASK 0x01000000 16674 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_DPD_STATUS_CURRENT_DQS_PHASE_ALIGN 0 16675 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_DPD_STATUS_CURRENT_DQS_PHASE_BITS 1 16676 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_DPD_STATUS_CURRENT_DQS_PHASE_SHIFT 24 16677 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_DPD_STATUS_CURRENT_DQS_PHASE_DEFAULT 0x00000000 16678 16679 /* DDR34_E0_PHY_BYTE_LANE_3 :: EDC_DPD_STATUS :: CURRENT_VDL_SETTING [23:16] */ 16680 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_DPD_STATUS_CURRENT_VDL_SETTING_MASK 0x00ff0000 16681 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_DPD_STATUS_CURRENT_VDL_SETTING_ALIGN 0 16682 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_DPD_STATUS_CURRENT_VDL_SETTING_BITS 8 16683 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_DPD_STATUS_CURRENT_VDL_SETTING_SHIFT 16 16684 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_DPD_STATUS_CURRENT_VDL_SETTING_DEFAULT 0x00000000 16685 16686 /* DDR34_E0_PHY_BYTE_LANE_3 :: EDC_DPD_STATUS :: reserved1 [15:13] */ 16687 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_DPD_STATUS_RESERVED1_MASK 0x0000e000 16688 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_DPD_STATUS_RESERVED1_ALIGN 0 16689 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_DPD_STATUS_RESERVED1_BITS 3 16690 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_DPD_STATUS_RESERVED1_SHIFT 13 16691 16692 /* DDR34_E0_PHY_BYTE_LANE_3 :: EDC_DPD_STATUS :: INIT_DQS_PHASE [12:12] */ 16693 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_DPD_STATUS_INIT_DQS_PHASE_MASK 0x00001000 16694 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_DPD_STATUS_INIT_DQS_PHASE_ALIGN 0 16695 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_DPD_STATUS_INIT_DQS_PHASE_BITS 1 16696 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_DPD_STATUS_INIT_DQS_PHASE_SHIFT 12 16697 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_DPD_STATUS_INIT_DQS_PHASE_DEFAULT 0x00000000 16698 16699 /* DDR34_E0_PHY_BYTE_LANE_3 :: EDC_DPD_STATUS :: INIT_VDL_SETTING [11:04] */ 16700 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_DPD_STATUS_INIT_VDL_SETTING_MASK 0x00000ff0 16701 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_DPD_STATUS_INIT_VDL_SETTING_ALIGN 0 16702 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_DPD_STATUS_INIT_VDL_SETTING_BITS 8 16703 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_DPD_STATUS_INIT_VDL_SETTING_SHIFT 4 16704 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_DPD_STATUS_INIT_VDL_SETTING_DEFAULT 0x00000000 16705 16706 /* DDR34_E0_PHY_BYTE_LANE_3 :: EDC_DPD_STATUS :: EDGE_ERROR [03:03] */ 16707 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_DPD_STATUS_EDGE_ERROR_MASK 0x00000008 16708 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_DPD_STATUS_EDGE_ERROR_ALIGN 0 16709 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_DPD_STATUS_EDGE_ERROR_BITS 1 16710 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_DPD_STATUS_EDGE_ERROR_SHIFT 3 16711 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_DPD_STATUS_EDGE_ERROR_DEFAULT 0x00000000 16712 16713 /* DDR34_E0_PHY_BYTE_LANE_3 :: EDC_DPD_STATUS :: MONITOR_BUSY [02:02] */ 16714 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_DPD_STATUS_MONITOR_BUSY_MASK 0x00000004 16715 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_DPD_STATUS_MONITOR_BUSY_ALIGN 0 16716 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_DPD_STATUS_MONITOR_BUSY_BITS 1 16717 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_DPD_STATUS_MONITOR_BUSY_SHIFT 2 16718 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_DPD_STATUS_MONITOR_BUSY_DEFAULT 0x00000000 16719 16720 /* DDR34_E0_PHY_BYTE_LANE_3 :: EDC_DPD_STATUS :: INIT_BUSY [01:01] */ 16721 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_DPD_STATUS_INIT_BUSY_MASK 0x00000002 16722 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_DPD_STATUS_INIT_BUSY_ALIGN 0 16723 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_DPD_STATUS_INIT_BUSY_BITS 1 16724 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_DPD_STATUS_INIT_BUSY_SHIFT 1 16725 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_DPD_STATUS_INIT_BUSY_DEFAULT 0x00000000 16726 16727 /* DDR34_E0_PHY_BYTE_LANE_3 :: EDC_DPD_STATUS :: INIT_DONE [00:00] */ 16728 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_DPD_STATUS_INIT_DONE_MASK 0x00000001 16729 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_DPD_STATUS_INIT_DONE_ALIGN 0 16730 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_DPD_STATUS_INIT_DONE_BITS 1 16731 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_DPD_STATUS_INIT_DONE_SHIFT 0 16732 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_DPD_STATUS_INIT_DONE_DEFAULT 0x00000000 16733 16734 /*************************************************************************** 16735 *EDC_DPD_OUT_CONTROL - GDDR5M EDC digital phase detector output signal control register 16736 */ 16737 /* DDR34_E0_PHY_BYTE_LANE_3 :: EDC_DPD_OUT_CONTROL :: reserved0 [31:20] */ 16738 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_DPD_OUT_CONTROL_RESERVED0_MASK 0xfff00000 16739 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_DPD_OUT_CONTROL_RESERVED0_ALIGN 0 16740 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_DPD_OUT_CONTROL_RESERVED0_BITS 12 16741 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_DPD_OUT_CONTROL_RESERVED0_SHIFT 20 16742 16743 /* DDR34_E0_PHY_BYTE_LANE_3 :: EDC_DPD_OUT_CONTROL :: LOWER_LIMIT [19:12] */ 16744 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_DPD_OUT_CONTROL_LOWER_LIMIT_MASK 0x000ff000 16745 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_DPD_OUT_CONTROL_LOWER_LIMIT_ALIGN 0 16746 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_DPD_OUT_CONTROL_LOWER_LIMIT_BITS 8 16747 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_DPD_OUT_CONTROL_LOWER_LIMIT_SHIFT 12 16748 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_DPD_OUT_CONTROL_LOWER_LIMIT_DEFAULT 0x00000000 16749 16750 /* DDR34_E0_PHY_BYTE_LANE_3 :: EDC_DPD_OUT_CONTROL :: UPPER_LIMIT [11:04] */ 16751 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_DPD_OUT_CONTROL_UPPER_LIMIT_MASK 0x00000ff0 16752 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_DPD_OUT_CONTROL_UPPER_LIMIT_ALIGN 0 16753 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_DPD_OUT_CONTROL_UPPER_LIMIT_BITS 8 16754 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_DPD_OUT_CONTROL_UPPER_LIMIT_SHIFT 4 16755 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_DPD_OUT_CONTROL_UPPER_LIMIT_DEFAULT 0x00000000 16756 16757 /* DDR34_E0_PHY_BYTE_LANE_3 :: EDC_DPD_OUT_CONTROL :: reserved1 [03:01] */ 16758 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_DPD_OUT_CONTROL_RESERVED1_MASK 0x0000000e 16759 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_DPD_OUT_CONTROL_RESERVED1_ALIGN 0 16760 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_DPD_OUT_CONTROL_RESERVED1_BITS 3 16761 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_DPD_OUT_CONTROL_RESERVED1_SHIFT 1 16762 16763 /* DDR34_E0_PHY_BYTE_LANE_3 :: EDC_DPD_OUT_CONTROL :: ENABLE [00:00] */ 16764 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_DPD_OUT_CONTROL_ENABLE_MASK 0x00000001 16765 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_DPD_OUT_CONTROL_ENABLE_ALIGN 0 16766 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_DPD_OUT_CONTROL_ENABLE_BITS 1 16767 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_DPD_OUT_CONTROL_ENABLE_SHIFT 0 16768 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_DPD_OUT_CONTROL_ENABLE_DEFAULT 0x00000000 16769 16770 /*************************************************************************** 16771 *EDC_DPD_OUT_STATUS - GDDR5M EDC digital phase detector output signal status register 16772 */ 16773 /* DDR34_E0_PHY_BYTE_LANE_3 :: EDC_DPD_OUT_STATUS :: reserved0 [31:12] */ 16774 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_DPD_OUT_STATUS_RESERVED0_MASK 0xfffff000 16775 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_DPD_OUT_STATUS_RESERVED0_ALIGN 0 16776 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_DPD_OUT_STATUS_RESERVED0_BITS 20 16777 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_DPD_OUT_STATUS_RESERVED0_SHIFT 12 16778 16779 /* DDR34_E0_PHY_BYTE_LANE_3 :: EDC_DPD_OUT_STATUS :: VDL_SETTING [11:04] */ 16780 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_DPD_OUT_STATUS_VDL_SETTING_MASK 0x00000ff0 16781 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_DPD_OUT_STATUS_VDL_SETTING_ALIGN 0 16782 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_DPD_OUT_STATUS_VDL_SETTING_BITS 8 16783 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_DPD_OUT_STATUS_VDL_SETTING_SHIFT 4 16784 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_DPD_OUT_STATUS_VDL_SETTING_DEFAULT 0x00000000 16785 16786 /* DDR34_E0_PHY_BYTE_LANE_3 :: EDC_DPD_OUT_STATUS :: reserved1 [03:01] */ 16787 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_DPD_OUT_STATUS_RESERVED1_MASK 0x0000000e 16788 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_DPD_OUT_STATUS_RESERVED1_ALIGN 0 16789 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_DPD_OUT_STATUS_RESERVED1_BITS 3 16790 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_DPD_OUT_STATUS_RESERVED1_SHIFT 1 16791 16792 /* DDR34_E0_PHY_BYTE_LANE_3 :: EDC_DPD_OUT_STATUS :: VALID [00:00] */ 16793 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_DPD_OUT_STATUS_VALID_MASK 0x00000001 16794 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_DPD_OUT_STATUS_VALID_ALIGN 0 16795 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_DPD_OUT_STATUS_VALID_BITS 1 16796 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_DPD_OUT_STATUS_VALID_SHIFT 0 16797 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_DPD_OUT_STATUS_VALID_DEFAULT 0x00000000 16798 16799 /*************************************************************************** 16800 *EDC_DPD_OUT_STATUS_CLEAR - GDDR5M EDC digital phase detector output signal status clear register 16801 */ 16802 /* DDR34_E0_PHY_BYTE_LANE_3 :: EDC_DPD_OUT_STATUS_CLEAR :: reserved0 [31:01] */ 16803 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_DPD_OUT_STATUS_CLEAR_RESERVED0_MASK 0xfffffffe 16804 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_DPD_OUT_STATUS_CLEAR_RESERVED0_ALIGN 0 16805 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_DPD_OUT_STATUS_CLEAR_RESERVED0_BITS 31 16806 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_DPD_OUT_STATUS_CLEAR_RESERVED0_SHIFT 1 16807 16808 /* DDR34_E0_PHY_BYTE_LANE_3 :: EDC_DPD_OUT_STATUS_CLEAR :: CLEAR [00:00] */ 16809 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_DPD_OUT_STATUS_CLEAR_CLEAR_MASK 0x00000001 16810 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_DPD_OUT_STATUS_CLEAR_CLEAR_ALIGN 0 16811 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_DPD_OUT_STATUS_CLEAR_CLEAR_BITS 1 16812 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_DPD_OUT_STATUS_CLEAR_CLEAR_SHIFT 0 16813 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_DPD_OUT_STATUS_CLEAR_CLEAR_DEFAULT 0x00000000 16814 16815 /*************************************************************************** 16816 *EDC_CRC_CONTROL - GDDR5M EDC signal path CRC control register 16817 */ 16818 /* DDR34_E0_PHY_BYTE_LANE_3 :: EDC_CRC_CONTROL :: BUSY [31:31] */ 16819 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_CRC_CONTROL_BUSY_MASK 0x80000000 16820 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_CRC_CONTROL_BUSY_ALIGN 0 16821 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_CRC_CONTROL_BUSY_BITS 1 16822 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_CRC_CONTROL_BUSY_SHIFT 31 16823 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_CRC_CONTROL_BUSY_DEFAULT 0x00000000 16824 16825 /* DDR34_E0_PHY_BYTE_LANE_3 :: EDC_CRC_CONTROL :: reserved0 [30:17] */ 16826 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_CRC_CONTROL_RESERVED0_MASK 0x7ffe0000 16827 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_CRC_CONTROL_RESERVED0_ALIGN 0 16828 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_CRC_CONTROL_RESERVED0_BITS 14 16829 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_CRC_CONTROL_RESERVED0_SHIFT 17 16830 16831 /* DDR34_E0_PHY_BYTE_LANE_3 :: EDC_CRC_CONTROL :: FORCE [16:16] */ 16832 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_CRC_CONTROL_FORCE_MASK 0x00010000 16833 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_CRC_CONTROL_FORCE_ALIGN 0 16834 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_CRC_CONTROL_FORCE_BITS 1 16835 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_CRC_CONTROL_FORCE_SHIFT 16 16836 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_CRC_CONTROL_FORCE_DEFAULT 0x00000000 16837 16838 /* DDR34_E0_PHY_BYTE_LANE_3 :: EDC_CRC_CONTROL :: reserved1 [15:11] */ 16839 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_CRC_CONTROL_RESERVED1_MASK 0x0000f800 16840 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_CRC_CONTROL_RESERVED1_ALIGN 0 16841 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_CRC_CONTROL_RESERVED1_BITS 5 16842 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_CRC_CONTROL_RESERVED1_SHIFT 11 16843 16844 /* DDR34_E0_PHY_BYTE_LANE_3 :: EDC_CRC_CONTROL :: CRCWL [10:08] */ 16845 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_CRC_CONTROL_CRCWL_MASK 0x00000700 16846 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_CRC_CONTROL_CRCWL_ALIGN 0 16847 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_CRC_CONTROL_CRCWL_BITS 3 16848 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_CRC_CONTROL_CRCWL_SHIFT 8 16849 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_CRC_CONTROL_CRCWL_DEFAULT 0x00000000 16850 16851 /* DDR34_E0_PHY_BYTE_LANE_3 :: EDC_CRC_CONTROL :: reserved2 [07:06] */ 16852 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_CRC_CONTROL_RESERVED2_MASK 0x000000c0 16853 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_CRC_CONTROL_RESERVED2_ALIGN 0 16854 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_CRC_CONTROL_RESERVED2_BITS 2 16855 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_CRC_CONTROL_RESERVED2_SHIFT 6 16856 16857 /* DDR34_E0_PHY_BYTE_LANE_3 :: EDC_CRC_CONTROL :: CRCRL [05:04] */ 16858 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_CRC_CONTROL_CRCRL_MASK 0x00000030 16859 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_CRC_CONTROL_CRCRL_ALIGN 0 16860 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_CRC_CONTROL_CRCRL_BITS 2 16861 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_CRC_CONTROL_CRCRL_SHIFT 4 16862 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_CRC_CONTROL_CRCRL_DEFAULT 0x00000000 16863 16864 /* DDR34_E0_PHY_BYTE_LANE_3 :: EDC_CRC_CONTROL :: reserved3 [03:03] */ 16865 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_CRC_CONTROL_RESERVED3_MASK 0x00000008 16866 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_CRC_CONTROL_RESERVED3_ALIGN 0 16867 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_CRC_CONTROL_RESERVED3_BITS 1 16868 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_CRC_CONTROL_RESERVED3_SHIFT 3 16869 16870 /* DDR34_E0_PHY_BYTE_LANE_3 :: EDC_CRC_CONTROL :: COUNT_MODE [02:02] */ 16871 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_CRC_CONTROL_COUNT_MODE_MASK 0x00000004 16872 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_CRC_CONTROL_COUNT_MODE_ALIGN 0 16873 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_CRC_CONTROL_COUNT_MODE_BITS 1 16874 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_CRC_CONTROL_COUNT_MODE_SHIFT 2 16875 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_CRC_CONTROL_COUNT_MODE_DEFAULT 0x00000000 16876 16877 /* DDR34_E0_PHY_BYTE_LANE_3 :: EDC_CRC_CONTROL :: ENABLE_WR [01:01] */ 16878 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_CRC_CONTROL_ENABLE_WR_MASK 0x00000002 16879 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_CRC_CONTROL_ENABLE_WR_ALIGN 0 16880 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_CRC_CONTROL_ENABLE_WR_BITS 1 16881 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_CRC_CONTROL_ENABLE_WR_SHIFT 1 16882 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_CRC_CONTROL_ENABLE_WR_DEFAULT 0x00000000 16883 16884 /* DDR34_E0_PHY_BYTE_LANE_3 :: EDC_CRC_CONTROL :: ENABLE_RD [00:00] */ 16885 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_CRC_CONTROL_ENABLE_RD_MASK 0x00000001 16886 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_CRC_CONTROL_ENABLE_RD_ALIGN 0 16887 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_CRC_CONTROL_ENABLE_RD_BITS 1 16888 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_CRC_CONTROL_ENABLE_RD_SHIFT 0 16889 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_CRC_CONTROL_ENABLE_RD_DEFAULT 0x00000000 16890 16891 /*************************************************************************** 16892 *EDC_CRC_STATUS - GDDR5M EDC signal path CRC status register 16893 */ 16894 /* DDR34_E0_PHY_BYTE_LANE_3 :: EDC_CRC_STATUS :: reserved0 [31:04] */ 16895 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_CRC_STATUS_RESERVED0_MASK 0xfffffff0 16896 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_CRC_STATUS_RESERVED0_ALIGN 0 16897 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_CRC_STATUS_RESERVED0_BITS 28 16898 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_CRC_STATUS_RESERVED0_SHIFT 4 16899 16900 /* DDR34_E0_PHY_BYTE_LANE_3 :: EDC_CRC_STATUS :: WR_FAIL [03:03] */ 16901 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_CRC_STATUS_WR_FAIL_MASK 0x00000008 16902 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_CRC_STATUS_WR_FAIL_ALIGN 0 16903 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_CRC_STATUS_WR_FAIL_BITS 1 16904 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_CRC_STATUS_WR_FAIL_SHIFT 3 16905 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_CRC_STATUS_WR_FAIL_DEFAULT 0x00000000 16906 16907 /* DDR34_E0_PHY_BYTE_LANE_3 :: EDC_CRC_STATUS :: WR_PASS [02:02] */ 16908 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_CRC_STATUS_WR_PASS_MASK 0x00000004 16909 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_CRC_STATUS_WR_PASS_ALIGN 0 16910 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_CRC_STATUS_WR_PASS_BITS 1 16911 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_CRC_STATUS_WR_PASS_SHIFT 2 16912 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_CRC_STATUS_WR_PASS_DEFAULT 0x00000000 16913 16914 /* DDR34_E0_PHY_BYTE_LANE_3 :: EDC_CRC_STATUS :: RD_FAIL [01:01] */ 16915 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_CRC_STATUS_RD_FAIL_MASK 0x00000002 16916 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_CRC_STATUS_RD_FAIL_ALIGN 0 16917 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_CRC_STATUS_RD_FAIL_BITS 1 16918 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_CRC_STATUS_RD_FAIL_SHIFT 1 16919 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_CRC_STATUS_RD_FAIL_DEFAULT 0x00000000 16920 16921 /* DDR34_E0_PHY_BYTE_LANE_3 :: EDC_CRC_STATUS :: RD_PASS [00:00] */ 16922 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_CRC_STATUS_RD_PASS_MASK 0x00000001 16923 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_CRC_STATUS_RD_PASS_ALIGN 0 16924 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_CRC_STATUS_RD_PASS_BITS 1 16925 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_CRC_STATUS_RD_PASS_SHIFT 0 16926 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_CRC_STATUS_RD_PASS_DEFAULT 0x00000000 16927 16928 /*************************************************************************** 16929 *EDC_CRC_COUNT - GDDR5M EDC signal path CRC counter register 16930 */ 16931 /* DDR34_E0_PHY_BYTE_LANE_3 :: EDC_CRC_COUNT :: reserved0 [31:28] */ 16932 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_CRC_COUNT_RESERVED0_MASK 0xf0000000 16933 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_CRC_COUNT_RESERVED0_ALIGN 0 16934 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_CRC_COUNT_RESERVED0_BITS 4 16935 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_CRC_COUNT_RESERVED0_SHIFT 28 16936 16937 /* DDR34_E0_PHY_BYTE_LANE_3 :: EDC_CRC_COUNT :: WR_COUNT [27:16] */ 16938 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_CRC_COUNT_WR_COUNT_MASK 0x0fff0000 16939 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_CRC_COUNT_WR_COUNT_ALIGN 0 16940 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_CRC_COUNT_WR_COUNT_BITS 12 16941 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_CRC_COUNT_WR_COUNT_SHIFT 16 16942 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_CRC_COUNT_WR_COUNT_DEFAULT 0x00000000 16943 16944 /* DDR34_E0_PHY_BYTE_LANE_3 :: EDC_CRC_COUNT :: reserved1 [15:12] */ 16945 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_CRC_COUNT_RESERVED1_MASK 0x0000f000 16946 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_CRC_COUNT_RESERVED1_ALIGN 0 16947 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_CRC_COUNT_RESERVED1_BITS 4 16948 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_CRC_COUNT_RESERVED1_SHIFT 12 16949 16950 /* DDR34_E0_PHY_BYTE_LANE_3 :: EDC_CRC_COUNT :: RD_COUNT [11:00] */ 16951 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_CRC_COUNT_RD_COUNT_MASK 0x00000fff 16952 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_CRC_COUNT_RD_COUNT_ALIGN 0 16953 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_CRC_COUNT_RD_COUNT_BITS 12 16954 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_CRC_COUNT_RD_COUNT_SHIFT 0 16955 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_CRC_COUNT_RD_COUNT_DEFAULT 0x00000000 16956 16957 /*************************************************************************** 16958 *EDC_CRC_STATUS_CLEAR - GDDR5M EDC signal path CRC counter register 16959 */ 16960 /* DDR34_E0_PHY_BYTE_LANE_3 :: EDC_CRC_STATUS_CLEAR :: reserved0 [31:01] */ 16961 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_CRC_STATUS_CLEAR_RESERVED0_MASK 0xfffffffe 16962 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_CRC_STATUS_CLEAR_RESERVED0_ALIGN 0 16963 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_CRC_STATUS_CLEAR_RESERVED0_BITS 31 16964 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_CRC_STATUS_CLEAR_RESERVED0_SHIFT 1 16965 16966 /* DDR34_E0_PHY_BYTE_LANE_3 :: EDC_CRC_STATUS_CLEAR :: CLEAR [00:00] */ 16967 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_CRC_STATUS_CLEAR_CLEAR_MASK 0x00000001 16968 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_CRC_STATUS_CLEAR_CLEAR_ALIGN 0 16969 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_CRC_STATUS_CLEAR_CLEAR_BITS 1 16970 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_CRC_STATUS_CLEAR_CLEAR_SHIFT 0 16971 #define DDR34_E0_PHY_BYTE_LANE_3_EDC_CRC_STATUS_CLEAR_CLEAR_DEFAULT 0x00000000 16972 16973 /*************************************************************************** 16974 *BL_SPARE_REG - Byte-Lane Spare register 16975 */ 16976 /* DDR34_E0_PHY_BYTE_LANE_3 :: BL_SPARE_REG :: reserved_for_eco0 [31:00] */ 16977 #define DDR34_E0_PHY_BYTE_LANE_3_BL_SPARE_REG_RESERVED_for_eco0_MASK 0xffffffff 16978 #define DDR34_E0_PHY_BYTE_LANE_3_BL_SPARE_REG_RESERVED_for_eco0_ALIGN 0 16979 #define DDR34_E0_PHY_BYTE_LANE_3_BL_SPARE_REG_RESERVED_for_eco0_BITS 32 16980 #define DDR34_E0_PHY_BYTE_LANE_3_BL_SPARE_REG_RESERVED_for_eco0_SHIFT 0 16981 #define DDR34_E0_PHY_BYTE_LANE_3_BL_SPARE_REG_RESERVED_for_eco0_DEFAULT 0x00000000 16982 16983 #endif /* #ifndef DDR34_E0_PHY_H__ */ 16984 16985 /* End of File */ 16986