ddr40.h (716569B)
1 /* 2 * 3 * 4 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 5 * 6 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 7 * 8 * THIS SOFTWARE MAY ONLY BE USED SUBJECT TO AN EXECUTED SOFTWARE LICENSE 9 * AGREEMENT BETWEEN THE USER AND BROADCOM. YOU HAVE NO RIGHT TO USE OR 10 * EXPLOIT THIS MATERIAL EXCEPT SUBJECT TO THE TERMS OF SUCH AN AGREEMENT. 11 * 12 * $brcm_Workfile: $ 13 * $brcm_Revision: $ 14 * $brcm_Date: $ 15 * 16 * Module Description: 17 * DO NOT EDIT THIS FILE DIRECTLY 18 * 19 * This module was generated magically with RDB from a source description 20 * file. You must edit the source file for changes to be made to this file. 21 * 22 * 23 * Date: Generated on Tue Dec 6 15:19:23 2011 24 * MD5 Checksum 84dde632045f866a8fab58fb0f667b68 25 * 26 * Compiled with: RDB Utility 5.0 27 * RDB Parser 3.0 28 * rdb2macro.pm 4.0 29 * Perl Interpreter 5.008008 30 * Operating System linux 31 * 32 * Spec Versions: DDR40_PHY_ADDR_CTL 3 33 * DDR40_PHY_WORD_LANE 04 34 * 35 * RDB Files: /projects/ntsw-sw2/home/mbasoglu/sdk/src/soc/phy/regs/ddr40/ddr40_phy_top_blockdef.rdb 36 * /projects/ntsw-sw2/home/mbasoglu/sdk/src/soc/phy/regs/ddr40/ddr40_phy_addr_ctl.rdb 37 * /projects/ntsw-sw2/home/mbasoglu/sdk/src/soc/phy/regs/ddr40/ddr40_phy_word_lane.rdb 38 * 39 * Revision History: 40 * 41 * $brcm_Log: $ 42 */ 43 44 #ifndef DDR40_H__ 45 #define DDR40_H__ 46 47 /** 48 * m = memory, c = core, r = register, f = field, d = data. 49 */ 50 #if !defined(GET_FIELD) && !defined(SET_FIELD) 51 #define BRCM_ALIGN(c,r,f) c##_##r##_##f##_ALIGN 52 #define BRCM_BITS(c,r,f) c##_##r##_##f##_BITS 53 #define BRCM_MASK(c,r,f) c##_##r##_##f##_MASK 54 #define BRCM_SHIFT(c,r,f) c##_##r##_##f##_SHIFT 55 56 #define GET_FIELD(m,c,r,f) \ 57 ((((m) & BRCM_MASK(c,r,f)) >> BRCM_SHIFT(c,r,f)) << BRCM_ALIGN(c,r,f)) 58 59 #define SET_FIELD(m,c,r,f,d) \ 60 ((m) = (((m) & ~BRCM_MASK(c,r,f)) | ((((d) >> BRCM_ALIGN(c,r,f)) << \ 61 BRCM_SHIFT(c,r,f)) & BRCM_MASK(c,r,f))) \ 62 ) 63 64 #define SET_TYPE_FIELD(m,c,r,f,d) SET_FIELD(m,c,r,f,c##_##d) 65 #define SET_NAME_FIELD(m,c,r,f,d) SET_FIELD(m,c,r,f,c##_##r##_##f##_##d) 66 #define SET_VALUE_FIELD(m,c,r,f,d) SET_FIELD(m,c,r,f,d) 67 68 #endif /* GET & SET */ 69 70 /**************************************************************************** 71 * Core Enums. 72 */ 73 /**************************************************************************** 74 * DDR40_PHY_DDR40_PHY_CONTROL_REGS 75 */ 76 77 /* Address & Control revision register */ 78 #define READ_DDR40_PHY_CONTROL_REGS_REVISIONr(_unit, _pc, _val) \ 79 DDR40_REG_READ((_unit), (_pc), 0x00, 0x00000000, (_val)) 80 #define WRITE_DDR40_PHY_CONTROL_REGS_REVISIONr(_unit, _pc, _val) \ 81 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x00000000, (_val)) 82 #define MODIFY_DDR40_PHY_CONTROL_REGS_REVISIONr(_unit, _pc, _val, _mask) \ 83 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x00000000, (_val), (_mask)) 84 85 /* PHY clock power management control register */ 86 #define READ_DDR40_PHY_CONTROL_REGS_CLK_PM_CTRLr(_unit, _pc, _val) \ 87 DDR40_REG_READ((_unit), (_pc), 0x00, 0x00000004, (_val)) 88 #define WRITE_DDR40_PHY_CONTROL_REGS_CLK_PM_CTRLr(_unit, _pc, _val) \ 89 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x00000004, (_val)) 90 #define MODIFY_DDR40_PHY_CONTROL_REGS_CLK_PM_CTRLr(_unit, _pc, _val, _mask) \ 91 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x00000004, (_val), (_mask)) 92 93 /* PHY PLL status register */ 94 #define READ_DDR40_PHY_CONTROL_REGS_PLL_STATUSr(_unit, _pc, _val) \ 95 DDR40_REG_READ((_unit), (_pc), 0x00, 0x00000010, (_val)) 96 #define WRITE_DDR40_PHY_CONTROL_REGS_PLL_STATUSr(_unit, _pc, _val) \ 97 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x00000010, (_val)) 98 #define MODIFY_DDR40_PHY_CONTROL_REGS_PLL_STATUSr(_unit, _pc, _val, _mask) \ 99 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x00000010, (_val), (_mask)) 100 101 /* PHY PLL configuration register */ 102 #define READ_DDR40_PHY_CONTROL_REGS_PLL_CONFIGr(_unit, _pc, _val) \ 103 DDR40_REG_READ((_unit), (_pc), 0x00, 0x00000014, (_val)) 104 #define WRITE_DDR40_PHY_CONTROL_REGS_PLL_CONFIGr(_unit, _pc, _val) \ 105 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x00000014, (_val)) 106 #define MODIFY_DDR40_PHY_CONTROL_REGS_PLL_CONFIGr(_unit, _pc, _val, _mask) \ 107 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x00000014, (_val), (_mask)) 108 109 /* PHY PLL control register */ 110 #define READ_DDR40_PHY_CONTROL_REGS_PLL_CONTROLr(_unit, _pc, _val) \ 111 DDR40_REG_READ((_unit), (_pc), 0x00, 0x00000018, (_val)) 112 #define WRITE_DDR40_PHY_CONTROL_REGS_PLL_CONTROLr(_unit, _pc, _val) \ 113 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x00000018, (_val)) 114 #define MODIFY_DDR40_PHY_CONTROL_REGS_PLL_CONTROLr(_unit, _pc, _val, _mask) \ 115 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x00000018, (_val), (_mask)) 116 117 /* PHY PLL dividers control register */ 118 #define READ_DDR40_PHY_CONTROL_REGS_PLL_DIVIDERSr(_unit, _pc, _val) \ 119 DDR40_REG_READ((_unit), (_pc), 0x00, 0x0000001c, (_val)) 120 #define WRITE_DDR40_PHY_CONTROL_REGS_PLL_DIVIDERSr(_unit, _pc, _val) \ 121 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x0000001c, (_val)) 122 #define MODIFY_DDR40_PHY_CONTROL_REGS_PLL_DIVIDERSr(_unit, _pc, _val, _mask) \ 123 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000001c, (_val), (_mask)) 124 125 /* Aux Control register */ 126 #define READ_DDR40_PHY_CONTROL_REGS_AUX_CONTROLr(_unit, _pc, _val) \ 127 DDR40_REG_READ((_unit), (_pc), 0x00, 0x00000020, (_val)) 128 #define WRITE_DDR40_PHY_CONTROL_REGS_AUX_CONTROLr(_unit, _pc, _val) \ 129 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x00000020, (_val)) 130 #define MODIFY_DDR40_PHY_CONTROL_REGS_AUX_CONTROLr(_unit, _pc, _val, _mask) \ 131 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x00000020, (_val), (_mask)) 132 133 /* Address & Control coarse VDL static override control register */ 134 #define READ_DDR40_PHY_CONTROL_REGS_VDL_OVRIDE_BYTE_CTLr(_unit, _pc, _val) \ 135 DDR40_REG_READ((_unit), (_pc), 0x00, 0x00000030, (_val)) 136 #define WRITE_DDR40_PHY_CONTROL_REGS_VDL_OVRIDE_BYTE_CTLr(_unit, _pc, _val) \ 137 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x00000030, (_val)) 138 #define MODIFY_DDR40_PHY_CONTROL_REGS_VDL_OVRIDE_BYTE_CTLr(_unit, _pc, _val, _mask) \ 139 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x00000030, (_val), (_mask)) 140 141 /* Address & Control fine VDL static override control register */ 142 #define READ_DDR40_PHY_CONTROL_REGS_VDL_OVRIDE_BIT_CTLr(_unit, _pc, _val) \ 143 DDR40_REG_READ((_unit), (_pc), 0x00, 0x00000034, (_val)) 144 #define WRITE_DDR40_PHY_CONTROL_REGS_VDL_OVRIDE_BIT_CTLr(_unit, _pc, _val) \ 145 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x00000034, (_val)) 146 #define MODIFY_DDR40_PHY_CONTROL_REGS_VDL_OVRIDE_BIT_CTLr(_unit, _pc, _val, _mask) \ 147 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x00000034, (_val), (_mask)) 148 149 /* Idle mode SSTL pad control register */ 150 #define READ_DDR40_PHY_CONTROL_REGS_IDLE_PAD_CONTROLr(_unit, _pc, _val) \ 151 DDR40_REG_READ((_unit), (_pc), 0x00, 0x00000038, (_val)) 152 #define WRITE_DDR40_PHY_CONTROL_REGS_IDLE_PAD_CONTROLr(_unit, _pc, _val) \ 153 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x00000038, (_val)) 154 #define MODIFY_DDR40_PHY_CONTROL_REGS_IDLE_PAD_CONTROLr(_unit, _pc, _val, _mask) \ 155 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x00000038, (_val), (_mask)) 156 157 /* PVT Compensation control and status register */ 158 #define READ_DDR40_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTLr(_unit, _pc, _val) \ 159 DDR40_REG_READ((_unit), (_pc), 0x00, 0x0000003c, (_val)) 160 #define WRITE_DDR40_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTLr(_unit, _pc, _val) \ 161 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x0000003c, (_val)) 162 #define MODIFY_DDR40_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTLr(_unit, _pc, _val, _mask) \ 163 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000003c, (_val), (_mask)) 164 165 /* SSTL pad drive characteristics control register */ 166 #define READ_DDR40_PHY_CONTROL_REGS_DRIVE_PAD_CTLr(_unit, _pc, _val) \ 167 DDR40_REG_READ((_unit), (_pc), 0x00, 0x00000040, (_val)) 168 #define WRITE_DDR40_PHY_CONTROL_REGS_DRIVE_PAD_CTLr(_unit, _pc, _val) \ 169 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x00000040, (_val)) 170 #define MODIFY_DDR40_PHY_CONTROL_REGS_DRIVE_PAD_CTLr(_unit, _pc, _val, _mask) \ 171 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x00000040, (_val), (_mask)) 172 173 /* PHY Auto Init rd_data_dly result register */ 174 #define READ_DDR40_PHY_CONTROL_REGS_VDL_RD_DATA_DLY_STATUSr(_unit, _pc, _val) \ 175 DDR40_REG_READ((_unit), (_pc), 0x00, 0x00000044, (_val)) 176 #define WRITE_DDR40_PHY_CONTROL_REGS_VDL_RD_DATA_DLY_STATUSr(_unit, _pc, _val) \ 177 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x00000044, (_val)) 178 #define MODIFY_DDR40_PHY_CONTROL_REGS_VDL_RD_DATA_DLY_STATUSr(_unit, _pc, _val, _mask) \ 179 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x00000044, (_val), (_mask)) 180 181 /* PHY VDL calibration control register */ 182 #define READ_DDR40_PHY_CONTROL_REGS_VDL_CALIBRATEr(_unit, _pc, _val) \ 183 DDR40_REG_READ((_unit), (_pc), 0x00, 0x00000048, (_val)) 184 #define WRITE_DDR40_PHY_CONTROL_REGS_VDL_CALIBRATEr(_unit, _pc, _val) \ 185 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x00000048, (_val)) 186 #define MODIFY_DDR40_PHY_CONTROL_REGS_VDL_CALIBRATEr(_unit, _pc, _val, _mask) \ 187 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x00000048, (_val), (_mask)) 188 189 /* PHY VDL calibration status register */ 190 #define READ_DDR40_PHY_CONTROL_REGS_VDL_CALIB_STATUSr(_unit, _pc, _val) \ 191 DDR40_REG_READ((_unit), (_pc), 0x00, 0x0000004c, (_val)) 192 #define WRITE_DDR40_PHY_CONTROL_REGS_VDL_CALIB_STATUSr(_unit, _pc, _val) \ 193 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x0000004c, (_val)) 194 #define MODIFY_DDR40_PHY_CONTROL_REGS_VDL_CALIB_STATUSr(_unit, _pc, _val, _mask) \ 195 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000004c, (_val), (_mask)) 196 197 /* PHY DQ VDL calibration status register */ 198 #define READ_DDR40_PHY_CONTROL_REGS_VDL_DQ_CALIB_STATUSr(_unit, _pc, _val) \ 199 DDR40_REG_READ((_unit), (_pc), 0x00, 0x00000050, (_val)) 200 #define WRITE_DDR40_PHY_CONTROL_REGS_VDL_DQ_CALIB_STATUSr(_unit, _pc, _val) \ 201 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x00000050, (_val)) 202 #define MODIFY_DDR40_PHY_CONTROL_REGS_VDL_DQ_CALIB_STATUSr(_unit, _pc, _val, _mask) \ 203 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x00000050, (_val), (_mask)) 204 205 /* PHY Write Channel VDL calibration status register */ 206 #define READ_DDR40_PHY_CONTROL_REGS_VDL_WR_CHAN_CALIB_STATUSr(_unit, _pc, _val) \ 207 DDR40_REG_READ((_unit), (_pc), 0x00, 0x00000054, (_val)) 208 #define WRITE_DDR40_PHY_CONTROL_REGS_VDL_WR_CHAN_CALIB_STATUSr(_unit, _pc, _val) \ 209 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x00000054, (_val)) 210 #define MODIFY_DDR40_PHY_CONTROL_REGS_VDL_WR_CHAN_CALIB_STATUSr(_unit, _pc, _val, _mask) \ 211 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x00000054, (_val), (_mask)) 212 213 /* PHY Read Enable VDL calibration status register */ 214 #define READ_DDR40_PHY_CONTROL_REGS_VDL_RD_EN_CALIB_STATUSr(_unit, _pc, _val) \ 215 DDR40_REG_READ((_unit), (_pc), 0x00, 0x00000058, (_val)) 216 #define WRITE_DDR40_PHY_CONTROL_REGS_VDL_RD_EN_CALIB_STATUSr(_unit, _pc, _val) \ 217 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x00000058, (_val)) 218 #define MODIFY_DDR40_PHY_CONTROL_REGS_VDL_RD_EN_CALIB_STATUSr(_unit, _pc, _val, _mask) \ 219 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x00000058, (_val), (_mask)) 220 221 /* Virtual VTT Control and Status register */ 222 #define READ_DDR40_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROLr(_unit, _pc, _val) \ 223 DDR40_REG_READ((_unit), (_pc), 0x00, 0x0000005c, (_val)) 224 #define WRITE_DDR40_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROLr(_unit, _pc, _val) \ 225 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x0000005c, (_val)) 226 #define MODIFY_DDR40_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROLr(_unit, _pc, _val, _mask) \ 227 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000005c, (_val), (_mask)) 228 229 /* Virtual VTT Control and Status register */ 230 #define READ_DDR40_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUSr(_unit, _pc, _val) \ 231 DDR40_REG_READ((_unit), (_pc), 0x00, 0x00000060, (_val)) 232 #define WRITE_DDR40_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUSr(_unit, _pc, _val) \ 233 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x00000060, (_val)) 234 #define MODIFY_DDR40_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUSr(_unit, _pc, _val, _mask) \ 235 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x00000060, (_val), (_mask)) 236 237 /* Virtual VTT Connections register */ 238 #define READ_DDR40_PHY_CONTROL_REGS_VIRTUAL_VTT_CONNECTIONSr(_unit, _pc, _val) \ 239 DDR40_REG_READ((_unit), (_pc), 0x00, 0x00000064, (_val)) 240 #define WRITE_DDR40_PHY_CONTROL_REGS_VIRTUAL_VTT_CONNECTIONSr(_unit, _pc, _val) \ 241 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x00000064, (_val)) 242 #define MODIFY_DDR40_PHY_CONTROL_REGS_VIRTUAL_VTT_CONNECTIONSr(_unit, _pc, _val, _mask) \ 243 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x00000064, (_val), (_mask)) 244 245 /* Virtual VTT Override register */ 246 #define READ_DDR40_PHY_CONTROL_REGS_VIRTUAL_VTT_OVERRIDEr(_unit, _pc, _val) \ 247 DDR40_REG_READ((_unit), (_pc), 0x00, 0x00000068, (_val)) 248 #define WRITE_DDR40_PHY_CONTROL_REGS_VIRTUAL_VTT_OVERRIDEr(_unit, _pc, _val) \ 249 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x00000068, (_val)) 250 #define MODIFY_DDR40_PHY_CONTROL_REGS_VIRTUAL_VTT_OVERRIDEr(_unit, _pc, _val, _mask) \ 251 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x00000068, (_val), (_mask)) 252 253 /* VREF DAC Control register */ 254 #define READ_DDR40_PHY_CONTROL_REGS_VREF_DAC_CONTROLr(_unit, _pc, _val) \ 255 DDR40_REG_READ((_unit), (_pc), 0x00, 0x0000006c, (_val)) 256 #define WRITE_DDR40_PHY_CONTROL_REGS_VREF_DAC_CONTROLr(_unit, _pc, _val) \ 257 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x0000006c, (_val)) 258 #define MODIFY_DDR40_PHY_CONTROL_REGS_VREF_DAC_CONTROLr(_unit, _pc, _val, _mask) \ 259 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000006c, (_val), (_mask)) 260 261 /* PhyBist Control Register */ 262 #define READ_DDR40_PHY_CONTROL_REGS_PHYBIST_CNTRLr(_unit, _pc, _val) \ 263 DDR40_REG_READ((_unit), (_pc), 0x00, 0x00000070, (_val)) 264 #define WRITE_DDR40_PHY_CONTROL_REGS_PHYBIST_CNTRLr(_unit, _pc, _val) \ 265 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x00000070, (_val)) 266 #define MODIFY_DDR40_PHY_CONTROL_REGS_PHYBIST_CNTRLr(_unit, _pc, _val, _mask) \ 267 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x00000070, (_val), (_mask)) 268 269 /* PhyBist Seed Register */ 270 #define READ_DDR40_PHY_CONTROL_REGS_PHYBIST_SEEDr(_unit, _pc, _val) \ 271 DDR40_REG_READ((_unit), (_pc), 0x00, 0x00000074, (_val)) 272 #define WRITE_DDR40_PHY_CONTROL_REGS_PHYBIST_SEEDr(_unit, _pc, _val) \ 273 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x00000074, (_val)) 274 #define MODIFY_DDR40_PHY_CONTROL_REGS_PHYBIST_SEEDr(_unit, _pc, _val, _mask) \ 275 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x00000074, (_val), (_mask)) 276 277 /* PhyBist General Status Register */ 278 #define READ_DDR40_PHY_CONTROL_REGS_PHYBIST_STATUSr(_unit, _pc, _val) \ 279 DDR40_REG_READ((_unit), (_pc), 0x00, 0x00000078, (_val)) 280 #define WRITE_DDR40_PHY_CONTROL_REGS_PHYBIST_STATUSr(_unit, _pc, _val) \ 281 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x00000078, (_val)) 282 #define MODIFY_DDR40_PHY_CONTROL_REGS_PHYBIST_STATUSr(_unit, _pc, _val, _mask) \ 283 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x00000078, (_val), (_mask)) 284 285 /* PhyBist Per-Bit Control Pad Status Register */ 286 #define READ_DDR40_PHY_CONTROL_REGS_PHYBIST_CTL_STATUSr(_unit, _pc, _val) \ 287 DDR40_REG_READ((_unit), (_pc), 0x00, 0x0000007c, (_val)) 288 #define WRITE_DDR40_PHY_CONTROL_REGS_PHYBIST_CTL_STATUSr(_unit, _pc, _val) \ 289 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x0000007c, (_val)) 290 #define MODIFY_DDR40_PHY_CONTROL_REGS_PHYBIST_CTL_STATUSr(_unit, _pc, _val, _mask) \ 291 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000007c, (_val), (_mask)) 292 293 /* PhyBist Per-Bit DQ Pad Status Register */ 294 #define READ_DDR40_PHY_CONTROL_REGS_PHYBIST_DQ_STATUSr(_unit, _pc, _val) \ 295 DDR40_REG_READ((_unit), (_pc), 0x00, 0x00000080, (_val)) 296 #define WRITE_DDR40_PHY_CONTROL_REGS_PHYBIST_DQ_STATUSr(_unit, _pc, _val) \ 297 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x00000080, (_val)) 298 #define MODIFY_DDR40_PHY_CONTROL_REGS_PHYBIST_DQ_STATUSr(_unit, _pc, _val, _mask) \ 299 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x00000080, (_val), (_mask)) 300 301 /* PhyBist Per-Bit DM and CK Pad Status Register */ 302 #define READ_DDR40_PHY_CONTROL_REGS_PHYBIST_MISC_STATUSr(_unit, _pc, _val) \ 303 DDR40_REG_READ((_unit), (_pc), 0x00, 0x00000084, (_val)) 304 #define WRITE_DDR40_PHY_CONTROL_REGS_PHYBIST_MISC_STATUSr(_unit, _pc, _val) \ 305 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x00000084, (_val)) 306 #define MODIFY_DDR40_PHY_CONTROL_REGS_PHYBIST_MISC_STATUSr(_unit, _pc, _val, _mask) \ 307 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x00000084, (_val), (_mask)) 308 309 /* DRAM Command Register */ 310 #define READ_DDR40_PHY_CONTROL_REGS_COMMAND_REGr(_unit, _pc, _val) \ 311 DDR40_REG_READ((_unit), (_pc), 0x00, 0x00000090, (_val)) 312 #define WRITE_DDR40_PHY_CONTROL_REGS_COMMAND_REGr(_unit, _pc, _val) \ 313 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x00000090, (_val)) 314 #define MODIFY_DDR40_PHY_CONTROL_REGS_COMMAND_REGr(_unit, _pc, _val, _mask) \ 315 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x00000090, (_val), (_mask)) 316 317 /* Mode Register 0 */ 318 #define READ_DDR40_PHY_CONTROL_REGS_MODE_REG0r(_unit, _pc, _val) \ 319 DDR40_REG_READ((_unit), (_pc), 0x00, 0x00000094, (_val)) 320 #define WRITE_DDR40_PHY_CONTROL_REGS_MODE_REG0r(_unit, _pc, _val) \ 321 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x00000094, (_val)) 322 #define MODIFY_DDR40_PHY_CONTROL_REGS_MODE_REG0r(_unit, _pc, _val, _mask) \ 323 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x00000094, (_val), (_mask)) 324 325 /* Mode Register 1 */ 326 #define READ_DDR40_PHY_CONTROL_REGS_MODE_REG1r(_unit, _pc, _val) \ 327 DDR40_REG_READ((_unit), (_pc), 0x00, 0x00000098, (_val)) 328 #define WRITE_DDR40_PHY_CONTROL_REGS_MODE_REG1r(_unit, _pc, _val) \ 329 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x00000098, (_val)) 330 #define MODIFY_DDR40_PHY_CONTROL_REGS_MODE_REG1r(_unit, _pc, _val, _mask) \ 331 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x00000098, (_val), (_mask)) 332 333 /* Mode Register 2 */ 334 #define READ_DDR40_PHY_CONTROL_REGS_MODE_REG2r(_unit, _pc, _val) \ 335 DDR40_REG_READ((_unit), (_pc), 0x00, 0x0000009c, (_val)) 336 #define WRITE_DDR40_PHY_CONTROL_REGS_MODE_REG2r(_unit, _pc, _val) \ 337 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x0000009c, (_val)) 338 #define MODIFY_DDR40_PHY_CONTROL_REGS_MODE_REG2r(_unit, _pc, _val, _mask) \ 339 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000009c, (_val), (_mask)) 340 341 /* Mode Register 3 */ 342 #define READ_DDR40_PHY_CONTROL_REGS_MODE_REG3r(_unit, _pc, _val) \ 343 DDR40_REG_READ((_unit), (_pc), 0x00, 0x000000a0, (_val)) 344 #define WRITE_DDR40_PHY_CONTROL_REGS_MODE_REG3r(_unit, _pc, _val) \ 345 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x000000a0, (_val)) 346 #define MODIFY_DDR40_PHY_CONTROL_REGS_MODE_REG3r(_unit, _pc, _val, _mask) \ 347 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x000000a0, (_val), (_mask)) 348 349 /* Standby Control register */ 350 #define READ_DDR40_PHY_CONTROL_REGS_STANDBY_CONTROLr(_unit, _pc, _val) \ 351 DDR40_REG_READ((_unit), (_pc), 0x00, 0x000000a4, (_val)) 352 #define WRITE_DDR40_PHY_CONTROL_REGS_STANDBY_CONTROLr(_unit, _pc, _val) \ 353 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x000000a4, (_val)) 354 #define MODIFY_DDR40_PHY_CONTROL_REGS_STANDBY_CONTROLr(_unit, _pc, _val, _mask) \ 355 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x000000a4, (_val), (_mask)) 356 357 /* Strap Control register */ 358 #define READ_DDR40_PHY_CONTROL_REGS_STRAP_CONTROLr(_unit, _pc, _val) \ 359 DDR40_REG_READ((_unit), (_pc), 0x00, 0x000000b0, (_val)) 360 #define WRITE_DDR40_PHY_CONTROL_REGS_STRAP_CONTROLr(_unit, _pc, _val) \ 361 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x000000b0, (_val)) 362 #define MODIFY_DDR40_PHY_CONTROL_REGS_STRAP_CONTROLr(_unit, _pc, _val, _mask) \ 363 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x000000b0, (_val), (_mask)) 364 365 /* Strap Control register */ 366 #define READ_DDR40_PHY_CONTROL_REGS_STRAP_CONTROL2r(_unit, _pc, _val) \ 367 DDR40_REG_READ((_unit), (_pc), 0x00, 0x000000b4, (_val)) 368 #define WRITE_DDR40_PHY_CONTROL_REGS_STRAP_CONTROL2r(_unit, _pc, _val) \ 369 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x000000b4, (_val)) 370 #define MODIFY_DDR40_PHY_CONTROL_REGS_STRAP_CONTROL2r(_unit, _pc, _val, _mask) \ 371 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x000000b4, (_val), (_mask)) 372 373 /* Strap Status register */ 374 #define READ_DDR40_PHY_CONTROL_REGS_STRAP_STATUSr(_unit, _pc, _val) \ 375 DDR40_REG_READ((_unit), (_pc), 0x00, 0x000000b8, (_val)) 376 #define WRITE_DDR40_PHY_CONTROL_REGS_STRAP_STATUSr(_unit, _pc, _val) \ 377 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x000000b8, (_val)) 378 #define MODIFY_DDR40_PHY_CONTROL_REGS_STRAP_STATUSr(_unit, _pc, _val, _mask) \ 379 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x000000b8, (_val), (_mask)) 380 381 /* Strap Status register */ 382 #define READ_DDR40_PHY_CONTROL_REGS_STRAP_STATUS2r(_unit, _pc, _val) \ 383 DDR40_REG_READ((_unit), (_pc), 0x00, 0x000000bc, (_val)) 384 #define WRITE_DDR40_PHY_CONTROL_REGS_STRAP_STATUS2r(_unit, _pc, _val) \ 385 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x000000bc, (_val)) 386 #define MODIFY_DDR40_PHY_CONTROL_REGS_STRAP_STATUS2r(_unit, _pc, _val, _mask) \ 387 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x000000bc, (_val), (_mask)) 388 389 /* Freeze-on-error enable register */ 390 #define READ_DDR40_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLEr(_unit, _pc, _val) \ 391 DDR40_REG_READ((_unit), (_pc), 0x00, 0x000000c0, (_val)) 392 #define WRITE_DDR40_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLEr(_unit, _pc, _val) \ 393 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x000000c0, (_val)) 394 #define MODIFY_DDR40_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLEr(_unit, _pc, _val, _mask) \ 395 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x000000c0, (_val), (_mask)) 396 397 /* Datapth Loopback control register */ 398 #define READ_DDR40_PHY_CONTROL_REGS_DATAPATH_LOOPBACKr(_unit, _pc, _val) \ 399 DDR40_REG_READ((_unit), (_pc), 0x00, 0x000000c4, (_val)) 400 #define WRITE_DDR40_PHY_CONTROL_REGS_DATAPATH_LOOPBACKr(_unit, _pc, _val) \ 401 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x000000c4, (_val)) 402 #define MODIFY_DDR40_PHY_CONTROL_REGS_DATAPATH_LOOPBACKr(_unit, _pc, _val, _mask) \ 403 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x000000c4, (_val), (_mask)) 404 405 406 /**************************************************************************** 407 * DDR40_PHY_DDR40_PHY_WORD_LANE_0 408 */ 409 410 /* Read Enable Byte VDL static override control register */ 411 #define READ_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE_RD_ENr(_unit, _pc, _val) \ 412 DDR40_REG_READ((_unit), (_pc), 0x00, 0x00000200, (_val)) 413 #define WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE_RD_ENr(_unit, _pc, _val) \ 414 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x00000200, (_val)) 415 #define MODIFY_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE_RD_ENr(_unit, _pc, _val, _mask) \ 416 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x00000200, (_val), (_mask)) 417 418 /* Write Byte VDL static override control register */ 419 #define READ_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_Wr(_unit, _pc, _val) \ 420 DDR40_REG_READ((_unit), (_pc), 0x00, 0x00000204, (_val)) 421 #define WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_Wr(_unit, _pc, _val) \ 422 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x00000204, (_val)) 423 #define MODIFY_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_Wr(_unit, _pc, _val, _mask) \ 424 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x00000204, (_val), (_mask)) 425 426 /* Read Byte DQSP VDL static override control register */ 427 #define READ_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_Pr(_unit, _pc, _val) \ 428 DDR40_REG_READ((_unit), (_pc), 0x00, 0x00000208, (_val)) 429 #define WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_Pr(_unit, _pc, _val) \ 430 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x00000208, (_val)) 431 #define MODIFY_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_Pr(_unit, _pc, _val, _mask) \ 432 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x00000208, (_val), (_mask)) 433 434 /* Read Byte DQSN VDL static override control register */ 435 #define READ_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_Nr(_unit, _pc, _val) \ 436 DDR40_REG_READ((_unit), (_pc), 0x00, 0x0000020c, (_val)) 437 #define WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_Nr(_unit, _pc, _val) \ 438 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x0000020c, (_val)) 439 #define MODIFY_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_Nr(_unit, _pc, _val, _mask) \ 440 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000020c, (_val), (_mask)) 441 442 /* Write Bit VDL static override control register */ 443 #define READ_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_Wr(_unit, _pc, _val) \ 444 DDR40_REG_READ((_unit), (_pc), 0x00, 0x00000210, (_val)) 445 #define WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_Wr(_unit, _pc, _val) \ 446 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x00000210, (_val)) 447 #define MODIFY_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_Wr(_unit, _pc, _val, _mask) \ 448 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x00000210, (_val), (_mask)) 449 450 /* Write Bit VDL static override control register */ 451 #define READ_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_Wr(_unit, _pc, _val) \ 452 DDR40_REG_READ((_unit), (_pc), 0x00, 0x00000214, (_val)) 453 #define WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_Wr(_unit, _pc, _val) \ 454 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x00000214, (_val)) 455 #define MODIFY_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_Wr(_unit, _pc, _val, _mask) \ 456 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x00000214, (_val), (_mask)) 457 458 /* Write Bit VDL static override control register */ 459 #define READ_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_Wr(_unit, _pc, _val) \ 460 DDR40_REG_READ((_unit), (_pc), 0x00, 0x00000218, (_val)) 461 #define WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_Wr(_unit, _pc, _val) \ 462 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x00000218, (_val)) 463 #define MODIFY_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_Wr(_unit, _pc, _val, _mask) \ 464 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x00000218, (_val), (_mask)) 465 466 /* Write Bit VDL static override control register */ 467 #define READ_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_Wr(_unit, _pc, _val) \ 468 DDR40_REG_READ((_unit), (_pc), 0x00, 0x0000021c, (_val)) 469 #define WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_Wr(_unit, _pc, _val) \ 470 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x0000021c, (_val)) 471 #define MODIFY_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_Wr(_unit, _pc, _val, _mask) \ 472 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000021c, (_val), (_mask)) 473 474 /* Write Bit VDL static override control register */ 475 #define READ_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_Wr(_unit, _pc, _val) \ 476 DDR40_REG_READ((_unit), (_pc), 0x00, 0x00000220, (_val)) 477 #define WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_Wr(_unit, _pc, _val) \ 478 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x00000220, (_val)) 479 #define MODIFY_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_Wr(_unit, _pc, _val, _mask) \ 480 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x00000220, (_val), (_mask)) 481 482 /* Write Bit VDL static override control register */ 483 #define READ_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_Wr(_unit, _pc, _val) \ 484 DDR40_REG_READ((_unit), (_pc), 0x00, 0x00000224, (_val)) 485 #define WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_Wr(_unit, _pc, _val) \ 486 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x00000224, (_val)) 487 #define MODIFY_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_Wr(_unit, _pc, _val, _mask) \ 488 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x00000224, (_val), (_mask)) 489 490 /* Write Bit VDL static override control register */ 491 #define READ_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_Wr(_unit, _pc, _val) \ 492 DDR40_REG_READ((_unit), (_pc), 0x00, 0x00000228, (_val)) 493 #define WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_Wr(_unit, _pc, _val) \ 494 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x00000228, (_val)) 495 #define MODIFY_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_Wr(_unit, _pc, _val, _mask) \ 496 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x00000228, (_val), (_mask)) 497 498 /* Write Bit VDL static override control register */ 499 #define READ_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_Wr(_unit, _pc, _val) \ 500 DDR40_REG_READ((_unit), (_pc), 0x00, 0x0000022c, (_val)) 501 #define WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_Wr(_unit, _pc, _val) \ 502 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x0000022c, (_val)) 503 #define MODIFY_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_Wr(_unit, _pc, _val, _mask) \ 504 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000022c, (_val), (_mask)) 505 506 /* Write Bit VDL static override control register */ 507 #define READ_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_DM_Wr(_unit, _pc, _val) \ 508 DDR40_REG_READ((_unit), (_pc), 0x00, 0x00000230, (_val)) 509 #define WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_DM_Wr(_unit, _pc, _val) \ 510 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x00000230, (_val)) 511 #define MODIFY_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_DM_Wr(_unit, _pc, _val, _mask) \ 512 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x00000230, (_val), (_mask)) 513 514 /* Read DQSP Bit VDL static override control register */ 515 #define READ_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_Pr(_unit, _pc, _val) \ 516 DDR40_REG_READ((_unit), (_pc), 0x00, 0x00000234, (_val)) 517 #define WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_Pr(_unit, _pc, _val) \ 518 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x00000234, (_val)) 519 #define MODIFY_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_Pr(_unit, _pc, _val, _mask) \ 520 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x00000234, (_val), (_mask)) 521 522 /* Read DQSN Bit VDL static override control register */ 523 #define READ_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_Nr(_unit, _pc, _val) \ 524 DDR40_REG_READ((_unit), (_pc), 0x00, 0x00000238, (_val)) 525 #define WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_Nr(_unit, _pc, _val) \ 526 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x00000238, (_val)) 527 #define MODIFY_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_Nr(_unit, _pc, _val, _mask) \ 528 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x00000238, (_val), (_mask)) 529 530 /* Read DQSP Bit VDL static override control register */ 531 #define READ_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_Pr(_unit, _pc, _val) \ 532 DDR40_REG_READ((_unit), (_pc), 0x00, 0x0000023c, (_val)) 533 #define WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_Pr(_unit, _pc, _val) \ 534 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x0000023c, (_val)) 535 #define MODIFY_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_Pr(_unit, _pc, _val, _mask) \ 536 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000023c, (_val), (_mask)) 537 538 /* Read DQSN Bit VDL static override control register */ 539 #define READ_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_Nr(_unit, _pc, _val) \ 540 DDR40_REG_READ((_unit), (_pc), 0x00, 0x00000240, (_val)) 541 #define WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_Nr(_unit, _pc, _val) \ 542 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x00000240, (_val)) 543 #define MODIFY_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_Nr(_unit, _pc, _val, _mask) \ 544 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x00000240, (_val), (_mask)) 545 546 /* Read DQSP Bit VDL static override control register */ 547 #define READ_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_Pr(_unit, _pc, _val) \ 548 DDR40_REG_READ((_unit), (_pc), 0x00, 0x00000244, (_val)) 549 #define WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_Pr(_unit, _pc, _val) \ 550 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x00000244, (_val)) 551 #define MODIFY_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_Pr(_unit, _pc, _val, _mask) \ 552 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x00000244, (_val), (_mask)) 553 554 /* Read DQSN Bit VDL static override control register */ 555 #define READ_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_Nr(_unit, _pc, _val) \ 556 DDR40_REG_READ((_unit), (_pc), 0x00, 0x00000248, (_val)) 557 #define WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_Nr(_unit, _pc, _val) \ 558 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x00000248, (_val)) 559 #define MODIFY_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_Nr(_unit, _pc, _val, _mask) \ 560 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x00000248, (_val), (_mask)) 561 562 /* Read DQSP Bit VDL static override control register */ 563 #define READ_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_Pr(_unit, _pc, _val) \ 564 DDR40_REG_READ((_unit), (_pc), 0x00, 0x0000024c, (_val)) 565 #define WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_Pr(_unit, _pc, _val) \ 566 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x0000024c, (_val)) 567 #define MODIFY_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_Pr(_unit, _pc, _val, _mask) \ 568 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000024c, (_val), (_mask)) 569 570 /* Read DQSN Bit VDL static override control register */ 571 #define READ_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_Nr(_unit, _pc, _val) \ 572 DDR40_REG_READ((_unit), (_pc), 0x00, 0x00000250, (_val)) 573 #define WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_Nr(_unit, _pc, _val) \ 574 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x00000250, (_val)) 575 #define MODIFY_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_Nr(_unit, _pc, _val, _mask) \ 576 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x00000250, (_val), (_mask)) 577 578 /* Read DQSP Bit VDL static override control register */ 579 #define READ_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_Pr(_unit, _pc, _val) \ 580 DDR40_REG_READ((_unit), (_pc), 0x00, 0x00000254, (_val)) 581 #define WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_Pr(_unit, _pc, _val) \ 582 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x00000254, (_val)) 583 #define MODIFY_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_Pr(_unit, _pc, _val, _mask) \ 584 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x00000254, (_val), (_mask)) 585 586 /* Read DQSN Bit VDL static override control register */ 587 #define READ_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_Nr(_unit, _pc, _val) \ 588 DDR40_REG_READ((_unit), (_pc), 0x00, 0x00000258, (_val)) 589 #define WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_Nr(_unit, _pc, _val) \ 590 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x00000258, (_val)) 591 #define MODIFY_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_Nr(_unit, _pc, _val, _mask) \ 592 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x00000258, (_val), (_mask)) 593 594 /* Read DQSP Bit VDL static override control register */ 595 #define READ_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_Pr(_unit, _pc, _val) \ 596 DDR40_REG_READ((_unit), (_pc), 0x00, 0x0000025c, (_val)) 597 #define WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_Pr(_unit, _pc, _val) \ 598 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x0000025c, (_val)) 599 #define MODIFY_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_Pr(_unit, _pc, _val, _mask) \ 600 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000025c, (_val), (_mask)) 601 602 /* Read DQSN Bit VDL static override control register */ 603 #define READ_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_Nr(_unit, _pc, _val) \ 604 DDR40_REG_READ((_unit), (_pc), 0x00, 0x00000260, (_val)) 605 #define WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_Nr(_unit, _pc, _val) \ 606 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x00000260, (_val)) 607 #define MODIFY_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_Nr(_unit, _pc, _val, _mask) \ 608 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x00000260, (_val), (_mask)) 609 610 /* Read DQSP Bit VDL static override control register */ 611 #define READ_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_Pr(_unit, _pc, _val) \ 612 DDR40_REG_READ((_unit), (_pc), 0x00, 0x00000264, (_val)) 613 #define WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_Pr(_unit, _pc, _val) \ 614 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x00000264, (_val)) 615 #define MODIFY_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_Pr(_unit, _pc, _val, _mask) \ 616 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x00000264, (_val), (_mask)) 617 618 /* Read DQSN Bit VDL static override control register */ 619 #define READ_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_Nr(_unit, _pc, _val) \ 620 DDR40_REG_READ((_unit), (_pc), 0x00, 0x00000268, (_val)) 621 #define WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_Nr(_unit, _pc, _val) \ 622 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x00000268, (_val)) 623 #define MODIFY_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_Nr(_unit, _pc, _val, _mask) \ 624 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x00000268, (_val), (_mask)) 625 626 /* Read DQSP Bit VDL static override control register */ 627 #define READ_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_Pr(_unit, _pc, _val) \ 628 DDR40_REG_READ((_unit), (_pc), 0x00, 0x0000026c, (_val)) 629 #define WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_Pr(_unit, _pc, _val) \ 630 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x0000026c, (_val)) 631 #define MODIFY_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_Pr(_unit, _pc, _val, _mask) \ 632 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000026c, (_val), (_mask)) 633 634 /* Read DQSN Bit VDL static override control register */ 635 #define READ_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_Nr(_unit, _pc, _val) \ 636 DDR40_REG_READ((_unit), (_pc), 0x00, 0x00000270, (_val)) 637 #define WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_Nr(_unit, _pc, _val) \ 638 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x00000270, (_val)) 639 #define MODIFY_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_Nr(_unit, _pc, _val, _mask) \ 640 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x00000270, (_val), (_mask)) 641 642 /* Read Enable Bit VDL static override control register */ 643 #define READ_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT_RD_ENr(_unit, _pc, _val) \ 644 DDR40_REG_READ((_unit), (_pc), 0x00, 0x00000274, (_val)) 645 #define WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT_RD_ENr(_unit, _pc, _val) \ 646 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x00000274, (_val)) 647 #define MODIFY_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT_RD_ENr(_unit, _pc, _val, _mask) \ 648 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x00000274, (_val), (_mask)) 649 650 /* Write Byte VDL static override control register */ 651 #define READ_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_Wr(_unit, _pc, _val) \ 652 DDR40_REG_READ((_unit), (_pc), 0x00, 0x000002a4, (_val)) 653 #define WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_Wr(_unit, _pc, _val) \ 654 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x000002a4, (_val)) 655 #define MODIFY_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_Wr(_unit, _pc, _val, _mask) \ 656 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x000002a4, (_val), (_mask)) 657 658 /* Read Byte DQSP VDL static override control register */ 659 #define READ_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_Pr(_unit, _pc, _val) \ 660 DDR40_REG_READ((_unit), (_pc), 0x00, 0x000002a8, (_val)) 661 #define WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_Pr(_unit, _pc, _val) \ 662 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x000002a8, (_val)) 663 #define MODIFY_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_Pr(_unit, _pc, _val, _mask) \ 664 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x000002a8, (_val), (_mask)) 665 666 /* Read Byte DQSN VDL static override control register */ 667 #define READ_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_Nr(_unit, _pc, _val) \ 668 DDR40_REG_READ((_unit), (_pc), 0x00, 0x000002ac, (_val)) 669 #define WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_Nr(_unit, _pc, _val) \ 670 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x000002ac, (_val)) 671 #define MODIFY_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_Nr(_unit, _pc, _val, _mask) \ 672 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x000002ac, (_val), (_mask)) 673 674 /* Write Bit VDL static override control register */ 675 #define READ_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_Wr(_unit, _pc, _val) \ 676 DDR40_REG_READ((_unit), (_pc), 0x00, 0x000002b0, (_val)) 677 #define WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_Wr(_unit, _pc, _val) \ 678 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x000002b0, (_val)) 679 #define MODIFY_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_Wr(_unit, _pc, _val, _mask) \ 680 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x000002b0, (_val), (_mask)) 681 682 /* Write Bit VDL static override control register */ 683 #define READ_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_Wr(_unit, _pc, _val) \ 684 DDR40_REG_READ((_unit), (_pc), 0x00, 0x000002b4, (_val)) 685 #define WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_Wr(_unit, _pc, _val) \ 686 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x000002b4, (_val)) 687 #define MODIFY_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_Wr(_unit, _pc, _val, _mask) \ 688 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x000002b4, (_val), (_mask)) 689 690 /* Write Bit VDL static override control register */ 691 #define READ_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_Wr(_unit, _pc, _val) \ 692 DDR40_REG_READ((_unit), (_pc), 0x00, 0x000002b8, (_val)) 693 #define WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_Wr(_unit, _pc, _val) \ 694 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x000002b8, (_val)) 695 #define MODIFY_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_Wr(_unit, _pc, _val, _mask) \ 696 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x000002b8, (_val), (_mask)) 697 698 /* Write Bit VDL static override control register */ 699 #define READ_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_Wr(_unit, _pc, _val) \ 700 DDR40_REG_READ((_unit), (_pc), 0x00, 0x000002bc, (_val)) 701 #define WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_Wr(_unit, _pc, _val) \ 702 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x000002bc, (_val)) 703 #define MODIFY_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_Wr(_unit, _pc, _val, _mask) \ 704 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x000002bc, (_val), (_mask)) 705 706 /* Write Bit VDL static override control register */ 707 #define READ_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_Wr(_unit, _pc, _val) \ 708 DDR40_REG_READ((_unit), (_pc), 0x00, 0x000002c0, (_val)) 709 #define WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_Wr(_unit, _pc, _val) \ 710 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x000002c0, (_val)) 711 #define MODIFY_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_Wr(_unit, _pc, _val, _mask) \ 712 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x000002c0, (_val), (_mask)) 713 714 /* Write Bit VDL static override control register */ 715 #define READ_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_Wr(_unit, _pc, _val) \ 716 DDR40_REG_READ((_unit), (_pc), 0x00, 0x000002c4, (_val)) 717 #define WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_Wr(_unit, _pc, _val) \ 718 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x000002c4, (_val)) 719 #define MODIFY_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_Wr(_unit, _pc, _val, _mask) \ 720 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x000002c4, (_val), (_mask)) 721 722 /* Write Bit VDL static override control register */ 723 #define READ_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_Wr(_unit, _pc, _val) \ 724 DDR40_REG_READ((_unit), (_pc), 0x00, 0x000002c8, (_val)) 725 #define WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_Wr(_unit, _pc, _val) \ 726 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x000002c8, (_val)) 727 #define MODIFY_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_Wr(_unit, _pc, _val, _mask) \ 728 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x000002c8, (_val), (_mask)) 729 730 /* Write Bit VDL static override control register */ 731 #define READ_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_Wr(_unit, _pc, _val) \ 732 DDR40_REG_READ((_unit), (_pc), 0x00, 0x000002cc, (_val)) 733 #define WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_Wr(_unit, _pc, _val) \ 734 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x000002cc, (_val)) 735 #define MODIFY_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_Wr(_unit, _pc, _val, _mask) \ 736 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x000002cc, (_val), (_mask)) 737 738 /* Write Bit VDL static override control register */ 739 #define READ_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_DM_Wr(_unit, _pc, _val) \ 740 DDR40_REG_READ((_unit), (_pc), 0x00, 0x000002d0, (_val)) 741 #define WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_DM_Wr(_unit, _pc, _val) \ 742 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x000002d0, (_val)) 743 #define MODIFY_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_DM_Wr(_unit, _pc, _val, _mask) \ 744 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x000002d0, (_val), (_mask)) 745 746 /* Read DQSP Bit VDL static override control register */ 747 #define READ_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_Pr(_unit, _pc, _val) \ 748 DDR40_REG_READ((_unit), (_pc), 0x00, 0x000002d4, (_val)) 749 #define WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_Pr(_unit, _pc, _val) \ 750 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x000002d4, (_val)) 751 #define MODIFY_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_Pr(_unit, _pc, _val, _mask) \ 752 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x000002d4, (_val), (_mask)) 753 754 /* Read DQSN Bit VDL static override control register */ 755 #define READ_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_Nr(_unit, _pc, _val) \ 756 DDR40_REG_READ((_unit), (_pc), 0x00, 0x000002d8, (_val)) 757 #define WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_Nr(_unit, _pc, _val) \ 758 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x000002d8, (_val)) 759 #define MODIFY_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_Nr(_unit, _pc, _val, _mask) \ 760 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x000002d8, (_val), (_mask)) 761 762 /* Read DQSP Bit VDL static override control register */ 763 #define READ_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_Pr(_unit, _pc, _val) \ 764 DDR40_REG_READ((_unit), (_pc), 0x00, 0x000002dc, (_val)) 765 #define WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_Pr(_unit, _pc, _val) \ 766 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x000002dc, (_val)) 767 #define MODIFY_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_Pr(_unit, _pc, _val, _mask) \ 768 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x000002dc, (_val), (_mask)) 769 770 /* Read DQSN Bit VDL static override control register */ 771 #define READ_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_Nr(_unit, _pc, _val) \ 772 DDR40_REG_READ((_unit), (_pc), 0x00, 0x000002e0, (_val)) 773 #define WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_Nr(_unit, _pc, _val) \ 774 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x000002e0, (_val)) 775 #define MODIFY_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_Nr(_unit, _pc, _val, _mask) \ 776 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x000002e0, (_val), (_mask)) 777 778 /* Read DQSP Bit VDL static override control register */ 779 #define READ_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_Pr(_unit, _pc, _val) \ 780 DDR40_REG_READ((_unit), (_pc), 0x00, 0x000002e4, (_val)) 781 #define WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_Pr(_unit, _pc, _val) \ 782 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x000002e4, (_val)) 783 #define MODIFY_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_Pr(_unit, _pc, _val, _mask) \ 784 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x000002e4, (_val), (_mask)) 785 786 /* Read DQSN Bit VDL static override control register */ 787 #define READ_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_Nr(_unit, _pc, _val) \ 788 DDR40_REG_READ((_unit), (_pc), 0x00, 0x000002e8, (_val)) 789 #define WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_Nr(_unit, _pc, _val) \ 790 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x000002e8, (_val)) 791 #define MODIFY_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_Nr(_unit, _pc, _val, _mask) \ 792 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x000002e8, (_val), (_mask)) 793 794 /* Read DQSP Bit VDL static override control register */ 795 #define READ_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_Pr(_unit, _pc, _val) \ 796 DDR40_REG_READ((_unit), (_pc), 0x00, 0x000002ec, (_val)) 797 #define WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_Pr(_unit, _pc, _val) \ 798 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x000002ec, (_val)) 799 #define MODIFY_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_Pr(_unit, _pc, _val, _mask) \ 800 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x000002ec, (_val), (_mask)) 801 802 /* Read DQSN Bit VDL static override control register */ 803 #define READ_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_Nr(_unit, _pc, _val) \ 804 DDR40_REG_READ((_unit), (_pc), 0x00, 0x000002f0, (_val)) 805 #define WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_Nr(_unit, _pc, _val) \ 806 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x000002f0, (_val)) 807 #define MODIFY_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_Nr(_unit, _pc, _val, _mask) \ 808 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x000002f0, (_val), (_mask)) 809 810 /* Read DQSP Bit VDL static override control register */ 811 #define READ_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_Pr(_unit, _pc, _val) \ 812 DDR40_REG_READ((_unit), (_pc), 0x00, 0x000002f4, (_val)) 813 #define WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_Pr(_unit, _pc, _val) \ 814 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x000002f4, (_val)) 815 #define MODIFY_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_Pr(_unit, _pc, _val, _mask) \ 816 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x000002f4, (_val), (_mask)) 817 818 /* Read DQSN Bit VDL static override control register */ 819 #define READ_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_Nr(_unit, _pc, _val) \ 820 DDR40_REG_READ((_unit), (_pc), 0x00, 0x000002f8, (_val)) 821 #define WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_Nr(_unit, _pc, _val) \ 822 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x000002f8, (_val)) 823 #define MODIFY_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_Nr(_unit, _pc, _val, _mask) \ 824 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x000002f8, (_val), (_mask)) 825 826 /* Read DQSP Bit VDL static override control register */ 827 #define READ_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_Pr(_unit, _pc, _val) \ 828 DDR40_REG_READ((_unit), (_pc), 0x00, 0x000002fc, (_val)) 829 #define WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_Pr(_unit, _pc, _val) \ 830 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x000002fc, (_val)) 831 #define MODIFY_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_Pr(_unit, _pc, _val, _mask) \ 832 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x000002fc, (_val), (_mask)) 833 834 /* Read DQSN Bit VDL static override control register */ 835 #define READ_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_Nr(_unit, _pc, _val) \ 836 DDR40_REG_READ((_unit), (_pc), 0x00, 0x00000300, (_val)) 837 #define WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_Nr(_unit, _pc, _val) \ 838 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x00000300, (_val)) 839 #define MODIFY_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_Nr(_unit, _pc, _val, _mask) \ 840 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x00000300, (_val), (_mask)) 841 842 /* Read DQSP Bit VDL static override control register */ 843 #define READ_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_Pr(_unit, _pc, _val) \ 844 DDR40_REG_READ((_unit), (_pc), 0x00, 0x00000304, (_val)) 845 #define WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_Pr(_unit, _pc, _val) \ 846 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x00000304, (_val)) 847 #define MODIFY_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_Pr(_unit, _pc, _val, _mask) \ 848 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x00000304, (_val), (_mask)) 849 850 /* Read DQSN Bit VDL static override control register */ 851 #define READ_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_Nr(_unit, _pc, _val) \ 852 DDR40_REG_READ((_unit), (_pc), 0x00, 0x00000308, (_val)) 853 #define WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_Nr(_unit, _pc, _val) \ 854 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x00000308, (_val)) 855 #define MODIFY_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_Nr(_unit, _pc, _val, _mask) \ 856 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x00000308, (_val), (_mask)) 857 858 /* Read DQSP Bit VDL static override control register */ 859 #define READ_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_Pr(_unit, _pc, _val) \ 860 DDR40_REG_READ((_unit), (_pc), 0x00, 0x0000030c, (_val)) 861 #define WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_Pr(_unit, _pc, _val) \ 862 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x0000030c, (_val)) 863 #define MODIFY_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_Pr(_unit, _pc, _val, _mask) \ 864 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000030c, (_val), (_mask)) 865 866 /* Read DQSN Bit VDL static override control register */ 867 #define READ_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_Nr(_unit, _pc, _val) \ 868 DDR40_REG_READ((_unit), (_pc), 0x00, 0x00000310, (_val)) 869 #define WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_Nr(_unit, _pc, _val) \ 870 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x00000310, (_val)) 871 #define MODIFY_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_Nr(_unit, _pc, _val, _mask) \ 872 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x00000310, (_val), (_mask)) 873 874 /* Read Enable Bit VDL static override control register */ 875 #define READ_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT_RD_ENr(_unit, _pc, _val) \ 876 DDR40_REG_READ((_unit), (_pc), 0x00, 0x00000314, (_val)) 877 #define WRITE_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT_RD_ENr(_unit, _pc, _val) \ 878 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x00000314, (_val)) 879 #define MODIFY_DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT_RD_ENr(_unit, _pc, _val, _mask) \ 880 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x00000314, (_val), (_mask)) 881 882 /* Read DQSP VDL dynamic override control register */ 883 #define READ_DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_R_Pr(_unit, _pc, _val) \ 884 DDR40_REG_READ((_unit), (_pc), 0x00, 0x00000328, (_val)) 885 #define WRITE_DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_R_Pr(_unit, _pc, _val) \ 886 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x00000328, (_val)) 887 #define MODIFY_DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_R_Pr(_unit, _pc, _val, _mask) \ 888 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x00000328, (_val), (_mask)) 889 890 /* Read DQSN VDL dynamic override control register */ 891 #define READ_DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_R_Nr(_unit, _pc, _val) \ 892 DDR40_REG_READ((_unit), (_pc), 0x00, 0x0000032c, (_val)) 893 #define WRITE_DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_R_Nr(_unit, _pc, _val) \ 894 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x0000032c, (_val)) 895 #define MODIFY_DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_R_Nr(_unit, _pc, _val, _mask) \ 896 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000032c, (_val), (_mask)) 897 898 /* Read DQ-P VDL dynamic override control register */ 899 #define READ_DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_Pr(_unit, _pc, _val) \ 900 DDR40_REG_READ((_unit), (_pc), 0x00, 0x00000330, (_val)) 901 #define WRITE_DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_Pr(_unit, _pc, _val) \ 902 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x00000330, (_val)) 903 #define MODIFY_DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_Pr(_unit, _pc, _val, _mask) \ 904 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x00000330, (_val), (_mask)) 905 906 /* Read DQ-N VDL dynamic override control register */ 907 #define READ_DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_Nr(_unit, _pc, _val) \ 908 DDR40_REG_READ((_unit), (_pc), 0x00, 0x00000334, (_val)) 909 #define WRITE_DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_Nr(_unit, _pc, _val) \ 910 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x00000334, (_val)) 911 #define MODIFY_DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_Nr(_unit, _pc, _val, _mask) \ 912 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x00000334, (_val), (_mask)) 913 914 /* Write DQ Byte VDL dynamic override control register */ 915 #define READ_DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_Wr(_unit, _pc, _val) \ 916 DDR40_REG_READ((_unit), (_pc), 0x00, 0x00000338, (_val)) 917 #define WRITE_DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_Wr(_unit, _pc, _val) \ 918 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x00000338, (_val)) 919 #define MODIFY_DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_Wr(_unit, _pc, _val, _mask) \ 920 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x00000338, (_val), (_mask)) 921 922 /* Write DQ Bit VDL dynamic override control register */ 923 #define READ_DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_Wr(_unit, _pc, _val) \ 924 DDR40_REG_READ((_unit), (_pc), 0x00, 0x0000033c, (_val)) 925 #define WRITE_DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_Wr(_unit, _pc, _val) \ 926 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x0000033c, (_val)) 927 #define MODIFY_DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_Wr(_unit, _pc, _val, _mask) \ 928 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000033c, (_val), (_mask)) 929 930 /* Read DQSP VDL dynamic override control register */ 931 #define READ_DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_R_Pr(_unit, _pc, _val) \ 932 DDR40_REG_READ((_unit), (_pc), 0x00, 0x00000348, (_val)) 933 #define WRITE_DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_R_Pr(_unit, _pc, _val) \ 934 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x00000348, (_val)) 935 #define MODIFY_DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_R_Pr(_unit, _pc, _val, _mask) \ 936 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x00000348, (_val), (_mask)) 937 938 /* Read DQSN VDL dynamic override control register */ 939 #define READ_DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_R_Nr(_unit, _pc, _val) \ 940 DDR40_REG_READ((_unit), (_pc), 0x00, 0x0000034c, (_val)) 941 #define WRITE_DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_R_Nr(_unit, _pc, _val) \ 942 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x0000034c, (_val)) 943 #define MODIFY_DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_R_Nr(_unit, _pc, _val, _mask) \ 944 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000034c, (_val), (_mask)) 945 946 /* Read DQ-P VDL dynamic override control register */ 947 #define READ_DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_Pr(_unit, _pc, _val) \ 948 DDR40_REG_READ((_unit), (_pc), 0x00, 0x00000350, (_val)) 949 #define WRITE_DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_Pr(_unit, _pc, _val) \ 950 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x00000350, (_val)) 951 #define MODIFY_DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_Pr(_unit, _pc, _val, _mask) \ 952 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x00000350, (_val), (_mask)) 953 954 /* Read DQ-N VDL dynamic override control register */ 955 #define READ_DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_Nr(_unit, _pc, _val) \ 956 DDR40_REG_READ((_unit), (_pc), 0x00, 0x00000354, (_val)) 957 #define WRITE_DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_Nr(_unit, _pc, _val) \ 958 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x00000354, (_val)) 959 #define MODIFY_DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_Nr(_unit, _pc, _val, _mask) \ 960 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x00000354, (_val), (_mask)) 961 962 /* Write DQ Byte VDL dynamic override control register */ 963 #define READ_DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_Wr(_unit, _pc, _val) \ 964 DDR40_REG_READ((_unit), (_pc), 0x00, 0x00000358, (_val)) 965 #define WRITE_DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_Wr(_unit, _pc, _val) \ 966 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x00000358, (_val)) 967 #define MODIFY_DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_Wr(_unit, _pc, _val, _mask) \ 968 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x00000358, (_val), (_mask)) 969 970 /* Write DQ Bit VDL dynamic override control register */ 971 #define READ_DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_Wr(_unit, _pc, _val) \ 972 DDR40_REG_READ((_unit), (_pc), 0x00, 0x0000035c, (_val)) 973 #define WRITE_DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_Wr(_unit, _pc, _val) \ 974 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x0000035c, (_val)) 975 #define MODIFY_DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_Wr(_unit, _pc, _val, _mask) \ 976 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000035c, (_val), (_mask)) 977 978 /* Word Lane read channel control register */ 979 #define READ_DDR40_PHY_WORD_LANE_0_READ_DATA_DLYr(_unit, _pc, _val) \ 980 DDR40_REG_READ((_unit), (_pc), 0x00, 0x00000360, (_val)) 981 #define WRITE_DDR40_PHY_WORD_LANE_0_READ_DATA_DLYr(_unit, _pc, _val) \ 982 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x00000360, (_val)) 983 #define MODIFY_DDR40_PHY_WORD_LANE_0_READ_DATA_DLYr(_unit, _pc, _val, _mask) \ 984 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x00000360, (_val), (_mask)) 985 986 /* Word Lane read channel control register */ 987 #define READ_DDR40_PHY_WORD_LANE_0_READ_CONTROLr(_unit, _pc, _val) \ 988 DDR40_REG_READ((_unit), (_pc), 0x00, 0x00000364, (_val)) 989 #define WRITE_DDR40_PHY_WORD_LANE_0_READ_CONTROLr(_unit, _pc, _val) \ 990 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x00000364, (_val)) 991 #define MODIFY_DDR40_PHY_WORD_LANE_0_READ_CONTROLr(_unit, _pc, _val, _mask) \ 992 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x00000364, (_val), (_mask)) 993 994 /* Read fifo data register, first data */ 995 #define READ_DDR40_PHY_WORD_LANE_0_READ_FIFO_DATA_BL0_0r(_unit, _pc, _val) \ 996 DDR40_REG_READ((_unit), (_pc), 0x00, 0x00000370, (_val)) 997 #define WRITE_DDR40_PHY_WORD_LANE_0_READ_FIFO_DATA_BL0_0r(_unit, _pc, _val) \ 998 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x00000370, (_val)) 999 #define MODIFY_DDR40_PHY_WORD_LANE_0_READ_FIFO_DATA_BL0_0r(_unit, _pc, _val, _mask) \ 1000 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x00000370, (_val), (_mask)) 1001 1002 /* Read fifo data register, second data */ 1003 #define READ_DDR40_PHY_WORD_LANE_0_READ_FIFO_DATA_BL0_1r(_unit, _pc, _val) \ 1004 DDR40_REG_READ((_unit), (_pc), 0x00, 0x00000374, (_val)) 1005 #define WRITE_DDR40_PHY_WORD_LANE_0_READ_FIFO_DATA_BL0_1r(_unit, _pc, _val) \ 1006 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x00000374, (_val)) 1007 #define MODIFY_DDR40_PHY_WORD_LANE_0_READ_FIFO_DATA_BL0_1r(_unit, _pc, _val, _mask) \ 1008 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x00000374, (_val), (_mask)) 1009 1010 /* Read fifo data register, third data */ 1011 #define READ_DDR40_PHY_WORD_LANE_0_READ_FIFO_DATA_BL0_2r(_unit, _pc, _val) \ 1012 DDR40_REG_READ((_unit), (_pc), 0x00, 0x00000378, (_val)) 1013 #define WRITE_DDR40_PHY_WORD_LANE_0_READ_FIFO_DATA_BL0_2r(_unit, _pc, _val) \ 1014 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x00000378, (_val)) 1015 #define MODIFY_DDR40_PHY_WORD_LANE_0_READ_FIFO_DATA_BL0_2r(_unit, _pc, _val, _mask) \ 1016 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x00000378, (_val), (_mask)) 1017 1018 /* Read fifo data register, fourth data */ 1019 #define READ_DDR40_PHY_WORD_LANE_0_READ_FIFO_DATA_BL0_3r(_unit, _pc, _val) \ 1020 DDR40_REG_READ((_unit), (_pc), 0x00, 0x0000037c, (_val)) 1021 #define WRITE_DDR40_PHY_WORD_LANE_0_READ_FIFO_DATA_BL0_3r(_unit, _pc, _val) \ 1022 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x0000037c, (_val)) 1023 #define MODIFY_DDR40_PHY_WORD_LANE_0_READ_FIFO_DATA_BL0_3r(_unit, _pc, _val, _mask) \ 1024 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000037c, (_val), (_mask)) 1025 1026 /* Read fifo data register, first data */ 1027 #define READ_DDR40_PHY_WORD_LANE_0_READ_FIFO_DATA_BL1_0r(_unit, _pc, _val) \ 1028 DDR40_REG_READ((_unit), (_pc), 0x00, 0x00000380, (_val)) 1029 #define WRITE_DDR40_PHY_WORD_LANE_0_READ_FIFO_DATA_BL1_0r(_unit, _pc, _val) \ 1030 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x00000380, (_val)) 1031 #define MODIFY_DDR40_PHY_WORD_LANE_0_READ_FIFO_DATA_BL1_0r(_unit, _pc, _val, _mask) \ 1032 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x00000380, (_val), (_mask)) 1033 1034 /* Read fifo data register, second data */ 1035 #define READ_DDR40_PHY_WORD_LANE_0_READ_FIFO_DATA_BL1_1r(_unit, _pc, _val) \ 1036 DDR40_REG_READ((_unit), (_pc), 0x00, 0x00000384, (_val)) 1037 #define WRITE_DDR40_PHY_WORD_LANE_0_READ_FIFO_DATA_BL1_1r(_unit, _pc, _val) \ 1038 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x00000384, (_val)) 1039 #define MODIFY_DDR40_PHY_WORD_LANE_0_READ_FIFO_DATA_BL1_1r(_unit, _pc, _val, _mask) \ 1040 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x00000384, (_val), (_mask)) 1041 1042 /* Read fifo data register, third data */ 1043 #define READ_DDR40_PHY_WORD_LANE_0_READ_FIFO_DATA_BL1_2r(_unit, _pc, _val) \ 1044 DDR40_REG_READ((_unit), (_pc), 0x00, 0x00000388, (_val)) 1045 #define WRITE_DDR40_PHY_WORD_LANE_0_READ_FIFO_DATA_BL1_2r(_unit, _pc, _val) \ 1046 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x00000388, (_val)) 1047 #define MODIFY_DDR40_PHY_WORD_LANE_0_READ_FIFO_DATA_BL1_2r(_unit, _pc, _val, _mask) \ 1048 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x00000388, (_val), (_mask)) 1049 1050 /* Read fifo data register, fourth data */ 1051 #define READ_DDR40_PHY_WORD_LANE_0_READ_FIFO_DATA_BL1_3r(_unit, _pc, _val) \ 1052 DDR40_REG_READ((_unit), (_pc), 0x00, 0x0000038c, (_val)) 1053 #define WRITE_DDR40_PHY_WORD_LANE_0_READ_FIFO_DATA_BL1_3r(_unit, _pc, _val) \ 1054 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x0000038c, (_val)) 1055 #define MODIFY_DDR40_PHY_WORD_LANE_0_READ_FIFO_DATA_BL1_3r(_unit, _pc, _val, _mask) \ 1056 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000038c, (_val), (_mask)) 1057 1058 /* Read fifo status register */ 1059 #define READ_DDR40_PHY_WORD_LANE_0_READ_FIFO_STATUSr(_unit, _pc, _val) \ 1060 DDR40_REG_READ((_unit), (_pc), 0x00, 0x00000390, (_val)) 1061 #define WRITE_DDR40_PHY_WORD_LANE_0_READ_FIFO_STATUSr(_unit, _pc, _val) \ 1062 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x00000390, (_val)) 1063 #define MODIFY_DDR40_PHY_WORD_LANE_0_READ_FIFO_STATUSr(_unit, _pc, _val, _mask) \ 1064 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x00000390, (_val), (_mask)) 1065 1066 /* Read fifo status clear register */ 1067 #define READ_DDR40_PHY_WORD_LANE_0_READ_FIFO_CLEARr(_unit, _pc, _val) \ 1068 DDR40_REG_READ((_unit), (_pc), 0x00, 0x00000394, (_val)) 1069 #define WRITE_DDR40_PHY_WORD_LANE_0_READ_FIFO_CLEARr(_unit, _pc, _val) \ 1070 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x00000394, (_val)) 1071 #define MODIFY_DDR40_PHY_WORD_LANE_0_READ_FIFO_CLEARr(_unit, _pc, _val, _mask) \ 1072 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x00000394, (_val), (_mask)) 1073 1074 /* Idle mode SSTL pad control register */ 1075 #define READ_DDR40_PHY_WORD_LANE_0_IDLE_PAD_CONTROLr(_unit, _pc, _val) \ 1076 DDR40_REG_READ((_unit), (_pc), 0x00, 0x000003a0, (_val)) 1077 #define WRITE_DDR40_PHY_WORD_LANE_0_IDLE_PAD_CONTROLr(_unit, _pc, _val) \ 1078 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x000003a0, (_val)) 1079 #define MODIFY_DDR40_PHY_WORD_LANE_0_IDLE_PAD_CONTROLr(_unit, _pc, _val, _mask) \ 1080 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x000003a0, (_val), (_mask)) 1081 1082 /* SSTL pad drive characteristics control register */ 1083 #define READ_DDR40_PHY_WORD_LANE_0_DRIVE_PAD_CTLr(_unit, _pc, _val) \ 1084 DDR40_REG_READ((_unit), (_pc), 0x00, 0x000003a4, (_val)) 1085 #define WRITE_DDR40_PHY_WORD_LANE_0_DRIVE_PAD_CTLr(_unit, _pc, _val) \ 1086 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x000003a4, (_val)) 1087 #define MODIFY_DDR40_PHY_WORD_LANE_0_DRIVE_PAD_CTLr(_unit, _pc, _val, _mask) \ 1088 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x000003a4, (_val), (_mask)) 1089 1090 /* Clock pad disable register */ 1091 #define READ_DDR40_PHY_WORD_LANE_0_CLOCK_PAD_DISABLEr(_unit, _pc, _val) \ 1092 DDR40_REG_READ((_unit), (_pc), 0x00, 0x000003a8, (_val)) 1093 #define WRITE_DDR40_PHY_WORD_LANE_0_CLOCK_PAD_DISABLEr(_unit, _pc, _val) \ 1094 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x000003a8, (_val)) 1095 #define MODIFY_DDR40_PHY_WORD_LANE_0_CLOCK_PAD_DISABLEr(_unit, _pc, _val, _mask) \ 1096 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x000003a8, (_val), (_mask)) 1097 1098 /* Write cycle preamble control register */ 1099 #define READ_DDR40_PHY_WORD_LANE_0_WR_PREAMBLE_MODEr(_unit, _pc, _val) \ 1100 DDR40_REG_READ((_unit), (_pc), 0x00, 0x000003ac, (_val)) 1101 #define WRITE_DDR40_PHY_WORD_LANE_0_WR_PREAMBLE_MODEr(_unit, _pc, _val) \ 1102 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x000003ac, (_val)) 1103 #define MODIFY_DDR40_PHY_WORD_LANE_0_WR_PREAMBLE_MODEr(_unit, _pc, _val, _mask) \ 1104 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x000003ac, (_val), (_mask)) 1105 1106 /* PHYBIST mode VDL step select adjustment register */ 1107 #define READ_DDR40_PHY_WORD_LANE_0_PHYBIST_VDL_ADJr(_unit, _pc, _val) \ 1108 DDR40_REG_READ((_unit), (_pc), 0x00, 0x000003b0, (_val)) 1109 #define WRITE_DDR40_PHY_WORD_LANE_0_PHYBIST_VDL_ADJr(_unit, _pc, _val) \ 1110 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x000003b0, (_val)) 1111 #define MODIFY_DDR40_PHY_WORD_LANE_0_PHYBIST_VDL_ADJr(_unit, _pc, _val, _mask) \ 1112 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x000003b0, (_val), (_mask)) 1113 1114 1115 /**************************************************************************** 1116 * DDR40_PHY_DDR40_PHY_WORD_LANE_1 1117 */ 1118 1119 /* Read Enable Byte VDL static override control register */ 1120 #define READ_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE_RD_ENr(_unit, _pc, _val) \ 1121 DDR40_REG_READ((_unit), (_pc), 0x00, 0x00000400, (_val)) 1122 #define WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE_RD_ENr(_unit, _pc, _val) \ 1123 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x00000400, (_val)) 1124 #define MODIFY_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE_RD_ENr(_unit, _pc, _val, _mask) \ 1125 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x00000400, (_val), (_mask)) 1126 1127 /* Write Byte VDL static override control register */ 1128 #define READ_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_Wr(_unit, _pc, _val) \ 1129 DDR40_REG_READ((_unit), (_pc), 0x00, 0x00000404, (_val)) 1130 #define WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_Wr(_unit, _pc, _val) \ 1131 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x00000404, (_val)) 1132 #define MODIFY_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_Wr(_unit, _pc, _val, _mask) \ 1133 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x00000404, (_val), (_mask)) 1134 1135 /* Read Byte DQSP VDL static override control register */ 1136 #define READ_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_Pr(_unit, _pc, _val) \ 1137 DDR40_REG_READ((_unit), (_pc), 0x00, 0x00000408, (_val)) 1138 #define WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_Pr(_unit, _pc, _val) \ 1139 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x00000408, (_val)) 1140 #define MODIFY_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_Pr(_unit, _pc, _val, _mask) \ 1141 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x00000408, (_val), (_mask)) 1142 1143 /* Read Byte DQSN VDL static override control register */ 1144 #define READ_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_Nr(_unit, _pc, _val) \ 1145 DDR40_REG_READ((_unit), (_pc), 0x00, 0x0000040c, (_val)) 1146 #define WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_Nr(_unit, _pc, _val) \ 1147 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x0000040c, (_val)) 1148 #define MODIFY_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_Nr(_unit, _pc, _val, _mask) \ 1149 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000040c, (_val), (_mask)) 1150 1151 /* Write Bit VDL static override control register */ 1152 #define READ_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_Wr(_unit, _pc, _val) \ 1153 DDR40_REG_READ((_unit), (_pc), 0x00, 0x00000410, (_val)) 1154 #define WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_Wr(_unit, _pc, _val) \ 1155 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x00000410, (_val)) 1156 #define MODIFY_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_Wr(_unit, _pc, _val, _mask) \ 1157 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x00000410, (_val), (_mask)) 1158 1159 /* Write Bit VDL static override control register */ 1160 #define READ_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_Wr(_unit, _pc, _val) \ 1161 DDR40_REG_READ((_unit), (_pc), 0x00, 0x00000414, (_val)) 1162 #define WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_Wr(_unit, _pc, _val) \ 1163 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x00000414, (_val)) 1164 #define MODIFY_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_Wr(_unit, _pc, _val, _mask) \ 1165 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x00000414, (_val), (_mask)) 1166 1167 /* Write Bit VDL static override control register */ 1168 #define READ_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_Wr(_unit, _pc, _val) \ 1169 DDR40_REG_READ((_unit), (_pc), 0x00, 0x00000418, (_val)) 1170 #define WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_Wr(_unit, _pc, _val) \ 1171 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x00000418, (_val)) 1172 #define MODIFY_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_Wr(_unit, _pc, _val, _mask) \ 1173 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x00000418, (_val), (_mask)) 1174 1175 /* Write Bit VDL static override control register */ 1176 #define READ_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_Wr(_unit, _pc, _val) \ 1177 DDR40_REG_READ((_unit), (_pc), 0x00, 0x0000041c, (_val)) 1178 #define WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_Wr(_unit, _pc, _val) \ 1179 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x0000041c, (_val)) 1180 #define MODIFY_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_Wr(_unit, _pc, _val, _mask) \ 1181 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000041c, (_val), (_mask)) 1182 1183 /* Write Bit VDL static override control register */ 1184 #define READ_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_Wr(_unit, _pc, _val) \ 1185 DDR40_REG_READ((_unit), (_pc), 0x00, 0x00000420, (_val)) 1186 #define WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_Wr(_unit, _pc, _val) \ 1187 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x00000420, (_val)) 1188 #define MODIFY_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_Wr(_unit, _pc, _val, _mask) \ 1189 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x00000420, (_val), (_mask)) 1190 1191 /* Write Bit VDL static override control register */ 1192 #define READ_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_Wr(_unit, _pc, _val) \ 1193 DDR40_REG_READ((_unit), (_pc), 0x00, 0x00000424, (_val)) 1194 #define WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_Wr(_unit, _pc, _val) \ 1195 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x00000424, (_val)) 1196 #define MODIFY_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_Wr(_unit, _pc, _val, _mask) \ 1197 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x00000424, (_val), (_mask)) 1198 1199 /* Write Bit VDL static override control register */ 1200 #define READ_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_Wr(_unit, _pc, _val) \ 1201 DDR40_REG_READ((_unit), (_pc), 0x00, 0x00000428, (_val)) 1202 #define WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_Wr(_unit, _pc, _val) \ 1203 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x00000428, (_val)) 1204 #define MODIFY_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_Wr(_unit, _pc, _val, _mask) \ 1205 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x00000428, (_val), (_mask)) 1206 1207 /* Write Bit VDL static override control register */ 1208 #define READ_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_Wr(_unit, _pc, _val) \ 1209 DDR40_REG_READ((_unit), (_pc), 0x00, 0x0000042c, (_val)) 1210 #define WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_Wr(_unit, _pc, _val) \ 1211 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x0000042c, (_val)) 1212 #define MODIFY_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_Wr(_unit, _pc, _val, _mask) \ 1213 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000042c, (_val), (_mask)) 1214 1215 /* Write Bit VDL static override control register */ 1216 #define READ_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_DM_Wr(_unit, _pc, _val) \ 1217 DDR40_REG_READ((_unit), (_pc), 0x00, 0x00000430, (_val)) 1218 #define WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_DM_Wr(_unit, _pc, _val) \ 1219 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x00000430, (_val)) 1220 #define MODIFY_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_DM_Wr(_unit, _pc, _val, _mask) \ 1221 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x00000430, (_val), (_mask)) 1222 1223 /* Read DQSP Bit VDL static override control register */ 1224 #define READ_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_Pr(_unit, _pc, _val) \ 1225 DDR40_REG_READ((_unit), (_pc), 0x00, 0x00000434, (_val)) 1226 #define WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_Pr(_unit, _pc, _val) \ 1227 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x00000434, (_val)) 1228 #define MODIFY_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_Pr(_unit, _pc, _val, _mask) \ 1229 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x00000434, (_val), (_mask)) 1230 1231 /* Read DQSN Bit VDL static override control register */ 1232 #define READ_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_Nr(_unit, _pc, _val) \ 1233 DDR40_REG_READ((_unit), (_pc), 0x00, 0x00000438, (_val)) 1234 #define WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_Nr(_unit, _pc, _val) \ 1235 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x00000438, (_val)) 1236 #define MODIFY_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_Nr(_unit, _pc, _val, _mask) \ 1237 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x00000438, (_val), (_mask)) 1238 1239 /* Read DQSP Bit VDL static override control register */ 1240 #define READ_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_Pr(_unit, _pc, _val) \ 1241 DDR40_REG_READ((_unit), (_pc), 0x00, 0x0000043c, (_val)) 1242 #define WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_Pr(_unit, _pc, _val) \ 1243 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x0000043c, (_val)) 1244 #define MODIFY_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_Pr(_unit, _pc, _val, _mask) \ 1245 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000043c, (_val), (_mask)) 1246 1247 /* Read DQSN Bit VDL static override control register */ 1248 #define READ_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_Nr(_unit, _pc, _val) \ 1249 DDR40_REG_READ((_unit), (_pc), 0x00, 0x00000440, (_val)) 1250 #define WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_Nr(_unit, _pc, _val) \ 1251 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x00000440, (_val)) 1252 #define MODIFY_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_Nr(_unit, _pc, _val, _mask) \ 1253 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x00000440, (_val), (_mask)) 1254 1255 /* Read DQSP Bit VDL static override control register */ 1256 #define READ_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_Pr(_unit, _pc, _val) \ 1257 DDR40_REG_READ((_unit), (_pc), 0x00, 0x00000444, (_val)) 1258 #define WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_Pr(_unit, _pc, _val) \ 1259 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x00000444, (_val)) 1260 #define MODIFY_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_Pr(_unit, _pc, _val, _mask) \ 1261 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x00000444, (_val), (_mask)) 1262 1263 /* Read DQSN Bit VDL static override control register */ 1264 #define READ_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_Nr(_unit, _pc, _val) \ 1265 DDR40_REG_READ((_unit), (_pc), 0x00, 0x00000448, (_val)) 1266 #define WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_Nr(_unit, _pc, _val) \ 1267 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x00000448, (_val)) 1268 #define MODIFY_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_Nr(_unit, _pc, _val, _mask) \ 1269 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x00000448, (_val), (_mask)) 1270 1271 /* Read DQSP Bit VDL static override control register */ 1272 #define READ_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_Pr(_unit, _pc, _val) \ 1273 DDR40_REG_READ((_unit), (_pc), 0x00, 0x0000044c, (_val)) 1274 #define WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_Pr(_unit, _pc, _val) \ 1275 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x0000044c, (_val)) 1276 #define MODIFY_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_Pr(_unit, _pc, _val, _mask) \ 1277 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000044c, (_val), (_mask)) 1278 1279 /* Read DQSN Bit VDL static override control register */ 1280 #define READ_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_Nr(_unit, _pc, _val) \ 1281 DDR40_REG_READ((_unit), (_pc), 0x00, 0x00000450, (_val)) 1282 #define WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_Nr(_unit, _pc, _val) \ 1283 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x00000450, (_val)) 1284 #define MODIFY_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_Nr(_unit, _pc, _val, _mask) \ 1285 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x00000450, (_val), (_mask)) 1286 1287 /* Read DQSP Bit VDL static override control register */ 1288 #define READ_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_Pr(_unit, _pc, _val) \ 1289 DDR40_REG_READ((_unit), (_pc), 0x00, 0x00000454, (_val)) 1290 #define WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_Pr(_unit, _pc, _val) \ 1291 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x00000454, (_val)) 1292 #define MODIFY_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_Pr(_unit, _pc, _val, _mask) \ 1293 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x00000454, (_val), (_mask)) 1294 1295 /* Read DQSN Bit VDL static override control register */ 1296 #define READ_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_Nr(_unit, _pc, _val) \ 1297 DDR40_REG_READ((_unit), (_pc), 0x00, 0x00000458, (_val)) 1298 #define WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_Nr(_unit, _pc, _val) \ 1299 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x00000458, (_val)) 1300 #define MODIFY_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_Nr(_unit, _pc, _val, _mask) \ 1301 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x00000458, (_val), (_mask)) 1302 1303 /* Read DQSP Bit VDL static override control register */ 1304 #define READ_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_Pr(_unit, _pc, _val) \ 1305 DDR40_REG_READ((_unit), (_pc), 0x00, 0x0000045c, (_val)) 1306 #define WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_Pr(_unit, _pc, _val) \ 1307 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x0000045c, (_val)) 1308 #define MODIFY_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_Pr(_unit, _pc, _val, _mask) \ 1309 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000045c, (_val), (_mask)) 1310 1311 /* Read DQSN Bit VDL static override control register */ 1312 #define READ_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_Nr(_unit, _pc, _val) \ 1313 DDR40_REG_READ((_unit), (_pc), 0x00, 0x00000460, (_val)) 1314 #define WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_Nr(_unit, _pc, _val) \ 1315 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x00000460, (_val)) 1316 #define MODIFY_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_Nr(_unit, _pc, _val, _mask) \ 1317 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x00000460, (_val), (_mask)) 1318 1319 /* Read DQSP Bit VDL static override control register */ 1320 #define READ_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_Pr(_unit, _pc, _val) \ 1321 DDR40_REG_READ((_unit), (_pc), 0x00, 0x00000464, (_val)) 1322 #define WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_Pr(_unit, _pc, _val) \ 1323 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x00000464, (_val)) 1324 #define MODIFY_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_Pr(_unit, _pc, _val, _mask) \ 1325 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x00000464, (_val), (_mask)) 1326 1327 /* Read DQSN Bit VDL static override control register */ 1328 #define READ_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_Nr(_unit, _pc, _val) \ 1329 DDR40_REG_READ((_unit), (_pc), 0x00, 0x00000468, (_val)) 1330 #define WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_Nr(_unit, _pc, _val) \ 1331 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x00000468, (_val)) 1332 #define MODIFY_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_Nr(_unit, _pc, _val, _mask) \ 1333 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x00000468, (_val), (_mask)) 1334 1335 /* Read DQSP Bit VDL static override control register */ 1336 #define READ_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_Pr(_unit, _pc, _val) \ 1337 DDR40_REG_READ((_unit), (_pc), 0x00, 0x0000046c, (_val)) 1338 #define WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_Pr(_unit, _pc, _val) \ 1339 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x0000046c, (_val)) 1340 #define MODIFY_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_Pr(_unit, _pc, _val, _mask) \ 1341 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000046c, (_val), (_mask)) 1342 1343 /* Read DQSN Bit VDL static override control register */ 1344 #define READ_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_Nr(_unit, _pc, _val) \ 1345 DDR40_REG_READ((_unit), (_pc), 0x00, 0x00000470, (_val)) 1346 #define WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_Nr(_unit, _pc, _val) \ 1347 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x00000470, (_val)) 1348 #define MODIFY_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_Nr(_unit, _pc, _val, _mask) \ 1349 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x00000470, (_val), (_mask)) 1350 1351 /* Read Enable Bit VDL static override control register */ 1352 #define READ_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT_RD_ENr(_unit, _pc, _val) \ 1353 DDR40_REG_READ((_unit), (_pc), 0x00, 0x00000474, (_val)) 1354 #define WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT_RD_ENr(_unit, _pc, _val) \ 1355 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x00000474, (_val)) 1356 #define MODIFY_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT_RD_ENr(_unit, _pc, _val, _mask) \ 1357 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x00000474, (_val), (_mask)) 1358 1359 /* Write Byte VDL static override control register */ 1360 #define READ_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_Wr(_unit, _pc, _val) \ 1361 DDR40_REG_READ((_unit), (_pc), 0x00, 0x000004a4, (_val)) 1362 #define WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_Wr(_unit, _pc, _val) \ 1363 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x000004a4, (_val)) 1364 #define MODIFY_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_Wr(_unit, _pc, _val, _mask) \ 1365 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x000004a4, (_val), (_mask)) 1366 1367 /* Read Byte DQSP VDL static override control register */ 1368 #define READ_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_Pr(_unit, _pc, _val) \ 1369 DDR40_REG_READ((_unit), (_pc), 0x00, 0x000004a8, (_val)) 1370 #define WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_Pr(_unit, _pc, _val) \ 1371 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x000004a8, (_val)) 1372 #define MODIFY_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_Pr(_unit, _pc, _val, _mask) \ 1373 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x000004a8, (_val), (_mask)) 1374 1375 /* Read Byte DQSN VDL static override control register */ 1376 #define READ_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_Nr(_unit, _pc, _val) \ 1377 DDR40_REG_READ((_unit), (_pc), 0x00, 0x000004ac, (_val)) 1378 #define WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_Nr(_unit, _pc, _val) \ 1379 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x000004ac, (_val)) 1380 #define MODIFY_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_Nr(_unit, _pc, _val, _mask) \ 1381 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x000004ac, (_val), (_mask)) 1382 1383 /* Write Bit VDL static override control register */ 1384 #define READ_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_Wr(_unit, _pc, _val) \ 1385 DDR40_REG_READ((_unit), (_pc), 0x00, 0x000004b0, (_val)) 1386 #define WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_Wr(_unit, _pc, _val) \ 1387 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x000004b0, (_val)) 1388 #define MODIFY_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_Wr(_unit, _pc, _val, _mask) \ 1389 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x000004b0, (_val), (_mask)) 1390 1391 /* Write Bit VDL static override control register */ 1392 #define READ_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_Wr(_unit, _pc, _val) \ 1393 DDR40_REG_READ((_unit), (_pc), 0x00, 0x000004b4, (_val)) 1394 #define WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_Wr(_unit, _pc, _val) \ 1395 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x000004b4, (_val)) 1396 #define MODIFY_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_Wr(_unit, _pc, _val, _mask) \ 1397 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x000004b4, (_val), (_mask)) 1398 1399 /* Write Bit VDL static override control register */ 1400 #define READ_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_Wr(_unit, _pc, _val) \ 1401 DDR40_REG_READ((_unit), (_pc), 0x00, 0x000004b8, (_val)) 1402 #define WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_Wr(_unit, _pc, _val) \ 1403 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x000004b8, (_val)) 1404 #define MODIFY_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_Wr(_unit, _pc, _val, _mask) \ 1405 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x000004b8, (_val), (_mask)) 1406 1407 /* Write Bit VDL static override control register */ 1408 #define READ_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_Wr(_unit, _pc, _val) \ 1409 DDR40_REG_READ((_unit), (_pc), 0x00, 0x000004bc, (_val)) 1410 #define WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_Wr(_unit, _pc, _val) \ 1411 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x000004bc, (_val)) 1412 #define MODIFY_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_Wr(_unit, _pc, _val, _mask) \ 1413 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x000004bc, (_val), (_mask)) 1414 1415 /* Write Bit VDL static override control register */ 1416 #define READ_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_Wr(_unit, _pc, _val) \ 1417 DDR40_REG_READ((_unit), (_pc), 0x00, 0x000004c0, (_val)) 1418 #define WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_Wr(_unit, _pc, _val) \ 1419 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x000004c0, (_val)) 1420 #define MODIFY_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_Wr(_unit, _pc, _val, _mask) \ 1421 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x000004c0, (_val), (_mask)) 1422 1423 /* Write Bit VDL static override control register */ 1424 #define READ_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_Wr(_unit, _pc, _val) \ 1425 DDR40_REG_READ((_unit), (_pc), 0x00, 0x000004c4, (_val)) 1426 #define WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_Wr(_unit, _pc, _val) \ 1427 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x000004c4, (_val)) 1428 #define MODIFY_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_Wr(_unit, _pc, _val, _mask) \ 1429 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x000004c4, (_val), (_mask)) 1430 1431 /* Write Bit VDL static override control register */ 1432 #define READ_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_Wr(_unit, _pc, _val) \ 1433 DDR40_REG_READ((_unit), (_pc), 0x00, 0x000004c8, (_val)) 1434 #define WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_Wr(_unit, _pc, _val) \ 1435 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x000004c8, (_val)) 1436 #define MODIFY_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_Wr(_unit, _pc, _val, _mask) \ 1437 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x000004c8, (_val), (_mask)) 1438 1439 /* Write Bit VDL static override control register */ 1440 #define READ_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_Wr(_unit, _pc, _val) \ 1441 DDR40_REG_READ((_unit), (_pc), 0x00, 0x000004cc, (_val)) 1442 #define WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_Wr(_unit, _pc, _val) \ 1443 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x000004cc, (_val)) 1444 #define MODIFY_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_Wr(_unit, _pc, _val, _mask) \ 1445 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x000004cc, (_val), (_mask)) 1446 1447 /* Write Bit VDL static override control register */ 1448 #define READ_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_DM_Wr(_unit, _pc, _val) \ 1449 DDR40_REG_READ((_unit), (_pc), 0x00, 0x000004d0, (_val)) 1450 #define WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_DM_Wr(_unit, _pc, _val) \ 1451 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x000004d0, (_val)) 1452 #define MODIFY_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_DM_Wr(_unit, _pc, _val, _mask) \ 1453 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x000004d0, (_val), (_mask)) 1454 1455 /* Read DQSP Bit VDL static override control register */ 1456 #define READ_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_Pr(_unit, _pc, _val) \ 1457 DDR40_REG_READ((_unit), (_pc), 0x00, 0x000004d4, (_val)) 1458 #define WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_Pr(_unit, _pc, _val) \ 1459 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x000004d4, (_val)) 1460 #define MODIFY_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_Pr(_unit, _pc, _val, _mask) \ 1461 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x000004d4, (_val), (_mask)) 1462 1463 /* Read DQSN Bit VDL static override control register */ 1464 #define READ_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_Nr(_unit, _pc, _val) \ 1465 DDR40_REG_READ((_unit), (_pc), 0x00, 0x000004d8, (_val)) 1466 #define WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_Nr(_unit, _pc, _val) \ 1467 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x000004d8, (_val)) 1468 #define MODIFY_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_Nr(_unit, _pc, _val, _mask) \ 1469 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x000004d8, (_val), (_mask)) 1470 1471 /* Read DQSP Bit VDL static override control register */ 1472 #define READ_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_Pr(_unit, _pc, _val) \ 1473 DDR40_REG_READ((_unit), (_pc), 0x00, 0x000004dc, (_val)) 1474 #define WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_Pr(_unit, _pc, _val) \ 1475 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x000004dc, (_val)) 1476 #define MODIFY_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_Pr(_unit, _pc, _val, _mask) \ 1477 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x000004dc, (_val), (_mask)) 1478 1479 /* Read DQSN Bit VDL static override control register */ 1480 #define READ_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_Nr(_unit, _pc, _val) \ 1481 DDR40_REG_READ((_unit), (_pc), 0x00, 0x000004e0, (_val)) 1482 #define WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_Nr(_unit, _pc, _val) \ 1483 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x000004e0, (_val)) 1484 #define MODIFY_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_Nr(_unit, _pc, _val, _mask) \ 1485 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x000004e0, (_val), (_mask)) 1486 1487 /* Read DQSP Bit VDL static override control register */ 1488 #define READ_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_Pr(_unit, _pc, _val) \ 1489 DDR40_REG_READ((_unit), (_pc), 0x00, 0x000004e4, (_val)) 1490 #define WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_Pr(_unit, _pc, _val) \ 1491 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x000004e4, (_val)) 1492 #define MODIFY_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_Pr(_unit, _pc, _val, _mask) \ 1493 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x000004e4, (_val), (_mask)) 1494 1495 /* Read DQSN Bit VDL static override control register */ 1496 #define READ_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_Nr(_unit, _pc, _val) \ 1497 DDR40_REG_READ((_unit), (_pc), 0x00, 0x000004e8, (_val)) 1498 #define WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_Nr(_unit, _pc, _val) \ 1499 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x000004e8, (_val)) 1500 #define MODIFY_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_Nr(_unit, _pc, _val, _mask) \ 1501 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x000004e8, (_val), (_mask)) 1502 1503 /* Read DQSP Bit VDL static override control register */ 1504 #define READ_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_Pr(_unit, _pc, _val) \ 1505 DDR40_REG_READ((_unit), (_pc), 0x00, 0x000004ec, (_val)) 1506 #define WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_Pr(_unit, _pc, _val) \ 1507 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x000004ec, (_val)) 1508 #define MODIFY_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_Pr(_unit, _pc, _val, _mask) \ 1509 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x000004ec, (_val), (_mask)) 1510 1511 /* Read DQSN Bit VDL static override control register */ 1512 #define READ_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_Nr(_unit, _pc, _val) \ 1513 DDR40_REG_READ((_unit), (_pc), 0x00, 0x000004f0, (_val)) 1514 #define WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_Nr(_unit, _pc, _val) \ 1515 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x000004f0, (_val)) 1516 #define MODIFY_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_Nr(_unit, _pc, _val, _mask) \ 1517 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x000004f0, (_val), (_mask)) 1518 1519 /* Read DQSP Bit VDL static override control register */ 1520 #define READ_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_Pr(_unit, _pc, _val) \ 1521 DDR40_REG_READ((_unit), (_pc), 0x00, 0x000004f4, (_val)) 1522 #define WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_Pr(_unit, _pc, _val) \ 1523 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x000004f4, (_val)) 1524 #define MODIFY_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_Pr(_unit, _pc, _val, _mask) \ 1525 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x000004f4, (_val), (_mask)) 1526 1527 /* Read DQSN Bit VDL static override control register */ 1528 #define READ_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_Nr(_unit, _pc, _val) \ 1529 DDR40_REG_READ((_unit), (_pc), 0x00, 0x000004f8, (_val)) 1530 #define WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_Nr(_unit, _pc, _val) \ 1531 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x000004f8, (_val)) 1532 #define MODIFY_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_Nr(_unit, _pc, _val, _mask) \ 1533 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x000004f8, (_val), (_mask)) 1534 1535 /* Read DQSP Bit VDL static override control register */ 1536 #define READ_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_Pr(_unit, _pc, _val) \ 1537 DDR40_REG_READ((_unit), (_pc), 0x00, 0x000004fc, (_val)) 1538 #define WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_Pr(_unit, _pc, _val) \ 1539 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x000004fc, (_val)) 1540 #define MODIFY_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_Pr(_unit, _pc, _val, _mask) \ 1541 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x000004fc, (_val), (_mask)) 1542 1543 /* Read DQSN Bit VDL static override control register */ 1544 #define READ_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_Nr(_unit, _pc, _val) \ 1545 DDR40_REG_READ((_unit), (_pc), 0x00, 0x00000500, (_val)) 1546 #define WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_Nr(_unit, _pc, _val) \ 1547 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x00000500, (_val)) 1548 #define MODIFY_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_Nr(_unit, _pc, _val, _mask) \ 1549 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x00000500, (_val), (_mask)) 1550 1551 /* Read DQSP Bit VDL static override control register */ 1552 #define READ_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_Pr(_unit, _pc, _val) \ 1553 DDR40_REG_READ((_unit), (_pc), 0x00, 0x00000504, (_val)) 1554 #define WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_Pr(_unit, _pc, _val) \ 1555 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x00000504, (_val)) 1556 #define MODIFY_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_Pr(_unit, _pc, _val, _mask) \ 1557 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x00000504, (_val), (_mask)) 1558 1559 /* Read DQSN Bit VDL static override control register */ 1560 #define READ_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_Nr(_unit, _pc, _val) \ 1561 DDR40_REG_READ((_unit), (_pc), 0x00, 0x00000508, (_val)) 1562 #define WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_Nr(_unit, _pc, _val) \ 1563 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x00000508, (_val)) 1564 #define MODIFY_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_Nr(_unit, _pc, _val, _mask) \ 1565 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x00000508, (_val), (_mask)) 1566 1567 /* Read DQSP Bit VDL static override control register */ 1568 #define READ_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_Pr(_unit, _pc, _val) \ 1569 DDR40_REG_READ((_unit), (_pc), 0x00, 0x0000050c, (_val)) 1570 #define WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_Pr(_unit, _pc, _val) \ 1571 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x0000050c, (_val)) 1572 #define MODIFY_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_Pr(_unit, _pc, _val, _mask) \ 1573 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000050c, (_val), (_mask)) 1574 1575 /* Read DQSN Bit VDL static override control register */ 1576 #define READ_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_Nr(_unit, _pc, _val) \ 1577 DDR40_REG_READ((_unit), (_pc), 0x00, 0x00000510, (_val)) 1578 #define WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_Nr(_unit, _pc, _val) \ 1579 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x00000510, (_val)) 1580 #define MODIFY_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_Nr(_unit, _pc, _val, _mask) \ 1581 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x00000510, (_val), (_mask)) 1582 1583 /* Read Enable Bit VDL static override control register */ 1584 #define READ_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT_RD_ENr(_unit, _pc, _val) \ 1585 DDR40_REG_READ((_unit), (_pc), 0x00, 0x00000514, (_val)) 1586 #define WRITE_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT_RD_ENr(_unit, _pc, _val) \ 1587 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x00000514, (_val)) 1588 #define MODIFY_DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT_RD_ENr(_unit, _pc, _val, _mask) \ 1589 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x00000514, (_val), (_mask)) 1590 1591 /* Read DQSP VDL dynamic override control register */ 1592 #define READ_DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_R_Pr(_unit, _pc, _val) \ 1593 DDR40_REG_READ((_unit), (_pc), 0x00, 0x00000528, (_val)) 1594 #define WRITE_DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_R_Pr(_unit, _pc, _val) \ 1595 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x00000528, (_val)) 1596 #define MODIFY_DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_R_Pr(_unit, _pc, _val, _mask) \ 1597 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x00000528, (_val), (_mask)) 1598 1599 /* Read DQSN VDL dynamic override control register */ 1600 #define READ_DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_R_Nr(_unit, _pc, _val) \ 1601 DDR40_REG_READ((_unit), (_pc), 0x00, 0x0000052c, (_val)) 1602 #define WRITE_DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_R_Nr(_unit, _pc, _val) \ 1603 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x0000052c, (_val)) 1604 #define MODIFY_DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_R_Nr(_unit, _pc, _val, _mask) \ 1605 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000052c, (_val), (_mask)) 1606 1607 /* Read DQ-P VDL dynamic override control register */ 1608 #define READ_DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_Pr(_unit, _pc, _val) \ 1609 DDR40_REG_READ((_unit), (_pc), 0x00, 0x00000530, (_val)) 1610 #define WRITE_DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_Pr(_unit, _pc, _val) \ 1611 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x00000530, (_val)) 1612 #define MODIFY_DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_Pr(_unit, _pc, _val, _mask) \ 1613 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x00000530, (_val), (_mask)) 1614 1615 /* Read DQ-N VDL dynamic override control register */ 1616 #define READ_DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_Nr(_unit, _pc, _val) \ 1617 DDR40_REG_READ((_unit), (_pc), 0x00, 0x00000534, (_val)) 1618 #define WRITE_DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_Nr(_unit, _pc, _val) \ 1619 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x00000534, (_val)) 1620 #define MODIFY_DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_Nr(_unit, _pc, _val, _mask) \ 1621 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x00000534, (_val), (_mask)) 1622 1623 /* Write DQ Byte VDL dynamic override control register */ 1624 #define READ_DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_Wr(_unit, _pc, _val) \ 1625 DDR40_REG_READ((_unit), (_pc), 0x00, 0x00000538, (_val)) 1626 #define WRITE_DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_Wr(_unit, _pc, _val) \ 1627 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x00000538, (_val)) 1628 #define MODIFY_DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_Wr(_unit, _pc, _val, _mask) \ 1629 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x00000538, (_val), (_mask)) 1630 1631 /* Write DQ Bit VDL dynamic override control register */ 1632 #define READ_DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_Wr(_unit, _pc, _val) \ 1633 DDR40_REG_READ((_unit), (_pc), 0x00, 0x0000053c, (_val)) 1634 #define WRITE_DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_Wr(_unit, _pc, _val) \ 1635 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x0000053c, (_val)) 1636 #define MODIFY_DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_Wr(_unit, _pc, _val, _mask) \ 1637 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000053c, (_val), (_mask)) 1638 1639 /* Read DQSP VDL dynamic override control register */ 1640 #define READ_DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_R_Pr(_unit, _pc, _val) \ 1641 DDR40_REG_READ((_unit), (_pc), 0x00, 0x00000548, (_val)) 1642 #define WRITE_DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_R_Pr(_unit, _pc, _val) \ 1643 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x00000548, (_val)) 1644 #define MODIFY_DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_R_Pr(_unit, _pc, _val, _mask) \ 1645 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x00000548, (_val), (_mask)) 1646 1647 /* Read DQSN VDL dynamic override control register */ 1648 #define READ_DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_R_Nr(_unit, _pc, _val) \ 1649 DDR40_REG_READ((_unit), (_pc), 0x00, 0x0000054c, (_val)) 1650 #define WRITE_DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_R_Nr(_unit, _pc, _val) \ 1651 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x0000054c, (_val)) 1652 #define MODIFY_DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_R_Nr(_unit, _pc, _val, _mask) \ 1653 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000054c, (_val), (_mask)) 1654 1655 /* Read DQ-P VDL dynamic override control register */ 1656 #define READ_DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_Pr(_unit, _pc, _val) \ 1657 DDR40_REG_READ((_unit), (_pc), 0x00, 0x00000550, (_val)) 1658 #define WRITE_DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_Pr(_unit, _pc, _val) \ 1659 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x00000550, (_val)) 1660 #define MODIFY_DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_Pr(_unit, _pc, _val, _mask) \ 1661 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x00000550, (_val), (_mask)) 1662 1663 /* Read DQ-N VDL dynamic override control register */ 1664 #define READ_DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_Nr(_unit, _pc, _val) \ 1665 DDR40_REG_READ((_unit), (_pc), 0x00, 0x00000554, (_val)) 1666 #define WRITE_DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_Nr(_unit, _pc, _val) \ 1667 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x00000554, (_val)) 1668 #define MODIFY_DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_Nr(_unit, _pc, _val, _mask) \ 1669 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x00000554, (_val), (_mask)) 1670 1671 /* Write DQ Byte VDL dynamic override control register */ 1672 #define READ_DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_Wr(_unit, _pc, _val) \ 1673 DDR40_REG_READ((_unit), (_pc), 0x00, 0x00000558, (_val)) 1674 #define WRITE_DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_Wr(_unit, _pc, _val) \ 1675 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x00000558, (_val)) 1676 #define MODIFY_DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_Wr(_unit, _pc, _val, _mask) \ 1677 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x00000558, (_val), (_mask)) 1678 1679 /* Write DQ Bit VDL dynamic override control register */ 1680 #define READ_DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_Wr(_unit, _pc, _val) \ 1681 DDR40_REG_READ((_unit), (_pc), 0x00, 0x0000055c, (_val)) 1682 #define WRITE_DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_Wr(_unit, _pc, _val) \ 1683 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x0000055c, (_val)) 1684 #define MODIFY_DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_Wr(_unit, _pc, _val, _mask) \ 1685 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000055c, (_val), (_mask)) 1686 1687 /* Word Lane read channel control register */ 1688 #define READ_DDR40_PHY_WORD_LANE_1_READ_DATA_DLYr(_unit, _pc, _val) \ 1689 DDR40_REG_READ((_unit), (_pc), 0x00, 0x00000560, (_val)) 1690 #define WRITE_DDR40_PHY_WORD_LANE_1_READ_DATA_DLYr(_unit, _pc, _val) \ 1691 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x00000560, (_val)) 1692 #define MODIFY_DDR40_PHY_WORD_LANE_1_READ_DATA_DLYr(_unit, _pc, _val, _mask) \ 1693 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x00000560, (_val), (_mask)) 1694 1695 /* Word Lane read channel control register */ 1696 #define READ_DDR40_PHY_WORD_LANE_1_READ_CONTROLr(_unit, _pc, _val) \ 1697 DDR40_REG_READ((_unit), (_pc), 0x00, 0x00000564, (_val)) 1698 #define WRITE_DDR40_PHY_WORD_LANE_1_READ_CONTROLr(_unit, _pc, _val) \ 1699 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x00000564, (_val)) 1700 #define MODIFY_DDR40_PHY_WORD_LANE_1_READ_CONTROLr(_unit, _pc, _val, _mask) \ 1701 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x00000564, (_val), (_mask)) 1702 1703 /* Read fifo data register, first data */ 1704 #define READ_DDR40_PHY_WORD_LANE_1_READ_FIFO_DATA_BL0_0r(_unit, _pc, _val) \ 1705 DDR40_REG_READ((_unit), (_pc), 0x00, 0x00000570, (_val)) 1706 #define WRITE_DDR40_PHY_WORD_LANE_1_READ_FIFO_DATA_BL0_0r(_unit, _pc, _val) \ 1707 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x00000570, (_val)) 1708 #define MODIFY_DDR40_PHY_WORD_LANE_1_READ_FIFO_DATA_BL0_0r(_unit, _pc, _val, _mask) \ 1709 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x00000570, (_val), (_mask)) 1710 1711 /* Read fifo data register, second data */ 1712 #define READ_DDR40_PHY_WORD_LANE_1_READ_FIFO_DATA_BL0_1r(_unit, _pc, _val) \ 1713 DDR40_REG_READ((_unit), (_pc), 0x00, 0x00000574, (_val)) 1714 #define WRITE_DDR40_PHY_WORD_LANE_1_READ_FIFO_DATA_BL0_1r(_unit, _pc, _val) \ 1715 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x00000574, (_val)) 1716 #define MODIFY_DDR40_PHY_WORD_LANE_1_READ_FIFO_DATA_BL0_1r(_unit, _pc, _val, _mask) \ 1717 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x00000574, (_val), (_mask)) 1718 1719 /* Read fifo data register, third data */ 1720 #define READ_DDR40_PHY_WORD_LANE_1_READ_FIFO_DATA_BL0_2r(_unit, _pc, _val) \ 1721 DDR40_REG_READ((_unit), (_pc), 0x00, 0x00000578, (_val)) 1722 #define WRITE_DDR40_PHY_WORD_LANE_1_READ_FIFO_DATA_BL0_2r(_unit, _pc, _val) \ 1723 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x00000578, (_val)) 1724 #define MODIFY_DDR40_PHY_WORD_LANE_1_READ_FIFO_DATA_BL0_2r(_unit, _pc, _val, _mask) \ 1725 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x00000578, (_val), (_mask)) 1726 1727 /* Read fifo data register, fourth data */ 1728 #define READ_DDR40_PHY_WORD_LANE_1_READ_FIFO_DATA_BL0_3r(_unit, _pc, _val) \ 1729 DDR40_REG_READ((_unit), (_pc), 0x00, 0x0000057c, (_val)) 1730 #define WRITE_DDR40_PHY_WORD_LANE_1_READ_FIFO_DATA_BL0_3r(_unit, _pc, _val) \ 1731 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x0000057c, (_val)) 1732 #define MODIFY_DDR40_PHY_WORD_LANE_1_READ_FIFO_DATA_BL0_3r(_unit, _pc, _val, _mask) \ 1733 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000057c, (_val), (_mask)) 1734 1735 /* Read fifo data register, first data */ 1736 #define READ_DDR40_PHY_WORD_LANE_1_READ_FIFO_DATA_BL1_0r(_unit, _pc, _val) \ 1737 DDR40_REG_READ((_unit), (_pc), 0x00, 0x00000580, (_val)) 1738 #define WRITE_DDR40_PHY_WORD_LANE_1_READ_FIFO_DATA_BL1_0r(_unit, _pc, _val) \ 1739 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x00000580, (_val)) 1740 #define MODIFY_DDR40_PHY_WORD_LANE_1_READ_FIFO_DATA_BL1_0r(_unit, _pc, _val, _mask) \ 1741 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x00000580, (_val), (_mask)) 1742 1743 /* Read fifo data register, second data */ 1744 #define READ_DDR40_PHY_WORD_LANE_1_READ_FIFO_DATA_BL1_1r(_unit, _pc, _val) \ 1745 DDR40_REG_READ((_unit), (_pc), 0x00, 0x00000584, (_val)) 1746 #define WRITE_DDR40_PHY_WORD_LANE_1_READ_FIFO_DATA_BL1_1r(_unit, _pc, _val) \ 1747 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x00000584, (_val)) 1748 #define MODIFY_DDR40_PHY_WORD_LANE_1_READ_FIFO_DATA_BL1_1r(_unit, _pc, _val, _mask) \ 1749 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x00000584, (_val), (_mask)) 1750 1751 /* Read fifo data register, third data */ 1752 #define READ_DDR40_PHY_WORD_LANE_1_READ_FIFO_DATA_BL1_2r(_unit, _pc, _val) \ 1753 DDR40_REG_READ((_unit), (_pc), 0x00, 0x00000588, (_val)) 1754 #define WRITE_DDR40_PHY_WORD_LANE_1_READ_FIFO_DATA_BL1_2r(_unit, _pc, _val) \ 1755 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x00000588, (_val)) 1756 #define MODIFY_DDR40_PHY_WORD_LANE_1_READ_FIFO_DATA_BL1_2r(_unit, _pc, _val, _mask) \ 1757 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x00000588, (_val), (_mask)) 1758 1759 /* Read fifo data register, fourth data */ 1760 #define READ_DDR40_PHY_WORD_LANE_1_READ_FIFO_DATA_BL1_3r(_unit, _pc, _val) \ 1761 DDR40_REG_READ((_unit), (_pc), 0x00, 0x0000058c, (_val)) 1762 #define WRITE_DDR40_PHY_WORD_LANE_1_READ_FIFO_DATA_BL1_3r(_unit, _pc, _val) \ 1763 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x0000058c, (_val)) 1764 #define MODIFY_DDR40_PHY_WORD_LANE_1_READ_FIFO_DATA_BL1_3r(_unit, _pc, _val, _mask) \ 1765 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x0000058c, (_val), (_mask)) 1766 1767 /* Read fifo status register */ 1768 #define READ_DDR40_PHY_WORD_LANE_1_READ_FIFO_STATUSr(_unit, _pc, _val) \ 1769 DDR40_REG_READ((_unit), (_pc), 0x00, 0x00000590, (_val)) 1770 #define WRITE_DDR40_PHY_WORD_LANE_1_READ_FIFO_STATUSr(_unit, _pc, _val) \ 1771 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x00000590, (_val)) 1772 #define MODIFY_DDR40_PHY_WORD_LANE_1_READ_FIFO_STATUSr(_unit, _pc, _val, _mask) \ 1773 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x00000590, (_val), (_mask)) 1774 1775 /* Read fifo status clear register */ 1776 #define READ_DDR40_PHY_WORD_LANE_1_READ_FIFO_CLEARr(_unit, _pc, _val) \ 1777 DDR40_REG_READ((_unit), (_pc), 0x00, 0x00000594, (_val)) 1778 #define WRITE_DDR40_PHY_WORD_LANE_1_READ_FIFO_CLEARr(_unit, _pc, _val) \ 1779 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x00000594, (_val)) 1780 #define MODIFY_DDR40_PHY_WORD_LANE_1_READ_FIFO_CLEARr(_unit, _pc, _val, _mask) \ 1781 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x00000594, (_val), (_mask)) 1782 1783 /* Idle mode SSTL pad control register */ 1784 #define READ_DDR40_PHY_WORD_LANE_1_IDLE_PAD_CONTROLr(_unit, _pc, _val) \ 1785 DDR40_REG_READ((_unit), (_pc), 0x00, 0x000005a0, (_val)) 1786 #define WRITE_DDR40_PHY_WORD_LANE_1_IDLE_PAD_CONTROLr(_unit, _pc, _val) \ 1787 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x000005a0, (_val)) 1788 #define MODIFY_DDR40_PHY_WORD_LANE_1_IDLE_PAD_CONTROLr(_unit, _pc, _val, _mask) \ 1789 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x000005a0, (_val), (_mask)) 1790 1791 /* SSTL pad drive characteristics control register */ 1792 #define READ_DDR40_PHY_WORD_LANE_1_DRIVE_PAD_CTLr(_unit, _pc, _val) \ 1793 DDR40_REG_READ((_unit), (_pc), 0x00, 0x000005a4, (_val)) 1794 #define WRITE_DDR40_PHY_WORD_LANE_1_DRIVE_PAD_CTLr(_unit, _pc, _val) \ 1795 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x000005a4, (_val)) 1796 #define MODIFY_DDR40_PHY_WORD_LANE_1_DRIVE_PAD_CTLr(_unit, _pc, _val, _mask) \ 1797 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x000005a4, (_val), (_mask)) 1798 1799 /* Clock pad disable register */ 1800 #define READ_DDR40_PHY_WORD_LANE_1_CLOCK_PAD_DISABLEr(_unit, _pc, _val) \ 1801 DDR40_REG_READ((_unit), (_pc), 0x00, 0x000005a8, (_val)) 1802 #define WRITE_DDR40_PHY_WORD_LANE_1_CLOCK_PAD_DISABLEr(_unit, _pc, _val) \ 1803 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x000005a8, (_val)) 1804 #define MODIFY_DDR40_PHY_WORD_LANE_1_CLOCK_PAD_DISABLEr(_unit, _pc, _val, _mask) \ 1805 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x000005a8, (_val), (_mask)) 1806 1807 /* Write cycle preamble control register */ 1808 #define READ_DDR40_PHY_WORD_LANE_1_WR_PREAMBLE_MODEr(_unit, _pc, _val) \ 1809 DDR40_REG_READ((_unit), (_pc), 0x00, 0x000005ac, (_val)) 1810 #define WRITE_DDR40_PHY_WORD_LANE_1_WR_PREAMBLE_MODEr(_unit, _pc, _val) \ 1811 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x000005ac, (_val)) 1812 #define MODIFY_DDR40_PHY_WORD_LANE_1_WR_PREAMBLE_MODEr(_unit, _pc, _val, _mask) \ 1813 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x000005ac, (_val), (_mask)) 1814 1815 /* PHYBIST mode VDL step select adjustment register */ 1816 #define READ_DDR40_PHY_WORD_LANE_1_PHYBIST_VDL_ADJr(_unit, _pc, _val) \ 1817 DDR40_REG_READ((_unit), (_pc), 0x00, 0x000005b0, (_val)) 1818 #define WRITE_DDR40_PHY_WORD_LANE_1_PHYBIST_VDL_ADJr(_unit, _pc, _val) \ 1819 DDR40_REG_WRITE((_unit), (_pc), 0x00, 0x000005b0, (_val)) 1820 #define MODIFY_DDR40_PHY_WORD_LANE_1_PHYBIST_VDL_ADJr(_unit, _pc, _val, _mask) \ 1821 DDR40_REG_MODIFY((_unit), (_pc), 0x00, 0x000005b0, (_val), (_mask)) 1822 1823 1824 /**************************************************************************** 1825 * DDR40_PHY_DDR40_PHY_CONTROL_REGS 1826 */ 1827 /**************************************************************************** 1828 * DDR40_PHY_CONTROL_REGS :: REVISION 1829 */ 1830 /* DDR40_PHY_CONTROL_REGS :: REVISION :: reserved0 [31:16] */ 1831 #define DDR40_PHY_CONTROL_REGS_REVISION_RESERVED0_MASK 0xffff0000 1832 #define DDR40_PHY_CONTROL_REGS_REVISION_RESERVED0_ALIGN 0 1833 #define DDR40_PHY_CONTROL_REGS_REVISION_RESERVED0_BITS 16 1834 #define DDR40_PHY_CONTROL_REGS_REVISION_RESERVED0_SHIFT 16 1835 1836 /* DDR40_PHY_CONTROL_REGS :: REVISION :: MAJOR [15:08] */ 1837 #define DDR40_PHY_CONTROL_REGS_REVISION_MAJOR_MASK 0x0000ff00 1838 #define DDR40_PHY_CONTROL_REGS_REVISION_MAJOR_ALIGN 0 1839 #define DDR40_PHY_CONTROL_REGS_REVISION_MAJOR_BITS 8 1840 #define DDR40_PHY_CONTROL_REGS_REVISION_MAJOR_SHIFT 8 1841 1842 /* DDR40_PHY_CONTROL_REGS :: REVISION :: MINOR [07:00] */ 1843 #define DDR40_PHY_CONTROL_REGS_REVISION_MINOR_MASK 0x000000ff 1844 #define DDR40_PHY_CONTROL_REGS_REVISION_MINOR_ALIGN 0 1845 #define DDR40_PHY_CONTROL_REGS_REVISION_MINOR_BITS 8 1846 #define DDR40_PHY_CONTROL_REGS_REVISION_MINOR_SHIFT 0 1847 1848 1849 /**************************************************************************** 1850 * DDR40_PHY_CONTROL_REGS :: CLK_PM_CTRL 1851 */ 1852 /* DDR40_PHY_CONTROL_REGS :: CLK_PM_CTRL :: reserved0 [31:01] */ 1853 #define DDR40_PHY_CONTROL_REGS_CLK_PM_CTRL_RESERVED0_MASK 0xfffffffe 1854 #define DDR40_PHY_CONTROL_REGS_CLK_PM_CTRL_RESERVED0_ALIGN 0 1855 #define DDR40_PHY_CONTROL_REGS_CLK_PM_CTRL_RESERVED0_BITS 31 1856 #define DDR40_PHY_CONTROL_REGS_CLK_PM_CTRL_RESERVED0_SHIFT 1 1857 1858 /* DDR40_PHY_CONTROL_REGS :: CLK_PM_CTRL :: DIS_DDR_CLK [00:00] */ 1859 #define DDR40_PHY_CONTROL_REGS_CLK_PM_CTRL_DIS_DDR_CLK_MASK 0x00000001 1860 #define DDR40_PHY_CONTROL_REGS_CLK_PM_CTRL_DIS_DDR_CLK_ALIGN 0 1861 #define DDR40_PHY_CONTROL_REGS_CLK_PM_CTRL_DIS_DDR_CLK_BITS 1 1862 #define DDR40_PHY_CONTROL_REGS_CLK_PM_CTRL_DIS_DDR_CLK_SHIFT 0 1863 1864 1865 /**************************************************************************** 1866 * DDR40_PHY_CONTROL_REGS :: PLL_STATUS 1867 */ 1868 /* DDR40_PHY_CONTROL_REGS :: PLL_STATUS :: reserved0 [31:27] */ 1869 #define DDR40_PHY_CONTROL_REGS_PLL_STATUS_RESERVED0_MASK 0xf8000000 1870 #define DDR40_PHY_CONTROL_REGS_PLL_STATUS_RESERVED0_ALIGN 0 1871 #define DDR40_PHY_CONTROL_REGS_PLL_STATUS_RESERVED0_BITS 5 1872 #define DDR40_PHY_CONTROL_REGS_PLL_STATUS_RESERVED0_SHIFT 27 1873 1874 /* DDR40_PHY_CONTROL_REGS :: PLL_STATUS :: LOCK_LOST [26:26] */ 1875 #define DDR40_PHY_CONTROL_REGS_PLL_STATUS_LOCK_LOST_MASK 0x04000000 1876 #define DDR40_PHY_CONTROL_REGS_PLL_STATUS_LOCK_LOST_ALIGN 0 1877 #define DDR40_PHY_CONTROL_REGS_PLL_STATUS_LOCK_LOST_BITS 1 1878 #define DDR40_PHY_CONTROL_REGS_PLL_STATUS_LOCK_LOST_SHIFT 26 1879 1880 /* DDR40_PHY_CONTROL_REGS :: PLL_STATUS :: DDR_MHZ [25:14] */ 1881 #define DDR40_PHY_CONTROL_REGS_PLL_STATUS_DDR_MHZ_MASK 0x03ffc000 1882 #define DDR40_PHY_CONTROL_REGS_PLL_STATUS_DDR_MHZ_ALIGN 0 1883 #define DDR40_PHY_CONTROL_REGS_PLL_STATUS_DDR_MHZ_BITS 12 1884 #define DDR40_PHY_CONTROL_REGS_PLL_STATUS_DDR_MHZ_SHIFT 14 1885 1886 /* DDR40_PHY_CONTROL_REGS :: PLL_STATUS :: CLOCKING_4X [13:13] */ 1887 #define DDR40_PHY_CONTROL_REGS_PLL_STATUS_CLOCKING_4X_MASK 0x00002000 1888 #define DDR40_PHY_CONTROL_REGS_PLL_STATUS_CLOCKING_4X_ALIGN 0 1889 #define DDR40_PHY_CONTROL_REGS_PLL_STATUS_CLOCKING_4X_BITS 1 1890 #define DDR40_PHY_CONTROL_REGS_PLL_STATUS_CLOCKING_4X_SHIFT 13 1891 1892 /* DDR40_PHY_CONTROL_REGS :: PLL_STATUS :: STATUS [12:01] */ 1893 #define DDR40_PHY_CONTROL_REGS_PLL_STATUS_STATUS_MASK 0x00001ffe 1894 #define DDR40_PHY_CONTROL_REGS_PLL_STATUS_STATUS_ALIGN 0 1895 #define DDR40_PHY_CONTROL_REGS_PLL_STATUS_STATUS_BITS 12 1896 #define DDR40_PHY_CONTROL_REGS_PLL_STATUS_STATUS_SHIFT 1 1897 1898 /* DDR40_PHY_CONTROL_REGS :: PLL_STATUS :: LOCK [00:00] */ 1899 #define DDR40_PHY_CONTROL_REGS_PLL_STATUS_LOCK_MASK 0x00000001 1900 #define DDR40_PHY_CONTROL_REGS_PLL_STATUS_LOCK_ALIGN 0 1901 #define DDR40_PHY_CONTROL_REGS_PLL_STATUS_LOCK_BITS 1 1902 #define DDR40_PHY_CONTROL_REGS_PLL_STATUS_LOCK_SHIFT 0 1903 1904 1905 /**************************************************************************** 1906 * DDR40_PHY_CONTROL_REGS :: PLL_CONFIG 1907 */ 1908 /* DDR40_PHY_CONTROL_REGS :: PLL_CONFIG :: reserved0 [31:07] */ 1909 #define DDR40_PHY_CONTROL_REGS_PLL_CONFIG_RESERVED0_MASK 0xffffff80 1910 #define DDR40_PHY_CONTROL_REGS_PLL_CONFIG_RESERVED0_ALIGN 0 1911 #define DDR40_PHY_CONTROL_REGS_PLL_CONFIG_RESERVED0_BITS 25 1912 #define DDR40_PHY_CONTROL_REGS_PLL_CONFIG_RESERVED0_SHIFT 7 1913 1914 /* DDR40_PHY_CONTROL_REGS :: PLL_CONFIG :: LP40_PLL_POST_RESET [06:06] */ 1915 #define DDR40_PHY_CONTROL_REGS_PLL_CONFIG_LP40_PLL_POST_RESET_MASK 0x00000040 1916 #define DDR40_PHY_CONTROL_REGS_PLL_CONFIG_LP40_PLL_POST_RESET_ALIGN 0 1917 #define DDR40_PHY_CONTROL_REGS_PLL_CONFIG_LP40_PLL_POST_RESET_BITS 1 1918 #define DDR40_PHY_CONTROL_REGS_PLL_CONFIG_LP40_PLL_POST_RESET_SHIFT 6 1919 1920 /* DDR40_PHY_CONTROL_REGS :: PLL_CONFIG :: RESET_POST_DIV [05:05] */ 1921 #define DDR40_PHY_CONTROL_REGS_PLL_CONFIG_RESET_POST_DIV_MASK 0x00000020 1922 #define DDR40_PHY_CONTROL_REGS_PLL_CONFIG_RESET_POST_DIV_ALIGN 0 1923 #define DDR40_PHY_CONTROL_REGS_PLL_CONFIG_RESET_POST_DIV_BITS 1 1924 #define DDR40_PHY_CONTROL_REGS_PLL_CONFIG_RESET_POST_DIV_SHIFT 5 1925 1926 /* DDR40_PHY_CONTROL_REGS :: PLL_CONFIG :: LDO_CTRL [04:03] */ 1927 #define DDR40_PHY_CONTROL_REGS_PLL_CONFIG_LDO_CTRL_MASK 0x00000018 1928 #define DDR40_PHY_CONTROL_REGS_PLL_CONFIG_LDO_CTRL_ALIGN 0 1929 #define DDR40_PHY_CONTROL_REGS_PLL_CONFIG_LDO_CTRL_BITS 2 1930 #define DDR40_PHY_CONTROL_REGS_PLL_CONFIG_LDO_CTRL_SHIFT 3 1931 1932 /* DDR40_PHY_CONTROL_REGS :: PLL_CONFIG :: reserved1 [02:02] */ 1933 #define DDR40_PHY_CONTROL_REGS_PLL_CONFIG_RESERVED1_MASK 0x00000004 1934 #define DDR40_PHY_CONTROL_REGS_PLL_CONFIG_RESERVED1_ALIGN 0 1935 #define DDR40_PHY_CONTROL_REGS_PLL_CONFIG_RESERVED1_BITS 1 1936 #define DDR40_PHY_CONTROL_REGS_PLL_CONFIG_RESERVED1_SHIFT 2 1937 1938 /* DDR40_PHY_CONTROL_REGS :: PLL_CONFIG :: RESET [01:01] */ 1939 #define DDR40_PHY_CONTROL_REGS_PLL_CONFIG_RESET_MASK 0x00000002 1940 #define DDR40_PHY_CONTROL_REGS_PLL_CONFIG_RESET_ALIGN 0 1941 #define DDR40_PHY_CONTROL_REGS_PLL_CONFIG_RESET_BITS 1 1942 #define DDR40_PHY_CONTROL_REGS_PLL_CONFIG_RESET_SHIFT 1 1943 1944 /* DDR40_PHY_CONTROL_REGS :: PLL_CONFIG :: PWRDN [00:00] */ 1945 #define DDR40_PHY_CONTROL_REGS_PLL_CONFIG_PWRDN_MASK 0x00000001 1946 #define DDR40_PHY_CONTROL_REGS_PLL_CONFIG_PWRDN_ALIGN 0 1947 #define DDR40_PHY_CONTROL_REGS_PLL_CONFIG_PWRDN_BITS 1 1948 #define DDR40_PHY_CONTROL_REGS_PLL_CONFIG_PWRDN_SHIFT 0 1949 1950 1951 /**************************************************************************** 1952 * DDR40_PHY_CONTROL_REGS :: PLL_CONTROL 1953 */ 1954 /* DDR40_PHY_CONTROL_REGS :: PLL_CONTROL :: reserved0 [31:31] */ 1955 #define DDR40_PHY_CONTROL_REGS_PLL_CONTROL_RESERVED0_MASK 0x80000000 1956 #define DDR40_PHY_CONTROL_REGS_PLL_CONTROL_RESERVED0_ALIGN 0 1957 #define DDR40_PHY_CONTROL_REGS_PLL_CONTROL_RESERVED0_BITS 1 1958 #define DDR40_PHY_CONTROL_REGS_PLL_CONTROL_RESERVED0_SHIFT 31 1959 1960 /* DDR40_PHY_CONTROL_REGS :: PLL_CONTROL :: i_kp [30:27] */ 1961 #define DDR40_PHY_CONTROL_REGS_PLL_CONTROL_I_KP_MASK 0x78000000 1962 #define DDR40_PHY_CONTROL_REGS_PLL_CONTROL_I_KP_ALIGN 0 1963 #define DDR40_PHY_CONTROL_REGS_PLL_CONTROL_I_KP_BITS 4 1964 #define DDR40_PHY_CONTROL_REGS_PLL_CONTROL_I_KP_SHIFT 27 1965 1966 /* DDR40_PHY_CONTROL_REGS :: PLL_CONTROL :: i_ki [26:24] */ 1967 #define DDR40_PHY_CONTROL_REGS_PLL_CONTROL_I_KI_MASK 0x07000000 1968 #define DDR40_PHY_CONTROL_REGS_PLL_CONTROL_I_KI_ALIGN 0 1969 #define DDR40_PHY_CONTROL_REGS_PLL_CONTROL_I_KI_BITS 3 1970 #define DDR40_PHY_CONTROL_REGS_PLL_CONTROL_I_KI_SHIFT 24 1971 1972 /* DDR40_PHY_CONTROL_REGS :: PLL_CONTROL :: i_ka [23:21] */ 1973 #define DDR40_PHY_CONTROL_REGS_PLL_CONTROL_I_KA_MASK 0x00e00000 1974 #define DDR40_PHY_CONTROL_REGS_PLL_CONTROL_I_KA_ALIGN 0 1975 #define DDR40_PHY_CONTROL_REGS_PLL_CONTROL_I_KA_BITS 3 1976 #define DDR40_PHY_CONTROL_REGS_PLL_CONTROL_I_KA_SHIFT 21 1977 1978 /* DDR40_PHY_CONTROL_REGS :: PLL_CONTROL :: PLL_CONTROL [20:00] */ 1979 #define DDR40_PHY_CONTROL_REGS_PLL_CONTROL_PLL_CONTROL_MASK 0x001fffff 1980 #define DDR40_PHY_CONTROL_REGS_PLL_CONTROL_PLL_CONTROL_ALIGN 0 1981 #define DDR40_PHY_CONTROL_REGS_PLL_CONTROL_PLL_CONTROL_BITS 21 1982 #define DDR40_PHY_CONTROL_REGS_PLL_CONTROL_PLL_CONTROL_SHIFT 0 1983 1984 1985 /**************************************************************************** 1986 * DDR40_PHY_CONTROL_REGS :: PLL_DIVIDERS 1987 */ 1988 /* DDR40_PHY_CONTROL_REGS :: PLL_DIVIDERS :: reserved0 [31:16] */ 1989 #define DDR40_PHY_CONTROL_REGS_PLL_DIVIDERS_RESERVED0_MASK 0xffff0000 1990 #define DDR40_PHY_CONTROL_REGS_PLL_DIVIDERS_RESERVED0_ALIGN 0 1991 #define DDR40_PHY_CONTROL_REGS_PLL_DIVIDERS_RESERVED0_BITS 16 1992 #define DDR40_PHY_CONTROL_REGS_PLL_DIVIDERS_RESERVED0_SHIFT 16 1993 1994 /* DDR40_PHY_CONTROL_REGS :: PLL_DIVIDERS :: NDIV_40LP_HI [15:15] */ 1995 #define DDR40_PHY_CONTROL_REGS_PLL_DIVIDERS_NDIV_40LP_HI_MASK 0x00008000 1996 #define DDR40_PHY_CONTROL_REGS_PLL_DIVIDERS_NDIV_40LP_HI_ALIGN 0 1997 #define DDR40_PHY_CONTROL_REGS_PLL_DIVIDERS_NDIV_40LP_HI_BITS 1 1998 #define DDR40_PHY_CONTROL_REGS_PLL_DIVIDERS_NDIV_40LP_HI_SHIFT 15 1999 2000 /* DDR40_PHY_CONTROL_REGS :: PLL_DIVIDERS :: NDIV_40LP_LO [14:14] */ 2001 #define DDR40_PHY_CONTROL_REGS_PLL_DIVIDERS_NDIV_40LP_LO_MASK 0x00004000 2002 #define DDR40_PHY_CONTROL_REGS_PLL_DIVIDERS_NDIV_40LP_LO_ALIGN 0 2003 #define DDR40_PHY_CONTROL_REGS_PLL_DIVIDERS_NDIV_40LP_LO_BITS 1 2004 #define DDR40_PHY_CONTROL_REGS_PLL_DIVIDERS_NDIV_40LP_LO_SHIFT 14 2005 2006 /* DDR40_PHY_CONTROL_REGS :: PLL_DIVIDERS :: POST_DIV [13:11] */ 2007 #define DDR40_PHY_CONTROL_REGS_PLL_DIVIDERS_POST_DIV_MASK 0x00003800 2008 #define DDR40_PHY_CONTROL_REGS_PLL_DIVIDERS_POST_DIV_ALIGN 0 2009 #define DDR40_PHY_CONTROL_REGS_PLL_DIVIDERS_POST_DIV_BITS 3 2010 #define DDR40_PHY_CONTROL_REGS_PLL_DIVIDERS_POST_DIV_SHIFT 11 2011 2012 /* DDR40_PHY_CONTROL_REGS :: PLL_DIVIDERS :: PDIV [10:08] */ 2013 #define DDR40_PHY_CONTROL_REGS_PLL_DIVIDERS_PDIV_MASK 0x00000700 2014 #define DDR40_PHY_CONTROL_REGS_PLL_DIVIDERS_PDIV_ALIGN 0 2015 #define DDR40_PHY_CONTROL_REGS_PLL_DIVIDERS_PDIV_BITS 3 2016 #define DDR40_PHY_CONTROL_REGS_PLL_DIVIDERS_PDIV_SHIFT 8 2017 2018 /* DDR40_PHY_CONTROL_REGS :: PLL_DIVIDERS :: NDIV [07:00] */ 2019 #define DDR40_PHY_CONTROL_REGS_PLL_DIVIDERS_NDIV_MASK 0x000000ff 2020 #define DDR40_PHY_CONTROL_REGS_PLL_DIVIDERS_NDIV_ALIGN 0 2021 #define DDR40_PHY_CONTROL_REGS_PLL_DIVIDERS_NDIV_BITS 8 2022 #define DDR40_PHY_CONTROL_REGS_PLL_DIVIDERS_NDIV_SHIFT 0 2023 2024 2025 /**************************************************************************** 2026 * DDR40_PHY_CONTROL_REGS :: AUX_CONTROL 2027 */ 2028 /* DDR40_PHY_CONTROL_REGS :: AUX_CONTROL :: reserved0 [31:10] */ 2029 #define DDR40_PHY_CONTROL_REGS_AUX_CONTROL_RESERVED0_MASK 0xfffffc00 2030 #define DDR40_PHY_CONTROL_REGS_AUX_CONTROL_RESERVED0_ALIGN 0 2031 #define DDR40_PHY_CONTROL_REGS_AUX_CONTROL_RESERVED0_BITS 22 2032 #define DDR40_PHY_CONTROL_REGS_AUX_CONTROL_RESERVED0_SHIFT 10 2033 2034 /* DDR40_PHY_CONTROL_REGS :: AUX_CONTROL :: is_cs [09:07] */ 2035 #define DDR40_PHY_CONTROL_REGS_AUX_CONTROL_IS_CS_MASK 0x00000380 2036 #define DDR40_PHY_CONTROL_REGS_AUX_CONTROL_IS_CS_ALIGN 0 2037 #define DDR40_PHY_CONTROL_REGS_AUX_CONTROL_IS_CS_BITS 3 2038 #define DDR40_PHY_CONTROL_REGS_AUX_CONTROL_IS_CS_SHIFT 7 2039 2040 /* DDR40_PHY_CONTROL_REGS :: AUX_CONTROL :: is_ad [06:04] */ 2041 #define DDR40_PHY_CONTROL_REGS_AUX_CONTROL_IS_AD_MASK 0x00000070 2042 #define DDR40_PHY_CONTROL_REGS_AUX_CONTROL_IS_AD_ALIGN 0 2043 #define DDR40_PHY_CONTROL_REGS_AUX_CONTROL_IS_AD_BITS 3 2044 #define DDR40_PHY_CONTROL_REGS_AUX_CONTROL_IS_AD_SHIFT 4 2045 2046 /* DDR40_PHY_CONTROL_REGS :: AUX_CONTROL :: is_odt [03:01] */ 2047 #define DDR40_PHY_CONTROL_REGS_AUX_CONTROL_IS_ODT_MASK 0x0000000e 2048 #define DDR40_PHY_CONTROL_REGS_AUX_CONTROL_IS_ODT_ALIGN 0 2049 #define DDR40_PHY_CONTROL_REGS_AUX_CONTROL_IS_ODT_BITS 3 2050 #define DDR40_PHY_CONTROL_REGS_AUX_CONTROL_IS_ODT_SHIFT 1 2051 2052 /* DDR40_PHY_CONTROL_REGS :: AUX_CONTROL :: override [00:00] */ 2053 #define DDR40_PHY_CONTROL_REGS_AUX_CONTROL_OVERRIDE_MASK 0x00000001 2054 #define DDR40_PHY_CONTROL_REGS_AUX_CONTROL_OVERRIDE_ALIGN 0 2055 #define DDR40_PHY_CONTROL_REGS_AUX_CONTROL_OVERRIDE_BITS 1 2056 #define DDR40_PHY_CONTROL_REGS_AUX_CONTROL_OVERRIDE_SHIFT 0 2057 2058 2059 /**************************************************************************** 2060 * DDR40_PHY_CONTROL_REGS :: VDL_OVRIDE_BYTE_CTL 2061 */ 2062 /* DDR40_PHY_CONTROL_REGS :: VDL_OVRIDE_BYTE_CTL :: busy [31:31] */ 2063 #define DDR40_PHY_CONTROL_REGS_VDL_OVRIDE_BYTE_CTL_BUSY_MASK 0x80000000 2064 #define DDR40_PHY_CONTROL_REGS_VDL_OVRIDE_BYTE_CTL_BUSY_ALIGN 0 2065 #define DDR40_PHY_CONTROL_REGS_VDL_OVRIDE_BYTE_CTL_BUSY_BITS 1 2066 #define DDR40_PHY_CONTROL_REGS_VDL_OVRIDE_BYTE_CTL_BUSY_SHIFT 31 2067 2068 /* DDR40_PHY_CONTROL_REGS :: VDL_OVRIDE_BYTE_CTL :: reserved0 [30:17] */ 2069 #define DDR40_PHY_CONTROL_REGS_VDL_OVRIDE_BYTE_CTL_RESERVED0_MASK 0x7ffe0000 2070 #define DDR40_PHY_CONTROL_REGS_VDL_OVRIDE_BYTE_CTL_RESERVED0_ALIGN 0 2071 #define DDR40_PHY_CONTROL_REGS_VDL_OVRIDE_BYTE_CTL_RESERVED0_BITS 14 2072 #define DDR40_PHY_CONTROL_REGS_VDL_OVRIDE_BYTE_CTL_RESERVED0_SHIFT 17 2073 2074 /* DDR40_PHY_CONTROL_REGS :: VDL_OVRIDE_BYTE_CTL :: ovr_en [16:16] */ 2075 #define DDR40_PHY_CONTROL_REGS_VDL_OVRIDE_BYTE_CTL_OVR_EN_MASK 0x00010000 2076 #define DDR40_PHY_CONTROL_REGS_VDL_OVRIDE_BYTE_CTL_OVR_EN_ALIGN 0 2077 #define DDR40_PHY_CONTROL_REGS_VDL_OVRIDE_BYTE_CTL_OVR_EN_BITS 1 2078 #define DDR40_PHY_CONTROL_REGS_VDL_OVRIDE_BYTE_CTL_OVR_EN_SHIFT 16 2079 2080 /* DDR40_PHY_CONTROL_REGS :: VDL_OVRIDE_BYTE_CTL :: reserved1 [15:09] */ 2081 #define DDR40_PHY_CONTROL_REGS_VDL_OVRIDE_BYTE_CTL_RESERVED1_MASK 0x0000fe00 2082 #define DDR40_PHY_CONTROL_REGS_VDL_OVRIDE_BYTE_CTL_RESERVED1_ALIGN 0 2083 #define DDR40_PHY_CONTROL_REGS_VDL_OVRIDE_BYTE_CTL_RESERVED1_BITS 7 2084 #define DDR40_PHY_CONTROL_REGS_VDL_OVRIDE_BYTE_CTL_RESERVED1_SHIFT 9 2085 2086 /* DDR40_PHY_CONTROL_REGS :: VDL_OVRIDE_BYTE_CTL :: byte_sel [08:08] */ 2087 #define DDR40_PHY_CONTROL_REGS_VDL_OVRIDE_BYTE_CTL_BYTE_SEL_MASK 0x00000100 2088 #define DDR40_PHY_CONTROL_REGS_VDL_OVRIDE_BYTE_CTL_BYTE_SEL_ALIGN 0 2089 #define DDR40_PHY_CONTROL_REGS_VDL_OVRIDE_BYTE_CTL_BYTE_SEL_BITS 1 2090 #define DDR40_PHY_CONTROL_REGS_VDL_OVRIDE_BYTE_CTL_BYTE_SEL_SHIFT 8 2091 2092 /* DDR40_PHY_CONTROL_REGS :: VDL_OVRIDE_BYTE_CTL :: reserved2 [07:06] */ 2093 #define DDR40_PHY_CONTROL_REGS_VDL_OVRIDE_BYTE_CTL_RESERVED2_MASK 0x000000c0 2094 #define DDR40_PHY_CONTROL_REGS_VDL_OVRIDE_BYTE_CTL_RESERVED2_ALIGN 0 2095 #define DDR40_PHY_CONTROL_REGS_VDL_OVRIDE_BYTE_CTL_RESERVED2_BITS 2 2096 #define DDR40_PHY_CONTROL_REGS_VDL_OVRIDE_BYTE_CTL_RESERVED2_SHIFT 6 2097 2098 /* DDR40_PHY_CONTROL_REGS :: VDL_OVRIDE_BYTE_CTL :: ovr_step [05:00] */ 2099 #define DDR40_PHY_CONTROL_REGS_VDL_OVRIDE_BYTE_CTL_OVR_STEP_MASK 0x0000003f 2100 #define DDR40_PHY_CONTROL_REGS_VDL_OVRIDE_BYTE_CTL_OVR_STEP_ALIGN 0 2101 #define DDR40_PHY_CONTROL_REGS_VDL_OVRIDE_BYTE_CTL_OVR_STEP_BITS 6 2102 #define DDR40_PHY_CONTROL_REGS_VDL_OVRIDE_BYTE_CTL_OVR_STEP_SHIFT 0 2103 2104 2105 /**************************************************************************** 2106 * DDR40_PHY_CONTROL_REGS :: VDL_OVRIDE_BIT_CTL 2107 */ 2108 /* DDR40_PHY_CONTROL_REGS :: VDL_OVRIDE_BIT_CTL :: busy [31:31] */ 2109 #define DDR40_PHY_CONTROL_REGS_VDL_OVRIDE_BIT_CTL_BUSY_MASK 0x80000000 2110 #define DDR40_PHY_CONTROL_REGS_VDL_OVRIDE_BIT_CTL_BUSY_ALIGN 0 2111 #define DDR40_PHY_CONTROL_REGS_VDL_OVRIDE_BIT_CTL_BUSY_BITS 1 2112 #define DDR40_PHY_CONTROL_REGS_VDL_OVRIDE_BIT_CTL_BUSY_SHIFT 31 2113 2114 /* DDR40_PHY_CONTROL_REGS :: VDL_OVRIDE_BIT_CTL :: reserved0 [30:17] */ 2115 #define DDR40_PHY_CONTROL_REGS_VDL_OVRIDE_BIT_CTL_RESERVED0_MASK 0x7ffe0000 2116 #define DDR40_PHY_CONTROL_REGS_VDL_OVRIDE_BIT_CTL_RESERVED0_ALIGN 0 2117 #define DDR40_PHY_CONTROL_REGS_VDL_OVRIDE_BIT_CTL_RESERVED0_BITS 14 2118 #define DDR40_PHY_CONTROL_REGS_VDL_OVRIDE_BIT_CTL_RESERVED0_SHIFT 17 2119 2120 /* DDR40_PHY_CONTROL_REGS :: VDL_OVRIDE_BIT_CTL :: ovr_en [16:16] */ 2121 #define DDR40_PHY_CONTROL_REGS_VDL_OVRIDE_BIT_CTL_OVR_EN_MASK 0x00010000 2122 #define DDR40_PHY_CONTROL_REGS_VDL_OVRIDE_BIT_CTL_OVR_EN_ALIGN 0 2123 #define DDR40_PHY_CONTROL_REGS_VDL_OVRIDE_BIT_CTL_OVR_EN_BITS 1 2124 #define DDR40_PHY_CONTROL_REGS_VDL_OVRIDE_BIT_CTL_OVR_EN_SHIFT 16 2125 2126 /* DDR40_PHY_CONTROL_REGS :: VDL_OVRIDE_BIT_CTL :: reserved1 [15:09] */ 2127 #define DDR40_PHY_CONTROL_REGS_VDL_OVRIDE_BIT_CTL_RESERVED1_MASK 0x0000fe00 2128 #define DDR40_PHY_CONTROL_REGS_VDL_OVRIDE_BIT_CTL_RESERVED1_ALIGN 0 2129 #define DDR40_PHY_CONTROL_REGS_VDL_OVRIDE_BIT_CTL_RESERVED1_BITS 7 2130 #define DDR40_PHY_CONTROL_REGS_VDL_OVRIDE_BIT_CTL_RESERVED1_SHIFT 9 2131 2132 /* DDR40_PHY_CONTROL_REGS :: VDL_OVRIDE_BIT_CTL :: byte_sel [08:08] */ 2133 #define DDR40_PHY_CONTROL_REGS_VDL_OVRIDE_BIT_CTL_BYTE_SEL_MASK 0x00000100 2134 #define DDR40_PHY_CONTROL_REGS_VDL_OVRIDE_BIT_CTL_BYTE_SEL_ALIGN 0 2135 #define DDR40_PHY_CONTROL_REGS_VDL_OVRIDE_BIT_CTL_BYTE_SEL_BITS 1 2136 #define DDR40_PHY_CONTROL_REGS_VDL_OVRIDE_BIT_CTL_BYTE_SEL_SHIFT 8 2137 2138 /* DDR40_PHY_CONTROL_REGS :: VDL_OVRIDE_BIT_CTL :: reserved2 [07:06] */ 2139 #define DDR40_PHY_CONTROL_REGS_VDL_OVRIDE_BIT_CTL_RESERVED2_MASK 0x000000c0 2140 #define DDR40_PHY_CONTROL_REGS_VDL_OVRIDE_BIT_CTL_RESERVED2_ALIGN 0 2141 #define DDR40_PHY_CONTROL_REGS_VDL_OVRIDE_BIT_CTL_RESERVED2_BITS 2 2142 #define DDR40_PHY_CONTROL_REGS_VDL_OVRIDE_BIT_CTL_RESERVED2_SHIFT 6 2143 2144 /* DDR40_PHY_CONTROL_REGS :: VDL_OVRIDE_BIT_CTL :: ovr_step [05:00] */ 2145 #define DDR40_PHY_CONTROL_REGS_VDL_OVRIDE_BIT_CTL_OVR_STEP_MASK 0x0000003f 2146 #define DDR40_PHY_CONTROL_REGS_VDL_OVRIDE_BIT_CTL_OVR_STEP_ALIGN 0 2147 #define DDR40_PHY_CONTROL_REGS_VDL_OVRIDE_BIT_CTL_OVR_STEP_BITS 6 2148 #define DDR40_PHY_CONTROL_REGS_VDL_OVRIDE_BIT_CTL_OVR_STEP_SHIFT 0 2149 2150 2151 /**************************************************************************** 2152 * DDR40_PHY_CONTROL_REGS :: IDLE_PAD_CONTROL 2153 */ 2154 /* DDR40_PHY_CONTROL_REGS :: IDLE_PAD_CONTROL :: idle [31:31] */ 2155 #define DDR40_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_IDLE_MASK 0x80000000 2156 #define DDR40_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_IDLE_ALIGN 0 2157 #define DDR40_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_IDLE_BITS 1 2158 #define DDR40_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_IDLE_SHIFT 31 2159 2160 /* DDR40_PHY_CONTROL_REGS :: IDLE_PAD_CONTROL :: reserved0 [30:09] */ 2161 #define DDR40_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_RESERVED0_MASK 0x7ffffe00 2162 #define DDR40_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_RESERVED0_ALIGN 0 2163 #define DDR40_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_RESERVED0_BITS 22 2164 #define DDR40_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_RESERVED0_SHIFT 9 2165 2166 /* DDR40_PHY_CONTROL_REGS :: IDLE_PAD_CONTROL :: rxenb [08:08] */ 2167 #define DDR40_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_RXENB_MASK 0x00000100 2168 #define DDR40_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_RXENB_ALIGN 0 2169 #define DDR40_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_RXENB_BITS 1 2170 #define DDR40_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_RXENB_SHIFT 8 2171 2172 /* DDR40_PHY_CONTROL_REGS :: IDLE_PAD_CONTROL :: reserved1 [07:07] */ 2173 #define DDR40_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_RESERVED1_MASK 0x00000080 2174 #define DDR40_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_RESERVED1_ALIGN 0 2175 #define DDR40_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_RESERVED1_BITS 1 2176 #define DDR40_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_RESERVED1_SHIFT 7 2177 2178 /* DDR40_PHY_CONTROL_REGS :: IDLE_PAD_CONTROL :: ctl_iddq [06:06] */ 2179 #define DDR40_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_CTL_IDDQ_MASK 0x00000040 2180 #define DDR40_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_CTL_IDDQ_ALIGN 0 2181 #define DDR40_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_CTL_IDDQ_BITS 1 2182 #define DDR40_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_CTL_IDDQ_SHIFT 6 2183 2184 /* DDR40_PHY_CONTROL_REGS :: IDLE_PAD_CONTROL :: ctl_reb [05:05] */ 2185 #define DDR40_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_CTL_REB_MASK 0x00000020 2186 #define DDR40_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_CTL_REB_ALIGN 0 2187 #define DDR40_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_CTL_REB_BITS 1 2188 #define DDR40_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_CTL_REB_SHIFT 5 2189 2190 /* DDR40_PHY_CONTROL_REGS :: IDLE_PAD_CONTROL :: ctl_oeb [04:04] */ 2191 #define DDR40_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_CTL_OEB_MASK 0x00000010 2192 #define DDR40_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_CTL_OEB_ALIGN 0 2193 #define DDR40_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_CTL_OEB_BITS 1 2194 #define DDR40_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_CTL_OEB_SHIFT 4 2195 2196 /* DDR40_PHY_CONTROL_REGS :: IDLE_PAD_CONTROL :: reserved2 [03:03] */ 2197 #define DDR40_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_RESERVED2_MASK 0x00000008 2198 #define DDR40_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_RESERVED2_ALIGN 0 2199 #define DDR40_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_RESERVED2_BITS 1 2200 #define DDR40_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_RESERVED2_SHIFT 3 2201 2202 /* DDR40_PHY_CONTROL_REGS :: IDLE_PAD_CONTROL :: cke_iddq [02:02] */ 2203 #define DDR40_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_CKE_IDDQ_MASK 0x00000004 2204 #define DDR40_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_CKE_IDDQ_ALIGN 0 2205 #define DDR40_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_CKE_IDDQ_BITS 1 2206 #define DDR40_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_CKE_IDDQ_SHIFT 2 2207 2208 /* DDR40_PHY_CONTROL_REGS :: IDLE_PAD_CONTROL :: cke_reb [01:01] */ 2209 #define DDR40_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_CKE_REB_MASK 0x00000002 2210 #define DDR40_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_CKE_REB_ALIGN 0 2211 #define DDR40_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_CKE_REB_BITS 1 2212 #define DDR40_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_CKE_REB_SHIFT 1 2213 2214 /* DDR40_PHY_CONTROL_REGS :: IDLE_PAD_CONTROL :: cke_oeb [00:00] */ 2215 #define DDR40_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_CKE_OEB_MASK 0x00000001 2216 #define DDR40_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_CKE_OEB_ALIGN 0 2217 #define DDR40_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_CKE_OEB_BITS 1 2218 #define DDR40_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_CKE_OEB_SHIFT 0 2219 2220 2221 /**************************************************************************** 2222 * DDR40_PHY_CONTROL_REGS :: ZQ_PVT_COMP_CTL 2223 */ 2224 /* DDR40_PHY_CONTROL_REGS :: ZQ_PVT_COMP_CTL :: reserved0 [31:30] */ 2225 #define DDR40_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_RESERVED0_MASK 0xc0000000 2226 #define DDR40_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_RESERVED0_ALIGN 0 2227 #define DDR40_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_RESERVED0_BITS 2 2228 #define DDR40_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_RESERVED0_SHIFT 30 2229 2230 /* DDR40_PHY_CONTROL_REGS :: ZQ_PVT_COMP_CTL :: addr_zs_val [29:28] */ 2231 #define DDR40_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_ADDR_ZS_VAL_MASK 0x30000000 2232 #define DDR40_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_ADDR_ZS_VAL_ALIGN 0 2233 #define DDR40_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_ADDR_ZS_VAL_BITS 2 2234 #define DDR40_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_ADDR_ZS_VAL_SHIFT 28 2235 2236 /* DDR40_PHY_CONTROL_REGS :: ZQ_PVT_COMP_CTL :: dq_zs_val [27:26] */ 2237 #define DDR40_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_DQ_ZS_VAL_MASK 0x0c000000 2238 #define DDR40_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_DQ_ZS_VAL_ALIGN 0 2239 #define DDR40_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_DQ_ZS_VAL_BITS 2 2240 #define DDR40_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_DQ_ZS_VAL_SHIFT 26 2241 2242 /* DDR40_PHY_CONTROL_REGS :: ZQ_PVT_COMP_CTL :: update_mode [25:25] */ 2243 #define DDR40_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_UPDATE_MODE_MASK 0x02000000 2244 #define DDR40_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_UPDATE_MODE_ALIGN 0 2245 #define DDR40_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_UPDATE_MODE_BITS 1 2246 #define DDR40_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_UPDATE_MODE_SHIFT 25 2247 2248 /* DDR40_PHY_CONTROL_REGS :: ZQ_PVT_COMP_CTL :: pd_done [24:24] */ 2249 #define DDR40_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_PD_DONE_MASK 0x01000000 2250 #define DDR40_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_PD_DONE_ALIGN 0 2251 #define DDR40_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_PD_DONE_BITS 1 2252 #define DDR40_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_PD_DONE_SHIFT 24 2253 2254 /* DDR40_PHY_CONTROL_REGS :: ZQ_PVT_COMP_CTL :: nd_done [23:23] */ 2255 #define DDR40_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_ND_DONE_MASK 0x00800000 2256 #define DDR40_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_ND_DONE_ALIGN 0 2257 #define DDR40_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_ND_DONE_BITS 1 2258 #define DDR40_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_ND_DONE_SHIFT 23 2259 2260 /* DDR40_PHY_CONTROL_REGS :: ZQ_PVT_COMP_CTL :: sample_done [22:22] */ 2261 #define DDR40_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_SAMPLE_DONE_MASK 0x00400000 2262 #define DDR40_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_SAMPLE_DONE_ALIGN 0 2263 #define DDR40_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_SAMPLE_DONE_BITS 1 2264 #define DDR40_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_SAMPLE_DONE_SHIFT 22 2265 2266 /* DDR40_PHY_CONTROL_REGS :: ZQ_PVT_COMP_CTL :: auto_sample_en [21:21] */ 2267 #define DDR40_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_AUTO_SAMPLE_EN_MASK 0x00200000 2268 #define DDR40_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_AUTO_SAMPLE_EN_ALIGN 0 2269 #define DDR40_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_AUTO_SAMPLE_EN_BITS 1 2270 #define DDR40_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_AUTO_SAMPLE_EN_SHIFT 21 2271 2272 /* DDR40_PHY_CONTROL_REGS :: ZQ_PVT_COMP_CTL :: sample_en [20:20] */ 2273 #define DDR40_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_SAMPLE_EN_MASK 0x00100000 2274 #define DDR40_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_SAMPLE_EN_ALIGN 0 2275 #define DDR40_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_SAMPLE_EN_BITS 1 2276 #define DDR40_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_SAMPLE_EN_SHIFT 20 2277 2278 /* DDR40_PHY_CONTROL_REGS :: ZQ_PVT_COMP_CTL :: addr_ovr_en [19:19] */ 2279 #define DDR40_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_ADDR_OVR_EN_MASK 0x00080000 2280 #define DDR40_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_ADDR_OVR_EN_ALIGN 0 2281 #define DDR40_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_ADDR_OVR_EN_BITS 1 2282 #define DDR40_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_ADDR_OVR_EN_SHIFT 19 2283 2284 /* DDR40_PHY_CONTROL_REGS :: ZQ_PVT_COMP_CTL :: dq_ovr_en [18:18] */ 2285 #define DDR40_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_DQ_OVR_EN_MASK 0x00040000 2286 #define DDR40_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_DQ_OVR_EN_ALIGN 0 2287 #define DDR40_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_DQ_OVR_EN_BITS 1 2288 #define DDR40_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_DQ_OVR_EN_SHIFT 18 2289 2290 /* DDR40_PHY_CONTROL_REGS :: ZQ_PVT_COMP_CTL :: pd_comp [17:15] */ 2291 #define DDR40_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_PD_COMP_MASK 0x00038000 2292 #define DDR40_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_PD_COMP_ALIGN 0 2293 #define DDR40_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_PD_COMP_BITS 3 2294 #define DDR40_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_PD_COMP_SHIFT 15 2295 2296 /* DDR40_PHY_CONTROL_REGS :: ZQ_PVT_COMP_CTL :: nd_comp [14:12] */ 2297 #define DDR40_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_ND_COMP_MASK 0x00007000 2298 #define DDR40_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_ND_COMP_ALIGN 0 2299 #define DDR40_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_ND_COMP_BITS 3 2300 #define DDR40_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_ND_COMP_SHIFT 12 2301 2302 /* DDR40_PHY_CONTROL_REGS :: ZQ_PVT_COMP_CTL :: addr_pd_override_val [11:09] */ 2303 #define DDR40_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_ADDR_PD_OVERRIDE_VAL_MASK 0x00000e00 2304 #define DDR40_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_ADDR_PD_OVERRIDE_VAL_ALIGN 0 2305 #define DDR40_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_ADDR_PD_OVERRIDE_VAL_BITS 3 2306 #define DDR40_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_ADDR_PD_OVERRIDE_VAL_SHIFT 9 2307 2308 /* DDR40_PHY_CONTROL_REGS :: ZQ_PVT_COMP_CTL :: addr_nd_override_val [08:06] */ 2309 #define DDR40_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_ADDR_ND_OVERRIDE_VAL_MASK 0x000001c0 2310 #define DDR40_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_ADDR_ND_OVERRIDE_VAL_ALIGN 0 2311 #define DDR40_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_ADDR_ND_OVERRIDE_VAL_BITS 3 2312 #define DDR40_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_ADDR_ND_OVERRIDE_VAL_SHIFT 6 2313 2314 /* DDR40_PHY_CONTROL_REGS :: ZQ_PVT_COMP_CTL :: dq_pd_override_val [05:03] */ 2315 #define DDR40_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_DQ_PD_OVERRIDE_VAL_MASK 0x00000038 2316 #define DDR40_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_DQ_PD_OVERRIDE_VAL_ALIGN 0 2317 #define DDR40_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_DQ_PD_OVERRIDE_VAL_BITS 3 2318 #define DDR40_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_DQ_PD_OVERRIDE_VAL_SHIFT 3 2319 2320 /* DDR40_PHY_CONTROL_REGS :: ZQ_PVT_COMP_CTL :: dq_nd_override_val [02:00] */ 2321 #define DDR40_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_DQ_ND_OVERRIDE_VAL_MASK 0x00000007 2322 #define DDR40_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_DQ_ND_OVERRIDE_VAL_ALIGN 0 2323 #define DDR40_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_DQ_ND_OVERRIDE_VAL_BITS 3 2324 #define DDR40_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_DQ_ND_OVERRIDE_VAL_SHIFT 0 2325 2326 2327 /**************************************************************************** 2328 * DDR40_PHY_CONTROL_REGS :: DRIVE_PAD_CTL 2329 */ 2330 /* DDR40_PHY_CONTROL_REGS :: DRIVE_PAD_CTL :: reserved0 [31:14] */ 2331 #define DDR40_PHY_CONTROL_REGS_DRIVE_PAD_CTL_RESERVED0_MASK 0xffffc000 2332 #define DDR40_PHY_CONTROL_REGS_DRIVE_PAD_CTL_RESERVED0_ALIGN 0 2333 #define DDR40_PHY_CONTROL_REGS_DRIVE_PAD_CTL_RESERVED0_BITS 18 2334 #define DDR40_PHY_CONTROL_REGS_DRIVE_PAD_CTL_RESERVED0_SHIFT 14 2335 2336 /* DDR40_PHY_CONTROL_REGS :: DRIVE_PAD_CTL :: auto_oeb [13:13] */ 2337 #define DDR40_PHY_CONTROL_REGS_DRIVE_PAD_CTL_AUTO_OEB_MASK 0x00002000 2338 #define DDR40_PHY_CONTROL_REGS_DRIVE_PAD_CTL_AUTO_OEB_ALIGN 0 2339 #define DDR40_PHY_CONTROL_REGS_DRIVE_PAD_CTL_AUTO_OEB_BITS 1 2340 #define DDR40_PHY_CONTROL_REGS_DRIVE_PAD_CTL_AUTO_OEB_SHIFT 13 2341 2342 /* DDR40_PHY_CONTROL_REGS :: DRIVE_PAD_CTL :: iddq_a15 [12:12] */ 2343 #define DDR40_PHY_CONTROL_REGS_DRIVE_PAD_CTL_IDDQ_A15_MASK 0x00001000 2344 #define DDR40_PHY_CONTROL_REGS_DRIVE_PAD_CTL_IDDQ_A15_ALIGN 0 2345 #define DDR40_PHY_CONTROL_REGS_DRIVE_PAD_CTL_IDDQ_A15_BITS 1 2346 #define DDR40_PHY_CONTROL_REGS_DRIVE_PAD_CTL_IDDQ_A15_SHIFT 12 2347 2348 /* DDR40_PHY_CONTROL_REGS :: DRIVE_PAD_CTL :: iddq_a14 [11:11] */ 2349 #define DDR40_PHY_CONTROL_REGS_DRIVE_PAD_CTL_IDDQ_A14_MASK 0x00000800 2350 #define DDR40_PHY_CONTROL_REGS_DRIVE_PAD_CTL_IDDQ_A14_ALIGN 0 2351 #define DDR40_PHY_CONTROL_REGS_DRIVE_PAD_CTL_IDDQ_A14_BITS 1 2352 #define DDR40_PHY_CONTROL_REGS_DRIVE_PAD_CTL_IDDQ_A14_SHIFT 11 2353 2354 /* DDR40_PHY_CONTROL_REGS :: DRIVE_PAD_CTL :: iddq_a13 [10:10] */ 2355 #define DDR40_PHY_CONTROL_REGS_DRIVE_PAD_CTL_IDDQ_A13_MASK 0x00000400 2356 #define DDR40_PHY_CONTROL_REGS_DRIVE_PAD_CTL_IDDQ_A13_ALIGN 0 2357 #define DDR40_PHY_CONTROL_REGS_DRIVE_PAD_CTL_IDDQ_A13_BITS 1 2358 #define DDR40_PHY_CONTROL_REGS_DRIVE_PAD_CTL_IDDQ_A13_SHIFT 10 2359 2360 /* DDR40_PHY_CONTROL_REGS :: DRIVE_PAD_CTL :: iddq_aux [09:07] */ 2361 #define DDR40_PHY_CONTROL_REGS_DRIVE_PAD_CTL_IDDQ_AUX_MASK 0x00000380 2362 #define DDR40_PHY_CONTROL_REGS_DRIVE_PAD_CTL_IDDQ_AUX_ALIGN 0 2363 #define DDR40_PHY_CONTROL_REGS_DRIVE_PAD_CTL_IDDQ_AUX_BITS 3 2364 #define DDR40_PHY_CONTROL_REGS_DRIVE_PAD_CTL_IDDQ_AUX_SHIFT 7 2365 2366 /* DDR40_PHY_CONTROL_REGS :: DRIVE_PAD_CTL :: half_strength [06:06] */ 2367 #define DDR40_PHY_CONTROL_REGS_DRIVE_PAD_CTL_HALF_STRENGTH_MASK 0x00000040 2368 #define DDR40_PHY_CONTROL_REGS_DRIVE_PAD_CTL_HALF_STRENGTH_ALIGN 0 2369 #define DDR40_PHY_CONTROL_REGS_DRIVE_PAD_CTL_HALF_STRENGTH_BITS 1 2370 #define DDR40_PHY_CONTROL_REGS_DRIVE_PAD_CTL_HALF_STRENGTH_SHIFT 6 2371 2372 /* DDR40_PHY_CONTROL_REGS :: DRIVE_PAD_CTL :: gddr_symmetry [05:05] */ 2373 #define DDR40_PHY_CONTROL_REGS_DRIVE_PAD_CTL_GDDR_SYMMETRY_MASK 0x00000020 2374 #define DDR40_PHY_CONTROL_REGS_DRIVE_PAD_CTL_GDDR_SYMMETRY_ALIGN 0 2375 #define DDR40_PHY_CONTROL_REGS_DRIVE_PAD_CTL_GDDR_SYMMETRY_BITS 1 2376 #define DDR40_PHY_CONTROL_REGS_DRIVE_PAD_CTL_GDDR_SYMMETRY_SHIFT 5 2377 2378 /* DDR40_PHY_CONTROL_REGS :: DRIVE_PAD_CTL :: vddo_volts [04:03] */ 2379 #define DDR40_PHY_CONTROL_REGS_DRIVE_PAD_CTL_VDDO_VOLTS_MASK 0x00000018 2380 #define DDR40_PHY_CONTROL_REGS_DRIVE_PAD_CTL_VDDO_VOLTS_ALIGN 0 2381 #define DDR40_PHY_CONTROL_REGS_DRIVE_PAD_CTL_VDDO_VOLTS_BITS 2 2382 #define DDR40_PHY_CONTROL_REGS_DRIVE_PAD_CTL_VDDO_VOLTS_SHIFT 3 2383 2384 /* DDR40_PHY_CONTROL_REGS :: DRIVE_PAD_CTL :: rt60b [02:02] */ 2385 #define DDR40_PHY_CONTROL_REGS_DRIVE_PAD_CTL_RT60B_MASK 0x00000004 2386 #define DDR40_PHY_CONTROL_REGS_DRIVE_PAD_CTL_RT60B_ALIGN 0 2387 #define DDR40_PHY_CONTROL_REGS_DRIVE_PAD_CTL_RT60B_BITS 1 2388 #define DDR40_PHY_CONTROL_REGS_DRIVE_PAD_CTL_RT60B_SHIFT 2 2389 2390 /* DDR40_PHY_CONTROL_REGS :: DRIVE_PAD_CTL :: rt120b_g [01:01] */ 2391 #define DDR40_PHY_CONTROL_REGS_DRIVE_PAD_CTL_RT120B_G_MASK 0x00000002 2392 #define DDR40_PHY_CONTROL_REGS_DRIVE_PAD_CTL_RT120B_G_ALIGN 0 2393 #define DDR40_PHY_CONTROL_REGS_DRIVE_PAD_CTL_RT120B_G_BITS 1 2394 #define DDR40_PHY_CONTROL_REGS_DRIVE_PAD_CTL_RT120B_G_SHIFT 1 2395 2396 /* DDR40_PHY_CONTROL_REGS :: DRIVE_PAD_CTL :: g_ddr [00:00] */ 2397 #define DDR40_PHY_CONTROL_REGS_DRIVE_PAD_CTL_G_DDR_MASK 0x00000001 2398 #define DDR40_PHY_CONTROL_REGS_DRIVE_PAD_CTL_G_DDR_ALIGN 0 2399 #define DDR40_PHY_CONTROL_REGS_DRIVE_PAD_CTL_G_DDR_BITS 1 2400 #define DDR40_PHY_CONTROL_REGS_DRIVE_PAD_CTL_G_DDR_SHIFT 0 2401 2402 2403 /**************************************************************************** 2404 * DDR40_PHY_CONTROL_REGS :: VDL_RD_DATA_DLY_STATUS 2405 */ 2406 /* DDR40_PHY_CONTROL_REGS :: VDL_RD_DATA_DLY_STATUS :: reserved0 [31:12] */ 2407 #define DDR40_PHY_CONTROL_REGS_VDL_RD_DATA_DLY_STATUS_RESERVED0_MASK 0xfffff000 2408 #define DDR40_PHY_CONTROL_REGS_VDL_RD_DATA_DLY_STATUS_RESERVED0_ALIGN 0 2409 #define DDR40_PHY_CONTROL_REGS_VDL_RD_DATA_DLY_STATUS_RESERVED0_BITS 20 2410 #define DDR40_PHY_CONTROL_REGS_VDL_RD_DATA_DLY_STATUS_RESERVED0_SHIFT 12 2411 2412 /* DDR40_PHY_CONTROL_REGS :: VDL_RD_DATA_DLY_STATUS :: auto_init_state [11:06] */ 2413 #define DDR40_PHY_CONTROL_REGS_VDL_RD_DATA_DLY_STATUS_AUTO_INIT_STATE_MASK 0x00000fc0 2414 #define DDR40_PHY_CONTROL_REGS_VDL_RD_DATA_DLY_STATUS_AUTO_INIT_STATE_ALIGN 0 2415 #define DDR40_PHY_CONTROL_REGS_VDL_RD_DATA_DLY_STATUS_AUTO_INIT_STATE_BITS 6 2416 #define DDR40_PHY_CONTROL_REGS_VDL_RD_DATA_DLY_STATUS_AUTO_INIT_STATE_SHIFT 6 2417 2418 /* DDR40_PHY_CONTROL_REGS :: VDL_RD_DATA_DLY_STATUS :: rd_data_dly_max [05:03] */ 2419 #define DDR40_PHY_CONTROL_REGS_VDL_RD_DATA_DLY_STATUS_RD_DATA_DLY_MAX_MASK 0x00000038 2420 #define DDR40_PHY_CONTROL_REGS_VDL_RD_DATA_DLY_STATUS_RD_DATA_DLY_MAX_ALIGN 0 2421 #define DDR40_PHY_CONTROL_REGS_VDL_RD_DATA_DLY_STATUS_RD_DATA_DLY_MAX_BITS 3 2422 #define DDR40_PHY_CONTROL_REGS_VDL_RD_DATA_DLY_STATUS_RD_DATA_DLY_MAX_SHIFT 3 2423 2424 /* DDR40_PHY_CONTROL_REGS :: VDL_RD_DATA_DLY_STATUS :: rd_data_dly_min [02:00] */ 2425 #define DDR40_PHY_CONTROL_REGS_VDL_RD_DATA_DLY_STATUS_RD_DATA_DLY_MIN_MASK 0x00000007 2426 #define DDR40_PHY_CONTROL_REGS_VDL_RD_DATA_DLY_STATUS_RD_DATA_DLY_MIN_ALIGN 0 2427 #define DDR40_PHY_CONTROL_REGS_VDL_RD_DATA_DLY_STATUS_RD_DATA_DLY_MIN_BITS 3 2428 #define DDR40_PHY_CONTROL_REGS_VDL_RD_DATA_DLY_STATUS_RD_DATA_DLY_MIN_SHIFT 0 2429 2430 2431 /**************************************************************************** 2432 * DDR40_PHY_CONTROL_REGS :: VDL_CALIBRATE 2433 */ 2434 /* DDR40_PHY_CONTROL_REGS :: VDL_CALIBRATE :: reserved0 [31:29] */ 2435 #define DDR40_PHY_CONTROL_REGS_VDL_CALIBRATE_RESERVED0_MASK 0xe0000000 2436 #define DDR40_PHY_CONTROL_REGS_VDL_CALIBRATE_RESERVED0_ALIGN 0 2437 #define DDR40_PHY_CONTROL_REGS_VDL_CALIBRATE_RESERVED0_BITS 3 2438 #define DDR40_PHY_CONTROL_REGS_VDL_CALIBRATE_RESERVED0_SHIFT 29 2439 2440 /* DDR40_PHY_CONTROL_REGS :: VDL_CALIBRATE :: use_straps [28:28] */ 2441 #define DDR40_PHY_CONTROL_REGS_VDL_CALIBRATE_USE_STRAPS_MASK 0x10000000 2442 #define DDR40_PHY_CONTROL_REGS_VDL_CALIBRATE_USE_STRAPS_ALIGN 0 2443 #define DDR40_PHY_CONTROL_REGS_VDL_CALIBRATE_USE_STRAPS_BITS 1 2444 #define DDR40_PHY_CONTROL_REGS_VDL_CALIBRATE_USE_STRAPS_SHIFT 28 2445 2446 /* DDR40_PHY_CONTROL_REGS :: VDL_CALIBRATE :: auto_init [27:27] */ 2447 #define DDR40_PHY_CONTROL_REGS_VDL_CALIBRATE_AUTO_INIT_MASK 0x08000000 2448 #define DDR40_PHY_CONTROL_REGS_VDL_CALIBRATE_AUTO_INIT_ALIGN 0 2449 #define DDR40_PHY_CONTROL_REGS_VDL_CALIBRATE_AUTO_INIT_BITS 1 2450 #define DDR40_PHY_CONTROL_REGS_VDL_CALIBRATE_AUTO_INIT_SHIFT 27 2451 2452 /* DDR40_PHY_CONTROL_REGS :: VDL_CALIBRATE :: skip_rst [26:26] */ 2453 #define DDR40_PHY_CONTROL_REGS_VDL_CALIBRATE_SKIP_RST_MASK 0x04000000 2454 #define DDR40_PHY_CONTROL_REGS_VDL_CALIBRATE_SKIP_RST_ALIGN 0 2455 #define DDR40_PHY_CONTROL_REGS_VDL_CALIBRATE_SKIP_RST_BITS 1 2456 #define DDR40_PHY_CONTROL_REGS_VDL_CALIBRATE_SKIP_RST_SHIFT 26 2457 2458 /* DDR40_PHY_CONTROL_REGS :: VDL_CALIBRATE :: exit_in_sr [25:25] */ 2459 #define DDR40_PHY_CONTROL_REGS_VDL_CALIBRATE_EXIT_IN_SR_MASK 0x02000000 2460 #define DDR40_PHY_CONTROL_REGS_VDL_CALIBRATE_EXIT_IN_SR_ALIGN 0 2461 #define DDR40_PHY_CONTROL_REGS_VDL_CALIBRATE_EXIT_IN_SR_BITS 1 2462 #define DDR40_PHY_CONTROL_REGS_VDL_CALIBRATE_EXIT_IN_SR_SHIFT 25 2463 2464 /* DDR40_PHY_CONTROL_REGS :: VDL_CALIBRATE :: rd_dly_cal [24:24] */ 2465 #define DDR40_PHY_CONTROL_REGS_VDL_CALIBRATE_RD_DLY_CAL_MASK 0x01000000 2466 #define DDR40_PHY_CONTROL_REGS_VDL_CALIBRATE_RD_DLY_CAL_ALIGN 0 2467 #define DDR40_PHY_CONTROL_REGS_VDL_CALIBRATE_RD_DLY_CAL_BITS 1 2468 #define DDR40_PHY_CONTROL_REGS_VDL_CALIBRATE_RD_DLY_CAL_SHIFT 24 2469 2470 /* DDR40_PHY_CONTROL_REGS :: VDL_CALIBRATE :: bit_refresh [23:23] */ 2471 #define DDR40_PHY_CONTROL_REGS_VDL_CALIBRATE_BIT_REFRESH_MASK 0x00800000 2472 #define DDR40_PHY_CONTROL_REGS_VDL_CALIBRATE_BIT_REFRESH_ALIGN 0 2473 #define DDR40_PHY_CONTROL_REGS_VDL_CALIBRATE_BIT_REFRESH_BITS 1 2474 #define DDR40_PHY_CONTROL_REGS_VDL_CALIBRATE_BIT_REFRESH_SHIFT 23 2475 2476 /* DDR40_PHY_CONTROL_REGS :: VDL_CALIBRATE :: set_wr_dq [22:22] */ 2477 #define DDR40_PHY_CONTROL_REGS_VDL_CALIBRATE_SET_WR_DQ_MASK 0x00400000 2478 #define DDR40_PHY_CONTROL_REGS_VDL_CALIBRATE_SET_WR_DQ_ALIGN 0 2479 #define DDR40_PHY_CONTROL_REGS_VDL_CALIBRATE_SET_WR_DQ_BITS 1 2480 #define DDR40_PHY_CONTROL_REGS_VDL_CALIBRATE_SET_WR_DQ_SHIFT 22 2481 2482 /* DDR40_PHY_CONTROL_REGS :: VDL_CALIBRATE :: dq0_only [21:21] */ 2483 #define DDR40_PHY_CONTROL_REGS_VDL_CALIBRATE_DQ0_ONLY_MASK 0x00200000 2484 #define DDR40_PHY_CONTROL_REGS_VDL_CALIBRATE_DQ0_ONLY_ALIGN 0 2485 #define DDR40_PHY_CONTROL_REGS_VDL_CALIBRATE_DQ0_ONLY_BITS 1 2486 #define DDR40_PHY_CONTROL_REGS_VDL_CALIBRATE_DQ0_ONLY_SHIFT 21 2487 2488 /* DDR40_PHY_CONTROL_REGS :: VDL_CALIBRATE :: set_mr_mpr [20:20] */ 2489 #define DDR40_PHY_CONTROL_REGS_VDL_CALIBRATE_SET_MR_MPR_MASK 0x00100000 2490 #define DDR40_PHY_CONTROL_REGS_VDL_CALIBRATE_SET_MR_MPR_ALIGN 0 2491 #define DDR40_PHY_CONTROL_REGS_VDL_CALIBRATE_SET_MR_MPR_BITS 1 2492 #define DDR40_PHY_CONTROL_REGS_VDL_CALIBRATE_SET_MR_MPR_SHIFT 20 2493 2494 /* DDR40_PHY_CONTROL_REGS :: VDL_CALIBRATE :: bit_cal [19:19] */ 2495 #define DDR40_PHY_CONTROL_REGS_VDL_CALIBRATE_BIT_CAL_MASK 0x00080000 2496 #define DDR40_PHY_CONTROL_REGS_VDL_CALIBRATE_BIT_CAL_ALIGN 0 2497 #define DDR40_PHY_CONTROL_REGS_VDL_CALIBRATE_BIT_CAL_BITS 1 2498 #define DDR40_PHY_CONTROL_REGS_VDL_CALIBRATE_BIT_CAL_SHIFT 19 2499 2500 /* DDR40_PHY_CONTROL_REGS :: VDL_CALIBRATE :: rd_en_cal [18:18] */ 2501 #define DDR40_PHY_CONTROL_REGS_VDL_CALIBRATE_RD_EN_CAL_MASK 0x00040000 2502 #define DDR40_PHY_CONTROL_REGS_VDL_CALIBRATE_RD_EN_CAL_ALIGN 0 2503 #define DDR40_PHY_CONTROL_REGS_VDL_CALIBRATE_RD_EN_CAL_BITS 1 2504 #define DDR40_PHY_CONTROL_REGS_VDL_CALIBRATE_RD_EN_CAL_SHIFT 18 2505 2506 /* DDR40_PHY_CONTROL_REGS :: VDL_CALIBRATE :: calib_bit_offset [17:12] */ 2507 #define DDR40_PHY_CONTROL_REGS_VDL_CALIBRATE_CALIB_BIT_OFFSET_MASK 0x0003f000 2508 #define DDR40_PHY_CONTROL_REGS_VDL_CALIBRATE_CALIB_BIT_OFFSET_ALIGN 0 2509 #define DDR40_PHY_CONTROL_REGS_VDL_CALIBRATE_CALIB_BIT_OFFSET_BITS 6 2510 #define DDR40_PHY_CONTROL_REGS_VDL_CALIBRATE_CALIB_BIT_OFFSET_SHIFT 12 2511 2512 /* DDR40_PHY_CONTROL_REGS :: VDL_CALIBRATE :: calib_dqs_clocks [11:11] */ 2513 #define DDR40_PHY_CONTROL_REGS_VDL_CALIBRATE_CALIB_DQS_CLOCKS_MASK 0x00000800 2514 #define DDR40_PHY_CONTROL_REGS_VDL_CALIBRATE_CALIB_DQS_CLOCKS_ALIGN 0 2515 #define DDR40_PHY_CONTROL_REGS_VDL_CALIBRATE_CALIB_DQS_CLOCKS_BITS 1 2516 #define DDR40_PHY_CONTROL_REGS_VDL_CALIBRATE_CALIB_DQS_CLOCKS_SHIFT 11 2517 2518 /* DDR40_PHY_CONTROL_REGS :: VDL_CALIBRATE :: calib_dqs_pair [10:10] */ 2519 #define DDR40_PHY_CONTROL_REGS_VDL_CALIBRATE_CALIB_DQS_PAIR_MASK 0x00000400 2520 #define DDR40_PHY_CONTROL_REGS_VDL_CALIBRATE_CALIB_DQS_PAIR_ALIGN 0 2521 #define DDR40_PHY_CONTROL_REGS_VDL_CALIBRATE_CALIB_DQS_PAIR_BITS 1 2522 #define DDR40_PHY_CONTROL_REGS_VDL_CALIBRATE_CALIB_DQS_PAIR_SHIFT 10 2523 2524 /* DDR40_PHY_CONTROL_REGS :: VDL_CALIBRATE :: calib_steps [09:09] */ 2525 #define DDR40_PHY_CONTROL_REGS_VDL_CALIBRATE_CALIB_STEPS_MASK 0x00000200 2526 #define DDR40_PHY_CONTROL_REGS_VDL_CALIBRATE_CALIB_STEPS_ALIGN 0 2527 #define DDR40_PHY_CONTROL_REGS_VDL_CALIBRATE_CALIB_STEPS_BITS 1 2528 #define DDR40_PHY_CONTROL_REGS_VDL_CALIBRATE_CALIB_STEPS_SHIFT 9 2529 2530 /* DDR40_PHY_CONTROL_REGS :: VDL_CALIBRATE :: calib_auto [08:08] */ 2531 #define DDR40_PHY_CONTROL_REGS_VDL_CALIBRATE_CALIB_AUTO_MASK 0x00000100 2532 #define DDR40_PHY_CONTROL_REGS_VDL_CALIBRATE_CALIB_AUTO_ALIGN 0 2533 #define DDR40_PHY_CONTROL_REGS_VDL_CALIBRATE_CALIB_AUTO_BITS 1 2534 #define DDR40_PHY_CONTROL_REGS_VDL_CALIBRATE_CALIB_AUTO_SHIFT 8 2535 2536 /* DDR40_PHY_CONTROL_REGS :: VDL_CALIBRATE :: calib_ftm [07:07] */ 2537 #define DDR40_PHY_CONTROL_REGS_VDL_CALIBRATE_CALIB_FTM_MASK 0x00000080 2538 #define DDR40_PHY_CONTROL_REGS_VDL_CALIBRATE_CALIB_FTM_ALIGN 0 2539 #define DDR40_PHY_CONTROL_REGS_VDL_CALIBRATE_CALIB_FTM_BITS 1 2540 #define DDR40_PHY_CONTROL_REGS_VDL_CALIBRATE_CALIB_FTM_SHIFT 7 2541 2542 /* DDR40_PHY_CONTROL_REGS :: VDL_CALIBRATE :: calib_phybist [06:06] */ 2543 #define DDR40_PHY_CONTROL_REGS_VDL_CALIBRATE_CALIB_PHYBIST_MASK 0x00000040 2544 #define DDR40_PHY_CONTROL_REGS_VDL_CALIBRATE_CALIB_PHYBIST_ALIGN 0 2545 #define DDR40_PHY_CONTROL_REGS_VDL_CALIBRATE_CALIB_PHYBIST_BITS 1 2546 #define DDR40_PHY_CONTROL_REGS_VDL_CALIBRATE_CALIB_PHYBIST_SHIFT 6 2547 2548 /* DDR40_PHY_CONTROL_REGS :: VDL_CALIBRATE :: calib_byte [05:05] */ 2549 #define DDR40_PHY_CONTROL_REGS_VDL_CALIBRATE_CALIB_BYTE_MASK 0x00000020 2550 #define DDR40_PHY_CONTROL_REGS_VDL_CALIBRATE_CALIB_BYTE_ALIGN 0 2551 #define DDR40_PHY_CONTROL_REGS_VDL_CALIBRATE_CALIB_BYTE_BITS 1 2552 #define DDR40_PHY_CONTROL_REGS_VDL_CALIBRATE_CALIB_BYTE_SHIFT 5 2553 2554 /* DDR40_PHY_CONTROL_REGS :: VDL_CALIBRATE :: calib_clocks [04:04] */ 2555 #define DDR40_PHY_CONTROL_REGS_VDL_CALIBRATE_CALIB_CLOCKS_MASK 0x00000010 2556 #define DDR40_PHY_CONTROL_REGS_VDL_CALIBRATE_CALIB_CLOCKS_ALIGN 0 2557 #define DDR40_PHY_CONTROL_REGS_VDL_CALIBRATE_CALIB_CLOCKS_BITS 1 2558 #define DDR40_PHY_CONTROL_REGS_VDL_CALIBRATE_CALIB_CLOCKS_SHIFT 4 2559 2560 /* DDR40_PHY_CONTROL_REGS :: VDL_CALIBRATE :: calib_test [03:03] */ 2561 #define DDR40_PHY_CONTROL_REGS_VDL_CALIBRATE_CALIB_TEST_MASK 0x00000008 2562 #define DDR40_PHY_CONTROL_REGS_VDL_CALIBRATE_CALIB_TEST_ALIGN 0 2563 #define DDR40_PHY_CONTROL_REGS_VDL_CALIBRATE_CALIB_TEST_BITS 1 2564 #define DDR40_PHY_CONTROL_REGS_VDL_CALIBRATE_CALIB_TEST_SHIFT 3 2565 2566 /* DDR40_PHY_CONTROL_REGS :: VDL_CALIBRATE :: calib_always [02:02] */ 2567 #define DDR40_PHY_CONTROL_REGS_VDL_CALIBRATE_CALIB_ALWAYS_MASK 0x00000004 2568 #define DDR40_PHY_CONTROL_REGS_VDL_CALIBRATE_CALIB_ALWAYS_ALIGN 0 2569 #define DDR40_PHY_CONTROL_REGS_VDL_CALIBRATE_CALIB_ALWAYS_BITS 1 2570 #define DDR40_PHY_CONTROL_REGS_VDL_CALIBRATE_CALIB_ALWAYS_SHIFT 2 2571 2572 /* DDR40_PHY_CONTROL_REGS :: VDL_CALIBRATE :: calib_once [01:01] */ 2573 #define DDR40_PHY_CONTROL_REGS_VDL_CALIBRATE_CALIB_ONCE_MASK 0x00000002 2574 #define DDR40_PHY_CONTROL_REGS_VDL_CALIBRATE_CALIB_ONCE_ALIGN 0 2575 #define DDR40_PHY_CONTROL_REGS_VDL_CALIBRATE_CALIB_ONCE_BITS 1 2576 #define DDR40_PHY_CONTROL_REGS_VDL_CALIBRATE_CALIB_ONCE_SHIFT 1 2577 2578 /* DDR40_PHY_CONTROL_REGS :: VDL_CALIBRATE :: calib_fast [00:00] */ 2579 #define DDR40_PHY_CONTROL_REGS_VDL_CALIBRATE_CALIB_FAST_MASK 0x00000001 2580 #define DDR40_PHY_CONTROL_REGS_VDL_CALIBRATE_CALIB_FAST_ALIGN 0 2581 #define DDR40_PHY_CONTROL_REGS_VDL_CALIBRATE_CALIB_FAST_BITS 1 2582 #define DDR40_PHY_CONTROL_REGS_VDL_CALIBRATE_CALIB_FAST_SHIFT 0 2583 2584 2585 /**************************************************************************** 2586 * DDR40_PHY_CONTROL_REGS :: VDL_CALIB_STATUS 2587 */ 2588 /* DDR40_PHY_CONTROL_REGS :: VDL_CALIB_STATUS :: reserved0 [31:30] */ 2589 #define DDR40_PHY_CONTROL_REGS_VDL_CALIB_STATUS_RESERVED0_MASK 0xc0000000 2590 #define DDR40_PHY_CONTROL_REGS_VDL_CALIB_STATUS_RESERVED0_ALIGN 0 2591 #define DDR40_PHY_CONTROL_REGS_VDL_CALIB_STATUS_RESERVED0_BITS 2 2592 #define DDR40_PHY_CONTROL_REGS_VDL_CALIB_STATUS_RESERVED0_SHIFT 30 2593 2594 /* DDR40_PHY_CONTROL_REGS :: VDL_CALIB_STATUS :: auto_init_fail [29:29] */ 2595 #define DDR40_PHY_CONTROL_REGS_VDL_CALIB_STATUS_AUTO_INIT_FAIL_MASK 0x20000000 2596 #define DDR40_PHY_CONTROL_REGS_VDL_CALIB_STATUS_AUTO_INIT_FAIL_ALIGN 0 2597 #define DDR40_PHY_CONTROL_REGS_VDL_CALIB_STATUS_AUTO_INIT_FAIL_BITS 1 2598 #define DDR40_PHY_CONTROL_REGS_VDL_CALIB_STATUS_AUTO_INIT_FAIL_SHIFT 29 2599 2600 /* DDR40_PHY_CONTROL_REGS :: VDL_CALIB_STATUS :: auto_init_done [28:28] */ 2601 #define DDR40_PHY_CONTROL_REGS_VDL_CALIB_STATUS_AUTO_INIT_DONE_MASK 0x10000000 2602 #define DDR40_PHY_CONTROL_REGS_VDL_CALIB_STATUS_AUTO_INIT_DONE_ALIGN 0 2603 #define DDR40_PHY_CONTROL_REGS_VDL_CALIB_STATUS_AUTO_INIT_DONE_BITS 1 2604 #define DDR40_PHY_CONTROL_REGS_VDL_CALIB_STATUS_AUTO_INIT_DONE_SHIFT 28 2605 2606 /* DDR40_PHY_CONTROL_REGS :: VDL_CALIB_STATUS :: calib_rd_data_dly_error [27:27] */ 2607 #define DDR40_PHY_CONTROL_REGS_VDL_CALIB_STATUS_CALIB_RD_DATA_DLY_ERROR_MASK 0x08000000 2608 #define DDR40_PHY_CONTROL_REGS_VDL_CALIB_STATUS_CALIB_RD_DATA_DLY_ERROR_ALIGN 0 2609 #define DDR40_PHY_CONTROL_REGS_VDL_CALIB_STATUS_CALIB_RD_DATA_DLY_ERROR_BITS 1 2610 #define DDR40_PHY_CONTROL_REGS_VDL_CALIB_STATUS_CALIB_RD_DATA_DLY_ERROR_SHIFT 27 2611 2612 /* DDR40_PHY_CONTROL_REGS :: VDL_CALIB_STATUS :: calib_read_en_error [26:23] */ 2613 #define DDR40_PHY_CONTROL_REGS_VDL_CALIB_STATUS_CALIB_READ_EN_ERROR_MASK 0x07800000 2614 #define DDR40_PHY_CONTROL_REGS_VDL_CALIB_STATUS_CALIB_READ_EN_ERROR_ALIGN 0 2615 #define DDR40_PHY_CONTROL_REGS_VDL_CALIB_STATUS_CALIB_READ_EN_ERROR_BITS 4 2616 #define DDR40_PHY_CONTROL_REGS_VDL_CALIB_STATUS_CALIB_READ_EN_ERROR_SHIFT 23 2617 2618 /* DDR40_PHY_CONTROL_REGS :: VDL_CALIB_STATUS :: calib_byte_error [22:19] */ 2619 #define DDR40_PHY_CONTROL_REGS_VDL_CALIB_STATUS_CALIB_BYTE_ERROR_MASK 0x00780000 2620 #define DDR40_PHY_CONTROL_REGS_VDL_CALIB_STATUS_CALIB_BYTE_ERROR_ALIGN 0 2621 #define DDR40_PHY_CONTROL_REGS_VDL_CALIB_STATUS_CALIB_BYTE_ERROR_BITS 4 2622 #define DDR40_PHY_CONTROL_REGS_VDL_CALIB_STATUS_CALIB_BYTE_ERROR_SHIFT 19 2623 2624 /* DDR40_PHY_CONTROL_REGS :: VDL_CALIB_STATUS :: calib_byte_sel [18:18] */ 2625 #define DDR40_PHY_CONTROL_REGS_VDL_CALIB_STATUS_CALIB_BYTE_SEL_MASK 0x00040000 2626 #define DDR40_PHY_CONTROL_REGS_VDL_CALIB_STATUS_CALIB_BYTE_SEL_ALIGN 0 2627 #define DDR40_PHY_CONTROL_REGS_VDL_CALIB_STATUS_CALIB_BYTE_SEL_BITS 1 2628 #define DDR40_PHY_CONTROL_REGS_VDL_CALIB_STATUS_CALIB_BYTE_SEL_SHIFT 18 2629 2630 /* DDR40_PHY_CONTROL_REGS :: VDL_CALIB_STATUS :: calib_bit_offset [17:12] */ 2631 #define DDR40_PHY_CONTROL_REGS_VDL_CALIB_STATUS_CALIB_BIT_OFFSET_MASK 0x0003f000 2632 #define DDR40_PHY_CONTROL_REGS_VDL_CALIB_STATUS_CALIB_BIT_OFFSET_ALIGN 0 2633 #define DDR40_PHY_CONTROL_REGS_VDL_CALIB_STATUS_CALIB_BIT_OFFSET_BITS 6 2634 #define DDR40_PHY_CONTROL_REGS_VDL_CALIB_STATUS_CALIB_BIT_OFFSET_SHIFT 12 2635 2636 /* DDR40_PHY_CONTROL_REGS :: VDL_CALIB_STATUS :: calib_total [11:02] */ 2637 #define DDR40_PHY_CONTROL_REGS_VDL_CALIB_STATUS_CALIB_TOTAL_MASK 0x00000ffc 2638 #define DDR40_PHY_CONTROL_REGS_VDL_CALIB_STATUS_CALIB_TOTAL_ALIGN 0 2639 #define DDR40_PHY_CONTROL_REGS_VDL_CALIB_STATUS_CALIB_TOTAL_BITS 10 2640 #define DDR40_PHY_CONTROL_REGS_VDL_CALIB_STATUS_CALIB_TOTAL_SHIFT 2 2641 2642 /* DDR40_PHY_CONTROL_REGS :: VDL_CALIB_STATUS :: calib_lock [01:01] */ 2643 #define DDR40_PHY_CONTROL_REGS_VDL_CALIB_STATUS_CALIB_LOCK_MASK 0x00000002 2644 #define DDR40_PHY_CONTROL_REGS_VDL_CALIB_STATUS_CALIB_LOCK_ALIGN 0 2645 #define DDR40_PHY_CONTROL_REGS_VDL_CALIB_STATUS_CALIB_LOCK_BITS 1 2646 #define DDR40_PHY_CONTROL_REGS_VDL_CALIB_STATUS_CALIB_LOCK_SHIFT 1 2647 2648 /* DDR40_PHY_CONTROL_REGS :: VDL_CALIB_STATUS :: calib_idle [00:00] */ 2649 #define DDR40_PHY_CONTROL_REGS_VDL_CALIB_STATUS_CALIB_IDLE_MASK 0x00000001 2650 #define DDR40_PHY_CONTROL_REGS_VDL_CALIB_STATUS_CALIB_IDLE_ALIGN 0 2651 #define DDR40_PHY_CONTROL_REGS_VDL_CALIB_STATUS_CALIB_IDLE_BITS 1 2652 #define DDR40_PHY_CONTROL_REGS_VDL_CALIB_STATUS_CALIB_IDLE_SHIFT 0 2653 2654 2655 /**************************************************************************** 2656 * DDR40_PHY_CONTROL_REGS :: VDL_DQ_CALIB_STATUS 2657 */ 2658 /* DDR40_PHY_CONTROL_REGS :: VDL_DQ_CALIB_STATUS :: reserved0 [31:26] */ 2659 #define DDR40_PHY_CONTROL_REGS_VDL_DQ_CALIB_STATUS_RESERVED0_MASK 0xfc000000 2660 #define DDR40_PHY_CONTROL_REGS_VDL_DQ_CALIB_STATUS_RESERVED0_ALIGN 0 2661 #define DDR40_PHY_CONTROL_REGS_VDL_DQ_CALIB_STATUS_RESERVED0_BITS 6 2662 #define DDR40_PHY_CONTROL_REGS_VDL_DQ_CALIB_STATUS_RESERVED0_SHIFT 26 2663 2664 /* DDR40_PHY_CONTROL_REGS :: VDL_DQ_CALIB_STATUS :: dqs_calib_total [25:16] */ 2665 #define DDR40_PHY_CONTROL_REGS_VDL_DQ_CALIB_STATUS_DQS_CALIB_TOTAL_MASK 0x03ff0000 2666 #define DDR40_PHY_CONTROL_REGS_VDL_DQ_CALIB_STATUS_DQS_CALIB_TOTAL_ALIGN 0 2667 #define DDR40_PHY_CONTROL_REGS_VDL_DQ_CALIB_STATUS_DQS_CALIB_TOTAL_BITS 10 2668 #define DDR40_PHY_CONTROL_REGS_VDL_DQ_CALIB_STATUS_DQS_CALIB_TOTAL_SHIFT 16 2669 2670 /* DDR40_PHY_CONTROL_REGS :: VDL_DQ_CALIB_STATUS :: reserved1 [15:14] */ 2671 #define DDR40_PHY_CONTROL_REGS_VDL_DQ_CALIB_STATUS_RESERVED1_MASK 0x0000c000 2672 #define DDR40_PHY_CONTROL_REGS_VDL_DQ_CALIB_STATUS_RESERVED1_ALIGN 0 2673 #define DDR40_PHY_CONTROL_REGS_VDL_DQ_CALIB_STATUS_RESERVED1_BITS 2 2674 #define DDR40_PHY_CONTROL_REGS_VDL_DQ_CALIB_STATUS_RESERVED1_SHIFT 14 2675 2676 /* DDR40_PHY_CONTROL_REGS :: VDL_DQ_CALIB_STATUS :: dq_calib_total [13:04] */ 2677 #define DDR40_PHY_CONTROL_REGS_VDL_DQ_CALIB_STATUS_DQ_CALIB_TOTAL_MASK 0x00003ff0 2678 #define DDR40_PHY_CONTROL_REGS_VDL_DQ_CALIB_STATUS_DQ_CALIB_TOTAL_ALIGN 0 2679 #define DDR40_PHY_CONTROL_REGS_VDL_DQ_CALIB_STATUS_DQ_CALIB_TOTAL_BITS 10 2680 #define DDR40_PHY_CONTROL_REGS_VDL_DQ_CALIB_STATUS_DQ_CALIB_TOTAL_SHIFT 4 2681 2682 /* DDR40_PHY_CONTROL_REGS :: VDL_DQ_CALIB_STATUS :: dqs_calib_clocks [03:03] */ 2683 #define DDR40_PHY_CONTROL_REGS_VDL_DQ_CALIB_STATUS_DQS_CALIB_CLOCKS_MASK 0x00000008 2684 #define DDR40_PHY_CONTROL_REGS_VDL_DQ_CALIB_STATUS_DQS_CALIB_CLOCKS_ALIGN 0 2685 #define DDR40_PHY_CONTROL_REGS_VDL_DQ_CALIB_STATUS_DQS_CALIB_CLOCKS_BITS 1 2686 #define DDR40_PHY_CONTROL_REGS_VDL_DQ_CALIB_STATUS_DQS_CALIB_CLOCKS_SHIFT 3 2687 2688 /* DDR40_PHY_CONTROL_REGS :: VDL_DQ_CALIB_STATUS :: dqs_calib_mode [02:02] */ 2689 #define DDR40_PHY_CONTROL_REGS_VDL_DQ_CALIB_STATUS_DQS_CALIB_MODE_MASK 0x00000004 2690 #define DDR40_PHY_CONTROL_REGS_VDL_DQ_CALIB_STATUS_DQS_CALIB_MODE_ALIGN 0 2691 #define DDR40_PHY_CONTROL_REGS_VDL_DQ_CALIB_STATUS_DQS_CALIB_MODE_BITS 1 2692 #define DDR40_PHY_CONTROL_REGS_VDL_DQ_CALIB_STATUS_DQS_CALIB_MODE_SHIFT 2 2693 2694 /* DDR40_PHY_CONTROL_REGS :: VDL_DQ_CALIB_STATUS :: dqs_calib_lock [01:01] */ 2695 #define DDR40_PHY_CONTROL_REGS_VDL_DQ_CALIB_STATUS_DQS_CALIB_LOCK_MASK 0x00000002 2696 #define DDR40_PHY_CONTROL_REGS_VDL_DQ_CALIB_STATUS_DQS_CALIB_LOCK_ALIGN 0 2697 #define DDR40_PHY_CONTROL_REGS_VDL_DQ_CALIB_STATUS_DQS_CALIB_LOCK_BITS 1 2698 #define DDR40_PHY_CONTROL_REGS_VDL_DQ_CALIB_STATUS_DQS_CALIB_LOCK_SHIFT 1 2699 2700 /* DDR40_PHY_CONTROL_REGS :: VDL_DQ_CALIB_STATUS :: dq_calib_lock [00:00] */ 2701 #define DDR40_PHY_CONTROL_REGS_VDL_DQ_CALIB_STATUS_DQ_CALIB_LOCK_MASK 0x00000001 2702 #define DDR40_PHY_CONTROL_REGS_VDL_DQ_CALIB_STATUS_DQ_CALIB_LOCK_ALIGN 0 2703 #define DDR40_PHY_CONTROL_REGS_VDL_DQ_CALIB_STATUS_DQ_CALIB_LOCK_BITS 1 2704 #define DDR40_PHY_CONTROL_REGS_VDL_DQ_CALIB_STATUS_DQ_CALIB_LOCK_SHIFT 0 2705 2706 2707 /**************************************************************************** 2708 * DDR40_PHY_CONTROL_REGS :: VDL_WR_CHAN_CALIB_STATUS 2709 */ 2710 /* DDR40_PHY_CONTROL_REGS :: VDL_WR_CHAN_CALIB_STATUS :: reserved0 [31:22] */ 2711 #define DDR40_PHY_CONTROL_REGS_VDL_WR_CHAN_CALIB_STATUS_RESERVED0_MASK 0xffc00000 2712 #define DDR40_PHY_CONTROL_REGS_VDL_WR_CHAN_CALIB_STATUS_RESERVED0_ALIGN 0 2713 #define DDR40_PHY_CONTROL_REGS_VDL_WR_CHAN_CALIB_STATUS_RESERVED0_BITS 10 2714 #define DDR40_PHY_CONTROL_REGS_VDL_WR_CHAN_CALIB_STATUS_RESERVED0_SHIFT 22 2715 2716 /* DDR40_PHY_CONTROL_REGS :: VDL_WR_CHAN_CALIB_STATUS :: wr_chan_calib_bit_offset [21:16] */ 2717 #define DDR40_PHY_CONTROL_REGS_VDL_WR_CHAN_CALIB_STATUS_WR_CHAN_CALIB_BIT_OFFSET_MASK 0x003f0000 2718 #define DDR40_PHY_CONTROL_REGS_VDL_WR_CHAN_CALIB_STATUS_WR_CHAN_CALIB_BIT_OFFSET_ALIGN 0 2719 #define DDR40_PHY_CONTROL_REGS_VDL_WR_CHAN_CALIB_STATUS_WR_CHAN_CALIB_BIT_OFFSET_BITS 6 2720 #define DDR40_PHY_CONTROL_REGS_VDL_WR_CHAN_CALIB_STATUS_WR_CHAN_CALIB_BIT_OFFSET_SHIFT 16 2721 2722 /* DDR40_PHY_CONTROL_REGS :: VDL_WR_CHAN_CALIB_STATUS :: reserved1 [15:14] */ 2723 #define DDR40_PHY_CONTROL_REGS_VDL_WR_CHAN_CALIB_STATUS_RESERVED1_MASK 0x0000c000 2724 #define DDR40_PHY_CONTROL_REGS_VDL_WR_CHAN_CALIB_STATUS_RESERVED1_ALIGN 0 2725 #define DDR40_PHY_CONTROL_REGS_VDL_WR_CHAN_CALIB_STATUS_RESERVED1_BITS 2 2726 #define DDR40_PHY_CONTROL_REGS_VDL_WR_CHAN_CALIB_STATUS_RESERVED1_SHIFT 14 2727 2728 /* DDR40_PHY_CONTROL_REGS :: VDL_WR_CHAN_CALIB_STATUS :: wr_chan_calib_total [13:04] */ 2729 #define DDR40_PHY_CONTROL_REGS_VDL_WR_CHAN_CALIB_STATUS_WR_CHAN_CALIB_TOTAL_MASK 0x00003ff0 2730 #define DDR40_PHY_CONTROL_REGS_VDL_WR_CHAN_CALIB_STATUS_WR_CHAN_CALIB_TOTAL_ALIGN 0 2731 #define DDR40_PHY_CONTROL_REGS_VDL_WR_CHAN_CALIB_STATUS_WR_CHAN_CALIB_TOTAL_BITS 10 2732 #define DDR40_PHY_CONTROL_REGS_VDL_WR_CHAN_CALIB_STATUS_WR_CHAN_CALIB_TOTAL_SHIFT 4 2733 2734 /* DDR40_PHY_CONTROL_REGS :: VDL_WR_CHAN_CALIB_STATUS :: reserved2 [03:03] */ 2735 #define DDR40_PHY_CONTROL_REGS_VDL_WR_CHAN_CALIB_STATUS_RESERVED2_MASK 0x00000008 2736 #define DDR40_PHY_CONTROL_REGS_VDL_WR_CHAN_CALIB_STATUS_RESERVED2_ALIGN 0 2737 #define DDR40_PHY_CONTROL_REGS_VDL_WR_CHAN_CALIB_STATUS_RESERVED2_BITS 1 2738 #define DDR40_PHY_CONTROL_REGS_VDL_WR_CHAN_CALIB_STATUS_RESERVED2_SHIFT 3 2739 2740 /* DDR40_PHY_CONTROL_REGS :: VDL_WR_CHAN_CALIB_STATUS :: wr_chan_calib_clocks [02:02] */ 2741 #define DDR40_PHY_CONTROL_REGS_VDL_WR_CHAN_CALIB_STATUS_WR_CHAN_CALIB_CLOCKS_MASK 0x00000004 2742 #define DDR40_PHY_CONTROL_REGS_VDL_WR_CHAN_CALIB_STATUS_WR_CHAN_CALIB_CLOCKS_ALIGN 0 2743 #define DDR40_PHY_CONTROL_REGS_VDL_WR_CHAN_CALIB_STATUS_WR_CHAN_CALIB_CLOCKS_BITS 1 2744 #define DDR40_PHY_CONTROL_REGS_VDL_WR_CHAN_CALIB_STATUS_WR_CHAN_CALIB_CLOCKS_SHIFT 2 2745 2746 /* DDR40_PHY_CONTROL_REGS :: VDL_WR_CHAN_CALIB_STATUS :: wr_chan_calib_byte_sel [01:01] */ 2747 #define DDR40_PHY_CONTROL_REGS_VDL_WR_CHAN_CALIB_STATUS_WR_CHAN_CALIB_BYTE_SEL_MASK 0x00000002 2748 #define DDR40_PHY_CONTROL_REGS_VDL_WR_CHAN_CALIB_STATUS_WR_CHAN_CALIB_BYTE_SEL_ALIGN 0 2749 #define DDR40_PHY_CONTROL_REGS_VDL_WR_CHAN_CALIB_STATUS_WR_CHAN_CALIB_BYTE_SEL_BITS 1 2750 #define DDR40_PHY_CONTROL_REGS_VDL_WR_CHAN_CALIB_STATUS_WR_CHAN_CALIB_BYTE_SEL_SHIFT 1 2751 2752 /* DDR40_PHY_CONTROL_REGS :: VDL_WR_CHAN_CALIB_STATUS :: wr_chan_calib_lock [00:00] */ 2753 #define DDR40_PHY_CONTROL_REGS_VDL_WR_CHAN_CALIB_STATUS_WR_CHAN_CALIB_LOCK_MASK 0x00000001 2754 #define DDR40_PHY_CONTROL_REGS_VDL_WR_CHAN_CALIB_STATUS_WR_CHAN_CALIB_LOCK_ALIGN 0 2755 #define DDR40_PHY_CONTROL_REGS_VDL_WR_CHAN_CALIB_STATUS_WR_CHAN_CALIB_LOCK_BITS 1 2756 #define DDR40_PHY_CONTROL_REGS_VDL_WR_CHAN_CALIB_STATUS_WR_CHAN_CALIB_LOCK_SHIFT 0 2757 2758 2759 /**************************************************************************** 2760 * DDR40_PHY_CONTROL_REGS :: VDL_RD_EN_CALIB_STATUS 2761 */ 2762 /* DDR40_PHY_CONTROL_REGS :: VDL_RD_EN_CALIB_STATUS :: reserved0 [31:22] */ 2763 #define DDR40_PHY_CONTROL_REGS_VDL_RD_EN_CALIB_STATUS_RESERVED0_MASK 0xffc00000 2764 #define DDR40_PHY_CONTROL_REGS_VDL_RD_EN_CALIB_STATUS_RESERVED0_ALIGN 0 2765 #define DDR40_PHY_CONTROL_REGS_VDL_RD_EN_CALIB_STATUS_RESERVED0_BITS 10 2766 #define DDR40_PHY_CONTROL_REGS_VDL_RD_EN_CALIB_STATUS_RESERVED0_SHIFT 22 2767 2768 /* DDR40_PHY_CONTROL_REGS :: VDL_RD_EN_CALIB_STATUS :: rd_en_calib_bit_offset [21:16] */ 2769 #define DDR40_PHY_CONTROL_REGS_VDL_RD_EN_CALIB_STATUS_RD_EN_CALIB_BIT_OFFSET_MASK 0x003f0000 2770 #define DDR40_PHY_CONTROL_REGS_VDL_RD_EN_CALIB_STATUS_RD_EN_CALIB_BIT_OFFSET_ALIGN 0 2771 #define DDR40_PHY_CONTROL_REGS_VDL_RD_EN_CALIB_STATUS_RD_EN_CALIB_BIT_OFFSET_BITS 6 2772 #define DDR40_PHY_CONTROL_REGS_VDL_RD_EN_CALIB_STATUS_RD_EN_CALIB_BIT_OFFSET_SHIFT 16 2773 2774 /* DDR40_PHY_CONTROL_REGS :: VDL_RD_EN_CALIB_STATUS :: reserved1 [15:14] */ 2775 #define DDR40_PHY_CONTROL_REGS_VDL_RD_EN_CALIB_STATUS_RESERVED1_MASK 0x0000c000 2776 #define DDR40_PHY_CONTROL_REGS_VDL_RD_EN_CALIB_STATUS_RESERVED1_ALIGN 0 2777 #define DDR40_PHY_CONTROL_REGS_VDL_RD_EN_CALIB_STATUS_RESERVED1_BITS 2 2778 #define DDR40_PHY_CONTROL_REGS_VDL_RD_EN_CALIB_STATUS_RESERVED1_SHIFT 14 2779 2780 /* DDR40_PHY_CONTROL_REGS :: VDL_RD_EN_CALIB_STATUS :: rd_en_calib_total [13:04] */ 2781 #define DDR40_PHY_CONTROL_REGS_VDL_RD_EN_CALIB_STATUS_RD_EN_CALIB_TOTAL_MASK 0x00003ff0 2782 #define DDR40_PHY_CONTROL_REGS_VDL_RD_EN_CALIB_STATUS_RD_EN_CALIB_TOTAL_ALIGN 0 2783 #define DDR40_PHY_CONTROL_REGS_VDL_RD_EN_CALIB_STATUS_RD_EN_CALIB_TOTAL_BITS 10 2784 #define DDR40_PHY_CONTROL_REGS_VDL_RD_EN_CALIB_STATUS_RD_EN_CALIB_TOTAL_SHIFT 4 2785 2786 /* DDR40_PHY_CONTROL_REGS :: VDL_RD_EN_CALIB_STATUS :: reserved2 [03:03] */ 2787 #define DDR40_PHY_CONTROL_REGS_VDL_RD_EN_CALIB_STATUS_RESERVED2_MASK 0x00000008 2788 #define DDR40_PHY_CONTROL_REGS_VDL_RD_EN_CALIB_STATUS_RESERVED2_ALIGN 0 2789 #define DDR40_PHY_CONTROL_REGS_VDL_RD_EN_CALIB_STATUS_RESERVED2_BITS 1 2790 #define DDR40_PHY_CONTROL_REGS_VDL_RD_EN_CALIB_STATUS_RESERVED2_SHIFT 3 2791 2792 /* DDR40_PHY_CONTROL_REGS :: VDL_RD_EN_CALIB_STATUS :: rd_en_calib_clocks [02:02] */ 2793 #define DDR40_PHY_CONTROL_REGS_VDL_RD_EN_CALIB_STATUS_RD_EN_CALIB_CLOCKS_MASK 0x00000004 2794 #define DDR40_PHY_CONTROL_REGS_VDL_RD_EN_CALIB_STATUS_RD_EN_CALIB_CLOCKS_ALIGN 0 2795 #define DDR40_PHY_CONTROL_REGS_VDL_RD_EN_CALIB_STATUS_RD_EN_CALIB_CLOCKS_BITS 1 2796 #define DDR40_PHY_CONTROL_REGS_VDL_RD_EN_CALIB_STATUS_RD_EN_CALIB_CLOCKS_SHIFT 2 2797 2798 /* DDR40_PHY_CONTROL_REGS :: VDL_RD_EN_CALIB_STATUS :: rd_en_calib_byte_sel [01:01] */ 2799 #define DDR40_PHY_CONTROL_REGS_VDL_RD_EN_CALIB_STATUS_RD_EN_CALIB_BYTE_SEL_MASK 0x00000002 2800 #define DDR40_PHY_CONTROL_REGS_VDL_RD_EN_CALIB_STATUS_RD_EN_CALIB_BYTE_SEL_ALIGN 0 2801 #define DDR40_PHY_CONTROL_REGS_VDL_RD_EN_CALIB_STATUS_RD_EN_CALIB_BYTE_SEL_BITS 1 2802 #define DDR40_PHY_CONTROL_REGS_VDL_RD_EN_CALIB_STATUS_RD_EN_CALIB_BYTE_SEL_SHIFT 1 2803 2804 /* DDR40_PHY_CONTROL_REGS :: VDL_RD_EN_CALIB_STATUS :: rd_en_calib_lock [00:00] */ 2805 #define DDR40_PHY_CONTROL_REGS_VDL_RD_EN_CALIB_STATUS_RD_EN_CALIB_LOCK_MASK 0x00000001 2806 #define DDR40_PHY_CONTROL_REGS_VDL_RD_EN_CALIB_STATUS_RD_EN_CALIB_LOCK_ALIGN 0 2807 #define DDR40_PHY_CONTROL_REGS_VDL_RD_EN_CALIB_STATUS_RD_EN_CALIB_LOCK_BITS 1 2808 #define DDR40_PHY_CONTROL_REGS_VDL_RD_EN_CALIB_STATUS_RD_EN_CALIB_LOCK_SHIFT 0 2809 2810 2811 /**************************************************************************** 2812 * DDR40_PHY_CONTROL_REGS :: VIRTUAL_VTT_CONTROL 2813 */ 2814 /* DDR40_PHY_CONTROL_REGS :: VIRTUAL_VTT_CONTROL :: reserved0 [31:06] */ 2815 #define DDR40_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_RESERVED0_MASK 0xffffffc0 2816 #define DDR40_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_RESERVED0_ALIGN 0 2817 #define DDR40_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_RESERVED0_BITS 26 2818 #define DDR40_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_RESERVED0_SHIFT 6 2819 2820 /* DDR40_PHY_CONTROL_REGS :: VIRTUAL_VTT_CONTROL :: low_vtt [05:05] */ 2821 #define DDR40_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_LOW_VTT_MASK 0x00000020 2822 #define DDR40_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_LOW_VTT_ALIGN 0 2823 #define DDR40_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_LOW_VTT_BITS 1 2824 #define DDR40_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_LOW_VTT_SHIFT 5 2825 2826 /* DDR40_PHY_CONTROL_REGS :: VIRTUAL_VTT_CONTROL :: high_vtt [04:04] */ 2827 #define DDR40_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_HIGH_VTT_MASK 0x00000010 2828 #define DDR40_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_HIGH_VTT_ALIGN 0 2829 #define DDR40_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_HIGH_VTT_BITS 1 2830 #define DDR40_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_HIGH_VTT_SHIFT 4 2831 2832 /* DDR40_PHY_CONTROL_REGS :: VIRTUAL_VTT_CONTROL :: error_reset [03:03] */ 2833 #define DDR40_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_ERROR_RESET_MASK 0x00000008 2834 #define DDR40_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_ERROR_RESET_ALIGN 0 2835 #define DDR40_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_ERROR_RESET_BITS 1 2836 #define DDR40_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_ERROR_RESET_SHIFT 3 2837 2838 /* DDR40_PHY_CONTROL_REGS :: VIRTUAL_VTT_CONTROL :: enable_ctl_idle [02:02] */ 2839 #define DDR40_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_ENABLE_CTL_IDLE_MASK 0x00000004 2840 #define DDR40_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_ENABLE_CTL_IDLE_ALIGN 0 2841 #define DDR40_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_ENABLE_CTL_IDLE_BITS 1 2842 #define DDR40_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_ENABLE_CTL_IDLE_SHIFT 2 2843 2844 /* DDR40_PHY_CONTROL_REGS :: VIRTUAL_VTT_CONTROL :: enable_cs_idle [01:01] */ 2845 #define DDR40_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_ENABLE_CS_IDLE_MASK 0x00000002 2846 #define DDR40_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_ENABLE_CS_IDLE_ALIGN 0 2847 #define DDR40_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_ENABLE_CS_IDLE_BITS 1 2848 #define DDR40_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_ENABLE_CS_IDLE_SHIFT 1 2849 2850 /* DDR40_PHY_CONTROL_REGS :: VIRTUAL_VTT_CONTROL :: enable_cke_idle [00:00] */ 2851 #define DDR40_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_ENABLE_CKE_IDLE_MASK 0x00000001 2852 #define DDR40_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_ENABLE_CKE_IDLE_ALIGN 0 2853 #define DDR40_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_ENABLE_CKE_IDLE_BITS 1 2854 #define DDR40_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_ENABLE_CKE_IDLE_SHIFT 0 2855 2856 2857 /**************************************************************************** 2858 * DDR40_PHY_CONTROL_REGS :: VIRTUAL_VTT_STATUS 2859 */ 2860 /* DDR40_PHY_CONTROL_REGS :: VIRTUAL_VTT_STATUS :: reserved0 [31:19] */ 2861 #define DDR40_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS_RESERVED0_MASK 0xfff80000 2862 #define DDR40_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS_RESERVED0_ALIGN 0 2863 #define DDR40_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS_RESERVED0_BITS 13 2864 #define DDR40_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS_RESERVED0_SHIFT 19 2865 2866 /* DDR40_PHY_CONTROL_REGS :: VIRTUAL_VTT_STATUS :: error [18:03] */ 2867 #define DDR40_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS_ERROR_MASK 0x0007fff8 2868 #define DDR40_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS_ERROR_ALIGN 0 2869 #define DDR40_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS_ERROR_BITS 16 2870 #define DDR40_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS_ERROR_SHIFT 3 2871 2872 /* DDR40_PHY_CONTROL_REGS :: VIRTUAL_VTT_STATUS :: error_low [02:02] */ 2873 #define DDR40_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS_ERROR_LOW_MASK 0x00000004 2874 #define DDR40_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS_ERROR_LOW_ALIGN 0 2875 #define DDR40_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS_ERROR_LOW_BITS 1 2876 #define DDR40_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS_ERROR_LOW_SHIFT 2 2877 2878 /* DDR40_PHY_CONTROL_REGS :: VIRTUAL_VTT_STATUS :: error_high [01:01] */ 2879 #define DDR40_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS_ERROR_HIGH_MASK 0x00000002 2880 #define DDR40_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS_ERROR_HIGH_ALIGN 0 2881 #define DDR40_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS_ERROR_HIGH_BITS 1 2882 #define DDR40_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS_ERROR_HIGH_SHIFT 1 2883 2884 /* DDR40_PHY_CONTROL_REGS :: VIRTUAL_VTT_STATUS :: ready [00:00] */ 2885 #define DDR40_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS_READY_MASK 0x00000001 2886 #define DDR40_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS_READY_ALIGN 0 2887 #define DDR40_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS_READY_BITS 1 2888 #define DDR40_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS_READY_SHIFT 0 2889 2890 2891 /**************************************************************************** 2892 * DDR40_PHY_CONTROL_REGS :: VIRTUAL_VTT_CONNECTIONS 2893 */ 2894 /* DDR40_PHY_CONTROL_REGS :: VIRTUAL_VTT_CONNECTIONS :: reserved0 [31:27] */ 2895 #define DDR40_PHY_CONTROL_REGS_VIRTUAL_VTT_CONNECTIONS_RESERVED0_MASK 0xf8000000 2896 #define DDR40_PHY_CONTROL_REGS_VIRTUAL_VTT_CONNECTIONS_RESERVED0_ALIGN 0 2897 #define DDR40_PHY_CONTROL_REGS_VIRTUAL_VTT_CONNECTIONS_RESERVED0_BITS 5 2898 #define DDR40_PHY_CONTROL_REGS_VIRTUAL_VTT_CONNECTIONS_RESERVED0_SHIFT 27 2899 2900 /* DDR40_PHY_CONTROL_REGS :: VIRTUAL_VTT_CONNECTIONS :: mask [26:00] */ 2901 #define DDR40_PHY_CONTROL_REGS_VIRTUAL_VTT_CONNECTIONS_MASK_MASK 0x07ffffff 2902 #define DDR40_PHY_CONTROL_REGS_VIRTUAL_VTT_CONNECTIONS_MASK_ALIGN 0 2903 #define DDR40_PHY_CONTROL_REGS_VIRTUAL_VTT_CONNECTIONS_MASK_BITS 27 2904 #define DDR40_PHY_CONTROL_REGS_VIRTUAL_VTT_CONNECTIONS_MASK_SHIFT 0 2905 2906 2907 /**************************************************************************** 2908 * DDR40_PHY_CONTROL_REGS :: VIRTUAL_VTT_OVERRIDE 2909 */ 2910 /* DDR40_PHY_CONTROL_REGS :: VIRTUAL_VTT_OVERRIDE :: reserved0 [31:27] */ 2911 #define DDR40_PHY_CONTROL_REGS_VIRTUAL_VTT_OVERRIDE_RESERVED0_MASK 0xf8000000 2912 #define DDR40_PHY_CONTROL_REGS_VIRTUAL_VTT_OVERRIDE_RESERVED0_ALIGN 0 2913 #define DDR40_PHY_CONTROL_REGS_VIRTUAL_VTT_OVERRIDE_RESERVED0_BITS 5 2914 #define DDR40_PHY_CONTROL_REGS_VIRTUAL_VTT_OVERRIDE_RESERVED0_SHIFT 27 2915 2916 /* DDR40_PHY_CONTROL_REGS :: VIRTUAL_VTT_OVERRIDE :: mask [26:00] */ 2917 #define DDR40_PHY_CONTROL_REGS_VIRTUAL_VTT_OVERRIDE_MASK_MASK 0x07ffffff 2918 #define DDR40_PHY_CONTROL_REGS_VIRTUAL_VTT_OVERRIDE_MASK_ALIGN 0 2919 #define DDR40_PHY_CONTROL_REGS_VIRTUAL_VTT_OVERRIDE_MASK_BITS 27 2920 #define DDR40_PHY_CONTROL_REGS_VIRTUAL_VTT_OVERRIDE_MASK_SHIFT 0 2921 2922 2923 /**************************************************************************** 2924 * DDR40_PHY_CONTROL_REGS :: VREF_DAC_CONTROL 2925 */ 2926 /* DDR40_PHY_CONTROL_REGS :: VREF_DAC_CONTROL :: reserved0 [31:21] */ 2927 #define DDR40_PHY_CONTROL_REGS_VREF_DAC_CONTROL_RESERVED0_MASK 0xffe00000 2928 #define DDR40_PHY_CONTROL_REGS_VREF_DAC_CONTROL_RESERVED0_ALIGN 0 2929 #define DDR40_PHY_CONTROL_REGS_VREF_DAC_CONTROL_RESERVED0_BITS 11 2930 #define DDR40_PHY_CONTROL_REGS_VREF_DAC_CONTROL_RESERVED0_SHIFT 21 2931 2932 /* DDR40_PHY_CONTROL_REGS :: VREF_DAC_CONTROL :: LDO_CK1_GT_INT [20:20] */ 2933 #define DDR40_PHY_CONTROL_REGS_VREF_DAC_CONTROL_LDO_CK1_GT_INT_MASK 0x00100000 2934 #define DDR40_PHY_CONTROL_REGS_VREF_DAC_CONTROL_LDO_CK1_GT_INT_ALIGN 0 2935 #define DDR40_PHY_CONTROL_REGS_VREF_DAC_CONTROL_LDO_CK1_GT_INT_BITS 1 2936 #define DDR40_PHY_CONTROL_REGS_VREF_DAC_CONTROL_LDO_CK1_GT_INT_SHIFT 20 2937 2938 /* DDR40_PHY_CONTROL_REGS :: VREF_DAC_CONTROL :: LDO_CK0_GT_INT [19:19] */ 2939 #define DDR40_PHY_CONTROL_REGS_VREF_DAC_CONTROL_LDO_CK0_GT_INT_MASK 0x00080000 2940 #define DDR40_PHY_CONTROL_REGS_VREF_DAC_CONTROL_LDO_CK0_GT_INT_ALIGN 0 2941 #define DDR40_PHY_CONTROL_REGS_VREF_DAC_CONTROL_LDO_CK0_GT_INT_BITS 1 2942 #define DDR40_PHY_CONTROL_REGS_VREF_DAC_CONTROL_LDO_CK0_GT_INT_SHIFT 19 2943 2944 /* DDR40_PHY_CONTROL_REGS :: VREF_DAC_CONTROL :: LDO_GT_INT [18:18] */ 2945 #define DDR40_PHY_CONTROL_REGS_VREF_DAC_CONTROL_LDO_GT_INT_MASK 0x00040000 2946 #define DDR40_PHY_CONTROL_REGS_VREF_DAC_CONTROL_LDO_GT_INT_ALIGN 0 2947 #define DDR40_PHY_CONTROL_REGS_VREF_DAC_CONTROL_LDO_GT_INT_BITS 1 2948 #define DDR40_PHY_CONTROL_REGS_VREF_DAC_CONTROL_LDO_GT_INT_SHIFT 18 2949 2950 /* DDR40_PHY_CONTROL_REGS :: VREF_DAC_CONTROL :: EXT_GT_INT [17:17] */ 2951 #define DDR40_PHY_CONTROL_REGS_VREF_DAC_CONTROL_EXT_GT_INT_MASK 0x00020000 2952 #define DDR40_PHY_CONTROL_REGS_VREF_DAC_CONTROL_EXT_GT_INT_ALIGN 0 2953 #define DDR40_PHY_CONTROL_REGS_VREF_DAC_CONTROL_EXT_GT_INT_BITS 1 2954 #define DDR40_PHY_CONTROL_REGS_VREF_DAC_CONTROL_EXT_GT_INT_SHIFT 17 2955 2956 /* DDR40_PHY_CONTROL_REGS :: VREF_DAC_CONTROL :: LDO_TESTOUT_MUX_CTL [16:15] */ 2957 #define DDR40_PHY_CONTROL_REGS_VREF_DAC_CONTROL_LDO_TESTOUT_MUX_CTL_MASK 0x00018000 2958 #define DDR40_PHY_CONTROL_REGS_VREF_DAC_CONTROL_LDO_TESTOUT_MUX_CTL_ALIGN 0 2959 #define DDR40_PHY_CONTROL_REGS_VREF_DAC_CONTROL_LDO_TESTOUT_MUX_CTL_BITS 2 2960 #define DDR40_PHY_CONTROL_REGS_VREF_DAC_CONTROL_LDO_TESTOUT_MUX_CTL_SHIFT 15 2961 2962 /* DDR40_PHY_CONTROL_REGS :: VREF_DAC_CONTROL :: TEST [14:14] */ 2963 #define DDR40_PHY_CONTROL_REGS_VREF_DAC_CONTROL_TEST_MASK 0x00004000 2964 #define DDR40_PHY_CONTROL_REGS_VREF_DAC_CONTROL_TEST_ALIGN 0 2965 #define DDR40_PHY_CONTROL_REGS_VREF_DAC_CONTROL_TEST_BITS 1 2966 #define DDR40_PHY_CONTROL_REGS_VREF_DAC_CONTROL_TEST_SHIFT 14 2967 2968 /* DDR40_PHY_CONTROL_REGS :: VREF_DAC_CONTROL :: PDN1 [13:13] */ 2969 #define DDR40_PHY_CONTROL_REGS_VREF_DAC_CONTROL_PDN1_MASK 0x00002000 2970 #define DDR40_PHY_CONTROL_REGS_VREF_DAC_CONTROL_PDN1_ALIGN 0 2971 #define DDR40_PHY_CONTROL_REGS_VREF_DAC_CONTROL_PDN1_BITS 1 2972 #define DDR40_PHY_CONTROL_REGS_VREF_DAC_CONTROL_PDN1_SHIFT 13 2973 2974 /* DDR40_PHY_CONTROL_REGS :: VREF_DAC_CONTROL :: PDN0 [12:12] */ 2975 #define DDR40_PHY_CONTROL_REGS_VREF_DAC_CONTROL_PDN0_MASK 0x00001000 2976 #define DDR40_PHY_CONTROL_REGS_VREF_DAC_CONTROL_PDN0_ALIGN 0 2977 #define DDR40_PHY_CONTROL_REGS_VREF_DAC_CONTROL_PDN0_BITS 1 2978 #define DDR40_PHY_CONTROL_REGS_VREF_DAC_CONTROL_PDN0_SHIFT 12 2979 2980 /* DDR40_PHY_CONTROL_REGS :: VREF_DAC_CONTROL :: DAC1 [11:06] */ 2981 #define DDR40_PHY_CONTROL_REGS_VREF_DAC_CONTROL_DAC1_MASK 0x00000fc0 2982 #define DDR40_PHY_CONTROL_REGS_VREF_DAC_CONTROL_DAC1_ALIGN 0 2983 #define DDR40_PHY_CONTROL_REGS_VREF_DAC_CONTROL_DAC1_BITS 6 2984 #define DDR40_PHY_CONTROL_REGS_VREF_DAC_CONTROL_DAC1_SHIFT 6 2985 2986 /* DDR40_PHY_CONTROL_REGS :: VREF_DAC_CONTROL :: DAC0 [05:00] */ 2987 #define DDR40_PHY_CONTROL_REGS_VREF_DAC_CONTROL_DAC0_MASK 0x0000003f 2988 #define DDR40_PHY_CONTROL_REGS_VREF_DAC_CONTROL_DAC0_ALIGN 0 2989 #define DDR40_PHY_CONTROL_REGS_VREF_DAC_CONTROL_DAC0_BITS 6 2990 #define DDR40_PHY_CONTROL_REGS_VREF_DAC_CONTROL_DAC0_SHIFT 0 2991 2992 2993 /**************************************************************************** 2994 * DDR40_PHY_CONTROL_REGS :: PHYBIST_CNTRL 2995 */ 2996 /* DDR40_PHY_CONTROL_REGS :: PHYBIST_CNTRL :: reserved0 [31:14] */ 2997 #define DDR40_PHY_CONTROL_REGS_PHYBIST_CNTRL_RESERVED0_MASK 0xffffc000 2998 #define DDR40_PHY_CONTROL_REGS_PHYBIST_CNTRL_RESERVED0_ALIGN 0 2999 #define DDR40_PHY_CONTROL_REGS_PHYBIST_CNTRL_RESERVED0_BITS 18 3000 #define DDR40_PHY_CONTROL_REGS_PHYBIST_CNTRL_RESERVED0_SHIFT 14 3001 3002 /* DDR40_PHY_CONTROL_REGS :: PHYBIST_CNTRL :: force_error_sel [13:08] */ 3003 #define DDR40_PHY_CONTROL_REGS_PHYBIST_CNTRL_FORCE_ERROR_SEL_MASK 0x00003f00 3004 #define DDR40_PHY_CONTROL_REGS_PHYBIST_CNTRL_FORCE_ERROR_SEL_ALIGN 0 3005 #define DDR40_PHY_CONTROL_REGS_PHYBIST_CNTRL_FORCE_ERROR_SEL_BITS 6 3006 #define DDR40_PHY_CONTROL_REGS_PHYBIST_CNTRL_FORCE_ERROR_SEL_SHIFT 8 3007 3008 /* DDR40_PHY_CONTROL_REGS :: PHYBIST_CNTRL :: reserved1 [07:05] */ 3009 #define DDR40_PHY_CONTROL_REGS_PHYBIST_CNTRL_RESERVED1_MASK 0x000000e0 3010 #define DDR40_PHY_CONTROL_REGS_PHYBIST_CNTRL_RESERVED1_ALIGN 0 3011 #define DDR40_PHY_CONTROL_REGS_PHYBIST_CNTRL_RESERVED1_BITS 3 3012 #define DDR40_PHY_CONTROL_REGS_PHYBIST_CNTRL_RESERVED1_SHIFT 5 3013 3014 /* DDR40_PHY_CONTROL_REGS :: PHYBIST_CNTRL :: bench_mode [04:04] */ 3015 #define DDR40_PHY_CONTROL_REGS_PHYBIST_CNTRL_BENCH_MODE_MASK 0x00000010 3016 #define DDR40_PHY_CONTROL_REGS_PHYBIST_CNTRL_BENCH_MODE_ALIGN 0 3017 #define DDR40_PHY_CONTROL_REGS_PHYBIST_CNTRL_BENCH_MODE_BITS 1 3018 #define DDR40_PHY_CONTROL_REGS_PHYBIST_CNTRL_BENCH_MODE_SHIFT 4 3019 3020 /* DDR40_PHY_CONTROL_REGS :: PHYBIST_CNTRL :: force_dat_error [03:03] */ 3021 #define DDR40_PHY_CONTROL_REGS_PHYBIST_CNTRL_FORCE_DAT_ERROR_MASK 0x00000008 3022 #define DDR40_PHY_CONTROL_REGS_PHYBIST_CNTRL_FORCE_DAT_ERROR_ALIGN 0 3023 #define DDR40_PHY_CONTROL_REGS_PHYBIST_CNTRL_FORCE_DAT_ERROR_BITS 1 3024 #define DDR40_PHY_CONTROL_REGS_PHYBIST_CNTRL_FORCE_DAT_ERROR_SHIFT 3 3025 3026 /* DDR40_PHY_CONTROL_REGS :: PHYBIST_CNTRL :: force_ctl_error [02:02] */ 3027 #define DDR40_PHY_CONTROL_REGS_PHYBIST_CNTRL_FORCE_CTL_ERROR_MASK 0x00000004 3028 #define DDR40_PHY_CONTROL_REGS_PHYBIST_CNTRL_FORCE_CTL_ERROR_ALIGN 0 3029 #define DDR40_PHY_CONTROL_REGS_PHYBIST_CNTRL_FORCE_CTL_ERROR_BITS 1 3030 #define DDR40_PHY_CONTROL_REGS_PHYBIST_CNTRL_FORCE_CTL_ERROR_SHIFT 2 3031 3032 /* DDR40_PHY_CONTROL_REGS :: PHYBIST_CNTRL :: int_loopback [01:01] */ 3033 #define DDR40_PHY_CONTROL_REGS_PHYBIST_CNTRL_INT_LOOPBACK_MASK 0x00000002 3034 #define DDR40_PHY_CONTROL_REGS_PHYBIST_CNTRL_INT_LOOPBACK_ALIGN 0 3035 #define DDR40_PHY_CONTROL_REGS_PHYBIST_CNTRL_INT_LOOPBACK_BITS 1 3036 #define DDR40_PHY_CONTROL_REGS_PHYBIST_CNTRL_INT_LOOPBACK_SHIFT 1 3037 3038 /* DDR40_PHY_CONTROL_REGS :: PHYBIST_CNTRL :: enable [00:00] */ 3039 #define DDR40_PHY_CONTROL_REGS_PHYBIST_CNTRL_ENABLE_MASK 0x00000001 3040 #define DDR40_PHY_CONTROL_REGS_PHYBIST_CNTRL_ENABLE_ALIGN 0 3041 #define DDR40_PHY_CONTROL_REGS_PHYBIST_CNTRL_ENABLE_BITS 1 3042 #define DDR40_PHY_CONTROL_REGS_PHYBIST_CNTRL_ENABLE_SHIFT 0 3043 3044 3045 /**************************************************************************** 3046 * DDR40_PHY_CONTROL_REGS :: PHYBIST_SEED 3047 */ 3048 /* DDR40_PHY_CONTROL_REGS :: PHYBIST_SEED :: seed [31:00] */ 3049 #define DDR40_PHY_CONTROL_REGS_PHYBIST_SEED_SEED_MASK 0xffffffff 3050 #define DDR40_PHY_CONTROL_REGS_PHYBIST_SEED_SEED_ALIGN 0 3051 #define DDR40_PHY_CONTROL_REGS_PHYBIST_SEED_SEED_BITS 32 3052 #define DDR40_PHY_CONTROL_REGS_PHYBIST_SEED_SEED_SHIFT 0 3053 3054 3055 /**************************************************************************** 3056 * DDR40_PHY_CONTROL_REGS :: PHYBIST_STATUS 3057 */ 3058 /* DDR40_PHY_CONTROL_REGS :: PHYBIST_STATUS :: reserved0 [31:04] */ 3059 #define DDR40_PHY_CONTROL_REGS_PHYBIST_STATUS_RESERVED0_MASK 0xfffffff0 3060 #define DDR40_PHY_CONTROL_REGS_PHYBIST_STATUS_RESERVED0_ALIGN 0 3061 #define DDR40_PHY_CONTROL_REGS_PHYBIST_STATUS_RESERVED0_BITS 28 3062 #define DDR40_PHY_CONTROL_REGS_PHYBIST_STATUS_RESERVED0_SHIFT 4 3063 3064 /* DDR40_PHY_CONTROL_REGS :: PHYBIST_STATUS :: dat_pass [03:03] */ 3065 #define DDR40_PHY_CONTROL_REGS_PHYBIST_STATUS_DAT_PASS_MASK 0x00000008 3066 #define DDR40_PHY_CONTROL_REGS_PHYBIST_STATUS_DAT_PASS_ALIGN 0 3067 #define DDR40_PHY_CONTROL_REGS_PHYBIST_STATUS_DAT_PASS_BITS 1 3068 #define DDR40_PHY_CONTROL_REGS_PHYBIST_STATUS_DAT_PASS_SHIFT 3 3069 3070 /* DDR40_PHY_CONTROL_REGS :: PHYBIST_STATUS :: ctl_pass [02:02] */ 3071 #define DDR40_PHY_CONTROL_REGS_PHYBIST_STATUS_CTL_PASS_MASK 0x00000004 3072 #define DDR40_PHY_CONTROL_REGS_PHYBIST_STATUS_CTL_PASS_ALIGN 0 3073 #define DDR40_PHY_CONTROL_REGS_PHYBIST_STATUS_CTL_PASS_BITS 1 3074 #define DDR40_PHY_CONTROL_REGS_PHYBIST_STATUS_CTL_PASS_SHIFT 2 3075 3076 /* DDR40_PHY_CONTROL_REGS :: PHYBIST_STATUS :: dat_done [01:01] */ 3077 #define DDR40_PHY_CONTROL_REGS_PHYBIST_STATUS_DAT_DONE_MASK 0x00000002 3078 #define DDR40_PHY_CONTROL_REGS_PHYBIST_STATUS_DAT_DONE_ALIGN 0 3079 #define DDR40_PHY_CONTROL_REGS_PHYBIST_STATUS_DAT_DONE_BITS 1 3080 #define DDR40_PHY_CONTROL_REGS_PHYBIST_STATUS_DAT_DONE_SHIFT 1 3081 3082 /* DDR40_PHY_CONTROL_REGS :: PHYBIST_STATUS :: ctl_done [00:00] */ 3083 #define DDR40_PHY_CONTROL_REGS_PHYBIST_STATUS_CTL_DONE_MASK 0x00000001 3084 #define DDR40_PHY_CONTROL_REGS_PHYBIST_STATUS_CTL_DONE_ALIGN 0 3085 #define DDR40_PHY_CONTROL_REGS_PHYBIST_STATUS_CTL_DONE_BITS 1 3086 #define DDR40_PHY_CONTROL_REGS_PHYBIST_STATUS_CTL_DONE_SHIFT 0 3087 3088 3089 /**************************************************************************** 3090 * DDR40_PHY_CONTROL_REGS :: PHYBIST_CTL_STATUS 3091 */ 3092 /* DDR40_PHY_CONTROL_REGS :: PHYBIST_CTL_STATUS :: reserved0 [31:27] */ 3093 #define DDR40_PHY_CONTROL_REGS_PHYBIST_CTL_STATUS_RESERVED0_MASK 0xf8000000 3094 #define DDR40_PHY_CONTROL_REGS_PHYBIST_CTL_STATUS_RESERVED0_ALIGN 0 3095 #define DDR40_PHY_CONTROL_REGS_PHYBIST_CTL_STATUS_RESERVED0_BITS 5 3096 #define DDR40_PHY_CONTROL_REGS_PHYBIST_CTL_STATUS_RESERVED0_SHIFT 27 3097 3098 /* DDR40_PHY_CONTROL_REGS :: PHYBIST_CTL_STATUS :: ctl_errors [26:00] */ 3099 #define DDR40_PHY_CONTROL_REGS_PHYBIST_CTL_STATUS_CTL_ERRORS_MASK 0x07ffffff 3100 #define DDR40_PHY_CONTROL_REGS_PHYBIST_CTL_STATUS_CTL_ERRORS_ALIGN 0 3101 #define DDR40_PHY_CONTROL_REGS_PHYBIST_CTL_STATUS_CTL_ERRORS_BITS 27 3102 #define DDR40_PHY_CONTROL_REGS_PHYBIST_CTL_STATUS_CTL_ERRORS_SHIFT 0 3103 3104 3105 /**************************************************************************** 3106 * DDR40_PHY_CONTROL_REGS :: PHYBIST_DQ_STATUS 3107 */ 3108 /* DDR40_PHY_CONTROL_REGS :: PHYBIST_DQ_STATUS :: dat_errors [31:00] */ 3109 #define DDR40_PHY_CONTROL_REGS_PHYBIST_DQ_STATUS_DAT_ERRORS_MASK 0xffffffff 3110 #define DDR40_PHY_CONTROL_REGS_PHYBIST_DQ_STATUS_DAT_ERRORS_ALIGN 0 3111 #define DDR40_PHY_CONTROL_REGS_PHYBIST_DQ_STATUS_DAT_ERRORS_BITS 32 3112 #define DDR40_PHY_CONTROL_REGS_PHYBIST_DQ_STATUS_DAT_ERRORS_SHIFT 0 3113 3114 3115 /**************************************************************************** 3116 * DDR40_PHY_CONTROL_REGS :: PHYBIST_MISC_STATUS 3117 */ 3118 /* DDR40_PHY_CONTROL_REGS :: PHYBIST_MISC_STATUS :: reserved0 [31:08] */ 3119 #define DDR40_PHY_CONTROL_REGS_PHYBIST_MISC_STATUS_RESERVED0_MASK 0xffffff00 3120 #define DDR40_PHY_CONTROL_REGS_PHYBIST_MISC_STATUS_RESERVED0_ALIGN 0 3121 #define DDR40_PHY_CONTROL_REGS_PHYBIST_MISC_STATUS_RESERVED0_BITS 24 3122 #define DDR40_PHY_CONTROL_REGS_PHYBIST_MISC_STATUS_RESERVED0_SHIFT 8 3123 3124 /* DDR40_PHY_CONTROL_REGS :: PHYBIST_MISC_STATUS :: ck_errors [07:04] */ 3125 #define DDR40_PHY_CONTROL_REGS_PHYBIST_MISC_STATUS_CK_ERRORS_MASK 0x000000f0 3126 #define DDR40_PHY_CONTROL_REGS_PHYBIST_MISC_STATUS_CK_ERRORS_ALIGN 0 3127 #define DDR40_PHY_CONTROL_REGS_PHYBIST_MISC_STATUS_CK_ERRORS_BITS 4 3128 #define DDR40_PHY_CONTROL_REGS_PHYBIST_MISC_STATUS_CK_ERRORS_SHIFT 4 3129 3130 /* DDR40_PHY_CONTROL_REGS :: PHYBIST_MISC_STATUS :: dm_errors [03:00] */ 3131 #define DDR40_PHY_CONTROL_REGS_PHYBIST_MISC_STATUS_DM_ERRORS_MASK 0x0000000f 3132 #define DDR40_PHY_CONTROL_REGS_PHYBIST_MISC_STATUS_DM_ERRORS_ALIGN 0 3133 #define DDR40_PHY_CONTROL_REGS_PHYBIST_MISC_STATUS_DM_ERRORS_BITS 4 3134 #define DDR40_PHY_CONTROL_REGS_PHYBIST_MISC_STATUS_DM_ERRORS_SHIFT 0 3135 3136 3137 /**************************************************************************** 3138 * DDR40_PHY_CONTROL_REGS :: COMMAND_REG 3139 */ 3140 /* DDR40_PHY_CONTROL_REGS :: COMMAND_REG :: reserved0 [31:25] */ 3141 #define DDR40_PHY_CONTROL_REGS_COMMAND_REG_RESERVED0_MASK 0xfe000000 3142 #define DDR40_PHY_CONTROL_REGS_COMMAND_REG_RESERVED0_ALIGN 0 3143 #define DDR40_PHY_CONTROL_REGS_COMMAND_REG_RESERVED0_BITS 7 3144 #define DDR40_PHY_CONTROL_REGS_COMMAND_REG_RESERVED0_SHIFT 25 3145 3146 /* DDR40_PHY_CONTROL_REGS :: COMMAND_REG :: aux [24:22] */ 3147 #define DDR40_PHY_CONTROL_REGS_COMMAND_REG_AUX_MASK 0x01c00000 3148 #define DDR40_PHY_CONTROL_REGS_COMMAND_REG_AUX_ALIGN 0 3149 #define DDR40_PHY_CONTROL_REGS_COMMAND_REG_AUX_BITS 3 3150 #define DDR40_PHY_CONTROL_REGS_COMMAND_REG_AUX_SHIFT 22 3151 3152 /* DDR40_PHY_CONTROL_REGS :: COMMAND_REG :: we [21:21] */ 3153 #define DDR40_PHY_CONTROL_REGS_COMMAND_REG_WE_MASK 0x00200000 3154 #define DDR40_PHY_CONTROL_REGS_COMMAND_REG_WE_ALIGN 0 3155 #define DDR40_PHY_CONTROL_REGS_COMMAND_REG_WE_BITS 1 3156 #define DDR40_PHY_CONTROL_REGS_COMMAND_REG_WE_SHIFT 21 3157 3158 /* DDR40_PHY_CONTROL_REGS :: COMMAND_REG :: cas [20:20] */ 3159 #define DDR40_PHY_CONTROL_REGS_COMMAND_REG_CAS_MASK 0x00100000 3160 #define DDR40_PHY_CONTROL_REGS_COMMAND_REG_CAS_ALIGN 0 3161 #define DDR40_PHY_CONTROL_REGS_COMMAND_REG_CAS_BITS 1 3162 #define DDR40_PHY_CONTROL_REGS_COMMAND_REG_CAS_SHIFT 20 3163 3164 /* DDR40_PHY_CONTROL_REGS :: COMMAND_REG :: ras [19:19] */ 3165 #define DDR40_PHY_CONTROL_REGS_COMMAND_REG_RAS_MASK 0x00080000 3166 #define DDR40_PHY_CONTROL_REGS_COMMAND_REG_RAS_ALIGN 0 3167 #define DDR40_PHY_CONTROL_REGS_COMMAND_REG_RAS_BITS 1 3168 #define DDR40_PHY_CONTROL_REGS_COMMAND_REG_RAS_SHIFT 19 3169 3170 /* DDR40_PHY_CONTROL_REGS :: COMMAND_REG :: ba [18:16] */ 3171 #define DDR40_PHY_CONTROL_REGS_COMMAND_REG_BA_MASK 0x00070000 3172 #define DDR40_PHY_CONTROL_REGS_COMMAND_REG_BA_ALIGN 0 3173 #define DDR40_PHY_CONTROL_REGS_COMMAND_REG_BA_BITS 3 3174 #define DDR40_PHY_CONTROL_REGS_COMMAND_REG_BA_SHIFT 16 3175 3176 /* DDR40_PHY_CONTROL_REGS :: COMMAND_REG :: ad [15:00] */ 3177 #define DDR40_PHY_CONTROL_REGS_COMMAND_REG_AD_MASK 0x0000ffff 3178 #define DDR40_PHY_CONTROL_REGS_COMMAND_REG_AD_ALIGN 0 3179 #define DDR40_PHY_CONTROL_REGS_COMMAND_REG_AD_BITS 16 3180 #define DDR40_PHY_CONTROL_REGS_COMMAND_REG_AD_SHIFT 0 3181 3182 3183 /**************************************************************************** 3184 * DDR40_PHY_CONTROL_REGS :: MODE_REG0 3185 */ 3186 /* DDR40_PHY_CONTROL_REGS :: MODE_REG0 :: reserved0 [31:17] */ 3187 #define DDR40_PHY_CONTROL_REGS_MODE_REG0_RESERVED0_MASK 0xfffe0000 3188 #define DDR40_PHY_CONTROL_REGS_MODE_REG0_RESERVED0_ALIGN 0 3189 #define DDR40_PHY_CONTROL_REGS_MODE_REG0_RESERVED0_BITS 15 3190 #define DDR40_PHY_CONTROL_REGS_MODE_REG0_RESERVED0_SHIFT 17 3191 3192 /* DDR40_PHY_CONTROL_REGS :: MODE_REG0 :: valid [16:16] */ 3193 #define DDR40_PHY_CONTROL_REGS_MODE_REG0_VALID_MASK 0x00010000 3194 #define DDR40_PHY_CONTROL_REGS_MODE_REG0_VALID_ALIGN 0 3195 #define DDR40_PHY_CONTROL_REGS_MODE_REG0_VALID_BITS 1 3196 #define DDR40_PHY_CONTROL_REGS_MODE_REG0_VALID_SHIFT 16 3197 3198 /* DDR40_PHY_CONTROL_REGS :: MODE_REG0 :: ad [15:00] */ 3199 #define DDR40_PHY_CONTROL_REGS_MODE_REG0_AD_MASK 0x0000ffff 3200 #define DDR40_PHY_CONTROL_REGS_MODE_REG0_AD_ALIGN 0 3201 #define DDR40_PHY_CONTROL_REGS_MODE_REG0_AD_BITS 16 3202 #define DDR40_PHY_CONTROL_REGS_MODE_REG0_AD_SHIFT 0 3203 3204 3205 /**************************************************************************** 3206 * DDR40_PHY_CONTROL_REGS :: MODE_REG1 3207 */ 3208 /* DDR40_PHY_CONTROL_REGS :: MODE_REG1 :: reserved0 [31:17] */ 3209 #define DDR40_PHY_CONTROL_REGS_MODE_REG1_RESERVED0_MASK 0xfffe0000 3210 #define DDR40_PHY_CONTROL_REGS_MODE_REG1_RESERVED0_ALIGN 0 3211 #define DDR40_PHY_CONTROL_REGS_MODE_REG1_RESERVED0_BITS 15 3212 #define DDR40_PHY_CONTROL_REGS_MODE_REG1_RESERVED0_SHIFT 17 3213 3214 /* DDR40_PHY_CONTROL_REGS :: MODE_REG1 :: valid [16:16] */ 3215 #define DDR40_PHY_CONTROL_REGS_MODE_REG1_VALID_MASK 0x00010000 3216 #define DDR40_PHY_CONTROL_REGS_MODE_REG1_VALID_ALIGN 0 3217 #define DDR40_PHY_CONTROL_REGS_MODE_REG1_VALID_BITS 1 3218 #define DDR40_PHY_CONTROL_REGS_MODE_REG1_VALID_SHIFT 16 3219 3220 /* DDR40_PHY_CONTROL_REGS :: MODE_REG1 :: ad [15:00] */ 3221 #define DDR40_PHY_CONTROL_REGS_MODE_REG1_AD_MASK 0x0000ffff 3222 #define DDR40_PHY_CONTROL_REGS_MODE_REG1_AD_ALIGN 0 3223 #define DDR40_PHY_CONTROL_REGS_MODE_REG1_AD_BITS 16 3224 #define DDR40_PHY_CONTROL_REGS_MODE_REG1_AD_SHIFT 0 3225 3226 3227 /**************************************************************************** 3228 * DDR40_PHY_CONTROL_REGS :: MODE_REG2 3229 */ 3230 /* DDR40_PHY_CONTROL_REGS :: MODE_REG2 :: reserved0 [31:17] */ 3231 #define DDR40_PHY_CONTROL_REGS_MODE_REG2_RESERVED0_MASK 0xfffe0000 3232 #define DDR40_PHY_CONTROL_REGS_MODE_REG2_RESERVED0_ALIGN 0 3233 #define DDR40_PHY_CONTROL_REGS_MODE_REG2_RESERVED0_BITS 15 3234 #define DDR40_PHY_CONTROL_REGS_MODE_REG2_RESERVED0_SHIFT 17 3235 3236 /* DDR40_PHY_CONTROL_REGS :: MODE_REG2 :: valid [16:16] */ 3237 #define DDR40_PHY_CONTROL_REGS_MODE_REG2_VALID_MASK 0x00010000 3238 #define DDR40_PHY_CONTROL_REGS_MODE_REG2_VALID_ALIGN 0 3239 #define DDR40_PHY_CONTROL_REGS_MODE_REG2_VALID_BITS 1 3240 #define DDR40_PHY_CONTROL_REGS_MODE_REG2_VALID_SHIFT 16 3241 3242 /* DDR40_PHY_CONTROL_REGS :: MODE_REG2 :: ad [15:00] */ 3243 #define DDR40_PHY_CONTROL_REGS_MODE_REG2_AD_MASK 0x0000ffff 3244 #define DDR40_PHY_CONTROL_REGS_MODE_REG2_AD_ALIGN 0 3245 #define DDR40_PHY_CONTROL_REGS_MODE_REG2_AD_BITS 16 3246 #define DDR40_PHY_CONTROL_REGS_MODE_REG2_AD_SHIFT 0 3247 3248 3249 /**************************************************************************** 3250 * DDR40_PHY_CONTROL_REGS :: MODE_REG3 3251 */ 3252 /* DDR40_PHY_CONTROL_REGS :: MODE_REG3 :: reserved0 [31:17] */ 3253 #define DDR40_PHY_CONTROL_REGS_MODE_REG3_RESERVED0_MASK 0xfffe0000 3254 #define DDR40_PHY_CONTROL_REGS_MODE_REG3_RESERVED0_ALIGN 0 3255 #define DDR40_PHY_CONTROL_REGS_MODE_REG3_RESERVED0_BITS 15 3256 #define DDR40_PHY_CONTROL_REGS_MODE_REG3_RESERVED0_SHIFT 17 3257 3258 /* DDR40_PHY_CONTROL_REGS :: MODE_REG3 :: valid [16:16] */ 3259 #define DDR40_PHY_CONTROL_REGS_MODE_REG3_VALID_MASK 0x00010000 3260 #define DDR40_PHY_CONTROL_REGS_MODE_REG3_VALID_ALIGN 0 3261 #define DDR40_PHY_CONTROL_REGS_MODE_REG3_VALID_BITS 1 3262 #define DDR40_PHY_CONTROL_REGS_MODE_REG3_VALID_SHIFT 16 3263 3264 /* DDR40_PHY_CONTROL_REGS :: MODE_REG3 :: ad [15:00] */ 3265 #define DDR40_PHY_CONTROL_REGS_MODE_REG3_AD_MASK 0x0000ffff 3266 #define DDR40_PHY_CONTROL_REGS_MODE_REG3_AD_ALIGN 0 3267 #define DDR40_PHY_CONTROL_REGS_MODE_REG3_AD_BITS 16 3268 #define DDR40_PHY_CONTROL_REGS_MODE_REG3_AD_SHIFT 0 3269 3270 3271 /**************************************************************************** 3272 * DDR40_PHY_CONTROL_REGS :: STANDBY_CONTROL 3273 */ 3274 /* DDR40_PHY_CONTROL_REGS :: STANDBY_CONTROL :: reserved0 [31:19] */ 3275 #define DDR40_PHY_CONTROL_REGS_STANDBY_CONTROL_RESERVED0_MASK 0xfff80000 3276 #define DDR40_PHY_CONTROL_REGS_STANDBY_CONTROL_RESERVED0_ALIGN 0 3277 #define DDR40_PHY_CONTROL_REGS_STANDBY_CONTROL_RESERVED0_BITS 13 3278 #define DDR40_PHY_CONTROL_REGS_STANDBY_CONTROL_RESERVED0_SHIFT 19 3279 3280 /* DDR40_PHY_CONTROL_REGS :: STANDBY_CONTROL :: standby_ready [18:18] */ 3281 #define DDR40_PHY_CONTROL_REGS_STANDBY_CONTROL_STANDBY_READY_MASK 0x00040000 3282 #define DDR40_PHY_CONTROL_REGS_STANDBY_CONTROL_STANDBY_READY_ALIGN 0 3283 #define DDR40_PHY_CONTROL_REGS_STANDBY_CONTROL_STANDBY_READY_BITS 1 3284 #define DDR40_PHY_CONTROL_REGS_STANDBY_CONTROL_STANDBY_READY_SHIFT 18 3285 3286 /* DDR40_PHY_CONTROL_REGS :: STANDBY_CONTROL :: standby_exit_pin_en [17:17] */ 3287 #define DDR40_PHY_CONTROL_REGS_STANDBY_CONTROL_STANDBY_EXIT_PIN_EN_MASK 0x00020000 3288 #define DDR40_PHY_CONTROL_REGS_STANDBY_CONTROL_STANDBY_EXIT_PIN_EN_ALIGN 0 3289 #define DDR40_PHY_CONTROL_REGS_STANDBY_CONTROL_STANDBY_EXIT_PIN_EN_BITS 1 3290 #define DDR40_PHY_CONTROL_REGS_STANDBY_CONTROL_STANDBY_EXIT_PIN_EN_SHIFT 17 3291 3292 /* DDR40_PHY_CONTROL_REGS :: STANDBY_CONTROL :: standby_active [16:16] */ 3293 #define DDR40_PHY_CONTROL_REGS_STANDBY_CONTROL_STANDBY_ACTIVE_MASK 0x00010000 3294 #define DDR40_PHY_CONTROL_REGS_STANDBY_CONTROL_STANDBY_ACTIVE_ALIGN 0 3295 #define DDR40_PHY_CONTROL_REGS_STANDBY_CONTROL_STANDBY_ACTIVE_BITS 1 3296 #define DDR40_PHY_CONTROL_REGS_STANDBY_CONTROL_STANDBY_ACTIVE_SHIFT 16 3297 3298 /* DDR40_PHY_CONTROL_REGS :: STANDBY_CONTROL :: armed [15:15] */ 3299 #define DDR40_PHY_CONTROL_REGS_STANDBY_CONTROL_ARMED_MASK 0x00008000 3300 #define DDR40_PHY_CONTROL_REGS_STANDBY_CONTROL_ARMED_ALIGN 0 3301 #define DDR40_PHY_CONTROL_REGS_STANDBY_CONTROL_ARMED_BITS 1 3302 #define DDR40_PHY_CONTROL_REGS_STANDBY_CONTROL_ARMED_SHIFT 15 3303 3304 /* DDR40_PHY_CONTROL_REGS :: STANDBY_CONTROL :: warmstart [14:14] */ 3305 #define DDR40_PHY_CONTROL_REGS_STANDBY_CONTROL_WARMSTART_MASK 0x00004000 3306 #define DDR40_PHY_CONTROL_REGS_STANDBY_CONTROL_WARMSTART_ALIGN 0 3307 #define DDR40_PHY_CONTROL_REGS_STANDBY_CONTROL_WARMSTART_BITS 1 3308 #define DDR40_PHY_CONTROL_REGS_STANDBY_CONTROL_WARMSTART_SHIFT 14 3309 3310 /* DDR40_PHY_CONTROL_REGS :: STANDBY_CONTROL :: pwrdown_ldo_volts [13:12] */ 3311 #define DDR40_PHY_CONTROL_REGS_STANDBY_CONTROL_PWRDOWN_LDO_VOLTS_MASK 0x00003000 3312 #define DDR40_PHY_CONTROL_REGS_STANDBY_CONTROL_PWRDOWN_LDO_VOLTS_ALIGN 0 3313 #define DDR40_PHY_CONTROL_REGS_STANDBY_CONTROL_PWRDOWN_LDO_VOLTS_BITS 2 3314 #define DDR40_PHY_CONTROL_REGS_STANDBY_CONTROL_PWRDOWN_LDO_VOLTS_SHIFT 12 3315 3316 /* DDR40_PHY_CONTROL_REGS :: STANDBY_CONTROL :: pwrdown_skip_mrs [11:11] */ 3317 #define DDR40_PHY_CONTROL_REGS_STANDBY_CONTROL_PWRDOWN_SKIP_MRS_MASK 0x00000800 3318 #define DDR40_PHY_CONTROL_REGS_STANDBY_CONTROL_PWRDOWN_SKIP_MRS_ALIGN 0 3319 #define DDR40_PHY_CONTROL_REGS_STANDBY_CONTROL_PWRDOWN_SKIP_MRS_BITS 1 3320 #define DDR40_PHY_CONTROL_REGS_STANDBY_CONTROL_PWRDOWN_SKIP_MRS_SHIFT 11 3321 3322 /* DDR40_PHY_CONTROL_REGS :: STANDBY_CONTROL :: pwrdown_rst_n [10:10] */ 3323 #define DDR40_PHY_CONTROL_REGS_STANDBY_CONTROL_PWRDOWN_RST_N_MASK 0x00000400 3324 #define DDR40_PHY_CONTROL_REGS_STANDBY_CONTROL_PWRDOWN_RST_N_ALIGN 0 3325 #define DDR40_PHY_CONTROL_REGS_STANDBY_CONTROL_PWRDOWN_RST_N_BITS 1 3326 #define DDR40_PHY_CONTROL_REGS_STANDBY_CONTROL_PWRDOWN_RST_N_SHIFT 10 3327 3328 /* DDR40_PHY_CONTROL_REGS :: STANDBY_CONTROL :: pwrdown_cke [09:09] */ 3329 #define DDR40_PHY_CONTROL_REGS_STANDBY_CONTROL_PWRDOWN_CKE_MASK 0x00000200 3330 #define DDR40_PHY_CONTROL_REGS_STANDBY_CONTROL_PWRDOWN_CKE_ALIGN 0 3331 #define DDR40_PHY_CONTROL_REGS_STANDBY_CONTROL_PWRDOWN_CKE_BITS 1 3332 #define DDR40_PHY_CONTROL_REGS_STANDBY_CONTROL_PWRDOWN_CKE_SHIFT 9 3333 3334 /* DDR40_PHY_CONTROL_REGS :: STANDBY_CONTROL :: ldo_volts [08:07] */ 3335 #define DDR40_PHY_CONTROL_REGS_STANDBY_CONTROL_LDO_VOLTS_MASK 0x00000180 3336 #define DDR40_PHY_CONTROL_REGS_STANDBY_CONTROL_LDO_VOLTS_ALIGN 0 3337 #define DDR40_PHY_CONTROL_REGS_STANDBY_CONTROL_LDO_VOLTS_BITS 2 3338 #define DDR40_PHY_CONTROL_REGS_STANDBY_CONTROL_LDO_VOLTS_SHIFT 7 3339 3340 /* DDR40_PHY_CONTROL_REGS :: STANDBY_CONTROL :: skip_mrs [06:06] */ 3341 #define DDR40_PHY_CONTROL_REGS_STANDBY_CONTROL_SKIP_MRS_MASK 0x00000040 3342 #define DDR40_PHY_CONTROL_REGS_STANDBY_CONTROL_SKIP_MRS_ALIGN 0 3343 #define DDR40_PHY_CONTROL_REGS_STANDBY_CONTROL_SKIP_MRS_BITS 1 3344 #define DDR40_PHY_CONTROL_REGS_STANDBY_CONTROL_SKIP_MRS_SHIFT 6 3345 3346 /* DDR40_PHY_CONTROL_REGS :: STANDBY_CONTROL :: rst_n [05:05] */ 3347 #define DDR40_PHY_CONTROL_REGS_STANDBY_CONTROL_RST_N_MASK 0x00000020 3348 #define DDR40_PHY_CONTROL_REGS_STANDBY_CONTROL_RST_N_ALIGN 0 3349 #define DDR40_PHY_CONTROL_REGS_STANDBY_CONTROL_RST_N_BITS 1 3350 #define DDR40_PHY_CONTROL_REGS_STANDBY_CONTROL_RST_N_SHIFT 5 3351 3352 /* DDR40_PHY_CONTROL_REGS :: STANDBY_CONTROL :: cke [04:04] */ 3353 #define DDR40_PHY_CONTROL_REGS_STANDBY_CONTROL_CKE_MASK 0x00000010 3354 #define DDR40_PHY_CONTROL_REGS_STANDBY_CONTROL_CKE_ALIGN 0 3355 #define DDR40_PHY_CONTROL_REGS_STANDBY_CONTROL_CKE_BITS 1 3356 #define DDR40_PHY_CONTROL_REGS_STANDBY_CONTROL_CKE_SHIFT 4 3357 3358 /* DDR40_PHY_CONTROL_REGS :: STANDBY_CONTROL :: standby [03:00] */ 3359 #define DDR40_PHY_CONTROL_REGS_STANDBY_CONTROL_STANDBY_MASK 0x0000000f 3360 #define DDR40_PHY_CONTROL_REGS_STANDBY_CONTROL_STANDBY_ALIGN 0 3361 #define DDR40_PHY_CONTROL_REGS_STANDBY_CONTROL_STANDBY_BITS 4 3362 #define DDR40_PHY_CONTROL_REGS_STANDBY_CONTROL_STANDBY_SHIFT 0 3363 3364 3365 /**************************************************************************** 3366 * DDR40_PHY_CONTROL_REGS :: STRAP_CONTROL 3367 */ 3368 /* DDR40_PHY_CONTROL_REGS :: STRAP_CONTROL :: reserved0 [31:28] */ 3369 #define DDR40_PHY_CONTROL_REGS_STRAP_CONTROL_RESERVED0_MASK 0xf0000000 3370 #define DDR40_PHY_CONTROL_REGS_STRAP_CONTROL_RESERVED0_ALIGN 0 3371 #define DDR40_PHY_CONTROL_REGS_STRAP_CONTROL_RESERVED0_BITS 4 3372 #define DDR40_PHY_CONTROL_REGS_STRAP_CONTROL_RESERVED0_SHIFT 28 3373 3374 /* DDR40_PHY_CONTROL_REGS :: STRAP_CONTROL :: mhz [27:16] */ 3375 #define DDR40_PHY_CONTROL_REGS_STRAP_CONTROL_MHZ_MASK 0x0fff0000 3376 #define DDR40_PHY_CONTROL_REGS_STRAP_CONTROL_MHZ_ALIGN 0 3377 #define DDR40_PHY_CONTROL_REGS_STRAP_CONTROL_MHZ_BITS 12 3378 #define DDR40_PHY_CONTROL_REGS_STRAP_CONTROL_MHZ_SHIFT 16 3379 3380 /* DDR40_PHY_CONTROL_REGS :: STRAP_CONTROL :: ad_width [15:14] */ 3381 #define DDR40_PHY_CONTROL_REGS_STRAP_CONTROL_AD_WIDTH_MASK 0x0000c000 3382 #define DDR40_PHY_CONTROL_REGS_STRAP_CONTROL_AD_WIDTH_ALIGN 0 3383 #define DDR40_PHY_CONTROL_REGS_STRAP_CONTROL_AD_WIDTH_BITS 2 3384 #define DDR40_PHY_CONTROL_REGS_STRAP_CONTROL_AD_WIDTH_SHIFT 14 3385 3386 /* DDR40_PHY_CONTROL_REGS :: STRAP_CONTROL :: dual_rank [13:13] */ 3387 #define DDR40_PHY_CONTROL_REGS_STRAP_CONTROL_DUAL_RANK_MASK 0x00002000 3388 #define DDR40_PHY_CONTROL_REGS_STRAP_CONTROL_DUAL_RANK_ALIGN 0 3389 #define DDR40_PHY_CONTROL_REGS_STRAP_CONTROL_DUAL_RANK_BITS 1 3390 #define DDR40_PHY_CONTROL_REGS_STRAP_CONTROL_DUAL_RANK_SHIFT 13 3391 3392 /* DDR40_PHY_CONTROL_REGS :: STRAP_CONTROL :: bus16 [12:12] */ 3393 #define DDR40_PHY_CONTROL_REGS_STRAP_CONTROL_BUS16_MASK 0x00001000 3394 #define DDR40_PHY_CONTROL_REGS_STRAP_CONTROL_BUS16_ALIGN 0 3395 #define DDR40_PHY_CONTROL_REGS_STRAP_CONTROL_BUS16_BITS 1 3396 #define DDR40_PHY_CONTROL_REGS_STRAP_CONTROL_BUS16_SHIFT 12 3397 3398 /* DDR40_PHY_CONTROL_REGS :: STRAP_CONTROL :: bus8 [11:11] */ 3399 #define DDR40_PHY_CONTROL_REGS_STRAP_CONTROL_BUS8_MASK 0x00000800 3400 #define DDR40_PHY_CONTROL_REGS_STRAP_CONTROL_BUS8_ALIGN 0 3401 #define DDR40_PHY_CONTROL_REGS_STRAP_CONTROL_BUS8_BITS 1 3402 #define DDR40_PHY_CONTROL_REGS_STRAP_CONTROL_BUS8_SHIFT 11 3403 3404 /* DDR40_PHY_CONTROL_REGS :: STRAP_CONTROL :: chip_width [10:10] */ 3405 #define DDR40_PHY_CONTROL_REGS_STRAP_CONTROL_CHIP_WIDTH_MASK 0x00000400 3406 #define DDR40_PHY_CONTROL_REGS_STRAP_CONTROL_CHIP_WIDTH_ALIGN 0 3407 #define DDR40_PHY_CONTROL_REGS_STRAP_CONTROL_CHIP_WIDTH_BITS 1 3408 #define DDR40_PHY_CONTROL_REGS_STRAP_CONTROL_CHIP_WIDTH_SHIFT 10 3409 3410 /* DDR40_PHY_CONTROL_REGS :: STRAP_CONTROL :: vddq [09:08] */ 3411 #define DDR40_PHY_CONTROL_REGS_STRAP_CONTROL_VDDQ_MASK 0x00000300 3412 #define DDR40_PHY_CONTROL_REGS_STRAP_CONTROL_VDDQ_ALIGN 0 3413 #define DDR40_PHY_CONTROL_REGS_STRAP_CONTROL_VDDQ_BITS 2 3414 #define DDR40_PHY_CONTROL_REGS_STRAP_CONTROL_VDDQ_SHIFT 8 3415 3416 /* DDR40_PHY_CONTROL_REGS :: STRAP_CONTROL :: chip_size [07:06] */ 3417 #define DDR40_PHY_CONTROL_REGS_STRAP_CONTROL_CHIP_SIZE_MASK 0x000000c0 3418 #define DDR40_PHY_CONTROL_REGS_STRAP_CONTROL_CHIP_SIZE_ALIGN 0 3419 #define DDR40_PHY_CONTROL_REGS_STRAP_CONTROL_CHIP_SIZE_BITS 2 3420 #define DDR40_PHY_CONTROL_REGS_STRAP_CONTROL_CHIP_SIZE_SHIFT 6 3421 3422 /* DDR40_PHY_CONTROL_REGS :: STRAP_CONTROL :: jedec_type [05:01] */ 3423 #define DDR40_PHY_CONTROL_REGS_STRAP_CONTROL_JEDEC_TYPE_MASK 0x0000003e 3424 #define DDR40_PHY_CONTROL_REGS_STRAP_CONTROL_JEDEC_TYPE_ALIGN 0 3425 #define DDR40_PHY_CONTROL_REGS_STRAP_CONTROL_JEDEC_TYPE_BITS 5 3426 #define DDR40_PHY_CONTROL_REGS_STRAP_CONTROL_JEDEC_TYPE_SHIFT 1 3427 3428 /* DDR40_PHY_CONTROL_REGS :: STRAP_CONTROL :: straps_valid [00:00] */ 3429 #define DDR40_PHY_CONTROL_REGS_STRAP_CONTROL_STRAPS_VALID_MASK 0x00000001 3430 #define DDR40_PHY_CONTROL_REGS_STRAP_CONTROL_STRAPS_VALID_ALIGN 0 3431 #define DDR40_PHY_CONTROL_REGS_STRAP_CONTROL_STRAPS_VALID_BITS 1 3432 #define DDR40_PHY_CONTROL_REGS_STRAP_CONTROL_STRAPS_VALID_SHIFT 0 3433 3434 3435 /**************************************************************************** 3436 * DDR40_PHY_CONTROL_REGS :: STRAP_CONTROL2 3437 */ 3438 /* DDR40_PHY_CONTROL_REGS :: STRAP_CONTROL2 :: reserved0 [31:21] */ 3439 #define DDR40_PHY_CONTROL_REGS_STRAP_CONTROL2_RESERVED0_MASK 0xffe00000 3440 #define DDR40_PHY_CONTROL_REGS_STRAP_CONTROL2_RESERVED0_ALIGN 0 3441 #define DDR40_PHY_CONTROL_REGS_STRAP_CONTROL2_RESERVED0_BITS 11 3442 #define DDR40_PHY_CONTROL_REGS_STRAP_CONTROL2_RESERVED0_SHIFT 21 3443 3444 /* DDR40_PHY_CONTROL_REGS :: STRAP_CONTROL2 :: ddr3 [20:20] */ 3445 #define DDR40_PHY_CONTROL_REGS_STRAP_CONTROL2_DDR3_MASK 0x00100000 3446 #define DDR40_PHY_CONTROL_REGS_STRAP_CONTROL2_DDR3_ALIGN 0 3447 #define DDR40_PHY_CONTROL_REGS_STRAP_CONTROL2_DDR3_BITS 1 3448 #define DDR40_PHY_CONTROL_REGS_STRAP_CONTROL2_DDR3_SHIFT 20 3449 3450 /* DDR40_PHY_CONTROL_REGS :: STRAP_CONTROL2 :: al [19:17] */ 3451 #define DDR40_PHY_CONTROL_REGS_STRAP_CONTROL2_AL_MASK 0x000e0000 3452 #define DDR40_PHY_CONTROL_REGS_STRAP_CONTROL2_AL_ALIGN 0 3453 #define DDR40_PHY_CONTROL_REGS_STRAP_CONTROL2_AL_BITS 3 3454 #define DDR40_PHY_CONTROL_REGS_STRAP_CONTROL2_AL_SHIFT 17 3455 3456 /* DDR40_PHY_CONTROL_REGS :: STRAP_CONTROL2 :: wr [16:12] */ 3457 #define DDR40_PHY_CONTROL_REGS_STRAP_CONTROL2_WR_MASK 0x0001f000 3458 #define DDR40_PHY_CONTROL_REGS_STRAP_CONTROL2_WR_ALIGN 0 3459 #define DDR40_PHY_CONTROL_REGS_STRAP_CONTROL2_WR_BITS 5 3460 #define DDR40_PHY_CONTROL_REGS_STRAP_CONTROL2_WR_SHIFT 12 3461 3462 /* DDR40_PHY_CONTROL_REGS :: STRAP_CONTROL2 :: cwl [11:07] */ 3463 #define DDR40_PHY_CONTROL_REGS_STRAP_CONTROL2_CWL_MASK 0x00000f80 3464 #define DDR40_PHY_CONTROL_REGS_STRAP_CONTROL2_CWL_ALIGN 0 3465 #define DDR40_PHY_CONTROL_REGS_STRAP_CONTROL2_CWL_BITS 5 3466 #define DDR40_PHY_CONTROL_REGS_STRAP_CONTROL2_CWL_SHIFT 7 3467 3468 /* DDR40_PHY_CONTROL_REGS :: STRAP_CONTROL2 :: cl [06:00] */ 3469 #define DDR40_PHY_CONTROL_REGS_STRAP_CONTROL2_CL_MASK 0x0000007f 3470 #define DDR40_PHY_CONTROL_REGS_STRAP_CONTROL2_CL_ALIGN 0 3471 #define DDR40_PHY_CONTROL_REGS_STRAP_CONTROL2_CL_BITS 7 3472 #define DDR40_PHY_CONTROL_REGS_STRAP_CONTROL2_CL_SHIFT 0 3473 3474 3475 /**************************************************************************** 3476 * DDR40_PHY_CONTROL_REGS :: STRAP_STATUS 3477 */ 3478 /* DDR40_PHY_CONTROL_REGS :: STRAP_STATUS :: reserved0 [31:30] */ 3479 #define DDR40_PHY_CONTROL_REGS_STRAP_STATUS_RESERVED0_MASK 0xc0000000 3480 #define DDR40_PHY_CONTROL_REGS_STRAP_STATUS_RESERVED0_ALIGN 0 3481 #define DDR40_PHY_CONTROL_REGS_STRAP_STATUS_RESERVED0_BITS 2 3482 #define DDR40_PHY_CONTROL_REGS_STRAP_STATUS_RESERVED0_SHIFT 30 3483 3484 /* DDR40_PHY_CONTROL_REGS :: STRAP_STATUS :: from_reg [29:29] */ 3485 #define DDR40_PHY_CONTROL_REGS_STRAP_STATUS_FROM_REG_MASK 0x20000000 3486 #define DDR40_PHY_CONTROL_REGS_STRAP_STATUS_FROM_REG_ALIGN 0 3487 #define DDR40_PHY_CONTROL_REGS_STRAP_STATUS_FROM_REG_BITS 1 3488 #define DDR40_PHY_CONTROL_REGS_STRAP_STATUS_FROM_REG_SHIFT 29 3489 3490 /* DDR40_PHY_CONTROL_REGS :: STRAP_STATUS :: from_memc [28:28] */ 3491 #define DDR40_PHY_CONTROL_REGS_STRAP_STATUS_FROM_MEMC_MASK 0x10000000 3492 #define DDR40_PHY_CONTROL_REGS_STRAP_STATUS_FROM_MEMC_ALIGN 0 3493 #define DDR40_PHY_CONTROL_REGS_STRAP_STATUS_FROM_MEMC_BITS 1 3494 #define DDR40_PHY_CONTROL_REGS_STRAP_STATUS_FROM_MEMC_SHIFT 28 3495 3496 /* DDR40_PHY_CONTROL_REGS :: STRAP_STATUS :: mhz [27:16] */ 3497 #define DDR40_PHY_CONTROL_REGS_STRAP_STATUS_MHZ_MASK 0x0fff0000 3498 #define DDR40_PHY_CONTROL_REGS_STRAP_STATUS_MHZ_ALIGN 0 3499 #define DDR40_PHY_CONTROL_REGS_STRAP_STATUS_MHZ_BITS 12 3500 #define DDR40_PHY_CONTROL_REGS_STRAP_STATUS_MHZ_SHIFT 16 3501 3502 /* DDR40_PHY_CONTROL_REGS :: STRAP_STATUS :: ad_width [15:14] */ 3503 #define DDR40_PHY_CONTROL_REGS_STRAP_STATUS_AD_WIDTH_MASK 0x0000c000 3504 #define DDR40_PHY_CONTROL_REGS_STRAP_STATUS_AD_WIDTH_ALIGN 0 3505 #define DDR40_PHY_CONTROL_REGS_STRAP_STATUS_AD_WIDTH_BITS 2 3506 #define DDR40_PHY_CONTROL_REGS_STRAP_STATUS_AD_WIDTH_SHIFT 14 3507 3508 /* DDR40_PHY_CONTROL_REGS :: STRAP_STATUS :: dual_rank [13:13] */ 3509 #define DDR40_PHY_CONTROL_REGS_STRAP_STATUS_DUAL_RANK_MASK 0x00002000 3510 #define DDR40_PHY_CONTROL_REGS_STRAP_STATUS_DUAL_RANK_ALIGN 0 3511 #define DDR40_PHY_CONTROL_REGS_STRAP_STATUS_DUAL_RANK_BITS 1 3512 #define DDR40_PHY_CONTROL_REGS_STRAP_STATUS_DUAL_RANK_SHIFT 13 3513 3514 /* DDR40_PHY_CONTROL_REGS :: STRAP_STATUS :: bus16 [12:12] */ 3515 #define DDR40_PHY_CONTROL_REGS_STRAP_STATUS_BUS16_MASK 0x00001000 3516 #define DDR40_PHY_CONTROL_REGS_STRAP_STATUS_BUS16_ALIGN 0 3517 #define DDR40_PHY_CONTROL_REGS_STRAP_STATUS_BUS16_BITS 1 3518 #define DDR40_PHY_CONTROL_REGS_STRAP_STATUS_BUS16_SHIFT 12 3519 3520 /* DDR40_PHY_CONTROL_REGS :: STRAP_STATUS :: bus8 [11:11] */ 3521 #define DDR40_PHY_CONTROL_REGS_STRAP_STATUS_BUS8_MASK 0x00000800 3522 #define DDR40_PHY_CONTROL_REGS_STRAP_STATUS_BUS8_ALIGN 0 3523 #define DDR40_PHY_CONTROL_REGS_STRAP_STATUS_BUS8_BITS 1 3524 #define DDR40_PHY_CONTROL_REGS_STRAP_STATUS_BUS8_SHIFT 11 3525 3526 /* DDR40_PHY_CONTROL_REGS :: STRAP_STATUS :: chip_width [10:10] */ 3527 #define DDR40_PHY_CONTROL_REGS_STRAP_STATUS_CHIP_WIDTH_MASK 0x00000400 3528 #define DDR40_PHY_CONTROL_REGS_STRAP_STATUS_CHIP_WIDTH_ALIGN 0 3529 #define DDR40_PHY_CONTROL_REGS_STRAP_STATUS_CHIP_WIDTH_BITS 1 3530 #define DDR40_PHY_CONTROL_REGS_STRAP_STATUS_CHIP_WIDTH_SHIFT 10 3531 3532 /* DDR40_PHY_CONTROL_REGS :: STRAP_STATUS :: vddq [09:08] */ 3533 #define DDR40_PHY_CONTROL_REGS_STRAP_STATUS_VDDQ_MASK 0x00000300 3534 #define DDR40_PHY_CONTROL_REGS_STRAP_STATUS_VDDQ_ALIGN 0 3535 #define DDR40_PHY_CONTROL_REGS_STRAP_STATUS_VDDQ_BITS 2 3536 #define DDR40_PHY_CONTROL_REGS_STRAP_STATUS_VDDQ_SHIFT 8 3537 3538 /* DDR40_PHY_CONTROL_REGS :: STRAP_STATUS :: chip_size [07:06] */ 3539 #define DDR40_PHY_CONTROL_REGS_STRAP_STATUS_CHIP_SIZE_MASK 0x000000c0 3540 #define DDR40_PHY_CONTROL_REGS_STRAP_STATUS_CHIP_SIZE_ALIGN 0 3541 #define DDR40_PHY_CONTROL_REGS_STRAP_STATUS_CHIP_SIZE_BITS 2 3542 #define DDR40_PHY_CONTROL_REGS_STRAP_STATUS_CHIP_SIZE_SHIFT 6 3543 3544 /* DDR40_PHY_CONTROL_REGS :: STRAP_STATUS :: jedec_type [05:01] */ 3545 #define DDR40_PHY_CONTROL_REGS_STRAP_STATUS_JEDEC_TYPE_MASK 0x0000003e 3546 #define DDR40_PHY_CONTROL_REGS_STRAP_STATUS_JEDEC_TYPE_ALIGN 0 3547 #define DDR40_PHY_CONTROL_REGS_STRAP_STATUS_JEDEC_TYPE_BITS 5 3548 #define DDR40_PHY_CONTROL_REGS_STRAP_STATUS_JEDEC_TYPE_SHIFT 1 3549 3550 /* DDR40_PHY_CONTROL_REGS :: STRAP_STATUS :: straps_valid [00:00] */ 3551 #define DDR40_PHY_CONTROL_REGS_STRAP_STATUS_STRAPS_VALID_MASK 0x00000001 3552 #define DDR40_PHY_CONTROL_REGS_STRAP_STATUS_STRAPS_VALID_ALIGN 0 3553 #define DDR40_PHY_CONTROL_REGS_STRAP_STATUS_STRAPS_VALID_BITS 1 3554 #define DDR40_PHY_CONTROL_REGS_STRAP_STATUS_STRAPS_VALID_SHIFT 0 3555 3556 3557 /**************************************************************************** 3558 * DDR40_PHY_CONTROL_REGS :: STRAP_STATUS2 3559 */ 3560 /* DDR40_PHY_CONTROL_REGS :: STRAP_STATUS2 :: reserved0 [31:21] */ 3561 #define DDR40_PHY_CONTROL_REGS_STRAP_STATUS2_RESERVED0_MASK 0xffe00000 3562 #define DDR40_PHY_CONTROL_REGS_STRAP_STATUS2_RESERVED0_ALIGN 0 3563 #define DDR40_PHY_CONTROL_REGS_STRAP_STATUS2_RESERVED0_BITS 11 3564 #define DDR40_PHY_CONTROL_REGS_STRAP_STATUS2_RESERVED0_SHIFT 21 3565 3566 /* DDR40_PHY_CONTROL_REGS :: STRAP_STATUS2 :: ddr3 [20:20] */ 3567 #define DDR40_PHY_CONTROL_REGS_STRAP_STATUS2_DDR3_MASK 0x00100000 3568 #define DDR40_PHY_CONTROL_REGS_STRAP_STATUS2_DDR3_ALIGN 0 3569 #define DDR40_PHY_CONTROL_REGS_STRAP_STATUS2_DDR3_BITS 1 3570 #define DDR40_PHY_CONTROL_REGS_STRAP_STATUS2_DDR3_SHIFT 20 3571 3572 /* DDR40_PHY_CONTROL_REGS :: STRAP_STATUS2 :: al [19:17] */ 3573 #define DDR40_PHY_CONTROL_REGS_STRAP_STATUS2_AL_MASK 0x000e0000 3574 #define DDR40_PHY_CONTROL_REGS_STRAP_STATUS2_AL_ALIGN 0 3575 #define DDR40_PHY_CONTROL_REGS_STRAP_STATUS2_AL_BITS 3 3576 #define DDR40_PHY_CONTROL_REGS_STRAP_STATUS2_AL_SHIFT 17 3577 3578 /* DDR40_PHY_CONTROL_REGS :: STRAP_STATUS2 :: wr [16:12] */ 3579 #define DDR40_PHY_CONTROL_REGS_STRAP_STATUS2_WR_MASK 0x0001f000 3580 #define DDR40_PHY_CONTROL_REGS_STRAP_STATUS2_WR_ALIGN 0 3581 #define DDR40_PHY_CONTROL_REGS_STRAP_STATUS2_WR_BITS 5 3582 #define DDR40_PHY_CONTROL_REGS_STRAP_STATUS2_WR_SHIFT 12 3583 3584 /* DDR40_PHY_CONTROL_REGS :: STRAP_STATUS2 :: cwl [11:07] */ 3585 #define DDR40_PHY_CONTROL_REGS_STRAP_STATUS2_CWL_MASK 0x00000f80 3586 #define DDR40_PHY_CONTROL_REGS_STRAP_STATUS2_CWL_ALIGN 0 3587 #define DDR40_PHY_CONTROL_REGS_STRAP_STATUS2_CWL_BITS 5 3588 #define DDR40_PHY_CONTROL_REGS_STRAP_STATUS2_CWL_SHIFT 7 3589 3590 /* DDR40_PHY_CONTROL_REGS :: STRAP_STATUS2 :: cl [06:00] */ 3591 #define DDR40_PHY_CONTROL_REGS_STRAP_STATUS2_CL_MASK 0x0000007f 3592 #define DDR40_PHY_CONTROL_REGS_STRAP_STATUS2_CL_ALIGN 0 3593 #define DDR40_PHY_CONTROL_REGS_STRAP_STATUS2_CL_BITS 7 3594 #define DDR40_PHY_CONTROL_REGS_STRAP_STATUS2_CL_SHIFT 0 3595 3596 3597 /**************************************************************************** 3598 * DDR40_PHY_CONTROL_REGS :: DEBUG_FREEZE_ENABLE 3599 */ 3600 /* DDR40_PHY_CONTROL_REGS :: DEBUG_FREEZE_ENABLE :: reserved0 [31:04] */ 3601 #define DDR40_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE_RESERVED0_MASK 0xfffffff0 3602 #define DDR40_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE_RESERVED0_ALIGN 0 3603 #define DDR40_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE_RESERVED0_BITS 28 3604 #define DDR40_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE_RESERVED0_SHIFT 4 3605 3606 /* DDR40_PHY_CONTROL_REGS :: DEBUG_FREEZE_ENABLE :: wl1_bl1 [03:03] */ 3607 #define DDR40_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE_WL1_BL1_MASK 0x00000008 3608 #define DDR40_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE_WL1_BL1_ALIGN 0 3609 #define DDR40_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE_WL1_BL1_BITS 1 3610 #define DDR40_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE_WL1_BL1_SHIFT 3 3611 3612 /* DDR40_PHY_CONTROL_REGS :: DEBUG_FREEZE_ENABLE :: wl1_bl0 [02:02] */ 3613 #define DDR40_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE_WL1_BL0_MASK 0x00000004 3614 #define DDR40_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE_WL1_BL0_ALIGN 0 3615 #define DDR40_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE_WL1_BL0_BITS 1 3616 #define DDR40_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE_WL1_BL0_SHIFT 2 3617 3618 /* DDR40_PHY_CONTROL_REGS :: DEBUG_FREEZE_ENABLE :: wl0_bl1 [01:01] */ 3619 #define DDR40_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE_WL0_BL1_MASK 0x00000002 3620 #define DDR40_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE_WL0_BL1_ALIGN 0 3621 #define DDR40_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE_WL0_BL1_BITS 1 3622 #define DDR40_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE_WL0_BL1_SHIFT 1 3623 3624 /* DDR40_PHY_CONTROL_REGS :: DEBUG_FREEZE_ENABLE :: wl0_bl0 [00:00] */ 3625 #define DDR40_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE_WL0_BL0_MASK 0x00000001 3626 #define DDR40_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE_WL0_BL0_ALIGN 0 3627 #define DDR40_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE_WL0_BL0_BITS 1 3628 #define DDR40_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE_WL0_BL0_SHIFT 0 3629 3630 3631 /**************************************************************************** 3632 * DDR40_PHY_CONTROL_REGS :: DATAPATH_LOOPBACK 3633 */ 3634 /* DDR40_PHY_CONTROL_REGS :: DATAPATH_LOOPBACK :: reserved0 [31:03] */ 3635 #define DDR40_PHY_CONTROL_REGS_DATAPATH_LOOPBACK_RESERVED0_MASK 0xfffffff8 3636 #define DDR40_PHY_CONTROL_REGS_DATAPATH_LOOPBACK_RESERVED0_ALIGN 0 3637 #define DDR40_PHY_CONTROL_REGS_DATAPATH_LOOPBACK_RESERVED0_BITS 29 3638 #define DDR40_PHY_CONTROL_REGS_DATAPATH_LOOPBACK_RESERVED0_SHIFT 3 3639 3640 /* DDR40_PHY_CONTROL_REGS :: DATAPATH_LOOPBACK :: xor_dm_rd_en [02:02] */ 3641 #define DDR40_PHY_CONTROL_REGS_DATAPATH_LOOPBACK_XOR_DM_RD_EN_MASK 0x00000004 3642 #define DDR40_PHY_CONTROL_REGS_DATAPATH_LOOPBACK_XOR_DM_RD_EN_ALIGN 0 3643 #define DDR40_PHY_CONTROL_REGS_DATAPATH_LOOPBACK_XOR_DM_RD_EN_BITS 1 3644 #define DDR40_PHY_CONTROL_REGS_DATAPATH_LOOPBACK_XOR_DM_RD_EN_SHIFT 2 3645 3646 /* DDR40_PHY_CONTROL_REGS :: DATAPATH_LOOPBACK :: use_addr_ctl [01:01] */ 3647 #define DDR40_PHY_CONTROL_REGS_DATAPATH_LOOPBACK_USE_ADDR_CTL_MASK 0x00000002 3648 #define DDR40_PHY_CONTROL_REGS_DATAPATH_LOOPBACK_USE_ADDR_CTL_ALIGN 0 3649 #define DDR40_PHY_CONTROL_REGS_DATAPATH_LOOPBACK_USE_ADDR_CTL_BITS 1 3650 #define DDR40_PHY_CONTROL_REGS_DATAPATH_LOOPBACK_USE_ADDR_CTL_SHIFT 1 3651 3652 /* DDR40_PHY_CONTROL_REGS :: DATAPATH_LOOPBACK :: enable [00:00] */ 3653 #define DDR40_PHY_CONTROL_REGS_DATAPATH_LOOPBACK_ENABLE_MASK 0x00000001 3654 #define DDR40_PHY_CONTROL_REGS_DATAPATH_LOOPBACK_ENABLE_ALIGN 0 3655 #define DDR40_PHY_CONTROL_REGS_DATAPATH_LOOPBACK_ENABLE_BITS 1 3656 #define DDR40_PHY_CONTROL_REGS_DATAPATH_LOOPBACK_ENABLE_SHIFT 0 3657 3658 3659 /**************************************************************************** 3660 * DDR40_PHY_DDR40_PHY_WORD_LANE_0 3661 */ 3662 /**************************************************************************** 3663 * DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE_RD_EN 3664 */ 3665 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE_RD_EN :: busy [31:31] */ 3666 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE_RD_EN_BUSY_MASK 0x80000000 3667 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE_RD_EN_BUSY_ALIGN 0 3668 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE_RD_EN_BUSY_BITS 1 3669 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE_RD_EN_BUSY_SHIFT 31 3670 3671 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE_RD_EN :: reserved0 [30:18] */ 3672 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE_RD_EN_RESERVED0_MASK 0x7ffc0000 3673 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE_RD_EN_RESERVED0_ALIGN 0 3674 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE_RD_EN_RESERVED0_BITS 13 3675 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE_RD_EN_RESERVED0_SHIFT 18 3676 3677 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE_RD_EN :: ovr_force [17:17] */ 3678 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE_RD_EN_OVR_FORCE_MASK 0x00020000 3679 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE_RD_EN_OVR_FORCE_ALIGN 0 3680 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE_RD_EN_OVR_FORCE_BITS 1 3681 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE_RD_EN_OVR_FORCE_SHIFT 17 3682 3683 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE_RD_EN :: ovr_en [16:16] */ 3684 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE_RD_EN_OVR_EN_MASK 0x00010000 3685 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE_RD_EN_OVR_EN_ALIGN 0 3686 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE_RD_EN_OVR_EN_BITS 1 3687 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE_RD_EN_OVR_EN_SHIFT 16 3688 3689 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE_RD_EN :: reserved1 [15:09] */ 3690 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE_RD_EN_RESERVED1_MASK 0x0000fe00 3691 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE_RD_EN_RESERVED1_ALIGN 0 3692 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE_RD_EN_RESERVED1_BITS 7 3693 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE_RD_EN_RESERVED1_SHIFT 9 3694 3695 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE_RD_EN :: byte_sel [08:08] */ 3696 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE_RD_EN_BYTE_SEL_MASK 0x00000100 3697 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE_RD_EN_BYTE_SEL_ALIGN 0 3698 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE_RD_EN_BYTE_SEL_BITS 1 3699 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE_RD_EN_BYTE_SEL_SHIFT 8 3700 3701 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE_RD_EN :: reserved2 [07:06] */ 3702 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE_RD_EN_RESERVED2_MASK 0x000000c0 3703 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE_RD_EN_RESERVED2_ALIGN 0 3704 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE_RD_EN_RESERVED2_BITS 2 3705 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE_RD_EN_RESERVED2_SHIFT 6 3706 3707 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE_RD_EN :: ovr_step [05:00] */ 3708 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE_RD_EN_OVR_STEP_MASK 0x0000003f 3709 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE_RD_EN_OVR_STEP_ALIGN 0 3710 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE_RD_EN_OVR_STEP_BITS 6 3711 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE_RD_EN_OVR_STEP_SHIFT 0 3712 3713 3714 /**************************************************************************** 3715 * DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_W 3716 */ 3717 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_W :: busy [31:31] */ 3718 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_W_BUSY_MASK 0x80000000 3719 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_W_BUSY_ALIGN 0 3720 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_W_BUSY_BITS 1 3721 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_W_BUSY_SHIFT 31 3722 3723 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_W :: reserved0 [30:18] */ 3724 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_W_RESERVED0_MASK 0x7ffc0000 3725 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_W_RESERVED0_ALIGN 0 3726 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_W_RESERVED0_BITS 13 3727 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_W_RESERVED0_SHIFT 18 3728 3729 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_W :: ovr_force [17:17] */ 3730 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_W_OVR_FORCE_MASK 0x00020000 3731 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_W_OVR_FORCE_ALIGN 0 3732 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_W_OVR_FORCE_BITS 1 3733 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_W_OVR_FORCE_SHIFT 17 3734 3735 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_W :: ovr_en [16:16] */ 3736 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_W_OVR_EN_MASK 0x00010000 3737 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_W_OVR_EN_ALIGN 0 3738 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_W_OVR_EN_BITS 1 3739 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_W_OVR_EN_SHIFT 16 3740 3741 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_W :: reserved1 [15:09] */ 3742 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_W_RESERVED1_MASK 0x0000fe00 3743 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_W_RESERVED1_ALIGN 0 3744 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_W_RESERVED1_BITS 7 3745 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_W_RESERVED1_SHIFT 9 3746 3747 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_W :: byte_sel [08:08] */ 3748 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_W_BYTE_SEL_MASK 0x00000100 3749 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_W_BYTE_SEL_ALIGN 0 3750 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_W_BYTE_SEL_BITS 1 3751 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_W_BYTE_SEL_SHIFT 8 3752 3753 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_W :: reserved2 [07:06] */ 3754 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_W_RESERVED2_MASK 0x000000c0 3755 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_W_RESERVED2_ALIGN 0 3756 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_W_RESERVED2_BITS 2 3757 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_W_RESERVED2_SHIFT 6 3758 3759 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_W :: ovr_step [05:00] */ 3760 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_W_OVR_STEP_MASK 0x0000003f 3761 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_W_OVR_STEP_ALIGN 0 3762 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_W_OVR_STEP_BITS 6 3763 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_W_OVR_STEP_SHIFT 0 3764 3765 3766 /**************************************************************************** 3767 * DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_R_P 3768 */ 3769 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_R_P :: busy [31:31] */ 3770 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_P_BUSY_MASK 0x80000000 3771 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_P_BUSY_ALIGN 0 3772 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_P_BUSY_BITS 1 3773 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_P_BUSY_SHIFT 31 3774 3775 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_R_P :: reserved0 [30:18] */ 3776 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_P_RESERVED0_MASK 0x7ffc0000 3777 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_P_RESERVED0_ALIGN 0 3778 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_P_RESERVED0_BITS 13 3779 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_P_RESERVED0_SHIFT 18 3780 3781 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_R_P :: ovr_force [17:17] */ 3782 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_P_OVR_FORCE_MASK 0x00020000 3783 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_P_OVR_FORCE_ALIGN 0 3784 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_P_OVR_FORCE_BITS 1 3785 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_P_OVR_FORCE_SHIFT 17 3786 3787 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_R_P :: ovr_en [16:16] */ 3788 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_P_OVR_EN_MASK 0x00010000 3789 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_P_OVR_EN_ALIGN 0 3790 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_P_OVR_EN_BITS 1 3791 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_P_OVR_EN_SHIFT 16 3792 3793 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_R_P :: reserved1 [15:09] */ 3794 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_P_RESERVED1_MASK 0x0000fe00 3795 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_P_RESERVED1_ALIGN 0 3796 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_P_RESERVED1_BITS 7 3797 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_P_RESERVED1_SHIFT 9 3798 3799 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_R_P :: byte_sel [08:08] */ 3800 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_P_BYTE_SEL_MASK 0x00000100 3801 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_P_BYTE_SEL_ALIGN 0 3802 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_P_BYTE_SEL_BITS 1 3803 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_P_BYTE_SEL_SHIFT 8 3804 3805 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_R_P :: reserved2 [07:06] */ 3806 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_P_RESERVED2_MASK 0x000000c0 3807 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_P_RESERVED2_ALIGN 0 3808 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_P_RESERVED2_BITS 2 3809 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_P_RESERVED2_SHIFT 6 3810 3811 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_R_P :: ovr_step [05:00] */ 3812 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_P_OVR_STEP_MASK 0x0000003f 3813 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_P_OVR_STEP_ALIGN 0 3814 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_P_OVR_STEP_BITS 6 3815 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_P_OVR_STEP_SHIFT 0 3816 3817 3818 /**************************************************************************** 3819 * DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_R_N 3820 */ 3821 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_R_N :: busy [31:31] */ 3822 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_N_BUSY_MASK 0x80000000 3823 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_N_BUSY_ALIGN 0 3824 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_N_BUSY_BITS 1 3825 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_N_BUSY_SHIFT 31 3826 3827 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_R_N :: reserved0 [30:18] */ 3828 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_N_RESERVED0_MASK 0x7ffc0000 3829 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_N_RESERVED0_ALIGN 0 3830 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_N_RESERVED0_BITS 13 3831 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_N_RESERVED0_SHIFT 18 3832 3833 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_R_N :: ovr_force [17:17] */ 3834 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_N_OVR_FORCE_MASK 0x00020000 3835 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_N_OVR_FORCE_ALIGN 0 3836 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_N_OVR_FORCE_BITS 1 3837 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_N_OVR_FORCE_SHIFT 17 3838 3839 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_R_N :: ovr_en [16:16] */ 3840 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_N_OVR_EN_MASK 0x00010000 3841 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_N_OVR_EN_ALIGN 0 3842 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_N_OVR_EN_BITS 1 3843 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_N_OVR_EN_SHIFT 16 3844 3845 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_R_N :: reserved1 [15:09] */ 3846 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_N_RESERVED1_MASK 0x0000fe00 3847 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_N_RESERVED1_ALIGN 0 3848 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_N_RESERVED1_BITS 7 3849 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_N_RESERVED1_SHIFT 9 3850 3851 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_R_N :: byte_sel [08:08] */ 3852 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_N_BYTE_SEL_MASK 0x00000100 3853 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_N_BYTE_SEL_ALIGN 0 3854 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_N_BYTE_SEL_BITS 1 3855 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_N_BYTE_SEL_SHIFT 8 3856 3857 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_R_N :: reserved2 [07:06] */ 3858 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_N_RESERVED2_MASK 0x000000c0 3859 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_N_RESERVED2_ALIGN 0 3860 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_N_RESERVED2_BITS 2 3861 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_N_RESERVED2_SHIFT 6 3862 3863 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_R_N :: ovr_step [05:00] */ 3864 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_N_OVR_STEP_MASK 0x0000003f 3865 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_N_OVR_STEP_ALIGN 0 3866 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_N_OVR_STEP_BITS 6 3867 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_N_OVR_STEP_SHIFT 0 3868 3869 3870 /**************************************************************************** 3871 * DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT0_W 3872 */ 3873 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: busy [31:31] */ 3874 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_W_BUSY_MASK 0x80000000 3875 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_W_BUSY_ALIGN 0 3876 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_W_BUSY_BITS 1 3877 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_W_BUSY_SHIFT 31 3878 3879 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: reserved0 [30:18] */ 3880 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_W_RESERVED0_MASK 0x7ffc0000 3881 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_W_RESERVED0_ALIGN 0 3882 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_W_RESERVED0_BITS 13 3883 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_W_RESERVED0_SHIFT 18 3884 3885 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: ovr_force [17:17] */ 3886 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_W_OVR_FORCE_MASK 0x00020000 3887 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_W_OVR_FORCE_ALIGN 0 3888 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_W_OVR_FORCE_BITS 1 3889 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_W_OVR_FORCE_SHIFT 17 3890 3891 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: ovr_en [16:16] */ 3892 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_W_OVR_EN_MASK 0x00010000 3893 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_W_OVR_EN_ALIGN 0 3894 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_W_OVR_EN_BITS 1 3895 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_W_OVR_EN_SHIFT 16 3896 3897 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: reserved1 [15:09] */ 3898 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_W_RESERVED1_MASK 0x0000fe00 3899 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_W_RESERVED1_ALIGN 0 3900 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_W_RESERVED1_BITS 7 3901 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_W_RESERVED1_SHIFT 9 3902 3903 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: byte_sel [08:08] */ 3904 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_W_BYTE_SEL_MASK 0x00000100 3905 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_W_BYTE_SEL_ALIGN 0 3906 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_W_BYTE_SEL_BITS 1 3907 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_W_BYTE_SEL_SHIFT 8 3908 3909 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: reserved2 [07:06] */ 3910 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_W_RESERVED2_MASK 0x000000c0 3911 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_W_RESERVED2_ALIGN 0 3912 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_W_RESERVED2_BITS 2 3913 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_W_RESERVED2_SHIFT 6 3914 3915 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT0_W :: ovr_step [05:00] */ 3916 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_W_OVR_STEP_MASK 0x0000003f 3917 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_W_OVR_STEP_ALIGN 0 3918 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_W_OVR_STEP_BITS 6 3919 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_W_OVR_STEP_SHIFT 0 3920 3921 3922 /**************************************************************************** 3923 * DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT1_W 3924 */ 3925 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: busy [31:31] */ 3926 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_W_BUSY_MASK 0x80000000 3927 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_W_BUSY_ALIGN 0 3928 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_W_BUSY_BITS 1 3929 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_W_BUSY_SHIFT 31 3930 3931 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: reserved0 [30:18] */ 3932 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_W_RESERVED0_MASK 0x7ffc0000 3933 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_W_RESERVED0_ALIGN 0 3934 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_W_RESERVED0_BITS 13 3935 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_W_RESERVED0_SHIFT 18 3936 3937 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: ovr_force [17:17] */ 3938 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_W_OVR_FORCE_MASK 0x00020000 3939 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_W_OVR_FORCE_ALIGN 0 3940 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_W_OVR_FORCE_BITS 1 3941 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_W_OVR_FORCE_SHIFT 17 3942 3943 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: ovr_en [16:16] */ 3944 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_W_OVR_EN_MASK 0x00010000 3945 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_W_OVR_EN_ALIGN 0 3946 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_W_OVR_EN_BITS 1 3947 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_W_OVR_EN_SHIFT 16 3948 3949 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: reserved1 [15:09] */ 3950 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_W_RESERVED1_MASK 0x0000fe00 3951 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_W_RESERVED1_ALIGN 0 3952 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_W_RESERVED1_BITS 7 3953 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_W_RESERVED1_SHIFT 9 3954 3955 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: byte_sel [08:08] */ 3956 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_W_BYTE_SEL_MASK 0x00000100 3957 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_W_BYTE_SEL_ALIGN 0 3958 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_W_BYTE_SEL_BITS 1 3959 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_W_BYTE_SEL_SHIFT 8 3960 3961 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: reserved2 [07:06] */ 3962 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_W_RESERVED2_MASK 0x000000c0 3963 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_W_RESERVED2_ALIGN 0 3964 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_W_RESERVED2_BITS 2 3965 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_W_RESERVED2_SHIFT 6 3966 3967 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT1_W :: ovr_step [05:00] */ 3968 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_W_OVR_STEP_MASK 0x0000003f 3969 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_W_OVR_STEP_ALIGN 0 3970 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_W_OVR_STEP_BITS 6 3971 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_W_OVR_STEP_SHIFT 0 3972 3973 3974 /**************************************************************************** 3975 * DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT2_W 3976 */ 3977 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: busy [31:31] */ 3978 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_W_BUSY_MASK 0x80000000 3979 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_W_BUSY_ALIGN 0 3980 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_W_BUSY_BITS 1 3981 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_W_BUSY_SHIFT 31 3982 3983 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: reserved0 [30:18] */ 3984 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_W_RESERVED0_MASK 0x7ffc0000 3985 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_W_RESERVED0_ALIGN 0 3986 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_W_RESERVED0_BITS 13 3987 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_W_RESERVED0_SHIFT 18 3988 3989 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: ovr_force [17:17] */ 3990 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_W_OVR_FORCE_MASK 0x00020000 3991 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_W_OVR_FORCE_ALIGN 0 3992 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_W_OVR_FORCE_BITS 1 3993 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_W_OVR_FORCE_SHIFT 17 3994 3995 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: ovr_en [16:16] */ 3996 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_W_OVR_EN_MASK 0x00010000 3997 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_W_OVR_EN_ALIGN 0 3998 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_W_OVR_EN_BITS 1 3999 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_W_OVR_EN_SHIFT 16 4000 4001 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: reserved1 [15:09] */ 4002 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_W_RESERVED1_MASK 0x0000fe00 4003 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_W_RESERVED1_ALIGN 0 4004 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_W_RESERVED1_BITS 7 4005 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_W_RESERVED1_SHIFT 9 4006 4007 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: byte_sel [08:08] */ 4008 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_W_BYTE_SEL_MASK 0x00000100 4009 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_W_BYTE_SEL_ALIGN 0 4010 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_W_BYTE_SEL_BITS 1 4011 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_W_BYTE_SEL_SHIFT 8 4012 4013 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: reserved2 [07:06] */ 4014 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_W_RESERVED2_MASK 0x000000c0 4015 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_W_RESERVED2_ALIGN 0 4016 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_W_RESERVED2_BITS 2 4017 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_W_RESERVED2_SHIFT 6 4018 4019 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT2_W :: ovr_step [05:00] */ 4020 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_W_OVR_STEP_MASK 0x0000003f 4021 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_W_OVR_STEP_ALIGN 0 4022 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_W_OVR_STEP_BITS 6 4023 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_W_OVR_STEP_SHIFT 0 4024 4025 4026 /**************************************************************************** 4027 * DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT3_W 4028 */ 4029 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: busy [31:31] */ 4030 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_W_BUSY_MASK 0x80000000 4031 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_W_BUSY_ALIGN 0 4032 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_W_BUSY_BITS 1 4033 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_W_BUSY_SHIFT 31 4034 4035 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: reserved0 [30:18] */ 4036 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_W_RESERVED0_MASK 0x7ffc0000 4037 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_W_RESERVED0_ALIGN 0 4038 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_W_RESERVED0_BITS 13 4039 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_W_RESERVED0_SHIFT 18 4040 4041 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: ovr_force [17:17] */ 4042 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_W_OVR_FORCE_MASK 0x00020000 4043 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_W_OVR_FORCE_ALIGN 0 4044 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_W_OVR_FORCE_BITS 1 4045 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_W_OVR_FORCE_SHIFT 17 4046 4047 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: ovr_en [16:16] */ 4048 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_W_OVR_EN_MASK 0x00010000 4049 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_W_OVR_EN_ALIGN 0 4050 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_W_OVR_EN_BITS 1 4051 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_W_OVR_EN_SHIFT 16 4052 4053 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: reserved1 [15:09] */ 4054 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_W_RESERVED1_MASK 0x0000fe00 4055 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_W_RESERVED1_ALIGN 0 4056 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_W_RESERVED1_BITS 7 4057 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_W_RESERVED1_SHIFT 9 4058 4059 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: byte_sel [08:08] */ 4060 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_W_BYTE_SEL_MASK 0x00000100 4061 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_W_BYTE_SEL_ALIGN 0 4062 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_W_BYTE_SEL_BITS 1 4063 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_W_BYTE_SEL_SHIFT 8 4064 4065 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: reserved2 [07:06] */ 4066 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_W_RESERVED2_MASK 0x000000c0 4067 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_W_RESERVED2_ALIGN 0 4068 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_W_RESERVED2_BITS 2 4069 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_W_RESERVED2_SHIFT 6 4070 4071 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT3_W :: ovr_step [05:00] */ 4072 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_W_OVR_STEP_MASK 0x0000003f 4073 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_W_OVR_STEP_ALIGN 0 4074 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_W_OVR_STEP_BITS 6 4075 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_W_OVR_STEP_SHIFT 0 4076 4077 4078 /**************************************************************************** 4079 * DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT4_W 4080 */ 4081 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: busy [31:31] */ 4082 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_W_BUSY_MASK 0x80000000 4083 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_W_BUSY_ALIGN 0 4084 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_W_BUSY_BITS 1 4085 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_W_BUSY_SHIFT 31 4086 4087 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: reserved0 [30:18] */ 4088 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_W_RESERVED0_MASK 0x7ffc0000 4089 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_W_RESERVED0_ALIGN 0 4090 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_W_RESERVED0_BITS 13 4091 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_W_RESERVED0_SHIFT 18 4092 4093 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: ovr_force [17:17] */ 4094 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_W_OVR_FORCE_MASK 0x00020000 4095 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_W_OVR_FORCE_ALIGN 0 4096 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_W_OVR_FORCE_BITS 1 4097 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_W_OVR_FORCE_SHIFT 17 4098 4099 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: ovr_en [16:16] */ 4100 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_W_OVR_EN_MASK 0x00010000 4101 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_W_OVR_EN_ALIGN 0 4102 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_W_OVR_EN_BITS 1 4103 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_W_OVR_EN_SHIFT 16 4104 4105 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: reserved1 [15:09] */ 4106 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_W_RESERVED1_MASK 0x0000fe00 4107 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_W_RESERVED1_ALIGN 0 4108 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_W_RESERVED1_BITS 7 4109 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_W_RESERVED1_SHIFT 9 4110 4111 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: byte_sel [08:08] */ 4112 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_W_BYTE_SEL_MASK 0x00000100 4113 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_W_BYTE_SEL_ALIGN 0 4114 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_W_BYTE_SEL_BITS 1 4115 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_W_BYTE_SEL_SHIFT 8 4116 4117 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: reserved2 [07:06] */ 4118 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_W_RESERVED2_MASK 0x000000c0 4119 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_W_RESERVED2_ALIGN 0 4120 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_W_RESERVED2_BITS 2 4121 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_W_RESERVED2_SHIFT 6 4122 4123 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT4_W :: ovr_step [05:00] */ 4124 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_W_OVR_STEP_MASK 0x0000003f 4125 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_W_OVR_STEP_ALIGN 0 4126 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_W_OVR_STEP_BITS 6 4127 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_W_OVR_STEP_SHIFT 0 4128 4129 4130 /**************************************************************************** 4131 * DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT5_W 4132 */ 4133 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: busy [31:31] */ 4134 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_W_BUSY_MASK 0x80000000 4135 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_W_BUSY_ALIGN 0 4136 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_W_BUSY_BITS 1 4137 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_W_BUSY_SHIFT 31 4138 4139 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: reserved0 [30:18] */ 4140 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_W_RESERVED0_MASK 0x7ffc0000 4141 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_W_RESERVED0_ALIGN 0 4142 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_W_RESERVED0_BITS 13 4143 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_W_RESERVED0_SHIFT 18 4144 4145 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: ovr_force [17:17] */ 4146 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_W_OVR_FORCE_MASK 0x00020000 4147 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_W_OVR_FORCE_ALIGN 0 4148 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_W_OVR_FORCE_BITS 1 4149 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_W_OVR_FORCE_SHIFT 17 4150 4151 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: ovr_en [16:16] */ 4152 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_W_OVR_EN_MASK 0x00010000 4153 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_W_OVR_EN_ALIGN 0 4154 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_W_OVR_EN_BITS 1 4155 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_W_OVR_EN_SHIFT 16 4156 4157 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: reserved1 [15:09] */ 4158 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_W_RESERVED1_MASK 0x0000fe00 4159 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_W_RESERVED1_ALIGN 0 4160 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_W_RESERVED1_BITS 7 4161 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_W_RESERVED1_SHIFT 9 4162 4163 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: byte_sel [08:08] */ 4164 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_W_BYTE_SEL_MASK 0x00000100 4165 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_W_BYTE_SEL_ALIGN 0 4166 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_W_BYTE_SEL_BITS 1 4167 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_W_BYTE_SEL_SHIFT 8 4168 4169 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: reserved2 [07:06] */ 4170 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_W_RESERVED2_MASK 0x000000c0 4171 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_W_RESERVED2_ALIGN 0 4172 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_W_RESERVED2_BITS 2 4173 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_W_RESERVED2_SHIFT 6 4174 4175 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT5_W :: ovr_step [05:00] */ 4176 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_W_OVR_STEP_MASK 0x0000003f 4177 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_W_OVR_STEP_ALIGN 0 4178 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_W_OVR_STEP_BITS 6 4179 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_W_OVR_STEP_SHIFT 0 4180 4181 4182 /**************************************************************************** 4183 * DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT6_W 4184 */ 4185 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: busy [31:31] */ 4186 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_W_BUSY_MASK 0x80000000 4187 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_W_BUSY_ALIGN 0 4188 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_W_BUSY_BITS 1 4189 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_W_BUSY_SHIFT 31 4190 4191 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: reserved0 [30:18] */ 4192 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_W_RESERVED0_MASK 0x7ffc0000 4193 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_W_RESERVED0_ALIGN 0 4194 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_W_RESERVED0_BITS 13 4195 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_W_RESERVED0_SHIFT 18 4196 4197 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: ovr_force [17:17] */ 4198 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_W_OVR_FORCE_MASK 0x00020000 4199 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_W_OVR_FORCE_ALIGN 0 4200 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_W_OVR_FORCE_BITS 1 4201 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_W_OVR_FORCE_SHIFT 17 4202 4203 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: ovr_en [16:16] */ 4204 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_W_OVR_EN_MASK 0x00010000 4205 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_W_OVR_EN_ALIGN 0 4206 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_W_OVR_EN_BITS 1 4207 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_W_OVR_EN_SHIFT 16 4208 4209 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: reserved1 [15:09] */ 4210 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_W_RESERVED1_MASK 0x0000fe00 4211 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_W_RESERVED1_ALIGN 0 4212 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_W_RESERVED1_BITS 7 4213 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_W_RESERVED1_SHIFT 9 4214 4215 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: byte_sel [08:08] */ 4216 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_W_BYTE_SEL_MASK 0x00000100 4217 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_W_BYTE_SEL_ALIGN 0 4218 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_W_BYTE_SEL_BITS 1 4219 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_W_BYTE_SEL_SHIFT 8 4220 4221 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: reserved2 [07:06] */ 4222 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_W_RESERVED2_MASK 0x000000c0 4223 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_W_RESERVED2_ALIGN 0 4224 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_W_RESERVED2_BITS 2 4225 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_W_RESERVED2_SHIFT 6 4226 4227 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT6_W :: ovr_step [05:00] */ 4228 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_W_OVR_STEP_MASK 0x0000003f 4229 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_W_OVR_STEP_ALIGN 0 4230 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_W_OVR_STEP_BITS 6 4231 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_W_OVR_STEP_SHIFT 0 4232 4233 4234 /**************************************************************************** 4235 * DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT7_W 4236 */ 4237 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: busy [31:31] */ 4238 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_W_BUSY_MASK 0x80000000 4239 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_W_BUSY_ALIGN 0 4240 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_W_BUSY_BITS 1 4241 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_W_BUSY_SHIFT 31 4242 4243 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: reserved0 [30:18] */ 4244 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_W_RESERVED0_MASK 0x7ffc0000 4245 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_W_RESERVED0_ALIGN 0 4246 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_W_RESERVED0_BITS 13 4247 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_W_RESERVED0_SHIFT 18 4248 4249 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: ovr_force [17:17] */ 4250 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_W_OVR_FORCE_MASK 0x00020000 4251 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_W_OVR_FORCE_ALIGN 0 4252 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_W_OVR_FORCE_BITS 1 4253 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_W_OVR_FORCE_SHIFT 17 4254 4255 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: ovr_en [16:16] */ 4256 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_W_OVR_EN_MASK 0x00010000 4257 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_W_OVR_EN_ALIGN 0 4258 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_W_OVR_EN_BITS 1 4259 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_W_OVR_EN_SHIFT 16 4260 4261 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: reserved1 [15:09] */ 4262 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_W_RESERVED1_MASK 0x0000fe00 4263 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_W_RESERVED1_ALIGN 0 4264 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_W_RESERVED1_BITS 7 4265 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_W_RESERVED1_SHIFT 9 4266 4267 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: byte_sel [08:08] */ 4268 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_W_BYTE_SEL_MASK 0x00000100 4269 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_W_BYTE_SEL_ALIGN 0 4270 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_W_BYTE_SEL_BITS 1 4271 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_W_BYTE_SEL_SHIFT 8 4272 4273 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: reserved2 [07:06] */ 4274 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_W_RESERVED2_MASK 0x000000c0 4275 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_W_RESERVED2_ALIGN 0 4276 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_W_RESERVED2_BITS 2 4277 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_W_RESERVED2_SHIFT 6 4278 4279 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT7_W :: ovr_step [05:00] */ 4280 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_W_OVR_STEP_MASK 0x0000003f 4281 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_W_OVR_STEP_ALIGN 0 4282 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_W_OVR_STEP_BITS 6 4283 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_W_OVR_STEP_SHIFT 0 4284 4285 4286 /**************************************************************************** 4287 * DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_DM_W 4288 */ 4289 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_DM_W :: busy [31:31] */ 4290 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_DM_W_BUSY_MASK 0x80000000 4291 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_DM_W_BUSY_ALIGN 0 4292 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_DM_W_BUSY_BITS 1 4293 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_DM_W_BUSY_SHIFT 31 4294 4295 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_DM_W :: reserved0 [30:18] */ 4296 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_DM_W_RESERVED0_MASK 0x7ffc0000 4297 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_DM_W_RESERVED0_ALIGN 0 4298 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_DM_W_RESERVED0_BITS 13 4299 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_DM_W_RESERVED0_SHIFT 18 4300 4301 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_DM_W :: ovr_force [17:17] */ 4302 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_DM_W_OVR_FORCE_MASK 0x00020000 4303 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_DM_W_OVR_FORCE_ALIGN 0 4304 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_DM_W_OVR_FORCE_BITS 1 4305 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_DM_W_OVR_FORCE_SHIFT 17 4306 4307 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_DM_W :: ovr_en [16:16] */ 4308 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_DM_W_OVR_EN_MASK 0x00010000 4309 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_DM_W_OVR_EN_ALIGN 0 4310 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_DM_W_OVR_EN_BITS 1 4311 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_DM_W_OVR_EN_SHIFT 16 4312 4313 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_DM_W :: reserved1 [15:09] */ 4314 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_DM_W_RESERVED1_MASK 0x0000fe00 4315 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_DM_W_RESERVED1_ALIGN 0 4316 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_DM_W_RESERVED1_BITS 7 4317 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_DM_W_RESERVED1_SHIFT 9 4318 4319 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_DM_W :: byte_sel [08:08] */ 4320 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_DM_W_BYTE_SEL_MASK 0x00000100 4321 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_DM_W_BYTE_SEL_ALIGN 0 4322 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_DM_W_BYTE_SEL_BITS 1 4323 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_DM_W_BYTE_SEL_SHIFT 8 4324 4325 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_DM_W :: reserved2 [07:06] */ 4326 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_DM_W_RESERVED2_MASK 0x000000c0 4327 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_DM_W_RESERVED2_ALIGN 0 4328 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_DM_W_RESERVED2_BITS 2 4329 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_DM_W_RESERVED2_SHIFT 6 4330 4331 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_DM_W :: ovr_step [05:00] */ 4332 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_DM_W_OVR_STEP_MASK 0x0000003f 4333 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_DM_W_OVR_STEP_ALIGN 0 4334 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_DM_W_OVR_STEP_BITS 6 4335 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_DM_W_OVR_STEP_SHIFT 0 4336 4337 4338 /**************************************************************************** 4339 * DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P 4340 */ 4341 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: busy [31:31] */ 4342 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_P_BUSY_MASK 0x80000000 4343 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_P_BUSY_ALIGN 0 4344 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_P_BUSY_BITS 1 4345 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_P_BUSY_SHIFT 31 4346 4347 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: reserved0 [30:18] */ 4348 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_P_RESERVED0_MASK 0x7ffc0000 4349 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_P_RESERVED0_ALIGN 0 4350 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_P_RESERVED0_BITS 13 4351 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_P_RESERVED0_SHIFT 18 4352 4353 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: ovr_force [17:17] */ 4354 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_P_OVR_FORCE_MASK 0x00020000 4355 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_P_OVR_FORCE_ALIGN 0 4356 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_P_OVR_FORCE_BITS 1 4357 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_P_OVR_FORCE_SHIFT 17 4358 4359 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: ovr_en [16:16] */ 4360 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_P_OVR_EN_MASK 0x00010000 4361 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_P_OVR_EN_ALIGN 0 4362 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_P_OVR_EN_BITS 1 4363 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_P_OVR_EN_SHIFT 16 4364 4365 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: reserved1 [15:09] */ 4366 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_P_RESERVED1_MASK 0x0000fe00 4367 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_P_RESERVED1_ALIGN 0 4368 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_P_RESERVED1_BITS 7 4369 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_P_RESERVED1_SHIFT 9 4370 4371 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: byte_sel [08:08] */ 4372 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_P_BYTE_SEL_MASK 0x00000100 4373 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_P_BYTE_SEL_ALIGN 0 4374 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_P_BYTE_SEL_BITS 1 4375 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_P_BYTE_SEL_SHIFT 8 4376 4377 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: reserved2 [07:06] */ 4378 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_P_RESERVED2_MASK 0x000000c0 4379 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_P_RESERVED2_ALIGN 0 4380 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_P_RESERVED2_BITS 2 4381 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_P_RESERVED2_SHIFT 6 4382 4383 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: ovr_step [05:00] */ 4384 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_P_OVR_STEP_MASK 0x0000003f 4385 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_P_OVR_STEP_ALIGN 0 4386 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_P_OVR_STEP_BITS 6 4387 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_P_OVR_STEP_SHIFT 0 4388 4389 4390 /**************************************************************************** 4391 * DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N 4392 */ 4393 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: busy [31:31] */ 4394 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_N_BUSY_MASK 0x80000000 4395 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_N_BUSY_ALIGN 0 4396 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_N_BUSY_BITS 1 4397 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_N_BUSY_SHIFT 31 4398 4399 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: reserved0 [30:18] */ 4400 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_N_RESERVED0_MASK 0x7ffc0000 4401 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_N_RESERVED0_ALIGN 0 4402 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_N_RESERVED0_BITS 13 4403 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_N_RESERVED0_SHIFT 18 4404 4405 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: ovr_force [17:17] */ 4406 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_N_OVR_FORCE_MASK 0x00020000 4407 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_N_OVR_FORCE_ALIGN 0 4408 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_N_OVR_FORCE_BITS 1 4409 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_N_OVR_FORCE_SHIFT 17 4410 4411 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: ovr_en [16:16] */ 4412 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_N_OVR_EN_MASK 0x00010000 4413 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_N_OVR_EN_ALIGN 0 4414 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_N_OVR_EN_BITS 1 4415 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_N_OVR_EN_SHIFT 16 4416 4417 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: reserved1 [15:09] */ 4418 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_N_RESERVED1_MASK 0x0000fe00 4419 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_N_RESERVED1_ALIGN 0 4420 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_N_RESERVED1_BITS 7 4421 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_N_RESERVED1_SHIFT 9 4422 4423 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: byte_sel [08:08] */ 4424 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_N_BYTE_SEL_MASK 0x00000100 4425 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_N_BYTE_SEL_ALIGN 0 4426 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_N_BYTE_SEL_BITS 1 4427 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_N_BYTE_SEL_SHIFT 8 4428 4429 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: reserved2 [07:06] */ 4430 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_N_RESERVED2_MASK 0x000000c0 4431 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_N_RESERVED2_ALIGN 0 4432 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_N_RESERVED2_BITS 2 4433 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_N_RESERVED2_SHIFT 6 4434 4435 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: ovr_step [05:00] */ 4436 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_N_OVR_STEP_MASK 0x0000003f 4437 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_N_OVR_STEP_ALIGN 0 4438 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_N_OVR_STEP_BITS 6 4439 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_N_OVR_STEP_SHIFT 0 4440 4441 4442 /**************************************************************************** 4443 * DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P 4444 */ 4445 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: busy [31:31] */ 4446 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_P_BUSY_MASK 0x80000000 4447 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_P_BUSY_ALIGN 0 4448 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_P_BUSY_BITS 1 4449 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_P_BUSY_SHIFT 31 4450 4451 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: reserved0 [30:18] */ 4452 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_P_RESERVED0_MASK 0x7ffc0000 4453 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_P_RESERVED0_ALIGN 0 4454 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_P_RESERVED0_BITS 13 4455 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_P_RESERVED0_SHIFT 18 4456 4457 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: ovr_force [17:17] */ 4458 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_P_OVR_FORCE_MASK 0x00020000 4459 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_P_OVR_FORCE_ALIGN 0 4460 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_P_OVR_FORCE_BITS 1 4461 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_P_OVR_FORCE_SHIFT 17 4462 4463 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: ovr_en [16:16] */ 4464 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_P_OVR_EN_MASK 0x00010000 4465 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_P_OVR_EN_ALIGN 0 4466 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_P_OVR_EN_BITS 1 4467 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_P_OVR_EN_SHIFT 16 4468 4469 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: reserved1 [15:09] */ 4470 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_P_RESERVED1_MASK 0x0000fe00 4471 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_P_RESERVED1_ALIGN 0 4472 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_P_RESERVED1_BITS 7 4473 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_P_RESERVED1_SHIFT 9 4474 4475 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: byte_sel [08:08] */ 4476 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_P_BYTE_SEL_MASK 0x00000100 4477 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_P_BYTE_SEL_ALIGN 0 4478 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_P_BYTE_SEL_BITS 1 4479 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_P_BYTE_SEL_SHIFT 8 4480 4481 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: reserved2 [07:06] */ 4482 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_P_RESERVED2_MASK 0x000000c0 4483 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_P_RESERVED2_ALIGN 0 4484 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_P_RESERVED2_BITS 2 4485 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_P_RESERVED2_SHIFT 6 4486 4487 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: ovr_step [05:00] */ 4488 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_P_OVR_STEP_MASK 0x0000003f 4489 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_P_OVR_STEP_ALIGN 0 4490 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_P_OVR_STEP_BITS 6 4491 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_P_OVR_STEP_SHIFT 0 4492 4493 4494 /**************************************************************************** 4495 * DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N 4496 */ 4497 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: busy [31:31] */ 4498 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_N_BUSY_MASK 0x80000000 4499 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_N_BUSY_ALIGN 0 4500 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_N_BUSY_BITS 1 4501 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_N_BUSY_SHIFT 31 4502 4503 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: reserved0 [30:18] */ 4504 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_N_RESERVED0_MASK 0x7ffc0000 4505 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_N_RESERVED0_ALIGN 0 4506 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_N_RESERVED0_BITS 13 4507 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_N_RESERVED0_SHIFT 18 4508 4509 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: ovr_force [17:17] */ 4510 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_N_OVR_FORCE_MASK 0x00020000 4511 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_N_OVR_FORCE_ALIGN 0 4512 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_N_OVR_FORCE_BITS 1 4513 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_N_OVR_FORCE_SHIFT 17 4514 4515 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: ovr_en [16:16] */ 4516 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_N_OVR_EN_MASK 0x00010000 4517 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_N_OVR_EN_ALIGN 0 4518 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_N_OVR_EN_BITS 1 4519 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_N_OVR_EN_SHIFT 16 4520 4521 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: reserved1 [15:09] */ 4522 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_N_RESERVED1_MASK 0x0000fe00 4523 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_N_RESERVED1_ALIGN 0 4524 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_N_RESERVED1_BITS 7 4525 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_N_RESERVED1_SHIFT 9 4526 4527 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: byte_sel [08:08] */ 4528 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_N_BYTE_SEL_MASK 0x00000100 4529 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_N_BYTE_SEL_ALIGN 0 4530 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_N_BYTE_SEL_BITS 1 4531 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_N_BYTE_SEL_SHIFT 8 4532 4533 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: reserved2 [07:06] */ 4534 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_N_RESERVED2_MASK 0x000000c0 4535 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_N_RESERVED2_ALIGN 0 4536 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_N_RESERVED2_BITS 2 4537 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_N_RESERVED2_SHIFT 6 4538 4539 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: ovr_step [05:00] */ 4540 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_N_OVR_STEP_MASK 0x0000003f 4541 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_N_OVR_STEP_ALIGN 0 4542 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_N_OVR_STEP_BITS 6 4543 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_N_OVR_STEP_SHIFT 0 4544 4545 4546 /**************************************************************************** 4547 * DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P 4548 */ 4549 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: busy [31:31] */ 4550 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_P_BUSY_MASK 0x80000000 4551 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_P_BUSY_ALIGN 0 4552 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_P_BUSY_BITS 1 4553 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_P_BUSY_SHIFT 31 4554 4555 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: reserved0 [30:18] */ 4556 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_P_RESERVED0_MASK 0x7ffc0000 4557 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_P_RESERVED0_ALIGN 0 4558 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_P_RESERVED0_BITS 13 4559 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_P_RESERVED0_SHIFT 18 4560 4561 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: ovr_force [17:17] */ 4562 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_P_OVR_FORCE_MASK 0x00020000 4563 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_P_OVR_FORCE_ALIGN 0 4564 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_P_OVR_FORCE_BITS 1 4565 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_P_OVR_FORCE_SHIFT 17 4566 4567 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: ovr_en [16:16] */ 4568 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_P_OVR_EN_MASK 0x00010000 4569 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_P_OVR_EN_ALIGN 0 4570 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_P_OVR_EN_BITS 1 4571 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_P_OVR_EN_SHIFT 16 4572 4573 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: reserved1 [15:09] */ 4574 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_P_RESERVED1_MASK 0x0000fe00 4575 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_P_RESERVED1_ALIGN 0 4576 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_P_RESERVED1_BITS 7 4577 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_P_RESERVED1_SHIFT 9 4578 4579 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: byte_sel [08:08] */ 4580 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_P_BYTE_SEL_MASK 0x00000100 4581 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_P_BYTE_SEL_ALIGN 0 4582 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_P_BYTE_SEL_BITS 1 4583 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_P_BYTE_SEL_SHIFT 8 4584 4585 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: reserved2 [07:06] */ 4586 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_P_RESERVED2_MASK 0x000000c0 4587 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_P_RESERVED2_ALIGN 0 4588 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_P_RESERVED2_BITS 2 4589 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_P_RESERVED2_SHIFT 6 4590 4591 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: ovr_step [05:00] */ 4592 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_P_OVR_STEP_MASK 0x0000003f 4593 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_P_OVR_STEP_ALIGN 0 4594 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_P_OVR_STEP_BITS 6 4595 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_P_OVR_STEP_SHIFT 0 4596 4597 4598 /**************************************************************************** 4599 * DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N 4600 */ 4601 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: busy [31:31] */ 4602 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_N_BUSY_MASK 0x80000000 4603 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_N_BUSY_ALIGN 0 4604 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_N_BUSY_BITS 1 4605 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_N_BUSY_SHIFT 31 4606 4607 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: reserved0 [30:18] */ 4608 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_N_RESERVED0_MASK 0x7ffc0000 4609 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_N_RESERVED0_ALIGN 0 4610 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_N_RESERVED0_BITS 13 4611 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_N_RESERVED0_SHIFT 18 4612 4613 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: ovr_force [17:17] */ 4614 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_N_OVR_FORCE_MASK 0x00020000 4615 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_N_OVR_FORCE_ALIGN 0 4616 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_N_OVR_FORCE_BITS 1 4617 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_N_OVR_FORCE_SHIFT 17 4618 4619 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: ovr_en [16:16] */ 4620 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_N_OVR_EN_MASK 0x00010000 4621 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_N_OVR_EN_ALIGN 0 4622 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_N_OVR_EN_BITS 1 4623 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_N_OVR_EN_SHIFT 16 4624 4625 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: reserved1 [15:09] */ 4626 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_N_RESERVED1_MASK 0x0000fe00 4627 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_N_RESERVED1_ALIGN 0 4628 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_N_RESERVED1_BITS 7 4629 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_N_RESERVED1_SHIFT 9 4630 4631 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: byte_sel [08:08] */ 4632 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_N_BYTE_SEL_MASK 0x00000100 4633 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_N_BYTE_SEL_ALIGN 0 4634 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_N_BYTE_SEL_BITS 1 4635 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_N_BYTE_SEL_SHIFT 8 4636 4637 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: reserved2 [07:06] */ 4638 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_N_RESERVED2_MASK 0x000000c0 4639 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_N_RESERVED2_ALIGN 0 4640 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_N_RESERVED2_BITS 2 4641 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_N_RESERVED2_SHIFT 6 4642 4643 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: ovr_step [05:00] */ 4644 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_N_OVR_STEP_MASK 0x0000003f 4645 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_N_OVR_STEP_ALIGN 0 4646 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_N_OVR_STEP_BITS 6 4647 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_N_OVR_STEP_SHIFT 0 4648 4649 4650 /**************************************************************************** 4651 * DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P 4652 */ 4653 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: busy [31:31] */ 4654 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_P_BUSY_MASK 0x80000000 4655 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_P_BUSY_ALIGN 0 4656 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_P_BUSY_BITS 1 4657 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_P_BUSY_SHIFT 31 4658 4659 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: reserved0 [30:18] */ 4660 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_P_RESERVED0_MASK 0x7ffc0000 4661 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_P_RESERVED0_ALIGN 0 4662 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_P_RESERVED0_BITS 13 4663 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_P_RESERVED0_SHIFT 18 4664 4665 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: ovr_force [17:17] */ 4666 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_P_OVR_FORCE_MASK 0x00020000 4667 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_P_OVR_FORCE_ALIGN 0 4668 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_P_OVR_FORCE_BITS 1 4669 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_P_OVR_FORCE_SHIFT 17 4670 4671 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: ovr_en [16:16] */ 4672 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_P_OVR_EN_MASK 0x00010000 4673 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_P_OVR_EN_ALIGN 0 4674 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_P_OVR_EN_BITS 1 4675 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_P_OVR_EN_SHIFT 16 4676 4677 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: reserved1 [15:09] */ 4678 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_P_RESERVED1_MASK 0x0000fe00 4679 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_P_RESERVED1_ALIGN 0 4680 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_P_RESERVED1_BITS 7 4681 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_P_RESERVED1_SHIFT 9 4682 4683 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: byte_sel [08:08] */ 4684 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_P_BYTE_SEL_MASK 0x00000100 4685 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_P_BYTE_SEL_ALIGN 0 4686 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_P_BYTE_SEL_BITS 1 4687 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_P_BYTE_SEL_SHIFT 8 4688 4689 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: reserved2 [07:06] */ 4690 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_P_RESERVED2_MASK 0x000000c0 4691 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_P_RESERVED2_ALIGN 0 4692 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_P_RESERVED2_BITS 2 4693 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_P_RESERVED2_SHIFT 6 4694 4695 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: ovr_step [05:00] */ 4696 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_P_OVR_STEP_MASK 0x0000003f 4697 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_P_OVR_STEP_ALIGN 0 4698 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_P_OVR_STEP_BITS 6 4699 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_P_OVR_STEP_SHIFT 0 4700 4701 4702 /**************************************************************************** 4703 * DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N 4704 */ 4705 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: busy [31:31] */ 4706 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_N_BUSY_MASK 0x80000000 4707 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_N_BUSY_ALIGN 0 4708 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_N_BUSY_BITS 1 4709 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_N_BUSY_SHIFT 31 4710 4711 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: reserved0 [30:18] */ 4712 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_N_RESERVED0_MASK 0x7ffc0000 4713 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_N_RESERVED0_ALIGN 0 4714 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_N_RESERVED0_BITS 13 4715 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_N_RESERVED0_SHIFT 18 4716 4717 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: ovr_force [17:17] */ 4718 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_N_OVR_FORCE_MASK 0x00020000 4719 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_N_OVR_FORCE_ALIGN 0 4720 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_N_OVR_FORCE_BITS 1 4721 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_N_OVR_FORCE_SHIFT 17 4722 4723 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: ovr_en [16:16] */ 4724 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_N_OVR_EN_MASK 0x00010000 4725 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_N_OVR_EN_ALIGN 0 4726 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_N_OVR_EN_BITS 1 4727 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_N_OVR_EN_SHIFT 16 4728 4729 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: reserved1 [15:09] */ 4730 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_N_RESERVED1_MASK 0x0000fe00 4731 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_N_RESERVED1_ALIGN 0 4732 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_N_RESERVED1_BITS 7 4733 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_N_RESERVED1_SHIFT 9 4734 4735 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: byte_sel [08:08] */ 4736 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_N_BYTE_SEL_MASK 0x00000100 4737 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_N_BYTE_SEL_ALIGN 0 4738 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_N_BYTE_SEL_BITS 1 4739 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_N_BYTE_SEL_SHIFT 8 4740 4741 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: reserved2 [07:06] */ 4742 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_N_RESERVED2_MASK 0x000000c0 4743 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_N_RESERVED2_ALIGN 0 4744 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_N_RESERVED2_BITS 2 4745 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_N_RESERVED2_SHIFT 6 4746 4747 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: ovr_step [05:00] */ 4748 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_N_OVR_STEP_MASK 0x0000003f 4749 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_N_OVR_STEP_ALIGN 0 4750 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_N_OVR_STEP_BITS 6 4751 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_N_OVR_STEP_SHIFT 0 4752 4753 4754 /**************************************************************************** 4755 * DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P 4756 */ 4757 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: busy [31:31] */ 4758 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_P_BUSY_MASK 0x80000000 4759 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_P_BUSY_ALIGN 0 4760 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_P_BUSY_BITS 1 4761 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_P_BUSY_SHIFT 31 4762 4763 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: reserved0 [30:18] */ 4764 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_P_RESERVED0_MASK 0x7ffc0000 4765 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_P_RESERVED0_ALIGN 0 4766 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_P_RESERVED0_BITS 13 4767 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_P_RESERVED0_SHIFT 18 4768 4769 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: ovr_force [17:17] */ 4770 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_P_OVR_FORCE_MASK 0x00020000 4771 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_P_OVR_FORCE_ALIGN 0 4772 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_P_OVR_FORCE_BITS 1 4773 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_P_OVR_FORCE_SHIFT 17 4774 4775 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: ovr_en [16:16] */ 4776 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_P_OVR_EN_MASK 0x00010000 4777 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_P_OVR_EN_ALIGN 0 4778 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_P_OVR_EN_BITS 1 4779 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_P_OVR_EN_SHIFT 16 4780 4781 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: reserved1 [15:09] */ 4782 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_P_RESERVED1_MASK 0x0000fe00 4783 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_P_RESERVED1_ALIGN 0 4784 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_P_RESERVED1_BITS 7 4785 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_P_RESERVED1_SHIFT 9 4786 4787 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: byte_sel [08:08] */ 4788 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_P_BYTE_SEL_MASK 0x00000100 4789 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_P_BYTE_SEL_ALIGN 0 4790 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_P_BYTE_SEL_BITS 1 4791 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_P_BYTE_SEL_SHIFT 8 4792 4793 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: reserved2 [07:06] */ 4794 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_P_RESERVED2_MASK 0x000000c0 4795 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_P_RESERVED2_ALIGN 0 4796 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_P_RESERVED2_BITS 2 4797 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_P_RESERVED2_SHIFT 6 4798 4799 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: ovr_step [05:00] */ 4800 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_P_OVR_STEP_MASK 0x0000003f 4801 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_P_OVR_STEP_ALIGN 0 4802 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_P_OVR_STEP_BITS 6 4803 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_P_OVR_STEP_SHIFT 0 4804 4805 4806 /**************************************************************************** 4807 * DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N 4808 */ 4809 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: busy [31:31] */ 4810 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_N_BUSY_MASK 0x80000000 4811 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_N_BUSY_ALIGN 0 4812 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_N_BUSY_BITS 1 4813 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_N_BUSY_SHIFT 31 4814 4815 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: reserved0 [30:18] */ 4816 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_N_RESERVED0_MASK 0x7ffc0000 4817 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_N_RESERVED0_ALIGN 0 4818 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_N_RESERVED0_BITS 13 4819 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_N_RESERVED0_SHIFT 18 4820 4821 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: ovr_force [17:17] */ 4822 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_N_OVR_FORCE_MASK 0x00020000 4823 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_N_OVR_FORCE_ALIGN 0 4824 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_N_OVR_FORCE_BITS 1 4825 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_N_OVR_FORCE_SHIFT 17 4826 4827 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: ovr_en [16:16] */ 4828 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_N_OVR_EN_MASK 0x00010000 4829 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_N_OVR_EN_ALIGN 0 4830 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_N_OVR_EN_BITS 1 4831 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_N_OVR_EN_SHIFT 16 4832 4833 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: reserved1 [15:09] */ 4834 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_N_RESERVED1_MASK 0x0000fe00 4835 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_N_RESERVED1_ALIGN 0 4836 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_N_RESERVED1_BITS 7 4837 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_N_RESERVED1_SHIFT 9 4838 4839 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: byte_sel [08:08] */ 4840 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_N_BYTE_SEL_MASK 0x00000100 4841 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_N_BYTE_SEL_ALIGN 0 4842 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_N_BYTE_SEL_BITS 1 4843 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_N_BYTE_SEL_SHIFT 8 4844 4845 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: reserved2 [07:06] */ 4846 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_N_RESERVED2_MASK 0x000000c0 4847 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_N_RESERVED2_ALIGN 0 4848 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_N_RESERVED2_BITS 2 4849 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_N_RESERVED2_SHIFT 6 4850 4851 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: ovr_step [05:00] */ 4852 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_N_OVR_STEP_MASK 0x0000003f 4853 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_N_OVR_STEP_ALIGN 0 4854 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_N_OVR_STEP_BITS 6 4855 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_N_OVR_STEP_SHIFT 0 4856 4857 4858 /**************************************************************************** 4859 * DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P 4860 */ 4861 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: busy [31:31] */ 4862 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_P_BUSY_MASK 0x80000000 4863 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_P_BUSY_ALIGN 0 4864 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_P_BUSY_BITS 1 4865 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_P_BUSY_SHIFT 31 4866 4867 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: reserved0 [30:18] */ 4868 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_P_RESERVED0_MASK 0x7ffc0000 4869 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_P_RESERVED0_ALIGN 0 4870 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_P_RESERVED0_BITS 13 4871 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_P_RESERVED0_SHIFT 18 4872 4873 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: ovr_force [17:17] */ 4874 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_P_OVR_FORCE_MASK 0x00020000 4875 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_P_OVR_FORCE_ALIGN 0 4876 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_P_OVR_FORCE_BITS 1 4877 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_P_OVR_FORCE_SHIFT 17 4878 4879 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: ovr_en [16:16] */ 4880 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_P_OVR_EN_MASK 0x00010000 4881 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_P_OVR_EN_ALIGN 0 4882 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_P_OVR_EN_BITS 1 4883 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_P_OVR_EN_SHIFT 16 4884 4885 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: reserved1 [15:09] */ 4886 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_P_RESERVED1_MASK 0x0000fe00 4887 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_P_RESERVED1_ALIGN 0 4888 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_P_RESERVED1_BITS 7 4889 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_P_RESERVED1_SHIFT 9 4890 4891 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: byte_sel [08:08] */ 4892 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_P_BYTE_SEL_MASK 0x00000100 4893 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_P_BYTE_SEL_ALIGN 0 4894 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_P_BYTE_SEL_BITS 1 4895 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_P_BYTE_SEL_SHIFT 8 4896 4897 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: reserved2 [07:06] */ 4898 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_P_RESERVED2_MASK 0x000000c0 4899 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_P_RESERVED2_ALIGN 0 4900 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_P_RESERVED2_BITS 2 4901 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_P_RESERVED2_SHIFT 6 4902 4903 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: ovr_step [05:00] */ 4904 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_P_OVR_STEP_MASK 0x0000003f 4905 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_P_OVR_STEP_ALIGN 0 4906 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_P_OVR_STEP_BITS 6 4907 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_P_OVR_STEP_SHIFT 0 4908 4909 4910 /**************************************************************************** 4911 * DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N 4912 */ 4913 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: busy [31:31] */ 4914 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_N_BUSY_MASK 0x80000000 4915 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_N_BUSY_ALIGN 0 4916 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_N_BUSY_BITS 1 4917 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_N_BUSY_SHIFT 31 4918 4919 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: reserved0 [30:18] */ 4920 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_N_RESERVED0_MASK 0x7ffc0000 4921 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_N_RESERVED0_ALIGN 0 4922 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_N_RESERVED0_BITS 13 4923 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_N_RESERVED0_SHIFT 18 4924 4925 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: ovr_force [17:17] */ 4926 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_N_OVR_FORCE_MASK 0x00020000 4927 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_N_OVR_FORCE_ALIGN 0 4928 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_N_OVR_FORCE_BITS 1 4929 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_N_OVR_FORCE_SHIFT 17 4930 4931 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: ovr_en [16:16] */ 4932 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_N_OVR_EN_MASK 0x00010000 4933 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_N_OVR_EN_ALIGN 0 4934 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_N_OVR_EN_BITS 1 4935 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_N_OVR_EN_SHIFT 16 4936 4937 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: reserved1 [15:09] */ 4938 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_N_RESERVED1_MASK 0x0000fe00 4939 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_N_RESERVED1_ALIGN 0 4940 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_N_RESERVED1_BITS 7 4941 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_N_RESERVED1_SHIFT 9 4942 4943 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: byte_sel [08:08] */ 4944 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_N_BYTE_SEL_MASK 0x00000100 4945 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_N_BYTE_SEL_ALIGN 0 4946 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_N_BYTE_SEL_BITS 1 4947 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_N_BYTE_SEL_SHIFT 8 4948 4949 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: reserved2 [07:06] */ 4950 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_N_RESERVED2_MASK 0x000000c0 4951 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_N_RESERVED2_ALIGN 0 4952 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_N_RESERVED2_BITS 2 4953 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_N_RESERVED2_SHIFT 6 4954 4955 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: ovr_step [05:00] */ 4956 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_N_OVR_STEP_MASK 0x0000003f 4957 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_N_OVR_STEP_ALIGN 0 4958 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_N_OVR_STEP_BITS 6 4959 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_N_OVR_STEP_SHIFT 0 4960 4961 4962 /**************************************************************************** 4963 * DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P 4964 */ 4965 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: busy [31:31] */ 4966 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_P_BUSY_MASK 0x80000000 4967 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_P_BUSY_ALIGN 0 4968 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_P_BUSY_BITS 1 4969 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_P_BUSY_SHIFT 31 4970 4971 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: reserved0 [30:18] */ 4972 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_P_RESERVED0_MASK 0x7ffc0000 4973 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_P_RESERVED0_ALIGN 0 4974 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_P_RESERVED0_BITS 13 4975 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_P_RESERVED0_SHIFT 18 4976 4977 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: ovr_force [17:17] */ 4978 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_P_OVR_FORCE_MASK 0x00020000 4979 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_P_OVR_FORCE_ALIGN 0 4980 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_P_OVR_FORCE_BITS 1 4981 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_P_OVR_FORCE_SHIFT 17 4982 4983 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: ovr_en [16:16] */ 4984 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_P_OVR_EN_MASK 0x00010000 4985 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_P_OVR_EN_ALIGN 0 4986 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_P_OVR_EN_BITS 1 4987 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_P_OVR_EN_SHIFT 16 4988 4989 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: reserved1 [15:09] */ 4990 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_P_RESERVED1_MASK 0x0000fe00 4991 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_P_RESERVED1_ALIGN 0 4992 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_P_RESERVED1_BITS 7 4993 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_P_RESERVED1_SHIFT 9 4994 4995 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: byte_sel [08:08] */ 4996 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_P_BYTE_SEL_MASK 0x00000100 4997 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_P_BYTE_SEL_ALIGN 0 4998 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_P_BYTE_SEL_BITS 1 4999 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_P_BYTE_SEL_SHIFT 8 5000 5001 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: reserved2 [07:06] */ 5002 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_P_RESERVED2_MASK 0x000000c0 5003 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_P_RESERVED2_ALIGN 0 5004 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_P_RESERVED2_BITS 2 5005 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_P_RESERVED2_SHIFT 6 5006 5007 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: ovr_step [05:00] */ 5008 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_P_OVR_STEP_MASK 0x0000003f 5009 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_P_OVR_STEP_ALIGN 0 5010 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_P_OVR_STEP_BITS 6 5011 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_P_OVR_STEP_SHIFT 0 5012 5013 5014 /**************************************************************************** 5015 * DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N 5016 */ 5017 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: busy [31:31] */ 5018 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_N_BUSY_MASK 0x80000000 5019 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_N_BUSY_ALIGN 0 5020 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_N_BUSY_BITS 1 5021 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_N_BUSY_SHIFT 31 5022 5023 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: reserved0 [30:18] */ 5024 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_N_RESERVED0_MASK 0x7ffc0000 5025 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_N_RESERVED0_ALIGN 0 5026 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_N_RESERVED0_BITS 13 5027 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_N_RESERVED0_SHIFT 18 5028 5029 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: ovr_force [17:17] */ 5030 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_N_OVR_FORCE_MASK 0x00020000 5031 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_N_OVR_FORCE_ALIGN 0 5032 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_N_OVR_FORCE_BITS 1 5033 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_N_OVR_FORCE_SHIFT 17 5034 5035 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: ovr_en [16:16] */ 5036 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_N_OVR_EN_MASK 0x00010000 5037 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_N_OVR_EN_ALIGN 0 5038 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_N_OVR_EN_BITS 1 5039 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_N_OVR_EN_SHIFT 16 5040 5041 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: reserved1 [15:09] */ 5042 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_N_RESERVED1_MASK 0x0000fe00 5043 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_N_RESERVED1_ALIGN 0 5044 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_N_RESERVED1_BITS 7 5045 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_N_RESERVED1_SHIFT 9 5046 5047 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: byte_sel [08:08] */ 5048 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_N_BYTE_SEL_MASK 0x00000100 5049 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_N_BYTE_SEL_ALIGN 0 5050 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_N_BYTE_SEL_BITS 1 5051 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_N_BYTE_SEL_SHIFT 8 5052 5053 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: reserved2 [07:06] */ 5054 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_N_RESERVED2_MASK 0x000000c0 5055 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_N_RESERVED2_ALIGN 0 5056 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_N_RESERVED2_BITS 2 5057 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_N_RESERVED2_SHIFT 6 5058 5059 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: ovr_step [05:00] */ 5060 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_N_OVR_STEP_MASK 0x0000003f 5061 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_N_OVR_STEP_ALIGN 0 5062 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_N_OVR_STEP_BITS 6 5063 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_N_OVR_STEP_SHIFT 0 5064 5065 5066 /**************************************************************************** 5067 * DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P 5068 */ 5069 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: busy [31:31] */ 5070 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_P_BUSY_MASK 0x80000000 5071 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_P_BUSY_ALIGN 0 5072 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_P_BUSY_BITS 1 5073 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_P_BUSY_SHIFT 31 5074 5075 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: reserved0 [30:18] */ 5076 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_P_RESERVED0_MASK 0x7ffc0000 5077 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_P_RESERVED0_ALIGN 0 5078 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_P_RESERVED0_BITS 13 5079 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_P_RESERVED0_SHIFT 18 5080 5081 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: ovr_force [17:17] */ 5082 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_P_OVR_FORCE_MASK 0x00020000 5083 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_P_OVR_FORCE_ALIGN 0 5084 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_P_OVR_FORCE_BITS 1 5085 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_P_OVR_FORCE_SHIFT 17 5086 5087 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: ovr_en [16:16] */ 5088 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_P_OVR_EN_MASK 0x00010000 5089 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_P_OVR_EN_ALIGN 0 5090 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_P_OVR_EN_BITS 1 5091 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_P_OVR_EN_SHIFT 16 5092 5093 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: reserved1 [15:09] */ 5094 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_P_RESERVED1_MASK 0x0000fe00 5095 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_P_RESERVED1_ALIGN 0 5096 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_P_RESERVED1_BITS 7 5097 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_P_RESERVED1_SHIFT 9 5098 5099 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: byte_sel [08:08] */ 5100 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_P_BYTE_SEL_MASK 0x00000100 5101 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_P_BYTE_SEL_ALIGN 0 5102 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_P_BYTE_SEL_BITS 1 5103 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_P_BYTE_SEL_SHIFT 8 5104 5105 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: reserved2 [07:06] */ 5106 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_P_RESERVED2_MASK 0x000000c0 5107 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_P_RESERVED2_ALIGN 0 5108 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_P_RESERVED2_BITS 2 5109 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_P_RESERVED2_SHIFT 6 5110 5111 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: ovr_step [05:00] */ 5112 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_P_OVR_STEP_MASK 0x0000003f 5113 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_P_OVR_STEP_ALIGN 0 5114 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_P_OVR_STEP_BITS 6 5115 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_P_OVR_STEP_SHIFT 0 5116 5117 5118 /**************************************************************************** 5119 * DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N 5120 */ 5121 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: busy [31:31] */ 5122 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_N_BUSY_MASK 0x80000000 5123 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_N_BUSY_ALIGN 0 5124 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_N_BUSY_BITS 1 5125 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_N_BUSY_SHIFT 31 5126 5127 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: reserved0 [30:18] */ 5128 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_N_RESERVED0_MASK 0x7ffc0000 5129 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_N_RESERVED0_ALIGN 0 5130 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_N_RESERVED0_BITS 13 5131 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_N_RESERVED0_SHIFT 18 5132 5133 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: ovr_force [17:17] */ 5134 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_N_OVR_FORCE_MASK 0x00020000 5135 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_N_OVR_FORCE_ALIGN 0 5136 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_N_OVR_FORCE_BITS 1 5137 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_N_OVR_FORCE_SHIFT 17 5138 5139 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: ovr_en [16:16] */ 5140 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_N_OVR_EN_MASK 0x00010000 5141 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_N_OVR_EN_ALIGN 0 5142 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_N_OVR_EN_BITS 1 5143 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_N_OVR_EN_SHIFT 16 5144 5145 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: reserved1 [15:09] */ 5146 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_N_RESERVED1_MASK 0x0000fe00 5147 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_N_RESERVED1_ALIGN 0 5148 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_N_RESERVED1_BITS 7 5149 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_N_RESERVED1_SHIFT 9 5150 5151 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: byte_sel [08:08] */ 5152 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_N_BYTE_SEL_MASK 0x00000100 5153 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_N_BYTE_SEL_ALIGN 0 5154 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_N_BYTE_SEL_BITS 1 5155 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_N_BYTE_SEL_SHIFT 8 5156 5157 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: reserved2 [07:06] */ 5158 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_N_RESERVED2_MASK 0x000000c0 5159 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_N_RESERVED2_ALIGN 0 5160 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_N_RESERVED2_BITS 2 5161 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_N_RESERVED2_SHIFT 6 5162 5163 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: ovr_step [05:00] */ 5164 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_N_OVR_STEP_MASK 0x0000003f 5165 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_N_OVR_STEP_ALIGN 0 5166 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_N_OVR_STEP_BITS 6 5167 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_N_OVR_STEP_SHIFT 0 5168 5169 5170 /**************************************************************************** 5171 * DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN 5172 */ 5173 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: busy [31:31] */ 5174 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_BUSY_MASK 0x80000000 5175 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_BUSY_ALIGN 0 5176 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_BUSY_BITS 1 5177 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_BUSY_SHIFT 31 5178 5179 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: reserved0 [30:18] */ 5180 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_RESERVED0_MASK 0x7ffc0000 5181 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_RESERVED0_ALIGN 0 5182 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_RESERVED0_BITS 13 5183 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_RESERVED0_SHIFT 18 5184 5185 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: ovr_force [17:17] */ 5186 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_OVR_FORCE_MASK 0x00020000 5187 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_OVR_FORCE_ALIGN 0 5188 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_OVR_FORCE_BITS 1 5189 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_OVR_FORCE_SHIFT 17 5190 5191 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: ovr_en [16:16] */ 5192 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_OVR_EN_MASK 0x00010000 5193 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_OVR_EN_ALIGN 0 5194 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_OVR_EN_BITS 1 5195 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_OVR_EN_SHIFT 16 5196 5197 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: reserved1 [15:09] */ 5198 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_RESERVED1_MASK 0x0000fe00 5199 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_RESERVED1_ALIGN 0 5200 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_RESERVED1_BITS 7 5201 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_RESERVED1_SHIFT 9 5202 5203 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: byte_sel [08:08] */ 5204 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_BYTE_SEL_MASK 0x00000100 5205 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_BYTE_SEL_ALIGN 0 5206 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_BYTE_SEL_BITS 1 5207 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_BYTE_SEL_SHIFT 8 5208 5209 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: reserved2 [07:06] */ 5210 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_RESERVED2_MASK 0x000000c0 5211 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_RESERVED2_ALIGN 0 5212 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_RESERVED2_BITS 2 5213 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_RESERVED2_SHIFT 6 5214 5215 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: ovr_step [05:00] */ 5216 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_OVR_STEP_MASK 0x0000003f 5217 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_OVR_STEP_ALIGN 0 5218 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_OVR_STEP_BITS 6 5219 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT_RD_EN_OVR_STEP_SHIFT 0 5220 5221 5222 /**************************************************************************** 5223 * DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_W 5224 */ 5225 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_W :: busy [31:31] */ 5226 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_W_BUSY_MASK 0x80000000 5227 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_W_BUSY_ALIGN 0 5228 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_W_BUSY_BITS 1 5229 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_W_BUSY_SHIFT 31 5230 5231 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_W :: reserved0 [30:18] */ 5232 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_W_RESERVED0_MASK 0x7ffc0000 5233 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_W_RESERVED0_ALIGN 0 5234 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_W_RESERVED0_BITS 13 5235 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_W_RESERVED0_SHIFT 18 5236 5237 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_W :: ovr_force [17:17] */ 5238 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_W_OVR_FORCE_MASK 0x00020000 5239 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_W_OVR_FORCE_ALIGN 0 5240 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_W_OVR_FORCE_BITS 1 5241 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_W_OVR_FORCE_SHIFT 17 5242 5243 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_W :: ovr_en [16:16] */ 5244 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_W_OVR_EN_MASK 0x00010000 5245 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_W_OVR_EN_ALIGN 0 5246 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_W_OVR_EN_BITS 1 5247 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_W_OVR_EN_SHIFT 16 5248 5249 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_W :: reserved1 [15:09] */ 5250 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_W_RESERVED1_MASK 0x0000fe00 5251 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_W_RESERVED1_ALIGN 0 5252 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_W_RESERVED1_BITS 7 5253 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_W_RESERVED1_SHIFT 9 5254 5255 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_W :: byte_sel [08:08] */ 5256 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_W_BYTE_SEL_MASK 0x00000100 5257 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_W_BYTE_SEL_ALIGN 0 5258 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_W_BYTE_SEL_BITS 1 5259 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_W_BYTE_SEL_SHIFT 8 5260 5261 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_W :: reserved2 [07:06] */ 5262 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_W_RESERVED2_MASK 0x000000c0 5263 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_W_RESERVED2_ALIGN 0 5264 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_W_RESERVED2_BITS 2 5265 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_W_RESERVED2_SHIFT 6 5266 5267 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_W :: ovr_step [05:00] */ 5268 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_W_OVR_STEP_MASK 0x0000003f 5269 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_W_OVR_STEP_ALIGN 0 5270 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_W_OVR_STEP_BITS 6 5271 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_W_OVR_STEP_SHIFT 0 5272 5273 5274 /**************************************************************************** 5275 * DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_R_P 5276 */ 5277 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_R_P :: busy [31:31] */ 5278 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_P_BUSY_MASK 0x80000000 5279 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_P_BUSY_ALIGN 0 5280 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_P_BUSY_BITS 1 5281 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_P_BUSY_SHIFT 31 5282 5283 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_R_P :: reserved0 [30:18] */ 5284 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_P_RESERVED0_MASK 0x7ffc0000 5285 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_P_RESERVED0_ALIGN 0 5286 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_P_RESERVED0_BITS 13 5287 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_P_RESERVED0_SHIFT 18 5288 5289 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_R_P :: ovr_force [17:17] */ 5290 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_P_OVR_FORCE_MASK 0x00020000 5291 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_P_OVR_FORCE_ALIGN 0 5292 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_P_OVR_FORCE_BITS 1 5293 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_P_OVR_FORCE_SHIFT 17 5294 5295 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_R_P :: ovr_en [16:16] */ 5296 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_P_OVR_EN_MASK 0x00010000 5297 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_P_OVR_EN_ALIGN 0 5298 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_P_OVR_EN_BITS 1 5299 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_P_OVR_EN_SHIFT 16 5300 5301 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_R_P :: reserved1 [15:09] */ 5302 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_P_RESERVED1_MASK 0x0000fe00 5303 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_P_RESERVED1_ALIGN 0 5304 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_P_RESERVED1_BITS 7 5305 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_P_RESERVED1_SHIFT 9 5306 5307 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_R_P :: byte_sel [08:08] */ 5308 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_P_BYTE_SEL_MASK 0x00000100 5309 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_P_BYTE_SEL_ALIGN 0 5310 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_P_BYTE_SEL_BITS 1 5311 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_P_BYTE_SEL_SHIFT 8 5312 5313 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_R_P :: reserved2 [07:06] */ 5314 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_P_RESERVED2_MASK 0x000000c0 5315 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_P_RESERVED2_ALIGN 0 5316 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_P_RESERVED2_BITS 2 5317 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_P_RESERVED2_SHIFT 6 5318 5319 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_R_P :: ovr_step [05:00] */ 5320 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_P_OVR_STEP_MASK 0x0000003f 5321 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_P_OVR_STEP_ALIGN 0 5322 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_P_OVR_STEP_BITS 6 5323 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_P_OVR_STEP_SHIFT 0 5324 5325 5326 /**************************************************************************** 5327 * DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_R_N 5328 */ 5329 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_R_N :: busy [31:31] */ 5330 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_N_BUSY_MASK 0x80000000 5331 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_N_BUSY_ALIGN 0 5332 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_N_BUSY_BITS 1 5333 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_N_BUSY_SHIFT 31 5334 5335 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_R_N :: reserved0 [30:18] */ 5336 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_N_RESERVED0_MASK 0x7ffc0000 5337 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_N_RESERVED0_ALIGN 0 5338 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_N_RESERVED0_BITS 13 5339 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_N_RESERVED0_SHIFT 18 5340 5341 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_R_N :: ovr_force [17:17] */ 5342 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_N_OVR_FORCE_MASK 0x00020000 5343 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_N_OVR_FORCE_ALIGN 0 5344 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_N_OVR_FORCE_BITS 1 5345 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_N_OVR_FORCE_SHIFT 17 5346 5347 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_R_N :: ovr_en [16:16] */ 5348 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_N_OVR_EN_MASK 0x00010000 5349 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_N_OVR_EN_ALIGN 0 5350 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_N_OVR_EN_BITS 1 5351 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_N_OVR_EN_SHIFT 16 5352 5353 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_R_N :: reserved1 [15:09] */ 5354 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_N_RESERVED1_MASK 0x0000fe00 5355 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_N_RESERVED1_ALIGN 0 5356 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_N_RESERVED1_BITS 7 5357 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_N_RESERVED1_SHIFT 9 5358 5359 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_R_N :: byte_sel [08:08] */ 5360 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_N_BYTE_SEL_MASK 0x00000100 5361 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_N_BYTE_SEL_ALIGN 0 5362 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_N_BYTE_SEL_BITS 1 5363 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_N_BYTE_SEL_SHIFT 8 5364 5365 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_R_N :: reserved2 [07:06] */ 5366 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_N_RESERVED2_MASK 0x000000c0 5367 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_N_RESERVED2_ALIGN 0 5368 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_N_RESERVED2_BITS 2 5369 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_N_RESERVED2_SHIFT 6 5370 5371 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_R_N :: ovr_step [05:00] */ 5372 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_N_OVR_STEP_MASK 0x0000003f 5373 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_N_OVR_STEP_ALIGN 0 5374 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_N_OVR_STEP_BITS 6 5375 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_N_OVR_STEP_SHIFT 0 5376 5377 5378 /**************************************************************************** 5379 * DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT0_W 5380 */ 5381 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: busy [31:31] */ 5382 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_W_BUSY_MASK 0x80000000 5383 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_W_BUSY_ALIGN 0 5384 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_W_BUSY_BITS 1 5385 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_W_BUSY_SHIFT 31 5386 5387 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: reserved0 [30:18] */ 5388 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_W_RESERVED0_MASK 0x7ffc0000 5389 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_W_RESERVED0_ALIGN 0 5390 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_W_RESERVED0_BITS 13 5391 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_W_RESERVED0_SHIFT 18 5392 5393 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: ovr_force [17:17] */ 5394 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_W_OVR_FORCE_MASK 0x00020000 5395 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_W_OVR_FORCE_ALIGN 0 5396 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_W_OVR_FORCE_BITS 1 5397 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_W_OVR_FORCE_SHIFT 17 5398 5399 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: ovr_en [16:16] */ 5400 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_W_OVR_EN_MASK 0x00010000 5401 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_W_OVR_EN_ALIGN 0 5402 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_W_OVR_EN_BITS 1 5403 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_W_OVR_EN_SHIFT 16 5404 5405 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: reserved1 [15:09] */ 5406 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_W_RESERVED1_MASK 0x0000fe00 5407 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_W_RESERVED1_ALIGN 0 5408 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_W_RESERVED1_BITS 7 5409 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_W_RESERVED1_SHIFT 9 5410 5411 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: byte_sel [08:08] */ 5412 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_W_BYTE_SEL_MASK 0x00000100 5413 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_W_BYTE_SEL_ALIGN 0 5414 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_W_BYTE_SEL_BITS 1 5415 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_W_BYTE_SEL_SHIFT 8 5416 5417 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: reserved2 [07:06] */ 5418 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_W_RESERVED2_MASK 0x000000c0 5419 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_W_RESERVED2_ALIGN 0 5420 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_W_RESERVED2_BITS 2 5421 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_W_RESERVED2_SHIFT 6 5422 5423 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT0_W :: ovr_step [05:00] */ 5424 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_W_OVR_STEP_MASK 0x0000003f 5425 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_W_OVR_STEP_ALIGN 0 5426 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_W_OVR_STEP_BITS 6 5427 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_W_OVR_STEP_SHIFT 0 5428 5429 5430 /**************************************************************************** 5431 * DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT1_W 5432 */ 5433 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: busy [31:31] */ 5434 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_W_BUSY_MASK 0x80000000 5435 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_W_BUSY_ALIGN 0 5436 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_W_BUSY_BITS 1 5437 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_W_BUSY_SHIFT 31 5438 5439 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: reserved0 [30:18] */ 5440 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_W_RESERVED0_MASK 0x7ffc0000 5441 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_W_RESERVED0_ALIGN 0 5442 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_W_RESERVED0_BITS 13 5443 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_W_RESERVED0_SHIFT 18 5444 5445 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: ovr_force [17:17] */ 5446 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_W_OVR_FORCE_MASK 0x00020000 5447 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_W_OVR_FORCE_ALIGN 0 5448 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_W_OVR_FORCE_BITS 1 5449 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_W_OVR_FORCE_SHIFT 17 5450 5451 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: ovr_en [16:16] */ 5452 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_W_OVR_EN_MASK 0x00010000 5453 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_W_OVR_EN_ALIGN 0 5454 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_W_OVR_EN_BITS 1 5455 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_W_OVR_EN_SHIFT 16 5456 5457 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: reserved1 [15:09] */ 5458 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_W_RESERVED1_MASK 0x0000fe00 5459 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_W_RESERVED1_ALIGN 0 5460 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_W_RESERVED1_BITS 7 5461 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_W_RESERVED1_SHIFT 9 5462 5463 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: byte_sel [08:08] */ 5464 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_W_BYTE_SEL_MASK 0x00000100 5465 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_W_BYTE_SEL_ALIGN 0 5466 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_W_BYTE_SEL_BITS 1 5467 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_W_BYTE_SEL_SHIFT 8 5468 5469 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: reserved2 [07:06] */ 5470 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_W_RESERVED2_MASK 0x000000c0 5471 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_W_RESERVED2_ALIGN 0 5472 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_W_RESERVED2_BITS 2 5473 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_W_RESERVED2_SHIFT 6 5474 5475 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT1_W :: ovr_step [05:00] */ 5476 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_W_OVR_STEP_MASK 0x0000003f 5477 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_W_OVR_STEP_ALIGN 0 5478 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_W_OVR_STEP_BITS 6 5479 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_W_OVR_STEP_SHIFT 0 5480 5481 5482 /**************************************************************************** 5483 * DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT2_W 5484 */ 5485 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: busy [31:31] */ 5486 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_W_BUSY_MASK 0x80000000 5487 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_W_BUSY_ALIGN 0 5488 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_W_BUSY_BITS 1 5489 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_W_BUSY_SHIFT 31 5490 5491 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: reserved0 [30:18] */ 5492 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_W_RESERVED0_MASK 0x7ffc0000 5493 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_W_RESERVED0_ALIGN 0 5494 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_W_RESERVED0_BITS 13 5495 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_W_RESERVED0_SHIFT 18 5496 5497 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: ovr_force [17:17] */ 5498 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_W_OVR_FORCE_MASK 0x00020000 5499 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_W_OVR_FORCE_ALIGN 0 5500 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_W_OVR_FORCE_BITS 1 5501 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_W_OVR_FORCE_SHIFT 17 5502 5503 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: ovr_en [16:16] */ 5504 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_W_OVR_EN_MASK 0x00010000 5505 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_W_OVR_EN_ALIGN 0 5506 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_W_OVR_EN_BITS 1 5507 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_W_OVR_EN_SHIFT 16 5508 5509 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: reserved1 [15:09] */ 5510 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_W_RESERVED1_MASK 0x0000fe00 5511 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_W_RESERVED1_ALIGN 0 5512 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_W_RESERVED1_BITS 7 5513 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_W_RESERVED1_SHIFT 9 5514 5515 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: byte_sel [08:08] */ 5516 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_W_BYTE_SEL_MASK 0x00000100 5517 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_W_BYTE_SEL_ALIGN 0 5518 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_W_BYTE_SEL_BITS 1 5519 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_W_BYTE_SEL_SHIFT 8 5520 5521 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: reserved2 [07:06] */ 5522 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_W_RESERVED2_MASK 0x000000c0 5523 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_W_RESERVED2_ALIGN 0 5524 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_W_RESERVED2_BITS 2 5525 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_W_RESERVED2_SHIFT 6 5526 5527 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT2_W :: ovr_step [05:00] */ 5528 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_W_OVR_STEP_MASK 0x0000003f 5529 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_W_OVR_STEP_ALIGN 0 5530 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_W_OVR_STEP_BITS 6 5531 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_W_OVR_STEP_SHIFT 0 5532 5533 5534 /**************************************************************************** 5535 * DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT3_W 5536 */ 5537 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: busy [31:31] */ 5538 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_W_BUSY_MASK 0x80000000 5539 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_W_BUSY_ALIGN 0 5540 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_W_BUSY_BITS 1 5541 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_W_BUSY_SHIFT 31 5542 5543 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: reserved0 [30:18] */ 5544 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_W_RESERVED0_MASK 0x7ffc0000 5545 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_W_RESERVED0_ALIGN 0 5546 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_W_RESERVED0_BITS 13 5547 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_W_RESERVED0_SHIFT 18 5548 5549 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: ovr_force [17:17] */ 5550 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_W_OVR_FORCE_MASK 0x00020000 5551 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_W_OVR_FORCE_ALIGN 0 5552 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_W_OVR_FORCE_BITS 1 5553 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_W_OVR_FORCE_SHIFT 17 5554 5555 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: ovr_en [16:16] */ 5556 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_W_OVR_EN_MASK 0x00010000 5557 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_W_OVR_EN_ALIGN 0 5558 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_W_OVR_EN_BITS 1 5559 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_W_OVR_EN_SHIFT 16 5560 5561 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: reserved1 [15:09] */ 5562 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_W_RESERVED1_MASK 0x0000fe00 5563 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_W_RESERVED1_ALIGN 0 5564 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_W_RESERVED1_BITS 7 5565 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_W_RESERVED1_SHIFT 9 5566 5567 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: byte_sel [08:08] */ 5568 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_W_BYTE_SEL_MASK 0x00000100 5569 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_W_BYTE_SEL_ALIGN 0 5570 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_W_BYTE_SEL_BITS 1 5571 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_W_BYTE_SEL_SHIFT 8 5572 5573 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: reserved2 [07:06] */ 5574 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_W_RESERVED2_MASK 0x000000c0 5575 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_W_RESERVED2_ALIGN 0 5576 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_W_RESERVED2_BITS 2 5577 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_W_RESERVED2_SHIFT 6 5578 5579 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT3_W :: ovr_step [05:00] */ 5580 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_W_OVR_STEP_MASK 0x0000003f 5581 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_W_OVR_STEP_ALIGN 0 5582 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_W_OVR_STEP_BITS 6 5583 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_W_OVR_STEP_SHIFT 0 5584 5585 5586 /**************************************************************************** 5587 * DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT4_W 5588 */ 5589 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: busy [31:31] */ 5590 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_W_BUSY_MASK 0x80000000 5591 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_W_BUSY_ALIGN 0 5592 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_W_BUSY_BITS 1 5593 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_W_BUSY_SHIFT 31 5594 5595 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: reserved0 [30:18] */ 5596 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_W_RESERVED0_MASK 0x7ffc0000 5597 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_W_RESERVED0_ALIGN 0 5598 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_W_RESERVED0_BITS 13 5599 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_W_RESERVED0_SHIFT 18 5600 5601 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: ovr_force [17:17] */ 5602 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_W_OVR_FORCE_MASK 0x00020000 5603 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_W_OVR_FORCE_ALIGN 0 5604 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_W_OVR_FORCE_BITS 1 5605 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_W_OVR_FORCE_SHIFT 17 5606 5607 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: ovr_en [16:16] */ 5608 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_W_OVR_EN_MASK 0x00010000 5609 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_W_OVR_EN_ALIGN 0 5610 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_W_OVR_EN_BITS 1 5611 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_W_OVR_EN_SHIFT 16 5612 5613 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: reserved1 [15:09] */ 5614 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_W_RESERVED1_MASK 0x0000fe00 5615 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_W_RESERVED1_ALIGN 0 5616 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_W_RESERVED1_BITS 7 5617 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_W_RESERVED1_SHIFT 9 5618 5619 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: byte_sel [08:08] */ 5620 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_W_BYTE_SEL_MASK 0x00000100 5621 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_W_BYTE_SEL_ALIGN 0 5622 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_W_BYTE_SEL_BITS 1 5623 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_W_BYTE_SEL_SHIFT 8 5624 5625 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: reserved2 [07:06] */ 5626 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_W_RESERVED2_MASK 0x000000c0 5627 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_W_RESERVED2_ALIGN 0 5628 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_W_RESERVED2_BITS 2 5629 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_W_RESERVED2_SHIFT 6 5630 5631 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT4_W :: ovr_step [05:00] */ 5632 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_W_OVR_STEP_MASK 0x0000003f 5633 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_W_OVR_STEP_ALIGN 0 5634 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_W_OVR_STEP_BITS 6 5635 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_W_OVR_STEP_SHIFT 0 5636 5637 5638 /**************************************************************************** 5639 * DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT5_W 5640 */ 5641 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: busy [31:31] */ 5642 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_W_BUSY_MASK 0x80000000 5643 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_W_BUSY_ALIGN 0 5644 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_W_BUSY_BITS 1 5645 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_W_BUSY_SHIFT 31 5646 5647 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: reserved0 [30:18] */ 5648 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_W_RESERVED0_MASK 0x7ffc0000 5649 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_W_RESERVED0_ALIGN 0 5650 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_W_RESERVED0_BITS 13 5651 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_W_RESERVED0_SHIFT 18 5652 5653 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: ovr_force [17:17] */ 5654 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_W_OVR_FORCE_MASK 0x00020000 5655 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_W_OVR_FORCE_ALIGN 0 5656 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_W_OVR_FORCE_BITS 1 5657 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_W_OVR_FORCE_SHIFT 17 5658 5659 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: ovr_en [16:16] */ 5660 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_W_OVR_EN_MASK 0x00010000 5661 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_W_OVR_EN_ALIGN 0 5662 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_W_OVR_EN_BITS 1 5663 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_W_OVR_EN_SHIFT 16 5664 5665 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: reserved1 [15:09] */ 5666 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_W_RESERVED1_MASK 0x0000fe00 5667 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_W_RESERVED1_ALIGN 0 5668 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_W_RESERVED1_BITS 7 5669 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_W_RESERVED1_SHIFT 9 5670 5671 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: byte_sel [08:08] */ 5672 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_W_BYTE_SEL_MASK 0x00000100 5673 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_W_BYTE_SEL_ALIGN 0 5674 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_W_BYTE_SEL_BITS 1 5675 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_W_BYTE_SEL_SHIFT 8 5676 5677 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: reserved2 [07:06] */ 5678 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_W_RESERVED2_MASK 0x000000c0 5679 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_W_RESERVED2_ALIGN 0 5680 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_W_RESERVED2_BITS 2 5681 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_W_RESERVED2_SHIFT 6 5682 5683 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT5_W :: ovr_step [05:00] */ 5684 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_W_OVR_STEP_MASK 0x0000003f 5685 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_W_OVR_STEP_ALIGN 0 5686 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_W_OVR_STEP_BITS 6 5687 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_W_OVR_STEP_SHIFT 0 5688 5689 5690 /**************************************************************************** 5691 * DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT6_W 5692 */ 5693 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: busy [31:31] */ 5694 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_W_BUSY_MASK 0x80000000 5695 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_W_BUSY_ALIGN 0 5696 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_W_BUSY_BITS 1 5697 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_W_BUSY_SHIFT 31 5698 5699 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: reserved0 [30:18] */ 5700 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_W_RESERVED0_MASK 0x7ffc0000 5701 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_W_RESERVED0_ALIGN 0 5702 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_W_RESERVED0_BITS 13 5703 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_W_RESERVED0_SHIFT 18 5704 5705 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: ovr_force [17:17] */ 5706 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_W_OVR_FORCE_MASK 0x00020000 5707 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_W_OVR_FORCE_ALIGN 0 5708 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_W_OVR_FORCE_BITS 1 5709 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_W_OVR_FORCE_SHIFT 17 5710 5711 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: ovr_en [16:16] */ 5712 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_W_OVR_EN_MASK 0x00010000 5713 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_W_OVR_EN_ALIGN 0 5714 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_W_OVR_EN_BITS 1 5715 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_W_OVR_EN_SHIFT 16 5716 5717 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: reserved1 [15:09] */ 5718 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_W_RESERVED1_MASK 0x0000fe00 5719 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_W_RESERVED1_ALIGN 0 5720 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_W_RESERVED1_BITS 7 5721 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_W_RESERVED1_SHIFT 9 5722 5723 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: byte_sel [08:08] */ 5724 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_W_BYTE_SEL_MASK 0x00000100 5725 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_W_BYTE_SEL_ALIGN 0 5726 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_W_BYTE_SEL_BITS 1 5727 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_W_BYTE_SEL_SHIFT 8 5728 5729 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: reserved2 [07:06] */ 5730 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_W_RESERVED2_MASK 0x000000c0 5731 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_W_RESERVED2_ALIGN 0 5732 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_W_RESERVED2_BITS 2 5733 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_W_RESERVED2_SHIFT 6 5734 5735 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT6_W :: ovr_step [05:00] */ 5736 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_W_OVR_STEP_MASK 0x0000003f 5737 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_W_OVR_STEP_ALIGN 0 5738 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_W_OVR_STEP_BITS 6 5739 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_W_OVR_STEP_SHIFT 0 5740 5741 5742 /**************************************************************************** 5743 * DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT7_W 5744 */ 5745 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: busy [31:31] */ 5746 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_W_BUSY_MASK 0x80000000 5747 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_W_BUSY_ALIGN 0 5748 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_W_BUSY_BITS 1 5749 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_W_BUSY_SHIFT 31 5750 5751 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: reserved0 [30:18] */ 5752 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_W_RESERVED0_MASK 0x7ffc0000 5753 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_W_RESERVED0_ALIGN 0 5754 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_W_RESERVED0_BITS 13 5755 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_W_RESERVED0_SHIFT 18 5756 5757 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: ovr_force [17:17] */ 5758 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_W_OVR_FORCE_MASK 0x00020000 5759 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_W_OVR_FORCE_ALIGN 0 5760 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_W_OVR_FORCE_BITS 1 5761 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_W_OVR_FORCE_SHIFT 17 5762 5763 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: ovr_en [16:16] */ 5764 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_W_OVR_EN_MASK 0x00010000 5765 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_W_OVR_EN_ALIGN 0 5766 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_W_OVR_EN_BITS 1 5767 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_W_OVR_EN_SHIFT 16 5768 5769 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: reserved1 [15:09] */ 5770 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_W_RESERVED1_MASK 0x0000fe00 5771 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_W_RESERVED1_ALIGN 0 5772 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_W_RESERVED1_BITS 7 5773 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_W_RESERVED1_SHIFT 9 5774 5775 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: byte_sel [08:08] */ 5776 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_W_BYTE_SEL_MASK 0x00000100 5777 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_W_BYTE_SEL_ALIGN 0 5778 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_W_BYTE_SEL_BITS 1 5779 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_W_BYTE_SEL_SHIFT 8 5780 5781 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: reserved2 [07:06] */ 5782 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_W_RESERVED2_MASK 0x000000c0 5783 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_W_RESERVED2_ALIGN 0 5784 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_W_RESERVED2_BITS 2 5785 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_W_RESERVED2_SHIFT 6 5786 5787 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT7_W :: ovr_step [05:00] */ 5788 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_W_OVR_STEP_MASK 0x0000003f 5789 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_W_OVR_STEP_ALIGN 0 5790 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_W_OVR_STEP_BITS 6 5791 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_W_OVR_STEP_SHIFT 0 5792 5793 5794 /**************************************************************************** 5795 * DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_DM_W 5796 */ 5797 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_DM_W :: busy [31:31] */ 5798 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_DM_W_BUSY_MASK 0x80000000 5799 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_DM_W_BUSY_ALIGN 0 5800 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_DM_W_BUSY_BITS 1 5801 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_DM_W_BUSY_SHIFT 31 5802 5803 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_DM_W :: reserved0 [30:18] */ 5804 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_DM_W_RESERVED0_MASK 0x7ffc0000 5805 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_DM_W_RESERVED0_ALIGN 0 5806 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_DM_W_RESERVED0_BITS 13 5807 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_DM_W_RESERVED0_SHIFT 18 5808 5809 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_DM_W :: ovr_force [17:17] */ 5810 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_DM_W_OVR_FORCE_MASK 0x00020000 5811 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_DM_W_OVR_FORCE_ALIGN 0 5812 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_DM_W_OVR_FORCE_BITS 1 5813 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_DM_W_OVR_FORCE_SHIFT 17 5814 5815 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_DM_W :: ovr_en [16:16] */ 5816 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_DM_W_OVR_EN_MASK 0x00010000 5817 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_DM_W_OVR_EN_ALIGN 0 5818 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_DM_W_OVR_EN_BITS 1 5819 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_DM_W_OVR_EN_SHIFT 16 5820 5821 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_DM_W :: reserved1 [15:09] */ 5822 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_DM_W_RESERVED1_MASK 0x0000fe00 5823 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_DM_W_RESERVED1_ALIGN 0 5824 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_DM_W_RESERVED1_BITS 7 5825 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_DM_W_RESERVED1_SHIFT 9 5826 5827 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_DM_W :: byte_sel [08:08] */ 5828 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_DM_W_BYTE_SEL_MASK 0x00000100 5829 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_DM_W_BYTE_SEL_ALIGN 0 5830 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_DM_W_BYTE_SEL_BITS 1 5831 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_DM_W_BYTE_SEL_SHIFT 8 5832 5833 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_DM_W :: reserved2 [07:06] */ 5834 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_DM_W_RESERVED2_MASK 0x000000c0 5835 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_DM_W_RESERVED2_ALIGN 0 5836 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_DM_W_RESERVED2_BITS 2 5837 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_DM_W_RESERVED2_SHIFT 6 5838 5839 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_DM_W :: ovr_step [05:00] */ 5840 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_DM_W_OVR_STEP_MASK 0x0000003f 5841 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_DM_W_OVR_STEP_ALIGN 0 5842 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_DM_W_OVR_STEP_BITS 6 5843 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_DM_W_OVR_STEP_SHIFT 0 5844 5845 5846 /**************************************************************************** 5847 * DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P 5848 */ 5849 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: busy [31:31] */ 5850 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_P_BUSY_MASK 0x80000000 5851 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_P_BUSY_ALIGN 0 5852 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_P_BUSY_BITS 1 5853 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_P_BUSY_SHIFT 31 5854 5855 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: reserved0 [30:18] */ 5856 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_P_RESERVED0_MASK 0x7ffc0000 5857 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_P_RESERVED0_ALIGN 0 5858 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_P_RESERVED0_BITS 13 5859 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_P_RESERVED0_SHIFT 18 5860 5861 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: ovr_force [17:17] */ 5862 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_P_OVR_FORCE_MASK 0x00020000 5863 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_P_OVR_FORCE_ALIGN 0 5864 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_P_OVR_FORCE_BITS 1 5865 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_P_OVR_FORCE_SHIFT 17 5866 5867 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: ovr_en [16:16] */ 5868 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_P_OVR_EN_MASK 0x00010000 5869 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_P_OVR_EN_ALIGN 0 5870 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_P_OVR_EN_BITS 1 5871 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_P_OVR_EN_SHIFT 16 5872 5873 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: reserved1 [15:09] */ 5874 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_P_RESERVED1_MASK 0x0000fe00 5875 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_P_RESERVED1_ALIGN 0 5876 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_P_RESERVED1_BITS 7 5877 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_P_RESERVED1_SHIFT 9 5878 5879 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: byte_sel [08:08] */ 5880 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_P_BYTE_SEL_MASK 0x00000100 5881 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_P_BYTE_SEL_ALIGN 0 5882 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_P_BYTE_SEL_BITS 1 5883 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_P_BYTE_SEL_SHIFT 8 5884 5885 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: reserved2 [07:06] */ 5886 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_P_RESERVED2_MASK 0x000000c0 5887 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_P_RESERVED2_ALIGN 0 5888 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_P_RESERVED2_BITS 2 5889 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_P_RESERVED2_SHIFT 6 5890 5891 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: ovr_step [05:00] */ 5892 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_P_OVR_STEP_MASK 0x0000003f 5893 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_P_OVR_STEP_ALIGN 0 5894 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_P_OVR_STEP_BITS 6 5895 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_P_OVR_STEP_SHIFT 0 5896 5897 5898 /**************************************************************************** 5899 * DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N 5900 */ 5901 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: busy [31:31] */ 5902 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_N_BUSY_MASK 0x80000000 5903 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_N_BUSY_ALIGN 0 5904 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_N_BUSY_BITS 1 5905 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_N_BUSY_SHIFT 31 5906 5907 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: reserved0 [30:18] */ 5908 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_N_RESERVED0_MASK 0x7ffc0000 5909 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_N_RESERVED0_ALIGN 0 5910 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_N_RESERVED0_BITS 13 5911 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_N_RESERVED0_SHIFT 18 5912 5913 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: ovr_force [17:17] */ 5914 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_N_OVR_FORCE_MASK 0x00020000 5915 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_N_OVR_FORCE_ALIGN 0 5916 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_N_OVR_FORCE_BITS 1 5917 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_N_OVR_FORCE_SHIFT 17 5918 5919 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: ovr_en [16:16] */ 5920 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_N_OVR_EN_MASK 0x00010000 5921 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_N_OVR_EN_ALIGN 0 5922 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_N_OVR_EN_BITS 1 5923 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_N_OVR_EN_SHIFT 16 5924 5925 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: reserved1 [15:09] */ 5926 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_N_RESERVED1_MASK 0x0000fe00 5927 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_N_RESERVED1_ALIGN 0 5928 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_N_RESERVED1_BITS 7 5929 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_N_RESERVED1_SHIFT 9 5930 5931 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: byte_sel [08:08] */ 5932 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_N_BYTE_SEL_MASK 0x00000100 5933 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_N_BYTE_SEL_ALIGN 0 5934 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_N_BYTE_SEL_BITS 1 5935 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_N_BYTE_SEL_SHIFT 8 5936 5937 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: reserved2 [07:06] */ 5938 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_N_RESERVED2_MASK 0x000000c0 5939 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_N_RESERVED2_ALIGN 0 5940 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_N_RESERVED2_BITS 2 5941 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_N_RESERVED2_SHIFT 6 5942 5943 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: ovr_step [05:00] */ 5944 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_N_OVR_STEP_MASK 0x0000003f 5945 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_N_OVR_STEP_ALIGN 0 5946 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_N_OVR_STEP_BITS 6 5947 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_N_OVR_STEP_SHIFT 0 5948 5949 5950 /**************************************************************************** 5951 * DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P 5952 */ 5953 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: busy [31:31] */ 5954 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_P_BUSY_MASK 0x80000000 5955 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_P_BUSY_ALIGN 0 5956 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_P_BUSY_BITS 1 5957 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_P_BUSY_SHIFT 31 5958 5959 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: reserved0 [30:18] */ 5960 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_P_RESERVED0_MASK 0x7ffc0000 5961 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_P_RESERVED0_ALIGN 0 5962 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_P_RESERVED0_BITS 13 5963 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_P_RESERVED0_SHIFT 18 5964 5965 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: ovr_force [17:17] */ 5966 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_P_OVR_FORCE_MASK 0x00020000 5967 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_P_OVR_FORCE_ALIGN 0 5968 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_P_OVR_FORCE_BITS 1 5969 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_P_OVR_FORCE_SHIFT 17 5970 5971 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: ovr_en [16:16] */ 5972 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_P_OVR_EN_MASK 0x00010000 5973 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_P_OVR_EN_ALIGN 0 5974 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_P_OVR_EN_BITS 1 5975 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_P_OVR_EN_SHIFT 16 5976 5977 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: reserved1 [15:09] */ 5978 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_P_RESERVED1_MASK 0x0000fe00 5979 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_P_RESERVED1_ALIGN 0 5980 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_P_RESERVED1_BITS 7 5981 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_P_RESERVED1_SHIFT 9 5982 5983 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: byte_sel [08:08] */ 5984 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_P_BYTE_SEL_MASK 0x00000100 5985 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_P_BYTE_SEL_ALIGN 0 5986 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_P_BYTE_SEL_BITS 1 5987 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_P_BYTE_SEL_SHIFT 8 5988 5989 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: reserved2 [07:06] */ 5990 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_P_RESERVED2_MASK 0x000000c0 5991 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_P_RESERVED2_ALIGN 0 5992 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_P_RESERVED2_BITS 2 5993 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_P_RESERVED2_SHIFT 6 5994 5995 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: ovr_step [05:00] */ 5996 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_P_OVR_STEP_MASK 0x0000003f 5997 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_P_OVR_STEP_ALIGN 0 5998 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_P_OVR_STEP_BITS 6 5999 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_P_OVR_STEP_SHIFT 0 6000 6001 6002 /**************************************************************************** 6003 * DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N 6004 */ 6005 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: busy [31:31] */ 6006 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_N_BUSY_MASK 0x80000000 6007 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_N_BUSY_ALIGN 0 6008 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_N_BUSY_BITS 1 6009 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_N_BUSY_SHIFT 31 6010 6011 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: reserved0 [30:18] */ 6012 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_N_RESERVED0_MASK 0x7ffc0000 6013 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_N_RESERVED0_ALIGN 0 6014 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_N_RESERVED0_BITS 13 6015 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_N_RESERVED0_SHIFT 18 6016 6017 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: ovr_force [17:17] */ 6018 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_N_OVR_FORCE_MASK 0x00020000 6019 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_N_OVR_FORCE_ALIGN 0 6020 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_N_OVR_FORCE_BITS 1 6021 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_N_OVR_FORCE_SHIFT 17 6022 6023 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: ovr_en [16:16] */ 6024 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_N_OVR_EN_MASK 0x00010000 6025 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_N_OVR_EN_ALIGN 0 6026 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_N_OVR_EN_BITS 1 6027 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_N_OVR_EN_SHIFT 16 6028 6029 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: reserved1 [15:09] */ 6030 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_N_RESERVED1_MASK 0x0000fe00 6031 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_N_RESERVED1_ALIGN 0 6032 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_N_RESERVED1_BITS 7 6033 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_N_RESERVED1_SHIFT 9 6034 6035 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: byte_sel [08:08] */ 6036 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_N_BYTE_SEL_MASK 0x00000100 6037 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_N_BYTE_SEL_ALIGN 0 6038 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_N_BYTE_SEL_BITS 1 6039 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_N_BYTE_SEL_SHIFT 8 6040 6041 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: reserved2 [07:06] */ 6042 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_N_RESERVED2_MASK 0x000000c0 6043 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_N_RESERVED2_ALIGN 0 6044 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_N_RESERVED2_BITS 2 6045 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_N_RESERVED2_SHIFT 6 6046 6047 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: ovr_step [05:00] */ 6048 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_N_OVR_STEP_MASK 0x0000003f 6049 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_N_OVR_STEP_ALIGN 0 6050 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_N_OVR_STEP_BITS 6 6051 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_N_OVR_STEP_SHIFT 0 6052 6053 6054 /**************************************************************************** 6055 * DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P 6056 */ 6057 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: busy [31:31] */ 6058 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_P_BUSY_MASK 0x80000000 6059 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_P_BUSY_ALIGN 0 6060 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_P_BUSY_BITS 1 6061 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_P_BUSY_SHIFT 31 6062 6063 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: reserved0 [30:18] */ 6064 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_P_RESERVED0_MASK 0x7ffc0000 6065 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_P_RESERVED0_ALIGN 0 6066 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_P_RESERVED0_BITS 13 6067 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_P_RESERVED0_SHIFT 18 6068 6069 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: ovr_force [17:17] */ 6070 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_P_OVR_FORCE_MASK 0x00020000 6071 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_P_OVR_FORCE_ALIGN 0 6072 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_P_OVR_FORCE_BITS 1 6073 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_P_OVR_FORCE_SHIFT 17 6074 6075 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: ovr_en [16:16] */ 6076 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_P_OVR_EN_MASK 0x00010000 6077 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_P_OVR_EN_ALIGN 0 6078 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_P_OVR_EN_BITS 1 6079 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_P_OVR_EN_SHIFT 16 6080 6081 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: reserved1 [15:09] */ 6082 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_P_RESERVED1_MASK 0x0000fe00 6083 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_P_RESERVED1_ALIGN 0 6084 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_P_RESERVED1_BITS 7 6085 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_P_RESERVED1_SHIFT 9 6086 6087 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: byte_sel [08:08] */ 6088 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_P_BYTE_SEL_MASK 0x00000100 6089 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_P_BYTE_SEL_ALIGN 0 6090 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_P_BYTE_SEL_BITS 1 6091 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_P_BYTE_SEL_SHIFT 8 6092 6093 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: reserved2 [07:06] */ 6094 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_P_RESERVED2_MASK 0x000000c0 6095 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_P_RESERVED2_ALIGN 0 6096 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_P_RESERVED2_BITS 2 6097 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_P_RESERVED2_SHIFT 6 6098 6099 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: ovr_step [05:00] */ 6100 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_P_OVR_STEP_MASK 0x0000003f 6101 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_P_OVR_STEP_ALIGN 0 6102 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_P_OVR_STEP_BITS 6 6103 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_P_OVR_STEP_SHIFT 0 6104 6105 6106 /**************************************************************************** 6107 * DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N 6108 */ 6109 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: busy [31:31] */ 6110 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_N_BUSY_MASK 0x80000000 6111 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_N_BUSY_ALIGN 0 6112 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_N_BUSY_BITS 1 6113 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_N_BUSY_SHIFT 31 6114 6115 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: reserved0 [30:18] */ 6116 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_N_RESERVED0_MASK 0x7ffc0000 6117 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_N_RESERVED0_ALIGN 0 6118 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_N_RESERVED0_BITS 13 6119 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_N_RESERVED0_SHIFT 18 6120 6121 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: ovr_force [17:17] */ 6122 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_N_OVR_FORCE_MASK 0x00020000 6123 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_N_OVR_FORCE_ALIGN 0 6124 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_N_OVR_FORCE_BITS 1 6125 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_N_OVR_FORCE_SHIFT 17 6126 6127 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: ovr_en [16:16] */ 6128 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_N_OVR_EN_MASK 0x00010000 6129 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_N_OVR_EN_ALIGN 0 6130 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_N_OVR_EN_BITS 1 6131 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_N_OVR_EN_SHIFT 16 6132 6133 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: reserved1 [15:09] */ 6134 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_N_RESERVED1_MASK 0x0000fe00 6135 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_N_RESERVED1_ALIGN 0 6136 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_N_RESERVED1_BITS 7 6137 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_N_RESERVED1_SHIFT 9 6138 6139 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: byte_sel [08:08] */ 6140 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_N_BYTE_SEL_MASK 0x00000100 6141 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_N_BYTE_SEL_ALIGN 0 6142 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_N_BYTE_SEL_BITS 1 6143 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_N_BYTE_SEL_SHIFT 8 6144 6145 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: reserved2 [07:06] */ 6146 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_N_RESERVED2_MASK 0x000000c0 6147 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_N_RESERVED2_ALIGN 0 6148 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_N_RESERVED2_BITS 2 6149 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_N_RESERVED2_SHIFT 6 6150 6151 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: ovr_step [05:00] */ 6152 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_N_OVR_STEP_MASK 0x0000003f 6153 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_N_OVR_STEP_ALIGN 0 6154 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_N_OVR_STEP_BITS 6 6155 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_N_OVR_STEP_SHIFT 0 6156 6157 6158 /**************************************************************************** 6159 * DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P 6160 */ 6161 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: busy [31:31] */ 6162 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_P_BUSY_MASK 0x80000000 6163 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_P_BUSY_ALIGN 0 6164 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_P_BUSY_BITS 1 6165 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_P_BUSY_SHIFT 31 6166 6167 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: reserved0 [30:18] */ 6168 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_P_RESERVED0_MASK 0x7ffc0000 6169 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_P_RESERVED0_ALIGN 0 6170 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_P_RESERVED0_BITS 13 6171 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_P_RESERVED0_SHIFT 18 6172 6173 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: ovr_force [17:17] */ 6174 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_P_OVR_FORCE_MASK 0x00020000 6175 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_P_OVR_FORCE_ALIGN 0 6176 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_P_OVR_FORCE_BITS 1 6177 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_P_OVR_FORCE_SHIFT 17 6178 6179 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: ovr_en [16:16] */ 6180 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_P_OVR_EN_MASK 0x00010000 6181 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_P_OVR_EN_ALIGN 0 6182 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_P_OVR_EN_BITS 1 6183 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_P_OVR_EN_SHIFT 16 6184 6185 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: reserved1 [15:09] */ 6186 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_P_RESERVED1_MASK 0x0000fe00 6187 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_P_RESERVED1_ALIGN 0 6188 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_P_RESERVED1_BITS 7 6189 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_P_RESERVED1_SHIFT 9 6190 6191 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: byte_sel [08:08] */ 6192 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_P_BYTE_SEL_MASK 0x00000100 6193 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_P_BYTE_SEL_ALIGN 0 6194 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_P_BYTE_SEL_BITS 1 6195 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_P_BYTE_SEL_SHIFT 8 6196 6197 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: reserved2 [07:06] */ 6198 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_P_RESERVED2_MASK 0x000000c0 6199 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_P_RESERVED2_ALIGN 0 6200 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_P_RESERVED2_BITS 2 6201 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_P_RESERVED2_SHIFT 6 6202 6203 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: ovr_step [05:00] */ 6204 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_P_OVR_STEP_MASK 0x0000003f 6205 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_P_OVR_STEP_ALIGN 0 6206 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_P_OVR_STEP_BITS 6 6207 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_P_OVR_STEP_SHIFT 0 6208 6209 6210 /**************************************************************************** 6211 * DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N 6212 */ 6213 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: busy [31:31] */ 6214 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_N_BUSY_MASK 0x80000000 6215 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_N_BUSY_ALIGN 0 6216 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_N_BUSY_BITS 1 6217 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_N_BUSY_SHIFT 31 6218 6219 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: reserved0 [30:18] */ 6220 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_N_RESERVED0_MASK 0x7ffc0000 6221 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_N_RESERVED0_ALIGN 0 6222 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_N_RESERVED0_BITS 13 6223 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_N_RESERVED0_SHIFT 18 6224 6225 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: ovr_force [17:17] */ 6226 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_N_OVR_FORCE_MASK 0x00020000 6227 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_N_OVR_FORCE_ALIGN 0 6228 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_N_OVR_FORCE_BITS 1 6229 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_N_OVR_FORCE_SHIFT 17 6230 6231 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: ovr_en [16:16] */ 6232 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_N_OVR_EN_MASK 0x00010000 6233 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_N_OVR_EN_ALIGN 0 6234 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_N_OVR_EN_BITS 1 6235 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_N_OVR_EN_SHIFT 16 6236 6237 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: reserved1 [15:09] */ 6238 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_N_RESERVED1_MASK 0x0000fe00 6239 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_N_RESERVED1_ALIGN 0 6240 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_N_RESERVED1_BITS 7 6241 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_N_RESERVED1_SHIFT 9 6242 6243 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: byte_sel [08:08] */ 6244 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_N_BYTE_SEL_MASK 0x00000100 6245 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_N_BYTE_SEL_ALIGN 0 6246 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_N_BYTE_SEL_BITS 1 6247 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_N_BYTE_SEL_SHIFT 8 6248 6249 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: reserved2 [07:06] */ 6250 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_N_RESERVED2_MASK 0x000000c0 6251 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_N_RESERVED2_ALIGN 0 6252 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_N_RESERVED2_BITS 2 6253 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_N_RESERVED2_SHIFT 6 6254 6255 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: ovr_step [05:00] */ 6256 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_N_OVR_STEP_MASK 0x0000003f 6257 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_N_OVR_STEP_ALIGN 0 6258 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_N_OVR_STEP_BITS 6 6259 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_N_OVR_STEP_SHIFT 0 6260 6261 6262 /**************************************************************************** 6263 * DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P 6264 */ 6265 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: busy [31:31] */ 6266 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_P_BUSY_MASK 0x80000000 6267 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_P_BUSY_ALIGN 0 6268 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_P_BUSY_BITS 1 6269 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_P_BUSY_SHIFT 31 6270 6271 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: reserved0 [30:18] */ 6272 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_P_RESERVED0_MASK 0x7ffc0000 6273 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_P_RESERVED0_ALIGN 0 6274 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_P_RESERVED0_BITS 13 6275 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_P_RESERVED0_SHIFT 18 6276 6277 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: ovr_force [17:17] */ 6278 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_P_OVR_FORCE_MASK 0x00020000 6279 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_P_OVR_FORCE_ALIGN 0 6280 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_P_OVR_FORCE_BITS 1 6281 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_P_OVR_FORCE_SHIFT 17 6282 6283 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: ovr_en [16:16] */ 6284 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_P_OVR_EN_MASK 0x00010000 6285 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_P_OVR_EN_ALIGN 0 6286 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_P_OVR_EN_BITS 1 6287 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_P_OVR_EN_SHIFT 16 6288 6289 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: reserved1 [15:09] */ 6290 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_P_RESERVED1_MASK 0x0000fe00 6291 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_P_RESERVED1_ALIGN 0 6292 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_P_RESERVED1_BITS 7 6293 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_P_RESERVED1_SHIFT 9 6294 6295 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: byte_sel [08:08] */ 6296 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_P_BYTE_SEL_MASK 0x00000100 6297 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_P_BYTE_SEL_ALIGN 0 6298 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_P_BYTE_SEL_BITS 1 6299 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_P_BYTE_SEL_SHIFT 8 6300 6301 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: reserved2 [07:06] */ 6302 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_P_RESERVED2_MASK 0x000000c0 6303 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_P_RESERVED2_ALIGN 0 6304 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_P_RESERVED2_BITS 2 6305 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_P_RESERVED2_SHIFT 6 6306 6307 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: ovr_step [05:00] */ 6308 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_P_OVR_STEP_MASK 0x0000003f 6309 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_P_OVR_STEP_ALIGN 0 6310 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_P_OVR_STEP_BITS 6 6311 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_P_OVR_STEP_SHIFT 0 6312 6313 6314 /**************************************************************************** 6315 * DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N 6316 */ 6317 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: busy [31:31] */ 6318 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_N_BUSY_MASK 0x80000000 6319 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_N_BUSY_ALIGN 0 6320 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_N_BUSY_BITS 1 6321 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_N_BUSY_SHIFT 31 6322 6323 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: reserved0 [30:18] */ 6324 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_N_RESERVED0_MASK 0x7ffc0000 6325 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_N_RESERVED0_ALIGN 0 6326 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_N_RESERVED0_BITS 13 6327 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_N_RESERVED0_SHIFT 18 6328 6329 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: ovr_force [17:17] */ 6330 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_N_OVR_FORCE_MASK 0x00020000 6331 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_N_OVR_FORCE_ALIGN 0 6332 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_N_OVR_FORCE_BITS 1 6333 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_N_OVR_FORCE_SHIFT 17 6334 6335 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: ovr_en [16:16] */ 6336 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_N_OVR_EN_MASK 0x00010000 6337 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_N_OVR_EN_ALIGN 0 6338 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_N_OVR_EN_BITS 1 6339 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_N_OVR_EN_SHIFT 16 6340 6341 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: reserved1 [15:09] */ 6342 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_N_RESERVED1_MASK 0x0000fe00 6343 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_N_RESERVED1_ALIGN 0 6344 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_N_RESERVED1_BITS 7 6345 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_N_RESERVED1_SHIFT 9 6346 6347 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: byte_sel [08:08] */ 6348 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_N_BYTE_SEL_MASK 0x00000100 6349 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_N_BYTE_SEL_ALIGN 0 6350 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_N_BYTE_SEL_BITS 1 6351 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_N_BYTE_SEL_SHIFT 8 6352 6353 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: reserved2 [07:06] */ 6354 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_N_RESERVED2_MASK 0x000000c0 6355 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_N_RESERVED2_ALIGN 0 6356 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_N_RESERVED2_BITS 2 6357 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_N_RESERVED2_SHIFT 6 6358 6359 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: ovr_step [05:00] */ 6360 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_N_OVR_STEP_MASK 0x0000003f 6361 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_N_OVR_STEP_ALIGN 0 6362 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_N_OVR_STEP_BITS 6 6363 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_N_OVR_STEP_SHIFT 0 6364 6365 6366 /**************************************************************************** 6367 * DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P 6368 */ 6369 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: busy [31:31] */ 6370 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_P_BUSY_MASK 0x80000000 6371 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_P_BUSY_ALIGN 0 6372 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_P_BUSY_BITS 1 6373 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_P_BUSY_SHIFT 31 6374 6375 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: reserved0 [30:18] */ 6376 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_P_RESERVED0_MASK 0x7ffc0000 6377 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_P_RESERVED0_ALIGN 0 6378 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_P_RESERVED0_BITS 13 6379 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_P_RESERVED0_SHIFT 18 6380 6381 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: ovr_force [17:17] */ 6382 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_P_OVR_FORCE_MASK 0x00020000 6383 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_P_OVR_FORCE_ALIGN 0 6384 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_P_OVR_FORCE_BITS 1 6385 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_P_OVR_FORCE_SHIFT 17 6386 6387 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: ovr_en [16:16] */ 6388 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_P_OVR_EN_MASK 0x00010000 6389 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_P_OVR_EN_ALIGN 0 6390 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_P_OVR_EN_BITS 1 6391 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_P_OVR_EN_SHIFT 16 6392 6393 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: reserved1 [15:09] */ 6394 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_P_RESERVED1_MASK 0x0000fe00 6395 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_P_RESERVED1_ALIGN 0 6396 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_P_RESERVED1_BITS 7 6397 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_P_RESERVED1_SHIFT 9 6398 6399 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: byte_sel [08:08] */ 6400 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_P_BYTE_SEL_MASK 0x00000100 6401 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_P_BYTE_SEL_ALIGN 0 6402 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_P_BYTE_SEL_BITS 1 6403 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_P_BYTE_SEL_SHIFT 8 6404 6405 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: reserved2 [07:06] */ 6406 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_P_RESERVED2_MASK 0x000000c0 6407 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_P_RESERVED2_ALIGN 0 6408 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_P_RESERVED2_BITS 2 6409 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_P_RESERVED2_SHIFT 6 6410 6411 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: ovr_step [05:00] */ 6412 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_P_OVR_STEP_MASK 0x0000003f 6413 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_P_OVR_STEP_ALIGN 0 6414 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_P_OVR_STEP_BITS 6 6415 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_P_OVR_STEP_SHIFT 0 6416 6417 6418 /**************************************************************************** 6419 * DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N 6420 */ 6421 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: busy [31:31] */ 6422 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_N_BUSY_MASK 0x80000000 6423 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_N_BUSY_ALIGN 0 6424 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_N_BUSY_BITS 1 6425 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_N_BUSY_SHIFT 31 6426 6427 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: reserved0 [30:18] */ 6428 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_N_RESERVED0_MASK 0x7ffc0000 6429 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_N_RESERVED0_ALIGN 0 6430 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_N_RESERVED0_BITS 13 6431 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_N_RESERVED0_SHIFT 18 6432 6433 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: ovr_force [17:17] */ 6434 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_N_OVR_FORCE_MASK 0x00020000 6435 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_N_OVR_FORCE_ALIGN 0 6436 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_N_OVR_FORCE_BITS 1 6437 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_N_OVR_FORCE_SHIFT 17 6438 6439 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: ovr_en [16:16] */ 6440 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_N_OVR_EN_MASK 0x00010000 6441 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_N_OVR_EN_ALIGN 0 6442 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_N_OVR_EN_BITS 1 6443 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_N_OVR_EN_SHIFT 16 6444 6445 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: reserved1 [15:09] */ 6446 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_N_RESERVED1_MASK 0x0000fe00 6447 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_N_RESERVED1_ALIGN 0 6448 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_N_RESERVED1_BITS 7 6449 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_N_RESERVED1_SHIFT 9 6450 6451 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: byte_sel [08:08] */ 6452 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_N_BYTE_SEL_MASK 0x00000100 6453 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_N_BYTE_SEL_ALIGN 0 6454 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_N_BYTE_SEL_BITS 1 6455 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_N_BYTE_SEL_SHIFT 8 6456 6457 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: reserved2 [07:06] */ 6458 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_N_RESERVED2_MASK 0x000000c0 6459 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_N_RESERVED2_ALIGN 0 6460 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_N_RESERVED2_BITS 2 6461 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_N_RESERVED2_SHIFT 6 6462 6463 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: ovr_step [05:00] */ 6464 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_N_OVR_STEP_MASK 0x0000003f 6465 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_N_OVR_STEP_ALIGN 0 6466 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_N_OVR_STEP_BITS 6 6467 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_N_OVR_STEP_SHIFT 0 6468 6469 6470 /**************************************************************************** 6471 * DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P 6472 */ 6473 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: busy [31:31] */ 6474 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_P_BUSY_MASK 0x80000000 6475 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_P_BUSY_ALIGN 0 6476 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_P_BUSY_BITS 1 6477 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_P_BUSY_SHIFT 31 6478 6479 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: reserved0 [30:18] */ 6480 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_P_RESERVED0_MASK 0x7ffc0000 6481 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_P_RESERVED0_ALIGN 0 6482 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_P_RESERVED0_BITS 13 6483 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_P_RESERVED0_SHIFT 18 6484 6485 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: ovr_force [17:17] */ 6486 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_P_OVR_FORCE_MASK 0x00020000 6487 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_P_OVR_FORCE_ALIGN 0 6488 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_P_OVR_FORCE_BITS 1 6489 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_P_OVR_FORCE_SHIFT 17 6490 6491 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: ovr_en [16:16] */ 6492 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_P_OVR_EN_MASK 0x00010000 6493 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_P_OVR_EN_ALIGN 0 6494 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_P_OVR_EN_BITS 1 6495 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_P_OVR_EN_SHIFT 16 6496 6497 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: reserved1 [15:09] */ 6498 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_P_RESERVED1_MASK 0x0000fe00 6499 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_P_RESERVED1_ALIGN 0 6500 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_P_RESERVED1_BITS 7 6501 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_P_RESERVED1_SHIFT 9 6502 6503 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: byte_sel [08:08] */ 6504 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_P_BYTE_SEL_MASK 0x00000100 6505 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_P_BYTE_SEL_ALIGN 0 6506 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_P_BYTE_SEL_BITS 1 6507 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_P_BYTE_SEL_SHIFT 8 6508 6509 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: reserved2 [07:06] */ 6510 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_P_RESERVED2_MASK 0x000000c0 6511 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_P_RESERVED2_ALIGN 0 6512 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_P_RESERVED2_BITS 2 6513 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_P_RESERVED2_SHIFT 6 6514 6515 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: ovr_step [05:00] */ 6516 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_P_OVR_STEP_MASK 0x0000003f 6517 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_P_OVR_STEP_ALIGN 0 6518 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_P_OVR_STEP_BITS 6 6519 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_P_OVR_STEP_SHIFT 0 6520 6521 6522 /**************************************************************************** 6523 * DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N 6524 */ 6525 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: busy [31:31] */ 6526 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_N_BUSY_MASK 0x80000000 6527 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_N_BUSY_ALIGN 0 6528 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_N_BUSY_BITS 1 6529 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_N_BUSY_SHIFT 31 6530 6531 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: reserved0 [30:18] */ 6532 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_N_RESERVED0_MASK 0x7ffc0000 6533 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_N_RESERVED0_ALIGN 0 6534 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_N_RESERVED0_BITS 13 6535 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_N_RESERVED0_SHIFT 18 6536 6537 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: ovr_force [17:17] */ 6538 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_N_OVR_FORCE_MASK 0x00020000 6539 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_N_OVR_FORCE_ALIGN 0 6540 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_N_OVR_FORCE_BITS 1 6541 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_N_OVR_FORCE_SHIFT 17 6542 6543 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: ovr_en [16:16] */ 6544 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_N_OVR_EN_MASK 0x00010000 6545 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_N_OVR_EN_ALIGN 0 6546 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_N_OVR_EN_BITS 1 6547 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_N_OVR_EN_SHIFT 16 6548 6549 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: reserved1 [15:09] */ 6550 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_N_RESERVED1_MASK 0x0000fe00 6551 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_N_RESERVED1_ALIGN 0 6552 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_N_RESERVED1_BITS 7 6553 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_N_RESERVED1_SHIFT 9 6554 6555 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: byte_sel [08:08] */ 6556 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_N_BYTE_SEL_MASK 0x00000100 6557 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_N_BYTE_SEL_ALIGN 0 6558 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_N_BYTE_SEL_BITS 1 6559 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_N_BYTE_SEL_SHIFT 8 6560 6561 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: reserved2 [07:06] */ 6562 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_N_RESERVED2_MASK 0x000000c0 6563 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_N_RESERVED2_ALIGN 0 6564 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_N_RESERVED2_BITS 2 6565 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_N_RESERVED2_SHIFT 6 6566 6567 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: ovr_step [05:00] */ 6568 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_N_OVR_STEP_MASK 0x0000003f 6569 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_N_OVR_STEP_ALIGN 0 6570 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_N_OVR_STEP_BITS 6 6571 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_N_OVR_STEP_SHIFT 0 6572 6573 6574 /**************************************************************************** 6575 * DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P 6576 */ 6577 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: busy [31:31] */ 6578 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_P_BUSY_MASK 0x80000000 6579 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_P_BUSY_ALIGN 0 6580 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_P_BUSY_BITS 1 6581 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_P_BUSY_SHIFT 31 6582 6583 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: reserved0 [30:18] */ 6584 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_P_RESERVED0_MASK 0x7ffc0000 6585 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_P_RESERVED0_ALIGN 0 6586 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_P_RESERVED0_BITS 13 6587 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_P_RESERVED0_SHIFT 18 6588 6589 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: ovr_force [17:17] */ 6590 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_P_OVR_FORCE_MASK 0x00020000 6591 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_P_OVR_FORCE_ALIGN 0 6592 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_P_OVR_FORCE_BITS 1 6593 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_P_OVR_FORCE_SHIFT 17 6594 6595 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: ovr_en [16:16] */ 6596 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_P_OVR_EN_MASK 0x00010000 6597 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_P_OVR_EN_ALIGN 0 6598 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_P_OVR_EN_BITS 1 6599 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_P_OVR_EN_SHIFT 16 6600 6601 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: reserved1 [15:09] */ 6602 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_P_RESERVED1_MASK 0x0000fe00 6603 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_P_RESERVED1_ALIGN 0 6604 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_P_RESERVED1_BITS 7 6605 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_P_RESERVED1_SHIFT 9 6606 6607 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: byte_sel [08:08] */ 6608 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_P_BYTE_SEL_MASK 0x00000100 6609 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_P_BYTE_SEL_ALIGN 0 6610 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_P_BYTE_SEL_BITS 1 6611 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_P_BYTE_SEL_SHIFT 8 6612 6613 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: reserved2 [07:06] */ 6614 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_P_RESERVED2_MASK 0x000000c0 6615 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_P_RESERVED2_ALIGN 0 6616 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_P_RESERVED2_BITS 2 6617 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_P_RESERVED2_SHIFT 6 6618 6619 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: ovr_step [05:00] */ 6620 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_P_OVR_STEP_MASK 0x0000003f 6621 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_P_OVR_STEP_ALIGN 0 6622 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_P_OVR_STEP_BITS 6 6623 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_P_OVR_STEP_SHIFT 0 6624 6625 6626 /**************************************************************************** 6627 * DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N 6628 */ 6629 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: busy [31:31] */ 6630 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_N_BUSY_MASK 0x80000000 6631 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_N_BUSY_ALIGN 0 6632 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_N_BUSY_BITS 1 6633 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_N_BUSY_SHIFT 31 6634 6635 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: reserved0 [30:18] */ 6636 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_N_RESERVED0_MASK 0x7ffc0000 6637 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_N_RESERVED0_ALIGN 0 6638 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_N_RESERVED0_BITS 13 6639 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_N_RESERVED0_SHIFT 18 6640 6641 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: ovr_force [17:17] */ 6642 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_N_OVR_FORCE_MASK 0x00020000 6643 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_N_OVR_FORCE_ALIGN 0 6644 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_N_OVR_FORCE_BITS 1 6645 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_N_OVR_FORCE_SHIFT 17 6646 6647 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: ovr_en [16:16] */ 6648 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_N_OVR_EN_MASK 0x00010000 6649 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_N_OVR_EN_ALIGN 0 6650 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_N_OVR_EN_BITS 1 6651 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_N_OVR_EN_SHIFT 16 6652 6653 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: reserved1 [15:09] */ 6654 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_N_RESERVED1_MASK 0x0000fe00 6655 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_N_RESERVED1_ALIGN 0 6656 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_N_RESERVED1_BITS 7 6657 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_N_RESERVED1_SHIFT 9 6658 6659 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: byte_sel [08:08] */ 6660 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_N_BYTE_SEL_MASK 0x00000100 6661 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_N_BYTE_SEL_ALIGN 0 6662 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_N_BYTE_SEL_BITS 1 6663 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_N_BYTE_SEL_SHIFT 8 6664 6665 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: reserved2 [07:06] */ 6666 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_N_RESERVED2_MASK 0x000000c0 6667 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_N_RESERVED2_ALIGN 0 6668 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_N_RESERVED2_BITS 2 6669 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_N_RESERVED2_SHIFT 6 6670 6671 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: ovr_step [05:00] */ 6672 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_N_OVR_STEP_MASK 0x0000003f 6673 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_N_OVR_STEP_ALIGN 0 6674 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_N_OVR_STEP_BITS 6 6675 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_N_OVR_STEP_SHIFT 0 6676 6677 6678 /**************************************************************************** 6679 * DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN 6680 */ 6681 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: busy [31:31] */ 6682 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_BUSY_MASK 0x80000000 6683 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_BUSY_ALIGN 0 6684 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_BUSY_BITS 1 6685 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_BUSY_SHIFT 31 6686 6687 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: reserved0 [30:18] */ 6688 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_RESERVED0_MASK 0x7ffc0000 6689 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_RESERVED0_ALIGN 0 6690 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_RESERVED0_BITS 13 6691 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_RESERVED0_SHIFT 18 6692 6693 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: ovr_force [17:17] */ 6694 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_OVR_FORCE_MASK 0x00020000 6695 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_OVR_FORCE_ALIGN 0 6696 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_OVR_FORCE_BITS 1 6697 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_OVR_FORCE_SHIFT 17 6698 6699 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: ovr_en [16:16] */ 6700 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_OVR_EN_MASK 0x00010000 6701 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_OVR_EN_ALIGN 0 6702 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_OVR_EN_BITS 1 6703 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_OVR_EN_SHIFT 16 6704 6705 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: reserved1 [15:09] */ 6706 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_RESERVED1_MASK 0x0000fe00 6707 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_RESERVED1_ALIGN 0 6708 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_RESERVED1_BITS 7 6709 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_RESERVED1_SHIFT 9 6710 6711 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: byte_sel [08:08] */ 6712 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_BYTE_SEL_MASK 0x00000100 6713 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_BYTE_SEL_ALIGN 0 6714 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_BYTE_SEL_BITS 1 6715 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_BYTE_SEL_SHIFT 8 6716 6717 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: reserved2 [07:06] */ 6718 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_RESERVED2_MASK 0x000000c0 6719 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_RESERVED2_ALIGN 0 6720 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_RESERVED2_BITS 2 6721 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_RESERVED2_SHIFT 6 6722 6723 /* DDR40_PHY_WORD_LANE_0 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: ovr_step [05:00] */ 6724 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_OVR_STEP_MASK 0x0000003f 6725 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_OVR_STEP_ALIGN 0 6726 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_OVR_STEP_BITS 6 6727 #define DDR40_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT_RD_EN_OVR_STEP_SHIFT 0 6728 6729 6730 /**************************************************************************** 6731 * DDR40_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE0_R_P 6732 */ 6733 /* DDR40_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE0_R_P :: reserved0 [31:17] */ 6734 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_R_P_RESERVED0_MASK 0xfffe0000 6735 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_R_P_RESERVED0_ALIGN 0 6736 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_R_P_RESERVED0_BITS 15 6737 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_R_P_RESERVED0_SHIFT 17 6738 6739 /* DDR40_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE0_R_P :: ovr_en [16:16] */ 6740 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_R_P_OVR_EN_MASK 0x00010000 6741 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_R_P_OVR_EN_ALIGN 0 6742 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_R_P_OVR_EN_BITS 1 6743 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_R_P_OVR_EN_SHIFT 16 6744 6745 /* DDR40_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE0_R_P :: reserved1 [15:09] */ 6746 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_R_P_RESERVED1_MASK 0x0000fe00 6747 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_R_P_RESERVED1_ALIGN 0 6748 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_R_P_RESERVED1_BITS 7 6749 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_R_P_RESERVED1_SHIFT 9 6750 6751 /* DDR40_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE0_R_P :: byte_sel [08:08] */ 6752 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_R_P_BYTE_SEL_MASK 0x00000100 6753 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_R_P_BYTE_SEL_ALIGN 0 6754 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_R_P_BYTE_SEL_BITS 1 6755 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_R_P_BYTE_SEL_SHIFT 8 6756 6757 /* DDR40_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE0_R_P :: reserved2 [07:06] */ 6758 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_R_P_RESERVED2_MASK 0x000000c0 6759 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_R_P_RESERVED2_ALIGN 0 6760 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_R_P_RESERVED2_BITS 2 6761 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_R_P_RESERVED2_SHIFT 6 6762 6763 /* DDR40_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE0_R_P :: ovr_step [05:00] */ 6764 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_R_P_OVR_STEP_MASK 0x0000003f 6765 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_R_P_OVR_STEP_ALIGN 0 6766 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_R_P_OVR_STEP_BITS 6 6767 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_R_P_OVR_STEP_SHIFT 0 6768 6769 6770 /**************************************************************************** 6771 * DDR40_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE0_R_N 6772 */ 6773 /* DDR40_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE0_R_N :: reserved0 [31:17] */ 6774 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_R_N_RESERVED0_MASK 0xfffe0000 6775 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_R_N_RESERVED0_ALIGN 0 6776 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_R_N_RESERVED0_BITS 15 6777 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_R_N_RESERVED0_SHIFT 17 6778 6779 /* DDR40_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE0_R_N :: ovr_en [16:16] */ 6780 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_R_N_OVR_EN_MASK 0x00010000 6781 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_R_N_OVR_EN_ALIGN 0 6782 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_R_N_OVR_EN_BITS 1 6783 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_R_N_OVR_EN_SHIFT 16 6784 6785 /* DDR40_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE0_R_N :: reserved1 [15:09] */ 6786 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_R_N_RESERVED1_MASK 0x0000fe00 6787 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_R_N_RESERVED1_ALIGN 0 6788 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_R_N_RESERVED1_BITS 7 6789 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_R_N_RESERVED1_SHIFT 9 6790 6791 /* DDR40_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE0_R_N :: byte_sel [08:08] */ 6792 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_R_N_BYTE_SEL_MASK 0x00000100 6793 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_R_N_BYTE_SEL_ALIGN 0 6794 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_R_N_BYTE_SEL_BITS 1 6795 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_R_N_BYTE_SEL_SHIFT 8 6796 6797 /* DDR40_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE0_R_N :: reserved2 [07:06] */ 6798 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_R_N_RESERVED2_MASK 0x000000c0 6799 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_R_N_RESERVED2_ALIGN 0 6800 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_R_N_RESERVED2_BITS 2 6801 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_R_N_RESERVED2_SHIFT 6 6802 6803 /* DDR40_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE0_R_N :: ovr_step [05:00] */ 6804 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_R_N_OVR_STEP_MASK 0x0000003f 6805 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_R_N_OVR_STEP_ALIGN 0 6806 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_R_N_OVR_STEP_BITS 6 6807 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_R_N_OVR_STEP_SHIFT 0 6808 6809 6810 /**************************************************************************** 6811 * DDR40_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P 6812 */ 6813 /* DDR40_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: reserved0 [31:25] */ 6814 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_RESERVED0_MASK 0xfe000000 6815 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_RESERVED0_ALIGN 0 6816 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_RESERVED0_BITS 7 6817 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_RESERVED0_SHIFT 25 6818 6819 /* DDR40_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: dm_ovr_en [24:24] */ 6820 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_DM_OVR_EN_MASK 0x01000000 6821 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_DM_OVR_EN_ALIGN 0 6822 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_DM_OVR_EN_BITS 1 6823 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_DM_OVR_EN_SHIFT 24 6824 6825 /* DDR40_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: ovr_en [23:16] */ 6826 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_OVR_EN_MASK 0x00ff0000 6827 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_OVR_EN_ALIGN 0 6828 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_OVR_EN_BITS 8 6829 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_OVR_EN_SHIFT 16 6830 6831 /* DDR40_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: reserved1 [15:09] */ 6832 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_RESERVED1_MASK 0x0000fe00 6833 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_RESERVED1_ALIGN 0 6834 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_RESERVED1_BITS 7 6835 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_RESERVED1_SHIFT 9 6836 6837 /* DDR40_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: byte_sel [08:08] */ 6838 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_BYTE_SEL_MASK 0x00000100 6839 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_BYTE_SEL_ALIGN 0 6840 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_BYTE_SEL_BITS 1 6841 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_BYTE_SEL_SHIFT 8 6842 6843 /* DDR40_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: reserved2 [07:06] */ 6844 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_RESERVED2_MASK 0x000000c0 6845 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_RESERVED2_ALIGN 0 6846 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_RESERVED2_BITS 2 6847 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_RESERVED2_SHIFT 6 6848 6849 /* DDR40_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: ovr_step [05:00] */ 6850 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_OVR_STEP_MASK 0x0000003f 6851 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_OVR_STEP_ALIGN 0 6852 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_OVR_STEP_BITS 6 6853 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_OVR_STEP_SHIFT 0 6854 6855 6856 /**************************************************************************** 6857 * DDR40_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N 6858 */ 6859 /* DDR40_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: reserved0 [31:25] */ 6860 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_RESERVED0_MASK 0xfe000000 6861 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_RESERVED0_ALIGN 0 6862 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_RESERVED0_BITS 7 6863 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_RESERVED0_SHIFT 25 6864 6865 /* DDR40_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: dm_ovr_en [24:24] */ 6866 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_DM_OVR_EN_MASK 0x01000000 6867 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_DM_OVR_EN_ALIGN 0 6868 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_DM_OVR_EN_BITS 1 6869 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_DM_OVR_EN_SHIFT 24 6870 6871 /* DDR40_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: ovr_en [23:16] */ 6872 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_OVR_EN_MASK 0x00ff0000 6873 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_OVR_EN_ALIGN 0 6874 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_OVR_EN_BITS 8 6875 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_OVR_EN_SHIFT 16 6876 6877 /* DDR40_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: reserved1 [15:09] */ 6878 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_RESERVED1_MASK 0x0000fe00 6879 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_RESERVED1_ALIGN 0 6880 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_RESERVED1_BITS 7 6881 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_RESERVED1_SHIFT 9 6882 6883 /* DDR40_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: byte_sel [08:08] */ 6884 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_BYTE_SEL_MASK 0x00000100 6885 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_BYTE_SEL_ALIGN 0 6886 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_BYTE_SEL_BITS 1 6887 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_BYTE_SEL_SHIFT 8 6888 6889 /* DDR40_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: reserved2 [07:06] */ 6890 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_RESERVED2_MASK 0x000000c0 6891 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_RESERVED2_ALIGN 0 6892 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_RESERVED2_BITS 2 6893 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_RESERVED2_SHIFT 6 6894 6895 /* DDR40_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: ovr_step [05:00] */ 6896 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_OVR_STEP_MASK 0x0000003f 6897 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_OVR_STEP_ALIGN 0 6898 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_OVR_STEP_BITS 6 6899 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_OVR_STEP_SHIFT 0 6900 6901 6902 /**************************************************************************** 6903 * DDR40_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE0_W 6904 */ 6905 /* DDR40_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE0_W :: reserved0 [31:17] */ 6906 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_W_RESERVED0_MASK 0xfffe0000 6907 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_W_RESERVED0_ALIGN 0 6908 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_W_RESERVED0_BITS 15 6909 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_W_RESERVED0_SHIFT 17 6910 6911 /* DDR40_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE0_W :: ovr_en [16:16] */ 6912 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_W_OVR_EN_MASK 0x00010000 6913 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_W_OVR_EN_ALIGN 0 6914 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_W_OVR_EN_BITS 1 6915 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_W_OVR_EN_SHIFT 16 6916 6917 /* DDR40_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE0_W :: reserved1 [15:09] */ 6918 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_W_RESERVED1_MASK 0x0000fe00 6919 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_W_RESERVED1_ALIGN 0 6920 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_W_RESERVED1_BITS 7 6921 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_W_RESERVED1_SHIFT 9 6922 6923 /* DDR40_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE0_W :: byte_sel [08:08] */ 6924 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_W_BYTE_SEL_MASK 0x00000100 6925 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_W_BYTE_SEL_ALIGN 0 6926 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_W_BYTE_SEL_BITS 1 6927 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_W_BYTE_SEL_SHIFT 8 6928 6929 /* DDR40_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE0_W :: reserved2 [07:06] */ 6930 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_W_RESERVED2_MASK 0x000000c0 6931 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_W_RESERVED2_ALIGN 0 6932 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_W_RESERVED2_BITS 2 6933 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_W_RESERVED2_SHIFT 6 6934 6935 /* DDR40_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE0_W :: ovr_step [05:00] */ 6936 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_W_OVR_STEP_MASK 0x0000003f 6937 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_W_OVR_STEP_ALIGN 0 6938 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_W_OVR_STEP_BITS 6 6939 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_W_OVR_STEP_SHIFT 0 6940 6941 6942 /**************************************************************************** 6943 * DDR40_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_W 6944 */ 6945 /* DDR40_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: reserved0 [31:25] */ 6946 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_RESERVED0_MASK 0xfe000000 6947 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_RESERVED0_ALIGN 0 6948 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_RESERVED0_BITS 7 6949 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_RESERVED0_SHIFT 25 6950 6951 /* DDR40_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: dm_ovr_en [24:24] */ 6952 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_DM_OVR_EN_MASK 0x01000000 6953 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_DM_OVR_EN_ALIGN 0 6954 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_DM_OVR_EN_BITS 1 6955 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_DM_OVR_EN_SHIFT 24 6956 6957 /* DDR40_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: ovr_en [23:16] */ 6958 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_OVR_EN_MASK 0x00ff0000 6959 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_OVR_EN_ALIGN 0 6960 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_OVR_EN_BITS 8 6961 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_OVR_EN_SHIFT 16 6962 6963 /* DDR40_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: reserved1 [15:09] */ 6964 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_RESERVED1_MASK 0x0000fe00 6965 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_RESERVED1_ALIGN 0 6966 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_RESERVED1_BITS 7 6967 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_RESERVED1_SHIFT 9 6968 6969 /* DDR40_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: byte_sel [08:08] */ 6970 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_BYTE_SEL_MASK 0x00000100 6971 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_BYTE_SEL_ALIGN 0 6972 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_BYTE_SEL_BITS 1 6973 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_BYTE_SEL_SHIFT 8 6974 6975 /* DDR40_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: reserved2 [07:06] */ 6976 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_RESERVED2_MASK 0x000000c0 6977 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_RESERVED2_ALIGN 0 6978 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_RESERVED2_BITS 2 6979 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_RESERVED2_SHIFT 6 6980 6981 /* DDR40_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: ovr_step [05:00] */ 6982 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_OVR_STEP_MASK 0x0000003f 6983 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_OVR_STEP_ALIGN 0 6984 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_OVR_STEP_BITS 6 6985 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_W_OVR_STEP_SHIFT 0 6986 6987 6988 /**************************************************************************** 6989 * DDR40_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE1_R_P 6990 */ 6991 /* DDR40_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE1_R_P :: reserved0 [31:17] */ 6992 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_R_P_RESERVED0_MASK 0xfffe0000 6993 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_R_P_RESERVED0_ALIGN 0 6994 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_R_P_RESERVED0_BITS 15 6995 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_R_P_RESERVED0_SHIFT 17 6996 6997 /* DDR40_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE1_R_P :: ovr_en [16:16] */ 6998 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_R_P_OVR_EN_MASK 0x00010000 6999 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_R_P_OVR_EN_ALIGN 0 7000 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_R_P_OVR_EN_BITS 1 7001 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_R_P_OVR_EN_SHIFT 16 7002 7003 /* DDR40_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE1_R_P :: reserved1 [15:09] */ 7004 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_R_P_RESERVED1_MASK 0x0000fe00 7005 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_R_P_RESERVED1_ALIGN 0 7006 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_R_P_RESERVED1_BITS 7 7007 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_R_P_RESERVED1_SHIFT 9 7008 7009 /* DDR40_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE1_R_P :: byte_sel [08:08] */ 7010 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_R_P_BYTE_SEL_MASK 0x00000100 7011 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_R_P_BYTE_SEL_ALIGN 0 7012 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_R_P_BYTE_SEL_BITS 1 7013 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_R_P_BYTE_SEL_SHIFT 8 7014 7015 /* DDR40_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE1_R_P :: reserved2 [07:06] */ 7016 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_R_P_RESERVED2_MASK 0x000000c0 7017 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_R_P_RESERVED2_ALIGN 0 7018 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_R_P_RESERVED2_BITS 2 7019 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_R_P_RESERVED2_SHIFT 6 7020 7021 /* DDR40_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE1_R_P :: ovr_step [05:00] */ 7022 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_R_P_OVR_STEP_MASK 0x0000003f 7023 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_R_P_OVR_STEP_ALIGN 0 7024 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_R_P_OVR_STEP_BITS 6 7025 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_R_P_OVR_STEP_SHIFT 0 7026 7027 7028 /**************************************************************************** 7029 * DDR40_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE1_R_N 7030 */ 7031 /* DDR40_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE1_R_N :: reserved0 [31:17] */ 7032 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_R_N_RESERVED0_MASK 0xfffe0000 7033 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_R_N_RESERVED0_ALIGN 0 7034 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_R_N_RESERVED0_BITS 15 7035 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_R_N_RESERVED0_SHIFT 17 7036 7037 /* DDR40_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE1_R_N :: ovr_en [16:16] */ 7038 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_R_N_OVR_EN_MASK 0x00010000 7039 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_R_N_OVR_EN_ALIGN 0 7040 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_R_N_OVR_EN_BITS 1 7041 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_R_N_OVR_EN_SHIFT 16 7042 7043 /* DDR40_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE1_R_N :: reserved1 [15:09] */ 7044 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_R_N_RESERVED1_MASK 0x0000fe00 7045 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_R_N_RESERVED1_ALIGN 0 7046 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_R_N_RESERVED1_BITS 7 7047 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_R_N_RESERVED1_SHIFT 9 7048 7049 /* DDR40_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE1_R_N :: byte_sel [08:08] */ 7050 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_R_N_BYTE_SEL_MASK 0x00000100 7051 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_R_N_BYTE_SEL_ALIGN 0 7052 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_R_N_BYTE_SEL_BITS 1 7053 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_R_N_BYTE_SEL_SHIFT 8 7054 7055 /* DDR40_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE1_R_N :: reserved2 [07:06] */ 7056 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_R_N_RESERVED2_MASK 0x000000c0 7057 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_R_N_RESERVED2_ALIGN 0 7058 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_R_N_RESERVED2_BITS 2 7059 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_R_N_RESERVED2_SHIFT 6 7060 7061 /* DDR40_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE1_R_N :: ovr_step [05:00] */ 7062 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_R_N_OVR_STEP_MASK 0x0000003f 7063 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_R_N_OVR_STEP_ALIGN 0 7064 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_R_N_OVR_STEP_BITS 6 7065 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_R_N_OVR_STEP_SHIFT 0 7066 7067 7068 /**************************************************************************** 7069 * DDR40_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P 7070 */ 7071 /* DDR40_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: reserved0 [31:25] */ 7072 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_RESERVED0_MASK 0xfe000000 7073 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_RESERVED0_ALIGN 0 7074 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_RESERVED0_BITS 7 7075 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_RESERVED0_SHIFT 25 7076 7077 /* DDR40_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: dm_ovr_en [24:24] */ 7078 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_DM_OVR_EN_MASK 0x01000000 7079 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_DM_OVR_EN_ALIGN 0 7080 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_DM_OVR_EN_BITS 1 7081 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_DM_OVR_EN_SHIFT 24 7082 7083 /* DDR40_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: ovr_en [23:16] */ 7084 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_OVR_EN_MASK 0x00ff0000 7085 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_OVR_EN_ALIGN 0 7086 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_OVR_EN_BITS 8 7087 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_OVR_EN_SHIFT 16 7088 7089 /* DDR40_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: reserved1 [15:09] */ 7090 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_RESERVED1_MASK 0x0000fe00 7091 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_RESERVED1_ALIGN 0 7092 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_RESERVED1_BITS 7 7093 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_RESERVED1_SHIFT 9 7094 7095 /* DDR40_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: byte_sel [08:08] */ 7096 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_BYTE_SEL_MASK 0x00000100 7097 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_BYTE_SEL_ALIGN 0 7098 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_BYTE_SEL_BITS 1 7099 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_BYTE_SEL_SHIFT 8 7100 7101 /* DDR40_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: reserved2 [07:06] */ 7102 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_RESERVED2_MASK 0x000000c0 7103 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_RESERVED2_ALIGN 0 7104 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_RESERVED2_BITS 2 7105 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_RESERVED2_SHIFT 6 7106 7107 /* DDR40_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: ovr_step [05:00] */ 7108 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_OVR_STEP_MASK 0x0000003f 7109 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_OVR_STEP_ALIGN 0 7110 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_OVR_STEP_BITS 6 7111 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_OVR_STEP_SHIFT 0 7112 7113 7114 /**************************************************************************** 7115 * DDR40_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N 7116 */ 7117 /* DDR40_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: reserved0 [31:25] */ 7118 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_RESERVED0_MASK 0xfe000000 7119 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_RESERVED0_ALIGN 0 7120 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_RESERVED0_BITS 7 7121 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_RESERVED0_SHIFT 25 7122 7123 /* DDR40_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: dm_ovr_en [24:24] */ 7124 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_DM_OVR_EN_MASK 0x01000000 7125 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_DM_OVR_EN_ALIGN 0 7126 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_DM_OVR_EN_BITS 1 7127 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_DM_OVR_EN_SHIFT 24 7128 7129 /* DDR40_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: ovr_en [23:16] */ 7130 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_OVR_EN_MASK 0x00ff0000 7131 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_OVR_EN_ALIGN 0 7132 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_OVR_EN_BITS 8 7133 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_OVR_EN_SHIFT 16 7134 7135 /* DDR40_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: reserved1 [15:09] */ 7136 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_RESERVED1_MASK 0x0000fe00 7137 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_RESERVED1_ALIGN 0 7138 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_RESERVED1_BITS 7 7139 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_RESERVED1_SHIFT 9 7140 7141 /* DDR40_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: byte_sel [08:08] */ 7142 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_BYTE_SEL_MASK 0x00000100 7143 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_BYTE_SEL_ALIGN 0 7144 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_BYTE_SEL_BITS 1 7145 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_BYTE_SEL_SHIFT 8 7146 7147 /* DDR40_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: reserved2 [07:06] */ 7148 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_RESERVED2_MASK 0x000000c0 7149 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_RESERVED2_ALIGN 0 7150 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_RESERVED2_BITS 2 7151 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_RESERVED2_SHIFT 6 7152 7153 /* DDR40_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: ovr_step [05:00] */ 7154 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_OVR_STEP_MASK 0x0000003f 7155 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_OVR_STEP_ALIGN 0 7156 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_OVR_STEP_BITS 6 7157 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_OVR_STEP_SHIFT 0 7158 7159 7160 /**************************************************************************** 7161 * DDR40_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE1_W 7162 */ 7163 /* DDR40_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE1_W :: reserved0 [31:17] */ 7164 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_W_RESERVED0_MASK 0xfffe0000 7165 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_W_RESERVED0_ALIGN 0 7166 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_W_RESERVED0_BITS 15 7167 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_W_RESERVED0_SHIFT 17 7168 7169 /* DDR40_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE1_W :: ovr_en [16:16] */ 7170 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_W_OVR_EN_MASK 0x00010000 7171 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_W_OVR_EN_ALIGN 0 7172 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_W_OVR_EN_BITS 1 7173 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_W_OVR_EN_SHIFT 16 7174 7175 /* DDR40_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE1_W :: reserved1 [15:09] */ 7176 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_W_RESERVED1_MASK 0x0000fe00 7177 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_W_RESERVED1_ALIGN 0 7178 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_W_RESERVED1_BITS 7 7179 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_W_RESERVED1_SHIFT 9 7180 7181 /* DDR40_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE1_W :: byte_sel [08:08] */ 7182 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_W_BYTE_SEL_MASK 0x00000100 7183 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_W_BYTE_SEL_ALIGN 0 7184 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_W_BYTE_SEL_BITS 1 7185 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_W_BYTE_SEL_SHIFT 8 7186 7187 /* DDR40_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE1_W :: reserved2 [07:06] */ 7188 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_W_RESERVED2_MASK 0x000000c0 7189 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_W_RESERVED2_ALIGN 0 7190 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_W_RESERVED2_BITS 2 7191 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_W_RESERVED2_SHIFT 6 7192 7193 /* DDR40_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE1_W :: ovr_step [05:00] */ 7194 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_W_OVR_STEP_MASK 0x0000003f 7195 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_W_OVR_STEP_ALIGN 0 7196 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_W_OVR_STEP_BITS 6 7197 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_W_OVR_STEP_SHIFT 0 7198 7199 7200 /**************************************************************************** 7201 * DDR40_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_W 7202 */ 7203 /* DDR40_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: reserved0 [31:25] */ 7204 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_RESERVED0_MASK 0xfe000000 7205 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_RESERVED0_ALIGN 0 7206 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_RESERVED0_BITS 7 7207 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_RESERVED0_SHIFT 25 7208 7209 /* DDR40_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: dm_ovr_en [24:24] */ 7210 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_DM_OVR_EN_MASK 0x01000000 7211 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_DM_OVR_EN_ALIGN 0 7212 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_DM_OVR_EN_BITS 1 7213 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_DM_OVR_EN_SHIFT 24 7214 7215 /* DDR40_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: ovr_en [23:16] */ 7216 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_OVR_EN_MASK 0x00ff0000 7217 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_OVR_EN_ALIGN 0 7218 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_OVR_EN_BITS 8 7219 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_OVR_EN_SHIFT 16 7220 7221 /* DDR40_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: reserved1 [15:09] */ 7222 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_RESERVED1_MASK 0x0000fe00 7223 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_RESERVED1_ALIGN 0 7224 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_RESERVED1_BITS 7 7225 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_RESERVED1_SHIFT 9 7226 7227 /* DDR40_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: byte_sel [08:08] */ 7228 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_BYTE_SEL_MASK 0x00000100 7229 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_BYTE_SEL_ALIGN 0 7230 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_BYTE_SEL_BITS 1 7231 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_BYTE_SEL_SHIFT 8 7232 7233 /* DDR40_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: reserved2 [07:06] */ 7234 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_RESERVED2_MASK 0x000000c0 7235 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_RESERVED2_ALIGN 0 7236 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_RESERVED2_BITS 2 7237 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_RESERVED2_SHIFT 6 7238 7239 /* DDR40_PHY_WORD_LANE_0 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: ovr_step [05:00] */ 7240 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_OVR_STEP_MASK 0x0000003f 7241 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_OVR_STEP_ALIGN 0 7242 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_OVR_STEP_BITS 6 7243 #define DDR40_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_W_OVR_STEP_SHIFT 0 7244 7245 7246 /**************************************************************************** 7247 * DDR40_PHY_WORD_LANE_0 :: READ_DATA_DLY 7248 */ 7249 /* DDR40_PHY_WORD_LANE_0 :: READ_DATA_DLY :: reserved0 [31:03] */ 7250 #define DDR40_PHY_WORD_LANE_0_READ_DATA_DLY_RESERVED0_MASK 0xfffffff8 7251 #define DDR40_PHY_WORD_LANE_0_READ_DATA_DLY_RESERVED0_ALIGN 0 7252 #define DDR40_PHY_WORD_LANE_0_READ_DATA_DLY_RESERVED0_BITS 29 7253 #define DDR40_PHY_WORD_LANE_0_READ_DATA_DLY_RESERVED0_SHIFT 3 7254 7255 /* DDR40_PHY_WORD_LANE_0 :: READ_DATA_DLY :: rd_data_dly [02:00] */ 7256 #define DDR40_PHY_WORD_LANE_0_READ_DATA_DLY_RD_DATA_DLY_MASK 0x00000007 7257 #define DDR40_PHY_WORD_LANE_0_READ_DATA_DLY_RD_DATA_DLY_ALIGN 0 7258 #define DDR40_PHY_WORD_LANE_0_READ_DATA_DLY_RD_DATA_DLY_BITS 3 7259 #define DDR40_PHY_WORD_LANE_0_READ_DATA_DLY_RD_DATA_DLY_SHIFT 0 7260 7261 7262 /**************************************************************************** 7263 * DDR40_PHY_WORD_LANE_0 :: READ_CONTROL 7264 */ 7265 /* DDR40_PHY_WORD_LANE_0 :: READ_CONTROL :: reserved0 [31:03] */ 7266 #define DDR40_PHY_WORD_LANE_0_READ_CONTROL_RESERVED0_MASK 0xfffffff8 7267 #define DDR40_PHY_WORD_LANE_0_READ_CONTROL_RESERVED0_ALIGN 0 7268 #define DDR40_PHY_WORD_LANE_0_READ_CONTROL_RESERVED0_BITS 29 7269 #define DDR40_PHY_WORD_LANE_0_READ_CONTROL_RESERVED0_SHIFT 3 7270 7271 /* DDR40_PHY_WORD_LANE_0 :: READ_CONTROL :: dq_odt_enable [02:02] */ 7272 #define DDR40_PHY_WORD_LANE_0_READ_CONTROL_DQ_ODT_ENABLE_MASK 0x00000004 7273 #define DDR40_PHY_WORD_LANE_0_READ_CONTROL_DQ_ODT_ENABLE_ALIGN 0 7274 #define DDR40_PHY_WORD_LANE_0_READ_CONTROL_DQ_ODT_ENABLE_BITS 1 7275 #define DDR40_PHY_WORD_LANE_0_READ_CONTROL_DQ_ODT_ENABLE_SHIFT 2 7276 7277 /* DDR40_PHY_WORD_LANE_0 :: READ_CONTROL :: dq_odt_te_adj [01:01] */ 7278 #define DDR40_PHY_WORD_LANE_0_READ_CONTROL_DQ_ODT_TE_ADJ_MASK 0x00000002 7279 #define DDR40_PHY_WORD_LANE_0_READ_CONTROL_DQ_ODT_TE_ADJ_ALIGN 0 7280 #define DDR40_PHY_WORD_LANE_0_READ_CONTROL_DQ_ODT_TE_ADJ_BITS 1 7281 #define DDR40_PHY_WORD_LANE_0_READ_CONTROL_DQ_ODT_TE_ADJ_SHIFT 1 7282 7283 /* DDR40_PHY_WORD_LANE_0 :: READ_CONTROL :: dq_odt_le_adj [00:00] */ 7284 #define DDR40_PHY_WORD_LANE_0_READ_CONTROL_DQ_ODT_LE_ADJ_MASK 0x00000001 7285 #define DDR40_PHY_WORD_LANE_0_READ_CONTROL_DQ_ODT_LE_ADJ_ALIGN 0 7286 #define DDR40_PHY_WORD_LANE_0_READ_CONTROL_DQ_ODT_LE_ADJ_BITS 1 7287 #define DDR40_PHY_WORD_LANE_0_READ_CONTROL_DQ_ODT_LE_ADJ_SHIFT 0 7288 7289 7290 /**************************************************************************** 7291 * DDR40_PHY_WORD_LANE_0 :: READ_FIFO_DATA_BL0_0 7292 */ 7293 /* DDR40_PHY_WORD_LANE_0 :: READ_FIFO_DATA_BL0_0 :: reserved0 [31:16] */ 7294 #define DDR40_PHY_WORD_LANE_0_READ_FIFO_DATA_BL0_0_RESERVED0_MASK 0xffff0000 7295 #define DDR40_PHY_WORD_LANE_0_READ_FIFO_DATA_BL0_0_RESERVED0_ALIGN 0 7296 #define DDR40_PHY_WORD_LANE_0_READ_FIFO_DATA_BL0_0_RESERVED0_BITS 16 7297 #define DDR40_PHY_WORD_LANE_0_READ_FIFO_DATA_BL0_0_RESERVED0_SHIFT 16 7298 7299 /* DDR40_PHY_WORD_LANE_0 :: READ_FIFO_DATA_BL0_0 :: data_p [15:08] */ 7300 #define DDR40_PHY_WORD_LANE_0_READ_FIFO_DATA_BL0_0_DATA_P_MASK 0x0000ff00 7301 #define DDR40_PHY_WORD_LANE_0_READ_FIFO_DATA_BL0_0_DATA_P_ALIGN 0 7302 #define DDR40_PHY_WORD_LANE_0_READ_FIFO_DATA_BL0_0_DATA_P_BITS 8 7303 #define DDR40_PHY_WORD_LANE_0_READ_FIFO_DATA_BL0_0_DATA_P_SHIFT 8 7304 7305 /* DDR40_PHY_WORD_LANE_0 :: READ_FIFO_DATA_BL0_0 :: data_n [07:00] */ 7306 #define DDR40_PHY_WORD_LANE_0_READ_FIFO_DATA_BL0_0_DATA_N_MASK 0x000000ff 7307 #define DDR40_PHY_WORD_LANE_0_READ_FIFO_DATA_BL0_0_DATA_N_ALIGN 0 7308 #define DDR40_PHY_WORD_LANE_0_READ_FIFO_DATA_BL0_0_DATA_N_BITS 8 7309 #define DDR40_PHY_WORD_LANE_0_READ_FIFO_DATA_BL0_0_DATA_N_SHIFT 0 7310 7311 7312 /**************************************************************************** 7313 * DDR40_PHY_WORD_LANE_0 :: READ_FIFO_DATA_BL0_1 7314 */ 7315 /* DDR40_PHY_WORD_LANE_0 :: READ_FIFO_DATA_BL0_1 :: reserved0 [31:16] */ 7316 #define DDR40_PHY_WORD_LANE_0_READ_FIFO_DATA_BL0_1_RESERVED0_MASK 0xffff0000 7317 #define DDR40_PHY_WORD_LANE_0_READ_FIFO_DATA_BL0_1_RESERVED0_ALIGN 0 7318 #define DDR40_PHY_WORD_LANE_0_READ_FIFO_DATA_BL0_1_RESERVED0_BITS 16 7319 #define DDR40_PHY_WORD_LANE_0_READ_FIFO_DATA_BL0_1_RESERVED0_SHIFT 16 7320 7321 /* DDR40_PHY_WORD_LANE_0 :: READ_FIFO_DATA_BL0_1 :: data_p [15:08] */ 7322 #define DDR40_PHY_WORD_LANE_0_READ_FIFO_DATA_BL0_1_DATA_P_MASK 0x0000ff00 7323 #define DDR40_PHY_WORD_LANE_0_READ_FIFO_DATA_BL0_1_DATA_P_ALIGN 0 7324 #define DDR40_PHY_WORD_LANE_0_READ_FIFO_DATA_BL0_1_DATA_P_BITS 8 7325 #define DDR40_PHY_WORD_LANE_0_READ_FIFO_DATA_BL0_1_DATA_P_SHIFT 8 7326 7327 /* DDR40_PHY_WORD_LANE_0 :: READ_FIFO_DATA_BL0_1 :: data_n [07:00] */ 7328 #define DDR40_PHY_WORD_LANE_0_READ_FIFO_DATA_BL0_1_DATA_N_MASK 0x000000ff 7329 #define DDR40_PHY_WORD_LANE_0_READ_FIFO_DATA_BL0_1_DATA_N_ALIGN 0 7330 #define DDR40_PHY_WORD_LANE_0_READ_FIFO_DATA_BL0_1_DATA_N_BITS 8 7331 #define DDR40_PHY_WORD_LANE_0_READ_FIFO_DATA_BL0_1_DATA_N_SHIFT 0 7332 7333 7334 /**************************************************************************** 7335 * DDR40_PHY_WORD_LANE_0 :: READ_FIFO_DATA_BL0_2 7336 */ 7337 /* DDR40_PHY_WORD_LANE_0 :: READ_FIFO_DATA_BL0_2 :: reserved0 [31:16] */ 7338 #define DDR40_PHY_WORD_LANE_0_READ_FIFO_DATA_BL0_2_RESERVED0_MASK 0xffff0000 7339 #define DDR40_PHY_WORD_LANE_0_READ_FIFO_DATA_BL0_2_RESERVED0_ALIGN 0 7340 #define DDR40_PHY_WORD_LANE_0_READ_FIFO_DATA_BL0_2_RESERVED0_BITS 16 7341 #define DDR40_PHY_WORD_LANE_0_READ_FIFO_DATA_BL0_2_RESERVED0_SHIFT 16 7342 7343 /* DDR40_PHY_WORD_LANE_0 :: READ_FIFO_DATA_BL0_2 :: data_p [15:08] */ 7344 #define DDR40_PHY_WORD_LANE_0_READ_FIFO_DATA_BL0_2_DATA_P_MASK 0x0000ff00 7345 #define DDR40_PHY_WORD_LANE_0_READ_FIFO_DATA_BL0_2_DATA_P_ALIGN 0 7346 #define DDR40_PHY_WORD_LANE_0_READ_FIFO_DATA_BL0_2_DATA_P_BITS 8 7347 #define DDR40_PHY_WORD_LANE_0_READ_FIFO_DATA_BL0_2_DATA_P_SHIFT 8 7348 7349 /* DDR40_PHY_WORD_LANE_0 :: READ_FIFO_DATA_BL0_2 :: data_n [07:00] */ 7350 #define DDR40_PHY_WORD_LANE_0_READ_FIFO_DATA_BL0_2_DATA_N_MASK 0x000000ff 7351 #define DDR40_PHY_WORD_LANE_0_READ_FIFO_DATA_BL0_2_DATA_N_ALIGN 0 7352 #define DDR40_PHY_WORD_LANE_0_READ_FIFO_DATA_BL0_2_DATA_N_BITS 8 7353 #define DDR40_PHY_WORD_LANE_0_READ_FIFO_DATA_BL0_2_DATA_N_SHIFT 0 7354 7355 7356 /**************************************************************************** 7357 * DDR40_PHY_WORD_LANE_0 :: READ_FIFO_DATA_BL0_3 7358 */ 7359 /* DDR40_PHY_WORD_LANE_0 :: READ_FIFO_DATA_BL0_3 :: reserved0 [31:16] */ 7360 #define DDR40_PHY_WORD_LANE_0_READ_FIFO_DATA_BL0_3_RESERVED0_MASK 0xffff0000 7361 #define DDR40_PHY_WORD_LANE_0_READ_FIFO_DATA_BL0_3_RESERVED0_ALIGN 0 7362 #define DDR40_PHY_WORD_LANE_0_READ_FIFO_DATA_BL0_3_RESERVED0_BITS 16 7363 #define DDR40_PHY_WORD_LANE_0_READ_FIFO_DATA_BL0_3_RESERVED0_SHIFT 16 7364 7365 /* DDR40_PHY_WORD_LANE_0 :: READ_FIFO_DATA_BL0_3 :: data_p [15:08] */ 7366 #define DDR40_PHY_WORD_LANE_0_READ_FIFO_DATA_BL0_3_DATA_P_MASK 0x0000ff00 7367 #define DDR40_PHY_WORD_LANE_0_READ_FIFO_DATA_BL0_3_DATA_P_ALIGN 0 7368 #define DDR40_PHY_WORD_LANE_0_READ_FIFO_DATA_BL0_3_DATA_P_BITS 8 7369 #define DDR40_PHY_WORD_LANE_0_READ_FIFO_DATA_BL0_3_DATA_P_SHIFT 8 7370 7371 /* DDR40_PHY_WORD_LANE_0 :: READ_FIFO_DATA_BL0_3 :: data_n [07:00] */ 7372 #define DDR40_PHY_WORD_LANE_0_READ_FIFO_DATA_BL0_3_DATA_N_MASK 0x000000ff 7373 #define DDR40_PHY_WORD_LANE_0_READ_FIFO_DATA_BL0_3_DATA_N_ALIGN 0 7374 #define DDR40_PHY_WORD_LANE_0_READ_FIFO_DATA_BL0_3_DATA_N_BITS 8 7375 #define DDR40_PHY_WORD_LANE_0_READ_FIFO_DATA_BL0_3_DATA_N_SHIFT 0 7376 7377 7378 /**************************************************************************** 7379 * DDR40_PHY_WORD_LANE_0 :: READ_FIFO_DATA_BL1_0 7380 */ 7381 /* DDR40_PHY_WORD_LANE_0 :: READ_FIFO_DATA_BL1_0 :: reserved0 [31:16] */ 7382 #define DDR40_PHY_WORD_LANE_0_READ_FIFO_DATA_BL1_0_RESERVED0_MASK 0xffff0000 7383 #define DDR40_PHY_WORD_LANE_0_READ_FIFO_DATA_BL1_0_RESERVED0_ALIGN 0 7384 #define DDR40_PHY_WORD_LANE_0_READ_FIFO_DATA_BL1_0_RESERVED0_BITS 16 7385 #define DDR40_PHY_WORD_LANE_0_READ_FIFO_DATA_BL1_0_RESERVED0_SHIFT 16 7386 7387 /* DDR40_PHY_WORD_LANE_0 :: READ_FIFO_DATA_BL1_0 :: data_p [15:08] */ 7388 #define DDR40_PHY_WORD_LANE_0_READ_FIFO_DATA_BL1_0_DATA_P_MASK 0x0000ff00 7389 #define DDR40_PHY_WORD_LANE_0_READ_FIFO_DATA_BL1_0_DATA_P_ALIGN 0 7390 #define DDR40_PHY_WORD_LANE_0_READ_FIFO_DATA_BL1_0_DATA_P_BITS 8 7391 #define DDR40_PHY_WORD_LANE_0_READ_FIFO_DATA_BL1_0_DATA_P_SHIFT 8 7392 7393 /* DDR40_PHY_WORD_LANE_0 :: READ_FIFO_DATA_BL1_0 :: data_n [07:00] */ 7394 #define DDR40_PHY_WORD_LANE_0_READ_FIFO_DATA_BL1_0_DATA_N_MASK 0x000000ff 7395 #define DDR40_PHY_WORD_LANE_0_READ_FIFO_DATA_BL1_0_DATA_N_ALIGN 0 7396 #define DDR40_PHY_WORD_LANE_0_READ_FIFO_DATA_BL1_0_DATA_N_BITS 8 7397 #define DDR40_PHY_WORD_LANE_0_READ_FIFO_DATA_BL1_0_DATA_N_SHIFT 0 7398 7399 7400 /**************************************************************************** 7401 * DDR40_PHY_WORD_LANE_0 :: READ_FIFO_DATA_BL1_1 7402 */ 7403 /* DDR40_PHY_WORD_LANE_0 :: READ_FIFO_DATA_BL1_1 :: reserved0 [31:16] */ 7404 #define DDR40_PHY_WORD_LANE_0_READ_FIFO_DATA_BL1_1_RESERVED0_MASK 0xffff0000 7405 #define DDR40_PHY_WORD_LANE_0_READ_FIFO_DATA_BL1_1_RESERVED0_ALIGN 0 7406 #define DDR40_PHY_WORD_LANE_0_READ_FIFO_DATA_BL1_1_RESERVED0_BITS 16 7407 #define DDR40_PHY_WORD_LANE_0_READ_FIFO_DATA_BL1_1_RESERVED0_SHIFT 16 7408 7409 /* DDR40_PHY_WORD_LANE_0 :: READ_FIFO_DATA_BL1_1 :: data_p [15:08] */ 7410 #define DDR40_PHY_WORD_LANE_0_READ_FIFO_DATA_BL1_1_DATA_P_MASK 0x0000ff00 7411 #define DDR40_PHY_WORD_LANE_0_READ_FIFO_DATA_BL1_1_DATA_P_ALIGN 0 7412 #define DDR40_PHY_WORD_LANE_0_READ_FIFO_DATA_BL1_1_DATA_P_BITS 8 7413 #define DDR40_PHY_WORD_LANE_0_READ_FIFO_DATA_BL1_1_DATA_P_SHIFT 8 7414 7415 /* DDR40_PHY_WORD_LANE_0 :: READ_FIFO_DATA_BL1_1 :: data_n [07:00] */ 7416 #define DDR40_PHY_WORD_LANE_0_READ_FIFO_DATA_BL1_1_DATA_N_MASK 0x000000ff 7417 #define DDR40_PHY_WORD_LANE_0_READ_FIFO_DATA_BL1_1_DATA_N_ALIGN 0 7418 #define DDR40_PHY_WORD_LANE_0_READ_FIFO_DATA_BL1_1_DATA_N_BITS 8 7419 #define DDR40_PHY_WORD_LANE_0_READ_FIFO_DATA_BL1_1_DATA_N_SHIFT 0 7420 7421 7422 /**************************************************************************** 7423 * DDR40_PHY_WORD_LANE_0 :: READ_FIFO_DATA_BL1_2 7424 */ 7425 /* DDR40_PHY_WORD_LANE_0 :: READ_FIFO_DATA_BL1_2 :: reserved0 [31:16] */ 7426 #define DDR40_PHY_WORD_LANE_0_READ_FIFO_DATA_BL1_2_RESERVED0_MASK 0xffff0000 7427 #define DDR40_PHY_WORD_LANE_0_READ_FIFO_DATA_BL1_2_RESERVED0_ALIGN 0 7428 #define DDR40_PHY_WORD_LANE_0_READ_FIFO_DATA_BL1_2_RESERVED0_BITS 16 7429 #define DDR40_PHY_WORD_LANE_0_READ_FIFO_DATA_BL1_2_RESERVED0_SHIFT 16 7430 7431 /* DDR40_PHY_WORD_LANE_0 :: READ_FIFO_DATA_BL1_2 :: data_p [15:08] */ 7432 #define DDR40_PHY_WORD_LANE_0_READ_FIFO_DATA_BL1_2_DATA_P_MASK 0x0000ff00 7433 #define DDR40_PHY_WORD_LANE_0_READ_FIFO_DATA_BL1_2_DATA_P_ALIGN 0 7434 #define DDR40_PHY_WORD_LANE_0_READ_FIFO_DATA_BL1_2_DATA_P_BITS 8 7435 #define DDR40_PHY_WORD_LANE_0_READ_FIFO_DATA_BL1_2_DATA_P_SHIFT 8 7436 7437 /* DDR40_PHY_WORD_LANE_0 :: READ_FIFO_DATA_BL1_2 :: data_n [07:00] */ 7438 #define DDR40_PHY_WORD_LANE_0_READ_FIFO_DATA_BL1_2_DATA_N_MASK 0x000000ff 7439 #define DDR40_PHY_WORD_LANE_0_READ_FIFO_DATA_BL1_2_DATA_N_ALIGN 0 7440 #define DDR40_PHY_WORD_LANE_0_READ_FIFO_DATA_BL1_2_DATA_N_BITS 8 7441 #define DDR40_PHY_WORD_LANE_0_READ_FIFO_DATA_BL1_2_DATA_N_SHIFT 0 7442 7443 7444 /**************************************************************************** 7445 * DDR40_PHY_WORD_LANE_0 :: READ_FIFO_DATA_BL1_3 7446 */ 7447 /* DDR40_PHY_WORD_LANE_0 :: READ_FIFO_DATA_BL1_3 :: reserved0 [31:16] */ 7448 #define DDR40_PHY_WORD_LANE_0_READ_FIFO_DATA_BL1_3_RESERVED0_MASK 0xffff0000 7449 #define DDR40_PHY_WORD_LANE_0_READ_FIFO_DATA_BL1_3_RESERVED0_ALIGN 0 7450 #define DDR40_PHY_WORD_LANE_0_READ_FIFO_DATA_BL1_3_RESERVED0_BITS 16 7451 #define DDR40_PHY_WORD_LANE_0_READ_FIFO_DATA_BL1_3_RESERVED0_SHIFT 16 7452 7453 /* DDR40_PHY_WORD_LANE_0 :: READ_FIFO_DATA_BL1_3 :: data_p [15:08] */ 7454 #define DDR40_PHY_WORD_LANE_0_READ_FIFO_DATA_BL1_3_DATA_P_MASK 0x0000ff00 7455 #define DDR40_PHY_WORD_LANE_0_READ_FIFO_DATA_BL1_3_DATA_P_ALIGN 0 7456 #define DDR40_PHY_WORD_LANE_0_READ_FIFO_DATA_BL1_3_DATA_P_BITS 8 7457 #define DDR40_PHY_WORD_LANE_0_READ_FIFO_DATA_BL1_3_DATA_P_SHIFT 8 7458 7459 /* DDR40_PHY_WORD_LANE_0 :: READ_FIFO_DATA_BL1_3 :: data_n [07:00] */ 7460 #define DDR40_PHY_WORD_LANE_0_READ_FIFO_DATA_BL1_3_DATA_N_MASK 0x000000ff 7461 #define DDR40_PHY_WORD_LANE_0_READ_FIFO_DATA_BL1_3_DATA_N_ALIGN 0 7462 #define DDR40_PHY_WORD_LANE_0_READ_FIFO_DATA_BL1_3_DATA_N_BITS 8 7463 #define DDR40_PHY_WORD_LANE_0_READ_FIFO_DATA_BL1_3_DATA_N_SHIFT 0 7464 7465 7466 /**************************************************************************** 7467 * DDR40_PHY_WORD_LANE_0 :: READ_FIFO_STATUS 7468 */ 7469 /* DDR40_PHY_WORD_LANE_0 :: READ_FIFO_STATUS :: reserved0 [31:08] */ 7470 #define DDR40_PHY_WORD_LANE_0_READ_FIFO_STATUS_RESERVED0_MASK 0xffffff00 7471 #define DDR40_PHY_WORD_LANE_0_READ_FIFO_STATUS_RESERVED0_ALIGN 0 7472 #define DDR40_PHY_WORD_LANE_0_READ_FIFO_STATUS_RESERVED0_BITS 24 7473 #define DDR40_PHY_WORD_LANE_0_READ_FIFO_STATUS_RESERVED0_SHIFT 8 7474 7475 /* DDR40_PHY_WORD_LANE_0 :: READ_FIFO_STATUS :: status1 [07:04] */ 7476 #define DDR40_PHY_WORD_LANE_0_READ_FIFO_STATUS_STATUS1_MASK 0x000000f0 7477 #define DDR40_PHY_WORD_LANE_0_READ_FIFO_STATUS_STATUS1_ALIGN 0 7478 #define DDR40_PHY_WORD_LANE_0_READ_FIFO_STATUS_STATUS1_BITS 4 7479 #define DDR40_PHY_WORD_LANE_0_READ_FIFO_STATUS_STATUS1_SHIFT 4 7480 7481 /* DDR40_PHY_WORD_LANE_0 :: READ_FIFO_STATUS :: status0 [03:00] */ 7482 #define DDR40_PHY_WORD_LANE_0_READ_FIFO_STATUS_STATUS0_MASK 0x0000000f 7483 #define DDR40_PHY_WORD_LANE_0_READ_FIFO_STATUS_STATUS0_ALIGN 0 7484 #define DDR40_PHY_WORD_LANE_0_READ_FIFO_STATUS_STATUS0_BITS 4 7485 #define DDR40_PHY_WORD_LANE_0_READ_FIFO_STATUS_STATUS0_SHIFT 0 7486 7487 7488 /**************************************************************************** 7489 * DDR40_PHY_WORD_LANE_0 :: READ_FIFO_CLEAR 7490 */ 7491 /* DDR40_PHY_WORD_LANE_0 :: READ_FIFO_CLEAR :: reserved0 [31:01] */ 7492 #define DDR40_PHY_WORD_LANE_0_READ_FIFO_CLEAR_RESERVED0_MASK 0xfffffffe 7493 #define DDR40_PHY_WORD_LANE_0_READ_FIFO_CLEAR_RESERVED0_ALIGN 0 7494 #define DDR40_PHY_WORD_LANE_0_READ_FIFO_CLEAR_RESERVED0_BITS 31 7495 #define DDR40_PHY_WORD_LANE_0_READ_FIFO_CLEAR_RESERVED0_SHIFT 1 7496 7497 /* DDR40_PHY_WORD_LANE_0 :: READ_FIFO_CLEAR :: clear [00:00] */ 7498 #define DDR40_PHY_WORD_LANE_0_READ_FIFO_CLEAR_CLEAR_MASK 0x00000001 7499 #define DDR40_PHY_WORD_LANE_0_READ_FIFO_CLEAR_CLEAR_ALIGN 0 7500 #define DDR40_PHY_WORD_LANE_0_READ_FIFO_CLEAR_CLEAR_BITS 1 7501 #define DDR40_PHY_WORD_LANE_0_READ_FIFO_CLEAR_CLEAR_SHIFT 0 7502 7503 7504 /**************************************************************************** 7505 * DDR40_PHY_WORD_LANE_0 :: IDLE_PAD_CONTROL 7506 */ 7507 /* DDR40_PHY_WORD_LANE_0 :: IDLE_PAD_CONTROL :: idle [31:31] */ 7508 #define DDR40_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_IDLE_MASK 0x80000000 7509 #define DDR40_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_IDLE_ALIGN 0 7510 #define DDR40_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_IDLE_BITS 1 7511 #define DDR40_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_IDLE_SHIFT 31 7512 7513 /* DDR40_PHY_WORD_LANE_0 :: IDLE_PAD_CONTROL :: reserved0 [30:24] */ 7514 #define DDR40_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_RESERVED0_MASK 0x7f000000 7515 #define DDR40_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_RESERVED0_ALIGN 0 7516 #define DDR40_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_RESERVED0_BITS 7 7517 #define DDR40_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_RESERVED0_SHIFT 24 7518 7519 /* DDR40_PHY_WORD_LANE_0 :: IDLE_PAD_CONTROL :: auto_dq_rxenb_mode [23:22] */ 7520 #define DDR40_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_AUTO_DQ_RXENB_MODE_MASK 0x00c00000 7521 #define DDR40_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_AUTO_DQ_RXENB_MODE_ALIGN 0 7522 #define DDR40_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_AUTO_DQ_RXENB_MODE_BITS 2 7523 #define DDR40_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_AUTO_DQ_RXENB_MODE_SHIFT 22 7524 7525 /* DDR40_PHY_WORD_LANE_0 :: IDLE_PAD_CONTROL :: auto_dq_iddq_mode [21:20] */ 7526 #define DDR40_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_AUTO_DQ_IDDQ_MODE_MASK 0x00300000 7527 #define DDR40_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_AUTO_DQ_IDDQ_MODE_ALIGN 0 7528 #define DDR40_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_AUTO_DQ_IDDQ_MODE_BITS 2 7529 #define DDR40_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_AUTO_DQ_IDDQ_MODE_SHIFT 20 7530 7531 /* DDR40_PHY_WORD_LANE_0 :: IDLE_PAD_CONTROL :: dq_rxenb [19:19] */ 7532 #define DDR40_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_DQ_RXENB_MASK 0x00080000 7533 #define DDR40_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_DQ_RXENB_ALIGN 0 7534 #define DDR40_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_DQ_RXENB_BITS 1 7535 #define DDR40_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_DQ_RXENB_SHIFT 19 7536 7537 /* DDR40_PHY_WORD_LANE_0 :: IDLE_PAD_CONTROL :: dq_iddq [18:18] */ 7538 #define DDR40_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_DQ_IDDQ_MASK 0x00040000 7539 #define DDR40_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_DQ_IDDQ_ALIGN 0 7540 #define DDR40_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_DQ_IDDQ_BITS 1 7541 #define DDR40_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_DQ_IDDQ_SHIFT 18 7542 7543 /* DDR40_PHY_WORD_LANE_0 :: IDLE_PAD_CONTROL :: dq_reb [17:17] */ 7544 #define DDR40_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_DQ_REB_MASK 0x00020000 7545 #define DDR40_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_DQ_REB_ALIGN 0 7546 #define DDR40_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_DQ_REB_BITS 1 7547 #define DDR40_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_DQ_REB_SHIFT 17 7548 7549 /* DDR40_PHY_WORD_LANE_0 :: IDLE_PAD_CONTROL :: dq_oeb [16:16] */ 7550 #define DDR40_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_DQ_OEB_MASK 0x00010000 7551 #define DDR40_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_DQ_OEB_ALIGN 0 7552 #define DDR40_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_DQ_OEB_BITS 1 7553 #define DDR40_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_DQ_OEB_SHIFT 16 7554 7555 /* DDR40_PHY_WORD_LANE_0 :: IDLE_PAD_CONTROL :: read_enb_rxenb [15:15] */ 7556 #define DDR40_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_READ_ENB_RXENB_MASK 0x00008000 7557 #define DDR40_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_READ_ENB_RXENB_ALIGN 0 7558 #define DDR40_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_READ_ENB_RXENB_BITS 1 7559 #define DDR40_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_READ_ENB_RXENB_SHIFT 15 7560 7561 /* DDR40_PHY_WORD_LANE_0 :: IDLE_PAD_CONTROL :: read_enb_iddq [14:14] */ 7562 #define DDR40_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_READ_ENB_IDDQ_MASK 0x00004000 7563 #define DDR40_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_READ_ENB_IDDQ_ALIGN 0 7564 #define DDR40_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_READ_ENB_IDDQ_BITS 1 7565 #define DDR40_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_READ_ENB_IDDQ_SHIFT 14 7566 7567 /* DDR40_PHY_WORD_LANE_0 :: IDLE_PAD_CONTROL :: read_enb_reb [13:13] */ 7568 #define DDR40_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_READ_ENB_REB_MASK 0x00002000 7569 #define DDR40_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_READ_ENB_REB_ALIGN 0 7570 #define DDR40_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_READ_ENB_REB_BITS 1 7571 #define DDR40_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_READ_ENB_REB_SHIFT 13 7572 7573 /* DDR40_PHY_WORD_LANE_0 :: IDLE_PAD_CONTROL :: read_enb_oeb [12:12] */ 7574 #define DDR40_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_READ_ENB_OEB_MASK 0x00001000 7575 #define DDR40_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_READ_ENB_OEB_ALIGN 0 7576 #define DDR40_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_READ_ENB_OEB_BITS 1 7577 #define DDR40_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_READ_ENB_OEB_SHIFT 12 7578 7579 /* DDR40_PHY_WORD_LANE_0 :: IDLE_PAD_CONTROL :: dqs_rxenb [11:11] */ 7580 #define DDR40_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_DQS_RXENB_MASK 0x00000800 7581 #define DDR40_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_DQS_RXENB_ALIGN 0 7582 #define DDR40_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_DQS_RXENB_BITS 1 7583 #define DDR40_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_DQS_RXENB_SHIFT 11 7584 7585 /* DDR40_PHY_WORD_LANE_0 :: IDLE_PAD_CONTROL :: dqs_iddq [10:10] */ 7586 #define DDR40_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_DQS_IDDQ_MASK 0x00000400 7587 #define DDR40_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_DQS_IDDQ_ALIGN 0 7588 #define DDR40_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_DQS_IDDQ_BITS 1 7589 #define DDR40_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_DQS_IDDQ_SHIFT 10 7590 7591 /* DDR40_PHY_WORD_LANE_0 :: IDLE_PAD_CONTROL :: dqs_reb [09:09] */ 7592 #define DDR40_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_DQS_REB_MASK 0x00000200 7593 #define DDR40_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_DQS_REB_ALIGN 0 7594 #define DDR40_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_DQS_REB_BITS 1 7595 #define DDR40_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_DQS_REB_SHIFT 9 7596 7597 /* DDR40_PHY_WORD_LANE_0 :: IDLE_PAD_CONTROL :: dqs_oeb [08:08] */ 7598 #define DDR40_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_DQS_OEB_MASK 0x00000100 7599 #define DDR40_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_DQS_OEB_ALIGN 0 7600 #define DDR40_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_DQS_OEB_BITS 1 7601 #define DDR40_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_DQS_OEB_SHIFT 8 7602 7603 /* DDR40_PHY_WORD_LANE_0 :: IDLE_PAD_CONTROL :: clk1_rxenb [07:07] */ 7604 #define DDR40_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_CLK1_RXENB_MASK 0x00000080 7605 #define DDR40_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_CLK1_RXENB_ALIGN 0 7606 #define DDR40_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_CLK1_RXENB_BITS 1 7607 #define DDR40_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_CLK1_RXENB_SHIFT 7 7608 7609 /* DDR40_PHY_WORD_LANE_0 :: IDLE_PAD_CONTROL :: clk1_iddq [06:06] */ 7610 #define DDR40_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_CLK1_IDDQ_MASK 0x00000040 7611 #define DDR40_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_CLK1_IDDQ_ALIGN 0 7612 #define DDR40_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_CLK1_IDDQ_BITS 1 7613 #define DDR40_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_CLK1_IDDQ_SHIFT 6 7614 7615 /* DDR40_PHY_WORD_LANE_0 :: IDLE_PAD_CONTROL :: clk1_reb [05:05] */ 7616 #define DDR40_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_CLK1_REB_MASK 0x00000020 7617 #define DDR40_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_CLK1_REB_ALIGN 0 7618 #define DDR40_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_CLK1_REB_BITS 1 7619 #define DDR40_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_CLK1_REB_SHIFT 5 7620 7621 /* DDR40_PHY_WORD_LANE_0 :: IDLE_PAD_CONTROL :: clk1_oeb [04:04] */ 7622 #define DDR40_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_CLK1_OEB_MASK 0x00000010 7623 #define DDR40_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_CLK1_OEB_ALIGN 0 7624 #define DDR40_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_CLK1_OEB_BITS 1 7625 #define DDR40_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_CLK1_OEB_SHIFT 4 7626 7627 /* DDR40_PHY_WORD_LANE_0 :: IDLE_PAD_CONTROL :: clk0_rxenb [03:03] */ 7628 #define DDR40_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_CLK0_RXENB_MASK 0x00000008 7629 #define DDR40_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_CLK0_RXENB_ALIGN 0 7630 #define DDR40_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_CLK0_RXENB_BITS 1 7631 #define DDR40_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_CLK0_RXENB_SHIFT 3 7632 7633 /* DDR40_PHY_WORD_LANE_0 :: IDLE_PAD_CONTROL :: clk0_iddq [02:02] */ 7634 #define DDR40_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_CLK0_IDDQ_MASK 0x00000004 7635 #define DDR40_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_CLK0_IDDQ_ALIGN 0 7636 #define DDR40_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_CLK0_IDDQ_BITS 1 7637 #define DDR40_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_CLK0_IDDQ_SHIFT 2 7638 7639 /* DDR40_PHY_WORD_LANE_0 :: IDLE_PAD_CONTROL :: clk0_reb [01:01] */ 7640 #define DDR40_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_CLK0_REB_MASK 0x00000002 7641 #define DDR40_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_CLK0_REB_ALIGN 0 7642 #define DDR40_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_CLK0_REB_BITS 1 7643 #define DDR40_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_CLK0_REB_SHIFT 1 7644 7645 /* DDR40_PHY_WORD_LANE_0 :: IDLE_PAD_CONTROL :: clk0_oeb [00:00] */ 7646 #define DDR40_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_CLK0_OEB_MASK 0x00000001 7647 #define DDR40_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_CLK0_OEB_ALIGN 0 7648 #define DDR40_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_CLK0_OEB_BITS 1 7649 #define DDR40_PHY_WORD_LANE_0_IDLE_PAD_CONTROL_CLK0_OEB_SHIFT 0 7650 7651 7652 /**************************************************************************** 7653 * DDR40_PHY_WORD_LANE_0 :: DRIVE_PAD_CTL 7654 */ 7655 /* DDR40_PHY_WORD_LANE_0 :: DRIVE_PAD_CTL :: reserved0 [31:12] */ 7656 #define DDR40_PHY_WORD_LANE_0_DRIVE_PAD_CTL_RESERVED0_MASK 0xfffff000 7657 #define DDR40_PHY_WORD_LANE_0_DRIVE_PAD_CTL_RESERVED0_ALIGN 0 7658 #define DDR40_PHY_WORD_LANE_0_DRIVE_PAD_CTL_RESERVED0_BITS 20 7659 #define DDR40_PHY_WORD_LANE_0_DRIVE_PAD_CTL_RESERVED0_SHIFT 12 7660 7661 /* DDR40_PHY_WORD_LANE_0 :: DRIVE_PAD_CTL :: no_dqs_rd [11:11] */ 7662 #define DDR40_PHY_WORD_LANE_0_DRIVE_PAD_CTL_NO_DQS_RD_MASK 0x00000800 7663 #define DDR40_PHY_WORD_LANE_0_DRIVE_PAD_CTL_NO_DQS_RD_ALIGN 0 7664 #define DDR40_PHY_WORD_LANE_0_DRIVE_PAD_CTL_NO_DQS_RD_BITS 1 7665 #define DDR40_PHY_WORD_LANE_0_DRIVE_PAD_CTL_NO_DQS_RD_SHIFT 11 7666 7667 /* DDR40_PHY_WORD_LANE_0 :: DRIVE_PAD_CTL :: dqs_always_on [10:10] */ 7668 #define DDR40_PHY_WORD_LANE_0_DRIVE_PAD_CTL_DQS_ALWAYS_ON_MASK 0x00000400 7669 #define DDR40_PHY_WORD_LANE_0_DRIVE_PAD_CTL_DQS_ALWAYS_ON_ALIGN 0 7670 #define DDR40_PHY_WORD_LANE_0_DRIVE_PAD_CTL_DQS_ALWAYS_ON_BITS 1 7671 #define DDR40_PHY_WORD_LANE_0_DRIVE_PAD_CTL_DQS_ALWAYS_ON_SHIFT 10 7672 7673 /* DDR40_PHY_WORD_LANE_0 :: DRIVE_PAD_CTL :: dqs_tx_dis [09:09] */ 7674 #define DDR40_PHY_WORD_LANE_0_DRIVE_PAD_CTL_DQS_TX_DIS_MASK 0x00000200 7675 #define DDR40_PHY_WORD_LANE_0_DRIVE_PAD_CTL_DQS_TX_DIS_ALIGN 0 7676 #define DDR40_PHY_WORD_LANE_0_DRIVE_PAD_CTL_DQS_TX_DIS_BITS 1 7677 #define DDR40_PHY_WORD_LANE_0_DRIVE_PAD_CTL_DQS_TX_DIS_SHIFT 9 7678 7679 /* DDR40_PHY_WORD_LANE_0 :: DRIVE_PAD_CTL :: half_strength_ck [08:08] */ 7680 #define DDR40_PHY_WORD_LANE_0_DRIVE_PAD_CTL_HALF_STRENGTH_CK_MASK 0x00000100 7681 #define DDR40_PHY_WORD_LANE_0_DRIVE_PAD_CTL_HALF_STRENGTH_CK_ALIGN 0 7682 #define DDR40_PHY_WORD_LANE_0_DRIVE_PAD_CTL_HALF_STRENGTH_CK_BITS 1 7683 #define DDR40_PHY_WORD_LANE_0_DRIVE_PAD_CTL_HALF_STRENGTH_CK_SHIFT 8 7684 7685 /* DDR40_PHY_WORD_LANE_0 :: DRIVE_PAD_CTL :: half_strength [07:07] */ 7686 #define DDR40_PHY_WORD_LANE_0_DRIVE_PAD_CTL_HALF_STRENGTH_MASK 0x00000080 7687 #define DDR40_PHY_WORD_LANE_0_DRIVE_PAD_CTL_HALF_STRENGTH_ALIGN 0 7688 #define DDR40_PHY_WORD_LANE_0_DRIVE_PAD_CTL_HALF_STRENGTH_BITS 1 7689 #define DDR40_PHY_WORD_LANE_0_DRIVE_PAD_CTL_HALF_STRENGTH_SHIFT 7 7690 7691 /* DDR40_PHY_WORD_LANE_0 :: DRIVE_PAD_CTL :: rdqs_en [06:06] */ 7692 #define DDR40_PHY_WORD_LANE_0_DRIVE_PAD_CTL_RDQS_EN_MASK 0x00000040 7693 #define DDR40_PHY_WORD_LANE_0_DRIVE_PAD_CTL_RDQS_EN_ALIGN 0 7694 #define DDR40_PHY_WORD_LANE_0_DRIVE_PAD_CTL_RDQS_EN_BITS 1 7695 #define DDR40_PHY_WORD_LANE_0_DRIVE_PAD_CTL_RDQS_EN_SHIFT 6 7696 7697 /* DDR40_PHY_WORD_LANE_0 :: DRIVE_PAD_CTL :: gddr_symmetry [05:05] */ 7698 #define DDR40_PHY_WORD_LANE_0_DRIVE_PAD_CTL_GDDR_SYMMETRY_MASK 0x00000020 7699 #define DDR40_PHY_WORD_LANE_0_DRIVE_PAD_CTL_GDDR_SYMMETRY_ALIGN 0 7700 #define DDR40_PHY_WORD_LANE_0_DRIVE_PAD_CTL_GDDR_SYMMETRY_BITS 1 7701 #define DDR40_PHY_WORD_LANE_0_DRIVE_PAD_CTL_GDDR_SYMMETRY_SHIFT 5 7702 7703 /* DDR40_PHY_WORD_LANE_0 :: DRIVE_PAD_CTL :: vddo_volts [04:03] */ 7704 #define DDR40_PHY_WORD_LANE_0_DRIVE_PAD_CTL_VDDO_VOLTS_MASK 0x00000018 7705 #define DDR40_PHY_WORD_LANE_0_DRIVE_PAD_CTL_VDDO_VOLTS_ALIGN 0 7706 #define DDR40_PHY_WORD_LANE_0_DRIVE_PAD_CTL_VDDO_VOLTS_BITS 2 7707 #define DDR40_PHY_WORD_LANE_0_DRIVE_PAD_CTL_VDDO_VOLTS_SHIFT 3 7708 7709 /* DDR40_PHY_WORD_LANE_0 :: DRIVE_PAD_CTL :: rt60b [02:02] */ 7710 #define DDR40_PHY_WORD_LANE_0_DRIVE_PAD_CTL_RT60B_MASK 0x00000004 7711 #define DDR40_PHY_WORD_LANE_0_DRIVE_PAD_CTL_RT60B_ALIGN 0 7712 #define DDR40_PHY_WORD_LANE_0_DRIVE_PAD_CTL_RT60B_BITS 1 7713 #define DDR40_PHY_WORD_LANE_0_DRIVE_PAD_CTL_RT60B_SHIFT 2 7714 7715 /* DDR40_PHY_WORD_LANE_0 :: DRIVE_PAD_CTL :: rt120b_g [01:01] */ 7716 #define DDR40_PHY_WORD_LANE_0_DRIVE_PAD_CTL_RT120B_G_MASK 0x00000002 7717 #define DDR40_PHY_WORD_LANE_0_DRIVE_PAD_CTL_RT120B_G_ALIGN 0 7718 #define DDR40_PHY_WORD_LANE_0_DRIVE_PAD_CTL_RT120B_G_BITS 1 7719 #define DDR40_PHY_WORD_LANE_0_DRIVE_PAD_CTL_RT120B_G_SHIFT 1 7720 7721 /* DDR40_PHY_WORD_LANE_0 :: DRIVE_PAD_CTL :: g_ddr [00:00] */ 7722 #define DDR40_PHY_WORD_LANE_0_DRIVE_PAD_CTL_G_DDR_MASK 0x00000001 7723 #define DDR40_PHY_WORD_LANE_0_DRIVE_PAD_CTL_G_DDR_ALIGN 0 7724 #define DDR40_PHY_WORD_LANE_0_DRIVE_PAD_CTL_G_DDR_BITS 1 7725 #define DDR40_PHY_WORD_LANE_0_DRIVE_PAD_CTL_G_DDR_SHIFT 0 7726 7727 7728 /**************************************************************************** 7729 * DDR40_PHY_WORD_LANE_0 :: CLOCK_PAD_DISABLE 7730 */ 7731 /* DDR40_PHY_WORD_LANE_0 :: CLOCK_PAD_DISABLE :: reserved0 [31:03] */ 7732 #define DDR40_PHY_WORD_LANE_0_CLOCK_PAD_DISABLE_RESERVED0_MASK 0xfffffff8 7733 #define DDR40_PHY_WORD_LANE_0_CLOCK_PAD_DISABLE_RESERVED0_ALIGN 0 7734 #define DDR40_PHY_WORD_LANE_0_CLOCK_PAD_DISABLE_RESERVED0_BITS 29 7735 #define DDR40_PHY_WORD_LANE_0_CLOCK_PAD_DISABLE_RESERVED0_SHIFT 3 7736 7737 /* DDR40_PHY_WORD_LANE_0 :: CLOCK_PAD_DISABLE :: dm_pad_dis [02:02] */ 7738 #define DDR40_PHY_WORD_LANE_0_CLOCK_PAD_DISABLE_DM_PAD_DIS_MASK 0x00000004 7739 #define DDR40_PHY_WORD_LANE_0_CLOCK_PAD_DISABLE_DM_PAD_DIS_ALIGN 0 7740 #define DDR40_PHY_WORD_LANE_0_CLOCK_PAD_DISABLE_DM_PAD_DIS_BITS 1 7741 #define DDR40_PHY_WORD_LANE_0_CLOCK_PAD_DISABLE_DM_PAD_DIS_SHIFT 2 7742 7743 /* DDR40_PHY_WORD_LANE_0 :: CLOCK_PAD_DISABLE :: clk1_pad_dis [01:01] */ 7744 #define DDR40_PHY_WORD_LANE_0_CLOCK_PAD_DISABLE_CLK1_PAD_DIS_MASK 0x00000002 7745 #define DDR40_PHY_WORD_LANE_0_CLOCK_PAD_DISABLE_CLK1_PAD_DIS_ALIGN 0 7746 #define DDR40_PHY_WORD_LANE_0_CLOCK_PAD_DISABLE_CLK1_PAD_DIS_BITS 1 7747 #define DDR40_PHY_WORD_LANE_0_CLOCK_PAD_DISABLE_CLK1_PAD_DIS_SHIFT 1 7748 7749 /* DDR40_PHY_WORD_LANE_0 :: CLOCK_PAD_DISABLE :: clk0_pad_dis [00:00] */ 7750 #define DDR40_PHY_WORD_LANE_0_CLOCK_PAD_DISABLE_CLK0_PAD_DIS_MASK 0x00000001 7751 #define DDR40_PHY_WORD_LANE_0_CLOCK_PAD_DISABLE_CLK0_PAD_DIS_ALIGN 0 7752 #define DDR40_PHY_WORD_LANE_0_CLOCK_PAD_DISABLE_CLK0_PAD_DIS_BITS 1 7753 #define DDR40_PHY_WORD_LANE_0_CLOCK_PAD_DISABLE_CLK0_PAD_DIS_SHIFT 0 7754 7755 7756 /**************************************************************************** 7757 * DDR40_PHY_WORD_LANE_0 :: WR_PREAMBLE_MODE 7758 */ 7759 /* DDR40_PHY_WORD_LANE_0 :: WR_PREAMBLE_MODE :: reserved0 [31:02] */ 7760 #define DDR40_PHY_WORD_LANE_0_WR_PREAMBLE_MODE_RESERVED0_MASK 0xfffffffc 7761 #define DDR40_PHY_WORD_LANE_0_WR_PREAMBLE_MODE_RESERVED0_ALIGN 0 7762 #define DDR40_PHY_WORD_LANE_0_WR_PREAMBLE_MODE_RESERVED0_BITS 30 7763 #define DDR40_PHY_WORD_LANE_0_WR_PREAMBLE_MODE_RESERVED0_SHIFT 2 7764 7765 /* DDR40_PHY_WORD_LANE_0 :: WR_PREAMBLE_MODE :: long [01:01] */ 7766 #define DDR40_PHY_WORD_LANE_0_WR_PREAMBLE_MODE_LONG_MASK 0x00000002 7767 #define DDR40_PHY_WORD_LANE_0_WR_PREAMBLE_MODE_LONG_ALIGN 0 7768 #define DDR40_PHY_WORD_LANE_0_WR_PREAMBLE_MODE_LONG_BITS 1 7769 #define DDR40_PHY_WORD_LANE_0_WR_PREAMBLE_MODE_LONG_SHIFT 1 7770 7771 /* DDR40_PHY_WORD_LANE_0 :: WR_PREAMBLE_MODE :: mode [00:00] */ 7772 #define DDR40_PHY_WORD_LANE_0_WR_PREAMBLE_MODE_MODE_MASK 0x00000001 7773 #define DDR40_PHY_WORD_LANE_0_WR_PREAMBLE_MODE_MODE_ALIGN 0 7774 #define DDR40_PHY_WORD_LANE_0_WR_PREAMBLE_MODE_MODE_BITS 1 7775 #define DDR40_PHY_WORD_LANE_0_WR_PREAMBLE_MODE_MODE_SHIFT 0 7776 7777 7778 /**************************************************************************** 7779 * DDR40_PHY_WORD_LANE_0 :: PHYBIST_VDL_ADJ 7780 */ 7781 /* DDR40_PHY_WORD_LANE_0 :: PHYBIST_VDL_ADJ :: reserved0 [31:29] */ 7782 #define DDR40_PHY_WORD_LANE_0_PHYBIST_VDL_ADJ_RESERVED0_MASK 0xe0000000 7783 #define DDR40_PHY_WORD_LANE_0_PHYBIST_VDL_ADJ_RESERVED0_ALIGN 0 7784 #define DDR40_PHY_WORD_LANE_0_PHYBIST_VDL_ADJ_RESERVED0_BITS 3 7785 #define DDR40_PHY_WORD_LANE_0_PHYBIST_VDL_ADJ_RESERVED0_SHIFT 29 7786 7787 /* DDR40_PHY_WORD_LANE_0 :: PHYBIST_VDL_ADJ :: dq1_vdl_adj [28:24] */ 7788 #define DDR40_PHY_WORD_LANE_0_PHYBIST_VDL_ADJ_DQ1_VDL_ADJ_MASK 0x1f000000 7789 #define DDR40_PHY_WORD_LANE_0_PHYBIST_VDL_ADJ_DQ1_VDL_ADJ_ALIGN 0 7790 #define DDR40_PHY_WORD_LANE_0_PHYBIST_VDL_ADJ_DQ1_VDL_ADJ_BITS 5 7791 #define DDR40_PHY_WORD_LANE_0_PHYBIST_VDL_ADJ_DQ1_VDL_ADJ_SHIFT 24 7792 7793 /* DDR40_PHY_WORD_LANE_0 :: PHYBIST_VDL_ADJ :: reserved1 [23:21] */ 7794 #define DDR40_PHY_WORD_LANE_0_PHYBIST_VDL_ADJ_RESERVED1_MASK 0x00e00000 7795 #define DDR40_PHY_WORD_LANE_0_PHYBIST_VDL_ADJ_RESERVED1_ALIGN 0 7796 #define DDR40_PHY_WORD_LANE_0_PHYBIST_VDL_ADJ_RESERVED1_BITS 3 7797 #define DDR40_PHY_WORD_LANE_0_PHYBIST_VDL_ADJ_RESERVED1_SHIFT 21 7798 7799 /* DDR40_PHY_WORD_LANE_0 :: PHYBIST_VDL_ADJ :: dq0_vdl_adj [20:16] */ 7800 #define DDR40_PHY_WORD_LANE_0_PHYBIST_VDL_ADJ_DQ0_VDL_ADJ_MASK 0x001f0000 7801 #define DDR40_PHY_WORD_LANE_0_PHYBIST_VDL_ADJ_DQ0_VDL_ADJ_ALIGN 0 7802 #define DDR40_PHY_WORD_LANE_0_PHYBIST_VDL_ADJ_DQ0_VDL_ADJ_BITS 5 7803 #define DDR40_PHY_WORD_LANE_0_PHYBIST_VDL_ADJ_DQ0_VDL_ADJ_SHIFT 16 7804 7805 /* DDR40_PHY_WORD_LANE_0 :: PHYBIST_VDL_ADJ :: reserved2 [15:13] */ 7806 #define DDR40_PHY_WORD_LANE_0_PHYBIST_VDL_ADJ_RESERVED2_MASK 0x0000e000 7807 #define DDR40_PHY_WORD_LANE_0_PHYBIST_VDL_ADJ_RESERVED2_ALIGN 0 7808 #define DDR40_PHY_WORD_LANE_0_PHYBIST_VDL_ADJ_RESERVED2_BITS 3 7809 #define DDR40_PHY_WORD_LANE_0_PHYBIST_VDL_ADJ_RESERVED2_SHIFT 13 7810 7811 /* DDR40_PHY_WORD_LANE_0 :: PHYBIST_VDL_ADJ :: dqs1_vdl_adj [12:08] */ 7812 #define DDR40_PHY_WORD_LANE_0_PHYBIST_VDL_ADJ_DQS1_VDL_ADJ_MASK 0x00001f00 7813 #define DDR40_PHY_WORD_LANE_0_PHYBIST_VDL_ADJ_DQS1_VDL_ADJ_ALIGN 0 7814 #define DDR40_PHY_WORD_LANE_0_PHYBIST_VDL_ADJ_DQS1_VDL_ADJ_BITS 5 7815 #define DDR40_PHY_WORD_LANE_0_PHYBIST_VDL_ADJ_DQS1_VDL_ADJ_SHIFT 8 7816 7817 /* DDR40_PHY_WORD_LANE_0 :: PHYBIST_VDL_ADJ :: reserved3 [07:05] */ 7818 #define DDR40_PHY_WORD_LANE_0_PHYBIST_VDL_ADJ_RESERVED3_MASK 0x000000e0 7819 #define DDR40_PHY_WORD_LANE_0_PHYBIST_VDL_ADJ_RESERVED3_ALIGN 0 7820 #define DDR40_PHY_WORD_LANE_0_PHYBIST_VDL_ADJ_RESERVED3_BITS 3 7821 #define DDR40_PHY_WORD_LANE_0_PHYBIST_VDL_ADJ_RESERVED3_SHIFT 5 7822 7823 /* DDR40_PHY_WORD_LANE_0 :: PHYBIST_VDL_ADJ :: dqs0_vdl_adj [04:00] */ 7824 #define DDR40_PHY_WORD_LANE_0_PHYBIST_VDL_ADJ_DQS0_VDL_ADJ_MASK 0x0000001f 7825 #define DDR40_PHY_WORD_LANE_0_PHYBIST_VDL_ADJ_DQS0_VDL_ADJ_ALIGN 0 7826 #define DDR40_PHY_WORD_LANE_0_PHYBIST_VDL_ADJ_DQS0_VDL_ADJ_BITS 5 7827 #define DDR40_PHY_WORD_LANE_0_PHYBIST_VDL_ADJ_DQS0_VDL_ADJ_SHIFT 0 7828 7829 7830 /**************************************************************************** 7831 * DDR40_PHY_DDR40_PHY_WORD_LANE_1 7832 */ 7833 /**************************************************************************** 7834 * DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE_RD_EN 7835 */ 7836 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE_RD_EN :: busy [31:31] */ 7837 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE_RD_EN_BUSY_MASK 0x80000000 7838 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE_RD_EN_BUSY_ALIGN 0 7839 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE_RD_EN_BUSY_BITS 1 7840 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE_RD_EN_BUSY_SHIFT 31 7841 7842 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE_RD_EN :: reserved0 [30:18] */ 7843 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE_RD_EN_RESERVED0_MASK 0x7ffc0000 7844 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE_RD_EN_RESERVED0_ALIGN 0 7845 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE_RD_EN_RESERVED0_BITS 13 7846 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE_RD_EN_RESERVED0_SHIFT 18 7847 7848 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE_RD_EN :: ovr_force [17:17] */ 7849 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE_RD_EN_OVR_FORCE_MASK 0x00020000 7850 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE_RD_EN_OVR_FORCE_ALIGN 0 7851 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE_RD_EN_OVR_FORCE_BITS 1 7852 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE_RD_EN_OVR_FORCE_SHIFT 17 7853 7854 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE_RD_EN :: ovr_en [16:16] */ 7855 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE_RD_EN_OVR_EN_MASK 0x00010000 7856 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE_RD_EN_OVR_EN_ALIGN 0 7857 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE_RD_EN_OVR_EN_BITS 1 7858 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE_RD_EN_OVR_EN_SHIFT 16 7859 7860 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE_RD_EN :: reserved1 [15:09] */ 7861 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE_RD_EN_RESERVED1_MASK 0x0000fe00 7862 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE_RD_EN_RESERVED1_ALIGN 0 7863 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE_RD_EN_RESERVED1_BITS 7 7864 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE_RD_EN_RESERVED1_SHIFT 9 7865 7866 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE_RD_EN :: byte_sel [08:08] */ 7867 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE_RD_EN_BYTE_SEL_MASK 0x00000100 7868 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE_RD_EN_BYTE_SEL_ALIGN 0 7869 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE_RD_EN_BYTE_SEL_BITS 1 7870 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE_RD_EN_BYTE_SEL_SHIFT 8 7871 7872 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE_RD_EN :: reserved2 [07:06] */ 7873 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE_RD_EN_RESERVED2_MASK 0x000000c0 7874 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE_RD_EN_RESERVED2_ALIGN 0 7875 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE_RD_EN_RESERVED2_BITS 2 7876 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE_RD_EN_RESERVED2_SHIFT 6 7877 7878 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE_RD_EN :: ovr_step [05:00] */ 7879 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE_RD_EN_OVR_STEP_MASK 0x0000003f 7880 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE_RD_EN_OVR_STEP_ALIGN 0 7881 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE_RD_EN_OVR_STEP_BITS 6 7882 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE_RD_EN_OVR_STEP_SHIFT 0 7883 7884 7885 /**************************************************************************** 7886 * DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_W 7887 */ 7888 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_W :: busy [31:31] */ 7889 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_W_BUSY_MASK 0x80000000 7890 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_W_BUSY_ALIGN 0 7891 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_W_BUSY_BITS 1 7892 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_W_BUSY_SHIFT 31 7893 7894 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_W :: reserved0 [30:18] */ 7895 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_W_RESERVED0_MASK 0x7ffc0000 7896 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_W_RESERVED0_ALIGN 0 7897 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_W_RESERVED0_BITS 13 7898 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_W_RESERVED0_SHIFT 18 7899 7900 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_W :: ovr_force [17:17] */ 7901 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_W_OVR_FORCE_MASK 0x00020000 7902 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_W_OVR_FORCE_ALIGN 0 7903 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_W_OVR_FORCE_BITS 1 7904 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_W_OVR_FORCE_SHIFT 17 7905 7906 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_W :: ovr_en [16:16] */ 7907 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_W_OVR_EN_MASK 0x00010000 7908 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_W_OVR_EN_ALIGN 0 7909 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_W_OVR_EN_BITS 1 7910 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_W_OVR_EN_SHIFT 16 7911 7912 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_W :: reserved1 [15:09] */ 7913 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_W_RESERVED1_MASK 0x0000fe00 7914 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_W_RESERVED1_ALIGN 0 7915 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_W_RESERVED1_BITS 7 7916 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_W_RESERVED1_SHIFT 9 7917 7918 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_W :: byte_sel [08:08] */ 7919 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_W_BYTE_SEL_MASK 0x00000100 7920 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_W_BYTE_SEL_ALIGN 0 7921 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_W_BYTE_SEL_BITS 1 7922 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_W_BYTE_SEL_SHIFT 8 7923 7924 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_W :: reserved2 [07:06] */ 7925 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_W_RESERVED2_MASK 0x000000c0 7926 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_W_RESERVED2_ALIGN 0 7927 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_W_RESERVED2_BITS 2 7928 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_W_RESERVED2_SHIFT 6 7929 7930 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_W :: ovr_step [05:00] */ 7931 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_W_OVR_STEP_MASK 0x0000003f 7932 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_W_OVR_STEP_ALIGN 0 7933 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_W_OVR_STEP_BITS 6 7934 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_W_OVR_STEP_SHIFT 0 7935 7936 7937 /**************************************************************************** 7938 * DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_R_P 7939 */ 7940 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_R_P :: busy [31:31] */ 7941 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_P_BUSY_MASK 0x80000000 7942 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_P_BUSY_ALIGN 0 7943 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_P_BUSY_BITS 1 7944 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_P_BUSY_SHIFT 31 7945 7946 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_R_P :: reserved0 [30:18] */ 7947 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_P_RESERVED0_MASK 0x7ffc0000 7948 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_P_RESERVED0_ALIGN 0 7949 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_P_RESERVED0_BITS 13 7950 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_P_RESERVED0_SHIFT 18 7951 7952 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_R_P :: ovr_force [17:17] */ 7953 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_P_OVR_FORCE_MASK 0x00020000 7954 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_P_OVR_FORCE_ALIGN 0 7955 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_P_OVR_FORCE_BITS 1 7956 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_P_OVR_FORCE_SHIFT 17 7957 7958 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_R_P :: ovr_en [16:16] */ 7959 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_P_OVR_EN_MASK 0x00010000 7960 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_P_OVR_EN_ALIGN 0 7961 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_P_OVR_EN_BITS 1 7962 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_P_OVR_EN_SHIFT 16 7963 7964 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_R_P :: reserved1 [15:09] */ 7965 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_P_RESERVED1_MASK 0x0000fe00 7966 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_P_RESERVED1_ALIGN 0 7967 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_P_RESERVED1_BITS 7 7968 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_P_RESERVED1_SHIFT 9 7969 7970 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_R_P :: byte_sel [08:08] */ 7971 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_P_BYTE_SEL_MASK 0x00000100 7972 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_P_BYTE_SEL_ALIGN 0 7973 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_P_BYTE_SEL_BITS 1 7974 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_P_BYTE_SEL_SHIFT 8 7975 7976 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_R_P :: reserved2 [07:06] */ 7977 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_P_RESERVED2_MASK 0x000000c0 7978 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_P_RESERVED2_ALIGN 0 7979 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_P_RESERVED2_BITS 2 7980 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_P_RESERVED2_SHIFT 6 7981 7982 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_R_P :: ovr_step [05:00] */ 7983 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_P_OVR_STEP_MASK 0x0000003f 7984 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_P_OVR_STEP_ALIGN 0 7985 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_P_OVR_STEP_BITS 6 7986 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_P_OVR_STEP_SHIFT 0 7987 7988 7989 /**************************************************************************** 7990 * DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_R_N 7991 */ 7992 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_R_N :: busy [31:31] */ 7993 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_N_BUSY_MASK 0x80000000 7994 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_N_BUSY_ALIGN 0 7995 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_N_BUSY_BITS 1 7996 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_N_BUSY_SHIFT 31 7997 7998 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_R_N :: reserved0 [30:18] */ 7999 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_N_RESERVED0_MASK 0x7ffc0000 8000 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_N_RESERVED0_ALIGN 0 8001 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_N_RESERVED0_BITS 13 8002 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_N_RESERVED0_SHIFT 18 8003 8004 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_R_N :: ovr_force [17:17] */ 8005 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_N_OVR_FORCE_MASK 0x00020000 8006 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_N_OVR_FORCE_ALIGN 0 8007 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_N_OVR_FORCE_BITS 1 8008 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_N_OVR_FORCE_SHIFT 17 8009 8010 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_R_N :: ovr_en [16:16] */ 8011 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_N_OVR_EN_MASK 0x00010000 8012 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_N_OVR_EN_ALIGN 0 8013 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_N_OVR_EN_BITS 1 8014 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_N_OVR_EN_SHIFT 16 8015 8016 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_R_N :: reserved1 [15:09] */ 8017 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_N_RESERVED1_MASK 0x0000fe00 8018 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_N_RESERVED1_ALIGN 0 8019 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_N_RESERVED1_BITS 7 8020 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_N_RESERVED1_SHIFT 9 8021 8022 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_R_N :: byte_sel [08:08] */ 8023 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_N_BYTE_SEL_MASK 0x00000100 8024 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_N_BYTE_SEL_ALIGN 0 8025 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_N_BYTE_SEL_BITS 1 8026 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_N_BYTE_SEL_SHIFT 8 8027 8028 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_R_N :: reserved2 [07:06] */ 8029 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_N_RESERVED2_MASK 0x000000c0 8030 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_N_RESERVED2_ALIGN 0 8031 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_N_RESERVED2_BITS 2 8032 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_N_RESERVED2_SHIFT 6 8033 8034 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_R_N :: ovr_step [05:00] */ 8035 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_N_OVR_STEP_MASK 0x0000003f 8036 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_N_OVR_STEP_ALIGN 0 8037 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_N_OVR_STEP_BITS 6 8038 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_N_OVR_STEP_SHIFT 0 8039 8040 8041 /**************************************************************************** 8042 * DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT0_W 8043 */ 8044 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT0_W :: busy [31:31] */ 8045 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_W_BUSY_MASK 0x80000000 8046 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_W_BUSY_ALIGN 0 8047 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_W_BUSY_BITS 1 8048 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_W_BUSY_SHIFT 31 8049 8050 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT0_W :: reserved0 [30:18] */ 8051 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_W_RESERVED0_MASK 0x7ffc0000 8052 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_W_RESERVED0_ALIGN 0 8053 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_W_RESERVED0_BITS 13 8054 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_W_RESERVED0_SHIFT 18 8055 8056 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT0_W :: ovr_force [17:17] */ 8057 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_W_OVR_FORCE_MASK 0x00020000 8058 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_W_OVR_FORCE_ALIGN 0 8059 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_W_OVR_FORCE_BITS 1 8060 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_W_OVR_FORCE_SHIFT 17 8061 8062 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT0_W :: ovr_en [16:16] */ 8063 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_W_OVR_EN_MASK 0x00010000 8064 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_W_OVR_EN_ALIGN 0 8065 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_W_OVR_EN_BITS 1 8066 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_W_OVR_EN_SHIFT 16 8067 8068 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT0_W :: reserved1 [15:09] */ 8069 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_W_RESERVED1_MASK 0x0000fe00 8070 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_W_RESERVED1_ALIGN 0 8071 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_W_RESERVED1_BITS 7 8072 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_W_RESERVED1_SHIFT 9 8073 8074 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT0_W :: byte_sel [08:08] */ 8075 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_W_BYTE_SEL_MASK 0x00000100 8076 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_W_BYTE_SEL_ALIGN 0 8077 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_W_BYTE_SEL_BITS 1 8078 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_W_BYTE_SEL_SHIFT 8 8079 8080 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT0_W :: reserved2 [07:06] */ 8081 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_W_RESERVED2_MASK 0x000000c0 8082 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_W_RESERVED2_ALIGN 0 8083 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_W_RESERVED2_BITS 2 8084 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_W_RESERVED2_SHIFT 6 8085 8086 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT0_W :: ovr_step [05:00] */ 8087 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_W_OVR_STEP_MASK 0x0000003f 8088 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_W_OVR_STEP_ALIGN 0 8089 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_W_OVR_STEP_BITS 6 8090 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_W_OVR_STEP_SHIFT 0 8091 8092 8093 /**************************************************************************** 8094 * DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT1_W 8095 */ 8096 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT1_W :: busy [31:31] */ 8097 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_W_BUSY_MASK 0x80000000 8098 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_W_BUSY_ALIGN 0 8099 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_W_BUSY_BITS 1 8100 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_W_BUSY_SHIFT 31 8101 8102 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT1_W :: reserved0 [30:18] */ 8103 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_W_RESERVED0_MASK 0x7ffc0000 8104 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_W_RESERVED0_ALIGN 0 8105 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_W_RESERVED0_BITS 13 8106 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_W_RESERVED0_SHIFT 18 8107 8108 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT1_W :: ovr_force [17:17] */ 8109 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_W_OVR_FORCE_MASK 0x00020000 8110 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_W_OVR_FORCE_ALIGN 0 8111 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_W_OVR_FORCE_BITS 1 8112 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_W_OVR_FORCE_SHIFT 17 8113 8114 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT1_W :: ovr_en [16:16] */ 8115 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_W_OVR_EN_MASK 0x00010000 8116 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_W_OVR_EN_ALIGN 0 8117 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_W_OVR_EN_BITS 1 8118 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_W_OVR_EN_SHIFT 16 8119 8120 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT1_W :: reserved1 [15:09] */ 8121 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_W_RESERVED1_MASK 0x0000fe00 8122 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_W_RESERVED1_ALIGN 0 8123 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_W_RESERVED1_BITS 7 8124 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_W_RESERVED1_SHIFT 9 8125 8126 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT1_W :: byte_sel [08:08] */ 8127 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_W_BYTE_SEL_MASK 0x00000100 8128 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_W_BYTE_SEL_ALIGN 0 8129 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_W_BYTE_SEL_BITS 1 8130 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_W_BYTE_SEL_SHIFT 8 8131 8132 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT1_W :: reserved2 [07:06] */ 8133 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_W_RESERVED2_MASK 0x000000c0 8134 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_W_RESERVED2_ALIGN 0 8135 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_W_RESERVED2_BITS 2 8136 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_W_RESERVED2_SHIFT 6 8137 8138 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT1_W :: ovr_step [05:00] */ 8139 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_W_OVR_STEP_MASK 0x0000003f 8140 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_W_OVR_STEP_ALIGN 0 8141 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_W_OVR_STEP_BITS 6 8142 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_W_OVR_STEP_SHIFT 0 8143 8144 8145 /**************************************************************************** 8146 * DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT2_W 8147 */ 8148 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT2_W :: busy [31:31] */ 8149 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_W_BUSY_MASK 0x80000000 8150 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_W_BUSY_ALIGN 0 8151 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_W_BUSY_BITS 1 8152 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_W_BUSY_SHIFT 31 8153 8154 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT2_W :: reserved0 [30:18] */ 8155 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_W_RESERVED0_MASK 0x7ffc0000 8156 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_W_RESERVED0_ALIGN 0 8157 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_W_RESERVED0_BITS 13 8158 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_W_RESERVED0_SHIFT 18 8159 8160 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT2_W :: ovr_force [17:17] */ 8161 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_W_OVR_FORCE_MASK 0x00020000 8162 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_W_OVR_FORCE_ALIGN 0 8163 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_W_OVR_FORCE_BITS 1 8164 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_W_OVR_FORCE_SHIFT 17 8165 8166 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT2_W :: ovr_en [16:16] */ 8167 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_W_OVR_EN_MASK 0x00010000 8168 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_W_OVR_EN_ALIGN 0 8169 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_W_OVR_EN_BITS 1 8170 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_W_OVR_EN_SHIFT 16 8171 8172 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT2_W :: reserved1 [15:09] */ 8173 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_W_RESERVED1_MASK 0x0000fe00 8174 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_W_RESERVED1_ALIGN 0 8175 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_W_RESERVED1_BITS 7 8176 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_W_RESERVED1_SHIFT 9 8177 8178 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT2_W :: byte_sel [08:08] */ 8179 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_W_BYTE_SEL_MASK 0x00000100 8180 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_W_BYTE_SEL_ALIGN 0 8181 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_W_BYTE_SEL_BITS 1 8182 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_W_BYTE_SEL_SHIFT 8 8183 8184 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT2_W :: reserved2 [07:06] */ 8185 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_W_RESERVED2_MASK 0x000000c0 8186 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_W_RESERVED2_ALIGN 0 8187 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_W_RESERVED2_BITS 2 8188 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_W_RESERVED2_SHIFT 6 8189 8190 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT2_W :: ovr_step [05:00] */ 8191 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_W_OVR_STEP_MASK 0x0000003f 8192 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_W_OVR_STEP_ALIGN 0 8193 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_W_OVR_STEP_BITS 6 8194 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_W_OVR_STEP_SHIFT 0 8195 8196 8197 /**************************************************************************** 8198 * DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT3_W 8199 */ 8200 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT3_W :: busy [31:31] */ 8201 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_W_BUSY_MASK 0x80000000 8202 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_W_BUSY_ALIGN 0 8203 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_W_BUSY_BITS 1 8204 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_W_BUSY_SHIFT 31 8205 8206 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT3_W :: reserved0 [30:18] */ 8207 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_W_RESERVED0_MASK 0x7ffc0000 8208 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_W_RESERVED0_ALIGN 0 8209 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_W_RESERVED0_BITS 13 8210 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_W_RESERVED0_SHIFT 18 8211 8212 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT3_W :: ovr_force [17:17] */ 8213 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_W_OVR_FORCE_MASK 0x00020000 8214 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_W_OVR_FORCE_ALIGN 0 8215 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_W_OVR_FORCE_BITS 1 8216 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_W_OVR_FORCE_SHIFT 17 8217 8218 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT3_W :: ovr_en [16:16] */ 8219 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_W_OVR_EN_MASK 0x00010000 8220 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_W_OVR_EN_ALIGN 0 8221 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_W_OVR_EN_BITS 1 8222 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_W_OVR_EN_SHIFT 16 8223 8224 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT3_W :: reserved1 [15:09] */ 8225 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_W_RESERVED1_MASK 0x0000fe00 8226 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_W_RESERVED1_ALIGN 0 8227 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_W_RESERVED1_BITS 7 8228 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_W_RESERVED1_SHIFT 9 8229 8230 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT3_W :: byte_sel [08:08] */ 8231 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_W_BYTE_SEL_MASK 0x00000100 8232 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_W_BYTE_SEL_ALIGN 0 8233 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_W_BYTE_SEL_BITS 1 8234 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_W_BYTE_SEL_SHIFT 8 8235 8236 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT3_W :: reserved2 [07:06] */ 8237 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_W_RESERVED2_MASK 0x000000c0 8238 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_W_RESERVED2_ALIGN 0 8239 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_W_RESERVED2_BITS 2 8240 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_W_RESERVED2_SHIFT 6 8241 8242 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT3_W :: ovr_step [05:00] */ 8243 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_W_OVR_STEP_MASK 0x0000003f 8244 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_W_OVR_STEP_ALIGN 0 8245 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_W_OVR_STEP_BITS 6 8246 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_W_OVR_STEP_SHIFT 0 8247 8248 8249 /**************************************************************************** 8250 * DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT4_W 8251 */ 8252 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT4_W :: busy [31:31] */ 8253 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_W_BUSY_MASK 0x80000000 8254 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_W_BUSY_ALIGN 0 8255 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_W_BUSY_BITS 1 8256 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_W_BUSY_SHIFT 31 8257 8258 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT4_W :: reserved0 [30:18] */ 8259 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_W_RESERVED0_MASK 0x7ffc0000 8260 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_W_RESERVED0_ALIGN 0 8261 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_W_RESERVED0_BITS 13 8262 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_W_RESERVED0_SHIFT 18 8263 8264 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT4_W :: ovr_force [17:17] */ 8265 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_W_OVR_FORCE_MASK 0x00020000 8266 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_W_OVR_FORCE_ALIGN 0 8267 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_W_OVR_FORCE_BITS 1 8268 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_W_OVR_FORCE_SHIFT 17 8269 8270 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT4_W :: ovr_en [16:16] */ 8271 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_W_OVR_EN_MASK 0x00010000 8272 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_W_OVR_EN_ALIGN 0 8273 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_W_OVR_EN_BITS 1 8274 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_W_OVR_EN_SHIFT 16 8275 8276 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT4_W :: reserved1 [15:09] */ 8277 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_W_RESERVED1_MASK 0x0000fe00 8278 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_W_RESERVED1_ALIGN 0 8279 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_W_RESERVED1_BITS 7 8280 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_W_RESERVED1_SHIFT 9 8281 8282 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT4_W :: byte_sel [08:08] */ 8283 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_W_BYTE_SEL_MASK 0x00000100 8284 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_W_BYTE_SEL_ALIGN 0 8285 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_W_BYTE_SEL_BITS 1 8286 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_W_BYTE_SEL_SHIFT 8 8287 8288 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT4_W :: reserved2 [07:06] */ 8289 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_W_RESERVED2_MASK 0x000000c0 8290 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_W_RESERVED2_ALIGN 0 8291 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_W_RESERVED2_BITS 2 8292 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_W_RESERVED2_SHIFT 6 8293 8294 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT4_W :: ovr_step [05:00] */ 8295 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_W_OVR_STEP_MASK 0x0000003f 8296 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_W_OVR_STEP_ALIGN 0 8297 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_W_OVR_STEP_BITS 6 8298 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_W_OVR_STEP_SHIFT 0 8299 8300 8301 /**************************************************************************** 8302 * DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT5_W 8303 */ 8304 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT5_W :: busy [31:31] */ 8305 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_W_BUSY_MASK 0x80000000 8306 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_W_BUSY_ALIGN 0 8307 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_W_BUSY_BITS 1 8308 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_W_BUSY_SHIFT 31 8309 8310 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT5_W :: reserved0 [30:18] */ 8311 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_W_RESERVED0_MASK 0x7ffc0000 8312 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_W_RESERVED0_ALIGN 0 8313 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_W_RESERVED0_BITS 13 8314 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_W_RESERVED0_SHIFT 18 8315 8316 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT5_W :: ovr_force [17:17] */ 8317 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_W_OVR_FORCE_MASK 0x00020000 8318 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_W_OVR_FORCE_ALIGN 0 8319 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_W_OVR_FORCE_BITS 1 8320 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_W_OVR_FORCE_SHIFT 17 8321 8322 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT5_W :: ovr_en [16:16] */ 8323 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_W_OVR_EN_MASK 0x00010000 8324 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_W_OVR_EN_ALIGN 0 8325 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_W_OVR_EN_BITS 1 8326 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_W_OVR_EN_SHIFT 16 8327 8328 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT5_W :: reserved1 [15:09] */ 8329 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_W_RESERVED1_MASK 0x0000fe00 8330 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_W_RESERVED1_ALIGN 0 8331 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_W_RESERVED1_BITS 7 8332 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_W_RESERVED1_SHIFT 9 8333 8334 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT5_W :: byte_sel [08:08] */ 8335 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_W_BYTE_SEL_MASK 0x00000100 8336 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_W_BYTE_SEL_ALIGN 0 8337 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_W_BYTE_SEL_BITS 1 8338 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_W_BYTE_SEL_SHIFT 8 8339 8340 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT5_W :: reserved2 [07:06] */ 8341 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_W_RESERVED2_MASK 0x000000c0 8342 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_W_RESERVED2_ALIGN 0 8343 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_W_RESERVED2_BITS 2 8344 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_W_RESERVED2_SHIFT 6 8345 8346 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT5_W :: ovr_step [05:00] */ 8347 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_W_OVR_STEP_MASK 0x0000003f 8348 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_W_OVR_STEP_ALIGN 0 8349 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_W_OVR_STEP_BITS 6 8350 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_W_OVR_STEP_SHIFT 0 8351 8352 8353 /**************************************************************************** 8354 * DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT6_W 8355 */ 8356 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT6_W :: busy [31:31] */ 8357 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_W_BUSY_MASK 0x80000000 8358 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_W_BUSY_ALIGN 0 8359 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_W_BUSY_BITS 1 8360 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_W_BUSY_SHIFT 31 8361 8362 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT6_W :: reserved0 [30:18] */ 8363 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_W_RESERVED0_MASK 0x7ffc0000 8364 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_W_RESERVED0_ALIGN 0 8365 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_W_RESERVED0_BITS 13 8366 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_W_RESERVED0_SHIFT 18 8367 8368 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT6_W :: ovr_force [17:17] */ 8369 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_W_OVR_FORCE_MASK 0x00020000 8370 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_W_OVR_FORCE_ALIGN 0 8371 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_W_OVR_FORCE_BITS 1 8372 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_W_OVR_FORCE_SHIFT 17 8373 8374 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT6_W :: ovr_en [16:16] */ 8375 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_W_OVR_EN_MASK 0x00010000 8376 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_W_OVR_EN_ALIGN 0 8377 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_W_OVR_EN_BITS 1 8378 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_W_OVR_EN_SHIFT 16 8379 8380 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT6_W :: reserved1 [15:09] */ 8381 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_W_RESERVED1_MASK 0x0000fe00 8382 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_W_RESERVED1_ALIGN 0 8383 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_W_RESERVED1_BITS 7 8384 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_W_RESERVED1_SHIFT 9 8385 8386 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT6_W :: byte_sel [08:08] */ 8387 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_W_BYTE_SEL_MASK 0x00000100 8388 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_W_BYTE_SEL_ALIGN 0 8389 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_W_BYTE_SEL_BITS 1 8390 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_W_BYTE_SEL_SHIFT 8 8391 8392 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT6_W :: reserved2 [07:06] */ 8393 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_W_RESERVED2_MASK 0x000000c0 8394 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_W_RESERVED2_ALIGN 0 8395 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_W_RESERVED2_BITS 2 8396 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_W_RESERVED2_SHIFT 6 8397 8398 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT6_W :: ovr_step [05:00] */ 8399 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_W_OVR_STEP_MASK 0x0000003f 8400 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_W_OVR_STEP_ALIGN 0 8401 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_W_OVR_STEP_BITS 6 8402 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_W_OVR_STEP_SHIFT 0 8403 8404 8405 /**************************************************************************** 8406 * DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT7_W 8407 */ 8408 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT7_W :: busy [31:31] */ 8409 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_W_BUSY_MASK 0x80000000 8410 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_W_BUSY_ALIGN 0 8411 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_W_BUSY_BITS 1 8412 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_W_BUSY_SHIFT 31 8413 8414 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT7_W :: reserved0 [30:18] */ 8415 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_W_RESERVED0_MASK 0x7ffc0000 8416 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_W_RESERVED0_ALIGN 0 8417 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_W_RESERVED0_BITS 13 8418 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_W_RESERVED0_SHIFT 18 8419 8420 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT7_W :: ovr_force [17:17] */ 8421 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_W_OVR_FORCE_MASK 0x00020000 8422 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_W_OVR_FORCE_ALIGN 0 8423 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_W_OVR_FORCE_BITS 1 8424 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_W_OVR_FORCE_SHIFT 17 8425 8426 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT7_W :: ovr_en [16:16] */ 8427 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_W_OVR_EN_MASK 0x00010000 8428 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_W_OVR_EN_ALIGN 0 8429 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_W_OVR_EN_BITS 1 8430 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_W_OVR_EN_SHIFT 16 8431 8432 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT7_W :: reserved1 [15:09] */ 8433 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_W_RESERVED1_MASK 0x0000fe00 8434 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_W_RESERVED1_ALIGN 0 8435 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_W_RESERVED1_BITS 7 8436 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_W_RESERVED1_SHIFT 9 8437 8438 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT7_W :: byte_sel [08:08] */ 8439 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_W_BYTE_SEL_MASK 0x00000100 8440 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_W_BYTE_SEL_ALIGN 0 8441 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_W_BYTE_SEL_BITS 1 8442 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_W_BYTE_SEL_SHIFT 8 8443 8444 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT7_W :: reserved2 [07:06] */ 8445 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_W_RESERVED2_MASK 0x000000c0 8446 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_W_RESERVED2_ALIGN 0 8447 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_W_RESERVED2_BITS 2 8448 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_W_RESERVED2_SHIFT 6 8449 8450 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT7_W :: ovr_step [05:00] */ 8451 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_W_OVR_STEP_MASK 0x0000003f 8452 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_W_OVR_STEP_ALIGN 0 8453 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_W_OVR_STEP_BITS 6 8454 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_W_OVR_STEP_SHIFT 0 8455 8456 8457 /**************************************************************************** 8458 * DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_DM_W 8459 */ 8460 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_DM_W :: busy [31:31] */ 8461 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_DM_W_BUSY_MASK 0x80000000 8462 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_DM_W_BUSY_ALIGN 0 8463 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_DM_W_BUSY_BITS 1 8464 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_DM_W_BUSY_SHIFT 31 8465 8466 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_DM_W :: reserved0 [30:18] */ 8467 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_DM_W_RESERVED0_MASK 0x7ffc0000 8468 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_DM_W_RESERVED0_ALIGN 0 8469 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_DM_W_RESERVED0_BITS 13 8470 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_DM_W_RESERVED0_SHIFT 18 8471 8472 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_DM_W :: ovr_force [17:17] */ 8473 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_DM_W_OVR_FORCE_MASK 0x00020000 8474 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_DM_W_OVR_FORCE_ALIGN 0 8475 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_DM_W_OVR_FORCE_BITS 1 8476 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_DM_W_OVR_FORCE_SHIFT 17 8477 8478 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_DM_W :: ovr_en [16:16] */ 8479 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_DM_W_OVR_EN_MASK 0x00010000 8480 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_DM_W_OVR_EN_ALIGN 0 8481 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_DM_W_OVR_EN_BITS 1 8482 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_DM_W_OVR_EN_SHIFT 16 8483 8484 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_DM_W :: reserved1 [15:09] */ 8485 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_DM_W_RESERVED1_MASK 0x0000fe00 8486 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_DM_W_RESERVED1_ALIGN 0 8487 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_DM_W_RESERVED1_BITS 7 8488 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_DM_W_RESERVED1_SHIFT 9 8489 8490 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_DM_W :: byte_sel [08:08] */ 8491 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_DM_W_BYTE_SEL_MASK 0x00000100 8492 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_DM_W_BYTE_SEL_ALIGN 0 8493 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_DM_W_BYTE_SEL_BITS 1 8494 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_DM_W_BYTE_SEL_SHIFT 8 8495 8496 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_DM_W :: reserved2 [07:06] */ 8497 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_DM_W_RESERVED2_MASK 0x000000c0 8498 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_DM_W_RESERVED2_ALIGN 0 8499 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_DM_W_RESERVED2_BITS 2 8500 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_DM_W_RESERVED2_SHIFT 6 8501 8502 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_DM_W :: ovr_step [05:00] */ 8503 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_DM_W_OVR_STEP_MASK 0x0000003f 8504 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_DM_W_OVR_STEP_ALIGN 0 8505 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_DM_W_OVR_STEP_BITS 6 8506 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_DM_W_OVR_STEP_SHIFT 0 8507 8508 8509 /**************************************************************************** 8510 * DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT0_R_P 8511 */ 8512 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: busy [31:31] */ 8513 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_P_BUSY_MASK 0x80000000 8514 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_P_BUSY_ALIGN 0 8515 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_P_BUSY_BITS 1 8516 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_P_BUSY_SHIFT 31 8517 8518 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: reserved0 [30:18] */ 8519 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_P_RESERVED0_MASK 0x7ffc0000 8520 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_P_RESERVED0_ALIGN 0 8521 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_P_RESERVED0_BITS 13 8522 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_P_RESERVED0_SHIFT 18 8523 8524 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: ovr_force [17:17] */ 8525 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_P_OVR_FORCE_MASK 0x00020000 8526 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_P_OVR_FORCE_ALIGN 0 8527 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_P_OVR_FORCE_BITS 1 8528 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_P_OVR_FORCE_SHIFT 17 8529 8530 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: ovr_en [16:16] */ 8531 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_P_OVR_EN_MASK 0x00010000 8532 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_P_OVR_EN_ALIGN 0 8533 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_P_OVR_EN_BITS 1 8534 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_P_OVR_EN_SHIFT 16 8535 8536 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: reserved1 [15:09] */ 8537 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_P_RESERVED1_MASK 0x0000fe00 8538 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_P_RESERVED1_ALIGN 0 8539 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_P_RESERVED1_BITS 7 8540 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_P_RESERVED1_SHIFT 9 8541 8542 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: byte_sel [08:08] */ 8543 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_P_BYTE_SEL_MASK 0x00000100 8544 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_P_BYTE_SEL_ALIGN 0 8545 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_P_BYTE_SEL_BITS 1 8546 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_P_BYTE_SEL_SHIFT 8 8547 8548 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: reserved2 [07:06] */ 8549 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_P_RESERVED2_MASK 0x000000c0 8550 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_P_RESERVED2_ALIGN 0 8551 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_P_RESERVED2_BITS 2 8552 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_P_RESERVED2_SHIFT 6 8553 8554 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT0_R_P :: ovr_step [05:00] */ 8555 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_P_OVR_STEP_MASK 0x0000003f 8556 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_P_OVR_STEP_ALIGN 0 8557 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_P_OVR_STEP_BITS 6 8558 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_P_OVR_STEP_SHIFT 0 8559 8560 8561 /**************************************************************************** 8562 * DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT0_R_N 8563 */ 8564 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: busy [31:31] */ 8565 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_N_BUSY_MASK 0x80000000 8566 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_N_BUSY_ALIGN 0 8567 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_N_BUSY_BITS 1 8568 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_N_BUSY_SHIFT 31 8569 8570 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: reserved0 [30:18] */ 8571 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_N_RESERVED0_MASK 0x7ffc0000 8572 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_N_RESERVED0_ALIGN 0 8573 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_N_RESERVED0_BITS 13 8574 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_N_RESERVED0_SHIFT 18 8575 8576 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: ovr_force [17:17] */ 8577 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_N_OVR_FORCE_MASK 0x00020000 8578 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_N_OVR_FORCE_ALIGN 0 8579 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_N_OVR_FORCE_BITS 1 8580 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_N_OVR_FORCE_SHIFT 17 8581 8582 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: ovr_en [16:16] */ 8583 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_N_OVR_EN_MASK 0x00010000 8584 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_N_OVR_EN_ALIGN 0 8585 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_N_OVR_EN_BITS 1 8586 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_N_OVR_EN_SHIFT 16 8587 8588 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: reserved1 [15:09] */ 8589 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_N_RESERVED1_MASK 0x0000fe00 8590 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_N_RESERVED1_ALIGN 0 8591 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_N_RESERVED1_BITS 7 8592 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_N_RESERVED1_SHIFT 9 8593 8594 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: byte_sel [08:08] */ 8595 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_N_BYTE_SEL_MASK 0x00000100 8596 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_N_BYTE_SEL_ALIGN 0 8597 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_N_BYTE_SEL_BITS 1 8598 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_N_BYTE_SEL_SHIFT 8 8599 8600 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: reserved2 [07:06] */ 8601 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_N_RESERVED2_MASK 0x000000c0 8602 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_N_RESERVED2_ALIGN 0 8603 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_N_RESERVED2_BITS 2 8604 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_N_RESERVED2_SHIFT 6 8605 8606 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT0_R_N :: ovr_step [05:00] */ 8607 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_N_OVR_STEP_MASK 0x0000003f 8608 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_N_OVR_STEP_ALIGN 0 8609 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_N_OVR_STEP_BITS 6 8610 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_N_OVR_STEP_SHIFT 0 8611 8612 8613 /**************************************************************************** 8614 * DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT1_R_P 8615 */ 8616 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: busy [31:31] */ 8617 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_P_BUSY_MASK 0x80000000 8618 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_P_BUSY_ALIGN 0 8619 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_P_BUSY_BITS 1 8620 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_P_BUSY_SHIFT 31 8621 8622 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: reserved0 [30:18] */ 8623 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_P_RESERVED0_MASK 0x7ffc0000 8624 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_P_RESERVED0_ALIGN 0 8625 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_P_RESERVED0_BITS 13 8626 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_P_RESERVED0_SHIFT 18 8627 8628 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: ovr_force [17:17] */ 8629 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_P_OVR_FORCE_MASK 0x00020000 8630 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_P_OVR_FORCE_ALIGN 0 8631 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_P_OVR_FORCE_BITS 1 8632 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_P_OVR_FORCE_SHIFT 17 8633 8634 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: ovr_en [16:16] */ 8635 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_P_OVR_EN_MASK 0x00010000 8636 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_P_OVR_EN_ALIGN 0 8637 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_P_OVR_EN_BITS 1 8638 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_P_OVR_EN_SHIFT 16 8639 8640 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: reserved1 [15:09] */ 8641 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_P_RESERVED1_MASK 0x0000fe00 8642 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_P_RESERVED1_ALIGN 0 8643 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_P_RESERVED1_BITS 7 8644 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_P_RESERVED1_SHIFT 9 8645 8646 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: byte_sel [08:08] */ 8647 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_P_BYTE_SEL_MASK 0x00000100 8648 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_P_BYTE_SEL_ALIGN 0 8649 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_P_BYTE_SEL_BITS 1 8650 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_P_BYTE_SEL_SHIFT 8 8651 8652 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: reserved2 [07:06] */ 8653 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_P_RESERVED2_MASK 0x000000c0 8654 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_P_RESERVED2_ALIGN 0 8655 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_P_RESERVED2_BITS 2 8656 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_P_RESERVED2_SHIFT 6 8657 8658 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT1_R_P :: ovr_step [05:00] */ 8659 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_P_OVR_STEP_MASK 0x0000003f 8660 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_P_OVR_STEP_ALIGN 0 8661 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_P_OVR_STEP_BITS 6 8662 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_P_OVR_STEP_SHIFT 0 8663 8664 8665 /**************************************************************************** 8666 * DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT1_R_N 8667 */ 8668 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: busy [31:31] */ 8669 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_N_BUSY_MASK 0x80000000 8670 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_N_BUSY_ALIGN 0 8671 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_N_BUSY_BITS 1 8672 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_N_BUSY_SHIFT 31 8673 8674 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: reserved0 [30:18] */ 8675 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_N_RESERVED0_MASK 0x7ffc0000 8676 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_N_RESERVED0_ALIGN 0 8677 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_N_RESERVED0_BITS 13 8678 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_N_RESERVED0_SHIFT 18 8679 8680 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: ovr_force [17:17] */ 8681 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_N_OVR_FORCE_MASK 0x00020000 8682 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_N_OVR_FORCE_ALIGN 0 8683 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_N_OVR_FORCE_BITS 1 8684 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_N_OVR_FORCE_SHIFT 17 8685 8686 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: ovr_en [16:16] */ 8687 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_N_OVR_EN_MASK 0x00010000 8688 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_N_OVR_EN_ALIGN 0 8689 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_N_OVR_EN_BITS 1 8690 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_N_OVR_EN_SHIFT 16 8691 8692 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: reserved1 [15:09] */ 8693 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_N_RESERVED1_MASK 0x0000fe00 8694 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_N_RESERVED1_ALIGN 0 8695 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_N_RESERVED1_BITS 7 8696 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_N_RESERVED1_SHIFT 9 8697 8698 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: byte_sel [08:08] */ 8699 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_N_BYTE_SEL_MASK 0x00000100 8700 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_N_BYTE_SEL_ALIGN 0 8701 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_N_BYTE_SEL_BITS 1 8702 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_N_BYTE_SEL_SHIFT 8 8703 8704 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: reserved2 [07:06] */ 8705 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_N_RESERVED2_MASK 0x000000c0 8706 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_N_RESERVED2_ALIGN 0 8707 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_N_RESERVED2_BITS 2 8708 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_N_RESERVED2_SHIFT 6 8709 8710 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT1_R_N :: ovr_step [05:00] */ 8711 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_N_OVR_STEP_MASK 0x0000003f 8712 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_N_OVR_STEP_ALIGN 0 8713 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_N_OVR_STEP_BITS 6 8714 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_N_OVR_STEP_SHIFT 0 8715 8716 8717 /**************************************************************************** 8718 * DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT2_R_P 8719 */ 8720 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: busy [31:31] */ 8721 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_P_BUSY_MASK 0x80000000 8722 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_P_BUSY_ALIGN 0 8723 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_P_BUSY_BITS 1 8724 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_P_BUSY_SHIFT 31 8725 8726 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: reserved0 [30:18] */ 8727 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_P_RESERVED0_MASK 0x7ffc0000 8728 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_P_RESERVED0_ALIGN 0 8729 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_P_RESERVED0_BITS 13 8730 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_P_RESERVED0_SHIFT 18 8731 8732 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: ovr_force [17:17] */ 8733 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_P_OVR_FORCE_MASK 0x00020000 8734 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_P_OVR_FORCE_ALIGN 0 8735 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_P_OVR_FORCE_BITS 1 8736 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_P_OVR_FORCE_SHIFT 17 8737 8738 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: ovr_en [16:16] */ 8739 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_P_OVR_EN_MASK 0x00010000 8740 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_P_OVR_EN_ALIGN 0 8741 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_P_OVR_EN_BITS 1 8742 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_P_OVR_EN_SHIFT 16 8743 8744 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: reserved1 [15:09] */ 8745 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_P_RESERVED1_MASK 0x0000fe00 8746 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_P_RESERVED1_ALIGN 0 8747 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_P_RESERVED1_BITS 7 8748 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_P_RESERVED1_SHIFT 9 8749 8750 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: byte_sel [08:08] */ 8751 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_P_BYTE_SEL_MASK 0x00000100 8752 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_P_BYTE_SEL_ALIGN 0 8753 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_P_BYTE_SEL_BITS 1 8754 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_P_BYTE_SEL_SHIFT 8 8755 8756 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: reserved2 [07:06] */ 8757 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_P_RESERVED2_MASK 0x000000c0 8758 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_P_RESERVED2_ALIGN 0 8759 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_P_RESERVED2_BITS 2 8760 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_P_RESERVED2_SHIFT 6 8761 8762 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT2_R_P :: ovr_step [05:00] */ 8763 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_P_OVR_STEP_MASK 0x0000003f 8764 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_P_OVR_STEP_ALIGN 0 8765 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_P_OVR_STEP_BITS 6 8766 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_P_OVR_STEP_SHIFT 0 8767 8768 8769 /**************************************************************************** 8770 * DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT2_R_N 8771 */ 8772 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: busy [31:31] */ 8773 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_N_BUSY_MASK 0x80000000 8774 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_N_BUSY_ALIGN 0 8775 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_N_BUSY_BITS 1 8776 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_N_BUSY_SHIFT 31 8777 8778 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: reserved0 [30:18] */ 8779 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_N_RESERVED0_MASK 0x7ffc0000 8780 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_N_RESERVED0_ALIGN 0 8781 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_N_RESERVED0_BITS 13 8782 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_N_RESERVED0_SHIFT 18 8783 8784 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: ovr_force [17:17] */ 8785 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_N_OVR_FORCE_MASK 0x00020000 8786 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_N_OVR_FORCE_ALIGN 0 8787 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_N_OVR_FORCE_BITS 1 8788 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_N_OVR_FORCE_SHIFT 17 8789 8790 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: ovr_en [16:16] */ 8791 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_N_OVR_EN_MASK 0x00010000 8792 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_N_OVR_EN_ALIGN 0 8793 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_N_OVR_EN_BITS 1 8794 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_N_OVR_EN_SHIFT 16 8795 8796 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: reserved1 [15:09] */ 8797 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_N_RESERVED1_MASK 0x0000fe00 8798 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_N_RESERVED1_ALIGN 0 8799 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_N_RESERVED1_BITS 7 8800 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_N_RESERVED1_SHIFT 9 8801 8802 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: byte_sel [08:08] */ 8803 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_N_BYTE_SEL_MASK 0x00000100 8804 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_N_BYTE_SEL_ALIGN 0 8805 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_N_BYTE_SEL_BITS 1 8806 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_N_BYTE_SEL_SHIFT 8 8807 8808 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: reserved2 [07:06] */ 8809 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_N_RESERVED2_MASK 0x000000c0 8810 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_N_RESERVED2_ALIGN 0 8811 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_N_RESERVED2_BITS 2 8812 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_N_RESERVED2_SHIFT 6 8813 8814 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT2_R_N :: ovr_step [05:00] */ 8815 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_N_OVR_STEP_MASK 0x0000003f 8816 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_N_OVR_STEP_ALIGN 0 8817 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_N_OVR_STEP_BITS 6 8818 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_N_OVR_STEP_SHIFT 0 8819 8820 8821 /**************************************************************************** 8822 * DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT3_R_P 8823 */ 8824 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: busy [31:31] */ 8825 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_P_BUSY_MASK 0x80000000 8826 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_P_BUSY_ALIGN 0 8827 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_P_BUSY_BITS 1 8828 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_P_BUSY_SHIFT 31 8829 8830 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: reserved0 [30:18] */ 8831 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_P_RESERVED0_MASK 0x7ffc0000 8832 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_P_RESERVED0_ALIGN 0 8833 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_P_RESERVED0_BITS 13 8834 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_P_RESERVED0_SHIFT 18 8835 8836 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: ovr_force [17:17] */ 8837 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_P_OVR_FORCE_MASK 0x00020000 8838 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_P_OVR_FORCE_ALIGN 0 8839 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_P_OVR_FORCE_BITS 1 8840 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_P_OVR_FORCE_SHIFT 17 8841 8842 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: ovr_en [16:16] */ 8843 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_P_OVR_EN_MASK 0x00010000 8844 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_P_OVR_EN_ALIGN 0 8845 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_P_OVR_EN_BITS 1 8846 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_P_OVR_EN_SHIFT 16 8847 8848 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: reserved1 [15:09] */ 8849 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_P_RESERVED1_MASK 0x0000fe00 8850 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_P_RESERVED1_ALIGN 0 8851 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_P_RESERVED1_BITS 7 8852 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_P_RESERVED1_SHIFT 9 8853 8854 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: byte_sel [08:08] */ 8855 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_P_BYTE_SEL_MASK 0x00000100 8856 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_P_BYTE_SEL_ALIGN 0 8857 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_P_BYTE_SEL_BITS 1 8858 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_P_BYTE_SEL_SHIFT 8 8859 8860 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: reserved2 [07:06] */ 8861 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_P_RESERVED2_MASK 0x000000c0 8862 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_P_RESERVED2_ALIGN 0 8863 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_P_RESERVED2_BITS 2 8864 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_P_RESERVED2_SHIFT 6 8865 8866 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT3_R_P :: ovr_step [05:00] */ 8867 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_P_OVR_STEP_MASK 0x0000003f 8868 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_P_OVR_STEP_ALIGN 0 8869 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_P_OVR_STEP_BITS 6 8870 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_P_OVR_STEP_SHIFT 0 8871 8872 8873 /**************************************************************************** 8874 * DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT3_R_N 8875 */ 8876 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: busy [31:31] */ 8877 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_N_BUSY_MASK 0x80000000 8878 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_N_BUSY_ALIGN 0 8879 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_N_BUSY_BITS 1 8880 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_N_BUSY_SHIFT 31 8881 8882 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: reserved0 [30:18] */ 8883 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_N_RESERVED0_MASK 0x7ffc0000 8884 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_N_RESERVED0_ALIGN 0 8885 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_N_RESERVED0_BITS 13 8886 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_N_RESERVED0_SHIFT 18 8887 8888 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: ovr_force [17:17] */ 8889 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_N_OVR_FORCE_MASK 0x00020000 8890 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_N_OVR_FORCE_ALIGN 0 8891 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_N_OVR_FORCE_BITS 1 8892 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_N_OVR_FORCE_SHIFT 17 8893 8894 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: ovr_en [16:16] */ 8895 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_N_OVR_EN_MASK 0x00010000 8896 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_N_OVR_EN_ALIGN 0 8897 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_N_OVR_EN_BITS 1 8898 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_N_OVR_EN_SHIFT 16 8899 8900 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: reserved1 [15:09] */ 8901 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_N_RESERVED1_MASK 0x0000fe00 8902 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_N_RESERVED1_ALIGN 0 8903 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_N_RESERVED1_BITS 7 8904 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_N_RESERVED1_SHIFT 9 8905 8906 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: byte_sel [08:08] */ 8907 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_N_BYTE_SEL_MASK 0x00000100 8908 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_N_BYTE_SEL_ALIGN 0 8909 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_N_BYTE_SEL_BITS 1 8910 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_N_BYTE_SEL_SHIFT 8 8911 8912 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: reserved2 [07:06] */ 8913 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_N_RESERVED2_MASK 0x000000c0 8914 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_N_RESERVED2_ALIGN 0 8915 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_N_RESERVED2_BITS 2 8916 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_N_RESERVED2_SHIFT 6 8917 8918 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT3_R_N :: ovr_step [05:00] */ 8919 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_N_OVR_STEP_MASK 0x0000003f 8920 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_N_OVR_STEP_ALIGN 0 8921 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_N_OVR_STEP_BITS 6 8922 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_N_OVR_STEP_SHIFT 0 8923 8924 8925 /**************************************************************************** 8926 * DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT4_R_P 8927 */ 8928 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: busy [31:31] */ 8929 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_P_BUSY_MASK 0x80000000 8930 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_P_BUSY_ALIGN 0 8931 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_P_BUSY_BITS 1 8932 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_P_BUSY_SHIFT 31 8933 8934 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: reserved0 [30:18] */ 8935 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_P_RESERVED0_MASK 0x7ffc0000 8936 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_P_RESERVED0_ALIGN 0 8937 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_P_RESERVED0_BITS 13 8938 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_P_RESERVED0_SHIFT 18 8939 8940 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: ovr_force [17:17] */ 8941 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_P_OVR_FORCE_MASK 0x00020000 8942 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_P_OVR_FORCE_ALIGN 0 8943 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_P_OVR_FORCE_BITS 1 8944 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_P_OVR_FORCE_SHIFT 17 8945 8946 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: ovr_en [16:16] */ 8947 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_P_OVR_EN_MASK 0x00010000 8948 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_P_OVR_EN_ALIGN 0 8949 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_P_OVR_EN_BITS 1 8950 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_P_OVR_EN_SHIFT 16 8951 8952 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: reserved1 [15:09] */ 8953 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_P_RESERVED1_MASK 0x0000fe00 8954 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_P_RESERVED1_ALIGN 0 8955 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_P_RESERVED1_BITS 7 8956 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_P_RESERVED1_SHIFT 9 8957 8958 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: byte_sel [08:08] */ 8959 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_P_BYTE_SEL_MASK 0x00000100 8960 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_P_BYTE_SEL_ALIGN 0 8961 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_P_BYTE_SEL_BITS 1 8962 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_P_BYTE_SEL_SHIFT 8 8963 8964 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: reserved2 [07:06] */ 8965 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_P_RESERVED2_MASK 0x000000c0 8966 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_P_RESERVED2_ALIGN 0 8967 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_P_RESERVED2_BITS 2 8968 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_P_RESERVED2_SHIFT 6 8969 8970 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT4_R_P :: ovr_step [05:00] */ 8971 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_P_OVR_STEP_MASK 0x0000003f 8972 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_P_OVR_STEP_ALIGN 0 8973 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_P_OVR_STEP_BITS 6 8974 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_P_OVR_STEP_SHIFT 0 8975 8976 8977 /**************************************************************************** 8978 * DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT4_R_N 8979 */ 8980 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: busy [31:31] */ 8981 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_N_BUSY_MASK 0x80000000 8982 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_N_BUSY_ALIGN 0 8983 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_N_BUSY_BITS 1 8984 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_N_BUSY_SHIFT 31 8985 8986 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: reserved0 [30:18] */ 8987 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_N_RESERVED0_MASK 0x7ffc0000 8988 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_N_RESERVED0_ALIGN 0 8989 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_N_RESERVED0_BITS 13 8990 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_N_RESERVED0_SHIFT 18 8991 8992 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: ovr_force [17:17] */ 8993 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_N_OVR_FORCE_MASK 0x00020000 8994 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_N_OVR_FORCE_ALIGN 0 8995 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_N_OVR_FORCE_BITS 1 8996 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_N_OVR_FORCE_SHIFT 17 8997 8998 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: ovr_en [16:16] */ 8999 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_N_OVR_EN_MASK 0x00010000 9000 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_N_OVR_EN_ALIGN 0 9001 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_N_OVR_EN_BITS 1 9002 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_N_OVR_EN_SHIFT 16 9003 9004 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: reserved1 [15:09] */ 9005 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_N_RESERVED1_MASK 0x0000fe00 9006 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_N_RESERVED1_ALIGN 0 9007 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_N_RESERVED1_BITS 7 9008 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_N_RESERVED1_SHIFT 9 9009 9010 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: byte_sel [08:08] */ 9011 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_N_BYTE_SEL_MASK 0x00000100 9012 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_N_BYTE_SEL_ALIGN 0 9013 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_N_BYTE_SEL_BITS 1 9014 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_N_BYTE_SEL_SHIFT 8 9015 9016 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: reserved2 [07:06] */ 9017 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_N_RESERVED2_MASK 0x000000c0 9018 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_N_RESERVED2_ALIGN 0 9019 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_N_RESERVED2_BITS 2 9020 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_N_RESERVED2_SHIFT 6 9021 9022 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT4_R_N :: ovr_step [05:00] */ 9023 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_N_OVR_STEP_MASK 0x0000003f 9024 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_N_OVR_STEP_ALIGN 0 9025 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_N_OVR_STEP_BITS 6 9026 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_N_OVR_STEP_SHIFT 0 9027 9028 9029 /**************************************************************************** 9030 * DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT5_R_P 9031 */ 9032 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: busy [31:31] */ 9033 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_P_BUSY_MASK 0x80000000 9034 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_P_BUSY_ALIGN 0 9035 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_P_BUSY_BITS 1 9036 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_P_BUSY_SHIFT 31 9037 9038 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: reserved0 [30:18] */ 9039 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_P_RESERVED0_MASK 0x7ffc0000 9040 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_P_RESERVED0_ALIGN 0 9041 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_P_RESERVED0_BITS 13 9042 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_P_RESERVED0_SHIFT 18 9043 9044 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: ovr_force [17:17] */ 9045 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_P_OVR_FORCE_MASK 0x00020000 9046 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_P_OVR_FORCE_ALIGN 0 9047 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_P_OVR_FORCE_BITS 1 9048 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_P_OVR_FORCE_SHIFT 17 9049 9050 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: ovr_en [16:16] */ 9051 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_P_OVR_EN_MASK 0x00010000 9052 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_P_OVR_EN_ALIGN 0 9053 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_P_OVR_EN_BITS 1 9054 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_P_OVR_EN_SHIFT 16 9055 9056 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: reserved1 [15:09] */ 9057 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_P_RESERVED1_MASK 0x0000fe00 9058 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_P_RESERVED1_ALIGN 0 9059 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_P_RESERVED1_BITS 7 9060 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_P_RESERVED1_SHIFT 9 9061 9062 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: byte_sel [08:08] */ 9063 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_P_BYTE_SEL_MASK 0x00000100 9064 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_P_BYTE_SEL_ALIGN 0 9065 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_P_BYTE_SEL_BITS 1 9066 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_P_BYTE_SEL_SHIFT 8 9067 9068 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: reserved2 [07:06] */ 9069 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_P_RESERVED2_MASK 0x000000c0 9070 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_P_RESERVED2_ALIGN 0 9071 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_P_RESERVED2_BITS 2 9072 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_P_RESERVED2_SHIFT 6 9073 9074 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT5_R_P :: ovr_step [05:00] */ 9075 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_P_OVR_STEP_MASK 0x0000003f 9076 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_P_OVR_STEP_ALIGN 0 9077 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_P_OVR_STEP_BITS 6 9078 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_P_OVR_STEP_SHIFT 0 9079 9080 9081 /**************************************************************************** 9082 * DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT5_R_N 9083 */ 9084 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: busy [31:31] */ 9085 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_N_BUSY_MASK 0x80000000 9086 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_N_BUSY_ALIGN 0 9087 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_N_BUSY_BITS 1 9088 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_N_BUSY_SHIFT 31 9089 9090 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: reserved0 [30:18] */ 9091 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_N_RESERVED0_MASK 0x7ffc0000 9092 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_N_RESERVED0_ALIGN 0 9093 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_N_RESERVED0_BITS 13 9094 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_N_RESERVED0_SHIFT 18 9095 9096 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: ovr_force [17:17] */ 9097 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_N_OVR_FORCE_MASK 0x00020000 9098 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_N_OVR_FORCE_ALIGN 0 9099 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_N_OVR_FORCE_BITS 1 9100 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_N_OVR_FORCE_SHIFT 17 9101 9102 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: ovr_en [16:16] */ 9103 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_N_OVR_EN_MASK 0x00010000 9104 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_N_OVR_EN_ALIGN 0 9105 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_N_OVR_EN_BITS 1 9106 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_N_OVR_EN_SHIFT 16 9107 9108 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: reserved1 [15:09] */ 9109 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_N_RESERVED1_MASK 0x0000fe00 9110 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_N_RESERVED1_ALIGN 0 9111 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_N_RESERVED1_BITS 7 9112 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_N_RESERVED1_SHIFT 9 9113 9114 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: byte_sel [08:08] */ 9115 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_N_BYTE_SEL_MASK 0x00000100 9116 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_N_BYTE_SEL_ALIGN 0 9117 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_N_BYTE_SEL_BITS 1 9118 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_N_BYTE_SEL_SHIFT 8 9119 9120 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: reserved2 [07:06] */ 9121 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_N_RESERVED2_MASK 0x000000c0 9122 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_N_RESERVED2_ALIGN 0 9123 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_N_RESERVED2_BITS 2 9124 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_N_RESERVED2_SHIFT 6 9125 9126 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT5_R_N :: ovr_step [05:00] */ 9127 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_N_OVR_STEP_MASK 0x0000003f 9128 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_N_OVR_STEP_ALIGN 0 9129 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_N_OVR_STEP_BITS 6 9130 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_N_OVR_STEP_SHIFT 0 9131 9132 9133 /**************************************************************************** 9134 * DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT6_R_P 9135 */ 9136 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: busy [31:31] */ 9137 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_P_BUSY_MASK 0x80000000 9138 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_P_BUSY_ALIGN 0 9139 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_P_BUSY_BITS 1 9140 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_P_BUSY_SHIFT 31 9141 9142 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: reserved0 [30:18] */ 9143 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_P_RESERVED0_MASK 0x7ffc0000 9144 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_P_RESERVED0_ALIGN 0 9145 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_P_RESERVED0_BITS 13 9146 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_P_RESERVED0_SHIFT 18 9147 9148 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: ovr_force [17:17] */ 9149 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_P_OVR_FORCE_MASK 0x00020000 9150 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_P_OVR_FORCE_ALIGN 0 9151 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_P_OVR_FORCE_BITS 1 9152 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_P_OVR_FORCE_SHIFT 17 9153 9154 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: ovr_en [16:16] */ 9155 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_P_OVR_EN_MASK 0x00010000 9156 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_P_OVR_EN_ALIGN 0 9157 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_P_OVR_EN_BITS 1 9158 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_P_OVR_EN_SHIFT 16 9159 9160 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: reserved1 [15:09] */ 9161 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_P_RESERVED1_MASK 0x0000fe00 9162 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_P_RESERVED1_ALIGN 0 9163 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_P_RESERVED1_BITS 7 9164 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_P_RESERVED1_SHIFT 9 9165 9166 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: byte_sel [08:08] */ 9167 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_P_BYTE_SEL_MASK 0x00000100 9168 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_P_BYTE_SEL_ALIGN 0 9169 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_P_BYTE_SEL_BITS 1 9170 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_P_BYTE_SEL_SHIFT 8 9171 9172 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: reserved2 [07:06] */ 9173 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_P_RESERVED2_MASK 0x000000c0 9174 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_P_RESERVED2_ALIGN 0 9175 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_P_RESERVED2_BITS 2 9176 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_P_RESERVED2_SHIFT 6 9177 9178 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT6_R_P :: ovr_step [05:00] */ 9179 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_P_OVR_STEP_MASK 0x0000003f 9180 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_P_OVR_STEP_ALIGN 0 9181 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_P_OVR_STEP_BITS 6 9182 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_P_OVR_STEP_SHIFT 0 9183 9184 9185 /**************************************************************************** 9186 * DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT6_R_N 9187 */ 9188 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: busy [31:31] */ 9189 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_N_BUSY_MASK 0x80000000 9190 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_N_BUSY_ALIGN 0 9191 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_N_BUSY_BITS 1 9192 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_N_BUSY_SHIFT 31 9193 9194 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: reserved0 [30:18] */ 9195 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_N_RESERVED0_MASK 0x7ffc0000 9196 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_N_RESERVED0_ALIGN 0 9197 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_N_RESERVED0_BITS 13 9198 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_N_RESERVED0_SHIFT 18 9199 9200 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: ovr_force [17:17] */ 9201 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_N_OVR_FORCE_MASK 0x00020000 9202 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_N_OVR_FORCE_ALIGN 0 9203 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_N_OVR_FORCE_BITS 1 9204 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_N_OVR_FORCE_SHIFT 17 9205 9206 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: ovr_en [16:16] */ 9207 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_N_OVR_EN_MASK 0x00010000 9208 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_N_OVR_EN_ALIGN 0 9209 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_N_OVR_EN_BITS 1 9210 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_N_OVR_EN_SHIFT 16 9211 9212 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: reserved1 [15:09] */ 9213 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_N_RESERVED1_MASK 0x0000fe00 9214 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_N_RESERVED1_ALIGN 0 9215 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_N_RESERVED1_BITS 7 9216 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_N_RESERVED1_SHIFT 9 9217 9218 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: byte_sel [08:08] */ 9219 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_N_BYTE_SEL_MASK 0x00000100 9220 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_N_BYTE_SEL_ALIGN 0 9221 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_N_BYTE_SEL_BITS 1 9222 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_N_BYTE_SEL_SHIFT 8 9223 9224 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: reserved2 [07:06] */ 9225 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_N_RESERVED2_MASK 0x000000c0 9226 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_N_RESERVED2_ALIGN 0 9227 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_N_RESERVED2_BITS 2 9228 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_N_RESERVED2_SHIFT 6 9229 9230 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT6_R_N :: ovr_step [05:00] */ 9231 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_N_OVR_STEP_MASK 0x0000003f 9232 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_N_OVR_STEP_ALIGN 0 9233 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_N_OVR_STEP_BITS 6 9234 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_N_OVR_STEP_SHIFT 0 9235 9236 9237 /**************************************************************************** 9238 * DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT7_R_P 9239 */ 9240 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: busy [31:31] */ 9241 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_P_BUSY_MASK 0x80000000 9242 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_P_BUSY_ALIGN 0 9243 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_P_BUSY_BITS 1 9244 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_P_BUSY_SHIFT 31 9245 9246 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: reserved0 [30:18] */ 9247 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_P_RESERVED0_MASK 0x7ffc0000 9248 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_P_RESERVED0_ALIGN 0 9249 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_P_RESERVED0_BITS 13 9250 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_P_RESERVED0_SHIFT 18 9251 9252 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: ovr_force [17:17] */ 9253 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_P_OVR_FORCE_MASK 0x00020000 9254 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_P_OVR_FORCE_ALIGN 0 9255 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_P_OVR_FORCE_BITS 1 9256 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_P_OVR_FORCE_SHIFT 17 9257 9258 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: ovr_en [16:16] */ 9259 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_P_OVR_EN_MASK 0x00010000 9260 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_P_OVR_EN_ALIGN 0 9261 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_P_OVR_EN_BITS 1 9262 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_P_OVR_EN_SHIFT 16 9263 9264 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: reserved1 [15:09] */ 9265 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_P_RESERVED1_MASK 0x0000fe00 9266 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_P_RESERVED1_ALIGN 0 9267 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_P_RESERVED1_BITS 7 9268 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_P_RESERVED1_SHIFT 9 9269 9270 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: byte_sel [08:08] */ 9271 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_P_BYTE_SEL_MASK 0x00000100 9272 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_P_BYTE_SEL_ALIGN 0 9273 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_P_BYTE_SEL_BITS 1 9274 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_P_BYTE_SEL_SHIFT 8 9275 9276 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: reserved2 [07:06] */ 9277 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_P_RESERVED2_MASK 0x000000c0 9278 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_P_RESERVED2_ALIGN 0 9279 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_P_RESERVED2_BITS 2 9280 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_P_RESERVED2_SHIFT 6 9281 9282 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT7_R_P :: ovr_step [05:00] */ 9283 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_P_OVR_STEP_MASK 0x0000003f 9284 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_P_OVR_STEP_ALIGN 0 9285 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_P_OVR_STEP_BITS 6 9286 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_P_OVR_STEP_SHIFT 0 9287 9288 9289 /**************************************************************************** 9290 * DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT7_R_N 9291 */ 9292 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: busy [31:31] */ 9293 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_N_BUSY_MASK 0x80000000 9294 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_N_BUSY_ALIGN 0 9295 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_N_BUSY_BITS 1 9296 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_N_BUSY_SHIFT 31 9297 9298 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: reserved0 [30:18] */ 9299 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_N_RESERVED0_MASK 0x7ffc0000 9300 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_N_RESERVED0_ALIGN 0 9301 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_N_RESERVED0_BITS 13 9302 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_N_RESERVED0_SHIFT 18 9303 9304 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: ovr_force [17:17] */ 9305 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_N_OVR_FORCE_MASK 0x00020000 9306 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_N_OVR_FORCE_ALIGN 0 9307 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_N_OVR_FORCE_BITS 1 9308 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_N_OVR_FORCE_SHIFT 17 9309 9310 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: ovr_en [16:16] */ 9311 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_N_OVR_EN_MASK 0x00010000 9312 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_N_OVR_EN_ALIGN 0 9313 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_N_OVR_EN_BITS 1 9314 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_N_OVR_EN_SHIFT 16 9315 9316 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: reserved1 [15:09] */ 9317 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_N_RESERVED1_MASK 0x0000fe00 9318 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_N_RESERVED1_ALIGN 0 9319 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_N_RESERVED1_BITS 7 9320 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_N_RESERVED1_SHIFT 9 9321 9322 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: byte_sel [08:08] */ 9323 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_N_BYTE_SEL_MASK 0x00000100 9324 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_N_BYTE_SEL_ALIGN 0 9325 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_N_BYTE_SEL_BITS 1 9326 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_N_BYTE_SEL_SHIFT 8 9327 9328 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: reserved2 [07:06] */ 9329 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_N_RESERVED2_MASK 0x000000c0 9330 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_N_RESERVED2_ALIGN 0 9331 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_N_RESERVED2_BITS 2 9332 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_N_RESERVED2_SHIFT 6 9333 9334 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT7_R_N :: ovr_step [05:00] */ 9335 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_N_OVR_STEP_MASK 0x0000003f 9336 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_N_OVR_STEP_ALIGN 0 9337 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_N_OVR_STEP_BITS 6 9338 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_N_OVR_STEP_SHIFT 0 9339 9340 9341 /**************************************************************************** 9342 * DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT_RD_EN 9343 */ 9344 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: busy [31:31] */ 9345 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT_RD_EN_BUSY_MASK 0x80000000 9346 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT_RD_EN_BUSY_ALIGN 0 9347 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT_RD_EN_BUSY_BITS 1 9348 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT_RD_EN_BUSY_SHIFT 31 9349 9350 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: reserved0 [30:18] */ 9351 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT_RD_EN_RESERVED0_MASK 0x7ffc0000 9352 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT_RD_EN_RESERVED0_ALIGN 0 9353 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT_RD_EN_RESERVED0_BITS 13 9354 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT_RD_EN_RESERVED0_SHIFT 18 9355 9356 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: ovr_force [17:17] */ 9357 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT_RD_EN_OVR_FORCE_MASK 0x00020000 9358 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT_RD_EN_OVR_FORCE_ALIGN 0 9359 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT_RD_EN_OVR_FORCE_BITS 1 9360 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT_RD_EN_OVR_FORCE_SHIFT 17 9361 9362 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: ovr_en [16:16] */ 9363 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT_RD_EN_OVR_EN_MASK 0x00010000 9364 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT_RD_EN_OVR_EN_ALIGN 0 9365 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT_RD_EN_OVR_EN_BITS 1 9366 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT_RD_EN_OVR_EN_SHIFT 16 9367 9368 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: reserved1 [15:09] */ 9369 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT_RD_EN_RESERVED1_MASK 0x0000fe00 9370 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT_RD_EN_RESERVED1_ALIGN 0 9371 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT_RD_EN_RESERVED1_BITS 7 9372 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT_RD_EN_RESERVED1_SHIFT 9 9373 9374 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: byte_sel [08:08] */ 9375 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT_RD_EN_BYTE_SEL_MASK 0x00000100 9376 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT_RD_EN_BYTE_SEL_ALIGN 0 9377 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT_RD_EN_BYTE_SEL_BITS 1 9378 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT_RD_EN_BYTE_SEL_SHIFT 8 9379 9380 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: reserved2 [07:06] */ 9381 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT_RD_EN_RESERVED2_MASK 0x000000c0 9382 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT_RD_EN_RESERVED2_ALIGN 0 9383 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT_RD_EN_RESERVED2_BITS 2 9384 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT_RD_EN_RESERVED2_SHIFT 6 9385 9386 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE0_BIT_RD_EN :: ovr_step [05:00] */ 9387 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT_RD_EN_OVR_STEP_MASK 0x0000003f 9388 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT_RD_EN_OVR_STEP_ALIGN 0 9389 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT_RD_EN_OVR_STEP_BITS 6 9390 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT_RD_EN_OVR_STEP_SHIFT 0 9391 9392 9393 /**************************************************************************** 9394 * DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_W 9395 */ 9396 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_W :: busy [31:31] */ 9397 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_W_BUSY_MASK 0x80000000 9398 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_W_BUSY_ALIGN 0 9399 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_W_BUSY_BITS 1 9400 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_W_BUSY_SHIFT 31 9401 9402 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_W :: reserved0 [30:18] */ 9403 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_W_RESERVED0_MASK 0x7ffc0000 9404 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_W_RESERVED0_ALIGN 0 9405 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_W_RESERVED0_BITS 13 9406 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_W_RESERVED0_SHIFT 18 9407 9408 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_W :: ovr_force [17:17] */ 9409 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_W_OVR_FORCE_MASK 0x00020000 9410 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_W_OVR_FORCE_ALIGN 0 9411 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_W_OVR_FORCE_BITS 1 9412 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_W_OVR_FORCE_SHIFT 17 9413 9414 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_W :: ovr_en [16:16] */ 9415 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_W_OVR_EN_MASK 0x00010000 9416 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_W_OVR_EN_ALIGN 0 9417 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_W_OVR_EN_BITS 1 9418 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_W_OVR_EN_SHIFT 16 9419 9420 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_W :: reserved1 [15:09] */ 9421 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_W_RESERVED1_MASK 0x0000fe00 9422 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_W_RESERVED1_ALIGN 0 9423 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_W_RESERVED1_BITS 7 9424 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_W_RESERVED1_SHIFT 9 9425 9426 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_W :: byte_sel [08:08] */ 9427 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_W_BYTE_SEL_MASK 0x00000100 9428 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_W_BYTE_SEL_ALIGN 0 9429 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_W_BYTE_SEL_BITS 1 9430 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_W_BYTE_SEL_SHIFT 8 9431 9432 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_W :: reserved2 [07:06] */ 9433 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_W_RESERVED2_MASK 0x000000c0 9434 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_W_RESERVED2_ALIGN 0 9435 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_W_RESERVED2_BITS 2 9436 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_W_RESERVED2_SHIFT 6 9437 9438 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_W :: ovr_step [05:00] */ 9439 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_W_OVR_STEP_MASK 0x0000003f 9440 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_W_OVR_STEP_ALIGN 0 9441 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_W_OVR_STEP_BITS 6 9442 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_W_OVR_STEP_SHIFT 0 9443 9444 9445 /**************************************************************************** 9446 * DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_R_P 9447 */ 9448 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_R_P :: busy [31:31] */ 9449 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_P_BUSY_MASK 0x80000000 9450 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_P_BUSY_ALIGN 0 9451 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_P_BUSY_BITS 1 9452 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_P_BUSY_SHIFT 31 9453 9454 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_R_P :: reserved0 [30:18] */ 9455 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_P_RESERVED0_MASK 0x7ffc0000 9456 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_P_RESERVED0_ALIGN 0 9457 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_P_RESERVED0_BITS 13 9458 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_P_RESERVED0_SHIFT 18 9459 9460 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_R_P :: ovr_force [17:17] */ 9461 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_P_OVR_FORCE_MASK 0x00020000 9462 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_P_OVR_FORCE_ALIGN 0 9463 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_P_OVR_FORCE_BITS 1 9464 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_P_OVR_FORCE_SHIFT 17 9465 9466 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_R_P :: ovr_en [16:16] */ 9467 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_P_OVR_EN_MASK 0x00010000 9468 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_P_OVR_EN_ALIGN 0 9469 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_P_OVR_EN_BITS 1 9470 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_P_OVR_EN_SHIFT 16 9471 9472 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_R_P :: reserved1 [15:09] */ 9473 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_P_RESERVED1_MASK 0x0000fe00 9474 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_P_RESERVED1_ALIGN 0 9475 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_P_RESERVED1_BITS 7 9476 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_P_RESERVED1_SHIFT 9 9477 9478 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_R_P :: byte_sel [08:08] */ 9479 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_P_BYTE_SEL_MASK 0x00000100 9480 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_P_BYTE_SEL_ALIGN 0 9481 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_P_BYTE_SEL_BITS 1 9482 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_P_BYTE_SEL_SHIFT 8 9483 9484 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_R_P :: reserved2 [07:06] */ 9485 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_P_RESERVED2_MASK 0x000000c0 9486 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_P_RESERVED2_ALIGN 0 9487 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_P_RESERVED2_BITS 2 9488 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_P_RESERVED2_SHIFT 6 9489 9490 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_R_P :: ovr_step [05:00] */ 9491 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_P_OVR_STEP_MASK 0x0000003f 9492 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_P_OVR_STEP_ALIGN 0 9493 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_P_OVR_STEP_BITS 6 9494 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_P_OVR_STEP_SHIFT 0 9495 9496 9497 /**************************************************************************** 9498 * DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_R_N 9499 */ 9500 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_R_N :: busy [31:31] */ 9501 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_N_BUSY_MASK 0x80000000 9502 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_N_BUSY_ALIGN 0 9503 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_N_BUSY_BITS 1 9504 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_N_BUSY_SHIFT 31 9505 9506 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_R_N :: reserved0 [30:18] */ 9507 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_N_RESERVED0_MASK 0x7ffc0000 9508 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_N_RESERVED0_ALIGN 0 9509 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_N_RESERVED0_BITS 13 9510 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_N_RESERVED0_SHIFT 18 9511 9512 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_R_N :: ovr_force [17:17] */ 9513 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_N_OVR_FORCE_MASK 0x00020000 9514 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_N_OVR_FORCE_ALIGN 0 9515 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_N_OVR_FORCE_BITS 1 9516 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_N_OVR_FORCE_SHIFT 17 9517 9518 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_R_N :: ovr_en [16:16] */ 9519 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_N_OVR_EN_MASK 0x00010000 9520 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_N_OVR_EN_ALIGN 0 9521 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_N_OVR_EN_BITS 1 9522 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_N_OVR_EN_SHIFT 16 9523 9524 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_R_N :: reserved1 [15:09] */ 9525 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_N_RESERVED1_MASK 0x0000fe00 9526 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_N_RESERVED1_ALIGN 0 9527 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_N_RESERVED1_BITS 7 9528 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_N_RESERVED1_SHIFT 9 9529 9530 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_R_N :: byte_sel [08:08] */ 9531 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_N_BYTE_SEL_MASK 0x00000100 9532 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_N_BYTE_SEL_ALIGN 0 9533 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_N_BYTE_SEL_BITS 1 9534 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_N_BYTE_SEL_SHIFT 8 9535 9536 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_R_N :: reserved2 [07:06] */ 9537 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_N_RESERVED2_MASK 0x000000c0 9538 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_N_RESERVED2_ALIGN 0 9539 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_N_RESERVED2_BITS 2 9540 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_N_RESERVED2_SHIFT 6 9541 9542 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_R_N :: ovr_step [05:00] */ 9543 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_N_OVR_STEP_MASK 0x0000003f 9544 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_N_OVR_STEP_ALIGN 0 9545 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_N_OVR_STEP_BITS 6 9546 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_N_OVR_STEP_SHIFT 0 9547 9548 9549 /**************************************************************************** 9550 * DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT0_W 9551 */ 9552 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT0_W :: busy [31:31] */ 9553 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_W_BUSY_MASK 0x80000000 9554 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_W_BUSY_ALIGN 0 9555 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_W_BUSY_BITS 1 9556 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_W_BUSY_SHIFT 31 9557 9558 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT0_W :: reserved0 [30:18] */ 9559 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_W_RESERVED0_MASK 0x7ffc0000 9560 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_W_RESERVED0_ALIGN 0 9561 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_W_RESERVED0_BITS 13 9562 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_W_RESERVED0_SHIFT 18 9563 9564 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT0_W :: ovr_force [17:17] */ 9565 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_W_OVR_FORCE_MASK 0x00020000 9566 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_W_OVR_FORCE_ALIGN 0 9567 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_W_OVR_FORCE_BITS 1 9568 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_W_OVR_FORCE_SHIFT 17 9569 9570 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT0_W :: ovr_en [16:16] */ 9571 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_W_OVR_EN_MASK 0x00010000 9572 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_W_OVR_EN_ALIGN 0 9573 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_W_OVR_EN_BITS 1 9574 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_W_OVR_EN_SHIFT 16 9575 9576 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT0_W :: reserved1 [15:09] */ 9577 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_W_RESERVED1_MASK 0x0000fe00 9578 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_W_RESERVED1_ALIGN 0 9579 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_W_RESERVED1_BITS 7 9580 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_W_RESERVED1_SHIFT 9 9581 9582 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT0_W :: byte_sel [08:08] */ 9583 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_W_BYTE_SEL_MASK 0x00000100 9584 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_W_BYTE_SEL_ALIGN 0 9585 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_W_BYTE_SEL_BITS 1 9586 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_W_BYTE_SEL_SHIFT 8 9587 9588 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT0_W :: reserved2 [07:06] */ 9589 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_W_RESERVED2_MASK 0x000000c0 9590 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_W_RESERVED2_ALIGN 0 9591 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_W_RESERVED2_BITS 2 9592 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_W_RESERVED2_SHIFT 6 9593 9594 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT0_W :: ovr_step [05:00] */ 9595 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_W_OVR_STEP_MASK 0x0000003f 9596 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_W_OVR_STEP_ALIGN 0 9597 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_W_OVR_STEP_BITS 6 9598 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_W_OVR_STEP_SHIFT 0 9599 9600 9601 /**************************************************************************** 9602 * DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT1_W 9603 */ 9604 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT1_W :: busy [31:31] */ 9605 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_W_BUSY_MASK 0x80000000 9606 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_W_BUSY_ALIGN 0 9607 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_W_BUSY_BITS 1 9608 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_W_BUSY_SHIFT 31 9609 9610 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT1_W :: reserved0 [30:18] */ 9611 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_W_RESERVED0_MASK 0x7ffc0000 9612 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_W_RESERVED0_ALIGN 0 9613 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_W_RESERVED0_BITS 13 9614 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_W_RESERVED0_SHIFT 18 9615 9616 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT1_W :: ovr_force [17:17] */ 9617 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_W_OVR_FORCE_MASK 0x00020000 9618 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_W_OVR_FORCE_ALIGN 0 9619 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_W_OVR_FORCE_BITS 1 9620 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_W_OVR_FORCE_SHIFT 17 9621 9622 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT1_W :: ovr_en [16:16] */ 9623 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_W_OVR_EN_MASK 0x00010000 9624 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_W_OVR_EN_ALIGN 0 9625 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_W_OVR_EN_BITS 1 9626 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_W_OVR_EN_SHIFT 16 9627 9628 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT1_W :: reserved1 [15:09] */ 9629 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_W_RESERVED1_MASK 0x0000fe00 9630 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_W_RESERVED1_ALIGN 0 9631 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_W_RESERVED1_BITS 7 9632 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_W_RESERVED1_SHIFT 9 9633 9634 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT1_W :: byte_sel [08:08] */ 9635 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_W_BYTE_SEL_MASK 0x00000100 9636 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_W_BYTE_SEL_ALIGN 0 9637 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_W_BYTE_SEL_BITS 1 9638 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_W_BYTE_SEL_SHIFT 8 9639 9640 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT1_W :: reserved2 [07:06] */ 9641 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_W_RESERVED2_MASK 0x000000c0 9642 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_W_RESERVED2_ALIGN 0 9643 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_W_RESERVED2_BITS 2 9644 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_W_RESERVED2_SHIFT 6 9645 9646 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT1_W :: ovr_step [05:00] */ 9647 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_W_OVR_STEP_MASK 0x0000003f 9648 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_W_OVR_STEP_ALIGN 0 9649 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_W_OVR_STEP_BITS 6 9650 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_W_OVR_STEP_SHIFT 0 9651 9652 9653 /**************************************************************************** 9654 * DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT2_W 9655 */ 9656 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT2_W :: busy [31:31] */ 9657 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_W_BUSY_MASK 0x80000000 9658 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_W_BUSY_ALIGN 0 9659 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_W_BUSY_BITS 1 9660 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_W_BUSY_SHIFT 31 9661 9662 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT2_W :: reserved0 [30:18] */ 9663 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_W_RESERVED0_MASK 0x7ffc0000 9664 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_W_RESERVED0_ALIGN 0 9665 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_W_RESERVED0_BITS 13 9666 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_W_RESERVED0_SHIFT 18 9667 9668 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT2_W :: ovr_force [17:17] */ 9669 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_W_OVR_FORCE_MASK 0x00020000 9670 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_W_OVR_FORCE_ALIGN 0 9671 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_W_OVR_FORCE_BITS 1 9672 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_W_OVR_FORCE_SHIFT 17 9673 9674 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT2_W :: ovr_en [16:16] */ 9675 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_W_OVR_EN_MASK 0x00010000 9676 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_W_OVR_EN_ALIGN 0 9677 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_W_OVR_EN_BITS 1 9678 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_W_OVR_EN_SHIFT 16 9679 9680 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT2_W :: reserved1 [15:09] */ 9681 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_W_RESERVED1_MASK 0x0000fe00 9682 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_W_RESERVED1_ALIGN 0 9683 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_W_RESERVED1_BITS 7 9684 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_W_RESERVED1_SHIFT 9 9685 9686 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT2_W :: byte_sel [08:08] */ 9687 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_W_BYTE_SEL_MASK 0x00000100 9688 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_W_BYTE_SEL_ALIGN 0 9689 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_W_BYTE_SEL_BITS 1 9690 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_W_BYTE_SEL_SHIFT 8 9691 9692 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT2_W :: reserved2 [07:06] */ 9693 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_W_RESERVED2_MASK 0x000000c0 9694 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_W_RESERVED2_ALIGN 0 9695 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_W_RESERVED2_BITS 2 9696 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_W_RESERVED2_SHIFT 6 9697 9698 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT2_W :: ovr_step [05:00] */ 9699 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_W_OVR_STEP_MASK 0x0000003f 9700 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_W_OVR_STEP_ALIGN 0 9701 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_W_OVR_STEP_BITS 6 9702 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_W_OVR_STEP_SHIFT 0 9703 9704 9705 /**************************************************************************** 9706 * DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT3_W 9707 */ 9708 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT3_W :: busy [31:31] */ 9709 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_W_BUSY_MASK 0x80000000 9710 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_W_BUSY_ALIGN 0 9711 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_W_BUSY_BITS 1 9712 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_W_BUSY_SHIFT 31 9713 9714 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT3_W :: reserved0 [30:18] */ 9715 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_W_RESERVED0_MASK 0x7ffc0000 9716 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_W_RESERVED0_ALIGN 0 9717 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_W_RESERVED0_BITS 13 9718 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_W_RESERVED0_SHIFT 18 9719 9720 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT3_W :: ovr_force [17:17] */ 9721 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_W_OVR_FORCE_MASK 0x00020000 9722 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_W_OVR_FORCE_ALIGN 0 9723 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_W_OVR_FORCE_BITS 1 9724 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_W_OVR_FORCE_SHIFT 17 9725 9726 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT3_W :: ovr_en [16:16] */ 9727 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_W_OVR_EN_MASK 0x00010000 9728 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_W_OVR_EN_ALIGN 0 9729 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_W_OVR_EN_BITS 1 9730 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_W_OVR_EN_SHIFT 16 9731 9732 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT3_W :: reserved1 [15:09] */ 9733 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_W_RESERVED1_MASK 0x0000fe00 9734 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_W_RESERVED1_ALIGN 0 9735 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_W_RESERVED1_BITS 7 9736 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_W_RESERVED1_SHIFT 9 9737 9738 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT3_W :: byte_sel [08:08] */ 9739 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_W_BYTE_SEL_MASK 0x00000100 9740 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_W_BYTE_SEL_ALIGN 0 9741 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_W_BYTE_SEL_BITS 1 9742 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_W_BYTE_SEL_SHIFT 8 9743 9744 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT3_W :: reserved2 [07:06] */ 9745 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_W_RESERVED2_MASK 0x000000c0 9746 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_W_RESERVED2_ALIGN 0 9747 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_W_RESERVED2_BITS 2 9748 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_W_RESERVED2_SHIFT 6 9749 9750 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT3_W :: ovr_step [05:00] */ 9751 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_W_OVR_STEP_MASK 0x0000003f 9752 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_W_OVR_STEP_ALIGN 0 9753 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_W_OVR_STEP_BITS 6 9754 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_W_OVR_STEP_SHIFT 0 9755 9756 9757 /**************************************************************************** 9758 * DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT4_W 9759 */ 9760 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT4_W :: busy [31:31] */ 9761 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_W_BUSY_MASK 0x80000000 9762 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_W_BUSY_ALIGN 0 9763 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_W_BUSY_BITS 1 9764 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_W_BUSY_SHIFT 31 9765 9766 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT4_W :: reserved0 [30:18] */ 9767 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_W_RESERVED0_MASK 0x7ffc0000 9768 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_W_RESERVED0_ALIGN 0 9769 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_W_RESERVED0_BITS 13 9770 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_W_RESERVED0_SHIFT 18 9771 9772 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT4_W :: ovr_force [17:17] */ 9773 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_W_OVR_FORCE_MASK 0x00020000 9774 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_W_OVR_FORCE_ALIGN 0 9775 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_W_OVR_FORCE_BITS 1 9776 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_W_OVR_FORCE_SHIFT 17 9777 9778 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT4_W :: ovr_en [16:16] */ 9779 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_W_OVR_EN_MASK 0x00010000 9780 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_W_OVR_EN_ALIGN 0 9781 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_W_OVR_EN_BITS 1 9782 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_W_OVR_EN_SHIFT 16 9783 9784 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT4_W :: reserved1 [15:09] */ 9785 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_W_RESERVED1_MASK 0x0000fe00 9786 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_W_RESERVED1_ALIGN 0 9787 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_W_RESERVED1_BITS 7 9788 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_W_RESERVED1_SHIFT 9 9789 9790 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT4_W :: byte_sel [08:08] */ 9791 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_W_BYTE_SEL_MASK 0x00000100 9792 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_W_BYTE_SEL_ALIGN 0 9793 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_W_BYTE_SEL_BITS 1 9794 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_W_BYTE_SEL_SHIFT 8 9795 9796 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT4_W :: reserved2 [07:06] */ 9797 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_W_RESERVED2_MASK 0x000000c0 9798 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_W_RESERVED2_ALIGN 0 9799 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_W_RESERVED2_BITS 2 9800 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_W_RESERVED2_SHIFT 6 9801 9802 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT4_W :: ovr_step [05:00] */ 9803 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_W_OVR_STEP_MASK 0x0000003f 9804 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_W_OVR_STEP_ALIGN 0 9805 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_W_OVR_STEP_BITS 6 9806 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_W_OVR_STEP_SHIFT 0 9807 9808 9809 /**************************************************************************** 9810 * DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT5_W 9811 */ 9812 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT5_W :: busy [31:31] */ 9813 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_W_BUSY_MASK 0x80000000 9814 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_W_BUSY_ALIGN 0 9815 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_W_BUSY_BITS 1 9816 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_W_BUSY_SHIFT 31 9817 9818 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT5_W :: reserved0 [30:18] */ 9819 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_W_RESERVED0_MASK 0x7ffc0000 9820 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_W_RESERVED0_ALIGN 0 9821 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_W_RESERVED0_BITS 13 9822 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_W_RESERVED0_SHIFT 18 9823 9824 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT5_W :: ovr_force [17:17] */ 9825 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_W_OVR_FORCE_MASK 0x00020000 9826 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_W_OVR_FORCE_ALIGN 0 9827 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_W_OVR_FORCE_BITS 1 9828 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_W_OVR_FORCE_SHIFT 17 9829 9830 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT5_W :: ovr_en [16:16] */ 9831 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_W_OVR_EN_MASK 0x00010000 9832 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_W_OVR_EN_ALIGN 0 9833 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_W_OVR_EN_BITS 1 9834 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_W_OVR_EN_SHIFT 16 9835 9836 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT5_W :: reserved1 [15:09] */ 9837 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_W_RESERVED1_MASK 0x0000fe00 9838 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_W_RESERVED1_ALIGN 0 9839 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_W_RESERVED1_BITS 7 9840 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_W_RESERVED1_SHIFT 9 9841 9842 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT5_W :: byte_sel [08:08] */ 9843 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_W_BYTE_SEL_MASK 0x00000100 9844 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_W_BYTE_SEL_ALIGN 0 9845 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_W_BYTE_SEL_BITS 1 9846 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_W_BYTE_SEL_SHIFT 8 9847 9848 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT5_W :: reserved2 [07:06] */ 9849 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_W_RESERVED2_MASK 0x000000c0 9850 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_W_RESERVED2_ALIGN 0 9851 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_W_RESERVED2_BITS 2 9852 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_W_RESERVED2_SHIFT 6 9853 9854 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT5_W :: ovr_step [05:00] */ 9855 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_W_OVR_STEP_MASK 0x0000003f 9856 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_W_OVR_STEP_ALIGN 0 9857 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_W_OVR_STEP_BITS 6 9858 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_W_OVR_STEP_SHIFT 0 9859 9860 9861 /**************************************************************************** 9862 * DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT6_W 9863 */ 9864 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT6_W :: busy [31:31] */ 9865 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_W_BUSY_MASK 0x80000000 9866 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_W_BUSY_ALIGN 0 9867 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_W_BUSY_BITS 1 9868 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_W_BUSY_SHIFT 31 9869 9870 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT6_W :: reserved0 [30:18] */ 9871 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_W_RESERVED0_MASK 0x7ffc0000 9872 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_W_RESERVED0_ALIGN 0 9873 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_W_RESERVED0_BITS 13 9874 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_W_RESERVED0_SHIFT 18 9875 9876 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT6_W :: ovr_force [17:17] */ 9877 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_W_OVR_FORCE_MASK 0x00020000 9878 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_W_OVR_FORCE_ALIGN 0 9879 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_W_OVR_FORCE_BITS 1 9880 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_W_OVR_FORCE_SHIFT 17 9881 9882 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT6_W :: ovr_en [16:16] */ 9883 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_W_OVR_EN_MASK 0x00010000 9884 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_W_OVR_EN_ALIGN 0 9885 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_W_OVR_EN_BITS 1 9886 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_W_OVR_EN_SHIFT 16 9887 9888 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT6_W :: reserved1 [15:09] */ 9889 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_W_RESERVED1_MASK 0x0000fe00 9890 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_W_RESERVED1_ALIGN 0 9891 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_W_RESERVED1_BITS 7 9892 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_W_RESERVED1_SHIFT 9 9893 9894 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT6_W :: byte_sel [08:08] */ 9895 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_W_BYTE_SEL_MASK 0x00000100 9896 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_W_BYTE_SEL_ALIGN 0 9897 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_W_BYTE_SEL_BITS 1 9898 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_W_BYTE_SEL_SHIFT 8 9899 9900 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT6_W :: reserved2 [07:06] */ 9901 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_W_RESERVED2_MASK 0x000000c0 9902 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_W_RESERVED2_ALIGN 0 9903 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_W_RESERVED2_BITS 2 9904 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_W_RESERVED2_SHIFT 6 9905 9906 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT6_W :: ovr_step [05:00] */ 9907 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_W_OVR_STEP_MASK 0x0000003f 9908 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_W_OVR_STEP_ALIGN 0 9909 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_W_OVR_STEP_BITS 6 9910 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_W_OVR_STEP_SHIFT 0 9911 9912 9913 /**************************************************************************** 9914 * DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT7_W 9915 */ 9916 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT7_W :: busy [31:31] */ 9917 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_W_BUSY_MASK 0x80000000 9918 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_W_BUSY_ALIGN 0 9919 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_W_BUSY_BITS 1 9920 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_W_BUSY_SHIFT 31 9921 9922 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT7_W :: reserved0 [30:18] */ 9923 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_W_RESERVED0_MASK 0x7ffc0000 9924 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_W_RESERVED0_ALIGN 0 9925 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_W_RESERVED0_BITS 13 9926 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_W_RESERVED0_SHIFT 18 9927 9928 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT7_W :: ovr_force [17:17] */ 9929 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_W_OVR_FORCE_MASK 0x00020000 9930 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_W_OVR_FORCE_ALIGN 0 9931 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_W_OVR_FORCE_BITS 1 9932 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_W_OVR_FORCE_SHIFT 17 9933 9934 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT7_W :: ovr_en [16:16] */ 9935 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_W_OVR_EN_MASK 0x00010000 9936 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_W_OVR_EN_ALIGN 0 9937 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_W_OVR_EN_BITS 1 9938 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_W_OVR_EN_SHIFT 16 9939 9940 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT7_W :: reserved1 [15:09] */ 9941 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_W_RESERVED1_MASK 0x0000fe00 9942 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_W_RESERVED1_ALIGN 0 9943 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_W_RESERVED1_BITS 7 9944 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_W_RESERVED1_SHIFT 9 9945 9946 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT7_W :: byte_sel [08:08] */ 9947 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_W_BYTE_SEL_MASK 0x00000100 9948 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_W_BYTE_SEL_ALIGN 0 9949 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_W_BYTE_SEL_BITS 1 9950 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_W_BYTE_SEL_SHIFT 8 9951 9952 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT7_W :: reserved2 [07:06] */ 9953 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_W_RESERVED2_MASK 0x000000c0 9954 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_W_RESERVED2_ALIGN 0 9955 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_W_RESERVED2_BITS 2 9956 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_W_RESERVED2_SHIFT 6 9957 9958 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT7_W :: ovr_step [05:00] */ 9959 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_W_OVR_STEP_MASK 0x0000003f 9960 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_W_OVR_STEP_ALIGN 0 9961 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_W_OVR_STEP_BITS 6 9962 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_W_OVR_STEP_SHIFT 0 9963 9964 9965 /**************************************************************************** 9966 * DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_DM_W 9967 */ 9968 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_DM_W :: busy [31:31] */ 9969 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_DM_W_BUSY_MASK 0x80000000 9970 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_DM_W_BUSY_ALIGN 0 9971 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_DM_W_BUSY_BITS 1 9972 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_DM_W_BUSY_SHIFT 31 9973 9974 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_DM_W :: reserved0 [30:18] */ 9975 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_DM_W_RESERVED0_MASK 0x7ffc0000 9976 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_DM_W_RESERVED0_ALIGN 0 9977 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_DM_W_RESERVED0_BITS 13 9978 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_DM_W_RESERVED0_SHIFT 18 9979 9980 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_DM_W :: ovr_force [17:17] */ 9981 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_DM_W_OVR_FORCE_MASK 0x00020000 9982 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_DM_W_OVR_FORCE_ALIGN 0 9983 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_DM_W_OVR_FORCE_BITS 1 9984 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_DM_W_OVR_FORCE_SHIFT 17 9985 9986 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_DM_W :: ovr_en [16:16] */ 9987 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_DM_W_OVR_EN_MASK 0x00010000 9988 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_DM_W_OVR_EN_ALIGN 0 9989 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_DM_W_OVR_EN_BITS 1 9990 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_DM_W_OVR_EN_SHIFT 16 9991 9992 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_DM_W :: reserved1 [15:09] */ 9993 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_DM_W_RESERVED1_MASK 0x0000fe00 9994 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_DM_W_RESERVED1_ALIGN 0 9995 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_DM_W_RESERVED1_BITS 7 9996 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_DM_W_RESERVED1_SHIFT 9 9997 9998 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_DM_W :: byte_sel [08:08] */ 9999 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_DM_W_BYTE_SEL_MASK 0x00000100 10000 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_DM_W_BYTE_SEL_ALIGN 0 10001 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_DM_W_BYTE_SEL_BITS 1 10002 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_DM_W_BYTE_SEL_SHIFT 8 10003 10004 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_DM_W :: reserved2 [07:06] */ 10005 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_DM_W_RESERVED2_MASK 0x000000c0 10006 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_DM_W_RESERVED2_ALIGN 0 10007 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_DM_W_RESERVED2_BITS 2 10008 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_DM_W_RESERVED2_SHIFT 6 10009 10010 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_DM_W :: ovr_step [05:00] */ 10011 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_DM_W_OVR_STEP_MASK 0x0000003f 10012 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_DM_W_OVR_STEP_ALIGN 0 10013 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_DM_W_OVR_STEP_BITS 6 10014 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_DM_W_OVR_STEP_SHIFT 0 10015 10016 10017 /**************************************************************************** 10018 * DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT0_R_P 10019 */ 10020 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: busy [31:31] */ 10021 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_P_BUSY_MASK 0x80000000 10022 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_P_BUSY_ALIGN 0 10023 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_P_BUSY_BITS 1 10024 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_P_BUSY_SHIFT 31 10025 10026 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: reserved0 [30:18] */ 10027 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_P_RESERVED0_MASK 0x7ffc0000 10028 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_P_RESERVED0_ALIGN 0 10029 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_P_RESERVED0_BITS 13 10030 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_P_RESERVED0_SHIFT 18 10031 10032 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: ovr_force [17:17] */ 10033 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_P_OVR_FORCE_MASK 0x00020000 10034 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_P_OVR_FORCE_ALIGN 0 10035 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_P_OVR_FORCE_BITS 1 10036 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_P_OVR_FORCE_SHIFT 17 10037 10038 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: ovr_en [16:16] */ 10039 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_P_OVR_EN_MASK 0x00010000 10040 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_P_OVR_EN_ALIGN 0 10041 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_P_OVR_EN_BITS 1 10042 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_P_OVR_EN_SHIFT 16 10043 10044 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: reserved1 [15:09] */ 10045 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_P_RESERVED1_MASK 0x0000fe00 10046 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_P_RESERVED1_ALIGN 0 10047 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_P_RESERVED1_BITS 7 10048 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_P_RESERVED1_SHIFT 9 10049 10050 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: byte_sel [08:08] */ 10051 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_P_BYTE_SEL_MASK 0x00000100 10052 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_P_BYTE_SEL_ALIGN 0 10053 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_P_BYTE_SEL_BITS 1 10054 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_P_BYTE_SEL_SHIFT 8 10055 10056 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: reserved2 [07:06] */ 10057 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_P_RESERVED2_MASK 0x000000c0 10058 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_P_RESERVED2_ALIGN 0 10059 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_P_RESERVED2_BITS 2 10060 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_P_RESERVED2_SHIFT 6 10061 10062 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT0_R_P :: ovr_step [05:00] */ 10063 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_P_OVR_STEP_MASK 0x0000003f 10064 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_P_OVR_STEP_ALIGN 0 10065 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_P_OVR_STEP_BITS 6 10066 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_P_OVR_STEP_SHIFT 0 10067 10068 10069 /**************************************************************************** 10070 * DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT0_R_N 10071 */ 10072 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: busy [31:31] */ 10073 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_N_BUSY_MASK 0x80000000 10074 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_N_BUSY_ALIGN 0 10075 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_N_BUSY_BITS 1 10076 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_N_BUSY_SHIFT 31 10077 10078 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: reserved0 [30:18] */ 10079 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_N_RESERVED0_MASK 0x7ffc0000 10080 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_N_RESERVED0_ALIGN 0 10081 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_N_RESERVED0_BITS 13 10082 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_N_RESERVED0_SHIFT 18 10083 10084 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: ovr_force [17:17] */ 10085 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_N_OVR_FORCE_MASK 0x00020000 10086 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_N_OVR_FORCE_ALIGN 0 10087 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_N_OVR_FORCE_BITS 1 10088 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_N_OVR_FORCE_SHIFT 17 10089 10090 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: ovr_en [16:16] */ 10091 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_N_OVR_EN_MASK 0x00010000 10092 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_N_OVR_EN_ALIGN 0 10093 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_N_OVR_EN_BITS 1 10094 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_N_OVR_EN_SHIFT 16 10095 10096 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: reserved1 [15:09] */ 10097 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_N_RESERVED1_MASK 0x0000fe00 10098 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_N_RESERVED1_ALIGN 0 10099 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_N_RESERVED1_BITS 7 10100 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_N_RESERVED1_SHIFT 9 10101 10102 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: byte_sel [08:08] */ 10103 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_N_BYTE_SEL_MASK 0x00000100 10104 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_N_BYTE_SEL_ALIGN 0 10105 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_N_BYTE_SEL_BITS 1 10106 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_N_BYTE_SEL_SHIFT 8 10107 10108 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: reserved2 [07:06] */ 10109 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_N_RESERVED2_MASK 0x000000c0 10110 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_N_RESERVED2_ALIGN 0 10111 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_N_RESERVED2_BITS 2 10112 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_N_RESERVED2_SHIFT 6 10113 10114 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT0_R_N :: ovr_step [05:00] */ 10115 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_N_OVR_STEP_MASK 0x0000003f 10116 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_N_OVR_STEP_ALIGN 0 10117 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_N_OVR_STEP_BITS 6 10118 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_N_OVR_STEP_SHIFT 0 10119 10120 10121 /**************************************************************************** 10122 * DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT1_R_P 10123 */ 10124 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: busy [31:31] */ 10125 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_P_BUSY_MASK 0x80000000 10126 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_P_BUSY_ALIGN 0 10127 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_P_BUSY_BITS 1 10128 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_P_BUSY_SHIFT 31 10129 10130 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: reserved0 [30:18] */ 10131 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_P_RESERVED0_MASK 0x7ffc0000 10132 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_P_RESERVED0_ALIGN 0 10133 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_P_RESERVED0_BITS 13 10134 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_P_RESERVED0_SHIFT 18 10135 10136 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: ovr_force [17:17] */ 10137 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_P_OVR_FORCE_MASK 0x00020000 10138 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_P_OVR_FORCE_ALIGN 0 10139 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_P_OVR_FORCE_BITS 1 10140 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_P_OVR_FORCE_SHIFT 17 10141 10142 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: ovr_en [16:16] */ 10143 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_P_OVR_EN_MASK 0x00010000 10144 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_P_OVR_EN_ALIGN 0 10145 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_P_OVR_EN_BITS 1 10146 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_P_OVR_EN_SHIFT 16 10147 10148 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: reserved1 [15:09] */ 10149 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_P_RESERVED1_MASK 0x0000fe00 10150 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_P_RESERVED1_ALIGN 0 10151 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_P_RESERVED1_BITS 7 10152 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_P_RESERVED1_SHIFT 9 10153 10154 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: byte_sel [08:08] */ 10155 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_P_BYTE_SEL_MASK 0x00000100 10156 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_P_BYTE_SEL_ALIGN 0 10157 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_P_BYTE_SEL_BITS 1 10158 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_P_BYTE_SEL_SHIFT 8 10159 10160 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: reserved2 [07:06] */ 10161 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_P_RESERVED2_MASK 0x000000c0 10162 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_P_RESERVED2_ALIGN 0 10163 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_P_RESERVED2_BITS 2 10164 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_P_RESERVED2_SHIFT 6 10165 10166 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT1_R_P :: ovr_step [05:00] */ 10167 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_P_OVR_STEP_MASK 0x0000003f 10168 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_P_OVR_STEP_ALIGN 0 10169 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_P_OVR_STEP_BITS 6 10170 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_P_OVR_STEP_SHIFT 0 10171 10172 10173 /**************************************************************************** 10174 * DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT1_R_N 10175 */ 10176 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: busy [31:31] */ 10177 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_N_BUSY_MASK 0x80000000 10178 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_N_BUSY_ALIGN 0 10179 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_N_BUSY_BITS 1 10180 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_N_BUSY_SHIFT 31 10181 10182 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: reserved0 [30:18] */ 10183 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_N_RESERVED0_MASK 0x7ffc0000 10184 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_N_RESERVED0_ALIGN 0 10185 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_N_RESERVED0_BITS 13 10186 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_N_RESERVED0_SHIFT 18 10187 10188 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: ovr_force [17:17] */ 10189 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_N_OVR_FORCE_MASK 0x00020000 10190 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_N_OVR_FORCE_ALIGN 0 10191 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_N_OVR_FORCE_BITS 1 10192 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_N_OVR_FORCE_SHIFT 17 10193 10194 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: ovr_en [16:16] */ 10195 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_N_OVR_EN_MASK 0x00010000 10196 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_N_OVR_EN_ALIGN 0 10197 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_N_OVR_EN_BITS 1 10198 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_N_OVR_EN_SHIFT 16 10199 10200 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: reserved1 [15:09] */ 10201 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_N_RESERVED1_MASK 0x0000fe00 10202 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_N_RESERVED1_ALIGN 0 10203 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_N_RESERVED1_BITS 7 10204 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_N_RESERVED1_SHIFT 9 10205 10206 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: byte_sel [08:08] */ 10207 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_N_BYTE_SEL_MASK 0x00000100 10208 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_N_BYTE_SEL_ALIGN 0 10209 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_N_BYTE_SEL_BITS 1 10210 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_N_BYTE_SEL_SHIFT 8 10211 10212 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: reserved2 [07:06] */ 10213 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_N_RESERVED2_MASK 0x000000c0 10214 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_N_RESERVED2_ALIGN 0 10215 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_N_RESERVED2_BITS 2 10216 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_N_RESERVED2_SHIFT 6 10217 10218 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT1_R_N :: ovr_step [05:00] */ 10219 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_N_OVR_STEP_MASK 0x0000003f 10220 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_N_OVR_STEP_ALIGN 0 10221 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_N_OVR_STEP_BITS 6 10222 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_N_OVR_STEP_SHIFT 0 10223 10224 10225 /**************************************************************************** 10226 * DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT2_R_P 10227 */ 10228 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: busy [31:31] */ 10229 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_P_BUSY_MASK 0x80000000 10230 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_P_BUSY_ALIGN 0 10231 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_P_BUSY_BITS 1 10232 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_P_BUSY_SHIFT 31 10233 10234 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: reserved0 [30:18] */ 10235 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_P_RESERVED0_MASK 0x7ffc0000 10236 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_P_RESERVED0_ALIGN 0 10237 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_P_RESERVED0_BITS 13 10238 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_P_RESERVED0_SHIFT 18 10239 10240 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: ovr_force [17:17] */ 10241 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_P_OVR_FORCE_MASK 0x00020000 10242 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_P_OVR_FORCE_ALIGN 0 10243 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_P_OVR_FORCE_BITS 1 10244 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_P_OVR_FORCE_SHIFT 17 10245 10246 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: ovr_en [16:16] */ 10247 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_P_OVR_EN_MASK 0x00010000 10248 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_P_OVR_EN_ALIGN 0 10249 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_P_OVR_EN_BITS 1 10250 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_P_OVR_EN_SHIFT 16 10251 10252 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: reserved1 [15:09] */ 10253 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_P_RESERVED1_MASK 0x0000fe00 10254 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_P_RESERVED1_ALIGN 0 10255 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_P_RESERVED1_BITS 7 10256 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_P_RESERVED1_SHIFT 9 10257 10258 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: byte_sel [08:08] */ 10259 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_P_BYTE_SEL_MASK 0x00000100 10260 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_P_BYTE_SEL_ALIGN 0 10261 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_P_BYTE_SEL_BITS 1 10262 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_P_BYTE_SEL_SHIFT 8 10263 10264 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: reserved2 [07:06] */ 10265 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_P_RESERVED2_MASK 0x000000c0 10266 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_P_RESERVED2_ALIGN 0 10267 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_P_RESERVED2_BITS 2 10268 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_P_RESERVED2_SHIFT 6 10269 10270 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT2_R_P :: ovr_step [05:00] */ 10271 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_P_OVR_STEP_MASK 0x0000003f 10272 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_P_OVR_STEP_ALIGN 0 10273 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_P_OVR_STEP_BITS 6 10274 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_P_OVR_STEP_SHIFT 0 10275 10276 10277 /**************************************************************************** 10278 * DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT2_R_N 10279 */ 10280 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: busy [31:31] */ 10281 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_N_BUSY_MASK 0x80000000 10282 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_N_BUSY_ALIGN 0 10283 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_N_BUSY_BITS 1 10284 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_N_BUSY_SHIFT 31 10285 10286 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: reserved0 [30:18] */ 10287 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_N_RESERVED0_MASK 0x7ffc0000 10288 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_N_RESERVED0_ALIGN 0 10289 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_N_RESERVED0_BITS 13 10290 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_N_RESERVED0_SHIFT 18 10291 10292 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: ovr_force [17:17] */ 10293 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_N_OVR_FORCE_MASK 0x00020000 10294 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_N_OVR_FORCE_ALIGN 0 10295 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_N_OVR_FORCE_BITS 1 10296 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_N_OVR_FORCE_SHIFT 17 10297 10298 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: ovr_en [16:16] */ 10299 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_N_OVR_EN_MASK 0x00010000 10300 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_N_OVR_EN_ALIGN 0 10301 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_N_OVR_EN_BITS 1 10302 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_N_OVR_EN_SHIFT 16 10303 10304 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: reserved1 [15:09] */ 10305 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_N_RESERVED1_MASK 0x0000fe00 10306 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_N_RESERVED1_ALIGN 0 10307 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_N_RESERVED1_BITS 7 10308 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_N_RESERVED1_SHIFT 9 10309 10310 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: byte_sel [08:08] */ 10311 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_N_BYTE_SEL_MASK 0x00000100 10312 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_N_BYTE_SEL_ALIGN 0 10313 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_N_BYTE_SEL_BITS 1 10314 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_N_BYTE_SEL_SHIFT 8 10315 10316 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: reserved2 [07:06] */ 10317 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_N_RESERVED2_MASK 0x000000c0 10318 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_N_RESERVED2_ALIGN 0 10319 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_N_RESERVED2_BITS 2 10320 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_N_RESERVED2_SHIFT 6 10321 10322 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT2_R_N :: ovr_step [05:00] */ 10323 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_N_OVR_STEP_MASK 0x0000003f 10324 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_N_OVR_STEP_ALIGN 0 10325 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_N_OVR_STEP_BITS 6 10326 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_N_OVR_STEP_SHIFT 0 10327 10328 10329 /**************************************************************************** 10330 * DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT3_R_P 10331 */ 10332 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: busy [31:31] */ 10333 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_P_BUSY_MASK 0x80000000 10334 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_P_BUSY_ALIGN 0 10335 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_P_BUSY_BITS 1 10336 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_P_BUSY_SHIFT 31 10337 10338 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: reserved0 [30:18] */ 10339 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_P_RESERVED0_MASK 0x7ffc0000 10340 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_P_RESERVED0_ALIGN 0 10341 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_P_RESERVED0_BITS 13 10342 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_P_RESERVED0_SHIFT 18 10343 10344 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: ovr_force [17:17] */ 10345 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_P_OVR_FORCE_MASK 0x00020000 10346 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_P_OVR_FORCE_ALIGN 0 10347 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_P_OVR_FORCE_BITS 1 10348 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_P_OVR_FORCE_SHIFT 17 10349 10350 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: ovr_en [16:16] */ 10351 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_P_OVR_EN_MASK 0x00010000 10352 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_P_OVR_EN_ALIGN 0 10353 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_P_OVR_EN_BITS 1 10354 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_P_OVR_EN_SHIFT 16 10355 10356 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: reserved1 [15:09] */ 10357 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_P_RESERVED1_MASK 0x0000fe00 10358 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_P_RESERVED1_ALIGN 0 10359 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_P_RESERVED1_BITS 7 10360 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_P_RESERVED1_SHIFT 9 10361 10362 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: byte_sel [08:08] */ 10363 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_P_BYTE_SEL_MASK 0x00000100 10364 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_P_BYTE_SEL_ALIGN 0 10365 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_P_BYTE_SEL_BITS 1 10366 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_P_BYTE_SEL_SHIFT 8 10367 10368 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: reserved2 [07:06] */ 10369 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_P_RESERVED2_MASK 0x000000c0 10370 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_P_RESERVED2_ALIGN 0 10371 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_P_RESERVED2_BITS 2 10372 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_P_RESERVED2_SHIFT 6 10373 10374 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT3_R_P :: ovr_step [05:00] */ 10375 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_P_OVR_STEP_MASK 0x0000003f 10376 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_P_OVR_STEP_ALIGN 0 10377 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_P_OVR_STEP_BITS 6 10378 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_P_OVR_STEP_SHIFT 0 10379 10380 10381 /**************************************************************************** 10382 * DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT3_R_N 10383 */ 10384 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: busy [31:31] */ 10385 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_N_BUSY_MASK 0x80000000 10386 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_N_BUSY_ALIGN 0 10387 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_N_BUSY_BITS 1 10388 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_N_BUSY_SHIFT 31 10389 10390 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: reserved0 [30:18] */ 10391 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_N_RESERVED0_MASK 0x7ffc0000 10392 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_N_RESERVED0_ALIGN 0 10393 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_N_RESERVED0_BITS 13 10394 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_N_RESERVED0_SHIFT 18 10395 10396 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: ovr_force [17:17] */ 10397 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_N_OVR_FORCE_MASK 0x00020000 10398 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_N_OVR_FORCE_ALIGN 0 10399 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_N_OVR_FORCE_BITS 1 10400 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_N_OVR_FORCE_SHIFT 17 10401 10402 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: ovr_en [16:16] */ 10403 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_N_OVR_EN_MASK 0x00010000 10404 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_N_OVR_EN_ALIGN 0 10405 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_N_OVR_EN_BITS 1 10406 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_N_OVR_EN_SHIFT 16 10407 10408 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: reserved1 [15:09] */ 10409 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_N_RESERVED1_MASK 0x0000fe00 10410 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_N_RESERVED1_ALIGN 0 10411 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_N_RESERVED1_BITS 7 10412 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_N_RESERVED1_SHIFT 9 10413 10414 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: byte_sel [08:08] */ 10415 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_N_BYTE_SEL_MASK 0x00000100 10416 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_N_BYTE_SEL_ALIGN 0 10417 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_N_BYTE_SEL_BITS 1 10418 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_N_BYTE_SEL_SHIFT 8 10419 10420 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: reserved2 [07:06] */ 10421 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_N_RESERVED2_MASK 0x000000c0 10422 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_N_RESERVED2_ALIGN 0 10423 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_N_RESERVED2_BITS 2 10424 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_N_RESERVED2_SHIFT 6 10425 10426 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT3_R_N :: ovr_step [05:00] */ 10427 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_N_OVR_STEP_MASK 0x0000003f 10428 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_N_OVR_STEP_ALIGN 0 10429 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_N_OVR_STEP_BITS 6 10430 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_N_OVR_STEP_SHIFT 0 10431 10432 10433 /**************************************************************************** 10434 * DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT4_R_P 10435 */ 10436 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: busy [31:31] */ 10437 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_P_BUSY_MASK 0x80000000 10438 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_P_BUSY_ALIGN 0 10439 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_P_BUSY_BITS 1 10440 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_P_BUSY_SHIFT 31 10441 10442 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: reserved0 [30:18] */ 10443 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_P_RESERVED0_MASK 0x7ffc0000 10444 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_P_RESERVED0_ALIGN 0 10445 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_P_RESERVED0_BITS 13 10446 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_P_RESERVED0_SHIFT 18 10447 10448 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: ovr_force [17:17] */ 10449 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_P_OVR_FORCE_MASK 0x00020000 10450 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_P_OVR_FORCE_ALIGN 0 10451 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_P_OVR_FORCE_BITS 1 10452 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_P_OVR_FORCE_SHIFT 17 10453 10454 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: ovr_en [16:16] */ 10455 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_P_OVR_EN_MASK 0x00010000 10456 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_P_OVR_EN_ALIGN 0 10457 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_P_OVR_EN_BITS 1 10458 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_P_OVR_EN_SHIFT 16 10459 10460 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: reserved1 [15:09] */ 10461 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_P_RESERVED1_MASK 0x0000fe00 10462 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_P_RESERVED1_ALIGN 0 10463 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_P_RESERVED1_BITS 7 10464 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_P_RESERVED1_SHIFT 9 10465 10466 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: byte_sel [08:08] */ 10467 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_P_BYTE_SEL_MASK 0x00000100 10468 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_P_BYTE_SEL_ALIGN 0 10469 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_P_BYTE_SEL_BITS 1 10470 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_P_BYTE_SEL_SHIFT 8 10471 10472 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: reserved2 [07:06] */ 10473 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_P_RESERVED2_MASK 0x000000c0 10474 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_P_RESERVED2_ALIGN 0 10475 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_P_RESERVED2_BITS 2 10476 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_P_RESERVED2_SHIFT 6 10477 10478 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT4_R_P :: ovr_step [05:00] */ 10479 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_P_OVR_STEP_MASK 0x0000003f 10480 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_P_OVR_STEP_ALIGN 0 10481 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_P_OVR_STEP_BITS 6 10482 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_P_OVR_STEP_SHIFT 0 10483 10484 10485 /**************************************************************************** 10486 * DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT4_R_N 10487 */ 10488 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: busy [31:31] */ 10489 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_N_BUSY_MASK 0x80000000 10490 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_N_BUSY_ALIGN 0 10491 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_N_BUSY_BITS 1 10492 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_N_BUSY_SHIFT 31 10493 10494 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: reserved0 [30:18] */ 10495 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_N_RESERVED0_MASK 0x7ffc0000 10496 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_N_RESERVED0_ALIGN 0 10497 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_N_RESERVED0_BITS 13 10498 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_N_RESERVED0_SHIFT 18 10499 10500 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: ovr_force [17:17] */ 10501 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_N_OVR_FORCE_MASK 0x00020000 10502 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_N_OVR_FORCE_ALIGN 0 10503 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_N_OVR_FORCE_BITS 1 10504 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_N_OVR_FORCE_SHIFT 17 10505 10506 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: ovr_en [16:16] */ 10507 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_N_OVR_EN_MASK 0x00010000 10508 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_N_OVR_EN_ALIGN 0 10509 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_N_OVR_EN_BITS 1 10510 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_N_OVR_EN_SHIFT 16 10511 10512 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: reserved1 [15:09] */ 10513 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_N_RESERVED1_MASK 0x0000fe00 10514 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_N_RESERVED1_ALIGN 0 10515 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_N_RESERVED1_BITS 7 10516 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_N_RESERVED1_SHIFT 9 10517 10518 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: byte_sel [08:08] */ 10519 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_N_BYTE_SEL_MASK 0x00000100 10520 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_N_BYTE_SEL_ALIGN 0 10521 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_N_BYTE_SEL_BITS 1 10522 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_N_BYTE_SEL_SHIFT 8 10523 10524 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: reserved2 [07:06] */ 10525 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_N_RESERVED2_MASK 0x000000c0 10526 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_N_RESERVED2_ALIGN 0 10527 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_N_RESERVED2_BITS 2 10528 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_N_RESERVED2_SHIFT 6 10529 10530 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT4_R_N :: ovr_step [05:00] */ 10531 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_N_OVR_STEP_MASK 0x0000003f 10532 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_N_OVR_STEP_ALIGN 0 10533 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_N_OVR_STEP_BITS 6 10534 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_N_OVR_STEP_SHIFT 0 10535 10536 10537 /**************************************************************************** 10538 * DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT5_R_P 10539 */ 10540 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: busy [31:31] */ 10541 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_P_BUSY_MASK 0x80000000 10542 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_P_BUSY_ALIGN 0 10543 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_P_BUSY_BITS 1 10544 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_P_BUSY_SHIFT 31 10545 10546 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: reserved0 [30:18] */ 10547 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_P_RESERVED0_MASK 0x7ffc0000 10548 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_P_RESERVED0_ALIGN 0 10549 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_P_RESERVED0_BITS 13 10550 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_P_RESERVED0_SHIFT 18 10551 10552 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: ovr_force [17:17] */ 10553 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_P_OVR_FORCE_MASK 0x00020000 10554 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_P_OVR_FORCE_ALIGN 0 10555 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_P_OVR_FORCE_BITS 1 10556 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_P_OVR_FORCE_SHIFT 17 10557 10558 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: ovr_en [16:16] */ 10559 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_P_OVR_EN_MASK 0x00010000 10560 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_P_OVR_EN_ALIGN 0 10561 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_P_OVR_EN_BITS 1 10562 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_P_OVR_EN_SHIFT 16 10563 10564 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: reserved1 [15:09] */ 10565 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_P_RESERVED1_MASK 0x0000fe00 10566 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_P_RESERVED1_ALIGN 0 10567 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_P_RESERVED1_BITS 7 10568 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_P_RESERVED1_SHIFT 9 10569 10570 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: byte_sel [08:08] */ 10571 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_P_BYTE_SEL_MASK 0x00000100 10572 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_P_BYTE_SEL_ALIGN 0 10573 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_P_BYTE_SEL_BITS 1 10574 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_P_BYTE_SEL_SHIFT 8 10575 10576 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: reserved2 [07:06] */ 10577 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_P_RESERVED2_MASK 0x000000c0 10578 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_P_RESERVED2_ALIGN 0 10579 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_P_RESERVED2_BITS 2 10580 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_P_RESERVED2_SHIFT 6 10581 10582 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT5_R_P :: ovr_step [05:00] */ 10583 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_P_OVR_STEP_MASK 0x0000003f 10584 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_P_OVR_STEP_ALIGN 0 10585 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_P_OVR_STEP_BITS 6 10586 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_P_OVR_STEP_SHIFT 0 10587 10588 10589 /**************************************************************************** 10590 * DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT5_R_N 10591 */ 10592 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: busy [31:31] */ 10593 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_N_BUSY_MASK 0x80000000 10594 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_N_BUSY_ALIGN 0 10595 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_N_BUSY_BITS 1 10596 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_N_BUSY_SHIFT 31 10597 10598 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: reserved0 [30:18] */ 10599 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_N_RESERVED0_MASK 0x7ffc0000 10600 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_N_RESERVED0_ALIGN 0 10601 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_N_RESERVED0_BITS 13 10602 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_N_RESERVED0_SHIFT 18 10603 10604 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: ovr_force [17:17] */ 10605 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_N_OVR_FORCE_MASK 0x00020000 10606 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_N_OVR_FORCE_ALIGN 0 10607 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_N_OVR_FORCE_BITS 1 10608 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_N_OVR_FORCE_SHIFT 17 10609 10610 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: ovr_en [16:16] */ 10611 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_N_OVR_EN_MASK 0x00010000 10612 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_N_OVR_EN_ALIGN 0 10613 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_N_OVR_EN_BITS 1 10614 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_N_OVR_EN_SHIFT 16 10615 10616 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: reserved1 [15:09] */ 10617 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_N_RESERVED1_MASK 0x0000fe00 10618 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_N_RESERVED1_ALIGN 0 10619 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_N_RESERVED1_BITS 7 10620 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_N_RESERVED1_SHIFT 9 10621 10622 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: byte_sel [08:08] */ 10623 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_N_BYTE_SEL_MASK 0x00000100 10624 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_N_BYTE_SEL_ALIGN 0 10625 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_N_BYTE_SEL_BITS 1 10626 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_N_BYTE_SEL_SHIFT 8 10627 10628 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: reserved2 [07:06] */ 10629 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_N_RESERVED2_MASK 0x000000c0 10630 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_N_RESERVED2_ALIGN 0 10631 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_N_RESERVED2_BITS 2 10632 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_N_RESERVED2_SHIFT 6 10633 10634 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT5_R_N :: ovr_step [05:00] */ 10635 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_N_OVR_STEP_MASK 0x0000003f 10636 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_N_OVR_STEP_ALIGN 0 10637 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_N_OVR_STEP_BITS 6 10638 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_N_OVR_STEP_SHIFT 0 10639 10640 10641 /**************************************************************************** 10642 * DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT6_R_P 10643 */ 10644 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: busy [31:31] */ 10645 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_P_BUSY_MASK 0x80000000 10646 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_P_BUSY_ALIGN 0 10647 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_P_BUSY_BITS 1 10648 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_P_BUSY_SHIFT 31 10649 10650 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: reserved0 [30:18] */ 10651 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_P_RESERVED0_MASK 0x7ffc0000 10652 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_P_RESERVED0_ALIGN 0 10653 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_P_RESERVED0_BITS 13 10654 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_P_RESERVED0_SHIFT 18 10655 10656 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: ovr_force [17:17] */ 10657 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_P_OVR_FORCE_MASK 0x00020000 10658 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_P_OVR_FORCE_ALIGN 0 10659 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_P_OVR_FORCE_BITS 1 10660 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_P_OVR_FORCE_SHIFT 17 10661 10662 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: ovr_en [16:16] */ 10663 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_P_OVR_EN_MASK 0x00010000 10664 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_P_OVR_EN_ALIGN 0 10665 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_P_OVR_EN_BITS 1 10666 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_P_OVR_EN_SHIFT 16 10667 10668 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: reserved1 [15:09] */ 10669 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_P_RESERVED1_MASK 0x0000fe00 10670 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_P_RESERVED1_ALIGN 0 10671 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_P_RESERVED1_BITS 7 10672 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_P_RESERVED1_SHIFT 9 10673 10674 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: byte_sel [08:08] */ 10675 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_P_BYTE_SEL_MASK 0x00000100 10676 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_P_BYTE_SEL_ALIGN 0 10677 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_P_BYTE_SEL_BITS 1 10678 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_P_BYTE_SEL_SHIFT 8 10679 10680 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: reserved2 [07:06] */ 10681 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_P_RESERVED2_MASK 0x000000c0 10682 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_P_RESERVED2_ALIGN 0 10683 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_P_RESERVED2_BITS 2 10684 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_P_RESERVED2_SHIFT 6 10685 10686 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT6_R_P :: ovr_step [05:00] */ 10687 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_P_OVR_STEP_MASK 0x0000003f 10688 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_P_OVR_STEP_ALIGN 0 10689 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_P_OVR_STEP_BITS 6 10690 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_P_OVR_STEP_SHIFT 0 10691 10692 10693 /**************************************************************************** 10694 * DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT6_R_N 10695 */ 10696 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: busy [31:31] */ 10697 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_N_BUSY_MASK 0x80000000 10698 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_N_BUSY_ALIGN 0 10699 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_N_BUSY_BITS 1 10700 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_N_BUSY_SHIFT 31 10701 10702 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: reserved0 [30:18] */ 10703 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_N_RESERVED0_MASK 0x7ffc0000 10704 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_N_RESERVED0_ALIGN 0 10705 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_N_RESERVED0_BITS 13 10706 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_N_RESERVED0_SHIFT 18 10707 10708 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: ovr_force [17:17] */ 10709 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_N_OVR_FORCE_MASK 0x00020000 10710 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_N_OVR_FORCE_ALIGN 0 10711 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_N_OVR_FORCE_BITS 1 10712 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_N_OVR_FORCE_SHIFT 17 10713 10714 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: ovr_en [16:16] */ 10715 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_N_OVR_EN_MASK 0x00010000 10716 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_N_OVR_EN_ALIGN 0 10717 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_N_OVR_EN_BITS 1 10718 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_N_OVR_EN_SHIFT 16 10719 10720 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: reserved1 [15:09] */ 10721 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_N_RESERVED1_MASK 0x0000fe00 10722 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_N_RESERVED1_ALIGN 0 10723 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_N_RESERVED1_BITS 7 10724 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_N_RESERVED1_SHIFT 9 10725 10726 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: byte_sel [08:08] */ 10727 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_N_BYTE_SEL_MASK 0x00000100 10728 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_N_BYTE_SEL_ALIGN 0 10729 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_N_BYTE_SEL_BITS 1 10730 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_N_BYTE_SEL_SHIFT 8 10731 10732 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: reserved2 [07:06] */ 10733 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_N_RESERVED2_MASK 0x000000c0 10734 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_N_RESERVED2_ALIGN 0 10735 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_N_RESERVED2_BITS 2 10736 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_N_RESERVED2_SHIFT 6 10737 10738 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT6_R_N :: ovr_step [05:00] */ 10739 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_N_OVR_STEP_MASK 0x0000003f 10740 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_N_OVR_STEP_ALIGN 0 10741 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_N_OVR_STEP_BITS 6 10742 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_N_OVR_STEP_SHIFT 0 10743 10744 10745 /**************************************************************************** 10746 * DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT7_R_P 10747 */ 10748 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: busy [31:31] */ 10749 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_P_BUSY_MASK 0x80000000 10750 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_P_BUSY_ALIGN 0 10751 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_P_BUSY_BITS 1 10752 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_P_BUSY_SHIFT 31 10753 10754 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: reserved0 [30:18] */ 10755 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_P_RESERVED0_MASK 0x7ffc0000 10756 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_P_RESERVED0_ALIGN 0 10757 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_P_RESERVED0_BITS 13 10758 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_P_RESERVED0_SHIFT 18 10759 10760 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: ovr_force [17:17] */ 10761 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_P_OVR_FORCE_MASK 0x00020000 10762 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_P_OVR_FORCE_ALIGN 0 10763 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_P_OVR_FORCE_BITS 1 10764 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_P_OVR_FORCE_SHIFT 17 10765 10766 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: ovr_en [16:16] */ 10767 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_P_OVR_EN_MASK 0x00010000 10768 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_P_OVR_EN_ALIGN 0 10769 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_P_OVR_EN_BITS 1 10770 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_P_OVR_EN_SHIFT 16 10771 10772 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: reserved1 [15:09] */ 10773 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_P_RESERVED1_MASK 0x0000fe00 10774 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_P_RESERVED1_ALIGN 0 10775 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_P_RESERVED1_BITS 7 10776 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_P_RESERVED1_SHIFT 9 10777 10778 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: byte_sel [08:08] */ 10779 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_P_BYTE_SEL_MASK 0x00000100 10780 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_P_BYTE_SEL_ALIGN 0 10781 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_P_BYTE_SEL_BITS 1 10782 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_P_BYTE_SEL_SHIFT 8 10783 10784 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: reserved2 [07:06] */ 10785 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_P_RESERVED2_MASK 0x000000c0 10786 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_P_RESERVED2_ALIGN 0 10787 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_P_RESERVED2_BITS 2 10788 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_P_RESERVED2_SHIFT 6 10789 10790 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT7_R_P :: ovr_step [05:00] */ 10791 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_P_OVR_STEP_MASK 0x0000003f 10792 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_P_OVR_STEP_ALIGN 0 10793 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_P_OVR_STEP_BITS 6 10794 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_P_OVR_STEP_SHIFT 0 10795 10796 10797 /**************************************************************************** 10798 * DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT7_R_N 10799 */ 10800 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: busy [31:31] */ 10801 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_N_BUSY_MASK 0x80000000 10802 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_N_BUSY_ALIGN 0 10803 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_N_BUSY_BITS 1 10804 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_N_BUSY_SHIFT 31 10805 10806 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: reserved0 [30:18] */ 10807 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_N_RESERVED0_MASK 0x7ffc0000 10808 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_N_RESERVED0_ALIGN 0 10809 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_N_RESERVED0_BITS 13 10810 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_N_RESERVED0_SHIFT 18 10811 10812 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: ovr_force [17:17] */ 10813 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_N_OVR_FORCE_MASK 0x00020000 10814 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_N_OVR_FORCE_ALIGN 0 10815 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_N_OVR_FORCE_BITS 1 10816 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_N_OVR_FORCE_SHIFT 17 10817 10818 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: ovr_en [16:16] */ 10819 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_N_OVR_EN_MASK 0x00010000 10820 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_N_OVR_EN_ALIGN 0 10821 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_N_OVR_EN_BITS 1 10822 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_N_OVR_EN_SHIFT 16 10823 10824 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: reserved1 [15:09] */ 10825 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_N_RESERVED1_MASK 0x0000fe00 10826 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_N_RESERVED1_ALIGN 0 10827 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_N_RESERVED1_BITS 7 10828 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_N_RESERVED1_SHIFT 9 10829 10830 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: byte_sel [08:08] */ 10831 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_N_BYTE_SEL_MASK 0x00000100 10832 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_N_BYTE_SEL_ALIGN 0 10833 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_N_BYTE_SEL_BITS 1 10834 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_N_BYTE_SEL_SHIFT 8 10835 10836 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: reserved2 [07:06] */ 10837 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_N_RESERVED2_MASK 0x000000c0 10838 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_N_RESERVED2_ALIGN 0 10839 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_N_RESERVED2_BITS 2 10840 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_N_RESERVED2_SHIFT 6 10841 10842 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT7_R_N :: ovr_step [05:00] */ 10843 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_N_OVR_STEP_MASK 0x0000003f 10844 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_N_OVR_STEP_ALIGN 0 10845 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_N_OVR_STEP_BITS 6 10846 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_N_OVR_STEP_SHIFT 0 10847 10848 10849 /**************************************************************************** 10850 * DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT_RD_EN 10851 */ 10852 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: busy [31:31] */ 10853 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT_RD_EN_BUSY_MASK 0x80000000 10854 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT_RD_EN_BUSY_ALIGN 0 10855 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT_RD_EN_BUSY_BITS 1 10856 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT_RD_EN_BUSY_SHIFT 31 10857 10858 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: reserved0 [30:18] */ 10859 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT_RD_EN_RESERVED0_MASK 0x7ffc0000 10860 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT_RD_EN_RESERVED0_ALIGN 0 10861 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT_RD_EN_RESERVED0_BITS 13 10862 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT_RD_EN_RESERVED0_SHIFT 18 10863 10864 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: ovr_force [17:17] */ 10865 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT_RD_EN_OVR_FORCE_MASK 0x00020000 10866 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT_RD_EN_OVR_FORCE_ALIGN 0 10867 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT_RD_EN_OVR_FORCE_BITS 1 10868 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT_RD_EN_OVR_FORCE_SHIFT 17 10869 10870 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: ovr_en [16:16] */ 10871 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT_RD_EN_OVR_EN_MASK 0x00010000 10872 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT_RD_EN_OVR_EN_ALIGN 0 10873 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT_RD_EN_OVR_EN_BITS 1 10874 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT_RD_EN_OVR_EN_SHIFT 16 10875 10876 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: reserved1 [15:09] */ 10877 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT_RD_EN_RESERVED1_MASK 0x0000fe00 10878 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT_RD_EN_RESERVED1_ALIGN 0 10879 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT_RD_EN_RESERVED1_BITS 7 10880 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT_RD_EN_RESERVED1_SHIFT 9 10881 10882 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: byte_sel [08:08] */ 10883 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT_RD_EN_BYTE_SEL_MASK 0x00000100 10884 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT_RD_EN_BYTE_SEL_ALIGN 0 10885 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT_RD_EN_BYTE_SEL_BITS 1 10886 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT_RD_EN_BYTE_SEL_SHIFT 8 10887 10888 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: reserved2 [07:06] */ 10889 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT_RD_EN_RESERVED2_MASK 0x000000c0 10890 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT_RD_EN_RESERVED2_ALIGN 0 10891 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT_RD_EN_RESERVED2_BITS 2 10892 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT_RD_EN_RESERVED2_SHIFT 6 10893 10894 /* DDR40_PHY_WORD_LANE_1 :: VDL_OVRIDE_BYTE1_BIT_RD_EN :: ovr_step [05:00] */ 10895 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT_RD_EN_OVR_STEP_MASK 0x0000003f 10896 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT_RD_EN_OVR_STEP_ALIGN 0 10897 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT_RD_EN_OVR_STEP_BITS 6 10898 #define DDR40_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT_RD_EN_OVR_STEP_SHIFT 0 10899 10900 10901 /**************************************************************************** 10902 * DDR40_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE0_R_P 10903 */ 10904 /* DDR40_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE0_R_P :: reserved0 [31:17] */ 10905 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_R_P_RESERVED0_MASK 0xfffe0000 10906 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_R_P_RESERVED0_ALIGN 0 10907 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_R_P_RESERVED0_BITS 15 10908 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_R_P_RESERVED0_SHIFT 17 10909 10910 /* DDR40_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE0_R_P :: ovr_en [16:16] */ 10911 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_R_P_OVR_EN_MASK 0x00010000 10912 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_R_P_OVR_EN_ALIGN 0 10913 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_R_P_OVR_EN_BITS 1 10914 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_R_P_OVR_EN_SHIFT 16 10915 10916 /* DDR40_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE0_R_P :: reserved1 [15:09] */ 10917 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_R_P_RESERVED1_MASK 0x0000fe00 10918 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_R_P_RESERVED1_ALIGN 0 10919 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_R_P_RESERVED1_BITS 7 10920 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_R_P_RESERVED1_SHIFT 9 10921 10922 /* DDR40_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE0_R_P :: byte_sel [08:08] */ 10923 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_R_P_BYTE_SEL_MASK 0x00000100 10924 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_R_P_BYTE_SEL_ALIGN 0 10925 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_R_P_BYTE_SEL_BITS 1 10926 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_R_P_BYTE_SEL_SHIFT 8 10927 10928 /* DDR40_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE0_R_P :: reserved2 [07:06] */ 10929 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_R_P_RESERVED2_MASK 0x000000c0 10930 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_R_P_RESERVED2_ALIGN 0 10931 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_R_P_RESERVED2_BITS 2 10932 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_R_P_RESERVED2_SHIFT 6 10933 10934 /* DDR40_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE0_R_P :: ovr_step [05:00] */ 10935 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_R_P_OVR_STEP_MASK 0x0000003f 10936 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_R_P_OVR_STEP_ALIGN 0 10937 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_R_P_OVR_STEP_BITS 6 10938 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_R_P_OVR_STEP_SHIFT 0 10939 10940 10941 /**************************************************************************** 10942 * DDR40_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE0_R_N 10943 */ 10944 /* DDR40_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE0_R_N :: reserved0 [31:17] */ 10945 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_R_N_RESERVED0_MASK 0xfffe0000 10946 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_R_N_RESERVED0_ALIGN 0 10947 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_R_N_RESERVED0_BITS 15 10948 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_R_N_RESERVED0_SHIFT 17 10949 10950 /* DDR40_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE0_R_N :: ovr_en [16:16] */ 10951 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_R_N_OVR_EN_MASK 0x00010000 10952 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_R_N_OVR_EN_ALIGN 0 10953 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_R_N_OVR_EN_BITS 1 10954 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_R_N_OVR_EN_SHIFT 16 10955 10956 /* DDR40_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE0_R_N :: reserved1 [15:09] */ 10957 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_R_N_RESERVED1_MASK 0x0000fe00 10958 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_R_N_RESERVED1_ALIGN 0 10959 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_R_N_RESERVED1_BITS 7 10960 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_R_N_RESERVED1_SHIFT 9 10961 10962 /* DDR40_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE0_R_N :: byte_sel [08:08] */ 10963 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_R_N_BYTE_SEL_MASK 0x00000100 10964 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_R_N_BYTE_SEL_ALIGN 0 10965 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_R_N_BYTE_SEL_BITS 1 10966 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_R_N_BYTE_SEL_SHIFT 8 10967 10968 /* DDR40_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE0_R_N :: reserved2 [07:06] */ 10969 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_R_N_RESERVED2_MASK 0x000000c0 10970 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_R_N_RESERVED2_ALIGN 0 10971 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_R_N_RESERVED2_BITS 2 10972 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_R_N_RESERVED2_SHIFT 6 10973 10974 /* DDR40_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE0_R_N :: ovr_step [05:00] */ 10975 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_R_N_OVR_STEP_MASK 0x0000003f 10976 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_R_N_OVR_STEP_ALIGN 0 10977 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_R_N_OVR_STEP_BITS 6 10978 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_R_N_OVR_STEP_SHIFT 0 10979 10980 10981 /**************************************************************************** 10982 * DDR40_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P 10983 */ 10984 /* DDR40_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: reserved0 [31:25] */ 10985 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_RESERVED0_MASK 0xfe000000 10986 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_RESERVED0_ALIGN 0 10987 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_RESERVED0_BITS 7 10988 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_RESERVED0_SHIFT 25 10989 10990 /* DDR40_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: dm_ovr_en [24:24] */ 10991 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_DM_OVR_EN_MASK 0x01000000 10992 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_DM_OVR_EN_ALIGN 0 10993 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_DM_OVR_EN_BITS 1 10994 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_DM_OVR_EN_SHIFT 24 10995 10996 /* DDR40_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: ovr_en [23:16] */ 10997 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_OVR_EN_MASK 0x00ff0000 10998 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_OVR_EN_ALIGN 0 10999 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_OVR_EN_BITS 8 11000 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_OVR_EN_SHIFT 16 11001 11002 /* DDR40_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: reserved1 [15:09] */ 11003 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_RESERVED1_MASK 0x0000fe00 11004 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_RESERVED1_ALIGN 0 11005 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_RESERVED1_BITS 7 11006 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_RESERVED1_SHIFT 9 11007 11008 /* DDR40_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: byte_sel [08:08] */ 11009 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_BYTE_SEL_MASK 0x00000100 11010 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_BYTE_SEL_ALIGN 0 11011 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_BYTE_SEL_BITS 1 11012 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_BYTE_SEL_SHIFT 8 11013 11014 /* DDR40_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: reserved2 [07:06] */ 11015 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_RESERVED2_MASK 0x000000c0 11016 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_RESERVED2_ALIGN 0 11017 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_RESERVED2_BITS 2 11018 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_RESERVED2_SHIFT 6 11019 11020 /* DDR40_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_P :: ovr_step [05:00] */ 11021 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_OVR_STEP_MASK 0x0000003f 11022 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_OVR_STEP_ALIGN 0 11023 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_OVR_STEP_BITS 6 11024 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_P_OVR_STEP_SHIFT 0 11025 11026 11027 /**************************************************************************** 11028 * DDR40_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N 11029 */ 11030 /* DDR40_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: reserved0 [31:25] */ 11031 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_RESERVED0_MASK 0xfe000000 11032 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_RESERVED0_ALIGN 0 11033 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_RESERVED0_BITS 7 11034 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_RESERVED0_SHIFT 25 11035 11036 /* DDR40_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: dm_ovr_en [24:24] */ 11037 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_DM_OVR_EN_MASK 0x01000000 11038 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_DM_OVR_EN_ALIGN 0 11039 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_DM_OVR_EN_BITS 1 11040 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_DM_OVR_EN_SHIFT 24 11041 11042 /* DDR40_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: ovr_en [23:16] */ 11043 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_OVR_EN_MASK 0x00ff0000 11044 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_OVR_EN_ALIGN 0 11045 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_OVR_EN_BITS 8 11046 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_OVR_EN_SHIFT 16 11047 11048 /* DDR40_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: reserved1 [15:09] */ 11049 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_RESERVED1_MASK 0x0000fe00 11050 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_RESERVED1_ALIGN 0 11051 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_RESERVED1_BITS 7 11052 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_RESERVED1_SHIFT 9 11053 11054 /* DDR40_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: byte_sel [08:08] */ 11055 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_BYTE_SEL_MASK 0x00000100 11056 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_BYTE_SEL_ALIGN 0 11057 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_BYTE_SEL_BITS 1 11058 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_BYTE_SEL_SHIFT 8 11059 11060 /* DDR40_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: reserved2 [07:06] */ 11061 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_RESERVED2_MASK 0x000000c0 11062 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_RESERVED2_ALIGN 0 11063 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_RESERVED2_BITS 2 11064 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_RESERVED2_SHIFT 6 11065 11066 /* DDR40_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE0_BIT_R_N :: ovr_step [05:00] */ 11067 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_OVR_STEP_MASK 0x0000003f 11068 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_OVR_STEP_ALIGN 0 11069 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_OVR_STEP_BITS 6 11070 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_N_OVR_STEP_SHIFT 0 11071 11072 11073 /**************************************************************************** 11074 * DDR40_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE0_W 11075 */ 11076 /* DDR40_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE0_W :: reserved0 [31:17] */ 11077 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_W_RESERVED0_MASK 0xfffe0000 11078 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_W_RESERVED0_ALIGN 0 11079 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_W_RESERVED0_BITS 15 11080 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_W_RESERVED0_SHIFT 17 11081 11082 /* DDR40_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE0_W :: ovr_en [16:16] */ 11083 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_W_OVR_EN_MASK 0x00010000 11084 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_W_OVR_EN_ALIGN 0 11085 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_W_OVR_EN_BITS 1 11086 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_W_OVR_EN_SHIFT 16 11087 11088 /* DDR40_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE0_W :: reserved1 [15:09] */ 11089 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_W_RESERVED1_MASK 0x0000fe00 11090 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_W_RESERVED1_ALIGN 0 11091 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_W_RESERVED1_BITS 7 11092 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_W_RESERVED1_SHIFT 9 11093 11094 /* DDR40_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE0_W :: byte_sel [08:08] */ 11095 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_W_BYTE_SEL_MASK 0x00000100 11096 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_W_BYTE_SEL_ALIGN 0 11097 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_W_BYTE_SEL_BITS 1 11098 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_W_BYTE_SEL_SHIFT 8 11099 11100 /* DDR40_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE0_W :: reserved2 [07:06] */ 11101 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_W_RESERVED2_MASK 0x000000c0 11102 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_W_RESERVED2_ALIGN 0 11103 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_W_RESERVED2_BITS 2 11104 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_W_RESERVED2_SHIFT 6 11105 11106 /* DDR40_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE0_W :: ovr_step [05:00] */ 11107 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_W_OVR_STEP_MASK 0x0000003f 11108 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_W_OVR_STEP_ALIGN 0 11109 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_W_OVR_STEP_BITS 6 11110 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_W_OVR_STEP_SHIFT 0 11111 11112 11113 /**************************************************************************** 11114 * DDR40_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE0_BIT_W 11115 */ 11116 /* DDR40_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: reserved0 [31:25] */ 11117 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_W_RESERVED0_MASK 0xfe000000 11118 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_W_RESERVED0_ALIGN 0 11119 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_W_RESERVED0_BITS 7 11120 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_W_RESERVED0_SHIFT 25 11121 11122 /* DDR40_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: dm_ovr_en [24:24] */ 11123 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_W_DM_OVR_EN_MASK 0x01000000 11124 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_W_DM_OVR_EN_ALIGN 0 11125 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_W_DM_OVR_EN_BITS 1 11126 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_W_DM_OVR_EN_SHIFT 24 11127 11128 /* DDR40_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: ovr_en [23:16] */ 11129 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_W_OVR_EN_MASK 0x00ff0000 11130 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_W_OVR_EN_ALIGN 0 11131 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_W_OVR_EN_BITS 8 11132 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_W_OVR_EN_SHIFT 16 11133 11134 /* DDR40_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: reserved1 [15:09] */ 11135 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_W_RESERVED1_MASK 0x0000fe00 11136 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_W_RESERVED1_ALIGN 0 11137 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_W_RESERVED1_BITS 7 11138 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_W_RESERVED1_SHIFT 9 11139 11140 /* DDR40_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: byte_sel [08:08] */ 11141 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_W_BYTE_SEL_MASK 0x00000100 11142 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_W_BYTE_SEL_ALIGN 0 11143 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_W_BYTE_SEL_BITS 1 11144 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_W_BYTE_SEL_SHIFT 8 11145 11146 /* DDR40_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: reserved2 [07:06] */ 11147 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_W_RESERVED2_MASK 0x000000c0 11148 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_W_RESERVED2_ALIGN 0 11149 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_W_RESERVED2_BITS 2 11150 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_W_RESERVED2_SHIFT 6 11151 11152 /* DDR40_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE0_BIT_W :: ovr_step [05:00] */ 11153 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_W_OVR_STEP_MASK 0x0000003f 11154 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_W_OVR_STEP_ALIGN 0 11155 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_W_OVR_STEP_BITS 6 11156 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_W_OVR_STEP_SHIFT 0 11157 11158 11159 /**************************************************************************** 11160 * DDR40_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE1_R_P 11161 */ 11162 /* DDR40_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE1_R_P :: reserved0 [31:17] */ 11163 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_R_P_RESERVED0_MASK 0xfffe0000 11164 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_R_P_RESERVED0_ALIGN 0 11165 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_R_P_RESERVED0_BITS 15 11166 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_R_P_RESERVED0_SHIFT 17 11167 11168 /* DDR40_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE1_R_P :: ovr_en [16:16] */ 11169 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_R_P_OVR_EN_MASK 0x00010000 11170 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_R_P_OVR_EN_ALIGN 0 11171 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_R_P_OVR_EN_BITS 1 11172 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_R_P_OVR_EN_SHIFT 16 11173 11174 /* DDR40_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE1_R_P :: reserved1 [15:09] */ 11175 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_R_P_RESERVED1_MASK 0x0000fe00 11176 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_R_P_RESERVED1_ALIGN 0 11177 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_R_P_RESERVED1_BITS 7 11178 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_R_P_RESERVED1_SHIFT 9 11179 11180 /* DDR40_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE1_R_P :: byte_sel [08:08] */ 11181 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_R_P_BYTE_SEL_MASK 0x00000100 11182 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_R_P_BYTE_SEL_ALIGN 0 11183 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_R_P_BYTE_SEL_BITS 1 11184 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_R_P_BYTE_SEL_SHIFT 8 11185 11186 /* DDR40_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE1_R_P :: reserved2 [07:06] */ 11187 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_R_P_RESERVED2_MASK 0x000000c0 11188 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_R_P_RESERVED2_ALIGN 0 11189 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_R_P_RESERVED2_BITS 2 11190 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_R_P_RESERVED2_SHIFT 6 11191 11192 /* DDR40_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE1_R_P :: ovr_step [05:00] */ 11193 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_R_P_OVR_STEP_MASK 0x0000003f 11194 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_R_P_OVR_STEP_ALIGN 0 11195 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_R_P_OVR_STEP_BITS 6 11196 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_R_P_OVR_STEP_SHIFT 0 11197 11198 11199 /**************************************************************************** 11200 * DDR40_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE1_R_N 11201 */ 11202 /* DDR40_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE1_R_N :: reserved0 [31:17] */ 11203 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_R_N_RESERVED0_MASK 0xfffe0000 11204 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_R_N_RESERVED0_ALIGN 0 11205 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_R_N_RESERVED0_BITS 15 11206 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_R_N_RESERVED0_SHIFT 17 11207 11208 /* DDR40_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE1_R_N :: ovr_en [16:16] */ 11209 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_R_N_OVR_EN_MASK 0x00010000 11210 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_R_N_OVR_EN_ALIGN 0 11211 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_R_N_OVR_EN_BITS 1 11212 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_R_N_OVR_EN_SHIFT 16 11213 11214 /* DDR40_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE1_R_N :: reserved1 [15:09] */ 11215 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_R_N_RESERVED1_MASK 0x0000fe00 11216 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_R_N_RESERVED1_ALIGN 0 11217 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_R_N_RESERVED1_BITS 7 11218 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_R_N_RESERVED1_SHIFT 9 11219 11220 /* DDR40_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE1_R_N :: byte_sel [08:08] */ 11221 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_R_N_BYTE_SEL_MASK 0x00000100 11222 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_R_N_BYTE_SEL_ALIGN 0 11223 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_R_N_BYTE_SEL_BITS 1 11224 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_R_N_BYTE_SEL_SHIFT 8 11225 11226 /* DDR40_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE1_R_N :: reserved2 [07:06] */ 11227 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_R_N_RESERVED2_MASK 0x000000c0 11228 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_R_N_RESERVED2_ALIGN 0 11229 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_R_N_RESERVED2_BITS 2 11230 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_R_N_RESERVED2_SHIFT 6 11231 11232 /* DDR40_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE1_R_N :: ovr_step [05:00] */ 11233 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_R_N_OVR_STEP_MASK 0x0000003f 11234 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_R_N_OVR_STEP_ALIGN 0 11235 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_R_N_OVR_STEP_BITS 6 11236 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_R_N_OVR_STEP_SHIFT 0 11237 11238 11239 /**************************************************************************** 11240 * DDR40_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P 11241 */ 11242 /* DDR40_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: reserved0 [31:25] */ 11243 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_RESERVED0_MASK 0xfe000000 11244 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_RESERVED0_ALIGN 0 11245 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_RESERVED0_BITS 7 11246 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_RESERVED0_SHIFT 25 11247 11248 /* DDR40_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: dm_ovr_en [24:24] */ 11249 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_DM_OVR_EN_MASK 0x01000000 11250 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_DM_OVR_EN_ALIGN 0 11251 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_DM_OVR_EN_BITS 1 11252 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_DM_OVR_EN_SHIFT 24 11253 11254 /* DDR40_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: ovr_en [23:16] */ 11255 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_OVR_EN_MASK 0x00ff0000 11256 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_OVR_EN_ALIGN 0 11257 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_OVR_EN_BITS 8 11258 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_OVR_EN_SHIFT 16 11259 11260 /* DDR40_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: reserved1 [15:09] */ 11261 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_RESERVED1_MASK 0x0000fe00 11262 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_RESERVED1_ALIGN 0 11263 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_RESERVED1_BITS 7 11264 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_RESERVED1_SHIFT 9 11265 11266 /* DDR40_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: byte_sel [08:08] */ 11267 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_BYTE_SEL_MASK 0x00000100 11268 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_BYTE_SEL_ALIGN 0 11269 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_BYTE_SEL_BITS 1 11270 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_BYTE_SEL_SHIFT 8 11271 11272 /* DDR40_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: reserved2 [07:06] */ 11273 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_RESERVED2_MASK 0x000000c0 11274 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_RESERVED2_ALIGN 0 11275 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_RESERVED2_BITS 2 11276 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_RESERVED2_SHIFT 6 11277 11278 /* DDR40_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_P :: ovr_step [05:00] */ 11279 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_OVR_STEP_MASK 0x0000003f 11280 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_OVR_STEP_ALIGN 0 11281 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_OVR_STEP_BITS 6 11282 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_P_OVR_STEP_SHIFT 0 11283 11284 11285 /**************************************************************************** 11286 * DDR40_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N 11287 */ 11288 /* DDR40_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: reserved0 [31:25] */ 11289 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_RESERVED0_MASK 0xfe000000 11290 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_RESERVED0_ALIGN 0 11291 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_RESERVED0_BITS 7 11292 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_RESERVED0_SHIFT 25 11293 11294 /* DDR40_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: dm_ovr_en [24:24] */ 11295 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_DM_OVR_EN_MASK 0x01000000 11296 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_DM_OVR_EN_ALIGN 0 11297 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_DM_OVR_EN_BITS 1 11298 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_DM_OVR_EN_SHIFT 24 11299 11300 /* DDR40_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: ovr_en [23:16] */ 11301 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_OVR_EN_MASK 0x00ff0000 11302 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_OVR_EN_ALIGN 0 11303 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_OVR_EN_BITS 8 11304 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_OVR_EN_SHIFT 16 11305 11306 /* DDR40_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: reserved1 [15:09] */ 11307 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_RESERVED1_MASK 0x0000fe00 11308 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_RESERVED1_ALIGN 0 11309 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_RESERVED1_BITS 7 11310 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_RESERVED1_SHIFT 9 11311 11312 /* DDR40_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: byte_sel [08:08] */ 11313 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_BYTE_SEL_MASK 0x00000100 11314 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_BYTE_SEL_ALIGN 0 11315 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_BYTE_SEL_BITS 1 11316 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_BYTE_SEL_SHIFT 8 11317 11318 /* DDR40_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: reserved2 [07:06] */ 11319 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_RESERVED2_MASK 0x000000c0 11320 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_RESERVED2_ALIGN 0 11321 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_RESERVED2_BITS 2 11322 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_RESERVED2_SHIFT 6 11323 11324 /* DDR40_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE1_BIT_R_N :: ovr_step [05:00] */ 11325 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_OVR_STEP_MASK 0x0000003f 11326 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_OVR_STEP_ALIGN 0 11327 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_OVR_STEP_BITS 6 11328 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_N_OVR_STEP_SHIFT 0 11329 11330 11331 /**************************************************************************** 11332 * DDR40_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE1_W 11333 */ 11334 /* DDR40_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE1_W :: reserved0 [31:17] */ 11335 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_W_RESERVED0_MASK 0xfffe0000 11336 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_W_RESERVED0_ALIGN 0 11337 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_W_RESERVED0_BITS 15 11338 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_W_RESERVED0_SHIFT 17 11339 11340 /* DDR40_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE1_W :: ovr_en [16:16] */ 11341 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_W_OVR_EN_MASK 0x00010000 11342 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_W_OVR_EN_ALIGN 0 11343 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_W_OVR_EN_BITS 1 11344 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_W_OVR_EN_SHIFT 16 11345 11346 /* DDR40_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE1_W :: reserved1 [15:09] */ 11347 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_W_RESERVED1_MASK 0x0000fe00 11348 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_W_RESERVED1_ALIGN 0 11349 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_W_RESERVED1_BITS 7 11350 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_W_RESERVED1_SHIFT 9 11351 11352 /* DDR40_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE1_W :: byte_sel [08:08] */ 11353 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_W_BYTE_SEL_MASK 0x00000100 11354 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_W_BYTE_SEL_ALIGN 0 11355 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_W_BYTE_SEL_BITS 1 11356 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_W_BYTE_SEL_SHIFT 8 11357 11358 /* DDR40_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE1_W :: reserved2 [07:06] */ 11359 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_W_RESERVED2_MASK 0x000000c0 11360 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_W_RESERVED2_ALIGN 0 11361 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_W_RESERVED2_BITS 2 11362 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_W_RESERVED2_SHIFT 6 11363 11364 /* DDR40_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE1_W :: ovr_step [05:00] */ 11365 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_W_OVR_STEP_MASK 0x0000003f 11366 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_W_OVR_STEP_ALIGN 0 11367 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_W_OVR_STEP_BITS 6 11368 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_W_OVR_STEP_SHIFT 0 11369 11370 11371 /**************************************************************************** 11372 * DDR40_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE1_BIT_W 11373 */ 11374 /* DDR40_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: reserved0 [31:25] */ 11375 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_W_RESERVED0_MASK 0xfe000000 11376 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_W_RESERVED0_ALIGN 0 11377 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_W_RESERVED0_BITS 7 11378 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_W_RESERVED0_SHIFT 25 11379 11380 /* DDR40_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: dm_ovr_en [24:24] */ 11381 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_W_DM_OVR_EN_MASK 0x01000000 11382 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_W_DM_OVR_EN_ALIGN 0 11383 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_W_DM_OVR_EN_BITS 1 11384 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_W_DM_OVR_EN_SHIFT 24 11385 11386 /* DDR40_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: ovr_en [23:16] */ 11387 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_W_OVR_EN_MASK 0x00ff0000 11388 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_W_OVR_EN_ALIGN 0 11389 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_W_OVR_EN_BITS 8 11390 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_W_OVR_EN_SHIFT 16 11391 11392 /* DDR40_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: reserved1 [15:09] */ 11393 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_W_RESERVED1_MASK 0x0000fe00 11394 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_W_RESERVED1_ALIGN 0 11395 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_W_RESERVED1_BITS 7 11396 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_W_RESERVED1_SHIFT 9 11397 11398 /* DDR40_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: byte_sel [08:08] */ 11399 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_W_BYTE_SEL_MASK 0x00000100 11400 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_W_BYTE_SEL_ALIGN 0 11401 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_W_BYTE_SEL_BITS 1 11402 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_W_BYTE_SEL_SHIFT 8 11403 11404 /* DDR40_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: reserved2 [07:06] */ 11405 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_W_RESERVED2_MASK 0x000000c0 11406 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_W_RESERVED2_ALIGN 0 11407 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_W_RESERVED2_BITS 2 11408 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_W_RESERVED2_SHIFT 6 11409 11410 /* DDR40_PHY_WORD_LANE_1 :: DYN_VDL_OVRIDE_BYTE1_BIT_W :: ovr_step [05:00] */ 11411 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_W_OVR_STEP_MASK 0x0000003f 11412 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_W_OVR_STEP_ALIGN 0 11413 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_W_OVR_STEP_BITS 6 11414 #define DDR40_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_W_OVR_STEP_SHIFT 0 11415 11416 11417 /**************************************************************************** 11418 * DDR40_PHY_WORD_LANE_1 :: READ_DATA_DLY 11419 */ 11420 /* DDR40_PHY_WORD_LANE_1 :: READ_DATA_DLY :: reserved0 [31:03] */ 11421 #define DDR40_PHY_WORD_LANE_1_READ_DATA_DLY_RESERVED0_MASK 0xfffffff8 11422 #define DDR40_PHY_WORD_LANE_1_READ_DATA_DLY_RESERVED0_ALIGN 0 11423 #define DDR40_PHY_WORD_LANE_1_READ_DATA_DLY_RESERVED0_BITS 29 11424 #define DDR40_PHY_WORD_LANE_1_READ_DATA_DLY_RESERVED0_SHIFT 3 11425 11426 /* DDR40_PHY_WORD_LANE_1 :: READ_DATA_DLY :: rd_data_dly [02:00] */ 11427 #define DDR40_PHY_WORD_LANE_1_READ_DATA_DLY_RD_DATA_DLY_MASK 0x00000007 11428 #define DDR40_PHY_WORD_LANE_1_READ_DATA_DLY_RD_DATA_DLY_ALIGN 0 11429 #define DDR40_PHY_WORD_LANE_1_READ_DATA_DLY_RD_DATA_DLY_BITS 3 11430 #define DDR40_PHY_WORD_LANE_1_READ_DATA_DLY_RD_DATA_DLY_SHIFT 0 11431 11432 11433 /**************************************************************************** 11434 * DDR40_PHY_WORD_LANE_1 :: READ_CONTROL 11435 */ 11436 /* DDR40_PHY_WORD_LANE_1 :: READ_CONTROL :: reserved0 [31:03] */ 11437 #define DDR40_PHY_WORD_LANE_1_READ_CONTROL_RESERVED0_MASK 0xfffffff8 11438 #define DDR40_PHY_WORD_LANE_1_READ_CONTROL_RESERVED0_ALIGN 0 11439 #define DDR40_PHY_WORD_LANE_1_READ_CONTROL_RESERVED0_BITS 29 11440 #define DDR40_PHY_WORD_LANE_1_READ_CONTROL_RESERVED0_SHIFT 3 11441 11442 /* DDR40_PHY_WORD_LANE_1 :: READ_CONTROL :: dq_odt_enable [02:02] */ 11443 #define DDR40_PHY_WORD_LANE_1_READ_CONTROL_DQ_ODT_ENABLE_MASK 0x00000004 11444 #define DDR40_PHY_WORD_LANE_1_READ_CONTROL_DQ_ODT_ENABLE_ALIGN 0 11445 #define DDR40_PHY_WORD_LANE_1_READ_CONTROL_DQ_ODT_ENABLE_BITS 1 11446 #define DDR40_PHY_WORD_LANE_1_READ_CONTROL_DQ_ODT_ENABLE_SHIFT 2 11447 11448 /* DDR40_PHY_WORD_LANE_1 :: READ_CONTROL :: dq_odt_te_adj [01:01] */ 11449 #define DDR40_PHY_WORD_LANE_1_READ_CONTROL_DQ_ODT_TE_ADJ_MASK 0x00000002 11450 #define DDR40_PHY_WORD_LANE_1_READ_CONTROL_DQ_ODT_TE_ADJ_ALIGN 0 11451 #define DDR40_PHY_WORD_LANE_1_READ_CONTROL_DQ_ODT_TE_ADJ_BITS 1 11452 #define DDR40_PHY_WORD_LANE_1_READ_CONTROL_DQ_ODT_TE_ADJ_SHIFT 1 11453 11454 /* DDR40_PHY_WORD_LANE_1 :: READ_CONTROL :: dq_odt_le_adj [00:00] */ 11455 #define DDR40_PHY_WORD_LANE_1_READ_CONTROL_DQ_ODT_LE_ADJ_MASK 0x00000001 11456 #define DDR40_PHY_WORD_LANE_1_READ_CONTROL_DQ_ODT_LE_ADJ_ALIGN 0 11457 #define DDR40_PHY_WORD_LANE_1_READ_CONTROL_DQ_ODT_LE_ADJ_BITS 1 11458 #define DDR40_PHY_WORD_LANE_1_READ_CONTROL_DQ_ODT_LE_ADJ_SHIFT 0 11459 11460 11461 /**************************************************************************** 11462 * DDR40_PHY_WORD_LANE_1 :: READ_FIFO_DATA_BL0_0 11463 */ 11464 /* DDR40_PHY_WORD_LANE_1 :: READ_FIFO_DATA_BL0_0 :: reserved0 [31:16] */ 11465 #define DDR40_PHY_WORD_LANE_1_READ_FIFO_DATA_BL0_0_RESERVED0_MASK 0xffff0000 11466 #define DDR40_PHY_WORD_LANE_1_READ_FIFO_DATA_BL0_0_RESERVED0_ALIGN 0 11467 #define DDR40_PHY_WORD_LANE_1_READ_FIFO_DATA_BL0_0_RESERVED0_BITS 16 11468 #define DDR40_PHY_WORD_LANE_1_READ_FIFO_DATA_BL0_0_RESERVED0_SHIFT 16 11469 11470 /* DDR40_PHY_WORD_LANE_1 :: READ_FIFO_DATA_BL0_0 :: data_p [15:08] */ 11471 #define DDR40_PHY_WORD_LANE_1_READ_FIFO_DATA_BL0_0_DATA_P_MASK 0x0000ff00 11472 #define DDR40_PHY_WORD_LANE_1_READ_FIFO_DATA_BL0_0_DATA_P_ALIGN 0 11473 #define DDR40_PHY_WORD_LANE_1_READ_FIFO_DATA_BL0_0_DATA_P_BITS 8 11474 #define DDR40_PHY_WORD_LANE_1_READ_FIFO_DATA_BL0_0_DATA_P_SHIFT 8 11475 11476 /* DDR40_PHY_WORD_LANE_1 :: READ_FIFO_DATA_BL0_0 :: data_n [07:00] */ 11477 #define DDR40_PHY_WORD_LANE_1_READ_FIFO_DATA_BL0_0_DATA_N_MASK 0x000000ff 11478 #define DDR40_PHY_WORD_LANE_1_READ_FIFO_DATA_BL0_0_DATA_N_ALIGN 0 11479 #define DDR40_PHY_WORD_LANE_1_READ_FIFO_DATA_BL0_0_DATA_N_BITS 8 11480 #define DDR40_PHY_WORD_LANE_1_READ_FIFO_DATA_BL0_0_DATA_N_SHIFT 0 11481 11482 11483 /**************************************************************************** 11484 * DDR40_PHY_WORD_LANE_1 :: READ_FIFO_DATA_BL0_1 11485 */ 11486 /* DDR40_PHY_WORD_LANE_1 :: READ_FIFO_DATA_BL0_1 :: reserved0 [31:16] */ 11487 #define DDR40_PHY_WORD_LANE_1_READ_FIFO_DATA_BL0_1_RESERVED0_MASK 0xffff0000 11488 #define DDR40_PHY_WORD_LANE_1_READ_FIFO_DATA_BL0_1_RESERVED0_ALIGN 0 11489 #define DDR40_PHY_WORD_LANE_1_READ_FIFO_DATA_BL0_1_RESERVED0_BITS 16 11490 #define DDR40_PHY_WORD_LANE_1_READ_FIFO_DATA_BL0_1_RESERVED0_SHIFT 16 11491 11492 /* DDR40_PHY_WORD_LANE_1 :: READ_FIFO_DATA_BL0_1 :: data_p [15:08] */ 11493 #define DDR40_PHY_WORD_LANE_1_READ_FIFO_DATA_BL0_1_DATA_P_MASK 0x0000ff00 11494 #define DDR40_PHY_WORD_LANE_1_READ_FIFO_DATA_BL0_1_DATA_P_ALIGN 0 11495 #define DDR40_PHY_WORD_LANE_1_READ_FIFO_DATA_BL0_1_DATA_P_BITS 8 11496 #define DDR40_PHY_WORD_LANE_1_READ_FIFO_DATA_BL0_1_DATA_P_SHIFT 8 11497 11498 /* DDR40_PHY_WORD_LANE_1 :: READ_FIFO_DATA_BL0_1 :: data_n [07:00] */ 11499 #define DDR40_PHY_WORD_LANE_1_READ_FIFO_DATA_BL0_1_DATA_N_MASK 0x000000ff 11500 #define DDR40_PHY_WORD_LANE_1_READ_FIFO_DATA_BL0_1_DATA_N_ALIGN 0 11501 #define DDR40_PHY_WORD_LANE_1_READ_FIFO_DATA_BL0_1_DATA_N_BITS 8 11502 #define DDR40_PHY_WORD_LANE_1_READ_FIFO_DATA_BL0_1_DATA_N_SHIFT 0 11503 11504 11505 /**************************************************************************** 11506 * DDR40_PHY_WORD_LANE_1 :: READ_FIFO_DATA_BL0_2 11507 */ 11508 /* DDR40_PHY_WORD_LANE_1 :: READ_FIFO_DATA_BL0_2 :: reserved0 [31:16] */ 11509 #define DDR40_PHY_WORD_LANE_1_READ_FIFO_DATA_BL0_2_RESERVED0_MASK 0xffff0000 11510 #define DDR40_PHY_WORD_LANE_1_READ_FIFO_DATA_BL0_2_RESERVED0_ALIGN 0 11511 #define DDR40_PHY_WORD_LANE_1_READ_FIFO_DATA_BL0_2_RESERVED0_BITS 16 11512 #define DDR40_PHY_WORD_LANE_1_READ_FIFO_DATA_BL0_2_RESERVED0_SHIFT 16 11513 11514 /* DDR40_PHY_WORD_LANE_1 :: READ_FIFO_DATA_BL0_2 :: data_p [15:08] */ 11515 #define DDR40_PHY_WORD_LANE_1_READ_FIFO_DATA_BL0_2_DATA_P_MASK 0x0000ff00 11516 #define DDR40_PHY_WORD_LANE_1_READ_FIFO_DATA_BL0_2_DATA_P_ALIGN 0 11517 #define DDR40_PHY_WORD_LANE_1_READ_FIFO_DATA_BL0_2_DATA_P_BITS 8 11518 #define DDR40_PHY_WORD_LANE_1_READ_FIFO_DATA_BL0_2_DATA_P_SHIFT 8 11519 11520 /* DDR40_PHY_WORD_LANE_1 :: READ_FIFO_DATA_BL0_2 :: data_n [07:00] */ 11521 #define DDR40_PHY_WORD_LANE_1_READ_FIFO_DATA_BL0_2_DATA_N_MASK 0x000000ff 11522 #define DDR40_PHY_WORD_LANE_1_READ_FIFO_DATA_BL0_2_DATA_N_ALIGN 0 11523 #define DDR40_PHY_WORD_LANE_1_READ_FIFO_DATA_BL0_2_DATA_N_BITS 8 11524 #define DDR40_PHY_WORD_LANE_1_READ_FIFO_DATA_BL0_2_DATA_N_SHIFT 0 11525 11526 11527 /**************************************************************************** 11528 * DDR40_PHY_WORD_LANE_1 :: READ_FIFO_DATA_BL0_3 11529 */ 11530 /* DDR40_PHY_WORD_LANE_1 :: READ_FIFO_DATA_BL0_3 :: reserved0 [31:16] */ 11531 #define DDR40_PHY_WORD_LANE_1_READ_FIFO_DATA_BL0_3_RESERVED0_MASK 0xffff0000 11532 #define DDR40_PHY_WORD_LANE_1_READ_FIFO_DATA_BL0_3_RESERVED0_ALIGN 0 11533 #define DDR40_PHY_WORD_LANE_1_READ_FIFO_DATA_BL0_3_RESERVED0_BITS 16 11534 #define DDR40_PHY_WORD_LANE_1_READ_FIFO_DATA_BL0_3_RESERVED0_SHIFT 16 11535 11536 /* DDR40_PHY_WORD_LANE_1 :: READ_FIFO_DATA_BL0_3 :: data_p [15:08] */ 11537 #define DDR40_PHY_WORD_LANE_1_READ_FIFO_DATA_BL0_3_DATA_P_MASK 0x0000ff00 11538 #define DDR40_PHY_WORD_LANE_1_READ_FIFO_DATA_BL0_3_DATA_P_ALIGN 0 11539 #define DDR40_PHY_WORD_LANE_1_READ_FIFO_DATA_BL0_3_DATA_P_BITS 8 11540 #define DDR40_PHY_WORD_LANE_1_READ_FIFO_DATA_BL0_3_DATA_P_SHIFT 8 11541 11542 /* DDR40_PHY_WORD_LANE_1 :: READ_FIFO_DATA_BL0_3 :: data_n [07:00] */ 11543 #define DDR40_PHY_WORD_LANE_1_READ_FIFO_DATA_BL0_3_DATA_N_MASK 0x000000ff 11544 #define DDR40_PHY_WORD_LANE_1_READ_FIFO_DATA_BL0_3_DATA_N_ALIGN 0 11545 #define DDR40_PHY_WORD_LANE_1_READ_FIFO_DATA_BL0_3_DATA_N_BITS 8 11546 #define DDR40_PHY_WORD_LANE_1_READ_FIFO_DATA_BL0_3_DATA_N_SHIFT 0 11547 11548 11549 /**************************************************************************** 11550 * DDR40_PHY_WORD_LANE_1 :: READ_FIFO_DATA_BL1_0 11551 */ 11552 /* DDR40_PHY_WORD_LANE_1 :: READ_FIFO_DATA_BL1_0 :: reserved0 [31:16] */ 11553 #define DDR40_PHY_WORD_LANE_1_READ_FIFO_DATA_BL1_0_RESERVED0_MASK 0xffff0000 11554 #define DDR40_PHY_WORD_LANE_1_READ_FIFO_DATA_BL1_0_RESERVED0_ALIGN 0 11555 #define DDR40_PHY_WORD_LANE_1_READ_FIFO_DATA_BL1_0_RESERVED0_BITS 16 11556 #define DDR40_PHY_WORD_LANE_1_READ_FIFO_DATA_BL1_0_RESERVED0_SHIFT 16 11557 11558 /* DDR40_PHY_WORD_LANE_1 :: READ_FIFO_DATA_BL1_0 :: data_p [15:08] */ 11559 #define DDR40_PHY_WORD_LANE_1_READ_FIFO_DATA_BL1_0_DATA_P_MASK 0x0000ff00 11560 #define DDR40_PHY_WORD_LANE_1_READ_FIFO_DATA_BL1_0_DATA_P_ALIGN 0 11561 #define DDR40_PHY_WORD_LANE_1_READ_FIFO_DATA_BL1_0_DATA_P_BITS 8 11562 #define DDR40_PHY_WORD_LANE_1_READ_FIFO_DATA_BL1_0_DATA_P_SHIFT 8 11563 11564 /* DDR40_PHY_WORD_LANE_1 :: READ_FIFO_DATA_BL1_0 :: data_n [07:00] */ 11565 #define DDR40_PHY_WORD_LANE_1_READ_FIFO_DATA_BL1_0_DATA_N_MASK 0x000000ff 11566 #define DDR40_PHY_WORD_LANE_1_READ_FIFO_DATA_BL1_0_DATA_N_ALIGN 0 11567 #define DDR40_PHY_WORD_LANE_1_READ_FIFO_DATA_BL1_0_DATA_N_BITS 8 11568 #define DDR40_PHY_WORD_LANE_1_READ_FIFO_DATA_BL1_0_DATA_N_SHIFT 0 11569 11570 11571 /**************************************************************************** 11572 * DDR40_PHY_WORD_LANE_1 :: READ_FIFO_DATA_BL1_1 11573 */ 11574 /* DDR40_PHY_WORD_LANE_1 :: READ_FIFO_DATA_BL1_1 :: reserved0 [31:16] */ 11575 #define DDR40_PHY_WORD_LANE_1_READ_FIFO_DATA_BL1_1_RESERVED0_MASK 0xffff0000 11576 #define DDR40_PHY_WORD_LANE_1_READ_FIFO_DATA_BL1_1_RESERVED0_ALIGN 0 11577 #define DDR40_PHY_WORD_LANE_1_READ_FIFO_DATA_BL1_1_RESERVED0_BITS 16 11578 #define DDR40_PHY_WORD_LANE_1_READ_FIFO_DATA_BL1_1_RESERVED0_SHIFT 16 11579 11580 /* DDR40_PHY_WORD_LANE_1 :: READ_FIFO_DATA_BL1_1 :: data_p [15:08] */ 11581 #define DDR40_PHY_WORD_LANE_1_READ_FIFO_DATA_BL1_1_DATA_P_MASK 0x0000ff00 11582 #define DDR40_PHY_WORD_LANE_1_READ_FIFO_DATA_BL1_1_DATA_P_ALIGN 0 11583 #define DDR40_PHY_WORD_LANE_1_READ_FIFO_DATA_BL1_1_DATA_P_BITS 8 11584 #define DDR40_PHY_WORD_LANE_1_READ_FIFO_DATA_BL1_1_DATA_P_SHIFT 8 11585 11586 /* DDR40_PHY_WORD_LANE_1 :: READ_FIFO_DATA_BL1_1 :: data_n [07:00] */ 11587 #define DDR40_PHY_WORD_LANE_1_READ_FIFO_DATA_BL1_1_DATA_N_MASK 0x000000ff 11588 #define DDR40_PHY_WORD_LANE_1_READ_FIFO_DATA_BL1_1_DATA_N_ALIGN 0 11589 #define DDR40_PHY_WORD_LANE_1_READ_FIFO_DATA_BL1_1_DATA_N_BITS 8 11590 #define DDR40_PHY_WORD_LANE_1_READ_FIFO_DATA_BL1_1_DATA_N_SHIFT 0 11591 11592 11593 /**************************************************************************** 11594 * DDR40_PHY_WORD_LANE_1 :: READ_FIFO_DATA_BL1_2 11595 */ 11596 /* DDR40_PHY_WORD_LANE_1 :: READ_FIFO_DATA_BL1_2 :: reserved0 [31:16] */ 11597 #define DDR40_PHY_WORD_LANE_1_READ_FIFO_DATA_BL1_2_RESERVED0_MASK 0xffff0000 11598 #define DDR40_PHY_WORD_LANE_1_READ_FIFO_DATA_BL1_2_RESERVED0_ALIGN 0 11599 #define DDR40_PHY_WORD_LANE_1_READ_FIFO_DATA_BL1_2_RESERVED0_BITS 16 11600 #define DDR40_PHY_WORD_LANE_1_READ_FIFO_DATA_BL1_2_RESERVED0_SHIFT 16 11601 11602 /* DDR40_PHY_WORD_LANE_1 :: READ_FIFO_DATA_BL1_2 :: data_p [15:08] */ 11603 #define DDR40_PHY_WORD_LANE_1_READ_FIFO_DATA_BL1_2_DATA_P_MASK 0x0000ff00 11604 #define DDR40_PHY_WORD_LANE_1_READ_FIFO_DATA_BL1_2_DATA_P_ALIGN 0 11605 #define DDR40_PHY_WORD_LANE_1_READ_FIFO_DATA_BL1_2_DATA_P_BITS 8 11606 #define DDR40_PHY_WORD_LANE_1_READ_FIFO_DATA_BL1_2_DATA_P_SHIFT 8 11607 11608 /* DDR40_PHY_WORD_LANE_1 :: READ_FIFO_DATA_BL1_2 :: data_n [07:00] */ 11609 #define DDR40_PHY_WORD_LANE_1_READ_FIFO_DATA_BL1_2_DATA_N_MASK 0x000000ff 11610 #define DDR40_PHY_WORD_LANE_1_READ_FIFO_DATA_BL1_2_DATA_N_ALIGN 0 11611 #define DDR40_PHY_WORD_LANE_1_READ_FIFO_DATA_BL1_2_DATA_N_BITS 8 11612 #define DDR40_PHY_WORD_LANE_1_READ_FIFO_DATA_BL1_2_DATA_N_SHIFT 0 11613 11614 11615 /**************************************************************************** 11616 * DDR40_PHY_WORD_LANE_1 :: READ_FIFO_DATA_BL1_3 11617 */ 11618 /* DDR40_PHY_WORD_LANE_1 :: READ_FIFO_DATA_BL1_3 :: reserved0 [31:16] */ 11619 #define DDR40_PHY_WORD_LANE_1_READ_FIFO_DATA_BL1_3_RESERVED0_MASK 0xffff0000 11620 #define DDR40_PHY_WORD_LANE_1_READ_FIFO_DATA_BL1_3_RESERVED0_ALIGN 0 11621 #define DDR40_PHY_WORD_LANE_1_READ_FIFO_DATA_BL1_3_RESERVED0_BITS 16 11622 #define DDR40_PHY_WORD_LANE_1_READ_FIFO_DATA_BL1_3_RESERVED0_SHIFT 16 11623 11624 /* DDR40_PHY_WORD_LANE_1 :: READ_FIFO_DATA_BL1_3 :: data_p [15:08] */ 11625 #define DDR40_PHY_WORD_LANE_1_READ_FIFO_DATA_BL1_3_DATA_P_MASK 0x0000ff00 11626 #define DDR40_PHY_WORD_LANE_1_READ_FIFO_DATA_BL1_3_DATA_P_ALIGN 0 11627 #define DDR40_PHY_WORD_LANE_1_READ_FIFO_DATA_BL1_3_DATA_P_BITS 8 11628 #define DDR40_PHY_WORD_LANE_1_READ_FIFO_DATA_BL1_3_DATA_P_SHIFT 8 11629 11630 /* DDR40_PHY_WORD_LANE_1 :: READ_FIFO_DATA_BL1_3 :: data_n [07:00] */ 11631 #define DDR40_PHY_WORD_LANE_1_READ_FIFO_DATA_BL1_3_DATA_N_MASK 0x000000ff 11632 #define DDR40_PHY_WORD_LANE_1_READ_FIFO_DATA_BL1_3_DATA_N_ALIGN 0 11633 #define DDR40_PHY_WORD_LANE_1_READ_FIFO_DATA_BL1_3_DATA_N_BITS 8 11634 #define DDR40_PHY_WORD_LANE_1_READ_FIFO_DATA_BL1_3_DATA_N_SHIFT 0 11635 11636 11637 /**************************************************************************** 11638 * DDR40_PHY_WORD_LANE_1 :: READ_FIFO_STATUS 11639 */ 11640 /* DDR40_PHY_WORD_LANE_1 :: READ_FIFO_STATUS :: reserved0 [31:08] */ 11641 #define DDR40_PHY_WORD_LANE_1_READ_FIFO_STATUS_RESERVED0_MASK 0xffffff00 11642 #define DDR40_PHY_WORD_LANE_1_READ_FIFO_STATUS_RESERVED0_ALIGN 0 11643 #define DDR40_PHY_WORD_LANE_1_READ_FIFO_STATUS_RESERVED0_BITS 24 11644 #define DDR40_PHY_WORD_LANE_1_READ_FIFO_STATUS_RESERVED0_SHIFT 8 11645 11646 /* DDR40_PHY_WORD_LANE_1 :: READ_FIFO_STATUS :: status1 [07:04] */ 11647 #define DDR40_PHY_WORD_LANE_1_READ_FIFO_STATUS_STATUS1_MASK 0x000000f0 11648 #define DDR40_PHY_WORD_LANE_1_READ_FIFO_STATUS_STATUS1_ALIGN 0 11649 #define DDR40_PHY_WORD_LANE_1_READ_FIFO_STATUS_STATUS1_BITS 4 11650 #define DDR40_PHY_WORD_LANE_1_READ_FIFO_STATUS_STATUS1_SHIFT 4 11651 11652 /* DDR40_PHY_WORD_LANE_1 :: READ_FIFO_STATUS :: status0 [03:00] */ 11653 #define DDR40_PHY_WORD_LANE_1_READ_FIFO_STATUS_STATUS0_MASK 0x0000000f 11654 #define DDR40_PHY_WORD_LANE_1_READ_FIFO_STATUS_STATUS0_ALIGN 0 11655 #define DDR40_PHY_WORD_LANE_1_READ_FIFO_STATUS_STATUS0_BITS 4 11656 #define DDR40_PHY_WORD_LANE_1_READ_FIFO_STATUS_STATUS0_SHIFT 0 11657 11658 11659 /**************************************************************************** 11660 * DDR40_PHY_WORD_LANE_1 :: READ_FIFO_CLEAR 11661 */ 11662 /* DDR40_PHY_WORD_LANE_1 :: READ_FIFO_CLEAR :: reserved0 [31:01] */ 11663 #define DDR40_PHY_WORD_LANE_1_READ_FIFO_CLEAR_RESERVED0_MASK 0xfffffffe 11664 #define DDR40_PHY_WORD_LANE_1_READ_FIFO_CLEAR_RESERVED0_ALIGN 0 11665 #define DDR40_PHY_WORD_LANE_1_READ_FIFO_CLEAR_RESERVED0_BITS 31 11666 #define DDR40_PHY_WORD_LANE_1_READ_FIFO_CLEAR_RESERVED0_SHIFT 1 11667 11668 /* DDR40_PHY_WORD_LANE_1 :: READ_FIFO_CLEAR :: clear [00:00] */ 11669 #define DDR40_PHY_WORD_LANE_1_READ_FIFO_CLEAR_CLEAR_MASK 0x00000001 11670 #define DDR40_PHY_WORD_LANE_1_READ_FIFO_CLEAR_CLEAR_ALIGN 0 11671 #define DDR40_PHY_WORD_LANE_1_READ_FIFO_CLEAR_CLEAR_BITS 1 11672 #define DDR40_PHY_WORD_LANE_1_READ_FIFO_CLEAR_CLEAR_SHIFT 0 11673 11674 11675 /**************************************************************************** 11676 * DDR40_PHY_WORD_LANE_1 :: IDLE_PAD_CONTROL 11677 */ 11678 /* DDR40_PHY_WORD_LANE_1 :: IDLE_PAD_CONTROL :: idle [31:31] */ 11679 #define DDR40_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_IDLE_MASK 0x80000000 11680 #define DDR40_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_IDLE_ALIGN 0 11681 #define DDR40_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_IDLE_BITS 1 11682 #define DDR40_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_IDLE_SHIFT 31 11683 11684 /* DDR40_PHY_WORD_LANE_1 :: IDLE_PAD_CONTROL :: reserved0 [30:24] */ 11685 #define DDR40_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_RESERVED0_MASK 0x7f000000 11686 #define DDR40_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_RESERVED0_ALIGN 0 11687 #define DDR40_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_RESERVED0_BITS 7 11688 #define DDR40_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_RESERVED0_SHIFT 24 11689 11690 /* DDR40_PHY_WORD_LANE_1 :: IDLE_PAD_CONTROL :: auto_dq_rxenb_mode [23:22] */ 11691 #define DDR40_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_AUTO_DQ_RXENB_MODE_MASK 0x00c00000 11692 #define DDR40_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_AUTO_DQ_RXENB_MODE_ALIGN 0 11693 #define DDR40_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_AUTO_DQ_RXENB_MODE_BITS 2 11694 #define DDR40_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_AUTO_DQ_RXENB_MODE_SHIFT 22 11695 11696 /* DDR40_PHY_WORD_LANE_1 :: IDLE_PAD_CONTROL :: auto_dq_iddq_mode [21:20] */ 11697 #define DDR40_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_AUTO_DQ_IDDQ_MODE_MASK 0x00300000 11698 #define DDR40_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_AUTO_DQ_IDDQ_MODE_ALIGN 0 11699 #define DDR40_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_AUTO_DQ_IDDQ_MODE_BITS 2 11700 #define DDR40_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_AUTO_DQ_IDDQ_MODE_SHIFT 20 11701 11702 /* DDR40_PHY_WORD_LANE_1 :: IDLE_PAD_CONTROL :: dq_rxenb [19:19] */ 11703 #define DDR40_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_DQ_RXENB_MASK 0x00080000 11704 #define DDR40_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_DQ_RXENB_ALIGN 0 11705 #define DDR40_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_DQ_RXENB_BITS 1 11706 #define DDR40_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_DQ_RXENB_SHIFT 19 11707 11708 /* DDR40_PHY_WORD_LANE_1 :: IDLE_PAD_CONTROL :: dq_iddq [18:18] */ 11709 #define DDR40_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_DQ_IDDQ_MASK 0x00040000 11710 #define DDR40_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_DQ_IDDQ_ALIGN 0 11711 #define DDR40_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_DQ_IDDQ_BITS 1 11712 #define DDR40_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_DQ_IDDQ_SHIFT 18 11713 11714 /* DDR40_PHY_WORD_LANE_1 :: IDLE_PAD_CONTROL :: dq_reb [17:17] */ 11715 #define DDR40_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_DQ_REB_MASK 0x00020000 11716 #define DDR40_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_DQ_REB_ALIGN 0 11717 #define DDR40_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_DQ_REB_BITS 1 11718 #define DDR40_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_DQ_REB_SHIFT 17 11719 11720 /* DDR40_PHY_WORD_LANE_1 :: IDLE_PAD_CONTROL :: dq_oeb [16:16] */ 11721 #define DDR40_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_DQ_OEB_MASK 0x00010000 11722 #define DDR40_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_DQ_OEB_ALIGN 0 11723 #define DDR40_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_DQ_OEB_BITS 1 11724 #define DDR40_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_DQ_OEB_SHIFT 16 11725 11726 /* DDR40_PHY_WORD_LANE_1 :: IDLE_PAD_CONTROL :: read_enb_rxenb [15:15] */ 11727 #define DDR40_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_READ_ENB_RXENB_MASK 0x00008000 11728 #define DDR40_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_READ_ENB_RXENB_ALIGN 0 11729 #define DDR40_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_READ_ENB_RXENB_BITS 1 11730 #define DDR40_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_READ_ENB_RXENB_SHIFT 15 11731 11732 /* DDR40_PHY_WORD_LANE_1 :: IDLE_PAD_CONTROL :: read_enb_iddq [14:14] */ 11733 #define DDR40_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_READ_ENB_IDDQ_MASK 0x00004000 11734 #define DDR40_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_READ_ENB_IDDQ_ALIGN 0 11735 #define DDR40_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_READ_ENB_IDDQ_BITS 1 11736 #define DDR40_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_READ_ENB_IDDQ_SHIFT 14 11737 11738 /* DDR40_PHY_WORD_LANE_1 :: IDLE_PAD_CONTROL :: read_enb_reb [13:13] */ 11739 #define DDR40_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_READ_ENB_REB_MASK 0x00002000 11740 #define DDR40_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_READ_ENB_REB_ALIGN 0 11741 #define DDR40_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_READ_ENB_REB_BITS 1 11742 #define DDR40_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_READ_ENB_REB_SHIFT 13 11743 11744 /* DDR40_PHY_WORD_LANE_1 :: IDLE_PAD_CONTROL :: read_enb_oeb [12:12] */ 11745 #define DDR40_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_READ_ENB_OEB_MASK 0x00001000 11746 #define DDR40_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_READ_ENB_OEB_ALIGN 0 11747 #define DDR40_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_READ_ENB_OEB_BITS 1 11748 #define DDR40_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_READ_ENB_OEB_SHIFT 12 11749 11750 /* DDR40_PHY_WORD_LANE_1 :: IDLE_PAD_CONTROL :: dqs_rxenb [11:11] */ 11751 #define DDR40_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_DQS_RXENB_MASK 0x00000800 11752 #define DDR40_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_DQS_RXENB_ALIGN 0 11753 #define DDR40_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_DQS_RXENB_BITS 1 11754 #define DDR40_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_DQS_RXENB_SHIFT 11 11755 11756 /* DDR40_PHY_WORD_LANE_1 :: IDLE_PAD_CONTROL :: dqs_iddq [10:10] */ 11757 #define DDR40_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_DQS_IDDQ_MASK 0x00000400 11758 #define DDR40_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_DQS_IDDQ_ALIGN 0 11759 #define DDR40_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_DQS_IDDQ_BITS 1 11760 #define DDR40_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_DQS_IDDQ_SHIFT 10 11761 11762 /* DDR40_PHY_WORD_LANE_1 :: IDLE_PAD_CONTROL :: dqs_reb [09:09] */ 11763 #define DDR40_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_DQS_REB_MASK 0x00000200 11764 #define DDR40_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_DQS_REB_ALIGN 0 11765 #define DDR40_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_DQS_REB_BITS 1 11766 #define DDR40_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_DQS_REB_SHIFT 9 11767 11768 /* DDR40_PHY_WORD_LANE_1 :: IDLE_PAD_CONTROL :: dqs_oeb [08:08] */ 11769 #define DDR40_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_DQS_OEB_MASK 0x00000100 11770 #define DDR40_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_DQS_OEB_ALIGN 0 11771 #define DDR40_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_DQS_OEB_BITS 1 11772 #define DDR40_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_DQS_OEB_SHIFT 8 11773 11774 /* DDR40_PHY_WORD_LANE_1 :: IDLE_PAD_CONTROL :: clk1_rxenb [07:07] */ 11775 #define DDR40_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_CLK1_RXENB_MASK 0x00000080 11776 #define DDR40_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_CLK1_RXENB_ALIGN 0 11777 #define DDR40_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_CLK1_RXENB_BITS 1 11778 #define DDR40_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_CLK1_RXENB_SHIFT 7 11779 11780 /* DDR40_PHY_WORD_LANE_1 :: IDLE_PAD_CONTROL :: clk1_iddq [06:06] */ 11781 #define DDR40_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_CLK1_IDDQ_MASK 0x00000040 11782 #define DDR40_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_CLK1_IDDQ_ALIGN 0 11783 #define DDR40_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_CLK1_IDDQ_BITS 1 11784 #define DDR40_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_CLK1_IDDQ_SHIFT 6 11785 11786 /* DDR40_PHY_WORD_LANE_1 :: IDLE_PAD_CONTROL :: clk1_reb [05:05] */ 11787 #define DDR40_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_CLK1_REB_MASK 0x00000020 11788 #define DDR40_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_CLK1_REB_ALIGN 0 11789 #define DDR40_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_CLK1_REB_BITS 1 11790 #define DDR40_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_CLK1_REB_SHIFT 5 11791 11792 /* DDR40_PHY_WORD_LANE_1 :: IDLE_PAD_CONTROL :: clk1_oeb [04:04] */ 11793 #define DDR40_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_CLK1_OEB_MASK 0x00000010 11794 #define DDR40_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_CLK1_OEB_ALIGN 0 11795 #define DDR40_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_CLK1_OEB_BITS 1 11796 #define DDR40_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_CLK1_OEB_SHIFT 4 11797 11798 /* DDR40_PHY_WORD_LANE_1 :: IDLE_PAD_CONTROL :: clk0_rxenb [03:03] */ 11799 #define DDR40_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_CLK0_RXENB_MASK 0x00000008 11800 #define DDR40_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_CLK0_RXENB_ALIGN 0 11801 #define DDR40_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_CLK0_RXENB_BITS 1 11802 #define DDR40_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_CLK0_RXENB_SHIFT 3 11803 11804 /* DDR40_PHY_WORD_LANE_1 :: IDLE_PAD_CONTROL :: clk0_iddq [02:02] */ 11805 #define DDR40_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_CLK0_IDDQ_MASK 0x00000004 11806 #define DDR40_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_CLK0_IDDQ_ALIGN 0 11807 #define DDR40_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_CLK0_IDDQ_BITS 1 11808 #define DDR40_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_CLK0_IDDQ_SHIFT 2 11809 11810 /* DDR40_PHY_WORD_LANE_1 :: IDLE_PAD_CONTROL :: clk0_reb [01:01] */ 11811 #define DDR40_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_CLK0_REB_MASK 0x00000002 11812 #define DDR40_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_CLK0_REB_ALIGN 0 11813 #define DDR40_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_CLK0_REB_BITS 1 11814 #define DDR40_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_CLK0_REB_SHIFT 1 11815 11816 /* DDR40_PHY_WORD_LANE_1 :: IDLE_PAD_CONTROL :: clk0_oeb [00:00] */ 11817 #define DDR40_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_CLK0_OEB_MASK 0x00000001 11818 #define DDR40_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_CLK0_OEB_ALIGN 0 11819 #define DDR40_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_CLK0_OEB_BITS 1 11820 #define DDR40_PHY_WORD_LANE_1_IDLE_PAD_CONTROL_CLK0_OEB_SHIFT 0 11821 11822 11823 /**************************************************************************** 11824 * DDR40_PHY_WORD_LANE_1 :: DRIVE_PAD_CTL 11825 */ 11826 /* DDR40_PHY_WORD_LANE_1 :: DRIVE_PAD_CTL :: reserved0 [31:12] */ 11827 #define DDR40_PHY_WORD_LANE_1_DRIVE_PAD_CTL_RESERVED0_MASK 0xfffff000 11828 #define DDR40_PHY_WORD_LANE_1_DRIVE_PAD_CTL_RESERVED0_ALIGN 0 11829 #define DDR40_PHY_WORD_LANE_1_DRIVE_PAD_CTL_RESERVED0_BITS 20 11830 #define DDR40_PHY_WORD_LANE_1_DRIVE_PAD_CTL_RESERVED0_SHIFT 12 11831 11832 /* DDR40_PHY_WORD_LANE_1 :: DRIVE_PAD_CTL :: no_dqs_rd [11:11] */ 11833 #define DDR40_PHY_WORD_LANE_1_DRIVE_PAD_CTL_NO_DQS_RD_MASK 0x00000800 11834 #define DDR40_PHY_WORD_LANE_1_DRIVE_PAD_CTL_NO_DQS_RD_ALIGN 0 11835 #define DDR40_PHY_WORD_LANE_1_DRIVE_PAD_CTL_NO_DQS_RD_BITS 1 11836 #define DDR40_PHY_WORD_LANE_1_DRIVE_PAD_CTL_NO_DQS_RD_SHIFT 11 11837 11838 /* DDR40_PHY_WORD_LANE_1 :: DRIVE_PAD_CTL :: dqs_always_on [10:10] */ 11839 #define DDR40_PHY_WORD_LANE_1_DRIVE_PAD_CTL_DQS_ALWAYS_ON_MASK 0x00000400 11840 #define DDR40_PHY_WORD_LANE_1_DRIVE_PAD_CTL_DQS_ALWAYS_ON_ALIGN 0 11841 #define DDR40_PHY_WORD_LANE_1_DRIVE_PAD_CTL_DQS_ALWAYS_ON_BITS 1 11842 #define DDR40_PHY_WORD_LANE_1_DRIVE_PAD_CTL_DQS_ALWAYS_ON_SHIFT 10 11843 11844 /* DDR40_PHY_WORD_LANE_1 :: DRIVE_PAD_CTL :: dqs_tx_dis [09:09] */ 11845 #define DDR40_PHY_WORD_LANE_1_DRIVE_PAD_CTL_DQS_TX_DIS_MASK 0x00000200 11846 #define DDR40_PHY_WORD_LANE_1_DRIVE_PAD_CTL_DQS_TX_DIS_ALIGN 0 11847 #define DDR40_PHY_WORD_LANE_1_DRIVE_PAD_CTL_DQS_TX_DIS_BITS 1 11848 #define DDR40_PHY_WORD_LANE_1_DRIVE_PAD_CTL_DQS_TX_DIS_SHIFT 9 11849 11850 /* DDR40_PHY_WORD_LANE_1 :: DRIVE_PAD_CTL :: half_strength_ck [08:08] */ 11851 #define DDR40_PHY_WORD_LANE_1_DRIVE_PAD_CTL_HALF_STRENGTH_CK_MASK 0x00000100 11852 #define DDR40_PHY_WORD_LANE_1_DRIVE_PAD_CTL_HALF_STRENGTH_CK_ALIGN 0 11853 #define DDR40_PHY_WORD_LANE_1_DRIVE_PAD_CTL_HALF_STRENGTH_CK_BITS 1 11854 #define DDR40_PHY_WORD_LANE_1_DRIVE_PAD_CTL_HALF_STRENGTH_CK_SHIFT 8 11855 11856 /* DDR40_PHY_WORD_LANE_1 :: DRIVE_PAD_CTL :: half_strength [07:07] */ 11857 #define DDR40_PHY_WORD_LANE_1_DRIVE_PAD_CTL_HALF_STRENGTH_MASK 0x00000080 11858 #define DDR40_PHY_WORD_LANE_1_DRIVE_PAD_CTL_HALF_STRENGTH_ALIGN 0 11859 #define DDR40_PHY_WORD_LANE_1_DRIVE_PAD_CTL_HALF_STRENGTH_BITS 1 11860 #define DDR40_PHY_WORD_LANE_1_DRIVE_PAD_CTL_HALF_STRENGTH_SHIFT 7 11861 11862 /* DDR40_PHY_WORD_LANE_1 :: DRIVE_PAD_CTL :: rdqs_en [06:06] */ 11863 #define DDR40_PHY_WORD_LANE_1_DRIVE_PAD_CTL_RDQS_EN_MASK 0x00000040 11864 #define DDR40_PHY_WORD_LANE_1_DRIVE_PAD_CTL_RDQS_EN_ALIGN 0 11865 #define DDR40_PHY_WORD_LANE_1_DRIVE_PAD_CTL_RDQS_EN_BITS 1 11866 #define DDR40_PHY_WORD_LANE_1_DRIVE_PAD_CTL_RDQS_EN_SHIFT 6 11867 11868 /* DDR40_PHY_WORD_LANE_1 :: DRIVE_PAD_CTL :: gddr_symmetry [05:05] */ 11869 #define DDR40_PHY_WORD_LANE_1_DRIVE_PAD_CTL_GDDR_SYMMETRY_MASK 0x00000020 11870 #define DDR40_PHY_WORD_LANE_1_DRIVE_PAD_CTL_GDDR_SYMMETRY_ALIGN 0 11871 #define DDR40_PHY_WORD_LANE_1_DRIVE_PAD_CTL_GDDR_SYMMETRY_BITS 1 11872 #define DDR40_PHY_WORD_LANE_1_DRIVE_PAD_CTL_GDDR_SYMMETRY_SHIFT 5 11873 11874 /* DDR40_PHY_WORD_LANE_1 :: DRIVE_PAD_CTL :: vddo_volts [04:03] */ 11875 #define DDR40_PHY_WORD_LANE_1_DRIVE_PAD_CTL_VDDO_VOLTS_MASK 0x00000018 11876 #define DDR40_PHY_WORD_LANE_1_DRIVE_PAD_CTL_VDDO_VOLTS_ALIGN 0 11877 #define DDR40_PHY_WORD_LANE_1_DRIVE_PAD_CTL_VDDO_VOLTS_BITS 2 11878 #define DDR40_PHY_WORD_LANE_1_DRIVE_PAD_CTL_VDDO_VOLTS_SHIFT 3 11879 11880 /* DDR40_PHY_WORD_LANE_1 :: DRIVE_PAD_CTL :: rt60b [02:02] */ 11881 #define DDR40_PHY_WORD_LANE_1_DRIVE_PAD_CTL_RT60B_MASK 0x00000004 11882 #define DDR40_PHY_WORD_LANE_1_DRIVE_PAD_CTL_RT60B_ALIGN 0 11883 #define DDR40_PHY_WORD_LANE_1_DRIVE_PAD_CTL_RT60B_BITS 1 11884 #define DDR40_PHY_WORD_LANE_1_DRIVE_PAD_CTL_RT60B_SHIFT 2 11885 11886 /* DDR40_PHY_WORD_LANE_1 :: DRIVE_PAD_CTL :: rt120b_g [01:01] */ 11887 #define DDR40_PHY_WORD_LANE_1_DRIVE_PAD_CTL_RT120B_G_MASK 0x00000002 11888 #define DDR40_PHY_WORD_LANE_1_DRIVE_PAD_CTL_RT120B_G_ALIGN 0 11889 #define DDR40_PHY_WORD_LANE_1_DRIVE_PAD_CTL_RT120B_G_BITS 1 11890 #define DDR40_PHY_WORD_LANE_1_DRIVE_PAD_CTL_RT120B_G_SHIFT 1 11891 11892 /* DDR40_PHY_WORD_LANE_1 :: DRIVE_PAD_CTL :: g_ddr [00:00] */ 11893 #define DDR40_PHY_WORD_LANE_1_DRIVE_PAD_CTL_G_DDR_MASK 0x00000001 11894 #define DDR40_PHY_WORD_LANE_1_DRIVE_PAD_CTL_G_DDR_ALIGN 0 11895 #define DDR40_PHY_WORD_LANE_1_DRIVE_PAD_CTL_G_DDR_BITS 1 11896 #define DDR40_PHY_WORD_LANE_1_DRIVE_PAD_CTL_G_DDR_SHIFT 0 11897 11898 11899 /**************************************************************************** 11900 * DDR40_PHY_WORD_LANE_1 :: CLOCK_PAD_DISABLE 11901 */ 11902 /* DDR40_PHY_WORD_LANE_1 :: CLOCK_PAD_DISABLE :: reserved0 [31:03] */ 11903 #define DDR40_PHY_WORD_LANE_1_CLOCK_PAD_DISABLE_RESERVED0_MASK 0xfffffff8 11904 #define DDR40_PHY_WORD_LANE_1_CLOCK_PAD_DISABLE_RESERVED0_ALIGN 0 11905 #define DDR40_PHY_WORD_LANE_1_CLOCK_PAD_DISABLE_RESERVED0_BITS 29 11906 #define DDR40_PHY_WORD_LANE_1_CLOCK_PAD_DISABLE_RESERVED0_SHIFT 3 11907 11908 /* DDR40_PHY_WORD_LANE_1 :: CLOCK_PAD_DISABLE :: dm_pad_dis [02:02] */ 11909 #define DDR40_PHY_WORD_LANE_1_CLOCK_PAD_DISABLE_DM_PAD_DIS_MASK 0x00000004 11910 #define DDR40_PHY_WORD_LANE_1_CLOCK_PAD_DISABLE_DM_PAD_DIS_ALIGN 0 11911 #define DDR40_PHY_WORD_LANE_1_CLOCK_PAD_DISABLE_DM_PAD_DIS_BITS 1 11912 #define DDR40_PHY_WORD_LANE_1_CLOCK_PAD_DISABLE_DM_PAD_DIS_SHIFT 2 11913 11914 /* DDR40_PHY_WORD_LANE_1 :: CLOCK_PAD_DISABLE :: clk1_pad_dis [01:01] */ 11915 #define DDR40_PHY_WORD_LANE_1_CLOCK_PAD_DISABLE_CLK1_PAD_DIS_MASK 0x00000002 11916 #define DDR40_PHY_WORD_LANE_1_CLOCK_PAD_DISABLE_CLK1_PAD_DIS_ALIGN 0 11917 #define DDR40_PHY_WORD_LANE_1_CLOCK_PAD_DISABLE_CLK1_PAD_DIS_BITS 1 11918 #define DDR40_PHY_WORD_LANE_1_CLOCK_PAD_DISABLE_CLK1_PAD_DIS_SHIFT 1 11919 11920 /* DDR40_PHY_WORD_LANE_1 :: CLOCK_PAD_DISABLE :: clk0_pad_dis [00:00] */ 11921 #define DDR40_PHY_WORD_LANE_1_CLOCK_PAD_DISABLE_CLK0_PAD_DIS_MASK 0x00000001 11922 #define DDR40_PHY_WORD_LANE_1_CLOCK_PAD_DISABLE_CLK0_PAD_DIS_ALIGN 0 11923 #define DDR40_PHY_WORD_LANE_1_CLOCK_PAD_DISABLE_CLK0_PAD_DIS_BITS 1 11924 #define DDR40_PHY_WORD_LANE_1_CLOCK_PAD_DISABLE_CLK0_PAD_DIS_SHIFT 0 11925 11926 11927 /**************************************************************************** 11928 * DDR40_PHY_WORD_LANE_1 :: WR_PREAMBLE_MODE 11929 */ 11930 /* DDR40_PHY_WORD_LANE_1 :: WR_PREAMBLE_MODE :: reserved0 [31:02] */ 11931 #define DDR40_PHY_WORD_LANE_1_WR_PREAMBLE_MODE_RESERVED0_MASK 0xfffffffc 11932 #define DDR40_PHY_WORD_LANE_1_WR_PREAMBLE_MODE_RESERVED0_ALIGN 0 11933 #define DDR40_PHY_WORD_LANE_1_WR_PREAMBLE_MODE_RESERVED0_BITS 30 11934 #define DDR40_PHY_WORD_LANE_1_WR_PREAMBLE_MODE_RESERVED0_SHIFT 2 11935 11936 /* DDR40_PHY_WORD_LANE_1 :: WR_PREAMBLE_MODE :: long [01:01] */ 11937 #define DDR40_PHY_WORD_LANE_1_WR_PREAMBLE_MODE_LONG_MASK 0x00000002 11938 #define DDR40_PHY_WORD_LANE_1_WR_PREAMBLE_MODE_LONG_ALIGN 0 11939 #define DDR40_PHY_WORD_LANE_1_WR_PREAMBLE_MODE_LONG_BITS 1 11940 #define DDR40_PHY_WORD_LANE_1_WR_PREAMBLE_MODE_LONG_SHIFT 1 11941 11942 /* DDR40_PHY_WORD_LANE_1 :: WR_PREAMBLE_MODE :: mode [00:00] */ 11943 #define DDR40_PHY_WORD_LANE_1_WR_PREAMBLE_MODE_MODE_MASK 0x00000001 11944 #define DDR40_PHY_WORD_LANE_1_WR_PREAMBLE_MODE_MODE_ALIGN 0 11945 #define DDR40_PHY_WORD_LANE_1_WR_PREAMBLE_MODE_MODE_BITS 1 11946 #define DDR40_PHY_WORD_LANE_1_WR_PREAMBLE_MODE_MODE_SHIFT 0 11947 11948 11949 /**************************************************************************** 11950 * DDR40_PHY_WORD_LANE_1 :: PHYBIST_VDL_ADJ 11951 */ 11952 /* DDR40_PHY_WORD_LANE_1 :: PHYBIST_VDL_ADJ :: reserved0 [31:29] */ 11953 #define DDR40_PHY_WORD_LANE_1_PHYBIST_VDL_ADJ_RESERVED0_MASK 0xe0000000 11954 #define DDR40_PHY_WORD_LANE_1_PHYBIST_VDL_ADJ_RESERVED0_ALIGN 0 11955 #define DDR40_PHY_WORD_LANE_1_PHYBIST_VDL_ADJ_RESERVED0_BITS 3 11956 #define DDR40_PHY_WORD_LANE_1_PHYBIST_VDL_ADJ_RESERVED0_SHIFT 29 11957 11958 /* DDR40_PHY_WORD_LANE_1 :: PHYBIST_VDL_ADJ :: dq1_vdl_adj [28:24] */ 11959 #define DDR40_PHY_WORD_LANE_1_PHYBIST_VDL_ADJ_DQ1_VDL_ADJ_MASK 0x1f000000 11960 #define DDR40_PHY_WORD_LANE_1_PHYBIST_VDL_ADJ_DQ1_VDL_ADJ_ALIGN 0 11961 #define DDR40_PHY_WORD_LANE_1_PHYBIST_VDL_ADJ_DQ1_VDL_ADJ_BITS 5 11962 #define DDR40_PHY_WORD_LANE_1_PHYBIST_VDL_ADJ_DQ1_VDL_ADJ_SHIFT 24 11963 11964 /* DDR40_PHY_WORD_LANE_1 :: PHYBIST_VDL_ADJ :: reserved1 [23:21] */ 11965 #define DDR40_PHY_WORD_LANE_1_PHYBIST_VDL_ADJ_RESERVED1_MASK 0x00e00000 11966 #define DDR40_PHY_WORD_LANE_1_PHYBIST_VDL_ADJ_RESERVED1_ALIGN 0 11967 #define DDR40_PHY_WORD_LANE_1_PHYBIST_VDL_ADJ_RESERVED1_BITS 3 11968 #define DDR40_PHY_WORD_LANE_1_PHYBIST_VDL_ADJ_RESERVED1_SHIFT 21 11969 11970 /* DDR40_PHY_WORD_LANE_1 :: PHYBIST_VDL_ADJ :: dq0_vdl_adj [20:16] */ 11971 #define DDR40_PHY_WORD_LANE_1_PHYBIST_VDL_ADJ_DQ0_VDL_ADJ_MASK 0x001f0000 11972 #define DDR40_PHY_WORD_LANE_1_PHYBIST_VDL_ADJ_DQ0_VDL_ADJ_ALIGN 0 11973 #define DDR40_PHY_WORD_LANE_1_PHYBIST_VDL_ADJ_DQ0_VDL_ADJ_BITS 5 11974 #define DDR40_PHY_WORD_LANE_1_PHYBIST_VDL_ADJ_DQ0_VDL_ADJ_SHIFT 16 11975 11976 /* DDR40_PHY_WORD_LANE_1 :: PHYBIST_VDL_ADJ :: reserved2 [15:13] */ 11977 #define DDR40_PHY_WORD_LANE_1_PHYBIST_VDL_ADJ_RESERVED2_MASK 0x0000e000 11978 #define DDR40_PHY_WORD_LANE_1_PHYBIST_VDL_ADJ_RESERVED2_ALIGN 0 11979 #define DDR40_PHY_WORD_LANE_1_PHYBIST_VDL_ADJ_RESERVED2_BITS 3 11980 #define DDR40_PHY_WORD_LANE_1_PHYBIST_VDL_ADJ_RESERVED2_SHIFT 13 11981 11982 /* DDR40_PHY_WORD_LANE_1 :: PHYBIST_VDL_ADJ :: dqs1_vdl_adj [12:08] */ 11983 #define DDR40_PHY_WORD_LANE_1_PHYBIST_VDL_ADJ_DQS1_VDL_ADJ_MASK 0x00001f00 11984 #define DDR40_PHY_WORD_LANE_1_PHYBIST_VDL_ADJ_DQS1_VDL_ADJ_ALIGN 0 11985 #define DDR40_PHY_WORD_LANE_1_PHYBIST_VDL_ADJ_DQS1_VDL_ADJ_BITS 5 11986 #define DDR40_PHY_WORD_LANE_1_PHYBIST_VDL_ADJ_DQS1_VDL_ADJ_SHIFT 8 11987 11988 /* DDR40_PHY_WORD_LANE_1 :: PHYBIST_VDL_ADJ :: reserved3 [07:05] */ 11989 #define DDR40_PHY_WORD_LANE_1_PHYBIST_VDL_ADJ_RESERVED3_MASK 0x000000e0 11990 #define DDR40_PHY_WORD_LANE_1_PHYBIST_VDL_ADJ_RESERVED3_ALIGN 0 11991 #define DDR40_PHY_WORD_LANE_1_PHYBIST_VDL_ADJ_RESERVED3_BITS 3 11992 #define DDR40_PHY_WORD_LANE_1_PHYBIST_VDL_ADJ_RESERVED3_SHIFT 5 11993 11994 /* DDR40_PHY_WORD_LANE_1 :: PHYBIST_VDL_ADJ :: dqs0_vdl_adj [04:00] */ 11995 #define DDR40_PHY_WORD_LANE_1_PHYBIST_VDL_ADJ_DQS0_VDL_ADJ_MASK 0x0000001f 11996 #define DDR40_PHY_WORD_LANE_1_PHYBIST_VDL_ADJ_DQS0_VDL_ADJ_ALIGN 0 11997 #define DDR40_PHY_WORD_LANE_1_PHYBIST_VDL_ADJ_DQS0_VDL_ADJ_BITS 5 11998 #define DDR40_PHY_WORD_LANE_1_PHYBIST_VDL_ADJ_DQS0_VDL_ADJ_SHIFT 0 11999 12000 12001 /**************************************************************************** 12002 * Datatype Definitions. 12003 */ 12004 #endif /* #ifndef DDR40_H__ */ 12005 12006 /* End of File */ 12007