openbcm

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ddr34.h (862283B)

      1 /*
      2  * 
      3  * 
      4  * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file.
      5  * 
      6  * Copyright 2007-2019 Broadcom Inc. All rights reserved.
      7  *
      8  * THIS SOFTWARE MAY ONLY BE USED SUBJECT TO AN EXECUTED SOFTWARE LICENSE
      9  * AGREEMENT  BETWEEN THE USER AND BROADCOM.  YOU HAVE NO RIGHT TO USE OR
     10  * EXPLOIT THIS MATERIAL EXCEPT SUBJECT TO THE TERMS OF SUCH AN AGREEMENT.
     11  *
     12  * $brcm_Workfile: $
     13  * $brcm_Revision: $
     14  * $brcm_Date: $
     15  *
     16  * Module Description:
     17  *                     DO NOT EDIT THIS FILE DIRECTLY
     18  *
     19  *
     20  * Revision History:
     21  *
     22  * $brcm_Log: $
     23  */
     24 
     25 #ifndef DDR34_H__
     26 #define DDR34_H__
     27 
     28 /**
     29  * m = memory, c = core, r = register, f = field, d = data.
     30  */
     31 #if !defined(GET_FIELD) && !defined(SET_FIELD)
     32 #define BRCM_ALIGN(c,r,f)   DDR34_PHY_FIELDS_TABLE(c##_##r##r_##f, 1)
     33 #define BRCM_BITS(c,r,f)    DDR34_PHY_FIELDS_TABLE(c##_##r##r_##f, 2)
     34 #define BRCM_MASK(c,r,f)    DDR34_PHY_FIELDS_TABLE(c##_##r##r_##f, 0)
     35 #define BRCM_SHIFT(c,r,f)   DDR34_PHY_FIELDS_TABLE(c##_##r##r_##f, 3)
     36 
     37 #define GET_FIELD(m,c,r,f) \
     38 	((((m) & BRCM_MASK(c,r,f)) >> BRCM_SHIFT(c,r,f)) << BRCM_ALIGN(c,r,f))
     39 
     40 #define SET_FIELD(m,c,r,f,d) \
     41 	((m) = (((m) & ~BRCM_MASK(c,r,f)) | ((((d) >> BRCM_ALIGN(c,r,f)) << \
     42 	 BRCM_SHIFT(c,r,f)) & BRCM_MASK(c,r,f))) \
     43 	)
     44 #endif /* GET & SET */
     45 
     46 
     47 #define DDR34_PHY_REGS_TABLE(_regs) _regs_tbl[_regs]
     48 #define DDR34_PHY_FIELDS_TABLE(_fields, _t) _fields_tbl[(_fields << 2) + _t]
     49 
     50 #include "phy_and28_e0.h"
     51 #include "phy_and28_f0.h"
     52 
     53 /*******************************************************************************
     54  */
     55 typedef enum ddr34_phy_regs_e {
     56     DDR34_PHY_CONTROL_REGS_REVISIONr,
     57     DDR34_PHY_CONTROL_REGS_PLL_STATUSr,
     58     DDR34_PHY_CONTROL_REGS_PLL_CONFIGr,
     59     DDR34_PHY_CONTROL_REGS_PLL_CONTROL1r,
     60     DDR34_PHY_CONTROL_REGS_PLL_CONTROL2r,
     61     DDR34_PHY_CONTROL_REGS_PLL_CONTROL3r,
     62     DDR34_PHY_CONTROL_REGS_PLL_DIVIDERSr,
     63     DDR34_PHY_CONTROL_REGS_PLL_FRAC_DIVIDERr,
     64     DDR34_PHY_CONTROL_REGS_PLL_SS_CONTROLr,
     65     DDR34_PHY_CONTROL_REGS_PLL_SS_LIMITr,
     66     DDR34_PHY_CONTROL_REGS_AUX_CONTROLr,
     67     DDR34_PHY_CONTROL_REGS_IDLE_PAD_CONTROLr,
     68     DDR34_PHY_CONTROL_REGS_IDLE_PAD_ENABLE0r,
     69     DDR34_PHY_CONTROL_REGS_IDLE_PAD_ENABLE1r,
     70     DDR34_PHY_CONTROL_REGS_DRIVE_PAD_CTLr,
     71     DDR34_PHY_CONTROL_REGS_STATIC_PAD_CTLr,
     72     DDR34_PHY_CONTROL_REGS_DRAM_CONFIGr,
     73     DDR34_PHY_CONTROL_REGS_DRAM_TIMING1r,
     74     DDR34_PHY_CONTROL_REGS_DRAM_TIMING2r,
     75     DDR34_PHY_CONTROL_REGS_DRAM_TIMING3r,
     76     DDR34_PHY_CONTROL_REGS_DRAM_TIMING4r,
     77     DDR34_PHY_CONTROL_REGS_VDL_CALIBRATEr,
     78     DDR34_PHY_CONTROL_REGS_VDL_CALIB_STATUS1r,
     79     DDR34_PHY_CONTROL_REGS_VDL_CALIB_STATUS2r,
     80     DDR34_PHY_CONTROL_REGS_VDL_MONITOR_CONTROLr,
     81     DDR34_PHY_CONTROL_REGS_VDL_MONITOR_REFr,
     82     DDR34_PHY_CONTROL_REGS_VDL_MONITOR_STATUSr,
     83     DDR34_PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDEr,
     84     DDR34_PHY_CONTROL_REGS_VDL_MONITOR_OUT_CONTROLr,
     85     DDR34_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUSr,
     86     DDR34_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_CLEARr,
     87     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD00r,
     88     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD01r,
     89     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD02r,
     90     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD03r,
     91     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD04r,
     92     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD05r,
     93     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD06r,
     94     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD07r,
     95     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD08r,
     96     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD09r,
     97     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD10r,
     98     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD11r,
     99     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD12r,
    100     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD13r,
    101     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD14r,
    102     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD15r,
    103     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_BA0r,
    104     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_BA1r,
    105     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_BA2r,
    106     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AUX0r,
    107     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AUX1r,
    108     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AUX2r,
    109     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_CS0r,
    110     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_CS1r,
    111     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_PARr,
    112     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_RAS_Nr,
    113     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_CAS_Nr,
    114     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_CKEr,
    115     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_RST_Nr,
    116     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_ODTr,
    117     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_WE_Nr,
    118     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_Pr,
    119     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_Nr,
    120     DDR34_PHY_CONTROL_REGS_VDL_CLK_CONTROLr,
    121     DDR34_PHY_CONTROL_REGS_VDL_LDE_CONTROLr,
    122     DDR34_PHY_CONTROL_REGS_REFRESHr,
    123     DDR34_PHY_CONTROL_REGS_UPDATE_VDLr,
    124     DDR34_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1r,
    125     DDR34_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2r,
    126     DDR34_PHY_CONTROL_REGS_COMMAND_REG1r,
    127     DDR34_PHY_CONTROL_REGS_COMMAND_AUX_REG1r,
    128     DDR34_PHY_CONTROL_REGS_COMMAND_REG2r,
    129     DDR34_PHY_CONTROL_REGS_COMMAND_AUX_REG2r,
    130     DDR34_PHY_CONTROL_REGS_COMMAND_REG3r,
    131     DDR34_PHY_CONTROL_REGS_COMMAND_AUX_REG3r,
    132     DDR34_PHY_CONTROL_REGS_COMMAND_REG4r,
    133     DDR34_PHY_CONTROL_REGS_COMMAND_AUX_REG4r,
    134     DDR34_PHY_CONTROL_REGS_COMMAND_REG_TIMERr,
    135     DDR34_PHY_CONTROL_REGS_MODE_REG0r,
    136     DDR34_PHY_CONTROL_REGS_MODE_REG1r,
    137     DDR34_PHY_CONTROL_REGS_MODE_REG2r,
    138     DDR34_PHY_CONTROL_REGS_MODE_REG3r,
    139     DDR34_PHY_CONTROL_REGS_MODE_REG4r,
    140     DDR34_PHY_CONTROL_REGS_MODE_REG5r,
    141     DDR34_PHY_CONTROL_REGS_MODE_REG6r,
    142     DDR34_PHY_CONTROL_REGS_MODE_REG7r,
    143     DDR34_PHY_CONTROL_REGS_MODE_REG8r,
    144     DDR34_PHY_CONTROL_REGS_MODE_REG15r,
    145     DDR34_PHY_CONTROL_REGS_MODE_REG63r,
    146     DDR34_PHY_CONTROL_REGS_ALERT_CLEARr,
    147     DDR34_PHY_CONTROL_REGS_ALERT_STATUSr,
    148     DDR34_PHY_CONTROL_REGS_CA_PARITYr,
    149     DDR34_PHY_CONTROL_REGS_CA_PLAYBACK_CONTROLr,
    150     DDR34_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS0r,
    151     DDR34_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS1r,
    152     DDR34_PHY_CONTROL_REGS_WRITE_LEVELING_CONTROLr,
    153     DDR34_PHY_CONTROL_REGS_WRITE_LEVELING_STATUSr,
    154     DDR34_PHY_CONTROL_REGS_READ_ENABLE_CONTROLr,
    155     DDR34_PHY_CONTROL_REGS_READ_ENABLE_STATUSr,
    156     DDR34_PHY_CONTROL_REGS_TRAFFIC_GEN_LFSR_SEEDr,
    157     DDR34_PHY_CONTROL_REGS_TRAFFIC_GEN_ADDRESS1r,
    158     DDR34_PHY_CONTROL_REGS_TRAFFIC_GEN_ADDRESS2r,
    159     DDR34_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROLr,
    160     DDR34_PHY_CONTROL_REGS_TRAFFIC_GEN_DATA_CONTROLr,
    161     DDR34_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_MASKr,
    162     DDR34_PHY_CONTROL_REGS_TRAFFIC_GEN_ECC_DQ_MASKr,
    163     DDR34_PHY_CONTROL_REGS_TRAFFIC_GEN_STATUSr,
    164     DDR34_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUSr,
    165     DDR34_PHY_CONTROL_REGS_TRAFFIC_GEN_ECC_STATUSr,
    166     DDR34_PHY_CONTROL_REGS_TRAFFIC_GEN_ERR_CNT_CONTROLr,
    167     DDR34_PHY_CONTROL_REGS_TRAFFIC_GEN_ERR_CNT_STATUSr,
    168     DDR34_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROLr,
    169     DDR34_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUSr,
    170     DDR34_PHY_CONTROL_REGS_VIRTUAL_VTT_CONNECTIONSr,
    171     DDR34_PHY_CONTROL_REGS_VIRTUAL_VTT_OVERRIDEr,
    172     DDR34_PHY_CONTROL_REGS_VREF_DAC_CONTROLr,
    173     DDR34_PHY_CONTROL_REGS_PHYBIST_CNTRLr,
    174     DDR34_PHY_CONTROL_REGS_PHYBIST_SEEDr,
    175     DDR34_PHY_CONTROL_REGS_PHYBIST_STATUSr,
    176     DDR34_PHY_CONTROL_REGS_PHYBIST_CTL_STATUSr,
    177     DDR34_PHY_CONTROL_REGS_PHYBIST_BL0_STATUSr,
    178     DDR34_PHY_CONTROL_REGS_PHYBIST_BL1_STATUSr,
    179     DDR34_PHY_CONTROL_REGS_PHYBIST_BL2_STATUSr,
    180     DDR34_PHY_CONTROL_REGS_PHYBIST_BL3_STATUSr,
    181     DDR34_PHY_CONTROL_REGS_PHYBIST_BL4_STATUSr,
    182     DDR34_PHY_CONTROL_REGS_STANDBY_CONTROLr,
    183     DDR34_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLEr,
    184     DDR34_PHY_CONTROL_REGS_DEBUG_MUX_CONTROLr,
    185     DDR34_PHY_CONTROL_REGS_DFI_CNTRLr,
    186     DDR34_PHY_CONTROL_REGS_WRITE_ODT_CNTRLr,
    187     DDR34_PHY_CONTROL_REGS_ABI_PAR_CNTRLr,
    188     DDR34_PHY_CONTROL_REGS_ZQ_CALr,
    189     DDR34_PHY_CONTROL_REGS_AC_SPARE_REGr,
    190     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_Pr,
    191     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_Nr,
    192     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0r,
    193     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1r,
    194     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2r,
    195     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3r,
    196     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4r,
    197     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5r,
    198     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6r,
    199     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7r,
    200     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DMr,
    201     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_EDCr,
    202     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSPr,
    203     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSNr,
    204     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0Pr,
    205     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0Nr,
    206     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1Pr,
    207     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1Nr,
    208     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2Pr,
    209     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2Nr,
    210     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3Pr,
    211     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3Nr,
    212     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4Pr,
    213     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4Nr,
    214     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5Pr,
    215     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5Nr,
    216     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6Pr,
    217     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6Nr,
    218     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7Pr,
    219     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7Nr,
    220     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMPr,
    221     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMNr,
    222     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCPr,
    223     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCNr,
    224     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0r,
    225     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1r,
    226     DDR34_PHY_BYTE_LANE_0_VDL_CLK_CONTROLr,
    227     DDR34_PHY_BYTE_LANE_0_VDL_LDE_CONTROLr,
    228     DDR34_PHY_BYTE_LANE_0_RD_EN_DLY_CYCr,
    229     DDR34_PHY_BYTE_LANE_0_WR_CHAN_DLY_CYCr,
    230     DDR34_PHY_BYTE_LANE_0_READ_CONTROLr,
    231     DDR34_PHY_BYTE_LANE_0_READ_FIFO_ADDRr,
    232     DDR34_PHY_BYTE_LANE_0_READ_FIFO_DATAr,
    233     DDR34_PHY_BYTE_LANE_0_READ_FIFO_DM_DBIr,
    234     DDR34_PHY_BYTE_LANE_0_READ_FIFO_STATUSr,
    235     DDR34_PHY_BYTE_LANE_0_READ_FIFO_CLEARr,
    236     DDR34_PHY_BYTE_LANE_0_IDLE_PAD_CONTROLr,
    237     DDR34_PHY_BYTE_LANE_0_DRIVE_PAD_CTLr,
    238     DDR34_PHY_BYTE_LANE_0_RD_EN_DRIVE_PAD_CTLr,
    239     DDR34_PHY_BYTE_LANE_0_STATIC_PAD_CTLr,
    240     DDR34_PHY_BYTE_LANE_0_WR_PREAMBLE_MODEr,
    241     DDR34_PHY_BYTE_LANE_0_ODT_CONTROLr,
    242     DDR34_PHY_BYTE_LANE_0_EDC_DPD_CONTROLr,
    243     DDR34_PHY_BYTE_LANE_0_EDC_DPD_STATUSr,
    244     DDR34_PHY_BYTE_LANE_0_EDC_DPD_OUT_CONTROLr,
    245     DDR34_PHY_BYTE_LANE_0_EDC_DPD_OUT_STATUSr,
    246     DDR34_PHY_BYTE_LANE_0_EDC_DPD_OUT_STATUS_CLEARr,
    247     DDR34_PHY_BYTE_LANE_0_EDC_CRC_CONTROLr,
    248     DDR34_PHY_BYTE_LANE_0_EDC_CRC_STATUSr,
    249     DDR34_PHY_BYTE_LANE_0_EDC_CRC_COUNTr,
    250     DDR34_PHY_BYTE_LANE_0_EDC_CRC_STATUS_CLEARr,
    251     DDR34_PHY_BYTE_LANE_0_BL_SPARE_REGr,
    252     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_Pr,
    253     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_Nr,
    254     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0r,
    255     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1r,
    256     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2r,
    257     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3r,
    258     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4r,
    259     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5r,
    260     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6r,
    261     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7r,
    262     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DMr,
    263     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_EDCr,
    264     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSPr,
    265     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSNr,
    266     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0Pr,
    267     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0Nr,
    268     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1Pr,
    269     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1Nr,
    270     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2Pr,
    271     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2Nr,
    272     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3Pr,
    273     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3Nr,
    274     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4Pr,
    275     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4Nr,
    276     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5Pr,
    277     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5Nr,
    278     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6Pr,
    279     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6Nr,
    280     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7Pr,
    281     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7Nr,
    282     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMPr,
    283     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMNr,
    284     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCPr,
    285     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCNr,
    286     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0r,
    287     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1r,
    288     DDR34_PHY_BYTE_LANE_1_VDL_CLK_CONTROLr,
    289     DDR34_PHY_BYTE_LANE_1_VDL_LDE_CONTROLr,
    290     DDR34_PHY_BYTE_LANE_1_RD_EN_DLY_CYCr,
    291     DDR34_PHY_BYTE_LANE_1_WR_CHAN_DLY_CYCr,
    292     DDR34_PHY_BYTE_LANE_1_READ_CONTROLr,
    293     DDR34_PHY_BYTE_LANE_1_READ_FIFO_ADDRr,
    294     DDR34_PHY_BYTE_LANE_1_READ_FIFO_DATAr,
    295     DDR34_PHY_BYTE_LANE_1_READ_FIFO_DM_DBIr,
    296     DDR34_PHY_BYTE_LANE_1_READ_FIFO_STATUSr,
    297     DDR34_PHY_BYTE_LANE_1_READ_FIFO_CLEARr,
    298     DDR34_PHY_BYTE_LANE_1_IDLE_PAD_CONTROLr,
    299     DDR34_PHY_BYTE_LANE_1_DRIVE_PAD_CTLr,
    300     DDR34_PHY_BYTE_LANE_1_RD_EN_DRIVE_PAD_CTLr,
    301     DDR34_PHY_BYTE_LANE_1_STATIC_PAD_CTLr,
    302     DDR34_PHY_BYTE_LANE_1_WR_PREAMBLE_MODEr,
    303     DDR34_PHY_BYTE_LANE_1_ODT_CONTROLr,
    304     DDR34_PHY_BYTE_LANE_1_EDC_DPD_CONTROLr,
    305     DDR34_PHY_BYTE_LANE_1_EDC_DPD_STATUSr,
    306     DDR34_PHY_BYTE_LANE_1_EDC_DPD_OUT_CONTROLr,
    307     DDR34_PHY_BYTE_LANE_1_EDC_DPD_OUT_STATUSr,
    308     DDR34_PHY_BYTE_LANE_1_EDC_DPD_OUT_STATUS_CLEARr,
    309     DDR34_PHY_BYTE_LANE_1_EDC_CRC_CONTROLr,
    310     DDR34_PHY_BYTE_LANE_1_EDC_CRC_STATUSr,
    311     DDR34_PHY_BYTE_LANE_1_EDC_CRC_COUNTr,
    312     DDR34_PHY_BYTE_LANE_1_EDC_CRC_STATUS_CLEARr,
    313     DDR34_PHY_BYTE_LANE_1_BL_SPARE_REGr,
    314     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_Pr,
    315     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_Nr,
    316     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ0r,
    317     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ1r,
    318     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ2r,
    319     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ3r,
    320     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ4r,
    321     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ5r,
    322     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ6r,
    323     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ7r,
    324     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DMr,
    325     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_EDCr,
    326     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSPr,
    327     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSNr,
    328     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0Pr,
    329     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0Nr,
    330     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1Pr,
    331     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1Nr,
    332     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2Pr,
    333     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2Nr,
    334     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3Pr,
    335     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3Nr,
    336     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4Pr,
    337     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4Nr,
    338     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5Pr,
    339     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5Nr,
    340     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6Pr,
    341     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6Nr,
    342     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7Pr,
    343     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7Nr,
    344     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMPr,
    345     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMNr,
    346     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EDCPr,
    347     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EDCNr,
    348     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS0r,
    349     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS1r,
    350     DDR34_PHY_BYTE_LANE_2_VDL_CLK_CONTROLr,
    351     DDR34_PHY_BYTE_LANE_2_VDL_LDE_CONTROLr,
    352     DDR34_PHY_BYTE_LANE_2_RD_EN_DLY_CYCr,
    353     DDR34_PHY_BYTE_LANE_2_WR_CHAN_DLY_CYCr,
    354     DDR34_PHY_BYTE_LANE_2_READ_CONTROLr,
    355     DDR34_PHY_BYTE_LANE_2_READ_FIFO_ADDRr,
    356     DDR34_PHY_BYTE_LANE_2_READ_FIFO_DATAr,
    357     DDR34_PHY_BYTE_LANE_2_READ_FIFO_DM_DBIr,
    358     DDR34_PHY_BYTE_LANE_2_READ_FIFO_STATUSr,
    359     DDR34_PHY_BYTE_LANE_2_READ_FIFO_CLEARr,
    360     DDR34_PHY_BYTE_LANE_2_IDLE_PAD_CONTROLr,
    361     DDR34_PHY_BYTE_LANE_2_DRIVE_PAD_CTLr,
    362     DDR34_PHY_BYTE_LANE_2_RD_EN_DRIVE_PAD_CTLr,
    363     DDR34_PHY_BYTE_LANE_2_STATIC_PAD_CTLr,
    364     DDR34_PHY_BYTE_LANE_2_WR_PREAMBLE_MODEr,
    365     DDR34_PHY_BYTE_LANE_2_ODT_CONTROLr,
    366     DDR34_PHY_BYTE_LANE_2_EDC_DPD_CONTROLr,
    367     DDR34_PHY_BYTE_LANE_2_EDC_DPD_STATUSr,
    368     DDR34_PHY_BYTE_LANE_2_EDC_DPD_OUT_CONTROLr,
    369     DDR34_PHY_BYTE_LANE_2_EDC_DPD_OUT_STATUSr,
    370     DDR34_PHY_BYTE_LANE_2_EDC_DPD_OUT_STATUS_CLEARr,
    371     DDR34_PHY_BYTE_LANE_2_EDC_CRC_CONTROLr,
    372     DDR34_PHY_BYTE_LANE_2_EDC_CRC_STATUSr,
    373     DDR34_PHY_BYTE_LANE_2_EDC_CRC_COUNTr,
    374     DDR34_PHY_BYTE_LANE_2_EDC_CRC_STATUS_CLEARr,
    375     DDR34_PHY_BYTE_LANE_2_BL_SPARE_REGr,
    376     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_Pr,
    377     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_Nr,
    378     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ0r,
    379     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ1r,
    380     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ2r,
    381     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ3r,
    382     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ4r,
    383     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ5r,
    384     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ6r,
    385     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ7r,
    386     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DMr,
    387     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_EDCr,
    388     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSPr,
    389     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSNr,
    390     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0Pr,
    391     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0Nr,
    392     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1Pr,
    393     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1Nr,
    394     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2Pr,
    395     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2Nr,
    396     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3Pr,
    397     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3Nr,
    398     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4Pr,
    399     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4Nr,
    400     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5Pr,
    401     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5Nr,
    402     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6Pr,
    403     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6Nr,
    404     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7Pr,
    405     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7Nr,
    406     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMPr,
    407     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMNr,
    408     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EDCPr,
    409     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EDCNr,
    410     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS0r,
    411     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS1r,
    412     DDR34_PHY_BYTE_LANE_3_VDL_CLK_CONTROLr,
    413     DDR34_PHY_BYTE_LANE_3_VDL_LDE_CONTROLr,
    414     DDR34_PHY_BYTE_LANE_3_RD_EN_DLY_CYCr,
    415     DDR34_PHY_BYTE_LANE_3_WR_CHAN_DLY_CYCr,
    416     DDR34_PHY_BYTE_LANE_3_READ_CONTROLr,
    417     DDR34_PHY_BYTE_LANE_3_READ_FIFO_ADDRr,
    418     DDR34_PHY_BYTE_LANE_3_READ_FIFO_DATAr,
    419     DDR34_PHY_BYTE_LANE_3_READ_FIFO_DM_DBIr,
    420     DDR34_PHY_BYTE_LANE_3_READ_FIFO_STATUSr,
    421     DDR34_PHY_BYTE_LANE_3_READ_FIFO_CLEARr,
    422     DDR34_PHY_BYTE_LANE_3_IDLE_PAD_CONTROLr,
    423     DDR34_PHY_BYTE_LANE_3_DRIVE_PAD_CTLr,
    424     DDR34_PHY_BYTE_LANE_3_RD_EN_DRIVE_PAD_CTLr,
    425     DDR34_PHY_BYTE_LANE_3_STATIC_PAD_CTLr,
    426     DDR34_PHY_BYTE_LANE_3_WR_PREAMBLE_MODEr,
    427     DDR34_PHY_BYTE_LANE_3_ODT_CONTROLr,
    428     DDR34_PHY_BYTE_LANE_3_EDC_DPD_CONTROLr,
    429     DDR34_PHY_BYTE_LANE_3_EDC_DPD_STATUSr,
    430     DDR34_PHY_BYTE_LANE_3_EDC_DPD_OUT_CONTROLr,
    431     DDR34_PHY_BYTE_LANE_3_EDC_DPD_OUT_STATUSr,
    432     DDR34_PHY_BYTE_LANE_3_EDC_DPD_OUT_STATUS_CLEARr,
    433     DDR34_PHY_BYTE_LANE_3_EDC_CRC_CONTROLr,
    434     DDR34_PHY_BYTE_LANE_3_EDC_CRC_STATUSr,
    435     DDR34_PHY_BYTE_LANE_3_EDC_CRC_COUNTr,
    436     DDR34_PHY_BYTE_LANE_3_EDC_CRC_STATUS_CLEARr,
    437     DDR34_PHY_BYTE_LANE_3_BL_SPARE_REGr,
    438     DDR34_PHY_CONTROL_REGS_DRIVE_PAD_CTL_2Tr,
    439     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CKr,
    440     DDR34_PHY_CONTROL_REGS_CMD_CYC_DLYr,
    441     DDR34_PHY_CONTROL_REGS_ALERT_DFIr,
    442     DDR34_PHY_CONTROL_REGS_PHYBIST_CA_MASKr,
    443     DDR34_PHY_CONTROL_REGS_PHYBIST_DQ_MASK1r,
    444     DDR34_PHY_CONTROL_REGS_PHYBIST_DQ_MASK2r,
    445     DDR34_PHY_CONTROL_REGS_ZQ_CAL2r,
    446     DDR34_PHY_CONTROL_REGS_RO_PROC_MON_CTLr,
    447     DDR34_PHY_CONTROL_REGS_RO_PROC_MON_STATUSr,
    448     DDR34_PHY_CONTROL_REGS_CK_DRIVE_PAD_CTLr,
    449     DDR34_PHY_CONTROL_REGS_BYTE_LANE_ALIGN_MASKSr,
    450     DDR34_PHY_CONTROL_REGS_CLOCK_IDLEr,
    451     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQSr,
    452     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_ALERTr,
    453     DDR34_PHY_BYTE_LANE_0_DQSP_DRIVE_PAD_CTLr,
    454     DDR34_PHY_BYTE_LANE_0_DQSN_DRIVE_PAD_CTLr,
    455     DDR34_PHY_BYTE_LANE_0_ALERT_DRIVE_PAD_CTLr,
    456     DDR34_PHY_BYTE_LANE_0_CLOCK_ENABLEr,
    457     DDR34_PHY_BYTE_LANE_0_CLOCK_IDLEr,
    458     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQSr,
    459     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_ALERTr,
    460     DDR34_PHY_BYTE_LANE_1_DQSP_DRIVE_PAD_CTLr,
    461     DDR34_PHY_BYTE_LANE_1_DQSN_DRIVE_PAD_CTLr,
    462     DDR34_PHY_BYTE_LANE_1_ALERT_DRIVE_PAD_CTLr,
    463     DDR34_PHY_BYTE_LANE_1_CLOCK_ENABLEr,
    464     DDR34_PHY_BYTE_LANE_1_CLOCK_IDLEr,
    465     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQSr,
    466     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_ALERTr,
    467     DDR34_PHY_BYTE_LANE_2_DQSP_DRIVE_PAD_CTLr,
    468     DDR34_PHY_BYTE_LANE_2_DQSN_DRIVE_PAD_CTLr,
    469     DDR34_PHY_BYTE_LANE_2_ALERT_DRIVE_PAD_CTLr,
    470     DDR34_PHY_BYTE_LANE_2_CLOCK_ENABLEr,
    471     DDR34_PHY_BYTE_LANE_2_CLOCK_IDLEr,
    472     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQSr,
    473     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_ALERTr,
    474     DDR34_PHY_BYTE_LANE_3_DQSP_DRIVE_PAD_CTLr,
    475     DDR34_PHY_BYTE_LANE_3_DQSN_DRIVE_PAD_CTLr,
    476     DDR34_PHY_BYTE_LANE_3_ALERT_DRIVE_PAD_CTLr,
    477     DDR34_PHY_BYTE_LANE_3_CLOCK_ENABLEr,
    478     DDR34_PHY_BYTE_LANE_3_CLOCK_IDLEr,
    479     DDR34_PHY_MAX_REG_INDEX
    480 } ddr34_phy_regs_t;
    481 
    482 /*******************************************************************************
    483  */
    484 typedef enum ddr34_phy_reg_fields_e {
    485     DDR34_PHY_CONTROL_REGS_REVISIONr_RESERVED0,
    486     DDR34_PHY_CONTROL_REGS_REVISIONr_PERFORMANCE,
    487     DDR34_PHY_CONTROL_REGS_REVISIONr_TECHNOLOGY,
    488     DDR34_PHY_CONTROL_REGS_REVISIONr_WB,
    489     DDR34_PHY_CONTROL_REGS_REVISIONr_BITS,
    490     DDR34_PHY_CONTROL_REGS_REVISIONr_MAJOR,
    491     DDR34_PHY_CONTROL_REGS_REVISIONr_MINOR,
    492     DDR34_PHY_CONTROL_REGS_PLL_STATUSr_RESERVED0,
    493     DDR34_PHY_CONTROL_REGS_PLL_STATUSr_LOCK_LOST,
    494     DDR34_PHY_CONTROL_REGS_PLL_STATUSr_CLOCKING_8X,
    495     DDR34_PHY_CONTROL_REGS_PLL_STATUSr_CLOCKING_4X,
    496     DDR34_PHY_CONTROL_REGS_PLL_STATUSr_CLOCKING_2X,
    497     DDR34_PHY_CONTROL_REGS_PLL_STATUSr_STATUS,
    498     DDR34_PHY_CONTROL_REGS_PLL_STATUSr_LOCK,
    499     DDR34_PHY_CONTROL_REGS_PLL_CONFIGr_RESERVED0,
    500     DDR34_PHY_CONTROL_REGS_PLL_CONFIGr_RESERVED_for_eco1,
    501     DDR34_PHY_CONTROL_REGS_PLL_CONFIGr_CK_LDO_REF_CTRL,
    502     DDR34_PHY_CONTROL_REGS_PLL_CONFIGr_CK_LDO_BIAS,
    503     DDR34_PHY_CONTROL_REGS_PLL_CONFIGr_PLL_LDO_REF_SEL,
    504     DDR34_PHY_CONTROL_REGS_PLL_CONFIGr_PLL_LDO_REF_CTRL,
    505     DDR34_PHY_CONTROL_REGS_PLL_CONFIGr_PLL_LDO_BIAS,
    506     DDR34_PHY_CONTROL_REGS_PLL_CONFIGr_HOLD,
    507     DDR34_PHY_CONTROL_REGS_PLL_CONFIGr_ENABLE,
    508     DDR34_PHY_CONTROL_REGS_PLL_CONFIGr_RESERVED2,
    509     DDR34_PHY_CONTROL_REGS_PLL_CONFIGr_FB_OFFSET,
    510     DDR34_PHY_CONTROL_REGS_PLL_CONFIGr_RESERVED3,
    511     DDR34_PHY_CONTROL_REGS_PLL_CONFIGr_RESET_POST_DIV,
    512     DDR34_PHY_CONTROL_REGS_PLL_CONFIGr_RESERVED4,
    513     DDR34_PHY_CONTROL_REGS_PLL_CONFIGr_RESET,
    514     DDR34_PHY_CONTROL_REGS_PLL_CONFIGr_PWRDN,
    515     DDR34_PHY_CONTROL_REGS_PLL_CONTROL1r_RESERVED0,
    516     DDR34_PHY_CONTROL_REGS_PLL_CONTROL1r_I_KP,
    517     DDR34_PHY_CONTROL_REGS_PLL_CONTROL1r_I_KI,
    518     DDR34_PHY_CONTROL_REGS_PLL_CONTROL1r_I_KA,
    519     DDR34_PHY_CONTROL_REGS_PLL_CONTROL2r_VCO_RANGE,
    520     DDR34_PHY_CONTROL_REGS_PLL_CONTROL2r_UNUSED2,
    521     DDR34_PHY_CONTROL_REGS_PLL_CONTROL2r_NDIV_RELOCK,
    522     DDR34_PHY_CONTROL_REGS_PLL_CONTROL2r_FAST_LOCK,
    523     DDR34_PHY_CONTROL_REGS_PLL_CONTROL2r_VCO_FB_DIV2,
    524     DDR34_PHY_CONTROL_REGS_PLL_CONTROL2r_POST_CTRL_RESETB,
    525     DDR34_PHY_CONTROL_REGS_PLL_CONTROL2r_PWM_RATE,
    526     DDR34_PHY_CONTROL_REGS_PLL_CONTROL2r_STAT_MODE,
    527     DDR34_PHY_CONTROL_REGS_PLL_CONTROL2r_UNUSED1,
    528     DDR34_PHY_CONTROL_REGS_PLL_CONTROL2r_STAT_UPDATE,
    529     DDR34_PHY_CONTROL_REGS_PLL_CONTROL2r_STAT_SELECT,
    530     DDR34_PHY_CONTROL_REGS_PLL_CONTROL2r_STAT_RESET,
    531     DDR34_PHY_CONTROL_REGS_PLL_CONTROL2r_DCO_CTRL_BYPASS_ENABLE,
    532     DDR34_PHY_CONTROL_REGS_PLL_CONTROL2r_DCO_CTRL_BYPASS,
    533     DDR34_PHY_CONTROL_REGS_PLL_CONTROL3r_PLL_CONTROL,
    534     DDR34_PHY_CONTROL_REGS_PLL_DIVIDERSr_RESERVED0,
    535     DDR34_PHY_CONTROL_REGS_PLL_DIVIDERSr_MDIV,
    536     DDR34_PHY_CONTROL_REGS_PLL_DIVIDERSr_RESERVED1,
    537     DDR34_PHY_CONTROL_REGS_PLL_DIVIDERSr_PDIV,
    538     DDR34_PHY_CONTROL_REGS_PLL_DIVIDERSr_RESERVED2,
    539     DDR34_PHY_CONTROL_REGS_PLL_DIVIDERSr_NDIV_INT,
    540     DDR34_PHY_CONTROL_REGS_PLL_FRAC_DIVIDERr_RESERVED0,
    541     DDR34_PHY_CONTROL_REGS_PLL_FRAC_DIVIDERr_NDIV_FRAC,
    542     DDR34_PHY_CONTROL_REGS_PLL_SS_CONTROLr_RESERVED0,
    543     DDR34_PHY_CONTROL_REGS_PLL_SS_CONTROLr_SSC_STEP,
    544     DDR34_PHY_CONTROL_REGS_PLL_SS_CONTROLr_RESERVED1,
    545     DDR34_PHY_CONTROL_REGS_PLL_SS_CONTROLr_SSC_MODE,
    546     DDR34_PHY_CONTROL_REGS_PLL_SS_LIMITr_RESERVED0,
    547     DDR34_PHY_CONTROL_REGS_PLL_SS_LIMITr_SSC_LIMIT,
    548     DDR34_PHY_CONTROL_REGS_PLL_SS_LIMITr_RESERVED1,
    549     DDR34_PHY_CONTROL_REGS_AUX_CONTROLr_RESERVED0,
    550     DDR34_PHY_CONTROL_REGS_AUX_CONTROLr_IS_ODT,
    551     DDR34_PHY_CONTROL_REGS_AUX_CONTROLr_RESERVED1,
    552     DDR34_PHY_CONTROL_REGS_AUX_CONTROLr_IS_CS,
    553     DDR34_PHY_CONTROL_REGS_AUX_CONTROLr_RESERVED2,
    554     DDR34_PHY_CONTROL_REGS_AUX_CONTROLr_IS_AD,
    555     DDR34_PHY_CONTROL_REGS_IDLE_PAD_CONTROLr_IDLE,
    556     DDR34_PHY_CONTROL_REGS_IDLE_PAD_CONTROLr_DIB_MODE,
    557     DDR34_PHY_CONTROL_REGS_IDLE_PAD_CONTROLr_RESERVED0,
    558     DDR34_PHY_CONTROL_REGS_IDLE_PAD_CONTROLr_RXENB,
    559     DDR34_PHY_CONTROL_REGS_IDLE_PAD_CONTROLr_IDDQ,
    560     DDR34_PHY_CONTROL_REGS_IDLE_PAD_CONTROLr_DOUT_N,
    561     DDR34_PHY_CONTROL_REGS_IDLE_PAD_CONTROLr_DOUT_P,
    562     DDR34_PHY_CONTROL_REGS_IDLE_PAD_ENABLE0r_RESERVED0,
    563     DDR34_PHY_CONTROL_REGS_IDLE_PAD_ENABLE0r_IO_IDLE_ENABLE,
    564     DDR34_PHY_CONTROL_REGS_IDLE_PAD_ENABLE1r_RESERVED0,
    565     DDR34_PHY_CONTROL_REGS_IDLE_PAD_ENABLE1r_IO_IDLE_ENABLE,
    566     DDR34_PHY_CONTROL_REGS_DRIVE_PAD_CTLr_RESERVED0,
    567     DDR34_PHY_CONTROL_REGS_DRIVE_PAD_CTLr_ADDR_CTL_PD_IDLE_STRENGTH,
    568     DDR34_PHY_CONTROL_REGS_DRIVE_PAD_CTLr_ADDR_CTL_ND_IDLE_STRENGTH,
    569     DDR34_PHY_CONTROL_REGS_DRIVE_PAD_CTLr_ADDR_CTL_PD_TERM_STRENGTH,
    570     DDR34_PHY_CONTROL_REGS_DRIVE_PAD_CTLr_ADDR_CTL_ND_TERM_STRENGTH,
    571     DDR34_PHY_CONTROL_REGS_DRIVE_PAD_CTLr_ADDR_CTL_PD_STRENGTH,
    572     DDR34_PHY_CONTROL_REGS_DRIVE_PAD_CTLr_ADDR_CTL_ND_STRENGTH,
    573     DDR34_PHY_CONTROL_REGS_STATIC_PAD_CTLr_RESERVED0,
    574     DDR34_PHY_CONTROL_REGS_STATIC_PAD_CTLr_AUTO_OEB,
    575     DDR34_PHY_CONTROL_REGS_STATIC_PAD_CTLr_IDDQ_GDDR5,
    576     DDR34_PHY_CONTROL_REGS_STATIC_PAD_CTLr_IDDQ_LPDDR,
    577     DDR34_PHY_CONTROL_REGS_STATIC_PAD_CTLr_IDDQ_CLK1,
    578     DDR34_PHY_CONTROL_REGS_STATIC_PAD_CTLr_IDDQ_CLK0,
    579     DDR34_PHY_CONTROL_REGS_STATIC_PAD_CTLr_IDDQ_ODT,
    580     DDR34_PHY_CONTROL_REGS_STATIC_PAD_CTLr_IDDQ_PAR,
    581     DDR34_PHY_CONTROL_REGS_STATIC_PAD_CTLr_IDDQ_BA,
    582     DDR34_PHY_CONTROL_REGS_STATIC_PAD_CTLr_IDDQ_AUX2,
    583     DDR34_PHY_CONTROL_REGS_STATIC_PAD_CTLr_IDDQ_AUX1,
    584     DDR34_PHY_CONTROL_REGS_STATIC_PAD_CTLr_IDDQ_AUX0,
    585     DDR34_PHY_CONTROL_REGS_STATIC_PAD_CTLr_IDDQ_CS1,
    586     DDR34_PHY_CONTROL_REGS_STATIC_PAD_CTLr_IDDQ_A15,
    587     DDR34_PHY_CONTROL_REGS_STATIC_PAD_CTLr_IDDQ_A14,
    588     DDR34_PHY_CONTROL_REGS_STATIC_PAD_CTLr_IDDQ_A13,
    589     DDR34_PHY_CONTROL_REGS_STATIC_PAD_CTLr_IDDQ_A12,
    590     DDR34_PHY_CONTROL_REGS_STATIC_PAD_CTLr_IDDQ_A11,
    591     DDR34_PHY_CONTROL_REGS_STATIC_PAD_CTLr_IDDQ_A10,
    592     DDR34_PHY_CONTROL_REGS_STATIC_PAD_CTLr_IDDQ_A09,
    593     DDR34_PHY_CONTROL_REGS_STATIC_PAD_CTLr_RESERVED1,
    594     DDR34_PHY_CONTROL_REGS_STATIC_PAD_CTLr_RX_MODE,
    595     DDR34_PHY_CONTROL_REGS_DRAM_CONFIGr_INIT_MODE,
    596     DDR34_PHY_CONTROL_REGS_DRAM_CONFIGr_RESERVED0,
    597     DDR34_PHY_CONTROL_REGS_DRAM_CONFIGr_ECC_ENABLED,
    598     DDR34_PHY_CONTROL_REGS_DRAM_CONFIGr_SPLIT_DQ_BUS,
    599     DDR34_PHY_CONTROL_REGS_DRAM_CONFIGr_BUS16,
    600     DDR34_PHY_CONTROL_REGS_DRAM_CONFIGr_BUS8,
    601     DDR34_PHY_CONTROL_REGS_DRAM_CONFIGr_RESERVED1,
    602     DDR34_PHY_CONTROL_REGS_DRAM_CONFIGr_EDC_MODE,
    603     DDR34_PHY_CONTROL_REGS_DRAM_CONFIGr_RDQS_MODE,
    604     DDR34_PHY_CONTROL_REGS_DRAM_CONFIGr_GROUP_BITS,
    605     DDR34_PHY_CONTROL_REGS_DRAM_CONFIGr_BANK_BITS,
    606     DDR34_PHY_CONTROL_REGS_DRAM_CONFIGr_COL_BITS,
    607     DDR34_PHY_CONTROL_REGS_DRAM_CONFIGr_ROW_BITS,
    608     DDR34_PHY_CONTROL_REGS_DRAM_CONFIGr_DRAM_TYPE,
    609     DDR34_PHY_CONTROL_REGS_DRAM_TIMING1r_TRAS,
    610     DDR34_PHY_CONTROL_REGS_DRAM_TIMING1r_TRRD,
    611     DDR34_PHY_CONTROL_REGS_DRAM_TIMING1r_TRP,
    612     DDR34_PHY_CONTROL_REGS_DRAM_TIMING1r_TRCD,
    613     DDR34_PHY_CONTROL_REGS_DRAM_TIMING2r_TRTP,
    614     DDR34_PHY_CONTROL_REGS_DRAM_TIMING2r_TWR,
    615     DDR34_PHY_CONTROL_REGS_DRAM_TIMING2r_TCWL,
    616     DDR34_PHY_CONTROL_REGS_DRAM_TIMING2r_TCAS,
    617     DDR34_PHY_CONTROL_REGS_DRAM_TIMING3r_RESERVED0,
    618     DDR34_PHY_CONTROL_REGS_DRAM_TIMING3r_TCAL,
    619     DDR34_PHY_CONTROL_REGS_DRAM_TIMING3r_TRTW,
    620     DDR34_PHY_CONTROL_REGS_DRAM_TIMING3r_TWTR,
    621     DDR34_PHY_CONTROL_REGS_DRAM_TIMING3r_TRFC,
    622     DDR34_PHY_CONTROL_REGS_DRAM_TIMING4r_temp,
    623     DDR34_PHY_CONTROL_REGS_VDL_CALIBRATEr_RESERVED0,
    624     DDR34_PHY_CONTROL_REGS_VDL_CALIBRATEr_RESERVED_for_padding1,
    625     DDR34_PHY_CONTROL_REGS_VDL_CALIBRATEr_HALF_STEPS,
    626     DDR34_PHY_CONTROL_REGS_VDL_CALIBRATEr_UPDATE_FAST,
    627     DDR34_PHY_CONTROL_REGS_VDL_CALIBRATEr_UPDATE_REGS,
    628     DDR34_PHY_CONTROL_REGS_VDL_CALIBRATEr_CALIB_FTM2,
    629     DDR34_PHY_CONTROL_REGS_VDL_CALIBRATEr_CALIB_PHYBIST,
    630     DDR34_PHY_CONTROL_REGS_VDL_CALIBRATEr_CALIB_ONCE,
    631     DDR34_PHY_CONTROL_REGS_VDL_CALIB_STATUS1r_RESERVED0,
    632     DDR34_PHY_CONTROL_REGS_VDL_CALIB_STATUS1r_CALIB_TOTAL_STEPS,
    633     DDR34_PHY_CONTROL_REGS_VDL_CALIB_STATUS1r_RESERVED1,
    634     DDR34_PHY_CONTROL_REGS_VDL_CALIB_STATUS1r_CALIB_BUS_ERROR,
    635     DDR34_PHY_CONTROL_REGS_VDL_CALIB_STATUS1r_CALIB_REGS_DONE,
    636     DDR34_PHY_CONTROL_REGS_VDL_CALIB_STATUS1r_CALIB_LOCK_6B,
    637     DDR34_PHY_CONTROL_REGS_VDL_CALIB_STATUS1r_CALIB_LOCK_4B,
    638     DDR34_PHY_CONTROL_REGS_VDL_CALIB_STATUS1r_CALIB_LOCK_2B,
    639     DDR34_PHY_CONTROL_REGS_VDL_CALIB_STATUS1r_CALIB_IDLE,
    640     DDR34_PHY_CONTROL_REGS_VDL_CALIB_STATUS2r_RESERVED0,
    641     DDR34_PHY_CONTROL_REGS_VDL_CALIB_STATUS2r_CALIB_4B_STEPS,
    642     DDR34_PHY_CONTROL_REGS_VDL_CALIB_STATUS2r_RESERVED1,
    643     DDR34_PHY_CONTROL_REGS_VDL_CALIB_STATUS2r_CALIB_2B_STEPS,
    644     DDR34_PHY_CONTROL_REGS_VDL_MONITOR_CONTROLr_RESERVED0,
    645     DDR34_PHY_CONTROL_REGS_VDL_MONITOR_CONTROLr_INTERVAL,
    646     DDR34_PHY_CONTROL_REGS_VDL_MONITOR_CONTROLr_RESERVED1,
    647     DDR34_PHY_CONTROL_REGS_VDL_MONITOR_CONTROLr_UPDATE,
    648     DDR34_PHY_CONTROL_REGS_VDL_MONITOR_CONTROLr_FORCE,
    649     DDR34_PHY_CONTROL_REGS_VDL_MONITOR_CONTROLr_DATA_RATE,
    650     DDR34_PHY_CONTROL_REGS_VDL_MONITOR_CONTROLr_ENABLE,
    651     DDR34_PHY_CONTROL_REGS_VDL_MONITOR_REFr_RESERVED0,
    652     DDR34_PHY_CONTROL_REGS_VDL_MONITOR_REFr_MONITOR_4B_STEPS,
    653     DDR34_PHY_CONTROL_REGS_VDL_MONITOR_REFr_RESERVED1,
    654     DDR34_PHY_CONTROL_REGS_VDL_MONITOR_REFr_MONITOR_2B_STEPS,
    655     DDR34_PHY_CONTROL_REGS_VDL_MONITOR_STATUSr_RESERVED0,
    656     DDR34_PHY_CONTROL_REGS_VDL_MONITOR_STATUSr_MONITOR_BUS_ERROR,
    657     DDR34_PHY_CONTROL_REGS_VDL_MONITOR_STATUSr_RESERVED1,
    658     DDR34_PHY_CONTROL_REGS_VDL_MONITOR_STATUSr_MONITOR_ADJ,
    659     DDR34_PHY_CONTROL_REGS_VDL_MONITOR_STATUSr_MONITOR_CHANGE,
    660     DDR34_PHY_CONTROL_REGS_VDL_MONITOR_STATUSr_RESERVED2,
    661     DDR34_PHY_CONTROL_REGS_VDL_MONITOR_STATUSr_MONITOR_TOTAL,
    662     DDR34_PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDEr_BUSY,
    663     DDR34_PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDEr_RESERVED0,
    664     DDR34_PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDEr_FORCE,
    665     DDR34_PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDEr_RESERVED1,
    666     DDR34_PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDEr_ADJ,
    667     DDR34_PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDEr_RESERVED2,
    668     DDR34_PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDEr_ENABLE,
    669     DDR34_PHY_CONTROL_REGS_VDL_MONITOR_OUT_CONTROLr_RESERVED0,
    670     DDR34_PHY_CONTROL_REGS_VDL_MONITOR_OUT_CONTROLr_LOWER_LIMIT,
    671     DDR34_PHY_CONTROL_REGS_VDL_MONITOR_OUT_CONTROLr_UPPER_LIMIT,
    672     DDR34_PHY_CONTROL_REGS_VDL_MONITOR_OUT_CONTROLr_RESERVED1,
    673     DDR34_PHY_CONTROL_REGS_VDL_MONITOR_OUT_CONTROLr_ENABLE,
    674     DDR34_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUSr_RESERVED0,
    675     DDR34_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUSr_MONITOR_CHANGE,
    676     DDR34_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUSr_RESERVED1,
    677     DDR34_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUSr_MONITOR_TOTAL,
    678     DDR34_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUSr_RESERVED2,
    679     DDR34_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUSr_VALID,
    680     DDR34_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUSr_CLEAR_RESERVED0,
    681     DDR34_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUSr_CLEAR_CLEAR,
    682     DDR34_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_CLEARr_RESERVED0,
    683     DDR34_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_CLEARr_CLEAR,
    684     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD00r_BUSY,
    685     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD00r_RESERVED0,
    686     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD00r_FORCE,
    687     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD00r_RESERVED1,
    688     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD00r_ADJ_EN,
    689     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD00r_RESERVED2,
    690     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD00r_VDL_STEP,
    691     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD01r_BUSY,
    692     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD01r_RESERVED0,
    693     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD01r_FORCE,
    694     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD01r_RESERVED1,
    695     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD01r_ADJ_EN,
    696     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD01r_RESERVED2,
    697     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD01r_VDL_STEP,
    698     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD02r_BUSY,
    699     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD02r_RESERVED0,
    700     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD02r_FORCE,
    701     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD02r_RESERVED1,
    702     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD02r_ADJ_EN,
    703     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD02r_RESERVED2,
    704     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD02r_VDL_STEP,
    705     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD03r_BUSY,
    706     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD03r_RESERVED0,
    707     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD03r_FORCE,
    708     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD03r_RESERVED1,
    709     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD03r_ADJ_EN,
    710     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD03r_RESERVED2,
    711     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD03r_VDL_STEP,
    712     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD04r_BUSY,
    713     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD04r_RESERVED0,
    714     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD04r_FORCE,
    715     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD04r_RESERVED1,
    716     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD04r_ADJ_EN,
    717     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD04r_RESERVED2,
    718     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD04r_VDL_STEP,
    719     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD05r_BUSY,
    720     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD05r_RESERVED0,
    721     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD05r_FORCE,
    722     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD05r_RESERVED1,
    723     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD05r_ADJ_EN,
    724     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD05r_RESERVED2,
    725     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD05r_VDL_STEP,
    726     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD06r_BUSY,
    727     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD06r_RESERVED0,
    728     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD06r_FORCE,
    729     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD06r_RESERVED1,
    730     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD06r_ADJ_EN,
    731     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD06r_RESERVED2,
    732     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD06r_VDL_STEP,
    733     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD07r_BUSY,
    734     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD07r_RESERVED0,
    735     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD07r_FORCE,
    736     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD07r_RESERVED1,
    737     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD07r_ADJ_EN,
    738     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD07r_RESERVED2,
    739     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD07r_VDL_STEP,
    740     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD08r_BUSY,
    741     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD08r_RESERVED0,
    742     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD08r_FORCE,
    743     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD08r_RESERVED1,
    744     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD08r_ADJ_EN,
    745     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD08r_RESERVED2,
    746     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD08r_VDL_STEP,
    747     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD09r_BUSY,
    748     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD09r_RESERVED0,
    749     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD09r_FORCE,
    750     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD09r_RESERVED1,
    751     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD09r_ADJ_EN,
    752     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD09r_RESERVED2,
    753     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD09r_VDL_STEP,
    754     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD10r_BUSY,
    755     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD10r_RESERVED0,
    756     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD10r_FORCE,
    757     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD10r_RESERVED1,
    758     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD10r_ADJ_EN,
    759     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD10r_RESERVED2,
    760     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD10r_VDL_STEP,
    761     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD11r_BUSY,
    762     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD11r_RESERVED0,
    763     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD11r_FORCE,
    764     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD11r_RESERVED1,
    765     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD11r_ADJ_EN,
    766     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD11r_RESERVED2,
    767     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD11r_VDL_STEP,
    768     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD12r_BUSY,
    769     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD12r_RESERVED0,
    770     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD12r_FORCE,
    771     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD12r_RESERVED1,
    772     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD12r_ADJ_EN,
    773     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD12r_RESERVED2,
    774     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD12r_VDL_STEP,
    775     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD13r_BUSY,
    776     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD13r_RESERVED0,
    777     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD13r_FORCE,
    778     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD13r_RESERVED1,
    779     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD13r_ADJ_EN,
    780     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD13r_RESERVED2,
    781     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD13r_VDL_STEP,
    782     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD14r_BUSY,
    783     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD14r_RESERVED0,
    784     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD14r_FORCE,
    785     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD14r_RESERVED1,
    786     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD14r_ADJ_EN,
    787     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD14r_RESERVED2,
    788     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD14r_VDL_STEP,
    789     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD15r_BUSY,
    790     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD15r_RESERVED0,
    791     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD15r_FORCE,
    792     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD15r_RESERVED1,
    793     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD15r_ADJ_EN,
    794     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD15r_RESERVED2,
    795     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD15r_VDL_STEP,
    796     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_BA0r_BUSY,
    797     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_BA0r_RESERVED0,
    798     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_BA0r_FORCE,
    799     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_BA0r_RESERVED1,
    800     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_BA0r_ADJ_EN,
    801     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_BA0r_RESERVED2,
    802     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_BA0r_VDL_STEP,
    803     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_BA1r_BUSY,
    804     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_BA1r_RESERVED0,
    805     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_BA1r_FORCE,
    806     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_BA1r_RESERVED1,
    807     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_BA1r_ADJ_EN,
    808     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_BA1r_RESERVED2,
    809     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_BA1r_VDL_STEP,
    810     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_BA2r_BUSY,
    811     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_BA2r_RESERVED0,
    812     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_BA2r_FORCE,
    813     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_BA2r_RESERVED1,
    814     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_BA2r_ADJ_EN,
    815     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_BA2r_RESERVED2,
    816     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_BA2r_VDL_STEP,
    817     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AUX0r_BUSY,
    818     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AUX0r_RESERVED0,
    819     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AUX0r_FORCE,
    820     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AUX0r_RESERVED1,
    821     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AUX0r_ADJ_EN,
    822     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AUX0r_RESERVED2,
    823     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AUX0r_VDL_STEP,
    824     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AUX1r_BUSY,
    825     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AUX1r_RESERVED0,
    826     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AUX1r_FORCE,
    827     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AUX1r_RESERVED1,
    828     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AUX1r_ADJ_EN,
    829     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AUX1r_RESERVED2,
    830     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AUX1r_VDL_STEP,
    831     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AUX2r_BUSY,
    832     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AUX2r_RESERVED0,
    833     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AUX2r_FORCE,
    834     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AUX2r_RESERVED1,
    835     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AUX2r_ADJ_EN,
    836     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AUX2r_RESERVED2,
    837     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AUX2r_VDL_STEP,
    838     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_CS0r_BUSY,
    839     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_CS0r_RESERVED0,
    840     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_CS0r_FORCE,
    841     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_CS0r_RESERVED1,
    842     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_CS0r_ADJ_EN,
    843     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_CS0r_RESERVED2,
    844     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_CS0r_VDL_STEP,
    845     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_CS1r_BUSY,
    846     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_CS1r_RESERVED0,
    847     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_CS1r_FORCE,
    848     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_CS1r_RESERVED1,
    849     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_CS1r_ADJ_EN,
    850     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_CS1r_RESERVED2,
    851     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_CS1r_VDL_STEP,
    852     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_PARr_BUSY,
    853     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_PARr_RESERVED0,
    854     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_PARr_FORCE,
    855     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_PARr_RESERVED1,
    856     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_PARr_ADJ_EN,
    857     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_PARr_RESERVED2,
    858     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_PARr_VDL_STEP,
    859     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_RAS_Nr_BUSY,
    860     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_RAS_Nr_RESERVED0,
    861     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_RAS_Nr_FORCE,
    862     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_RAS_Nr_RESERVED1,
    863     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_RAS_Nr_ADJ_EN,
    864     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_RAS_Nr_RESERVED2,
    865     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_RAS_Nr_VDL_STEP,
    866     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_CAS_Nr_BUSY,
    867     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_CAS_Nr_RESERVED0,
    868     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_CAS_Nr_FORCE,
    869     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_CAS_Nr_RESERVED1,
    870     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_CAS_Nr_ADJ_EN,
    871     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_CAS_Nr_RESERVED2,
    872     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_CAS_Nr_VDL_STEP,
    873     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_CKEr_BUSY,
    874     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_CKEr_RESERVED0,
    875     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_CKEr_FORCE,
    876     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_CKEr_RESERVED1,
    877     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_CKEr_ADJ_EN,
    878     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_CKEr_RESERVED2,
    879     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_CKEr_VDL_STEP,
    880     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_RST_Nr_BUSY,
    881     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_RST_Nr_RESERVED0,
    882     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_RST_Nr_FORCE,
    883     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_RST_Nr_RESERVED1,
    884     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_RST_Nr_ADJ_EN,
    885     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_RST_Nr_RESERVED2,
    886     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_RST_Nr_VDL_STEP,
    887     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_ODTr_BUSY,
    888     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_ODTr_RESERVED0,
    889     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_ODTr_FORCE,
    890     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_ODTr_RESERVED1,
    891     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_ODTr_ADJ_EN,
    892     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_ODTr_RESERVED2,
    893     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_ODTr_VDL_STEP,
    894     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_WE_Nr_BUSY,
    895     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_WE_Nr_RESERVED0,
    896     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_WE_Nr_FORCE,
    897     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_WE_Nr_RESERVED1,
    898     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_WE_Nr_ADJ_EN,
    899     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_WE_Nr_RESERVED2,
    900     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_WE_Nr_VDL_STEP,
    901     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_Pr_BUSY,
    902     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_Pr_RESERVED0,
    903     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_Pr_FORCE,
    904     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_Pr_RESERVED1,
    905     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_Pr_ADJ_EN,
    906     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_Pr_RESERVED2,
    907     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_Pr_VDL_STEP,
    908     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_Nr_BUSY,
    909     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_Nr_RESERVED0,
    910     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_Nr_FORCE,
    911     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_Nr_RESERVED1,
    912     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_Nr_ADJ_EN,
    913     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_Nr_RESERVED2,
    914     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_Nr_VDL_STEP,
    915     DDR34_PHY_CONTROL_REGS_VDL_CLK_CONTROLr_BUSY,
    916     DDR34_PHY_CONTROL_REGS_VDL_CLK_CONTROLr_RESERVED0,
    917     DDR34_PHY_CONTROL_REGS_VDL_CLK_CONTROLr_FORCE,
    918     DDR34_PHY_CONTROL_REGS_VDL_CLK_CONTROLr_RESERVED1,
    919     DDR34_PHY_CONTROL_REGS_VDL_CLK_CONTROLr_ADJ_EN,
    920     DDR34_PHY_CONTROL_REGS_VDL_CLK_CONTROLr_RESERVED2,
    921     DDR34_PHY_CONTROL_REGS_VDL_CLK_CONTROLr_VDL_STEP,
    922     DDR34_PHY_CONTROL_REGS_VDL_LDE_CONTROLr_BUSY,
    923     DDR34_PHY_CONTROL_REGS_VDL_LDE_CONTROLr_RESERVED0,
    924     DDR34_PHY_CONTROL_REGS_VDL_LDE_CONTROLr_FORCE,
    925     DDR34_PHY_CONTROL_REGS_VDL_LDE_CONTROLr_RESERVED1,
    926     DDR34_PHY_CONTROL_REGS_VDL_LDE_CONTROLr_ADJ_EN,
    927     DDR34_PHY_CONTROL_REGS_VDL_LDE_CONTROLr_RESERVED2,
    928     DDR34_PHY_CONTROL_REGS_VDL_LDE_CONTROLr_VDL_STEP,
    929     DDR34_PHY_CONTROL_REGS_REFRESHr_RESERVED0,
    930     DDR34_PHY_CONTROL_REGS_REFRESHr_ENABLE,
    931     DDR34_PHY_CONTROL_REGS_REFRESHr_PERIOD,
    932     DDR34_PHY_CONTROL_REGS_UPDATE_VDLr_RESERVED0,
    933     DDR34_PHY_CONTROL_REGS_UPDATE_VDLr_MODE,
    934     DDR34_PHY_CONTROL_REGS_UPDATE_VDLr_RESERVED1,
    935     DDR34_PHY_CONTROL_REGS_UPDATE_VDLr_DISABLE_INPUT,
    936     DDR34_PHY_CONTROL_REGS_UPDATE_VDLr_ENABLE,
    937     DDR34_PHY_CONTROL_REGS_UPDATE_VDLr_SNOOP1_RESERVED0,
    938     DDR34_PHY_CONTROL_REGS_UPDATE_VDLr_SNOOP1_MODE,
    939     DDR34_PHY_CONTROL_REGS_UPDATE_VDLr_SNOOP1_RESERVED1,
    940     DDR34_PHY_CONTROL_REGS_UPDATE_VDLr_SNOOP1_MASK,
    941     DDR34_PHY_CONTROL_REGS_UPDATE_VDLr_SNOOP1_RESERVED2,
    942     DDR34_PHY_CONTROL_REGS_UPDATE_VDLr_SNOOP1_CMD,
    943     DDR34_PHY_CONTROL_REGS_UPDATE_VDLr_SNOOP1_RESERVED3,
    944     DDR34_PHY_CONTROL_REGS_UPDATE_VDLr_SNOOP1_ENABLE,
    945     DDR34_PHY_CONTROL_REGS_UPDATE_VDLr_SNOOP2_RESERVED0,
    946     DDR34_PHY_CONTROL_REGS_UPDATE_VDLr_SNOOP2_MODE,
    947     DDR34_PHY_CONTROL_REGS_UPDATE_VDLr_SNOOP2_RESERVED1,
    948     DDR34_PHY_CONTROL_REGS_UPDATE_VDLr_SNOOP2_MASK,
    949     DDR34_PHY_CONTROL_REGS_UPDATE_VDLr_SNOOP2_RESERVED2,
    950     DDR34_PHY_CONTROL_REGS_UPDATE_VDLr_SNOOP2_CMD,
    951     DDR34_PHY_CONTROL_REGS_UPDATE_VDLr_SNOOP2_RESERVED3,
    952     DDR34_PHY_CONTROL_REGS_UPDATE_VDLr_SNOOP2_ENABLE,
    953     DDR34_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1r_RESERVED0,
    954     DDR34_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1r_MODE,
    955     DDR34_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1r_RESERVED1,
    956     DDR34_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1r_MASK,
    957     DDR34_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1r_RESERVED2,
    958     DDR34_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1r_CMD,
    959     DDR34_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1r_RESERVED3,
    960     DDR34_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1r_ENABLE,
    961     DDR34_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2r_RESERVED0,
    962     DDR34_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2r_MODE,
    963     DDR34_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2r_RESERVED1,
    964     DDR34_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2r_MASK,
    965     DDR34_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2r_RESERVED2,
    966     DDR34_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2r_CMD,
    967     DDR34_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2r_RESERVED3,
    968     DDR34_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2r_ENABLE,
    969     DDR34_PHY_CONTROL_REGS_COMMAND_REG1r_MCP,
    970     DDR34_PHY_CONTROL_REGS_COMMAND_REG1r_CS,
    971     DDR34_PHY_CONTROL_REGS_COMMAND_REG1r_AUX,
    972     DDR34_PHY_CONTROL_REGS_COMMAND_REG1r_ACT,
    973     DDR34_PHY_CONTROL_REGS_COMMAND_REG1r_WE,
    974     DDR34_PHY_CONTROL_REGS_COMMAND_REG1r_CAS,
    975     DDR34_PHY_CONTROL_REGS_COMMAND_REG1r_RAS,
    976     DDR34_PHY_CONTROL_REGS_COMMAND_REG1r_BA,
    977     DDR34_PHY_CONTROL_REGS_COMMAND_REG1r_AD,
    978     DDR34_PHY_CONTROL_REGS_COMMAND_AUX_REG1r_RESERVED0,
    979     DDR34_PHY_CONTROL_REGS_COMMAND_AUX_REG1r_AUX,
    980     DDR34_PHY_CONTROL_REGS_COMMAND_REG2r_MCP,
    981     DDR34_PHY_CONTROL_REGS_COMMAND_REG2r_CS,
    982     DDR34_PHY_CONTROL_REGS_COMMAND_REG2r_AUX,
    983     DDR34_PHY_CONTROL_REGS_COMMAND_REG2r_ACT,
    984     DDR34_PHY_CONTROL_REGS_COMMAND_REG2r_WE,
    985     DDR34_PHY_CONTROL_REGS_COMMAND_REG2r_CAS,
    986     DDR34_PHY_CONTROL_REGS_COMMAND_REG2r_RAS,
    987     DDR34_PHY_CONTROL_REGS_COMMAND_REG2r_BA,
    988     DDR34_PHY_CONTROL_REGS_COMMAND_REG2r_AD,
    989     DDR34_PHY_CONTROL_REGS_COMMAND_AUX_REG2r_RESERVED0,
    990     DDR34_PHY_CONTROL_REGS_COMMAND_AUX_REG2r_AUX,
    991     DDR34_PHY_CONTROL_REGS_COMMAND_REG3r_MCP,
    992     DDR34_PHY_CONTROL_REGS_COMMAND_REG3r_CS,
    993     DDR34_PHY_CONTROL_REGS_COMMAND_REG3r_AUX,
    994     DDR34_PHY_CONTROL_REGS_COMMAND_REG3r_ACT,
    995     DDR34_PHY_CONTROL_REGS_COMMAND_REG3r_WE,
    996     DDR34_PHY_CONTROL_REGS_COMMAND_REG3r_CAS,
    997     DDR34_PHY_CONTROL_REGS_COMMAND_REG3r_RAS,
    998     DDR34_PHY_CONTROL_REGS_COMMAND_REG3r_BA,
    999     DDR34_PHY_CONTROL_REGS_COMMAND_REG3r_AD,
   1000     DDR34_PHY_CONTROL_REGS_COMMAND_AUX_REG3r_RESERVED0,
   1001     DDR34_PHY_CONTROL_REGS_COMMAND_AUX_REG3r_AUX,
   1002     DDR34_PHY_CONTROL_REGS_COMMAND_REG4r_MCP,
   1003     DDR34_PHY_CONTROL_REGS_COMMAND_REG4r_CS,
   1004     DDR34_PHY_CONTROL_REGS_COMMAND_REG4r_AUX,
   1005     DDR34_PHY_CONTROL_REGS_COMMAND_REG4r_ACT,
   1006     DDR34_PHY_CONTROL_REGS_COMMAND_REG4r_WE,
   1007     DDR34_PHY_CONTROL_REGS_COMMAND_REG4r_CAS,
   1008     DDR34_PHY_CONTROL_REGS_COMMAND_REG4r_RAS,
   1009     DDR34_PHY_CONTROL_REGS_COMMAND_REG4r_BA,
   1010     DDR34_PHY_CONTROL_REGS_COMMAND_REG4r_AD,
   1011     DDR34_PHY_CONTROL_REGS_COMMAND_AUX_REG4r_RESERVED0,
   1012     DDR34_PHY_CONTROL_REGS_COMMAND_AUX_REG4r_AUX,
   1013     DDR34_PHY_CONTROL_REGS_COMMAND_REG_TIMERr_RESERVED0,
   1014     DDR34_PHY_CONTROL_REGS_COMMAND_REG_TIMERr_INIT_VAL,
   1015     DDR34_PHY_CONTROL_REGS_COMMAND_REG_TIMERr_COUNT,
   1016     DDR34_PHY_CONTROL_REGS_MODE_REG0r_RESERVED0,
   1017     DDR34_PHY_CONTROL_REGS_MODE_REG0r_VALID,
   1018     DDR34_PHY_CONTROL_REGS_MODE_REG0r_AD,
   1019     DDR34_PHY_CONTROL_REGS_MODE_REG1r_RESERVED0,
   1020     DDR34_PHY_CONTROL_REGS_MODE_REG1r_VALID,
   1021     DDR34_PHY_CONTROL_REGS_MODE_REG1r_AD,
   1022     DDR34_PHY_CONTROL_REGS_MODE_REG2r_RESERVED0,
   1023     DDR34_PHY_CONTROL_REGS_MODE_REG2r_VALID,
   1024     DDR34_PHY_CONTROL_REGS_MODE_REG2r_AD,
   1025     DDR34_PHY_CONTROL_REGS_MODE_REG3r_RESERVED0,
   1026     DDR34_PHY_CONTROL_REGS_MODE_REG3r_VALID,
   1027     DDR34_PHY_CONTROL_REGS_MODE_REG3r_AD,
   1028     DDR34_PHY_CONTROL_REGS_MODE_REG4r_RESERVED0,
   1029     DDR34_PHY_CONTROL_REGS_MODE_REG4r_VALID,
   1030     DDR34_PHY_CONTROL_REGS_MODE_REG4r_AD,
   1031     DDR34_PHY_CONTROL_REGS_MODE_REG5r_RESERVED0,
   1032     DDR34_PHY_CONTROL_REGS_MODE_REG5r_VALID,
   1033     DDR34_PHY_CONTROL_REGS_MODE_REG5r_AD,
   1034     DDR34_PHY_CONTROL_REGS_MODE_REG6r_RESERVED0,
   1035     DDR34_PHY_CONTROL_REGS_MODE_REG6r_VALID,
   1036     DDR34_PHY_CONTROL_REGS_MODE_REG6r_AD,
   1037     DDR34_PHY_CONTROL_REGS_MODE_REG7r_RESERVED0,
   1038     DDR34_PHY_CONTROL_REGS_MODE_REG7r_VALID,
   1039     DDR34_PHY_CONTROL_REGS_MODE_REG7r_AD,
   1040     DDR34_PHY_CONTROL_REGS_MODE_REG8r_RESERVED0,
   1041     DDR34_PHY_CONTROL_REGS_MODE_REG8r_VALID,
   1042     DDR34_PHY_CONTROL_REGS_MODE_REG8r_AD,
   1043     DDR34_PHY_CONTROL_REGS_MODE_REG15r_RESERVED0,
   1044     DDR34_PHY_CONTROL_REGS_MODE_REG15r_VALID,
   1045     DDR34_PHY_CONTROL_REGS_MODE_REG15r_AD,
   1046     DDR34_PHY_CONTROL_REGS_MODE_REG63r_RESERVED0,
   1047     DDR34_PHY_CONTROL_REGS_MODE_REG63r_VALID,
   1048     DDR34_PHY_CONTROL_REGS_MODE_REG63r_AD,
   1049     DDR34_PHY_CONTROL_REGS_ALERT_CLEARr_RESERVED0,
   1050     DDR34_PHY_CONTROL_REGS_ALERT_CLEARr_CLEAR,
   1051     DDR34_PHY_CONTROL_REGS_ALERT_STATUSr_RESERVED0,
   1052     DDR34_PHY_CONTROL_REGS_ALERT_STATUSr_STATUS,
   1053     DDR34_PHY_CONTROL_REGS_CA_PARITYr_RESERVED0,
   1054     DDR34_PHY_CONTROL_REGS_CA_PARITYr_ERROR,
   1055     DDR34_PHY_CONTROL_REGS_CA_PARITYr_ENABLE,
   1056     DDR34_PHY_CONTROL_REGS_CA_PLAYBACK_CONTROLr_RESERVED0,
   1057     DDR34_PHY_CONTROL_REGS_CA_PLAYBACK_CONTROLr_COUNT,
   1058     DDR34_PHY_CONTROL_REGS_CA_PLAYBACK_CONTROLr_RESERVED1,
   1059     DDR34_PHY_CONTROL_REGS_CA_PLAYBACK_CONTROLr_SAMPLE,
   1060     DDR34_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS0r_VALID,
   1061     DDR34_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS0r_RESERVED0,
   1062     DDR34_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS0r_DATA1,
   1063     DDR34_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS0r_RESERVED1,
   1064     DDR34_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS0r_DATA0,
   1065     DDR34_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS1r_VALID,
   1066     DDR34_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS1r_RESERVED0,
   1067     DDR34_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS1r_DATA1,
   1068     DDR34_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS1r_RESERVED1,
   1069     DDR34_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS1r_DATA0,
   1070     DDR34_PHY_CONTROL_REGS_WRITE_LEVELING_CONTROLr_RESERVED0,
   1071     DDR34_PHY_CONTROL_REGS_WRITE_LEVELING_CONTROLr_COUNT,
   1072     DDR34_PHY_CONTROL_REGS_WRITE_LEVELING_CONTROLr_RESERVED1,
   1073     DDR34_PHY_CONTROL_REGS_WRITE_LEVELING_CONTROLr_SAMPLE,
   1074     DDR34_PHY_CONTROL_REGS_WRITE_LEVELING_CONTROLr_CONTINUOUS,
   1075     DDR34_PHY_CONTROL_REGS_WRITE_LEVELING_CONTROLr_ENABLE,
   1076     DDR34_PHY_CONTROL_REGS_WRITE_LEVELING_STATUSr_RESERVED0,
   1077     DDR34_PHY_CONTROL_REGS_WRITE_LEVELING_STATUSr_EDC,
   1078     DDR34_PHY_CONTROL_REGS_WRITE_LEVELING_STATUSr_STATUS,
   1079     DDR34_PHY_CONTROL_REGS_WRITE_LEVELING_STATUSr_RESERVED1,
   1080     DDR34_PHY_CONTROL_REGS_WRITE_LEVELING_STATUSr_VALID,
   1081     DDR34_PHY_CONTROL_REGS_READ_ENABLE_CONTROLr_RESERVED0,
   1082     DDR34_PHY_CONTROL_REGS_READ_ENABLE_CONTROLr_TEST_CYCLE,
   1083     DDR34_PHY_CONTROL_REGS_READ_ENABLE_CONTROLr_SELECT,
   1084     DDR34_PHY_CONTROL_REGS_READ_ENABLE_CONTROLr_RESERVED1,
   1085     DDR34_PHY_CONTROL_REGS_READ_ENABLE_CONTROLr_CS_N,
   1086     DDR34_PHY_CONTROL_REGS_READ_ENABLE_CONTROLr_EDC_DATA,
   1087     DDR34_PHY_CONTROL_REGS_READ_ENABLE_CONTROLr_EDC_PHASE,
   1088     DDR34_PHY_CONTROL_REGS_READ_ENABLE_CONTROLr_DQS,
   1089     DDR34_PHY_CONTROL_REGS_READ_ENABLE_CONTROLr_ENABLE,
   1090     DDR34_PHY_CONTROL_REGS_READ_ENABLE_STATUSr_RESERVED0,
   1091     DDR34_PHY_CONTROL_REGS_READ_ENABLE_STATUSr_DATA,
   1092     DDR34_PHY_CONTROL_REGS_READ_ENABLE_STATUSr_RESERVED1,
   1093     DDR34_PHY_CONTROL_REGS_READ_ENABLE_STATUSr_BL4_STATUS,
   1094     DDR34_PHY_CONTROL_REGS_READ_ENABLE_STATUSr_BL3_STATUS,
   1095     DDR34_PHY_CONTROL_REGS_READ_ENABLE_STATUSr_BL2_STATUS,
   1096     DDR34_PHY_CONTROL_REGS_READ_ENABLE_STATUSr_BL1_STATUS,
   1097     DDR34_PHY_CONTROL_REGS_READ_ENABLE_STATUSr_BL0_STATUS,
   1098     DDR34_PHY_CONTROL_REGS_READ_ENABLE_STATUSr_RESERVED2,
   1099     DDR34_PHY_CONTROL_REGS_READ_ENABLE_STATUSr_VALID,
   1100     DDR34_PHY_CONTROL_REGS_TRAFFIC_GEN_LFSR_SEEDr_SEED,
   1101     DDR34_PHY_CONTROL_REGS_TRAFFIC_GEN_ADDRESS1r_RESERVED0,
   1102     DDR34_PHY_CONTROL_REGS_TRAFFIC_GEN_ADDRESS1r_BANK,
   1103     DDR34_PHY_CONTROL_REGS_TRAFFIC_GEN_ADDRESS1r_ROW,
   1104     DDR34_PHY_CONTROL_REGS_TRAFFIC_GEN_ADDRESS2r_RESERVED0,
   1105     DDR34_PHY_CONTROL_REGS_TRAFFIC_GEN_ADDRESS2r_BANK,
   1106     DDR34_PHY_CONTROL_REGS_TRAFFIC_GEN_ADDRESS2r_ROW,
   1107     DDR34_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROLr_RESERVED0,
   1108     DDR34_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROLr_DIAG_WRO,
   1109     DDR34_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROLr_DIAG_WRO_RD,
   1110     DDR34_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROLr_DIAG_WR_RD,
   1111     DDR34_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROLr_WR_NOISE,
   1112     DDR34_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROLr_RD_NOISE,
   1113     DDR34_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROLr_CLEAR_DRAM,
   1114     DDR34_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROLr_MASK_DM,
   1115     DDR34_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROLr_INIT_LFSR,
   1116     DDR34_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROLr_FIFO,
   1117     DDR34_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROLr_MPR,
   1118     DDR34_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROLr_RD_WR,
   1119     DDR34_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROLr_RD_EN,
   1120     DDR34_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROLr_ENABLE,
   1121     DDR34_PHY_CONTROL_REGS_TRAFFIC_GEN_DATA_CONTROLr_RESERVED0,
   1122     DDR34_PHY_CONTROL_REGS_TRAFFIC_GEN_DATA_CONTROLr_PATTERN,
   1123     DDR34_PHY_CONTROL_REGS_TRAFFIC_GEN_DATA_CONTROLr_LENGTH,
   1124     DDR34_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_MASKr_MASK,
   1125     DDR34_PHY_CONTROL_REGS_TRAFFIC_GEN_ECC_DQ_MASKr_RESERVED0,
   1126     DDR34_PHY_CONTROL_REGS_TRAFFIC_GEN_ECC_DQ_MASKr_MASK,
   1127     DDR34_PHY_CONTROL_REGS_TRAFFIC_GEN_STATUSr_RESERVED0,
   1128     DDR34_PHY_CONTROL_REGS_TRAFFIC_GEN_STATUSr_BUSY,
   1129     DDR34_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUSr_STATUS,
   1130     DDR34_PHY_CONTROL_REGS_TRAFFIC_GEN_ECC_STATUSr_RESERVED0,
   1131     DDR34_PHY_CONTROL_REGS_TRAFFIC_GEN_ECC_STATUSr_STATUS,
   1132     DDR34_PHY_CONTROL_REGS_TRAFFIC_GEN_ERR_CNT_CONTROLr_RESERVED0,
   1133     DDR34_PHY_CONTROL_REGS_TRAFFIC_GEN_ERR_CNT_CONTROLr_DQ_SEL,
   1134     DDR34_PHY_CONTROL_REGS_TRAFFIC_GEN_ERR_CNT_CONTROLr_RESERVED1,
   1135     DDR34_PHY_CONTROL_REGS_TRAFFIC_GEN_ERR_CNT_CONTROLr_CLEAR,
   1136     DDR34_PHY_CONTROL_REGS_TRAFFIC_GEN_ERR_CNT_CONTROLr_ENABLE,
   1137     DDR34_PHY_CONTROL_REGS_TRAFFIC_GEN_ERR_CNT_STATUSr_RESERVED0,
   1138     DDR34_PHY_CONTROL_REGS_TRAFFIC_GEN_ERR_CNT_STATUSr_COUNT,
   1139     DDR34_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROLr_RESERVED0,
   1140     DDR34_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROLr_RESERVED_for_eco1,
   1141     DDR34_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROLr_MAX_NOISE,
   1142     DDR34_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROLr_LOW_NOISE,
   1143     DDR34_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROLr_LOW_VTT,
   1144     DDR34_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROLr_HIGH_VTT,
   1145     DDR34_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROLr_ERROR_RESET,
   1146     DDR34_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROLr_ENABLE_CTL_IDLE,
   1147     DDR34_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROLr_ENABLE_CS_IDLE,
   1148     DDR34_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROLr_ENABLE_CKE_IDLE,
   1149     DDR34_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUSr_RESERVED0,
   1150     DDR34_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUSr_ERROR,
   1151     DDR34_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUSr_ERROR_LOW,
   1152     DDR34_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUSr_ERROR_HIGH,
   1153     DDR34_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUSr_READY,
   1154     DDR34_PHY_CONTROL_REGS_VIRTUAL_VTT_CONNECTIONSr_RESERVED0,
   1155     DDR34_PHY_CONTROL_REGS_VIRTUAL_VTT_CONNECTIONSr_MASK,
   1156     DDR34_PHY_CONTROL_REGS_VIRTUAL_VTT_OVERRIDEr_RESERVED0,
   1157     DDR34_PHY_CONTROL_REGS_VIRTUAL_VTT_OVERRIDEr_MASK,
   1158     DDR34_PHY_CONTROL_REGS_VREF_DAC_CONTROLr_RESERVED0,
   1159     DDR34_PHY_CONTROL_REGS_VREF_DAC_CONTROLr_AUX_GT_INT,
   1160     DDR34_PHY_CONTROL_REGS_VREF_DAC_CONTROLr_TESTOUT_MUX_CTL,
   1161     DDR34_PHY_CONTROL_REGS_VREF_DAC_CONTROLr_TEST,
   1162     DDR34_PHY_CONTROL_REGS_VREF_DAC_CONTROLr_PDN3,
   1163     DDR34_PHY_CONTROL_REGS_VREF_DAC_CONTROLr_PDN2,
   1164     DDR34_PHY_CONTROL_REGS_VREF_DAC_CONTROLr_PDN1,
   1165     DDR34_PHY_CONTROL_REGS_VREF_DAC_CONTROLr_PDN0,
   1166     DDR34_PHY_CONTROL_REGS_VREF_DAC_CONTROLr_DAC1,
   1167     DDR34_PHY_CONTROL_REGS_VREF_DAC_CONTROLr_DAC0,
   1168     DDR34_PHY_CONTROL_REGS_PHYBIST_CNTRLr_RESERVED0,
   1169     DDR34_PHY_CONTROL_REGS_PHYBIST_CNTRLr_CLK_PAD_ENB,
   1170     DDR34_PHY_CONTROL_REGS_PHYBIST_CNTRLr_RESERVED1,
   1171     DDR34_PHY_CONTROL_REGS_PHYBIST_CNTRLr_FORCE_DQ_ERROR_SEL,
   1172     DDR34_PHY_CONTROL_REGS_PHYBIST_CNTRLr_RESERVED2,
   1173     DDR34_PHY_CONTROL_REGS_PHYBIST_CNTRLr_FORCE_BL_ERROR_SEL,
   1174     DDR34_PHY_CONTROL_REGS_PHYBIST_CNTRLr_RESERVED3,
   1175     DDR34_PHY_CONTROL_REGS_PHYBIST_CNTRLr_FORCE_CTL_ERROR_SEL,
   1176     DDR34_PHY_CONTROL_REGS_PHYBIST_CNTRLr_RESERVED4,
   1177     DDR34_PHY_CONTROL_REGS_PHYBIST_CNTRLr_FORCE_DAT_ERROR,
   1178     DDR34_PHY_CONTROL_REGS_PHYBIST_CNTRLr_FORCE_CTL_ERROR,
   1179     DDR34_PHY_CONTROL_REGS_PHYBIST_CNTRLr_SSO,
   1180     DDR34_PHY_CONTROL_REGS_PHYBIST_CNTRLr_LENGTH,
   1181     DDR34_PHY_CONTROL_REGS_PHYBIST_CNTRLr_MODE,
   1182     DDR34_PHY_CONTROL_REGS_PHYBIST_CNTRLr_ENABLE,
   1183     DDR34_PHY_CONTROL_REGS_PHYBIST_SEEDr_SEED,
   1184     DDR34_PHY_CONTROL_REGS_PHYBIST_STATUSr_RESERVED0,
   1185     DDR34_PHY_CONTROL_REGS_PHYBIST_STATUSr_DAT_PASS,
   1186     DDR34_PHY_CONTROL_REGS_PHYBIST_STATUSr_CTL_PASS,
   1187     DDR34_PHY_CONTROL_REGS_PHYBIST_STATUSr_DAT_DONE,
   1188     DDR34_PHY_CONTROL_REGS_PHYBIST_STATUSr_CTL_DONE,
   1189     DDR34_PHY_CONTROL_REGS_PHYBIST_CTL_STATUSr_RESERVED0,
   1190     DDR34_PHY_CONTROL_REGS_PHYBIST_CTL_STATUSr_CTL_ERRORS,
   1191     DDR34_PHY_CONTROL_REGS_PHYBIST_BL0_STATUSr_RESERVED0,
   1192     DDR34_PHY_CONTROL_REGS_PHYBIST_BL0_STATUSr_EDC,
   1193     DDR34_PHY_CONTROL_REGS_PHYBIST_BL0_STATUSr_DM,
   1194     DDR34_PHY_CONTROL_REGS_PHYBIST_BL0_STATUSr_DQ,
   1195     DDR34_PHY_CONTROL_REGS_PHYBIST_BL1_STATUSr_RESERVED0,
   1196     DDR34_PHY_CONTROL_REGS_PHYBIST_BL1_STATUSr_EDC,
   1197     DDR34_PHY_CONTROL_REGS_PHYBIST_BL1_STATUSr_DM,
   1198     DDR34_PHY_CONTROL_REGS_PHYBIST_BL1_STATUSr_DQ,
   1199     DDR34_PHY_CONTROL_REGS_PHYBIST_BL2_STATUSr_RESERVED0,
   1200     DDR34_PHY_CONTROL_REGS_PHYBIST_BL2_STATUSr_EDC,
   1201     DDR34_PHY_CONTROL_REGS_PHYBIST_BL2_STATUSr_DM,
   1202     DDR34_PHY_CONTROL_REGS_PHYBIST_BL2_STATUSr_DQ,
   1203     DDR34_PHY_CONTROL_REGS_PHYBIST_BL3_STATUSr_RESERVED0,
   1204     DDR34_PHY_CONTROL_REGS_PHYBIST_BL3_STATUSr_EDC,
   1205     DDR34_PHY_CONTROL_REGS_PHYBIST_BL3_STATUSr_DM,
   1206     DDR34_PHY_CONTROL_REGS_PHYBIST_BL3_STATUSr_DQ,
   1207     DDR34_PHY_CONTROL_REGS_PHYBIST_BL4_STATUSr_RESERVED0,
   1208     DDR34_PHY_CONTROL_REGS_PHYBIST_BL4_STATUSr_EDC,
   1209     DDR34_PHY_CONTROL_REGS_PHYBIST_BL4_STATUSr_DM,
   1210     DDR34_PHY_CONTROL_REGS_PHYBIST_BL4_STATUSr_DQ,
   1211     DDR34_PHY_CONTROL_REGS_STANDBY_CONTROLr_RESERVED0,
   1212     DDR34_PHY_CONTROL_REGS_STANDBY_CONTROLr_STANDBY_READY,
   1213     DDR34_PHY_CONTROL_REGS_STANDBY_CONTROLr_STANDBY_EXIT_PIN_EN,
   1214     DDR34_PHY_CONTROL_REGS_STANDBY_CONTROLr_STANDBY_ACTIVE,
   1215     DDR34_PHY_CONTROL_REGS_STANDBY_CONTROLr_ARMED,
   1216     DDR34_PHY_CONTROL_REGS_STANDBY_CONTROLr_WARMSTART,
   1217     DDR34_PHY_CONTROL_REGS_STANDBY_CONTROLr_PWRDOWN_LDO_BIAS,
   1218     DDR34_PHY_CONTROL_REGS_STANDBY_CONTROLr_PWRDOWN_LDO_VOLTS,
   1219     DDR34_PHY_CONTROL_REGS_STANDBY_CONTROLr_PWRDOWN_SKIP_MRS,
   1220     DDR34_PHY_CONTROL_REGS_STANDBY_CONTROLr_PWRDOWN_RST_N,
   1221     DDR34_PHY_CONTROL_REGS_STANDBY_CONTROLr_PWRDOWN_CKE,
   1222     DDR34_PHY_CONTROL_REGS_STANDBY_CONTROLr_LDO_BIAS,
   1223     DDR34_PHY_CONTROL_REGS_STANDBY_CONTROLr_LDO_VOLTS,
   1224     DDR34_PHY_CONTROL_REGS_STANDBY_CONTROLr_SKIP_MRS,
   1225     DDR34_PHY_CONTROL_REGS_STANDBY_CONTROLr_RST_N,
   1226     DDR34_PHY_CONTROL_REGS_STANDBY_CONTROLr_CKE,
   1227     DDR34_PHY_CONTROL_REGS_STANDBY_CONTROLr_STANDBY,
   1228     DDR34_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLEr_RESERVED0,
   1229     DDR34_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLEr_WLECC,
   1230     DDR34_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLEr_WL1_BL1,
   1231     DDR34_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLEr_WL1_BL0,
   1232     DDR34_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLEr_WL0_BL1,
   1233     DDR34_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLEr_WL0_BL0,
   1234     DDR34_PHY_CONTROL_REGS_DEBUG_MUX_CONTROLr_RESERVED0,
   1235     DDR34_PHY_CONTROL_REGS_DEBUG_MUX_CONTROLr_BYTE_SEL,
   1236     DDR34_PHY_CONTROL_REGS_DEBUG_MUX_CONTROLr_RESERVED1,
   1237     DDR34_PHY_CONTROL_REGS_DEBUG_MUX_CONTROLr_PHASE_SEL,
   1238     DDR34_PHY_CONTROL_REGS_DEBUG_MUX_CONTROLr_SOURCE_SEL,
   1239     DDR34_PHY_CONTROL_REGS_DFI_CNTRLr_RESERVED0,
   1240     DDR34_PHY_CONTROL_REGS_DFI_CNTRLr_DFI_CS1,
   1241     DDR34_PHY_CONTROL_REGS_DFI_CNTRLr_DFI_CS0,
   1242     DDR34_PHY_CONTROL_REGS_DFI_CNTRLr_DFI_RST_N,
   1243     DDR34_PHY_CONTROL_REGS_DFI_CNTRLr_DFI_CKE,
   1244     DDR34_PHY_CONTROL_REGS_DFI_CNTRLr_ACK_ENABLE,
   1245     DDR34_PHY_CONTROL_REGS_DFI_CNTRLr_ACK_STATUS,
   1246     DDR34_PHY_CONTROL_REGS_DFI_CNTRLr_ASSERT_REQ,
   1247     DDR34_PHY_CONTROL_REGS_WRITE_ODT_CNTRLr_RESERVED0,
   1248     DDR34_PHY_CONTROL_REGS_WRITE_ODT_CNTRLr_ODT_FORCE_VALUE,
   1249     DDR34_PHY_CONTROL_REGS_WRITE_ODT_CNTRLr_ODT_FORCE,
   1250     DDR34_PHY_CONTROL_REGS_WRITE_ODT_CNTRLr_ODT_ENABLE,
   1251     DDR34_PHY_CONTROL_REGS_WRITE_ODT_CNTRLr_ODT_LENGTH,
   1252     DDR34_PHY_CONTROL_REGS_WRITE_ODT_CNTRLr_ODT_DELAY,
   1253     DDR34_PHY_CONTROL_REGS_ABI_PAR_CNTRLr_RESERVED0,
   1254     DDR34_PHY_CONTROL_REGS_ABI_PAR_CNTRLr_PAR_INCLUDE_AUX,
   1255     DDR34_PHY_CONTROL_REGS_ABI_PAR_CNTRLr_PAR_ENABLE,
   1256     DDR34_PHY_CONTROL_REGS_ABI_PAR_CNTRLr_ABI_INCLUDE_AUX,
   1257     DDR34_PHY_CONTROL_REGS_ABI_PAR_CNTRLr_ABI_ENABLE,
   1258     DDR34_PHY_CONTROL_REGS_ZQ_CALr_RESERVED0,
   1259     DDR34_PHY_CONTROL_REGS_ZQ_CALr_ZQ_PCOMP_STATUS,
   1260     DDR34_PHY_CONTROL_REGS_ZQ_CALr_ZQ_NCOMP_STATUS,
   1261     DDR34_PHY_CONTROL_REGS_ZQ_CALr_ZQ_IDDQ,
   1262     DDR34_PHY_CONTROL_REGS_ZQ_CALr_ZQ_DRIVE_P,
   1263     DDR34_PHY_CONTROL_REGS_ZQ_CALr_ZQ_DRIVE_N,
   1264     DDR34_PHY_CONTROL_REGS_ZQ_CALr_RESERVED_for_padding1,
   1265     DDR34_PHY_CONTROL_REGS_ZQ_CALr_ZQ_PCOMP_ENB,
   1266     DDR34_PHY_CONTROL_REGS_ZQ_CALr_ZQ_NCOMP_ENB,
   1267     DDR34_PHY_CONTROL_REGS_AC_SPARE_REGr_RESERVED_for_eco0,
   1268     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_Pr_BUSY,
   1269     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_Pr_RESERVED0,
   1270     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_Pr_FORCE,
   1271     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_Pr_RESERVED1,
   1272     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_Pr_ADJ_EN,
   1273     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_Pr_RESERVED2,
   1274     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_Pr_VDL_STEP,
   1275     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_Nr_BUSY,
   1276     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_Nr_RESERVED0,
   1277     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_Nr_FORCE,
   1278     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_Nr_RESERVED1,
   1279     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_Nr_ADJ_EN,
   1280     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_Nr_RESERVED2,
   1281     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_Nr_VDL_STEP,
   1282     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0r_BUSY,
   1283     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0r_RESERVED0,
   1284     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0r_FORCE,
   1285     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0r_RESERVED1,
   1286     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0r_ADJ_EN,
   1287     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0r_RESERVED2,
   1288     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0r_VDL_STEP,
   1289     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1r_BUSY,
   1290     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1r_RESERVED0,
   1291     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1r_FORCE,
   1292     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1r_RESERVED1,
   1293     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1r_ADJ_EN,
   1294     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1r_RESERVED2,
   1295     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1r_VDL_STEP,
   1296     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2r_BUSY,
   1297     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2r_RESERVED0,
   1298     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2r_FORCE,
   1299     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2r_RESERVED1,
   1300     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2r_ADJ_EN,
   1301     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2r_RESERVED2,
   1302     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2r_VDL_STEP,
   1303     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3r_BUSY,
   1304     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3r_RESERVED0,
   1305     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3r_FORCE,
   1306     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3r_RESERVED1,
   1307     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3r_ADJ_EN,
   1308     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3r_RESERVED2,
   1309     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3r_VDL_STEP,
   1310     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4r_BUSY,
   1311     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4r_RESERVED0,
   1312     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4r_FORCE,
   1313     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4r_RESERVED1,
   1314     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4r_ADJ_EN,
   1315     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4r_RESERVED2,
   1316     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4r_VDL_STEP,
   1317     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5r_BUSY,
   1318     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5r_RESERVED0,
   1319     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5r_FORCE,
   1320     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5r_RESERVED1,
   1321     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5r_ADJ_EN,
   1322     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5r_RESERVED2,
   1323     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5r_VDL_STEP,
   1324     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6r_BUSY,
   1325     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6r_RESERVED0,
   1326     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6r_FORCE,
   1327     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6r_RESERVED1,
   1328     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6r_ADJ_EN,
   1329     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6r_RESERVED2,
   1330     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6r_VDL_STEP,
   1331     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7r_BUSY,
   1332     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7r_RESERVED0,
   1333     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7r_FORCE,
   1334     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7r_RESERVED1,
   1335     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7r_ADJ_EN,
   1336     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7r_RESERVED2,
   1337     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7r_VDL_STEP,
   1338     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DMr_BUSY,
   1339     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DMr_RESERVED0,
   1340     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DMr_FORCE,
   1341     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DMr_RESERVED1,
   1342     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DMr_ADJ_EN,
   1343     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DMr_RESERVED2,
   1344     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DMr_VDL_STEP,
   1345     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_EDCr_BUSY,
   1346     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_EDCr_RESERVED0,
   1347     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_EDCr_FORCE,
   1348     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_EDCr_RESERVED1,
   1349     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_EDCr_ADJ_EN,
   1350     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_EDCr_RESERVED2,
   1351     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_EDCr_VDL_STEP,
   1352     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSPr_BUSY,
   1353     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSPr_RESERVED0,
   1354     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSPr_FORCE,
   1355     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSPr_RESERVED1,
   1356     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSPr_ADJ_EN,
   1357     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSPr_RESERVED2,
   1358     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSPr_VDL_STEP,
   1359     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSNr_BUSY,
   1360     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSNr_RESERVED0,
   1361     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSNr_FORCE,
   1362     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSNr_RESERVED1,
   1363     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSNr_ADJ_EN,
   1364     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSNr_RESERVED2,
   1365     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSNr_VDL_STEP,
   1366     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0Pr_BUSY,
   1367     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0Pr_RESERVED0,
   1368     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0Pr_FORCE,
   1369     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0Pr_RESERVED1,
   1370     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0Pr_ADJ_EN,
   1371     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0Pr_RESERVED2,
   1372     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0Pr_VDL_STEP,
   1373     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0Nr_BUSY,
   1374     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0Nr_RESERVED0,
   1375     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0Nr_FORCE,
   1376     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0Nr_RESERVED1,
   1377     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0Nr_ADJ_EN,
   1378     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0Nr_RESERVED2,
   1379     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0Nr_VDL_STEP,
   1380     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1Pr_BUSY,
   1381     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1Pr_RESERVED0,
   1382     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1Pr_FORCE,
   1383     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1Pr_RESERVED1,
   1384     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1Pr_ADJ_EN,
   1385     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1Pr_RESERVED2,
   1386     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1Pr_VDL_STEP,
   1387     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1Nr_BUSY,
   1388     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1Nr_RESERVED0,
   1389     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1Nr_FORCE,
   1390     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1Nr_RESERVED1,
   1391     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1Nr_ADJ_EN,
   1392     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1Nr_RESERVED2,
   1393     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1Nr_VDL_STEP,
   1394     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2Pr_BUSY,
   1395     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2Pr_RESERVED0,
   1396     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2Pr_FORCE,
   1397     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2Pr_RESERVED1,
   1398     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2Pr_ADJ_EN,
   1399     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2Pr_RESERVED2,
   1400     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2Pr_VDL_STEP,
   1401     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2Nr_BUSY,
   1402     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2Nr_RESERVED0,
   1403     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2Nr_FORCE,
   1404     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2Nr_RESERVED1,
   1405     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2Nr_ADJ_EN,
   1406     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2Nr_RESERVED2,
   1407     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2Nr_VDL_STEP,
   1408     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3Pr_BUSY,
   1409     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3Pr_RESERVED0,
   1410     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3Pr_FORCE,
   1411     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3Pr_RESERVED1,
   1412     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3Pr_ADJ_EN,
   1413     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3Pr_RESERVED2,
   1414     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3Pr_VDL_STEP,
   1415     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3Nr_BUSY,
   1416     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3Nr_RESERVED0,
   1417     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3Nr_FORCE,
   1418     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3Nr_RESERVED1,
   1419     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3Nr_ADJ_EN,
   1420     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3Nr_RESERVED2,
   1421     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3Nr_VDL_STEP,
   1422     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4Pr_BUSY,
   1423     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4Pr_RESERVED0,
   1424     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4Pr_FORCE,
   1425     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4Pr_RESERVED1,
   1426     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4Pr_ADJ_EN,
   1427     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4Pr_RESERVED2,
   1428     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4Pr_VDL_STEP,
   1429     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4Nr_BUSY,
   1430     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4Nr_RESERVED0,
   1431     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4Nr_FORCE,
   1432     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4Nr_RESERVED1,
   1433     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4Nr_ADJ_EN,
   1434     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4Nr_RESERVED2,
   1435     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4Nr_VDL_STEP,
   1436     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5Pr_BUSY,
   1437     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5Pr_RESERVED0,
   1438     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5Pr_FORCE,
   1439     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5Pr_RESERVED1,
   1440     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5Pr_ADJ_EN,
   1441     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5Pr_RESERVED2,
   1442     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5Pr_VDL_STEP,
   1443     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5Nr_BUSY,
   1444     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5Nr_RESERVED0,
   1445     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5Nr_FORCE,
   1446     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5Nr_RESERVED1,
   1447     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5Nr_ADJ_EN,
   1448     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5Nr_RESERVED2,
   1449     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5Nr_VDL_STEP,
   1450     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6Pr_BUSY,
   1451     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6Pr_RESERVED0,
   1452     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6Pr_FORCE,
   1453     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6Pr_RESERVED1,
   1454     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6Pr_ADJ_EN,
   1455     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6Pr_RESERVED2,
   1456     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6Pr_VDL_STEP,
   1457     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6Nr_BUSY,
   1458     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6Nr_RESERVED0,
   1459     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6Nr_FORCE,
   1460     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6Nr_RESERVED1,
   1461     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6Nr_ADJ_EN,
   1462     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6Nr_RESERVED2,
   1463     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6Nr_VDL_STEP,
   1464     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7Pr_BUSY,
   1465     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7Pr_RESERVED0,
   1466     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7Pr_FORCE,
   1467     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7Pr_RESERVED1,
   1468     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7Pr_ADJ_EN,
   1469     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7Pr_RESERVED2,
   1470     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7Pr_VDL_STEP,
   1471     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7Nr_BUSY,
   1472     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7Nr_RESERVED0,
   1473     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7Nr_FORCE,
   1474     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7Nr_RESERVED1,
   1475     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7Nr_ADJ_EN,
   1476     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7Nr_RESERVED2,
   1477     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7Nr_VDL_STEP,
   1478     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMPr_BUSY,
   1479     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMPr_RESERVED0,
   1480     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMPr_FORCE,
   1481     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMPr_RESERVED1,
   1482     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMPr_ADJ_EN,
   1483     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMPr_RESERVED2,
   1484     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMPr_VDL_STEP,
   1485     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMNr_BUSY,
   1486     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMNr_RESERVED0,
   1487     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMNr_FORCE,
   1488     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMNr_RESERVED1,
   1489     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMNr_ADJ_EN,
   1490     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMNr_RESERVED2,
   1491     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMNr_VDL_STEP,
   1492     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCPr_BUSY,
   1493     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCPr_RESERVED0,
   1494     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCPr_FORCE,
   1495     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCPr_RESERVED1,
   1496     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCPr_ADJ_EN,
   1497     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCPr_RESERVED2,
   1498     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCPr_VDL_STEP,
   1499     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCNr_BUSY,
   1500     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCNr_RESERVED0,
   1501     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCNr_FORCE,
   1502     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCNr_RESERVED1,
   1503     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCNr_ADJ_EN,
   1504     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCNr_RESERVED2,
   1505     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCNr_VDL_STEP,
   1506     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0r_BUSY,
   1507     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0r_RESERVED0,
   1508     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0r_FORCE,
   1509     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0r_RESERVED1,
   1510     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0r_ADJ_EN,
   1511     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0r_RESERVED2,
   1512     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0r_VDL_STEP,
   1513     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1r_BUSY,
   1514     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1r_RESERVED0,
   1515     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1r_FORCE,
   1516     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1r_RESERVED1,
   1517     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1r_ADJ_EN,
   1518     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1r_RESERVED2,
   1519     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1r_VDL_STEP,
   1520     DDR34_PHY_BYTE_LANE_0_VDL_CLK_CONTROLr_BUSY,
   1521     DDR34_PHY_BYTE_LANE_0_VDL_CLK_CONTROLr_RESERVED0,
   1522     DDR34_PHY_BYTE_LANE_0_VDL_CLK_CONTROLr_FORCE,
   1523     DDR34_PHY_BYTE_LANE_0_VDL_CLK_CONTROLr_RESERVED1,
   1524     DDR34_PHY_BYTE_LANE_0_VDL_CLK_CONTROLr_ADJ_EN,
   1525     DDR34_PHY_BYTE_LANE_0_VDL_CLK_CONTROLr_RESERVED2,
   1526     DDR34_PHY_BYTE_LANE_0_VDL_CLK_CONTROLr_VDL_STEP,
   1527     DDR34_PHY_BYTE_LANE_0_VDL_LDE_CONTROLr_BUSY,
   1528     DDR34_PHY_BYTE_LANE_0_VDL_LDE_CONTROLr_RESERVED0,
   1529     DDR34_PHY_BYTE_LANE_0_VDL_LDE_CONTROLr_FORCE,
   1530     DDR34_PHY_BYTE_LANE_0_VDL_LDE_CONTROLr_RESERVED1,
   1531     DDR34_PHY_BYTE_LANE_0_VDL_LDE_CONTROLr_ADJ_EN,
   1532     DDR34_PHY_BYTE_LANE_0_VDL_LDE_CONTROLr_RESERVED2,
   1533     DDR34_PHY_BYTE_LANE_0_VDL_LDE_CONTROLr_VDL_STEP,
   1534     DDR34_PHY_BYTE_LANE_0_RD_EN_DLY_CYCr_BUSY,
   1535     DDR34_PHY_BYTE_LANE_0_RD_EN_DLY_CYCr_RESERVED0,
   1536     DDR34_PHY_BYTE_LANE_0_RD_EN_DLY_CYCr_FORCE,
   1537     DDR34_PHY_BYTE_LANE_0_RD_EN_DLY_CYCr_RESERVED1,
   1538     DDR34_PHY_BYTE_LANE_0_RD_EN_DLY_CYCr_CS1_CYCLES,
   1539     DDR34_PHY_BYTE_LANE_0_RD_EN_DLY_CYCr_CS0_CYCLES,
   1540     DDR34_PHY_BYTE_LANE_0_WR_CHAN_DLY_CYCr_BUSY,
   1541     DDR34_PHY_BYTE_LANE_0_WR_CHAN_DLY_CYCr_RESERVED0,
   1542     DDR34_PHY_BYTE_LANE_0_WR_CHAN_DLY_CYCr_FORCE,
   1543     DDR34_PHY_BYTE_LANE_0_WR_CHAN_DLY_CYCr_RESERVED1,
   1544     DDR34_PHY_BYTE_LANE_0_WR_CHAN_DLY_CYCr_CYCLES,
   1545     DDR34_PHY_BYTE_LANE_0_READ_CONTROLr_RESERVED0,
   1546     DDR34_PHY_BYTE_LANE_0_READ_CONTROLr_MODE,
   1547     DDR34_PHY_BYTE_LANE_0_READ_CONTROLr_RESERVED1,
   1548     DDR34_PHY_BYTE_LANE_0_READ_CONTROLr_RD_DATA_DLY,
   1549     DDR34_PHY_BYTE_LANE_0_READ_FIFO_ADDRr_RESERVED0,
   1550     DDR34_PHY_BYTE_LANE_0_READ_FIFO_ADDRr_ADDR,
   1551     DDR34_PHY_BYTE_LANE_0_READ_FIFO_DATAr_DATA,
   1552     DDR34_PHY_BYTE_LANE_0_READ_FIFO_DM_DBIr_RESERVED0,
   1553     DDR34_PHY_BYTE_LANE_0_READ_FIFO_DM_DBIr_DM_DBI,
   1554     DDR34_PHY_BYTE_LANE_0_READ_FIFO_STATUSr_RESERVED0,
   1555     DDR34_PHY_BYTE_LANE_0_READ_FIFO_STATUSr_OVERFLOW,
   1556     DDR34_PHY_BYTE_LANE_0_READ_FIFO_STATUSr_UNDERFLOW,
   1557     DDR34_PHY_BYTE_LANE_0_READ_FIFO_CLEARr_RESERVED0,
   1558     DDR34_PHY_BYTE_LANE_0_READ_FIFO_CLEARr_CLEAR,
   1559     DDR34_PHY_BYTE_LANE_0_IDLE_PAD_CONTROLr_IDLE,
   1560     DDR34_PHY_BYTE_LANE_0_IDLE_PAD_CONTROLr_RESERVED0,
   1561     DDR34_PHY_BYTE_LANE_0_IDLE_PAD_CONTROLr_AUTO_DQ_RXENB_MODE,
   1562     DDR34_PHY_BYTE_LANE_0_IDLE_PAD_CONTROLr_AUTO_DQ_IDDQ_MODE,
   1563     DDR34_PHY_BYTE_LANE_0_IDLE_PAD_CONTROLr_RESERVED_for_padding1,
   1564     DDR34_PHY_BYTE_LANE_0_IDLE_PAD_CONTROLr_IO_IDLE_ENABLE,
   1565     DDR34_PHY_BYTE_LANE_0_IDLE_PAD_CONTROLr_RXENB,
   1566     DDR34_PHY_BYTE_LANE_0_IDLE_PAD_CONTROLr_IDDQ,
   1567     DDR34_PHY_BYTE_LANE_0_IDLE_PAD_CONTROLr_DOUT_N,
   1568     DDR34_PHY_BYTE_LANE_0_IDLE_PAD_CONTROLr_DOUT_P,
   1569     DDR34_PHY_BYTE_LANE_0_DRIVE_PAD_CTLr_RESERVED0,
   1570     DDR34_PHY_BYTE_LANE_0_DRIVE_PAD_CTLr_BL_PD_IDLE_STRENGTH,
   1571     DDR34_PHY_BYTE_LANE_0_DRIVE_PAD_CTLr_BL_ND_IDLE_STRENGTH,
   1572     DDR34_PHY_BYTE_LANE_0_DRIVE_PAD_CTLr_BL_PD_TERM_STRENGTH,
   1573     DDR34_PHY_BYTE_LANE_0_DRIVE_PAD_CTLr_BL_ND_TERM_STRENGTH,
   1574     DDR34_PHY_BYTE_LANE_0_DRIVE_PAD_CTLr_BL_PD_STRENGTH,
   1575     DDR34_PHY_BYTE_LANE_0_DRIVE_PAD_CTLr_BL_ND_STRENGTH,
   1576     DDR34_PHY_BYTE_LANE_0_RD_EN_DRIVE_PAD_CTLr_RESERVED0,
   1577     DDR34_PHY_BYTE_LANE_0_RD_EN_DRIVE_PAD_CTLr_EDC_RD_EN_PD_STRENGTH,
   1578     DDR34_PHY_BYTE_LANE_0_RD_EN_DRIVE_PAD_CTLr_EDC_RD_EN_ND_STRENGTH,
   1579     DDR34_PHY_BYTE_LANE_0_RD_EN_DRIVE_PAD_CTLr_BL_RD_EN_PD_STRENGTH,
   1580     DDR34_PHY_BYTE_LANE_0_RD_EN_DRIVE_PAD_CTLr_BL_RD_EN_ND_STRENGTH,
   1581     DDR34_PHY_BYTE_LANE_0_STATIC_PAD_CTLr_RESERVED0,
   1582     DDR34_PHY_BYTE_LANE_0_STATIC_PAD_CTLr_DQS_MODE,
   1583     DDR34_PHY_BYTE_LANE_0_STATIC_PAD_CTLr_RESERVED1,
   1584     DDR34_PHY_BYTE_LANE_0_STATIC_PAD_CTLr_EDC_MODE,
   1585     DDR34_PHY_BYTE_LANE_0_STATIC_PAD_CTLr_RESERVED2,
   1586     DDR34_PHY_BYTE_LANE_0_STATIC_PAD_CTLr_WDBI_ENABLE,
   1587     DDR34_PHY_BYTE_LANE_0_STATIC_PAD_CTLr_RDBI_ENABLE,
   1588     DDR34_PHY_BYTE_LANE_0_STATIC_PAD_CTLr_DM_MODE,
   1589     DDR34_PHY_BYTE_LANE_0_STATIC_PAD_CTLr_RESERVED3,
   1590     DDR34_PHY_BYTE_LANE_0_STATIC_PAD_CTLr_DQS_TX_DIS,
   1591     DDR34_PHY_BYTE_LANE_0_STATIC_PAD_CTLr_RESERVED4,
   1592     DDR34_PHY_BYTE_LANE_0_STATIC_PAD_CTLr_RX_MODE,
   1593     DDR34_PHY_BYTE_LANE_0_WR_PREAMBLE_MODEr_RESERVED0,
   1594     DDR34_PHY_BYTE_LANE_0_WR_PREAMBLE_MODEr_DQ_POSTAM_BITS,
   1595     DDR34_PHY_BYTE_LANE_0_WR_PREAMBLE_MODEr_DQ_PREAM_BITS,
   1596     DDR34_PHY_BYTE_LANE_0_WR_PREAMBLE_MODEr_DQS,
   1597     DDR34_PHY_BYTE_LANE_0_WR_PREAMBLE_MODEr_RESERVED1,
   1598     DDR34_PHY_BYTE_LANE_0_WR_PREAMBLE_MODEr_DQS_POSTAM_BITS,
   1599     DDR34_PHY_BYTE_LANE_0_WR_PREAMBLE_MODEr_DQS_PREAM_BITS,
   1600     DDR34_PHY_BYTE_LANE_0_ODT_CONTROLr_RESERVED_for_padding0,
   1601     DDR34_PHY_BYTE_LANE_0_ODT_CONTROLr_RESERVED1,
   1602     DDR34_PHY_BYTE_LANE_0_ODT_CONTROLr_ODT_ENABLE,
   1603     DDR34_PHY_BYTE_LANE_0_ODT_CONTROLr_ODT_DELAY,
   1604     DDR34_PHY_BYTE_LANE_0_ODT_CONTROLr_ODT_POST_LENGTH,
   1605     DDR34_PHY_BYTE_LANE_0_ODT_CONTROLr_ODT_PRE_LENGTH,
   1606     DDR34_PHY_BYTE_LANE_0_EDC_DPD_CONTROLr_RESERVED0,
   1607     DDR34_PHY_BYTE_LANE_0_EDC_DPD_CONTROLr_DQS_PHASE_OVERRIDE_VALUE,
   1608     DDR34_PHY_BYTE_LANE_0_EDC_DPD_CONTROLr_DQS_PHASE_OVERRIDE_ENABLE,
   1609     DDR34_PHY_BYTE_LANE_0_EDC_DPD_CONTROLr_SET_ADJ_EN,
   1610     DDR34_PHY_BYTE_LANE_0_EDC_DPD_CONTROLr_UPDATE,
   1611     DDR34_PHY_BYTE_LANE_0_EDC_DPD_CONTROLr_MONITOR,
   1612     DDR34_PHY_BYTE_LANE_0_EDC_DPD_CONTROLr_INIT,
   1613     DDR34_PHY_BYTE_LANE_0_EDC_DPD_STATUSr_RESERVED0,
   1614     DDR34_PHY_BYTE_LANE_0_EDC_DPD_STATUSr_CURRENT_DQS_PHASE,
   1615     DDR34_PHY_BYTE_LANE_0_EDC_DPD_STATUSr_CURRENT_VDL_SETTING,
   1616     DDR34_PHY_BYTE_LANE_0_EDC_DPD_STATUSr_RESERVED1,
   1617     DDR34_PHY_BYTE_LANE_0_EDC_DPD_STATUSr_INIT_DQS_PHASE,
   1618     DDR34_PHY_BYTE_LANE_0_EDC_DPD_STATUSr_INIT_VDL_SETTING,
   1619     DDR34_PHY_BYTE_LANE_0_EDC_DPD_STATUSr_EDGE_ERROR,
   1620     DDR34_PHY_BYTE_LANE_0_EDC_DPD_STATUSr_MONITOR_BUSY,
   1621     DDR34_PHY_BYTE_LANE_0_EDC_DPD_STATUSr_INIT_BUSY,
   1622     DDR34_PHY_BYTE_LANE_0_EDC_DPD_STATUSr_INIT_DONE,
   1623     DDR34_PHY_BYTE_LANE_0_EDC_DPD_OUT_CONTROLr_RESERVED0,
   1624     DDR34_PHY_BYTE_LANE_0_EDC_DPD_OUT_CONTROLr_LOWER_LIMIT,
   1625     DDR34_PHY_BYTE_LANE_0_EDC_DPD_OUT_CONTROLr_UPPER_LIMIT,
   1626     DDR34_PHY_BYTE_LANE_0_EDC_DPD_OUT_CONTROLr_RESERVED1,
   1627     DDR34_PHY_BYTE_LANE_0_EDC_DPD_OUT_CONTROLr_ENABLE,
   1628     DDR34_PHY_BYTE_LANE_0_EDC_DPD_OUT_STATUSr_RESERVED0,
   1629     DDR34_PHY_BYTE_LANE_0_EDC_DPD_OUT_STATUSr_VDL_SETTING,
   1630     DDR34_PHY_BYTE_LANE_0_EDC_DPD_OUT_STATUSr_RESERVED1,
   1631     DDR34_PHY_BYTE_LANE_0_EDC_DPD_OUT_STATUSr_VALID,
   1632     DDR34_PHY_BYTE_LANE_0_EDC_DPD_OUT_STATUSr_CLEAR_RESERVED0,
   1633     DDR34_PHY_BYTE_LANE_0_EDC_DPD_OUT_STATUSr_CLEAR_CLEAR,
   1634     DDR34_PHY_BYTE_LANE_0_EDC_DPD_OUT_STATUS_CLEARr_RESERVED0,
   1635     DDR34_PHY_BYTE_LANE_0_EDC_DPD_OUT_STATUS_CLEARr_CLEAR,
   1636     DDR34_PHY_BYTE_LANE_0_EDC_CRC_CONTROLr_BUSY,
   1637     DDR34_PHY_BYTE_LANE_0_EDC_CRC_CONTROLr_RESERVED0,
   1638     DDR34_PHY_BYTE_LANE_0_EDC_CRC_CONTROLr_FORCE,
   1639     DDR34_PHY_BYTE_LANE_0_EDC_CRC_CONTROLr_RESERVED1,
   1640     DDR34_PHY_BYTE_LANE_0_EDC_CRC_CONTROLr_CRCWL,
   1641     DDR34_PHY_BYTE_LANE_0_EDC_CRC_CONTROLr_RESERVED2,
   1642     DDR34_PHY_BYTE_LANE_0_EDC_CRC_CONTROLr_CRCRL,
   1643     DDR34_PHY_BYTE_LANE_0_EDC_CRC_CONTROLr_RESERVED3,
   1644     DDR34_PHY_BYTE_LANE_0_EDC_CRC_CONTROLr_COUNT_MODE,
   1645     DDR34_PHY_BYTE_LANE_0_EDC_CRC_CONTROLr_ENABLE_WR,
   1646     DDR34_PHY_BYTE_LANE_0_EDC_CRC_CONTROLr_ENABLE_RD,
   1647     DDR34_PHY_BYTE_LANE_0_EDC_CRC_STATUSr_RESERVED0,
   1648     DDR34_PHY_BYTE_LANE_0_EDC_CRC_STATUSr_WR_FAIL,
   1649     DDR34_PHY_BYTE_LANE_0_EDC_CRC_STATUSr_WR_PASS,
   1650     DDR34_PHY_BYTE_LANE_0_EDC_CRC_STATUSr_RD_FAIL,
   1651     DDR34_PHY_BYTE_LANE_0_EDC_CRC_STATUSr_RD_PASS,
   1652     DDR34_PHY_BYTE_LANE_0_EDC_CRC_STATUSr_CLEAR_RESERVED0,
   1653     DDR34_PHY_BYTE_LANE_0_EDC_CRC_STATUSr_CLEAR_CLEAR,
   1654     DDR34_PHY_BYTE_LANE_0_EDC_CRC_COUNTr_RESERVED0,
   1655     DDR34_PHY_BYTE_LANE_0_EDC_CRC_COUNTr_WR_COUNT,
   1656     DDR34_PHY_BYTE_LANE_0_EDC_CRC_COUNTr_RESERVED1,
   1657     DDR34_PHY_BYTE_LANE_0_EDC_CRC_COUNTr_RD_COUNT,
   1658     DDR34_PHY_BYTE_LANE_0_EDC_CRC_STATUS_CLEARr_RESERVED0,
   1659     DDR34_PHY_BYTE_LANE_0_EDC_CRC_STATUS_CLEARr_CLEAR,
   1660     DDR34_PHY_BYTE_LANE_0_BL_SPARE_REGr_RESERVED_for_eco0,
   1661     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_Pr_BUSY,
   1662     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_Pr_RESERVED0,
   1663     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_Pr_FORCE,
   1664     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_Pr_RESERVED1,
   1665     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_Pr_ADJ_EN,
   1666     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_Pr_RESERVED2,
   1667     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_Pr_VDL_STEP,
   1668     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_Nr_BUSY,
   1669     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_Nr_RESERVED0,
   1670     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_Nr_FORCE,
   1671     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_Nr_RESERVED1,
   1672     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_Nr_ADJ_EN,
   1673     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_Nr_RESERVED2,
   1674     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_Nr_VDL_STEP,
   1675     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0r_BUSY,
   1676     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0r_RESERVED0,
   1677     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0r_FORCE,
   1678     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0r_RESERVED1,
   1679     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0r_ADJ_EN,
   1680     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0r_RESERVED2,
   1681     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0r_VDL_STEP,
   1682     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1r_BUSY,
   1683     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1r_RESERVED0,
   1684     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1r_FORCE,
   1685     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1r_RESERVED1,
   1686     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1r_ADJ_EN,
   1687     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1r_RESERVED2,
   1688     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1r_VDL_STEP,
   1689     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2r_BUSY,
   1690     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2r_RESERVED0,
   1691     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2r_FORCE,
   1692     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2r_RESERVED1,
   1693     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2r_ADJ_EN,
   1694     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2r_RESERVED2,
   1695     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2r_VDL_STEP,
   1696     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3r_BUSY,
   1697     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3r_RESERVED0,
   1698     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3r_FORCE,
   1699     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3r_RESERVED1,
   1700     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3r_ADJ_EN,
   1701     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3r_RESERVED2,
   1702     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3r_VDL_STEP,
   1703     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4r_BUSY,
   1704     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4r_RESERVED0,
   1705     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4r_FORCE,
   1706     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4r_RESERVED1,
   1707     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4r_ADJ_EN,
   1708     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4r_RESERVED2,
   1709     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4r_VDL_STEP,
   1710     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5r_BUSY,
   1711     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5r_RESERVED0,
   1712     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5r_FORCE,
   1713     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5r_RESERVED1,
   1714     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5r_ADJ_EN,
   1715     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5r_RESERVED2,
   1716     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5r_VDL_STEP,
   1717     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6r_BUSY,
   1718     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6r_RESERVED0,
   1719     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6r_FORCE,
   1720     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6r_RESERVED1,
   1721     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6r_ADJ_EN,
   1722     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6r_RESERVED2,
   1723     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6r_VDL_STEP,
   1724     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7r_BUSY,
   1725     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7r_RESERVED0,
   1726     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7r_FORCE,
   1727     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7r_RESERVED1,
   1728     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7r_ADJ_EN,
   1729     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7r_RESERVED2,
   1730     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7r_VDL_STEP,
   1731     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DMr_BUSY,
   1732     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DMr_RESERVED0,
   1733     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DMr_FORCE,
   1734     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DMr_RESERVED1,
   1735     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DMr_ADJ_EN,
   1736     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DMr_RESERVED2,
   1737     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DMr_VDL_STEP,
   1738     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_EDCr_BUSY,
   1739     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_EDCr_RESERVED0,
   1740     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_EDCr_FORCE,
   1741     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_EDCr_RESERVED1,
   1742     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_EDCr_ADJ_EN,
   1743     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_EDCr_RESERVED2,
   1744     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_EDCr_VDL_STEP,
   1745     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSPr_BUSY,
   1746     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSPr_RESERVED0,
   1747     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSPr_FORCE,
   1748     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSPr_RESERVED1,
   1749     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSPr_ADJ_EN,
   1750     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSPr_RESERVED2,
   1751     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSPr_VDL_STEP,
   1752     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSNr_BUSY,
   1753     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSNr_RESERVED0,
   1754     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSNr_FORCE,
   1755     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSNr_RESERVED1,
   1756     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSNr_ADJ_EN,
   1757     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSNr_RESERVED2,
   1758     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSNr_VDL_STEP,
   1759     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0Pr_BUSY,
   1760     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0Pr_RESERVED0,
   1761     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0Pr_FORCE,
   1762     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0Pr_RESERVED1,
   1763     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0Pr_ADJ_EN,
   1764     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0Pr_RESERVED2,
   1765     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0Pr_VDL_STEP,
   1766     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0Nr_BUSY,
   1767     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0Nr_RESERVED0,
   1768     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0Nr_FORCE,
   1769     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0Nr_RESERVED1,
   1770     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0Nr_ADJ_EN,
   1771     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0Nr_RESERVED2,
   1772     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0Nr_VDL_STEP,
   1773     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1Pr_BUSY,
   1774     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1Pr_RESERVED0,
   1775     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1Pr_FORCE,
   1776     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1Pr_RESERVED1,
   1777     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1Pr_ADJ_EN,
   1778     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1Pr_RESERVED2,
   1779     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1Pr_VDL_STEP,
   1780     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1Nr_BUSY,
   1781     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1Nr_RESERVED0,
   1782     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1Nr_FORCE,
   1783     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1Nr_RESERVED1,
   1784     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1Nr_ADJ_EN,
   1785     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1Nr_RESERVED2,
   1786     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1Nr_VDL_STEP,
   1787     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2Pr_BUSY,
   1788     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2Pr_RESERVED0,
   1789     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2Pr_FORCE,
   1790     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2Pr_RESERVED1,
   1791     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2Pr_ADJ_EN,
   1792     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2Pr_RESERVED2,
   1793     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2Pr_VDL_STEP,
   1794     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2Nr_BUSY,
   1795     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2Nr_RESERVED0,
   1796     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2Nr_FORCE,
   1797     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2Nr_RESERVED1,
   1798     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2Nr_ADJ_EN,
   1799     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2Nr_RESERVED2,
   1800     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2Nr_VDL_STEP,
   1801     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3Pr_BUSY,
   1802     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3Pr_RESERVED0,
   1803     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3Pr_FORCE,
   1804     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3Pr_RESERVED1,
   1805     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3Pr_ADJ_EN,
   1806     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3Pr_RESERVED2,
   1807     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3Pr_VDL_STEP,
   1808     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3Nr_BUSY,
   1809     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3Nr_RESERVED0,
   1810     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3Nr_FORCE,
   1811     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3Nr_RESERVED1,
   1812     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3Nr_ADJ_EN,
   1813     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3Nr_RESERVED2,
   1814     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3Nr_VDL_STEP,
   1815     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4Pr_BUSY,
   1816     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4Pr_RESERVED0,
   1817     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4Pr_FORCE,
   1818     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4Pr_RESERVED1,
   1819     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4Pr_ADJ_EN,
   1820     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4Pr_RESERVED2,
   1821     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4Pr_VDL_STEP,
   1822     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4Nr_BUSY,
   1823     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4Nr_RESERVED0,
   1824     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4Nr_FORCE,
   1825     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4Nr_RESERVED1,
   1826     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4Nr_ADJ_EN,
   1827     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4Nr_RESERVED2,
   1828     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4Nr_VDL_STEP,
   1829     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5Pr_BUSY,
   1830     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5Pr_RESERVED0,
   1831     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5Pr_FORCE,
   1832     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5Pr_RESERVED1,
   1833     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5Pr_ADJ_EN,
   1834     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5Pr_RESERVED2,
   1835     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5Pr_VDL_STEP,
   1836     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5Nr_BUSY,
   1837     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5Nr_RESERVED0,
   1838     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5Nr_FORCE,
   1839     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5Nr_RESERVED1,
   1840     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5Nr_ADJ_EN,
   1841     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5Nr_RESERVED2,
   1842     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5Nr_VDL_STEP,
   1843     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6Pr_BUSY,
   1844     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6Pr_RESERVED0,
   1845     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6Pr_FORCE,
   1846     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6Pr_RESERVED1,
   1847     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6Pr_ADJ_EN,
   1848     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6Pr_RESERVED2,
   1849     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6Pr_VDL_STEP,
   1850     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6Nr_BUSY,
   1851     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6Nr_RESERVED0,
   1852     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6Nr_FORCE,
   1853     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6Nr_RESERVED1,
   1854     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6Nr_ADJ_EN,
   1855     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6Nr_RESERVED2,
   1856     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6Nr_VDL_STEP,
   1857     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7Pr_BUSY,
   1858     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7Pr_RESERVED0,
   1859     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7Pr_FORCE,
   1860     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7Pr_RESERVED1,
   1861     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7Pr_ADJ_EN,
   1862     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7Pr_RESERVED2,
   1863     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7Pr_VDL_STEP,
   1864     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7Nr_BUSY,
   1865     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7Nr_RESERVED0,
   1866     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7Nr_FORCE,
   1867     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7Nr_RESERVED1,
   1868     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7Nr_ADJ_EN,
   1869     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7Nr_RESERVED2,
   1870     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7Nr_VDL_STEP,
   1871     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMPr_BUSY,
   1872     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMPr_RESERVED0,
   1873     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMPr_FORCE,
   1874     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMPr_RESERVED1,
   1875     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMPr_ADJ_EN,
   1876     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMPr_RESERVED2,
   1877     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMPr_VDL_STEP,
   1878     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMNr_BUSY,
   1879     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMNr_RESERVED0,
   1880     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMNr_FORCE,
   1881     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMNr_RESERVED1,
   1882     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMNr_ADJ_EN,
   1883     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMNr_RESERVED2,
   1884     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMNr_VDL_STEP,
   1885     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCPr_BUSY,
   1886     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCPr_RESERVED0,
   1887     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCPr_FORCE,
   1888     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCPr_RESERVED1,
   1889     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCPr_ADJ_EN,
   1890     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCPr_RESERVED2,
   1891     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCPr_VDL_STEP,
   1892     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCNr_BUSY,
   1893     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCNr_RESERVED0,
   1894     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCNr_FORCE,
   1895     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCNr_RESERVED1,
   1896     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCNr_ADJ_EN,
   1897     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCNr_RESERVED2,
   1898     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCNr_VDL_STEP,
   1899     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0r_BUSY,
   1900     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0r_RESERVED0,
   1901     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0r_FORCE,
   1902     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0r_RESERVED1,
   1903     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0r_ADJ_EN,
   1904     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0r_RESERVED2,
   1905     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0r_VDL_STEP,
   1906     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1r_BUSY,
   1907     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1r_RESERVED0,
   1908     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1r_FORCE,
   1909     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1r_RESERVED1,
   1910     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1r_ADJ_EN,
   1911     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1r_RESERVED2,
   1912     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1r_VDL_STEP,
   1913     DDR34_PHY_BYTE_LANE_1_VDL_CLK_CONTROLr_BUSY,
   1914     DDR34_PHY_BYTE_LANE_1_VDL_CLK_CONTROLr_RESERVED0,
   1915     DDR34_PHY_BYTE_LANE_1_VDL_CLK_CONTROLr_FORCE,
   1916     DDR34_PHY_BYTE_LANE_1_VDL_CLK_CONTROLr_RESERVED1,
   1917     DDR34_PHY_BYTE_LANE_1_VDL_CLK_CONTROLr_ADJ_EN,
   1918     DDR34_PHY_BYTE_LANE_1_VDL_CLK_CONTROLr_RESERVED2,
   1919     DDR34_PHY_BYTE_LANE_1_VDL_CLK_CONTROLr_VDL_STEP,
   1920     DDR34_PHY_BYTE_LANE_1_VDL_LDE_CONTROLr_BUSY,
   1921     DDR34_PHY_BYTE_LANE_1_VDL_LDE_CONTROLr_RESERVED0,
   1922     DDR34_PHY_BYTE_LANE_1_VDL_LDE_CONTROLr_FORCE,
   1923     DDR34_PHY_BYTE_LANE_1_VDL_LDE_CONTROLr_RESERVED1,
   1924     DDR34_PHY_BYTE_LANE_1_VDL_LDE_CONTROLr_ADJ_EN,
   1925     DDR34_PHY_BYTE_LANE_1_VDL_LDE_CONTROLr_RESERVED2,
   1926     DDR34_PHY_BYTE_LANE_1_VDL_LDE_CONTROLr_VDL_STEP,
   1927     DDR34_PHY_BYTE_LANE_1_RD_EN_DLY_CYCr_BUSY,
   1928     DDR34_PHY_BYTE_LANE_1_RD_EN_DLY_CYCr_RESERVED0,
   1929     DDR34_PHY_BYTE_LANE_1_RD_EN_DLY_CYCr_FORCE,
   1930     DDR34_PHY_BYTE_LANE_1_RD_EN_DLY_CYCr_RESERVED1,
   1931     DDR34_PHY_BYTE_LANE_1_RD_EN_DLY_CYCr_CS1_CYCLES,
   1932     DDR34_PHY_BYTE_LANE_1_RD_EN_DLY_CYCr_CS0_CYCLES,
   1933     DDR34_PHY_BYTE_LANE_1_WR_CHAN_DLY_CYCr_BUSY,
   1934     DDR34_PHY_BYTE_LANE_1_WR_CHAN_DLY_CYCr_RESERVED0,
   1935     DDR34_PHY_BYTE_LANE_1_WR_CHAN_DLY_CYCr_FORCE,
   1936     DDR34_PHY_BYTE_LANE_1_WR_CHAN_DLY_CYCr_RESERVED1,
   1937     DDR34_PHY_BYTE_LANE_1_WR_CHAN_DLY_CYCr_CYCLES,
   1938     DDR34_PHY_BYTE_LANE_1_READ_CONTROLr_RESERVED0,
   1939     DDR34_PHY_BYTE_LANE_1_READ_CONTROLr_MODE,
   1940     DDR34_PHY_BYTE_LANE_1_READ_CONTROLr_RESERVED1,
   1941     DDR34_PHY_BYTE_LANE_1_READ_CONTROLr_RD_DATA_DLY,
   1942     DDR34_PHY_BYTE_LANE_1_READ_FIFO_ADDRr_RESERVED0,
   1943     DDR34_PHY_BYTE_LANE_1_READ_FIFO_ADDRr_ADDR,
   1944     DDR34_PHY_BYTE_LANE_1_READ_FIFO_DATAr_DATA,
   1945     DDR34_PHY_BYTE_LANE_1_READ_FIFO_DM_DBIr_RESERVED0,
   1946     DDR34_PHY_BYTE_LANE_1_READ_FIFO_DM_DBIr_DM_DBI,
   1947     DDR34_PHY_BYTE_LANE_1_READ_FIFO_STATUSr_RESERVED0,
   1948     DDR34_PHY_BYTE_LANE_1_READ_FIFO_STATUSr_OVERFLOW,
   1949     DDR34_PHY_BYTE_LANE_1_READ_FIFO_STATUSr_UNDERFLOW,
   1950     DDR34_PHY_BYTE_LANE_1_READ_FIFO_CLEARr_RESERVED0,
   1951     DDR34_PHY_BYTE_LANE_1_READ_FIFO_CLEARr_CLEAR,
   1952     DDR34_PHY_BYTE_LANE_1_IDLE_PAD_CONTROLr_IDLE,
   1953     DDR34_PHY_BYTE_LANE_1_IDLE_PAD_CONTROLr_RESERVED0,
   1954     DDR34_PHY_BYTE_LANE_1_IDLE_PAD_CONTROLr_AUTO_DQ_RXENB_MODE,
   1955     DDR34_PHY_BYTE_LANE_1_IDLE_PAD_CONTROLr_AUTO_DQ_IDDQ_MODE,
   1956     DDR34_PHY_BYTE_LANE_1_IDLE_PAD_CONTROLr_RESERVED_for_padding1,
   1957     DDR34_PHY_BYTE_LANE_1_IDLE_PAD_CONTROLr_IO_IDLE_ENABLE,
   1958     DDR34_PHY_BYTE_LANE_1_IDLE_PAD_CONTROLr_RXENB,
   1959     DDR34_PHY_BYTE_LANE_1_IDLE_PAD_CONTROLr_IDDQ,
   1960     DDR34_PHY_BYTE_LANE_1_IDLE_PAD_CONTROLr_DOUT_N,
   1961     DDR34_PHY_BYTE_LANE_1_IDLE_PAD_CONTROLr_DOUT_P,
   1962     DDR34_PHY_BYTE_LANE_1_DRIVE_PAD_CTLr_RESERVED0,
   1963     DDR34_PHY_BYTE_LANE_1_DRIVE_PAD_CTLr_BL_PD_IDLE_STRENGTH,
   1964     DDR34_PHY_BYTE_LANE_1_DRIVE_PAD_CTLr_BL_ND_IDLE_STRENGTH,
   1965     DDR34_PHY_BYTE_LANE_1_DRIVE_PAD_CTLr_BL_PD_TERM_STRENGTH,
   1966     DDR34_PHY_BYTE_LANE_1_DRIVE_PAD_CTLr_BL_ND_TERM_STRENGTH,
   1967     DDR34_PHY_BYTE_LANE_1_DRIVE_PAD_CTLr_BL_PD_STRENGTH,
   1968     DDR34_PHY_BYTE_LANE_1_DRIVE_PAD_CTLr_BL_ND_STRENGTH,
   1969     DDR34_PHY_BYTE_LANE_1_RD_EN_DRIVE_PAD_CTLr_RESERVED0,
   1970     DDR34_PHY_BYTE_LANE_1_RD_EN_DRIVE_PAD_CTLr_EDC_RD_EN_PD_STRENGTH,
   1971     DDR34_PHY_BYTE_LANE_1_RD_EN_DRIVE_PAD_CTLr_EDC_RD_EN_ND_STRENGTH,
   1972     DDR34_PHY_BYTE_LANE_1_RD_EN_DRIVE_PAD_CTLr_BL_RD_EN_PD_STRENGTH,
   1973     DDR34_PHY_BYTE_LANE_1_RD_EN_DRIVE_PAD_CTLr_BL_RD_EN_ND_STRENGTH,
   1974     DDR34_PHY_BYTE_LANE_1_STATIC_PAD_CTLr_RESERVED0,
   1975     DDR34_PHY_BYTE_LANE_1_STATIC_PAD_CTLr_DQS_MODE,
   1976     DDR34_PHY_BYTE_LANE_1_STATIC_PAD_CTLr_RESERVED1,
   1977     DDR34_PHY_BYTE_LANE_1_STATIC_PAD_CTLr_EDC_MODE,
   1978     DDR34_PHY_BYTE_LANE_1_STATIC_PAD_CTLr_RESERVED2,
   1979     DDR34_PHY_BYTE_LANE_1_STATIC_PAD_CTLr_WDBI_ENABLE,
   1980     DDR34_PHY_BYTE_LANE_1_STATIC_PAD_CTLr_RDBI_ENABLE,
   1981     DDR34_PHY_BYTE_LANE_1_STATIC_PAD_CTLr_DM_MODE,
   1982     DDR34_PHY_BYTE_LANE_1_STATIC_PAD_CTLr_RESERVED3,
   1983     DDR34_PHY_BYTE_LANE_1_STATIC_PAD_CTLr_DQS_TX_DIS,
   1984     DDR34_PHY_BYTE_LANE_1_STATIC_PAD_CTLr_RESERVED4,
   1985     DDR34_PHY_BYTE_LANE_1_STATIC_PAD_CTLr_RX_MODE,
   1986     DDR34_PHY_BYTE_LANE_1_WR_PREAMBLE_MODEr_RESERVED0,
   1987     DDR34_PHY_BYTE_LANE_1_WR_PREAMBLE_MODEr_DQ_POSTAM_BITS,
   1988     DDR34_PHY_BYTE_LANE_1_WR_PREAMBLE_MODEr_DQ_PREAM_BITS,
   1989     DDR34_PHY_BYTE_LANE_1_WR_PREAMBLE_MODEr_DQS,
   1990     DDR34_PHY_BYTE_LANE_1_WR_PREAMBLE_MODEr_RESERVED1,
   1991     DDR34_PHY_BYTE_LANE_1_WR_PREAMBLE_MODEr_DQS_POSTAM_BITS,
   1992     DDR34_PHY_BYTE_LANE_1_WR_PREAMBLE_MODEr_DQS_PREAM_BITS,
   1993     DDR34_PHY_BYTE_LANE_1_ODT_CONTROLr_RESERVED_for_padding0,
   1994     DDR34_PHY_BYTE_LANE_1_ODT_CONTROLr_RESERVED1,
   1995     DDR34_PHY_BYTE_LANE_1_ODT_CONTROLr_ODT_ENABLE,
   1996     DDR34_PHY_BYTE_LANE_1_ODT_CONTROLr_ODT_DELAY,
   1997     DDR34_PHY_BYTE_LANE_1_ODT_CONTROLr_ODT_POST_LENGTH,
   1998     DDR34_PHY_BYTE_LANE_1_ODT_CONTROLr_ODT_PRE_LENGTH,
   1999     DDR34_PHY_BYTE_LANE_1_EDC_DPD_CONTROLr_RESERVED0,
   2000     DDR34_PHY_BYTE_LANE_1_EDC_DPD_CONTROLr_DQS_PHASE_OVERRIDE_VALUE,
   2001     DDR34_PHY_BYTE_LANE_1_EDC_DPD_CONTROLr_DQS_PHASE_OVERRIDE_ENABLE,
   2002     DDR34_PHY_BYTE_LANE_1_EDC_DPD_CONTROLr_SET_ADJ_EN,
   2003     DDR34_PHY_BYTE_LANE_1_EDC_DPD_CONTROLr_UPDATE,
   2004     DDR34_PHY_BYTE_LANE_1_EDC_DPD_CONTROLr_MONITOR,
   2005     DDR34_PHY_BYTE_LANE_1_EDC_DPD_CONTROLr_INIT,
   2006     DDR34_PHY_BYTE_LANE_1_EDC_DPD_STATUSr_RESERVED0,
   2007     DDR34_PHY_BYTE_LANE_1_EDC_DPD_STATUSr_CURRENT_DQS_PHASE,
   2008     DDR34_PHY_BYTE_LANE_1_EDC_DPD_STATUSr_CURRENT_VDL_SETTING,
   2009     DDR34_PHY_BYTE_LANE_1_EDC_DPD_STATUSr_RESERVED1,
   2010     DDR34_PHY_BYTE_LANE_1_EDC_DPD_STATUSr_INIT_DQS_PHASE,
   2011     DDR34_PHY_BYTE_LANE_1_EDC_DPD_STATUSr_INIT_VDL_SETTING,
   2012     DDR34_PHY_BYTE_LANE_1_EDC_DPD_STATUSr_EDGE_ERROR,
   2013     DDR34_PHY_BYTE_LANE_1_EDC_DPD_STATUSr_MONITOR_BUSY,
   2014     DDR34_PHY_BYTE_LANE_1_EDC_DPD_STATUSr_INIT_BUSY,
   2015     DDR34_PHY_BYTE_LANE_1_EDC_DPD_STATUSr_INIT_DONE,
   2016     DDR34_PHY_BYTE_LANE_1_EDC_DPD_OUT_CONTROLr_RESERVED0,
   2017     DDR34_PHY_BYTE_LANE_1_EDC_DPD_OUT_CONTROLr_LOWER_LIMIT,
   2018     DDR34_PHY_BYTE_LANE_1_EDC_DPD_OUT_CONTROLr_UPPER_LIMIT,
   2019     DDR34_PHY_BYTE_LANE_1_EDC_DPD_OUT_CONTROLr_RESERVED1,
   2020     DDR34_PHY_BYTE_LANE_1_EDC_DPD_OUT_CONTROLr_ENABLE,
   2021     DDR34_PHY_BYTE_LANE_1_EDC_DPD_OUT_STATUSr_RESERVED0,
   2022     DDR34_PHY_BYTE_LANE_1_EDC_DPD_OUT_STATUSr_VDL_SETTING,
   2023     DDR34_PHY_BYTE_LANE_1_EDC_DPD_OUT_STATUSr_RESERVED1,
   2024     DDR34_PHY_BYTE_LANE_1_EDC_DPD_OUT_STATUSr_VALID,
   2025     DDR34_PHY_BYTE_LANE_1_EDC_DPD_OUT_STATUSr_CLEAR_RESERVED0,
   2026     DDR34_PHY_BYTE_LANE_1_EDC_DPD_OUT_STATUSr_CLEAR_CLEAR,
   2027     DDR34_PHY_BYTE_LANE_1_EDC_DPD_OUT_STATUS_CLEARr_RESERVED0,
   2028     DDR34_PHY_BYTE_LANE_1_EDC_DPD_OUT_STATUS_CLEARr_CLEAR,
   2029     DDR34_PHY_BYTE_LANE_1_EDC_CRC_CONTROLr_BUSY,
   2030     DDR34_PHY_BYTE_LANE_1_EDC_CRC_CONTROLr_RESERVED0,
   2031     DDR34_PHY_BYTE_LANE_1_EDC_CRC_CONTROLr_FORCE,
   2032     DDR34_PHY_BYTE_LANE_1_EDC_CRC_CONTROLr_RESERVED1,
   2033     DDR34_PHY_BYTE_LANE_1_EDC_CRC_CONTROLr_CRCWL,
   2034     DDR34_PHY_BYTE_LANE_1_EDC_CRC_CONTROLr_RESERVED2,
   2035     DDR34_PHY_BYTE_LANE_1_EDC_CRC_CONTROLr_CRCRL,
   2036     DDR34_PHY_BYTE_LANE_1_EDC_CRC_CONTROLr_RESERVED3,
   2037     DDR34_PHY_BYTE_LANE_1_EDC_CRC_CONTROLr_COUNT_MODE,
   2038     DDR34_PHY_BYTE_LANE_1_EDC_CRC_CONTROLr_ENABLE_WR,
   2039     DDR34_PHY_BYTE_LANE_1_EDC_CRC_CONTROLr_ENABLE_RD,
   2040     DDR34_PHY_BYTE_LANE_1_EDC_CRC_STATUSr_RESERVED0,
   2041     DDR34_PHY_BYTE_LANE_1_EDC_CRC_STATUSr_WR_FAIL,
   2042     DDR34_PHY_BYTE_LANE_1_EDC_CRC_STATUSr_WR_PASS,
   2043     DDR34_PHY_BYTE_LANE_1_EDC_CRC_STATUSr_RD_FAIL,
   2044     DDR34_PHY_BYTE_LANE_1_EDC_CRC_STATUSr_RD_PASS,
   2045     DDR34_PHY_BYTE_LANE_1_EDC_CRC_STATUSr_CLEAR_RESERVED0,
   2046     DDR34_PHY_BYTE_LANE_1_EDC_CRC_STATUSr_CLEAR_CLEAR,
   2047     DDR34_PHY_BYTE_LANE_1_EDC_CRC_COUNTr_RESERVED0,
   2048     DDR34_PHY_BYTE_LANE_1_EDC_CRC_COUNTr_WR_COUNT,
   2049     DDR34_PHY_BYTE_LANE_1_EDC_CRC_COUNTr_RESERVED1,
   2050     DDR34_PHY_BYTE_LANE_1_EDC_CRC_COUNTr_RD_COUNT,
   2051     DDR34_PHY_BYTE_LANE_1_EDC_CRC_STATUS_CLEARr_RESERVED0,
   2052     DDR34_PHY_BYTE_LANE_1_EDC_CRC_STATUS_CLEARr_CLEAR,
   2053     DDR34_PHY_BYTE_LANE_1_BL_SPARE_REGr_RESERVED_for_eco0,
   2054     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_Pr_BUSY,
   2055     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_Pr_RESERVED0,
   2056     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_Pr_FORCE,
   2057     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_Pr_RESERVED1,
   2058     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_Pr_ADJ_EN,
   2059     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_Pr_RESERVED2,
   2060     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_Pr_VDL_STEP,
   2061     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_Nr_BUSY,
   2062     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_Nr_RESERVED0,
   2063     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_Nr_FORCE,
   2064     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_Nr_RESERVED1,
   2065     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_Nr_ADJ_EN,
   2066     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_Nr_RESERVED2,
   2067     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_Nr_VDL_STEP,
   2068     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ0r_BUSY,
   2069     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ0r_RESERVED0,
   2070     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ0r_FORCE,
   2071     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ0r_RESERVED1,
   2072     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ0r_ADJ_EN,
   2073     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ0r_RESERVED2,
   2074     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ0r_VDL_STEP,
   2075     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ1r_BUSY,
   2076     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ1r_RESERVED0,
   2077     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ1r_FORCE,
   2078     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ1r_RESERVED1,
   2079     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ1r_ADJ_EN,
   2080     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ1r_RESERVED2,
   2081     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ1r_VDL_STEP,
   2082     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ2r_BUSY,
   2083     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ2r_RESERVED0,
   2084     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ2r_FORCE,
   2085     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ2r_RESERVED1,
   2086     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ2r_ADJ_EN,
   2087     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ2r_RESERVED2,
   2088     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ2r_VDL_STEP,
   2089     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ3r_BUSY,
   2090     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ3r_RESERVED0,
   2091     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ3r_FORCE,
   2092     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ3r_RESERVED1,
   2093     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ3r_ADJ_EN,
   2094     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ3r_RESERVED2,
   2095     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ3r_VDL_STEP,
   2096     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ4r_BUSY,
   2097     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ4r_RESERVED0,
   2098     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ4r_FORCE,
   2099     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ4r_RESERVED1,
   2100     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ4r_ADJ_EN,
   2101     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ4r_RESERVED2,
   2102     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ4r_VDL_STEP,
   2103     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ5r_BUSY,
   2104     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ5r_RESERVED0,
   2105     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ5r_FORCE,
   2106     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ5r_RESERVED1,
   2107     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ5r_ADJ_EN,
   2108     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ5r_RESERVED2,
   2109     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ5r_VDL_STEP,
   2110     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ6r_BUSY,
   2111     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ6r_RESERVED0,
   2112     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ6r_FORCE,
   2113     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ6r_RESERVED1,
   2114     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ6r_ADJ_EN,
   2115     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ6r_RESERVED2,
   2116     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ6r_VDL_STEP,
   2117     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ7r_BUSY,
   2118     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ7r_RESERVED0,
   2119     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ7r_FORCE,
   2120     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ7r_RESERVED1,
   2121     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ7r_ADJ_EN,
   2122     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ7r_RESERVED2,
   2123     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ7r_VDL_STEP,
   2124     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DMr_BUSY,
   2125     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DMr_RESERVED0,
   2126     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DMr_FORCE,
   2127     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DMr_RESERVED1,
   2128     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DMr_ADJ_EN,
   2129     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DMr_RESERVED2,
   2130     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DMr_VDL_STEP,
   2131     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_EDCr_BUSY,
   2132     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_EDCr_RESERVED0,
   2133     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_EDCr_FORCE,
   2134     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_EDCr_RESERVED1,
   2135     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_EDCr_ADJ_EN,
   2136     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_EDCr_RESERVED2,
   2137     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_EDCr_VDL_STEP,
   2138     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSPr_BUSY,
   2139     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSPr_RESERVED0,
   2140     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSPr_FORCE,
   2141     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSPr_RESERVED1,
   2142     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSPr_ADJ_EN,
   2143     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSPr_RESERVED2,
   2144     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSPr_VDL_STEP,
   2145     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSNr_BUSY,
   2146     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSNr_RESERVED0,
   2147     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSNr_FORCE,
   2148     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSNr_RESERVED1,
   2149     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSNr_ADJ_EN,
   2150     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSNr_RESERVED2,
   2151     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSNr_VDL_STEP,
   2152     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0Pr_BUSY,
   2153     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0Pr_RESERVED0,
   2154     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0Pr_FORCE,
   2155     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0Pr_RESERVED1,
   2156     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0Pr_ADJ_EN,
   2157     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0Pr_RESERVED2,
   2158     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0Pr_VDL_STEP,
   2159     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0Nr_BUSY,
   2160     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0Nr_RESERVED0,
   2161     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0Nr_FORCE,
   2162     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0Nr_RESERVED1,
   2163     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0Nr_ADJ_EN,
   2164     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0Nr_RESERVED2,
   2165     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0Nr_VDL_STEP,
   2166     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1Pr_BUSY,
   2167     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1Pr_RESERVED0,
   2168     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1Pr_FORCE,
   2169     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1Pr_RESERVED1,
   2170     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1Pr_ADJ_EN,
   2171     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1Pr_RESERVED2,
   2172     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1Pr_VDL_STEP,
   2173     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1Nr_BUSY,
   2174     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1Nr_RESERVED0,
   2175     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1Nr_FORCE,
   2176     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1Nr_RESERVED1,
   2177     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1Nr_ADJ_EN,
   2178     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1Nr_RESERVED2,
   2179     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1Nr_VDL_STEP,
   2180     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2Pr_BUSY,
   2181     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2Pr_RESERVED0,
   2182     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2Pr_FORCE,
   2183     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2Pr_RESERVED1,
   2184     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2Pr_ADJ_EN,
   2185     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2Pr_RESERVED2,
   2186     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2Pr_VDL_STEP,
   2187     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2Nr_BUSY,
   2188     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2Nr_RESERVED0,
   2189     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2Nr_FORCE,
   2190     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2Nr_RESERVED1,
   2191     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2Nr_ADJ_EN,
   2192     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2Nr_RESERVED2,
   2193     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2Nr_VDL_STEP,
   2194     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3Pr_BUSY,
   2195     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3Pr_RESERVED0,
   2196     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3Pr_FORCE,
   2197     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3Pr_RESERVED1,
   2198     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3Pr_ADJ_EN,
   2199     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3Pr_RESERVED2,
   2200     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3Pr_VDL_STEP,
   2201     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3Nr_BUSY,
   2202     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3Nr_RESERVED0,
   2203     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3Nr_FORCE,
   2204     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3Nr_RESERVED1,
   2205     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3Nr_ADJ_EN,
   2206     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3Nr_RESERVED2,
   2207     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3Nr_VDL_STEP,
   2208     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4Pr_BUSY,
   2209     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4Pr_RESERVED0,
   2210     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4Pr_FORCE,
   2211     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4Pr_RESERVED1,
   2212     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4Pr_ADJ_EN,
   2213     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4Pr_RESERVED2,
   2214     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4Pr_VDL_STEP,
   2215     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4Nr_BUSY,
   2216     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4Nr_RESERVED0,
   2217     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4Nr_FORCE,
   2218     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4Nr_RESERVED1,
   2219     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4Nr_ADJ_EN,
   2220     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4Nr_RESERVED2,
   2221     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4Nr_VDL_STEP,
   2222     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5Pr_BUSY,
   2223     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5Pr_RESERVED0,
   2224     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5Pr_FORCE,
   2225     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5Pr_RESERVED1,
   2226     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5Pr_ADJ_EN,
   2227     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5Pr_RESERVED2,
   2228     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5Pr_VDL_STEP,
   2229     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5Nr_BUSY,
   2230     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5Nr_RESERVED0,
   2231     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5Nr_FORCE,
   2232     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5Nr_RESERVED1,
   2233     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5Nr_ADJ_EN,
   2234     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5Nr_RESERVED2,
   2235     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5Nr_VDL_STEP,
   2236     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6Pr_BUSY,
   2237     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6Pr_RESERVED0,
   2238     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6Pr_FORCE,
   2239     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6Pr_RESERVED1,
   2240     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6Pr_ADJ_EN,
   2241     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6Pr_RESERVED2,
   2242     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6Pr_VDL_STEP,
   2243     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6Nr_BUSY,
   2244     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6Nr_RESERVED0,
   2245     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6Nr_FORCE,
   2246     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6Nr_RESERVED1,
   2247     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6Nr_ADJ_EN,
   2248     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6Nr_RESERVED2,
   2249     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6Nr_VDL_STEP,
   2250     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7Pr_BUSY,
   2251     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7Pr_RESERVED0,
   2252     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7Pr_FORCE,
   2253     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7Pr_RESERVED1,
   2254     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7Pr_ADJ_EN,
   2255     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7Pr_RESERVED2,
   2256     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7Pr_VDL_STEP,
   2257     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7Nr_BUSY,
   2258     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7Nr_RESERVED0,
   2259     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7Nr_FORCE,
   2260     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7Nr_RESERVED1,
   2261     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7Nr_ADJ_EN,
   2262     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7Nr_RESERVED2,
   2263     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7Nr_VDL_STEP,
   2264     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMPr_BUSY,
   2265     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMPr_RESERVED0,
   2266     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMPr_FORCE,
   2267     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMPr_RESERVED1,
   2268     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMPr_ADJ_EN,
   2269     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMPr_RESERVED2,
   2270     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMPr_VDL_STEP,
   2271     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMNr_BUSY,
   2272     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMNr_RESERVED0,
   2273     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMNr_FORCE,
   2274     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMNr_RESERVED1,
   2275     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMNr_ADJ_EN,
   2276     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMNr_RESERVED2,
   2277     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMNr_VDL_STEP,
   2278     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EDCPr_BUSY,
   2279     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EDCPr_RESERVED0,
   2280     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EDCPr_FORCE,
   2281     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EDCPr_RESERVED1,
   2282     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EDCPr_ADJ_EN,
   2283     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EDCPr_RESERVED2,
   2284     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EDCPr_VDL_STEP,
   2285     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EDCNr_BUSY,
   2286     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EDCNr_RESERVED0,
   2287     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EDCNr_FORCE,
   2288     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EDCNr_RESERVED1,
   2289     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EDCNr_ADJ_EN,
   2290     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EDCNr_RESERVED2,
   2291     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EDCNr_VDL_STEP,
   2292     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS0r_BUSY,
   2293     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS0r_RESERVED0,
   2294     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS0r_FORCE,
   2295     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS0r_RESERVED1,
   2296     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS0r_ADJ_EN,
   2297     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS0r_RESERVED2,
   2298     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS0r_VDL_STEP,
   2299     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS1r_BUSY,
   2300     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS1r_RESERVED0,
   2301     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS1r_FORCE,
   2302     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS1r_RESERVED1,
   2303     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS1r_ADJ_EN,
   2304     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS1r_RESERVED2,
   2305     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS1r_VDL_STEP,
   2306     DDR34_PHY_BYTE_LANE_2_VDL_CLK_CONTROLr_BUSY,
   2307     DDR34_PHY_BYTE_LANE_2_VDL_CLK_CONTROLr_RESERVED0,
   2308     DDR34_PHY_BYTE_LANE_2_VDL_CLK_CONTROLr_FORCE,
   2309     DDR34_PHY_BYTE_LANE_2_VDL_CLK_CONTROLr_RESERVED1,
   2310     DDR34_PHY_BYTE_LANE_2_VDL_CLK_CONTROLr_ADJ_EN,
   2311     DDR34_PHY_BYTE_LANE_2_VDL_CLK_CONTROLr_RESERVED2,
   2312     DDR34_PHY_BYTE_LANE_2_VDL_CLK_CONTROLr_VDL_STEP,
   2313     DDR34_PHY_BYTE_LANE_2_VDL_LDE_CONTROLr_BUSY,
   2314     DDR34_PHY_BYTE_LANE_2_VDL_LDE_CONTROLr_RESERVED0,
   2315     DDR34_PHY_BYTE_LANE_2_VDL_LDE_CONTROLr_FORCE,
   2316     DDR34_PHY_BYTE_LANE_2_VDL_LDE_CONTROLr_RESERVED1,
   2317     DDR34_PHY_BYTE_LANE_2_VDL_LDE_CONTROLr_ADJ_EN,
   2318     DDR34_PHY_BYTE_LANE_2_VDL_LDE_CONTROLr_RESERVED2,
   2319     DDR34_PHY_BYTE_LANE_2_VDL_LDE_CONTROLr_VDL_STEP,
   2320     DDR34_PHY_BYTE_LANE_2_RD_EN_DLY_CYCr_BUSY,
   2321     DDR34_PHY_BYTE_LANE_2_RD_EN_DLY_CYCr_RESERVED0,
   2322     DDR34_PHY_BYTE_LANE_2_RD_EN_DLY_CYCr_FORCE,
   2323     DDR34_PHY_BYTE_LANE_2_RD_EN_DLY_CYCr_RESERVED1,
   2324     DDR34_PHY_BYTE_LANE_2_RD_EN_DLY_CYCr_CS1_CYCLES,
   2325     DDR34_PHY_BYTE_LANE_2_RD_EN_DLY_CYCr_CS0_CYCLES,
   2326     DDR34_PHY_BYTE_LANE_2_WR_CHAN_DLY_CYCr_BUSY,
   2327     DDR34_PHY_BYTE_LANE_2_WR_CHAN_DLY_CYCr_RESERVED0,
   2328     DDR34_PHY_BYTE_LANE_2_WR_CHAN_DLY_CYCr_FORCE,
   2329     DDR34_PHY_BYTE_LANE_2_WR_CHAN_DLY_CYCr_RESERVED1,
   2330     DDR34_PHY_BYTE_LANE_2_WR_CHAN_DLY_CYCr_CYCLES,
   2331     DDR34_PHY_BYTE_LANE_2_READ_CONTROLr_RESERVED0,
   2332     DDR34_PHY_BYTE_LANE_2_READ_CONTROLr_MODE,
   2333     DDR34_PHY_BYTE_LANE_2_READ_CONTROLr_RESERVED1,
   2334     DDR34_PHY_BYTE_LANE_2_READ_CONTROLr_RD_DATA_DLY,
   2335     DDR34_PHY_BYTE_LANE_2_READ_FIFO_ADDRr_RESERVED0,
   2336     DDR34_PHY_BYTE_LANE_2_READ_FIFO_ADDRr_ADDR,
   2337     DDR34_PHY_BYTE_LANE_2_READ_FIFO_DATAr_DATA,
   2338     DDR34_PHY_BYTE_LANE_2_READ_FIFO_DM_DBIr_RESERVED0,
   2339     DDR34_PHY_BYTE_LANE_2_READ_FIFO_DM_DBIr_DM_DBI,
   2340     DDR34_PHY_BYTE_LANE_2_READ_FIFO_STATUSr_RESERVED0,
   2341     DDR34_PHY_BYTE_LANE_2_READ_FIFO_STATUSr_OVERFLOW,
   2342     DDR34_PHY_BYTE_LANE_2_READ_FIFO_STATUSr_UNDERFLOW,
   2343     DDR34_PHY_BYTE_LANE_2_READ_FIFO_CLEARr_RESERVED0,
   2344     DDR34_PHY_BYTE_LANE_2_READ_FIFO_CLEARr_CLEAR,
   2345     DDR34_PHY_BYTE_LANE_2_IDLE_PAD_CONTROLr_IDLE,
   2346     DDR34_PHY_BYTE_LANE_2_IDLE_PAD_CONTROLr_RESERVED0,
   2347     DDR34_PHY_BYTE_LANE_2_IDLE_PAD_CONTROLr_AUTO_DQ_RXENB_MODE,
   2348     DDR34_PHY_BYTE_LANE_2_IDLE_PAD_CONTROLr_AUTO_DQ_IDDQ_MODE,
   2349     DDR34_PHY_BYTE_LANE_2_IDLE_PAD_CONTROLr_RESERVED_for_padding1,
   2350     DDR34_PHY_BYTE_LANE_2_IDLE_PAD_CONTROLr_IO_IDLE_ENABLE,
   2351     DDR34_PHY_BYTE_LANE_2_IDLE_PAD_CONTROLr_RXENB,
   2352     DDR34_PHY_BYTE_LANE_2_IDLE_PAD_CONTROLr_IDDQ,
   2353     DDR34_PHY_BYTE_LANE_2_IDLE_PAD_CONTROLr_DOUT_N,
   2354     DDR34_PHY_BYTE_LANE_2_IDLE_PAD_CONTROLr_DOUT_P,
   2355     DDR34_PHY_BYTE_LANE_2_DRIVE_PAD_CTLr_RESERVED0,
   2356     DDR34_PHY_BYTE_LANE_2_DRIVE_PAD_CTLr_BL_PD_IDLE_STRENGTH,
   2357     DDR34_PHY_BYTE_LANE_2_DRIVE_PAD_CTLr_BL_ND_IDLE_STRENGTH,
   2358     DDR34_PHY_BYTE_LANE_2_DRIVE_PAD_CTLr_BL_PD_TERM_STRENGTH,
   2359     DDR34_PHY_BYTE_LANE_2_DRIVE_PAD_CTLr_BL_ND_TERM_STRENGTH,
   2360     DDR34_PHY_BYTE_LANE_2_DRIVE_PAD_CTLr_BL_PD_STRENGTH,
   2361     DDR34_PHY_BYTE_LANE_2_DRIVE_PAD_CTLr_BL_ND_STRENGTH,
   2362     DDR34_PHY_BYTE_LANE_2_RD_EN_DRIVE_PAD_CTLr_RESERVED0,
   2363     DDR34_PHY_BYTE_LANE_2_RD_EN_DRIVE_PAD_CTLr_EDC_RD_EN_PD_STRENGTH,
   2364     DDR34_PHY_BYTE_LANE_2_RD_EN_DRIVE_PAD_CTLr_EDC_RD_EN_ND_STRENGTH,
   2365     DDR34_PHY_BYTE_LANE_2_RD_EN_DRIVE_PAD_CTLr_BL_RD_EN_PD_STRENGTH,
   2366     DDR34_PHY_BYTE_LANE_2_RD_EN_DRIVE_PAD_CTLr_BL_RD_EN_ND_STRENGTH,
   2367     DDR34_PHY_BYTE_LANE_2_STATIC_PAD_CTLr_RESERVED0,
   2368     DDR34_PHY_BYTE_LANE_2_STATIC_PAD_CTLr_DQS_MODE,
   2369     DDR34_PHY_BYTE_LANE_2_STATIC_PAD_CTLr_RESERVED1,
   2370     DDR34_PHY_BYTE_LANE_2_STATIC_PAD_CTLr_EDC_MODE,
   2371     DDR34_PHY_BYTE_LANE_2_STATIC_PAD_CTLr_RESERVED2,
   2372     DDR34_PHY_BYTE_LANE_2_STATIC_PAD_CTLr_WDBI_ENABLE,
   2373     DDR34_PHY_BYTE_LANE_2_STATIC_PAD_CTLr_RDBI_ENABLE,
   2374     DDR34_PHY_BYTE_LANE_2_STATIC_PAD_CTLr_DM_MODE,
   2375     DDR34_PHY_BYTE_LANE_2_STATIC_PAD_CTLr_RESERVED3,
   2376     DDR34_PHY_BYTE_LANE_2_STATIC_PAD_CTLr_DQS_TX_DIS,
   2377     DDR34_PHY_BYTE_LANE_2_STATIC_PAD_CTLr_RESERVED4,
   2378     DDR34_PHY_BYTE_LANE_2_STATIC_PAD_CTLr_RX_MODE,
   2379     DDR34_PHY_BYTE_LANE_2_WR_PREAMBLE_MODEr_RESERVED0,
   2380     DDR34_PHY_BYTE_LANE_2_WR_PREAMBLE_MODEr_DQ_POSTAM_BITS,
   2381     DDR34_PHY_BYTE_LANE_2_WR_PREAMBLE_MODEr_DQ_PREAM_BITS,
   2382     DDR34_PHY_BYTE_LANE_2_WR_PREAMBLE_MODEr_DQS,
   2383     DDR34_PHY_BYTE_LANE_2_WR_PREAMBLE_MODEr_RESERVED1,
   2384     DDR34_PHY_BYTE_LANE_2_WR_PREAMBLE_MODEr_DQS_POSTAM_BITS,
   2385     DDR34_PHY_BYTE_LANE_2_WR_PREAMBLE_MODEr_DQS_PREAM_BITS,
   2386     DDR34_PHY_BYTE_LANE_2_ODT_CONTROLr_RESERVED_for_padding0,
   2387     DDR34_PHY_BYTE_LANE_2_ODT_CONTROLr_RESERVED1,
   2388     DDR34_PHY_BYTE_LANE_2_ODT_CONTROLr_ODT_ENABLE,
   2389     DDR34_PHY_BYTE_LANE_2_ODT_CONTROLr_ODT_DELAY,
   2390     DDR34_PHY_BYTE_LANE_2_ODT_CONTROLr_ODT_POST_LENGTH,
   2391     DDR34_PHY_BYTE_LANE_2_ODT_CONTROLr_ODT_PRE_LENGTH,
   2392     DDR34_PHY_BYTE_LANE_2_EDC_DPD_CONTROLr_RESERVED0,
   2393     DDR34_PHY_BYTE_LANE_2_EDC_DPD_CONTROLr_DQS_PHASE_OVERRIDE_VALUE,
   2394     DDR34_PHY_BYTE_LANE_2_EDC_DPD_CONTROLr_DQS_PHASE_OVERRIDE_ENABLE,
   2395     DDR34_PHY_BYTE_LANE_2_EDC_DPD_CONTROLr_SET_ADJ_EN,
   2396     DDR34_PHY_BYTE_LANE_2_EDC_DPD_CONTROLr_UPDATE,
   2397     DDR34_PHY_BYTE_LANE_2_EDC_DPD_CONTROLr_MONITOR,
   2398     DDR34_PHY_BYTE_LANE_2_EDC_DPD_CONTROLr_INIT,
   2399     DDR34_PHY_BYTE_LANE_2_EDC_DPD_STATUSr_RESERVED0,
   2400     DDR34_PHY_BYTE_LANE_2_EDC_DPD_STATUSr_CURRENT_DQS_PHASE,
   2401     DDR34_PHY_BYTE_LANE_2_EDC_DPD_STATUSr_CURRENT_VDL_SETTING,
   2402     DDR34_PHY_BYTE_LANE_2_EDC_DPD_STATUSr_RESERVED1,
   2403     DDR34_PHY_BYTE_LANE_2_EDC_DPD_STATUSr_INIT_DQS_PHASE,
   2404     DDR34_PHY_BYTE_LANE_2_EDC_DPD_STATUSr_INIT_VDL_SETTING,
   2405     DDR34_PHY_BYTE_LANE_2_EDC_DPD_STATUSr_EDGE_ERROR,
   2406     DDR34_PHY_BYTE_LANE_2_EDC_DPD_STATUSr_MONITOR_BUSY,
   2407     DDR34_PHY_BYTE_LANE_2_EDC_DPD_STATUSr_INIT_BUSY,
   2408     DDR34_PHY_BYTE_LANE_2_EDC_DPD_STATUSr_INIT_DONE,
   2409     DDR34_PHY_BYTE_LANE_2_EDC_DPD_OUT_CONTROLr_RESERVED0,
   2410     DDR34_PHY_BYTE_LANE_2_EDC_DPD_OUT_CONTROLr_LOWER_LIMIT,
   2411     DDR34_PHY_BYTE_LANE_2_EDC_DPD_OUT_CONTROLr_UPPER_LIMIT,
   2412     DDR34_PHY_BYTE_LANE_2_EDC_DPD_OUT_CONTROLr_RESERVED1,
   2413     DDR34_PHY_BYTE_LANE_2_EDC_DPD_OUT_CONTROLr_ENABLE,
   2414     DDR34_PHY_BYTE_LANE_2_EDC_DPD_OUT_STATUSr_RESERVED0,
   2415     DDR34_PHY_BYTE_LANE_2_EDC_DPD_OUT_STATUSr_VDL_SETTING,
   2416     DDR34_PHY_BYTE_LANE_2_EDC_DPD_OUT_STATUSr_RESERVED1,
   2417     DDR34_PHY_BYTE_LANE_2_EDC_DPD_OUT_STATUSr_VALID,
   2418     DDR34_PHY_BYTE_LANE_2_EDC_DPD_OUT_STATUSr_CLEAR_RESERVED0,
   2419     DDR34_PHY_BYTE_LANE_2_EDC_DPD_OUT_STATUSr_CLEAR_CLEAR,
   2420     DDR34_PHY_BYTE_LANE_2_EDC_DPD_OUT_STATUS_CLEARr_RESERVED0,
   2421     DDR34_PHY_BYTE_LANE_2_EDC_DPD_OUT_STATUS_CLEARr_CLEAR,
   2422     DDR34_PHY_BYTE_LANE_2_EDC_CRC_CONTROLr_BUSY,
   2423     DDR34_PHY_BYTE_LANE_2_EDC_CRC_CONTROLr_RESERVED0,
   2424     DDR34_PHY_BYTE_LANE_2_EDC_CRC_CONTROLr_FORCE,
   2425     DDR34_PHY_BYTE_LANE_2_EDC_CRC_CONTROLr_RESERVED1,
   2426     DDR34_PHY_BYTE_LANE_2_EDC_CRC_CONTROLr_CRCWL,
   2427     DDR34_PHY_BYTE_LANE_2_EDC_CRC_CONTROLr_RESERVED2,
   2428     DDR34_PHY_BYTE_LANE_2_EDC_CRC_CONTROLr_CRCRL,
   2429     DDR34_PHY_BYTE_LANE_2_EDC_CRC_CONTROLr_RESERVED3,
   2430     DDR34_PHY_BYTE_LANE_2_EDC_CRC_CONTROLr_COUNT_MODE,
   2431     DDR34_PHY_BYTE_LANE_2_EDC_CRC_CONTROLr_ENABLE_WR,
   2432     DDR34_PHY_BYTE_LANE_2_EDC_CRC_CONTROLr_ENABLE_RD,
   2433     DDR34_PHY_BYTE_LANE_2_EDC_CRC_STATUSr_RESERVED0,
   2434     DDR34_PHY_BYTE_LANE_2_EDC_CRC_STATUSr_WR_FAIL,
   2435     DDR34_PHY_BYTE_LANE_2_EDC_CRC_STATUSr_WR_PASS,
   2436     DDR34_PHY_BYTE_LANE_2_EDC_CRC_STATUSr_RD_FAIL,
   2437     DDR34_PHY_BYTE_LANE_2_EDC_CRC_STATUSr_RD_PASS,
   2438     DDR34_PHY_BYTE_LANE_2_EDC_CRC_STATUSr_CLEAR_RESERVED0,
   2439     DDR34_PHY_BYTE_LANE_2_EDC_CRC_STATUSr_CLEAR_CLEAR,
   2440     DDR34_PHY_BYTE_LANE_2_EDC_CRC_COUNTr_RESERVED0,
   2441     DDR34_PHY_BYTE_LANE_2_EDC_CRC_COUNTr_WR_COUNT,
   2442     DDR34_PHY_BYTE_LANE_2_EDC_CRC_COUNTr_RESERVED1,
   2443     DDR34_PHY_BYTE_LANE_2_EDC_CRC_COUNTr_RD_COUNT,
   2444     DDR34_PHY_BYTE_LANE_2_EDC_CRC_STATUS_CLEARr_RESERVED0,
   2445     DDR34_PHY_BYTE_LANE_2_EDC_CRC_STATUS_CLEARr_CLEAR,
   2446     DDR34_PHY_BYTE_LANE_2_BL_SPARE_REGr_RESERVED_for_eco0,
   2447     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_Pr_BUSY,
   2448     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_Pr_RESERVED0,
   2449     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_Pr_FORCE,
   2450     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_Pr_RESERVED1,
   2451     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_Pr_ADJ_EN,
   2452     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_Pr_RESERVED2,
   2453     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_Pr_VDL_STEP,
   2454     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_Nr_BUSY,
   2455     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_Nr_RESERVED0,
   2456     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_Nr_FORCE,
   2457     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_Nr_RESERVED1,
   2458     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_Nr_ADJ_EN,
   2459     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_Nr_RESERVED2,
   2460     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_Nr_VDL_STEP,
   2461     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ0r_BUSY,
   2462     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ0r_RESERVED0,
   2463     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ0r_FORCE,
   2464     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ0r_RESERVED1,
   2465     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ0r_ADJ_EN,
   2466     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ0r_RESERVED2,
   2467     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ0r_VDL_STEP,
   2468     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ1r_BUSY,
   2469     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ1r_RESERVED0,
   2470     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ1r_FORCE,
   2471     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ1r_RESERVED1,
   2472     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ1r_ADJ_EN,
   2473     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ1r_RESERVED2,
   2474     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ1r_VDL_STEP,
   2475     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ2r_BUSY,
   2476     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ2r_RESERVED0,
   2477     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ2r_FORCE,
   2478     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ2r_RESERVED1,
   2479     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ2r_ADJ_EN,
   2480     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ2r_RESERVED2,
   2481     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ2r_VDL_STEP,
   2482     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ3r_BUSY,
   2483     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ3r_RESERVED0,
   2484     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ3r_FORCE,
   2485     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ3r_RESERVED1,
   2486     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ3r_ADJ_EN,
   2487     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ3r_RESERVED2,
   2488     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ3r_VDL_STEP,
   2489     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ4r_BUSY,
   2490     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ4r_RESERVED0,
   2491     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ4r_FORCE,
   2492     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ4r_RESERVED1,
   2493     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ4r_ADJ_EN,
   2494     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ4r_RESERVED2,
   2495     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ4r_VDL_STEP,
   2496     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ5r_BUSY,
   2497     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ5r_RESERVED0,
   2498     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ5r_FORCE,
   2499     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ5r_RESERVED1,
   2500     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ5r_ADJ_EN,
   2501     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ5r_RESERVED2,
   2502     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ5r_VDL_STEP,
   2503     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ6r_BUSY,
   2504     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ6r_RESERVED0,
   2505     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ6r_FORCE,
   2506     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ6r_RESERVED1,
   2507     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ6r_ADJ_EN,
   2508     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ6r_RESERVED2,
   2509     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ6r_VDL_STEP,
   2510     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ7r_BUSY,
   2511     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ7r_RESERVED0,
   2512     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ7r_FORCE,
   2513     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ7r_RESERVED1,
   2514     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ7r_ADJ_EN,
   2515     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ7r_RESERVED2,
   2516     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ7r_VDL_STEP,
   2517     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DMr_BUSY,
   2518     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DMr_RESERVED0,
   2519     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DMr_FORCE,
   2520     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DMr_RESERVED1,
   2521     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DMr_ADJ_EN,
   2522     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DMr_RESERVED2,
   2523     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DMr_VDL_STEP,
   2524     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_EDCr_BUSY,
   2525     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_EDCr_RESERVED0,
   2526     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_EDCr_FORCE,
   2527     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_EDCr_RESERVED1,
   2528     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_EDCr_ADJ_EN,
   2529     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_EDCr_RESERVED2,
   2530     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_EDCr_VDL_STEP,
   2531     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSPr_BUSY,
   2532     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSPr_RESERVED0,
   2533     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSPr_FORCE,
   2534     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSPr_RESERVED1,
   2535     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSPr_ADJ_EN,
   2536     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSPr_RESERVED2,
   2537     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSPr_VDL_STEP,
   2538     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSNr_BUSY,
   2539     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSNr_RESERVED0,
   2540     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSNr_FORCE,
   2541     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSNr_RESERVED1,
   2542     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSNr_ADJ_EN,
   2543     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSNr_RESERVED2,
   2544     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSNr_VDL_STEP,
   2545     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0Pr_BUSY,
   2546     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0Pr_RESERVED0,
   2547     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0Pr_FORCE,
   2548     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0Pr_RESERVED1,
   2549     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0Pr_ADJ_EN,
   2550     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0Pr_RESERVED2,
   2551     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0Pr_VDL_STEP,
   2552     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0Nr_BUSY,
   2553     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0Nr_RESERVED0,
   2554     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0Nr_FORCE,
   2555     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0Nr_RESERVED1,
   2556     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0Nr_ADJ_EN,
   2557     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0Nr_RESERVED2,
   2558     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0Nr_VDL_STEP,
   2559     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1Pr_BUSY,
   2560     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1Pr_RESERVED0,
   2561     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1Pr_FORCE,
   2562     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1Pr_RESERVED1,
   2563     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1Pr_ADJ_EN,
   2564     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1Pr_RESERVED2,
   2565     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1Pr_VDL_STEP,
   2566     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1Nr_BUSY,
   2567     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1Nr_RESERVED0,
   2568     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1Nr_FORCE,
   2569     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1Nr_RESERVED1,
   2570     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1Nr_ADJ_EN,
   2571     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1Nr_RESERVED2,
   2572     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1Nr_VDL_STEP,
   2573     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2Pr_BUSY,
   2574     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2Pr_RESERVED0,
   2575     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2Pr_FORCE,
   2576     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2Pr_RESERVED1,
   2577     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2Pr_ADJ_EN,
   2578     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2Pr_RESERVED2,
   2579     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2Pr_VDL_STEP,
   2580     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2Nr_BUSY,
   2581     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2Nr_RESERVED0,
   2582     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2Nr_FORCE,
   2583     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2Nr_RESERVED1,
   2584     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2Nr_ADJ_EN,
   2585     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2Nr_RESERVED2,
   2586     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2Nr_VDL_STEP,
   2587     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3Pr_BUSY,
   2588     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3Pr_RESERVED0,
   2589     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3Pr_FORCE,
   2590     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3Pr_RESERVED1,
   2591     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3Pr_ADJ_EN,
   2592     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3Pr_RESERVED2,
   2593     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3Pr_VDL_STEP,
   2594     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3Nr_BUSY,
   2595     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3Nr_RESERVED0,
   2596     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3Nr_FORCE,
   2597     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3Nr_RESERVED1,
   2598     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3Nr_ADJ_EN,
   2599     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3Nr_RESERVED2,
   2600     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3Nr_VDL_STEP,
   2601     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4Pr_BUSY,
   2602     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4Pr_RESERVED0,
   2603     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4Pr_FORCE,
   2604     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4Pr_RESERVED1,
   2605     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4Pr_ADJ_EN,
   2606     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4Pr_RESERVED2,
   2607     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4Pr_VDL_STEP,
   2608     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4Nr_BUSY,
   2609     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4Nr_RESERVED0,
   2610     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4Nr_FORCE,
   2611     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4Nr_RESERVED1,
   2612     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4Nr_ADJ_EN,
   2613     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4Nr_RESERVED2,
   2614     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4Nr_VDL_STEP,
   2615     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5Pr_BUSY,
   2616     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5Pr_RESERVED0,
   2617     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5Pr_FORCE,
   2618     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5Pr_RESERVED1,
   2619     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5Pr_ADJ_EN,
   2620     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5Pr_RESERVED2,
   2621     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5Pr_VDL_STEP,
   2622     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5Nr_BUSY,
   2623     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5Nr_RESERVED0,
   2624     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5Nr_FORCE,
   2625     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5Nr_RESERVED1,
   2626     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5Nr_ADJ_EN,
   2627     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5Nr_RESERVED2,
   2628     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5Nr_VDL_STEP,
   2629     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6Pr_BUSY,
   2630     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6Pr_RESERVED0,
   2631     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6Pr_FORCE,
   2632     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6Pr_RESERVED1,
   2633     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6Pr_ADJ_EN,
   2634     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6Pr_RESERVED2,
   2635     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6Pr_VDL_STEP,
   2636     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6Nr_BUSY,
   2637     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6Nr_RESERVED0,
   2638     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6Nr_FORCE,
   2639     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6Nr_RESERVED1,
   2640     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6Nr_ADJ_EN,
   2641     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6Nr_RESERVED2,
   2642     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6Nr_VDL_STEP,
   2643     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7Pr_BUSY,
   2644     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7Pr_RESERVED0,
   2645     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7Pr_FORCE,
   2646     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7Pr_RESERVED1,
   2647     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7Pr_ADJ_EN,
   2648     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7Pr_RESERVED2,
   2649     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7Pr_VDL_STEP,
   2650     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7Nr_BUSY,
   2651     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7Nr_RESERVED0,
   2652     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7Nr_FORCE,
   2653     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7Nr_RESERVED1,
   2654     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7Nr_ADJ_EN,
   2655     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7Nr_RESERVED2,
   2656     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7Nr_VDL_STEP,
   2657     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMPr_BUSY,
   2658     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMPr_RESERVED0,
   2659     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMPr_FORCE,
   2660     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMPr_RESERVED1,
   2661     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMPr_ADJ_EN,
   2662     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMPr_RESERVED2,
   2663     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMPr_VDL_STEP,
   2664     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMNr_BUSY,
   2665     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMNr_RESERVED0,
   2666     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMNr_FORCE,
   2667     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMNr_RESERVED1,
   2668     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMNr_ADJ_EN,
   2669     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMNr_RESERVED2,
   2670     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMNr_VDL_STEP,
   2671     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EDCPr_BUSY,
   2672     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EDCPr_RESERVED0,
   2673     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EDCPr_FORCE,
   2674     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EDCPr_RESERVED1,
   2675     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EDCPr_ADJ_EN,
   2676     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EDCPr_RESERVED2,
   2677     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EDCPr_VDL_STEP,
   2678     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EDCNr_BUSY,
   2679     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EDCNr_RESERVED0,
   2680     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EDCNr_FORCE,
   2681     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EDCNr_RESERVED1,
   2682     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EDCNr_ADJ_EN,
   2683     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EDCNr_RESERVED2,
   2684     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EDCNr_VDL_STEP,
   2685     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS0r_BUSY,
   2686     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS0r_RESERVED0,
   2687     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS0r_FORCE,
   2688     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS0r_RESERVED1,
   2689     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS0r_ADJ_EN,
   2690     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS0r_RESERVED2,
   2691     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS0r_VDL_STEP,
   2692     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS1r_BUSY,
   2693     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS1r_RESERVED0,
   2694     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS1r_FORCE,
   2695     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS1r_RESERVED1,
   2696     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS1r_ADJ_EN,
   2697     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS1r_RESERVED2,
   2698     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS1r_VDL_STEP,
   2699     DDR34_PHY_BYTE_LANE_3_VDL_CLK_CONTROLr_BUSY,
   2700     DDR34_PHY_BYTE_LANE_3_VDL_CLK_CONTROLr_RESERVED0,
   2701     DDR34_PHY_BYTE_LANE_3_VDL_CLK_CONTROLr_FORCE,
   2702     DDR34_PHY_BYTE_LANE_3_VDL_CLK_CONTROLr_RESERVED1,
   2703     DDR34_PHY_BYTE_LANE_3_VDL_CLK_CONTROLr_ADJ_EN,
   2704     DDR34_PHY_BYTE_LANE_3_VDL_CLK_CONTROLr_RESERVED2,
   2705     DDR34_PHY_BYTE_LANE_3_VDL_CLK_CONTROLr_VDL_STEP,
   2706     DDR34_PHY_BYTE_LANE_3_VDL_LDE_CONTROLr_BUSY,
   2707     DDR34_PHY_BYTE_LANE_3_VDL_LDE_CONTROLr_RESERVED0,
   2708     DDR34_PHY_BYTE_LANE_3_VDL_LDE_CONTROLr_FORCE,
   2709     DDR34_PHY_BYTE_LANE_3_VDL_LDE_CONTROLr_RESERVED1,
   2710     DDR34_PHY_BYTE_LANE_3_VDL_LDE_CONTROLr_ADJ_EN,
   2711     DDR34_PHY_BYTE_LANE_3_VDL_LDE_CONTROLr_RESERVED2,
   2712     DDR34_PHY_BYTE_LANE_3_VDL_LDE_CONTROLr_VDL_STEP,
   2713     DDR34_PHY_BYTE_LANE_3_RD_EN_DLY_CYCr_BUSY,
   2714     DDR34_PHY_BYTE_LANE_3_RD_EN_DLY_CYCr_RESERVED0,
   2715     DDR34_PHY_BYTE_LANE_3_RD_EN_DLY_CYCr_FORCE,
   2716     DDR34_PHY_BYTE_LANE_3_RD_EN_DLY_CYCr_RESERVED1,
   2717     DDR34_PHY_BYTE_LANE_3_RD_EN_DLY_CYCr_CS1_CYCLES,
   2718     DDR34_PHY_BYTE_LANE_3_RD_EN_DLY_CYCr_CS0_CYCLES,
   2719     DDR34_PHY_BYTE_LANE_3_WR_CHAN_DLY_CYCr_BUSY,
   2720     DDR34_PHY_BYTE_LANE_3_WR_CHAN_DLY_CYCr_RESERVED0,
   2721     DDR34_PHY_BYTE_LANE_3_WR_CHAN_DLY_CYCr_FORCE,
   2722     DDR34_PHY_BYTE_LANE_3_WR_CHAN_DLY_CYCr_RESERVED1,
   2723     DDR34_PHY_BYTE_LANE_3_WR_CHAN_DLY_CYCr_CYCLES,
   2724     DDR34_PHY_BYTE_LANE_3_READ_CONTROLr_RESERVED0,
   2725     DDR34_PHY_BYTE_LANE_3_READ_CONTROLr_MODE,
   2726     DDR34_PHY_BYTE_LANE_3_READ_CONTROLr_RESERVED1,
   2727     DDR34_PHY_BYTE_LANE_3_READ_CONTROLr_RD_DATA_DLY,
   2728     DDR34_PHY_BYTE_LANE_3_READ_FIFO_ADDRr_RESERVED0,
   2729     DDR34_PHY_BYTE_LANE_3_READ_FIFO_ADDRr_ADDR,
   2730     DDR34_PHY_BYTE_LANE_3_READ_FIFO_DATAr_DATA,
   2731     DDR34_PHY_BYTE_LANE_3_READ_FIFO_DM_DBIr_RESERVED0,
   2732     DDR34_PHY_BYTE_LANE_3_READ_FIFO_DM_DBIr_DM_DBI,
   2733     DDR34_PHY_BYTE_LANE_3_READ_FIFO_STATUSr_RESERVED0,
   2734     DDR34_PHY_BYTE_LANE_3_READ_FIFO_STATUSr_OVERFLOW,
   2735     DDR34_PHY_BYTE_LANE_3_READ_FIFO_STATUSr_UNDERFLOW,
   2736     DDR34_PHY_BYTE_LANE_3_READ_FIFO_CLEARr_RESERVED0,
   2737     DDR34_PHY_BYTE_LANE_3_READ_FIFO_CLEARr_CLEAR,
   2738     DDR34_PHY_BYTE_LANE_3_IDLE_PAD_CONTROLr_IDLE,
   2739     DDR34_PHY_BYTE_LANE_3_IDLE_PAD_CONTROLr_RESERVED0,
   2740     DDR34_PHY_BYTE_LANE_3_IDLE_PAD_CONTROLr_AUTO_DQ_RXENB_MODE,
   2741     DDR34_PHY_BYTE_LANE_3_IDLE_PAD_CONTROLr_AUTO_DQ_IDDQ_MODE,
   2742     DDR34_PHY_BYTE_LANE_3_IDLE_PAD_CONTROLr_RESERVED_for_padding1,
   2743     DDR34_PHY_BYTE_LANE_3_IDLE_PAD_CONTROLr_IO_IDLE_ENABLE,
   2744     DDR34_PHY_BYTE_LANE_3_IDLE_PAD_CONTROLr_RXENB,
   2745     DDR34_PHY_BYTE_LANE_3_IDLE_PAD_CONTROLr_IDDQ,
   2746     DDR34_PHY_BYTE_LANE_3_IDLE_PAD_CONTROLr_DOUT_N,
   2747     DDR34_PHY_BYTE_LANE_3_IDLE_PAD_CONTROLr_DOUT_P,
   2748     DDR34_PHY_BYTE_LANE_3_DRIVE_PAD_CTLr_RESERVED0,
   2749     DDR34_PHY_BYTE_LANE_3_DRIVE_PAD_CTLr_BL_PD_IDLE_STRENGTH,
   2750     DDR34_PHY_BYTE_LANE_3_DRIVE_PAD_CTLr_BL_ND_IDLE_STRENGTH,
   2751     DDR34_PHY_BYTE_LANE_3_DRIVE_PAD_CTLr_BL_PD_TERM_STRENGTH,
   2752     DDR34_PHY_BYTE_LANE_3_DRIVE_PAD_CTLr_BL_ND_TERM_STRENGTH,
   2753     DDR34_PHY_BYTE_LANE_3_DRIVE_PAD_CTLr_BL_PD_STRENGTH,
   2754     DDR34_PHY_BYTE_LANE_3_DRIVE_PAD_CTLr_BL_ND_STRENGTH,
   2755     DDR34_PHY_BYTE_LANE_3_RD_EN_DRIVE_PAD_CTLr_RESERVED0,
   2756     DDR34_PHY_BYTE_LANE_3_RD_EN_DRIVE_PAD_CTLr_EDC_RD_EN_PD_STRENGTH,
   2757     DDR34_PHY_BYTE_LANE_3_RD_EN_DRIVE_PAD_CTLr_EDC_RD_EN_ND_STRENGTH,
   2758     DDR34_PHY_BYTE_LANE_3_RD_EN_DRIVE_PAD_CTLr_BL_RD_EN_PD_STRENGTH,
   2759     DDR34_PHY_BYTE_LANE_3_RD_EN_DRIVE_PAD_CTLr_BL_RD_EN_ND_STRENGTH,
   2760     DDR34_PHY_BYTE_LANE_3_STATIC_PAD_CTLr_RESERVED0,
   2761     DDR34_PHY_BYTE_LANE_3_STATIC_PAD_CTLr_DQS_MODE,
   2762     DDR34_PHY_BYTE_LANE_3_STATIC_PAD_CTLr_RESERVED1,
   2763     DDR34_PHY_BYTE_LANE_3_STATIC_PAD_CTLr_EDC_MODE,
   2764     DDR34_PHY_BYTE_LANE_3_STATIC_PAD_CTLr_RESERVED2,
   2765     DDR34_PHY_BYTE_LANE_3_STATIC_PAD_CTLr_WDBI_ENABLE,
   2766     DDR34_PHY_BYTE_LANE_3_STATIC_PAD_CTLr_RDBI_ENABLE,
   2767     DDR34_PHY_BYTE_LANE_3_STATIC_PAD_CTLr_DM_MODE,
   2768     DDR34_PHY_BYTE_LANE_3_STATIC_PAD_CTLr_RESERVED3,
   2769     DDR34_PHY_BYTE_LANE_3_STATIC_PAD_CTLr_DQS_TX_DIS,
   2770     DDR34_PHY_BYTE_LANE_3_STATIC_PAD_CTLr_RESERVED4,
   2771     DDR34_PHY_BYTE_LANE_3_STATIC_PAD_CTLr_RX_MODE,
   2772     DDR34_PHY_BYTE_LANE_3_WR_PREAMBLE_MODEr_RESERVED0,
   2773     DDR34_PHY_BYTE_LANE_3_WR_PREAMBLE_MODEr_DQ_POSTAM_BITS,
   2774     DDR34_PHY_BYTE_LANE_3_WR_PREAMBLE_MODEr_DQ_PREAM_BITS,
   2775     DDR34_PHY_BYTE_LANE_3_WR_PREAMBLE_MODEr_DQS,
   2776     DDR34_PHY_BYTE_LANE_3_WR_PREAMBLE_MODEr_RESERVED1,
   2777     DDR34_PHY_BYTE_LANE_3_WR_PREAMBLE_MODEr_DQS_POSTAM_BITS,
   2778     DDR34_PHY_BYTE_LANE_3_WR_PREAMBLE_MODEr_DQS_PREAM_BITS,
   2779     DDR34_PHY_BYTE_LANE_3_ODT_CONTROLr_RESERVED_for_padding0,
   2780     DDR34_PHY_BYTE_LANE_3_ODT_CONTROLr_RESERVED1,
   2781     DDR34_PHY_BYTE_LANE_3_ODT_CONTROLr_ODT_ENABLE,
   2782     DDR34_PHY_BYTE_LANE_3_ODT_CONTROLr_ODT_DELAY,
   2783     DDR34_PHY_BYTE_LANE_3_ODT_CONTROLr_ODT_POST_LENGTH,
   2784     DDR34_PHY_BYTE_LANE_3_ODT_CONTROLr_ODT_PRE_LENGTH,
   2785     DDR34_PHY_BYTE_LANE_3_EDC_DPD_CONTROLr_RESERVED0,
   2786     DDR34_PHY_BYTE_LANE_3_EDC_DPD_CONTROLr_DQS_PHASE_OVERRIDE_VALUE,
   2787     DDR34_PHY_BYTE_LANE_3_EDC_DPD_CONTROLr_DQS_PHASE_OVERRIDE_ENABLE,
   2788     DDR34_PHY_BYTE_LANE_3_EDC_DPD_CONTROLr_SET_ADJ_EN,
   2789     DDR34_PHY_BYTE_LANE_3_EDC_DPD_CONTROLr_UPDATE,
   2790     DDR34_PHY_BYTE_LANE_3_EDC_DPD_CONTROLr_MONITOR,
   2791     DDR34_PHY_BYTE_LANE_3_EDC_DPD_CONTROLr_INIT,
   2792     DDR34_PHY_BYTE_LANE_3_EDC_DPD_STATUSr_RESERVED0,
   2793     DDR34_PHY_BYTE_LANE_3_EDC_DPD_STATUSr_CURRENT_DQS_PHASE,
   2794     DDR34_PHY_BYTE_LANE_3_EDC_DPD_STATUSr_CURRENT_VDL_SETTING,
   2795     DDR34_PHY_BYTE_LANE_3_EDC_DPD_STATUSr_RESERVED1,
   2796     DDR34_PHY_BYTE_LANE_3_EDC_DPD_STATUSr_INIT_DQS_PHASE,
   2797     DDR34_PHY_BYTE_LANE_3_EDC_DPD_STATUSr_INIT_VDL_SETTING,
   2798     DDR34_PHY_BYTE_LANE_3_EDC_DPD_STATUSr_EDGE_ERROR,
   2799     DDR34_PHY_BYTE_LANE_3_EDC_DPD_STATUSr_MONITOR_BUSY,
   2800     DDR34_PHY_BYTE_LANE_3_EDC_DPD_STATUSr_INIT_BUSY,
   2801     DDR34_PHY_BYTE_LANE_3_EDC_DPD_STATUSr_INIT_DONE,
   2802     DDR34_PHY_BYTE_LANE_3_EDC_DPD_OUT_CONTROLr_RESERVED0,
   2803     DDR34_PHY_BYTE_LANE_3_EDC_DPD_OUT_CONTROLr_LOWER_LIMIT,
   2804     DDR34_PHY_BYTE_LANE_3_EDC_DPD_OUT_CONTROLr_UPPER_LIMIT,
   2805     DDR34_PHY_BYTE_LANE_3_EDC_DPD_OUT_CONTROLr_RESERVED1,
   2806     DDR34_PHY_BYTE_LANE_3_EDC_DPD_OUT_CONTROLr_ENABLE,
   2807     DDR34_PHY_BYTE_LANE_3_EDC_DPD_OUT_STATUSr_RESERVED0,
   2808     DDR34_PHY_BYTE_LANE_3_EDC_DPD_OUT_STATUSr_VDL_SETTING,
   2809     DDR34_PHY_BYTE_LANE_3_EDC_DPD_OUT_STATUSr_RESERVED1,
   2810     DDR34_PHY_BYTE_LANE_3_EDC_DPD_OUT_STATUSr_VALID,
   2811     DDR34_PHY_BYTE_LANE_3_EDC_DPD_OUT_STATUSr_CLEAR_RESERVED0,
   2812     DDR34_PHY_BYTE_LANE_3_EDC_DPD_OUT_STATUSr_CLEAR_CLEAR,
   2813     DDR34_PHY_BYTE_LANE_3_EDC_DPD_OUT_STATUS_CLEARr_RESERVED0,
   2814     DDR34_PHY_BYTE_LANE_3_EDC_DPD_OUT_STATUS_CLEARr_CLEAR,
   2815     DDR34_PHY_BYTE_LANE_3_EDC_CRC_CONTROLr_BUSY,
   2816     DDR34_PHY_BYTE_LANE_3_EDC_CRC_CONTROLr_RESERVED0,
   2817     DDR34_PHY_BYTE_LANE_3_EDC_CRC_CONTROLr_FORCE,
   2818     DDR34_PHY_BYTE_LANE_3_EDC_CRC_CONTROLr_RESERVED1,
   2819     DDR34_PHY_BYTE_LANE_3_EDC_CRC_CONTROLr_CRCWL,
   2820     DDR34_PHY_BYTE_LANE_3_EDC_CRC_CONTROLr_RESERVED2,
   2821     DDR34_PHY_BYTE_LANE_3_EDC_CRC_CONTROLr_CRCRL,
   2822     DDR34_PHY_BYTE_LANE_3_EDC_CRC_CONTROLr_RESERVED3,
   2823     DDR34_PHY_BYTE_LANE_3_EDC_CRC_CONTROLr_COUNT_MODE,
   2824     DDR34_PHY_BYTE_LANE_3_EDC_CRC_CONTROLr_ENABLE_WR,
   2825     DDR34_PHY_BYTE_LANE_3_EDC_CRC_CONTROLr_ENABLE_RD,
   2826     DDR34_PHY_BYTE_LANE_3_EDC_CRC_STATUSr_RESERVED0,
   2827     DDR34_PHY_BYTE_LANE_3_EDC_CRC_STATUSr_WR_FAIL,
   2828     DDR34_PHY_BYTE_LANE_3_EDC_CRC_STATUSr_WR_PASS,
   2829     DDR34_PHY_BYTE_LANE_3_EDC_CRC_STATUSr_RD_FAIL,
   2830     DDR34_PHY_BYTE_LANE_3_EDC_CRC_STATUSr_RD_PASS,
   2831     DDR34_PHY_BYTE_LANE_3_EDC_CRC_STATUSr_CLEAR_RESERVED0,
   2832     DDR34_PHY_BYTE_LANE_3_EDC_CRC_STATUSr_CLEAR_CLEAR,
   2833     DDR34_PHY_BYTE_LANE_3_EDC_CRC_COUNTr_RESERVED0,
   2834     DDR34_PHY_BYTE_LANE_3_EDC_CRC_COUNTr_WR_COUNT,
   2835     DDR34_PHY_BYTE_LANE_3_EDC_CRC_COUNTr_RESERVED1,
   2836     DDR34_PHY_BYTE_LANE_3_EDC_CRC_COUNTr_RD_COUNT,
   2837     DDR34_PHY_BYTE_LANE_3_EDC_CRC_STATUS_CLEARr_RESERVED0,
   2838     DDR34_PHY_BYTE_LANE_3_EDC_CRC_STATUS_CLEARr_CLEAR,
   2839     DDR34_PHY_BYTE_LANE_3_BL_SPARE_REGr_RESERVED_for_eco0,
   2840     DDR34_PHY_CONTROL_REGS_PLL_CONFIGr_PLL_LDO_PWRDOWN,
   2841     DDR34_PHY_CONTROL_REGS_PLL_CONFIGr_RESERVED1,
   2842     DDR34_PHY_CONTROL_REGS_PLL_CONFIGr_ENABLE_EXT_CTRL,
   2843     DDR34_PHY_CONTROL_REGS_PLL_CONFIGr_ISO_OUT,
   2844     DDR34_PHY_CONTROL_REGS_PLL_CONFIGr_ISO_IN,
   2845     DDR34_PHY_CONTROL_REGS_AUX_CONTROLr_AUX0_IS_ODT,
   2846     DDR34_PHY_CONTROL_REGS_AUX_CONTROLr_PAR_IS_ODT,
   2847     DDR34_PHY_CONTROL_REGS_DRIVE_PAD_CTLr_2T_RESERVED0,
   2848     DDR34_PHY_CONTROL_REGS_DRIVE_PAD_CTLr_2T_PD_IDLE_STRENGTH,
   2849     DDR34_PHY_CONTROL_REGS_DRIVE_PAD_CTLr_2T_ND_IDLE_STRENGTH,
   2850     DDR34_PHY_CONTROL_REGS_DRIVE_PAD_CTLr_2T_PD_TERM_STRENGTH,
   2851     DDR34_PHY_CONTROL_REGS_DRIVE_PAD_CTLr_2T_ND_TERM_STRENGTH,
   2852     DDR34_PHY_CONTROL_REGS_DRIVE_PAD_CTLr_2T_PD_STRENGTH,
   2853     DDR34_PHY_CONTROL_REGS_DRIVE_PAD_CTLr_2T_ND_STRENGTH,
   2854     DDR34_PHY_CONTROL_REGS_DRIVE_PAD_CTL_2Tr_RESERVED0,
   2855     DDR34_PHY_CONTROL_REGS_DRIVE_PAD_CTL_2Tr_PD_IDLE_STRENGTH,
   2856     DDR34_PHY_CONTROL_REGS_DRIVE_PAD_CTL_2Tr_ND_IDLE_STRENGTH,
   2857     DDR34_PHY_CONTROL_REGS_DRIVE_PAD_CTL_2Tr_PD_TERM_STRENGTH,
   2858     DDR34_PHY_CONTROL_REGS_DRIVE_PAD_CTL_2Tr_ND_TERM_STRENGTH,
   2859     DDR34_PHY_CONTROL_REGS_DRIVE_PAD_CTL_2Tr_PD_STRENGTH,
   2860     DDR34_PHY_CONTROL_REGS_DRIVE_PAD_CTL_2Tr_ND_STRENGTH,
   2861     DDR34_PHY_CONTROL_REGS_DRAM_CONFIGr_DDR4_GEARDOWN_ENABLE,
   2862     DDR34_PHY_CONTROL_REGS_DRAM_CONFIGr_RESERVED2,
   2863     DDR34_PHY_CONTROL_REGS_DRAM_TIMING4r_TEMP,
   2864     DDR34_PHY_CONTROL_REGS_VDL_CALIBRATEr_CALIB_FAST,
   2865     DDR34_PHY_CONTROL_REGS_VDL_MONITOR_STATUSr_ERROR,
   2866     DDR34_PHY_CONTROL_REGS_VDL_MONITOR_STATUSr_PAUSED,
   2867     DDR34_PHY_CONTROL_REGS_VDL_MONITOR_STATUSr_BUSY,
   2868     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CKr_BUSY,
   2869     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CKr_RESERVED0,
   2870     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CKr_FORCE,
   2871     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CKr_RESERVED1,
   2872     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CKr_ADJ_EN,
   2873     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CKr_RESERVED2,
   2874     DDR34_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CKr_VDL_STEP,
   2875     DDR34_PHY_CONTROL_REGS_CMD_CYC_DLYr_RESERVED0,
   2876     DDR34_PHY_CONTROL_REGS_CMD_CYC_DLYr_CKE,
   2877     DDR34_PHY_CONTROL_REGS_CMD_CYC_DLYr_WE_N,
   2878     DDR34_PHY_CONTROL_REGS_CMD_CYC_DLYr_CAS_N,
   2879     DDR34_PHY_CONTROL_REGS_CMD_CYC_DLYr_RAS_N,
   2880     DDR34_PHY_CONTROL_REGS_CMD_CYC_DLYr_CS_N,
   2881     DDR34_PHY_CONTROL_REGS_COMMAND_AUX_REG1r_AD16,
   2882     DDR34_PHY_CONTROL_REGS_COMMAND_AUX_REG2r_AD16,
   2883     DDR34_PHY_CONTROL_REGS_COMMAND_AUX_REG3r_AD16,
   2884     DDR34_PHY_CONTROL_REGS_COMMAND_AUX_REG4r_AD16,
   2885     DDR34_PHY_CONTROL_REGS_ALERT_STATUSr_BL3_STATE,
   2886     DDR34_PHY_CONTROL_REGS_ALERT_STATUSr_BL2_STATE,
   2887     DDR34_PHY_CONTROL_REGS_ALERT_STATUSr_BL1_STATE,
   2888     DDR34_PHY_CONTROL_REGS_ALERT_STATUSr_BL0_STATE,
   2889     DDR34_PHY_CONTROL_REGS_ALERT_STATUSr_RESERVED1,
   2890     DDR34_PHY_CONTROL_REGS_ALERT_STATUSr_BL3_ALERT,
   2891     DDR34_PHY_CONTROL_REGS_ALERT_STATUSr_BL2_ALERT,
   2892     DDR34_PHY_CONTROL_REGS_ALERT_STATUSr_BL1_ALERT,
   2893     DDR34_PHY_CONTROL_REGS_ALERT_STATUSr_BL0_ALERT,
   2894     DDR34_PHY_CONTROL_REGS_ALERT_DFIr_RESERVED0,
   2895     DDR34_PHY_CONTROL_REGS_ALERT_DFIr_MASK,
   2896     DDR34_PHY_CONTROL_REGS_READ_ENABLE_CONTROLr_RESERVED2,
   2897     DDR34_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROLr_RESERVED_FOR_ECO1,
   2898     DDR34_PHY_CONTROL_REGS_PHYBIST_CNTRLr_PATTERN_SEL,
   2899     DDR34_PHY_CONTROL_REGS_PHYBIST_CA_MASKr_MASK,
   2900     DDR34_PHY_CONTROL_REGS_PHYBIST_DQ_MASK1r_MASK,
   2901     DDR34_PHY_CONTROL_REGS_PHYBIST_DQ_MASK2r_RESERVED0,
   2902     DDR34_PHY_CONTROL_REGS_PHYBIST_DQ_MASK2r_ALERT_MASK,
   2903     DDR34_PHY_CONTROL_REGS_PHYBIST_DQ_MASK2r_RESERVED1,
   2904     DDR34_PHY_CONTROL_REGS_PHYBIST_DQ_MASK2r_DM_MASK,
   2905     DDR34_PHY_CONTROL_REGS_PHYBIST_DQ_MASK2r_RESERVED2,
   2906     DDR34_PHY_CONTROL_REGS_PHYBIST_BL0_STATUSr_ALERT,
   2907     DDR34_PHY_CONTROL_REGS_PHYBIST_BL1_STATUSr_ALERT,
   2908     DDR34_PHY_CONTROL_REGS_PHYBIST_BL2_STATUSr_ALERT,
   2909     DDR34_PHY_CONTROL_REGS_PHYBIST_BL3_STATUSr_ALERT,
   2910     DDR34_PHY_CONTROL_REGS_PHYBIST_BL4_STATUSr_ALERT,
   2911     DDR34_PHY_CONTROL_REGS_STANDBY_CONTROLr_PHY_STANDBY,
   2912     DDR34_PHY_CONTROL_REGS_STANDBY_CONTROLr_FORCE_CKE_RST_N,
   2913     DDR34_PHY_CONTROL_REGS_STANDBY_CONTROLr_BIT_PIPE_RESET,
   2914     DDR34_PHY_CONTROL_REGS_DFI_CNTRLr_SELF_REFRESH,
   2915     DDR34_PHY_CONTROL_REGS_DFI_CNTRLr_RESERVED1,
   2916     DDR34_PHY_CONTROL_REGS_WRITE_ODT_CNTRLr_ODT1_FORCE_VALUE,
   2917     DDR34_PHY_CONTROL_REGS_WRITE_ODT_CNTRLr_ODT1_FORCE,
   2918     DDR34_PHY_CONTROL_REGS_WRITE_ODT_CNTRLr_ODT1_ENABLE,
   2919     DDR34_PHY_CONTROL_REGS_WRITE_ODT_CNTRLr_ODT1_LENGTH,
   2920     DDR34_PHY_CONTROL_REGS_WRITE_ODT_CNTRLr_ODT1_DELAY,
   2921     DDR34_PHY_CONTROL_REGS_WRITE_ODT_CNTRLr_RESERVED1,
   2922     DDR34_PHY_CONTROL_REGS_WRITE_ODT_CNTRLr_ODT0_FORCE_VALUE,
   2923     DDR34_PHY_CONTROL_REGS_WRITE_ODT_CNTRLr_ODT0_FORCE,
   2924     DDR34_PHY_CONTROL_REGS_WRITE_ODT_CNTRLr_ODT0_ENABLE,
   2925     DDR34_PHY_CONTROL_REGS_WRITE_ODT_CNTRLr_ODT0_LENGTH,
   2926     DDR34_PHY_CONTROL_REGS_WRITE_ODT_CNTRLr_ODT0_DELAY,
   2927     DDR34_PHY_CONTROL_REGS_ABI_PAR_CNTRLr_PAR_ERROR,
   2928     DDR34_PHY_CONTROL_REGS_ZQ_CALr_RESERVED1,
   2929     DDR34_PHY_CONTROL_REGS_ZQ_CAL2r_RESERVED0,
   2930     DDR34_PHY_CONTROL_REGS_ZQ_CAL2r_ZQ_CAL_RESET,
   2931     DDR34_PHY_CONTROL_REGS_ZQ_CAL2r_ZQ_CAL_ERROR_N,
   2932     DDR34_PHY_CONTROL_REGS_ZQ_CAL2r_ZQ_CAL_ERROR_P,
   2933     DDR34_PHY_CONTROL_REGS_ZQ_CAL2r_ZQ_NSETTING,
   2934     DDR34_PHY_CONTROL_REGS_ZQ_CAL2r_ZQ_PSETTING,
   2935     DDR34_PHY_CONTROL_REGS_ZQ_CAL2r_ZQ_CAL_OP_COMPLETE_N,
   2936     DDR34_PHY_CONTROL_REGS_ZQ_CAL2r_ZQ_CAL_OP_COMPLETE_P,
   2937     DDR34_PHY_CONTROL_REGS_ZQ_CAL2r_ZQ_CAL_START_N,
   2938     DDR34_PHY_CONTROL_REGS_ZQ_CAL2r_ZQ_CAL_START_P,
   2939     DDR34_PHY_CONTROL_REGS_RO_PROC_MON_CTLr_RESERVED0,
   2940     DDR34_PHY_CONTROL_REGS_RO_PROC_MON_CTLr_BUSY,
   2941     DDR34_PHY_CONTROL_REGS_RO_PROC_MON_CTLr_TRIGGER,
   2942     DDR34_PHY_CONTROL_REGS_RO_PROC_MON_CTLr_RESET,
   2943     DDR34_PHY_CONTROL_REGS_RO_PROC_MON_CTLr_SEL,
   2944     DDR34_PHY_CONTROL_REGS_RO_PROC_MON_CTLr_EN,
   2945     DDR34_PHY_CONTROL_REGS_RO_PROC_MON_STATUSr_CLK_COUNT,
   2946     DDR34_PHY_CONTROL_REGS_RO_PROC_MON_STATUSr_RO_COUNT,
   2947     DDR34_PHY_CONTROL_REGS_CK_DRIVE_PAD_CTLr_RESERVED0,
   2948     DDR34_PHY_CONTROL_REGS_CK_DRIVE_PAD_CTLr_ADDR_CTL_PD_IDLE_STRENGTH,
   2949     DDR34_PHY_CONTROL_REGS_CK_DRIVE_PAD_CTLr_ADDR_CTL_ND_IDLE_STRENGTH,
   2950     DDR34_PHY_CONTROL_REGS_CK_DRIVE_PAD_CTLr_ADDR_CTL_PD_TERM_STRENGTH,
   2951     DDR34_PHY_CONTROL_REGS_CK_DRIVE_PAD_CTLr_ADDR_CTL_ND_TERM_STRENGTH,
   2952     DDR34_PHY_CONTROL_REGS_CK_DRIVE_PAD_CTLr_ADDR_CTL_PD_STRENGTH,
   2953     DDR34_PHY_CONTROL_REGS_CK_DRIVE_PAD_CTLr_ADDR_CTL_ND_STRENGTH,
   2954     DDR34_PHY_CONTROL_REGS_BYTE_LANE_ALIGN_MASKSr_RESERVED0,
   2955     DDR34_PHY_CONTROL_REGS_BYTE_LANE_ALIGN_MASKSr_MASK_ENABLE,
   2956     DDR34_PHY_CONTROL_REGS_BYTE_LANE_ALIGN_MASKSr_RESERVED1,
   2957     DDR34_PHY_CONTROL_REGS_BYTE_LANE_ALIGN_MASKSr_BL3_MASK,
   2958     DDR34_PHY_CONTROL_REGS_BYTE_LANE_ALIGN_MASKSr_BL2_MASK,
   2959     DDR34_PHY_CONTROL_REGS_BYTE_LANE_ALIGN_MASKSr_BL1_MASK,
   2960     DDR34_PHY_CONTROL_REGS_BYTE_LANE_ALIGN_MASKSr_BL0_MASK,
   2961     DDR34_PHY_CONTROL_REGS_CLOCK_IDLEr_RESERVED0,
   2962     DDR34_PHY_CONTROL_REGS_CLOCK_IDLEr_BIT_CLOCK_CS,
   2963     DDR34_PHY_CONTROL_REGS_CLOCK_IDLEr_BIT_CLOCK_LS,
   2964     DDR34_PHY_CONTROL_REGS_CLOCK_IDLEr_TO_MC_CLOCK,
   2965     DDR34_PHY_CONTROL_REGS_CLOCK_IDLEr_FROM_MC_CLOCK,
   2966     DDR34_PHY_CONTROL_REGS_CLOCK_IDLEr_BIT_CLOCK,
   2967     DDR34_PHY_CONTROL_REGS_AC_SPARE_REGr_RESERVED_FOR_ECO0,
   2968     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQSr_BUSY,
   2969     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQSr_RESERVED0,
   2970     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQSr_FORCE,
   2971     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQSr_RESERVED1,
   2972     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQSr_ADJ_EN,
   2973     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQSr_RESERVED2,
   2974     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQSr_VDL_STEP,
   2975     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_ALERTr_BUSY,
   2976     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_ALERTr_RESERVED0,
   2977     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_ALERTr_FORCE,
   2978     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_ALERTr_RESERVED1,
   2979     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_ALERTr_ADJ_EN,
   2980     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_ALERTr_RESERVED2,
   2981     DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_ALERTr_VDL_STEP,
   2982     DDR34_PHY_BYTE_LANE_0_RD_EN_DLY_CYCr_ENABLE_CS1,
   2983     DDR34_PHY_BYTE_LANE_0_WR_CHAN_DLY_CYCr_DQ_CYCLES,
   2984     DDR34_PHY_BYTE_LANE_0_WR_CHAN_DLY_CYCr_RESERVED2,
   2985     DDR34_PHY_BYTE_LANE_0_READ_CONTROLr_RD_EN_MODE,
   2986     DDR34_PHY_BYTE_LANE_0_DQSP_DRIVE_PAD_CTLr_RESERVED0,
   2987     DDR34_PHY_BYTE_LANE_0_DQSP_DRIVE_PAD_CTLr_BL_PD_TERM_STRENGTH,
   2988     DDR34_PHY_BYTE_LANE_0_DQSP_DRIVE_PAD_CTLr_BL_ND_TERM_STRENGTH,
   2989     DDR34_PHY_BYTE_LANE_0_DQSP_DRIVE_PAD_CTLr_BL_PD_STRENGTH,
   2990     DDR34_PHY_BYTE_LANE_0_DQSP_DRIVE_PAD_CTLr_BL_ND_STRENGTH,
   2991     DDR34_PHY_BYTE_LANE_0_DQSN_DRIVE_PAD_CTLr_RESERVED0,
   2992     DDR34_PHY_BYTE_LANE_0_DQSN_DRIVE_PAD_CTLr_BL_PD_TERM_STRENGTH,
   2993     DDR34_PHY_BYTE_LANE_0_DQSN_DRIVE_PAD_CTLr_BL_ND_TERM_STRENGTH,
   2994     DDR34_PHY_BYTE_LANE_0_DQSN_DRIVE_PAD_CTLr_BL_PD_STRENGTH,
   2995     DDR34_PHY_BYTE_LANE_0_DQSN_DRIVE_PAD_CTLr_BL_ND_STRENGTH,
   2996     DDR34_PHY_BYTE_LANE_0_ALERT_DRIVE_PAD_CTLr_RESERVED0,
   2997     DDR34_PHY_BYTE_LANE_0_ALERT_DRIVE_PAD_CTLr_BL_PD_TERM_STRENGTH,
   2998     DDR34_PHY_BYTE_LANE_0_ALERT_DRIVE_PAD_CTLr_BL_ND_TERM_STRENGTH,
   2999     DDR34_PHY_BYTE_LANE_0_ALERT_DRIVE_PAD_CTLr_BL_PD_STRENGTH,
   3000     DDR34_PHY_BYTE_LANE_0_ALERT_DRIVE_PAD_CTLr_BL_ND_STRENGTH,
   3001     DDR34_PHY_BYTE_LANE_0_STATIC_PAD_CTLr_DM_INVERT,
   3002     DDR34_PHY_BYTE_LANE_0_WR_PREAMBLE_MODEr_POSTAM_TERM_BITS,
   3003     DDR34_PHY_BYTE_LANE_0_WR_PREAMBLE_MODEr_DM_POSTAM_BITS,
   3004     DDR34_PHY_BYTE_LANE_0_WR_PREAMBLE_MODEr_DM_PREAM_BITS,
   3005     DDR34_PHY_BYTE_LANE_0_ODT_CONTROLr_RESERVED0,
   3006     DDR34_PHY_BYTE_LANE_0_CLOCK_ENABLEr_RESERVED0,
   3007     DDR34_PHY_BYTE_LANE_0_CLOCK_ENABLEr_TO_MC_CLOCK,
   3008     DDR34_PHY_BYTE_LANE_0_CLOCK_ENABLEr_FROM_MC_CLOCK,
   3009     DDR34_PHY_BYTE_LANE_0_CLOCK_ENABLEr_BIT_CLOCK,
   3010     DDR34_PHY_BYTE_LANE_0_CLOCK_IDLEr_RESERVED0,
   3011     DDR34_PHY_BYTE_LANE_0_CLOCK_IDLEr_TO_MC_CLOCK,
   3012     DDR34_PHY_BYTE_LANE_0_CLOCK_IDLEr_FROM_MC_CLOCK,
   3013     DDR34_PHY_BYTE_LANE_0_CLOCK_IDLEr_BIT_CLOCK,
   3014     DDR34_PHY_BYTE_LANE_0_BL_SPARE_REGr_RESERVED_FOR_ECO0,
   3015     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQSr_BUSY,
   3016     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQSr_RESERVED0,
   3017     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQSr_FORCE,
   3018     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQSr_RESERVED1,
   3019     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQSr_ADJ_EN,
   3020     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQSr_RESERVED2,
   3021     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQSr_VDL_STEP,
   3022     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_ALERTr_BUSY,
   3023     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_ALERTr_RESERVED0,
   3024     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_ALERTr_FORCE,
   3025     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_ALERTr_RESERVED1,
   3026     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_ALERTr_ADJ_EN,
   3027     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_ALERTr_RESERVED2,
   3028     DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_ALERTr_VDL_STEP,
   3029     DDR34_PHY_BYTE_LANE_1_RD_EN_DLY_CYCr_ENABLE_CS1,
   3030     DDR34_PHY_BYTE_LANE_1_WR_CHAN_DLY_CYCr_DQ_CYCLES,
   3031     DDR34_PHY_BYTE_LANE_1_WR_CHAN_DLY_CYCr_RESERVED2,
   3032     DDR34_PHY_BYTE_LANE_1_READ_CONTROLr_RD_EN_MODE,
   3033     DDR34_PHY_BYTE_LANE_1_DQSP_DRIVE_PAD_CTLr_RESERVED0,
   3034     DDR34_PHY_BYTE_LANE_1_DQSP_DRIVE_PAD_CTLr_BL_PD_TERM_STRENGTH,
   3035     DDR34_PHY_BYTE_LANE_1_DQSP_DRIVE_PAD_CTLr_BL_ND_TERM_STRENGTH,
   3036     DDR34_PHY_BYTE_LANE_1_DQSP_DRIVE_PAD_CTLr_BL_PD_STRENGTH,
   3037     DDR34_PHY_BYTE_LANE_1_DQSP_DRIVE_PAD_CTLr_BL_ND_STRENGTH,
   3038     DDR34_PHY_BYTE_LANE_1_DQSN_DRIVE_PAD_CTLr_RESERVED0,
   3039     DDR34_PHY_BYTE_LANE_1_DQSN_DRIVE_PAD_CTLr_BL_PD_TERM_STRENGTH,
   3040     DDR34_PHY_BYTE_LANE_1_DQSN_DRIVE_PAD_CTLr_BL_ND_TERM_STRENGTH,
   3041     DDR34_PHY_BYTE_LANE_1_DQSN_DRIVE_PAD_CTLr_BL_PD_STRENGTH,
   3042     DDR34_PHY_BYTE_LANE_1_DQSN_DRIVE_PAD_CTLr_BL_ND_STRENGTH,
   3043     DDR34_PHY_BYTE_LANE_1_ALERT_DRIVE_PAD_CTLr_RESERVED0,
   3044     DDR34_PHY_BYTE_LANE_1_ALERT_DRIVE_PAD_CTLr_BL_PD_TERM_STRENGTH,
   3045     DDR34_PHY_BYTE_LANE_1_ALERT_DRIVE_PAD_CTLr_BL_ND_TERM_STRENGTH,
   3046     DDR34_PHY_BYTE_LANE_1_ALERT_DRIVE_PAD_CTLr_BL_PD_STRENGTH,
   3047     DDR34_PHY_BYTE_LANE_1_ALERT_DRIVE_PAD_CTLr_BL_ND_STRENGTH,
   3048     DDR34_PHY_BYTE_LANE_1_STATIC_PAD_CTLr_DM_INVERT,
   3049     DDR34_PHY_BYTE_LANE_1_WR_PREAMBLE_MODEr_POSTAM_TERM_BITS,
   3050     DDR34_PHY_BYTE_LANE_1_WR_PREAMBLE_MODEr_DM_POSTAM_BITS,
   3051     DDR34_PHY_BYTE_LANE_1_WR_PREAMBLE_MODEr_DM_PREAM_BITS,
   3052     DDR34_PHY_BYTE_LANE_1_ODT_CONTROLr_RESERVED0,
   3053     DDR34_PHY_BYTE_LANE_1_CLOCK_ENABLEr_RESERVED0,
   3054     DDR34_PHY_BYTE_LANE_1_CLOCK_ENABLEr_TO_MC_CLOCK,
   3055     DDR34_PHY_BYTE_LANE_1_CLOCK_ENABLEr_FROM_MC_CLOCK,
   3056     DDR34_PHY_BYTE_LANE_1_CLOCK_ENABLEr_BIT_CLOCK,
   3057     DDR34_PHY_BYTE_LANE_1_CLOCK_IDLEr_RESERVED0,
   3058     DDR34_PHY_BYTE_LANE_1_CLOCK_IDLEr_TO_MC_CLOCK,
   3059     DDR34_PHY_BYTE_LANE_1_CLOCK_IDLEr_FROM_MC_CLOCK,
   3060     DDR34_PHY_BYTE_LANE_1_CLOCK_IDLEr_BIT_CLOCK,
   3061     DDR34_PHY_BYTE_LANE_1_BL_SPARE_REGr_RESERVED_FOR_ECO0,
   3062     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQSr_BUSY,
   3063     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQSr_RESERVED0,
   3064     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQSr_FORCE,
   3065     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQSr_RESERVED1,
   3066     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQSr_ADJ_EN,
   3067     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQSr_RESERVED2,
   3068     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQSr_VDL_STEP,
   3069     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_ALERTr_BUSY,
   3070     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_ALERTr_RESERVED0,
   3071     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_ALERTr_FORCE,
   3072     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_ALERTr_RESERVED1,
   3073     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_ALERTr_ADJ_EN,
   3074     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_ALERTr_RESERVED2,
   3075     DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_ALERTr_VDL_STEP,
   3076     DDR34_PHY_BYTE_LANE_2_RD_EN_DLY_CYCr_ENABLE_CS1,
   3077     DDR34_PHY_BYTE_LANE_2_WR_CHAN_DLY_CYCr_DQ_CYCLES,
   3078     DDR34_PHY_BYTE_LANE_2_WR_CHAN_DLY_CYCr_RESERVED2,
   3079     DDR34_PHY_BYTE_LANE_2_READ_CONTROLr_RD_EN_MODE,
   3080     DDR34_PHY_BYTE_LANE_2_DQSP_DRIVE_PAD_CTLr_RESERVED0,
   3081     DDR34_PHY_BYTE_LANE_2_DQSP_DRIVE_PAD_CTLr_BL_PD_TERM_STRENGTH,
   3082     DDR34_PHY_BYTE_LANE_2_DQSP_DRIVE_PAD_CTLr_BL_ND_TERM_STRENGTH,
   3083     DDR34_PHY_BYTE_LANE_2_DQSP_DRIVE_PAD_CTLr_BL_PD_STRENGTH,
   3084     DDR34_PHY_BYTE_LANE_2_DQSP_DRIVE_PAD_CTLr_BL_ND_STRENGTH,
   3085     DDR34_PHY_BYTE_LANE_2_DQSN_DRIVE_PAD_CTLr_RESERVED0,
   3086     DDR34_PHY_BYTE_LANE_2_DQSN_DRIVE_PAD_CTLr_BL_PD_TERM_STRENGTH,
   3087     DDR34_PHY_BYTE_LANE_2_DQSN_DRIVE_PAD_CTLr_BL_ND_TERM_STRENGTH,
   3088     DDR34_PHY_BYTE_LANE_2_DQSN_DRIVE_PAD_CTLr_BL_PD_STRENGTH,
   3089     DDR34_PHY_BYTE_LANE_2_DQSN_DRIVE_PAD_CTLr_BL_ND_STRENGTH,
   3090     DDR34_PHY_BYTE_LANE_2_ALERT_DRIVE_PAD_CTLr_RESERVED0,
   3091     DDR34_PHY_BYTE_LANE_2_ALERT_DRIVE_PAD_CTLr_BL_PD_TERM_STRENGTH,
   3092     DDR34_PHY_BYTE_LANE_2_ALERT_DRIVE_PAD_CTLr_BL_ND_TERM_STRENGTH,
   3093     DDR34_PHY_BYTE_LANE_2_ALERT_DRIVE_PAD_CTLr_BL_PD_STRENGTH,
   3094     DDR34_PHY_BYTE_LANE_2_ALERT_DRIVE_PAD_CTLr_BL_ND_STRENGTH,
   3095     DDR34_PHY_BYTE_LANE_2_STATIC_PAD_CTLr_DM_INVERT,
   3096     DDR34_PHY_BYTE_LANE_2_WR_PREAMBLE_MODEr_POSTAM_TERM_BITS,
   3097     DDR34_PHY_BYTE_LANE_2_WR_PREAMBLE_MODEr_DM_POSTAM_BITS,
   3098     DDR34_PHY_BYTE_LANE_2_WR_PREAMBLE_MODEr_DM_PREAM_BITS,
   3099     DDR34_PHY_BYTE_LANE_2_ODT_CONTROLr_RESERVED0,
   3100     DDR34_PHY_BYTE_LANE_2_CLOCK_ENABLEr_RESERVED0,
   3101     DDR34_PHY_BYTE_LANE_2_CLOCK_ENABLEr_TO_MC_CLOCK,
   3102     DDR34_PHY_BYTE_LANE_2_CLOCK_ENABLEr_FROM_MC_CLOCK,
   3103     DDR34_PHY_BYTE_LANE_2_CLOCK_ENABLEr_BIT_CLOCK,
   3104     DDR34_PHY_BYTE_LANE_2_CLOCK_IDLEr_RESERVED0,
   3105     DDR34_PHY_BYTE_LANE_2_CLOCK_IDLEr_TO_MC_CLOCK,
   3106     DDR34_PHY_BYTE_LANE_2_CLOCK_IDLEr_FROM_MC_CLOCK,
   3107     DDR34_PHY_BYTE_LANE_2_CLOCK_IDLEr_BIT_CLOCK,
   3108     DDR34_PHY_BYTE_LANE_2_BL_SPARE_REGr_RESERVED_FOR_ECO0,
   3109     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQSr_BUSY,
   3110     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQSr_RESERVED0,
   3111     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQSr_FORCE,
   3112     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQSr_RESERVED1,
   3113     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQSr_ADJ_EN,
   3114     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQSr_RESERVED2,
   3115     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQSr_VDL_STEP,
   3116     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_ALERTr_BUSY,
   3117     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_ALERTr_RESERVED0,
   3118     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_ALERTr_FORCE,
   3119     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_ALERTr_RESERVED1,
   3120     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_ALERTr_ADJ_EN,
   3121     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_ALERTr_RESERVED2,
   3122     DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_ALERTr_VDL_STEP,
   3123     DDR34_PHY_BYTE_LANE_3_RD_EN_DLY_CYCr_ENABLE_CS1,
   3124     DDR34_PHY_BYTE_LANE_3_WR_CHAN_DLY_CYCr_DQ_CYCLES,
   3125     DDR34_PHY_BYTE_LANE_3_WR_CHAN_DLY_CYCr_RESERVED2,
   3126     DDR34_PHY_BYTE_LANE_3_READ_CONTROLr_RD_EN_MODE,
   3127     DDR34_PHY_BYTE_LANE_3_DQSP_DRIVE_PAD_CTLr_RESERVED0,
   3128     DDR34_PHY_BYTE_LANE_3_DQSP_DRIVE_PAD_CTLr_BL_PD_TERM_STRENGTH,
   3129     DDR34_PHY_BYTE_LANE_3_DQSP_DRIVE_PAD_CTLr_BL_ND_TERM_STRENGTH,
   3130     DDR34_PHY_BYTE_LANE_3_DQSP_DRIVE_PAD_CTLr_BL_PD_STRENGTH,
   3131     DDR34_PHY_BYTE_LANE_3_DQSP_DRIVE_PAD_CTLr_BL_ND_STRENGTH,
   3132     DDR34_PHY_BYTE_LANE_3_DQSN_DRIVE_PAD_CTLr_RESERVED0,
   3133     DDR34_PHY_BYTE_LANE_3_DQSN_DRIVE_PAD_CTLr_BL_PD_TERM_STRENGTH,
   3134     DDR34_PHY_BYTE_LANE_3_DQSN_DRIVE_PAD_CTLr_BL_ND_TERM_STRENGTH,
   3135     DDR34_PHY_BYTE_LANE_3_DQSN_DRIVE_PAD_CTLr_BL_PD_STRENGTH,
   3136     DDR34_PHY_BYTE_LANE_3_DQSN_DRIVE_PAD_CTLr_BL_ND_STRENGTH,
   3137     DDR34_PHY_BYTE_LANE_3_ALERT_DRIVE_PAD_CTLr_RESERVED0,
   3138     DDR34_PHY_BYTE_LANE_3_ALERT_DRIVE_PAD_CTLr_BL_PD_TERM_STRENGTH,
   3139     DDR34_PHY_BYTE_LANE_3_ALERT_DRIVE_PAD_CTLr_BL_ND_TERM_STRENGTH,
   3140     DDR34_PHY_BYTE_LANE_3_ALERT_DRIVE_PAD_CTLr_BL_PD_STRENGTH,
   3141     DDR34_PHY_BYTE_LANE_3_ALERT_DRIVE_PAD_CTLr_BL_ND_STRENGTH,
   3142     DDR34_PHY_BYTE_LANE_3_STATIC_PAD_CTLr_DM_INVERT,
   3143     DDR34_PHY_BYTE_LANE_3_WR_PREAMBLE_MODEr_POSTAM_TERM_BITS,
   3144     DDR34_PHY_BYTE_LANE_3_WR_PREAMBLE_MODEr_DM_POSTAM_BITS,
   3145     DDR34_PHY_BYTE_LANE_3_WR_PREAMBLE_MODEr_DM_PREAM_BITS,
   3146     DDR34_PHY_BYTE_LANE_3_ODT_CONTROLr_RESERVED0,
   3147     DDR34_PHY_BYTE_LANE_3_CLOCK_ENABLEr_RESERVED0,
   3148     DDR34_PHY_BYTE_LANE_3_CLOCK_ENABLEr_TO_MC_CLOCK,
   3149     DDR34_PHY_BYTE_LANE_3_CLOCK_ENABLEr_FROM_MC_CLOCK,
   3150     DDR34_PHY_BYTE_LANE_3_CLOCK_ENABLEr_BIT_CLOCK,
   3151     DDR34_PHY_BYTE_LANE_3_CLOCK_IDLEr_RESERVED0,
   3152     DDR34_PHY_BYTE_LANE_3_CLOCK_IDLEr_TO_MC_CLOCK,
   3153     DDR34_PHY_BYTE_LANE_3_CLOCK_IDLEr_FROM_MC_CLOCK,
   3154     DDR34_PHY_BYTE_LANE_3_CLOCK_IDLEr_BIT_CLOCK,
   3155     DDR34_PHY_BYTE_LANE_3_BL_SPARE_REGr_RESERVED_FOR_ECO0,
   3156     DDR34_PHY_MAX_FIELD_INDEX
   3157 } ddr34_phy_reg_fields_t;
   3158 
   3159 /*******************************************************************************
   3160  */
   3161 #define INIT_DDR34_E0_PHY_REGS_TABLE()   { \
   3162     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_REVISIONr) = DDR34_E0_PHY_CONTROL_REGS_REVISION; \
   3163     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_PLL_STATUSr) = DDR34_E0_PHY_CONTROL_REGS_PLL_STATUS; \
   3164     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_PLL_CONFIGr) = DDR34_E0_PHY_CONTROL_REGS_PLL_CONFIG; \
   3165     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_PLL_CONTROL1r) = DDR34_E0_PHY_CONTROL_REGS_PLL_CONTROL1; \
   3166     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_PLL_CONTROL2r) = DDR34_E0_PHY_CONTROL_REGS_PLL_CONTROL2; \
   3167     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_PLL_CONTROL3r) = DDR34_E0_PHY_CONTROL_REGS_PLL_CONTROL3; \
   3168     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_PLL_DIVIDERSr) = DDR34_E0_PHY_CONTROL_REGS_PLL_DIVIDERS; \
   3169     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_PLL_FRAC_DIVIDERr) = DDR34_E0_PHY_CONTROL_REGS_PLL_FRAC_DIVIDER; \
   3170     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_PLL_SS_CONTROLr) = DDR34_E0_PHY_CONTROL_REGS_PLL_SS_CONTROL; \
   3171     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_PLL_SS_LIMITr) = DDR34_E0_PHY_CONTROL_REGS_PLL_SS_LIMIT; \
   3172     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_AUX_CONTROLr) = DDR34_E0_PHY_CONTROL_REGS_AUX_CONTROL; \
   3173     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_IDLE_PAD_CONTROLr) = DDR34_E0_PHY_CONTROL_REGS_IDLE_PAD_CONTROL; \
   3174     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_IDLE_PAD_ENABLE0r) = DDR34_E0_PHY_CONTROL_REGS_IDLE_PAD_ENABLE0; \
   3175     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_IDLE_PAD_ENABLE1r) = DDR34_E0_PHY_CONTROL_REGS_IDLE_PAD_ENABLE1; \
   3176     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_DRIVE_PAD_CTLr) = DDR34_E0_PHY_CONTROL_REGS_DRIVE_PAD_CTL; \
   3177     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_STATIC_PAD_CTLr) = DDR34_E0_PHY_CONTROL_REGS_STATIC_PAD_CTL; \
   3178     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_DRAM_CONFIGr) = DDR34_E0_PHY_CONTROL_REGS_DRAM_CONFIG; \
   3179     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_DRAM_TIMING1r) = DDR34_E0_PHY_CONTROL_REGS_DRAM_TIMING1; \
   3180     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_DRAM_TIMING2r) = DDR34_E0_PHY_CONTROL_REGS_DRAM_TIMING2; \
   3181     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_DRAM_TIMING3r) = DDR34_E0_PHY_CONTROL_REGS_DRAM_TIMING3; \
   3182     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_DRAM_TIMING4r) = DDR34_E0_PHY_CONTROL_REGS_DRAM_TIMING4; \
   3183     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CALIBRATEr) = DDR34_E0_PHY_CONTROL_REGS_VDL_CALIBRATE; \
   3184     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CALIB_STATUS1r) = DDR34_E0_PHY_CONTROL_REGS_VDL_CALIB_STATUS1; \
   3185     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CALIB_STATUS2r) = DDR34_E0_PHY_CONTROL_REGS_VDL_CALIB_STATUS2; \
   3186     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_MONITOR_CONTROLr) = DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_CONTROL; \
   3187     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_MONITOR_REFr) = DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_REF; \
   3188     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_MONITOR_STATUSr) = DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_STATUS; \
   3189     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDEr) = DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDE; \
   3190     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_MONITOR_OUT_CONTROLr) = DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_OUT_CONTROL; \
   3191     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUSr) = DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS; \
   3192     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_CLEARr) = DDR34_E0_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_CLEAR; \
   3193     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD00r) = DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD00; \
   3194     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD01r) = DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD01; \
   3195     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD02r) = DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD02; \
   3196     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD03r) = DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD03; \
   3197     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD04r) = DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD04; \
   3198     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD05r) = DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD05; \
   3199     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD06r) = DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD06; \
   3200     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD07r) = DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD07; \
   3201     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD08r) = DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD08; \
   3202     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD09r) = DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD09; \
   3203     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD10r) = DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD10; \
   3204     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD11r) = DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD11; \
   3205     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD12r) = DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD12; \
   3206     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD13r) = DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD13; \
   3207     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD14r) = DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD14; \
   3208     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD15r) = DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AD15; \
   3209     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_BA0r) = DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_BA0; \
   3210     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_BA1r) = DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_BA1; \
   3211     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_BA2r) = DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_BA2; \
   3212     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AUX0r) = DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AUX0; \
   3213     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AUX1r) = DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AUX1; \
   3214     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AUX2r) = DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_AUX2; \
   3215     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_CS0r) = DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_CS0; \
   3216     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_CS1r) = DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_CS1; \
   3217     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_PARr) = DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_PAR; \
   3218     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_RAS_Nr) = DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_RAS_N; \
   3219     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_CAS_Nr) = DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_CAS_N; \
   3220     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_CKEr) = DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_CKE; \
   3221     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_RST_Nr) = DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_RST_N; \
   3222     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_ODTr) = DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_ODT; \
   3223     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_WE_Nr) = DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_WE_N; \
   3224     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_Pr) = DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_P; \
   3225     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_Nr) = DDR34_E0_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_N; \
   3226     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CLK_CONTROLr) = DDR34_E0_PHY_CONTROL_REGS_VDL_CLK_CONTROL; \
   3227     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_LDE_CONTROLr) = DDR34_E0_PHY_CONTROL_REGS_VDL_LDE_CONTROL; \
   3228     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_REFRESHr) = DDR34_E0_PHY_CONTROL_REGS_REFRESH; \
   3229     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_UPDATE_VDLr) = DDR34_E0_PHY_CONTROL_REGS_UPDATE_VDL; \
   3230     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1r) = DDR34_E0_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1; \
   3231     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2r) = DDR34_E0_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2; \
   3232     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_COMMAND_REG1r) = DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG1; \
   3233     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_COMMAND_AUX_REG1r) = DDR34_E0_PHY_CONTROL_REGS_COMMAND_AUX_REG1; \
   3234     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_COMMAND_REG2r) = DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG2; \
   3235     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_COMMAND_AUX_REG2r) = DDR34_E0_PHY_CONTROL_REGS_COMMAND_AUX_REG2; \
   3236     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_COMMAND_REG3r) = DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG3; \
   3237     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_COMMAND_AUX_REG3r) = DDR34_E0_PHY_CONTROL_REGS_COMMAND_AUX_REG3; \
   3238     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_COMMAND_REG4r) = DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG4; \
   3239     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_COMMAND_AUX_REG4r) = DDR34_E0_PHY_CONTROL_REGS_COMMAND_AUX_REG4; \
   3240     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_COMMAND_REG_TIMERr) = DDR34_E0_PHY_CONTROL_REGS_COMMAND_REG_TIMER; \
   3241     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_MODE_REG0r) = DDR34_E0_PHY_CONTROL_REGS_MODE_REG0; \
   3242     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_MODE_REG1r) = DDR34_E0_PHY_CONTROL_REGS_MODE_REG1; \
   3243     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_MODE_REG2r) = DDR34_E0_PHY_CONTROL_REGS_MODE_REG2; \
   3244     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_MODE_REG3r) = DDR34_E0_PHY_CONTROL_REGS_MODE_REG3; \
   3245     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_MODE_REG4r) = DDR34_E0_PHY_CONTROL_REGS_MODE_REG4; \
   3246     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_MODE_REG5r) = DDR34_E0_PHY_CONTROL_REGS_MODE_REG5; \
   3247     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_MODE_REG6r) = DDR34_E0_PHY_CONTROL_REGS_MODE_REG6; \
   3248     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_MODE_REG7r) = DDR34_E0_PHY_CONTROL_REGS_MODE_REG7; \
   3249     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_MODE_REG8r) = DDR34_E0_PHY_CONTROL_REGS_MODE_REG8; \
   3250     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_MODE_REG15r) = DDR34_E0_PHY_CONTROL_REGS_MODE_REG15; \
   3251     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_MODE_REG63r) = DDR34_E0_PHY_CONTROL_REGS_MODE_REG63; \
   3252     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_ALERT_CLEARr) = DDR34_E0_PHY_CONTROL_REGS_ALERT_CLEAR; \
   3253     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_ALERT_STATUSr) = DDR34_E0_PHY_CONTROL_REGS_ALERT_STATUS; \
   3254     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_CA_PARITYr) = DDR34_E0_PHY_CONTROL_REGS_CA_PARITY; \
   3255     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_CA_PLAYBACK_CONTROLr) = DDR34_E0_PHY_CONTROL_REGS_CA_PLAYBACK_CONTROL; \
   3256     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS0r) = DDR34_E0_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS0; \
   3257     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS1r) = DDR34_E0_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS1; \
   3258     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_WRITE_LEVELING_CONTROLr) = DDR34_E0_PHY_CONTROL_REGS_WRITE_LEVELING_CONTROL; \
   3259     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_WRITE_LEVELING_STATUSr) = DDR34_E0_PHY_CONTROL_REGS_WRITE_LEVELING_STATUS; \
   3260     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_READ_ENABLE_CONTROLr) = DDR34_E0_PHY_CONTROL_REGS_READ_ENABLE_CONTROL; \
   3261     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_READ_ENABLE_STATUSr) = DDR34_E0_PHY_CONTROL_REGS_READ_ENABLE_STATUS; \
   3262     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_TRAFFIC_GEN_LFSR_SEEDr) = DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_LFSR_SEED; \
   3263     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_TRAFFIC_GEN_ADDRESS1r) = DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_ADDRESS1; \
   3264     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_TRAFFIC_GEN_ADDRESS2r) = DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_ADDRESS2; \
   3265     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROLr) = DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL; \
   3266     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_TRAFFIC_GEN_DATA_CONTROLr) = DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_DATA_CONTROL; \
   3267     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_MASKr) = DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_MASK; \
   3268     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_TRAFFIC_GEN_ECC_DQ_MASKr) = DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_ECC_DQ_MASK; \
   3269     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_TRAFFIC_GEN_STATUSr) = DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_STATUS; \
   3270     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUSr) = DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUS; \
   3271     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_TRAFFIC_GEN_ECC_STATUSr) = DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_ECC_STATUS; \
   3272     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_TRAFFIC_GEN_ERR_CNT_CONTROLr) = DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_ERR_CNT_CONTROL; \
   3273     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_TRAFFIC_GEN_ERR_CNT_STATUSr) = DDR34_E0_PHY_CONTROL_REGS_TRAFFIC_GEN_ERR_CNT_STATUS; \
   3274     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROLr) = DDR34_E0_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL; \
   3275     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUSr) = DDR34_E0_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS; \
   3276     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VIRTUAL_VTT_CONNECTIONSr) = DDR34_E0_PHY_CONTROL_REGS_VIRTUAL_VTT_CONNECTIONS; \
   3277     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VIRTUAL_VTT_OVERRIDEr) = DDR34_E0_PHY_CONTROL_REGS_VIRTUAL_VTT_OVERRIDE; \
   3278     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VREF_DAC_CONTROLr) = DDR34_E0_PHY_CONTROL_REGS_VREF_DAC_CONTROL; \
   3279     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_PHYBIST_CNTRLr) = DDR34_E0_PHY_CONTROL_REGS_PHYBIST_CNTRL; \
   3280     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_PHYBIST_SEEDr) = DDR34_E0_PHY_CONTROL_REGS_PHYBIST_SEED; \
   3281     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_PHYBIST_STATUSr) = DDR34_E0_PHY_CONTROL_REGS_PHYBIST_STATUS; \
   3282     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_PHYBIST_CTL_STATUSr) = DDR34_E0_PHY_CONTROL_REGS_PHYBIST_CTL_STATUS; \
   3283     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_PHYBIST_BL0_STATUSr) = DDR34_E0_PHY_CONTROL_REGS_PHYBIST_BL0_STATUS; \
   3284     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_PHYBIST_BL1_STATUSr) = DDR34_E0_PHY_CONTROL_REGS_PHYBIST_BL1_STATUS; \
   3285     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_PHYBIST_BL2_STATUSr) = DDR34_E0_PHY_CONTROL_REGS_PHYBIST_BL2_STATUS; \
   3286     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_PHYBIST_BL3_STATUSr) = DDR34_E0_PHY_CONTROL_REGS_PHYBIST_BL3_STATUS; \
   3287     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_PHYBIST_BL4_STATUSr) = DDR34_E0_PHY_CONTROL_REGS_PHYBIST_BL4_STATUS; \
   3288     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_STANDBY_CONTROLr) = DDR34_E0_PHY_CONTROL_REGS_STANDBY_CONTROL; \
   3289     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLEr) = DDR34_E0_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE; \
   3290     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_DEBUG_MUX_CONTROLr) = DDR34_E0_PHY_CONTROL_REGS_DEBUG_MUX_CONTROL; \
   3291     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_DFI_CNTRLr) = DDR34_E0_PHY_CONTROL_REGS_DFI_CNTRL; \
   3292     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_WRITE_ODT_CNTRLr) = DDR34_E0_PHY_CONTROL_REGS_WRITE_ODT_CNTRL; \
   3293     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_ABI_PAR_CNTRLr) = DDR34_E0_PHY_CONTROL_REGS_ABI_PAR_CNTRL; \
   3294     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_ZQ_CALr) = DDR34_E0_PHY_CONTROL_REGS_ZQ_CAL; \
   3295     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_AC_SPARE_REGr) = DDR34_E0_PHY_CONTROL_REGS_AC_SPARE_REG; \
   3296     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_Pr) = DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_P; \
   3297     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_Nr) = DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_N; \
   3298     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0r) = DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0; \
   3299     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1r) = DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1; \
   3300     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2r) = DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2; \
   3301     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3r) = DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3; \
   3302     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4r) = DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4; \
   3303     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5r) = DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5; \
   3304     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6r) = DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6; \
   3305     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7r) = DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7; \
   3306     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DMr) = DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DM; \
   3307     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_EDCr) = DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_EDC; \
   3308     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSPr) = DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSP; \
   3309     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSNr) = DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSN; \
   3310     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0Pr) = DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0P; \
   3311     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0Nr) = DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0N; \
   3312     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1Pr) = DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1P; \
   3313     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1Nr) = DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1N; \
   3314     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2Pr) = DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2P; \
   3315     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2Nr) = DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2N; \
   3316     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3Pr) = DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3P; \
   3317     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3Nr) = DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3N; \
   3318     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4Pr) = DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4P; \
   3319     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4Nr) = DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4N; \
   3320     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5Pr) = DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5P; \
   3321     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5Nr) = DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5N; \
   3322     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6Pr) = DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6P; \
   3323     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6Nr) = DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6N; \
   3324     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7Pr) = DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7P; \
   3325     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7Nr) = DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7N; \
   3326     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMPr) = DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMP; \
   3327     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMNr) = DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMN; \
   3328     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCPr) = DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCP; \
   3329     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCNr) = DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCN; \
   3330     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0r) = DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0; \
   3331     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1r) = DDR34_E0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1; \
   3332     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CLK_CONTROLr) = DDR34_E0_PHY_BYTE_LANE_0_VDL_CLK_CONTROL; \
   3333     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_LDE_CONTROLr) = DDR34_E0_PHY_BYTE_LANE_0_VDL_LDE_CONTROL; \
   3334     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_RD_EN_DLY_CYCr) = DDR34_E0_PHY_BYTE_LANE_0_RD_EN_DLY_CYC; \
   3335     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_WR_CHAN_DLY_CYCr) = DDR34_E0_PHY_BYTE_LANE_0_WR_CHAN_DLY_CYC; \
   3336     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_READ_CONTROLr) = DDR34_E0_PHY_BYTE_LANE_0_READ_CONTROL; \
   3337     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_READ_FIFO_ADDRr) = DDR34_E0_PHY_BYTE_LANE_0_READ_FIFO_ADDR; \
   3338     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_READ_FIFO_DATAr) = DDR34_E0_PHY_BYTE_LANE_0_READ_FIFO_DATA; \
   3339     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_READ_FIFO_DM_DBIr) = DDR34_E0_PHY_BYTE_LANE_0_READ_FIFO_DM_DBI; \
   3340     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_READ_FIFO_STATUSr) = DDR34_E0_PHY_BYTE_LANE_0_READ_FIFO_STATUS; \
   3341     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_READ_FIFO_CLEARr) = DDR34_E0_PHY_BYTE_LANE_0_READ_FIFO_CLEAR; \
   3342     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_IDLE_PAD_CONTROLr) = DDR34_E0_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL; \
   3343     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_DRIVE_PAD_CTLr) = DDR34_E0_PHY_BYTE_LANE_0_DRIVE_PAD_CTL; \
   3344     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_RD_EN_DRIVE_PAD_CTLr) = DDR34_E0_PHY_BYTE_LANE_0_RD_EN_DRIVE_PAD_CTL; \
   3345     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_STATIC_PAD_CTLr) = DDR34_E0_PHY_BYTE_LANE_0_STATIC_PAD_CTL; \
   3346     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_WR_PREAMBLE_MODEr) = DDR34_E0_PHY_BYTE_LANE_0_WR_PREAMBLE_MODE; \
   3347     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_ODT_CONTROLr) = DDR34_E0_PHY_BYTE_LANE_0_ODT_CONTROL; \
   3348     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_EDC_DPD_CONTROLr) = DDR34_E0_PHY_BYTE_LANE_0_EDC_DPD_CONTROL; \
   3349     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_EDC_DPD_STATUSr) = DDR34_E0_PHY_BYTE_LANE_0_EDC_DPD_STATUS; \
   3350     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_EDC_DPD_OUT_CONTROLr) = DDR34_E0_PHY_BYTE_LANE_0_EDC_DPD_OUT_CONTROL; \
   3351     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_EDC_DPD_OUT_STATUSr) = DDR34_E0_PHY_BYTE_LANE_0_EDC_DPD_OUT_STATUS; \
   3352     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_EDC_DPD_OUT_STATUS_CLEARr) = DDR34_E0_PHY_BYTE_LANE_0_EDC_DPD_OUT_STATUS_CLEAR; \
   3353     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_EDC_CRC_CONTROLr) = DDR34_E0_PHY_BYTE_LANE_0_EDC_CRC_CONTROL; \
   3354     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_EDC_CRC_STATUSr) = DDR34_E0_PHY_BYTE_LANE_0_EDC_CRC_STATUS; \
   3355     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_EDC_CRC_COUNTr) = DDR34_E0_PHY_BYTE_LANE_0_EDC_CRC_COUNT; \
   3356     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_EDC_CRC_STATUS_CLEARr) = DDR34_E0_PHY_BYTE_LANE_0_EDC_CRC_STATUS_CLEAR; \
   3357     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_BL_SPARE_REGr) = DDR34_E0_PHY_BYTE_LANE_0_BL_SPARE_REG; \
   3358     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_Pr) = DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_P; \
   3359     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_Nr) = DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_N; \
   3360     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0r) = DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0; \
   3361     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1r) = DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1; \
   3362     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2r) = DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2; \
   3363     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3r) = DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3; \
   3364     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4r) = DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4; \
   3365     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5r) = DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5; \
   3366     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6r) = DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6; \
   3367     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7r) = DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7; \
   3368     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DMr) = DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DM; \
   3369     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_EDCr) = DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_EDC; \
   3370     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSPr) = DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSP; \
   3371     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSNr) = DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSN; \
   3372     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0Pr) = DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0P; \
   3373     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0Nr) = DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0N; \
   3374     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1Pr) = DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1P; \
   3375     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1Nr) = DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1N; \
   3376     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2Pr) = DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2P; \
   3377     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2Nr) = DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2N; \
   3378     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3Pr) = DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3P; \
   3379     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3Nr) = DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3N; \
   3380     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4Pr) = DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4P; \
   3381     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4Nr) = DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4N; \
   3382     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5Pr) = DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5P; \
   3383     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5Nr) = DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5N; \
   3384     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6Pr) = DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6P; \
   3385     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6Nr) = DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6N; \
   3386     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7Pr) = DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7P; \
   3387     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7Nr) = DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7N; \
   3388     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMPr) = DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMP; \
   3389     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMNr) = DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMN; \
   3390     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCPr) = DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCP; \
   3391     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCNr) = DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCN; \
   3392     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0r) = DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0; \
   3393     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1r) = DDR34_E0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1; \
   3394     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CLK_CONTROLr) = DDR34_E0_PHY_BYTE_LANE_1_VDL_CLK_CONTROL; \
   3395     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_LDE_CONTROLr) = DDR34_E0_PHY_BYTE_LANE_1_VDL_LDE_CONTROL; \
   3396     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_RD_EN_DLY_CYCr) = DDR34_E0_PHY_BYTE_LANE_1_RD_EN_DLY_CYC; \
   3397     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_WR_CHAN_DLY_CYCr) = DDR34_E0_PHY_BYTE_LANE_1_WR_CHAN_DLY_CYC; \
   3398     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_READ_CONTROLr) = DDR34_E0_PHY_BYTE_LANE_1_READ_CONTROL; \
   3399     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_READ_FIFO_ADDRr) = DDR34_E0_PHY_BYTE_LANE_1_READ_FIFO_ADDR; \
   3400     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_READ_FIFO_DATAr) = DDR34_E0_PHY_BYTE_LANE_1_READ_FIFO_DATA; \
   3401     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_READ_FIFO_DM_DBIr) = DDR34_E0_PHY_BYTE_LANE_1_READ_FIFO_DM_DBI; \
   3402     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_READ_FIFO_STATUSr) = DDR34_E0_PHY_BYTE_LANE_1_READ_FIFO_STATUS; \
   3403     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_READ_FIFO_CLEARr) = DDR34_E0_PHY_BYTE_LANE_1_READ_FIFO_CLEAR; \
   3404     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_IDLE_PAD_CONTROLr) = DDR34_E0_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL; \
   3405     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_DRIVE_PAD_CTLr) = DDR34_E0_PHY_BYTE_LANE_1_DRIVE_PAD_CTL; \
   3406     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_RD_EN_DRIVE_PAD_CTLr) = DDR34_E0_PHY_BYTE_LANE_1_RD_EN_DRIVE_PAD_CTL; \
   3407     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_STATIC_PAD_CTLr) = DDR34_E0_PHY_BYTE_LANE_1_STATIC_PAD_CTL; \
   3408     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_WR_PREAMBLE_MODEr) = DDR34_E0_PHY_BYTE_LANE_1_WR_PREAMBLE_MODE; \
   3409     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_ODT_CONTROLr) = DDR34_E0_PHY_BYTE_LANE_1_ODT_CONTROL; \
   3410     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_EDC_DPD_CONTROLr) = DDR34_E0_PHY_BYTE_LANE_1_EDC_DPD_CONTROL; \
   3411     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_EDC_DPD_STATUSr) = DDR34_E0_PHY_BYTE_LANE_1_EDC_DPD_STATUS; \
   3412     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_EDC_DPD_OUT_CONTROLr) = DDR34_E0_PHY_BYTE_LANE_1_EDC_DPD_OUT_CONTROL; \
   3413     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_EDC_DPD_OUT_STATUSr) = DDR34_E0_PHY_BYTE_LANE_1_EDC_DPD_OUT_STATUS; \
   3414     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_EDC_DPD_OUT_STATUS_CLEARr) = DDR34_E0_PHY_BYTE_LANE_1_EDC_DPD_OUT_STATUS_CLEAR; \
   3415     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_EDC_CRC_CONTROLr) = DDR34_E0_PHY_BYTE_LANE_1_EDC_CRC_CONTROL; \
   3416     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_EDC_CRC_STATUSr) = DDR34_E0_PHY_BYTE_LANE_1_EDC_CRC_STATUS; \
   3417     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_EDC_CRC_COUNTr) = DDR34_E0_PHY_BYTE_LANE_1_EDC_CRC_COUNT; \
   3418     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_EDC_CRC_STATUS_CLEARr) = DDR34_E0_PHY_BYTE_LANE_1_EDC_CRC_STATUS_CLEAR; \
   3419     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_BL_SPARE_REGr) = DDR34_E0_PHY_BYTE_LANE_1_BL_SPARE_REG; \
   3420     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_Pr) = DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_P; \
   3421     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_Nr) = DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_N; \
   3422     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ0r) = DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ0; \
   3423     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ1r) = DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ1; \
   3424     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ2r) = DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ2; \
   3425     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ3r) = DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ3; \
   3426     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ4r) = DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ4; \
   3427     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ5r) = DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ5; \
   3428     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ6r) = DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ6; \
   3429     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ7r) = DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ7; \
   3430     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DMr) = DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DM; \
   3431     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_EDCr) = DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_EDC; \
   3432     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSPr) = DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSP; \
   3433     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSNr) = DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSN; \
   3434     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0Pr) = DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0P; \
   3435     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0Nr) = DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0N; \
   3436     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1Pr) = DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1P; \
   3437     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1Nr) = DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1N; \
   3438     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2Pr) = DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2P; \
   3439     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2Nr) = DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2N; \
   3440     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3Pr) = DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3P; \
   3441     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3Nr) = DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3N; \
   3442     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4Pr) = DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4P; \
   3443     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4Nr) = DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4N; \
   3444     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5Pr) = DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5P; \
   3445     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5Nr) = DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5N; \
   3446     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6Pr) = DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6P; \
   3447     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6Nr) = DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6N; \
   3448     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7Pr) = DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7P; \
   3449     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7Nr) = DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7N; \
   3450     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMPr) = DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMP; \
   3451     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMNr) = DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMN; \
   3452     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EDCPr) = DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EDCP; \
   3453     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EDCNr) = DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EDCN; \
   3454     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS0r) = DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS0; \
   3455     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS1r) = DDR34_E0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS1; \
   3456     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CLK_CONTROLr) = DDR34_E0_PHY_BYTE_LANE_2_VDL_CLK_CONTROL; \
   3457     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_LDE_CONTROLr) = DDR34_E0_PHY_BYTE_LANE_2_VDL_LDE_CONTROL; \
   3458     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_RD_EN_DLY_CYCr) = DDR34_E0_PHY_BYTE_LANE_2_RD_EN_DLY_CYC; \
   3459     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_WR_CHAN_DLY_CYCr) = DDR34_E0_PHY_BYTE_LANE_2_WR_CHAN_DLY_CYC; \
   3460     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_READ_CONTROLr) = DDR34_E0_PHY_BYTE_LANE_2_READ_CONTROL; \
   3461     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_READ_FIFO_ADDRr) = DDR34_E0_PHY_BYTE_LANE_2_READ_FIFO_ADDR; \
   3462     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_READ_FIFO_DATAr) = DDR34_E0_PHY_BYTE_LANE_2_READ_FIFO_DATA; \
   3463     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_READ_FIFO_DM_DBIr) = DDR34_E0_PHY_BYTE_LANE_2_READ_FIFO_DM_DBI; \
   3464     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_READ_FIFO_STATUSr) = DDR34_E0_PHY_BYTE_LANE_2_READ_FIFO_STATUS; \
   3465     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_READ_FIFO_CLEARr) = DDR34_E0_PHY_BYTE_LANE_2_READ_FIFO_CLEAR; \
   3466     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_IDLE_PAD_CONTROLr) = DDR34_E0_PHY_BYTE_LANE_2_IDLE_PAD_CONTROL; \
   3467     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_DRIVE_PAD_CTLr) = DDR34_E0_PHY_BYTE_LANE_2_DRIVE_PAD_CTL; \
   3468     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_RD_EN_DRIVE_PAD_CTLr) = DDR34_E0_PHY_BYTE_LANE_2_RD_EN_DRIVE_PAD_CTL; \
   3469     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_STATIC_PAD_CTLr) = DDR34_E0_PHY_BYTE_LANE_2_STATIC_PAD_CTL; \
   3470     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_WR_PREAMBLE_MODEr) = DDR34_E0_PHY_BYTE_LANE_2_WR_PREAMBLE_MODE; \
   3471     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_ODT_CONTROLr) = DDR34_E0_PHY_BYTE_LANE_2_ODT_CONTROL; \
   3472     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_EDC_DPD_CONTROLr) = DDR34_E0_PHY_BYTE_LANE_2_EDC_DPD_CONTROL; \
   3473     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_EDC_DPD_STATUSr) = DDR34_E0_PHY_BYTE_LANE_2_EDC_DPD_STATUS; \
   3474     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_EDC_DPD_OUT_CONTROLr) = DDR34_E0_PHY_BYTE_LANE_2_EDC_DPD_OUT_CONTROL; \
   3475     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_EDC_DPD_OUT_STATUSr) = DDR34_E0_PHY_BYTE_LANE_2_EDC_DPD_OUT_STATUS; \
   3476     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_EDC_DPD_OUT_STATUS_CLEARr) = DDR34_E0_PHY_BYTE_LANE_2_EDC_DPD_OUT_STATUS_CLEAR; \
   3477     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_EDC_CRC_CONTROLr) = DDR34_E0_PHY_BYTE_LANE_2_EDC_CRC_CONTROL; \
   3478     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_EDC_CRC_STATUSr) = DDR34_E0_PHY_BYTE_LANE_2_EDC_CRC_STATUS; \
   3479     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_EDC_CRC_COUNTr) = DDR34_E0_PHY_BYTE_LANE_2_EDC_CRC_COUNT; \
   3480     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_EDC_CRC_STATUS_CLEARr) = DDR34_E0_PHY_BYTE_LANE_2_EDC_CRC_STATUS_CLEAR; \
   3481     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_BL_SPARE_REGr) = DDR34_E0_PHY_BYTE_LANE_2_BL_SPARE_REG; \
   3482     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_Pr) = DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_P; \
   3483     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_Nr) = DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_N; \
   3484     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ0r) = DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ0; \
   3485     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ1r) = DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ1; \
   3486     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ2r) = DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ2; \
   3487     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ3r) = DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ3; \
   3488     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ4r) = DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ4; \
   3489     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ5r) = DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ5; \
   3490     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ6r) = DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ6; \
   3491     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ7r) = DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ7; \
   3492     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DMr) = DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DM; \
   3493     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_EDCr) = DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_EDC; \
   3494     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSPr) = DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSP; \
   3495     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSNr) = DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSN; \
   3496     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0Pr) = DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0P; \
   3497     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0Nr) = DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0N; \
   3498     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1Pr) = DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1P; \
   3499     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1Nr) = DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1N; \
   3500     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2Pr) = DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2P; \
   3501     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2Nr) = DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2N; \
   3502     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3Pr) = DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3P; \
   3503     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3Nr) = DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3N; \
   3504     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4Pr) = DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4P; \
   3505     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4Nr) = DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4N; \
   3506     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5Pr) = DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5P; \
   3507     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5Nr) = DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5N; \
   3508     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6Pr) = DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6P; \
   3509     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6Nr) = DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6N; \
   3510     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7Pr) = DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7P; \
   3511     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7Nr) = DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7N; \
   3512     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMPr) = DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMP; \
   3513     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMNr) = DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMN; \
   3514     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EDCPr) = DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EDCP; \
   3515     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EDCNr) = DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EDCN; \
   3516     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS0r) = DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS0; \
   3517     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS1r) = DDR34_E0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS1; \
   3518     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CLK_CONTROLr) = DDR34_E0_PHY_BYTE_LANE_3_VDL_CLK_CONTROL; \
   3519     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_LDE_CONTROLr) = DDR34_E0_PHY_BYTE_LANE_3_VDL_LDE_CONTROL; \
   3520     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_RD_EN_DLY_CYCr) = DDR34_E0_PHY_BYTE_LANE_3_RD_EN_DLY_CYC; \
   3521     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_WR_CHAN_DLY_CYCr) = DDR34_E0_PHY_BYTE_LANE_3_WR_CHAN_DLY_CYC; \
   3522     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_READ_CONTROLr) = DDR34_E0_PHY_BYTE_LANE_3_READ_CONTROL; \
   3523     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_READ_FIFO_ADDRr) = DDR34_E0_PHY_BYTE_LANE_3_READ_FIFO_ADDR; \
   3524     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_READ_FIFO_DATAr) = DDR34_E0_PHY_BYTE_LANE_3_READ_FIFO_DATA; \
   3525     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_READ_FIFO_DM_DBIr) = DDR34_E0_PHY_BYTE_LANE_3_READ_FIFO_DM_DBI; \
   3526     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_READ_FIFO_STATUSr) = DDR34_E0_PHY_BYTE_LANE_3_READ_FIFO_STATUS; \
   3527     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_READ_FIFO_CLEARr) = DDR34_E0_PHY_BYTE_LANE_3_READ_FIFO_CLEAR; \
   3528     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_IDLE_PAD_CONTROLr) = DDR34_E0_PHY_BYTE_LANE_3_IDLE_PAD_CONTROL; \
   3529     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_DRIVE_PAD_CTLr) = DDR34_E0_PHY_BYTE_LANE_3_DRIVE_PAD_CTL; \
   3530     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_RD_EN_DRIVE_PAD_CTLr) = DDR34_E0_PHY_BYTE_LANE_3_RD_EN_DRIVE_PAD_CTL; \
   3531     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_STATIC_PAD_CTLr) = DDR34_E0_PHY_BYTE_LANE_3_STATIC_PAD_CTL; \
   3532     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_WR_PREAMBLE_MODEr) = DDR34_E0_PHY_BYTE_LANE_3_WR_PREAMBLE_MODE; \
   3533     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_ODT_CONTROLr) = DDR34_E0_PHY_BYTE_LANE_3_ODT_CONTROL; \
   3534     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_EDC_DPD_CONTROLr) = DDR34_E0_PHY_BYTE_LANE_3_EDC_DPD_CONTROL; \
   3535     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_EDC_DPD_STATUSr) = DDR34_E0_PHY_BYTE_LANE_3_EDC_DPD_STATUS; \
   3536     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_EDC_DPD_OUT_CONTROLr) = DDR34_E0_PHY_BYTE_LANE_3_EDC_DPD_OUT_CONTROL; \
   3537     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_EDC_DPD_OUT_STATUSr) = DDR34_E0_PHY_BYTE_LANE_3_EDC_DPD_OUT_STATUS; \
   3538     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_EDC_DPD_OUT_STATUS_CLEARr) = DDR34_E0_PHY_BYTE_LANE_3_EDC_DPD_OUT_STATUS_CLEAR; \
   3539     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_EDC_CRC_CONTROLr) = DDR34_E0_PHY_BYTE_LANE_3_EDC_CRC_CONTROL; \
   3540     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_EDC_CRC_STATUSr) = DDR34_E0_PHY_BYTE_LANE_3_EDC_CRC_STATUS; \
   3541     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_EDC_CRC_COUNTr) = DDR34_E0_PHY_BYTE_LANE_3_EDC_CRC_COUNT; \
   3542     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_EDC_CRC_STATUS_CLEARr) = DDR34_E0_PHY_BYTE_LANE_3_EDC_CRC_STATUS_CLEAR; \
   3543     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_BL_SPARE_REGr) = DDR34_E0_PHY_BYTE_LANE_3_BL_SPARE_REG; \
   3544     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_IDLE_PAD_ENABLE0r) = DDR34_E0_PHY_CONTROL_REGS_IDLE_PAD_ENABLE0; \
   3545 }
   3546 
   3547 
   3548 /**********************************************/
   3549 #define INIT_DDR34_F0_PHY_REGS_TABLE()   { \
   3550     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_REVISIONr) = DDR34_F0_PHY_CONTROL_REGS_REVISION; \
   3551     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_PLL_STATUSr) = DDR34_F0_PHY_CONTROL_REGS_PLL_STATUS; \
   3552     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_PLL_CONFIGr) = DDR34_F0_PHY_CONTROL_REGS_PLL_CONFIG; \
   3553     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_PLL_CONTROL1r) = DDR34_F0_PHY_CONTROL_REGS_PLL_CONTROL1; \
   3554     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_PLL_CONTROL2r) = DDR34_F0_PHY_CONTROL_REGS_PLL_CONTROL2; \
   3555     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_PLL_CONTROL3r) = DDR34_F0_PHY_CONTROL_REGS_PLL_CONTROL3; \
   3556     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_PLL_DIVIDERSr) = DDR34_F0_PHY_CONTROL_REGS_PLL_DIVIDERS; \
   3557     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_PLL_FRAC_DIVIDERr) = DDR34_F0_PHY_CONTROL_REGS_PLL_FRAC_DIVIDER; \
   3558     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_PLL_SS_CONTROLr) = DDR34_F0_PHY_CONTROL_REGS_PLL_SS_CONTROL; \
   3559     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_PLL_SS_LIMITr) = DDR34_F0_PHY_CONTROL_REGS_PLL_SS_LIMIT; \
   3560     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_AUX_CONTROLr) = DDR34_F0_PHY_CONTROL_REGS_AUX_CONTROL; \
   3561     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_IDLE_PAD_CONTROLr) = DDR34_F0_PHY_CONTROL_REGS_IDLE_PAD_CONTROL; \
   3562     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_IDLE_PAD_ENABLE0r) = DDR34_F0_PHY_CONTROL_REGS_IDLE_PAD_ENABLE0; \
   3563     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_IDLE_PAD_ENABLE1r) = DDR34_F0_PHY_CONTROL_REGS_IDLE_PAD_ENABLE1; \
   3564     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_DRIVE_PAD_CTLr) = DDR34_F0_PHY_CONTROL_REGS_DRIVE_PAD_CTL; \
   3565     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_DRIVE_PAD_CTL_2Tr) = DDR34_F0_PHY_CONTROL_REGS_DRIVE_PAD_CTL_2T; \
   3566     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_STATIC_PAD_CTLr) = DDR34_F0_PHY_CONTROL_REGS_STATIC_PAD_CTL; \
   3567     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_DRAM_CONFIGr) = DDR34_F0_PHY_CONTROL_REGS_DRAM_CONFIG; \
   3568     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_DRAM_TIMING1r) = DDR34_F0_PHY_CONTROL_REGS_DRAM_TIMING1; \
   3569     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_DRAM_TIMING2r) = DDR34_F0_PHY_CONTROL_REGS_DRAM_TIMING2; \
   3570     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_DRAM_TIMING3r) = DDR34_F0_PHY_CONTROL_REGS_DRAM_TIMING3; \
   3571     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_DRAM_TIMING4r) = DDR34_F0_PHY_CONTROL_REGS_DRAM_TIMING4; \
   3572     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CALIBRATEr) = DDR34_F0_PHY_CONTROL_REGS_VDL_CALIBRATE; \
   3573     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CALIB_STATUS1r) = DDR34_F0_PHY_CONTROL_REGS_VDL_CALIB_STATUS1; \
   3574     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CALIB_STATUS2r) = DDR34_F0_PHY_CONTROL_REGS_VDL_CALIB_STATUS2; \
   3575     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_MONITOR_CONTROLr) = DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_CONTROL; \
   3576     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_MONITOR_REFr) = DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_REF; \
   3577     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_MONITOR_STATUSr) = DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_STATUS; \
   3578     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDEr) = DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDE; \
   3579     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_MONITOR_OUT_CONTROLr) = DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_OUT_CONTROL; \
   3580     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUSr) = DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS; \
   3581     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_CLEARr) = DDR34_F0_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_CLEAR; \
   3582     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD00r) = DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD00; \
   3583     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD01r) = DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD01; \
   3584     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD02r) = DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD02; \
   3585     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD03r) = DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD03; \
   3586     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD04r) = DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD04; \
   3587     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD05r) = DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD05; \
   3588     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD06r) = DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD06; \
   3589     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD07r) = DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD07; \
   3590     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD08r) = DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD08; \
   3591     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD09r) = DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD09; \
   3592     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD10r) = DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD10; \
   3593     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD11r) = DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD11; \
   3594     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD12r) = DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD12; \
   3595     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD13r) = DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD13; \
   3596     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD14r) = DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD14; \
   3597     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD15r) = DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AD15; \
   3598     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_BA0r) = DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_BA0; \
   3599     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_BA1r) = DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_BA1; \
   3600     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_BA2r) = DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_BA2; \
   3601     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AUX0r) = DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AUX0; \
   3602     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AUX1r) = DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AUX1; \
   3603     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AUX2r) = DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_AUX2; \
   3604     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_CS0r) = DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_CS0; \
   3605     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_CS1r) = DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_CS1; \
   3606     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_PARr) = DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_PAR; \
   3607     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_RAS_Nr) = DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_RAS_N; \
   3608     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_CAS_Nr) = DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_CAS_N; \
   3609     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_CKEr) = DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_CKE; \
   3610     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_RST_Nr) = DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_RST_N; \
   3611     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_ODTr) = DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_ODT; \
   3612     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_WE_Nr) = DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_WE_N; \
   3613     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CKr) = DDR34_F0_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK; \
   3614     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CLK_CONTROLr) = DDR34_F0_PHY_CONTROL_REGS_VDL_CLK_CONTROL; \
   3615     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_LDE_CONTROLr) = DDR34_F0_PHY_CONTROL_REGS_VDL_LDE_CONTROL; \
   3616     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_CMD_CYC_DLYr) = DDR34_F0_PHY_CONTROL_REGS_CMD_CYC_DLY; \
   3617     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_UPDATE_VDLr) = DDR34_F0_PHY_CONTROL_REGS_UPDATE_VDL; \
   3618     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1r) = DDR34_F0_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1; \
   3619     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2r) = DDR34_F0_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2; \
   3620     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_COMMAND_REG1r) = DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG1; \
   3621     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_COMMAND_AUX_REG1r) = DDR34_F0_PHY_CONTROL_REGS_COMMAND_AUX_REG1; \
   3622     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_COMMAND_REG2r) = DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG2; \
   3623     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_COMMAND_AUX_REG2r) = DDR34_F0_PHY_CONTROL_REGS_COMMAND_AUX_REG2; \
   3624     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_COMMAND_REG3r) = DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG3; \
   3625     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_COMMAND_AUX_REG3r) = DDR34_F0_PHY_CONTROL_REGS_COMMAND_AUX_REG3; \
   3626     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_COMMAND_REG4r) = DDR34_F0_PHY_CONTROL_REGS_COMMAND_REG4; \
   3627     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_COMMAND_AUX_REG4r) = DDR34_F0_PHY_CONTROL_REGS_COMMAND_AUX_REG4; \
   3628     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_MODE_REG0r) = DDR34_F0_PHY_CONTROL_REGS_MODE_REG0; \
   3629     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_MODE_REG1r) = DDR34_F0_PHY_CONTROL_REGS_MODE_REG1; \
   3630     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_MODE_REG2r) = DDR34_F0_PHY_CONTROL_REGS_MODE_REG2; \
   3631     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_MODE_REG3r) = DDR34_F0_PHY_CONTROL_REGS_MODE_REG3; \
   3632     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_MODE_REG4r) = DDR34_F0_PHY_CONTROL_REGS_MODE_REG4; \
   3633     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_MODE_REG5r) = DDR34_F0_PHY_CONTROL_REGS_MODE_REG5; \
   3634     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_MODE_REG6r) = DDR34_F0_PHY_CONTROL_REGS_MODE_REG6; \
   3635     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_MODE_REG7r) = DDR34_F0_PHY_CONTROL_REGS_MODE_REG7; \
   3636     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_MODE_REG8r) = DDR34_F0_PHY_CONTROL_REGS_MODE_REG8; \
   3637     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_MODE_REG15r) = DDR34_F0_PHY_CONTROL_REGS_MODE_REG15; \
   3638     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_MODE_REG63r) = DDR34_F0_PHY_CONTROL_REGS_MODE_REG63; \
   3639     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_ALERT_CLEARr) = DDR34_F0_PHY_CONTROL_REGS_ALERT_CLEAR; \
   3640     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_ALERT_STATUSr) = DDR34_F0_PHY_CONTROL_REGS_ALERT_STATUS; \
   3641     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_ALERT_DFIr) = DDR34_F0_PHY_CONTROL_REGS_ALERT_DFI; \
   3642     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_CA_PLAYBACK_CONTROLr) = DDR34_F0_PHY_CONTROL_REGS_CA_PLAYBACK_CONTROL; \
   3643     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS0r) = DDR34_F0_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS0; \
   3644     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS1r) = DDR34_F0_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS1; \
   3645     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_WRITE_LEVELING_CONTROLr) = DDR34_F0_PHY_CONTROL_REGS_WRITE_LEVELING_CONTROL; \
   3646     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_WRITE_LEVELING_STATUSr) = DDR34_F0_PHY_CONTROL_REGS_WRITE_LEVELING_STATUS; \
   3647     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_READ_ENABLE_CONTROLr) = DDR34_F0_PHY_CONTROL_REGS_READ_ENABLE_CONTROL; \
   3648     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_READ_ENABLE_STATUSr) = DDR34_F0_PHY_CONTROL_REGS_READ_ENABLE_STATUS; \
   3649     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROLr) = DDR34_F0_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL; \
   3650     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUSr) = DDR34_F0_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS; \
   3651     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VIRTUAL_VTT_CONNECTIONSr) = DDR34_F0_PHY_CONTROL_REGS_VIRTUAL_VTT_CONNECTIONS; \
   3652     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VIRTUAL_VTT_OVERRIDEr) = DDR34_F0_PHY_CONTROL_REGS_VIRTUAL_VTT_OVERRIDE; \
   3653     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VREF_DAC_CONTROLr) = DDR34_F0_PHY_CONTROL_REGS_VREF_DAC_CONTROL; \
   3654     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_PHYBIST_CNTRLr) = DDR34_F0_PHY_CONTROL_REGS_PHYBIST_CNTRL; \
   3655     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_PHYBIST_SEEDr) = DDR34_F0_PHY_CONTROL_REGS_PHYBIST_SEED; \
   3656     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_PHYBIST_CA_MASKr) = DDR34_F0_PHY_CONTROL_REGS_PHYBIST_CA_MASK; \
   3657     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_PHYBIST_DQ_MASK1r) = DDR34_F0_PHY_CONTROL_REGS_PHYBIST_DQ_MASK1; \
   3658     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_PHYBIST_DQ_MASK2r) = DDR34_F0_PHY_CONTROL_REGS_PHYBIST_DQ_MASK2; \
   3659     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_PHYBIST_STATUSr) = DDR34_F0_PHY_CONTROL_REGS_PHYBIST_STATUS; \
   3660     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_PHYBIST_CTL_STATUSr) = DDR34_F0_PHY_CONTROL_REGS_PHYBIST_CTL_STATUS; \
   3661     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_PHYBIST_BL0_STATUSr) = DDR34_F0_PHY_CONTROL_REGS_PHYBIST_BL0_STATUS; \
   3662     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_PHYBIST_BL1_STATUSr) = DDR34_F0_PHY_CONTROL_REGS_PHYBIST_BL1_STATUS; \
   3663     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_PHYBIST_BL2_STATUSr) = DDR34_F0_PHY_CONTROL_REGS_PHYBIST_BL2_STATUS; \
   3664     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_PHYBIST_BL3_STATUSr) = DDR34_F0_PHY_CONTROL_REGS_PHYBIST_BL3_STATUS; \
   3665     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_PHYBIST_BL4_STATUSr) = DDR34_F0_PHY_CONTROL_REGS_PHYBIST_BL4_STATUS; \
   3666     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_STANDBY_CONTROLr) = DDR34_F0_PHY_CONTROL_REGS_STANDBY_CONTROL; \
   3667     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLEr) = DDR34_F0_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE; \
   3668     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_DEBUG_MUX_CONTROLr) = DDR34_F0_PHY_CONTROL_REGS_DEBUG_MUX_CONTROL; \
   3669     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_DFI_CNTRLr) = DDR34_F0_PHY_CONTROL_REGS_DFI_CNTRL; \
   3670     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_WRITE_ODT_CNTRLr) = DDR34_F0_PHY_CONTROL_REGS_WRITE_ODT_CNTRL; \
   3671     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_ABI_PAR_CNTRLr) = DDR34_F0_PHY_CONTROL_REGS_ABI_PAR_CNTRL; \
   3672     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_ZQ_CALr) = DDR34_F0_PHY_CONTROL_REGS_ZQ_CAL; \
   3673     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_ZQ_CAL2r) = DDR34_F0_PHY_CONTROL_REGS_ZQ_CAL2; \
   3674     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_RO_PROC_MON_CTLr) = DDR34_F0_PHY_CONTROL_REGS_RO_PROC_MON_CTL; \
   3675     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_RO_PROC_MON_STATUSr) = DDR34_F0_PHY_CONTROL_REGS_RO_PROC_MON_STATUS; \
   3676     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_CK_DRIVE_PAD_CTLr) = DDR34_F0_PHY_CONTROL_REGS_CK_DRIVE_PAD_CTL; \
   3677     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_BYTE_LANE_ALIGN_MASKSr) = DDR34_F0_PHY_CONTROL_REGS_BYTE_LANE_ALIGN_MASKS; \
   3678     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_CLOCK_IDLEr) = DDR34_F0_PHY_CONTROL_REGS_CLOCK_IDLE; \
   3679     DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_AC_SPARE_REGr) = DDR34_F0_PHY_CONTROL_REGS_AC_SPARE_REG; \
   3680     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQSr) = DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS; \
   3681     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0r) = DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0; \
   3682     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1r) = DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1; \
   3683     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2r) = DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2; \
   3684     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3r) = DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3; \
   3685     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4r) = DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4; \
   3686     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5r) = DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5; \
   3687     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6r) = DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6; \
   3688     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7r) = DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7; \
   3689     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DMr) = DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DM; \
   3690     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_ALERTr) = DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_WR_ALERT; \
   3691     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSPr) = DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSP; \
   3692     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSNr) = DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSN; \
   3693     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0Pr) = DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0P; \
   3694     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0Nr) = DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0N; \
   3695     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1Pr) = DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1P; \
   3696     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1Nr) = DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1N; \
   3697     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2Pr) = DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2P; \
   3698     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2Nr) = DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2N; \
   3699     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3Pr) = DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3P; \
   3700     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3Nr) = DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3N; \
   3701     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4Pr) = DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4P; \
   3702     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4Nr) = DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4N; \
   3703     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5Pr) = DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5P; \
   3704     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5Nr) = DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5N; \
   3705     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6Pr) = DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6P; \
   3706     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6Nr) = DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6N; \
   3707     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7Pr) = DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7P; \
   3708     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7Nr) = DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7N; \
   3709     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMPr) = DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMP; \
   3710     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMNr) = DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMN; \
   3711     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0r) = DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0; \
   3712     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1r) = DDR34_F0_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1; \
   3713     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CLK_CONTROLr) = DDR34_F0_PHY_BYTE_LANE_0_VDL_CLK_CONTROL; \
   3714     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_LDE_CONTROLr) = DDR34_F0_PHY_BYTE_LANE_0_VDL_LDE_CONTROL; \
   3715     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_RD_EN_DLY_CYCr) = DDR34_F0_PHY_BYTE_LANE_0_RD_EN_DLY_CYC; \
   3716     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_WR_CHAN_DLY_CYCr) = DDR34_F0_PHY_BYTE_LANE_0_WR_CHAN_DLY_CYC; \
   3717     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_READ_CONTROLr) = DDR34_F0_PHY_BYTE_LANE_0_READ_CONTROL; \
   3718     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_READ_FIFO_ADDRr) = DDR34_F0_PHY_BYTE_LANE_0_READ_FIFO_ADDR; \
   3719     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_READ_FIFO_DATAr) = DDR34_F0_PHY_BYTE_LANE_0_READ_FIFO_DATA; \
   3720     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_READ_FIFO_DM_DBIr) = DDR34_F0_PHY_BYTE_LANE_0_READ_FIFO_DM_DBI; \
   3721     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_READ_FIFO_STATUSr) = DDR34_F0_PHY_BYTE_LANE_0_READ_FIFO_STATUS; \
   3722     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_READ_FIFO_CLEARr) = DDR34_F0_PHY_BYTE_LANE_0_READ_FIFO_CLEAR; \
   3723     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_IDLE_PAD_CONTROLr) = DDR34_F0_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL; \
   3724     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_DRIVE_PAD_CTLr) = DDR34_F0_PHY_BYTE_LANE_0_DRIVE_PAD_CTL; \
   3725     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_DQSP_DRIVE_PAD_CTLr) = DDR34_F0_PHY_BYTE_LANE_0_DQSP_DRIVE_PAD_CTL; \
   3726     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_DQSN_DRIVE_PAD_CTLr) = DDR34_F0_PHY_BYTE_LANE_0_DQSN_DRIVE_PAD_CTL; \
   3727     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_ALERT_DRIVE_PAD_CTLr) = DDR34_F0_PHY_BYTE_LANE_0_ALERT_DRIVE_PAD_CTL; \
   3728     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_RD_EN_DRIVE_PAD_CTLr) = DDR34_F0_PHY_BYTE_LANE_0_RD_EN_DRIVE_PAD_CTL; \
   3729     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_STATIC_PAD_CTLr) = DDR34_F0_PHY_BYTE_LANE_0_STATIC_PAD_CTL; \
   3730     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_WR_PREAMBLE_MODEr) = DDR34_F0_PHY_BYTE_LANE_0_WR_PREAMBLE_MODE; \
   3731     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_ODT_CONTROLr) = DDR34_F0_PHY_BYTE_LANE_0_ODT_CONTROL; \
   3732     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_CLOCK_ENABLEr) = DDR34_F0_PHY_BYTE_LANE_0_CLOCK_ENABLE; \
   3733     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_CLOCK_IDLEr) = DDR34_F0_PHY_BYTE_LANE_0_CLOCK_IDLE; \
   3734     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_BL_SPARE_REGr) = DDR34_F0_PHY_BYTE_LANE_0_BL_SPARE_REG; \
   3735     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQSr) = DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS; \
   3736     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0r) = DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0; \
   3737     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1r) = DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1; \
   3738     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2r) = DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2; \
   3739     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3r) = DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3; \
   3740     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4r) = DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4; \
   3741     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5r) = DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5; \
   3742     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6r) = DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6; \
   3743     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7r) = DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7; \
   3744     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DMr) = DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DM; \
   3745     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_ALERTr) = DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_WR_ALERT; \
   3746     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSPr) = DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSP; \
   3747     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSNr) = DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSN; \
   3748     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0Pr) = DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0P; \
   3749     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0Nr) = DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0N; \
   3750     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1Pr) = DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1P; \
   3751     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1Nr) = DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1N; \
   3752     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2Pr) = DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2P; \
   3753     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2Nr) = DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2N; \
   3754     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3Pr) = DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3P; \
   3755     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3Nr) = DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3N; \
   3756     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4Pr) = DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4P; \
   3757     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4Nr) = DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4N; \
   3758     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5Pr) = DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5P; \
   3759     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5Nr) = DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5N; \
   3760     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6Pr) = DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6P; \
   3761     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6Nr) = DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6N; \
   3762     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7Pr) = DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7P; \
   3763     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7Nr) = DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7N; \
   3764     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMPr) = DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMP; \
   3765     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMNr) = DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMN; \
   3766     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0r) = DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0; \
   3767     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1r) = DDR34_F0_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1; \
   3768     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CLK_CONTROLr) = DDR34_F0_PHY_BYTE_LANE_1_VDL_CLK_CONTROL; \
   3769     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_LDE_CONTROLr) = DDR34_F0_PHY_BYTE_LANE_1_VDL_LDE_CONTROL; \
   3770     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_RD_EN_DLY_CYCr) = DDR34_F0_PHY_BYTE_LANE_1_RD_EN_DLY_CYC; \
   3771     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_WR_CHAN_DLY_CYCr) = DDR34_F0_PHY_BYTE_LANE_1_WR_CHAN_DLY_CYC; \
   3772     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_READ_CONTROLr) = DDR34_F0_PHY_BYTE_LANE_1_READ_CONTROL; \
   3773     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_READ_FIFO_ADDRr) = DDR34_F0_PHY_BYTE_LANE_1_READ_FIFO_ADDR; \
   3774     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_READ_FIFO_DATAr) = DDR34_F0_PHY_BYTE_LANE_1_READ_FIFO_DATA; \
   3775     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_READ_FIFO_DM_DBIr) = DDR34_F0_PHY_BYTE_LANE_1_READ_FIFO_DM_DBI; \
   3776     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_READ_FIFO_STATUSr) = DDR34_F0_PHY_BYTE_LANE_1_READ_FIFO_STATUS; \
   3777     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_READ_FIFO_CLEARr) = DDR34_F0_PHY_BYTE_LANE_1_READ_FIFO_CLEAR; \
   3778     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_IDLE_PAD_CONTROLr) = DDR34_F0_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL; \
   3779     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_DRIVE_PAD_CTLr) = DDR34_F0_PHY_BYTE_LANE_1_DRIVE_PAD_CTL; \
   3780     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_DQSP_DRIVE_PAD_CTLr) = DDR34_F0_PHY_BYTE_LANE_1_DQSP_DRIVE_PAD_CTL; \
   3781     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_DQSN_DRIVE_PAD_CTLr) = DDR34_F0_PHY_BYTE_LANE_1_DQSN_DRIVE_PAD_CTL; \
   3782     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_ALERT_DRIVE_PAD_CTLr) = DDR34_F0_PHY_BYTE_LANE_1_ALERT_DRIVE_PAD_CTL; \
   3783     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_RD_EN_DRIVE_PAD_CTLr) = DDR34_F0_PHY_BYTE_LANE_1_RD_EN_DRIVE_PAD_CTL; \
   3784     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_STATIC_PAD_CTLr) = DDR34_F0_PHY_BYTE_LANE_1_STATIC_PAD_CTL; \
   3785     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_WR_PREAMBLE_MODEr) = DDR34_F0_PHY_BYTE_LANE_1_WR_PREAMBLE_MODE; \
   3786     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_ODT_CONTROLr) = DDR34_F0_PHY_BYTE_LANE_1_ODT_CONTROL; \
   3787     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_CLOCK_ENABLEr) = DDR34_F0_PHY_BYTE_LANE_1_CLOCK_ENABLE; \
   3788     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_CLOCK_IDLEr) = DDR34_F0_PHY_BYTE_LANE_1_CLOCK_IDLE; \
   3789     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_BL_SPARE_REGr) = DDR34_F0_PHY_BYTE_LANE_1_BL_SPARE_REG; \
   3790     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQSr) = DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS; \
   3791     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ0r) = DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ0; \
   3792     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ1r) = DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ1; \
   3793     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ2r) = DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ2; \
   3794     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ3r) = DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ3; \
   3795     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ4r) = DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ4; \
   3796     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ5r) = DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ5; \
   3797     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ6r) = DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ6; \
   3798     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ7r) = DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ7; \
   3799     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DMr) = DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DM; \
   3800     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_ALERTr) = DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_WR_ALERT; \
   3801     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSPr) = DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSP; \
   3802     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSNr) = DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSN; \
   3803     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0Pr) = DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0P; \
   3804     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0Nr) = DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0N; \
   3805     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1Pr) = DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1P; \
   3806     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1Nr) = DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1N; \
   3807     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2Pr) = DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2P; \
   3808     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2Nr) = DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2N; \
   3809     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3Pr) = DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3P; \
   3810     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3Nr) = DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3N; \
   3811     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4Pr) = DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4P; \
   3812     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4Nr) = DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4N; \
   3813     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5Pr) = DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5P; \
   3814     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5Nr) = DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5N; \
   3815     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6Pr) = DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6P; \
   3816     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6Nr) = DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6N; \
   3817     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7Pr) = DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7P; \
   3818     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7Nr) = DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7N; \
   3819     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMPr) = DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMP; \
   3820     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMNr) = DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMN; \
   3821     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS0r) = DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS0; \
   3822     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS1r) = DDR34_F0_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS1; \
   3823     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CLK_CONTROLr) = DDR34_F0_PHY_BYTE_LANE_2_VDL_CLK_CONTROL; \
   3824     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_LDE_CONTROLr) = DDR34_F0_PHY_BYTE_LANE_2_VDL_LDE_CONTROL; \
   3825     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_RD_EN_DLY_CYCr) = DDR34_F0_PHY_BYTE_LANE_2_RD_EN_DLY_CYC; \
   3826     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_WR_CHAN_DLY_CYCr) = DDR34_F0_PHY_BYTE_LANE_2_WR_CHAN_DLY_CYC; \
   3827     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_READ_CONTROLr) = DDR34_F0_PHY_BYTE_LANE_2_READ_CONTROL; \
   3828     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_READ_FIFO_ADDRr) = DDR34_F0_PHY_BYTE_LANE_2_READ_FIFO_ADDR; \
   3829     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_READ_FIFO_DATAr) = DDR34_F0_PHY_BYTE_LANE_2_READ_FIFO_DATA; \
   3830     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_READ_FIFO_DM_DBIr) = DDR34_F0_PHY_BYTE_LANE_2_READ_FIFO_DM_DBI; \
   3831     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_READ_FIFO_STATUSr) = DDR34_F0_PHY_BYTE_LANE_2_READ_FIFO_STATUS; \
   3832     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_READ_FIFO_CLEARr) = DDR34_F0_PHY_BYTE_LANE_2_READ_FIFO_CLEAR; \
   3833     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_IDLE_PAD_CONTROLr) = DDR34_F0_PHY_BYTE_LANE_2_IDLE_PAD_CONTROL; \
   3834     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_DRIVE_PAD_CTLr) = DDR34_F0_PHY_BYTE_LANE_2_DRIVE_PAD_CTL; \
   3835     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_DQSP_DRIVE_PAD_CTLr) = DDR34_F0_PHY_BYTE_LANE_2_DQSP_DRIVE_PAD_CTL; \
   3836     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_DQSN_DRIVE_PAD_CTLr) = DDR34_F0_PHY_BYTE_LANE_2_DQSN_DRIVE_PAD_CTL; \
   3837     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_ALERT_DRIVE_PAD_CTLr) = DDR34_F0_PHY_BYTE_LANE_2_ALERT_DRIVE_PAD_CTL; \
   3838     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_RD_EN_DRIVE_PAD_CTLr) = DDR34_F0_PHY_BYTE_LANE_2_RD_EN_DRIVE_PAD_CTL; \
   3839     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_STATIC_PAD_CTLr) = DDR34_F0_PHY_BYTE_LANE_2_STATIC_PAD_CTL; \
   3840     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_WR_PREAMBLE_MODEr) = DDR34_F0_PHY_BYTE_LANE_2_WR_PREAMBLE_MODE; \
   3841     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_ODT_CONTROLr) = DDR34_F0_PHY_BYTE_LANE_2_ODT_CONTROL; \
   3842     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_CLOCK_ENABLEr) = DDR34_F0_PHY_BYTE_LANE_2_CLOCK_ENABLE; \
   3843     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_CLOCK_IDLEr) = DDR34_F0_PHY_BYTE_LANE_2_CLOCK_IDLE; \
   3844     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_BL_SPARE_REGr) = DDR34_F0_PHY_BYTE_LANE_2_BL_SPARE_REG; \
   3845     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQSr) = DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS; \
   3846     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ0r) = DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ0; \
   3847     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ1r) = DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ1; \
   3848     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ2r) = DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ2; \
   3849     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ3r) = DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ3; \
   3850     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ4r) = DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ4; \
   3851     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ5r) = DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ5; \
   3852     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ6r) = DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ6; \
   3853     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ7r) = DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ7; \
   3854     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DMr) = DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DM; \
   3855     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_ALERTr) = DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_WR_ALERT; \
   3856     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSPr) = DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSP; \
   3857     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSNr) = DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSN; \
   3858     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0Pr) = DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0P; \
   3859     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0Nr) = DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0N; \
   3860     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1Pr) = DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1P; \
   3861     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1Nr) = DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1N; \
   3862     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2Pr) = DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2P; \
   3863     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2Nr) = DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2N; \
   3864     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3Pr) = DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3P; \
   3865     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3Nr) = DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3N; \
   3866     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4Pr) = DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4P; \
   3867     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4Nr) = DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4N; \
   3868     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5Pr) = DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5P; \
   3869     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5Nr) = DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5N; \
   3870     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6Pr) = DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6P; \
   3871     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6Nr) = DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6N; \
   3872     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7Pr) = DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7P; \
   3873     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7Nr) = DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7N; \
   3874     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMPr) = DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMP; \
   3875     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMNr) = DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMN; \
   3876     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS0r) = DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS0; \
   3877     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS1r) = DDR34_F0_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS1; \
   3878     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CLK_CONTROLr) = DDR34_F0_PHY_BYTE_LANE_3_VDL_CLK_CONTROL; \
   3879     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_LDE_CONTROLr) = DDR34_F0_PHY_BYTE_LANE_3_VDL_LDE_CONTROL; \
   3880     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_RD_EN_DLY_CYCr) = DDR34_F0_PHY_BYTE_LANE_3_RD_EN_DLY_CYC; \
   3881     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_WR_CHAN_DLY_CYCr) = DDR34_F0_PHY_BYTE_LANE_3_WR_CHAN_DLY_CYC; \
   3882     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_READ_CONTROLr) = DDR34_F0_PHY_BYTE_LANE_3_READ_CONTROL; \
   3883     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_READ_FIFO_ADDRr) = DDR34_F0_PHY_BYTE_LANE_3_READ_FIFO_ADDR; \
   3884     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_READ_FIFO_DATAr) = DDR34_F0_PHY_BYTE_LANE_3_READ_FIFO_DATA; \
   3885     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_READ_FIFO_DM_DBIr) = DDR34_F0_PHY_BYTE_LANE_3_READ_FIFO_DM_DBI; \
   3886     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_READ_FIFO_STATUSr) = DDR34_F0_PHY_BYTE_LANE_3_READ_FIFO_STATUS; \
   3887     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_READ_FIFO_CLEARr) = DDR34_F0_PHY_BYTE_LANE_3_READ_FIFO_CLEAR; \
   3888     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_IDLE_PAD_CONTROLr) = DDR34_F0_PHY_BYTE_LANE_3_IDLE_PAD_CONTROL; \
   3889     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_DRIVE_PAD_CTLr) = DDR34_F0_PHY_BYTE_LANE_3_DRIVE_PAD_CTL; \
   3890     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_DQSP_DRIVE_PAD_CTLr) = DDR34_F0_PHY_BYTE_LANE_3_DQSP_DRIVE_PAD_CTL; \
   3891     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_DQSN_DRIVE_PAD_CTLr) = DDR34_F0_PHY_BYTE_LANE_3_DQSN_DRIVE_PAD_CTL; \
   3892     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_ALERT_DRIVE_PAD_CTLr) = DDR34_F0_PHY_BYTE_LANE_3_ALERT_DRIVE_PAD_CTL; \
   3893     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_RD_EN_DRIVE_PAD_CTLr) = DDR34_F0_PHY_BYTE_LANE_3_RD_EN_DRIVE_PAD_CTL; \
   3894     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_STATIC_PAD_CTLr) = DDR34_F0_PHY_BYTE_LANE_3_STATIC_PAD_CTL; \
   3895     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_WR_PREAMBLE_MODEr) = DDR34_F0_PHY_BYTE_LANE_3_WR_PREAMBLE_MODE; \
   3896     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_ODT_CONTROLr) = DDR34_F0_PHY_BYTE_LANE_3_ODT_CONTROL; \
   3897     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_CLOCK_ENABLEr) = DDR34_F0_PHY_BYTE_LANE_3_CLOCK_ENABLE; \
   3898     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_CLOCK_IDLEr) = DDR34_F0_PHY_BYTE_LANE_3_CLOCK_IDLE; \
   3899     DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_BL_SPARE_REGr) = DDR34_F0_PHY_BYTE_LANE_3_BL_SPARE_REG; \
   3900 }
   3901 
   3902 /**************************************************************
   3903  */
   3904 #define INIT_DDR34_SIGNE_FIELD(v, r, f) \
   3905         DDR34_PHY_FIELDS_TABLE(DDR34_##r##r_##f, 0) = DDR34_##v##_##r##_##f##_MASK; \
   3906         DDR34_PHY_FIELDS_TABLE(DDR34_##r##r_##f, 1) = DDR34_##v##_##r##_##f##_ALIGN; \
   3907         DDR34_PHY_FIELDS_TABLE(DDR34_##r##r_##f, 2) = DDR34_##v##_##r##_##f##_BITS; \
   3908         DDR34_PHY_FIELDS_TABLE(DDR34_##r##r_##f, 3) = DDR34_##v##_##r##_##f##_SHIFT; 
   3909 
   3910 #define INIT_DDR34_E0_PHY_FIELDS_TABLE()   { \
   3911     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_REVISION, RESERVED0); \
   3912     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_REVISION, PERFORMANCE); \
   3913     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_REVISION, TECHNOLOGY); \
   3914     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_REVISION, WB); \
   3915     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_REVISION, BITS); \
   3916     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_REVISION, MAJOR); \
   3917     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_REVISION, MINOR); \
   3918     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_PLL_STATUS, RESERVED0); \
   3919     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_PLL_STATUS, LOCK_LOST); \
   3920     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_PLL_STATUS, CLOCKING_8X); \
   3921     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_PLL_STATUS, CLOCKING_4X); \
   3922     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_PLL_STATUS, CLOCKING_2X); \
   3923     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_PLL_STATUS, STATUS); \
   3924     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_PLL_STATUS, LOCK); \
   3925     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_PLL_CONFIG, RESERVED0); \
   3926     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_PLL_CONFIG, RESERVED_for_eco1); \
   3927     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_PLL_CONFIG, CK_LDO_REF_CTRL); \
   3928     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_PLL_CONFIG, CK_LDO_BIAS); \
   3929     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_PLL_CONFIG, PLL_LDO_REF_SEL); \
   3930     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_PLL_CONFIG, PLL_LDO_REF_CTRL); \
   3931     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_PLL_CONFIG, PLL_LDO_BIAS); \
   3932     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_PLL_CONFIG, HOLD); \
   3933     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_PLL_CONFIG, ENABLE); \
   3934     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_PLL_CONFIG, RESERVED2); \
   3935     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_PLL_CONFIG, FB_OFFSET); \
   3936     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_PLL_CONFIG, RESERVED3); \
   3937     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_PLL_CONFIG, RESET_POST_DIV); \
   3938     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_PLL_CONFIG, RESERVED4); \
   3939     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_PLL_CONFIG, RESET); \
   3940     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_PLL_CONFIG, PWRDN); \
   3941     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_PLL_CONTROL1, RESERVED0); \
   3942     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_PLL_CONTROL1, I_KP); \
   3943     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_PLL_CONTROL1, I_KI); \
   3944     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_PLL_CONTROL1, I_KA); \
   3945     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_PLL_CONTROL2, VCO_RANGE); \
   3946     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_PLL_CONTROL2, UNUSED2); \
   3947     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_PLL_CONTROL2, NDIV_RELOCK); \
   3948     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_PLL_CONTROL2, FAST_LOCK); \
   3949     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_PLL_CONTROL2, VCO_FB_DIV2); \
   3950     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_PLL_CONTROL2, POST_CTRL_RESETB); \
   3951     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_PLL_CONTROL2, PWM_RATE); \
   3952     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_PLL_CONTROL2, STAT_MODE); \
   3953     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_PLL_CONTROL2, UNUSED1); \
   3954     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_PLL_CONTROL2, STAT_UPDATE); \
   3955     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_PLL_CONTROL2, STAT_SELECT); \
   3956     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_PLL_CONTROL2, STAT_RESET); \
   3957     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_PLL_CONTROL2, DCO_CTRL_BYPASS_ENABLE); \
   3958     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_PLL_CONTROL2, DCO_CTRL_BYPASS); \
   3959     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_PLL_CONTROL3, PLL_CONTROL); \
   3960     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_PLL_DIVIDERS, RESERVED0); \
   3961     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_PLL_DIVIDERS, MDIV); \
   3962     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_PLL_DIVIDERS, RESERVED1); \
   3963     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_PLL_DIVIDERS, PDIV); \
   3964     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_PLL_DIVIDERS, RESERVED2); \
   3965     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_PLL_DIVIDERS, NDIV_INT); \
   3966     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_PLL_FRAC_DIVIDER, RESERVED0); \
   3967     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_PLL_FRAC_DIVIDER, NDIV_FRAC); \
   3968     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_PLL_SS_CONTROL, RESERVED0); \
   3969     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_PLL_SS_CONTROL, SSC_STEP); \
   3970     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_PLL_SS_CONTROL, RESERVED1); \
   3971     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_PLL_SS_CONTROL, SSC_MODE); \
   3972     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_PLL_SS_LIMIT, RESERVED0); \
   3973     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_PLL_SS_LIMIT, SSC_LIMIT); \
   3974     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_PLL_SS_LIMIT, RESERVED1); \
   3975     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_AUX_CONTROL, RESERVED0); \
   3976     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_AUX_CONTROL, IS_ODT); \
   3977     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_AUX_CONTROL, RESERVED1); \
   3978     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_AUX_CONTROL, IS_CS); \
   3979     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_AUX_CONTROL, RESERVED2); \
   3980     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_AUX_CONTROL, IS_AD); \
   3981     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_IDLE_PAD_CONTROL, IDLE); \
   3982     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_IDLE_PAD_CONTROL, DIB_MODE); \
   3983     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_IDLE_PAD_CONTROL, RESERVED0); \
   3984     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_IDLE_PAD_CONTROL, RXENB); \
   3985     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_IDLE_PAD_CONTROL, IDDQ); \
   3986     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_IDLE_PAD_CONTROL, DOUT_N); \
   3987     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_IDLE_PAD_CONTROL, DOUT_P); \
   3988     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_IDLE_PAD_ENABLE0, RESERVED0); \
   3989     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_IDLE_PAD_ENABLE0, IO_IDLE_ENABLE); \
   3990     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_IDLE_PAD_ENABLE1, RESERVED0); \
   3991     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_IDLE_PAD_ENABLE1, IO_IDLE_ENABLE); \
   3992     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_DRIVE_PAD_CTL, RESERVED0); \
   3993     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_DRIVE_PAD_CTL, ADDR_CTL_PD_IDLE_STRENGTH); \
   3994     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_DRIVE_PAD_CTL, ADDR_CTL_ND_IDLE_STRENGTH); \
   3995     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_DRIVE_PAD_CTL, ADDR_CTL_PD_TERM_STRENGTH); \
   3996     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_DRIVE_PAD_CTL, ADDR_CTL_ND_TERM_STRENGTH); \
   3997     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_DRIVE_PAD_CTL, ADDR_CTL_PD_STRENGTH); \
   3998     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_DRIVE_PAD_CTL, ADDR_CTL_ND_STRENGTH); \
   3999     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_STATIC_PAD_CTL, RESERVED0); \
   4000     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_STATIC_PAD_CTL, AUTO_OEB); \
   4001     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_STATIC_PAD_CTL, IDDQ_GDDR5); \
   4002     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_STATIC_PAD_CTL, IDDQ_LPDDR); \
   4003     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_STATIC_PAD_CTL, IDDQ_CLK1); \
   4004     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_STATIC_PAD_CTL, IDDQ_CLK0); \
   4005     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_STATIC_PAD_CTL, IDDQ_ODT); \
   4006     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_STATIC_PAD_CTL, IDDQ_PAR); \
   4007     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_STATIC_PAD_CTL, IDDQ_BA); \
   4008     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_STATIC_PAD_CTL, IDDQ_AUX2); \
   4009     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_STATIC_PAD_CTL, IDDQ_AUX1); \
   4010     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_STATIC_PAD_CTL, IDDQ_AUX0); \
   4011     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_STATIC_PAD_CTL, IDDQ_CS1); \
   4012     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_STATIC_PAD_CTL, IDDQ_A15); \
   4013     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_STATIC_PAD_CTL, IDDQ_A14); \
   4014     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_STATIC_PAD_CTL, IDDQ_A13); \
   4015     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_STATIC_PAD_CTL, IDDQ_A12); \
   4016     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_STATIC_PAD_CTL, IDDQ_A11); \
   4017     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_STATIC_PAD_CTL, IDDQ_A10); \
   4018     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_STATIC_PAD_CTL, IDDQ_A09); \
   4019     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_STATIC_PAD_CTL, RESERVED1); \
   4020     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_STATIC_PAD_CTL, RX_MODE); \
   4021     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_DRAM_CONFIG, INIT_MODE); \
   4022     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_DRAM_CONFIG, RESERVED0); \
   4023     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_DRAM_CONFIG, ECC_ENABLED); \
   4024     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_DRAM_CONFIG, SPLIT_DQ_BUS); \
   4025     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_DRAM_CONFIG, BUS16); \
   4026     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_DRAM_CONFIG, BUS8); \
   4027     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_DRAM_CONFIG, RESERVED1); \
   4028     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_DRAM_CONFIG, EDC_MODE); \
   4029     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_DRAM_CONFIG, RDQS_MODE); \
   4030     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_DRAM_CONFIG, GROUP_BITS); \
   4031     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_DRAM_CONFIG, BANK_BITS); \
   4032     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_DRAM_CONFIG, COL_BITS); \
   4033     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_DRAM_CONFIG, ROW_BITS); \
   4034     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_DRAM_CONFIG, DRAM_TYPE); \
   4035     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_DRAM_TIMING1, TRAS); \
   4036     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_DRAM_TIMING1, TRRD); \
   4037     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_DRAM_TIMING1, TRP); \
   4038     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_DRAM_TIMING1, TRCD); \
   4039     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_DRAM_TIMING2, TRTP); \
   4040     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_DRAM_TIMING2, TWR); \
   4041     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_DRAM_TIMING2, TCWL); \
   4042     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_DRAM_TIMING2, TCAS); \
   4043     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_DRAM_TIMING3, RESERVED0); \
   4044     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_DRAM_TIMING3, TCAL); \
   4045     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_DRAM_TIMING3, TRTW); \
   4046     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_DRAM_TIMING3, TWTR); \
   4047     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_DRAM_TIMING3, TRFC); \
   4048     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_DRAM_TIMING4, temp); \
   4049     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CALIBRATE, RESERVED0); \
   4050     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CALIBRATE, RESERVED_for_padding1); \
   4051     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CALIBRATE, HALF_STEPS); \
   4052     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CALIBRATE, UPDATE_FAST); \
   4053     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CALIBRATE, UPDATE_REGS); \
   4054     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CALIBRATE, CALIB_FTM2); \
   4055     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CALIBRATE, CALIB_PHYBIST); \
   4056     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CALIBRATE, CALIB_ONCE); \
   4057     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CALIB_STATUS1, RESERVED0); \
   4058     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CALIB_STATUS1, CALIB_TOTAL_STEPS); \
   4059     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CALIB_STATUS1, RESERVED1); \
   4060     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CALIB_STATUS1, CALIB_BUS_ERROR); \
   4061     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CALIB_STATUS1, CALIB_REGS_DONE); \
   4062     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CALIB_STATUS1, CALIB_LOCK_6B); \
   4063     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CALIB_STATUS1, CALIB_LOCK_4B); \
   4064     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CALIB_STATUS1, CALIB_LOCK_2B); \
   4065     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CALIB_STATUS1, CALIB_IDLE); \
   4066     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CALIB_STATUS2, RESERVED0); \
   4067     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CALIB_STATUS2, CALIB_4B_STEPS); \
   4068     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CALIB_STATUS2, RESERVED1); \
   4069     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CALIB_STATUS2, CALIB_2B_STEPS); \
   4070     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_MONITOR_CONTROL, RESERVED0); \
   4071     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_MONITOR_CONTROL, INTERVAL); \
   4072     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_MONITOR_CONTROL, RESERVED1); \
   4073     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_MONITOR_CONTROL, UPDATE); \
   4074     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_MONITOR_CONTROL, FORCE); \
   4075     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_MONITOR_CONTROL, DATA_RATE); \
   4076     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_MONITOR_CONTROL, ENABLE); \
   4077     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_MONITOR_REF, RESERVED0); \
   4078     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_MONITOR_REF, MONITOR_4B_STEPS); \
   4079     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_MONITOR_REF, RESERVED1); \
   4080     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_MONITOR_REF, MONITOR_2B_STEPS); \
   4081     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_MONITOR_STATUS, RESERVED0); \
   4082     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_MONITOR_STATUS, MONITOR_BUS_ERROR); \
   4083     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_MONITOR_STATUS, RESERVED1); \
   4084     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_MONITOR_STATUS, MONITOR_ADJ); \
   4085     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_MONITOR_STATUS, MONITOR_CHANGE); \
   4086     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_MONITOR_STATUS, RESERVED2); \
   4087     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_MONITOR_STATUS, MONITOR_TOTAL); \
   4088     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDE, BUSY); \
   4089     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDE, RESERVED0); \
   4090     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDE, FORCE); \
   4091     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDE, RESERVED1); \
   4092     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDE, ADJ); \
   4093     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDE, RESERVED2); \
   4094     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDE, ENABLE); \
   4095     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_MONITOR_OUT_CONTROL, RESERVED0); \
   4096     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_MONITOR_OUT_CONTROL, LOWER_LIMIT); \
   4097     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_MONITOR_OUT_CONTROL, UPPER_LIMIT); \
   4098     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_MONITOR_OUT_CONTROL, RESERVED1); \
   4099     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_MONITOR_OUT_CONTROL, ENABLE); \
   4100     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS, RESERVED0); \
   4101     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS, MONITOR_CHANGE); \
   4102     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS, RESERVED1); \
   4103     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS, MONITOR_TOTAL); \
   4104     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS, RESERVED2); \
   4105     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS, VALID); \
   4106     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS, CLEAR_RESERVED0); \
   4107     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS, CLEAR_CLEAR); \
   4108     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_CLEAR, RESERVED0); \
   4109     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_CLEAR, CLEAR); \
   4110     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_AD00, BUSY); \
   4111     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_AD00, RESERVED0); \
   4112     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_AD00, FORCE); \
   4113     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_AD00, RESERVED1); \
   4114     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_AD00, ADJ_EN); \
   4115     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_AD00, RESERVED2); \
   4116     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_AD00, VDL_STEP); \
   4117     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_AD01, BUSY); \
   4118     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_AD01, RESERVED0); \
   4119     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_AD01, FORCE); \
   4120     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_AD01, RESERVED1); \
   4121     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_AD01, ADJ_EN); \
   4122     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_AD01, RESERVED2); \
   4123     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_AD01, VDL_STEP); \
   4124     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_AD02, BUSY); \
   4125     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_AD02, RESERVED0); \
   4126     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_AD02, FORCE); \
   4127     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_AD02, RESERVED1); \
   4128     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_AD02, ADJ_EN); \
   4129     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_AD02, RESERVED2); \
   4130     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_AD02, VDL_STEP); \
   4131     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_AD03, BUSY); \
   4132     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_AD03, RESERVED0); \
   4133     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_AD03, FORCE); \
   4134     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_AD03, RESERVED1); \
   4135     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_AD03, ADJ_EN); \
   4136     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_AD03, RESERVED2); \
   4137     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_AD03, VDL_STEP); \
   4138     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_AD04, BUSY); \
   4139     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_AD04, RESERVED0); \
   4140     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_AD04, FORCE); \
   4141     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_AD04, RESERVED1); \
   4142     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_AD04, ADJ_EN); \
   4143     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_AD04, RESERVED2); \
   4144     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_AD04, VDL_STEP); \
   4145     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_AD05, BUSY); \
   4146     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_AD05, RESERVED0); \
   4147     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_AD05, FORCE); \
   4148     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_AD05, RESERVED1); \
   4149     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_AD05, ADJ_EN); \
   4150     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_AD05, RESERVED2); \
   4151     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_AD05, VDL_STEP); \
   4152     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_AD06, BUSY); \
   4153     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_AD06, RESERVED0); \
   4154     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_AD06, FORCE); \
   4155     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_AD06, RESERVED1); \
   4156     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_AD06, ADJ_EN); \
   4157     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_AD06, RESERVED2); \
   4158     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_AD06, VDL_STEP); \
   4159     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_AD07, BUSY); \
   4160     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_AD07, RESERVED0); \
   4161     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_AD07, FORCE); \
   4162     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_AD07, RESERVED1); \
   4163     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_AD07, ADJ_EN); \
   4164     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_AD07, RESERVED2); \
   4165     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_AD07, VDL_STEP); \
   4166     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_AD08, BUSY); \
   4167     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_AD08, RESERVED0); \
   4168     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_AD08, FORCE); \
   4169     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_AD08, RESERVED1); \
   4170     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_AD08, ADJ_EN); \
   4171     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_AD08, RESERVED2); \
   4172     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_AD08, VDL_STEP); \
   4173     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_AD09, BUSY); \
   4174     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_AD09, RESERVED0); \
   4175     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_AD09, FORCE); \
   4176     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_AD09, RESERVED1); \
   4177     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_AD09, ADJ_EN); \
   4178     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_AD09, RESERVED2); \
   4179     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_AD09, VDL_STEP); \
   4180     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_AD10, BUSY); \
   4181     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_AD10, RESERVED0); \
   4182     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_AD10, FORCE); \
   4183     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_AD10, RESERVED1); \
   4184     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_AD10, ADJ_EN); \
   4185     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_AD10, RESERVED2); \
   4186     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_AD10, VDL_STEP); \
   4187     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_AD11, BUSY); \
   4188     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_AD11, RESERVED0); \
   4189     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_AD11, FORCE); \
   4190     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_AD11, RESERVED1); \
   4191     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_AD11, ADJ_EN); \
   4192     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_AD11, RESERVED2); \
   4193     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_AD11, VDL_STEP); \
   4194     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_AD12, BUSY); \
   4195     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_AD12, RESERVED0); \
   4196     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_AD12, FORCE); \
   4197     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_AD12, RESERVED1); \
   4198     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_AD12, ADJ_EN); \
   4199     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_AD12, RESERVED2); \
   4200     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_AD12, VDL_STEP); \
   4201     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_AD13, BUSY); \
   4202     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_AD13, RESERVED0); \
   4203     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_AD13, FORCE); \
   4204     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_AD13, RESERVED1); \
   4205     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_AD13, ADJ_EN); \
   4206     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_AD13, RESERVED2); \
   4207     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_AD13, VDL_STEP); \
   4208     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_AD14, BUSY); \
   4209     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_AD14, RESERVED0); \
   4210     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_AD14, FORCE); \
   4211     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_AD14, RESERVED1); \
   4212     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_AD14, ADJ_EN); \
   4213     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_AD14, RESERVED2); \
   4214     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_AD14, VDL_STEP); \
   4215     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_AD15, BUSY); \
   4216     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_AD15, RESERVED0); \
   4217     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_AD15, FORCE); \
   4218     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_AD15, RESERVED1); \
   4219     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_AD15, ADJ_EN); \
   4220     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_AD15, RESERVED2); \
   4221     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_AD15, VDL_STEP); \
   4222     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_BA0, BUSY); \
   4223     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_BA0, RESERVED0); \
   4224     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_BA0, FORCE); \
   4225     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_BA0, RESERVED1); \
   4226     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_BA0, ADJ_EN); \
   4227     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_BA0, RESERVED2); \
   4228     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_BA0, VDL_STEP); \
   4229     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_BA1, BUSY); \
   4230     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_BA1, RESERVED0); \
   4231     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_BA1, FORCE); \
   4232     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_BA1, RESERVED1); \
   4233     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_BA1, ADJ_EN); \
   4234     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_BA1, RESERVED2); \
   4235     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_BA1, VDL_STEP); \
   4236     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_BA2, BUSY); \
   4237     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_BA2, RESERVED0); \
   4238     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_BA2, FORCE); \
   4239     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_BA2, RESERVED1); \
   4240     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_BA2, ADJ_EN); \
   4241     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_BA2, RESERVED2); \
   4242     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_BA2, VDL_STEP); \
   4243     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_AUX0, BUSY); \
   4244     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_AUX0, RESERVED0); \
   4245     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_AUX0, FORCE); \
   4246     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_AUX0, RESERVED1); \
   4247     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_AUX0, ADJ_EN); \
   4248     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_AUX0, RESERVED2); \
   4249     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_AUX0, VDL_STEP); \
   4250     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_AUX1, BUSY); \
   4251     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_AUX1, RESERVED0); \
   4252     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_AUX1, FORCE); \
   4253     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_AUX1, RESERVED1); \
   4254     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_AUX1, ADJ_EN); \
   4255     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_AUX1, RESERVED2); \
   4256     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_AUX1, VDL_STEP); \
   4257     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_AUX2, BUSY); \
   4258     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_AUX2, RESERVED0); \
   4259     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_AUX2, FORCE); \
   4260     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_AUX2, RESERVED1); \
   4261     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_AUX2, ADJ_EN); \
   4262     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_AUX2, RESERVED2); \
   4263     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_AUX2, VDL_STEP); \
   4264     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_CS0, BUSY); \
   4265     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_CS0, RESERVED0); \
   4266     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_CS0, FORCE); \
   4267     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_CS0, RESERVED1); \
   4268     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_CS0, ADJ_EN); \
   4269     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_CS0, RESERVED2); \
   4270     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_CS0, VDL_STEP); \
   4271     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_CS1, BUSY); \
   4272     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_CS1, RESERVED0); \
   4273     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_CS1, FORCE); \
   4274     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_CS1, RESERVED1); \
   4275     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_CS1, ADJ_EN); \
   4276     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_CS1, RESERVED2); \
   4277     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_CS1, VDL_STEP); \
   4278     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_PAR, BUSY); \
   4279     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_PAR, RESERVED0); \
   4280     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_PAR, FORCE); \
   4281     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_PAR, RESERVED1); \
   4282     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_PAR, ADJ_EN); \
   4283     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_PAR, RESERVED2); \
   4284     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_PAR, VDL_STEP); \
   4285     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_RAS_N, BUSY); \
   4286     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_RAS_N, RESERVED0); \
   4287     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_RAS_N, FORCE); \
   4288     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_RAS_N, RESERVED1); \
   4289     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_RAS_N, ADJ_EN); \
   4290     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_RAS_N, RESERVED2); \
   4291     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_RAS_N, VDL_STEP); \
   4292     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_CAS_N, BUSY); \
   4293     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_CAS_N, RESERVED0); \
   4294     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_CAS_N, FORCE); \
   4295     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_CAS_N, RESERVED1); \
   4296     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_CAS_N, ADJ_EN); \
   4297     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_CAS_N, RESERVED2); \
   4298     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_CAS_N, VDL_STEP); \
   4299     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_CKE, BUSY); \
   4300     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_CKE, RESERVED0); \
   4301     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_CKE, FORCE); \
   4302     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_CKE, RESERVED1); \
   4303     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_CKE, ADJ_EN); \
   4304     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_CKE, RESERVED2); \
   4305     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_CKE, VDL_STEP); \
   4306     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_RST_N, BUSY); \
   4307     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_RST_N, RESERVED0); \
   4308     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_RST_N, FORCE); \
   4309     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_RST_N, RESERVED1); \
   4310     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_RST_N, ADJ_EN); \
   4311     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_RST_N, RESERVED2); \
   4312     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_RST_N, VDL_STEP); \
   4313     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_ODT, BUSY); \
   4314     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_ODT, RESERVED0); \
   4315     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_ODT, FORCE); \
   4316     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_ODT, RESERVED1); \
   4317     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_ODT, ADJ_EN); \
   4318     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_ODT, RESERVED2); \
   4319     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_ODT, VDL_STEP); \
   4320     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_WE_N, BUSY); \
   4321     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_WE_N, RESERVED0); \
   4322     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_WE_N, FORCE); \
   4323     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_WE_N, RESERVED1); \
   4324     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_WE_N, ADJ_EN); \
   4325     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_WE_N, RESERVED2); \
   4326     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_WE_N, VDL_STEP); \
   4327     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_P, BUSY); \
   4328     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_P, RESERVED0); \
   4329     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_P, FORCE); \
   4330     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_P, RESERVED1); \
   4331     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_P, ADJ_EN); \
   4332     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_P, RESERVED2); \
   4333     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_P, VDL_STEP); \
   4334     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_N, BUSY); \
   4335     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_N, RESERVED0); \
   4336     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_N, FORCE); \
   4337     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_N, RESERVED1); \
   4338     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_N, ADJ_EN); \
   4339     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_N, RESERVED2); \
   4340     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_N, VDL_STEP); \
   4341     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CLK_CONTROL, BUSY); \
   4342     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CLK_CONTROL, RESERVED0); \
   4343     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CLK_CONTROL, FORCE); \
   4344     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CLK_CONTROL, RESERVED1); \
   4345     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CLK_CONTROL, ADJ_EN); \
   4346     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CLK_CONTROL, RESERVED2); \
   4347     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_CLK_CONTROL, VDL_STEP); \
   4348     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_LDE_CONTROL, BUSY); \
   4349     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_LDE_CONTROL, RESERVED0); \
   4350     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_LDE_CONTROL, FORCE); \
   4351     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_LDE_CONTROL, RESERVED1); \
   4352     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_LDE_CONTROL, ADJ_EN); \
   4353     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_LDE_CONTROL, RESERVED2); \
   4354     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VDL_LDE_CONTROL, VDL_STEP); \
   4355     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_REFRESH, RESERVED0); \
   4356     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_REFRESH, ENABLE); \
   4357     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_REFRESH, PERIOD); \
   4358     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_UPDATE_VDL, RESERVED0); \
   4359     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_UPDATE_VDL, MODE); \
   4360     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_UPDATE_VDL, RESERVED1); \
   4361     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_UPDATE_VDL, DISABLE_INPUT); \
   4362     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_UPDATE_VDL, ENABLE); \
   4363     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_UPDATE_VDL, SNOOP1_RESERVED0); \
   4364     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_UPDATE_VDL, SNOOP1_MODE); \
   4365     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_UPDATE_VDL, SNOOP1_RESERVED1); \
   4366     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_UPDATE_VDL, SNOOP1_MASK); \
   4367     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_UPDATE_VDL, SNOOP1_RESERVED2); \
   4368     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_UPDATE_VDL, SNOOP1_CMD); \
   4369     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_UPDATE_VDL, SNOOP1_RESERVED3); \
   4370     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_UPDATE_VDL, SNOOP1_ENABLE); \
   4371     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_UPDATE_VDL, SNOOP2_RESERVED0); \
   4372     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_UPDATE_VDL, SNOOP2_MODE); \
   4373     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_UPDATE_VDL, SNOOP2_RESERVED1); \
   4374     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_UPDATE_VDL, SNOOP2_MASK); \
   4375     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_UPDATE_VDL, SNOOP2_RESERVED2); \
   4376     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_UPDATE_VDL, SNOOP2_CMD); \
   4377     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_UPDATE_VDL, SNOOP2_RESERVED3); \
   4378     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_UPDATE_VDL, SNOOP2_ENABLE); \
   4379     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1, RESERVED0); \
   4380     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1, MODE); \
   4381     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1, RESERVED1); \
   4382     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1, MASK); \
   4383     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1, RESERVED2); \
   4384     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1, CMD); \
   4385     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1, RESERVED3); \
   4386     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1, ENABLE); \
   4387     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2, RESERVED0); \
   4388     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2, MODE); \
   4389     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2, RESERVED1); \
   4390     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2, MASK); \
   4391     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2, RESERVED2); \
   4392     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2, CMD); \
   4393     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2, RESERVED3); \
   4394     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2, ENABLE); \
   4395     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_COMMAND_REG1, MCP); \
   4396     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_COMMAND_REG1, CS); \
   4397     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_COMMAND_REG1, AUX); \
   4398     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_COMMAND_REG1, ACT); \
   4399     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_COMMAND_REG1, WE); \
   4400     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_COMMAND_REG1, CAS); \
   4401     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_COMMAND_REG1, RAS); \
   4402     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_COMMAND_REG1, BA); \
   4403     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_COMMAND_REG1, AD); \
   4404     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_COMMAND_AUX_REG1, RESERVED0); \
   4405     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_COMMAND_AUX_REG1, AUX); \
   4406     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_COMMAND_REG2, MCP); \
   4407     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_COMMAND_REG2, CS); \
   4408     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_COMMAND_REG2, AUX); \
   4409     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_COMMAND_REG2, ACT); \
   4410     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_COMMAND_REG2, WE); \
   4411     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_COMMAND_REG2, CAS); \
   4412     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_COMMAND_REG2, RAS); \
   4413     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_COMMAND_REG2, BA); \
   4414     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_COMMAND_REG2, AD); \
   4415     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_COMMAND_AUX_REG2, RESERVED0); \
   4416     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_COMMAND_AUX_REG2, AUX); \
   4417     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_COMMAND_REG3, MCP); \
   4418     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_COMMAND_REG3, CS); \
   4419     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_COMMAND_REG3, AUX); \
   4420     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_COMMAND_REG3, ACT); \
   4421     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_COMMAND_REG3, WE); \
   4422     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_COMMAND_REG3, CAS); \
   4423     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_COMMAND_REG3, RAS); \
   4424     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_COMMAND_REG3, BA); \
   4425     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_COMMAND_REG3, AD); \
   4426     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_COMMAND_AUX_REG3, RESERVED0); \
   4427     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_COMMAND_AUX_REG3, AUX); \
   4428     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_COMMAND_REG4, MCP); \
   4429     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_COMMAND_REG4, CS); \
   4430     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_COMMAND_REG4, AUX); \
   4431     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_COMMAND_REG4, ACT); \
   4432     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_COMMAND_REG4, WE); \
   4433     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_COMMAND_REG4, CAS); \
   4434     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_COMMAND_REG4, RAS); \
   4435     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_COMMAND_REG4, BA); \
   4436     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_COMMAND_REG4, AD); \
   4437     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_COMMAND_AUX_REG4, RESERVED0); \
   4438     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_COMMAND_AUX_REG4, AUX); \
   4439     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_COMMAND_REG_TIMER, RESERVED0); \
   4440     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_COMMAND_REG_TIMER, INIT_VAL); \
   4441     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_COMMAND_REG_TIMER, COUNT); \
   4442     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_MODE_REG0, RESERVED0); \
   4443     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_MODE_REG0, VALID); \
   4444     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_MODE_REG0, AD); \
   4445     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_MODE_REG1, RESERVED0); \
   4446     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_MODE_REG1, VALID); \
   4447     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_MODE_REG1, AD); \
   4448     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_MODE_REG2, RESERVED0); \
   4449     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_MODE_REG2, VALID); \
   4450     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_MODE_REG2, AD); \
   4451     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_MODE_REG3, RESERVED0); \
   4452     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_MODE_REG3, VALID); \
   4453     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_MODE_REG3, AD); \
   4454     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_MODE_REG4, RESERVED0); \
   4455     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_MODE_REG4, VALID); \
   4456     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_MODE_REG4, AD); \
   4457     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_MODE_REG5, RESERVED0); \
   4458     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_MODE_REG5, VALID); \
   4459     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_MODE_REG5, AD); \
   4460     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_MODE_REG6, RESERVED0); \
   4461     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_MODE_REG6, VALID); \
   4462     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_MODE_REG6, AD); \
   4463     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_MODE_REG7, RESERVED0); \
   4464     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_MODE_REG7, VALID); \
   4465     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_MODE_REG7, AD); \
   4466     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_MODE_REG8, RESERVED0); \
   4467     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_MODE_REG8, VALID); \
   4468     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_MODE_REG8, AD); \
   4469     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_MODE_REG15, RESERVED0); \
   4470     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_MODE_REG15, VALID); \
   4471     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_MODE_REG15, AD); \
   4472     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_MODE_REG63, RESERVED0); \
   4473     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_MODE_REG63, VALID); \
   4474     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_MODE_REG63, AD); \
   4475     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_ALERT_CLEAR, RESERVED0); \
   4476     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_ALERT_CLEAR, CLEAR); \
   4477     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_ALERT_STATUS, RESERVED0); \
   4478     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_ALERT_STATUS, STATUS); \
   4479     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_CA_PARITY, RESERVED0); \
   4480     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_CA_PARITY, ERROR); \
   4481     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_CA_PARITY, ENABLE); \
   4482     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_CA_PLAYBACK_CONTROL, RESERVED0); \
   4483     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_CA_PLAYBACK_CONTROL, COUNT); \
   4484     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_CA_PLAYBACK_CONTROL, RESERVED1); \
   4485     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_CA_PLAYBACK_CONTROL, SAMPLE); \
   4486     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_CA_PLAYBACK_STATUS0, VALID); \
   4487     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_CA_PLAYBACK_STATUS0, RESERVED0); \
   4488     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_CA_PLAYBACK_STATUS0, DATA1); \
   4489     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_CA_PLAYBACK_STATUS0, RESERVED1); \
   4490     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_CA_PLAYBACK_STATUS0, DATA0); \
   4491     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_CA_PLAYBACK_STATUS1, VALID); \
   4492     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_CA_PLAYBACK_STATUS1, RESERVED0); \
   4493     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_CA_PLAYBACK_STATUS1, DATA1); \
   4494     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_CA_PLAYBACK_STATUS1, RESERVED1); \
   4495     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_CA_PLAYBACK_STATUS1, DATA0); \
   4496     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_WRITE_LEVELING_CONTROL, RESERVED0); \
   4497     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_WRITE_LEVELING_CONTROL, COUNT); \
   4498     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_WRITE_LEVELING_CONTROL, RESERVED1); \
   4499     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_WRITE_LEVELING_CONTROL, SAMPLE); \
   4500     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_WRITE_LEVELING_CONTROL, CONTINUOUS); \
   4501     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_WRITE_LEVELING_CONTROL, ENABLE); \
   4502     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_WRITE_LEVELING_STATUS, RESERVED0); \
   4503     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_WRITE_LEVELING_STATUS, EDC); \
   4504     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_WRITE_LEVELING_STATUS, STATUS); \
   4505     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_WRITE_LEVELING_STATUS, RESERVED1); \
   4506     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_WRITE_LEVELING_STATUS, VALID); \
   4507     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_READ_ENABLE_CONTROL, RESERVED0); \
   4508     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_READ_ENABLE_CONTROL, TEST_CYCLE); \
   4509     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_READ_ENABLE_CONTROL, SELECT); \
   4510     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_READ_ENABLE_CONTROL, RESERVED1); \
   4511     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_READ_ENABLE_CONTROL, CS_N); \
   4512     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_READ_ENABLE_CONTROL, EDC_DATA); \
   4513     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_READ_ENABLE_CONTROL, EDC_PHASE); \
   4514     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_READ_ENABLE_CONTROL, DQS); \
   4515     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_READ_ENABLE_CONTROL, ENABLE); \
   4516     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_READ_ENABLE_STATUS, RESERVED0); \
   4517     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_READ_ENABLE_STATUS, DATA); \
   4518     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_READ_ENABLE_STATUS, RESERVED1); \
   4519     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_READ_ENABLE_STATUS, BL4_STATUS); \
   4520     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_READ_ENABLE_STATUS, BL3_STATUS); \
   4521     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_READ_ENABLE_STATUS, BL2_STATUS); \
   4522     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_READ_ENABLE_STATUS, BL1_STATUS); \
   4523     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_READ_ENABLE_STATUS, BL0_STATUS); \
   4524     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_READ_ENABLE_STATUS, RESERVED2); \
   4525     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_READ_ENABLE_STATUS, VALID); \
   4526     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_TRAFFIC_GEN_LFSR_SEED, SEED); \
   4527     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_TRAFFIC_GEN_ADDRESS1, RESERVED0); \
   4528     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_TRAFFIC_GEN_ADDRESS1, BANK); \
   4529     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_TRAFFIC_GEN_ADDRESS1, ROW); \
   4530     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_TRAFFIC_GEN_ADDRESS2, RESERVED0); \
   4531     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_TRAFFIC_GEN_ADDRESS2, BANK); \
   4532     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_TRAFFIC_GEN_ADDRESS2, ROW); \
   4533     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL, RESERVED0); \
   4534     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL, DIAG_WRO); \
   4535     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL, DIAG_WRO_RD); \
   4536     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL, DIAG_WR_RD); \
   4537     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL, WR_NOISE); \
   4538     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL, RD_NOISE); \
   4539     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL, CLEAR_DRAM); \
   4540     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL, MASK_DM); \
   4541     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL, INIT_LFSR); \
   4542     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL, FIFO); \
   4543     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL, MPR); \
   4544     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL, RD_WR); \
   4545     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL, RD_EN); \
   4546     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL, ENABLE); \
   4547     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_TRAFFIC_GEN_DATA_CONTROL, RESERVED0); \
   4548     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_TRAFFIC_GEN_DATA_CONTROL, PATTERN); \
   4549     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_TRAFFIC_GEN_DATA_CONTROL, LENGTH); \
   4550     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_MASK, MASK); \
   4551     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_TRAFFIC_GEN_ECC_DQ_MASK, RESERVED0); \
   4552     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_TRAFFIC_GEN_ECC_DQ_MASK, MASK); \
   4553     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_TRAFFIC_GEN_STATUS, RESERVED0); \
   4554     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_TRAFFIC_GEN_STATUS, BUSY); \
   4555     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUS, STATUS); \
   4556     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_TRAFFIC_GEN_ECC_STATUS, RESERVED0); \
   4557     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_TRAFFIC_GEN_ECC_STATUS, STATUS); \
   4558     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_TRAFFIC_GEN_ERR_CNT_CONTROL, RESERVED0); \
   4559     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_TRAFFIC_GEN_ERR_CNT_CONTROL, DQ_SEL); \
   4560     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_TRAFFIC_GEN_ERR_CNT_CONTROL, RESERVED1); \
   4561     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_TRAFFIC_GEN_ERR_CNT_CONTROL, CLEAR); \
   4562     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_TRAFFIC_GEN_ERR_CNT_CONTROL, ENABLE); \
   4563     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_TRAFFIC_GEN_ERR_CNT_STATUS, RESERVED0); \
   4564     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_TRAFFIC_GEN_ERR_CNT_STATUS, COUNT); \
   4565     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL, RESERVED0); \
   4566     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL, RESERVED_for_eco1); \
   4567     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL, MAX_NOISE); \
   4568     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL, LOW_NOISE); \
   4569     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL, LOW_VTT); \
   4570     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL, HIGH_VTT); \
   4571     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL, ERROR_RESET); \
   4572     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL, ENABLE_CTL_IDLE); \
   4573     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL, ENABLE_CS_IDLE); \
   4574     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL, ENABLE_CKE_IDLE); \
   4575     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS, RESERVED0); \
   4576     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS, ERROR); \
   4577     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS, ERROR_LOW); \
   4578     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS, ERROR_HIGH); \
   4579     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS, READY); \
   4580     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VIRTUAL_VTT_CONNECTIONS, RESERVED0); \
   4581     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VIRTUAL_VTT_CONNECTIONS, MASK); \
   4582     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VIRTUAL_VTT_OVERRIDE, RESERVED0); \
   4583     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VIRTUAL_VTT_OVERRIDE, MASK); \
   4584     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VREF_DAC_CONTROL, RESERVED0); \
   4585     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VREF_DAC_CONTROL, AUX_GT_INT); \
   4586     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VREF_DAC_CONTROL, TESTOUT_MUX_CTL); \
   4587     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VREF_DAC_CONTROL, TEST); \
   4588     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VREF_DAC_CONTROL, PDN3); \
   4589     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VREF_DAC_CONTROL, PDN2); \
   4590     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VREF_DAC_CONTROL, PDN1); \
   4591     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VREF_DAC_CONTROL, PDN0); \
   4592     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VREF_DAC_CONTROL, DAC1); \
   4593     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_VREF_DAC_CONTROL, DAC0); \
   4594     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_PHYBIST_CNTRL, RESERVED0); \
   4595     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_PHYBIST_CNTRL, CLK_PAD_ENB); \
   4596     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_PHYBIST_CNTRL, RESERVED1); \
   4597     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_PHYBIST_CNTRL, FORCE_DQ_ERROR_SEL); \
   4598     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_PHYBIST_CNTRL, RESERVED2); \
   4599     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_PHYBIST_CNTRL, FORCE_BL_ERROR_SEL); \
   4600     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_PHYBIST_CNTRL, RESERVED3); \
   4601     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_PHYBIST_CNTRL, FORCE_CTL_ERROR_SEL); \
   4602     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_PHYBIST_CNTRL, RESERVED4); \
   4603     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_PHYBIST_CNTRL, FORCE_DAT_ERROR); \
   4604     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_PHYBIST_CNTRL, FORCE_CTL_ERROR); \
   4605     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_PHYBIST_CNTRL, SSO); \
   4606     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_PHYBIST_CNTRL, LENGTH); \
   4607     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_PHYBIST_CNTRL, MODE); \
   4608     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_PHYBIST_CNTRL, ENABLE); \
   4609     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_PHYBIST_SEED, SEED); \
   4610     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_PHYBIST_STATUS, RESERVED0); \
   4611     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_PHYBIST_STATUS, DAT_PASS); \
   4612     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_PHYBIST_STATUS, CTL_PASS); \
   4613     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_PHYBIST_STATUS, DAT_DONE); \
   4614     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_PHYBIST_STATUS, CTL_DONE); \
   4615     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_PHYBIST_CTL_STATUS, RESERVED0); \
   4616     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_PHYBIST_CTL_STATUS, CTL_ERRORS); \
   4617     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_PHYBIST_BL0_STATUS, RESERVED0); \
   4618     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_PHYBIST_BL0_STATUS, EDC); \
   4619     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_PHYBIST_BL0_STATUS, DM); \
   4620     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_PHYBIST_BL0_STATUS, DQ); \
   4621     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_PHYBIST_BL1_STATUS, RESERVED0); \
   4622     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_PHYBIST_BL1_STATUS, EDC); \
   4623     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_PHYBIST_BL1_STATUS, DM); \
   4624     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_PHYBIST_BL1_STATUS, DQ); \
   4625     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_PHYBIST_BL2_STATUS, RESERVED0); \
   4626     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_PHYBIST_BL2_STATUS, EDC); \
   4627     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_PHYBIST_BL2_STATUS, DM); \
   4628     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_PHYBIST_BL2_STATUS, DQ); \
   4629     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_PHYBIST_BL3_STATUS, RESERVED0); \
   4630     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_PHYBIST_BL3_STATUS, EDC); \
   4631     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_PHYBIST_BL3_STATUS, DM); \
   4632     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_PHYBIST_BL3_STATUS, DQ); \
   4633     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_PHYBIST_BL4_STATUS, RESERVED0); \
   4634     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_PHYBIST_BL4_STATUS, EDC); \
   4635     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_PHYBIST_BL4_STATUS, DM); \
   4636     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_PHYBIST_BL4_STATUS, DQ); \
   4637     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_STANDBY_CONTROL, RESERVED0); \
   4638     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_STANDBY_CONTROL, STANDBY_READY); \
   4639     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_STANDBY_CONTROL, STANDBY_EXIT_PIN_EN); \
   4640     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_STANDBY_CONTROL, STANDBY_ACTIVE); \
   4641     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_STANDBY_CONTROL, ARMED); \
   4642     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_STANDBY_CONTROL, WARMSTART); \
   4643     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_STANDBY_CONTROL, PWRDOWN_LDO_BIAS); \
   4644     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_STANDBY_CONTROL, PWRDOWN_LDO_VOLTS); \
   4645     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_STANDBY_CONTROL, PWRDOWN_SKIP_MRS); \
   4646     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_STANDBY_CONTROL, PWRDOWN_RST_N); \
   4647     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_STANDBY_CONTROL, PWRDOWN_CKE); \
   4648     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_STANDBY_CONTROL, LDO_BIAS); \
   4649     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_STANDBY_CONTROL, LDO_VOLTS); \
   4650     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_STANDBY_CONTROL, SKIP_MRS); \
   4651     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_STANDBY_CONTROL, RST_N); \
   4652     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_STANDBY_CONTROL, CKE); \
   4653     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_STANDBY_CONTROL, STANDBY); \
   4654     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE, RESERVED0); \
   4655     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE, WLECC); \
   4656     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE, WL1_BL1); \
   4657     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE, WL1_BL0); \
   4658     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE, WL0_BL1); \
   4659     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE, WL0_BL0); \
   4660     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_DEBUG_MUX_CONTROL, RESERVED0); \
   4661     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_DEBUG_MUX_CONTROL, BYTE_SEL); \
   4662     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_DEBUG_MUX_CONTROL, RESERVED1); \
   4663     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_DEBUG_MUX_CONTROL, PHASE_SEL); \
   4664     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_DEBUG_MUX_CONTROL, SOURCE_SEL); \
   4665     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_DFI_CNTRL, RESERVED0); \
   4666     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_DFI_CNTRL, DFI_CS1); \
   4667     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_DFI_CNTRL, DFI_CS0); \
   4668     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_DFI_CNTRL, DFI_RST_N); \
   4669     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_DFI_CNTRL, DFI_CKE); \
   4670     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_DFI_CNTRL, ACK_ENABLE); \
   4671     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_DFI_CNTRL, ACK_STATUS); \
   4672     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_DFI_CNTRL, ASSERT_REQ); \
   4673     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_WRITE_ODT_CNTRL, RESERVED0); \
   4674     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_WRITE_ODT_CNTRL, ODT_FORCE_VALUE); \
   4675     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_WRITE_ODT_CNTRL, ODT_FORCE); \
   4676     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_WRITE_ODT_CNTRL, ODT_ENABLE); \
   4677     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_WRITE_ODT_CNTRL, ODT_LENGTH); \
   4678     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_WRITE_ODT_CNTRL, ODT_DELAY); \
   4679     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_ABI_PAR_CNTRL, RESERVED0); \
   4680     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_ABI_PAR_CNTRL, PAR_INCLUDE_AUX); \
   4681     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_ABI_PAR_CNTRL, PAR_ENABLE); \
   4682     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_ABI_PAR_CNTRL, ABI_INCLUDE_AUX); \
   4683     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_ABI_PAR_CNTRL, ABI_ENABLE); \
   4684     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_ZQ_CAL, RESERVED0); \
   4685     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_ZQ_CAL, ZQ_PCOMP_STATUS); \
   4686     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_ZQ_CAL, ZQ_NCOMP_STATUS); \
   4687     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_ZQ_CAL, ZQ_IDDQ); \
   4688     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_ZQ_CAL, ZQ_DRIVE_P); \
   4689     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_ZQ_CAL, ZQ_DRIVE_N); \
   4690     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_ZQ_CAL, RESERVED_for_padding1); \
   4691     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_ZQ_CAL, ZQ_PCOMP_ENB); \
   4692     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_ZQ_CAL, ZQ_NCOMP_ENB); \
   4693     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_AC_SPARE_REG, RESERVED_for_eco0); \
   4694     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_P, BUSY); \
   4695     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_P, RESERVED0); \
   4696     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_P, FORCE); \
   4697     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_P, RESERVED1); \
   4698     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_P, ADJ_EN); \
   4699     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_P, RESERVED2); \
   4700     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_P, VDL_STEP); \
   4701     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_N, BUSY); \
   4702     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_N, RESERVED0); \
   4703     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_N, FORCE); \
   4704     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_N, RESERVED1); \
   4705     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_N, ADJ_EN); \
   4706     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_N, RESERVED2); \
   4707     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_N, VDL_STEP); \
   4708     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0, BUSY); \
   4709     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0, RESERVED0); \
   4710     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0, FORCE); \
   4711     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0, RESERVED1); \
   4712     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0, ADJ_EN); \
   4713     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0, RESERVED2); \
   4714     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0, VDL_STEP); \
   4715     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1, BUSY); \
   4716     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1, RESERVED0); \
   4717     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1, FORCE); \
   4718     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1, RESERVED1); \
   4719     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1, ADJ_EN); \
   4720     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1, RESERVED2); \
   4721     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1, VDL_STEP); \
   4722     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2, BUSY); \
   4723     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2, RESERVED0); \
   4724     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2, FORCE); \
   4725     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2, RESERVED1); \
   4726     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2, ADJ_EN); \
   4727     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2, RESERVED2); \
   4728     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2, VDL_STEP); \
   4729     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3, BUSY); \
   4730     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3, RESERVED0); \
   4731     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3, FORCE); \
   4732     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3, RESERVED1); \
   4733     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3, ADJ_EN); \
   4734     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3, RESERVED2); \
   4735     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3, VDL_STEP); \
   4736     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4, BUSY); \
   4737     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4, RESERVED0); \
   4738     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4, FORCE); \
   4739     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4, RESERVED1); \
   4740     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4, ADJ_EN); \
   4741     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4, RESERVED2); \
   4742     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4, VDL_STEP); \
   4743     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5, BUSY); \
   4744     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5, RESERVED0); \
   4745     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5, FORCE); \
   4746     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5, RESERVED1); \
   4747     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5, ADJ_EN); \
   4748     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5, RESERVED2); \
   4749     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5, VDL_STEP); \
   4750     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6, BUSY); \
   4751     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6, RESERVED0); \
   4752     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6, FORCE); \
   4753     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6, RESERVED1); \
   4754     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6, ADJ_EN); \
   4755     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6, RESERVED2); \
   4756     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6, VDL_STEP); \
   4757     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7, BUSY); \
   4758     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7, RESERVED0); \
   4759     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7, FORCE); \
   4760     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7, RESERVED1); \
   4761     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7, ADJ_EN); \
   4762     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7, RESERVED2); \
   4763     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7, VDL_STEP); \
   4764     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_DM, BUSY); \
   4765     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_DM, RESERVED0); \
   4766     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_DM, FORCE); \
   4767     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_DM, RESERVED1); \
   4768     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_DM, ADJ_EN); \
   4769     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_DM, RESERVED2); \
   4770     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_DM, VDL_STEP); \
   4771     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_EDC, BUSY); \
   4772     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_EDC, RESERVED0); \
   4773     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_EDC, FORCE); \
   4774     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_EDC, RESERVED1); \
   4775     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_EDC, ADJ_EN); \
   4776     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_EDC, RESERVED2); \
   4777     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_EDC, VDL_STEP); \
   4778     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSP, BUSY); \
   4779     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSP, RESERVED0); \
   4780     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSP, FORCE); \
   4781     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSP, RESERVED1); \
   4782     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSP, ADJ_EN); \
   4783     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSP, RESERVED2); \
   4784     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSP, VDL_STEP); \
   4785     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSN, BUSY); \
   4786     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSN, RESERVED0); \
   4787     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSN, FORCE); \
   4788     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSN, RESERVED1); \
   4789     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSN, ADJ_EN); \
   4790     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSN, RESERVED2); \
   4791     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSN, VDL_STEP); \
   4792     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0P, BUSY); \
   4793     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0P, RESERVED0); \
   4794     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0P, FORCE); \
   4795     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0P, RESERVED1); \
   4796     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0P, ADJ_EN); \
   4797     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0P, RESERVED2); \
   4798     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0P, VDL_STEP); \
   4799     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0N, BUSY); \
   4800     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0N, RESERVED0); \
   4801     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0N, FORCE); \
   4802     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0N, RESERVED1); \
   4803     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0N, ADJ_EN); \
   4804     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0N, RESERVED2); \
   4805     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0N, VDL_STEP); \
   4806     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1P, BUSY); \
   4807     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1P, RESERVED0); \
   4808     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1P, FORCE); \
   4809     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1P, RESERVED1); \
   4810     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1P, ADJ_EN); \
   4811     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1P, RESERVED2); \
   4812     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1P, VDL_STEP); \
   4813     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1N, BUSY); \
   4814     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1N, RESERVED0); \
   4815     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1N, FORCE); \
   4816     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1N, RESERVED1); \
   4817     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1N, ADJ_EN); \
   4818     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1N, RESERVED2); \
   4819     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1N, VDL_STEP); \
   4820     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2P, BUSY); \
   4821     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2P, RESERVED0); \
   4822     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2P, FORCE); \
   4823     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2P, RESERVED1); \
   4824     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2P, ADJ_EN); \
   4825     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2P, RESERVED2); \
   4826     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2P, VDL_STEP); \
   4827     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2N, BUSY); \
   4828     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2N, RESERVED0); \
   4829     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2N, FORCE); \
   4830     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2N, RESERVED1); \
   4831     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2N, ADJ_EN); \
   4832     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2N, RESERVED2); \
   4833     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2N, VDL_STEP); \
   4834     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3P, BUSY); \
   4835     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3P, RESERVED0); \
   4836     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3P, FORCE); \
   4837     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3P, RESERVED1); \
   4838     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3P, ADJ_EN); \
   4839     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3P, RESERVED2); \
   4840     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3P, VDL_STEP); \
   4841     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3N, BUSY); \
   4842     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3N, RESERVED0); \
   4843     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3N, FORCE); \
   4844     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3N, RESERVED1); \
   4845     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3N, ADJ_EN); \
   4846     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3N, RESERVED2); \
   4847     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3N, VDL_STEP); \
   4848     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4P, BUSY); \
   4849     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4P, RESERVED0); \
   4850     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4P, FORCE); \
   4851     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4P, RESERVED1); \
   4852     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4P, ADJ_EN); \
   4853     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4P, RESERVED2); \
   4854     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4P, VDL_STEP); \
   4855     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4N, BUSY); \
   4856     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4N, RESERVED0); \
   4857     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4N, FORCE); \
   4858     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4N, RESERVED1); \
   4859     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4N, ADJ_EN); \
   4860     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4N, RESERVED2); \
   4861     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4N, VDL_STEP); \
   4862     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5P, BUSY); \
   4863     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5P, RESERVED0); \
   4864     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5P, FORCE); \
   4865     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5P, RESERVED1); \
   4866     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5P, ADJ_EN); \
   4867     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5P, RESERVED2); \
   4868     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5P, VDL_STEP); \
   4869     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5N, BUSY); \
   4870     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5N, RESERVED0); \
   4871     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5N, FORCE); \
   4872     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5N, RESERVED1); \
   4873     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5N, ADJ_EN); \
   4874     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5N, RESERVED2); \
   4875     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5N, VDL_STEP); \
   4876     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6P, BUSY); \
   4877     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6P, RESERVED0); \
   4878     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6P, FORCE); \
   4879     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6P, RESERVED1); \
   4880     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6P, ADJ_EN); \
   4881     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6P, RESERVED2); \
   4882     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6P, VDL_STEP); \
   4883     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6N, BUSY); \
   4884     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6N, RESERVED0); \
   4885     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6N, FORCE); \
   4886     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6N, RESERVED1); \
   4887     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6N, ADJ_EN); \
   4888     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6N, RESERVED2); \
   4889     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6N, VDL_STEP); \
   4890     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7P, BUSY); \
   4891     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7P, RESERVED0); \
   4892     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7P, FORCE); \
   4893     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7P, RESERVED1); \
   4894     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7P, ADJ_EN); \
   4895     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7P, RESERVED2); \
   4896     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7P, VDL_STEP); \
   4897     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7N, BUSY); \
   4898     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7N, RESERVED0); \
   4899     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7N, FORCE); \
   4900     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7N, RESERVED1); \
   4901     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7N, ADJ_EN); \
   4902     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7N, RESERVED2); \
   4903     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7N, VDL_STEP); \
   4904     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMP, BUSY); \
   4905     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMP, RESERVED0); \
   4906     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMP, FORCE); \
   4907     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMP, RESERVED1); \
   4908     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMP, ADJ_EN); \
   4909     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMP, RESERVED2); \
   4910     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMP, VDL_STEP); \
   4911     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMN, BUSY); \
   4912     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMN, RESERVED0); \
   4913     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMN, FORCE); \
   4914     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMN, RESERVED1); \
   4915     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMN, ADJ_EN); \
   4916     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMN, RESERVED2); \
   4917     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMN, VDL_STEP); \
   4918     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCP, BUSY); \
   4919     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCP, RESERVED0); \
   4920     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCP, FORCE); \
   4921     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCP, RESERVED1); \
   4922     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCP, ADJ_EN); \
   4923     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCP, RESERVED2); \
   4924     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCP, VDL_STEP); \
   4925     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCN, BUSY); \
   4926     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCN, RESERVED0); \
   4927     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCN, FORCE); \
   4928     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCN, RESERVED1); \
   4929     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCN, ADJ_EN); \
   4930     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCN, RESERVED2); \
   4931     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCN, VDL_STEP); \
   4932     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0, BUSY); \
   4933     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0, RESERVED0); \
   4934     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0, FORCE); \
   4935     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0, RESERVED1); \
   4936     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0, ADJ_EN); \
   4937     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0, RESERVED2); \
   4938     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0, VDL_STEP); \
   4939     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1, BUSY); \
   4940     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1, RESERVED0); \
   4941     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1, FORCE); \
   4942     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1, RESERVED1); \
   4943     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1, ADJ_EN); \
   4944     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1, RESERVED2); \
   4945     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1, VDL_STEP); \
   4946     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CLK_CONTROL, BUSY); \
   4947     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CLK_CONTROL, RESERVED0); \
   4948     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CLK_CONTROL, FORCE); \
   4949     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CLK_CONTROL, RESERVED1); \
   4950     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CLK_CONTROL, ADJ_EN); \
   4951     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CLK_CONTROL, RESERVED2); \
   4952     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_CLK_CONTROL, VDL_STEP); \
   4953     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_LDE_CONTROL, BUSY); \
   4954     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_LDE_CONTROL, RESERVED0); \
   4955     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_LDE_CONTROL, FORCE); \
   4956     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_LDE_CONTROL, RESERVED1); \
   4957     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_LDE_CONTROL, ADJ_EN); \
   4958     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_LDE_CONTROL, RESERVED2); \
   4959     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_VDL_LDE_CONTROL, VDL_STEP); \
   4960     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_RD_EN_DLY_CYC, BUSY); \
   4961     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_RD_EN_DLY_CYC, RESERVED0); \
   4962     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_RD_EN_DLY_CYC, FORCE); \
   4963     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_RD_EN_DLY_CYC, RESERVED1); \
   4964     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_RD_EN_DLY_CYC, CS1_CYCLES); \
   4965     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_RD_EN_DLY_CYC, CS0_CYCLES); \
   4966     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_WR_CHAN_DLY_CYC, BUSY); \
   4967     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_WR_CHAN_DLY_CYC, RESERVED0); \
   4968     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_WR_CHAN_DLY_CYC, FORCE); \
   4969     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_WR_CHAN_DLY_CYC, RESERVED1); \
   4970     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_WR_CHAN_DLY_CYC, CYCLES); \
   4971     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_READ_CONTROL, RESERVED0); \
   4972     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_READ_CONTROL, MODE); \
   4973     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_READ_CONTROL, RESERVED1); \
   4974     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_READ_CONTROL, RD_DATA_DLY); \
   4975     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_READ_FIFO_ADDR, RESERVED0); \
   4976     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_READ_FIFO_ADDR, ADDR); \
   4977     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_READ_FIFO_DATA, DATA); \
   4978     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_READ_FIFO_DM_DBI, RESERVED0); \
   4979     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_READ_FIFO_DM_DBI, DM_DBI); \
   4980     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_READ_FIFO_STATUS, RESERVED0); \
   4981     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_READ_FIFO_STATUS, OVERFLOW); \
   4982     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_READ_FIFO_STATUS, UNDERFLOW); \
   4983     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_READ_FIFO_CLEAR, RESERVED0); \
   4984     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_READ_FIFO_CLEAR, CLEAR); \
   4985     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_IDLE_PAD_CONTROL, IDLE); \
   4986     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_IDLE_PAD_CONTROL, RESERVED0); \
   4987     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_IDLE_PAD_CONTROL, AUTO_DQ_RXENB_MODE); \
   4988     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_IDLE_PAD_CONTROL, AUTO_DQ_IDDQ_MODE); \
   4989     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_IDLE_PAD_CONTROL, RESERVED_for_padding1); \
   4990     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_IDLE_PAD_CONTROL, IO_IDLE_ENABLE); \
   4991     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_IDLE_PAD_CONTROL, RXENB); \
   4992     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_IDLE_PAD_CONTROL, IDDQ); \
   4993     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_IDLE_PAD_CONTROL, DOUT_N); \
   4994     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_IDLE_PAD_CONTROL, DOUT_P); \
   4995     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_DRIVE_PAD_CTL, RESERVED0); \
   4996     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_DRIVE_PAD_CTL, BL_PD_IDLE_STRENGTH); \
   4997     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_DRIVE_PAD_CTL, BL_ND_IDLE_STRENGTH); \
   4998     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_DRIVE_PAD_CTL, BL_PD_TERM_STRENGTH); \
   4999     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_DRIVE_PAD_CTL, BL_ND_TERM_STRENGTH); \
   5000     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_DRIVE_PAD_CTL, BL_PD_STRENGTH); \
   5001     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_DRIVE_PAD_CTL, BL_ND_STRENGTH); \
   5002     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_RD_EN_DRIVE_PAD_CTL, RESERVED0); \
   5003     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_RD_EN_DRIVE_PAD_CTL, EDC_RD_EN_PD_STRENGTH); \
   5004     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_RD_EN_DRIVE_PAD_CTL, EDC_RD_EN_ND_STRENGTH); \
   5005     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_RD_EN_DRIVE_PAD_CTL, BL_RD_EN_PD_STRENGTH); \
   5006     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_RD_EN_DRIVE_PAD_CTL, BL_RD_EN_ND_STRENGTH); \
   5007     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_STATIC_PAD_CTL, RESERVED0); \
   5008     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_STATIC_PAD_CTL, DQS_MODE); \
   5009     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_STATIC_PAD_CTL, RESERVED1); \
   5010     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_STATIC_PAD_CTL, EDC_MODE); \
   5011     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_STATIC_PAD_CTL, RESERVED2); \
   5012     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_STATIC_PAD_CTL, WDBI_ENABLE); \
   5013     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_STATIC_PAD_CTL, RDBI_ENABLE); \
   5014     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_STATIC_PAD_CTL, DM_MODE); \
   5015     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_STATIC_PAD_CTL, RESERVED3); \
   5016     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_STATIC_PAD_CTL, DQS_TX_DIS); \
   5017     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_STATIC_PAD_CTL, RESERVED4); \
   5018     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_STATIC_PAD_CTL, RX_MODE); \
   5019     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_WR_PREAMBLE_MODE, RESERVED0); \
   5020     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_WR_PREAMBLE_MODE, DQ_POSTAM_BITS); \
   5021     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_WR_PREAMBLE_MODE, DQ_PREAM_BITS); \
   5022     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_WR_PREAMBLE_MODE, DQS); \
   5023     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_WR_PREAMBLE_MODE, RESERVED1); \
   5024     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_WR_PREAMBLE_MODE, DQS_POSTAM_BITS); \
   5025     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_WR_PREAMBLE_MODE, DQS_PREAM_BITS); \
   5026     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_ODT_CONTROL, RESERVED_for_padding0); \
   5027     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_ODT_CONTROL, RESERVED1); \
   5028     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_ODT_CONTROL, ODT_ENABLE); \
   5029     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_ODT_CONTROL, ODT_DELAY); \
   5030     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_ODT_CONTROL, ODT_POST_LENGTH); \
   5031     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_ODT_CONTROL, ODT_PRE_LENGTH); \
   5032     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_EDC_DPD_CONTROL, RESERVED0); \
   5033     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_EDC_DPD_CONTROL, DQS_PHASE_OVERRIDE_VALUE); \
   5034     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_EDC_DPD_CONTROL, DQS_PHASE_OVERRIDE_ENABLE); \
   5035     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_EDC_DPD_CONTROL, SET_ADJ_EN); \
   5036     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_EDC_DPD_CONTROL, UPDATE); \
   5037     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_EDC_DPD_CONTROL, MONITOR); \
   5038     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_EDC_DPD_CONTROL, INIT); \
   5039     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_EDC_DPD_STATUS, RESERVED0); \
   5040     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_EDC_DPD_STATUS, CURRENT_DQS_PHASE); \
   5041     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_EDC_DPD_STATUS, CURRENT_VDL_SETTING); \
   5042     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_EDC_DPD_STATUS, RESERVED1); \
   5043     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_EDC_DPD_STATUS, INIT_DQS_PHASE); \
   5044     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_EDC_DPD_STATUS, INIT_VDL_SETTING); \
   5045     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_EDC_DPD_STATUS, EDGE_ERROR); \
   5046     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_EDC_DPD_STATUS, MONITOR_BUSY); \
   5047     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_EDC_DPD_STATUS, INIT_BUSY); \
   5048     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_EDC_DPD_STATUS, INIT_DONE); \
   5049     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_EDC_DPD_OUT_CONTROL, RESERVED0); \
   5050     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_EDC_DPD_OUT_CONTROL, LOWER_LIMIT); \
   5051     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_EDC_DPD_OUT_CONTROL, UPPER_LIMIT); \
   5052     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_EDC_DPD_OUT_CONTROL, RESERVED1); \
   5053     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_EDC_DPD_OUT_CONTROL, ENABLE); \
   5054     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_EDC_DPD_OUT_STATUS, RESERVED0); \
   5055     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_EDC_DPD_OUT_STATUS, VDL_SETTING); \
   5056     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_EDC_DPD_OUT_STATUS, RESERVED1); \
   5057     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_EDC_DPD_OUT_STATUS, VALID); \
   5058     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_EDC_DPD_OUT_STATUS, CLEAR_RESERVED0); \
   5059     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_EDC_DPD_OUT_STATUS, CLEAR_CLEAR); \
   5060     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_EDC_DPD_OUT_STATUS_CLEAR, RESERVED0); \
   5061     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_EDC_DPD_OUT_STATUS_CLEAR, CLEAR); \
   5062     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_EDC_CRC_CONTROL, BUSY); \
   5063     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_EDC_CRC_CONTROL, RESERVED0); \
   5064     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_EDC_CRC_CONTROL, FORCE); \
   5065     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_EDC_CRC_CONTROL, RESERVED1); \
   5066     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_EDC_CRC_CONTROL, CRCWL); \
   5067     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_EDC_CRC_CONTROL, RESERVED2); \
   5068     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_EDC_CRC_CONTROL, CRCRL); \
   5069     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_EDC_CRC_CONTROL, RESERVED3); \
   5070     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_EDC_CRC_CONTROL, COUNT_MODE); \
   5071     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_EDC_CRC_CONTROL, ENABLE_WR); \
   5072     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_EDC_CRC_CONTROL, ENABLE_RD); \
   5073     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_EDC_CRC_STATUS, RESERVED0); \
   5074     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_EDC_CRC_STATUS, WR_FAIL); \
   5075     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_EDC_CRC_STATUS, WR_PASS); \
   5076     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_EDC_CRC_STATUS, RD_FAIL); \
   5077     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_EDC_CRC_STATUS, RD_PASS); \
   5078     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_EDC_CRC_STATUS, CLEAR_RESERVED0); \
   5079     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_EDC_CRC_STATUS, CLEAR_CLEAR); \
   5080     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_EDC_CRC_COUNT, RESERVED0); \
   5081     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_EDC_CRC_COUNT, WR_COUNT); \
   5082     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_EDC_CRC_COUNT, RESERVED1); \
   5083     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_EDC_CRC_COUNT, RD_COUNT); \
   5084     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_EDC_CRC_STATUS_CLEAR, RESERVED0); \
   5085     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_EDC_CRC_STATUS_CLEAR, CLEAR); \
   5086     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_0_BL_SPARE_REG, RESERVED_for_eco0); \
   5087     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_P, BUSY); \
   5088     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_P, RESERVED0); \
   5089     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_P, FORCE); \
   5090     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_P, RESERVED1); \
   5091     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_P, ADJ_EN); \
   5092     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_P, RESERVED2); \
   5093     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_P, VDL_STEP); \
   5094     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_N, BUSY); \
   5095     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_N, RESERVED0); \
   5096     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_N, FORCE); \
   5097     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_N, RESERVED1); \
   5098     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_N, ADJ_EN); \
   5099     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_N, RESERVED2); \
   5100     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_N, VDL_STEP); \
   5101     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0, BUSY); \
   5102     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0, RESERVED0); \
   5103     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0, FORCE); \
   5104     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0, RESERVED1); \
   5105     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0, ADJ_EN); \
   5106     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0, RESERVED2); \
   5107     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0, VDL_STEP); \
   5108     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1, BUSY); \
   5109     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1, RESERVED0); \
   5110     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1, FORCE); \
   5111     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1, RESERVED1); \
   5112     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1, ADJ_EN); \
   5113     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1, RESERVED2); \
   5114     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1, VDL_STEP); \
   5115     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2, BUSY); \
   5116     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2, RESERVED0); \
   5117     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2, FORCE); \
   5118     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2, RESERVED1); \
   5119     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2, ADJ_EN); \
   5120     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2, RESERVED2); \
   5121     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2, VDL_STEP); \
   5122     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3, BUSY); \
   5123     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3, RESERVED0); \
   5124     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3, FORCE); \
   5125     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3, RESERVED1); \
   5126     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3, ADJ_EN); \
   5127     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3, RESERVED2); \
   5128     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3, VDL_STEP); \
   5129     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4, BUSY); \
   5130     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4, RESERVED0); \
   5131     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4, FORCE); \
   5132     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4, RESERVED1); \
   5133     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4, ADJ_EN); \
   5134     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4, RESERVED2); \
   5135     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4, VDL_STEP); \
   5136     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5, BUSY); \
   5137     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5, RESERVED0); \
   5138     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5, FORCE); \
   5139     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5, RESERVED1); \
   5140     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5, ADJ_EN); \
   5141     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5, RESERVED2); \
   5142     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5, VDL_STEP); \
   5143     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6, BUSY); \
   5144     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6, RESERVED0); \
   5145     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6, FORCE); \
   5146     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6, RESERVED1); \
   5147     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6, ADJ_EN); \
   5148     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6, RESERVED2); \
   5149     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6, VDL_STEP); \
   5150     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7, BUSY); \
   5151     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7, RESERVED0); \
   5152     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7, FORCE); \
   5153     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7, RESERVED1); \
   5154     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7, ADJ_EN); \
   5155     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7, RESERVED2); \
   5156     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7, VDL_STEP); \
   5157     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_DM, BUSY); \
   5158     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_DM, RESERVED0); \
   5159     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_DM, FORCE); \
   5160     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_DM, RESERVED1); \
   5161     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_DM, ADJ_EN); \
   5162     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_DM, RESERVED2); \
   5163     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_DM, VDL_STEP); \
   5164     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_EDC, BUSY); \
   5165     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_EDC, RESERVED0); \
   5166     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_EDC, FORCE); \
   5167     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_EDC, RESERVED1); \
   5168     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_EDC, ADJ_EN); \
   5169     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_EDC, RESERVED2); \
   5170     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_EDC, VDL_STEP); \
   5171     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSP, BUSY); \
   5172     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSP, RESERVED0); \
   5173     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSP, FORCE); \
   5174     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSP, RESERVED1); \
   5175     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSP, ADJ_EN); \
   5176     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSP, RESERVED2); \
   5177     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSP, VDL_STEP); \
   5178     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSN, BUSY); \
   5179     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSN, RESERVED0); \
   5180     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSN, FORCE); \
   5181     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSN, RESERVED1); \
   5182     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSN, ADJ_EN); \
   5183     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSN, RESERVED2); \
   5184     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSN, VDL_STEP); \
   5185     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0P, BUSY); \
   5186     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0P, RESERVED0); \
   5187     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0P, FORCE); \
   5188     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0P, RESERVED1); \
   5189     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0P, ADJ_EN); \
   5190     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0P, RESERVED2); \
   5191     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0P, VDL_STEP); \
   5192     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0N, BUSY); \
   5193     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0N, RESERVED0); \
   5194     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0N, FORCE); \
   5195     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0N, RESERVED1); \
   5196     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0N, ADJ_EN); \
   5197     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0N, RESERVED2); \
   5198     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0N, VDL_STEP); \
   5199     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1P, BUSY); \
   5200     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1P, RESERVED0); \
   5201     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1P, FORCE); \
   5202     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1P, RESERVED1); \
   5203     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1P, ADJ_EN); \
   5204     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1P, RESERVED2); \
   5205     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1P, VDL_STEP); \
   5206     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1N, BUSY); \
   5207     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1N, RESERVED0); \
   5208     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1N, FORCE); \
   5209     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1N, RESERVED1); \
   5210     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1N, ADJ_EN); \
   5211     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1N, RESERVED2); \
   5212     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1N, VDL_STEP); \
   5213     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2P, BUSY); \
   5214     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2P, RESERVED0); \
   5215     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2P, FORCE); \
   5216     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2P, RESERVED1); \
   5217     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2P, ADJ_EN); \
   5218     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2P, RESERVED2); \
   5219     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2P, VDL_STEP); \
   5220     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2N, BUSY); \
   5221     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2N, RESERVED0); \
   5222     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2N, FORCE); \
   5223     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2N, RESERVED1); \
   5224     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2N, ADJ_EN); \
   5225     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2N, RESERVED2); \
   5226     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2N, VDL_STEP); \
   5227     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3P, BUSY); \
   5228     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3P, RESERVED0); \
   5229     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3P, FORCE); \
   5230     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3P, RESERVED1); \
   5231     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3P, ADJ_EN); \
   5232     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3P, RESERVED2); \
   5233     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3P, VDL_STEP); \
   5234     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3N, BUSY); \
   5235     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3N, RESERVED0); \
   5236     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3N, FORCE); \
   5237     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3N, RESERVED1); \
   5238     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3N, ADJ_EN); \
   5239     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3N, RESERVED2); \
   5240     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3N, VDL_STEP); \
   5241     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4P, BUSY); \
   5242     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4P, RESERVED0); \
   5243     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4P, FORCE); \
   5244     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4P, RESERVED1); \
   5245     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4P, ADJ_EN); \
   5246     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4P, RESERVED2); \
   5247     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4P, VDL_STEP); \
   5248     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4N, BUSY); \
   5249     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4N, RESERVED0); \
   5250     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4N, FORCE); \
   5251     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4N, RESERVED1); \
   5252     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4N, ADJ_EN); \
   5253     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4N, RESERVED2); \
   5254     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4N, VDL_STEP); \
   5255     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5P, BUSY); \
   5256     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5P, RESERVED0); \
   5257     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5P, FORCE); \
   5258     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5P, RESERVED1); \
   5259     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5P, ADJ_EN); \
   5260     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5P, RESERVED2); \
   5261     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5P, VDL_STEP); \
   5262     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5N, BUSY); \
   5263     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5N, RESERVED0); \
   5264     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5N, FORCE); \
   5265     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5N, RESERVED1); \
   5266     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5N, ADJ_EN); \
   5267     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5N, RESERVED2); \
   5268     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5N, VDL_STEP); \
   5269     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6P, BUSY); \
   5270     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6P, RESERVED0); \
   5271     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6P, FORCE); \
   5272     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6P, RESERVED1); \
   5273     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6P, ADJ_EN); \
   5274     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6P, RESERVED2); \
   5275     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6P, VDL_STEP); \
   5276     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6N, BUSY); \
   5277     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6N, RESERVED0); \
   5278     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6N, FORCE); \
   5279     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6N, RESERVED1); \
   5280     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6N, ADJ_EN); \
   5281     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6N, RESERVED2); \
   5282     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6N, VDL_STEP); \
   5283     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7P, BUSY); \
   5284     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7P, RESERVED0); \
   5285     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7P, FORCE); \
   5286     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7P, RESERVED1); \
   5287     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7P, ADJ_EN); \
   5288     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7P, RESERVED2); \
   5289     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7P, VDL_STEP); \
   5290     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7N, BUSY); \
   5291     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7N, RESERVED0); \
   5292     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7N, FORCE); \
   5293     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7N, RESERVED1); \
   5294     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7N, ADJ_EN); \
   5295     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7N, RESERVED2); \
   5296     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7N, VDL_STEP); \
   5297     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMP, BUSY); \
   5298     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMP, RESERVED0); \
   5299     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMP, FORCE); \
   5300     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMP, RESERVED1); \
   5301     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMP, ADJ_EN); \
   5302     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMP, RESERVED2); \
   5303     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMP, VDL_STEP); \
   5304     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMN, BUSY); \
   5305     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMN, RESERVED0); \
   5306     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMN, FORCE); \
   5307     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMN, RESERVED1); \
   5308     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMN, ADJ_EN); \
   5309     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMN, RESERVED2); \
   5310     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMN, VDL_STEP); \
   5311     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCP, BUSY); \
   5312     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCP, RESERVED0); \
   5313     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCP, FORCE); \
   5314     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCP, RESERVED1); \
   5315     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCP, ADJ_EN); \
   5316     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCP, RESERVED2); \
   5317     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCP, VDL_STEP); \
   5318     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCN, BUSY); \
   5319     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCN, RESERVED0); \
   5320     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCN, FORCE); \
   5321     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCN, RESERVED1); \
   5322     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCN, ADJ_EN); \
   5323     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCN, RESERVED2); \
   5324     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCN, VDL_STEP); \
   5325     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0, BUSY); \
   5326     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0, RESERVED0); \
   5327     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0, FORCE); \
   5328     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0, RESERVED1); \
   5329     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0, ADJ_EN); \
   5330     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0, RESERVED2); \
   5331     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0, VDL_STEP); \
   5332     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1, BUSY); \
   5333     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1, RESERVED0); \
   5334     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1, FORCE); \
   5335     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1, RESERVED1); \
   5336     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1, ADJ_EN); \
   5337     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1, RESERVED2); \
   5338     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1, VDL_STEP); \
   5339     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CLK_CONTROL, BUSY); \
   5340     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CLK_CONTROL, RESERVED0); \
   5341     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CLK_CONTROL, FORCE); \
   5342     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CLK_CONTROL, RESERVED1); \
   5343     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CLK_CONTROL, ADJ_EN); \
   5344     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CLK_CONTROL, RESERVED2); \
   5345     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_CLK_CONTROL, VDL_STEP); \
   5346     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_LDE_CONTROL, BUSY); \
   5347     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_LDE_CONTROL, RESERVED0); \
   5348     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_LDE_CONTROL, FORCE); \
   5349     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_LDE_CONTROL, RESERVED1); \
   5350     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_LDE_CONTROL, ADJ_EN); \
   5351     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_LDE_CONTROL, RESERVED2); \
   5352     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_VDL_LDE_CONTROL, VDL_STEP); \
   5353     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_RD_EN_DLY_CYC, BUSY); \
   5354     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_RD_EN_DLY_CYC, RESERVED0); \
   5355     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_RD_EN_DLY_CYC, FORCE); \
   5356     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_RD_EN_DLY_CYC, RESERVED1); \
   5357     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_RD_EN_DLY_CYC, CS1_CYCLES); \
   5358     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_RD_EN_DLY_CYC, CS0_CYCLES); \
   5359     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_WR_CHAN_DLY_CYC, BUSY); \
   5360     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_WR_CHAN_DLY_CYC, RESERVED0); \
   5361     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_WR_CHAN_DLY_CYC, FORCE); \
   5362     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_WR_CHAN_DLY_CYC, RESERVED1); \
   5363     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_WR_CHAN_DLY_CYC, CYCLES); \
   5364     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_READ_CONTROL, RESERVED0); \
   5365     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_READ_CONTROL, MODE); \
   5366     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_READ_CONTROL, RESERVED1); \
   5367     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_READ_CONTROL, RD_DATA_DLY); \
   5368     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_READ_FIFO_ADDR, RESERVED0); \
   5369     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_READ_FIFO_ADDR, ADDR); \
   5370     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_READ_FIFO_DATA, DATA); \
   5371     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_READ_FIFO_DM_DBI, RESERVED0); \
   5372     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_READ_FIFO_DM_DBI, DM_DBI); \
   5373     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_READ_FIFO_STATUS, RESERVED0); \
   5374     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_READ_FIFO_STATUS, OVERFLOW); \
   5375     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_READ_FIFO_STATUS, UNDERFLOW); \
   5376     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_READ_FIFO_CLEAR, RESERVED0); \
   5377     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_READ_FIFO_CLEAR, CLEAR); \
   5378     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_IDLE_PAD_CONTROL, IDLE); \
   5379     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_IDLE_PAD_CONTROL, RESERVED0); \
   5380     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_IDLE_PAD_CONTROL, AUTO_DQ_RXENB_MODE); \
   5381     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_IDLE_PAD_CONTROL, AUTO_DQ_IDDQ_MODE); \
   5382     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_IDLE_PAD_CONTROL, RESERVED_for_padding1); \
   5383     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_IDLE_PAD_CONTROL, IO_IDLE_ENABLE); \
   5384     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_IDLE_PAD_CONTROL, RXENB); \
   5385     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_IDLE_PAD_CONTROL, IDDQ); \
   5386     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_IDLE_PAD_CONTROL, DOUT_N); \
   5387     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_IDLE_PAD_CONTROL, DOUT_P); \
   5388     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_DRIVE_PAD_CTL, RESERVED0); \
   5389     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_DRIVE_PAD_CTL, BL_PD_IDLE_STRENGTH); \
   5390     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_DRIVE_PAD_CTL, BL_ND_IDLE_STRENGTH); \
   5391     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_DRIVE_PAD_CTL, BL_PD_TERM_STRENGTH); \
   5392     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_DRIVE_PAD_CTL, BL_ND_TERM_STRENGTH); \
   5393     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_DRIVE_PAD_CTL, BL_PD_STRENGTH); \
   5394     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_DRIVE_PAD_CTL, BL_ND_STRENGTH); \
   5395     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_RD_EN_DRIVE_PAD_CTL, RESERVED0); \
   5396     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_RD_EN_DRIVE_PAD_CTL, EDC_RD_EN_PD_STRENGTH); \
   5397     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_RD_EN_DRIVE_PAD_CTL, EDC_RD_EN_ND_STRENGTH); \
   5398     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_RD_EN_DRIVE_PAD_CTL, BL_RD_EN_PD_STRENGTH); \
   5399     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_RD_EN_DRIVE_PAD_CTL, BL_RD_EN_ND_STRENGTH); \
   5400     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_STATIC_PAD_CTL, RESERVED0); \
   5401     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_STATIC_PAD_CTL, DQS_MODE); \
   5402     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_STATIC_PAD_CTL, RESERVED1); \
   5403     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_STATIC_PAD_CTL, EDC_MODE); \
   5404     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_STATIC_PAD_CTL, RESERVED2); \
   5405     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_STATIC_PAD_CTL, WDBI_ENABLE); \
   5406     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_STATIC_PAD_CTL, RDBI_ENABLE); \
   5407     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_STATIC_PAD_CTL, DM_MODE); \
   5408     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_STATIC_PAD_CTL, RESERVED3); \
   5409     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_STATIC_PAD_CTL, DQS_TX_DIS); \
   5410     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_STATIC_PAD_CTL, RESERVED4); \
   5411     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_STATIC_PAD_CTL, RX_MODE); \
   5412     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_WR_PREAMBLE_MODE, RESERVED0); \
   5413     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_WR_PREAMBLE_MODE, DQ_POSTAM_BITS); \
   5414     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_WR_PREAMBLE_MODE, DQ_PREAM_BITS); \
   5415     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_WR_PREAMBLE_MODE, DQS); \
   5416     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_WR_PREAMBLE_MODE, RESERVED1); \
   5417     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_WR_PREAMBLE_MODE, DQS_POSTAM_BITS); \
   5418     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_WR_PREAMBLE_MODE, DQS_PREAM_BITS); \
   5419     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_ODT_CONTROL, RESERVED_for_padding0); \
   5420     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_ODT_CONTROL, RESERVED1); \
   5421     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_ODT_CONTROL, ODT_ENABLE); \
   5422     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_ODT_CONTROL, ODT_DELAY); \
   5423     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_ODT_CONTROL, ODT_POST_LENGTH); \
   5424     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_ODT_CONTROL, ODT_PRE_LENGTH); \
   5425     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_EDC_DPD_CONTROL, RESERVED0); \
   5426     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_EDC_DPD_CONTROL, DQS_PHASE_OVERRIDE_VALUE); \
   5427     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_EDC_DPD_CONTROL, DQS_PHASE_OVERRIDE_ENABLE); \
   5428     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_EDC_DPD_CONTROL, SET_ADJ_EN); \
   5429     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_EDC_DPD_CONTROL, UPDATE); \
   5430     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_EDC_DPD_CONTROL, MONITOR); \
   5431     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_EDC_DPD_CONTROL, INIT); \
   5432     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_EDC_DPD_STATUS, RESERVED0); \
   5433     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_EDC_DPD_STATUS, CURRENT_DQS_PHASE); \
   5434     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_EDC_DPD_STATUS, CURRENT_VDL_SETTING); \
   5435     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_EDC_DPD_STATUS, RESERVED1); \
   5436     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_EDC_DPD_STATUS, INIT_DQS_PHASE); \
   5437     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_EDC_DPD_STATUS, INIT_VDL_SETTING); \
   5438     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_EDC_DPD_STATUS, EDGE_ERROR); \
   5439     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_EDC_DPD_STATUS, MONITOR_BUSY); \
   5440     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_EDC_DPD_STATUS, INIT_BUSY); \
   5441     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_EDC_DPD_STATUS, INIT_DONE); \
   5442     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_EDC_DPD_OUT_CONTROL, RESERVED0); \
   5443     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_EDC_DPD_OUT_CONTROL, LOWER_LIMIT); \
   5444     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_EDC_DPD_OUT_CONTROL, UPPER_LIMIT); \
   5445     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_EDC_DPD_OUT_CONTROL, RESERVED1); \
   5446     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_EDC_DPD_OUT_CONTROL, ENABLE); \
   5447     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_EDC_DPD_OUT_STATUS, RESERVED0); \
   5448     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_EDC_DPD_OUT_STATUS, VDL_SETTING); \
   5449     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_EDC_DPD_OUT_STATUS, RESERVED1); \
   5450     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_EDC_DPD_OUT_STATUS, VALID); \
   5451     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_EDC_DPD_OUT_STATUS, CLEAR_RESERVED0); \
   5452     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_EDC_DPD_OUT_STATUS, CLEAR_CLEAR); \
   5453     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_EDC_DPD_OUT_STATUS_CLEAR, RESERVED0); \
   5454     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_EDC_DPD_OUT_STATUS_CLEAR, CLEAR); \
   5455     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_EDC_CRC_CONTROL, BUSY); \
   5456     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_EDC_CRC_CONTROL, RESERVED0); \
   5457     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_EDC_CRC_CONTROL, FORCE); \
   5458     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_EDC_CRC_CONTROL, RESERVED1); \
   5459     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_EDC_CRC_CONTROL, CRCWL); \
   5460     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_EDC_CRC_CONTROL, RESERVED2); \
   5461     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_EDC_CRC_CONTROL, CRCRL); \
   5462     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_EDC_CRC_CONTROL, RESERVED3); \
   5463     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_EDC_CRC_CONTROL, COUNT_MODE); \
   5464     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_EDC_CRC_CONTROL, ENABLE_WR); \
   5465     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_EDC_CRC_CONTROL, ENABLE_RD); \
   5466     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_EDC_CRC_STATUS, RESERVED0); \
   5467     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_EDC_CRC_STATUS, WR_FAIL); \
   5468     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_EDC_CRC_STATUS, WR_PASS); \
   5469     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_EDC_CRC_STATUS, RD_FAIL); \
   5470     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_EDC_CRC_STATUS, RD_PASS); \
   5471     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_EDC_CRC_STATUS, CLEAR_RESERVED0); \
   5472     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_EDC_CRC_STATUS, CLEAR_CLEAR); \
   5473     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_EDC_CRC_COUNT, RESERVED0); \
   5474     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_EDC_CRC_COUNT, WR_COUNT); \
   5475     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_EDC_CRC_COUNT, RESERVED1); \
   5476     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_EDC_CRC_COUNT, RD_COUNT); \
   5477     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_EDC_CRC_STATUS_CLEAR, RESERVED0); \
   5478     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_EDC_CRC_STATUS_CLEAR, CLEAR); \
   5479     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_1_BL_SPARE_REG, RESERVED_for_eco0); \
   5480     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_P, BUSY); \
   5481     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_P, RESERVED0); \
   5482     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_P, FORCE); \
   5483     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_P, RESERVED1); \
   5484     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_P, ADJ_EN); \
   5485     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_P, RESERVED2); \
   5486     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_P, VDL_STEP); \
   5487     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_N, BUSY); \
   5488     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_N, RESERVED0); \
   5489     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_N, FORCE); \
   5490     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_N, RESERVED1); \
   5491     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_N, ADJ_EN); \
   5492     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_N, RESERVED2); \
   5493     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_N, VDL_STEP); \
   5494     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ0, BUSY); \
   5495     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ0, RESERVED0); \
   5496     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ0, FORCE); \
   5497     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ0, RESERVED1); \
   5498     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ0, ADJ_EN); \
   5499     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ0, RESERVED2); \
   5500     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ0, VDL_STEP); \
   5501     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ1, BUSY); \
   5502     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ1, RESERVED0); \
   5503     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ1, FORCE); \
   5504     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ1, RESERVED1); \
   5505     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ1, ADJ_EN); \
   5506     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ1, RESERVED2); \
   5507     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ1, VDL_STEP); \
   5508     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ2, BUSY); \
   5509     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ2, RESERVED0); \
   5510     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ2, FORCE); \
   5511     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ2, RESERVED1); \
   5512     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ2, ADJ_EN); \
   5513     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ2, RESERVED2); \
   5514     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ2, VDL_STEP); \
   5515     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ3, BUSY); \
   5516     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ3, RESERVED0); \
   5517     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ3, FORCE); \
   5518     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ3, RESERVED1); \
   5519     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ3, ADJ_EN); \
   5520     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ3, RESERVED2); \
   5521     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ3, VDL_STEP); \
   5522     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ4, BUSY); \
   5523     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ4, RESERVED0); \
   5524     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ4, FORCE); \
   5525     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ4, RESERVED1); \
   5526     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ4, ADJ_EN); \
   5527     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ4, RESERVED2); \
   5528     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ4, VDL_STEP); \
   5529     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ5, BUSY); \
   5530     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ5, RESERVED0); \
   5531     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ5, FORCE); \
   5532     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ5, RESERVED1); \
   5533     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ5, ADJ_EN); \
   5534     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ5, RESERVED2); \
   5535     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ5, VDL_STEP); \
   5536     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ6, BUSY); \
   5537     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ6, RESERVED0); \
   5538     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ6, FORCE); \
   5539     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ6, RESERVED1); \
   5540     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ6, ADJ_EN); \
   5541     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ6, RESERVED2); \
   5542     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ6, VDL_STEP); \
   5543     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ7, BUSY); \
   5544     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ7, RESERVED0); \
   5545     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ7, FORCE); \
   5546     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ7, RESERVED1); \
   5547     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ7, ADJ_EN); \
   5548     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ7, RESERVED2); \
   5549     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ7, VDL_STEP); \
   5550     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_DM, BUSY); \
   5551     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_DM, RESERVED0); \
   5552     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_DM, FORCE); \
   5553     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_DM, RESERVED1); \
   5554     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_DM, ADJ_EN); \
   5555     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_DM, RESERVED2); \
   5556     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_DM, VDL_STEP); \
   5557     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_EDC, BUSY); \
   5558     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_EDC, RESERVED0); \
   5559     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_EDC, FORCE); \
   5560     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_EDC, RESERVED1); \
   5561     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_EDC, ADJ_EN); \
   5562     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_EDC, RESERVED2); \
   5563     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_EDC, VDL_STEP); \
   5564     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSP, BUSY); \
   5565     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSP, RESERVED0); \
   5566     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSP, FORCE); \
   5567     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSP, RESERVED1); \
   5568     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSP, ADJ_EN); \
   5569     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSP, RESERVED2); \
   5570     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSP, VDL_STEP); \
   5571     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSN, BUSY); \
   5572     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSN, RESERVED0); \
   5573     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSN, FORCE); \
   5574     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSN, RESERVED1); \
   5575     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSN, ADJ_EN); \
   5576     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSN, RESERVED2); \
   5577     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSN, VDL_STEP); \
   5578     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0P, BUSY); \
   5579     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0P, RESERVED0); \
   5580     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0P, FORCE); \
   5581     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0P, RESERVED1); \
   5582     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0P, ADJ_EN); \
   5583     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0P, RESERVED2); \
   5584     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0P, VDL_STEP); \
   5585     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0N, BUSY); \
   5586     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0N, RESERVED0); \
   5587     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0N, FORCE); \
   5588     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0N, RESERVED1); \
   5589     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0N, ADJ_EN); \
   5590     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0N, RESERVED2); \
   5591     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0N, VDL_STEP); \
   5592     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1P, BUSY); \
   5593     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1P, RESERVED0); \
   5594     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1P, FORCE); \
   5595     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1P, RESERVED1); \
   5596     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1P, ADJ_EN); \
   5597     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1P, RESERVED2); \
   5598     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1P, VDL_STEP); \
   5599     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1N, BUSY); \
   5600     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1N, RESERVED0); \
   5601     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1N, FORCE); \
   5602     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1N, RESERVED1); \
   5603     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1N, ADJ_EN); \
   5604     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1N, RESERVED2); \
   5605     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1N, VDL_STEP); \
   5606     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2P, BUSY); \
   5607     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2P, RESERVED0); \
   5608     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2P, FORCE); \
   5609     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2P, RESERVED1); \
   5610     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2P, ADJ_EN); \
   5611     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2P, RESERVED2); \
   5612     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2P, VDL_STEP); \
   5613     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2N, BUSY); \
   5614     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2N, RESERVED0); \
   5615     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2N, FORCE); \
   5616     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2N, RESERVED1); \
   5617     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2N, ADJ_EN); \
   5618     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2N, RESERVED2); \
   5619     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2N, VDL_STEP); \
   5620     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3P, BUSY); \
   5621     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3P, RESERVED0); \
   5622     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3P, FORCE); \
   5623     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3P, RESERVED1); \
   5624     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3P, ADJ_EN); \
   5625     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3P, RESERVED2); \
   5626     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3P, VDL_STEP); \
   5627     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3N, BUSY); \
   5628     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3N, RESERVED0); \
   5629     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3N, FORCE); \
   5630     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3N, RESERVED1); \
   5631     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3N, ADJ_EN); \
   5632     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3N, RESERVED2); \
   5633     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3N, VDL_STEP); \
   5634     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4P, BUSY); \
   5635     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4P, RESERVED0); \
   5636     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4P, FORCE); \
   5637     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4P, RESERVED1); \
   5638     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4P, ADJ_EN); \
   5639     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4P, RESERVED2); \
   5640     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4P, VDL_STEP); \
   5641     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4N, BUSY); \
   5642     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4N, RESERVED0); \
   5643     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4N, FORCE); \
   5644     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4N, RESERVED1); \
   5645     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4N, ADJ_EN); \
   5646     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4N, RESERVED2); \
   5647     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4N, VDL_STEP); \
   5648     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5P, BUSY); \
   5649     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5P, RESERVED0); \
   5650     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5P, FORCE); \
   5651     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5P, RESERVED1); \
   5652     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5P, ADJ_EN); \
   5653     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5P, RESERVED2); \
   5654     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5P, VDL_STEP); \
   5655     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5N, BUSY); \
   5656     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5N, RESERVED0); \
   5657     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5N, FORCE); \
   5658     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5N, RESERVED1); \
   5659     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5N, ADJ_EN); \
   5660     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5N, RESERVED2); \
   5661     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5N, VDL_STEP); \
   5662     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6P, BUSY); \
   5663     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6P, RESERVED0); \
   5664     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6P, FORCE); \
   5665     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6P, RESERVED1); \
   5666     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6P, ADJ_EN); \
   5667     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6P, RESERVED2); \
   5668     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6P, VDL_STEP); \
   5669     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6N, BUSY); \
   5670     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6N, RESERVED0); \
   5671     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6N, FORCE); \
   5672     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6N, RESERVED1); \
   5673     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6N, ADJ_EN); \
   5674     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6N, RESERVED2); \
   5675     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6N, VDL_STEP); \
   5676     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7P, BUSY); \
   5677     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7P, RESERVED0); \
   5678     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7P, FORCE); \
   5679     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7P, RESERVED1); \
   5680     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7P, ADJ_EN); \
   5681     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7P, RESERVED2); \
   5682     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7P, VDL_STEP); \
   5683     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7N, BUSY); \
   5684     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7N, RESERVED0); \
   5685     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7N, FORCE); \
   5686     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7N, RESERVED1); \
   5687     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7N, ADJ_EN); \
   5688     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7N, RESERVED2); \
   5689     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7N, VDL_STEP); \
   5690     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMP, BUSY); \
   5691     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMP, RESERVED0); \
   5692     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMP, FORCE); \
   5693     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMP, RESERVED1); \
   5694     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMP, ADJ_EN); \
   5695     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMP, RESERVED2); \
   5696     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMP, VDL_STEP); \
   5697     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMN, BUSY); \
   5698     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMN, RESERVED0); \
   5699     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMN, FORCE); \
   5700     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMN, RESERVED1); \
   5701     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMN, ADJ_EN); \
   5702     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMN, RESERVED2); \
   5703     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMN, VDL_STEP); \
   5704     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_EDCP, BUSY); \
   5705     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_EDCP, RESERVED0); \
   5706     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_EDCP, FORCE); \
   5707     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_EDCP, RESERVED1); \
   5708     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_EDCP, ADJ_EN); \
   5709     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_EDCP, RESERVED2); \
   5710     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_EDCP, VDL_STEP); \
   5711     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_EDCN, BUSY); \
   5712     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_EDCN, RESERVED0); \
   5713     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_EDCN, FORCE); \
   5714     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_EDCN, RESERVED1); \
   5715     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_EDCN, ADJ_EN); \
   5716     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_EDCN, RESERVED2); \
   5717     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_EDCN, VDL_STEP); \
   5718     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS0, BUSY); \
   5719     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS0, RESERVED0); \
   5720     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS0, FORCE); \
   5721     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS0, RESERVED1); \
   5722     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS0, ADJ_EN); \
   5723     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS0, RESERVED2); \
   5724     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS0, VDL_STEP); \
   5725     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS1, BUSY); \
   5726     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS1, RESERVED0); \
   5727     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS1, FORCE); \
   5728     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS1, RESERVED1); \
   5729     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS1, ADJ_EN); \
   5730     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS1, RESERVED2); \
   5731     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS1, VDL_STEP); \
   5732     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CLK_CONTROL, BUSY); \
   5733     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CLK_CONTROL, RESERVED0); \
   5734     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CLK_CONTROL, FORCE); \
   5735     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CLK_CONTROL, RESERVED1); \
   5736     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CLK_CONTROL, ADJ_EN); \
   5737     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CLK_CONTROL, RESERVED2); \
   5738     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_CLK_CONTROL, VDL_STEP); \
   5739     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_LDE_CONTROL, BUSY); \
   5740     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_LDE_CONTROL, RESERVED0); \
   5741     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_LDE_CONTROL, FORCE); \
   5742     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_LDE_CONTROL, RESERVED1); \
   5743     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_LDE_CONTROL, ADJ_EN); \
   5744     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_LDE_CONTROL, RESERVED2); \
   5745     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_VDL_LDE_CONTROL, VDL_STEP); \
   5746     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_RD_EN_DLY_CYC, BUSY); \
   5747     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_RD_EN_DLY_CYC, RESERVED0); \
   5748     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_RD_EN_DLY_CYC, FORCE); \
   5749     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_RD_EN_DLY_CYC, RESERVED1); \
   5750     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_RD_EN_DLY_CYC, CS1_CYCLES); \
   5751     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_RD_EN_DLY_CYC, CS0_CYCLES); \
   5752     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_WR_CHAN_DLY_CYC, BUSY); \
   5753     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_WR_CHAN_DLY_CYC, RESERVED0); \
   5754     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_WR_CHAN_DLY_CYC, FORCE); \
   5755     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_WR_CHAN_DLY_CYC, RESERVED1); \
   5756     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_WR_CHAN_DLY_CYC, CYCLES); \
   5757     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_READ_CONTROL, RESERVED0); \
   5758     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_READ_CONTROL, MODE); \
   5759     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_READ_CONTROL, RESERVED1); \
   5760     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_READ_CONTROL, RD_DATA_DLY); \
   5761     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_READ_FIFO_ADDR, RESERVED0); \
   5762     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_READ_FIFO_ADDR, ADDR); \
   5763     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_READ_FIFO_DATA, DATA); \
   5764     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_READ_FIFO_DM_DBI, RESERVED0); \
   5765     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_READ_FIFO_DM_DBI, DM_DBI); \
   5766     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_READ_FIFO_STATUS, RESERVED0); \
   5767     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_READ_FIFO_STATUS, OVERFLOW); \
   5768     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_READ_FIFO_STATUS, UNDERFLOW); \
   5769     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_READ_FIFO_CLEAR, RESERVED0); \
   5770     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_READ_FIFO_CLEAR, CLEAR); \
   5771     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_IDLE_PAD_CONTROL, IDLE); \
   5772     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_IDLE_PAD_CONTROL, RESERVED0); \
   5773     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_IDLE_PAD_CONTROL, AUTO_DQ_RXENB_MODE); \
   5774     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_IDLE_PAD_CONTROL, AUTO_DQ_IDDQ_MODE); \
   5775     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_IDLE_PAD_CONTROL, RESERVED_for_padding1); \
   5776     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_IDLE_PAD_CONTROL, IO_IDLE_ENABLE); \
   5777     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_IDLE_PAD_CONTROL, RXENB); \
   5778     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_IDLE_PAD_CONTROL, IDDQ); \
   5779     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_IDLE_PAD_CONTROL, DOUT_N); \
   5780     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_IDLE_PAD_CONTROL, DOUT_P); \
   5781     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_DRIVE_PAD_CTL, RESERVED0); \
   5782     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_DRIVE_PAD_CTL, BL_PD_IDLE_STRENGTH); \
   5783     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_DRIVE_PAD_CTL, BL_ND_IDLE_STRENGTH); \
   5784     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_DRIVE_PAD_CTL, BL_PD_TERM_STRENGTH); \
   5785     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_DRIVE_PAD_CTL, BL_ND_TERM_STRENGTH); \
   5786     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_DRIVE_PAD_CTL, BL_PD_STRENGTH); \
   5787     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_DRIVE_PAD_CTL, BL_ND_STRENGTH); \
   5788     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_RD_EN_DRIVE_PAD_CTL, RESERVED0); \
   5789     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_RD_EN_DRIVE_PAD_CTL, EDC_RD_EN_PD_STRENGTH); \
   5790     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_RD_EN_DRIVE_PAD_CTL, EDC_RD_EN_ND_STRENGTH); \
   5791     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_RD_EN_DRIVE_PAD_CTL, BL_RD_EN_PD_STRENGTH); \
   5792     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_RD_EN_DRIVE_PAD_CTL, BL_RD_EN_ND_STRENGTH); \
   5793     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_STATIC_PAD_CTL, RESERVED0); \
   5794     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_STATIC_PAD_CTL, DQS_MODE); \
   5795     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_STATIC_PAD_CTL, RESERVED1); \
   5796     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_STATIC_PAD_CTL, EDC_MODE); \
   5797     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_STATIC_PAD_CTL, RESERVED2); \
   5798     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_STATIC_PAD_CTL, WDBI_ENABLE); \
   5799     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_STATIC_PAD_CTL, RDBI_ENABLE); \
   5800     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_STATIC_PAD_CTL, DM_MODE); \
   5801     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_STATIC_PAD_CTL, RESERVED3); \
   5802     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_STATIC_PAD_CTL, DQS_TX_DIS); \
   5803     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_STATIC_PAD_CTL, RESERVED4); \
   5804     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_STATIC_PAD_CTL, RX_MODE); \
   5805     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_WR_PREAMBLE_MODE, RESERVED0); \
   5806     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_WR_PREAMBLE_MODE, DQ_POSTAM_BITS); \
   5807     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_WR_PREAMBLE_MODE, DQ_PREAM_BITS); \
   5808     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_WR_PREAMBLE_MODE, DQS); \
   5809     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_WR_PREAMBLE_MODE, RESERVED1); \
   5810     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_WR_PREAMBLE_MODE, DQS_POSTAM_BITS); \
   5811     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_WR_PREAMBLE_MODE, DQS_PREAM_BITS); \
   5812     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_ODT_CONTROL, RESERVED_for_padding0); \
   5813     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_ODT_CONTROL, RESERVED1); \
   5814     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_ODT_CONTROL, ODT_ENABLE); \
   5815     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_ODT_CONTROL, ODT_DELAY); \
   5816     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_ODT_CONTROL, ODT_POST_LENGTH); \
   5817     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_ODT_CONTROL, ODT_PRE_LENGTH); \
   5818     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_EDC_DPD_CONTROL, RESERVED0); \
   5819     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_EDC_DPD_CONTROL, DQS_PHASE_OVERRIDE_VALUE); \
   5820     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_EDC_DPD_CONTROL, DQS_PHASE_OVERRIDE_ENABLE); \
   5821     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_EDC_DPD_CONTROL, SET_ADJ_EN); \
   5822     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_EDC_DPD_CONTROL, UPDATE); \
   5823     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_EDC_DPD_CONTROL, MONITOR); \
   5824     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_EDC_DPD_CONTROL, INIT); \
   5825     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_EDC_DPD_STATUS, RESERVED0); \
   5826     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_EDC_DPD_STATUS, CURRENT_DQS_PHASE); \
   5827     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_EDC_DPD_STATUS, CURRENT_VDL_SETTING); \
   5828     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_EDC_DPD_STATUS, RESERVED1); \
   5829     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_EDC_DPD_STATUS, INIT_DQS_PHASE); \
   5830     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_EDC_DPD_STATUS, INIT_VDL_SETTING); \
   5831     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_EDC_DPD_STATUS, EDGE_ERROR); \
   5832     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_EDC_DPD_STATUS, MONITOR_BUSY); \
   5833     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_EDC_DPD_STATUS, INIT_BUSY); \
   5834     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_EDC_DPD_STATUS, INIT_DONE); \
   5835     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_EDC_DPD_OUT_CONTROL, RESERVED0); \
   5836     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_EDC_DPD_OUT_CONTROL, LOWER_LIMIT); \
   5837     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_EDC_DPD_OUT_CONTROL, UPPER_LIMIT); \
   5838     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_EDC_DPD_OUT_CONTROL, RESERVED1); \
   5839     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_EDC_DPD_OUT_CONTROL, ENABLE); \
   5840     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_EDC_DPD_OUT_STATUS, RESERVED0); \
   5841     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_EDC_DPD_OUT_STATUS, VDL_SETTING); \
   5842     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_EDC_DPD_OUT_STATUS, RESERVED1); \
   5843     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_EDC_DPD_OUT_STATUS, VALID); \
   5844     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_EDC_DPD_OUT_STATUS, CLEAR_RESERVED0); \
   5845     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_EDC_DPD_OUT_STATUS, CLEAR_CLEAR); \
   5846     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_EDC_DPD_OUT_STATUS_CLEAR, RESERVED0); \
   5847     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_EDC_DPD_OUT_STATUS_CLEAR, CLEAR); \
   5848     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_EDC_CRC_CONTROL, BUSY); \
   5849     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_EDC_CRC_CONTROL, RESERVED0); \
   5850     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_EDC_CRC_CONTROL, FORCE); \
   5851     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_EDC_CRC_CONTROL, RESERVED1); \
   5852     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_EDC_CRC_CONTROL, CRCWL); \
   5853     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_EDC_CRC_CONTROL, RESERVED2); \
   5854     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_EDC_CRC_CONTROL, CRCRL); \
   5855     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_EDC_CRC_CONTROL, RESERVED3); \
   5856     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_EDC_CRC_CONTROL, COUNT_MODE); \
   5857     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_EDC_CRC_CONTROL, ENABLE_WR); \
   5858     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_EDC_CRC_CONTROL, ENABLE_RD); \
   5859     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_EDC_CRC_STATUS, RESERVED0); \
   5860     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_EDC_CRC_STATUS, WR_FAIL); \
   5861     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_EDC_CRC_STATUS, WR_PASS); \
   5862     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_EDC_CRC_STATUS, RD_FAIL); \
   5863     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_EDC_CRC_STATUS, RD_PASS); \
   5864     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_EDC_CRC_STATUS, CLEAR_RESERVED0); \
   5865     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_EDC_CRC_STATUS, CLEAR_CLEAR); \
   5866     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_EDC_CRC_COUNT, RESERVED0); \
   5867     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_EDC_CRC_COUNT, WR_COUNT); \
   5868     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_EDC_CRC_COUNT, RESERVED1); \
   5869     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_EDC_CRC_COUNT, RD_COUNT); \
   5870     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_EDC_CRC_STATUS_CLEAR, RESERVED0); \
   5871     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_EDC_CRC_STATUS_CLEAR, CLEAR); \
   5872     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_2_BL_SPARE_REG, RESERVED_for_eco0); \
   5873     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_P, BUSY); \
   5874     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_P, RESERVED0); \
   5875     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_P, FORCE); \
   5876     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_P, RESERVED1); \
   5877     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_P, ADJ_EN); \
   5878     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_P, RESERVED2); \
   5879     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_P, VDL_STEP); \
   5880     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_N, BUSY); \
   5881     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_N, RESERVED0); \
   5882     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_N, FORCE); \
   5883     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_N, RESERVED1); \
   5884     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_N, ADJ_EN); \
   5885     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_N, RESERVED2); \
   5886     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_N, VDL_STEP); \
   5887     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ0, BUSY); \
   5888     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ0, RESERVED0); \
   5889     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ0, FORCE); \
   5890     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ0, RESERVED1); \
   5891     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ0, ADJ_EN); \
   5892     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ0, RESERVED2); \
   5893     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ0, VDL_STEP); \
   5894     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ1, BUSY); \
   5895     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ1, RESERVED0); \
   5896     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ1, FORCE); \
   5897     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ1, RESERVED1); \
   5898     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ1, ADJ_EN); \
   5899     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ1, RESERVED2); \
   5900     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ1, VDL_STEP); \
   5901     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ2, BUSY); \
   5902     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ2, RESERVED0); \
   5903     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ2, FORCE); \
   5904     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ2, RESERVED1); \
   5905     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ2, ADJ_EN); \
   5906     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ2, RESERVED2); \
   5907     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ2, VDL_STEP); \
   5908     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ3, BUSY); \
   5909     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ3, RESERVED0); \
   5910     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ3, FORCE); \
   5911     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ3, RESERVED1); \
   5912     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ3, ADJ_EN); \
   5913     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ3, RESERVED2); \
   5914     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ3, VDL_STEP); \
   5915     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ4, BUSY); \
   5916     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ4, RESERVED0); \
   5917     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ4, FORCE); \
   5918     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ4, RESERVED1); \
   5919     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ4, ADJ_EN); \
   5920     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ4, RESERVED2); \
   5921     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ4, VDL_STEP); \
   5922     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ5, BUSY); \
   5923     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ5, RESERVED0); \
   5924     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ5, FORCE); \
   5925     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ5, RESERVED1); \
   5926     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ5, ADJ_EN); \
   5927     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ5, RESERVED2); \
   5928     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ5, VDL_STEP); \
   5929     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ6, BUSY); \
   5930     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ6, RESERVED0); \
   5931     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ6, FORCE); \
   5932     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ6, RESERVED1); \
   5933     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ6, ADJ_EN); \
   5934     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ6, RESERVED2); \
   5935     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ6, VDL_STEP); \
   5936     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ7, BUSY); \
   5937     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ7, RESERVED0); \
   5938     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ7, FORCE); \
   5939     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ7, RESERVED1); \
   5940     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ7, ADJ_EN); \
   5941     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ7, RESERVED2); \
   5942     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ7, VDL_STEP); \
   5943     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_DM, BUSY); \
   5944     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_DM, RESERVED0); \
   5945     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_DM, FORCE); \
   5946     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_DM, RESERVED1); \
   5947     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_DM, ADJ_EN); \
   5948     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_DM, RESERVED2); \
   5949     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_DM, VDL_STEP); \
   5950     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_EDC, BUSY); \
   5951     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_EDC, RESERVED0); \
   5952     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_EDC, FORCE); \
   5953     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_EDC, RESERVED1); \
   5954     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_EDC, ADJ_EN); \
   5955     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_EDC, RESERVED2); \
   5956     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_EDC, VDL_STEP); \
   5957     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSP, BUSY); \
   5958     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSP, RESERVED0); \
   5959     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSP, FORCE); \
   5960     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSP, RESERVED1); \
   5961     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSP, ADJ_EN); \
   5962     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSP, RESERVED2); \
   5963     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSP, VDL_STEP); \
   5964     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSN, BUSY); \
   5965     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSN, RESERVED0); \
   5966     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSN, FORCE); \
   5967     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSN, RESERVED1); \
   5968     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSN, ADJ_EN); \
   5969     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSN, RESERVED2); \
   5970     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSN, VDL_STEP); \
   5971     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0P, BUSY); \
   5972     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0P, RESERVED0); \
   5973     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0P, FORCE); \
   5974     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0P, RESERVED1); \
   5975     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0P, ADJ_EN); \
   5976     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0P, RESERVED2); \
   5977     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0P, VDL_STEP); \
   5978     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0N, BUSY); \
   5979     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0N, RESERVED0); \
   5980     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0N, FORCE); \
   5981     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0N, RESERVED1); \
   5982     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0N, ADJ_EN); \
   5983     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0N, RESERVED2); \
   5984     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0N, VDL_STEP); \
   5985     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1P, BUSY); \
   5986     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1P, RESERVED0); \
   5987     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1P, FORCE); \
   5988     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1P, RESERVED1); \
   5989     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1P, ADJ_EN); \
   5990     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1P, RESERVED2); \
   5991     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1P, VDL_STEP); \
   5992     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1N, BUSY); \
   5993     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1N, RESERVED0); \
   5994     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1N, FORCE); \
   5995     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1N, RESERVED1); \
   5996     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1N, ADJ_EN); \
   5997     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1N, RESERVED2); \
   5998     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1N, VDL_STEP); \
   5999     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2P, BUSY); \
   6000     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2P, RESERVED0); \
   6001     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2P, FORCE); \
   6002     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2P, RESERVED1); \
   6003     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2P, ADJ_EN); \
   6004     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2P, RESERVED2); \
   6005     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2P, VDL_STEP); \
   6006     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2N, BUSY); \
   6007     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2N, RESERVED0); \
   6008     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2N, FORCE); \
   6009     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2N, RESERVED1); \
   6010     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2N, ADJ_EN); \
   6011     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2N, RESERVED2); \
   6012     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2N, VDL_STEP); \
   6013     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3P, BUSY); \
   6014     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3P, RESERVED0); \
   6015     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3P, FORCE); \
   6016     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3P, RESERVED1); \
   6017     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3P, ADJ_EN); \
   6018     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3P, RESERVED2); \
   6019     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3P, VDL_STEP); \
   6020     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3N, BUSY); \
   6021     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3N, RESERVED0); \
   6022     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3N, FORCE); \
   6023     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3N, RESERVED1); \
   6024     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3N, ADJ_EN); \
   6025     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3N, RESERVED2); \
   6026     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3N, VDL_STEP); \
   6027     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4P, BUSY); \
   6028     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4P, RESERVED0); \
   6029     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4P, FORCE); \
   6030     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4P, RESERVED1); \
   6031     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4P, ADJ_EN); \
   6032     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4P, RESERVED2); \
   6033     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4P, VDL_STEP); \
   6034     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4N, BUSY); \
   6035     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4N, RESERVED0); \
   6036     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4N, FORCE); \
   6037     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4N, RESERVED1); \
   6038     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4N, ADJ_EN); \
   6039     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4N, RESERVED2); \
   6040     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4N, VDL_STEP); \
   6041     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5P, BUSY); \
   6042     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5P, RESERVED0); \
   6043     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5P, FORCE); \
   6044     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5P, RESERVED1); \
   6045     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5P, ADJ_EN); \
   6046     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5P, RESERVED2); \
   6047     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5P, VDL_STEP); \
   6048     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5N, BUSY); \
   6049     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5N, RESERVED0); \
   6050     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5N, FORCE); \
   6051     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5N, RESERVED1); \
   6052     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5N, ADJ_EN); \
   6053     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5N, RESERVED2); \
   6054     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5N, VDL_STEP); \
   6055     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6P, BUSY); \
   6056     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6P, RESERVED0); \
   6057     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6P, FORCE); \
   6058     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6P, RESERVED1); \
   6059     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6P, ADJ_EN); \
   6060     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6P, RESERVED2); \
   6061     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6P, VDL_STEP); \
   6062     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6N, BUSY); \
   6063     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6N, RESERVED0); \
   6064     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6N, FORCE); \
   6065     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6N, RESERVED1); \
   6066     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6N, ADJ_EN); \
   6067     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6N, RESERVED2); \
   6068     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6N, VDL_STEP); \
   6069     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7P, BUSY); \
   6070     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7P, RESERVED0); \
   6071     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7P, FORCE); \
   6072     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7P, RESERVED1); \
   6073     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7P, ADJ_EN); \
   6074     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7P, RESERVED2); \
   6075     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7P, VDL_STEP); \
   6076     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7N, BUSY); \
   6077     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7N, RESERVED0); \
   6078     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7N, FORCE); \
   6079     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7N, RESERVED1); \
   6080     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7N, ADJ_EN); \
   6081     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7N, RESERVED2); \
   6082     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7N, VDL_STEP); \
   6083     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMP, BUSY); \
   6084     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMP, RESERVED0); \
   6085     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMP, FORCE); \
   6086     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMP, RESERVED1); \
   6087     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMP, ADJ_EN); \
   6088     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMP, RESERVED2); \
   6089     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMP, VDL_STEP); \
   6090     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMN, BUSY); \
   6091     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMN, RESERVED0); \
   6092     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMN, FORCE); \
   6093     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMN, RESERVED1); \
   6094     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMN, ADJ_EN); \
   6095     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMN, RESERVED2); \
   6096     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMN, VDL_STEP); \
   6097     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_EDCP, BUSY); \
   6098     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_EDCP, RESERVED0); \
   6099     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_EDCP, FORCE); \
   6100     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_EDCP, RESERVED1); \
   6101     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_EDCP, ADJ_EN); \
   6102     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_EDCP, RESERVED2); \
   6103     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_EDCP, VDL_STEP); \
   6104     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_EDCN, BUSY); \
   6105     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_EDCN, RESERVED0); \
   6106     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_EDCN, FORCE); \
   6107     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_EDCN, RESERVED1); \
   6108     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_EDCN, ADJ_EN); \
   6109     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_EDCN, RESERVED2); \
   6110     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_EDCN, VDL_STEP); \
   6111     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS0, BUSY); \
   6112     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS0, RESERVED0); \
   6113     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS0, FORCE); \
   6114     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS0, RESERVED1); \
   6115     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS0, ADJ_EN); \
   6116     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS0, RESERVED2); \
   6117     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS0, VDL_STEP); \
   6118     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS1, BUSY); \
   6119     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS1, RESERVED0); \
   6120     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS1, FORCE); \
   6121     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS1, RESERVED1); \
   6122     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS1, ADJ_EN); \
   6123     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS1, RESERVED2); \
   6124     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS1, VDL_STEP); \
   6125     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CLK_CONTROL, BUSY); \
   6126     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CLK_CONTROL, RESERVED0); \
   6127     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CLK_CONTROL, FORCE); \
   6128     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CLK_CONTROL, RESERVED1); \
   6129     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CLK_CONTROL, ADJ_EN); \
   6130     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CLK_CONTROL, RESERVED2); \
   6131     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_CLK_CONTROL, VDL_STEP); \
   6132     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_LDE_CONTROL, BUSY); \
   6133     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_LDE_CONTROL, RESERVED0); \
   6134     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_LDE_CONTROL, FORCE); \
   6135     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_LDE_CONTROL, RESERVED1); \
   6136     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_LDE_CONTROL, ADJ_EN); \
   6137     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_LDE_CONTROL, RESERVED2); \
   6138     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_VDL_LDE_CONTROL, VDL_STEP); \
   6139     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_RD_EN_DLY_CYC, BUSY); \
   6140     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_RD_EN_DLY_CYC, RESERVED0); \
   6141     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_RD_EN_DLY_CYC, FORCE); \
   6142     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_RD_EN_DLY_CYC, RESERVED1); \
   6143     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_RD_EN_DLY_CYC, CS1_CYCLES); \
   6144     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_RD_EN_DLY_CYC, CS0_CYCLES); \
   6145     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_WR_CHAN_DLY_CYC, BUSY); \
   6146     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_WR_CHAN_DLY_CYC, RESERVED0); \
   6147     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_WR_CHAN_DLY_CYC, FORCE); \
   6148     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_WR_CHAN_DLY_CYC, RESERVED1); \
   6149     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_WR_CHAN_DLY_CYC, CYCLES); \
   6150     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_READ_CONTROL, RESERVED0); \
   6151     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_READ_CONTROL, MODE); \
   6152     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_READ_CONTROL, RESERVED1); \
   6153     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_READ_CONTROL, RD_DATA_DLY); \
   6154     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_READ_FIFO_ADDR, RESERVED0); \
   6155     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_READ_FIFO_ADDR, ADDR); \
   6156     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_READ_FIFO_DATA, DATA); \
   6157     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_READ_FIFO_DM_DBI, RESERVED0); \
   6158     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_READ_FIFO_DM_DBI, DM_DBI); \
   6159     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_READ_FIFO_STATUS, RESERVED0); \
   6160     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_READ_FIFO_STATUS, OVERFLOW); \
   6161     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_READ_FIFO_STATUS, UNDERFLOW); \
   6162     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_READ_FIFO_CLEAR, RESERVED0); \
   6163     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_READ_FIFO_CLEAR, CLEAR); \
   6164     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_IDLE_PAD_CONTROL, IDLE); \
   6165     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_IDLE_PAD_CONTROL, RESERVED0); \
   6166     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_IDLE_PAD_CONTROL, AUTO_DQ_RXENB_MODE); \
   6167     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_IDLE_PAD_CONTROL, AUTO_DQ_IDDQ_MODE); \
   6168     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_IDLE_PAD_CONTROL, RESERVED_for_padding1); \
   6169     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_IDLE_PAD_CONTROL, IO_IDLE_ENABLE); \
   6170     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_IDLE_PAD_CONTROL, RXENB); \
   6171     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_IDLE_PAD_CONTROL, IDDQ); \
   6172     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_IDLE_PAD_CONTROL, DOUT_N); \
   6173     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_IDLE_PAD_CONTROL, DOUT_P); \
   6174     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_DRIVE_PAD_CTL, RESERVED0); \
   6175     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_DRIVE_PAD_CTL, BL_PD_IDLE_STRENGTH); \
   6176     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_DRIVE_PAD_CTL, BL_ND_IDLE_STRENGTH); \
   6177     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_DRIVE_PAD_CTL, BL_PD_TERM_STRENGTH); \
   6178     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_DRIVE_PAD_CTL, BL_ND_TERM_STRENGTH); \
   6179     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_DRIVE_PAD_CTL, BL_PD_STRENGTH); \
   6180     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_DRIVE_PAD_CTL, BL_ND_STRENGTH); \
   6181     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_RD_EN_DRIVE_PAD_CTL, RESERVED0); \
   6182     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_RD_EN_DRIVE_PAD_CTL, EDC_RD_EN_PD_STRENGTH); \
   6183     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_RD_EN_DRIVE_PAD_CTL, EDC_RD_EN_ND_STRENGTH); \
   6184     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_RD_EN_DRIVE_PAD_CTL, BL_RD_EN_PD_STRENGTH); \
   6185     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_RD_EN_DRIVE_PAD_CTL, BL_RD_EN_ND_STRENGTH); \
   6186     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_STATIC_PAD_CTL, RESERVED0); \
   6187     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_STATIC_PAD_CTL, DQS_MODE); \
   6188     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_STATIC_PAD_CTL, RESERVED1); \
   6189     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_STATIC_PAD_CTL, EDC_MODE); \
   6190     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_STATIC_PAD_CTL, RESERVED2); \
   6191     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_STATIC_PAD_CTL, WDBI_ENABLE); \
   6192     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_STATIC_PAD_CTL, RDBI_ENABLE); \
   6193     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_STATIC_PAD_CTL, DM_MODE); \
   6194     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_STATIC_PAD_CTL, RESERVED3); \
   6195     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_STATIC_PAD_CTL, DQS_TX_DIS); \
   6196     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_STATIC_PAD_CTL, RESERVED4); \
   6197     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_STATIC_PAD_CTL, RX_MODE); \
   6198     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_WR_PREAMBLE_MODE, RESERVED0); \
   6199     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_WR_PREAMBLE_MODE, DQ_POSTAM_BITS); \
   6200     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_WR_PREAMBLE_MODE, DQ_PREAM_BITS); \
   6201     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_WR_PREAMBLE_MODE, DQS); \
   6202     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_WR_PREAMBLE_MODE, RESERVED1); \
   6203     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_WR_PREAMBLE_MODE, DQS_POSTAM_BITS); \
   6204     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_WR_PREAMBLE_MODE, DQS_PREAM_BITS); \
   6205     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_ODT_CONTROL, RESERVED_for_padding0); \
   6206     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_ODT_CONTROL, RESERVED1); \
   6207     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_ODT_CONTROL, ODT_ENABLE); \
   6208     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_ODT_CONTROL, ODT_DELAY); \
   6209     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_ODT_CONTROL, ODT_POST_LENGTH); \
   6210     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_ODT_CONTROL, ODT_PRE_LENGTH); \
   6211     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_EDC_DPD_CONTROL, RESERVED0); \
   6212     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_EDC_DPD_CONTROL, DQS_PHASE_OVERRIDE_VALUE); \
   6213     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_EDC_DPD_CONTROL, DQS_PHASE_OVERRIDE_ENABLE); \
   6214     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_EDC_DPD_CONTROL, SET_ADJ_EN); \
   6215     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_EDC_DPD_CONTROL, UPDATE); \
   6216     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_EDC_DPD_CONTROL, MONITOR); \
   6217     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_EDC_DPD_CONTROL, INIT); \
   6218     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_EDC_DPD_STATUS, RESERVED0); \
   6219     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_EDC_DPD_STATUS, CURRENT_DQS_PHASE); \
   6220     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_EDC_DPD_STATUS, CURRENT_VDL_SETTING); \
   6221     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_EDC_DPD_STATUS, RESERVED1); \
   6222     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_EDC_DPD_STATUS, INIT_DQS_PHASE); \
   6223     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_EDC_DPD_STATUS, INIT_VDL_SETTING); \
   6224     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_EDC_DPD_STATUS, EDGE_ERROR); \
   6225     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_EDC_DPD_STATUS, MONITOR_BUSY); \
   6226     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_EDC_DPD_STATUS, INIT_BUSY); \
   6227     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_EDC_DPD_STATUS, INIT_DONE); \
   6228     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_EDC_DPD_OUT_CONTROL, RESERVED0); \
   6229     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_EDC_DPD_OUT_CONTROL, LOWER_LIMIT); \
   6230     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_EDC_DPD_OUT_CONTROL, UPPER_LIMIT); \
   6231     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_EDC_DPD_OUT_CONTROL, RESERVED1); \
   6232     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_EDC_DPD_OUT_CONTROL, ENABLE); \
   6233     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_EDC_DPD_OUT_STATUS, RESERVED0); \
   6234     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_EDC_DPD_OUT_STATUS, VDL_SETTING); \
   6235     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_EDC_DPD_OUT_STATUS, RESERVED1); \
   6236     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_EDC_DPD_OUT_STATUS, VALID); \
   6237     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_EDC_DPD_OUT_STATUS, CLEAR_RESERVED0); \
   6238     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_EDC_DPD_OUT_STATUS, CLEAR_CLEAR); \
   6239     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_EDC_DPD_OUT_STATUS_CLEAR, RESERVED0); \
   6240     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_EDC_DPD_OUT_STATUS_CLEAR, CLEAR); \
   6241     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_EDC_CRC_CONTROL, BUSY); \
   6242     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_EDC_CRC_CONTROL, RESERVED0); \
   6243     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_EDC_CRC_CONTROL, FORCE); \
   6244     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_EDC_CRC_CONTROL, RESERVED1); \
   6245     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_EDC_CRC_CONTROL, CRCWL); \
   6246     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_EDC_CRC_CONTROL, RESERVED2); \
   6247     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_EDC_CRC_CONTROL, CRCRL); \
   6248     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_EDC_CRC_CONTROL, RESERVED3); \
   6249     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_EDC_CRC_CONTROL, COUNT_MODE); \
   6250     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_EDC_CRC_CONTROL, ENABLE_WR); \
   6251     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_EDC_CRC_CONTROL, ENABLE_RD); \
   6252     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_EDC_CRC_STATUS, RESERVED0); \
   6253     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_EDC_CRC_STATUS, WR_FAIL); \
   6254     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_EDC_CRC_STATUS, WR_PASS); \
   6255     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_EDC_CRC_STATUS, RD_FAIL); \
   6256     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_EDC_CRC_STATUS, RD_PASS); \
   6257     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_EDC_CRC_STATUS, CLEAR_RESERVED0); \
   6258     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_EDC_CRC_STATUS, CLEAR_CLEAR); \
   6259     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_EDC_CRC_COUNT, RESERVED0); \
   6260     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_EDC_CRC_COUNT, WR_COUNT); \
   6261     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_EDC_CRC_COUNT, RESERVED1); \
   6262     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_EDC_CRC_COUNT, RD_COUNT); \
   6263     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_EDC_CRC_STATUS_CLEAR, RESERVED0); \
   6264     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_EDC_CRC_STATUS_CLEAR, CLEAR); \
   6265     INIT_DDR34_SIGNE_FIELD(E0, PHY_BYTE_LANE_3_BL_SPARE_REG, RESERVED_for_eco0); \
   6266     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_IDLE_PAD_ENABLE0, RESERVED0); \
   6267     INIT_DDR34_SIGNE_FIELD(E0, PHY_CONTROL_REGS_IDLE_PAD_ENABLE0, IO_IDLE_ENABLE); \
   6268 }
   6269 
   6270 
   6271 /**********************************************/
   6272 #define INIT_DDR34_F0_PHY_FIELDS_TABLE()   { \
   6273     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_REVISION, RESERVED0); \
   6274     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_REVISION, PERFORMANCE); \
   6275     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_REVISION, TECHNOLOGY); \
   6276     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_REVISION, WB); \
   6277     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_REVISION, BITS); \
   6278     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_REVISION, MAJOR); \
   6279     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_REVISION, MINOR); \
   6280     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_PLL_STATUS, RESERVED0); \
   6281     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_PLL_STATUS, LOCK_LOST); \
   6282     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_PLL_STATUS, CLOCKING_8X); \
   6283     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_PLL_STATUS, CLOCKING_4X); \
   6284     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_PLL_STATUS, CLOCKING_2X); \
   6285     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_PLL_STATUS, STATUS); \
   6286     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_PLL_STATUS, LOCK); \
   6287     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_PLL_CONFIG, RESERVED0); \
   6288     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_PLL_CONFIG, PLL_LDO_REF_SEL); \
   6289     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_PLL_CONFIG, PLL_LDO_REF_CTRL); \
   6290     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_PLL_CONFIG, PLL_LDO_BIAS); \
   6291     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_PLL_CONFIG, PLL_LDO_PWRDOWN); \
   6292     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_PLL_CONFIG, HOLD); \
   6293     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_PLL_CONFIG, ENABLE); \
   6294     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_PLL_CONFIG, RESERVED1); \
   6295     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_PLL_CONFIG, ENABLE_EXT_CTRL); \
   6296     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_PLL_CONFIG, RESET_POST_DIV); \
   6297     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_PLL_CONFIG, ISO_OUT); \
   6298     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_PLL_CONFIG, ISO_IN); \
   6299     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_PLL_CONFIG, RESET); \
   6300     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_PLL_CONFIG, PWRDN); \
   6301     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_PLL_CONTROL1, RESERVED0); \
   6302     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_PLL_CONTROL1, I_KP); \
   6303     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_PLL_CONTROL1, I_KI); \
   6304     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_PLL_CONTROL1, I_KA); \
   6305     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_PLL_CONTROL2, VCO_RANGE); \
   6306     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_PLL_CONTROL2, UNUSED2); \
   6307     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_PLL_CONTROL2, NDIV_RELOCK); \
   6308     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_PLL_CONTROL2, FAST_LOCK); \
   6309     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_PLL_CONTROL2, VCO_FB_DIV2); \
   6310     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_PLL_CONTROL2, POST_CTRL_RESETB); \
   6311     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_PLL_CONTROL2, PWM_RATE); \
   6312     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_PLL_CONTROL2, STAT_MODE); \
   6313     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_PLL_CONTROL2, UNUSED1); \
   6314     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_PLL_CONTROL2, STAT_UPDATE); \
   6315     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_PLL_CONTROL2, STAT_SELECT); \
   6316     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_PLL_CONTROL2, STAT_RESET); \
   6317     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_PLL_CONTROL2, DCO_CTRL_BYPASS_ENABLE); \
   6318     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_PLL_CONTROL2, DCO_CTRL_BYPASS); \
   6319     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_PLL_CONTROL3, PLL_CONTROL); \
   6320     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_PLL_DIVIDERS, RESERVED0); \
   6321     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_PLL_DIVIDERS, MDIV); \
   6322     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_PLL_DIVIDERS, RESERVED1); \
   6323     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_PLL_DIVIDERS, PDIV); \
   6324     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_PLL_DIVIDERS, RESERVED2); \
   6325     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_PLL_DIVIDERS, NDIV_INT); \
   6326     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_PLL_FRAC_DIVIDER, RESERVED0); \
   6327     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_PLL_FRAC_DIVIDER, NDIV_FRAC); \
   6328     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_PLL_SS_CONTROL, RESERVED0); \
   6329     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_PLL_SS_CONTROL, SSC_STEP); \
   6330     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_PLL_SS_CONTROL, RESERVED1); \
   6331     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_PLL_SS_CONTROL, SSC_MODE); \
   6332     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_PLL_SS_LIMIT, RESERVED0); \
   6333     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_PLL_SS_LIMIT, SSC_LIMIT); \
   6334     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_PLL_SS_LIMIT, RESERVED1); \
   6335     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_AUX_CONTROL, RESERVED0); \
   6336     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_AUX_CONTROL, AUX0_IS_ODT); \
   6337     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_AUX_CONTROL, PAR_IS_ODT); \
   6338     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_AUX_CONTROL, RESERVED1); \
   6339     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_IDLE_PAD_CONTROL, IDLE); \
   6340     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_IDLE_PAD_CONTROL, DIB_MODE); \
   6341     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_IDLE_PAD_CONTROL, RESERVED0); \
   6342     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_IDLE_PAD_CONTROL, RXENB); \
   6343     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_IDLE_PAD_CONTROL, IDDQ); \
   6344     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_IDLE_PAD_CONTROL, DOUT_N); \
   6345     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_IDLE_PAD_CONTROL, DOUT_P); \
   6346     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_IDLE_PAD_ENABLE0, RESERVED0); \
   6347     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_IDLE_PAD_ENABLE0, IO_IDLE_ENABLE); \
   6348     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_IDLE_PAD_ENABLE1, RESERVED0); \
   6349     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_IDLE_PAD_ENABLE1, IO_IDLE_ENABLE); \
   6350     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_DRIVE_PAD_CTL, RESERVED0); \
   6351     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_DRIVE_PAD_CTL, ADDR_CTL_PD_IDLE_STRENGTH); \
   6352     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_DRIVE_PAD_CTL, ADDR_CTL_ND_IDLE_STRENGTH); \
   6353     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_DRIVE_PAD_CTL, ADDR_CTL_PD_TERM_STRENGTH); \
   6354     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_DRIVE_PAD_CTL, ADDR_CTL_ND_TERM_STRENGTH); \
   6355     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_DRIVE_PAD_CTL, ADDR_CTL_PD_STRENGTH); \
   6356     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_DRIVE_PAD_CTL, ADDR_CTL_ND_STRENGTH); \
   6357     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_DRIVE_PAD_CTL, 2T_RESERVED0); \
   6358     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_DRIVE_PAD_CTL, 2T_PD_IDLE_STRENGTH); \
   6359     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_DRIVE_PAD_CTL, 2T_ND_IDLE_STRENGTH); \
   6360     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_DRIVE_PAD_CTL, 2T_PD_TERM_STRENGTH); \
   6361     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_DRIVE_PAD_CTL, 2T_ND_TERM_STRENGTH); \
   6362     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_DRIVE_PAD_CTL, 2T_PD_STRENGTH); \
   6363     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_DRIVE_PAD_CTL, 2T_ND_STRENGTH); \
   6364     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_DRIVE_PAD_CTL_2T, RESERVED0); \
   6365     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_DRIVE_PAD_CTL_2T, PD_IDLE_STRENGTH); \
   6366     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_DRIVE_PAD_CTL_2T, ND_IDLE_STRENGTH); \
   6367     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_DRIVE_PAD_CTL_2T, PD_TERM_STRENGTH); \
   6368     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_DRIVE_PAD_CTL_2T, ND_TERM_STRENGTH); \
   6369     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_DRIVE_PAD_CTL_2T, PD_STRENGTH); \
   6370     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_DRIVE_PAD_CTL_2T, ND_STRENGTH); \
   6371     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_STATIC_PAD_CTL, RESERVED0); \
   6372     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_STATIC_PAD_CTL, AUTO_OEB); \
   6373     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_STATIC_PAD_CTL, IDDQ_LPDDR); \
   6374     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_STATIC_PAD_CTL, IDDQ_CLK0); \
   6375     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_STATIC_PAD_CTL, IDDQ_ODT); \
   6376     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_STATIC_PAD_CTL, IDDQ_PAR); \
   6377     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_STATIC_PAD_CTL, IDDQ_BA); \
   6378     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_STATIC_PAD_CTL, IDDQ_AUX2); \
   6379     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_STATIC_PAD_CTL, IDDQ_AUX1); \
   6380     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_STATIC_PAD_CTL, IDDQ_AUX0); \
   6381     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_STATIC_PAD_CTL, IDDQ_CS1); \
   6382     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_STATIC_PAD_CTL, IDDQ_A15); \
   6383     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_STATIC_PAD_CTL, IDDQ_A14); \
   6384     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_STATIC_PAD_CTL, IDDQ_A13); \
   6385     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_STATIC_PAD_CTL, IDDQ_A12); \
   6386     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_STATIC_PAD_CTL, IDDQ_A11); \
   6387     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_STATIC_PAD_CTL, IDDQ_A10); \
   6388     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_STATIC_PAD_CTL, IDDQ_A09); \
   6389     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_STATIC_PAD_CTL, RESERVED1); \
   6390     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_STATIC_PAD_CTL, RX_MODE); \
   6391     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_DRAM_CONFIG, INIT_MODE); \
   6392     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_DRAM_CONFIG, RESERVED0); \
   6393     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_DRAM_CONFIG, SPLIT_DQ_BUS); \
   6394     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_DRAM_CONFIG, BUS16); \
   6395     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_DRAM_CONFIG, BUS8); \
   6396     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_DRAM_CONFIG, RESERVED1); \
   6397     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_DRAM_CONFIG, DDR4_GEARDOWN_ENABLE); \
   6398     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_DRAM_CONFIG, RESERVED2); \
   6399     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_DRAM_CONFIG, RDQS_MODE); \
   6400     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_DRAM_CONFIG, GROUP_BITS); \
   6401     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_DRAM_CONFIG, BANK_BITS); \
   6402     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_DRAM_CONFIG, COL_BITS); \
   6403     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_DRAM_CONFIG, ROW_BITS); \
   6404     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_DRAM_CONFIG, DRAM_TYPE); \
   6405     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_DRAM_TIMING1, TRAS); \
   6406     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_DRAM_TIMING1, TRRD); \
   6407     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_DRAM_TIMING1, TRP); \
   6408     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_DRAM_TIMING1, TRCD); \
   6409     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_DRAM_TIMING2, TRTP); \
   6410     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_DRAM_TIMING2, TWR); \
   6411     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_DRAM_TIMING2, TCWL); \
   6412     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_DRAM_TIMING2, TCAS); \
   6413     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_DRAM_TIMING3, RESERVED0); \
   6414     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_DRAM_TIMING3, TCAL); \
   6415     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_DRAM_TIMING3, TRTW); \
   6416     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_DRAM_TIMING3, TWTR); \
   6417     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_DRAM_TIMING3, TRFC); \
   6418     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_DRAM_TIMING4, TEMP); \
   6419     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CALIBRATE, RESERVED0); \
   6420     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CALIBRATE, CALIB_FAST); \
   6421     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CALIBRATE, HALF_STEPS); \
   6422     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CALIBRATE, UPDATE_FAST); \
   6423     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CALIBRATE, UPDATE_REGS); \
   6424     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CALIBRATE, CALIB_FTM2); \
   6425     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CALIBRATE, CALIB_PHYBIST); \
   6426     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CALIBRATE, CALIB_ONCE); \
   6427     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CALIB_STATUS1, RESERVED0); \
   6428     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CALIB_STATUS1, CALIB_TOTAL_STEPS); \
   6429     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CALIB_STATUS1, RESERVED1); \
   6430     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CALIB_STATUS1, CALIB_BUS_ERROR); \
   6431     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CALIB_STATUS1, CALIB_REGS_DONE); \
   6432     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CALIB_STATUS1, CALIB_LOCK_6B); \
   6433     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CALIB_STATUS1, CALIB_LOCK_4B); \
   6434     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CALIB_STATUS1, CALIB_LOCK_2B); \
   6435     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CALIB_STATUS1, CALIB_IDLE); \
   6436     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CALIB_STATUS2, RESERVED0); \
   6437     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CALIB_STATUS2, CALIB_4B_STEPS); \
   6438     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CALIB_STATUS2, RESERVED1); \
   6439     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CALIB_STATUS2, CALIB_2B_STEPS); \
   6440     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_MONITOR_CONTROL, RESERVED0); \
   6441     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_MONITOR_CONTROL, INTERVAL); \
   6442     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_MONITOR_CONTROL, RESERVED1); \
   6443     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_MONITOR_CONTROL, UPDATE); \
   6444     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_MONITOR_CONTROL, FORCE); \
   6445     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_MONITOR_CONTROL, DATA_RATE); \
   6446     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_MONITOR_CONTROL, ENABLE); \
   6447     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_MONITOR_REF, RESERVED0); \
   6448     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_MONITOR_REF, MONITOR_4B_STEPS); \
   6449     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_MONITOR_REF, RESERVED1); \
   6450     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_MONITOR_REF, MONITOR_2B_STEPS); \
   6451     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_MONITOR_STATUS, RESERVED0); \
   6452     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_MONITOR_STATUS, MONITOR_CHANGE); \
   6453     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_MONITOR_STATUS, RESERVED1); \
   6454     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_MONITOR_STATUS, MONITOR_TOTAL); \
   6455     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_MONITOR_STATUS, ERROR); \
   6456     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_MONITOR_STATUS, PAUSED); \
   6457     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_MONITOR_STATUS, BUSY); \
   6458     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDE, BUSY); \
   6459     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDE, RESERVED0); \
   6460     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDE, FORCE); \
   6461     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDE, RESERVED1); \
   6462     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDE, ADJ); \
   6463     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_MONITOR_OUT_CONTROL, RESERVED0); \
   6464     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_MONITOR_OUT_CONTROL, LOWER_LIMIT); \
   6465     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_MONITOR_OUT_CONTROL, UPPER_LIMIT); \
   6466     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_MONITOR_OUT_CONTROL, RESERVED1); \
   6467     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_MONITOR_OUT_CONTROL, ENABLE); \
   6468     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS, RESERVED0); \
   6469     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS, MONITOR_CHANGE); \
   6470     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS, RESERVED1); \
   6471     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS, MONITOR_TOTAL); \
   6472     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS, RESERVED2); \
   6473     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS, VALID); \
   6474     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS, CLEAR_RESERVED0); \
   6475     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS, CLEAR_CLEAR); \
   6476     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_CLEAR, RESERVED0); \
   6477     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_CLEAR, CLEAR); \
   6478     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_AD00, BUSY); \
   6479     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_AD00, RESERVED0); \
   6480     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_AD00, FORCE); \
   6481     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_AD00, RESERVED1); \
   6482     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_AD00, ADJ_EN); \
   6483     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_AD00, RESERVED2); \
   6484     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_AD00, VDL_STEP); \
   6485     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_AD01, BUSY); \
   6486     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_AD01, RESERVED0); \
   6487     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_AD01, FORCE); \
   6488     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_AD01, RESERVED1); \
   6489     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_AD01, ADJ_EN); \
   6490     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_AD01, RESERVED2); \
   6491     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_AD01, VDL_STEP); \
   6492     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_AD02, BUSY); \
   6493     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_AD02, RESERVED0); \
   6494     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_AD02, FORCE); \
   6495     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_AD02, RESERVED1); \
   6496     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_AD02, ADJ_EN); \
   6497     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_AD02, RESERVED2); \
   6498     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_AD02, VDL_STEP); \
   6499     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_AD03, BUSY); \
   6500     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_AD03, RESERVED0); \
   6501     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_AD03, FORCE); \
   6502     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_AD03, RESERVED1); \
   6503     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_AD03, ADJ_EN); \
   6504     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_AD03, RESERVED2); \
   6505     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_AD03, VDL_STEP); \
   6506     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_AD04, BUSY); \
   6507     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_AD04, RESERVED0); \
   6508     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_AD04, FORCE); \
   6509     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_AD04, RESERVED1); \
   6510     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_AD04, ADJ_EN); \
   6511     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_AD04, RESERVED2); \
   6512     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_AD04, VDL_STEP); \
   6513     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_AD05, BUSY); \
   6514     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_AD05, RESERVED0); \
   6515     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_AD05, FORCE); \
   6516     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_AD05, RESERVED1); \
   6517     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_AD05, ADJ_EN); \
   6518     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_AD05, RESERVED2); \
   6519     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_AD05, VDL_STEP); \
   6520     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_AD06, BUSY); \
   6521     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_AD06, RESERVED0); \
   6522     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_AD06, FORCE); \
   6523     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_AD06, RESERVED1); \
   6524     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_AD06, ADJ_EN); \
   6525     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_AD06, RESERVED2); \
   6526     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_AD06, VDL_STEP); \
   6527     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_AD07, BUSY); \
   6528     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_AD07, RESERVED0); \
   6529     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_AD07, FORCE); \
   6530     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_AD07, RESERVED1); \
   6531     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_AD07, ADJ_EN); \
   6532     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_AD07, RESERVED2); \
   6533     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_AD07, VDL_STEP); \
   6534     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_AD08, BUSY); \
   6535     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_AD08, RESERVED0); \
   6536     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_AD08, FORCE); \
   6537     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_AD08, RESERVED1); \
   6538     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_AD08, ADJ_EN); \
   6539     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_AD08, RESERVED2); \
   6540     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_AD08, VDL_STEP); \
   6541     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_AD09, BUSY); \
   6542     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_AD09, RESERVED0); \
   6543     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_AD09, FORCE); \
   6544     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_AD09, RESERVED1); \
   6545     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_AD09, ADJ_EN); \
   6546     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_AD09, RESERVED2); \
   6547     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_AD09, VDL_STEP); \
   6548     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_AD10, BUSY); \
   6549     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_AD10, RESERVED0); \
   6550     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_AD10, FORCE); \
   6551     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_AD10, RESERVED1); \
   6552     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_AD10, ADJ_EN); \
   6553     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_AD10, RESERVED2); \
   6554     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_AD10, VDL_STEP); \
   6555     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_AD11, BUSY); \
   6556     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_AD11, RESERVED0); \
   6557     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_AD11, FORCE); \
   6558     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_AD11, RESERVED1); \
   6559     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_AD11, ADJ_EN); \
   6560     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_AD11, RESERVED2); \
   6561     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_AD11, VDL_STEP); \
   6562     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_AD12, BUSY); \
   6563     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_AD12, RESERVED0); \
   6564     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_AD12, FORCE); \
   6565     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_AD12, RESERVED1); \
   6566     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_AD12, ADJ_EN); \
   6567     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_AD12, RESERVED2); \
   6568     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_AD12, VDL_STEP); \
   6569     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_AD13, BUSY); \
   6570     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_AD13, RESERVED0); \
   6571     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_AD13, FORCE); \
   6572     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_AD13, RESERVED1); \
   6573     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_AD13, ADJ_EN); \
   6574     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_AD13, RESERVED2); \
   6575     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_AD13, VDL_STEP); \
   6576     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_AD14, BUSY); \
   6577     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_AD14, RESERVED0); \
   6578     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_AD14, FORCE); \
   6579     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_AD14, RESERVED1); \
   6580     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_AD14, ADJ_EN); \
   6581     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_AD14, RESERVED2); \
   6582     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_AD14, VDL_STEP); \
   6583     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_AD15, BUSY); \
   6584     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_AD15, RESERVED0); \
   6585     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_AD15, FORCE); \
   6586     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_AD15, RESERVED1); \
   6587     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_AD15, ADJ_EN); \
   6588     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_AD15, RESERVED2); \
   6589     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_AD15, VDL_STEP); \
   6590     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_BA0, BUSY); \
   6591     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_BA0, RESERVED0); \
   6592     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_BA0, FORCE); \
   6593     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_BA0, RESERVED1); \
   6594     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_BA0, ADJ_EN); \
   6595     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_BA0, RESERVED2); \
   6596     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_BA0, VDL_STEP); \
   6597     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_BA1, BUSY); \
   6598     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_BA1, RESERVED0); \
   6599     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_BA1, FORCE); \
   6600     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_BA1, RESERVED1); \
   6601     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_BA1, ADJ_EN); \
   6602     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_BA1, RESERVED2); \
   6603     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_BA1, VDL_STEP); \
   6604     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_BA2, BUSY); \
   6605     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_BA2, RESERVED0); \
   6606     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_BA2, FORCE); \
   6607     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_BA2, RESERVED1); \
   6608     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_BA2, ADJ_EN); \
   6609     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_BA2, RESERVED2); \
   6610     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_BA2, VDL_STEP); \
   6611     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_AUX0, BUSY); \
   6612     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_AUX0, RESERVED0); \
   6613     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_AUX0, FORCE); \
   6614     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_AUX0, RESERVED1); \
   6615     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_AUX0, ADJ_EN); \
   6616     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_AUX0, RESERVED2); \
   6617     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_AUX0, VDL_STEP); \
   6618     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_AUX1, BUSY); \
   6619     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_AUX1, RESERVED0); \
   6620     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_AUX1, FORCE); \
   6621     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_AUX1, RESERVED1); \
   6622     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_AUX1, ADJ_EN); \
   6623     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_AUX1, RESERVED2); \
   6624     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_AUX1, VDL_STEP); \
   6625     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_AUX2, BUSY); \
   6626     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_AUX2, RESERVED0); \
   6627     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_AUX2, FORCE); \
   6628     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_AUX2, RESERVED1); \
   6629     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_AUX2, ADJ_EN); \
   6630     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_AUX2, RESERVED2); \
   6631     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_AUX2, VDL_STEP); \
   6632     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_CS0, BUSY); \
   6633     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_CS0, RESERVED0); \
   6634     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_CS0, FORCE); \
   6635     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_CS0, RESERVED1); \
   6636     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_CS0, ADJ_EN); \
   6637     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_CS0, RESERVED2); \
   6638     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_CS0, VDL_STEP); \
   6639     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_CS1, BUSY); \
   6640     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_CS1, RESERVED0); \
   6641     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_CS1, FORCE); \
   6642     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_CS1, RESERVED1); \
   6643     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_CS1, ADJ_EN); \
   6644     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_CS1, RESERVED2); \
   6645     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_CS1, VDL_STEP); \
   6646     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_PAR, BUSY); \
   6647     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_PAR, RESERVED0); \
   6648     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_PAR, FORCE); \
   6649     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_PAR, RESERVED1); \
   6650     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_PAR, ADJ_EN); \
   6651     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_PAR, RESERVED2); \
   6652     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_PAR, VDL_STEP); \
   6653     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_RAS_N, BUSY); \
   6654     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_RAS_N, RESERVED0); \
   6655     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_RAS_N, FORCE); \
   6656     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_RAS_N, RESERVED1); \
   6657     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_RAS_N, ADJ_EN); \
   6658     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_RAS_N, RESERVED2); \
   6659     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_RAS_N, VDL_STEP); \
   6660     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_CAS_N, BUSY); \
   6661     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_CAS_N, RESERVED0); \
   6662     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_CAS_N, FORCE); \
   6663     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_CAS_N, RESERVED1); \
   6664     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_CAS_N, ADJ_EN); \
   6665     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_CAS_N, RESERVED2); \
   6666     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_CAS_N, VDL_STEP); \
   6667     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_CKE, BUSY); \
   6668     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_CKE, RESERVED0); \
   6669     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_CKE, FORCE); \
   6670     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_CKE, RESERVED1); \
   6671     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_CKE, ADJ_EN); \
   6672     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_CKE, RESERVED2); \
   6673     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_CKE, VDL_STEP); \
   6674     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_RST_N, BUSY); \
   6675     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_RST_N, RESERVED0); \
   6676     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_RST_N, FORCE); \
   6677     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_RST_N, RESERVED1); \
   6678     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_RST_N, ADJ_EN); \
   6679     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_RST_N, RESERVED2); \
   6680     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_RST_N, VDL_STEP); \
   6681     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_ODT, BUSY); \
   6682     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_ODT, RESERVED0); \
   6683     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_ODT, FORCE); \
   6684     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_ODT, RESERVED1); \
   6685     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_ODT, ADJ_EN); \
   6686     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_ODT, RESERVED2); \
   6687     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_ODT, VDL_STEP); \
   6688     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_WE_N, BUSY); \
   6689     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_WE_N, RESERVED0); \
   6690     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_WE_N, FORCE); \
   6691     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_WE_N, RESERVED1); \
   6692     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_WE_N, ADJ_EN); \
   6693     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_WE_N, RESERVED2); \
   6694     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_WE_N, VDL_STEP); \
   6695     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK, BUSY); \
   6696     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK, RESERVED0); \
   6697     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK, FORCE); \
   6698     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK, RESERVED1); \
   6699     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK, ADJ_EN); \
   6700     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK, RESERVED2); \
   6701     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK, VDL_STEP); \
   6702     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CLK_CONTROL, BUSY); \
   6703     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CLK_CONTROL, RESERVED0); \
   6704     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CLK_CONTROL, FORCE); \
   6705     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CLK_CONTROL, RESERVED1); \
   6706     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CLK_CONTROL, ADJ_EN); \
   6707     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CLK_CONTROL, RESERVED2); \
   6708     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_CLK_CONTROL, VDL_STEP); \
   6709     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_LDE_CONTROL, BUSY); \
   6710     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_LDE_CONTROL, RESERVED0); \
   6711     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_LDE_CONTROL, FORCE); \
   6712     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_LDE_CONTROL, RESERVED1); \
   6713     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_LDE_CONTROL, ADJ_EN); \
   6714     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_LDE_CONTROL, RESERVED2); \
   6715     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VDL_LDE_CONTROL, VDL_STEP); \
   6716     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_CMD_CYC_DLY, RESERVED0); \
   6717     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_CMD_CYC_DLY, CKE); \
   6718     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_CMD_CYC_DLY, WE_N); \
   6719     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_CMD_CYC_DLY, CAS_N); \
   6720     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_CMD_CYC_DLY, RAS_N); \
   6721     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_CMD_CYC_DLY, CS_N); \
   6722     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_UPDATE_VDL, RESERVED0); \
   6723     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_UPDATE_VDL, MODE); \
   6724     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_UPDATE_VDL, RESERVED1); \
   6725     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_UPDATE_VDL, DISABLE_INPUT); \
   6726     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_UPDATE_VDL, ENABLE); \
   6727     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_UPDATE_VDL, SNOOP1_RESERVED0); \
   6728     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_UPDATE_VDL, SNOOP1_MASK); \
   6729     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_UPDATE_VDL, SNOOP1_RESERVED1); \
   6730     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_UPDATE_VDL, SNOOP1_CMD); \
   6731     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_UPDATE_VDL, SNOOP1_RESERVED2); \
   6732     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_UPDATE_VDL, SNOOP1_ENABLE); \
   6733     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_UPDATE_VDL, SNOOP2_RESERVED0); \
   6734     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_UPDATE_VDL, SNOOP2_MASK); \
   6735     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_UPDATE_VDL, SNOOP2_RESERVED1); \
   6736     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_UPDATE_VDL, SNOOP2_CMD); \
   6737     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_UPDATE_VDL, SNOOP2_RESERVED2); \
   6738     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_UPDATE_VDL, SNOOP2_ENABLE); \
   6739     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1, RESERVED0); \
   6740     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1, MASK); \
   6741     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1, RESERVED1); \
   6742     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1, CMD); \
   6743     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1, RESERVED2); \
   6744     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1, ENABLE); \
   6745     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2, RESERVED0); \
   6746     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2, MASK); \
   6747     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2, RESERVED1); \
   6748     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2, CMD); \
   6749     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2, RESERVED2); \
   6750     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2, ENABLE); \
   6751     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_COMMAND_REG1, MCP); \
   6752     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_COMMAND_REG1, CS); \
   6753     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_COMMAND_REG1, AUX); \
   6754     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_COMMAND_REG1, ACT); \
   6755     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_COMMAND_REG1, WE); \
   6756     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_COMMAND_REG1, CAS); \
   6757     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_COMMAND_REG1, RAS); \
   6758     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_COMMAND_REG1, BA); \
   6759     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_COMMAND_REG1, AD); \
   6760     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_COMMAND_AUX_REG1, RESERVED0); \
   6761     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_COMMAND_AUX_REG1, AD16); \
   6762     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_COMMAND_REG2, MCP); \
   6763     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_COMMAND_REG2, CS); \
   6764     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_COMMAND_REG2, AUX); \
   6765     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_COMMAND_REG2, ACT); \
   6766     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_COMMAND_REG2, WE); \
   6767     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_COMMAND_REG2, CAS); \
   6768     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_COMMAND_REG2, RAS); \
   6769     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_COMMAND_REG2, BA); \
   6770     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_COMMAND_REG2, AD); \
   6771     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_COMMAND_AUX_REG2, RESERVED0); \
   6772     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_COMMAND_AUX_REG2, AD16); \
   6773     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_COMMAND_REG3, MCP); \
   6774     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_COMMAND_REG3, CS); \
   6775     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_COMMAND_REG3, AUX); \
   6776     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_COMMAND_REG3, ACT); \
   6777     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_COMMAND_REG3, WE); \
   6778     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_COMMAND_REG3, CAS); \
   6779     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_COMMAND_REG3, RAS); \
   6780     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_COMMAND_REG3, BA); \
   6781     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_COMMAND_REG3, AD); \
   6782     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_COMMAND_AUX_REG3, RESERVED0); \
   6783     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_COMMAND_AUX_REG3, AD16); \
   6784     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_COMMAND_REG4, MCP); \
   6785     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_COMMAND_REG4, CS); \
   6786     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_COMMAND_REG4, AUX); \
   6787     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_COMMAND_REG4, ACT); \
   6788     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_COMMAND_REG4, WE); \
   6789     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_COMMAND_REG4, CAS); \
   6790     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_COMMAND_REG4, RAS); \
   6791     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_COMMAND_REG4, BA); \
   6792     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_COMMAND_REG4, AD); \
   6793     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_COMMAND_AUX_REG4, RESERVED0); \
   6794     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_COMMAND_AUX_REG4, AD16); \
   6795     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_MODE_REG0, RESERVED0); \
   6796     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_MODE_REG0, VALID); \
   6797     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_MODE_REG0, AD); \
   6798     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_MODE_REG1, RESERVED0); \
   6799     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_MODE_REG1, VALID); \
   6800     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_MODE_REG1, AD); \
   6801     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_MODE_REG2, RESERVED0); \
   6802     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_MODE_REG2, VALID); \
   6803     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_MODE_REG2, AD); \
   6804     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_MODE_REG3, RESERVED0); \
   6805     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_MODE_REG3, VALID); \
   6806     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_MODE_REG3, AD); \
   6807     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_MODE_REG4, RESERVED0); \
   6808     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_MODE_REG4, VALID); \
   6809     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_MODE_REG4, AD); \
   6810     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_MODE_REG5, RESERVED0); \
   6811     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_MODE_REG5, VALID); \
   6812     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_MODE_REG5, AD); \
   6813     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_MODE_REG6, RESERVED0); \
   6814     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_MODE_REG6, VALID); \
   6815     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_MODE_REG6, AD); \
   6816     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_MODE_REG7, RESERVED0); \
   6817     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_MODE_REG7, VALID); \
   6818     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_MODE_REG7, AD); \
   6819     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_MODE_REG8, RESERVED0); \
   6820     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_MODE_REG8, VALID); \
   6821     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_MODE_REG8, AD); \
   6822     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_MODE_REG15, RESERVED0); \
   6823     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_MODE_REG15, VALID); \
   6824     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_MODE_REG15, AD); \
   6825     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_MODE_REG63, RESERVED0); \
   6826     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_MODE_REG63, VALID); \
   6827     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_MODE_REG63, AD); \
   6828     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_ALERT_CLEAR, RESERVED0); \
   6829     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_ALERT_CLEAR, CLEAR); \
   6830     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_ALERT_STATUS, RESERVED0); \
   6831     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_ALERT_STATUS, BL3_STATE); \
   6832     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_ALERT_STATUS, BL2_STATE); \
   6833     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_ALERT_STATUS, BL1_STATE); \
   6834     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_ALERT_STATUS, BL0_STATE); \
   6835     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_ALERT_STATUS, RESERVED1); \
   6836     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_ALERT_STATUS, BL3_ALERT); \
   6837     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_ALERT_STATUS, BL2_ALERT); \
   6838     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_ALERT_STATUS, BL1_ALERT); \
   6839     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_ALERT_STATUS, BL0_ALERT); \
   6840     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_ALERT_DFI, RESERVED0); \
   6841     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_ALERT_DFI, MASK); \
   6842     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_CA_PLAYBACK_CONTROL, RESERVED0); \
   6843     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_CA_PLAYBACK_CONTROL, COUNT); \
   6844     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_CA_PLAYBACK_CONTROL, RESERVED1); \
   6845     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_CA_PLAYBACK_CONTROL, SAMPLE); \
   6846     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_CA_PLAYBACK_STATUS0, VALID); \
   6847     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_CA_PLAYBACK_STATUS0, RESERVED0); \
   6848     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_CA_PLAYBACK_STATUS0, DATA1); \
   6849     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_CA_PLAYBACK_STATUS0, RESERVED1); \
   6850     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_CA_PLAYBACK_STATUS0, DATA0); \
   6851     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_CA_PLAYBACK_STATUS1, VALID); \
   6852     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_CA_PLAYBACK_STATUS1, RESERVED0); \
   6853     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_CA_PLAYBACK_STATUS1, DATA1); \
   6854     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_CA_PLAYBACK_STATUS1, RESERVED1); \
   6855     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_CA_PLAYBACK_STATUS1, DATA0); \
   6856     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_WRITE_LEVELING_CONTROL, RESERVED0); \
   6857     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_WRITE_LEVELING_CONTROL, COUNT); \
   6858     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_WRITE_LEVELING_CONTROL, RESERVED1); \
   6859     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_WRITE_LEVELING_CONTROL, SAMPLE); \
   6860     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_WRITE_LEVELING_CONTROL, CONTINUOUS); \
   6861     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_WRITE_LEVELING_CONTROL, ENABLE); \
   6862     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_WRITE_LEVELING_STATUS, RESERVED0); \
   6863     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_WRITE_LEVELING_STATUS, STATUS); \
   6864     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_WRITE_LEVELING_STATUS, RESERVED1); \
   6865     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_WRITE_LEVELING_STATUS, VALID); \
   6866     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_READ_ENABLE_CONTROL, RESERVED0); \
   6867     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_READ_ENABLE_CONTROL, TEST_CYCLE); \
   6868     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_READ_ENABLE_CONTROL, SELECT); \
   6869     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_READ_ENABLE_CONTROL, RESERVED1); \
   6870     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_READ_ENABLE_CONTROL, CS_N); \
   6871     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_READ_ENABLE_CONTROL, RESERVED2); \
   6872     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_READ_ENABLE_CONTROL, DQS); \
   6873     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_READ_ENABLE_CONTROL, ENABLE); \
   6874     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_READ_ENABLE_STATUS, RESERVED0); \
   6875     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_READ_ENABLE_STATUS, DATA); \
   6876     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_READ_ENABLE_STATUS, RESERVED1); \
   6877     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_READ_ENABLE_STATUS, BL3_STATUS); \
   6878     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_READ_ENABLE_STATUS, BL2_STATUS); \
   6879     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_READ_ENABLE_STATUS, BL1_STATUS); \
   6880     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_READ_ENABLE_STATUS, BL0_STATUS); \
   6881     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_READ_ENABLE_STATUS, RESERVED2); \
   6882     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_READ_ENABLE_STATUS, VALID); \
   6883     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL, RESERVED0); \
   6884     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL, RESERVED_FOR_ECO1); \
   6885     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL, MAX_NOISE); \
   6886     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL, LOW_NOISE); \
   6887     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL, LOW_VTT); \
   6888     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL, HIGH_VTT); \
   6889     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL, ERROR_RESET); \
   6890     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL, ENABLE_CTL_IDLE); \
   6891     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL, ENABLE_CS_IDLE); \
   6892     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL, ENABLE_CKE_IDLE); \
   6893     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS, RESERVED0); \
   6894     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS, ERROR); \
   6895     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS, ERROR_LOW); \
   6896     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS, ERROR_HIGH); \
   6897     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS, READY); \
   6898     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VIRTUAL_VTT_CONNECTIONS, RESERVED0); \
   6899     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VIRTUAL_VTT_CONNECTIONS, MASK); \
   6900     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VIRTUAL_VTT_OVERRIDE, RESERVED0); \
   6901     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VIRTUAL_VTT_OVERRIDE, MASK); \
   6902     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VREF_DAC_CONTROL, RESERVED0); \
   6903     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VREF_DAC_CONTROL, AUX_GT_INT); \
   6904     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VREF_DAC_CONTROL, TESTOUT_MUX_CTL); \
   6905     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VREF_DAC_CONTROL, TEST); \
   6906     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VREF_DAC_CONTROL, PDN3); \
   6907     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VREF_DAC_CONTROL, PDN2); \
   6908     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VREF_DAC_CONTROL, PDN1); \
   6909     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VREF_DAC_CONTROL, PDN0); \
   6910     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VREF_DAC_CONTROL, DAC1); \
   6911     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_VREF_DAC_CONTROL, DAC0); \
   6912     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_PHYBIST_CNTRL, RESERVED0); \
   6913     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_PHYBIST_CNTRL, PATTERN_SEL); \
   6914     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_PHYBIST_CNTRL, FORCE_DQ_ERROR_SEL); \
   6915     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_PHYBIST_CNTRL, RESERVED1); \
   6916     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_PHYBIST_CNTRL, FORCE_BL_ERROR_SEL); \
   6917     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_PHYBIST_CNTRL, RESERVED2); \
   6918     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_PHYBIST_CNTRL, FORCE_CTL_ERROR_SEL); \
   6919     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_PHYBIST_CNTRL, RESERVED3); \
   6920     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_PHYBIST_CNTRL, FORCE_DAT_ERROR); \
   6921     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_PHYBIST_CNTRL, FORCE_CTL_ERROR); \
   6922     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_PHYBIST_CNTRL, SSO); \
   6923     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_PHYBIST_CNTRL, LENGTH); \
   6924     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_PHYBIST_CNTRL, MODE); \
   6925     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_PHYBIST_CNTRL, ENABLE); \
   6926     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_PHYBIST_SEED, SEED); \
   6927     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_PHYBIST_CA_MASK, MASK); \
   6928     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_PHYBIST_DQ_MASK1, MASK); \
   6929     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_PHYBIST_DQ_MASK2, RESERVED0); \
   6930     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_PHYBIST_DQ_MASK2, ALERT_MASK); \
   6931     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_PHYBIST_DQ_MASK2, RESERVED1); \
   6932     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_PHYBIST_DQ_MASK2, DM_MASK); \
   6933     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_PHYBIST_DQ_MASK2, RESERVED2); \
   6934     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_PHYBIST_STATUS, RESERVED0); \
   6935     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_PHYBIST_STATUS, DAT_PASS); \
   6936     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_PHYBIST_STATUS, CTL_PASS); \
   6937     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_PHYBIST_STATUS, DAT_DONE); \
   6938     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_PHYBIST_STATUS, CTL_DONE); \
   6939     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_PHYBIST_CTL_STATUS, RESERVED0); \
   6940     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_PHYBIST_CTL_STATUS, CTL_ERRORS); \
   6941     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_PHYBIST_BL0_STATUS, RESERVED0); \
   6942     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_PHYBIST_BL0_STATUS, ALERT); \
   6943     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_PHYBIST_BL0_STATUS, DM); \
   6944     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_PHYBIST_BL0_STATUS, DQ); \
   6945     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_PHYBIST_BL1_STATUS, RESERVED0); \
   6946     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_PHYBIST_BL1_STATUS, ALERT); \
   6947     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_PHYBIST_BL1_STATUS, DM); \
   6948     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_PHYBIST_BL1_STATUS, DQ); \
   6949     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_PHYBIST_BL2_STATUS, RESERVED0); \
   6950     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_PHYBIST_BL2_STATUS, ALERT); \
   6951     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_PHYBIST_BL2_STATUS, DM); \
   6952     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_PHYBIST_BL2_STATUS, DQ); \
   6953     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_PHYBIST_BL3_STATUS, RESERVED0); \
   6954     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_PHYBIST_BL3_STATUS, ALERT); \
   6955     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_PHYBIST_BL3_STATUS, DM); \
   6956     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_PHYBIST_BL3_STATUS, DQ); \
   6957     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_PHYBIST_BL4_STATUS, RESERVED0); \
   6958     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_PHYBIST_BL4_STATUS, ALERT); \
   6959     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_PHYBIST_BL4_STATUS, DM); \
   6960     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_PHYBIST_BL4_STATUS, DQ); \
   6961     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_STANDBY_CONTROL, RESERVED0); \
   6962     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_STANDBY_CONTROL, PHY_STANDBY); \
   6963     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_STANDBY_CONTROL, FORCE_CKE_RST_N); \
   6964     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_STANDBY_CONTROL, RST_N); \
   6965     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_STANDBY_CONTROL, CKE); \
   6966     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_STANDBY_CONTROL, BIT_PIPE_RESET); \
   6967     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE, RESERVED0); \
   6968     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE, WL1_BL1); \
   6969     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE, WL1_BL0); \
   6970     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE, WL0_BL1); \
   6971     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE, WL0_BL0); \
   6972     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_DEBUG_MUX_CONTROL, RESERVED0); \
   6973     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_DEBUG_MUX_CONTROL, BYTE_SEL); \
   6974     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_DEBUG_MUX_CONTROL, RESERVED1); \
   6975     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_DEBUG_MUX_CONTROL, PHASE_SEL); \
   6976     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_DEBUG_MUX_CONTROL, SOURCE_SEL); \
   6977     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_DFI_CNTRL, RESERVED0); \
   6978     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_DFI_CNTRL, SELF_REFRESH); \
   6979     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_DFI_CNTRL, DFI_CS1); \
   6980     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_DFI_CNTRL, DFI_CS0); \
   6981     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_DFI_CNTRL, DFI_RST_N); \
   6982     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_DFI_CNTRL, RESERVED1); \
   6983     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_DFI_CNTRL, DFI_CKE); \
   6984     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_DFI_CNTRL, ACK_ENABLE); \
   6985     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_DFI_CNTRL, ACK_STATUS); \
   6986     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_DFI_CNTRL, ASSERT_REQ); \
   6987     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_WRITE_ODT_CNTRL, RESERVED0); \
   6988     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_WRITE_ODT_CNTRL, ODT1_FORCE_VALUE); \
   6989     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_WRITE_ODT_CNTRL, ODT1_FORCE); \
   6990     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_WRITE_ODT_CNTRL, ODT1_ENABLE); \
   6991     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_WRITE_ODT_CNTRL, ODT1_LENGTH); \
   6992     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_WRITE_ODT_CNTRL, ODT1_DELAY); \
   6993     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_WRITE_ODT_CNTRL, RESERVED1); \
   6994     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_WRITE_ODT_CNTRL, ODT0_FORCE_VALUE); \
   6995     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_WRITE_ODT_CNTRL, ODT0_FORCE); \
   6996     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_WRITE_ODT_CNTRL, ODT0_ENABLE); \
   6997     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_WRITE_ODT_CNTRL, ODT0_LENGTH); \
   6998     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_WRITE_ODT_CNTRL, ODT0_DELAY); \
   6999     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_ABI_PAR_CNTRL, RESERVED0); \
   7000     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_ABI_PAR_CNTRL, PAR_ERROR); \
   7001     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_ABI_PAR_CNTRL, PAR_INCLUDE_AUX); \
   7002     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_ABI_PAR_CNTRL, PAR_ENABLE); \
   7003     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_ABI_PAR_CNTRL, ABI_INCLUDE_AUX); \
   7004     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_ABI_PAR_CNTRL, ABI_ENABLE); \
   7005     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_ZQ_CAL, RESERVED0); \
   7006     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_ZQ_CAL, ZQ_PCOMP_STATUS); \
   7007     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_ZQ_CAL, ZQ_NCOMP_STATUS); \
   7008     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_ZQ_CAL, ZQ_IDDQ); \
   7009     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_ZQ_CAL, ZQ_DRIVE_P); \
   7010     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_ZQ_CAL, ZQ_DRIVE_N); \
   7011     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_ZQ_CAL, RESERVED1); \
   7012     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_ZQ_CAL, ZQ_PCOMP_ENB); \
   7013     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_ZQ_CAL, ZQ_NCOMP_ENB); \
   7014     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_ZQ_CAL2, RESERVED0); \
   7015     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_ZQ_CAL2, ZQ_CAL_RESET); \
   7016     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_ZQ_CAL2, ZQ_CAL_ERROR_N); \
   7017     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_ZQ_CAL2, ZQ_CAL_ERROR_P); \
   7018     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_ZQ_CAL2, ZQ_NSETTING); \
   7019     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_ZQ_CAL2, ZQ_PSETTING); \
   7020     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_ZQ_CAL2, ZQ_CAL_OP_COMPLETE_N); \
   7021     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_ZQ_CAL2, ZQ_CAL_OP_COMPLETE_P); \
   7022     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_ZQ_CAL2, ZQ_CAL_START_N); \
   7023     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_ZQ_CAL2, ZQ_CAL_START_P); \
   7024     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_RO_PROC_MON_CTL, RESERVED0); \
   7025     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_RO_PROC_MON_CTL, BUSY); \
   7026     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_RO_PROC_MON_CTL, TRIGGER); \
   7027     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_RO_PROC_MON_CTL, RESET); \
   7028     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_RO_PROC_MON_CTL, SEL); \
   7029     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_RO_PROC_MON_CTL, EN); \
   7030     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_RO_PROC_MON_STATUS, CLK_COUNT); \
   7031     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_RO_PROC_MON_STATUS, RO_COUNT); \
   7032     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_CK_DRIVE_PAD_CTL, RESERVED0); \
   7033     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_CK_DRIVE_PAD_CTL, ADDR_CTL_PD_IDLE_STRENGTH); \
   7034     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_CK_DRIVE_PAD_CTL, ADDR_CTL_ND_IDLE_STRENGTH); \
   7035     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_CK_DRIVE_PAD_CTL, ADDR_CTL_PD_TERM_STRENGTH); \
   7036     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_CK_DRIVE_PAD_CTL, ADDR_CTL_ND_TERM_STRENGTH); \
   7037     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_CK_DRIVE_PAD_CTL, ADDR_CTL_PD_STRENGTH); \
   7038     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_CK_DRIVE_PAD_CTL, ADDR_CTL_ND_STRENGTH); \
   7039     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_BYTE_LANE_ALIGN_MASKS, RESERVED0); \
   7040     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_BYTE_LANE_ALIGN_MASKS, MASK_ENABLE); \
   7041     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_BYTE_LANE_ALIGN_MASKS, RESERVED1); \
   7042     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_BYTE_LANE_ALIGN_MASKS, BL3_MASK); \
   7043     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_BYTE_LANE_ALIGN_MASKS, BL2_MASK); \
   7044     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_BYTE_LANE_ALIGN_MASKS, BL1_MASK); \
   7045     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_BYTE_LANE_ALIGN_MASKS, BL0_MASK); \
   7046     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_CLOCK_IDLE, RESERVED0); \
   7047     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_CLOCK_IDLE, BIT_CLOCK_CS); \
   7048     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_CLOCK_IDLE, BIT_CLOCK_LS); \
   7049     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_CLOCK_IDLE, TO_MC_CLOCK); \
   7050     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_CLOCK_IDLE, FROM_MC_CLOCK); \
   7051     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_CLOCK_IDLE, BIT_CLOCK); \
   7052     INIT_DDR34_SIGNE_FIELD(F0, PHY_CONTROL_REGS_AC_SPARE_REG, RESERVED_FOR_ECO0); \
   7053     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS, BUSY); \
   7054     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS, RESERVED0); \
   7055     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS, FORCE); \
   7056     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS, RESERVED1); \
   7057     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS, ADJ_EN); \
   7058     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS, RESERVED2); \
   7059     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS, VDL_STEP); \
   7060     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0, BUSY); \
   7061     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0, RESERVED0); \
   7062     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0, FORCE); \
   7063     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0, RESERVED1); \
   7064     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0, ADJ_EN); \
   7065     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0, RESERVED2); \
   7066     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0, VDL_STEP); \
   7067     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1, BUSY); \
   7068     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1, RESERVED0); \
   7069     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1, FORCE); \
   7070     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1, RESERVED1); \
   7071     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1, ADJ_EN); \
   7072     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1, RESERVED2); \
   7073     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1, VDL_STEP); \
   7074     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2, BUSY); \
   7075     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2, RESERVED0); \
   7076     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2, FORCE); \
   7077     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2, RESERVED1); \
   7078     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2, ADJ_EN); \
   7079     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2, RESERVED2); \
   7080     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2, VDL_STEP); \
   7081     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3, BUSY); \
   7082     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3, RESERVED0); \
   7083     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3, FORCE); \
   7084     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3, RESERVED1); \
   7085     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3, ADJ_EN); \
   7086     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3, RESERVED2); \
   7087     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3, VDL_STEP); \
   7088     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4, BUSY); \
   7089     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4, RESERVED0); \
   7090     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4, FORCE); \
   7091     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4, RESERVED1); \
   7092     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4, ADJ_EN); \
   7093     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4, RESERVED2); \
   7094     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4, VDL_STEP); \
   7095     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5, BUSY); \
   7096     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5, RESERVED0); \
   7097     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5, FORCE); \
   7098     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5, RESERVED1); \
   7099     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5, ADJ_EN); \
   7100     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5, RESERVED2); \
   7101     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5, VDL_STEP); \
   7102     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6, BUSY); \
   7103     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6, RESERVED0); \
   7104     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6, FORCE); \
   7105     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6, RESERVED1); \
   7106     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6, ADJ_EN); \
   7107     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6, RESERVED2); \
   7108     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6, VDL_STEP); \
   7109     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7, BUSY); \
   7110     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7, RESERVED0); \
   7111     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7, FORCE); \
   7112     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7, RESERVED1); \
   7113     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7, ADJ_EN); \
   7114     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7, RESERVED2); \
   7115     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7, VDL_STEP); \
   7116     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_DM, BUSY); \
   7117     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_DM, RESERVED0); \
   7118     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_DM, FORCE); \
   7119     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_DM, RESERVED1); \
   7120     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_DM, ADJ_EN); \
   7121     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_DM, RESERVED2); \
   7122     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_DM, VDL_STEP); \
   7123     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_ALERT, BUSY); \
   7124     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_ALERT, RESERVED0); \
   7125     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_ALERT, FORCE); \
   7126     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_ALERT, RESERVED1); \
   7127     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_ALERT, ADJ_EN); \
   7128     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_ALERT, RESERVED2); \
   7129     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_WR_ALERT, VDL_STEP); \
   7130     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSP, BUSY); \
   7131     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSP, RESERVED0); \
   7132     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSP, FORCE); \
   7133     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSP, RESERVED1); \
   7134     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSP, ADJ_EN); \
   7135     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSP, RESERVED2); \
   7136     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSP, VDL_STEP); \
   7137     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSN, BUSY); \
   7138     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSN, RESERVED0); \
   7139     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSN, FORCE); \
   7140     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSN, RESERVED1); \
   7141     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSN, ADJ_EN); \
   7142     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSN, RESERVED2); \
   7143     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSN, VDL_STEP); \
   7144     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0P, BUSY); \
   7145     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0P, RESERVED0); \
   7146     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0P, FORCE); \
   7147     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0P, RESERVED1); \
   7148     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0P, ADJ_EN); \
   7149     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0P, RESERVED2); \
   7150     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0P, VDL_STEP); \
   7151     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0N, BUSY); \
   7152     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0N, RESERVED0); \
   7153     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0N, FORCE); \
   7154     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0N, RESERVED1); \
   7155     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0N, ADJ_EN); \
   7156     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0N, RESERVED2); \
   7157     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0N, VDL_STEP); \
   7158     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1P, BUSY); \
   7159     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1P, RESERVED0); \
   7160     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1P, FORCE); \
   7161     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1P, RESERVED1); \
   7162     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1P, ADJ_EN); \
   7163     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1P, RESERVED2); \
   7164     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1P, VDL_STEP); \
   7165     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1N, BUSY); \
   7166     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1N, RESERVED0); \
   7167     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1N, FORCE); \
   7168     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1N, RESERVED1); \
   7169     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1N, ADJ_EN); \
   7170     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1N, RESERVED2); \
   7171     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1N, VDL_STEP); \
   7172     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2P, BUSY); \
   7173     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2P, RESERVED0); \
   7174     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2P, FORCE); \
   7175     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2P, RESERVED1); \
   7176     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2P, ADJ_EN); \
   7177     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2P, RESERVED2); \
   7178     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2P, VDL_STEP); \
   7179     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2N, BUSY); \
   7180     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2N, RESERVED0); \
   7181     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2N, FORCE); \
   7182     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2N, RESERVED1); \
   7183     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2N, ADJ_EN); \
   7184     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2N, RESERVED2); \
   7185     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2N, VDL_STEP); \
   7186     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3P, BUSY); \
   7187     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3P, RESERVED0); \
   7188     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3P, FORCE); \
   7189     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3P, RESERVED1); \
   7190     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3P, ADJ_EN); \
   7191     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3P, RESERVED2); \
   7192     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3P, VDL_STEP); \
   7193     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3N, BUSY); \
   7194     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3N, RESERVED0); \
   7195     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3N, FORCE); \
   7196     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3N, RESERVED1); \
   7197     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3N, ADJ_EN); \
   7198     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3N, RESERVED2); \
   7199     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3N, VDL_STEP); \
   7200     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4P, BUSY); \
   7201     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4P, RESERVED0); \
   7202     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4P, FORCE); \
   7203     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4P, RESERVED1); \
   7204     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4P, ADJ_EN); \
   7205     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4P, RESERVED2); \
   7206     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4P, VDL_STEP); \
   7207     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4N, BUSY); \
   7208     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4N, RESERVED0); \
   7209     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4N, FORCE); \
   7210     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4N, RESERVED1); \
   7211     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4N, ADJ_EN); \
   7212     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4N, RESERVED2); \
   7213     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4N, VDL_STEP); \
   7214     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5P, BUSY); \
   7215     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5P, RESERVED0); \
   7216     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5P, FORCE); \
   7217     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5P, RESERVED1); \
   7218     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5P, ADJ_EN); \
   7219     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5P, RESERVED2); \
   7220     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5P, VDL_STEP); \
   7221     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5N, BUSY); \
   7222     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5N, RESERVED0); \
   7223     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5N, FORCE); \
   7224     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5N, RESERVED1); \
   7225     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5N, ADJ_EN); \
   7226     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5N, RESERVED2); \
   7227     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5N, VDL_STEP); \
   7228     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6P, BUSY); \
   7229     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6P, RESERVED0); \
   7230     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6P, FORCE); \
   7231     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6P, RESERVED1); \
   7232     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6P, ADJ_EN); \
   7233     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6P, RESERVED2); \
   7234     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6P, VDL_STEP); \
   7235     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6N, BUSY); \
   7236     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6N, RESERVED0); \
   7237     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6N, FORCE); \
   7238     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6N, RESERVED1); \
   7239     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6N, ADJ_EN); \
   7240     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6N, RESERVED2); \
   7241     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6N, VDL_STEP); \
   7242     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7P, BUSY); \
   7243     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7P, RESERVED0); \
   7244     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7P, FORCE); \
   7245     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7P, RESERVED1); \
   7246     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7P, ADJ_EN); \
   7247     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7P, RESERVED2); \
   7248     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7P, VDL_STEP); \
   7249     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7N, BUSY); \
   7250     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7N, RESERVED0); \
   7251     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7N, FORCE); \
   7252     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7N, RESERVED1); \
   7253     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7N, ADJ_EN); \
   7254     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7N, RESERVED2); \
   7255     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7N, VDL_STEP); \
   7256     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMP, BUSY); \
   7257     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMP, RESERVED0); \
   7258     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMP, FORCE); \
   7259     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMP, RESERVED1); \
   7260     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMP, ADJ_EN); \
   7261     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMP, RESERVED2); \
   7262     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMP, VDL_STEP); \
   7263     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMN, BUSY); \
   7264     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMN, RESERVED0); \
   7265     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMN, FORCE); \
   7266     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMN, RESERVED1); \
   7267     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMN, ADJ_EN); \
   7268     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMN, RESERVED2); \
   7269     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMN, VDL_STEP); \
   7270     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0, BUSY); \
   7271     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0, RESERVED0); \
   7272     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0, FORCE); \
   7273     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0, RESERVED1); \
   7274     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0, ADJ_EN); \
   7275     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0, RESERVED2); \
   7276     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0, VDL_STEP); \
   7277     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1, BUSY); \
   7278     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1, RESERVED0); \
   7279     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1, FORCE); \
   7280     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1, RESERVED1); \
   7281     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1, ADJ_EN); \
   7282     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1, RESERVED2); \
   7283     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1, VDL_STEP); \
   7284     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CLK_CONTROL, BUSY); \
   7285     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CLK_CONTROL, RESERVED0); \
   7286     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CLK_CONTROL, FORCE); \
   7287     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CLK_CONTROL, RESERVED1); \
   7288     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CLK_CONTROL, ADJ_EN); \
   7289     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CLK_CONTROL, RESERVED2); \
   7290     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_CLK_CONTROL, VDL_STEP); \
   7291     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_LDE_CONTROL, BUSY); \
   7292     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_LDE_CONTROL, RESERVED0); \
   7293     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_LDE_CONTROL, FORCE); \
   7294     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_LDE_CONTROL, RESERVED1); \
   7295     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_LDE_CONTROL, ADJ_EN); \
   7296     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_LDE_CONTROL, RESERVED2); \
   7297     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_VDL_LDE_CONTROL, VDL_STEP); \
   7298     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_RD_EN_DLY_CYC, BUSY); \
   7299     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_RD_EN_DLY_CYC, RESERVED0); \
   7300     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_RD_EN_DLY_CYC, FORCE); \
   7301     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_RD_EN_DLY_CYC, RESERVED1); \
   7302     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_RD_EN_DLY_CYC, ENABLE_CS1); \
   7303     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_RD_EN_DLY_CYC, CS1_CYCLES); \
   7304     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_RD_EN_DLY_CYC, CS0_CYCLES); \
   7305     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_WR_CHAN_DLY_CYC, BUSY); \
   7306     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_WR_CHAN_DLY_CYC, RESERVED0); \
   7307     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_WR_CHAN_DLY_CYC, FORCE); \
   7308     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_WR_CHAN_DLY_CYC, RESERVED1); \
   7309     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_WR_CHAN_DLY_CYC, DQ_CYCLES); \
   7310     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_WR_CHAN_DLY_CYC, RESERVED2); \
   7311     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_WR_CHAN_DLY_CYC, CYCLES); \
   7312     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_READ_CONTROL, RESERVED0); \
   7313     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_READ_CONTROL, MODE); \
   7314     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_READ_CONTROL, RD_EN_MODE); \
   7315     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_READ_CONTROL, RD_DATA_DLY); \
   7316     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_READ_FIFO_ADDR, RESERVED0); \
   7317     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_READ_FIFO_ADDR, ADDR); \
   7318     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_READ_FIFO_DATA, DATA); \
   7319     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_READ_FIFO_DM_DBI, RESERVED0); \
   7320     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_READ_FIFO_DM_DBI, DM_DBI); \
   7321     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_READ_FIFO_STATUS, RESERVED0); \
   7322     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_READ_FIFO_STATUS, OVERFLOW); \
   7323     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_READ_FIFO_STATUS, UNDERFLOW); \
   7324     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_READ_FIFO_CLEAR, RESERVED0); \
   7325     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_READ_FIFO_CLEAR, CLEAR); \
   7326     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_IDLE_PAD_CONTROL, IDLE); \
   7327     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_IDLE_PAD_CONTROL, RESERVED0); \
   7328     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_IDLE_PAD_CONTROL, AUTO_DQ_RXENB_MODE); \
   7329     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_IDLE_PAD_CONTROL, AUTO_DQ_IDDQ_MODE); \
   7330     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_IDLE_PAD_CONTROL, IO_IDLE_ENABLE); \
   7331     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_IDLE_PAD_CONTROL, RXENB); \
   7332     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_IDLE_PAD_CONTROL, IDDQ); \
   7333     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_IDLE_PAD_CONTROL, DOUT_N); \
   7334     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_IDLE_PAD_CONTROL, DOUT_P); \
   7335     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_DRIVE_PAD_CTL, RESERVED0); \
   7336     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_DRIVE_PAD_CTL, BL_PD_TERM_STRENGTH); \
   7337     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_DRIVE_PAD_CTL, BL_ND_TERM_STRENGTH); \
   7338     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_DRIVE_PAD_CTL, BL_PD_STRENGTH); \
   7339     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_DRIVE_PAD_CTL, BL_ND_STRENGTH); \
   7340     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_DQSP_DRIVE_PAD_CTL, RESERVED0); \
   7341     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_DQSP_DRIVE_PAD_CTL, BL_PD_TERM_STRENGTH); \
   7342     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_DQSP_DRIVE_PAD_CTL, BL_ND_TERM_STRENGTH); \
   7343     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_DQSP_DRIVE_PAD_CTL, BL_PD_STRENGTH); \
   7344     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_DQSP_DRIVE_PAD_CTL, BL_ND_STRENGTH); \
   7345     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_DQSN_DRIVE_PAD_CTL, RESERVED0); \
   7346     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_DQSN_DRIVE_PAD_CTL, BL_PD_TERM_STRENGTH); \
   7347     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_DQSN_DRIVE_PAD_CTL, BL_ND_TERM_STRENGTH); \
   7348     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_DQSN_DRIVE_PAD_CTL, BL_PD_STRENGTH); \
   7349     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_DQSN_DRIVE_PAD_CTL, BL_ND_STRENGTH); \
   7350     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_ALERT_DRIVE_PAD_CTL, RESERVED0); \
   7351     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_ALERT_DRIVE_PAD_CTL, BL_PD_TERM_STRENGTH); \
   7352     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_ALERT_DRIVE_PAD_CTL, BL_ND_TERM_STRENGTH); \
   7353     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_ALERT_DRIVE_PAD_CTL, BL_PD_STRENGTH); \
   7354     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_ALERT_DRIVE_PAD_CTL, BL_ND_STRENGTH); \
   7355     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_RD_EN_DRIVE_PAD_CTL, RESERVED0); \
   7356     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_RD_EN_DRIVE_PAD_CTL, BL_RD_EN_PD_STRENGTH); \
   7357     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_RD_EN_DRIVE_PAD_CTL, BL_RD_EN_ND_STRENGTH); \
   7358     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_STATIC_PAD_CTL, RESERVED0); \
   7359     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_STATIC_PAD_CTL, DM_INVERT); \
   7360     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_STATIC_PAD_CTL, WDBI_ENABLE); \
   7361     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_STATIC_PAD_CTL, RDBI_ENABLE); \
   7362     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_STATIC_PAD_CTL, DM_MODE); \
   7363     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_STATIC_PAD_CTL, RESERVED1); \
   7364     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_STATIC_PAD_CTL, DQS_TX_DIS); \
   7365     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_STATIC_PAD_CTL, RESERVED2); \
   7366     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_STATIC_PAD_CTL, RX_MODE); \
   7367     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_WR_PREAMBLE_MODE, RESERVED0); \
   7368     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_WR_PREAMBLE_MODE, POSTAM_TERM_BITS); \
   7369     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_WR_PREAMBLE_MODE, DM_POSTAM_BITS); \
   7370     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_WR_PREAMBLE_MODE, DM_PREAM_BITS); \
   7371     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_WR_PREAMBLE_MODE, DQ_POSTAM_BITS); \
   7372     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_WR_PREAMBLE_MODE, DQ_PREAM_BITS); \
   7373     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_WR_PREAMBLE_MODE, DQS); \
   7374     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_WR_PREAMBLE_MODE, DQS_POSTAM_BITS); \
   7375     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_WR_PREAMBLE_MODE, DQS_PREAM_BITS); \
   7376     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_ODT_CONTROL, RESERVED0); \
   7377     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_ODT_CONTROL, ODT_ENABLE); \
   7378     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_ODT_CONTROL, ODT_DELAY); \
   7379     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_ODT_CONTROL, ODT_POST_LENGTH); \
   7380     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_ODT_CONTROL, RESERVED1); \
   7381     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_ODT_CONTROL, ODT_PRE_LENGTH); \
   7382     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_CLOCK_ENABLE, RESERVED0); \
   7383     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_CLOCK_ENABLE, TO_MC_CLOCK); \
   7384     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_CLOCK_ENABLE, FROM_MC_CLOCK); \
   7385     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_CLOCK_ENABLE, BIT_CLOCK); \
   7386     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_CLOCK_IDLE, RESERVED0); \
   7387     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_CLOCK_IDLE, TO_MC_CLOCK); \
   7388     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_CLOCK_IDLE, FROM_MC_CLOCK); \
   7389     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_CLOCK_IDLE, BIT_CLOCK); \
   7390     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_0_BL_SPARE_REG, RESERVED_FOR_ECO0); \
   7391     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS, BUSY); \
   7392     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS, RESERVED0); \
   7393     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS, FORCE); \
   7394     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS, RESERVED1); \
   7395     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS, ADJ_EN); \
   7396     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS, RESERVED2); \
   7397     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS, VDL_STEP); \
   7398     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0, BUSY); \
   7399     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0, RESERVED0); \
   7400     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0, FORCE); \
   7401     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0, RESERVED1); \
   7402     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0, ADJ_EN); \
   7403     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0, RESERVED2); \
   7404     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0, VDL_STEP); \
   7405     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1, BUSY); \
   7406     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1, RESERVED0); \
   7407     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1, FORCE); \
   7408     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1, RESERVED1); \
   7409     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1, ADJ_EN); \
   7410     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1, RESERVED2); \
   7411     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1, VDL_STEP); \
   7412     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2, BUSY); \
   7413     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2, RESERVED0); \
   7414     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2, FORCE); \
   7415     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2, RESERVED1); \
   7416     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2, ADJ_EN); \
   7417     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2, RESERVED2); \
   7418     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2, VDL_STEP); \
   7419     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3, BUSY); \
   7420     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3, RESERVED0); \
   7421     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3, FORCE); \
   7422     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3, RESERVED1); \
   7423     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3, ADJ_EN); \
   7424     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3, RESERVED2); \
   7425     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3, VDL_STEP); \
   7426     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4, BUSY); \
   7427     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4, RESERVED0); \
   7428     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4, FORCE); \
   7429     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4, RESERVED1); \
   7430     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4, ADJ_EN); \
   7431     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4, RESERVED2); \
   7432     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4, VDL_STEP); \
   7433     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5, BUSY); \
   7434     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5, RESERVED0); \
   7435     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5, FORCE); \
   7436     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5, RESERVED1); \
   7437     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5, ADJ_EN); \
   7438     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5, RESERVED2); \
   7439     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5, VDL_STEP); \
   7440     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6, BUSY); \
   7441     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6, RESERVED0); \
   7442     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6, FORCE); \
   7443     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6, RESERVED1); \
   7444     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6, ADJ_EN); \
   7445     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6, RESERVED2); \
   7446     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6, VDL_STEP); \
   7447     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7, BUSY); \
   7448     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7, RESERVED0); \
   7449     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7, FORCE); \
   7450     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7, RESERVED1); \
   7451     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7, ADJ_EN); \
   7452     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7, RESERVED2); \
   7453     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7, VDL_STEP); \
   7454     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_DM, BUSY); \
   7455     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_DM, RESERVED0); \
   7456     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_DM, FORCE); \
   7457     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_DM, RESERVED1); \
   7458     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_DM, ADJ_EN); \
   7459     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_DM, RESERVED2); \
   7460     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_DM, VDL_STEP); \
   7461     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_ALERT, BUSY); \
   7462     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_ALERT, RESERVED0); \
   7463     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_ALERT, FORCE); \
   7464     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_ALERT, RESERVED1); \
   7465     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_ALERT, ADJ_EN); \
   7466     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_ALERT, RESERVED2); \
   7467     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_WR_ALERT, VDL_STEP); \
   7468     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSP, BUSY); \
   7469     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSP, RESERVED0); \
   7470     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSP, FORCE); \
   7471     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSP, RESERVED1); \
   7472     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSP, ADJ_EN); \
   7473     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSP, RESERVED2); \
   7474     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSP, VDL_STEP); \
   7475     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSN, BUSY); \
   7476     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSN, RESERVED0); \
   7477     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSN, FORCE); \
   7478     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSN, RESERVED1); \
   7479     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSN, ADJ_EN); \
   7480     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSN, RESERVED2); \
   7481     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSN, VDL_STEP); \
   7482     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0P, BUSY); \
   7483     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0P, RESERVED0); \
   7484     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0P, FORCE); \
   7485     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0P, RESERVED1); \
   7486     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0P, ADJ_EN); \
   7487     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0P, RESERVED2); \
   7488     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0P, VDL_STEP); \
   7489     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0N, BUSY); \
   7490     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0N, RESERVED0); \
   7491     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0N, FORCE); \
   7492     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0N, RESERVED1); \
   7493     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0N, ADJ_EN); \
   7494     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0N, RESERVED2); \
   7495     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0N, VDL_STEP); \
   7496     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1P, BUSY); \
   7497     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1P, RESERVED0); \
   7498     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1P, FORCE); \
   7499     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1P, RESERVED1); \
   7500     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1P, ADJ_EN); \
   7501     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1P, RESERVED2); \
   7502     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1P, VDL_STEP); \
   7503     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1N, BUSY); \
   7504     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1N, RESERVED0); \
   7505     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1N, FORCE); \
   7506     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1N, RESERVED1); \
   7507     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1N, ADJ_EN); \
   7508     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1N, RESERVED2); \
   7509     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1N, VDL_STEP); \
   7510     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2P, BUSY); \
   7511     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2P, RESERVED0); \
   7512     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2P, FORCE); \
   7513     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2P, RESERVED1); \
   7514     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2P, ADJ_EN); \
   7515     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2P, RESERVED2); \
   7516     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2P, VDL_STEP); \
   7517     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2N, BUSY); \
   7518     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2N, RESERVED0); \
   7519     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2N, FORCE); \
   7520     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2N, RESERVED1); \
   7521     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2N, ADJ_EN); \
   7522     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2N, RESERVED2); \
   7523     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2N, VDL_STEP); \
   7524     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3P, BUSY); \
   7525     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3P, RESERVED0); \
   7526     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3P, FORCE); \
   7527     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3P, RESERVED1); \
   7528     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3P, ADJ_EN); \
   7529     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3P, RESERVED2); \
   7530     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3P, VDL_STEP); \
   7531     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3N, BUSY); \
   7532     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3N, RESERVED0); \
   7533     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3N, FORCE); \
   7534     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3N, RESERVED1); \
   7535     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3N, ADJ_EN); \
   7536     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3N, RESERVED2); \
   7537     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3N, VDL_STEP); \
   7538     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4P, BUSY); \
   7539     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4P, RESERVED0); \
   7540     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4P, FORCE); \
   7541     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4P, RESERVED1); \
   7542     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4P, ADJ_EN); \
   7543     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4P, RESERVED2); \
   7544     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4P, VDL_STEP); \
   7545     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4N, BUSY); \
   7546     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4N, RESERVED0); \
   7547     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4N, FORCE); \
   7548     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4N, RESERVED1); \
   7549     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4N, ADJ_EN); \
   7550     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4N, RESERVED2); \
   7551     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4N, VDL_STEP); \
   7552     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5P, BUSY); \
   7553     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5P, RESERVED0); \
   7554     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5P, FORCE); \
   7555     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5P, RESERVED1); \
   7556     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5P, ADJ_EN); \
   7557     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5P, RESERVED2); \
   7558     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5P, VDL_STEP); \
   7559     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5N, BUSY); \
   7560     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5N, RESERVED0); \
   7561     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5N, FORCE); \
   7562     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5N, RESERVED1); \
   7563     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5N, ADJ_EN); \
   7564     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5N, RESERVED2); \
   7565     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5N, VDL_STEP); \
   7566     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6P, BUSY); \
   7567     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6P, RESERVED0); \
   7568     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6P, FORCE); \
   7569     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6P, RESERVED1); \
   7570     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6P, ADJ_EN); \
   7571     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6P, RESERVED2); \
   7572     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6P, VDL_STEP); \
   7573     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6N, BUSY); \
   7574     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6N, RESERVED0); \
   7575     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6N, FORCE); \
   7576     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6N, RESERVED1); \
   7577     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6N, ADJ_EN); \
   7578     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6N, RESERVED2); \
   7579     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6N, VDL_STEP); \
   7580     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7P, BUSY); \
   7581     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7P, RESERVED0); \
   7582     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7P, FORCE); \
   7583     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7P, RESERVED1); \
   7584     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7P, ADJ_EN); \
   7585     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7P, RESERVED2); \
   7586     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7P, VDL_STEP); \
   7587     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7N, BUSY); \
   7588     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7N, RESERVED0); \
   7589     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7N, FORCE); \
   7590     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7N, RESERVED1); \
   7591     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7N, ADJ_EN); \
   7592     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7N, RESERVED2); \
   7593     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7N, VDL_STEP); \
   7594     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMP, BUSY); \
   7595     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMP, RESERVED0); \
   7596     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMP, FORCE); \
   7597     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMP, RESERVED1); \
   7598     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMP, ADJ_EN); \
   7599     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMP, RESERVED2); \
   7600     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMP, VDL_STEP); \
   7601     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMN, BUSY); \
   7602     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMN, RESERVED0); \
   7603     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMN, FORCE); \
   7604     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMN, RESERVED1); \
   7605     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMN, ADJ_EN); \
   7606     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMN, RESERVED2); \
   7607     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMN, VDL_STEP); \
   7608     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0, BUSY); \
   7609     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0, RESERVED0); \
   7610     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0, FORCE); \
   7611     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0, RESERVED1); \
   7612     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0, ADJ_EN); \
   7613     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0, RESERVED2); \
   7614     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0, VDL_STEP); \
   7615     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1, BUSY); \
   7616     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1, RESERVED0); \
   7617     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1, FORCE); \
   7618     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1, RESERVED1); \
   7619     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1, ADJ_EN); \
   7620     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1, RESERVED2); \
   7621     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1, VDL_STEP); \
   7622     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CLK_CONTROL, BUSY); \
   7623     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CLK_CONTROL, RESERVED0); \
   7624     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CLK_CONTROL, FORCE); \
   7625     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CLK_CONTROL, RESERVED1); \
   7626     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CLK_CONTROL, ADJ_EN); \
   7627     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CLK_CONTROL, RESERVED2); \
   7628     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_CLK_CONTROL, VDL_STEP); \
   7629     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_LDE_CONTROL, BUSY); \
   7630     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_LDE_CONTROL, RESERVED0); \
   7631     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_LDE_CONTROL, FORCE); \
   7632     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_LDE_CONTROL, RESERVED1); \
   7633     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_LDE_CONTROL, ADJ_EN); \
   7634     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_LDE_CONTROL, RESERVED2); \
   7635     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_VDL_LDE_CONTROL, VDL_STEP); \
   7636     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_RD_EN_DLY_CYC, BUSY); \
   7637     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_RD_EN_DLY_CYC, RESERVED0); \
   7638     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_RD_EN_DLY_CYC, FORCE); \
   7639     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_RD_EN_DLY_CYC, RESERVED1); \
   7640     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_RD_EN_DLY_CYC, ENABLE_CS1); \
   7641     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_RD_EN_DLY_CYC, CS1_CYCLES); \
   7642     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_RD_EN_DLY_CYC, CS0_CYCLES); \
   7643     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_WR_CHAN_DLY_CYC, BUSY); \
   7644     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_WR_CHAN_DLY_CYC, RESERVED0); \
   7645     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_WR_CHAN_DLY_CYC, FORCE); \
   7646     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_WR_CHAN_DLY_CYC, RESERVED1); \
   7647     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_WR_CHAN_DLY_CYC, DQ_CYCLES); \
   7648     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_WR_CHAN_DLY_CYC, RESERVED2); \
   7649     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_WR_CHAN_DLY_CYC, CYCLES); \
   7650     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_READ_CONTROL, RESERVED0); \
   7651     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_READ_CONTROL, MODE); \
   7652     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_READ_CONTROL, RD_EN_MODE); \
   7653     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_READ_CONTROL, RD_DATA_DLY); \
   7654     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_READ_FIFO_ADDR, RESERVED0); \
   7655     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_READ_FIFO_ADDR, ADDR); \
   7656     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_READ_FIFO_DATA, DATA); \
   7657     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_READ_FIFO_DM_DBI, RESERVED0); \
   7658     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_READ_FIFO_DM_DBI, DM_DBI); \
   7659     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_READ_FIFO_STATUS, RESERVED0); \
   7660     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_READ_FIFO_STATUS, OVERFLOW); \
   7661     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_READ_FIFO_STATUS, UNDERFLOW); \
   7662     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_READ_FIFO_CLEAR, RESERVED0); \
   7663     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_READ_FIFO_CLEAR, CLEAR); \
   7664     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_IDLE_PAD_CONTROL, IDLE); \
   7665     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_IDLE_PAD_CONTROL, RESERVED0); \
   7666     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_IDLE_PAD_CONTROL, AUTO_DQ_RXENB_MODE); \
   7667     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_IDLE_PAD_CONTROL, AUTO_DQ_IDDQ_MODE); \
   7668     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_IDLE_PAD_CONTROL, IO_IDLE_ENABLE); \
   7669     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_IDLE_PAD_CONTROL, RXENB); \
   7670     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_IDLE_PAD_CONTROL, IDDQ); \
   7671     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_IDLE_PAD_CONTROL, DOUT_N); \
   7672     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_IDLE_PAD_CONTROL, DOUT_P); \
   7673     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_DRIVE_PAD_CTL, RESERVED0); \
   7674     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_DRIVE_PAD_CTL, BL_PD_TERM_STRENGTH); \
   7675     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_DRIVE_PAD_CTL, BL_ND_TERM_STRENGTH); \
   7676     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_DRIVE_PAD_CTL, BL_PD_STRENGTH); \
   7677     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_DRIVE_PAD_CTL, BL_ND_STRENGTH); \
   7678     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_DQSP_DRIVE_PAD_CTL, RESERVED0); \
   7679     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_DQSP_DRIVE_PAD_CTL, BL_PD_TERM_STRENGTH); \
   7680     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_DQSP_DRIVE_PAD_CTL, BL_ND_TERM_STRENGTH); \
   7681     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_DQSP_DRIVE_PAD_CTL, BL_PD_STRENGTH); \
   7682     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_DQSP_DRIVE_PAD_CTL, BL_ND_STRENGTH); \
   7683     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_DQSN_DRIVE_PAD_CTL, RESERVED0); \
   7684     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_DQSN_DRIVE_PAD_CTL, BL_PD_TERM_STRENGTH); \
   7685     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_DQSN_DRIVE_PAD_CTL, BL_ND_TERM_STRENGTH); \
   7686     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_DQSN_DRIVE_PAD_CTL, BL_PD_STRENGTH); \
   7687     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_DQSN_DRIVE_PAD_CTL, BL_ND_STRENGTH); \
   7688     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_ALERT_DRIVE_PAD_CTL, RESERVED0); \
   7689     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_ALERT_DRIVE_PAD_CTL, BL_PD_TERM_STRENGTH); \
   7690     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_ALERT_DRIVE_PAD_CTL, BL_ND_TERM_STRENGTH); \
   7691     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_ALERT_DRIVE_PAD_CTL, BL_PD_STRENGTH); \
   7692     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_ALERT_DRIVE_PAD_CTL, BL_ND_STRENGTH); \
   7693     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_RD_EN_DRIVE_PAD_CTL, RESERVED0); \
   7694     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_RD_EN_DRIVE_PAD_CTL, BL_RD_EN_PD_STRENGTH); \
   7695     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_RD_EN_DRIVE_PAD_CTL, BL_RD_EN_ND_STRENGTH); \
   7696     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_STATIC_PAD_CTL, RESERVED0); \
   7697     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_STATIC_PAD_CTL, DM_INVERT); \
   7698     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_STATIC_PAD_CTL, WDBI_ENABLE); \
   7699     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_STATIC_PAD_CTL, RDBI_ENABLE); \
   7700     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_STATIC_PAD_CTL, DM_MODE); \
   7701     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_STATIC_PAD_CTL, RESERVED1); \
   7702     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_STATIC_PAD_CTL, DQS_TX_DIS); \
   7703     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_STATIC_PAD_CTL, RESERVED2); \
   7704     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_STATIC_PAD_CTL, RX_MODE); \
   7705     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_WR_PREAMBLE_MODE, RESERVED0); \
   7706     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_WR_PREAMBLE_MODE, POSTAM_TERM_BITS); \
   7707     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_WR_PREAMBLE_MODE, DM_POSTAM_BITS); \
   7708     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_WR_PREAMBLE_MODE, DM_PREAM_BITS); \
   7709     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_WR_PREAMBLE_MODE, DQ_POSTAM_BITS); \
   7710     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_WR_PREAMBLE_MODE, DQ_PREAM_BITS); \
   7711     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_WR_PREAMBLE_MODE, DQS); \
   7712     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_WR_PREAMBLE_MODE, DQS_POSTAM_BITS); \
   7713     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_WR_PREAMBLE_MODE, DQS_PREAM_BITS); \
   7714     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_ODT_CONTROL, RESERVED0); \
   7715     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_ODT_CONTROL, ODT_ENABLE); \
   7716     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_ODT_CONTROL, ODT_DELAY); \
   7717     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_ODT_CONTROL, ODT_POST_LENGTH); \
   7718     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_ODT_CONTROL, RESERVED1); \
   7719     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_ODT_CONTROL, ODT_PRE_LENGTH); \
   7720     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_CLOCK_ENABLE, RESERVED0); \
   7721     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_CLOCK_ENABLE, TO_MC_CLOCK); \
   7722     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_CLOCK_ENABLE, FROM_MC_CLOCK); \
   7723     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_CLOCK_ENABLE, BIT_CLOCK); \
   7724     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_CLOCK_IDLE, RESERVED0); \
   7725     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_CLOCK_IDLE, TO_MC_CLOCK); \
   7726     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_CLOCK_IDLE, FROM_MC_CLOCK); \
   7727     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_CLOCK_IDLE, BIT_CLOCK); \
   7728     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_1_BL_SPARE_REG, RESERVED_FOR_ECO0); \
   7729     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS, BUSY); \
   7730     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS, RESERVED0); \
   7731     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS, FORCE); \
   7732     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS, RESERVED1); \
   7733     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS, ADJ_EN); \
   7734     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS, RESERVED2); \
   7735     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS, VDL_STEP); \
   7736     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ0, BUSY); \
   7737     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ0, RESERVED0); \
   7738     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ0, FORCE); \
   7739     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ0, RESERVED1); \
   7740     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ0, ADJ_EN); \
   7741     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ0, RESERVED2); \
   7742     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ0, VDL_STEP); \
   7743     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ1, BUSY); \
   7744     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ1, RESERVED0); \
   7745     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ1, FORCE); \
   7746     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ1, RESERVED1); \
   7747     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ1, ADJ_EN); \
   7748     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ1, RESERVED2); \
   7749     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ1, VDL_STEP); \
   7750     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ2, BUSY); \
   7751     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ2, RESERVED0); \
   7752     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ2, FORCE); \
   7753     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ2, RESERVED1); \
   7754     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ2, ADJ_EN); \
   7755     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ2, RESERVED2); \
   7756     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ2, VDL_STEP); \
   7757     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ3, BUSY); \
   7758     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ3, RESERVED0); \
   7759     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ3, FORCE); \
   7760     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ3, RESERVED1); \
   7761     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ3, ADJ_EN); \
   7762     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ3, RESERVED2); \
   7763     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ3, VDL_STEP); \
   7764     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ4, BUSY); \
   7765     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ4, RESERVED0); \
   7766     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ4, FORCE); \
   7767     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ4, RESERVED1); \
   7768     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ4, ADJ_EN); \
   7769     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ4, RESERVED2); \
   7770     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ4, VDL_STEP); \
   7771     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ5, BUSY); \
   7772     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ5, RESERVED0); \
   7773     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ5, FORCE); \
   7774     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ5, RESERVED1); \
   7775     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ5, ADJ_EN); \
   7776     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ5, RESERVED2); \
   7777     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ5, VDL_STEP); \
   7778     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ6, BUSY); \
   7779     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ6, RESERVED0); \
   7780     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ6, FORCE); \
   7781     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ6, RESERVED1); \
   7782     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ6, ADJ_EN); \
   7783     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ6, RESERVED2); \
   7784     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ6, VDL_STEP); \
   7785     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ7, BUSY); \
   7786     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ7, RESERVED0); \
   7787     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ7, FORCE); \
   7788     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ7, RESERVED1); \
   7789     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ7, ADJ_EN); \
   7790     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ7, RESERVED2); \
   7791     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ7, VDL_STEP); \
   7792     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_DM, BUSY); \
   7793     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_DM, RESERVED0); \
   7794     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_DM, FORCE); \
   7795     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_DM, RESERVED1); \
   7796     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_DM, ADJ_EN); \
   7797     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_DM, RESERVED2); \
   7798     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_DM, VDL_STEP); \
   7799     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_ALERT, BUSY); \
   7800     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_ALERT, RESERVED0); \
   7801     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_ALERT, FORCE); \
   7802     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_ALERT, RESERVED1); \
   7803     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_ALERT, ADJ_EN); \
   7804     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_ALERT, RESERVED2); \
   7805     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_WR_ALERT, VDL_STEP); \
   7806     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSP, BUSY); \
   7807     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSP, RESERVED0); \
   7808     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSP, FORCE); \
   7809     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSP, RESERVED1); \
   7810     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSP, ADJ_EN); \
   7811     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSP, RESERVED2); \
   7812     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSP, VDL_STEP); \
   7813     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSN, BUSY); \
   7814     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSN, RESERVED0); \
   7815     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSN, FORCE); \
   7816     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSN, RESERVED1); \
   7817     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSN, ADJ_EN); \
   7818     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSN, RESERVED2); \
   7819     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSN, VDL_STEP); \
   7820     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0P, BUSY); \
   7821     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0P, RESERVED0); \
   7822     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0P, FORCE); \
   7823     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0P, RESERVED1); \
   7824     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0P, ADJ_EN); \
   7825     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0P, RESERVED2); \
   7826     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0P, VDL_STEP); \
   7827     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0N, BUSY); \
   7828     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0N, RESERVED0); \
   7829     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0N, FORCE); \
   7830     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0N, RESERVED1); \
   7831     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0N, ADJ_EN); \
   7832     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0N, RESERVED2); \
   7833     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0N, VDL_STEP); \
   7834     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1P, BUSY); \
   7835     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1P, RESERVED0); \
   7836     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1P, FORCE); \
   7837     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1P, RESERVED1); \
   7838     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1P, ADJ_EN); \
   7839     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1P, RESERVED2); \
   7840     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1P, VDL_STEP); \
   7841     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1N, BUSY); \
   7842     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1N, RESERVED0); \
   7843     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1N, FORCE); \
   7844     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1N, RESERVED1); \
   7845     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1N, ADJ_EN); \
   7846     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1N, RESERVED2); \
   7847     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1N, VDL_STEP); \
   7848     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2P, BUSY); \
   7849     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2P, RESERVED0); \
   7850     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2P, FORCE); \
   7851     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2P, RESERVED1); \
   7852     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2P, ADJ_EN); \
   7853     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2P, RESERVED2); \
   7854     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2P, VDL_STEP); \
   7855     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2N, BUSY); \
   7856     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2N, RESERVED0); \
   7857     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2N, FORCE); \
   7858     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2N, RESERVED1); \
   7859     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2N, ADJ_EN); \
   7860     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2N, RESERVED2); \
   7861     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2N, VDL_STEP); \
   7862     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3P, BUSY); \
   7863     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3P, RESERVED0); \
   7864     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3P, FORCE); \
   7865     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3P, RESERVED1); \
   7866     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3P, ADJ_EN); \
   7867     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3P, RESERVED2); \
   7868     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3P, VDL_STEP); \
   7869     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3N, BUSY); \
   7870     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3N, RESERVED0); \
   7871     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3N, FORCE); \
   7872     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3N, RESERVED1); \
   7873     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3N, ADJ_EN); \
   7874     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3N, RESERVED2); \
   7875     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3N, VDL_STEP); \
   7876     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4P, BUSY); \
   7877     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4P, RESERVED0); \
   7878     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4P, FORCE); \
   7879     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4P, RESERVED1); \
   7880     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4P, ADJ_EN); \
   7881     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4P, RESERVED2); \
   7882     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4P, VDL_STEP); \
   7883     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4N, BUSY); \
   7884     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4N, RESERVED0); \
   7885     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4N, FORCE); \
   7886     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4N, RESERVED1); \
   7887     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4N, ADJ_EN); \
   7888     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4N, RESERVED2); \
   7889     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4N, VDL_STEP); \
   7890     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5P, BUSY); \
   7891     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5P, RESERVED0); \
   7892     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5P, FORCE); \
   7893     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5P, RESERVED1); \
   7894     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5P, ADJ_EN); \
   7895     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5P, RESERVED2); \
   7896     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5P, VDL_STEP); \
   7897     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5N, BUSY); \
   7898     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5N, RESERVED0); \
   7899     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5N, FORCE); \
   7900     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5N, RESERVED1); \
   7901     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5N, ADJ_EN); \
   7902     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5N, RESERVED2); \
   7903     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5N, VDL_STEP); \
   7904     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6P, BUSY); \
   7905     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6P, RESERVED0); \
   7906     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6P, FORCE); \
   7907     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6P, RESERVED1); \
   7908     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6P, ADJ_EN); \
   7909     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6P, RESERVED2); \
   7910     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6P, VDL_STEP); \
   7911     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6N, BUSY); \
   7912     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6N, RESERVED0); \
   7913     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6N, FORCE); \
   7914     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6N, RESERVED1); \
   7915     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6N, ADJ_EN); \
   7916     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6N, RESERVED2); \
   7917     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6N, VDL_STEP); \
   7918     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7P, BUSY); \
   7919     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7P, RESERVED0); \
   7920     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7P, FORCE); \
   7921     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7P, RESERVED1); \
   7922     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7P, ADJ_EN); \
   7923     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7P, RESERVED2); \
   7924     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7P, VDL_STEP); \
   7925     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7N, BUSY); \
   7926     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7N, RESERVED0); \
   7927     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7N, FORCE); \
   7928     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7N, RESERVED1); \
   7929     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7N, ADJ_EN); \
   7930     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7N, RESERVED2); \
   7931     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7N, VDL_STEP); \
   7932     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMP, BUSY); \
   7933     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMP, RESERVED0); \
   7934     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMP, FORCE); \
   7935     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMP, RESERVED1); \
   7936     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMP, ADJ_EN); \
   7937     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMP, RESERVED2); \
   7938     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMP, VDL_STEP); \
   7939     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMN, BUSY); \
   7940     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMN, RESERVED0); \
   7941     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMN, FORCE); \
   7942     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMN, RESERVED1); \
   7943     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMN, ADJ_EN); \
   7944     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMN, RESERVED2); \
   7945     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMN, VDL_STEP); \
   7946     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS0, BUSY); \
   7947     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS0, RESERVED0); \
   7948     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS0, FORCE); \
   7949     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS0, RESERVED1); \
   7950     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS0, ADJ_EN); \
   7951     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS0, RESERVED2); \
   7952     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS0, VDL_STEP); \
   7953     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS1, BUSY); \
   7954     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS1, RESERVED0); \
   7955     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS1, FORCE); \
   7956     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS1, RESERVED1); \
   7957     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS1, ADJ_EN); \
   7958     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS1, RESERVED2); \
   7959     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS1, VDL_STEP); \
   7960     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CLK_CONTROL, BUSY); \
   7961     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CLK_CONTROL, RESERVED0); \
   7962     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CLK_CONTROL, FORCE); \
   7963     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CLK_CONTROL, RESERVED1); \
   7964     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CLK_CONTROL, ADJ_EN); \
   7965     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CLK_CONTROL, RESERVED2); \
   7966     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_CLK_CONTROL, VDL_STEP); \
   7967     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_LDE_CONTROL, BUSY); \
   7968     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_LDE_CONTROL, RESERVED0); \
   7969     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_LDE_CONTROL, FORCE); \
   7970     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_LDE_CONTROL, RESERVED1); \
   7971     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_LDE_CONTROL, ADJ_EN); \
   7972     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_LDE_CONTROL, RESERVED2); \
   7973     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_VDL_LDE_CONTROL, VDL_STEP); \
   7974     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_RD_EN_DLY_CYC, BUSY); \
   7975     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_RD_EN_DLY_CYC, RESERVED0); \
   7976     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_RD_EN_DLY_CYC, FORCE); \
   7977     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_RD_EN_DLY_CYC, RESERVED1); \
   7978     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_RD_EN_DLY_CYC, ENABLE_CS1); \
   7979     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_RD_EN_DLY_CYC, CS1_CYCLES); \
   7980     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_RD_EN_DLY_CYC, CS0_CYCLES); \
   7981     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_WR_CHAN_DLY_CYC, BUSY); \
   7982     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_WR_CHAN_DLY_CYC, RESERVED0); \
   7983     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_WR_CHAN_DLY_CYC, FORCE); \
   7984     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_WR_CHAN_DLY_CYC, RESERVED1); \
   7985     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_WR_CHAN_DLY_CYC, DQ_CYCLES); \
   7986     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_WR_CHAN_DLY_CYC, RESERVED2); \
   7987     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_WR_CHAN_DLY_CYC, CYCLES); \
   7988     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_READ_CONTROL, RESERVED0); \
   7989     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_READ_CONTROL, MODE); \
   7990     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_READ_CONTROL, RD_EN_MODE); \
   7991     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_READ_CONTROL, RD_DATA_DLY); \
   7992     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_READ_FIFO_ADDR, RESERVED0); \
   7993     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_READ_FIFO_ADDR, ADDR); \
   7994     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_READ_FIFO_DATA, DATA); \
   7995     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_READ_FIFO_DM_DBI, RESERVED0); \
   7996     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_READ_FIFO_DM_DBI, DM_DBI); \
   7997     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_READ_FIFO_STATUS, RESERVED0); \
   7998     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_READ_FIFO_STATUS, OVERFLOW); \
   7999     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_READ_FIFO_STATUS, UNDERFLOW); \
   8000     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_READ_FIFO_CLEAR, RESERVED0); \
   8001     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_READ_FIFO_CLEAR, CLEAR); \
   8002     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_IDLE_PAD_CONTROL, IDLE); \
   8003     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_IDLE_PAD_CONTROL, RESERVED0); \
   8004     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_IDLE_PAD_CONTROL, AUTO_DQ_RXENB_MODE); \
   8005     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_IDLE_PAD_CONTROL, AUTO_DQ_IDDQ_MODE); \
   8006     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_IDLE_PAD_CONTROL, IO_IDLE_ENABLE); \
   8007     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_IDLE_PAD_CONTROL, RXENB); \
   8008     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_IDLE_PAD_CONTROL, IDDQ); \
   8009     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_IDLE_PAD_CONTROL, DOUT_N); \
   8010     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_IDLE_PAD_CONTROL, DOUT_P); \
   8011     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_DRIVE_PAD_CTL, RESERVED0); \
   8012     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_DRIVE_PAD_CTL, BL_PD_TERM_STRENGTH); \
   8013     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_DRIVE_PAD_CTL, BL_ND_TERM_STRENGTH); \
   8014     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_DRIVE_PAD_CTL, BL_PD_STRENGTH); \
   8015     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_DRIVE_PAD_CTL, BL_ND_STRENGTH); \
   8016     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_DQSP_DRIVE_PAD_CTL, RESERVED0); \
   8017     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_DQSP_DRIVE_PAD_CTL, BL_PD_TERM_STRENGTH); \
   8018     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_DQSP_DRIVE_PAD_CTL, BL_ND_TERM_STRENGTH); \
   8019     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_DQSP_DRIVE_PAD_CTL, BL_PD_STRENGTH); \
   8020     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_DQSP_DRIVE_PAD_CTL, BL_ND_STRENGTH); \
   8021     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_DQSN_DRIVE_PAD_CTL, RESERVED0); \
   8022     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_DQSN_DRIVE_PAD_CTL, BL_PD_TERM_STRENGTH); \
   8023     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_DQSN_DRIVE_PAD_CTL, BL_ND_TERM_STRENGTH); \
   8024     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_DQSN_DRIVE_PAD_CTL, BL_PD_STRENGTH); \
   8025     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_DQSN_DRIVE_PAD_CTL, BL_ND_STRENGTH); \
   8026     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_ALERT_DRIVE_PAD_CTL, RESERVED0); \
   8027     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_ALERT_DRIVE_PAD_CTL, BL_PD_TERM_STRENGTH); \
   8028     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_ALERT_DRIVE_PAD_CTL, BL_ND_TERM_STRENGTH); \
   8029     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_ALERT_DRIVE_PAD_CTL, BL_PD_STRENGTH); \
   8030     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_ALERT_DRIVE_PAD_CTL, BL_ND_STRENGTH); \
   8031     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_RD_EN_DRIVE_PAD_CTL, RESERVED0); \
   8032     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_RD_EN_DRIVE_PAD_CTL, BL_RD_EN_PD_STRENGTH); \
   8033     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_RD_EN_DRIVE_PAD_CTL, BL_RD_EN_ND_STRENGTH); \
   8034     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_STATIC_PAD_CTL, RESERVED0); \
   8035     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_STATIC_PAD_CTL, DM_INVERT); \
   8036     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_STATIC_PAD_CTL, WDBI_ENABLE); \
   8037     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_STATIC_PAD_CTL, RDBI_ENABLE); \
   8038     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_STATIC_PAD_CTL, DM_MODE); \
   8039     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_STATIC_PAD_CTL, RESERVED1); \
   8040     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_STATIC_PAD_CTL, DQS_TX_DIS); \
   8041     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_STATIC_PAD_CTL, RESERVED2); \
   8042     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_STATIC_PAD_CTL, RX_MODE); \
   8043     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_WR_PREAMBLE_MODE, RESERVED0); \
   8044     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_WR_PREAMBLE_MODE, POSTAM_TERM_BITS); \
   8045     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_WR_PREAMBLE_MODE, DM_POSTAM_BITS); \
   8046     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_WR_PREAMBLE_MODE, DM_PREAM_BITS); \
   8047     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_WR_PREAMBLE_MODE, DQ_POSTAM_BITS); \
   8048     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_WR_PREAMBLE_MODE, DQ_PREAM_BITS); \
   8049     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_WR_PREAMBLE_MODE, DQS); \
   8050     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_WR_PREAMBLE_MODE, DQS_POSTAM_BITS); \
   8051     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_WR_PREAMBLE_MODE, DQS_PREAM_BITS); \
   8052     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_ODT_CONTROL, RESERVED0); \
   8053     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_ODT_CONTROL, ODT_ENABLE); \
   8054     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_ODT_CONTROL, ODT_DELAY); \
   8055     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_ODT_CONTROL, ODT_POST_LENGTH); \
   8056     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_ODT_CONTROL, RESERVED1); \
   8057     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_ODT_CONTROL, ODT_PRE_LENGTH); \
   8058     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_CLOCK_ENABLE, RESERVED0); \
   8059     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_CLOCK_ENABLE, TO_MC_CLOCK); \
   8060     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_CLOCK_ENABLE, FROM_MC_CLOCK); \
   8061     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_CLOCK_ENABLE, BIT_CLOCK); \
   8062     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_CLOCK_IDLE, RESERVED0); \
   8063     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_CLOCK_IDLE, TO_MC_CLOCK); \
   8064     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_CLOCK_IDLE, FROM_MC_CLOCK); \
   8065     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_CLOCK_IDLE, BIT_CLOCK); \
   8066     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_2_BL_SPARE_REG, RESERVED_FOR_ECO0); \
   8067     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS, BUSY); \
   8068     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS, RESERVED0); \
   8069     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS, FORCE); \
   8070     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS, RESERVED1); \
   8071     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS, ADJ_EN); \
   8072     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS, RESERVED2); \
   8073     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS, VDL_STEP); \
   8074     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ0, BUSY); \
   8075     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ0, RESERVED0); \
   8076     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ0, FORCE); \
   8077     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ0, RESERVED1); \
   8078     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ0, ADJ_EN); \
   8079     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ0, RESERVED2); \
   8080     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ0, VDL_STEP); \
   8081     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ1, BUSY); \
   8082     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ1, RESERVED0); \
   8083     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ1, FORCE); \
   8084     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ1, RESERVED1); \
   8085     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ1, ADJ_EN); \
   8086     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ1, RESERVED2); \
   8087     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ1, VDL_STEP); \
   8088     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ2, BUSY); \
   8089     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ2, RESERVED0); \
   8090     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ2, FORCE); \
   8091     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ2, RESERVED1); \
   8092     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ2, ADJ_EN); \
   8093     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ2, RESERVED2); \
   8094     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ2, VDL_STEP); \
   8095     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ3, BUSY); \
   8096     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ3, RESERVED0); \
   8097     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ3, FORCE); \
   8098     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ3, RESERVED1); \
   8099     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ3, ADJ_EN); \
   8100     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ3, RESERVED2); \
   8101     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ3, VDL_STEP); \
   8102     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ4, BUSY); \
   8103     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ4, RESERVED0); \
   8104     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ4, FORCE); \
   8105     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ4, RESERVED1); \
   8106     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ4, ADJ_EN); \
   8107     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ4, RESERVED2); \
   8108     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ4, VDL_STEP); \
   8109     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ5, BUSY); \
   8110     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ5, RESERVED0); \
   8111     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ5, FORCE); \
   8112     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ5, RESERVED1); \
   8113     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ5, ADJ_EN); \
   8114     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ5, RESERVED2); \
   8115     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ5, VDL_STEP); \
   8116     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ6, BUSY); \
   8117     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ6, RESERVED0); \
   8118     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ6, FORCE); \
   8119     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ6, RESERVED1); \
   8120     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ6, ADJ_EN); \
   8121     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ6, RESERVED2); \
   8122     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ6, VDL_STEP); \
   8123     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ7, BUSY); \
   8124     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ7, RESERVED0); \
   8125     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ7, FORCE); \
   8126     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ7, RESERVED1); \
   8127     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ7, ADJ_EN); \
   8128     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ7, RESERVED2); \
   8129     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ7, VDL_STEP); \
   8130     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_DM, BUSY); \
   8131     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_DM, RESERVED0); \
   8132     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_DM, FORCE); \
   8133     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_DM, RESERVED1); \
   8134     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_DM, ADJ_EN); \
   8135     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_DM, RESERVED2); \
   8136     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_DM, VDL_STEP); \
   8137     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_ALERT, BUSY); \
   8138     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_ALERT, RESERVED0); \
   8139     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_ALERT, FORCE); \
   8140     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_ALERT, RESERVED1); \
   8141     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_ALERT, ADJ_EN); \
   8142     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_ALERT, RESERVED2); \
   8143     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_WR_ALERT, VDL_STEP); \
   8144     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSP, BUSY); \
   8145     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSP, RESERVED0); \
   8146     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSP, FORCE); \
   8147     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSP, RESERVED1); \
   8148     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSP, ADJ_EN); \
   8149     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSP, RESERVED2); \
   8150     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSP, VDL_STEP); \
   8151     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSN, BUSY); \
   8152     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSN, RESERVED0); \
   8153     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSN, FORCE); \
   8154     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSN, RESERVED1); \
   8155     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSN, ADJ_EN); \
   8156     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSN, RESERVED2); \
   8157     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSN, VDL_STEP); \
   8158     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0P, BUSY); \
   8159     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0P, RESERVED0); \
   8160     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0P, FORCE); \
   8161     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0P, RESERVED1); \
   8162     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0P, ADJ_EN); \
   8163     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0P, RESERVED2); \
   8164     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0P, VDL_STEP); \
   8165     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0N, BUSY); \
   8166     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0N, RESERVED0); \
   8167     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0N, FORCE); \
   8168     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0N, RESERVED1); \
   8169     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0N, ADJ_EN); \
   8170     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0N, RESERVED2); \
   8171     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0N, VDL_STEP); \
   8172     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1P, BUSY); \
   8173     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1P, RESERVED0); \
   8174     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1P, FORCE); \
   8175     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1P, RESERVED1); \
   8176     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1P, ADJ_EN); \
   8177     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1P, RESERVED2); \
   8178     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1P, VDL_STEP); \
   8179     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1N, BUSY); \
   8180     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1N, RESERVED0); \
   8181     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1N, FORCE); \
   8182     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1N, RESERVED1); \
   8183     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1N, ADJ_EN); \
   8184     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1N, RESERVED2); \
   8185     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1N, VDL_STEP); \
   8186     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2P, BUSY); \
   8187     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2P, RESERVED0); \
   8188     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2P, FORCE); \
   8189     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2P, RESERVED1); \
   8190     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2P, ADJ_EN); \
   8191     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2P, RESERVED2); \
   8192     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2P, VDL_STEP); \
   8193     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2N, BUSY); \
   8194     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2N, RESERVED0); \
   8195     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2N, FORCE); \
   8196     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2N, RESERVED1); \
   8197     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2N, ADJ_EN); \
   8198     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2N, RESERVED2); \
   8199     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2N, VDL_STEP); \
   8200     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3P, BUSY); \
   8201     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3P, RESERVED0); \
   8202     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3P, FORCE); \
   8203     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3P, RESERVED1); \
   8204     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3P, ADJ_EN); \
   8205     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3P, RESERVED2); \
   8206     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3P, VDL_STEP); \
   8207     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3N, BUSY); \
   8208     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3N, RESERVED0); \
   8209     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3N, FORCE); \
   8210     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3N, RESERVED1); \
   8211     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3N, ADJ_EN); \
   8212     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3N, RESERVED2); \
   8213     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3N, VDL_STEP); \
   8214     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4P, BUSY); \
   8215     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4P, RESERVED0); \
   8216     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4P, FORCE); \
   8217     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4P, RESERVED1); \
   8218     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4P, ADJ_EN); \
   8219     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4P, RESERVED2); \
   8220     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4P, VDL_STEP); \
   8221     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4N, BUSY); \
   8222     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4N, RESERVED0); \
   8223     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4N, FORCE); \
   8224     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4N, RESERVED1); \
   8225     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4N, ADJ_EN); \
   8226     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4N, RESERVED2); \
   8227     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4N, VDL_STEP); \
   8228     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5P, BUSY); \
   8229     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5P, RESERVED0); \
   8230     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5P, FORCE); \
   8231     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5P, RESERVED1); \
   8232     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5P, ADJ_EN); \
   8233     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5P, RESERVED2); \
   8234     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5P, VDL_STEP); \
   8235     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5N, BUSY); \
   8236     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5N, RESERVED0); \
   8237     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5N, FORCE); \
   8238     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5N, RESERVED1); \
   8239     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5N, ADJ_EN); \
   8240     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5N, RESERVED2); \
   8241     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5N, VDL_STEP); \
   8242     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6P, BUSY); \
   8243     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6P, RESERVED0); \
   8244     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6P, FORCE); \
   8245     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6P, RESERVED1); \
   8246     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6P, ADJ_EN); \
   8247     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6P, RESERVED2); \
   8248     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6P, VDL_STEP); \
   8249     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6N, BUSY); \
   8250     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6N, RESERVED0); \
   8251     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6N, FORCE); \
   8252     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6N, RESERVED1); \
   8253     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6N, ADJ_EN); \
   8254     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6N, RESERVED2); \
   8255     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6N, VDL_STEP); \
   8256     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7P, BUSY); \
   8257     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7P, RESERVED0); \
   8258     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7P, FORCE); \
   8259     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7P, RESERVED1); \
   8260     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7P, ADJ_EN); \
   8261     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7P, RESERVED2); \
   8262     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7P, VDL_STEP); \
   8263     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7N, BUSY); \
   8264     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7N, RESERVED0); \
   8265     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7N, FORCE); \
   8266     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7N, RESERVED1); \
   8267     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7N, ADJ_EN); \
   8268     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7N, RESERVED2); \
   8269     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7N, VDL_STEP); \
   8270     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMP, BUSY); \
   8271     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMP, RESERVED0); \
   8272     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMP, FORCE); \
   8273     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMP, RESERVED1); \
   8274     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMP, ADJ_EN); \
   8275     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMP, RESERVED2); \
   8276     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMP, VDL_STEP); \
   8277     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMN, BUSY); \
   8278     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMN, RESERVED0); \
   8279     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMN, FORCE); \
   8280     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMN, RESERVED1); \
   8281     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMN, ADJ_EN); \
   8282     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMN, RESERVED2); \
   8283     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMN, VDL_STEP); \
   8284     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS0, BUSY); \
   8285     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS0, RESERVED0); \
   8286     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS0, FORCE); \
   8287     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS0, RESERVED1); \
   8288     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS0, ADJ_EN); \
   8289     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS0, RESERVED2); \
   8290     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS0, VDL_STEP); \
   8291     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS1, BUSY); \
   8292     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS1, RESERVED0); \
   8293     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS1, FORCE); \
   8294     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS1, RESERVED1); \
   8295     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS1, ADJ_EN); \
   8296     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS1, RESERVED2); \
   8297     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS1, VDL_STEP); \
   8298     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CLK_CONTROL, BUSY); \
   8299     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CLK_CONTROL, RESERVED0); \
   8300     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CLK_CONTROL, FORCE); \
   8301     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CLK_CONTROL, RESERVED1); \
   8302     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CLK_CONTROL, ADJ_EN); \
   8303     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CLK_CONTROL, RESERVED2); \
   8304     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_CLK_CONTROL, VDL_STEP); \
   8305     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_LDE_CONTROL, BUSY); \
   8306     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_LDE_CONTROL, RESERVED0); \
   8307     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_LDE_CONTROL, FORCE); \
   8308     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_LDE_CONTROL, RESERVED1); \
   8309     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_LDE_CONTROL, ADJ_EN); \
   8310     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_LDE_CONTROL, RESERVED2); \
   8311     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_VDL_LDE_CONTROL, VDL_STEP); \
   8312     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_RD_EN_DLY_CYC, BUSY); \
   8313     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_RD_EN_DLY_CYC, RESERVED0); \
   8314     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_RD_EN_DLY_CYC, FORCE); \
   8315     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_RD_EN_DLY_CYC, RESERVED1); \
   8316     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_RD_EN_DLY_CYC, ENABLE_CS1); \
   8317     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_RD_EN_DLY_CYC, CS1_CYCLES); \
   8318     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_RD_EN_DLY_CYC, CS0_CYCLES); \
   8319     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_WR_CHAN_DLY_CYC, BUSY); \
   8320     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_WR_CHAN_DLY_CYC, RESERVED0); \
   8321     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_WR_CHAN_DLY_CYC, FORCE); \
   8322     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_WR_CHAN_DLY_CYC, RESERVED1); \
   8323     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_WR_CHAN_DLY_CYC, DQ_CYCLES); \
   8324     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_WR_CHAN_DLY_CYC, RESERVED2); \
   8325     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_WR_CHAN_DLY_CYC, CYCLES); \
   8326     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_READ_CONTROL, RESERVED0); \
   8327     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_READ_CONTROL, MODE); \
   8328     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_READ_CONTROL, RD_EN_MODE); \
   8329     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_READ_CONTROL, RD_DATA_DLY); \
   8330     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_READ_FIFO_ADDR, RESERVED0); \
   8331     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_READ_FIFO_ADDR, ADDR); \
   8332     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_READ_FIFO_DATA, DATA); \
   8333     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_READ_FIFO_DM_DBI, RESERVED0); \
   8334     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_READ_FIFO_DM_DBI, DM_DBI); \
   8335     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_READ_FIFO_STATUS, RESERVED0); \
   8336     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_READ_FIFO_STATUS, OVERFLOW); \
   8337     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_READ_FIFO_STATUS, UNDERFLOW); \
   8338     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_READ_FIFO_CLEAR, RESERVED0); \
   8339     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_READ_FIFO_CLEAR, CLEAR); \
   8340     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_IDLE_PAD_CONTROL, IDLE); \
   8341     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_IDLE_PAD_CONTROL, RESERVED0); \
   8342     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_IDLE_PAD_CONTROL, AUTO_DQ_RXENB_MODE); \
   8343     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_IDLE_PAD_CONTROL, AUTO_DQ_IDDQ_MODE); \
   8344     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_IDLE_PAD_CONTROL, IO_IDLE_ENABLE); \
   8345     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_IDLE_PAD_CONTROL, RXENB); \
   8346     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_IDLE_PAD_CONTROL, IDDQ); \
   8347     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_IDLE_PAD_CONTROL, DOUT_N); \
   8348     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_IDLE_PAD_CONTROL, DOUT_P); \
   8349     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_DRIVE_PAD_CTL, RESERVED0); \
   8350     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_DRIVE_PAD_CTL, BL_PD_TERM_STRENGTH); \
   8351     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_DRIVE_PAD_CTL, BL_ND_TERM_STRENGTH); \
   8352     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_DRIVE_PAD_CTL, BL_PD_STRENGTH); \
   8353     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_DRIVE_PAD_CTL, BL_ND_STRENGTH); \
   8354     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_DQSP_DRIVE_PAD_CTL, RESERVED0); \
   8355     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_DQSP_DRIVE_PAD_CTL, BL_PD_TERM_STRENGTH); \
   8356     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_DQSP_DRIVE_PAD_CTL, BL_ND_TERM_STRENGTH); \
   8357     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_DQSP_DRIVE_PAD_CTL, BL_PD_STRENGTH); \
   8358     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_DQSP_DRIVE_PAD_CTL, BL_ND_STRENGTH); \
   8359     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_DQSN_DRIVE_PAD_CTL, RESERVED0); \
   8360     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_DQSN_DRIVE_PAD_CTL, BL_PD_TERM_STRENGTH); \
   8361     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_DQSN_DRIVE_PAD_CTL, BL_ND_TERM_STRENGTH); \
   8362     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_DQSN_DRIVE_PAD_CTL, BL_PD_STRENGTH); \
   8363     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_DQSN_DRIVE_PAD_CTL, BL_ND_STRENGTH); \
   8364     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_ALERT_DRIVE_PAD_CTL, RESERVED0); \
   8365     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_ALERT_DRIVE_PAD_CTL, BL_PD_TERM_STRENGTH); \
   8366     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_ALERT_DRIVE_PAD_CTL, BL_ND_TERM_STRENGTH); \
   8367     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_ALERT_DRIVE_PAD_CTL, BL_PD_STRENGTH); \
   8368     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_ALERT_DRIVE_PAD_CTL, BL_ND_STRENGTH); \
   8369     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_RD_EN_DRIVE_PAD_CTL, RESERVED0); \
   8370     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_RD_EN_DRIVE_PAD_CTL, BL_RD_EN_PD_STRENGTH); \
   8371     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_RD_EN_DRIVE_PAD_CTL, BL_RD_EN_ND_STRENGTH); \
   8372     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_STATIC_PAD_CTL, RESERVED0); \
   8373     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_STATIC_PAD_CTL, DM_INVERT); \
   8374     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_STATIC_PAD_CTL, WDBI_ENABLE); \
   8375     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_STATIC_PAD_CTL, RDBI_ENABLE); \
   8376     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_STATIC_PAD_CTL, DM_MODE); \
   8377     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_STATIC_PAD_CTL, RESERVED1); \
   8378     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_STATIC_PAD_CTL, DQS_TX_DIS); \
   8379     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_STATIC_PAD_CTL, RESERVED2); \
   8380     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_STATIC_PAD_CTL, RX_MODE); \
   8381     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_WR_PREAMBLE_MODE, RESERVED0); \
   8382     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_WR_PREAMBLE_MODE, POSTAM_TERM_BITS); \
   8383     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_WR_PREAMBLE_MODE, DM_POSTAM_BITS); \
   8384     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_WR_PREAMBLE_MODE, DM_PREAM_BITS); \
   8385     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_WR_PREAMBLE_MODE, DQ_POSTAM_BITS); \
   8386     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_WR_PREAMBLE_MODE, DQ_PREAM_BITS); \
   8387     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_WR_PREAMBLE_MODE, DQS); \
   8388     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_WR_PREAMBLE_MODE, DQS_POSTAM_BITS); \
   8389     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_WR_PREAMBLE_MODE, DQS_PREAM_BITS); \
   8390     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_ODT_CONTROL, RESERVED0); \
   8391     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_ODT_CONTROL, ODT_ENABLE); \
   8392     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_ODT_CONTROL, ODT_DELAY); \
   8393     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_ODT_CONTROL, ODT_POST_LENGTH); \
   8394     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_ODT_CONTROL, RESERVED1); \
   8395     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_ODT_CONTROL, ODT_PRE_LENGTH); \
   8396     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_CLOCK_ENABLE, RESERVED0); \
   8397     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_CLOCK_ENABLE, TO_MC_CLOCK); \
   8398     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_CLOCK_ENABLE, FROM_MC_CLOCK); \
   8399     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_CLOCK_ENABLE, BIT_CLOCK); \
   8400     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_CLOCK_IDLE, RESERVED0); \
   8401     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_CLOCK_IDLE, TO_MC_CLOCK); \
   8402     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_CLOCK_IDLE, FROM_MC_CLOCK); \
   8403     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_CLOCK_IDLE, BIT_CLOCK); \
   8404     INIT_DDR34_SIGNE_FIELD(F0, PHY_BYTE_LANE_3_BL_SPARE_REG, RESERVED_FOR_ECO0); \
   8405 }
   8406 
   8407 /*******************************************************************************
   8408  */
   8409 /***************************************************************************
   8410  *DDR34_E0_PHY_CONTROL_REGS - DDR34 CORE DDR34 Address/Comand control registers
   8411  */
   8412 #define READ_DDR34_PHY_CONTROL_REGS_REVISIONr(_unit, _pc, _val) \
   8413         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_REVISIONr), (_val)) 
   8414 #define WRITE_DDR34_PHY_CONTROL_REGS_REVISIONr(_unit, _pc, _val) \
   8415         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_REVISIONr), (_val))
   8416 #define MODIFY_DDR34_PHY_CONTROL_REGS_REVISIONr(_unit, _pc, _val, _mask) \
   8417         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_REVISIONr), (_val), (_mask))
   8418 
   8419 #define READ_DDR34_PHY_CONTROL_REGS_PLL_STATUSr(_unit, _pc, _val) \
   8420         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_PLL_STATUSr), (_val)) 
   8421 #define WRITE_DDR34_PHY_CONTROL_REGS_PLL_STATUSr(_unit, _pc, _val) \
   8422         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_PLL_STATUSr), (_val))
   8423 #define MODIFY_DDR34_PHY_CONTROL_REGS_PLL_STATUSr(_unit, _pc, _val, _mask) \
   8424         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_PLL_STATUSr), (_val), (_mask))
   8425 
   8426 #define READ_DDR34_PHY_CONTROL_REGS_PLL_CONFIGr(_unit, _pc, _val) \
   8427         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_PLL_CONFIGr), (_val)) 
   8428 #define WRITE_DDR34_PHY_CONTROL_REGS_PLL_CONFIGr(_unit, _pc, _val) \
   8429         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_PLL_CONFIGr), (_val))
   8430 #define MODIFY_DDR34_PHY_CONTROL_REGS_PLL_CONFIGr(_unit, _pc, _val, _mask) \
   8431         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_PLL_CONFIGr), (_val), (_mask))
   8432 
   8433 #define READ_DDR34_PHY_CONTROL_REGS_PLL_CONTROL1r(_unit, _pc, _val) \
   8434         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_PLL_CONTROL1r), (_val)) 
   8435 #define WRITE_DDR34_PHY_CONTROL_REGS_PLL_CONTROL1r(_unit, _pc, _val) \
   8436         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_PLL_CONTROL1r), (_val))
   8437 #define MODIFY_DDR34_PHY_CONTROL_REGS_PLL_CONTROL1r(_unit, _pc, _val, _mask) \
   8438         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_PLL_CONTROL1r), (_val), (_mask))
   8439 
   8440 #define READ_DDR34_PHY_CONTROL_REGS_PLL_CONTROL2r(_unit, _pc, _val) \
   8441         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_PLL_CONTROL2r), (_val)) 
   8442 #define WRITE_DDR34_PHY_CONTROL_REGS_PLL_CONTROL2r(_unit, _pc, _val) \
   8443         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_PLL_CONTROL2r), (_val))
   8444 #define MODIFY_DDR34_PHY_CONTROL_REGS_PLL_CONTROL2r(_unit, _pc, _val, _mask) \
   8445         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_PLL_CONTROL2r), (_val), (_mask))
   8446 
   8447 #define READ_DDR34_PHY_CONTROL_REGS_PLL_CONTROL3r(_unit, _pc, _val) \
   8448         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_PLL_CONTROL3r), (_val)) 
   8449 #define WRITE_DDR34_PHY_CONTROL_REGS_PLL_CONTROL3r(_unit, _pc, _val) \
   8450         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_PLL_CONTROL3r), (_val))
   8451 #define MODIFY_DDR34_PHY_CONTROL_REGS_PLL_CONTROL3r(_unit, _pc, _val, _mask) \
   8452         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_PLL_CONTROL3r), (_val), (_mask))
   8453 
   8454 #define READ_DDR34_PHY_CONTROL_REGS_PLL_DIVIDERSr(_unit, _pc, _val) \
   8455         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_PLL_DIVIDERSr), (_val)) 
   8456 #define WRITE_DDR34_PHY_CONTROL_REGS_PLL_DIVIDERSr(_unit, _pc, _val) \
   8457         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_PLL_DIVIDERSr), (_val))
   8458 #define MODIFY_DDR34_PHY_CONTROL_REGS_PLL_DIVIDERSr(_unit, _pc, _val, _mask) \
   8459         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_PLL_DIVIDERSr), (_val), (_mask))
   8460 
   8461 #define READ_DDR34_PHY_CONTROL_REGS_PLL_FRAC_DIVIDERr(_unit, _pc, _val) \
   8462         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_PLL_FRAC_DIVIDERr), (_val)) 
   8463 #define WRITE_DDR34_PHY_CONTROL_REGS_PLL_FRAC_DIVIDERr(_unit, _pc, _val) \
   8464         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_PLL_FRAC_DIVIDERr), (_val))
   8465 #define MODIFY_DDR34_PHY_CONTROL_REGS_PLL_FRAC_DIVIDERr(_unit, _pc, _val, _mask) \
   8466         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_PLL_FRAC_DIVIDERr), (_val), (_mask))
   8467 
   8468 #define READ_DDR34_PHY_CONTROL_REGS_PLL_SS_CONTROLr(_unit, _pc, _val) \
   8469         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_PLL_SS_CONTROLr), (_val)) 
   8470 #define WRITE_DDR34_PHY_CONTROL_REGS_PLL_SS_CONTROLr(_unit, _pc, _val) \
   8471         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_PLL_SS_CONTROLr), (_val))
   8472 #define MODIFY_DDR34_PHY_CONTROL_REGS_PLL_SS_CONTROLr(_unit, _pc, _val, _mask) \
   8473         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_PLL_SS_CONTROLr), (_val), (_mask))
   8474 
   8475 #define READ_DDR34_PHY_CONTROL_REGS_PLL_SS_LIMITr(_unit, _pc, _val) \
   8476         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_PLL_SS_LIMITr), (_val)) 
   8477 #define WRITE_DDR34_PHY_CONTROL_REGS_PLL_SS_LIMITr(_unit, _pc, _val) \
   8478         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_PLL_SS_LIMITr), (_val))
   8479 #define MODIFY_DDR34_PHY_CONTROL_REGS_PLL_SS_LIMITr(_unit, _pc, _val, _mask) \
   8480         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_PLL_SS_LIMITr), (_val), (_mask))
   8481 
   8482 #define READ_DDR34_PHY_CONTROL_REGS_AUX_CONTROLr(_unit, _pc, _val) \
   8483         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_AUX_CONTROLr), (_val)) 
   8484 #define WRITE_DDR34_PHY_CONTROL_REGS_AUX_CONTROLr(_unit, _pc, _val) \
   8485         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_AUX_CONTROLr), (_val))
   8486 #define MODIFY_DDR34_PHY_CONTROL_REGS_AUX_CONTROLr(_unit, _pc, _val, _mask) \
   8487         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_AUX_CONTROLr), (_val), (_mask))
   8488 
   8489 #define READ_DDR34_PHY_CONTROL_REGS_IDLE_PAD_CONTROLr(_unit, _pc, _val) \
   8490         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_IDLE_PAD_CONTROLr), (_val)) 
   8491 #define WRITE_DDR34_PHY_CONTROL_REGS_IDLE_PAD_CONTROLr(_unit, _pc, _val) \
   8492         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_IDLE_PAD_CONTROLr), (_val))
   8493 #define MODIFY_DDR34_PHY_CONTROL_REGS_IDLE_PAD_CONTROLr(_unit, _pc, _val, _mask) \
   8494         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_IDLE_PAD_CONTROLr), (_val), (_mask))
   8495 
   8496 #define READ_DDR34_PHY_CONTROL_REGS_IDLE_PAD_ENABLE0r(_unit, _pc, _val) \
   8497         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_IDLE_PAD_ENABLE0r), (_val)) 
   8498 #define WRITE_DDR34_PHY_CONTROL_REGS_IDLE_PAD_ENABLE0r(_unit, _pc, _val) \
   8499         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_IDLE_PAD_ENABLE0r), (_val))
   8500 #define MODIFY_DDR34_PHY_CONTROL_REGS_IDLE_PAD_ENABLE0r(_unit, _pc, _val, _mask) \
   8501         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_IDLE_PAD_ENABLE0r), (_val), (_mask))
   8502 
   8503 #define READ_DDR34_PHY_CONTROL_REGS_IDLE_PAD_ENABLE1r(_unit, _pc, _val) \
   8504         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_IDLE_PAD_ENABLE1r), (_val)) 
   8505 #define WRITE_DDR34_PHY_CONTROL_REGS_IDLE_PAD_ENABLE1r(_unit, _pc, _val) \
   8506         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_IDLE_PAD_ENABLE1r), (_val))
   8507 #define MODIFY_DDR34_PHY_CONTROL_REGS_IDLE_PAD_ENABLE1r(_unit, _pc, _val, _mask) \
   8508         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_IDLE_PAD_ENABLE1r), (_val), (_mask))
   8509 
   8510 #define READ_DDR34_PHY_CONTROL_REGS_DRIVE_PAD_CTLr(_unit, _pc, _val) \
   8511         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_DRIVE_PAD_CTLr), (_val)) 
   8512 #define WRITE_DDR34_PHY_CONTROL_REGS_DRIVE_PAD_CTLr(_unit, _pc, _val) \
   8513         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_DRIVE_PAD_CTLr), (_val))
   8514 #define MODIFY_DDR34_PHY_CONTROL_REGS_DRIVE_PAD_CTLr(_unit, _pc, _val, _mask) \
   8515         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_DRIVE_PAD_CTLr), (_val), (_mask))
   8516 
   8517 #define READ_DDR34_PHY_CONTROL_REGS_STATIC_PAD_CTLr(_unit, _pc, _val) \
   8518         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_STATIC_PAD_CTLr), (_val)) 
   8519 #define WRITE_DDR34_PHY_CONTROL_REGS_STATIC_PAD_CTLr(_unit, _pc, _val) \
   8520         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_STATIC_PAD_CTLr), (_val))
   8521 #define MODIFY_DDR34_PHY_CONTROL_REGS_STATIC_PAD_CTLr(_unit, _pc, _val, _mask) \
   8522         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_STATIC_PAD_CTLr), (_val), (_mask))
   8523 
   8524 #define READ_DDR34_PHY_CONTROL_REGS_DRAM_CONFIGr(_unit, _pc, _val) \
   8525         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_DRAM_CONFIGr), (_val)) 
   8526 #define WRITE_DDR34_PHY_CONTROL_REGS_DRAM_CONFIGr(_unit, _pc, _val) \
   8527         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_DRAM_CONFIGr), (_val))
   8528 #define MODIFY_DDR34_PHY_CONTROL_REGS_DRAM_CONFIGr(_unit, _pc, _val, _mask) \
   8529         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_DRAM_CONFIGr), (_val), (_mask))
   8530 
   8531 #define READ_DDR34_PHY_CONTROL_REGS_DRAM_TIMING1r(_unit, _pc, _val) \
   8532         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_DRAM_TIMING1r), (_val)) 
   8533 #define WRITE_DDR34_PHY_CONTROL_REGS_DRAM_TIMING1r(_unit, _pc, _val) \
   8534         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_DRAM_TIMING1r), (_val))
   8535 #define MODIFY_DDR34_PHY_CONTROL_REGS_DRAM_TIMING1r(_unit, _pc, _val, _mask) \
   8536         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_DRAM_TIMING1r), (_val), (_mask))
   8537 
   8538 #define READ_DDR34_PHY_CONTROL_REGS_DRAM_TIMING2r(_unit, _pc, _val) \
   8539         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_DRAM_TIMING2r), (_val)) 
   8540 #define WRITE_DDR34_PHY_CONTROL_REGS_DRAM_TIMING2r(_unit, _pc, _val) \
   8541         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_DRAM_TIMING2r), (_val))
   8542 #define MODIFY_DDR34_PHY_CONTROL_REGS_DRAM_TIMING2r(_unit, _pc, _val, _mask) \
   8543         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_DRAM_TIMING2r), (_val), (_mask))
   8544 
   8545 #define READ_DDR34_PHY_CONTROL_REGS_DRAM_TIMING3r(_unit, _pc, _val) \
   8546         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_DRAM_TIMING3r), (_val)) 
   8547 #define WRITE_DDR34_PHY_CONTROL_REGS_DRAM_TIMING3r(_unit, _pc, _val) \
   8548         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_DRAM_TIMING3r), (_val))
   8549 #define MODIFY_DDR34_PHY_CONTROL_REGS_DRAM_TIMING3r(_unit, _pc, _val, _mask) \
   8550         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_DRAM_TIMING3r), (_val), (_mask))
   8551 
   8552 #define READ_DDR34_PHY_CONTROL_REGS_DRAM_TIMING4r(_unit, _pc, _val) \
   8553         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_DRAM_TIMING4r), (_val)) 
   8554 #define WRITE_DDR34_PHY_CONTROL_REGS_DRAM_TIMING4r(_unit, _pc, _val) \
   8555         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_DRAM_TIMING4r), (_val))
   8556 #define MODIFY_DDR34_PHY_CONTROL_REGS_DRAM_TIMING4r(_unit, _pc, _val, _mask) \
   8557         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_DRAM_TIMING4r), (_val), (_mask))
   8558 
   8559 #define READ_DDR34_PHY_CONTROL_REGS_VDL_CALIBRATEr(_unit, _pc, _val) \
   8560         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CALIBRATEr), (_val)) 
   8561 #define WRITE_DDR34_PHY_CONTROL_REGS_VDL_CALIBRATEr(_unit, _pc, _val) \
   8562         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CALIBRATEr), (_val))
   8563 #define MODIFY_DDR34_PHY_CONTROL_REGS_VDL_CALIBRATEr(_unit, _pc, _val, _mask) \
   8564         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CALIBRATEr), (_val), (_mask))
   8565 
   8566 #define READ_DDR34_PHY_CONTROL_REGS_VDL_CALIB_STATUS1r(_unit, _pc, _val) \
   8567         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CALIB_STATUS1r), (_val)) 
   8568 #define WRITE_DDR34_PHY_CONTROL_REGS_VDL_CALIB_STATUS1r(_unit, _pc, _val) \
   8569         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CALIB_STATUS1r), (_val))
   8570 #define MODIFY_DDR34_PHY_CONTROL_REGS_VDL_CALIB_STATUS1r(_unit, _pc, _val, _mask) \
   8571         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CALIB_STATUS1r), (_val), (_mask))
   8572 
   8573 #define READ_DDR34_PHY_CONTROL_REGS_VDL_CALIB_STATUS2r(_unit, _pc, _val) \
   8574         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CALIB_STATUS2r), (_val)) 
   8575 #define WRITE_DDR34_PHY_CONTROL_REGS_VDL_CALIB_STATUS2r(_unit, _pc, _val) \
   8576         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CALIB_STATUS2r), (_val))
   8577 #define MODIFY_DDR34_PHY_CONTROL_REGS_VDL_CALIB_STATUS2r(_unit, _pc, _val, _mask) \
   8578         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CALIB_STATUS2r), (_val), (_mask))
   8579 
   8580 #define READ_DDR34_PHY_CONTROL_REGS_VDL_MONITOR_CONTROLr(_unit, _pc, _val) \
   8581         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_MONITOR_CONTROLr), (_val)) 
   8582 #define WRITE_DDR34_PHY_CONTROL_REGS_VDL_MONITOR_CONTROLr(_unit, _pc, _val) \
   8583         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_MONITOR_CONTROLr), (_val))
   8584 #define MODIFY_DDR34_PHY_CONTROL_REGS_VDL_MONITOR_CONTROLr(_unit, _pc, _val, _mask) \
   8585         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_MONITOR_CONTROLr), (_val), (_mask))
   8586 
   8587 #define READ_DDR34_PHY_CONTROL_REGS_VDL_MONITOR_REFr(_unit, _pc, _val) \
   8588         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_MONITOR_REFr), (_val)) 
   8589 #define WRITE_DDR34_PHY_CONTROL_REGS_VDL_MONITOR_REFr(_unit, _pc, _val) \
   8590         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_MONITOR_REFr), (_val))
   8591 #define MODIFY_DDR34_PHY_CONTROL_REGS_VDL_MONITOR_REFr(_unit, _pc, _val, _mask) \
   8592         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_MONITOR_REFr), (_val), (_mask))
   8593 
   8594 #define READ_DDR34_PHY_CONTROL_REGS_VDL_MONITOR_STATUSr(_unit, _pc, _val) \
   8595         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_MONITOR_STATUSr), (_val)) 
   8596 #define WRITE_DDR34_PHY_CONTROL_REGS_VDL_MONITOR_STATUSr(_unit, _pc, _val) \
   8597         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_MONITOR_STATUSr), (_val))
   8598 #define MODIFY_DDR34_PHY_CONTROL_REGS_VDL_MONITOR_STATUSr(_unit, _pc, _val, _mask) \
   8599         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_MONITOR_STATUSr), (_val), (_mask))
   8600 
   8601 #define READ_DDR34_PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDEr(_unit, _pc, _val) \
   8602         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDEr), (_val)) 
   8603 #define WRITE_DDR34_PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDEr(_unit, _pc, _val) \
   8604         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDEr), (_val))
   8605 #define MODIFY_DDR34_PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDEr(_unit, _pc, _val, _mask) \
   8606         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDEr), (_val), (_mask))
   8607 
   8608 #define READ_DDR34_PHY_CONTROL_REGS_VDL_MONITOR_OUT_CONTROLr(_unit, _pc, _val) \
   8609         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_MONITOR_OUT_CONTROLr), (_val)) 
   8610 #define WRITE_DDR34_PHY_CONTROL_REGS_VDL_MONITOR_OUT_CONTROLr(_unit, _pc, _val) \
   8611         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_MONITOR_OUT_CONTROLr), (_val))
   8612 #define MODIFY_DDR34_PHY_CONTROL_REGS_VDL_MONITOR_OUT_CONTROLr(_unit, _pc, _val, _mask) \
   8613         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_MONITOR_OUT_CONTROLr), (_val), (_mask))
   8614 
   8615 #define READ_DDR34_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUSr(_unit, _pc, _val) \
   8616         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUSr), (_val)) 
   8617 #define WRITE_DDR34_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUSr(_unit, _pc, _val) \
   8618         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUSr), (_val))
   8619 #define MODIFY_DDR34_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUSr(_unit, _pc, _val, _mask) \
   8620         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUSr), (_val), (_mask))
   8621 
   8622 #define READ_DDR34_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_CLEARr(_unit, _pc, _val) \
   8623         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_CLEARr), (_val)) 
   8624 #define WRITE_DDR34_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_CLEARr(_unit, _pc, _val) \
   8625         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_CLEARr), (_val))
   8626 #define MODIFY_DDR34_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_CLEARr(_unit, _pc, _val, _mask) \
   8627         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_CLEARr), (_val), (_mask))
   8628 
   8629 #define READ_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD00r(_unit, _pc, _val) \
   8630         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD00r), (_val)) 
   8631 #define WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD00r(_unit, _pc, _val) \
   8632         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD00r), (_val))
   8633 #define MODIFY_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD00r(_unit, _pc, _val, _mask) \
   8634         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD00r), (_val), (_mask))
   8635 
   8636 #define READ_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD01r(_unit, _pc, _val) \
   8637         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD01r), (_val)) 
   8638 #define WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD01r(_unit, _pc, _val) \
   8639         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD01r), (_val))
   8640 #define MODIFY_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD01r(_unit, _pc, _val, _mask) \
   8641         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD01r), (_val), (_mask))
   8642 
   8643 #define READ_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD02r(_unit, _pc, _val) \
   8644         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD02r), (_val)) 
   8645 #define WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD02r(_unit, _pc, _val) \
   8646         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD02r), (_val))
   8647 #define MODIFY_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD02r(_unit, _pc, _val, _mask) \
   8648         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD02r), (_val), (_mask))
   8649 
   8650 #define READ_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD03r(_unit, _pc, _val) \
   8651         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD03r), (_val)) 
   8652 #define WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD03r(_unit, _pc, _val) \
   8653         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD03r), (_val))
   8654 #define MODIFY_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD03r(_unit, _pc, _val, _mask) \
   8655         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD03r), (_val), (_mask))
   8656 
   8657 #define READ_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD04r(_unit, _pc, _val) \
   8658         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD04r), (_val)) 
   8659 #define WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD04r(_unit, _pc, _val) \
   8660         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD04r), (_val))
   8661 #define MODIFY_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD04r(_unit, _pc, _val, _mask) \
   8662         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD04r), (_val), (_mask))
   8663 
   8664 #define READ_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD05r(_unit, _pc, _val) \
   8665         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD05r), (_val)) 
   8666 #define WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD05r(_unit, _pc, _val) \
   8667         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD05r), (_val))
   8668 #define MODIFY_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD05r(_unit, _pc, _val, _mask) \
   8669         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD05r), (_val), (_mask))
   8670 
   8671 #define READ_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD06r(_unit, _pc, _val) \
   8672         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD06r), (_val)) 
   8673 #define WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD06r(_unit, _pc, _val) \
   8674         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD06r), (_val))
   8675 #define MODIFY_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD06r(_unit, _pc, _val, _mask) \
   8676         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD06r), (_val), (_mask))
   8677 
   8678 #define READ_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD07r(_unit, _pc, _val) \
   8679         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD07r), (_val)) 
   8680 #define WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD07r(_unit, _pc, _val) \
   8681         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD07r), (_val))
   8682 #define MODIFY_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD07r(_unit, _pc, _val, _mask) \
   8683         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD07r), (_val), (_mask))
   8684 
   8685 #define READ_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD08r(_unit, _pc, _val) \
   8686         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD08r), (_val)) 
   8687 #define WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD08r(_unit, _pc, _val) \
   8688         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD08r), (_val))
   8689 #define MODIFY_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD08r(_unit, _pc, _val, _mask) \
   8690         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD08r), (_val), (_mask))
   8691 
   8692 #define READ_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD09r(_unit, _pc, _val) \
   8693         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD09r), (_val)) 
   8694 #define WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD09r(_unit, _pc, _val) \
   8695         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD09r), (_val))
   8696 #define MODIFY_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD09r(_unit, _pc, _val, _mask) \
   8697         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD09r), (_val), (_mask))
   8698 
   8699 #define READ_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD10r(_unit, _pc, _val) \
   8700         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD10r), (_val)) 
   8701 #define WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD10r(_unit, _pc, _val) \
   8702         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD10r), (_val))
   8703 #define MODIFY_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD10r(_unit, _pc, _val, _mask) \
   8704         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD10r), (_val), (_mask))
   8705 
   8706 #define READ_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD11r(_unit, _pc, _val) \
   8707         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD11r), (_val)) 
   8708 #define WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD11r(_unit, _pc, _val) \
   8709         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD11r), (_val))
   8710 #define MODIFY_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD11r(_unit, _pc, _val, _mask) \
   8711         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD11r), (_val), (_mask))
   8712 
   8713 #define READ_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD12r(_unit, _pc, _val) \
   8714         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD12r), (_val)) 
   8715 #define WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD12r(_unit, _pc, _val) \
   8716         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD12r), (_val))
   8717 #define MODIFY_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD12r(_unit, _pc, _val, _mask) \
   8718         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD12r), (_val), (_mask))
   8719 
   8720 #define READ_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD13r(_unit, _pc, _val) \
   8721         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD13r), (_val)) 
   8722 #define WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD13r(_unit, _pc, _val) \
   8723         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD13r), (_val))
   8724 #define MODIFY_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD13r(_unit, _pc, _val, _mask) \
   8725         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD13r), (_val), (_mask))
   8726 
   8727 #define READ_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD14r(_unit, _pc, _val) \
   8728         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD14r), (_val)) 
   8729 #define WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD14r(_unit, _pc, _val) \
   8730         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD14r), (_val))
   8731 #define MODIFY_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD14r(_unit, _pc, _val, _mask) \
   8732         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD14r), (_val), (_mask))
   8733 
   8734 #define READ_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD15r(_unit, _pc, _val) \
   8735         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD15r), (_val)) 
   8736 #define WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD15r(_unit, _pc, _val) \
   8737         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD15r), (_val))
   8738 #define MODIFY_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD15r(_unit, _pc, _val, _mask) \
   8739         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AD15r), (_val), (_mask))
   8740 
   8741 #define READ_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_BA0r(_unit, _pc, _val) \
   8742         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_BA0r), (_val)) 
   8743 #define WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_BA0r(_unit, _pc, _val) \
   8744         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_BA0r), (_val))
   8745 #define MODIFY_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_BA0r(_unit, _pc, _val, _mask) \
   8746         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_BA0r), (_val), (_mask))
   8747 
   8748 #define READ_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_BA1r(_unit, _pc, _val) \
   8749         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_BA1r), (_val)) 
   8750 #define WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_BA1r(_unit, _pc, _val) \
   8751         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_BA1r), (_val))
   8752 #define MODIFY_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_BA1r(_unit, _pc, _val, _mask) \
   8753         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_BA1r), (_val), (_mask))
   8754 
   8755 #define READ_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_BA2r(_unit, _pc, _val) \
   8756         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_BA2r), (_val)) 
   8757 #define WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_BA2r(_unit, _pc, _val) \
   8758         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_BA2r), (_val))
   8759 #define MODIFY_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_BA2r(_unit, _pc, _val, _mask) \
   8760         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_BA2r), (_val), (_mask))
   8761 
   8762 #define READ_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AUX0r(_unit, _pc, _val) \
   8763         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AUX0r), (_val)) 
   8764 #define WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AUX0r(_unit, _pc, _val) \
   8765         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AUX0r), (_val))
   8766 #define MODIFY_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AUX0r(_unit, _pc, _val, _mask) \
   8767         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AUX0r), (_val), (_mask))
   8768 
   8769 #define READ_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AUX1r(_unit, _pc, _val) \
   8770         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AUX1r), (_val)) 
   8771 #define WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AUX1r(_unit, _pc, _val) \
   8772         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AUX1r), (_val))
   8773 #define MODIFY_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AUX1r(_unit, _pc, _val, _mask) \
   8774         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AUX1r), (_val), (_mask))
   8775 
   8776 #define READ_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AUX2r(_unit, _pc, _val) \
   8777         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AUX2r), (_val)) 
   8778 #define WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AUX2r(_unit, _pc, _val) \
   8779         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AUX2r), (_val))
   8780 #define MODIFY_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AUX2r(_unit, _pc, _val, _mask) \
   8781         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_AUX2r), (_val), (_mask))
   8782 
   8783 #define READ_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_CS0r(_unit, _pc, _val) \
   8784         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_CS0r), (_val)) 
   8785 #define WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_CS0r(_unit, _pc, _val) \
   8786         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_CS0r), (_val))
   8787 #define MODIFY_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_CS0r(_unit, _pc, _val, _mask) \
   8788         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_CS0r), (_val), (_mask))
   8789 
   8790 #define READ_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_CS1r(_unit, _pc, _val) \
   8791         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_CS1r), (_val)) 
   8792 #define WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_CS1r(_unit, _pc, _val) \
   8793         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_CS1r), (_val))
   8794 #define MODIFY_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_CS1r(_unit, _pc, _val, _mask) \
   8795         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_CS1r), (_val), (_mask))
   8796 
   8797 #define READ_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_PARr(_unit, _pc, _val) \
   8798         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_PARr), (_val)) 
   8799 #define WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_PARr(_unit, _pc, _val) \
   8800         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_PARr), (_val))
   8801 #define MODIFY_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_PARr(_unit, _pc, _val, _mask) \
   8802         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_PARr), (_val), (_mask))
   8803 
   8804 #define READ_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_RAS_Nr(_unit, _pc, _val) \
   8805         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_RAS_Nr), (_val)) 
   8806 #define WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_RAS_Nr(_unit, _pc, _val) \
   8807         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_RAS_Nr), (_val))
   8808 #define MODIFY_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_RAS_Nr(_unit, _pc, _val, _mask) \
   8809         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_RAS_Nr), (_val), (_mask))
   8810 
   8811 #define READ_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_CAS_Nr(_unit, _pc, _val) \
   8812         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_CAS_Nr), (_val)) 
   8813 #define WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_CAS_Nr(_unit, _pc, _val) \
   8814         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_CAS_Nr), (_val))
   8815 #define MODIFY_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_CAS_Nr(_unit, _pc, _val, _mask) \
   8816         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_CAS_Nr), (_val), (_mask))
   8817 
   8818 #define READ_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_CKEr(_unit, _pc, _val) \
   8819         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_CKEr), (_val)) 
   8820 #define WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_CKEr(_unit, _pc, _val) \
   8821         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_CKEr), (_val))
   8822 #define MODIFY_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_CKEr(_unit, _pc, _val, _mask) \
   8823         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_CKEr), (_val), (_mask))
   8824 
   8825 #define READ_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_RST_Nr(_unit, _pc, _val) \
   8826         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_RST_Nr), (_val)) 
   8827 #define WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_RST_Nr(_unit, _pc, _val) \
   8828         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_RST_Nr), (_val))
   8829 #define MODIFY_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_RST_Nr(_unit, _pc, _val, _mask) \
   8830         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_RST_Nr), (_val), (_mask))
   8831 
   8832 #define READ_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_ODTr(_unit, _pc, _val) \
   8833         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_ODTr), (_val)) 
   8834 #define WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_ODTr(_unit, _pc, _val) \
   8835         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_ODTr), (_val))
   8836 #define MODIFY_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_ODTr(_unit, _pc, _val, _mask) \
   8837         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_ODTr), (_val), (_mask))
   8838 
   8839 #define READ_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_WE_Nr(_unit, _pc, _val) \
   8840         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_WE_Nr), (_val)) 
   8841 #define WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_WE_Nr(_unit, _pc, _val) \
   8842         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_WE_Nr), (_val))
   8843 #define MODIFY_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_WE_Nr(_unit, _pc, _val, _mask) \
   8844         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_WE_Nr), (_val), (_mask))
   8845 
   8846 #define READ_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_Pr(_unit, _pc, _val) \
   8847         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_Pr), (_val)) 
   8848 #define WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_Pr(_unit, _pc, _val) \
   8849         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_Pr), (_val))
   8850 #define MODIFY_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_Pr(_unit, _pc, _val, _mask) \
   8851         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_Pr), (_val), (_mask))
   8852 
   8853 #define READ_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_Nr(_unit, _pc, _val) \
   8854         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_Nr), (_val)) 
   8855 #define WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_Nr(_unit, _pc, _val) \
   8856         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_Nr), (_val))
   8857 #define MODIFY_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_Nr(_unit, _pc, _val, _mask) \
   8858         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_Nr), (_val), (_mask))
   8859 
   8860 #define READ_DDR34_PHY_CONTROL_REGS_VDL_CLK_CONTROLr(_unit, _pc, _val) \
   8861         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CLK_CONTROLr), (_val)) 
   8862 #define WRITE_DDR34_PHY_CONTROL_REGS_VDL_CLK_CONTROLr(_unit, _pc, _val) \
   8863         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CLK_CONTROLr), (_val))
   8864 #define MODIFY_DDR34_PHY_CONTROL_REGS_VDL_CLK_CONTROLr(_unit, _pc, _val, _mask) \
   8865         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CLK_CONTROLr), (_val), (_mask))
   8866 
   8867 #define READ_DDR34_PHY_CONTROL_REGS_VDL_LDE_CONTROLr(_unit, _pc, _val) \
   8868         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_LDE_CONTROLr), (_val)) 
   8869 #define WRITE_DDR34_PHY_CONTROL_REGS_VDL_LDE_CONTROLr(_unit, _pc, _val) \
   8870         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_LDE_CONTROLr), (_val))
   8871 #define MODIFY_DDR34_PHY_CONTROL_REGS_VDL_LDE_CONTROLr(_unit, _pc, _val, _mask) \
   8872         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_LDE_CONTROLr), (_val), (_mask))
   8873 
   8874 #define READ_DDR34_PHY_CONTROL_REGS_REFRESHr(_unit, _pc, _val) \
   8875         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_REFRESHr), (_val)) 
   8876 #define WRITE_DDR34_PHY_CONTROL_REGS_REFRESHr(_unit, _pc, _val) \
   8877         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_REFRESHr), (_val))
   8878 #define MODIFY_DDR34_PHY_CONTROL_REGS_REFRESHr(_unit, _pc, _val, _mask) \
   8879         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_REFRESHr), (_val), (_mask))
   8880 
   8881 #define READ_DDR34_PHY_CONTROL_REGS_UPDATE_VDLr(_unit, _pc, _val) \
   8882         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_UPDATE_VDLr), (_val)) 
   8883 #define WRITE_DDR34_PHY_CONTROL_REGS_UPDATE_VDLr(_unit, _pc, _val) \
   8884         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_UPDATE_VDLr), (_val))
   8885 #define MODIFY_DDR34_PHY_CONTROL_REGS_UPDATE_VDLr(_unit, _pc, _val, _mask) \
   8886         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_UPDATE_VDLr), (_val), (_mask))
   8887 
   8888 #define READ_DDR34_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1r(_unit, _pc, _val) \
   8889         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1r), (_val)) 
   8890 #define WRITE_DDR34_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1r(_unit, _pc, _val) \
   8891         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1r), (_val))
   8892 #define MODIFY_DDR34_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1r(_unit, _pc, _val, _mask) \
   8893         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1r), (_val), (_mask))
   8894 
   8895 #define READ_DDR34_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2r(_unit, _pc, _val) \
   8896         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2r), (_val)) 
   8897 #define WRITE_DDR34_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2r(_unit, _pc, _val) \
   8898         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2r), (_val))
   8899 #define MODIFY_DDR34_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2r(_unit, _pc, _val, _mask) \
   8900         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2r), (_val), (_mask))
   8901 
   8902 #define READ_DDR34_PHY_CONTROL_REGS_COMMAND_REG1r(_unit, _pc, _val) \
   8903         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_COMMAND_REG1r), (_val)) 
   8904 #define WRITE_DDR34_PHY_CONTROL_REGS_COMMAND_REG1r(_unit, _pc, _val) \
   8905         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_COMMAND_REG1r), (_val))
   8906 #define MODIFY_DDR34_PHY_CONTROL_REGS_COMMAND_REG1r(_unit, _pc, _val, _mask) \
   8907         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_COMMAND_REG1r), (_val), (_mask))
   8908 
   8909 #define READ_DDR34_PHY_CONTROL_REGS_COMMAND_AUX_REG1r(_unit, _pc, _val) \
   8910         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_COMMAND_AUX_REG1r), (_val)) 
   8911 #define WRITE_DDR34_PHY_CONTROL_REGS_COMMAND_AUX_REG1r(_unit, _pc, _val) \
   8912         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_COMMAND_AUX_REG1r), (_val))
   8913 #define MODIFY_DDR34_PHY_CONTROL_REGS_COMMAND_AUX_REG1r(_unit, _pc, _val, _mask) \
   8914         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_COMMAND_AUX_REG1r), (_val), (_mask))
   8915 
   8916 #define READ_DDR34_PHY_CONTROL_REGS_COMMAND_REG2r(_unit, _pc, _val) \
   8917         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_COMMAND_REG2r), (_val)) 
   8918 #define WRITE_DDR34_PHY_CONTROL_REGS_COMMAND_REG2r(_unit, _pc, _val) \
   8919         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_COMMAND_REG2r), (_val))
   8920 #define MODIFY_DDR34_PHY_CONTROL_REGS_COMMAND_REG2r(_unit, _pc, _val, _mask) \
   8921         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_COMMAND_REG2r), (_val), (_mask))
   8922 
   8923 #define READ_DDR34_PHY_CONTROL_REGS_COMMAND_AUX_REG2r(_unit, _pc, _val) \
   8924         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_COMMAND_AUX_REG2r), (_val)) 
   8925 #define WRITE_DDR34_PHY_CONTROL_REGS_COMMAND_AUX_REG2r(_unit, _pc, _val) \
   8926         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_COMMAND_AUX_REG2r), (_val))
   8927 #define MODIFY_DDR34_PHY_CONTROL_REGS_COMMAND_AUX_REG2r(_unit, _pc, _val, _mask) \
   8928         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_COMMAND_AUX_REG2r), (_val), (_mask))
   8929 
   8930 #define READ_DDR34_PHY_CONTROL_REGS_COMMAND_REG3r(_unit, _pc, _val) \
   8931         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_COMMAND_REG3r), (_val)) 
   8932 #define WRITE_DDR34_PHY_CONTROL_REGS_COMMAND_REG3r(_unit, _pc, _val) \
   8933         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_COMMAND_REG3r), (_val))
   8934 #define MODIFY_DDR34_PHY_CONTROL_REGS_COMMAND_REG3r(_unit, _pc, _val, _mask) \
   8935         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_COMMAND_REG3r), (_val), (_mask))
   8936 
   8937 #define READ_DDR34_PHY_CONTROL_REGS_COMMAND_AUX_REG3r(_unit, _pc, _val) \
   8938         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_COMMAND_AUX_REG3r), (_val)) 
   8939 #define WRITE_DDR34_PHY_CONTROL_REGS_COMMAND_AUX_REG3r(_unit, _pc, _val) \
   8940         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_COMMAND_AUX_REG3r), (_val))
   8941 #define MODIFY_DDR34_PHY_CONTROL_REGS_COMMAND_AUX_REG3r(_unit, _pc, _val, _mask) \
   8942         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_COMMAND_AUX_REG3r), (_val), (_mask))
   8943 
   8944 #define READ_DDR34_PHY_CONTROL_REGS_COMMAND_REG4r(_unit, _pc, _val) \
   8945         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_COMMAND_REG4r), (_val)) 
   8946 #define WRITE_DDR34_PHY_CONTROL_REGS_COMMAND_REG4r(_unit, _pc, _val) \
   8947         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_COMMAND_REG4r), (_val))
   8948 #define MODIFY_DDR34_PHY_CONTROL_REGS_COMMAND_REG4r(_unit, _pc, _val, _mask) \
   8949         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_COMMAND_REG4r), (_val), (_mask))
   8950 
   8951 #define READ_DDR34_PHY_CONTROL_REGS_COMMAND_AUX_REG4r(_unit, _pc, _val) \
   8952         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_COMMAND_AUX_REG4r), (_val)) 
   8953 #define WRITE_DDR34_PHY_CONTROL_REGS_COMMAND_AUX_REG4r(_unit, _pc, _val) \
   8954         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_COMMAND_AUX_REG4r), (_val))
   8955 #define MODIFY_DDR34_PHY_CONTROL_REGS_COMMAND_AUX_REG4r(_unit, _pc, _val, _mask) \
   8956         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_COMMAND_AUX_REG4r), (_val), (_mask))
   8957 
   8958 #define READ_DDR34_PHY_CONTROL_REGS_COMMAND_REG_TIMERr(_unit, _pc, _val) \
   8959         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_COMMAND_REG_TIMERr), (_val)) 
   8960 #define WRITE_DDR34_PHY_CONTROL_REGS_COMMAND_REG_TIMERr(_unit, _pc, _val) \
   8961         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_COMMAND_REG_TIMERr), (_val))
   8962 #define MODIFY_DDR34_PHY_CONTROL_REGS_COMMAND_REG_TIMERr(_unit, _pc, _val, _mask) \
   8963         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_COMMAND_REG_TIMERr), (_val), (_mask))
   8964 
   8965 #define READ_DDR34_PHY_CONTROL_REGS_MODE_REG0r(_unit, _pc, _val) \
   8966         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_MODE_REG0r), (_val)) 
   8967 #define WRITE_DDR34_PHY_CONTROL_REGS_MODE_REG0r(_unit, _pc, _val) \
   8968         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_MODE_REG0r), (_val))
   8969 #define MODIFY_DDR34_PHY_CONTROL_REGS_MODE_REG0r(_unit, _pc, _val, _mask) \
   8970         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_MODE_REG0r), (_val), (_mask))
   8971 
   8972 #define READ_DDR34_PHY_CONTROL_REGS_MODE_REG1r(_unit, _pc, _val) \
   8973         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_MODE_REG1r), (_val)) 
   8974 #define WRITE_DDR34_PHY_CONTROL_REGS_MODE_REG1r(_unit, _pc, _val) \
   8975         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_MODE_REG1r), (_val))
   8976 #define MODIFY_DDR34_PHY_CONTROL_REGS_MODE_REG1r(_unit, _pc, _val, _mask) \
   8977         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_MODE_REG1r), (_val), (_mask))
   8978 
   8979 #define READ_DDR34_PHY_CONTROL_REGS_MODE_REG2r(_unit, _pc, _val) \
   8980         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_MODE_REG2r), (_val)) 
   8981 #define WRITE_DDR34_PHY_CONTROL_REGS_MODE_REG2r(_unit, _pc, _val) \
   8982         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_MODE_REG2r), (_val))
   8983 #define MODIFY_DDR34_PHY_CONTROL_REGS_MODE_REG2r(_unit, _pc, _val, _mask) \
   8984         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_MODE_REG2r), (_val), (_mask))
   8985 
   8986 #define READ_DDR34_PHY_CONTROL_REGS_MODE_REG3r(_unit, _pc, _val) \
   8987         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_MODE_REG3r), (_val)) 
   8988 #define WRITE_DDR34_PHY_CONTROL_REGS_MODE_REG3r(_unit, _pc, _val) \
   8989         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_MODE_REG3r), (_val))
   8990 #define MODIFY_DDR34_PHY_CONTROL_REGS_MODE_REG3r(_unit, _pc, _val, _mask) \
   8991         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_MODE_REG3r), (_val), (_mask))
   8992 
   8993 #define READ_DDR34_PHY_CONTROL_REGS_MODE_REG4r(_unit, _pc, _val) \
   8994         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_MODE_REG4r), (_val)) 
   8995 #define WRITE_DDR34_PHY_CONTROL_REGS_MODE_REG4r(_unit, _pc, _val) \
   8996         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_MODE_REG4r), (_val))
   8997 #define MODIFY_DDR34_PHY_CONTROL_REGS_MODE_REG4r(_unit, _pc, _val, _mask) \
   8998         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_MODE_REG4r), (_val), (_mask))
   8999 
   9000 #define READ_DDR34_PHY_CONTROL_REGS_MODE_REG5r(_unit, _pc, _val) \
   9001         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_MODE_REG5r), (_val)) 
   9002 #define WRITE_DDR34_PHY_CONTROL_REGS_MODE_REG5r(_unit, _pc, _val) \
   9003         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_MODE_REG5r), (_val))
   9004 #define MODIFY_DDR34_PHY_CONTROL_REGS_MODE_REG5r(_unit, _pc, _val, _mask) \
   9005         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_MODE_REG5r), (_val), (_mask))
   9006 
   9007 #define READ_DDR34_PHY_CONTROL_REGS_MODE_REG6r(_unit, _pc, _val) \
   9008         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_MODE_REG6r), (_val)) 
   9009 #define WRITE_DDR34_PHY_CONTROL_REGS_MODE_REG6r(_unit, _pc, _val) \
   9010         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_MODE_REG6r), (_val))
   9011 #define MODIFY_DDR34_PHY_CONTROL_REGS_MODE_REG6r(_unit, _pc, _val, _mask) \
   9012         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_MODE_REG6r), (_val), (_mask))
   9013 
   9014 #define READ_DDR34_PHY_CONTROL_REGS_MODE_REG7r(_unit, _pc, _val) \
   9015         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_MODE_REG7r), (_val)) 
   9016 #define WRITE_DDR34_PHY_CONTROL_REGS_MODE_REG7r(_unit, _pc, _val) \
   9017         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_MODE_REG7r), (_val))
   9018 #define MODIFY_DDR34_PHY_CONTROL_REGS_MODE_REG7r(_unit, _pc, _val, _mask) \
   9019         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_MODE_REG7r), (_val), (_mask))
   9020 
   9021 #define READ_DDR34_PHY_CONTROL_REGS_MODE_REG8r(_unit, _pc, _val) \
   9022         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_MODE_REG8r), (_val)) 
   9023 #define WRITE_DDR34_PHY_CONTROL_REGS_MODE_REG8r(_unit, _pc, _val) \
   9024         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_MODE_REG8r), (_val))
   9025 #define MODIFY_DDR34_PHY_CONTROL_REGS_MODE_REG8r(_unit, _pc, _val, _mask) \
   9026         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_MODE_REG8r), (_val), (_mask))
   9027 
   9028 #define READ_DDR34_PHY_CONTROL_REGS_MODE_REG15r(_unit, _pc, _val) \
   9029         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_MODE_REG15r), (_val)) 
   9030 #define WRITE_DDR34_PHY_CONTROL_REGS_MODE_REG15r(_unit, _pc, _val) \
   9031         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_MODE_REG15r), (_val))
   9032 #define MODIFY_DDR34_PHY_CONTROL_REGS_MODE_REG15r(_unit, _pc, _val, _mask) \
   9033         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_MODE_REG15r), (_val), (_mask))
   9034 
   9035 #define READ_DDR34_PHY_CONTROL_REGS_MODE_REG63r(_unit, _pc, _val) \
   9036         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_MODE_REG63r), (_val)) 
   9037 #define WRITE_DDR34_PHY_CONTROL_REGS_MODE_REG63r(_unit, _pc, _val) \
   9038         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_MODE_REG63r), (_val))
   9039 #define MODIFY_DDR34_PHY_CONTROL_REGS_MODE_REG63r(_unit, _pc, _val, _mask) \
   9040         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_MODE_REG63r), (_val), (_mask))
   9041 
   9042 #define READ_DDR34_PHY_CONTROL_REGS_ALERT_CLEARr(_unit, _pc, _val) \
   9043         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_ALERT_CLEARr), (_val)) 
   9044 #define WRITE_DDR34_PHY_CONTROL_REGS_ALERT_CLEARr(_unit, _pc, _val) \
   9045         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_ALERT_CLEARr), (_val))
   9046 #define MODIFY_DDR34_PHY_CONTROL_REGS_ALERT_CLEARr(_unit, _pc, _val, _mask) \
   9047         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_ALERT_CLEARr), (_val), (_mask))
   9048 
   9049 #define READ_DDR34_PHY_CONTROL_REGS_ALERT_STATUSr(_unit, _pc, _val) \
   9050         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_ALERT_STATUSr), (_val)) 
   9051 #define WRITE_DDR34_PHY_CONTROL_REGS_ALERT_STATUSr(_unit, _pc, _val) \
   9052         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_ALERT_STATUSr), (_val))
   9053 #define MODIFY_DDR34_PHY_CONTROL_REGS_ALERT_STATUSr(_unit, _pc, _val, _mask) \
   9054         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_ALERT_STATUSr), (_val), (_mask))
   9055 
   9056 #define READ_DDR34_PHY_CONTROL_REGS_CA_PARITYr(_unit, _pc, _val) \
   9057         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_CA_PARITYr), (_val)) 
   9058 #define WRITE_DDR34_PHY_CONTROL_REGS_CA_PARITYr(_unit, _pc, _val) \
   9059         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_CA_PARITYr), (_val))
   9060 #define MODIFY_DDR34_PHY_CONTROL_REGS_CA_PARITYr(_unit, _pc, _val, _mask) \
   9061         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_CA_PARITYr), (_val), (_mask))
   9062 
   9063 #define READ_DDR34_PHY_CONTROL_REGS_CA_PLAYBACK_CONTROLr(_unit, _pc, _val) \
   9064         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_CA_PLAYBACK_CONTROLr), (_val)) 
   9065 #define WRITE_DDR34_PHY_CONTROL_REGS_CA_PLAYBACK_CONTROLr(_unit, _pc, _val) \
   9066         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_CA_PLAYBACK_CONTROLr), (_val))
   9067 #define MODIFY_DDR34_PHY_CONTROL_REGS_CA_PLAYBACK_CONTROLr(_unit, _pc, _val, _mask) \
   9068         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_CA_PLAYBACK_CONTROLr), (_val), (_mask))
   9069 
   9070 #define READ_DDR34_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS0r(_unit, _pc, _val) \
   9071         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS0r), (_val)) 
   9072 #define WRITE_DDR34_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS0r(_unit, _pc, _val) \
   9073         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS0r), (_val))
   9074 #define MODIFY_DDR34_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS0r(_unit, _pc, _val, _mask) \
   9075         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS0r), (_val), (_mask))
   9076 
   9077 #define READ_DDR34_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS1r(_unit, _pc, _val) \
   9078         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS1r), (_val)) 
   9079 #define WRITE_DDR34_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS1r(_unit, _pc, _val) \
   9080         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS1r), (_val))
   9081 #define MODIFY_DDR34_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS1r(_unit, _pc, _val, _mask) \
   9082         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS1r), (_val), (_mask))
   9083 
   9084 #define READ_DDR34_PHY_CONTROL_REGS_WRITE_LEVELING_CONTROLr(_unit, _pc, _val) \
   9085         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_WRITE_LEVELING_CONTROLr), (_val)) 
   9086 #define WRITE_DDR34_PHY_CONTROL_REGS_WRITE_LEVELING_CONTROLr(_unit, _pc, _val) \
   9087         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_WRITE_LEVELING_CONTROLr), (_val))
   9088 #define MODIFY_DDR34_PHY_CONTROL_REGS_WRITE_LEVELING_CONTROLr(_unit, _pc, _val, _mask) \
   9089         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_WRITE_LEVELING_CONTROLr), (_val), (_mask))
   9090 
   9091 #define READ_DDR34_PHY_CONTROL_REGS_WRITE_LEVELING_STATUSr(_unit, _pc, _val) \
   9092         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_WRITE_LEVELING_STATUSr), (_val)) 
   9093 #define WRITE_DDR34_PHY_CONTROL_REGS_WRITE_LEVELING_STATUSr(_unit, _pc, _val) \
   9094         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_WRITE_LEVELING_STATUSr), (_val))
   9095 #define MODIFY_DDR34_PHY_CONTROL_REGS_WRITE_LEVELING_STATUSr(_unit, _pc, _val, _mask) \
   9096         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_WRITE_LEVELING_STATUSr), (_val), (_mask))
   9097 
   9098 #define READ_DDR34_PHY_CONTROL_REGS_READ_ENABLE_CONTROLr(_unit, _pc, _val) \
   9099         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_READ_ENABLE_CONTROLr), (_val)) 
   9100 #define WRITE_DDR34_PHY_CONTROL_REGS_READ_ENABLE_CONTROLr(_unit, _pc, _val) \
   9101         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_READ_ENABLE_CONTROLr), (_val))
   9102 #define MODIFY_DDR34_PHY_CONTROL_REGS_READ_ENABLE_CONTROLr(_unit, _pc, _val, _mask) \
   9103         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_READ_ENABLE_CONTROLr), (_val), (_mask))
   9104 
   9105 #define READ_DDR34_PHY_CONTROL_REGS_READ_ENABLE_STATUSr(_unit, _pc, _val) \
   9106         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_READ_ENABLE_STATUSr), (_val)) 
   9107 #define WRITE_DDR34_PHY_CONTROL_REGS_READ_ENABLE_STATUSr(_unit, _pc, _val) \
   9108         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_READ_ENABLE_STATUSr), (_val))
   9109 #define MODIFY_DDR34_PHY_CONTROL_REGS_READ_ENABLE_STATUSr(_unit, _pc, _val, _mask) \
   9110         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_READ_ENABLE_STATUSr), (_val), (_mask))
   9111 
   9112 #define READ_DDR34_PHY_CONTROL_REGS_TRAFFIC_GEN_LFSR_SEEDr(_unit, _pc, _val) \
   9113         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_TRAFFIC_GEN_LFSR_SEEDr), (_val)) 
   9114 #define WRITE_DDR34_PHY_CONTROL_REGS_TRAFFIC_GEN_LFSR_SEEDr(_unit, _pc, _val) \
   9115         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_TRAFFIC_GEN_LFSR_SEEDr), (_val))
   9116 #define MODIFY_DDR34_PHY_CONTROL_REGS_TRAFFIC_GEN_LFSR_SEEDr(_unit, _pc, _val, _mask) \
   9117         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_TRAFFIC_GEN_LFSR_SEEDr), (_val), (_mask))
   9118 
   9119 #define READ_DDR34_PHY_CONTROL_REGS_TRAFFIC_GEN_ADDRESS1r(_unit, _pc, _val) \
   9120         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_TRAFFIC_GEN_ADDRESS1r), (_val)) 
   9121 #define WRITE_DDR34_PHY_CONTROL_REGS_TRAFFIC_GEN_ADDRESS1r(_unit, _pc, _val) \
   9122         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_TRAFFIC_GEN_ADDRESS1r), (_val))
   9123 #define MODIFY_DDR34_PHY_CONTROL_REGS_TRAFFIC_GEN_ADDRESS1r(_unit, _pc, _val, _mask) \
   9124         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_TRAFFIC_GEN_ADDRESS1r), (_val), (_mask))
   9125 
   9126 #define READ_DDR34_PHY_CONTROL_REGS_TRAFFIC_GEN_ADDRESS2r(_unit, _pc, _val) \
   9127         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_TRAFFIC_GEN_ADDRESS2r), (_val)) 
   9128 #define WRITE_DDR34_PHY_CONTROL_REGS_TRAFFIC_GEN_ADDRESS2r(_unit, _pc, _val) \
   9129         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_TRAFFIC_GEN_ADDRESS2r), (_val))
   9130 #define MODIFY_DDR34_PHY_CONTROL_REGS_TRAFFIC_GEN_ADDRESS2r(_unit, _pc, _val, _mask) \
   9131         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_TRAFFIC_GEN_ADDRESS2r), (_val), (_mask))
   9132 
   9133 #define READ_DDR34_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROLr(_unit, _pc, _val) \
   9134         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROLr), (_val)) 
   9135 #define WRITE_DDR34_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROLr(_unit, _pc, _val) \
   9136         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROLr), (_val))
   9137 #define MODIFY_DDR34_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROLr(_unit, _pc, _val, _mask) \
   9138         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROLr), (_val), (_mask))
   9139 
   9140 #define READ_DDR34_PHY_CONTROL_REGS_TRAFFIC_GEN_DATA_CONTROLr(_unit, _pc, _val) \
   9141         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_TRAFFIC_GEN_DATA_CONTROLr), (_val)) 
   9142 #define WRITE_DDR34_PHY_CONTROL_REGS_TRAFFIC_GEN_DATA_CONTROLr(_unit, _pc, _val) \
   9143         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_TRAFFIC_GEN_DATA_CONTROLr), (_val))
   9144 #define MODIFY_DDR34_PHY_CONTROL_REGS_TRAFFIC_GEN_DATA_CONTROLr(_unit, _pc, _val, _mask) \
   9145         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_TRAFFIC_GEN_DATA_CONTROLr), (_val), (_mask))
   9146 
   9147 #define READ_DDR34_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_MASKr(_unit, _pc, _val) \
   9148         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_MASKr), (_val)) 
   9149 #define WRITE_DDR34_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_MASKr(_unit, _pc, _val) \
   9150         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_MASKr), (_val))
   9151 #define MODIFY_DDR34_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_MASKr(_unit, _pc, _val, _mask) \
   9152         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_MASKr), (_val), (_mask))
   9153 
   9154 #define READ_DDR34_PHY_CONTROL_REGS_TRAFFIC_GEN_ECC_DQ_MASKr(_unit, _pc, _val) \
   9155         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_TRAFFIC_GEN_ECC_DQ_MASKr), (_val)) 
   9156 #define WRITE_DDR34_PHY_CONTROL_REGS_TRAFFIC_GEN_ECC_DQ_MASKr(_unit, _pc, _val) \
   9157         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_TRAFFIC_GEN_ECC_DQ_MASKr), (_val))
   9158 #define MODIFY_DDR34_PHY_CONTROL_REGS_TRAFFIC_GEN_ECC_DQ_MASKr(_unit, _pc, _val, _mask) \
   9159         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_TRAFFIC_GEN_ECC_DQ_MASKr), (_val), (_mask))
   9160 
   9161 #define READ_DDR34_PHY_CONTROL_REGS_TRAFFIC_GEN_STATUSr(_unit, _pc, _val) \
   9162         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_TRAFFIC_GEN_STATUSr), (_val)) 
   9163 #define WRITE_DDR34_PHY_CONTROL_REGS_TRAFFIC_GEN_STATUSr(_unit, _pc, _val) \
   9164         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_TRAFFIC_GEN_STATUSr), (_val))
   9165 #define MODIFY_DDR34_PHY_CONTROL_REGS_TRAFFIC_GEN_STATUSr(_unit, _pc, _val, _mask) \
   9166         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_TRAFFIC_GEN_STATUSr), (_val), (_mask))
   9167 
   9168 #define READ_DDR34_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUSr(_unit, _pc, _val) \
   9169         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUSr), (_val)) 
   9170 #define WRITE_DDR34_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUSr(_unit, _pc, _val) \
   9171         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUSr), (_val))
   9172 #define MODIFY_DDR34_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUSr(_unit, _pc, _val, _mask) \
   9173         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUSr), (_val), (_mask))
   9174 
   9175 #define READ_DDR34_PHY_CONTROL_REGS_TRAFFIC_GEN_ECC_STATUSr(_unit, _pc, _val) \
   9176         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_TRAFFIC_GEN_ECC_STATUSr), (_val)) 
   9177 #define WRITE_DDR34_PHY_CONTROL_REGS_TRAFFIC_GEN_ECC_STATUSr(_unit, _pc, _val) \
   9178         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_TRAFFIC_GEN_ECC_STATUSr), (_val))
   9179 #define MODIFY_DDR34_PHY_CONTROL_REGS_TRAFFIC_GEN_ECC_STATUSr(_unit, _pc, _val, _mask) \
   9180         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_TRAFFIC_GEN_ECC_STATUSr), (_val), (_mask))
   9181 
   9182 #define READ_DDR34_PHY_CONTROL_REGS_TRAFFIC_GEN_ERR_CNT_CONTROLr(_unit, _pc, _val) \
   9183         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_TRAFFIC_GEN_ERR_CNT_CONTROLr), (_val)) 
   9184 #define WRITE_DDR34_PHY_CONTROL_REGS_TRAFFIC_GEN_ERR_CNT_CONTROLr(_unit, _pc, _val) \
   9185         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_TRAFFIC_GEN_ERR_CNT_CONTROLr), (_val))
   9186 #define MODIFY_DDR34_PHY_CONTROL_REGS_TRAFFIC_GEN_ERR_CNT_CONTROLr(_unit, _pc, _val, _mask) \
   9187         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_TRAFFIC_GEN_ERR_CNT_CONTROLr), (_val), (_mask))
   9188 
   9189 #define READ_DDR34_PHY_CONTROL_REGS_TRAFFIC_GEN_ERR_CNT_STATUSr(_unit, _pc, _val) \
   9190         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_TRAFFIC_GEN_ERR_CNT_STATUSr), (_val)) 
   9191 #define WRITE_DDR34_PHY_CONTROL_REGS_TRAFFIC_GEN_ERR_CNT_STATUSr(_unit, _pc, _val) \
   9192         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_TRAFFIC_GEN_ERR_CNT_STATUSr), (_val))
   9193 #define MODIFY_DDR34_PHY_CONTROL_REGS_TRAFFIC_GEN_ERR_CNT_STATUSr(_unit, _pc, _val, _mask) \
   9194         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_TRAFFIC_GEN_ERR_CNT_STATUSr), (_val), (_mask))
   9195 
   9196 #define READ_DDR34_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROLr(_unit, _pc, _val) \
   9197         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROLr), (_val)) 
   9198 #define WRITE_DDR34_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROLr(_unit, _pc, _val) \
   9199         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROLr), (_val))
   9200 #define MODIFY_DDR34_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROLr(_unit, _pc, _val, _mask) \
   9201         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROLr), (_val), (_mask))
   9202 
   9203 #define READ_DDR34_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUSr(_unit, _pc, _val) \
   9204         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUSr), (_val)) 
   9205 #define WRITE_DDR34_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUSr(_unit, _pc, _val) \
   9206         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUSr), (_val))
   9207 #define MODIFY_DDR34_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUSr(_unit, _pc, _val, _mask) \
   9208         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUSr), (_val), (_mask))
   9209 
   9210 #define READ_DDR34_PHY_CONTROL_REGS_VIRTUAL_VTT_CONNECTIONSr(_unit, _pc, _val) \
   9211         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VIRTUAL_VTT_CONNECTIONSr), (_val)) 
   9212 #define WRITE_DDR34_PHY_CONTROL_REGS_VIRTUAL_VTT_CONNECTIONSr(_unit, _pc, _val) \
   9213         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VIRTUAL_VTT_CONNECTIONSr), (_val))
   9214 #define MODIFY_DDR34_PHY_CONTROL_REGS_VIRTUAL_VTT_CONNECTIONSr(_unit, _pc, _val, _mask) \
   9215         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VIRTUAL_VTT_CONNECTIONSr), (_val), (_mask))
   9216 
   9217 #define READ_DDR34_PHY_CONTROL_REGS_VIRTUAL_VTT_OVERRIDEr(_unit, _pc, _val) \
   9218         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VIRTUAL_VTT_OVERRIDEr), (_val)) 
   9219 #define WRITE_DDR34_PHY_CONTROL_REGS_VIRTUAL_VTT_OVERRIDEr(_unit, _pc, _val) \
   9220         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VIRTUAL_VTT_OVERRIDEr), (_val))
   9221 #define MODIFY_DDR34_PHY_CONTROL_REGS_VIRTUAL_VTT_OVERRIDEr(_unit, _pc, _val, _mask) \
   9222         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VIRTUAL_VTT_OVERRIDEr), (_val), (_mask))
   9223 
   9224 #define READ_DDR34_PHY_CONTROL_REGS_VREF_DAC_CONTROLr(_unit, _pc, _val) \
   9225         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VREF_DAC_CONTROLr), (_val)) 
   9226 #define WRITE_DDR34_PHY_CONTROL_REGS_VREF_DAC_CONTROLr(_unit, _pc, _val) \
   9227         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VREF_DAC_CONTROLr), (_val))
   9228 #define MODIFY_DDR34_PHY_CONTROL_REGS_VREF_DAC_CONTROLr(_unit, _pc, _val, _mask) \
   9229         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VREF_DAC_CONTROLr), (_val), (_mask))
   9230 
   9231 #define READ_DDR34_PHY_CONTROL_REGS_PHYBIST_CNTRLr(_unit, _pc, _val) \
   9232         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_PHYBIST_CNTRLr), (_val)) 
   9233 #define WRITE_DDR34_PHY_CONTROL_REGS_PHYBIST_CNTRLr(_unit, _pc, _val) \
   9234         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_PHYBIST_CNTRLr), (_val))
   9235 #define MODIFY_DDR34_PHY_CONTROL_REGS_PHYBIST_CNTRLr(_unit, _pc, _val, _mask) \
   9236         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_PHYBIST_CNTRLr), (_val), (_mask))
   9237 
   9238 #define READ_DDR34_PHY_CONTROL_REGS_PHYBIST_SEEDr(_unit, _pc, _val) \
   9239         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_PHYBIST_SEEDr), (_val)) 
   9240 #define WRITE_DDR34_PHY_CONTROL_REGS_PHYBIST_SEEDr(_unit, _pc, _val) \
   9241         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_PHYBIST_SEEDr), (_val))
   9242 #define MODIFY_DDR34_PHY_CONTROL_REGS_PHYBIST_SEEDr(_unit, _pc, _val, _mask) \
   9243         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_PHYBIST_SEEDr), (_val), (_mask))
   9244 
   9245 #define READ_DDR34_PHY_CONTROL_REGS_PHYBIST_STATUSr(_unit, _pc, _val) \
   9246         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_PHYBIST_STATUSr), (_val)) 
   9247 #define WRITE_DDR34_PHY_CONTROL_REGS_PHYBIST_STATUSr(_unit, _pc, _val) \
   9248         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_PHYBIST_STATUSr), (_val))
   9249 #define MODIFY_DDR34_PHY_CONTROL_REGS_PHYBIST_STATUSr(_unit, _pc, _val, _mask) \
   9250         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_PHYBIST_STATUSr), (_val), (_mask))
   9251 
   9252 #define READ_DDR34_PHY_CONTROL_REGS_PHYBIST_CTL_STATUSr(_unit, _pc, _val) \
   9253         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_PHYBIST_CTL_STATUSr), (_val)) 
   9254 #define WRITE_DDR34_PHY_CONTROL_REGS_PHYBIST_CTL_STATUSr(_unit, _pc, _val) \
   9255         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_PHYBIST_CTL_STATUSr), (_val))
   9256 #define MODIFY_DDR34_PHY_CONTROL_REGS_PHYBIST_CTL_STATUSr(_unit, _pc, _val, _mask) \
   9257         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_PHYBIST_CTL_STATUSr), (_val), (_mask))
   9258 
   9259 #define READ_DDR34_PHY_CONTROL_REGS_PHYBIST_BL0_STATUSr(_unit, _pc, _val) \
   9260         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_PHYBIST_BL0_STATUSr), (_val)) 
   9261 #define WRITE_DDR34_PHY_CONTROL_REGS_PHYBIST_BL0_STATUSr(_unit, _pc, _val) \
   9262         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_PHYBIST_BL0_STATUSr), (_val))
   9263 #define MODIFY_DDR34_PHY_CONTROL_REGS_PHYBIST_BL0_STATUSr(_unit, _pc, _val, _mask) \
   9264         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_PHYBIST_BL0_STATUSr), (_val), (_mask))
   9265 
   9266 #define READ_DDR34_PHY_CONTROL_REGS_PHYBIST_BL1_STATUSr(_unit, _pc, _val) \
   9267         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_PHYBIST_BL1_STATUSr), (_val)) 
   9268 #define WRITE_DDR34_PHY_CONTROL_REGS_PHYBIST_BL1_STATUSr(_unit, _pc, _val) \
   9269         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_PHYBIST_BL1_STATUSr), (_val))
   9270 #define MODIFY_DDR34_PHY_CONTROL_REGS_PHYBIST_BL1_STATUSr(_unit, _pc, _val, _mask) \
   9271         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_PHYBIST_BL1_STATUSr), (_val), (_mask))
   9272 
   9273 #define READ_DDR34_PHY_CONTROL_REGS_PHYBIST_BL2_STATUSr(_unit, _pc, _val) \
   9274         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_PHYBIST_BL2_STATUSr), (_val)) 
   9275 #define WRITE_DDR34_PHY_CONTROL_REGS_PHYBIST_BL2_STATUSr(_unit, _pc, _val) \
   9276         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_PHYBIST_BL2_STATUSr), (_val))
   9277 #define MODIFY_DDR34_PHY_CONTROL_REGS_PHYBIST_BL2_STATUSr(_unit, _pc, _val, _mask) \
   9278         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_PHYBIST_BL2_STATUSr), (_val), (_mask))
   9279 
   9280 #define READ_DDR34_PHY_CONTROL_REGS_PHYBIST_BL3_STATUSr(_unit, _pc, _val) \
   9281         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_PHYBIST_BL3_STATUSr), (_val)) 
   9282 #define WRITE_DDR34_PHY_CONTROL_REGS_PHYBIST_BL3_STATUSr(_unit, _pc, _val) \
   9283         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_PHYBIST_BL3_STATUSr), (_val))
   9284 #define MODIFY_DDR34_PHY_CONTROL_REGS_PHYBIST_BL3_STATUSr(_unit, _pc, _val, _mask) \
   9285         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_PHYBIST_BL3_STATUSr), (_val), (_mask))
   9286 
   9287 #define READ_DDR34_PHY_CONTROL_REGS_PHYBIST_BL4_STATUSr(_unit, _pc, _val) \
   9288         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_PHYBIST_BL4_STATUSr), (_val)) 
   9289 #define WRITE_DDR34_PHY_CONTROL_REGS_PHYBIST_BL4_STATUSr(_unit, _pc, _val) \
   9290         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_PHYBIST_BL4_STATUSr), (_val))
   9291 #define MODIFY_DDR34_PHY_CONTROL_REGS_PHYBIST_BL4_STATUSr(_unit, _pc, _val, _mask) \
   9292         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_PHYBIST_BL4_STATUSr), (_val), (_mask))
   9293 
   9294 #define READ_DDR34_PHY_CONTROL_REGS_STANDBY_CONTROLr(_unit, _pc, _val) \
   9295         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_STANDBY_CONTROLr), (_val)) 
   9296 #define WRITE_DDR34_PHY_CONTROL_REGS_STANDBY_CONTROLr(_unit, _pc, _val) \
   9297         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_STANDBY_CONTROLr), (_val))
   9298 #define MODIFY_DDR34_PHY_CONTROL_REGS_STANDBY_CONTROLr(_unit, _pc, _val, _mask) \
   9299         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_STANDBY_CONTROLr), (_val), (_mask))
   9300 
   9301 #define READ_DDR34_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLEr(_unit, _pc, _val) \
   9302         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLEr), (_val)) 
   9303 #define WRITE_DDR34_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLEr(_unit, _pc, _val) \
   9304         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLEr), (_val))
   9305 #define MODIFY_DDR34_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLEr(_unit, _pc, _val, _mask) \
   9306         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLEr), (_val), (_mask))
   9307 
   9308 #define READ_DDR34_PHY_CONTROL_REGS_DEBUG_MUX_CONTROLr(_unit, _pc, _val) \
   9309         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_DEBUG_MUX_CONTROLr), (_val)) 
   9310 #define WRITE_DDR34_PHY_CONTROL_REGS_DEBUG_MUX_CONTROLr(_unit, _pc, _val) \
   9311         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_DEBUG_MUX_CONTROLr), (_val))
   9312 #define MODIFY_DDR34_PHY_CONTROL_REGS_DEBUG_MUX_CONTROLr(_unit, _pc, _val, _mask) \
   9313         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_DEBUG_MUX_CONTROLr), (_val), (_mask))
   9314 
   9315 #define READ_DDR34_PHY_CONTROL_REGS_DFI_CNTRLr(_unit, _pc, _val) \
   9316         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_DFI_CNTRLr), (_val)) 
   9317 #define WRITE_DDR34_PHY_CONTROL_REGS_DFI_CNTRLr(_unit, _pc, _val) \
   9318         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_DFI_CNTRLr), (_val))
   9319 #define MODIFY_DDR34_PHY_CONTROL_REGS_DFI_CNTRLr(_unit, _pc, _val, _mask) \
   9320         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_DFI_CNTRLr), (_val), (_mask))
   9321 
   9322 #define READ_DDR34_PHY_CONTROL_REGS_WRITE_ODT_CNTRLr(_unit, _pc, _val) \
   9323         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_WRITE_ODT_CNTRLr), (_val)) 
   9324 #define WRITE_DDR34_PHY_CONTROL_REGS_WRITE_ODT_CNTRLr(_unit, _pc, _val) \
   9325         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_WRITE_ODT_CNTRLr), (_val))
   9326 #define MODIFY_DDR34_PHY_CONTROL_REGS_WRITE_ODT_CNTRLr(_unit, _pc, _val, _mask) \
   9327         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_WRITE_ODT_CNTRLr), (_val), (_mask))
   9328 
   9329 #define READ_DDR34_PHY_CONTROL_REGS_ABI_PAR_CNTRLr(_unit, _pc, _val) \
   9330         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_ABI_PAR_CNTRLr), (_val)) 
   9331 #define WRITE_DDR34_PHY_CONTROL_REGS_ABI_PAR_CNTRLr(_unit, _pc, _val) \
   9332         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_ABI_PAR_CNTRLr), (_val))
   9333 #define MODIFY_DDR34_PHY_CONTROL_REGS_ABI_PAR_CNTRLr(_unit, _pc, _val, _mask) \
   9334         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_ABI_PAR_CNTRLr), (_val), (_mask))
   9335 
   9336 #define READ_DDR34_PHY_CONTROL_REGS_ZQ_CALr(_unit, _pc, _val) \
   9337         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_ZQ_CALr), (_val)) 
   9338 #define WRITE_DDR34_PHY_CONTROL_REGS_ZQ_CALr(_unit, _pc, _val) \
   9339         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_ZQ_CALr), (_val))
   9340 #define MODIFY_DDR34_PHY_CONTROL_REGS_ZQ_CALr(_unit, _pc, _val, _mask) \
   9341         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_ZQ_CALr), (_val), (_mask))
   9342 
   9343 #define READ_DDR34_PHY_CONTROL_REGS_AC_SPARE_REGr(_unit, _pc, _val) \
   9344         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_AC_SPARE_REGr), (_val)) 
   9345 #define WRITE_DDR34_PHY_CONTROL_REGS_AC_SPARE_REGr(_unit, _pc, _val) \
   9346         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_AC_SPARE_REGr), (_val))
   9347 #define MODIFY_DDR34_PHY_CONTROL_REGS_AC_SPARE_REGr(_unit, _pc, _val, _mask) \
   9348         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_AC_SPARE_REGr), (_val), (_mask))
   9349 
   9350 
   9351 /***************************************************************************
   9352  *DDR34_E0_PHY_BYTE_LANE_0 - DDR34 CORE DDR34 Byte Lane #0 control registers
   9353  */
   9354 #define READ_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_Pr(_unit, _pc, _val) \
   9355         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_Pr), (_val)) 
   9356 #define WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_Pr(_unit, _pc, _val) \
   9357         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_Pr), (_val))
   9358 #define MODIFY_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_Pr(_unit, _pc, _val, _mask) \
   9359         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_Pr), (_val), (_mask))
   9360 
   9361 #define READ_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_Nr(_unit, _pc, _val) \
   9362         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_Nr), (_val)) 
   9363 #define WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_Nr(_unit, _pc, _val) \
   9364         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_Nr), (_val))
   9365 #define MODIFY_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_Nr(_unit, _pc, _val, _mask) \
   9366         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_Nr), (_val), (_mask))
   9367 
   9368 #define READ_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0r(_unit, _pc, _val) \
   9369         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0r), (_val)) 
   9370 #define WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0r(_unit, _pc, _val) \
   9371         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0r), (_val))
   9372 #define MODIFY_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0r(_unit, _pc, _val, _mask) \
   9373         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0r), (_val), (_mask))
   9374 
   9375 #define READ_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1r(_unit, _pc, _val) \
   9376         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1r), (_val)) 
   9377 #define WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1r(_unit, _pc, _val) \
   9378         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1r), (_val))
   9379 #define MODIFY_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1r(_unit, _pc, _val, _mask) \
   9380         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1r), (_val), (_mask))
   9381 
   9382 #define READ_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2r(_unit, _pc, _val) \
   9383         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2r), (_val)) 
   9384 #define WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2r(_unit, _pc, _val) \
   9385         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2r), (_val))
   9386 #define MODIFY_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2r(_unit, _pc, _val, _mask) \
   9387         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2r), (_val), (_mask))
   9388 
   9389 #define READ_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3r(_unit, _pc, _val) \
   9390         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3r), (_val)) 
   9391 #define WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3r(_unit, _pc, _val) \
   9392         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3r), (_val))
   9393 #define MODIFY_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3r(_unit, _pc, _val, _mask) \
   9394         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3r), (_val), (_mask))
   9395 
   9396 #define READ_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4r(_unit, _pc, _val) \
   9397         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4r), (_val)) 
   9398 #define WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4r(_unit, _pc, _val) \
   9399         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4r), (_val))
   9400 #define MODIFY_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4r(_unit, _pc, _val, _mask) \
   9401         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4r), (_val), (_mask))
   9402 
   9403 #define READ_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5r(_unit, _pc, _val) \
   9404         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5r), (_val)) 
   9405 #define WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5r(_unit, _pc, _val) \
   9406         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5r), (_val))
   9407 #define MODIFY_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5r(_unit, _pc, _val, _mask) \
   9408         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5r), (_val), (_mask))
   9409 
   9410 #define READ_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6r(_unit, _pc, _val) \
   9411         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6r), (_val)) 
   9412 #define WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6r(_unit, _pc, _val) \
   9413         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6r), (_val))
   9414 #define MODIFY_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6r(_unit, _pc, _val, _mask) \
   9415         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6r), (_val), (_mask))
   9416 
   9417 #define READ_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7r(_unit, _pc, _val) \
   9418         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7r), (_val)) 
   9419 #define WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7r(_unit, _pc, _val) \
   9420         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7r), (_val))
   9421 #define MODIFY_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7r(_unit, _pc, _val, _mask) \
   9422         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7r), (_val), (_mask))
   9423 
   9424 #define READ_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DMr(_unit, _pc, _val) \
   9425         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DMr), (_val)) 
   9426 #define WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DMr(_unit, _pc, _val) \
   9427         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DMr), (_val))
   9428 #define MODIFY_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DMr(_unit, _pc, _val, _mask) \
   9429         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DMr), (_val), (_mask))
   9430 
   9431 #define READ_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_EDCr(_unit, _pc, _val) \
   9432         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_EDCr), (_val)) 
   9433 #define WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_EDCr(_unit, _pc, _val) \
   9434         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_EDCr), (_val))
   9435 #define MODIFY_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_EDCr(_unit, _pc, _val, _mask) \
   9436         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_EDCr), (_val), (_mask))
   9437 
   9438 #define READ_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSPr(_unit, _pc, _val) \
   9439         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSPr), (_val)) 
   9440 #define WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSPr(_unit, _pc, _val) \
   9441         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSPr), (_val))
   9442 #define MODIFY_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSPr(_unit, _pc, _val, _mask) \
   9443         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSPr), (_val), (_mask))
   9444 
   9445 #define READ_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSNr(_unit, _pc, _val) \
   9446         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSNr), (_val)) 
   9447 #define WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSNr(_unit, _pc, _val) \
   9448         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSNr), (_val))
   9449 #define MODIFY_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSNr(_unit, _pc, _val, _mask) \
   9450         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSNr), (_val), (_mask))
   9451 
   9452 #define READ_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0Pr(_unit, _pc, _val) \
   9453         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0Pr), (_val)) 
   9454 #define WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0Pr(_unit, _pc, _val) \
   9455         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0Pr), (_val))
   9456 #define MODIFY_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0Pr(_unit, _pc, _val, _mask) \
   9457         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0Pr), (_val), (_mask))
   9458 
   9459 #define READ_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0Nr(_unit, _pc, _val) \
   9460         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0Nr), (_val)) 
   9461 #define WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0Nr(_unit, _pc, _val) \
   9462         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0Nr), (_val))
   9463 #define MODIFY_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0Nr(_unit, _pc, _val, _mask) \
   9464         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0Nr), (_val), (_mask))
   9465 
   9466 #define READ_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1Pr(_unit, _pc, _val) \
   9467         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1Pr), (_val)) 
   9468 #define WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1Pr(_unit, _pc, _val) \
   9469         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1Pr), (_val))
   9470 #define MODIFY_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1Pr(_unit, _pc, _val, _mask) \
   9471         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1Pr), (_val), (_mask))
   9472 
   9473 #define READ_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1Nr(_unit, _pc, _val) \
   9474         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1Nr), (_val)) 
   9475 #define WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1Nr(_unit, _pc, _val) \
   9476         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1Nr), (_val))
   9477 #define MODIFY_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1Nr(_unit, _pc, _val, _mask) \
   9478         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1Nr), (_val), (_mask))
   9479 
   9480 #define READ_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2Pr(_unit, _pc, _val) \
   9481         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2Pr), (_val)) 
   9482 #define WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2Pr(_unit, _pc, _val) \
   9483         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2Pr), (_val))
   9484 #define MODIFY_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2Pr(_unit, _pc, _val, _mask) \
   9485         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2Pr), (_val), (_mask))
   9486 
   9487 #define READ_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2Nr(_unit, _pc, _val) \
   9488         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2Nr), (_val)) 
   9489 #define WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2Nr(_unit, _pc, _val) \
   9490         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2Nr), (_val))
   9491 #define MODIFY_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2Nr(_unit, _pc, _val, _mask) \
   9492         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2Nr), (_val), (_mask))
   9493 
   9494 #define READ_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3Pr(_unit, _pc, _val) \
   9495         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3Pr), (_val)) 
   9496 #define WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3Pr(_unit, _pc, _val) \
   9497         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3Pr), (_val))
   9498 #define MODIFY_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3Pr(_unit, _pc, _val, _mask) \
   9499         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3Pr), (_val), (_mask))
   9500 
   9501 #define READ_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3Nr(_unit, _pc, _val) \
   9502         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3Nr), (_val)) 
   9503 #define WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3Nr(_unit, _pc, _val) \
   9504         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3Nr), (_val))
   9505 #define MODIFY_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3Nr(_unit, _pc, _val, _mask) \
   9506         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3Nr), (_val), (_mask))
   9507 
   9508 #define READ_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4Pr(_unit, _pc, _val) \
   9509         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4Pr), (_val)) 
   9510 #define WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4Pr(_unit, _pc, _val) \
   9511         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4Pr), (_val))
   9512 #define MODIFY_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4Pr(_unit, _pc, _val, _mask) \
   9513         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4Pr), (_val), (_mask))
   9514 
   9515 #define READ_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4Nr(_unit, _pc, _val) \
   9516         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4Nr), (_val)) 
   9517 #define WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4Nr(_unit, _pc, _val) \
   9518         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4Nr), (_val))
   9519 #define MODIFY_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4Nr(_unit, _pc, _val, _mask) \
   9520         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4Nr), (_val), (_mask))
   9521 
   9522 #define READ_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5Pr(_unit, _pc, _val) \
   9523         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5Pr), (_val)) 
   9524 #define WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5Pr(_unit, _pc, _val) \
   9525         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5Pr), (_val))
   9526 #define MODIFY_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5Pr(_unit, _pc, _val, _mask) \
   9527         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5Pr), (_val), (_mask))
   9528 
   9529 #define READ_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5Nr(_unit, _pc, _val) \
   9530         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5Nr), (_val)) 
   9531 #define WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5Nr(_unit, _pc, _val) \
   9532         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5Nr), (_val))
   9533 #define MODIFY_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5Nr(_unit, _pc, _val, _mask) \
   9534         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5Nr), (_val), (_mask))
   9535 
   9536 #define READ_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6Pr(_unit, _pc, _val) \
   9537         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6Pr), (_val)) 
   9538 #define WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6Pr(_unit, _pc, _val) \
   9539         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6Pr), (_val))
   9540 #define MODIFY_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6Pr(_unit, _pc, _val, _mask) \
   9541         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6Pr), (_val), (_mask))
   9542 
   9543 #define READ_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6Nr(_unit, _pc, _val) \
   9544         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6Nr), (_val)) 
   9545 #define WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6Nr(_unit, _pc, _val) \
   9546         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6Nr), (_val))
   9547 #define MODIFY_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6Nr(_unit, _pc, _val, _mask) \
   9548         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6Nr), (_val), (_mask))
   9549 
   9550 #define READ_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7Pr(_unit, _pc, _val) \
   9551         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7Pr), (_val)) 
   9552 #define WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7Pr(_unit, _pc, _val) \
   9553         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7Pr), (_val))
   9554 #define MODIFY_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7Pr(_unit, _pc, _val, _mask) \
   9555         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7Pr), (_val), (_mask))
   9556 
   9557 #define READ_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7Nr(_unit, _pc, _val) \
   9558         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7Nr), (_val)) 
   9559 #define WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7Nr(_unit, _pc, _val) \
   9560         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7Nr), (_val))
   9561 #define MODIFY_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7Nr(_unit, _pc, _val, _mask) \
   9562         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7Nr), (_val), (_mask))
   9563 
   9564 #define READ_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMPr(_unit, _pc, _val) \
   9565         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMPr), (_val)) 
   9566 #define WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMPr(_unit, _pc, _val) \
   9567         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMPr), (_val))
   9568 #define MODIFY_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMPr(_unit, _pc, _val, _mask) \
   9569         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMPr), (_val), (_mask))
   9570 
   9571 #define READ_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMNr(_unit, _pc, _val) \
   9572         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMNr), (_val)) 
   9573 #define WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMNr(_unit, _pc, _val) \
   9574         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMNr), (_val))
   9575 #define MODIFY_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMNr(_unit, _pc, _val, _mask) \
   9576         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMNr), (_val), (_mask))
   9577 
   9578 #define READ_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCPr(_unit, _pc, _val) \
   9579         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCPr), (_val)) 
   9580 #define WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCPr(_unit, _pc, _val) \
   9581         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCPr), (_val))
   9582 #define MODIFY_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCPr(_unit, _pc, _val, _mask) \
   9583         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCPr), (_val), (_mask))
   9584 
   9585 #define READ_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCNr(_unit, _pc, _val) \
   9586         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCNr), (_val)) 
   9587 #define WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCNr(_unit, _pc, _val) \
   9588         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCNr), (_val))
   9589 #define MODIFY_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCNr(_unit, _pc, _val, _mask) \
   9590         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCNr), (_val), (_mask))
   9591 
   9592 #define READ_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0r(_unit, _pc, _val) \
   9593         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0r), (_val)) 
   9594 #define WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0r(_unit, _pc, _val) \
   9595         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0r), (_val))
   9596 #define MODIFY_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0r(_unit, _pc, _val, _mask) \
   9597         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0r), (_val), (_mask))
   9598 
   9599 #define READ_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1r(_unit, _pc, _val) \
   9600         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1r), (_val)) 
   9601 #define WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1r(_unit, _pc, _val) \
   9602         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1r), (_val))
   9603 #define MODIFY_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1r(_unit, _pc, _val, _mask) \
   9604         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1r), (_val), (_mask))
   9605 
   9606 #define READ_DDR34_PHY_BYTE_LANE_0_VDL_CLK_CONTROLr(_unit, _pc, _val) \
   9607         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CLK_CONTROLr), (_val)) 
   9608 #define WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CLK_CONTROLr(_unit, _pc, _val) \
   9609         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CLK_CONTROLr), (_val))
   9610 #define MODIFY_DDR34_PHY_BYTE_LANE_0_VDL_CLK_CONTROLr(_unit, _pc, _val, _mask) \
   9611         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CLK_CONTROLr), (_val), (_mask))
   9612 
   9613 #define READ_DDR34_PHY_BYTE_LANE_0_VDL_LDE_CONTROLr(_unit, _pc, _val) \
   9614         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_LDE_CONTROLr), (_val)) 
   9615 #define WRITE_DDR34_PHY_BYTE_LANE_0_VDL_LDE_CONTROLr(_unit, _pc, _val) \
   9616         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_LDE_CONTROLr), (_val))
   9617 #define MODIFY_DDR34_PHY_BYTE_LANE_0_VDL_LDE_CONTROLr(_unit, _pc, _val, _mask) \
   9618         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_LDE_CONTROLr), (_val), (_mask))
   9619 
   9620 #define READ_DDR34_PHY_BYTE_LANE_0_RD_EN_DLY_CYCr(_unit, _pc, _val) \
   9621         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_RD_EN_DLY_CYCr), (_val)) 
   9622 #define WRITE_DDR34_PHY_BYTE_LANE_0_RD_EN_DLY_CYCr(_unit, _pc, _val) \
   9623         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_RD_EN_DLY_CYCr), (_val))
   9624 #define MODIFY_DDR34_PHY_BYTE_LANE_0_RD_EN_DLY_CYCr(_unit, _pc, _val, _mask) \
   9625         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_RD_EN_DLY_CYCr), (_val), (_mask))
   9626 
   9627 #define READ_DDR34_PHY_BYTE_LANE_0_WR_CHAN_DLY_CYCr(_unit, _pc, _val) \
   9628         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_WR_CHAN_DLY_CYCr), (_val)) 
   9629 #define WRITE_DDR34_PHY_BYTE_LANE_0_WR_CHAN_DLY_CYCr(_unit, _pc, _val) \
   9630         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_WR_CHAN_DLY_CYCr), (_val))
   9631 #define MODIFY_DDR34_PHY_BYTE_LANE_0_WR_CHAN_DLY_CYCr(_unit, _pc, _val, _mask) \
   9632         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_WR_CHAN_DLY_CYCr), (_val), (_mask))
   9633 
   9634 #define READ_DDR34_PHY_BYTE_LANE_0_READ_CONTROLr(_unit, _pc, _val) \
   9635         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_READ_CONTROLr), (_val)) 
   9636 #define WRITE_DDR34_PHY_BYTE_LANE_0_READ_CONTROLr(_unit, _pc, _val) \
   9637         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_READ_CONTROLr), (_val))
   9638 #define MODIFY_DDR34_PHY_BYTE_LANE_0_READ_CONTROLr(_unit, _pc, _val, _mask) \
   9639         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_READ_CONTROLr), (_val), (_mask))
   9640 
   9641 #define READ_DDR34_PHY_BYTE_LANE_0_READ_FIFO_ADDRr(_unit, _pc, _val) \
   9642         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_READ_FIFO_ADDRr), (_val)) 
   9643 #define WRITE_DDR34_PHY_BYTE_LANE_0_READ_FIFO_ADDRr(_unit, _pc, _val) \
   9644         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_READ_FIFO_ADDRr), (_val))
   9645 #define MODIFY_DDR34_PHY_BYTE_LANE_0_READ_FIFO_ADDRr(_unit, _pc, _val, _mask) \
   9646         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_READ_FIFO_ADDRr), (_val), (_mask))
   9647 
   9648 #define READ_DDR34_PHY_BYTE_LANE_0_READ_FIFO_DATAr(_unit, _pc, _val) \
   9649         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_READ_FIFO_DATAr), (_val)) 
   9650 #define WRITE_DDR34_PHY_BYTE_LANE_0_READ_FIFO_DATAr(_unit, _pc, _val) \
   9651         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_READ_FIFO_DATAr), (_val))
   9652 #define MODIFY_DDR34_PHY_BYTE_LANE_0_READ_FIFO_DATAr(_unit, _pc, _val, _mask) \
   9653         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_READ_FIFO_DATAr), (_val), (_mask))
   9654 
   9655 #define READ_DDR34_PHY_BYTE_LANE_0_READ_FIFO_DM_DBIr(_unit, _pc, _val) \
   9656         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_READ_FIFO_DM_DBIr), (_val)) 
   9657 #define WRITE_DDR34_PHY_BYTE_LANE_0_READ_FIFO_DM_DBIr(_unit, _pc, _val) \
   9658         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_READ_FIFO_DM_DBIr), (_val))
   9659 #define MODIFY_DDR34_PHY_BYTE_LANE_0_READ_FIFO_DM_DBIr(_unit, _pc, _val, _mask) \
   9660         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_READ_FIFO_DM_DBIr), (_val), (_mask))
   9661 
   9662 #define READ_DDR34_PHY_BYTE_LANE_0_READ_FIFO_STATUSr(_unit, _pc, _val) \
   9663         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_READ_FIFO_STATUSr), (_val)) 
   9664 #define WRITE_DDR34_PHY_BYTE_LANE_0_READ_FIFO_STATUSr(_unit, _pc, _val) \
   9665         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_READ_FIFO_STATUSr), (_val))
   9666 #define MODIFY_DDR34_PHY_BYTE_LANE_0_READ_FIFO_STATUSr(_unit, _pc, _val, _mask) \
   9667         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_READ_FIFO_STATUSr), (_val), (_mask))
   9668 
   9669 #define READ_DDR34_PHY_BYTE_LANE_0_READ_FIFO_CLEARr(_unit, _pc, _val) \
   9670         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_READ_FIFO_CLEARr), (_val)) 
   9671 #define WRITE_DDR34_PHY_BYTE_LANE_0_READ_FIFO_CLEARr(_unit, _pc, _val) \
   9672         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_READ_FIFO_CLEARr), (_val))
   9673 #define MODIFY_DDR34_PHY_BYTE_LANE_0_READ_FIFO_CLEARr(_unit, _pc, _val, _mask) \
   9674         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_READ_FIFO_CLEARr), (_val), (_mask))
   9675 
   9676 #define READ_DDR34_PHY_BYTE_LANE_0_IDLE_PAD_CONTROLr(_unit, _pc, _val) \
   9677         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_IDLE_PAD_CONTROLr), (_val)) 
   9678 #define WRITE_DDR34_PHY_BYTE_LANE_0_IDLE_PAD_CONTROLr(_unit, _pc, _val) \
   9679         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_IDLE_PAD_CONTROLr), (_val))
   9680 #define MODIFY_DDR34_PHY_BYTE_LANE_0_IDLE_PAD_CONTROLr(_unit, _pc, _val, _mask) \
   9681         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_IDLE_PAD_CONTROLr), (_val), (_mask))
   9682 
   9683 #define READ_DDR34_PHY_BYTE_LANE_0_DRIVE_PAD_CTLr(_unit, _pc, _val) \
   9684         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_DRIVE_PAD_CTLr), (_val)) 
   9685 #define WRITE_DDR34_PHY_BYTE_LANE_0_DRIVE_PAD_CTLr(_unit, _pc, _val) \
   9686         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_DRIVE_PAD_CTLr), (_val))
   9687 #define MODIFY_DDR34_PHY_BYTE_LANE_0_DRIVE_PAD_CTLr(_unit, _pc, _val, _mask) \
   9688         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_DRIVE_PAD_CTLr), (_val), (_mask))
   9689 
   9690 #define READ_DDR34_PHY_BYTE_LANE_0_RD_EN_DRIVE_PAD_CTLr(_unit, _pc, _val) \
   9691         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_RD_EN_DRIVE_PAD_CTLr), (_val)) 
   9692 #define WRITE_DDR34_PHY_BYTE_LANE_0_RD_EN_DRIVE_PAD_CTLr(_unit, _pc, _val) \
   9693         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_RD_EN_DRIVE_PAD_CTLr), (_val))
   9694 #define MODIFY_DDR34_PHY_BYTE_LANE_0_RD_EN_DRIVE_PAD_CTLr(_unit, _pc, _val, _mask) \
   9695         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_RD_EN_DRIVE_PAD_CTLr), (_val), (_mask))
   9696 
   9697 #define READ_DDR34_PHY_BYTE_LANE_0_STATIC_PAD_CTLr(_unit, _pc, _val) \
   9698         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_STATIC_PAD_CTLr), (_val)) 
   9699 #define WRITE_DDR34_PHY_BYTE_LANE_0_STATIC_PAD_CTLr(_unit, _pc, _val) \
   9700         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_STATIC_PAD_CTLr), (_val))
   9701 #define MODIFY_DDR34_PHY_BYTE_LANE_0_STATIC_PAD_CTLr(_unit, _pc, _val, _mask) \
   9702         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_STATIC_PAD_CTLr), (_val), (_mask))
   9703 
   9704 #define READ_DDR34_PHY_BYTE_LANE_0_WR_PREAMBLE_MODEr(_unit, _pc, _val) \
   9705         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_WR_PREAMBLE_MODEr), (_val)) 
   9706 #define WRITE_DDR34_PHY_BYTE_LANE_0_WR_PREAMBLE_MODEr(_unit, _pc, _val) \
   9707         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_WR_PREAMBLE_MODEr), (_val))
   9708 #define MODIFY_DDR34_PHY_BYTE_LANE_0_WR_PREAMBLE_MODEr(_unit, _pc, _val, _mask) \
   9709         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_WR_PREAMBLE_MODEr), (_val), (_mask))
   9710 
   9711 #define READ_DDR34_PHY_BYTE_LANE_0_ODT_CONTROLr(_unit, _pc, _val) \
   9712         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_ODT_CONTROLr), (_val)) 
   9713 #define WRITE_DDR34_PHY_BYTE_LANE_0_ODT_CONTROLr(_unit, _pc, _val) \
   9714         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_ODT_CONTROLr), (_val))
   9715 #define MODIFY_DDR34_PHY_BYTE_LANE_0_ODT_CONTROLr(_unit, _pc, _val, _mask) \
   9716         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_ODT_CONTROLr), (_val), (_mask))
   9717 
   9718 #define READ_DDR34_PHY_BYTE_LANE_0_EDC_DPD_CONTROLr(_unit, _pc, _val) \
   9719         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_EDC_DPD_CONTROLr), (_val)) 
   9720 #define WRITE_DDR34_PHY_BYTE_LANE_0_EDC_DPD_CONTROLr(_unit, _pc, _val) \
   9721         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_EDC_DPD_CONTROLr), (_val))
   9722 #define MODIFY_DDR34_PHY_BYTE_LANE_0_EDC_DPD_CONTROLr(_unit, _pc, _val, _mask) \
   9723         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_EDC_DPD_CONTROLr), (_val), (_mask))
   9724 
   9725 #define READ_DDR34_PHY_BYTE_LANE_0_EDC_DPD_STATUSr(_unit, _pc, _val) \
   9726         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_EDC_DPD_STATUSr), (_val)) 
   9727 #define WRITE_DDR34_PHY_BYTE_LANE_0_EDC_DPD_STATUSr(_unit, _pc, _val) \
   9728         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_EDC_DPD_STATUSr), (_val))
   9729 #define MODIFY_DDR34_PHY_BYTE_LANE_0_EDC_DPD_STATUSr(_unit, _pc, _val, _mask) \
   9730         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_EDC_DPD_STATUSr), (_val), (_mask))
   9731 
   9732 #define READ_DDR34_PHY_BYTE_LANE_0_EDC_DPD_OUT_CONTROLr(_unit, _pc, _val) \
   9733         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_EDC_DPD_OUT_CONTROLr), (_val)) 
   9734 #define WRITE_DDR34_PHY_BYTE_LANE_0_EDC_DPD_OUT_CONTROLr(_unit, _pc, _val) \
   9735         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_EDC_DPD_OUT_CONTROLr), (_val))
   9736 #define MODIFY_DDR34_PHY_BYTE_LANE_0_EDC_DPD_OUT_CONTROLr(_unit, _pc, _val, _mask) \
   9737         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_EDC_DPD_OUT_CONTROLr), (_val), (_mask))
   9738 
   9739 #define READ_DDR34_PHY_BYTE_LANE_0_EDC_DPD_OUT_STATUSr(_unit, _pc, _val) \
   9740         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_EDC_DPD_OUT_STATUSr), (_val)) 
   9741 #define WRITE_DDR34_PHY_BYTE_LANE_0_EDC_DPD_OUT_STATUSr(_unit, _pc, _val) \
   9742         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_EDC_DPD_OUT_STATUSr), (_val))
   9743 #define MODIFY_DDR34_PHY_BYTE_LANE_0_EDC_DPD_OUT_STATUSr(_unit, _pc, _val, _mask) \
   9744         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_EDC_DPD_OUT_STATUSr), (_val), (_mask))
   9745 
   9746 #define READ_DDR34_PHY_BYTE_LANE_0_EDC_DPD_OUT_STATUS_CLEARr(_unit, _pc, _val) \
   9747         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_EDC_DPD_OUT_STATUS_CLEARr), (_val)) 
   9748 #define WRITE_DDR34_PHY_BYTE_LANE_0_EDC_DPD_OUT_STATUS_CLEARr(_unit, _pc, _val) \
   9749         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_EDC_DPD_OUT_STATUS_CLEARr), (_val))
   9750 #define MODIFY_DDR34_PHY_BYTE_LANE_0_EDC_DPD_OUT_STATUS_CLEARr(_unit, _pc, _val, _mask) \
   9751         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_EDC_DPD_OUT_STATUS_CLEARr), (_val), (_mask))
   9752 
   9753 #define READ_DDR34_PHY_BYTE_LANE_0_EDC_CRC_CONTROLr(_unit, _pc, _val) \
   9754         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_EDC_CRC_CONTROLr), (_val)) 
   9755 #define WRITE_DDR34_PHY_BYTE_LANE_0_EDC_CRC_CONTROLr(_unit, _pc, _val) \
   9756         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_EDC_CRC_CONTROLr), (_val))
   9757 #define MODIFY_DDR34_PHY_BYTE_LANE_0_EDC_CRC_CONTROLr(_unit, _pc, _val, _mask) \
   9758         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_EDC_CRC_CONTROLr), (_val), (_mask))
   9759 
   9760 #define READ_DDR34_PHY_BYTE_LANE_0_EDC_CRC_STATUSr(_unit, _pc, _val) \
   9761         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_EDC_CRC_STATUSr), (_val)) 
   9762 #define WRITE_DDR34_PHY_BYTE_LANE_0_EDC_CRC_STATUSr(_unit, _pc, _val) \
   9763         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_EDC_CRC_STATUSr), (_val))
   9764 #define MODIFY_DDR34_PHY_BYTE_LANE_0_EDC_CRC_STATUSr(_unit, _pc, _val, _mask) \
   9765         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_EDC_CRC_STATUSr), (_val), (_mask))
   9766 
   9767 #define READ_DDR34_PHY_BYTE_LANE_0_EDC_CRC_COUNTr(_unit, _pc, _val) \
   9768         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_EDC_CRC_COUNTr), (_val)) 
   9769 #define WRITE_DDR34_PHY_BYTE_LANE_0_EDC_CRC_COUNTr(_unit, _pc, _val) \
   9770         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_EDC_CRC_COUNTr), (_val))
   9771 #define MODIFY_DDR34_PHY_BYTE_LANE_0_EDC_CRC_COUNTr(_unit, _pc, _val, _mask) \
   9772         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_EDC_CRC_COUNTr), (_val), (_mask))
   9773 
   9774 #define READ_DDR34_PHY_BYTE_LANE_0_EDC_CRC_STATUS_CLEARr(_unit, _pc, _val) \
   9775         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_EDC_CRC_STATUS_CLEARr), (_val)) 
   9776 #define WRITE_DDR34_PHY_BYTE_LANE_0_EDC_CRC_STATUS_CLEARr(_unit, _pc, _val) \
   9777         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_EDC_CRC_STATUS_CLEARr), (_val))
   9778 #define MODIFY_DDR34_PHY_BYTE_LANE_0_EDC_CRC_STATUS_CLEARr(_unit, _pc, _val, _mask) \
   9779         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_EDC_CRC_STATUS_CLEARr), (_val), (_mask))
   9780 
   9781 #define READ_DDR34_PHY_BYTE_LANE_0_BL_SPARE_REGr(_unit, _pc, _val) \
   9782         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_BL_SPARE_REGr), (_val)) 
   9783 #define WRITE_DDR34_PHY_BYTE_LANE_0_BL_SPARE_REGr(_unit, _pc, _val) \
   9784         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_BL_SPARE_REGr), (_val))
   9785 #define MODIFY_DDR34_PHY_BYTE_LANE_0_BL_SPARE_REGr(_unit, _pc, _val, _mask) \
   9786         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_BL_SPARE_REGr), (_val), (_mask))
   9787 
   9788 
   9789 /***************************************************************************
   9790  *DDR34_E0_PHY_BYTE_LANE_1 - DDR34 CORE DDR34 Byte Lane #1 control registers
   9791  */
   9792 #define READ_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_Pr(_unit, _pc, _val) \
   9793         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_Pr), (_val)) 
   9794 #define WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_Pr(_unit, _pc, _val) \
   9795         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_Pr), (_val))
   9796 #define MODIFY_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_Pr(_unit, _pc, _val, _mask) \
   9797         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_Pr), (_val), (_mask))
   9798 
   9799 #define READ_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_Nr(_unit, _pc, _val) \
   9800         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_Nr), (_val)) 
   9801 #define WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_Nr(_unit, _pc, _val) \
   9802         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_Nr), (_val))
   9803 #define MODIFY_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_Nr(_unit, _pc, _val, _mask) \
   9804         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_Nr), (_val), (_mask))
   9805 
   9806 #define READ_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0r(_unit, _pc, _val) \
   9807         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0r), (_val)) 
   9808 #define WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0r(_unit, _pc, _val) \
   9809         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0r), (_val))
   9810 #define MODIFY_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0r(_unit, _pc, _val, _mask) \
   9811         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0r), (_val), (_mask))
   9812 
   9813 #define READ_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1r(_unit, _pc, _val) \
   9814         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1r), (_val)) 
   9815 #define WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1r(_unit, _pc, _val) \
   9816         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1r), (_val))
   9817 #define MODIFY_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1r(_unit, _pc, _val, _mask) \
   9818         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1r), (_val), (_mask))
   9819 
   9820 #define READ_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2r(_unit, _pc, _val) \
   9821         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2r), (_val)) 
   9822 #define WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2r(_unit, _pc, _val) \
   9823         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2r), (_val))
   9824 #define MODIFY_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2r(_unit, _pc, _val, _mask) \
   9825         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2r), (_val), (_mask))
   9826 
   9827 #define READ_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3r(_unit, _pc, _val) \
   9828         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3r), (_val)) 
   9829 #define WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3r(_unit, _pc, _val) \
   9830         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3r), (_val))
   9831 #define MODIFY_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3r(_unit, _pc, _val, _mask) \
   9832         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3r), (_val), (_mask))
   9833 
   9834 #define READ_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4r(_unit, _pc, _val) \
   9835         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4r), (_val)) 
   9836 #define WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4r(_unit, _pc, _val) \
   9837         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4r), (_val))
   9838 #define MODIFY_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4r(_unit, _pc, _val, _mask) \
   9839         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4r), (_val), (_mask))
   9840 
   9841 #define READ_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5r(_unit, _pc, _val) \
   9842         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5r), (_val)) 
   9843 #define WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5r(_unit, _pc, _val) \
   9844         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5r), (_val))
   9845 #define MODIFY_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5r(_unit, _pc, _val, _mask) \
   9846         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5r), (_val), (_mask))
   9847 
   9848 #define READ_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6r(_unit, _pc, _val) \
   9849         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6r), (_val)) 
   9850 #define WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6r(_unit, _pc, _val) \
   9851         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6r), (_val))
   9852 #define MODIFY_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6r(_unit, _pc, _val, _mask) \
   9853         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6r), (_val), (_mask))
   9854 
   9855 #define READ_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7r(_unit, _pc, _val) \
   9856         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7r), (_val)) 
   9857 #define WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7r(_unit, _pc, _val) \
   9858         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7r), (_val))
   9859 #define MODIFY_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7r(_unit, _pc, _val, _mask) \
   9860         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7r), (_val), (_mask))
   9861 
   9862 #define READ_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DMr(_unit, _pc, _val) \
   9863         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DMr), (_val)) 
   9864 #define WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DMr(_unit, _pc, _val) \
   9865         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DMr), (_val))
   9866 #define MODIFY_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DMr(_unit, _pc, _val, _mask) \
   9867         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DMr), (_val), (_mask))
   9868 
   9869 #define READ_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_EDCr(_unit, _pc, _val) \
   9870         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_EDCr), (_val)) 
   9871 #define WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_EDCr(_unit, _pc, _val) \
   9872         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_EDCr), (_val))
   9873 #define MODIFY_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_EDCr(_unit, _pc, _val, _mask) \
   9874         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_EDCr), (_val), (_mask))
   9875 
   9876 #define READ_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSPr(_unit, _pc, _val) \
   9877         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSPr), (_val)) 
   9878 #define WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSPr(_unit, _pc, _val) \
   9879         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSPr), (_val))
   9880 #define MODIFY_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSPr(_unit, _pc, _val, _mask) \
   9881         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSPr), (_val), (_mask))
   9882 
   9883 #define READ_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSNr(_unit, _pc, _val) \
   9884         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSNr), (_val)) 
   9885 #define WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSNr(_unit, _pc, _val) \
   9886         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSNr), (_val))
   9887 #define MODIFY_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSNr(_unit, _pc, _val, _mask) \
   9888         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSNr), (_val), (_mask))
   9889 
   9890 #define READ_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0Pr(_unit, _pc, _val) \
   9891         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0Pr), (_val)) 
   9892 #define WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0Pr(_unit, _pc, _val) \
   9893         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0Pr), (_val))
   9894 #define MODIFY_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0Pr(_unit, _pc, _val, _mask) \
   9895         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0Pr), (_val), (_mask))
   9896 
   9897 #define READ_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0Nr(_unit, _pc, _val) \
   9898         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0Nr), (_val)) 
   9899 #define WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0Nr(_unit, _pc, _val) \
   9900         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0Nr), (_val))
   9901 #define MODIFY_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0Nr(_unit, _pc, _val, _mask) \
   9902         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0Nr), (_val), (_mask))
   9903 
   9904 #define READ_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1Pr(_unit, _pc, _val) \
   9905         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1Pr), (_val)) 
   9906 #define WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1Pr(_unit, _pc, _val) \
   9907         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1Pr), (_val))
   9908 #define MODIFY_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1Pr(_unit, _pc, _val, _mask) \
   9909         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1Pr), (_val), (_mask))
   9910 
   9911 #define READ_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1Nr(_unit, _pc, _val) \
   9912         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1Nr), (_val)) 
   9913 #define WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1Nr(_unit, _pc, _val) \
   9914         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1Nr), (_val))
   9915 #define MODIFY_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1Nr(_unit, _pc, _val, _mask) \
   9916         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1Nr), (_val), (_mask))
   9917 
   9918 #define READ_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2Pr(_unit, _pc, _val) \
   9919         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2Pr), (_val)) 
   9920 #define WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2Pr(_unit, _pc, _val) \
   9921         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2Pr), (_val))
   9922 #define MODIFY_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2Pr(_unit, _pc, _val, _mask) \
   9923         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2Pr), (_val), (_mask))
   9924 
   9925 #define READ_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2Nr(_unit, _pc, _val) \
   9926         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2Nr), (_val)) 
   9927 #define WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2Nr(_unit, _pc, _val) \
   9928         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2Nr), (_val))
   9929 #define MODIFY_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2Nr(_unit, _pc, _val, _mask) \
   9930         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2Nr), (_val), (_mask))
   9931 
   9932 #define READ_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3Pr(_unit, _pc, _val) \
   9933         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3Pr), (_val)) 
   9934 #define WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3Pr(_unit, _pc, _val) \
   9935         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3Pr), (_val))
   9936 #define MODIFY_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3Pr(_unit, _pc, _val, _mask) \
   9937         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3Pr), (_val), (_mask))
   9938 
   9939 #define READ_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3Nr(_unit, _pc, _val) \
   9940         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3Nr), (_val)) 
   9941 #define WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3Nr(_unit, _pc, _val) \
   9942         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3Nr), (_val))
   9943 #define MODIFY_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3Nr(_unit, _pc, _val, _mask) \
   9944         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3Nr), (_val), (_mask))
   9945 
   9946 #define READ_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4Pr(_unit, _pc, _val) \
   9947         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4Pr), (_val)) 
   9948 #define WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4Pr(_unit, _pc, _val) \
   9949         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4Pr), (_val))
   9950 #define MODIFY_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4Pr(_unit, _pc, _val, _mask) \
   9951         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4Pr), (_val), (_mask))
   9952 
   9953 #define READ_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4Nr(_unit, _pc, _val) \
   9954         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4Nr), (_val)) 
   9955 #define WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4Nr(_unit, _pc, _val) \
   9956         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4Nr), (_val))
   9957 #define MODIFY_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4Nr(_unit, _pc, _val, _mask) \
   9958         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4Nr), (_val), (_mask))
   9959 
   9960 #define READ_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5Pr(_unit, _pc, _val) \
   9961         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5Pr), (_val)) 
   9962 #define WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5Pr(_unit, _pc, _val) \
   9963         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5Pr), (_val))
   9964 #define MODIFY_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5Pr(_unit, _pc, _val, _mask) \
   9965         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5Pr), (_val), (_mask))
   9966 
   9967 #define READ_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5Nr(_unit, _pc, _val) \
   9968         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5Nr), (_val)) 
   9969 #define WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5Nr(_unit, _pc, _val) \
   9970         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5Nr), (_val))
   9971 #define MODIFY_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5Nr(_unit, _pc, _val, _mask) \
   9972         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5Nr), (_val), (_mask))
   9973 
   9974 #define READ_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6Pr(_unit, _pc, _val) \
   9975         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6Pr), (_val)) 
   9976 #define WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6Pr(_unit, _pc, _val) \
   9977         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6Pr), (_val))
   9978 #define MODIFY_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6Pr(_unit, _pc, _val, _mask) \
   9979         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6Pr), (_val), (_mask))
   9980 
   9981 #define READ_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6Nr(_unit, _pc, _val) \
   9982         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6Nr), (_val)) 
   9983 #define WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6Nr(_unit, _pc, _val) \
   9984         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6Nr), (_val))
   9985 #define MODIFY_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6Nr(_unit, _pc, _val, _mask) \
   9986         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6Nr), (_val), (_mask))
   9987 
   9988 #define READ_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7Pr(_unit, _pc, _val) \
   9989         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7Pr), (_val)) 
   9990 #define WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7Pr(_unit, _pc, _val) \
   9991         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7Pr), (_val))
   9992 #define MODIFY_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7Pr(_unit, _pc, _val, _mask) \
   9993         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7Pr), (_val), (_mask))
   9994 
   9995 #define READ_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7Nr(_unit, _pc, _val) \
   9996         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7Nr), (_val)) 
   9997 #define WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7Nr(_unit, _pc, _val) \
   9998         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7Nr), (_val))
   9999 #define MODIFY_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7Nr(_unit, _pc, _val, _mask) \
  10000         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7Nr), (_val), (_mask))
  10001 
  10002 #define READ_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMPr(_unit, _pc, _val) \
  10003         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMPr), (_val)) 
  10004 #define WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMPr(_unit, _pc, _val) \
  10005         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMPr), (_val))
  10006 #define MODIFY_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMPr(_unit, _pc, _val, _mask) \
  10007         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMPr), (_val), (_mask))
  10008 
  10009 #define READ_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMNr(_unit, _pc, _val) \
  10010         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMNr), (_val)) 
  10011 #define WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMNr(_unit, _pc, _val) \
  10012         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMNr), (_val))
  10013 #define MODIFY_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMNr(_unit, _pc, _val, _mask) \
  10014         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMNr), (_val), (_mask))
  10015 
  10016 #define READ_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCPr(_unit, _pc, _val) \
  10017         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCPr), (_val)) 
  10018 #define WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCPr(_unit, _pc, _val) \
  10019         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCPr), (_val))
  10020 #define MODIFY_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCPr(_unit, _pc, _val, _mask) \
  10021         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCPr), (_val), (_mask))
  10022 
  10023 #define READ_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCNr(_unit, _pc, _val) \
  10024         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCNr), (_val)) 
  10025 #define WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCNr(_unit, _pc, _val) \
  10026         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCNr), (_val))
  10027 #define MODIFY_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCNr(_unit, _pc, _val, _mask) \
  10028         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCNr), (_val), (_mask))
  10029 
  10030 #define READ_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0r(_unit, _pc, _val) \
  10031         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0r), (_val)) 
  10032 #define WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0r(_unit, _pc, _val) \
  10033         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0r), (_val))
  10034 #define MODIFY_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0r(_unit, _pc, _val, _mask) \
  10035         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0r), (_val), (_mask))
  10036 
  10037 #define READ_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1r(_unit, _pc, _val) \
  10038         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1r), (_val)) 
  10039 #define WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1r(_unit, _pc, _val) \
  10040         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1r), (_val))
  10041 #define MODIFY_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1r(_unit, _pc, _val, _mask) \
  10042         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1r), (_val), (_mask))
  10043 
  10044 #define READ_DDR34_PHY_BYTE_LANE_1_VDL_CLK_CONTROLr(_unit, _pc, _val) \
  10045         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CLK_CONTROLr), (_val)) 
  10046 #define WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CLK_CONTROLr(_unit, _pc, _val) \
  10047         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CLK_CONTROLr), (_val))
  10048 #define MODIFY_DDR34_PHY_BYTE_LANE_1_VDL_CLK_CONTROLr(_unit, _pc, _val, _mask) \
  10049         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CLK_CONTROLr), (_val), (_mask))
  10050 
  10051 #define READ_DDR34_PHY_BYTE_LANE_1_VDL_LDE_CONTROLr(_unit, _pc, _val) \
  10052         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_LDE_CONTROLr), (_val)) 
  10053 #define WRITE_DDR34_PHY_BYTE_LANE_1_VDL_LDE_CONTROLr(_unit, _pc, _val) \
  10054         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_LDE_CONTROLr), (_val))
  10055 #define MODIFY_DDR34_PHY_BYTE_LANE_1_VDL_LDE_CONTROLr(_unit, _pc, _val, _mask) \
  10056         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_LDE_CONTROLr), (_val), (_mask))
  10057 
  10058 #define READ_DDR34_PHY_BYTE_LANE_1_RD_EN_DLY_CYCr(_unit, _pc, _val) \
  10059         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_RD_EN_DLY_CYCr), (_val)) 
  10060 #define WRITE_DDR34_PHY_BYTE_LANE_1_RD_EN_DLY_CYCr(_unit, _pc, _val) \
  10061         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_RD_EN_DLY_CYCr), (_val))
  10062 #define MODIFY_DDR34_PHY_BYTE_LANE_1_RD_EN_DLY_CYCr(_unit, _pc, _val, _mask) \
  10063         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_RD_EN_DLY_CYCr), (_val), (_mask))
  10064 
  10065 #define READ_DDR34_PHY_BYTE_LANE_1_WR_CHAN_DLY_CYCr(_unit, _pc, _val) \
  10066         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_WR_CHAN_DLY_CYCr), (_val)) 
  10067 #define WRITE_DDR34_PHY_BYTE_LANE_1_WR_CHAN_DLY_CYCr(_unit, _pc, _val) \
  10068         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_WR_CHAN_DLY_CYCr), (_val))
  10069 #define MODIFY_DDR34_PHY_BYTE_LANE_1_WR_CHAN_DLY_CYCr(_unit, _pc, _val, _mask) \
  10070         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_WR_CHAN_DLY_CYCr), (_val), (_mask))
  10071 
  10072 #define READ_DDR34_PHY_BYTE_LANE_1_READ_CONTROLr(_unit, _pc, _val) \
  10073         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_READ_CONTROLr), (_val)) 
  10074 #define WRITE_DDR34_PHY_BYTE_LANE_1_READ_CONTROLr(_unit, _pc, _val) \
  10075         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_READ_CONTROLr), (_val))
  10076 #define MODIFY_DDR34_PHY_BYTE_LANE_1_READ_CONTROLr(_unit, _pc, _val, _mask) \
  10077         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_READ_CONTROLr), (_val), (_mask))
  10078 
  10079 #define READ_DDR34_PHY_BYTE_LANE_1_READ_FIFO_ADDRr(_unit, _pc, _val) \
  10080         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_READ_FIFO_ADDRr), (_val)) 
  10081 #define WRITE_DDR34_PHY_BYTE_LANE_1_READ_FIFO_ADDRr(_unit, _pc, _val) \
  10082         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_READ_FIFO_ADDRr), (_val))
  10083 #define MODIFY_DDR34_PHY_BYTE_LANE_1_READ_FIFO_ADDRr(_unit, _pc, _val, _mask) \
  10084         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_READ_FIFO_ADDRr), (_val), (_mask))
  10085 
  10086 #define READ_DDR34_PHY_BYTE_LANE_1_READ_FIFO_DATAr(_unit, _pc, _val) \
  10087         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_READ_FIFO_DATAr), (_val)) 
  10088 #define WRITE_DDR34_PHY_BYTE_LANE_1_READ_FIFO_DATAr(_unit, _pc, _val) \
  10089         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_READ_FIFO_DATAr), (_val))
  10090 #define MODIFY_DDR34_PHY_BYTE_LANE_1_READ_FIFO_DATAr(_unit, _pc, _val, _mask) \
  10091         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_READ_FIFO_DATAr), (_val), (_mask))
  10092 
  10093 #define READ_DDR34_PHY_BYTE_LANE_1_READ_FIFO_DM_DBIr(_unit, _pc, _val) \
  10094         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_READ_FIFO_DM_DBIr), (_val)) 
  10095 #define WRITE_DDR34_PHY_BYTE_LANE_1_READ_FIFO_DM_DBIr(_unit, _pc, _val) \
  10096         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_READ_FIFO_DM_DBIr), (_val))
  10097 #define MODIFY_DDR34_PHY_BYTE_LANE_1_READ_FIFO_DM_DBIr(_unit, _pc, _val, _mask) \
  10098         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_READ_FIFO_DM_DBIr), (_val), (_mask))
  10099 
  10100 #define READ_DDR34_PHY_BYTE_LANE_1_READ_FIFO_STATUSr(_unit, _pc, _val) \
  10101         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_READ_FIFO_STATUSr), (_val)) 
  10102 #define WRITE_DDR34_PHY_BYTE_LANE_1_READ_FIFO_STATUSr(_unit, _pc, _val) \
  10103         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_READ_FIFO_STATUSr), (_val))
  10104 #define MODIFY_DDR34_PHY_BYTE_LANE_1_READ_FIFO_STATUSr(_unit, _pc, _val, _mask) \
  10105         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_READ_FIFO_STATUSr), (_val), (_mask))
  10106 
  10107 #define READ_DDR34_PHY_BYTE_LANE_1_READ_FIFO_CLEARr(_unit, _pc, _val) \
  10108         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_READ_FIFO_CLEARr), (_val)) 
  10109 #define WRITE_DDR34_PHY_BYTE_LANE_1_READ_FIFO_CLEARr(_unit, _pc, _val) \
  10110         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_READ_FIFO_CLEARr), (_val))
  10111 #define MODIFY_DDR34_PHY_BYTE_LANE_1_READ_FIFO_CLEARr(_unit, _pc, _val, _mask) \
  10112         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_READ_FIFO_CLEARr), (_val), (_mask))
  10113 
  10114 #define READ_DDR34_PHY_BYTE_LANE_1_IDLE_PAD_CONTROLr(_unit, _pc, _val) \
  10115         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_IDLE_PAD_CONTROLr), (_val)) 
  10116 #define WRITE_DDR34_PHY_BYTE_LANE_1_IDLE_PAD_CONTROLr(_unit, _pc, _val) \
  10117         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_IDLE_PAD_CONTROLr), (_val))
  10118 #define MODIFY_DDR34_PHY_BYTE_LANE_1_IDLE_PAD_CONTROLr(_unit, _pc, _val, _mask) \
  10119         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_IDLE_PAD_CONTROLr), (_val), (_mask))
  10120 
  10121 #define READ_DDR34_PHY_BYTE_LANE_1_DRIVE_PAD_CTLr(_unit, _pc, _val) \
  10122         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_DRIVE_PAD_CTLr), (_val)) 
  10123 #define WRITE_DDR34_PHY_BYTE_LANE_1_DRIVE_PAD_CTLr(_unit, _pc, _val) \
  10124         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_DRIVE_PAD_CTLr), (_val))
  10125 #define MODIFY_DDR34_PHY_BYTE_LANE_1_DRIVE_PAD_CTLr(_unit, _pc, _val, _mask) \
  10126         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_DRIVE_PAD_CTLr), (_val), (_mask))
  10127 
  10128 #define READ_DDR34_PHY_BYTE_LANE_1_RD_EN_DRIVE_PAD_CTLr(_unit, _pc, _val) \
  10129         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_RD_EN_DRIVE_PAD_CTLr), (_val)) 
  10130 #define WRITE_DDR34_PHY_BYTE_LANE_1_RD_EN_DRIVE_PAD_CTLr(_unit, _pc, _val) \
  10131         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_RD_EN_DRIVE_PAD_CTLr), (_val))
  10132 #define MODIFY_DDR34_PHY_BYTE_LANE_1_RD_EN_DRIVE_PAD_CTLr(_unit, _pc, _val, _mask) \
  10133         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_RD_EN_DRIVE_PAD_CTLr), (_val), (_mask))
  10134 
  10135 #define READ_DDR34_PHY_BYTE_LANE_1_STATIC_PAD_CTLr(_unit, _pc, _val) \
  10136         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_STATIC_PAD_CTLr), (_val)) 
  10137 #define WRITE_DDR34_PHY_BYTE_LANE_1_STATIC_PAD_CTLr(_unit, _pc, _val) \
  10138         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_STATIC_PAD_CTLr), (_val))
  10139 #define MODIFY_DDR34_PHY_BYTE_LANE_1_STATIC_PAD_CTLr(_unit, _pc, _val, _mask) \
  10140         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_STATIC_PAD_CTLr), (_val), (_mask))
  10141 
  10142 #define READ_DDR34_PHY_BYTE_LANE_1_WR_PREAMBLE_MODEr(_unit, _pc, _val) \
  10143         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_WR_PREAMBLE_MODEr), (_val)) 
  10144 #define WRITE_DDR34_PHY_BYTE_LANE_1_WR_PREAMBLE_MODEr(_unit, _pc, _val) \
  10145         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_WR_PREAMBLE_MODEr), (_val))
  10146 #define MODIFY_DDR34_PHY_BYTE_LANE_1_WR_PREAMBLE_MODEr(_unit, _pc, _val, _mask) \
  10147         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_WR_PREAMBLE_MODEr), (_val), (_mask))
  10148 
  10149 #define READ_DDR34_PHY_BYTE_LANE_1_ODT_CONTROLr(_unit, _pc, _val) \
  10150         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_ODT_CONTROLr), (_val)) 
  10151 #define WRITE_DDR34_PHY_BYTE_LANE_1_ODT_CONTROLr(_unit, _pc, _val) \
  10152         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_ODT_CONTROLr), (_val))
  10153 #define MODIFY_DDR34_PHY_BYTE_LANE_1_ODT_CONTROLr(_unit, _pc, _val, _mask) \
  10154         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_ODT_CONTROLr), (_val), (_mask))
  10155 
  10156 #define READ_DDR34_PHY_BYTE_LANE_1_EDC_DPD_CONTROLr(_unit, _pc, _val) \
  10157         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_EDC_DPD_CONTROLr), (_val)) 
  10158 #define WRITE_DDR34_PHY_BYTE_LANE_1_EDC_DPD_CONTROLr(_unit, _pc, _val) \
  10159         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_EDC_DPD_CONTROLr), (_val))
  10160 #define MODIFY_DDR34_PHY_BYTE_LANE_1_EDC_DPD_CONTROLr(_unit, _pc, _val, _mask) \
  10161         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_EDC_DPD_CONTROLr), (_val), (_mask))
  10162 
  10163 #define READ_DDR34_PHY_BYTE_LANE_1_EDC_DPD_STATUSr(_unit, _pc, _val) \
  10164         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_EDC_DPD_STATUSr), (_val)) 
  10165 #define WRITE_DDR34_PHY_BYTE_LANE_1_EDC_DPD_STATUSr(_unit, _pc, _val) \
  10166         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_EDC_DPD_STATUSr), (_val))
  10167 #define MODIFY_DDR34_PHY_BYTE_LANE_1_EDC_DPD_STATUSr(_unit, _pc, _val, _mask) \
  10168         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_EDC_DPD_STATUSr), (_val), (_mask))
  10169 
  10170 #define READ_DDR34_PHY_BYTE_LANE_1_EDC_DPD_OUT_CONTROLr(_unit, _pc, _val) \
  10171         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_EDC_DPD_OUT_CONTROLr), (_val)) 
  10172 #define WRITE_DDR34_PHY_BYTE_LANE_1_EDC_DPD_OUT_CONTROLr(_unit, _pc, _val) \
  10173         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_EDC_DPD_OUT_CONTROLr), (_val))
  10174 #define MODIFY_DDR34_PHY_BYTE_LANE_1_EDC_DPD_OUT_CONTROLr(_unit, _pc, _val, _mask) \
  10175         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_EDC_DPD_OUT_CONTROLr), (_val), (_mask))
  10176 
  10177 #define READ_DDR34_PHY_BYTE_LANE_1_EDC_DPD_OUT_STATUSr(_unit, _pc, _val) \
  10178         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_EDC_DPD_OUT_STATUSr), (_val)) 
  10179 #define WRITE_DDR34_PHY_BYTE_LANE_1_EDC_DPD_OUT_STATUSr(_unit, _pc, _val) \
  10180         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_EDC_DPD_OUT_STATUSr), (_val))
  10181 #define MODIFY_DDR34_PHY_BYTE_LANE_1_EDC_DPD_OUT_STATUSr(_unit, _pc, _val, _mask) \
  10182         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_EDC_DPD_OUT_STATUSr), (_val), (_mask))
  10183 
  10184 #define READ_DDR34_PHY_BYTE_LANE_1_EDC_DPD_OUT_STATUS_CLEARr(_unit, _pc, _val) \
  10185         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_EDC_DPD_OUT_STATUS_CLEARr), (_val)) 
  10186 #define WRITE_DDR34_PHY_BYTE_LANE_1_EDC_DPD_OUT_STATUS_CLEARr(_unit, _pc, _val) \
  10187         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_EDC_DPD_OUT_STATUS_CLEARr), (_val))
  10188 #define MODIFY_DDR34_PHY_BYTE_LANE_1_EDC_DPD_OUT_STATUS_CLEARr(_unit, _pc, _val, _mask) \
  10189         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_EDC_DPD_OUT_STATUS_CLEARr), (_val), (_mask))
  10190 
  10191 #define READ_DDR34_PHY_BYTE_LANE_1_EDC_CRC_CONTROLr(_unit, _pc, _val) \
  10192         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_EDC_CRC_CONTROLr), (_val)) 
  10193 #define WRITE_DDR34_PHY_BYTE_LANE_1_EDC_CRC_CONTROLr(_unit, _pc, _val) \
  10194         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_EDC_CRC_CONTROLr), (_val))
  10195 #define MODIFY_DDR34_PHY_BYTE_LANE_1_EDC_CRC_CONTROLr(_unit, _pc, _val, _mask) \
  10196         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_EDC_CRC_CONTROLr), (_val), (_mask))
  10197 
  10198 #define READ_DDR34_PHY_BYTE_LANE_1_EDC_CRC_STATUSr(_unit, _pc, _val) \
  10199         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_EDC_CRC_STATUSr), (_val)) 
  10200 #define WRITE_DDR34_PHY_BYTE_LANE_1_EDC_CRC_STATUSr(_unit, _pc, _val) \
  10201         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_EDC_CRC_STATUSr), (_val))
  10202 #define MODIFY_DDR34_PHY_BYTE_LANE_1_EDC_CRC_STATUSr(_unit, _pc, _val, _mask) \
  10203         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_EDC_CRC_STATUSr), (_val), (_mask))
  10204 
  10205 #define READ_DDR34_PHY_BYTE_LANE_1_EDC_CRC_COUNTr(_unit, _pc, _val) \
  10206         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_EDC_CRC_COUNTr), (_val)) 
  10207 #define WRITE_DDR34_PHY_BYTE_LANE_1_EDC_CRC_COUNTr(_unit, _pc, _val) \
  10208         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_EDC_CRC_COUNTr), (_val))
  10209 #define MODIFY_DDR34_PHY_BYTE_LANE_1_EDC_CRC_COUNTr(_unit, _pc, _val, _mask) \
  10210         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_EDC_CRC_COUNTr), (_val), (_mask))
  10211 
  10212 #define READ_DDR34_PHY_BYTE_LANE_1_EDC_CRC_STATUS_CLEARr(_unit, _pc, _val) \
  10213         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_EDC_CRC_STATUS_CLEARr), (_val)) 
  10214 #define WRITE_DDR34_PHY_BYTE_LANE_1_EDC_CRC_STATUS_CLEARr(_unit, _pc, _val) \
  10215         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_EDC_CRC_STATUS_CLEARr), (_val))
  10216 #define MODIFY_DDR34_PHY_BYTE_LANE_1_EDC_CRC_STATUS_CLEARr(_unit, _pc, _val, _mask) \
  10217         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_EDC_CRC_STATUS_CLEARr), (_val), (_mask))
  10218 
  10219 #define READ_DDR34_PHY_BYTE_LANE_1_BL_SPARE_REGr(_unit, _pc, _val) \
  10220         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_BL_SPARE_REGr), (_val)) 
  10221 #define WRITE_DDR34_PHY_BYTE_LANE_1_BL_SPARE_REGr(_unit, _pc, _val) \
  10222         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_BL_SPARE_REGr), (_val))
  10223 #define MODIFY_DDR34_PHY_BYTE_LANE_1_BL_SPARE_REGr(_unit, _pc, _val, _mask) \
  10224         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_BL_SPARE_REGr), (_val), (_mask))
  10225 
  10226 
  10227 /***************************************************************************
  10228  *DDR34_E0_PHY_BYTE_LANE_2 - DDR34 CORE DDR34 Byte Lane #2 control registers
  10229  */
  10230 #define READ_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_Pr(_unit, _pc, _val) \
  10231         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_Pr), (_val)) 
  10232 #define WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_Pr(_unit, _pc, _val) \
  10233         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_Pr), (_val))
  10234 #define MODIFY_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_Pr(_unit, _pc, _val, _mask) \
  10235         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_Pr), (_val), (_mask))
  10236 
  10237 #define READ_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_Nr(_unit, _pc, _val) \
  10238         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_Nr), (_val)) 
  10239 #define WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_Nr(_unit, _pc, _val) \
  10240         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_Nr), (_val))
  10241 #define MODIFY_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_Nr(_unit, _pc, _val, _mask) \
  10242         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_Nr), (_val), (_mask))
  10243 
  10244 #define READ_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ0r(_unit, _pc, _val) \
  10245         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ0r), (_val)) 
  10246 #define WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ0r(_unit, _pc, _val) \
  10247         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ0r), (_val))
  10248 #define MODIFY_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ0r(_unit, _pc, _val, _mask) \
  10249         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ0r), (_val), (_mask))
  10250 
  10251 #define READ_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ1r(_unit, _pc, _val) \
  10252         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ1r), (_val)) 
  10253 #define WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ1r(_unit, _pc, _val) \
  10254         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ1r), (_val))
  10255 #define MODIFY_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ1r(_unit, _pc, _val, _mask) \
  10256         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ1r), (_val), (_mask))
  10257 
  10258 #define READ_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ2r(_unit, _pc, _val) \
  10259         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ2r), (_val)) 
  10260 #define WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ2r(_unit, _pc, _val) \
  10261         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ2r), (_val))
  10262 #define MODIFY_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ2r(_unit, _pc, _val, _mask) \
  10263         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ2r), (_val), (_mask))
  10264 
  10265 #define READ_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ3r(_unit, _pc, _val) \
  10266         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ3r), (_val)) 
  10267 #define WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ3r(_unit, _pc, _val) \
  10268         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ3r), (_val))
  10269 #define MODIFY_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ3r(_unit, _pc, _val, _mask) \
  10270         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ3r), (_val), (_mask))
  10271 
  10272 #define READ_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ4r(_unit, _pc, _val) \
  10273         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ4r), (_val)) 
  10274 #define WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ4r(_unit, _pc, _val) \
  10275         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ4r), (_val))
  10276 #define MODIFY_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ4r(_unit, _pc, _val, _mask) \
  10277         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ4r), (_val), (_mask))
  10278 
  10279 #define READ_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ5r(_unit, _pc, _val) \
  10280         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ5r), (_val)) 
  10281 #define WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ5r(_unit, _pc, _val) \
  10282         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ5r), (_val))
  10283 #define MODIFY_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ5r(_unit, _pc, _val, _mask) \
  10284         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ5r), (_val), (_mask))
  10285 
  10286 #define READ_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ6r(_unit, _pc, _val) \
  10287         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ6r), (_val)) 
  10288 #define WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ6r(_unit, _pc, _val) \
  10289         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ6r), (_val))
  10290 #define MODIFY_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ6r(_unit, _pc, _val, _mask) \
  10291         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ6r), (_val), (_mask))
  10292 
  10293 #define READ_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ7r(_unit, _pc, _val) \
  10294         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ7r), (_val)) 
  10295 #define WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ7r(_unit, _pc, _val) \
  10296         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ7r), (_val))
  10297 #define MODIFY_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ7r(_unit, _pc, _val, _mask) \
  10298         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ7r), (_val), (_mask))
  10299 
  10300 #define READ_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DMr(_unit, _pc, _val) \
  10301         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DMr), (_val)) 
  10302 #define WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DMr(_unit, _pc, _val) \
  10303         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DMr), (_val))
  10304 #define MODIFY_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DMr(_unit, _pc, _val, _mask) \
  10305         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DMr), (_val), (_mask))
  10306 
  10307 #define READ_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_EDCr(_unit, _pc, _val) \
  10308         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_EDCr), (_val)) 
  10309 #define WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_EDCr(_unit, _pc, _val) \
  10310         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_EDCr), (_val))
  10311 #define MODIFY_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_EDCr(_unit, _pc, _val, _mask) \
  10312         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_EDCr), (_val), (_mask))
  10313 
  10314 #define READ_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSPr(_unit, _pc, _val) \
  10315         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSPr), (_val)) 
  10316 #define WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSPr(_unit, _pc, _val) \
  10317         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSPr), (_val))
  10318 #define MODIFY_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSPr(_unit, _pc, _val, _mask) \
  10319         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSPr), (_val), (_mask))
  10320 
  10321 #define READ_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSNr(_unit, _pc, _val) \
  10322         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSNr), (_val)) 
  10323 #define WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSNr(_unit, _pc, _val) \
  10324         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSNr), (_val))
  10325 #define MODIFY_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSNr(_unit, _pc, _val, _mask) \
  10326         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSNr), (_val), (_mask))
  10327 
  10328 #define READ_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0Pr(_unit, _pc, _val) \
  10329         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0Pr), (_val)) 
  10330 #define WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0Pr(_unit, _pc, _val) \
  10331         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0Pr), (_val))
  10332 #define MODIFY_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0Pr(_unit, _pc, _val, _mask) \
  10333         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0Pr), (_val), (_mask))
  10334 
  10335 #define READ_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0Nr(_unit, _pc, _val) \
  10336         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0Nr), (_val)) 
  10337 #define WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0Nr(_unit, _pc, _val) \
  10338         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0Nr), (_val))
  10339 #define MODIFY_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0Nr(_unit, _pc, _val, _mask) \
  10340         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0Nr), (_val), (_mask))
  10341 
  10342 #define READ_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1Pr(_unit, _pc, _val) \
  10343         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1Pr), (_val)) 
  10344 #define WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1Pr(_unit, _pc, _val) \
  10345         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1Pr), (_val))
  10346 #define MODIFY_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1Pr(_unit, _pc, _val, _mask) \
  10347         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1Pr), (_val), (_mask))
  10348 
  10349 #define READ_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1Nr(_unit, _pc, _val) \
  10350         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1Nr), (_val)) 
  10351 #define WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1Nr(_unit, _pc, _val) \
  10352         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1Nr), (_val))
  10353 #define MODIFY_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1Nr(_unit, _pc, _val, _mask) \
  10354         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1Nr), (_val), (_mask))
  10355 
  10356 #define READ_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2Pr(_unit, _pc, _val) \
  10357         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2Pr), (_val)) 
  10358 #define WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2Pr(_unit, _pc, _val) \
  10359         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2Pr), (_val))
  10360 #define MODIFY_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2Pr(_unit, _pc, _val, _mask) \
  10361         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2Pr), (_val), (_mask))
  10362 
  10363 #define READ_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2Nr(_unit, _pc, _val) \
  10364         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2Nr), (_val)) 
  10365 #define WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2Nr(_unit, _pc, _val) \
  10366         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2Nr), (_val))
  10367 #define MODIFY_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2Nr(_unit, _pc, _val, _mask) \
  10368         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2Nr), (_val), (_mask))
  10369 
  10370 #define READ_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3Pr(_unit, _pc, _val) \
  10371         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3Pr), (_val)) 
  10372 #define WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3Pr(_unit, _pc, _val) \
  10373         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3Pr), (_val))
  10374 #define MODIFY_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3Pr(_unit, _pc, _val, _mask) \
  10375         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3Pr), (_val), (_mask))
  10376 
  10377 #define READ_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3Nr(_unit, _pc, _val) \
  10378         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3Nr), (_val)) 
  10379 #define WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3Nr(_unit, _pc, _val) \
  10380         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3Nr), (_val))
  10381 #define MODIFY_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3Nr(_unit, _pc, _val, _mask) \
  10382         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3Nr), (_val), (_mask))
  10383 
  10384 #define READ_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4Pr(_unit, _pc, _val) \
  10385         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4Pr), (_val)) 
  10386 #define WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4Pr(_unit, _pc, _val) \
  10387         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4Pr), (_val))
  10388 #define MODIFY_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4Pr(_unit, _pc, _val, _mask) \
  10389         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4Pr), (_val), (_mask))
  10390 
  10391 #define READ_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4Nr(_unit, _pc, _val) \
  10392         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4Nr), (_val)) 
  10393 #define WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4Nr(_unit, _pc, _val) \
  10394         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4Nr), (_val))
  10395 #define MODIFY_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4Nr(_unit, _pc, _val, _mask) \
  10396         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4Nr), (_val), (_mask))
  10397 
  10398 #define READ_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5Pr(_unit, _pc, _val) \
  10399         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5Pr), (_val)) 
  10400 #define WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5Pr(_unit, _pc, _val) \
  10401         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5Pr), (_val))
  10402 #define MODIFY_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5Pr(_unit, _pc, _val, _mask) \
  10403         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5Pr), (_val), (_mask))
  10404 
  10405 #define READ_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5Nr(_unit, _pc, _val) \
  10406         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5Nr), (_val)) 
  10407 #define WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5Nr(_unit, _pc, _val) \
  10408         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5Nr), (_val))
  10409 #define MODIFY_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5Nr(_unit, _pc, _val, _mask) \
  10410         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5Nr), (_val), (_mask))
  10411 
  10412 #define READ_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6Pr(_unit, _pc, _val) \
  10413         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6Pr), (_val)) 
  10414 #define WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6Pr(_unit, _pc, _val) \
  10415         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6Pr), (_val))
  10416 #define MODIFY_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6Pr(_unit, _pc, _val, _mask) \
  10417         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6Pr), (_val), (_mask))
  10418 
  10419 #define READ_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6Nr(_unit, _pc, _val) \
  10420         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6Nr), (_val)) 
  10421 #define WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6Nr(_unit, _pc, _val) \
  10422         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6Nr), (_val))
  10423 #define MODIFY_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6Nr(_unit, _pc, _val, _mask) \
  10424         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6Nr), (_val), (_mask))
  10425 
  10426 #define READ_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7Pr(_unit, _pc, _val) \
  10427         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7Pr), (_val)) 
  10428 #define WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7Pr(_unit, _pc, _val) \
  10429         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7Pr), (_val))
  10430 #define MODIFY_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7Pr(_unit, _pc, _val, _mask) \
  10431         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7Pr), (_val), (_mask))
  10432 
  10433 #define READ_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7Nr(_unit, _pc, _val) \
  10434         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7Nr), (_val)) 
  10435 #define WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7Nr(_unit, _pc, _val) \
  10436         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7Nr), (_val))
  10437 #define MODIFY_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7Nr(_unit, _pc, _val, _mask) \
  10438         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7Nr), (_val), (_mask))
  10439 
  10440 #define READ_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMPr(_unit, _pc, _val) \
  10441         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMPr), (_val)) 
  10442 #define WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMPr(_unit, _pc, _val) \
  10443         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMPr), (_val))
  10444 #define MODIFY_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMPr(_unit, _pc, _val, _mask) \
  10445         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMPr), (_val), (_mask))
  10446 
  10447 #define READ_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMNr(_unit, _pc, _val) \
  10448         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMNr), (_val)) 
  10449 #define WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMNr(_unit, _pc, _val) \
  10450         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMNr), (_val))
  10451 #define MODIFY_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMNr(_unit, _pc, _val, _mask) \
  10452         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMNr), (_val), (_mask))
  10453 
  10454 #define READ_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EDCPr(_unit, _pc, _val) \
  10455         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EDCPr), (_val)) 
  10456 #define WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EDCPr(_unit, _pc, _val) \
  10457         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EDCPr), (_val))
  10458 #define MODIFY_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EDCPr(_unit, _pc, _val, _mask) \
  10459         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EDCPr), (_val), (_mask))
  10460 
  10461 #define READ_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EDCNr(_unit, _pc, _val) \
  10462         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EDCNr), (_val)) 
  10463 #define WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EDCNr(_unit, _pc, _val) \
  10464         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EDCNr), (_val))
  10465 #define MODIFY_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EDCNr(_unit, _pc, _val, _mask) \
  10466         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EDCNr), (_val), (_mask))
  10467 
  10468 #define READ_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS0r(_unit, _pc, _val) \
  10469         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS0r), (_val)) 
  10470 #define WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS0r(_unit, _pc, _val) \
  10471         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS0r), (_val))
  10472 #define MODIFY_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS0r(_unit, _pc, _val, _mask) \
  10473         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS0r), (_val), (_mask))
  10474 
  10475 #define READ_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS1r(_unit, _pc, _val) \
  10476         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS1r), (_val)) 
  10477 #define WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS1r(_unit, _pc, _val) \
  10478         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS1r), (_val))
  10479 #define MODIFY_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS1r(_unit, _pc, _val, _mask) \
  10480         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS1r), (_val), (_mask))
  10481 
  10482 #define READ_DDR34_PHY_BYTE_LANE_2_VDL_CLK_CONTROLr(_unit, _pc, _val) \
  10483         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CLK_CONTROLr), (_val)) 
  10484 #define WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CLK_CONTROLr(_unit, _pc, _val) \
  10485         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CLK_CONTROLr), (_val))
  10486 #define MODIFY_DDR34_PHY_BYTE_LANE_2_VDL_CLK_CONTROLr(_unit, _pc, _val, _mask) \
  10487         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CLK_CONTROLr), (_val), (_mask))
  10488 
  10489 #define READ_DDR34_PHY_BYTE_LANE_2_VDL_LDE_CONTROLr(_unit, _pc, _val) \
  10490         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_LDE_CONTROLr), (_val)) 
  10491 #define WRITE_DDR34_PHY_BYTE_LANE_2_VDL_LDE_CONTROLr(_unit, _pc, _val) \
  10492         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_LDE_CONTROLr), (_val))
  10493 #define MODIFY_DDR34_PHY_BYTE_LANE_2_VDL_LDE_CONTROLr(_unit, _pc, _val, _mask) \
  10494         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_LDE_CONTROLr), (_val), (_mask))
  10495 
  10496 #define READ_DDR34_PHY_BYTE_LANE_2_RD_EN_DLY_CYCr(_unit, _pc, _val) \
  10497         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_RD_EN_DLY_CYCr), (_val)) 
  10498 #define WRITE_DDR34_PHY_BYTE_LANE_2_RD_EN_DLY_CYCr(_unit, _pc, _val) \
  10499         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_RD_EN_DLY_CYCr), (_val))
  10500 #define MODIFY_DDR34_PHY_BYTE_LANE_2_RD_EN_DLY_CYCr(_unit, _pc, _val, _mask) \
  10501         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_RD_EN_DLY_CYCr), (_val), (_mask))
  10502 
  10503 #define READ_DDR34_PHY_BYTE_LANE_2_WR_CHAN_DLY_CYCr(_unit, _pc, _val) \
  10504         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_WR_CHAN_DLY_CYCr), (_val)) 
  10505 #define WRITE_DDR34_PHY_BYTE_LANE_2_WR_CHAN_DLY_CYCr(_unit, _pc, _val) \
  10506         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_WR_CHAN_DLY_CYCr), (_val))
  10507 #define MODIFY_DDR34_PHY_BYTE_LANE_2_WR_CHAN_DLY_CYCr(_unit, _pc, _val, _mask) \
  10508         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_WR_CHAN_DLY_CYCr), (_val), (_mask))
  10509 
  10510 #define READ_DDR34_PHY_BYTE_LANE_2_READ_CONTROLr(_unit, _pc, _val) \
  10511         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_READ_CONTROLr), (_val)) 
  10512 #define WRITE_DDR34_PHY_BYTE_LANE_2_READ_CONTROLr(_unit, _pc, _val) \
  10513         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_READ_CONTROLr), (_val))
  10514 #define MODIFY_DDR34_PHY_BYTE_LANE_2_READ_CONTROLr(_unit, _pc, _val, _mask) \
  10515         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_READ_CONTROLr), (_val), (_mask))
  10516 
  10517 #define READ_DDR34_PHY_BYTE_LANE_2_READ_FIFO_ADDRr(_unit, _pc, _val) \
  10518         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_READ_FIFO_ADDRr), (_val)) 
  10519 #define WRITE_DDR34_PHY_BYTE_LANE_2_READ_FIFO_ADDRr(_unit, _pc, _val) \
  10520         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_READ_FIFO_ADDRr), (_val))
  10521 #define MODIFY_DDR34_PHY_BYTE_LANE_2_READ_FIFO_ADDRr(_unit, _pc, _val, _mask) \
  10522         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_READ_FIFO_ADDRr), (_val), (_mask))
  10523 
  10524 #define READ_DDR34_PHY_BYTE_LANE_2_READ_FIFO_DATAr(_unit, _pc, _val) \
  10525         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_READ_FIFO_DATAr), (_val)) 
  10526 #define WRITE_DDR34_PHY_BYTE_LANE_2_READ_FIFO_DATAr(_unit, _pc, _val) \
  10527         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_READ_FIFO_DATAr), (_val))
  10528 #define MODIFY_DDR34_PHY_BYTE_LANE_2_READ_FIFO_DATAr(_unit, _pc, _val, _mask) \
  10529         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_READ_FIFO_DATAr), (_val), (_mask))
  10530 
  10531 #define READ_DDR34_PHY_BYTE_LANE_2_READ_FIFO_DM_DBIr(_unit, _pc, _val) \
  10532         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_READ_FIFO_DM_DBIr), (_val)) 
  10533 #define WRITE_DDR34_PHY_BYTE_LANE_2_READ_FIFO_DM_DBIr(_unit, _pc, _val) \
  10534         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_READ_FIFO_DM_DBIr), (_val))
  10535 #define MODIFY_DDR34_PHY_BYTE_LANE_2_READ_FIFO_DM_DBIr(_unit, _pc, _val, _mask) \
  10536         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_READ_FIFO_DM_DBIr), (_val), (_mask))
  10537 
  10538 #define READ_DDR34_PHY_BYTE_LANE_2_READ_FIFO_STATUSr(_unit, _pc, _val) \
  10539         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_READ_FIFO_STATUSr), (_val)) 
  10540 #define WRITE_DDR34_PHY_BYTE_LANE_2_READ_FIFO_STATUSr(_unit, _pc, _val) \
  10541         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_READ_FIFO_STATUSr), (_val))
  10542 #define MODIFY_DDR34_PHY_BYTE_LANE_2_READ_FIFO_STATUSr(_unit, _pc, _val, _mask) \
  10543         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_READ_FIFO_STATUSr), (_val), (_mask))
  10544 
  10545 #define READ_DDR34_PHY_BYTE_LANE_2_READ_FIFO_CLEARr(_unit, _pc, _val) \
  10546         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_READ_FIFO_CLEARr), (_val)) 
  10547 #define WRITE_DDR34_PHY_BYTE_LANE_2_READ_FIFO_CLEARr(_unit, _pc, _val) \
  10548         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_READ_FIFO_CLEARr), (_val))
  10549 #define MODIFY_DDR34_PHY_BYTE_LANE_2_READ_FIFO_CLEARr(_unit, _pc, _val, _mask) \
  10550         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_READ_FIFO_CLEARr), (_val), (_mask))
  10551 
  10552 #define READ_DDR34_PHY_BYTE_LANE_2_IDLE_PAD_CONTROLr(_unit, _pc, _val) \
  10553         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_IDLE_PAD_CONTROLr), (_val)) 
  10554 #define WRITE_DDR34_PHY_BYTE_LANE_2_IDLE_PAD_CONTROLr(_unit, _pc, _val) \
  10555         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_IDLE_PAD_CONTROLr), (_val))
  10556 #define MODIFY_DDR34_PHY_BYTE_LANE_2_IDLE_PAD_CONTROLr(_unit, _pc, _val, _mask) \
  10557         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_IDLE_PAD_CONTROLr), (_val), (_mask))
  10558 
  10559 #define READ_DDR34_PHY_BYTE_LANE_2_DRIVE_PAD_CTLr(_unit, _pc, _val) \
  10560         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_DRIVE_PAD_CTLr), (_val)) 
  10561 #define WRITE_DDR34_PHY_BYTE_LANE_2_DRIVE_PAD_CTLr(_unit, _pc, _val) \
  10562         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_DRIVE_PAD_CTLr), (_val))
  10563 #define MODIFY_DDR34_PHY_BYTE_LANE_2_DRIVE_PAD_CTLr(_unit, _pc, _val, _mask) \
  10564         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_DRIVE_PAD_CTLr), (_val), (_mask))
  10565 
  10566 #define READ_DDR34_PHY_BYTE_LANE_2_RD_EN_DRIVE_PAD_CTLr(_unit, _pc, _val) \
  10567         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_RD_EN_DRIVE_PAD_CTLr), (_val)) 
  10568 #define WRITE_DDR34_PHY_BYTE_LANE_2_RD_EN_DRIVE_PAD_CTLr(_unit, _pc, _val) \
  10569         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_RD_EN_DRIVE_PAD_CTLr), (_val))
  10570 #define MODIFY_DDR34_PHY_BYTE_LANE_2_RD_EN_DRIVE_PAD_CTLr(_unit, _pc, _val, _mask) \
  10571         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_RD_EN_DRIVE_PAD_CTLr), (_val), (_mask))
  10572 
  10573 #define READ_DDR34_PHY_BYTE_LANE_2_STATIC_PAD_CTLr(_unit, _pc, _val) \
  10574         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_STATIC_PAD_CTLr), (_val)) 
  10575 #define WRITE_DDR34_PHY_BYTE_LANE_2_STATIC_PAD_CTLr(_unit, _pc, _val) \
  10576         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_STATIC_PAD_CTLr), (_val))
  10577 #define MODIFY_DDR34_PHY_BYTE_LANE_2_STATIC_PAD_CTLr(_unit, _pc, _val, _mask) \
  10578         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_STATIC_PAD_CTLr), (_val), (_mask))
  10579 
  10580 #define READ_DDR34_PHY_BYTE_LANE_2_WR_PREAMBLE_MODEr(_unit, _pc, _val) \
  10581         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_WR_PREAMBLE_MODEr), (_val)) 
  10582 #define WRITE_DDR34_PHY_BYTE_LANE_2_WR_PREAMBLE_MODEr(_unit, _pc, _val) \
  10583         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_WR_PREAMBLE_MODEr), (_val))
  10584 #define MODIFY_DDR34_PHY_BYTE_LANE_2_WR_PREAMBLE_MODEr(_unit, _pc, _val, _mask) \
  10585         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_WR_PREAMBLE_MODEr), (_val), (_mask))
  10586 
  10587 #define READ_DDR34_PHY_BYTE_LANE_2_ODT_CONTROLr(_unit, _pc, _val) \
  10588         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_ODT_CONTROLr), (_val)) 
  10589 #define WRITE_DDR34_PHY_BYTE_LANE_2_ODT_CONTROLr(_unit, _pc, _val) \
  10590         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_ODT_CONTROLr), (_val))
  10591 #define MODIFY_DDR34_PHY_BYTE_LANE_2_ODT_CONTROLr(_unit, _pc, _val, _mask) \
  10592         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_ODT_CONTROLr), (_val), (_mask))
  10593 
  10594 #define READ_DDR34_PHY_BYTE_LANE_2_EDC_DPD_CONTROLr(_unit, _pc, _val) \
  10595         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_EDC_DPD_CONTROLr), (_val)) 
  10596 #define WRITE_DDR34_PHY_BYTE_LANE_2_EDC_DPD_CONTROLr(_unit, _pc, _val) \
  10597         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_EDC_DPD_CONTROLr), (_val))
  10598 #define MODIFY_DDR34_PHY_BYTE_LANE_2_EDC_DPD_CONTROLr(_unit, _pc, _val, _mask) \
  10599         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_EDC_DPD_CONTROLr), (_val), (_mask))
  10600 
  10601 #define READ_DDR34_PHY_BYTE_LANE_2_EDC_DPD_STATUSr(_unit, _pc, _val) \
  10602         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_EDC_DPD_STATUSr), (_val)) 
  10603 #define WRITE_DDR34_PHY_BYTE_LANE_2_EDC_DPD_STATUSr(_unit, _pc, _val) \
  10604         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_EDC_DPD_STATUSr), (_val))
  10605 #define MODIFY_DDR34_PHY_BYTE_LANE_2_EDC_DPD_STATUSr(_unit, _pc, _val, _mask) \
  10606         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_EDC_DPD_STATUSr), (_val), (_mask))
  10607 
  10608 #define READ_DDR34_PHY_BYTE_LANE_2_EDC_DPD_OUT_CONTROLr(_unit, _pc, _val) \
  10609         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_EDC_DPD_OUT_CONTROLr), (_val)) 
  10610 #define WRITE_DDR34_PHY_BYTE_LANE_2_EDC_DPD_OUT_CONTROLr(_unit, _pc, _val) \
  10611         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_EDC_DPD_OUT_CONTROLr), (_val))
  10612 #define MODIFY_DDR34_PHY_BYTE_LANE_2_EDC_DPD_OUT_CONTROLr(_unit, _pc, _val, _mask) \
  10613         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_EDC_DPD_OUT_CONTROLr), (_val), (_mask))
  10614 
  10615 #define READ_DDR34_PHY_BYTE_LANE_2_EDC_DPD_OUT_STATUSr(_unit, _pc, _val) \
  10616         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_EDC_DPD_OUT_STATUSr), (_val)) 
  10617 #define WRITE_DDR34_PHY_BYTE_LANE_2_EDC_DPD_OUT_STATUSr(_unit, _pc, _val) \
  10618         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_EDC_DPD_OUT_STATUSr), (_val))
  10619 #define MODIFY_DDR34_PHY_BYTE_LANE_2_EDC_DPD_OUT_STATUSr(_unit, _pc, _val, _mask) \
  10620         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_EDC_DPD_OUT_STATUSr), (_val), (_mask))
  10621 
  10622 #define READ_DDR34_PHY_BYTE_LANE_2_EDC_DPD_OUT_STATUS_CLEARr(_unit, _pc, _val) \
  10623         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_EDC_DPD_OUT_STATUS_CLEARr), (_val)) 
  10624 #define WRITE_DDR34_PHY_BYTE_LANE_2_EDC_DPD_OUT_STATUS_CLEARr(_unit, _pc, _val) \
  10625         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_EDC_DPD_OUT_STATUS_CLEARr), (_val))
  10626 #define MODIFY_DDR34_PHY_BYTE_LANE_2_EDC_DPD_OUT_STATUS_CLEARr(_unit, _pc, _val, _mask) \
  10627         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_EDC_DPD_OUT_STATUS_CLEARr), (_val), (_mask))
  10628 
  10629 #define READ_DDR34_PHY_BYTE_LANE_2_EDC_CRC_CONTROLr(_unit, _pc, _val) \
  10630         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_EDC_CRC_CONTROLr), (_val)) 
  10631 #define WRITE_DDR34_PHY_BYTE_LANE_2_EDC_CRC_CONTROLr(_unit, _pc, _val) \
  10632         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_EDC_CRC_CONTROLr), (_val))
  10633 #define MODIFY_DDR34_PHY_BYTE_LANE_2_EDC_CRC_CONTROLr(_unit, _pc, _val, _mask) \
  10634         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_EDC_CRC_CONTROLr), (_val), (_mask))
  10635 
  10636 #define READ_DDR34_PHY_BYTE_LANE_2_EDC_CRC_STATUSr(_unit, _pc, _val) \
  10637         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_EDC_CRC_STATUSr), (_val)) 
  10638 #define WRITE_DDR34_PHY_BYTE_LANE_2_EDC_CRC_STATUSr(_unit, _pc, _val) \
  10639         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_EDC_CRC_STATUSr), (_val))
  10640 #define MODIFY_DDR34_PHY_BYTE_LANE_2_EDC_CRC_STATUSr(_unit, _pc, _val, _mask) \
  10641         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_EDC_CRC_STATUSr), (_val), (_mask))
  10642 
  10643 #define READ_DDR34_PHY_BYTE_LANE_2_EDC_CRC_COUNTr(_unit, _pc, _val) \
  10644         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_EDC_CRC_COUNTr), (_val)) 
  10645 #define WRITE_DDR34_PHY_BYTE_LANE_2_EDC_CRC_COUNTr(_unit, _pc, _val) \
  10646         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_EDC_CRC_COUNTr), (_val))
  10647 #define MODIFY_DDR34_PHY_BYTE_LANE_2_EDC_CRC_COUNTr(_unit, _pc, _val, _mask) \
  10648         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_EDC_CRC_COUNTr), (_val), (_mask))
  10649 
  10650 #define READ_DDR34_PHY_BYTE_LANE_2_EDC_CRC_STATUS_CLEARr(_unit, _pc, _val) \
  10651         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_EDC_CRC_STATUS_CLEARr), (_val)) 
  10652 #define WRITE_DDR34_PHY_BYTE_LANE_2_EDC_CRC_STATUS_CLEARr(_unit, _pc, _val) \
  10653         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_EDC_CRC_STATUS_CLEARr), (_val))
  10654 #define MODIFY_DDR34_PHY_BYTE_LANE_2_EDC_CRC_STATUS_CLEARr(_unit, _pc, _val, _mask) \
  10655         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_EDC_CRC_STATUS_CLEARr), (_val), (_mask))
  10656 
  10657 #define READ_DDR34_PHY_BYTE_LANE_2_BL_SPARE_REGr(_unit, _pc, _val) \
  10658         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_BL_SPARE_REGr), (_val)) 
  10659 #define WRITE_DDR34_PHY_BYTE_LANE_2_BL_SPARE_REGr(_unit, _pc, _val) \
  10660         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_BL_SPARE_REGr), (_val))
  10661 #define MODIFY_DDR34_PHY_BYTE_LANE_2_BL_SPARE_REGr(_unit, _pc, _val, _mask) \
  10662         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_BL_SPARE_REGr), (_val), (_mask))
  10663 
  10664 
  10665 /***************************************************************************
  10666  *DDR34_E0_PHY_BYTE_LANE_3 - DDR34 CORE DDR34 Byte Lane #3 control registers
  10667  */
  10668 #define READ_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_Pr(_unit, _pc, _val) \
  10669         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_Pr), (_val)) 
  10670 #define WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_Pr(_unit, _pc, _val) \
  10671         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_Pr), (_val))
  10672 #define MODIFY_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_Pr(_unit, _pc, _val, _mask) \
  10673         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_Pr), (_val), (_mask))
  10674 
  10675 #define READ_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_Nr(_unit, _pc, _val) \
  10676         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_Nr), (_val)) 
  10677 #define WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_Nr(_unit, _pc, _val) \
  10678         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_Nr), (_val))
  10679 #define MODIFY_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_Nr(_unit, _pc, _val, _mask) \
  10680         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_Nr), (_val), (_mask))
  10681 
  10682 #define READ_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ0r(_unit, _pc, _val) \
  10683         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ0r), (_val)) 
  10684 #define WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ0r(_unit, _pc, _val) \
  10685         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ0r), (_val))
  10686 #define MODIFY_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ0r(_unit, _pc, _val, _mask) \
  10687         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ0r), (_val), (_mask))
  10688 
  10689 #define READ_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ1r(_unit, _pc, _val) \
  10690         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ1r), (_val)) 
  10691 #define WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ1r(_unit, _pc, _val) \
  10692         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ1r), (_val))
  10693 #define MODIFY_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ1r(_unit, _pc, _val, _mask) \
  10694         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ1r), (_val), (_mask))
  10695 
  10696 #define READ_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ2r(_unit, _pc, _val) \
  10697         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ2r), (_val)) 
  10698 #define WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ2r(_unit, _pc, _val) \
  10699         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ2r), (_val))
  10700 #define MODIFY_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ2r(_unit, _pc, _val, _mask) \
  10701         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ2r), (_val), (_mask))
  10702 
  10703 #define READ_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ3r(_unit, _pc, _val) \
  10704         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ3r), (_val)) 
  10705 #define WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ3r(_unit, _pc, _val) \
  10706         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ3r), (_val))
  10707 #define MODIFY_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ3r(_unit, _pc, _val, _mask) \
  10708         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ3r), (_val), (_mask))
  10709 
  10710 #define READ_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ4r(_unit, _pc, _val) \
  10711         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ4r), (_val)) 
  10712 #define WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ4r(_unit, _pc, _val) \
  10713         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ4r), (_val))
  10714 #define MODIFY_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ4r(_unit, _pc, _val, _mask) \
  10715         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ4r), (_val), (_mask))
  10716 
  10717 #define READ_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ5r(_unit, _pc, _val) \
  10718         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ5r), (_val)) 
  10719 #define WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ5r(_unit, _pc, _val) \
  10720         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ5r), (_val))
  10721 #define MODIFY_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ5r(_unit, _pc, _val, _mask) \
  10722         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ5r), (_val), (_mask))
  10723 
  10724 #define READ_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ6r(_unit, _pc, _val) \
  10725         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ6r), (_val)) 
  10726 #define WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ6r(_unit, _pc, _val) \
  10727         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ6r), (_val))
  10728 #define MODIFY_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ6r(_unit, _pc, _val, _mask) \
  10729         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ6r), (_val), (_mask))
  10730 
  10731 #define READ_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ7r(_unit, _pc, _val) \
  10732         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ7r), (_val)) 
  10733 #define WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ7r(_unit, _pc, _val) \
  10734         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ7r), (_val))
  10735 #define MODIFY_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ7r(_unit, _pc, _val, _mask) \
  10736         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ7r), (_val), (_mask))
  10737 
  10738 #define READ_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DMr(_unit, _pc, _val) \
  10739         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DMr), (_val)) 
  10740 #define WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DMr(_unit, _pc, _val) \
  10741         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DMr), (_val))
  10742 #define MODIFY_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DMr(_unit, _pc, _val, _mask) \
  10743         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DMr), (_val), (_mask))
  10744 
  10745 #define READ_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_EDCr(_unit, _pc, _val) \
  10746         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_EDCr), (_val)) 
  10747 #define WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_EDCr(_unit, _pc, _val) \
  10748         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_EDCr), (_val))
  10749 #define MODIFY_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_EDCr(_unit, _pc, _val, _mask) \
  10750         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_EDCr), (_val), (_mask))
  10751 
  10752 #define READ_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSPr(_unit, _pc, _val) \
  10753         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSPr), (_val)) 
  10754 #define WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSPr(_unit, _pc, _val) \
  10755         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSPr), (_val))
  10756 #define MODIFY_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSPr(_unit, _pc, _val, _mask) \
  10757         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSPr), (_val), (_mask))
  10758 
  10759 #define READ_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSNr(_unit, _pc, _val) \
  10760         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSNr), (_val)) 
  10761 #define WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSNr(_unit, _pc, _val) \
  10762         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSNr), (_val))
  10763 #define MODIFY_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSNr(_unit, _pc, _val, _mask) \
  10764         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSNr), (_val), (_mask))
  10765 
  10766 #define READ_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0Pr(_unit, _pc, _val) \
  10767         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0Pr), (_val)) 
  10768 #define WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0Pr(_unit, _pc, _val) \
  10769         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0Pr), (_val))
  10770 #define MODIFY_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0Pr(_unit, _pc, _val, _mask) \
  10771         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0Pr), (_val), (_mask))
  10772 
  10773 #define READ_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0Nr(_unit, _pc, _val) \
  10774         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0Nr), (_val)) 
  10775 #define WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0Nr(_unit, _pc, _val) \
  10776         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0Nr), (_val))
  10777 #define MODIFY_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0Nr(_unit, _pc, _val, _mask) \
  10778         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0Nr), (_val), (_mask))
  10779 
  10780 #define READ_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1Pr(_unit, _pc, _val) \
  10781         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1Pr), (_val)) 
  10782 #define WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1Pr(_unit, _pc, _val) \
  10783         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1Pr), (_val))
  10784 #define MODIFY_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1Pr(_unit, _pc, _val, _mask) \
  10785         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1Pr), (_val), (_mask))
  10786 
  10787 #define READ_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1Nr(_unit, _pc, _val) \
  10788         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1Nr), (_val)) 
  10789 #define WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1Nr(_unit, _pc, _val) \
  10790         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1Nr), (_val))
  10791 #define MODIFY_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1Nr(_unit, _pc, _val, _mask) \
  10792         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1Nr), (_val), (_mask))
  10793 
  10794 #define READ_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2Pr(_unit, _pc, _val) \
  10795         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2Pr), (_val)) 
  10796 #define WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2Pr(_unit, _pc, _val) \
  10797         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2Pr), (_val))
  10798 #define MODIFY_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2Pr(_unit, _pc, _val, _mask) \
  10799         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2Pr), (_val), (_mask))
  10800 
  10801 #define READ_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2Nr(_unit, _pc, _val) \
  10802         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2Nr), (_val)) 
  10803 #define WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2Nr(_unit, _pc, _val) \
  10804         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2Nr), (_val))
  10805 #define MODIFY_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2Nr(_unit, _pc, _val, _mask) \
  10806         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2Nr), (_val), (_mask))
  10807 
  10808 #define READ_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3Pr(_unit, _pc, _val) \
  10809         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3Pr), (_val)) 
  10810 #define WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3Pr(_unit, _pc, _val) \
  10811         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3Pr), (_val))
  10812 #define MODIFY_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3Pr(_unit, _pc, _val, _mask) \
  10813         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3Pr), (_val), (_mask))
  10814 
  10815 #define READ_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3Nr(_unit, _pc, _val) \
  10816         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3Nr), (_val)) 
  10817 #define WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3Nr(_unit, _pc, _val) \
  10818         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3Nr), (_val))
  10819 #define MODIFY_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3Nr(_unit, _pc, _val, _mask) \
  10820         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3Nr), (_val), (_mask))
  10821 
  10822 #define READ_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4Pr(_unit, _pc, _val) \
  10823         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4Pr), (_val)) 
  10824 #define WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4Pr(_unit, _pc, _val) \
  10825         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4Pr), (_val))
  10826 #define MODIFY_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4Pr(_unit, _pc, _val, _mask) \
  10827         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4Pr), (_val), (_mask))
  10828 
  10829 #define READ_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4Nr(_unit, _pc, _val) \
  10830         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4Nr), (_val)) 
  10831 #define WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4Nr(_unit, _pc, _val) \
  10832         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4Nr), (_val))
  10833 #define MODIFY_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4Nr(_unit, _pc, _val, _mask) \
  10834         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4Nr), (_val), (_mask))
  10835 
  10836 #define READ_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5Pr(_unit, _pc, _val) \
  10837         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5Pr), (_val)) 
  10838 #define WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5Pr(_unit, _pc, _val) \
  10839         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5Pr), (_val))
  10840 #define MODIFY_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5Pr(_unit, _pc, _val, _mask) \
  10841         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5Pr), (_val), (_mask))
  10842 
  10843 #define READ_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5Nr(_unit, _pc, _val) \
  10844         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5Nr), (_val)) 
  10845 #define WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5Nr(_unit, _pc, _val) \
  10846         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5Nr), (_val))
  10847 #define MODIFY_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5Nr(_unit, _pc, _val, _mask) \
  10848         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5Nr), (_val), (_mask))
  10849 
  10850 #define READ_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6Pr(_unit, _pc, _val) \
  10851         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6Pr), (_val)) 
  10852 #define WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6Pr(_unit, _pc, _val) \
  10853         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6Pr), (_val))
  10854 #define MODIFY_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6Pr(_unit, _pc, _val, _mask) \
  10855         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6Pr), (_val), (_mask))
  10856 
  10857 #define READ_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6Nr(_unit, _pc, _val) \
  10858         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6Nr), (_val)) 
  10859 #define WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6Nr(_unit, _pc, _val) \
  10860         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6Nr), (_val))
  10861 #define MODIFY_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6Nr(_unit, _pc, _val, _mask) \
  10862         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6Nr), (_val), (_mask))
  10863 
  10864 #define READ_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7Pr(_unit, _pc, _val) \
  10865         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7Pr), (_val)) 
  10866 #define WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7Pr(_unit, _pc, _val) \
  10867         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7Pr), (_val))
  10868 #define MODIFY_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7Pr(_unit, _pc, _val, _mask) \
  10869         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7Pr), (_val), (_mask))
  10870 
  10871 #define READ_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7Nr(_unit, _pc, _val) \
  10872         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7Nr), (_val)) 
  10873 #define WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7Nr(_unit, _pc, _val) \
  10874         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7Nr), (_val))
  10875 #define MODIFY_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7Nr(_unit, _pc, _val, _mask) \
  10876         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7Nr), (_val), (_mask))
  10877 
  10878 #define READ_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMPr(_unit, _pc, _val) \
  10879         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMPr), (_val)) 
  10880 #define WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMPr(_unit, _pc, _val) \
  10881         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMPr), (_val))
  10882 #define MODIFY_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMPr(_unit, _pc, _val, _mask) \
  10883         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMPr), (_val), (_mask))
  10884 
  10885 #define READ_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMNr(_unit, _pc, _val) \
  10886         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMNr), (_val)) 
  10887 #define WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMNr(_unit, _pc, _val) \
  10888         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMNr), (_val))
  10889 #define MODIFY_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMNr(_unit, _pc, _val, _mask) \
  10890         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMNr), (_val), (_mask))
  10891 
  10892 #define READ_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EDCPr(_unit, _pc, _val) \
  10893         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EDCPr), (_val)) 
  10894 #define WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EDCPr(_unit, _pc, _val) \
  10895         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EDCPr), (_val))
  10896 #define MODIFY_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EDCPr(_unit, _pc, _val, _mask) \
  10897         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EDCPr), (_val), (_mask))
  10898 
  10899 #define READ_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EDCNr(_unit, _pc, _val) \
  10900         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EDCNr), (_val)) 
  10901 #define WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EDCNr(_unit, _pc, _val) \
  10902         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EDCNr), (_val))
  10903 #define MODIFY_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EDCNr(_unit, _pc, _val, _mask) \
  10904         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EDCNr), (_val), (_mask))
  10905 
  10906 #define READ_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS0r(_unit, _pc, _val) \
  10907         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS0r), (_val)) 
  10908 #define WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS0r(_unit, _pc, _val) \
  10909         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS0r), (_val))
  10910 #define MODIFY_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS0r(_unit, _pc, _val, _mask) \
  10911         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS0r), (_val), (_mask))
  10912 
  10913 #define READ_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS1r(_unit, _pc, _val) \
  10914         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS1r), (_val)) 
  10915 #define WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS1r(_unit, _pc, _val) \
  10916         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS1r), (_val))
  10917 #define MODIFY_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS1r(_unit, _pc, _val, _mask) \
  10918         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS1r), (_val), (_mask))
  10919 
  10920 #define READ_DDR34_PHY_BYTE_LANE_3_VDL_CLK_CONTROLr(_unit, _pc, _val) \
  10921         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CLK_CONTROLr), (_val)) 
  10922 #define WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CLK_CONTROLr(_unit, _pc, _val) \
  10923         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CLK_CONTROLr), (_val))
  10924 #define MODIFY_DDR34_PHY_BYTE_LANE_3_VDL_CLK_CONTROLr(_unit, _pc, _val, _mask) \
  10925         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CLK_CONTROLr), (_val), (_mask))
  10926 
  10927 #define READ_DDR34_PHY_BYTE_LANE_3_VDL_LDE_CONTROLr(_unit, _pc, _val) \
  10928         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_LDE_CONTROLr), (_val)) 
  10929 #define WRITE_DDR34_PHY_BYTE_LANE_3_VDL_LDE_CONTROLr(_unit, _pc, _val) \
  10930         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_LDE_CONTROLr), (_val))
  10931 #define MODIFY_DDR34_PHY_BYTE_LANE_3_VDL_LDE_CONTROLr(_unit, _pc, _val, _mask) \
  10932         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_LDE_CONTROLr), (_val), (_mask))
  10933 
  10934 #define READ_DDR34_PHY_BYTE_LANE_3_RD_EN_DLY_CYCr(_unit, _pc, _val) \
  10935         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_RD_EN_DLY_CYCr), (_val)) 
  10936 #define WRITE_DDR34_PHY_BYTE_LANE_3_RD_EN_DLY_CYCr(_unit, _pc, _val) \
  10937         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_RD_EN_DLY_CYCr), (_val))
  10938 #define MODIFY_DDR34_PHY_BYTE_LANE_3_RD_EN_DLY_CYCr(_unit, _pc, _val, _mask) \
  10939         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_RD_EN_DLY_CYCr), (_val), (_mask))
  10940 
  10941 #define READ_DDR34_PHY_BYTE_LANE_3_WR_CHAN_DLY_CYCr(_unit, _pc, _val) \
  10942         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_WR_CHAN_DLY_CYCr), (_val)) 
  10943 #define WRITE_DDR34_PHY_BYTE_LANE_3_WR_CHAN_DLY_CYCr(_unit, _pc, _val) \
  10944         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_WR_CHAN_DLY_CYCr), (_val))
  10945 #define MODIFY_DDR34_PHY_BYTE_LANE_3_WR_CHAN_DLY_CYCr(_unit, _pc, _val, _mask) \
  10946         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_WR_CHAN_DLY_CYCr), (_val), (_mask))
  10947 
  10948 #define READ_DDR34_PHY_BYTE_LANE_3_READ_CONTROLr(_unit, _pc, _val) \
  10949         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_READ_CONTROLr), (_val)) 
  10950 #define WRITE_DDR34_PHY_BYTE_LANE_3_READ_CONTROLr(_unit, _pc, _val) \
  10951         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_READ_CONTROLr), (_val))
  10952 #define MODIFY_DDR34_PHY_BYTE_LANE_3_READ_CONTROLr(_unit, _pc, _val, _mask) \
  10953         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_READ_CONTROLr), (_val), (_mask))
  10954 
  10955 #define READ_DDR34_PHY_BYTE_LANE_3_READ_FIFO_ADDRr(_unit, _pc, _val) \
  10956         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_READ_FIFO_ADDRr), (_val)) 
  10957 #define WRITE_DDR34_PHY_BYTE_LANE_3_READ_FIFO_ADDRr(_unit, _pc, _val) \
  10958         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_READ_FIFO_ADDRr), (_val))
  10959 #define MODIFY_DDR34_PHY_BYTE_LANE_3_READ_FIFO_ADDRr(_unit, _pc, _val, _mask) \
  10960         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_READ_FIFO_ADDRr), (_val), (_mask))
  10961 
  10962 #define READ_DDR34_PHY_BYTE_LANE_3_READ_FIFO_DATAr(_unit, _pc, _val) \
  10963         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_READ_FIFO_DATAr), (_val)) 
  10964 #define WRITE_DDR34_PHY_BYTE_LANE_3_READ_FIFO_DATAr(_unit, _pc, _val) \
  10965         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_READ_FIFO_DATAr), (_val))
  10966 #define MODIFY_DDR34_PHY_BYTE_LANE_3_READ_FIFO_DATAr(_unit, _pc, _val, _mask) \
  10967         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_READ_FIFO_DATAr), (_val), (_mask))
  10968 
  10969 #define READ_DDR34_PHY_BYTE_LANE_3_READ_FIFO_DM_DBIr(_unit, _pc, _val) \
  10970         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_READ_FIFO_DM_DBIr), (_val)) 
  10971 #define WRITE_DDR34_PHY_BYTE_LANE_3_READ_FIFO_DM_DBIr(_unit, _pc, _val) \
  10972         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_READ_FIFO_DM_DBIr), (_val))
  10973 #define MODIFY_DDR34_PHY_BYTE_LANE_3_READ_FIFO_DM_DBIr(_unit, _pc, _val, _mask) \
  10974         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_READ_FIFO_DM_DBIr), (_val), (_mask))
  10975 
  10976 #define READ_DDR34_PHY_BYTE_LANE_3_READ_FIFO_STATUSr(_unit, _pc, _val) \
  10977         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_READ_FIFO_STATUSr), (_val)) 
  10978 #define WRITE_DDR34_PHY_BYTE_LANE_3_READ_FIFO_STATUSr(_unit, _pc, _val) \
  10979         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_READ_FIFO_STATUSr), (_val))
  10980 #define MODIFY_DDR34_PHY_BYTE_LANE_3_READ_FIFO_STATUSr(_unit, _pc, _val, _mask) \
  10981         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_READ_FIFO_STATUSr), (_val), (_mask))
  10982 
  10983 #define READ_DDR34_PHY_BYTE_LANE_3_READ_FIFO_CLEARr(_unit, _pc, _val) \
  10984         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_READ_FIFO_CLEARr), (_val)) 
  10985 #define WRITE_DDR34_PHY_BYTE_LANE_3_READ_FIFO_CLEARr(_unit, _pc, _val) \
  10986         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_READ_FIFO_CLEARr), (_val))
  10987 #define MODIFY_DDR34_PHY_BYTE_LANE_3_READ_FIFO_CLEARr(_unit, _pc, _val, _mask) \
  10988         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_READ_FIFO_CLEARr), (_val), (_mask))
  10989 
  10990 #define READ_DDR34_PHY_BYTE_LANE_3_IDLE_PAD_CONTROLr(_unit, _pc, _val) \
  10991         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_IDLE_PAD_CONTROLr), (_val)) 
  10992 #define WRITE_DDR34_PHY_BYTE_LANE_3_IDLE_PAD_CONTROLr(_unit, _pc, _val) \
  10993         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_IDLE_PAD_CONTROLr), (_val))
  10994 #define MODIFY_DDR34_PHY_BYTE_LANE_3_IDLE_PAD_CONTROLr(_unit, _pc, _val, _mask) \
  10995         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_IDLE_PAD_CONTROLr), (_val), (_mask))
  10996 
  10997 #define READ_DDR34_PHY_BYTE_LANE_3_DRIVE_PAD_CTLr(_unit, _pc, _val) \
  10998         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_DRIVE_PAD_CTLr), (_val)) 
  10999 #define WRITE_DDR34_PHY_BYTE_LANE_3_DRIVE_PAD_CTLr(_unit, _pc, _val) \
  11000         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_DRIVE_PAD_CTLr), (_val))
  11001 #define MODIFY_DDR34_PHY_BYTE_LANE_3_DRIVE_PAD_CTLr(_unit, _pc, _val, _mask) \
  11002         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_DRIVE_PAD_CTLr), (_val), (_mask))
  11003 
  11004 #define READ_DDR34_PHY_BYTE_LANE_3_RD_EN_DRIVE_PAD_CTLr(_unit, _pc, _val) \
  11005         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_RD_EN_DRIVE_PAD_CTLr), (_val)) 
  11006 #define WRITE_DDR34_PHY_BYTE_LANE_3_RD_EN_DRIVE_PAD_CTLr(_unit, _pc, _val) \
  11007         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_RD_EN_DRIVE_PAD_CTLr), (_val))
  11008 #define MODIFY_DDR34_PHY_BYTE_LANE_3_RD_EN_DRIVE_PAD_CTLr(_unit, _pc, _val, _mask) \
  11009         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_RD_EN_DRIVE_PAD_CTLr), (_val), (_mask))
  11010 
  11011 #define READ_DDR34_PHY_BYTE_LANE_3_STATIC_PAD_CTLr(_unit, _pc, _val) \
  11012         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_STATIC_PAD_CTLr), (_val)) 
  11013 #define WRITE_DDR34_PHY_BYTE_LANE_3_STATIC_PAD_CTLr(_unit, _pc, _val) \
  11014         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_STATIC_PAD_CTLr), (_val))
  11015 #define MODIFY_DDR34_PHY_BYTE_LANE_3_STATIC_PAD_CTLr(_unit, _pc, _val, _mask) \
  11016         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_STATIC_PAD_CTLr), (_val), (_mask))
  11017 
  11018 #define READ_DDR34_PHY_BYTE_LANE_3_WR_PREAMBLE_MODEr(_unit, _pc, _val) \
  11019         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_WR_PREAMBLE_MODEr), (_val)) 
  11020 #define WRITE_DDR34_PHY_BYTE_LANE_3_WR_PREAMBLE_MODEr(_unit, _pc, _val) \
  11021         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_WR_PREAMBLE_MODEr), (_val))
  11022 #define MODIFY_DDR34_PHY_BYTE_LANE_3_WR_PREAMBLE_MODEr(_unit, _pc, _val, _mask) \
  11023         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_WR_PREAMBLE_MODEr), (_val), (_mask))
  11024 
  11025 #define READ_DDR34_PHY_BYTE_LANE_3_ODT_CONTROLr(_unit, _pc, _val) \
  11026         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_ODT_CONTROLr), (_val)) 
  11027 #define WRITE_DDR34_PHY_BYTE_LANE_3_ODT_CONTROLr(_unit, _pc, _val) \
  11028         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_ODT_CONTROLr), (_val))
  11029 #define MODIFY_DDR34_PHY_BYTE_LANE_3_ODT_CONTROLr(_unit, _pc, _val, _mask) \
  11030         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_ODT_CONTROLr), (_val), (_mask))
  11031 
  11032 #define READ_DDR34_PHY_BYTE_LANE_3_EDC_DPD_CONTROLr(_unit, _pc, _val) \
  11033         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_EDC_DPD_CONTROLr), (_val)) 
  11034 #define WRITE_DDR34_PHY_BYTE_LANE_3_EDC_DPD_CONTROLr(_unit, _pc, _val) \
  11035         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_EDC_DPD_CONTROLr), (_val))
  11036 #define MODIFY_DDR34_PHY_BYTE_LANE_3_EDC_DPD_CONTROLr(_unit, _pc, _val, _mask) \
  11037         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_EDC_DPD_CONTROLr), (_val), (_mask))
  11038 
  11039 #define READ_DDR34_PHY_BYTE_LANE_3_EDC_DPD_STATUSr(_unit, _pc, _val) \
  11040         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_EDC_DPD_STATUSr), (_val)) 
  11041 #define WRITE_DDR34_PHY_BYTE_LANE_3_EDC_DPD_STATUSr(_unit, _pc, _val) \
  11042         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_EDC_DPD_STATUSr), (_val))
  11043 #define MODIFY_DDR34_PHY_BYTE_LANE_3_EDC_DPD_STATUSr(_unit, _pc, _val, _mask) \
  11044         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_EDC_DPD_STATUSr), (_val), (_mask))
  11045 
  11046 #define READ_DDR34_PHY_BYTE_LANE_3_EDC_DPD_OUT_CONTROLr(_unit, _pc, _val) \
  11047         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_EDC_DPD_OUT_CONTROLr), (_val)) 
  11048 #define WRITE_DDR34_PHY_BYTE_LANE_3_EDC_DPD_OUT_CONTROLr(_unit, _pc, _val) \
  11049         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_EDC_DPD_OUT_CONTROLr), (_val))
  11050 #define MODIFY_DDR34_PHY_BYTE_LANE_3_EDC_DPD_OUT_CONTROLr(_unit, _pc, _val, _mask) \
  11051         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_EDC_DPD_OUT_CONTROLr), (_val), (_mask))
  11052 
  11053 #define READ_DDR34_PHY_BYTE_LANE_3_EDC_DPD_OUT_STATUSr(_unit, _pc, _val) \
  11054         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_EDC_DPD_OUT_STATUSr), (_val)) 
  11055 #define WRITE_DDR34_PHY_BYTE_LANE_3_EDC_DPD_OUT_STATUSr(_unit, _pc, _val) \
  11056         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_EDC_DPD_OUT_STATUSr), (_val))
  11057 #define MODIFY_DDR34_PHY_BYTE_LANE_3_EDC_DPD_OUT_STATUSr(_unit, _pc, _val, _mask) \
  11058         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_EDC_DPD_OUT_STATUSr), (_val), (_mask))
  11059 
  11060 #define READ_DDR34_PHY_BYTE_LANE_3_EDC_DPD_OUT_STATUS_CLEARr(_unit, _pc, _val) \
  11061         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_EDC_DPD_OUT_STATUS_CLEARr), (_val)) 
  11062 #define WRITE_DDR34_PHY_BYTE_LANE_3_EDC_DPD_OUT_STATUS_CLEARr(_unit, _pc, _val) \
  11063         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_EDC_DPD_OUT_STATUS_CLEARr), (_val))
  11064 #define MODIFY_DDR34_PHY_BYTE_LANE_3_EDC_DPD_OUT_STATUS_CLEARr(_unit, _pc, _val, _mask) \
  11065         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_EDC_DPD_OUT_STATUS_CLEARr), (_val), (_mask))
  11066 
  11067 #define READ_DDR34_PHY_BYTE_LANE_3_EDC_CRC_CONTROLr(_unit, _pc, _val) \
  11068         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_EDC_CRC_CONTROLr), (_val)) 
  11069 #define WRITE_DDR34_PHY_BYTE_LANE_3_EDC_CRC_CONTROLr(_unit, _pc, _val) \
  11070         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_EDC_CRC_CONTROLr), (_val))
  11071 #define MODIFY_DDR34_PHY_BYTE_LANE_3_EDC_CRC_CONTROLr(_unit, _pc, _val, _mask) \
  11072         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_EDC_CRC_CONTROLr), (_val), (_mask))
  11073 
  11074 #define READ_DDR34_PHY_BYTE_LANE_3_EDC_CRC_STATUSr(_unit, _pc, _val) \
  11075         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_EDC_CRC_STATUSr), (_val)) 
  11076 #define WRITE_DDR34_PHY_BYTE_LANE_3_EDC_CRC_STATUSr(_unit, _pc, _val) \
  11077         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_EDC_CRC_STATUSr), (_val))
  11078 #define MODIFY_DDR34_PHY_BYTE_LANE_3_EDC_CRC_STATUSr(_unit, _pc, _val, _mask) \
  11079         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_EDC_CRC_STATUSr), (_val), (_mask))
  11080 
  11081 #define READ_DDR34_PHY_BYTE_LANE_3_EDC_CRC_COUNTr(_unit, _pc, _val) \
  11082         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_EDC_CRC_COUNTr), (_val)) 
  11083 #define WRITE_DDR34_PHY_BYTE_LANE_3_EDC_CRC_COUNTr(_unit, _pc, _val) \
  11084         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_EDC_CRC_COUNTr), (_val))
  11085 #define MODIFY_DDR34_PHY_BYTE_LANE_3_EDC_CRC_COUNTr(_unit, _pc, _val, _mask) \
  11086         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_EDC_CRC_COUNTr), (_val), (_mask))
  11087 
  11088 #define READ_DDR34_PHY_BYTE_LANE_3_EDC_CRC_STATUS_CLEARr(_unit, _pc, _val) \
  11089         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_EDC_CRC_STATUS_CLEARr), (_val)) 
  11090 #define WRITE_DDR34_PHY_BYTE_LANE_3_EDC_CRC_STATUS_CLEARr(_unit, _pc, _val) \
  11091         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_EDC_CRC_STATUS_CLEARr), (_val))
  11092 #define MODIFY_DDR34_PHY_BYTE_LANE_3_EDC_CRC_STATUS_CLEARr(_unit, _pc, _val, _mask) \
  11093         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_EDC_CRC_STATUS_CLEARr), (_val), (_mask))
  11094 
  11095 #define READ_DDR34_PHY_BYTE_LANE_3_BL_SPARE_REGr(_unit, _pc, _val) \
  11096         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_BL_SPARE_REGr), (_val)) 
  11097 #define WRITE_DDR34_PHY_BYTE_LANE_3_BL_SPARE_REGr(_unit, _pc, _val) \
  11098         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_BL_SPARE_REGr), (_val))
  11099 #define MODIFY_DDR34_PHY_BYTE_LANE_3_BL_SPARE_REGr(_unit, _pc, _val, _mask) \
  11100         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_BL_SPARE_REGr), (_val), (_mask))
  11101 
  11102 
  11103 /****************************************************************************
  11104  */
  11105 /****************************************************************************
  11106  * DDR34_F0_PHY_CONTROL_REGS
  11107  */
  11108 #define READ_DDR34_PHY_CONTROL_REGS_DRIVE_PAD_CTL_2Tr(_unit, _pc, _val) \
  11109         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_DRIVE_PAD_CTL_2Tr), (_val)) 
  11110 #define WRITE_DDR34_PHY_CONTROL_REGS_DRIVE_PAD_CTL_2Tr(_unit, _pc, _val) \
  11111         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_DRIVE_PAD_CTL_2Tr), (_val))
  11112 #define MODIFY_DDR34_PHY_CONTROL_REGS_DRIVE_PAD_CTL_2Tr(_unit, _pc, _val, _mask) \
  11113         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_DRIVE_PAD_CTL_2Tr), (_val), (_mask))
  11114 
  11115 #define READ_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CKr(_unit, _pc, _val) \
  11116         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CKr), (_val)) 
  11117 #define WRITE_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CKr(_unit, _pc, _val) \
  11118         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CKr), (_val))
  11119 #define MODIFY_DDR34_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CKr(_unit, _pc, _val, _mask) \
  11120         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CKr), (_val), (_mask))
  11121 
  11122 #define READ_DDR34_PHY_CONTROL_REGS_CMD_CYC_DLYr(_unit, _pc, _val) \
  11123         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_CMD_CYC_DLYr), (_val)) 
  11124 #define WRITE_DDR34_PHY_CONTROL_REGS_CMD_CYC_DLYr(_unit, _pc, _val) \
  11125         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_CMD_CYC_DLYr), (_val))
  11126 #define MODIFY_DDR34_PHY_CONTROL_REGS_CMD_CYC_DLYr(_unit, _pc, _val, _mask) \
  11127         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_CMD_CYC_DLYr), (_val), (_mask))
  11128 
  11129 #define READ_DDR34_PHY_CONTROL_REGS_ALERT_DFIr(_unit, _pc, _val) \
  11130         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_ALERT_DFIr), (_val)) 
  11131 #define WRITE_DDR34_PHY_CONTROL_REGS_ALERT_DFIr(_unit, _pc, _val) \
  11132         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_ALERT_DFIr), (_val))
  11133 #define MODIFY_DDR34_PHY_CONTROL_REGS_ALERT_DFIr(_unit, _pc, _val, _mask) \
  11134         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_ALERT_DFIr), (_val), (_mask))
  11135 
  11136 #define READ_DDR34_PHY_CONTROL_REGS_PHYBIST_CA_MASKr(_unit, _pc, _val) \
  11137         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_PHYBIST_CA_MASKr), (_val)) 
  11138 #define WRITE_DDR34_PHY_CONTROL_REGS_PHYBIST_CA_MASKr(_unit, _pc, _val) \
  11139         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_PHYBIST_CA_MASKr), (_val))
  11140 #define MODIFY_DDR34_PHY_CONTROL_REGS_PHYBIST_CA_MASKr(_unit, _pc, _val, _mask) \
  11141         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_PHYBIST_CA_MASKr), (_val), (_mask))
  11142 
  11143 #define READ_DDR34_PHY_CONTROL_REGS_PHYBIST_DQ_MASK1r(_unit, _pc, _val) \
  11144         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_PHYBIST_DQ_MASK1r), (_val)) 
  11145 #define WRITE_DDR34_PHY_CONTROL_REGS_PHYBIST_DQ_MASK1r(_unit, _pc, _val) \
  11146         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_PHYBIST_DQ_MASK1r), (_val))
  11147 #define MODIFY_DDR34_PHY_CONTROL_REGS_PHYBIST_DQ_MASK1r(_unit, _pc, _val, _mask) \
  11148         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_PHYBIST_DQ_MASK1r), (_val), (_mask))
  11149 
  11150 #define READ_DDR34_PHY_CONTROL_REGS_PHYBIST_DQ_MASK2r(_unit, _pc, _val) \
  11151         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_PHYBIST_DQ_MASK2r), (_val)) 
  11152 #define WRITE_DDR34_PHY_CONTROL_REGS_PHYBIST_DQ_MASK2r(_unit, _pc, _val) \
  11153         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_PHYBIST_DQ_MASK2r), (_val))
  11154 #define MODIFY_DDR34_PHY_CONTROL_REGS_PHYBIST_DQ_MASK2r(_unit, _pc, _val, _mask) \
  11155         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_PHYBIST_DQ_MASK2r), (_val), (_mask))
  11156 
  11157 #define READ_DDR34_PHY_CONTROL_REGS_ZQ_CAL2r(_unit, _pc, _val) \
  11158         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_ZQ_CAL2r), (_val)) 
  11159 #define WRITE_DDR34_PHY_CONTROL_REGS_ZQ_CAL2r(_unit, _pc, _val) \
  11160         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_ZQ_CAL2r), (_val))
  11161 #define MODIFY_DDR34_PHY_CONTROL_REGS_ZQ_CAL2r(_unit, _pc, _val, _mask) \
  11162         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_ZQ_CAL2r), (_val), (_mask))
  11163 
  11164 #define READ_DDR34_PHY_CONTROL_REGS_RO_PROC_MON_CTLr(_unit, _pc, _val) \
  11165         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_RO_PROC_MON_CTLr), (_val)) 
  11166 #define WRITE_DDR34_PHY_CONTROL_REGS_RO_PROC_MON_CTLr(_unit, _pc, _val) \
  11167         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_RO_PROC_MON_CTLr), (_val))
  11168 #define MODIFY_DDR34_PHY_CONTROL_REGS_RO_PROC_MON_CTLr(_unit, _pc, _val, _mask) \
  11169         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_RO_PROC_MON_CTLr), (_val), (_mask))
  11170 
  11171 #define READ_DDR34_PHY_CONTROL_REGS_RO_PROC_MON_STATUSr(_unit, _pc, _val) \
  11172         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_RO_PROC_MON_STATUSr), (_val)) 
  11173 #define WRITE_DDR34_PHY_CONTROL_REGS_RO_PROC_MON_STATUSr(_unit, _pc, _val) \
  11174         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_RO_PROC_MON_STATUSr), (_val))
  11175 #define MODIFY_DDR34_PHY_CONTROL_REGS_RO_PROC_MON_STATUSr(_unit, _pc, _val, _mask) \
  11176         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_RO_PROC_MON_STATUSr), (_val), (_mask))
  11177 
  11178 #define READ_DDR34_PHY_CONTROL_REGS_CK_DRIVE_PAD_CTLr(_unit, _pc, _val) \
  11179         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_CK_DRIVE_PAD_CTLr), (_val)) 
  11180 #define WRITE_DDR34_PHY_CONTROL_REGS_CK_DRIVE_PAD_CTLr(_unit, _pc, _val) \
  11181         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_CK_DRIVE_PAD_CTLr), (_val))
  11182 #define MODIFY_DDR34_PHY_CONTROL_REGS_CK_DRIVE_PAD_CTLr(_unit, _pc, _val, _mask) \
  11183         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_CK_DRIVE_PAD_CTLr), (_val), (_mask))
  11184 
  11185 #define READ_DDR34_PHY_CONTROL_REGS_BYTE_LANE_ALIGN_MASKSr(_unit, _pc, _val) \
  11186         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_BYTE_LANE_ALIGN_MASKSr), (_val)) 
  11187 #define WRITE_DDR34_PHY_CONTROL_REGS_BYTE_LANE_ALIGN_MASKSr(_unit, _pc, _val) \
  11188         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_BYTE_LANE_ALIGN_MASKSr), (_val))
  11189 #define MODIFY_DDR34_PHY_CONTROL_REGS_BYTE_LANE_ALIGN_MASKSr(_unit, _pc, _val, _mask) \
  11190         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_BYTE_LANE_ALIGN_MASKSr), (_val), (_mask))
  11191 
  11192 #define READ_DDR34_PHY_CONTROL_REGS_CLOCK_IDLEr(_unit, _pc, _val) \
  11193         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_CLOCK_IDLEr), (_val)) 
  11194 #define WRITE_DDR34_PHY_CONTROL_REGS_CLOCK_IDLEr(_unit, _pc, _val) \
  11195         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_CLOCK_IDLEr), (_val))
  11196 #define MODIFY_DDR34_PHY_CONTROL_REGS_CLOCK_IDLEr(_unit, _pc, _val, _mask) \
  11197         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_CONTROL_REGS_CLOCK_IDLEr), (_val), (_mask))
  11198 
  11199 
  11200 /****************************************************************************
  11201  * DDR34_F0_PHY_BYTE_LANE_0
  11202  */
  11203 #define READ_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQSr(_unit, _pc, _val) \
  11204         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQSr), (_val)) 
  11205 #define WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQSr(_unit, _pc, _val) \
  11206         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQSr), (_val))
  11207 #define MODIFY_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQSr(_unit, _pc, _val, _mask) \
  11208         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQSr), (_val), (_mask))
  11209 
  11210 #define READ_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_ALERTr(_unit, _pc, _val) \
  11211         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_ALERTr), (_val)) 
  11212 #define WRITE_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_ALERTr(_unit, _pc, _val) \
  11213         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_ALERTr), (_val))
  11214 #define MODIFY_DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_ALERTr(_unit, _pc, _val, _mask) \
  11215         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_VDL_CONTROL_WR_ALERTr), (_val), (_mask))
  11216 
  11217 #define READ_DDR34_PHY_BYTE_LANE_0_DQSP_DRIVE_PAD_CTLr(_unit, _pc, _val) \
  11218         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_DQSP_DRIVE_PAD_CTLr), (_val)) 
  11219 #define WRITE_DDR34_PHY_BYTE_LANE_0_DQSP_DRIVE_PAD_CTLr(_unit, _pc, _val) \
  11220         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_DQSP_DRIVE_PAD_CTLr), (_val))
  11221 #define MODIFY_DDR34_PHY_BYTE_LANE_0_DQSP_DRIVE_PAD_CTLr(_unit, _pc, _val, _mask) \
  11222         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_DQSP_DRIVE_PAD_CTLr), (_val), (_mask))
  11223 
  11224 #define READ_DDR34_PHY_BYTE_LANE_0_DQSN_DRIVE_PAD_CTLr(_unit, _pc, _val) \
  11225         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_DQSN_DRIVE_PAD_CTLr), (_val)) 
  11226 #define WRITE_DDR34_PHY_BYTE_LANE_0_DQSN_DRIVE_PAD_CTLr(_unit, _pc, _val) \
  11227         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_DQSN_DRIVE_PAD_CTLr), (_val))
  11228 #define MODIFY_DDR34_PHY_BYTE_LANE_0_DQSN_DRIVE_PAD_CTLr(_unit, _pc, _val, _mask) \
  11229         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_DQSN_DRIVE_PAD_CTLr), (_val), (_mask))
  11230 
  11231 #define READ_DDR34_PHY_BYTE_LANE_0_ALERT_DRIVE_PAD_CTLr(_unit, _pc, _val) \
  11232         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_ALERT_DRIVE_PAD_CTLr), (_val)) 
  11233 #define WRITE_DDR34_PHY_BYTE_LANE_0_ALERT_DRIVE_PAD_CTLr(_unit, _pc, _val) \
  11234         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_ALERT_DRIVE_PAD_CTLr), (_val))
  11235 #define MODIFY_DDR34_PHY_BYTE_LANE_0_ALERT_DRIVE_PAD_CTLr(_unit, _pc, _val, _mask) \
  11236         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_ALERT_DRIVE_PAD_CTLr), (_val), (_mask))
  11237 
  11238 #define READ_DDR34_PHY_BYTE_LANE_0_CLOCK_ENABLEr(_unit, _pc, _val) \
  11239         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_CLOCK_ENABLEr), (_val)) 
  11240 #define WRITE_DDR34_PHY_BYTE_LANE_0_CLOCK_ENABLEr(_unit, _pc, _val) \
  11241         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_CLOCK_ENABLEr), (_val))
  11242 #define MODIFY_DDR34_PHY_BYTE_LANE_0_CLOCK_ENABLEr(_unit, _pc, _val, _mask) \
  11243         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_CLOCK_ENABLEr), (_val), (_mask))
  11244 
  11245 #define READ_DDR34_PHY_BYTE_LANE_0_CLOCK_IDLEr(_unit, _pc, _val) \
  11246         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_CLOCK_IDLEr), (_val)) 
  11247 #define WRITE_DDR34_PHY_BYTE_LANE_0_CLOCK_IDLEr(_unit, _pc, _val) \
  11248         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_CLOCK_IDLEr), (_val))
  11249 #define MODIFY_DDR34_PHY_BYTE_LANE_0_CLOCK_IDLEr(_unit, _pc, _val, _mask) \
  11250         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_0_CLOCK_IDLEr), (_val), (_mask))
  11251 
  11252 
  11253 /****************************************************************************
  11254  * DDR34_F0_PHY_BYTE_LANE_1
  11255  */
  11256 #define READ_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQSr(_unit, _pc, _val) \
  11257         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQSr), (_val)) 
  11258 #define WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQSr(_unit, _pc, _val) \
  11259         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQSr), (_val))
  11260 #define MODIFY_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQSr(_unit, _pc, _val, _mask) \
  11261         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQSr), (_val), (_mask))
  11262 
  11263 #define READ_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_ALERTr(_unit, _pc, _val) \
  11264         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_ALERTr), (_val)) 
  11265 #define WRITE_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_ALERTr(_unit, _pc, _val) \
  11266         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_ALERTr), (_val))
  11267 #define MODIFY_DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_ALERTr(_unit, _pc, _val, _mask) \
  11268         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_VDL_CONTROL_WR_ALERTr), (_val), (_mask))
  11269 
  11270 #define READ_DDR34_PHY_BYTE_LANE_1_DQSP_DRIVE_PAD_CTLr(_unit, _pc, _val) \
  11271         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_DQSP_DRIVE_PAD_CTLr), (_val)) 
  11272 #define WRITE_DDR34_PHY_BYTE_LANE_1_DQSP_DRIVE_PAD_CTLr(_unit, _pc, _val) \
  11273         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_DQSP_DRIVE_PAD_CTLr), (_val))
  11274 #define MODIFY_DDR34_PHY_BYTE_LANE_1_DQSP_DRIVE_PAD_CTLr(_unit, _pc, _val, _mask) \
  11275         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_DQSP_DRIVE_PAD_CTLr), (_val), (_mask))
  11276 
  11277 #define READ_DDR34_PHY_BYTE_LANE_1_DQSN_DRIVE_PAD_CTLr(_unit, _pc, _val) \
  11278         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_DQSN_DRIVE_PAD_CTLr), (_val)) 
  11279 #define WRITE_DDR34_PHY_BYTE_LANE_1_DQSN_DRIVE_PAD_CTLr(_unit, _pc, _val) \
  11280         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_DQSN_DRIVE_PAD_CTLr), (_val))
  11281 #define MODIFY_DDR34_PHY_BYTE_LANE_1_DQSN_DRIVE_PAD_CTLr(_unit, _pc, _val, _mask) \
  11282         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_DQSN_DRIVE_PAD_CTLr), (_val), (_mask))
  11283 
  11284 #define READ_DDR34_PHY_BYTE_LANE_1_ALERT_DRIVE_PAD_CTLr(_unit, _pc, _val) \
  11285         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_ALERT_DRIVE_PAD_CTLr), (_val)) 
  11286 #define WRITE_DDR34_PHY_BYTE_LANE_1_ALERT_DRIVE_PAD_CTLr(_unit, _pc, _val) \
  11287         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_ALERT_DRIVE_PAD_CTLr), (_val))
  11288 #define MODIFY_DDR34_PHY_BYTE_LANE_1_ALERT_DRIVE_PAD_CTLr(_unit, _pc, _val, _mask) \
  11289         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_ALERT_DRIVE_PAD_CTLr), (_val), (_mask))
  11290 
  11291 #define READ_DDR34_PHY_BYTE_LANE_1_CLOCK_ENABLEr(_unit, _pc, _val) \
  11292         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_CLOCK_ENABLEr), (_val)) 
  11293 #define WRITE_DDR34_PHY_BYTE_LANE_1_CLOCK_ENABLEr(_unit, _pc, _val) \
  11294         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_CLOCK_ENABLEr), (_val))
  11295 #define MODIFY_DDR34_PHY_BYTE_LANE_1_CLOCK_ENABLEr(_unit, _pc, _val, _mask) \
  11296         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_CLOCK_ENABLEr), (_val), (_mask))
  11297 
  11298 #define READ_DDR34_PHY_BYTE_LANE_1_CLOCK_IDLEr(_unit, _pc, _val) \
  11299         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_CLOCK_IDLEr), (_val)) 
  11300 #define WRITE_DDR34_PHY_BYTE_LANE_1_CLOCK_IDLEr(_unit, _pc, _val) \
  11301         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_CLOCK_IDLEr), (_val))
  11302 #define MODIFY_DDR34_PHY_BYTE_LANE_1_CLOCK_IDLEr(_unit, _pc, _val, _mask) \
  11303         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_1_CLOCK_IDLEr), (_val), (_mask))
  11304 
  11305 
  11306 /****************************************************************************
  11307  * DDR34_F0_PHY_BYTE_LANE_2
  11308  */
  11309 #define READ_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQSr(_unit, _pc, _val) \
  11310         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQSr), (_val)) 
  11311 #define WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQSr(_unit, _pc, _val) \
  11312         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQSr), (_val))
  11313 #define MODIFY_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQSr(_unit, _pc, _val, _mask) \
  11314         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQSr), (_val), (_mask))
  11315 
  11316 #define READ_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_ALERTr(_unit, _pc, _val) \
  11317         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_ALERTr), (_val)) 
  11318 #define WRITE_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_ALERTr(_unit, _pc, _val) \
  11319         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_ALERTr), (_val))
  11320 #define MODIFY_DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_ALERTr(_unit, _pc, _val, _mask) \
  11321         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_VDL_CONTROL_WR_ALERTr), (_val), (_mask))
  11322 
  11323 #define READ_DDR34_PHY_BYTE_LANE_2_DQSP_DRIVE_PAD_CTLr(_unit, _pc, _val) \
  11324         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_DQSP_DRIVE_PAD_CTLr), (_val)) 
  11325 #define WRITE_DDR34_PHY_BYTE_LANE_2_DQSP_DRIVE_PAD_CTLr(_unit, _pc, _val) \
  11326         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_DQSP_DRIVE_PAD_CTLr), (_val))
  11327 #define MODIFY_DDR34_PHY_BYTE_LANE_2_DQSP_DRIVE_PAD_CTLr(_unit, _pc, _val, _mask) \
  11328         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_DQSP_DRIVE_PAD_CTLr), (_val), (_mask))
  11329 
  11330 #define READ_DDR34_PHY_BYTE_LANE_2_DQSN_DRIVE_PAD_CTLr(_unit, _pc, _val) \
  11331         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_DQSN_DRIVE_PAD_CTLr), (_val)) 
  11332 #define WRITE_DDR34_PHY_BYTE_LANE_2_DQSN_DRIVE_PAD_CTLr(_unit, _pc, _val) \
  11333         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_DQSN_DRIVE_PAD_CTLr), (_val))
  11334 #define MODIFY_DDR34_PHY_BYTE_LANE_2_DQSN_DRIVE_PAD_CTLr(_unit, _pc, _val, _mask) \
  11335         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_DQSN_DRIVE_PAD_CTLr), (_val), (_mask))
  11336 
  11337 #define READ_DDR34_PHY_BYTE_LANE_2_ALERT_DRIVE_PAD_CTLr(_unit, _pc, _val) \
  11338         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_ALERT_DRIVE_PAD_CTLr), (_val)) 
  11339 #define WRITE_DDR34_PHY_BYTE_LANE_2_ALERT_DRIVE_PAD_CTLr(_unit, _pc, _val) \
  11340         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_ALERT_DRIVE_PAD_CTLr), (_val))
  11341 #define MODIFY_DDR34_PHY_BYTE_LANE_2_ALERT_DRIVE_PAD_CTLr(_unit, _pc, _val, _mask) \
  11342         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_ALERT_DRIVE_PAD_CTLr), (_val), (_mask))
  11343 
  11344 #define READ_DDR34_PHY_BYTE_LANE_2_CLOCK_ENABLEr(_unit, _pc, _val) \
  11345         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_CLOCK_ENABLEr), (_val)) 
  11346 #define WRITE_DDR34_PHY_BYTE_LANE_2_CLOCK_ENABLEr(_unit, _pc, _val) \
  11347         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_CLOCK_ENABLEr), (_val))
  11348 #define MODIFY_DDR34_PHY_BYTE_LANE_2_CLOCK_ENABLEr(_unit, _pc, _val, _mask) \
  11349         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_CLOCK_ENABLEr), (_val), (_mask))
  11350 
  11351 #define READ_DDR34_PHY_BYTE_LANE_2_CLOCK_IDLEr(_unit, _pc, _val) \
  11352         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_CLOCK_IDLEr), (_val)) 
  11353 #define WRITE_DDR34_PHY_BYTE_LANE_2_CLOCK_IDLEr(_unit, _pc, _val) \
  11354         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_CLOCK_IDLEr), (_val))
  11355 #define MODIFY_DDR34_PHY_BYTE_LANE_2_CLOCK_IDLEr(_unit, _pc, _val, _mask) \
  11356         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_2_CLOCK_IDLEr), (_val), (_mask))
  11357 
  11358 
  11359 /****************************************************************************
  11360  * DDR34_F0_PHY_BYTE_LANE_3
  11361  */
  11362 #define READ_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQSr(_unit, _pc, _val) \
  11363         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQSr), (_val)) 
  11364 #define WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQSr(_unit, _pc, _val) \
  11365         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQSr), (_val))
  11366 #define MODIFY_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQSr(_unit, _pc, _val, _mask) \
  11367         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQSr), (_val), (_mask))
  11368 
  11369 #define READ_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_ALERTr(_unit, _pc, _val) \
  11370         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_ALERTr), (_val)) 
  11371 #define WRITE_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_ALERTr(_unit, _pc, _val) \
  11372         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_ALERTr), (_val))
  11373 #define MODIFY_DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_ALERTr(_unit, _pc, _val, _mask) \
  11374         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_VDL_CONTROL_WR_ALERTr), (_val), (_mask))
  11375 
  11376 #define READ_DDR34_PHY_BYTE_LANE_3_DQSP_DRIVE_PAD_CTLr(_unit, _pc, _val) \
  11377         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_DQSP_DRIVE_PAD_CTLr), (_val)) 
  11378 #define WRITE_DDR34_PHY_BYTE_LANE_3_DQSP_DRIVE_PAD_CTLr(_unit, _pc, _val) \
  11379         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_DQSP_DRIVE_PAD_CTLr), (_val))
  11380 #define MODIFY_DDR34_PHY_BYTE_LANE_3_DQSP_DRIVE_PAD_CTLr(_unit, _pc, _val, _mask) \
  11381         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_DQSP_DRIVE_PAD_CTLr), (_val), (_mask))
  11382 
  11383 #define READ_DDR34_PHY_BYTE_LANE_3_DQSN_DRIVE_PAD_CTLr(_unit, _pc, _val) \
  11384         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_DQSN_DRIVE_PAD_CTLr), (_val)) 
  11385 #define WRITE_DDR34_PHY_BYTE_LANE_3_DQSN_DRIVE_PAD_CTLr(_unit, _pc, _val) \
  11386         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_DQSN_DRIVE_PAD_CTLr), (_val))
  11387 #define MODIFY_DDR34_PHY_BYTE_LANE_3_DQSN_DRIVE_PAD_CTLr(_unit, _pc, _val, _mask) \
  11388         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_DQSN_DRIVE_PAD_CTLr), (_val), (_mask))
  11389 
  11390 #define READ_DDR34_PHY_BYTE_LANE_3_ALERT_DRIVE_PAD_CTLr(_unit, _pc, _val) \
  11391         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_ALERT_DRIVE_PAD_CTLr), (_val)) 
  11392 #define WRITE_DDR34_PHY_BYTE_LANE_3_ALERT_DRIVE_PAD_CTLr(_unit, _pc, _val) \
  11393         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_ALERT_DRIVE_PAD_CTLr), (_val))
  11394 #define MODIFY_DDR34_PHY_BYTE_LANE_3_ALERT_DRIVE_PAD_CTLr(_unit, _pc, _val, _mask) \
  11395         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_ALERT_DRIVE_PAD_CTLr), (_val), (_mask))
  11396 
  11397 #define READ_DDR34_PHY_BYTE_LANE_3_CLOCK_ENABLEr(_unit, _pc, _val) \
  11398         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_CLOCK_ENABLEr), (_val)) 
  11399 #define WRITE_DDR34_PHY_BYTE_LANE_3_CLOCK_ENABLEr(_unit, _pc, _val) \
  11400         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_CLOCK_ENABLEr), (_val))
  11401 #define MODIFY_DDR34_PHY_BYTE_LANE_3_CLOCK_ENABLEr(_unit, _pc, _val, _mask) \
  11402         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_CLOCK_ENABLEr), (_val), (_mask))
  11403 
  11404 #define READ_DDR34_PHY_BYTE_LANE_3_CLOCK_IDLEr(_unit, _pc, _val) \
  11405         DDR34_REG_READ((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_CLOCK_IDLEr), (_val)) 
  11406 #define WRITE_DDR34_PHY_BYTE_LANE_3_CLOCK_IDLEr(_unit, _pc, _val) \
  11407         DDR34_REG_WRITE((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_CLOCK_IDLEr), (_val))
  11408 #define MODIFY_DDR34_PHY_BYTE_LANE_3_CLOCK_IDLEr(_unit, _pc, _val, _mask) \
  11409         DDR34_REG_MODIFY((_unit), (_pc), 0x00, DDR34_PHY_REGS_TABLE(DDR34_PHY_BYTE_LANE_3_CLOCK_IDLEr), (_val), (_mask))
  11410 
  11411 
  11412 #endif /* DDR34_H__ */
  11413