ddr23.h (161231B)
1 /*************************************************************************** 2 * 3 * 4 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 5 * 6 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 7 * 8 * $brcm_Workfile: $ 9 * $brcm_Revision: $ 10 * $brcm_Date: $ 11 * 12 * Module Description: 13 * DO NOT EDIT THIS FILE DIRECTLY 14 * 15 * This module was generated magically with RDB from a source description 16 * file. You must edit the source file for changes to be made to this file. 17 * 18 * 19 * Date: Generated on Wed Jan 21 14:22:25 2009 20 * MD5 Checksum f9d424ae6d1d678638d610ed40ca6807 21 * 22 * Compiled with: RDB Utility 5.0 23 * RDB Parser 3.0 24 * rdb2macro.pm 4.0 25 * Perl Interpreter 5.008008 26 * Operating System linux 27 * 28 * Spec Versions: DDR23_PHY_ADDR_CTL 1 29 * DDR23_PHY_BYTE_LANE 04 30 * 31 * RDB Files: /projects/ntsw-sw/home/zhongx/views/system_sim_ss_bringup/sdk/src/soc/phy/regs/ddr23/ddr23.rdb 32 * /projects/ntsw-sw/home/zhongx/views/system_sim_ss_bringup/sdk/src/soc/phy/regs/ddr23/ddr23_phy_addr_ctl.rdb 33 * /projects/ntsw-sw/home/zhongx/views/system_sim_ss_bringup/sdk/src/soc/phy/regs/ddr23/ddr23_phy_byte_lane.rdb 34 * 35 * Revision History: 36 * 37 * $brcm_Log: $ 38 */ 39 40 #ifndef DDR23_H__ 41 #define DDR23_H__ 42 43 /** 44 * m = memory, c = core, r = register, f = field, d = data. 45 */ 46 #if !defined(GET_FIELD) && !defined(SET_FIELD) 47 #define BRCM_ALIGN(c,r,f) c##_##r##_##f##_ALIGN 48 #define BRCM_BITS(c,r,f) c##_##r##_##f##_BITS 49 #define BRCM_MASK(c,r,f) c##_##r##_##f##_MASK 50 #define BRCM_SHIFT(c,r,f) c##_##r##_##f##_SHIFT 51 52 #define GET_FIELD(m,c,r,f) \ 53 ((((m) & BRCM_MASK(c,r,f)) >> BRCM_SHIFT(c,r,f)) << BRCM_ALIGN(c,r,f)) 54 55 #define SET_FIELD(m,c,r,f,d) \ 56 ((m) = (((m) & ~BRCM_MASK(c,r,f)) | ((((d) >> BRCM_ALIGN(c,r,f)) << \ 57 BRCM_SHIFT(c,r,f)) & BRCM_MASK(c,r,f))) \ 58 ) 59 60 #define SET_TYPE_FIELD(m,c,r,f,d) SET_FIELD(m,c,r,f,c##_##d) 61 #define SET_NAME_FIELD(m,c,r,f,d) SET_FIELD(m,c,r,f,c##_##r##_##f##_##d) 62 #define SET_VALUE_FIELD(m,c,r,f,d) SET_FIELD(m,c,r,f,d) 63 64 #endif /* GET & SET */ 65 66 /**************************************************************************** 67 * Core Enums. 68 */ 69 /**************************************************************************** 70 * DDR23_PHY_DDR23_PHY_ADDR_CTL 71 */ 72 73 /* Address & Control revision register */ 74 #define READ_DDR23_PHY_ADDR_CTL_REVISIONr(_unit, _pc, _val) \ 75 DDR23_REG_READ((_unit), (_pc), 0x00, 0x00000000, (_val)) 76 #define WRITE_DDR23_PHY_ADDR_CTL_REVISIONr(_unit, _pc, _val) \ 77 DDR23_REG_WRITE((_unit), (_pc), 0x00, 0x00000000, (_val)) 78 #define MODIFY_DDR23_PHY_ADDR_CTL_REVISIONr(_unit, _pc, _val, _mask) \ 79 DDR23_REG_MODIFY((_unit), (_pc), 0x00, 0x00000000, (_val), (_mask)) 80 81 /* PHY clock power management control register */ 82 #define READ_DDR23_PHY_ADDR_CTL_CLK_PM_CTRLr(_unit, _pc, _val) \ 83 DDR23_REG_READ((_unit), (_pc), 0x00, 0x00000004, (_val)) 84 #define WRITE_DDR23_PHY_ADDR_CTL_CLK_PM_CTRLr(_unit, _pc, _val) \ 85 DDR23_REG_WRITE((_unit), (_pc), 0x00, 0x00000004, (_val)) 86 #define MODIFY_DDR23_PHY_ADDR_CTL_CLK_PM_CTRLr(_unit, _pc, _val, _mask) \ 87 DDR23_REG_MODIFY((_unit), (_pc), 0x00, 0x00000004, (_val), (_mask)) 88 89 /* PHY PLL status register */ 90 #define READ_DDR23_PHY_ADDR_CTL_PLL_STATUSr(_unit, _pc, _val) \ 91 DDR23_REG_READ((_unit), (_pc), 0x00, 0x00000010, (_val)) 92 #define WRITE_DDR23_PHY_ADDR_CTL_PLL_STATUSr(_unit, _pc, _val) \ 93 DDR23_REG_WRITE((_unit), (_pc), 0x00, 0x00000010, (_val)) 94 #define MODIFY_DDR23_PHY_ADDR_CTL_PLL_STATUSr(_unit, _pc, _val, _mask) \ 95 DDR23_REG_MODIFY((_unit), (_pc), 0x00, 0x00000010, (_val), (_mask)) 96 97 /* PHY PLL configuration register */ 98 #define READ_DDR23_PHY_ADDR_CTL_PLL_CONFIGr(_unit, _pc, _val) \ 99 DDR23_REG_READ((_unit), (_pc), 0x00, 0x00000014, (_val)) 100 #define WRITE_DDR23_PHY_ADDR_CTL_PLL_CONFIGr(_unit, _pc, _val) \ 101 DDR23_REG_WRITE((_unit), (_pc), 0x00, 0x00000014, (_val)) 102 #define MODIFY_DDR23_PHY_ADDR_CTL_PLL_CONFIGr(_unit, _pc, _val, _mask) \ 103 DDR23_REG_MODIFY((_unit), (_pc), 0x00, 0x00000014, (_val), (_mask)) 104 105 /* PHY PLL pre-divider control register */ 106 #define READ_DDR23_PHY_ADDR_CTL_PLL_PRE_DIVIDERr(_unit, _pc, _val) \ 107 DDR23_REG_READ((_unit), (_pc), 0x00, 0x00000018, (_val)) 108 #define WRITE_DDR23_PHY_ADDR_CTL_PLL_PRE_DIVIDERr(_unit, _pc, _val) \ 109 DDR23_REG_WRITE((_unit), (_pc), 0x00, 0x00000018, (_val)) 110 #define MODIFY_DDR23_PHY_ADDR_CTL_PLL_PRE_DIVIDERr(_unit, _pc, _val, _mask) \ 111 DDR23_REG_MODIFY((_unit), (_pc), 0x00, 0x00000018, (_val), (_mask)) 112 113 /* PHY PLL divider control register */ 114 #define READ_DDR23_PHY_ADDR_CTL_PLL_DIVIDERr(_unit, _pc, _val) \ 115 DDR23_REG_READ((_unit), (_pc), 0x00, 0x0000001c, (_val)) 116 #define WRITE_DDR23_PHY_ADDR_CTL_PLL_DIVIDERr(_unit, _pc, _val) \ 117 DDR23_REG_WRITE((_unit), (_pc), 0x00, 0x0000001c, (_val)) 118 #define MODIFY_DDR23_PHY_ADDR_CTL_PLL_DIVIDERr(_unit, _pc, _val, _mask) \ 119 DDR23_REG_MODIFY((_unit), (_pc), 0x00, 0x0000001c, (_val), (_mask)) 120 121 /* PHY PLL analog control register #1 */ 122 #define READ_DDR23_PHY_ADDR_CTL_PLL_CONTROL1r(_unit, _pc, _val) \ 123 DDR23_REG_READ((_unit), (_pc), 0x00, 0x00000020, (_val)) 124 #define WRITE_DDR23_PHY_ADDR_CTL_PLL_CONTROL1r(_unit, _pc, _val) \ 125 DDR23_REG_WRITE((_unit), (_pc), 0x00, 0x00000020, (_val)) 126 #define MODIFY_DDR23_PHY_ADDR_CTL_PLL_CONTROL1r(_unit, _pc, _val, _mask) \ 127 DDR23_REG_MODIFY((_unit), (_pc), 0x00, 0x00000020, (_val), (_mask)) 128 129 /* PHY PLL analog control register #2 */ 130 #define READ_DDR23_PHY_ADDR_CTL_PLL_CONTROL2r(_unit, _pc, _val) \ 131 DDR23_REG_READ((_unit), (_pc), 0x00, 0x00000024, (_val)) 132 #define WRITE_DDR23_PHY_ADDR_CTL_PLL_CONTROL2r(_unit, _pc, _val) \ 133 DDR23_REG_WRITE((_unit), (_pc), 0x00, 0x00000024, (_val)) 134 #define MODIFY_DDR23_PHY_ADDR_CTL_PLL_CONTROL2r(_unit, _pc, _val, _mask) \ 135 DDR23_REG_MODIFY((_unit), (_pc), 0x00, 0x00000024, (_val), (_mask)) 136 137 /* PHY PLL spread spectrum config register */ 138 #define READ_DDR23_PHY_ADDR_CTL_PLL_SS_ENr(_unit, _pc, _val) \ 139 DDR23_REG_READ((_unit), (_pc), 0x00, 0x00000028, (_val)) 140 #define WRITE_DDR23_PHY_ADDR_CTL_PLL_SS_ENr(_unit, _pc, _val) \ 141 DDR23_REG_WRITE((_unit), (_pc), 0x00, 0x00000028, (_val)) 142 #define MODIFY_DDR23_PHY_ADDR_CTL_PLL_SS_ENr(_unit, _pc, _val, _mask) \ 143 DDR23_REG_MODIFY((_unit), (_pc), 0x00, 0x00000028, (_val), (_mask)) 144 145 /* PHY PLL spread spectrum config register */ 146 #define READ_DDR23_PHY_ADDR_CTL_PLL_SS_CFGr(_unit, _pc, _val) \ 147 DDR23_REG_READ((_unit), (_pc), 0x00, 0x0000002c, (_val)) 148 #define WRITE_DDR23_PHY_ADDR_CTL_PLL_SS_CFGr(_unit, _pc, _val) \ 149 DDR23_REG_WRITE((_unit), (_pc), 0x00, 0x0000002c, (_val)) 150 #define MODIFY_DDR23_PHY_ADDR_CTL_PLL_SS_CFGr(_unit, _pc, _val, _mask) \ 151 DDR23_REG_MODIFY((_unit), (_pc), 0x00, 0x0000002c, (_val), (_mask)) 152 153 /* Address & Control VDL static override control register */ 154 #define READ_DDR23_PHY_ADDR_CTL_STATIC_VDL_OVERRIDEr(_unit, _pc, _val) \ 155 DDR23_REG_READ((_unit), (_pc), 0x00, 0x00000030, (_val)) 156 #define WRITE_DDR23_PHY_ADDR_CTL_STATIC_VDL_OVERRIDEr(_unit, _pc, _val) \ 157 DDR23_REG_WRITE((_unit), (_pc), 0x00, 0x00000030, (_val)) 158 #define MODIFY_DDR23_PHY_ADDR_CTL_STATIC_VDL_OVERRIDEr(_unit, _pc, _val, _mask) \ 159 DDR23_REG_MODIFY((_unit), (_pc), 0x00, 0x00000030, (_val), (_mask)) 160 161 /* Address & Control VDL dynamic override control register */ 162 #define READ_DDR23_PHY_ADDR_CTL_DYNAMIC_VDL_OVERRIDEr(_unit, _pc, _val) \ 163 DDR23_REG_READ((_unit), (_pc), 0x00, 0x00000034, (_val)) 164 #define WRITE_DDR23_PHY_ADDR_CTL_DYNAMIC_VDL_OVERRIDEr(_unit, _pc, _val) \ 165 DDR23_REG_WRITE((_unit), (_pc), 0x00, 0x00000034, (_val)) 166 #define MODIFY_DDR23_PHY_ADDR_CTL_DYNAMIC_VDL_OVERRIDEr(_unit, _pc, _val, _mask) \ 167 DDR23_REG_MODIFY((_unit), (_pc), 0x00, 0x00000034, (_val), (_mask)) 168 169 /* Idle mode SSTL pad control register */ 170 #define READ_DDR23_PHY_ADDR_CTL_IDLE_PAD_CONTROLr(_unit, _pc, _val) \ 171 DDR23_REG_READ((_unit), (_pc), 0x00, 0x00000038, (_val)) 172 #define WRITE_DDR23_PHY_ADDR_CTL_IDLE_PAD_CONTROLr(_unit, _pc, _val) \ 173 DDR23_REG_WRITE((_unit), (_pc), 0x00, 0x00000038, (_val)) 174 #define MODIFY_DDR23_PHY_ADDR_CTL_IDLE_PAD_CONTROLr(_unit, _pc, _val, _mask) \ 175 DDR23_REG_MODIFY((_unit), (_pc), 0x00, 0x00000038, (_val), (_mask)) 176 177 /* PVT Compensation control and status register */ 178 #define READ_DDR23_PHY_ADDR_CTL_ZQ_PVT_COMP_CTLr(_unit, _pc, _val) \ 179 DDR23_REG_READ((_unit), (_pc), 0x00, 0x0000003c, (_val)) 180 #define WRITE_DDR23_PHY_ADDR_CTL_ZQ_PVT_COMP_CTLr(_unit, _pc, _val) \ 181 DDR23_REG_WRITE((_unit), (_pc), 0x00, 0x0000003c, (_val)) 182 #define MODIFY_DDR23_PHY_ADDR_CTL_ZQ_PVT_COMP_CTLr(_unit, _pc, _val, _mask) \ 183 DDR23_REG_MODIFY((_unit), (_pc), 0x00, 0x0000003c, (_val), (_mask)) 184 185 /* SSTL pad drive characteristics control register */ 186 #define READ_DDR23_PHY_ADDR_CTL_DRIVE_PAD_CTLr(_unit, _pc, _val) \ 187 DDR23_REG_READ((_unit), (_pc), 0x00, 0x00000040, (_val)) 188 #define WRITE_DDR23_PHY_ADDR_CTL_DRIVE_PAD_CTLr(_unit, _pc, _val) \ 189 DDR23_REG_WRITE((_unit), (_pc), 0x00, 0x00000040, (_val)) 190 #define MODIFY_DDR23_PHY_ADDR_CTL_DRIVE_PAD_CTLr(_unit, _pc, _val, _mask) \ 191 DDR23_REG_MODIFY((_unit), (_pc), 0x00, 0x00000040, (_val), (_mask)) 192 193 /* Clock Regulator control register */ 194 #define READ_DDR23_PHY_ADDR_CTL_CLOCK_REG_CONTROLr(_unit, _pc, _val) \ 195 DDR23_REG_READ((_unit), (_pc), 0x00, 0x00000044, (_val)) 196 #define WRITE_DDR23_PHY_ADDR_CTL_CLOCK_REG_CONTROLr(_unit, _pc, _val) \ 197 DDR23_REG_WRITE((_unit), (_pc), 0x00, 0x00000044, (_val)) 198 #define MODIFY_DDR23_PHY_ADDR_CTL_CLOCK_REG_CONTROLr(_unit, _pc, _val, _mask) \ 199 DDR23_REG_MODIFY((_unit), (_pc), 0x00, 0x00000044, (_val), (_mask)) 200 201 202 /**************************************************************************** 203 * DDR23_PHY_DDR23_PHY_BYTE_LANE0 204 */ 205 206 /* Byte lane revision register */ 207 #define READ_DDR23_PHY_BYTE_LANE0_REVISIONr(_unit, _pc, _val) \ 208 DDR23_REG_READ((_unit), (_pc), 0x00, 0x00000100, (_val)) 209 #define WRITE_DDR23_PHY_BYTE_LANE0_REVISIONr(_unit, _pc, _val) \ 210 DDR23_REG_WRITE((_unit), (_pc), 0x00, 0x00000100, (_val)) 211 #define MODIFY_DDR23_PHY_BYTE_LANE0_REVISIONr(_unit, _pc, _val, _mask) \ 212 DDR23_REG_MODIFY((_unit), (_pc), 0x00, 0x00000100, (_val), (_mask)) 213 214 /* Byte lane VDL calibration control register */ 215 #define READ_DDR23_PHY_BYTE_LANE0_VDL_CALIBRATEr(_unit, _pc, _val) \ 216 DDR23_REG_READ((_unit), (_pc), 0x00, 0x00000104, (_val)) 217 #define WRITE_DDR23_PHY_BYTE_LANE0_VDL_CALIBRATEr(_unit, _pc, _val) \ 218 DDR23_REG_WRITE((_unit), (_pc), 0x00, 0x00000104, (_val)) 219 #define MODIFY_DDR23_PHY_BYTE_LANE0_VDL_CALIBRATEr(_unit, _pc, _val, _mask) \ 220 DDR23_REG_MODIFY((_unit), (_pc), 0x00, 0x00000104, (_val), (_mask)) 221 222 /* Byte lane VDL calibration status register */ 223 #define READ_DDR23_PHY_BYTE_LANE0_VDL_STATUSr(_unit, _pc, _val) \ 224 DDR23_REG_READ((_unit), (_pc), 0x00, 0x00000108, (_val)) 225 #define WRITE_DDR23_PHY_BYTE_LANE0_VDL_STATUSr(_unit, _pc, _val) \ 226 DDR23_REG_WRITE((_unit), (_pc), 0x00, 0x00000108, (_val)) 227 #define MODIFY_DDR23_PHY_BYTE_LANE0_VDL_STATUSr(_unit, _pc, _val, _mask) \ 228 DDR23_REG_MODIFY((_unit), (_pc), 0x00, 0x00000108, (_val), (_mask)) 229 230 /* Read DQSP VDL static override control register */ 231 #define READ_DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_0r(_unit, _pc, _val) \ 232 DDR23_REG_READ((_unit), (_pc), 0x00, 0x00000110, (_val)) 233 #define WRITE_DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_0r(_unit, _pc, _val) \ 234 DDR23_REG_WRITE((_unit), (_pc), 0x00, 0x00000110, (_val)) 235 #define MODIFY_DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_0r(_unit, _pc, _val, _mask) \ 236 DDR23_REG_MODIFY((_unit), (_pc), 0x00, 0x00000110, (_val), (_mask)) 237 238 /* Read DQSN VDL static override control register */ 239 #define READ_DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_1r(_unit, _pc, _val) \ 240 DDR23_REG_READ((_unit), (_pc), 0x00, 0x00000114, (_val)) 241 #define WRITE_DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_1r(_unit, _pc, _val) \ 242 DDR23_REG_WRITE((_unit), (_pc), 0x00, 0x00000114, (_val)) 243 #define MODIFY_DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_1r(_unit, _pc, _val, _mask) \ 244 DDR23_REG_MODIFY((_unit), (_pc), 0x00, 0x00000114, (_val), (_mask)) 245 246 /* Read Enable VDL static override control register */ 247 #define READ_DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_2r(_unit, _pc, _val) \ 248 DDR23_REG_READ((_unit), (_pc), 0x00, 0x00000118, (_val)) 249 #define WRITE_DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_2r(_unit, _pc, _val) \ 250 DDR23_REG_WRITE((_unit), (_pc), 0x00, 0x00000118, (_val)) 251 #define MODIFY_DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_2r(_unit, _pc, _val, _mask) \ 252 DDR23_REG_MODIFY((_unit), (_pc), 0x00, 0x00000118, (_val), (_mask)) 253 254 /* Write data and mask VDL static override control register */ 255 #define READ_DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_3r(_unit, _pc, _val) \ 256 DDR23_REG_READ((_unit), (_pc), 0x00, 0x0000011c, (_val)) 257 #define WRITE_DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_3r(_unit, _pc, _val) \ 258 DDR23_REG_WRITE((_unit), (_pc), 0x00, 0x0000011c, (_val)) 259 #define MODIFY_DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_3r(_unit, _pc, _val, _mask) \ 260 DDR23_REG_MODIFY((_unit), (_pc), 0x00, 0x0000011c, (_val), (_mask)) 261 262 /* Read DQSP VDL dynamic override control register */ 263 #define READ_DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_4r(_unit, _pc, _val) \ 264 DDR23_REG_READ((_unit), (_pc), 0x00, 0x00000120, (_val)) 265 #define WRITE_DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_4r(_unit, _pc, _val) \ 266 DDR23_REG_WRITE((_unit), (_pc), 0x00, 0x00000120, (_val)) 267 #define MODIFY_DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_4r(_unit, _pc, _val, _mask) \ 268 DDR23_REG_MODIFY((_unit), (_pc), 0x00, 0x00000120, (_val), (_mask)) 269 270 /* Read DQSN VDL dynamic override control register */ 271 #define READ_DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_5r(_unit, _pc, _val) \ 272 DDR23_REG_READ((_unit), (_pc), 0x00, 0x00000124, (_val)) 273 #define WRITE_DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_5r(_unit, _pc, _val) \ 274 DDR23_REG_WRITE((_unit), (_pc), 0x00, 0x00000124, (_val)) 275 #define MODIFY_DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_5r(_unit, _pc, _val, _mask) \ 276 DDR23_REG_MODIFY((_unit), (_pc), 0x00, 0x00000124, (_val), (_mask)) 277 278 /* Read Enable VDL dynamic override control register */ 279 #define READ_DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_6r(_unit, _pc, _val) \ 280 DDR23_REG_READ((_unit), (_pc), 0x00, 0x00000128, (_val)) 281 #define WRITE_DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_6r(_unit, _pc, _val) \ 282 DDR23_REG_WRITE((_unit), (_pc), 0x00, 0x00000128, (_val)) 283 #define MODIFY_DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_6r(_unit, _pc, _val, _mask) \ 284 DDR23_REG_MODIFY((_unit), (_pc), 0x00, 0x00000128, (_val), (_mask)) 285 286 /* Write data and mask VDL dynamic override control register */ 287 #define READ_DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_7r(_unit, _pc, _val) \ 288 DDR23_REG_READ((_unit), (_pc), 0x00, 0x0000012c, (_val)) 289 #define WRITE_DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_7r(_unit, _pc, _val) \ 290 DDR23_REG_WRITE((_unit), (_pc), 0x00, 0x0000012c, (_val)) 291 #define MODIFY_DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_7r(_unit, _pc, _val, _mask) \ 292 DDR23_REG_MODIFY((_unit), (_pc), 0x00, 0x0000012c, (_val), (_mask)) 293 294 /* Byte Lane read channel control register */ 295 #define READ_DDR23_PHY_BYTE_LANE0_READ_CONTROLr(_unit, _pc, _val) \ 296 DDR23_REG_READ((_unit), (_pc), 0x00, 0x00000130, (_val)) 297 #define WRITE_DDR23_PHY_BYTE_LANE0_READ_CONTROLr(_unit, _pc, _val) \ 298 DDR23_REG_WRITE((_unit), (_pc), 0x00, 0x00000130, (_val)) 299 #define MODIFY_DDR23_PHY_BYTE_LANE0_READ_CONTROLr(_unit, _pc, _val, _mask) \ 300 DDR23_REG_MODIFY((_unit), (_pc), 0x00, 0x00000130, (_val), (_mask)) 301 302 /* Read fifo status register */ 303 #define READ_DDR23_PHY_BYTE_LANE0_READ_FIFO_STATUSr(_unit, _pc, _val) \ 304 DDR23_REG_READ((_unit), (_pc), 0x00, 0x00000134, (_val)) 305 #define WRITE_DDR23_PHY_BYTE_LANE0_READ_FIFO_STATUSr(_unit, _pc, _val) \ 306 DDR23_REG_WRITE((_unit), (_pc), 0x00, 0x00000134, (_val)) 307 #define MODIFY_DDR23_PHY_BYTE_LANE0_READ_FIFO_STATUSr(_unit, _pc, _val, _mask) \ 308 DDR23_REG_MODIFY((_unit), (_pc), 0x00, 0x00000134, (_val), (_mask)) 309 310 /* Read fifo status clear register */ 311 #define READ_DDR23_PHY_BYTE_LANE0_READ_FIFO_CLEARr(_unit, _pc, _val) \ 312 DDR23_REG_READ((_unit), (_pc), 0x00, 0x00000138, (_val)) 313 #define WRITE_DDR23_PHY_BYTE_LANE0_READ_FIFO_CLEARr(_unit, _pc, _val) \ 314 DDR23_REG_WRITE((_unit), (_pc), 0x00, 0x00000138, (_val)) 315 #define MODIFY_DDR23_PHY_BYTE_LANE0_READ_FIFO_CLEARr(_unit, _pc, _val, _mask) \ 316 DDR23_REG_MODIFY((_unit), (_pc), 0x00, 0x00000138, (_val), (_mask)) 317 318 /* Idle mode SSTL pad control register */ 319 #define READ_DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROLr(_unit, _pc, _val) \ 320 DDR23_REG_READ((_unit), (_pc), 0x00, 0x0000013c, (_val)) 321 #define WRITE_DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROLr(_unit, _pc, _val) \ 322 DDR23_REG_WRITE((_unit), (_pc), 0x00, 0x0000013c, (_val)) 323 #define MODIFY_DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROLr(_unit, _pc, _val, _mask) \ 324 DDR23_REG_MODIFY((_unit), (_pc), 0x00, 0x0000013c, (_val), (_mask)) 325 326 /* SSTL pad drive characteristics control register */ 327 #define READ_DDR23_PHY_BYTE_LANE0_DRIVE_PAD_CTLr(_unit, _pc, _val) \ 328 DDR23_REG_READ((_unit), (_pc), 0x00, 0x00000140, (_val)) 329 #define WRITE_DDR23_PHY_BYTE_LANE0_DRIVE_PAD_CTLr(_unit, _pc, _val) \ 330 DDR23_REG_WRITE((_unit), (_pc), 0x00, 0x00000140, (_val)) 331 #define MODIFY_DDR23_PHY_BYTE_LANE0_DRIVE_PAD_CTLr(_unit, _pc, _val, _mask) \ 332 DDR23_REG_MODIFY((_unit), (_pc), 0x00, 0x00000140, (_val), (_mask)) 333 334 /* Clock pad disable register */ 335 #define READ_DDR23_PHY_BYTE_LANE0_CLOCK_PAD_DISABLEr(_unit, _pc, _val) \ 336 DDR23_REG_READ((_unit), (_pc), 0x00, 0x00000144, (_val)) 337 #define WRITE_DDR23_PHY_BYTE_LANE0_CLOCK_PAD_DISABLEr(_unit, _pc, _val) \ 338 DDR23_REG_WRITE((_unit), (_pc), 0x00, 0x00000144, (_val)) 339 #define MODIFY_DDR23_PHY_BYTE_LANE0_CLOCK_PAD_DISABLEr(_unit, _pc, _val, _mask) \ 340 DDR23_REG_MODIFY((_unit), (_pc), 0x00, 0x00000144, (_val), (_mask)) 341 342 /* Write cycle preamble control register */ 343 #define READ_DDR23_PHY_BYTE_LANE0_WR_PREAMBLE_MODEr(_unit, _pc, _val) \ 344 DDR23_REG_READ((_unit), (_pc), 0x00, 0x00000148, (_val)) 345 #define WRITE_DDR23_PHY_BYTE_LANE0_WR_PREAMBLE_MODEr(_unit, _pc, _val) \ 346 DDR23_REG_WRITE((_unit), (_pc), 0x00, 0x00000148, (_val)) 347 #define MODIFY_DDR23_PHY_BYTE_LANE0_WR_PREAMBLE_MODEr(_unit, _pc, _val, _mask) \ 348 DDR23_REG_MODIFY((_unit), (_pc), 0x00, 0x00000148, (_val), (_mask)) 349 350 /* Clock Regulator control register */ 351 #define READ_DDR23_PHY_BYTE_LANE0_CLOCK_REG_CONTROLr(_unit, _pc, _val) \ 352 DDR23_REG_READ((_unit), (_pc), 0x00, 0x0000014c, (_val)) 353 #define WRITE_DDR23_PHY_BYTE_LANE0_CLOCK_REG_CONTROLr(_unit, _pc, _val) \ 354 DDR23_REG_WRITE((_unit), (_pc), 0x00, 0x0000014c, (_val)) 355 #define MODIFY_DDR23_PHY_BYTE_LANE0_CLOCK_REG_CONTROLr(_unit, _pc, _val, _mask) \ 356 DDR23_REG_MODIFY((_unit), (_pc), 0x00, 0x0000014c, (_val), (_mask)) 357 358 359 /**************************************************************************** 360 * DDR23_PHY_DDR23_PHY_BYTE_LANE1 361 */ 362 363 /* Byte lane revision register */ 364 #define READ_DDR23_PHY_BYTE_LANE1_REVISIONr(_unit, _pc, _val) \ 365 DDR23_REG_READ((_unit), (_pc), 0x00, 0x00000200, (_val)) 366 #define WRITE_DDR23_PHY_BYTE_LANE1_REVISIONr(_unit, _pc, _val) \ 367 DDR23_REG_WRITE((_unit), (_pc), 0x00, 0x00000200, (_val)) 368 #define MODIFY_DDR23_PHY_BYTE_LANE1_REVISIONr(_unit, _pc, _val, _mask) \ 369 DDR23_REG_MODIFY((_unit), (_pc), 0x00, 0x00000200, (_val), (_mask)) 370 371 /* Byte lane VDL calibration control register */ 372 #define READ_DDR23_PHY_BYTE_LANE1_VDL_CALIBRATEr(_unit, _pc, _val) \ 373 DDR23_REG_READ((_unit), (_pc), 0x00, 0x00000204, (_val)) 374 #define WRITE_DDR23_PHY_BYTE_LANE1_VDL_CALIBRATEr(_unit, _pc, _val) \ 375 DDR23_REG_WRITE((_unit), (_pc), 0x00, 0x00000204, (_val)) 376 #define MODIFY_DDR23_PHY_BYTE_LANE1_VDL_CALIBRATEr(_unit, _pc, _val, _mask) \ 377 DDR23_REG_MODIFY((_unit), (_pc), 0x00, 0x00000204, (_val), (_mask)) 378 379 /* Byte lane VDL calibration status register */ 380 #define READ_DDR23_PHY_BYTE_LANE1_VDL_STATUSr(_unit, _pc, _val) \ 381 DDR23_REG_READ((_unit), (_pc), 0x00, 0x00000208, (_val)) 382 #define WRITE_DDR23_PHY_BYTE_LANE1_VDL_STATUSr(_unit, _pc, _val) \ 383 DDR23_REG_WRITE((_unit), (_pc), 0x00, 0x00000208, (_val)) 384 #define MODIFY_DDR23_PHY_BYTE_LANE1_VDL_STATUSr(_unit, _pc, _val, _mask) \ 385 DDR23_REG_MODIFY((_unit), (_pc), 0x00, 0x00000208, (_val), (_mask)) 386 387 /* Read DQSP VDL static override control register */ 388 #define READ_DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_0r(_unit, _pc, _val) \ 389 DDR23_REG_READ((_unit), (_pc), 0x00, 0x00000210, (_val)) 390 #define WRITE_DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_0r(_unit, _pc, _val) \ 391 DDR23_REG_WRITE((_unit), (_pc), 0x00, 0x00000210, (_val)) 392 #define MODIFY_DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_0r(_unit, _pc, _val, _mask) \ 393 DDR23_REG_MODIFY((_unit), (_pc), 0x00, 0x00000210, (_val), (_mask)) 394 395 /* Read DQSN VDL static override control register */ 396 #define READ_DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_1r(_unit, _pc, _val) \ 397 DDR23_REG_READ((_unit), (_pc), 0x00, 0x00000214, (_val)) 398 #define WRITE_DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_1r(_unit, _pc, _val) \ 399 DDR23_REG_WRITE((_unit), (_pc), 0x00, 0x00000214, (_val)) 400 #define MODIFY_DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_1r(_unit, _pc, _val, _mask) \ 401 DDR23_REG_MODIFY((_unit), (_pc), 0x00, 0x00000214, (_val), (_mask)) 402 403 /* Read Enable VDL static override control register */ 404 #define READ_DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_2r(_unit, _pc, _val) \ 405 DDR23_REG_READ((_unit), (_pc), 0x00, 0x00000218, (_val)) 406 #define WRITE_DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_2r(_unit, _pc, _val) \ 407 DDR23_REG_WRITE((_unit), (_pc), 0x00, 0x00000218, (_val)) 408 #define MODIFY_DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_2r(_unit, _pc, _val, _mask) \ 409 DDR23_REG_MODIFY((_unit), (_pc), 0x00, 0x00000218, (_val), (_mask)) 410 411 /* Write data and mask VDL static override control register */ 412 #define READ_DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_3r(_unit, _pc, _val) \ 413 DDR23_REG_READ((_unit), (_pc), 0x00, 0x0000021c, (_val)) 414 #define WRITE_DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_3r(_unit, _pc, _val) \ 415 DDR23_REG_WRITE((_unit), (_pc), 0x00, 0x0000021c, (_val)) 416 #define MODIFY_DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_3r(_unit, _pc, _val, _mask) \ 417 DDR23_REG_MODIFY((_unit), (_pc), 0x00, 0x0000021c, (_val), (_mask)) 418 419 /* Read DQSP VDL dynamic override control register */ 420 #define READ_DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_4r(_unit, _pc, _val) \ 421 DDR23_REG_READ((_unit), (_pc), 0x00, 0x00000220, (_val)) 422 #define WRITE_DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_4r(_unit, _pc, _val) \ 423 DDR23_REG_WRITE((_unit), (_pc), 0x00, 0x00000220, (_val)) 424 #define MODIFY_DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_4r(_unit, _pc, _val, _mask) \ 425 DDR23_REG_MODIFY((_unit), (_pc), 0x00, 0x00000220, (_val), (_mask)) 426 427 /* Read DQSN VDL dynamic override control register */ 428 #define READ_DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_5r(_unit, _pc, _val) \ 429 DDR23_REG_READ((_unit), (_pc), 0x00, 0x00000224, (_val)) 430 #define WRITE_DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_5r(_unit, _pc, _val) \ 431 DDR23_REG_WRITE((_unit), (_pc), 0x00, 0x00000224, (_val)) 432 #define MODIFY_DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_5r(_unit, _pc, _val, _mask) \ 433 DDR23_REG_MODIFY((_unit), (_pc), 0x00, 0x00000224, (_val), (_mask)) 434 435 /* Read Enable VDL dynamic override control register */ 436 #define READ_DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_6r(_unit, _pc, _val) \ 437 DDR23_REG_READ((_unit), (_pc), 0x00, 0x00000228, (_val)) 438 #define WRITE_DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_6r(_unit, _pc, _val) \ 439 DDR23_REG_WRITE((_unit), (_pc), 0x00, 0x00000228, (_val)) 440 #define MODIFY_DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_6r(_unit, _pc, _val, _mask) \ 441 DDR23_REG_MODIFY((_unit), (_pc), 0x00, 0x00000228, (_val), (_mask)) 442 443 /* Write data and mask VDL dynamic override control register */ 444 #define READ_DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_7r(_unit, _pc, _val) \ 445 DDR23_REG_READ((_unit), (_pc), 0x00, 0x0000022c, (_val)) 446 #define WRITE_DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_7r(_unit, _pc, _val) \ 447 DDR23_REG_WRITE((_unit), (_pc), 0x00, 0x0000022c, (_val)) 448 #define MODIFY_DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_7r(_unit, _pc, _val, _mask) \ 449 DDR23_REG_MODIFY((_unit), (_pc), 0x00, 0x0000022c, (_val), (_mask)) 450 451 /* Byte Lane read channel control register */ 452 #define READ_DDR23_PHY_BYTE_LANE1_READ_CONTROLr(_unit, _pc, _val) \ 453 DDR23_REG_READ((_unit), (_pc), 0x00, 0x00000230, (_val)) 454 #define WRITE_DDR23_PHY_BYTE_LANE1_READ_CONTROLr(_unit, _pc, _val) \ 455 DDR23_REG_WRITE((_unit), (_pc), 0x00, 0x00000230, (_val)) 456 #define MODIFY_DDR23_PHY_BYTE_LANE1_READ_CONTROLr(_unit, _pc, _val, _mask) \ 457 DDR23_REG_MODIFY((_unit), (_pc), 0x00, 0x00000230, (_val), (_mask)) 458 459 /* Read fifo status register */ 460 #define READ_DDR23_PHY_BYTE_LANE1_READ_FIFO_STATUSr(_unit, _pc, _val) \ 461 DDR23_REG_READ((_unit), (_pc), 0x00, 0x00000234, (_val)) 462 #define WRITE_DDR23_PHY_BYTE_LANE1_READ_FIFO_STATUSr(_unit, _pc, _val) \ 463 DDR23_REG_WRITE((_unit), (_pc), 0x00, 0x00000234, (_val)) 464 #define MODIFY_DDR23_PHY_BYTE_LANE1_READ_FIFO_STATUSr(_unit, _pc, _val, _mask) \ 465 DDR23_REG_MODIFY((_unit), (_pc), 0x00, 0x00000234, (_val), (_mask)) 466 467 /* Read fifo status clear register */ 468 #define READ_DDR23_PHY_BYTE_LANE1_READ_FIFO_CLEARr(_unit, _pc, _val) \ 469 DDR23_REG_READ((_unit), (_pc), 0x00, 0x00000238, (_val)) 470 #define WRITE_DDR23_PHY_BYTE_LANE1_READ_FIFO_CLEARr(_unit, _pc, _val) \ 471 DDR23_REG_WRITE((_unit), (_pc), 0x00, 0x00000238, (_val)) 472 #define MODIFY_DDR23_PHY_BYTE_LANE1_READ_FIFO_CLEARr(_unit, _pc, _val, _mask) \ 473 DDR23_REG_MODIFY((_unit), (_pc), 0x00, 0x00000238, (_val), (_mask)) 474 475 /* Idle mode SSTL pad control register */ 476 #define READ_DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROLr(_unit, _pc, _val) \ 477 DDR23_REG_READ((_unit), (_pc), 0x00, 0x0000023c, (_val)) 478 #define WRITE_DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROLr(_unit, _pc, _val) \ 479 DDR23_REG_WRITE((_unit), (_pc), 0x00, 0x0000023c, (_val)) 480 #define MODIFY_DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROLr(_unit, _pc, _val, _mask) \ 481 DDR23_REG_MODIFY((_unit), (_pc), 0x00, 0x0000023c, (_val), (_mask)) 482 483 /* SSTL pad drive characteristics control register */ 484 #define READ_DDR23_PHY_BYTE_LANE1_DRIVE_PAD_CTLr(_unit, _pc, _val) \ 485 DDR23_REG_READ((_unit), (_pc), 0x00, 0x00000240, (_val)) 486 #define WRITE_DDR23_PHY_BYTE_LANE1_DRIVE_PAD_CTLr(_unit, _pc, _val) \ 487 DDR23_REG_WRITE((_unit), (_pc), 0x00, 0x00000240, (_val)) 488 #define MODIFY_DDR23_PHY_BYTE_LANE1_DRIVE_PAD_CTLr(_unit, _pc, _val, _mask) \ 489 DDR23_REG_MODIFY((_unit), (_pc), 0x00, 0x00000240, (_val), (_mask)) 490 491 /* Clock pad disable register */ 492 #define READ_DDR23_PHY_BYTE_LANE1_CLOCK_PAD_DISABLEr(_unit, _pc, _val) \ 493 DDR23_REG_READ((_unit), (_pc), 0x00, 0x00000244, (_val)) 494 #define WRITE_DDR23_PHY_BYTE_LANE1_CLOCK_PAD_DISABLEr(_unit, _pc, _val) \ 495 DDR23_REG_WRITE((_unit), (_pc), 0x00, 0x00000244, (_val)) 496 #define MODIFY_DDR23_PHY_BYTE_LANE1_CLOCK_PAD_DISABLEr(_unit, _pc, _val, _mask) \ 497 DDR23_REG_MODIFY((_unit), (_pc), 0x00, 0x00000244, (_val), (_mask)) 498 499 /* Write cycle preamble control register */ 500 #define READ_DDR23_PHY_BYTE_LANE1_WR_PREAMBLE_MODEr(_unit, _pc, _val) \ 501 DDR23_REG_READ((_unit), (_pc), 0x00, 0x00000248, (_val)) 502 #define WRITE_DDR23_PHY_BYTE_LANE1_WR_PREAMBLE_MODEr(_unit, _pc, _val) \ 503 DDR23_REG_WRITE((_unit), (_pc), 0x00, 0x00000248, (_val)) 504 #define MODIFY_DDR23_PHY_BYTE_LANE1_WR_PREAMBLE_MODEr(_unit, _pc, _val, _mask) \ 505 DDR23_REG_MODIFY((_unit), (_pc), 0x00, 0x00000248, (_val), (_mask)) 506 507 /* Clock Regulator control register */ 508 #define READ_DDR23_PHY_BYTE_LANE1_CLOCK_REG_CONTROLr(_unit, _pc, _val) \ 509 DDR23_REG_READ((_unit), (_pc), 0x00, 0x0000024c, (_val)) 510 #define WRITE_DDR23_PHY_BYTE_LANE1_CLOCK_REG_CONTROLr(_unit, _pc, _val) \ 511 DDR23_REG_WRITE((_unit), (_pc), 0x00, 0x0000024c, (_val)) 512 #define MODIFY_DDR23_PHY_BYTE_LANE1_CLOCK_REG_CONTROLr(_unit, _pc, _val, _mask) \ 513 DDR23_REG_MODIFY((_unit), (_pc), 0x00, 0x0000024c, (_val), (_mask)) 514 515 516 /**************************************************************************** 517 * DDR23_PHY_DDR23_PHY_ADDR_CTL 518 */ 519 /**************************************************************************** 520 * DDR23_PHY_ADDR_CTL :: REVISION 521 */ 522 /* DDR23_PHY_ADDR_CTL :: REVISION :: reserved0 [31:16] */ 523 #define DDR23_PHY_ADDR_CTL_REVISION_RESERVED0_MASK 0xffff0000 524 #define DDR23_PHY_ADDR_CTL_REVISION_RESERVED0_ALIGN 0 525 #define DDR23_PHY_ADDR_CTL_REVISION_RESERVED0_BITS 16 526 #define DDR23_PHY_ADDR_CTL_REVISION_RESERVED0_SHIFT 16 527 528 /* DDR23_PHY_ADDR_CTL :: REVISION :: MAJOR [15:08] */ 529 #define DDR23_PHY_ADDR_CTL_REVISION_MAJOR_MASK 0x0000ff00 530 #define DDR23_PHY_ADDR_CTL_REVISION_MAJOR_ALIGN 0 531 #define DDR23_PHY_ADDR_CTL_REVISION_MAJOR_BITS 8 532 #define DDR23_PHY_ADDR_CTL_REVISION_MAJOR_SHIFT 8 533 534 /* DDR23_PHY_ADDR_CTL :: REVISION :: MINOR [07:00] */ 535 #define DDR23_PHY_ADDR_CTL_REVISION_MINOR_MASK 0x000000ff 536 #define DDR23_PHY_ADDR_CTL_REVISION_MINOR_ALIGN 0 537 #define DDR23_PHY_ADDR_CTL_REVISION_MINOR_BITS 8 538 #define DDR23_PHY_ADDR_CTL_REVISION_MINOR_SHIFT 0 539 540 541 /**************************************************************************** 542 * DDR23_PHY_ADDR_CTL :: CLK_PM_CTRL 543 */ 544 /* DDR23_PHY_ADDR_CTL :: CLK_PM_CTRL :: reserved0 [31:01] */ 545 #define DDR23_PHY_ADDR_CTL_CLK_PM_CTRL_RESERVED0_MASK 0xfffffffe 546 #define DDR23_PHY_ADDR_CTL_CLK_PM_CTRL_RESERVED0_ALIGN 0 547 #define DDR23_PHY_ADDR_CTL_CLK_PM_CTRL_RESERVED0_BITS 31 548 #define DDR23_PHY_ADDR_CTL_CLK_PM_CTRL_RESERVED0_SHIFT 1 549 550 /* DDR23_PHY_ADDR_CTL :: CLK_PM_CTRL :: DIS_DDR_CLK [00:00] */ 551 #define DDR23_PHY_ADDR_CTL_CLK_PM_CTRL_DIS_DDR_CLK_MASK 0x00000001 552 #define DDR23_PHY_ADDR_CTL_CLK_PM_CTRL_DIS_DDR_CLK_ALIGN 0 553 #define DDR23_PHY_ADDR_CTL_CLK_PM_CTRL_DIS_DDR_CLK_BITS 1 554 #define DDR23_PHY_ADDR_CTL_CLK_PM_CTRL_DIS_DDR_CLK_SHIFT 0 555 556 557 /**************************************************************************** 558 * DDR23_PHY_ADDR_CTL :: PLL_STATUS 559 */ 560 /* DDR23_PHY_ADDR_CTL :: PLL_STATUS :: reserved0 [31:01] */ 561 #define DDR23_PHY_ADDR_CTL_PLL_STATUS_RESERVED0_MASK 0xfffffffe 562 #define DDR23_PHY_ADDR_CTL_PLL_STATUS_RESERVED0_ALIGN 0 563 #define DDR23_PHY_ADDR_CTL_PLL_STATUS_RESERVED0_BITS 31 564 #define DDR23_PHY_ADDR_CTL_PLL_STATUS_RESERVED0_SHIFT 1 565 566 /* DDR23_PHY_ADDR_CTL :: PLL_STATUS :: LOCK [00:00] */ 567 #define DDR23_PHY_ADDR_CTL_PLL_STATUS_LOCK_MASK 0x00000001 568 #define DDR23_PHY_ADDR_CTL_PLL_STATUS_LOCK_ALIGN 0 569 #define DDR23_PHY_ADDR_CTL_PLL_STATUS_LOCK_BITS 1 570 #define DDR23_PHY_ADDR_CTL_PLL_STATUS_LOCK_SHIFT 0 571 572 573 /**************************************************************************** 574 * DDR23_PHY_ADDR_CTL :: PLL_CONFIG 575 */ 576 /* DDR23_PHY_ADDR_CTL :: PLL_CONFIG :: DIV2_CLK_RESET [31:31] */ 577 #define DDR23_PHY_ADDR_CTL_PLL_CONFIG_DIV2_CLK_RESET_MASK 0x80000000 578 #define DDR23_PHY_ADDR_CTL_PLL_CONFIG_DIV2_CLK_RESET_ALIGN 0 579 #define DDR23_PHY_ADDR_CTL_PLL_CONFIG_DIV2_CLK_RESET_BITS 1 580 #define DDR23_PHY_ADDR_CTL_PLL_CONFIG_DIV2_CLK_RESET_SHIFT 31 581 582 /* DDR23_PHY_ADDR_CTL :: PLL_CONFIG :: reserved0 [30:22] */ 583 #define DDR23_PHY_ADDR_CTL_PLL_CONFIG_RESERVED0_MASK 0x7fc00000 584 #define DDR23_PHY_ADDR_CTL_PLL_CONFIG_RESERVED0_ALIGN 0 585 #define DDR23_PHY_ADDR_CTL_PLL_CONFIG_RESERVED0_BITS 9 586 #define DDR23_PHY_ADDR_CTL_PLL_CONFIG_RESERVED0_SHIFT 22 587 588 /* DDR23_PHY_ADDR_CTL :: PLL_CONFIG :: TEST_SEL [21:17] */ 589 #define DDR23_PHY_ADDR_CTL_PLL_CONFIG_TEST_SEL_MASK 0x003e0000 590 #define DDR23_PHY_ADDR_CTL_PLL_CONFIG_TEST_SEL_ALIGN 0 591 #define DDR23_PHY_ADDR_CTL_PLL_CONFIG_TEST_SEL_BITS 5 592 #define DDR23_PHY_ADDR_CTL_PLL_CONFIG_TEST_SEL_SHIFT 17 593 594 /* DDR23_PHY_ADDR_CTL :: PLL_CONFIG :: TEST_EN [16:16] */ 595 #define DDR23_PHY_ADDR_CTL_PLL_CONFIG_TEST_EN_MASK 0x00010000 596 #define DDR23_PHY_ADDR_CTL_PLL_CONFIG_TEST_EN_ALIGN 0 597 #define DDR23_PHY_ADDR_CTL_PLL_CONFIG_TEST_EN_BITS 1 598 #define DDR23_PHY_ADDR_CTL_PLL_CONFIG_TEST_EN_SHIFT 16 599 600 /* DDR23_PHY_ADDR_CTL :: PLL_CONFIG :: BGAP_ADJ [15:12] */ 601 #define DDR23_PHY_ADDR_CTL_PLL_CONFIG_BGAP_ADJ_MASK 0x0000f000 602 #define DDR23_PHY_ADDR_CTL_PLL_CONFIG_BGAP_ADJ_ALIGN 0 603 #define DDR23_PHY_ADDR_CTL_PLL_CONFIG_BGAP_ADJ_BITS 4 604 #define DDR23_PHY_ADDR_CTL_PLL_CONFIG_BGAP_ADJ_SHIFT 12 605 606 /* DDR23_PHY_ADDR_CTL :: PLL_CONFIG :: reserved1 [11:08] */ 607 #define DDR23_PHY_ADDR_CTL_PLL_CONFIG_RESERVED1_MASK 0x00000f00 608 #define DDR23_PHY_ADDR_CTL_PLL_CONFIG_RESERVED1_ALIGN 0 609 #define DDR23_PHY_ADDR_CTL_PLL_CONFIG_RESERVED1_BITS 4 610 #define DDR23_PHY_ADDR_CTL_PLL_CONFIG_RESERVED1_SHIFT 8 611 612 /* DDR23_PHY_ADDR_CTL :: PLL_CONFIG :: VCO_RNG [07:07] */ 613 #define DDR23_PHY_ADDR_CTL_PLL_CONFIG_VCO_RNG_MASK 0x00000080 614 #define DDR23_PHY_ADDR_CTL_PLL_CONFIG_VCO_RNG_ALIGN 0 615 #define DDR23_PHY_ADDR_CTL_PLL_CONFIG_VCO_RNG_BITS 1 616 #define DDR23_PHY_ADDR_CTL_PLL_CONFIG_VCO_RNG_SHIFT 7 617 618 /* DDR23_PHY_ADDR_CTL :: PLL_CONFIG :: PWRDN_CH1 [06:06] */ 619 #define DDR23_PHY_ADDR_CTL_PLL_CONFIG_PWRDN_CH1_MASK 0x00000040 620 #define DDR23_PHY_ADDR_CTL_PLL_CONFIG_PWRDN_CH1_ALIGN 0 621 #define DDR23_PHY_ADDR_CTL_PLL_CONFIG_PWRDN_CH1_BITS 1 622 #define DDR23_PHY_ADDR_CTL_PLL_CONFIG_PWRDN_CH1_SHIFT 6 623 624 /* DDR23_PHY_ADDR_CTL :: PLL_CONFIG :: BYPEN [05:05] */ 625 #define DDR23_PHY_ADDR_CTL_PLL_CONFIG_BYPEN_MASK 0x00000020 626 #define DDR23_PHY_ADDR_CTL_PLL_CONFIG_BYPEN_ALIGN 0 627 #define DDR23_PHY_ADDR_CTL_PLL_CONFIG_BYPEN_BITS 1 628 #define DDR23_PHY_ADDR_CTL_PLL_CONFIG_BYPEN_SHIFT 5 629 630 /* DDR23_PHY_ADDR_CTL :: PLL_CONFIG :: ENB_CLKOUT [04:04] */ 631 #define DDR23_PHY_ADDR_CTL_PLL_CONFIG_ENB_CLKOUT_MASK 0x00000010 632 #define DDR23_PHY_ADDR_CTL_PLL_CONFIG_ENB_CLKOUT_ALIGN 0 633 #define DDR23_PHY_ADDR_CTL_PLL_CONFIG_ENB_CLKOUT_BITS 1 634 #define DDR23_PHY_ADDR_CTL_PLL_CONFIG_ENB_CLKOUT_SHIFT 4 635 636 /* DDR23_PHY_ADDR_CTL :: PLL_CONFIG :: DRESET [03:03] */ 637 #define DDR23_PHY_ADDR_CTL_PLL_CONFIG_DRESET_MASK 0x00000008 638 #define DDR23_PHY_ADDR_CTL_PLL_CONFIG_DRESET_ALIGN 0 639 #define DDR23_PHY_ADDR_CTL_PLL_CONFIG_DRESET_BITS 1 640 #define DDR23_PHY_ADDR_CTL_PLL_CONFIG_DRESET_SHIFT 3 641 642 /* DDR23_PHY_ADDR_CTL :: PLL_CONFIG :: ARESET [02:02] */ 643 #define DDR23_PHY_ADDR_CTL_PLL_CONFIG_ARESET_MASK 0x00000004 644 #define DDR23_PHY_ADDR_CTL_PLL_CONFIG_ARESET_ALIGN 0 645 #define DDR23_PHY_ADDR_CTL_PLL_CONFIG_ARESET_BITS 1 646 #define DDR23_PHY_ADDR_CTL_PLL_CONFIG_ARESET_SHIFT 2 647 648 /* DDR23_PHY_ADDR_CTL :: PLL_CONFIG :: reserved2 [01:01] */ 649 #define DDR23_PHY_ADDR_CTL_PLL_CONFIG_RESERVED2_MASK 0x00000002 650 #define DDR23_PHY_ADDR_CTL_PLL_CONFIG_RESERVED2_ALIGN 0 651 #define DDR23_PHY_ADDR_CTL_PLL_CONFIG_RESERVED2_BITS 1 652 #define DDR23_PHY_ADDR_CTL_PLL_CONFIG_RESERVED2_SHIFT 1 653 654 /* DDR23_PHY_ADDR_CTL :: PLL_CONFIG :: PWRDN [00:00] */ 655 #define DDR23_PHY_ADDR_CTL_PLL_CONFIG_PWRDN_MASK 0x00000001 656 #define DDR23_PHY_ADDR_CTL_PLL_CONFIG_PWRDN_ALIGN 0 657 #define DDR23_PHY_ADDR_CTL_PLL_CONFIG_PWRDN_BITS 1 658 #define DDR23_PHY_ADDR_CTL_PLL_CONFIG_PWRDN_SHIFT 0 659 660 661 /**************************************************************************** 662 * DDR23_PHY_ADDR_CTL :: PLL_PRE_DIVIDER 663 */ 664 /* DDR23_PHY_ADDR_CTL :: PLL_PRE_DIVIDER :: reserved0 [31:27] */ 665 #define DDR23_PHY_ADDR_CTL_PLL_PRE_DIVIDER_RESERVED0_MASK 0xf8000000 666 #define DDR23_PHY_ADDR_CTL_PLL_PRE_DIVIDER_RESERVED0_ALIGN 0 667 #define DDR23_PHY_ADDR_CTL_PLL_PRE_DIVIDER_RESERVED0_BITS 5 668 #define DDR23_PHY_ADDR_CTL_PLL_PRE_DIVIDER_RESERVED0_SHIFT 27 669 670 /* DDR23_PHY_ADDR_CTL :: PLL_PRE_DIVIDER :: NDIV_DITHER_MFB [26:26] */ 671 #define DDR23_PHY_ADDR_CTL_PLL_PRE_DIVIDER_NDIV_DITHER_MFB_MASK 0x04000000 672 #define DDR23_PHY_ADDR_CTL_PLL_PRE_DIVIDER_NDIV_DITHER_MFB_ALIGN 0 673 #define DDR23_PHY_ADDR_CTL_PLL_PRE_DIVIDER_NDIV_DITHER_MFB_BITS 1 674 #define DDR23_PHY_ADDR_CTL_PLL_PRE_DIVIDER_NDIV_DITHER_MFB_SHIFT 26 675 676 /* DDR23_PHY_ADDR_CTL :: PLL_PRE_DIVIDER :: NDIV_PWRDN [25:25] */ 677 #define DDR23_PHY_ADDR_CTL_PLL_PRE_DIVIDER_NDIV_PWRDN_MASK 0x02000000 678 #define DDR23_PHY_ADDR_CTL_PLL_PRE_DIVIDER_NDIV_PWRDN_ALIGN 0 679 #define DDR23_PHY_ADDR_CTL_PLL_PRE_DIVIDER_NDIV_PWRDN_BITS 1 680 #define DDR23_PHY_ADDR_CTL_PLL_PRE_DIVIDER_NDIV_PWRDN_SHIFT 25 681 682 /* DDR23_PHY_ADDR_CTL :: PLL_PRE_DIVIDER :: reserved1 [24:23] */ 683 #define DDR23_PHY_ADDR_CTL_PLL_PRE_DIVIDER_RESERVED1_MASK 0x01800000 684 #define DDR23_PHY_ADDR_CTL_PLL_PRE_DIVIDER_RESERVED1_ALIGN 0 685 #define DDR23_PHY_ADDR_CTL_PLL_PRE_DIVIDER_RESERVED1_BITS 2 686 #define DDR23_PHY_ADDR_CTL_PLL_PRE_DIVIDER_RESERVED1_SHIFT 23 687 688 /* DDR23_PHY_ADDR_CTL :: PLL_PRE_DIVIDER :: NDIV_MODE [22:20] */ 689 #define DDR23_PHY_ADDR_CTL_PLL_PRE_DIVIDER_NDIV_MODE_MASK 0x00700000 690 #define DDR23_PHY_ADDR_CTL_PLL_PRE_DIVIDER_NDIV_MODE_ALIGN 0 691 #define DDR23_PHY_ADDR_CTL_PLL_PRE_DIVIDER_NDIV_MODE_BITS 3 692 #define DDR23_PHY_ADDR_CTL_PLL_PRE_DIVIDER_NDIV_MODE_SHIFT 20 693 694 /* DDR23_PHY_ADDR_CTL :: PLL_PRE_DIVIDER :: reserved2 [19:17] */ 695 #define DDR23_PHY_ADDR_CTL_PLL_PRE_DIVIDER_RESERVED2_MASK 0x000e0000 696 #define DDR23_PHY_ADDR_CTL_PLL_PRE_DIVIDER_RESERVED2_ALIGN 0 697 #define DDR23_PHY_ADDR_CTL_PLL_PRE_DIVIDER_RESERVED2_BITS 3 698 #define DDR23_PHY_ADDR_CTL_PLL_PRE_DIVIDER_RESERVED2_SHIFT 17 699 700 /* DDR23_PHY_ADDR_CTL :: PLL_PRE_DIVIDER :: NDIV_INT [16:08] */ 701 #define DDR23_PHY_ADDR_CTL_PLL_PRE_DIVIDER_NDIV_INT_MASK 0x0001ff00 702 #define DDR23_PHY_ADDR_CTL_PLL_PRE_DIVIDER_NDIV_INT_ALIGN 0 703 #define DDR23_PHY_ADDR_CTL_PLL_PRE_DIVIDER_NDIV_INT_BITS 9 704 #define DDR23_PHY_ADDR_CTL_PLL_PRE_DIVIDER_NDIV_INT_SHIFT 8 705 706 /* DDR23_PHY_ADDR_CTL :: PLL_PRE_DIVIDER :: P2DIV [07:04] */ 707 #define DDR23_PHY_ADDR_CTL_PLL_PRE_DIVIDER_P2DIV_MASK 0x000000f0 708 #define DDR23_PHY_ADDR_CTL_PLL_PRE_DIVIDER_P2DIV_ALIGN 0 709 #define DDR23_PHY_ADDR_CTL_PLL_PRE_DIVIDER_P2DIV_BITS 4 710 #define DDR23_PHY_ADDR_CTL_PLL_PRE_DIVIDER_P2DIV_SHIFT 4 711 712 /* DDR23_PHY_ADDR_CTL :: PLL_PRE_DIVIDER :: P1DIV [03:00] */ 713 #define DDR23_PHY_ADDR_CTL_PLL_PRE_DIVIDER_P1DIV_MASK 0x0000000f 714 #define DDR23_PHY_ADDR_CTL_PLL_PRE_DIVIDER_P1DIV_ALIGN 0 715 #define DDR23_PHY_ADDR_CTL_PLL_PRE_DIVIDER_P1DIV_BITS 4 716 #define DDR23_PHY_ADDR_CTL_PLL_PRE_DIVIDER_P1DIV_SHIFT 0 717 718 719 /**************************************************************************** 720 * DDR23_PHY_ADDR_CTL :: PLL_DIVIDER 721 */ 722 /* DDR23_PHY_ADDR_CTL :: PLL_DIVIDER :: M1DIV [31:24] */ 723 #define DDR23_PHY_ADDR_CTL_PLL_DIVIDER_M1DIV_MASK 0xff000000 724 #define DDR23_PHY_ADDR_CTL_PLL_DIVIDER_M1DIV_ALIGN 0 725 #define DDR23_PHY_ADDR_CTL_PLL_DIVIDER_M1DIV_BITS 8 726 #define DDR23_PHY_ADDR_CTL_PLL_DIVIDER_M1DIV_SHIFT 24 727 728 /* DDR23_PHY_ADDR_CTL :: PLL_DIVIDER :: NDIV_FRAC [23:00] */ 729 #define DDR23_PHY_ADDR_CTL_PLL_DIVIDER_NDIV_FRAC_MASK 0x00ffffff 730 #define DDR23_PHY_ADDR_CTL_PLL_DIVIDER_NDIV_FRAC_ALIGN 0 731 #define DDR23_PHY_ADDR_CTL_PLL_DIVIDER_NDIV_FRAC_BITS 24 732 #define DDR23_PHY_ADDR_CTL_PLL_DIVIDER_NDIV_FRAC_SHIFT 0 733 734 735 /**************************************************************************** 736 * DDR23_PHY_ADDR_CTL :: PLL_CONTROL1 737 */ 738 /* DDR23_PHY_ADDR_CTL :: PLL_CONTROL1 :: TESTA_SEL [31:30] */ 739 #define DDR23_PHY_ADDR_CTL_PLL_CONTROL1_TESTA_SEL_MASK 0xc0000000 740 #define DDR23_PHY_ADDR_CTL_PLL_CONTROL1_TESTA_SEL_ALIGN 0 741 #define DDR23_PHY_ADDR_CTL_PLL_CONTROL1_TESTA_SEL_BITS 2 742 #define DDR23_PHY_ADDR_CTL_PLL_CONTROL1_TESTA_SEL_SHIFT 30 743 744 /* DDR23_PHY_ADDR_CTL :: PLL_CONTROL1 :: KVCO_XS [29:27] */ 745 #define DDR23_PHY_ADDR_CTL_PLL_CONTROL1_KVCO_XS_MASK 0x38000000 746 #define DDR23_PHY_ADDR_CTL_PLL_CONTROL1_KVCO_XS_ALIGN 0 747 #define DDR23_PHY_ADDR_CTL_PLL_CONTROL1_KVCO_XS_BITS 3 748 #define DDR23_PHY_ADDR_CTL_PLL_CONTROL1_KVCO_XS_SHIFT 27 749 750 /* DDR23_PHY_ADDR_CTL :: PLL_CONTROL1 :: KVCO_XF [26:24] */ 751 #define DDR23_PHY_ADDR_CTL_PLL_CONTROL1_KVCO_XF_MASK 0x07000000 752 #define DDR23_PHY_ADDR_CTL_PLL_CONTROL1_KVCO_XF_ALIGN 0 753 #define DDR23_PHY_ADDR_CTL_PLL_CONTROL1_KVCO_XF_BITS 3 754 #define DDR23_PHY_ADDR_CTL_PLL_CONTROL1_KVCO_XF_SHIFT 24 755 756 /* DDR23_PHY_ADDR_CTL :: PLL_CONTROL1 :: LPF_BW [23:22] */ 757 #define DDR23_PHY_ADDR_CTL_PLL_CONTROL1_LPF_BW_MASK 0x00c00000 758 #define DDR23_PHY_ADDR_CTL_PLL_CONTROL1_LPF_BW_ALIGN 0 759 #define DDR23_PHY_ADDR_CTL_PLL_CONTROL1_LPF_BW_BITS 2 760 #define DDR23_PHY_ADDR_CTL_PLL_CONTROL1_LPF_BW_SHIFT 22 761 762 /* DDR23_PHY_ADDR_CTL :: PLL_CONTROL1 :: LF_ORDER [21:21] */ 763 #define DDR23_PHY_ADDR_CTL_PLL_CONTROL1_LF_ORDER_MASK 0x00200000 764 #define DDR23_PHY_ADDR_CTL_PLL_CONTROL1_LF_ORDER_ALIGN 0 765 #define DDR23_PHY_ADDR_CTL_PLL_CONTROL1_LF_ORDER_BITS 1 766 #define DDR23_PHY_ADDR_CTL_PLL_CONTROL1_LF_ORDER_SHIFT 21 767 768 /* DDR23_PHY_ADDR_CTL :: PLL_CONTROL1 :: CN [20:19] */ 769 #define DDR23_PHY_ADDR_CTL_PLL_CONTROL1_CN_MASK 0x00180000 770 #define DDR23_PHY_ADDR_CTL_PLL_CONTROL1_CN_ALIGN 0 771 #define DDR23_PHY_ADDR_CTL_PLL_CONTROL1_CN_BITS 2 772 #define DDR23_PHY_ADDR_CTL_PLL_CONTROL1_CN_SHIFT 19 773 774 /* DDR23_PHY_ADDR_CTL :: PLL_CONTROL1 :: RN [18:17] */ 775 #define DDR23_PHY_ADDR_CTL_PLL_CONTROL1_RN_MASK 0x00060000 776 #define DDR23_PHY_ADDR_CTL_PLL_CONTROL1_RN_ALIGN 0 777 #define DDR23_PHY_ADDR_CTL_PLL_CONTROL1_RN_BITS 2 778 #define DDR23_PHY_ADDR_CTL_PLL_CONTROL1_RN_SHIFT 17 779 780 /* DDR23_PHY_ADDR_CTL :: PLL_CONTROL1 :: CP [16:15] */ 781 #define DDR23_PHY_ADDR_CTL_PLL_CONTROL1_CP_MASK 0x00018000 782 #define DDR23_PHY_ADDR_CTL_PLL_CONTROL1_CP_ALIGN 0 783 #define DDR23_PHY_ADDR_CTL_PLL_CONTROL1_CP_BITS 2 784 #define DDR23_PHY_ADDR_CTL_PLL_CONTROL1_CP_SHIFT 15 785 786 /* DDR23_PHY_ADDR_CTL :: PLL_CONTROL1 :: CZ [14:13] */ 787 #define DDR23_PHY_ADDR_CTL_PLL_CONTROL1_CZ_MASK 0x00006000 788 #define DDR23_PHY_ADDR_CTL_PLL_CONTROL1_CZ_ALIGN 0 789 #define DDR23_PHY_ADDR_CTL_PLL_CONTROL1_CZ_BITS 2 790 #define DDR23_PHY_ADDR_CTL_PLL_CONTROL1_CZ_SHIFT 13 791 792 /* DDR23_PHY_ADDR_CTL :: PLL_CONTROL1 :: RZ [12:10] */ 793 #define DDR23_PHY_ADDR_CTL_PLL_CONTROL1_RZ_MASK 0x00001c00 794 #define DDR23_PHY_ADDR_CTL_PLL_CONTROL1_RZ_ALIGN 0 795 #define DDR23_PHY_ADDR_CTL_PLL_CONTROL1_RZ_BITS 3 796 #define DDR23_PHY_ADDR_CTL_PLL_CONTROL1_RZ_SHIFT 10 797 798 /* DDR23_PHY_ADDR_CTL :: PLL_CONTROL1 :: ICPX [09:05] */ 799 #define DDR23_PHY_ADDR_CTL_PLL_CONTROL1_ICPX_MASK 0x000003e0 800 #define DDR23_PHY_ADDR_CTL_PLL_CONTROL1_ICPX_ALIGN 0 801 #define DDR23_PHY_ADDR_CTL_PLL_CONTROL1_ICPX_BITS 5 802 #define DDR23_PHY_ADDR_CTL_PLL_CONTROL1_ICPX_SHIFT 5 803 804 /* DDR23_PHY_ADDR_CTL :: PLL_CONTROL1 :: ICP_OFF [04:00] */ 805 #define DDR23_PHY_ADDR_CTL_PLL_CONTROL1_ICP_OFF_MASK 0x0000001f 806 #define DDR23_PHY_ADDR_CTL_PLL_CONTROL1_ICP_OFF_ALIGN 0 807 #define DDR23_PHY_ADDR_CTL_PLL_CONTROL1_ICP_OFF_BITS 5 808 #define DDR23_PHY_ADDR_CTL_PLL_CONTROL1_ICP_OFF_SHIFT 0 809 810 811 /**************************************************************************** 812 * DDR23_PHY_ADDR_CTL :: PLL_CONTROL2 813 */ 814 /* DDR23_PHY_ADDR_CTL :: PLL_CONTROL2 :: reserved0 [31:06] */ 815 #define DDR23_PHY_ADDR_CTL_PLL_CONTROL2_RESERVED0_MASK 0xffffffc0 816 #define DDR23_PHY_ADDR_CTL_PLL_CONTROL2_RESERVED0_ALIGN 0 817 #define DDR23_PHY_ADDR_CTL_PLL_CONTROL2_RESERVED0_BITS 26 818 #define DDR23_PHY_ADDR_CTL_PLL_CONTROL2_RESERVED0_SHIFT 6 819 820 /* DDR23_PHY_ADDR_CTL :: PLL_CONTROL2 :: PTAP_ADJ [05:04] */ 821 #define DDR23_PHY_ADDR_CTL_PLL_CONTROL2_PTAP_ADJ_MASK 0x00000030 822 #define DDR23_PHY_ADDR_CTL_PLL_CONTROL2_PTAP_ADJ_ALIGN 0 823 #define DDR23_PHY_ADDR_CTL_PLL_CONTROL2_PTAP_ADJ_BITS 2 824 #define DDR23_PHY_ADDR_CTL_PLL_CONTROL2_PTAP_ADJ_SHIFT 4 825 826 /* DDR23_PHY_ADDR_CTL :: PLL_CONTROL2 :: CTAP_ADJ [03:02] */ 827 #define DDR23_PHY_ADDR_CTL_PLL_CONTROL2_CTAP_ADJ_MASK 0x0000000c 828 #define DDR23_PHY_ADDR_CTL_PLL_CONTROL2_CTAP_ADJ_ALIGN 0 829 #define DDR23_PHY_ADDR_CTL_PLL_CONTROL2_CTAP_ADJ_BITS 2 830 #define DDR23_PHY_ADDR_CTL_PLL_CONTROL2_CTAP_ADJ_SHIFT 2 831 832 /* DDR23_PHY_ADDR_CTL :: PLL_CONTROL2 :: LOWCUR_EN [01:01] */ 833 #define DDR23_PHY_ADDR_CTL_PLL_CONTROL2_LOWCUR_EN_MASK 0x00000002 834 #define DDR23_PHY_ADDR_CTL_PLL_CONTROL2_LOWCUR_EN_ALIGN 0 835 #define DDR23_PHY_ADDR_CTL_PLL_CONTROL2_LOWCUR_EN_BITS 1 836 #define DDR23_PHY_ADDR_CTL_PLL_CONTROL2_LOWCUR_EN_SHIFT 1 837 838 /* DDR23_PHY_ADDR_CTL :: PLL_CONTROL2 :: BIASIN_EN [00:00] */ 839 #define DDR23_PHY_ADDR_CTL_PLL_CONTROL2_BIASIN_EN_MASK 0x00000001 840 #define DDR23_PHY_ADDR_CTL_PLL_CONTROL2_BIASIN_EN_ALIGN 0 841 #define DDR23_PHY_ADDR_CTL_PLL_CONTROL2_BIASIN_EN_BITS 1 842 #define DDR23_PHY_ADDR_CTL_PLL_CONTROL2_BIASIN_EN_SHIFT 0 843 844 845 /**************************************************************************** 846 * DDR23_PHY_ADDR_CTL :: PLL_SS_EN 847 */ 848 /* DDR23_PHY_ADDR_CTL :: PLL_SS_EN :: reserved0 [31:01] */ 849 #define DDR23_PHY_ADDR_CTL_PLL_SS_EN_RESERVED0_MASK 0xfffffffe 850 #define DDR23_PHY_ADDR_CTL_PLL_SS_EN_RESERVED0_ALIGN 0 851 #define DDR23_PHY_ADDR_CTL_PLL_SS_EN_RESERVED0_BITS 31 852 #define DDR23_PHY_ADDR_CTL_PLL_SS_EN_RESERVED0_SHIFT 1 853 854 /* DDR23_PHY_ADDR_CTL :: PLL_SS_EN :: SS_EN [00:00] */ 855 #define DDR23_PHY_ADDR_CTL_PLL_SS_EN_SS_EN_MASK 0x00000001 856 #define DDR23_PHY_ADDR_CTL_PLL_SS_EN_SS_EN_ALIGN 0 857 #define DDR23_PHY_ADDR_CTL_PLL_SS_EN_SS_EN_BITS 1 858 #define DDR23_PHY_ADDR_CTL_PLL_SS_EN_SS_EN_SHIFT 0 859 860 861 /**************************************************************************** 862 * DDR23_PHY_ADDR_CTL :: PLL_SS_CFG 863 */ 864 /* DDR23_PHY_ADDR_CTL :: PLL_SS_CFG :: REF_CYC_PER_TICK [31:16] */ 865 #define DDR23_PHY_ADDR_CTL_PLL_SS_CFG_REF_CYC_PER_TICK_MASK 0xffff0000 866 #define DDR23_PHY_ADDR_CTL_PLL_SS_CFG_REF_CYC_PER_TICK_ALIGN 0 867 #define DDR23_PHY_ADDR_CTL_PLL_SS_CFG_REF_CYC_PER_TICK_BITS 16 868 #define DDR23_PHY_ADDR_CTL_PLL_SS_CFG_REF_CYC_PER_TICK_SHIFT 16 869 870 /* DDR23_PHY_ADDR_CTL :: PLL_SS_CFG :: NDIV_AMP [15:00] */ 871 #define DDR23_PHY_ADDR_CTL_PLL_SS_CFG_NDIV_AMP_MASK 0x0000ffff 872 #define DDR23_PHY_ADDR_CTL_PLL_SS_CFG_NDIV_AMP_ALIGN 0 873 #define DDR23_PHY_ADDR_CTL_PLL_SS_CFG_NDIV_AMP_BITS 16 874 #define DDR23_PHY_ADDR_CTL_PLL_SS_CFG_NDIV_AMP_SHIFT 0 875 876 877 /**************************************************************************** 878 * DDR23_PHY_ADDR_CTL :: STATIC_VDL_OVERRIDE 879 */ 880 /* DDR23_PHY_ADDR_CTL :: STATIC_VDL_OVERRIDE :: reserved0 [31:21] */ 881 #define DDR23_PHY_ADDR_CTL_STATIC_VDL_OVERRIDE_RESERVED0_MASK 0xffe00000 882 #define DDR23_PHY_ADDR_CTL_STATIC_VDL_OVERRIDE_RESERVED0_ALIGN 0 883 #define DDR23_PHY_ADDR_CTL_STATIC_VDL_OVERRIDE_RESERVED0_BITS 11 884 #define DDR23_PHY_ADDR_CTL_STATIC_VDL_OVERRIDE_RESERVED0_SHIFT 21 885 886 /* DDR23_PHY_ADDR_CTL :: STATIC_VDL_OVERRIDE :: ovr_force [20:20] */ 887 #define DDR23_PHY_ADDR_CTL_STATIC_VDL_OVERRIDE_OVR_FORCE_MASK 0x00100000 888 #define DDR23_PHY_ADDR_CTL_STATIC_VDL_OVERRIDE_OVR_FORCE_ALIGN 0 889 #define DDR23_PHY_ADDR_CTL_STATIC_VDL_OVERRIDE_OVR_FORCE_BITS 1 890 #define DDR23_PHY_ADDR_CTL_STATIC_VDL_OVERRIDE_OVR_FORCE_SHIFT 20 891 892 /* DDR23_PHY_ADDR_CTL :: STATIC_VDL_OVERRIDE :: reserved1 [19:17] */ 893 #define DDR23_PHY_ADDR_CTL_STATIC_VDL_OVERRIDE_RESERVED1_MASK 0x000e0000 894 #define DDR23_PHY_ADDR_CTL_STATIC_VDL_OVERRIDE_RESERVED1_ALIGN 0 895 #define DDR23_PHY_ADDR_CTL_STATIC_VDL_OVERRIDE_RESERVED1_BITS 3 896 #define DDR23_PHY_ADDR_CTL_STATIC_VDL_OVERRIDE_RESERVED1_SHIFT 17 897 898 /* DDR23_PHY_ADDR_CTL :: STATIC_VDL_OVERRIDE :: ovr_en [16:16] */ 899 #define DDR23_PHY_ADDR_CTL_STATIC_VDL_OVERRIDE_OVR_EN_MASK 0x00010000 900 #define DDR23_PHY_ADDR_CTL_STATIC_VDL_OVERRIDE_OVR_EN_ALIGN 0 901 #define DDR23_PHY_ADDR_CTL_STATIC_VDL_OVERRIDE_OVR_EN_BITS 1 902 #define DDR23_PHY_ADDR_CTL_STATIC_VDL_OVERRIDE_OVR_EN_SHIFT 16 903 904 /* DDR23_PHY_ADDR_CTL :: STATIC_VDL_OVERRIDE :: reserved2 [15:14] */ 905 #define DDR23_PHY_ADDR_CTL_STATIC_VDL_OVERRIDE_RESERVED2_MASK 0x0000c000 906 #define DDR23_PHY_ADDR_CTL_STATIC_VDL_OVERRIDE_RESERVED2_ALIGN 0 907 #define DDR23_PHY_ADDR_CTL_STATIC_VDL_OVERRIDE_RESERVED2_BITS 2 908 #define DDR23_PHY_ADDR_CTL_STATIC_VDL_OVERRIDE_RESERVED2_SHIFT 14 909 910 /* DDR23_PHY_ADDR_CTL :: STATIC_VDL_OVERRIDE :: ovr_fine_fall [13:12] */ 911 #define DDR23_PHY_ADDR_CTL_STATIC_VDL_OVERRIDE_OVR_FINE_FALL_MASK 0x00003000 912 #define DDR23_PHY_ADDR_CTL_STATIC_VDL_OVERRIDE_OVR_FINE_FALL_ALIGN 0 913 #define DDR23_PHY_ADDR_CTL_STATIC_VDL_OVERRIDE_OVR_FINE_FALL_BITS 2 914 #define DDR23_PHY_ADDR_CTL_STATIC_VDL_OVERRIDE_OVR_FINE_FALL_SHIFT 12 915 916 /* DDR23_PHY_ADDR_CTL :: STATIC_VDL_OVERRIDE :: reserved3 [11:10] */ 917 #define DDR23_PHY_ADDR_CTL_STATIC_VDL_OVERRIDE_RESERVED3_MASK 0x00000c00 918 #define DDR23_PHY_ADDR_CTL_STATIC_VDL_OVERRIDE_RESERVED3_ALIGN 0 919 #define DDR23_PHY_ADDR_CTL_STATIC_VDL_OVERRIDE_RESERVED3_BITS 2 920 #define DDR23_PHY_ADDR_CTL_STATIC_VDL_OVERRIDE_RESERVED3_SHIFT 10 921 922 /* DDR23_PHY_ADDR_CTL :: STATIC_VDL_OVERRIDE :: ovr_fine_rise [09:08] */ 923 #define DDR23_PHY_ADDR_CTL_STATIC_VDL_OVERRIDE_OVR_FINE_RISE_MASK 0x00000300 924 #define DDR23_PHY_ADDR_CTL_STATIC_VDL_OVERRIDE_OVR_FINE_RISE_ALIGN 0 925 #define DDR23_PHY_ADDR_CTL_STATIC_VDL_OVERRIDE_OVR_FINE_RISE_BITS 2 926 #define DDR23_PHY_ADDR_CTL_STATIC_VDL_OVERRIDE_OVR_FINE_RISE_SHIFT 8 927 928 /* DDR23_PHY_ADDR_CTL :: STATIC_VDL_OVERRIDE :: reserved4 [07:06] */ 929 #define DDR23_PHY_ADDR_CTL_STATIC_VDL_OVERRIDE_RESERVED4_MASK 0x000000c0 930 #define DDR23_PHY_ADDR_CTL_STATIC_VDL_OVERRIDE_RESERVED4_ALIGN 0 931 #define DDR23_PHY_ADDR_CTL_STATIC_VDL_OVERRIDE_RESERVED4_BITS 2 932 #define DDR23_PHY_ADDR_CTL_STATIC_VDL_OVERRIDE_RESERVED4_SHIFT 6 933 934 /* DDR23_PHY_ADDR_CTL :: STATIC_VDL_OVERRIDE :: ovr_step [05:00] */ 935 #define DDR23_PHY_ADDR_CTL_STATIC_VDL_OVERRIDE_OVR_STEP_MASK 0x0000003f 936 #define DDR23_PHY_ADDR_CTL_STATIC_VDL_OVERRIDE_OVR_STEP_ALIGN 0 937 #define DDR23_PHY_ADDR_CTL_STATIC_VDL_OVERRIDE_OVR_STEP_BITS 6 938 #define DDR23_PHY_ADDR_CTL_STATIC_VDL_OVERRIDE_OVR_STEP_SHIFT 0 939 940 941 /**************************************************************************** 942 * DDR23_PHY_ADDR_CTL :: DYNAMIC_VDL_OVERRIDE 943 */ 944 /* DDR23_PHY_ADDR_CTL :: DYNAMIC_VDL_OVERRIDE :: reserved0 [31:17] */ 945 #define DDR23_PHY_ADDR_CTL_DYNAMIC_VDL_OVERRIDE_RESERVED0_MASK 0xfffe0000 946 #define DDR23_PHY_ADDR_CTL_DYNAMIC_VDL_OVERRIDE_RESERVED0_ALIGN 0 947 #define DDR23_PHY_ADDR_CTL_DYNAMIC_VDL_OVERRIDE_RESERVED0_BITS 15 948 #define DDR23_PHY_ADDR_CTL_DYNAMIC_VDL_OVERRIDE_RESERVED0_SHIFT 17 949 950 /* DDR23_PHY_ADDR_CTL :: DYNAMIC_VDL_OVERRIDE :: ovr_en [16:16] */ 951 #define DDR23_PHY_ADDR_CTL_DYNAMIC_VDL_OVERRIDE_OVR_EN_MASK 0x00010000 952 #define DDR23_PHY_ADDR_CTL_DYNAMIC_VDL_OVERRIDE_OVR_EN_ALIGN 0 953 #define DDR23_PHY_ADDR_CTL_DYNAMIC_VDL_OVERRIDE_OVR_EN_BITS 1 954 #define DDR23_PHY_ADDR_CTL_DYNAMIC_VDL_OVERRIDE_OVR_EN_SHIFT 16 955 956 /* DDR23_PHY_ADDR_CTL :: DYNAMIC_VDL_OVERRIDE :: reserved1 [15:14] */ 957 #define DDR23_PHY_ADDR_CTL_DYNAMIC_VDL_OVERRIDE_RESERVED1_MASK 0x0000c000 958 #define DDR23_PHY_ADDR_CTL_DYNAMIC_VDL_OVERRIDE_RESERVED1_ALIGN 0 959 #define DDR23_PHY_ADDR_CTL_DYNAMIC_VDL_OVERRIDE_RESERVED1_BITS 2 960 #define DDR23_PHY_ADDR_CTL_DYNAMIC_VDL_OVERRIDE_RESERVED1_SHIFT 14 961 962 /* DDR23_PHY_ADDR_CTL :: DYNAMIC_VDL_OVERRIDE :: ovr_fine_fall [13:12] */ 963 #define DDR23_PHY_ADDR_CTL_DYNAMIC_VDL_OVERRIDE_OVR_FINE_FALL_MASK 0x00003000 964 #define DDR23_PHY_ADDR_CTL_DYNAMIC_VDL_OVERRIDE_OVR_FINE_FALL_ALIGN 0 965 #define DDR23_PHY_ADDR_CTL_DYNAMIC_VDL_OVERRIDE_OVR_FINE_FALL_BITS 2 966 #define DDR23_PHY_ADDR_CTL_DYNAMIC_VDL_OVERRIDE_OVR_FINE_FALL_SHIFT 12 967 968 /* DDR23_PHY_ADDR_CTL :: DYNAMIC_VDL_OVERRIDE :: reserved2 [11:10] */ 969 #define DDR23_PHY_ADDR_CTL_DYNAMIC_VDL_OVERRIDE_RESERVED2_MASK 0x00000c00 970 #define DDR23_PHY_ADDR_CTL_DYNAMIC_VDL_OVERRIDE_RESERVED2_ALIGN 0 971 #define DDR23_PHY_ADDR_CTL_DYNAMIC_VDL_OVERRIDE_RESERVED2_BITS 2 972 #define DDR23_PHY_ADDR_CTL_DYNAMIC_VDL_OVERRIDE_RESERVED2_SHIFT 10 973 974 /* DDR23_PHY_ADDR_CTL :: DYNAMIC_VDL_OVERRIDE :: ovr_fine_rise [09:08] */ 975 #define DDR23_PHY_ADDR_CTL_DYNAMIC_VDL_OVERRIDE_OVR_FINE_RISE_MASK 0x00000300 976 #define DDR23_PHY_ADDR_CTL_DYNAMIC_VDL_OVERRIDE_OVR_FINE_RISE_ALIGN 0 977 #define DDR23_PHY_ADDR_CTL_DYNAMIC_VDL_OVERRIDE_OVR_FINE_RISE_BITS 2 978 #define DDR23_PHY_ADDR_CTL_DYNAMIC_VDL_OVERRIDE_OVR_FINE_RISE_SHIFT 8 979 980 /* DDR23_PHY_ADDR_CTL :: DYNAMIC_VDL_OVERRIDE :: reserved3 [07:06] */ 981 #define DDR23_PHY_ADDR_CTL_DYNAMIC_VDL_OVERRIDE_RESERVED3_MASK 0x000000c0 982 #define DDR23_PHY_ADDR_CTL_DYNAMIC_VDL_OVERRIDE_RESERVED3_ALIGN 0 983 #define DDR23_PHY_ADDR_CTL_DYNAMIC_VDL_OVERRIDE_RESERVED3_BITS 2 984 #define DDR23_PHY_ADDR_CTL_DYNAMIC_VDL_OVERRIDE_RESERVED3_SHIFT 6 985 986 /* DDR23_PHY_ADDR_CTL :: DYNAMIC_VDL_OVERRIDE :: ovr_step [05:00] */ 987 #define DDR23_PHY_ADDR_CTL_DYNAMIC_VDL_OVERRIDE_OVR_STEP_MASK 0x0000003f 988 #define DDR23_PHY_ADDR_CTL_DYNAMIC_VDL_OVERRIDE_OVR_STEP_ALIGN 0 989 #define DDR23_PHY_ADDR_CTL_DYNAMIC_VDL_OVERRIDE_OVR_STEP_BITS 6 990 #define DDR23_PHY_ADDR_CTL_DYNAMIC_VDL_OVERRIDE_OVR_STEP_SHIFT 0 991 992 993 /**************************************************************************** 994 * DDR23_PHY_ADDR_CTL :: IDLE_PAD_CONTROL 995 */ 996 /* DDR23_PHY_ADDR_CTL :: IDLE_PAD_CONTROL :: idle [31:31] */ 997 #define DDR23_PHY_ADDR_CTL_IDLE_PAD_CONTROL_IDLE_MASK 0x80000000 998 #define DDR23_PHY_ADDR_CTL_IDLE_PAD_CONTROL_IDLE_ALIGN 0 999 #define DDR23_PHY_ADDR_CTL_IDLE_PAD_CONTROL_IDLE_BITS 1 1000 #define DDR23_PHY_ADDR_CTL_IDLE_PAD_CONTROL_IDLE_SHIFT 31 1001 1002 /* DDR23_PHY_ADDR_CTL :: IDLE_PAD_CONTROL :: reserved0 [30:09] */ 1003 #define DDR23_PHY_ADDR_CTL_IDLE_PAD_CONTROL_RESERVED0_MASK 0x7ffffe00 1004 #define DDR23_PHY_ADDR_CTL_IDLE_PAD_CONTROL_RESERVED0_ALIGN 0 1005 #define DDR23_PHY_ADDR_CTL_IDLE_PAD_CONTROL_RESERVED0_BITS 22 1006 #define DDR23_PHY_ADDR_CTL_IDLE_PAD_CONTROL_RESERVED0_SHIFT 9 1007 1008 /* DDR23_PHY_ADDR_CTL :: IDLE_PAD_CONTROL :: rxenb [08:08] */ 1009 #define DDR23_PHY_ADDR_CTL_IDLE_PAD_CONTROL_RXENB_MASK 0x00000100 1010 #define DDR23_PHY_ADDR_CTL_IDLE_PAD_CONTROL_RXENB_ALIGN 0 1011 #define DDR23_PHY_ADDR_CTL_IDLE_PAD_CONTROL_RXENB_BITS 1 1012 #define DDR23_PHY_ADDR_CTL_IDLE_PAD_CONTROL_RXENB_SHIFT 8 1013 1014 /* DDR23_PHY_ADDR_CTL :: IDLE_PAD_CONTROL :: reserved1 [07:07] */ 1015 #define DDR23_PHY_ADDR_CTL_IDLE_PAD_CONTROL_RESERVED1_MASK 0x00000080 1016 #define DDR23_PHY_ADDR_CTL_IDLE_PAD_CONTROL_RESERVED1_ALIGN 0 1017 #define DDR23_PHY_ADDR_CTL_IDLE_PAD_CONTROL_RESERVED1_BITS 1 1018 #define DDR23_PHY_ADDR_CTL_IDLE_PAD_CONTROL_RESERVED1_SHIFT 7 1019 1020 /* DDR23_PHY_ADDR_CTL :: IDLE_PAD_CONTROL :: ctl_iddq [06:06] */ 1021 #define DDR23_PHY_ADDR_CTL_IDLE_PAD_CONTROL_CTL_IDDQ_MASK 0x00000040 1022 #define DDR23_PHY_ADDR_CTL_IDLE_PAD_CONTROL_CTL_IDDQ_ALIGN 0 1023 #define DDR23_PHY_ADDR_CTL_IDLE_PAD_CONTROL_CTL_IDDQ_BITS 1 1024 #define DDR23_PHY_ADDR_CTL_IDLE_PAD_CONTROL_CTL_IDDQ_SHIFT 6 1025 1026 /* DDR23_PHY_ADDR_CTL :: IDLE_PAD_CONTROL :: ctl_reb [05:05] */ 1027 #define DDR23_PHY_ADDR_CTL_IDLE_PAD_CONTROL_CTL_REB_MASK 0x00000020 1028 #define DDR23_PHY_ADDR_CTL_IDLE_PAD_CONTROL_CTL_REB_ALIGN 0 1029 #define DDR23_PHY_ADDR_CTL_IDLE_PAD_CONTROL_CTL_REB_BITS 1 1030 #define DDR23_PHY_ADDR_CTL_IDLE_PAD_CONTROL_CTL_REB_SHIFT 5 1031 1032 /* DDR23_PHY_ADDR_CTL :: IDLE_PAD_CONTROL :: ctl_oeb [04:04] */ 1033 #define DDR23_PHY_ADDR_CTL_IDLE_PAD_CONTROL_CTL_OEB_MASK 0x00000010 1034 #define DDR23_PHY_ADDR_CTL_IDLE_PAD_CONTROL_CTL_OEB_ALIGN 0 1035 #define DDR23_PHY_ADDR_CTL_IDLE_PAD_CONTROL_CTL_OEB_BITS 1 1036 #define DDR23_PHY_ADDR_CTL_IDLE_PAD_CONTROL_CTL_OEB_SHIFT 4 1037 1038 /* DDR23_PHY_ADDR_CTL :: IDLE_PAD_CONTROL :: reserved2 [03:03] */ 1039 #define DDR23_PHY_ADDR_CTL_IDLE_PAD_CONTROL_RESERVED2_MASK 0x00000008 1040 #define DDR23_PHY_ADDR_CTL_IDLE_PAD_CONTROL_RESERVED2_ALIGN 0 1041 #define DDR23_PHY_ADDR_CTL_IDLE_PAD_CONTROL_RESERVED2_BITS 1 1042 #define DDR23_PHY_ADDR_CTL_IDLE_PAD_CONTROL_RESERVED2_SHIFT 3 1043 1044 /* DDR23_PHY_ADDR_CTL :: IDLE_PAD_CONTROL :: cke_iddq [02:02] */ 1045 #define DDR23_PHY_ADDR_CTL_IDLE_PAD_CONTROL_CKE_IDDQ_MASK 0x00000004 1046 #define DDR23_PHY_ADDR_CTL_IDLE_PAD_CONTROL_CKE_IDDQ_ALIGN 0 1047 #define DDR23_PHY_ADDR_CTL_IDLE_PAD_CONTROL_CKE_IDDQ_BITS 1 1048 #define DDR23_PHY_ADDR_CTL_IDLE_PAD_CONTROL_CKE_IDDQ_SHIFT 2 1049 1050 /* DDR23_PHY_ADDR_CTL :: IDLE_PAD_CONTROL :: cke_reb [01:01] */ 1051 #define DDR23_PHY_ADDR_CTL_IDLE_PAD_CONTROL_CKE_REB_MASK 0x00000002 1052 #define DDR23_PHY_ADDR_CTL_IDLE_PAD_CONTROL_CKE_REB_ALIGN 0 1053 #define DDR23_PHY_ADDR_CTL_IDLE_PAD_CONTROL_CKE_REB_BITS 1 1054 #define DDR23_PHY_ADDR_CTL_IDLE_PAD_CONTROL_CKE_REB_SHIFT 1 1055 1056 /* DDR23_PHY_ADDR_CTL :: IDLE_PAD_CONTROL :: cke_oeb [00:00] */ 1057 #define DDR23_PHY_ADDR_CTL_IDLE_PAD_CONTROL_CKE_OEB_MASK 0x00000001 1058 #define DDR23_PHY_ADDR_CTL_IDLE_PAD_CONTROL_CKE_OEB_ALIGN 0 1059 #define DDR23_PHY_ADDR_CTL_IDLE_PAD_CONTROL_CKE_OEB_BITS 1 1060 #define DDR23_PHY_ADDR_CTL_IDLE_PAD_CONTROL_CKE_OEB_SHIFT 0 1061 1062 1063 /**************************************************************************** 1064 * DDR23_PHY_ADDR_CTL :: ZQ_PVT_COMP_CTL 1065 */ 1066 /* DDR23_PHY_ADDR_CTL :: ZQ_PVT_COMP_CTL :: reserved0 [31:31] */ 1067 #define DDR23_PHY_ADDR_CTL_ZQ_PVT_COMP_CTL_RESERVED0_MASK 0x80000000 1068 #define DDR23_PHY_ADDR_CTL_ZQ_PVT_COMP_CTL_RESERVED0_ALIGN 0 1069 #define DDR23_PHY_ADDR_CTL_ZQ_PVT_COMP_CTL_RESERVED0_BITS 1 1070 #define DDR23_PHY_ADDR_CTL_ZQ_PVT_COMP_CTL_RESERVED0_SHIFT 31 1071 1072 /* DDR23_PHY_ADDR_CTL :: ZQ_PVT_COMP_CTL :: pd_done [30:30] */ 1073 #define DDR23_PHY_ADDR_CTL_ZQ_PVT_COMP_CTL_PD_DONE_MASK 0x40000000 1074 #define DDR23_PHY_ADDR_CTL_ZQ_PVT_COMP_CTL_PD_DONE_ALIGN 0 1075 #define DDR23_PHY_ADDR_CTL_ZQ_PVT_COMP_CTL_PD_DONE_BITS 1 1076 #define DDR23_PHY_ADDR_CTL_ZQ_PVT_COMP_CTL_PD_DONE_SHIFT 30 1077 1078 /* DDR23_PHY_ADDR_CTL :: ZQ_PVT_COMP_CTL :: nd_done [29:29] */ 1079 #define DDR23_PHY_ADDR_CTL_ZQ_PVT_COMP_CTL_ND_DONE_MASK 0x20000000 1080 #define DDR23_PHY_ADDR_CTL_ZQ_PVT_COMP_CTL_ND_DONE_ALIGN 0 1081 #define DDR23_PHY_ADDR_CTL_ZQ_PVT_COMP_CTL_ND_DONE_BITS 1 1082 #define DDR23_PHY_ADDR_CTL_ZQ_PVT_COMP_CTL_ND_DONE_SHIFT 29 1083 1084 /* DDR23_PHY_ADDR_CTL :: ZQ_PVT_COMP_CTL :: sample_done [28:28] */ 1085 #define DDR23_PHY_ADDR_CTL_ZQ_PVT_COMP_CTL_SAMPLE_DONE_MASK 0x10000000 1086 #define DDR23_PHY_ADDR_CTL_ZQ_PVT_COMP_CTL_SAMPLE_DONE_ALIGN 0 1087 #define DDR23_PHY_ADDR_CTL_ZQ_PVT_COMP_CTL_SAMPLE_DONE_BITS 1 1088 #define DDR23_PHY_ADDR_CTL_ZQ_PVT_COMP_CTL_SAMPLE_DONE_SHIFT 28 1089 1090 /* DDR23_PHY_ADDR_CTL :: ZQ_PVT_COMP_CTL :: auto_sample_en [27:27] */ 1091 #define DDR23_PHY_ADDR_CTL_ZQ_PVT_COMP_CTL_AUTO_SAMPLE_EN_MASK 0x08000000 1092 #define DDR23_PHY_ADDR_CTL_ZQ_PVT_COMP_CTL_AUTO_SAMPLE_EN_ALIGN 0 1093 #define DDR23_PHY_ADDR_CTL_ZQ_PVT_COMP_CTL_AUTO_SAMPLE_EN_BITS 1 1094 #define DDR23_PHY_ADDR_CTL_ZQ_PVT_COMP_CTL_AUTO_SAMPLE_EN_SHIFT 27 1095 1096 /* DDR23_PHY_ADDR_CTL :: ZQ_PVT_COMP_CTL :: sample_en [26:26] */ 1097 #define DDR23_PHY_ADDR_CTL_ZQ_PVT_COMP_CTL_SAMPLE_EN_MASK 0x04000000 1098 #define DDR23_PHY_ADDR_CTL_ZQ_PVT_COMP_CTL_SAMPLE_EN_ALIGN 0 1099 #define DDR23_PHY_ADDR_CTL_ZQ_PVT_COMP_CTL_SAMPLE_EN_BITS 1 1100 #define DDR23_PHY_ADDR_CTL_ZQ_PVT_COMP_CTL_SAMPLE_EN_SHIFT 26 1101 1102 /* DDR23_PHY_ADDR_CTL :: ZQ_PVT_COMP_CTL :: addr_ovr_en [25:25] */ 1103 #define DDR23_PHY_ADDR_CTL_ZQ_PVT_COMP_CTL_ADDR_OVR_EN_MASK 0x02000000 1104 #define DDR23_PHY_ADDR_CTL_ZQ_PVT_COMP_CTL_ADDR_OVR_EN_ALIGN 0 1105 #define DDR23_PHY_ADDR_CTL_ZQ_PVT_COMP_CTL_ADDR_OVR_EN_BITS 1 1106 #define DDR23_PHY_ADDR_CTL_ZQ_PVT_COMP_CTL_ADDR_OVR_EN_SHIFT 25 1107 1108 /* DDR23_PHY_ADDR_CTL :: ZQ_PVT_COMP_CTL :: dq_ovr_en [24:24] */ 1109 #define DDR23_PHY_ADDR_CTL_ZQ_PVT_COMP_CTL_DQ_OVR_EN_MASK 0x01000000 1110 #define DDR23_PHY_ADDR_CTL_ZQ_PVT_COMP_CTL_DQ_OVR_EN_ALIGN 0 1111 #define DDR23_PHY_ADDR_CTL_ZQ_PVT_COMP_CTL_DQ_OVR_EN_BITS 1 1112 #define DDR23_PHY_ADDR_CTL_ZQ_PVT_COMP_CTL_DQ_OVR_EN_SHIFT 24 1113 1114 /* DDR23_PHY_ADDR_CTL :: ZQ_PVT_COMP_CTL :: pd_comp [23:20] */ 1115 #define DDR23_PHY_ADDR_CTL_ZQ_PVT_COMP_CTL_PD_COMP_MASK 0x00f00000 1116 #define DDR23_PHY_ADDR_CTL_ZQ_PVT_COMP_CTL_PD_COMP_ALIGN 0 1117 #define DDR23_PHY_ADDR_CTL_ZQ_PVT_COMP_CTL_PD_COMP_BITS 4 1118 #define DDR23_PHY_ADDR_CTL_ZQ_PVT_COMP_CTL_PD_COMP_SHIFT 20 1119 1120 /* DDR23_PHY_ADDR_CTL :: ZQ_PVT_COMP_CTL :: nd_comp [19:16] */ 1121 #define DDR23_PHY_ADDR_CTL_ZQ_PVT_COMP_CTL_ND_COMP_MASK 0x000f0000 1122 #define DDR23_PHY_ADDR_CTL_ZQ_PVT_COMP_CTL_ND_COMP_ALIGN 0 1123 #define DDR23_PHY_ADDR_CTL_ZQ_PVT_COMP_CTL_ND_COMP_BITS 4 1124 #define DDR23_PHY_ADDR_CTL_ZQ_PVT_COMP_CTL_ND_COMP_SHIFT 16 1125 1126 /* DDR23_PHY_ADDR_CTL :: ZQ_PVT_COMP_CTL :: addr_pd_override_val [15:12] */ 1127 #define DDR23_PHY_ADDR_CTL_ZQ_PVT_COMP_CTL_ADDR_PD_OVERRIDE_VAL_MASK 0x0000f000 1128 #define DDR23_PHY_ADDR_CTL_ZQ_PVT_COMP_CTL_ADDR_PD_OVERRIDE_VAL_ALIGN 0 1129 #define DDR23_PHY_ADDR_CTL_ZQ_PVT_COMP_CTL_ADDR_PD_OVERRIDE_VAL_BITS 4 1130 #define DDR23_PHY_ADDR_CTL_ZQ_PVT_COMP_CTL_ADDR_PD_OVERRIDE_VAL_SHIFT 12 1131 1132 /* DDR23_PHY_ADDR_CTL :: ZQ_PVT_COMP_CTL :: addr_nd_override_val [11:08] */ 1133 #define DDR23_PHY_ADDR_CTL_ZQ_PVT_COMP_CTL_ADDR_ND_OVERRIDE_VAL_MASK 0x00000f00 1134 #define DDR23_PHY_ADDR_CTL_ZQ_PVT_COMP_CTL_ADDR_ND_OVERRIDE_VAL_ALIGN 0 1135 #define DDR23_PHY_ADDR_CTL_ZQ_PVT_COMP_CTL_ADDR_ND_OVERRIDE_VAL_BITS 4 1136 #define DDR23_PHY_ADDR_CTL_ZQ_PVT_COMP_CTL_ADDR_ND_OVERRIDE_VAL_SHIFT 8 1137 1138 /* DDR23_PHY_ADDR_CTL :: ZQ_PVT_COMP_CTL :: dq_pd_override_val [07:04] */ 1139 #define DDR23_PHY_ADDR_CTL_ZQ_PVT_COMP_CTL_DQ_PD_OVERRIDE_VAL_MASK 0x000000f0 1140 #define DDR23_PHY_ADDR_CTL_ZQ_PVT_COMP_CTL_DQ_PD_OVERRIDE_VAL_ALIGN 0 1141 #define DDR23_PHY_ADDR_CTL_ZQ_PVT_COMP_CTL_DQ_PD_OVERRIDE_VAL_BITS 4 1142 #define DDR23_PHY_ADDR_CTL_ZQ_PVT_COMP_CTL_DQ_PD_OVERRIDE_VAL_SHIFT 4 1143 1144 /* DDR23_PHY_ADDR_CTL :: ZQ_PVT_COMP_CTL :: dq_nd_override_val [03:00] */ 1145 #define DDR23_PHY_ADDR_CTL_ZQ_PVT_COMP_CTL_DQ_ND_OVERRIDE_VAL_MASK 0x0000000f 1146 #define DDR23_PHY_ADDR_CTL_ZQ_PVT_COMP_CTL_DQ_ND_OVERRIDE_VAL_ALIGN 0 1147 #define DDR23_PHY_ADDR_CTL_ZQ_PVT_COMP_CTL_DQ_ND_OVERRIDE_VAL_BITS 4 1148 #define DDR23_PHY_ADDR_CTL_ZQ_PVT_COMP_CTL_DQ_ND_OVERRIDE_VAL_SHIFT 0 1149 1150 1151 /**************************************************************************** 1152 * DDR23_PHY_ADDR_CTL :: DRIVE_PAD_CTL 1153 */ 1154 /* DDR23_PHY_ADDR_CTL :: DRIVE_PAD_CTL :: reserved0 [31:05] */ 1155 #define DDR23_PHY_ADDR_CTL_DRIVE_PAD_CTL_RESERVED0_MASK 0xffffffe0 1156 #define DDR23_PHY_ADDR_CTL_DRIVE_PAD_CTL_RESERVED0_ALIGN 0 1157 #define DDR23_PHY_ADDR_CTL_DRIVE_PAD_CTL_RESERVED0_BITS 27 1158 #define DDR23_PHY_ADDR_CTL_DRIVE_PAD_CTL_RESERVED0_SHIFT 5 1159 1160 /* DDR23_PHY_ADDR_CTL :: DRIVE_PAD_CTL :: rt60b [04:04] */ 1161 #define DDR23_PHY_ADDR_CTL_DRIVE_PAD_CTL_RT60B_MASK 0x00000010 1162 #define DDR23_PHY_ADDR_CTL_DRIVE_PAD_CTL_RT60B_ALIGN 0 1163 #define DDR23_PHY_ADDR_CTL_DRIVE_PAD_CTL_RT60B_BITS 1 1164 #define DDR23_PHY_ADDR_CTL_DRIVE_PAD_CTL_RT60B_SHIFT 4 1165 1166 /* DDR23_PHY_ADDR_CTL :: DRIVE_PAD_CTL :: sel_sstl18 [03:03] */ 1167 #define DDR23_PHY_ADDR_CTL_DRIVE_PAD_CTL_SEL_SSTL18_MASK 0x00000008 1168 #define DDR23_PHY_ADDR_CTL_DRIVE_PAD_CTL_SEL_SSTL18_ALIGN 0 1169 #define DDR23_PHY_ADDR_CTL_DRIVE_PAD_CTL_SEL_SSTL18_BITS 1 1170 #define DDR23_PHY_ADDR_CTL_DRIVE_PAD_CTL_SEL_SSTL18_SHIFT 3 1171 1172 /* DDR23_PHY_ADDR_CTL :: DRIVE_PAD_CTL :: seltxdrv_ci [02:02] */ 1173 #define DDR23_PHY_ADDR_CTL_DRIVE_PAD_CTL_SELTXDRV_CI_MASK 0x00000004 1174 #define DDR23_PHY_ADDR_CTL_DRIVE_PAD_CTL_SELTXDRV_CI_ALIGN 0 1175 #define DDR23_PHY_ADDR_CTL_DRIVE_PAD_CTL_SELTXDRV_CI_BITS 1 1176 #define DDR23_PHY_ADDR_CTL_DRIVE_PAD_CTL_SELTXDRV_CI_SHIFT 2 1177 1178 /* DDR23_PHY_ADDR_CTL :: DRIVE_PAD_CTL :: selrxdrv [01:01] */ 1179 #define DDR23_PHY_ADDR_CTL_DRIVE_PAD_CTL_SELRXDRV_MASK 0x00000002 1180 #define DDR23_PHY_ADDR_CTL_DRIVE_PAD_CTL_SELRXDRV_ALIGN 0 1181 #define DDR23_PHY_ADDR_CTL_DRIVE_PAD_CTL_SELRXDRV_BITS 1 1182 #define DDR23_PHY_ADDR_CTL_DRIVE_PAD_CTL_SELRXDRV_SHIFT 1 1183 1184 /* DDR23_PHY_ADDR_CTL :: DRIVE_PAD_CTL :: slew [00:00] */ 1185 #define DDR23_PHY_ADDR_CTL_DRIVE_PAD_CTL_SLEW_MASK 0x00000001 1186 #define DDR23_PHY_ADDR_CTL_DRIVE_PAD_CTL_SLEW_ALIGN 0 1187 #define DDR23_PHY_ADDR_CTL_DRIVE_PAD_CTL_SLEW_BITS 1 1188 #define DDR23_PHY_ADDR_CTL_DRIVE_PAD_CTL_SLEW_SHIFT 0 1189 1190 1191 /**************************************************************************** 1192 * DDR23_PHY_ADDR_CTL :: CLOCK_REG_CONTROL 1193 */ 1194 /* DDR23_PHY_ADDR_CTL :: CLOCK_REG_CONTROL :: reserved0 [31:02] */ 1195 #define DDR23_PHY_ADDR_CTL_CLOCK_REG_CONTROL_RESERVED0_MASK 0xfffffffc 1196 #define DDR23_PHY_ADDR_CTL_CLOCK_REG_CONTROL_RESERVED0_ALIGN 0 1197 #define DDR23_PHY_ADDR_CTL_CLOCK_REG_CONTROL_RESERVED0_BITS 30 1198 #define DDR23_PHY_ADDR_CTL_CLOCK_REG_CONTROL_RESERVED0_SHIFT 2 1199 1200 /* DDR23_PHY_ADDR_CTL :: CLOCK_REG_CONTROL :: half_power [01:01] */ 1201 #define DDR23_PHY_ADDR_CTL_CLOCK_REG_CONTROL_HALF_POWER_MASK 0x00000002 1202 #define DDR23_PHY_ADDR_CTL_CLOCK_REG_CONTROL_HALF_POWER_ALIGN 0 1203 #define DDR23_PHY_ADDR_CTL_CLOCK_REG_CONTROL_HALF_POWER_BITS 1 1204 #define DDR23_PHY_ADDR_CTL_CLOCK_REG_CONTROL_HALF_POWER_SHIFT 1 1205 1206 /* DDR23_PHY_ADDR_CTL :: CLOCK_REG_CONTROL :: pwrdn [00:00] */ 1207 #define DDR23_PHY_ADDR_CTL_CLOCK_REG_CONTROL_PWRDN_MASK 0x00000001 1208 #define DDR23_PHY_ADDR_CTL_CLOCK_REG_CONTROL_PWRDN_ALIGN 0 1209 #define DDR23_PHY_ADDR_CTL_CLOCK_REG_CONTROL_PWRDN_BITS 1 1210 #define DDR23_PHY_ADDR_CTL_CLOCK_REG_CONTROL_PWRDN_SHIFT 0 1211 1212 1213 /**************************************************************************** 1214 * DDR23_PHY_DDR23_PHY_BYTE_LANE0 1215 */ 1216 /**************************************************************************** 1217 * DDR23_PHY_BYTE_LANE0 :: REVISION 1218 */ 1219 /* DDR23_PHY_BYTE_LANE0 :: REVISION :: reserved0 [31:16] */ 1220 #define DDR23_PHY_BYTE_LANE0_REVISION_RESERVED0_MASK 0xffff0000 1221 #define DDR23_PHY_BYTE_LANE0_REVISION_RESERVED0_ALIGN 0 1222 #define DDR23_PHY_BYTE_LANE0_REVISION_RESERVED0_BITS 16 1223 #define DDR23_PHY_BYTE_LANE0_REVISION_RESERVED0_SHIFT 16 1224 1225 /* DDR23_PHY_BYTE_LANE0 :: REVISION :: MAJOR [15:08] */ 1226 #define DDR23_PHY_BYTE_LANE0_REVISION_MAJOR_MASK 0x0000ff00 1227 #define DDR23_PHY_BYTE_LANE0_REVISION_MAJOR_ALIGN 0 1228 #define DDR23_PHY_BYTE_LANE0_REVISION_MAJOR_BITS 8 1229 #define DDR23_PHY_BYTE_LANE0_REVISION_MAJOR_SHIFT 8 1230 1231 /* DDR23_PHY_BYTE_LANE0 :: REVISION :: MINOR [07:00] */ 1232 #define DDR23_PHY_BYTE_LANE0_REVISION_MINOR_MASK 0x000000ff 1233 #define DDR23_PHY_BYTE_LANE0_REVISION_MINOR_ALIGN 0 1234 #define DDR23_PHY_BYTE_LANE0_REVISION_MINOR_BITS 8 1235 #define DDR23_PHY_BYTE_LANE0_REVISION_MINOR_SHIFT 0 1236 1237 1238 /**************************************************************************** 1239 * DDR23_PHY_BYTE_LANE0 :: VDL_CALIBRATE 1240 */ 1241 /* DDR23_PHY_BYTE_LANE0 :: VDL_CALIBRATE :: reserved0 [31:05] */ 1242 #define DDR23_PHY_BYTE_LANE0_VDL_CALIBRATE_RESERVED0_MASK 0xffffffe0 1243 #define DDR23_PHY_BYTE_LANE0_VDL_CALIBRATE_RESERVED0_ALIGN 0 1244 #define DDR23_PHY_BYTE_LANE0_VDL_CALIBRATE_RESERVED0_BITS 27 1245 #define DDR23_PHY_BYTE_LANE0_VDL_CALIBRATE_RESERVED0_SHIFT 5 1246 1247 /* DDR23_PHY_BYTE_LANE0 :: VDL_CALIBRATE :: calib_clocks [04:04] */ 1248 #define DDR23_PHY_BYTE_LANE0_VDL_CALIBRATE_CALIB_CLOCKS_MASK 0x00000010 1249 #define DDR23_PHY_BYTE_LANE0_VDL_CALIBRATE_CALIB_CLOCKS_ALIGN 0 1250 #define DDR23_PHY_BYTE_LANE0_VDL_CALIBRATE_CALIB_CLOCKS_BITS 1 1251 #define DDR23_PHY_BYTE_LANE0_VDL_CALIBRATE_CALIB_CLOCKS_SHIFT 4 1252 1253 /* DDR23_PHY_BYTE_LANE0 :: VDL_CALIBRATE :: calib_test [03:03] */ 1254 #define DDR23_PHY_BYTE_LANE0_VDL_CALIBRATE_CALIB_TEST_MASK 0x00000008 1255 #define DDR23_PHY_BYTE_LANE0_VDL_CALIBRATE_CALIB_TEST_ALIGN 0 1256 #define DDR23_PHY_BYTE_LANE0_VDL_CALIBRATE_CALIB_TEST_BITS 1 1257 #define DDR23_PHY_BYTE_LANE0_VDL_CALIBRATE_CALIB_TEST_SHIFT 3 1258 1259 /* DDR23_PHY_BYTE_LANE0 :: VDL_CALIBRATE :: calib_always [02:02] */ 1260 #define DDR23_PHY_BYTE_LANE0_VDL_CALIBRATE_CALIB_ALWAYS_MASK 0x00000004 1261 #define DDR23_PHY_BYTE_LANE0_VDL_CALIBRATE_CALIB_ALWAYS_ALIGN 0 1262 #define DDR23_PHY_BYTE_LANE0_VDL_CALIBRATE_CALIB_ALWAYS_BITS 1 1263 #define DDR23_PHY_BYTE_LANE0_VDL_CALIBRATE_CALIB_ALWAYS_SHIFT 2 1264 1265 /* DDR23_PHY_BYTE_LANE0 :: VDL_CALIBRATE :: calib_once [01:01] */ 1266 #define DDR23_PHY_BYTE_LANE0_VDL_CALIBRATE_CALIB_ONCE_MASK 0x00000002 1267 #define DDR23_PHY_BYTE_LANE0_VDL_CALIBRATE_CALIB_ONCE_ALIGN 0 1268 #define DDR23_PHY_BYTE_LANE0_VDL_CALIBRATE_CALIB_ONCE_BITS 1 1269 #define DDR23_PHY_BYTE_LANE0_VDL_CALIBRATE_CALIB_ONCE_SHIFT 1 1270 1271 /* DDR23_PHY_BYTE_LANE0 :: VDL_CALIBRATE :: calib_fast [00:00] */ 1272 #define DDR23_PHY_BYTE_LANE0_VDL_CALIBRATE_CALIB_FAST_MASK 0x00000001 1273 #define DDR23_PHY_BYTE_LANE0_VDL_CALIBRATE_CALIB_FAST_ALIGN 0 1274 #define DDR23_PHY_BYTE_LANE0_VDL_CALIBRATE_CALIB_FAST_BITS 1 1275 #define DDR23_PHY_BYTE_LANE0_VDL_CALIBRATE_CALIB_FAST_SHIFT 0 1276 1277 1278 /**************************************************************************** 1279 * DDR23_PHY_BYTE_LANE0 :: VDL_STATUS 1280 */ 1281 /* DDR23_PHY_BYTE_LANE0 :: VDL_STATUS :: reserved0 [31:14] */ 1282 #define DDR23_PHY_BYTE_LANE0_VDL_STATUS_RESERVED0_MASK 0xffffc000 1283 #define DDR23_PHY_BYTE_LANE0_VDL_STATUS_RESERVED0_ALIGN 0 1284 #define DDR23_PHY_BYTE_LANE0_VDL_STATUS_RESERVED0_BITS 18 1285 #define DDR23_PHY_BYTE_LANE0_VDL_STATUS_RESERVED0_SHIFT 14 1286 1287 /* DDR23_PHY_BYTE_LANE0 :: VDL_STATUS :: calib_total [13:04] */ 1288 #define DDR23_PHY_BYTE_LANE0_VDL_STATUS_CALIB_TOTAL_MASK 0x00003ff0 1289 #define DDR23_PHY_BYTE_LANE0_VDL_STATUS_CALIB_TOTAL_ALIGN 0 1290 #define DDR23_PHY_BYTE_LANE0_VDL_STATUS_CALIB_TOTAL_BITS 10 1291 #define DDR23_PHY_BYTE_LANE0_VDL_STATUS_CALIB_TOTAL_SHIFT 4 1292 1293 /* DDR23_PHY_BYTE_LANE0 :: VDL_STATUS :: reserved1 [03:02] */ 1294 #define DDR23_PHY_BYTE_LANE0_VDL_STATUS_RESERVED1_MASK 0x0000000c 1295 #define DDR23_PHY_BYTE_LANE0_VDL_STATUS_RESERVED1_ALIGN 0 1296 #define DDR23_PHY_BYTE_LANE0_VDL_STATUS_RESERVED1_BITS 2 1297 #define DDR23_PHY_BYTE_LANE0_VDL_STATUS_RESERVED1_SHIFT 2 1298 1299 /* DDR23_PHY_BYTE_LANE0 :: VDL_STATUS :: calib_lock [01:01] */ 1300 #define DDR23_PHY_BYTE_LANE0_VDL_STATUS_CALIB_LOCK_MASK 0x00000002 1301 #define DDR23_PHY_BYTE_LANE0_VDL_STATUS_CALIB_LOCK_ALIGN 0 1302 #define DDR23_PHY_BYTE_LANE0_VDL_STATUS_CALIB_LOCK_BITS 1 1303 #define DDR23_PHY_BYTE_LANE0_VDL_STATUS_CALIB_LOCK_SHIFT 1 1304 1305 /* DDR23_PHY_BYTE_LANE0 :: VDL_STATUS :: calib_idle [00:00] */ 1306 #define DDR23_PHY_BYTE_LANE0_VDL_STATUS_CALIB_IDLE_MASK 0x00000001 1307 #define DDR23_PHY_BYTE_LANE0_VDL_STATUS_CALIB_IDLE_ALIGN 0 1308 #define DDR23_PHY_BYTE_LANE0_VDL_STATUS_CALIB_IDLE_BITS 1 1309 #define DDR23_PHY_BYTE_LANE0_VDL_STATUS_CALIB_IDLE_SHIFT 0 1310 1311 1312 /**************************************************************************** 1313 * DDR23_PHY_BYTE_LANE0 :: VDL_OVERRIDE_0 1314 */ 1315 /* DDR23_PHY_BYTE_LANE0 :: VDL_OVERRIDE_0 :: reserved0 [31:17] */ 1316 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_0_RESERVED0_MASK 0xfffe0000 1317 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_0_RESERVED0_ALIGN 0 1318 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_0_RESERVED0_BITS 15 1319 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_0_RESERVED0_SHIFT 17 1320 1321 /* DDR23_PHY_BYTE_LANE0 :: VDL_OVERRIDE_0 :: ovr_en [16:16] */ 1322 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_0_OVR_EN_MASK 0x00010000 1323 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_0_OVR_EN_ALIGN 0 1324 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_0_OVR_EN_BITS 1 1325 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_0_OVR_EN_SHIFT 16 1326 1327 /* DDR23_PHY_BYTE_LANE0 :: VDL_OVERRIDE_0 :: reserved1 [15:14] */ 1328 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_0_RESERVED1_MASK 0x0000c000 1329 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_0_RESERVED1_ALIGN 0 1330 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_0_RESERVED1_BITS 2 1331 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_0_RESERVED1_SHIFT 14 1332 1333 /* DDR23_PHY_BYTE_LANE0 :: VDL_OVERRIDE_0 :: ovr_fine_fall [13:12] */ 1334 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_0_OVR_FINE_FALL_MASK 0x00003000 1335 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_0_OVR_FINE_FALL_ALIGN 0 1336 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_0_OVR_FINE_FALL_BITS 2 1337 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_0_OVR_FINE_FALL_SHIFT 12 1338 1339 /* DDR23_PHY_BYTE_LANE0 :: VDL_OVERRIDE_0 :: reserved2 [11:10] */ 1340 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_0_RESERVED2_MASK 0x00000c00 1341 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_0_RESERVED2_ALIGN 0 1342 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_0_RESERVED2_BITS 2 1343 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_0_RESERVED2_SHIFT 10 1344 1345 /* DDR23_PHY_BYTE_LANE0 :: VDL_OVERRIDE_0 :: ovr_fine_rise [09:08] */ 1346 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_0_OVR_FINE_RISE_MASK 0x00000300 1347 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_0_OVR_FINE_RISE_ALIGN 0 1348 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_0_OVR_FINE_RISE_BITS 2 1349 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_0_OVR_FINE_RISE_SHIFT 8 1350 1351 /* DDR23_PHY_BYTE_LANE0 :: VDL_OVERRIDE_0 :: reserved3 [07:06] */ 1352 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_0_RESERVED3_MASK 0x000000c0 1353 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_0_RESERVED3_ALIGN 0 1354 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_0_RESERVED3_BITS 2 1355 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_0_RESERVED3_SHIFT 6 1356 1357 /* DDR23_PHY_BYTE_LANE0 :: VDL_OVERRIDE_0 :: ovr_step [05:00] */ 1358 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_0_OVR_STEP_MASK 0x0000003f 1359 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_0_OVR_STEP_ALIGN 0 1360 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_0_OVR_STEP_BITS 6 1361 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_0_OVR_STEP_SHIFT 0 1362 1363 1364 /**************************************************************************** 1365 * DDR23_PHY_BYTE_LANE0 :: VDL_OVERRIDE_1 1366 */ 1367 /* DDR23_PHY_BYTE_LANE0 :: VDL_OVERRIDE_1 :: reserved0 [31:17] */ 1368 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_1_RESERVED0_MASK 0xfffe0000 1369 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_1_RESERVED0_ALIGN 0 1370 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_1_RESERVED0_BITS 15 1371 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_1_RESERVED0_SHIFT 17 1372 1373 /* DDR23_PHY_BYTE_LANE0 :: VDL_OVERRIDE_1 :: ovr_en [16:16] */ 1374 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_1_OVR_EN_MASK 0x00010000 1375 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_1_OVR_EN_ALIGN 0 1376 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_1_OVR_EN_BITS 1 1377 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_1_OVR_EN_SHIFT 16 1378 1379 /* DDR23_PHY_BYTE_LANE0 :: VDL_OVERRIDE_1 :: reserved1 [15:14] */ 1380 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_1_RESERVED1_MASK 0x0000c000 1381 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_1_RESERVED1_ALIGN 0 1382 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_1_RESERVED1_BITS 2 1383 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_1_RESERVED1_SHIFT 14 1384 1385 /* DDR23_PHY_BYTE_LANE0 :: VDL_OVERRIDE_1 :: ovr_fine_fall [13:12] */ 1386 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_1_OVR_FINE_FALL_MASK 0x00003000 1387 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_1_OVR_FINE_FALL_ALIGN 0 1388 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_1_OVR_FINE_FALL_BITS 2 1389 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_1_OVR_FINE_FALL_SHIFT 12 1390 1391 /* DDR23_PHY_BYTE_LANE0 :: VDL_OVERRIDE_1 :: reserved2 [11:10] */ 1392 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_1_RESERVED2_MASK 0x00000c00 1393 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_1_RESERVED2_ALIGN 0 1394 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_1_RESERVED2_BITS 2 1395 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_1_RESERVED2_SHIFT 10 1396 1397 /* DDR23_PHY_BYTE_LANE0 :: VDL_OVERRIDE_1 :: ovr_fine_rise [09:08] */ 1398 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_1_OVR_FINE_RISE_MASK 0x00000300 1399 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_1_OVR_FINE_RISE_ALIGN 0 1400 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_1_OVR_FINE_RISE_BITS 2 1401 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_1_OVR_FINE_RISE_SHIFT 8 1402 1403 /* DDR23_PHY_BYTE_LANE0 :: VDL_OVERRIDE_1 :: reserved3 [07:06] */ 1404 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_1_RESERVED3_MASK 0x000000c0 1405 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_1_RESERVED3_ALIGN 0 1406 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_1_RESERVED3_BITS 2 1407 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_1_RESERVED3_SHIFT 6 1408 1409 /* DDR23_PHY_BYTE_LANE0 :: VDL_OVERRIDE_1 :: ovr_step [05:00] */ 1410 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_1_OVR_STEP_MASK 0x0000003f 1411 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_1_OVR_STEP_ALIGN 0 1412 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_1_OVR_STEP_BITS 6 1413 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_1_OVR_STEP_SHIFT 0 1414 1415 1416 /**************************************************************************** 1417 * DDR23_PHY_BYTE_LANE0 :: VDL_OVERRIDE_2 1418 */ 1419 /* DDR23_PHY_BYTE_LANE0 :: VDL_OVERRIDE_2 :: reserved0 [31:17] */ 1420 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_2_RESERVED0_MASK 0xfffe0000 1421 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_2_RESERVED0_ALIGN 0 1422 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_2_RESERVED0_BITS 15 1423 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_2_RESERVED0_SHIFT 17 1424 1425 /* DDR23_PHY_BYTE_LANE0 :: VDL_OVERRIDE_2 :: ovr_en [16:16] */ 1426 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_2_OVR_EN_MASK 0x00010000 1427 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_2_OVR_EN_ALIGN 0 1428 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_2_OVR_EN_BITS 1 1429 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_2_OVR_EN_SHIFT 16 1430 1431 /* DDR23_PHY_BYTE_LANE0 :: VDL_OVERRIDE_2 :: reserved1 [15:14] */ 1432 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_2_RESERVED1_MASK 0x0000c000 1433 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_2_RESERVED1_ALIGN 0 1434 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_2_RESERVED1_BITS 2 1435 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_2_RESERVED1_SHIFT 14 1436 1437 /* DDR23_PHY_BYTE_LANE0 :: VDL_OVERRIDE_2 :: ovr_fine_fall [13:12] */ 1438 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_2_OVR_FINE_FALL_MASK 0x00003000 1439 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_2_OVR_FINE_FALL_ALIGN 0 1440 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_2_OVR_FINE_FALL_BITS 2 1441 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_2_OVR_FINE_FALL_SHIFT 12 1442 1443 /* DDR23_PHY_BYTE_LANE0 :: VDL_OVERRIDE_2 :: reserved2 [11:10] */ 1444 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_2_RESERVED2_MASK 0x00000c00 1445 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_2_RESERVED2_ALIGN 0 1446 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_2_RESERVED2_BITS 2 1447 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_2_RESERVED2_SHIFT 10 1448 1449 /* DDR23_PHY_BYTE_LANE0 :: VDL_OVERRIDE_2 :: ovr_fine_rise [09:08] */ 1450 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_2_OVR_FINE_RISE_MASK 0x00000300 1451 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_2_OVR_FINE_RISE_ALIGN 0 1452 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_2_OVR_FINE_RISE_BITS 2 1453 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_2_OVR_FINE_RISE_SHIFT 8 1454 1455 /* DDR23_PHY_BYTE_LANE0 :: VDL_OVERRIDE_2 :: reserved3 [07:06] */ 1456 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_2_RESERVED3_MASK 0x000000c0 1457 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_2_RESERVED3_ALIGN 0 1458 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_2_RESERVED3_BITS 2 1459 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_2_RESERVED3_SHIFT 6 1460 1461 /* DDR23_PHY_BYTE_LANE0 :: VDL_OVERRIDE_2 :: ovr_step [05:00] */ 1462 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_2_OVR_STEP_MASK 0x0000003f 1463 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_2_OVR_STEP_ALIGN 0 1464 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_2_OVR_STEP_BITS 6 1465 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_2_OVR_STEP_SHIFT 0 1466 1467 1468 /**************************************************************************** 1469 * DDR23_PHY_BYTE_LANE0 :: VDL_OVERRIDE_3 1470 */ 1471 /* DDR23_PHY_BYTE_LANE0 :: VDL_OVERRIDE_3 :: reserved0 [31:17] */ 1472 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_3_RESERVED0_MASK 0xfffe0000 1473 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_3_RESERVED0_ALIGN 0 1474 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_3_RESERVED0_BITS 15 1475 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_3_RESERVED0_SHIFT 17 1476 1477 /* DDR23_PHY_BYTE_LANE0 :: VDL_OVERRIDE_3 :: ovr_en [16:16] */ 1478 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_3_OVR_EN_MASK 0x00010000 1479 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_3_OVR_EN_ALIGN 0 1480 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_3_OVR_EN_BITS 1 1481 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_3_OVR_EN_SHIFT 16 1482 1483 /* DDR23_PHY_BYTE_LANE0 :: VDL_OVERRIDE_3 :: reserved1 [15:14] */ 1484 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_3_RESERVED1_MASK 0x0000c000 1485 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_3_RESERVED1_ALIGN 0 1486 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_3_RESERVED1_BITS 2 1487 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_3_RESERVED1_SHIFT 14 1488 1489 /* DDR23_PHY_BYTE_LANE0 :: VDL_OVERRIDE_3 :: ovr_fine_fall [13:12] */ 1490 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_3_OVR_FINE_FALL_MASK 0x00003000 1491 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_3_OVR_FINE_FALL_ALIGN 0 1492 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_3_OVR_FINE_FALL_BITS 2 1493 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_3_OVR_FINE_FALL_SHIFT 12 1494 1495 /* DDR23_PHY_BYTE_LANE0 :: VDL_OVERRIDE_3 :: reserved2 [11:10] */ 1496 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_3_RESERVED2_MASK 0x00000c00 1497 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_3_RESERVED2_ALIGN 0 1498 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_3_RESERVED2_BITS 2 1499 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_3_RESERVED2_SHIFT 10 1500 1501 /* DDR23_PHY_BYTE_LANE0 :: VDL_OVERRIDE_3 :: ovr_fine_rise [09:08] */ 1502 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_3_OVR_FINE_RISE_MASK 0x00000300 1503 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_3_OVR_FINE_RISE_ALIGN 0 1504 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_3_OVR_FINE_RISE_BITS 2 1505 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_3_OVR_FINE_RISE_SHIFT 8 1506 1507 /* DDR23_PHY_BYTE_LANE0 :: VDL_OVERRIDE_3 :: reserved3 [07:06] */ 1508 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_3_RESERVED3_MASK 0x000000c0 1509 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_3_RESERVED3_ALIGN 0 1510 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_3_RESERVED3_BITS 2 1511 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_3_RESERVED3_SHIFT 6 1512 1513 /* DDR23_PHY_BYTE_LANE0 :: VDL_OVERRIDE_3 :: ovr_step [05:00] */ 1514 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_3_OVR_STEP_MASK 0x0000003f 1515 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_3_OVR_STEP_ALIGN 0 1516 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_3_OVR_STEP_BITS 6 1517 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_3_OVR_STEP_SHIFT 0 1518 1519 1520 /**************************************************************************** 1521 * DDR23_PHY_BYTE_LANE0 :: VDL_OVERRIDE_4 1522 */ 1523 /* DDR23_PHY_BYTE_LANE0 :: VDL_OVERRIDE_4 :: reserved0 [31:17] */ 1524 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_4_RESERVED0_MASK 0xfffe0000 1525 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_4_RESERVED0_ALIGN 0 1526 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_4_RESERVED0_BITS 15 1527 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_4_RESERVED0_SHIFT 17 1528 1529 /* DDR23_PHY_BYTE_LANE0 :: VDL_OVERRIDE_4 :: ovr_en [16:16] */ 1530 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_4_OVR_EN_MASK 0x00010000 1531 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_4_OVR_EN_ALIGN 0 1532 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_4_OVR_EN_BITS 1 1533 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_4_OVR_EN_SHIFT 16 1534 1535 /* DDR23_PHY_BYTE_LANE0 :: VDL_OVERRIDE_4 :: reserved1 [15:14] */ 1536 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_4_RESERVED1_MASK 0x0000c000 1537 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_4_RESERVED1_ALIGN 0 1538 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_4_RESERVED1_BITS 2 1539 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_4_RESERVED1_SHIFT 14 1540 1541 /* DDR23_PHY_BYTE_LANE0 :: VDL_OVERRIDE_4 :: ovr_fine_fall [13:12] */ 1542 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_4_OVR_FINE_FALL_MASK 0x00003000 1543 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_4_OVR_FINE_FALL_ALIGN 0 1544 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_4_OVR_FINE_FALL_BITS 2 1545 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_4_OVR_FINE_FALL_SHIFT 12 1546 1547 /* DDR23_PHY_BYTE_LANE0 :: VDL_OVERRIDE_4 :: reserved2 [11:10] */ 1548 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_4_RESERVED2_MASK 0x00000c00 1549 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_4_RESERVED2_ALIGN 0 1550 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_4_RESERVED2_BITS 2 1551 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_4_RESERVED2_SHIFT 10 1552 1553 /* DDR23_PHY_BYTE_LANE0 :: VDL_OVERRIDE_4 :: ovr_fine_rise [09:08] */ 1554 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_4_OVR_FINE_RISE_MASK 0x00000300 1555 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_4_OVR_FINE_RISE_ALIGN 0 1556 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_4_OVR_FINE_RISE_BITS 2 1557 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_4_OVR_FINE_RISE_SHIFT 8 1558 1559 /* DDR23_PHY_BYTE_LANE0 :: VDL_OVERRIDE_4 :: reserved3 [07:06] */ 1560 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_4_RESERVED3_MASK 0x000000c0 1561 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_4_RESERVED3_ALIGN 0 1562 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_4_RESERVED3_BITS 2 1563 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_4_RESERVED3_SHIFT 6 1564 1565 /* DDR23_PHY_BYTE_LANE0 :: VDL_OVERRIDE_4 :: ovr_step [05:00] */ 1566 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_4_OVR_STEP_MASK 0x0000003f 1567 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_4_OVR_STEP_ALIGN 0 1568 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_4_OVR_STEP_BITS 6 1569 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_4_OVR_STEP_SHIFT 0 1570 1571 1572 /**************************************************************************** 1573 * DDR23_PHY_BYTE_LANE0 :: VDL_OVERRIDE_5 1574 */ 1575 /* DDR23_PHY_BYTE_LANE0 :: VDL_OVERRIDE_5 :: reserved0 [31:17] */ 1576 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_5_RESERVED0_MASK 0xfffe0000 1577 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_5_RESERVED0_ALIGN 0 1578 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_5_RESERVED0_BITS 15 1579 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_5_RESERVED0_SHIFT 17 1580 1581 /* DDR23_PHY_BYTE_LANE0 :: VDL_OVERRIDE_5 :: ovr_en [16:16] */ 1582 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_5_OVR_EN_MASK 0x00010000 1583 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_5_OVR_EN_ALIGN 0 1584 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_5_OVR_EN_BITS 1 1585 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_5_OVR_EN_SHIFT 16 1586 1587 /* DDR23_PHY_BYTE_LANE0 :: VDL_OVERRIDE_5 :: reserved1 [15:14] */ 1588 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_5_RESERVED1_MASK 0x0000c000 1589 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_5_RESERVED1_ALIGN 0 1590 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_5_RESERVED1_BITS 2 1591 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_5_RESERVED1_SHIFT 14 1592 1593 /* DDR23_PHY_BYTE_LANE0 :: VDL_OVERRIDE_5 :: ovr_fine_fall [13:12] */ 1594 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_5_OVR_FINE_FALL_MASK 0x00003000 1595 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_5_OVR_FINE_FALL_ALIGN 0 1596 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_5_OVR_FINE_FALL_BITS 2 1597 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_5_OVR_FINE_FALL_SHIFT 12 1598 1599 /* DDR23_PHY_BYTE_LANE0 :: VDL_OVERRIDE_5 :: reserved2 [11:10] */ 1600 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_5_RESERVED2_MASK 0x00000c00 1601 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_5_RESERVED2_ALIGN 0 1602 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_5_RESERVED2_BITS 2 1603 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_5_RESERVED2_SHIFT 10 1604 1605 /* DDR23_PHY_BYTE_LANE0 :: VDL_OVERRIDE_5 :: ovr_fine_rise [09:08] */ 1606 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_5_OVR_FINE_RISE_MASK 0x00000300 1607 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_5_OVR_FINE_RISE_ALIGN 0 1608 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_5_OVR_FINE_RISE_BITS 2 1609 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_5_OVR_FINE_RISE_SHIFT 8 1610 1611 /* DDR23_PHY_BYTE_LANE0 :: VDL_OVERRIDE_5 :: reserved3 [07:06] */ 1612 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_5_RESERVED3_MASK 0x000000c0 1613 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_5_RESERVED3_ALIGN 0 1614 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_5_RESERVED3_BITS 2 1615 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_5_RESERVED3_SHIFT 6 1616 1617 /* DDR23_PHY_BYTE_LANE0 :: VDL_OVERRIDE_5 :: ovr_step [05:00] */ 1618 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_5_OVR_STEP_MASK 0x0000003f 1619 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_5_OVR_STEP_ALIGN 0 1620 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_5_OVR_STEP_BITS 6 1621 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_5_OVR_STEP_SHIFT 0 1622 1623 1624 /**************************************************************************** 1625 * DDR23_PHY_BYTE_LANE0 :: VDL_OVERRIDE_6 1626 */ 1627 /* DDR23_PHY_BYTE_LANE0 :: VDL_OVERRIDE_6 :: reserved0 [31:17] */ 1628 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_6_RESERVED0_MASK 0xfffe0000 1629 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_6_RESERVED0_ALIGN 0 1630 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_6_RESERVED0_BITS 15 1631 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_6_RESERVED0_SHIFT 17 1632 1633 /* DDR23_PHY_BYTE_LANE0 :: VDL_OVERRIDE_6 :: ovr_en [16:16] */ 1634 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_6_OVR_EN_MASK 0x00010000 1635 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_6_OVR_EN_ALIGN 0 1636 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_6_OVR_EN_BITS 1 1637 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_6_OVR_EN_SHIFT 16 1638 1639 /* DDR23_PHY_BYTE_LANE0 :: VDL_OVERRIDE_6 :: reserved1 [15:14] */ 1640 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_6_RESERVED1_MASK 0x0000c000 1641 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_6_RESERVED1_ALIGN 0 1642 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_6_RESERVED1_BITS 2 1643 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_6_RESERVED1_SHIFT 14 1644 1645 /* DDR23_PHY_BYTE_LANE0 :: VDL_OVERRIDE_6 :: ovr_fine_fall [13:12] */ 1646 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_6_OVR_FINE_FALL_MASK 0x00003000 1647 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_6_OVR_FINE_FALL_ALIGN 0 1648 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_6_OVR_FINE_FALL_BITS 2 1649 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_6_OVR_FINE_FALL_SHIFT 12 1650 1651 /* DDR23_PHY_BYTE_LANE0 :: VDL_OVERRIDE_6 :: reserved2 [11:10] */ 1652 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_6_RESERVED2_MASK 0x00000c00 1653 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_6_RESERVED2_ALIGN 0 1654 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_6_RESERVED2_BITS 2 1655 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_6_RESERVED2_SHIFT 10 1656 1657 /* DDR23_PHY_BYTE_LANE0 :: VDL_OVERRIDE_6 :: ovr_fine_rise [09:08] */ 1658 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_6_OVR_FINE_RISE_MASK 0x00000300 1659 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_6_OVR_FINE_RISE_ALIGN 0 1660 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_6_OVR_FINE_RISE_BITS 2 1661 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_6_OVR_FINE_RISE_SHIFT 8 1662 1663 /* DDR23_PHY_BYTE_LANE0 :: VDL_OVERRIDE_6 :: reserved3 [07:06] */ 1664 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_6_RESERVED3_MASK 0x000000c0 1665 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_6_RESERVED3_ALIGN 0 1666 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_6_RESERVED3_BITS 2 1667 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_6_RESERVED3_SHIFT 6 1668 1669 /* DDR23_PHY_BYTE_LANE0 :: VDL_OVERRIDE_6 :: ovr_step [05:00] */ 1670 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_6_OVR_STEP_MASK 0x0000003f 1671 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_6_OVR_STEP_ALIGN 0 1672 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_6_OVR_STEP_BITS 6 1673 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_6_OVR_STEP_SHIFT 0 1674 1675 1676 /**************************************************************************** 1677 * DDR23_PHY_BYTE_LANE0 :: VDL_OVERRIDE_7 1678 */ 1679 /* DDR23_PHY_BYTE_LANE0 :: VDL_OVERRIDE_7 :: reserved0 [31:17] */ 1680 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_7_RESERVED0_MASK 0xfffe0000 1681 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_7_RESERVED0_ALIGN 0 1682 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_7_RESERVED0_BITS 15 1683 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_7_RESERVED0_SHIFT 17 1684 1685 /* DDR23_PHY_BYTE_LANE0 :: VDL_OVERRIDE_7 :: ovr_en [16:16] */ 1686 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_7_OVR_EN_MASK 0x00010000 1687 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_7_OVR_EN_ALIGN 0 1688 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_7_OVR_EN_BITS 1 1689 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_7_OVR_EN_SHIFT 16 1690 1691 /* DDR23_PHY_BYTE_LANE0 :: VDL_OVERRIDE_7 :: reserved1 [15:14] */ 1692 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_7_RESERVED1_MASK 0x0000c000 1693 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_7_RESERVED1_ALIGN 0 1694 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_7_RESERVED1_BITS 2 1695 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_7_RESERVED1_SHIFT 14 1696 1697 /* DDR23_PHY_BYTE_LANE0 :: VDL_OVERRIDE_7 :: ovr_fine_fall [13:12] */ 1698 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_7_OVR_FINE_FALL_MASK 0x00003000 1699 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_7_OVR_FINE_FALL_ALIGN 0 1700 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_7_OVR_FINE_FALL_BITS 2 1701 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_7_OVR_FINE_FALL_SHIFT 12 1702 1703 /* DDR23_PHY_BYTE_LANE0 :: VDL_OVERRIDE_7 :: reserved2 [11:10] */ 1704 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_7_RESERVED2_MASK 0x00000c00 1705 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_7_RESERVED2_ALIGN 0 1706 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_7_RESERVED2_BITS 2 1707 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_7_RESERVED2_SHIFT 10 1708 1709 /* DDR23_PHY_BYTE_LANE0 :: VDL_OVERRIDE_7 :: ovr_fine_rise [09:08] */ 1710 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_7_OVR_FINE_RISE_MASK 0x00000300 1711 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_7_OVR_FINE_RISE_ALIGN 0 1712 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_7_OVR_FINE_RISE_BITS 2 1713 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_7_OVR_FINE_RISE_SHIFT 8 1714 1715 /* DDR23_PHY_BYTE_LANE0 :: VDL_OVERRIDE_7 :: reserved3 [07:06] */ 1716 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_7_RESERVED3_MASK 0x000000c0 1717 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_7_RESERVED3_ALIGN 0 1718 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_7_RESERVED3_BITS 2 1719 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_7_RESERVED3_SHIFT 6 1720 1721 /* DDR23_PHY_BYTE_LANE0 :: VDL_OVERRIDE_7 :: ovr_step [05:00] */ 1722 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_7_OVR_STEP_MASK 0x0000003f 1723 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_7_OVR_STEP_ALIGN 0 1724 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_7_OVR_STEP_BITS 6 1725 #define DDR23_PHY_BYTE_LANE0_VDL_OVERRIDE_7_OVR_STEP_SHIFT 0 1726 1727 1728 /**************************************************************************** 1729 * DDR23_PHY_BYTE_LANE0 :: READ_CONTROL 1730 */ 1731 /* DDR23_PHY_BYTE_LANE0 :: READ_CONTROL :: reserved0 [31:10] */ 1732 #define DDR23_PHY_BYTE_LANE0_READ_CONTROL_RESERVED0_MASK 0xfffffc00 1733 #define DDR23_PHY_BYTE_LANE0_READ_CONTROL_RESERVED0_ALIGN 0 1734 #define DDR23_PHY_BYTE_LANE0_READ_CONTROL_RESERVED0_BITS 22 1735 #define DDR23_PHY_BYTE_LANE0_READ_CONTROL_RESERVED0_SHIFT 10 1736 1737 /* DDR23_PHY_BYTE_LANE0 :: READ_CONTROL :: rd_data_dly [09:08] */ 1738 #define DDR23_PHY_BYTE_LANE0_READ_CONTROL_RD_DATA_DLY_MASK 0x00000300 1739 #define DDR23_PHY_BYTE_LANE0_READ_CONTROL_RD_DATA_DLY_ALIGN 0 1740 #define DDR23_PHY_BYTE_LANE0_READ_CONTROL_RD_DATA_DLY_BITS 2 1741 #define DDR23_PHY_BYTE_LANE0_READ_CONTROL_RD_DATA_DLY_SHIFT 8 1742 1743 /* DDR23_PHY_BYTE_LANE0 :: READ_CONTROL :: reserved1 [07:04] */ 1744 #define DDR23_PHY_BYTE_LANE0_READ_CONTROL_RESERVED1_MASK 0x000000f0 1745 #define DDR23_PHY_BYTE_LANE0_READ_CONTROL_RESERVED1_ALIGN 0 1746 #define DDR23_PHY_BYTE_LANE0_READ_CONTROL_RESERVED1_BITS 4 1747 #define DDR23_PHY_BYTE_LANE0_READ_CONTROL_RESERVED1_SHIFT 4 1748 1749 /* DDR23_PHY_BYTE_LANE0 :: READ_CONTROL :: dq_odt_enable [03:03] */ 1750 #define DDR23_PHY_BYTE_LANE0_READ_CONTROL_DQ_ODT_ENABLE_MASK 0x00000008 1751 #define DDR23_PHY_BYTE_LANE0_READ_CONTROL_DQ_ODT_ENABLE_ALIGN 0 1752 #define DDR23_PHY_BYTE_LANE0_READ_CONTROL_DQ_ODT_ENABLE_BITS 1 1753 #define DDR23_PHY_BYTE_LANE0_READ_CONTROL_DQ_ODT_ENABLE_SHIFT 3 1754 1755 /* DDR23_PHY_BYTE_LANE0 :: READ_CONTROL :: dq_odt_adj [02:02] */ 1756 #define DDR23_PHY_BYTE_LANE0_READ_CONTROL_DQ_ODT_ADJ_MASK 0x00000004 1757 #define DDR23_PHY_BYTE_LANE0_READ_CONTROL_DQ_ODT_ADJ_ALIGN 0 1758 #define DDR23_PHY_BYTE_LANE0_READ_CONTROL_DQ_ODT_ADJ_BITS 1 1759 #define DDR23_PHY_BYTE_LANE0_READ_CONTROL_DQ_ODT_ADJ_SHIFT 2 1760 1761 /* DDR23_PHY_BYTE_LANE0 :: READ_CONTROL :: rd_enb_odt_enable [01:01] */ 1762 #define DDR23_PHY_BYTE_LANE0_READ_CONTROL_RD_ENB_ODT_ENABLE_MASK 0x00000002 1763 #define DDR23_PHY_BYTE_LANE0_READ_CONTROL_RD_ENB_ODT_ENABLE_ALIGN 0 1764 #define DDR23_PHY_BYTE_LANE0_READ_CONTROL_RD_ENB_ODT_ENABLE_BITS 1 1765 #define DDR23_PHY_BYTE_LANE0_READ_CONTROL_RD_ENB_ODT_ENABLE_SHIFT 1 1766 1767 /* DDR23_PHY_BYTE_LANE0 :: READ_CONTROL :: rd_enb_odt_adj [00:00] */ 1768 #define DDR23_PHY_BYTE_LANE0_READ_CONTROL_RD_ENB_ODT_ADJ_MASK 0x00000001 1769 #define DDR23_PHY_BYTE_LANE0_READ_CONTROL_RD_ENB_ODT_ADJ_ALIGN 0 1770 #define DDR23_PHY_BYTE_LANE0_READ_CONTROL_RD_ENB_ODT_ADJ_BITS 1 1771 #define DDR23_PHY_BYTE_LANE0_READ_CONTROL_RD_ENB_ODT_ADJ_SHIFT 0 1772 1773 1774 /**************************************************************************** 1775 * DDR23_PHY_BYTE_LANE0 :: READ_FIFO_STATUS 1776 */ 1777 /* DDR23_PHY_BYTE_LANE0 :: READ_FIFO_STATUS :: reserved0 [31:04] */ 1778 #define DDR23_PHY_BYTE_LANE0_READ_FIFO_STATUS_RESERVED0_MASK 0xfffffff0 1779 #define DDR23_PHY_BYTE_LANE0_READ_FIFO_STATUS_RESERVED0_ALIGN 0 1780 #define DDR23_PHY_BYTE_LANE0_READ_FIFO_STATUS_RESERVED0_BITS 28 1781 #define DDR23_PHY_BYTE_LANE0_READ_FIFO_STATUS_RESERVED0_SHIFT 4 1782 1783 /* DDR23_PHY_BYTE_LANE0 :: READ_FIFO_STATUS :: status [03:00] */ 1784 #define DDR23_PHY_BYTE_LANE0_READ_FIFO_STATUS_STATUS_MASK 0x0000000f 1785 #define DDR23_PHY_BYTE_LANE0_READ_FIFO_STATUS_STATUS_ALIGN 0 1786 #define DDR23_PHY_BYTE_LANE0_READ_FIFO_STATUS_STATUS_BITS 4 1787 #define DDR23_PHY_BYTE_LANE0_READ_FIFO_STATUS_STATUS_SHIFT 0 1788 1789 1790 /**************************************************************************** 1791 * DDR23_PHY_BYTE_LANE0 :: READ_FIFO_CLEAR 1792 */ 1793 /* DDR23_PHY_BYTE_LANE0 :: READ_FIFO_CLEAR :: reserved0 [31:01] */ 1794 #define DDR23_PHY_BYTE_LANE0_READ_FIFO_CLEAR_RESERVED0_MASK 0xfffffffe 1795 #define DDR23_PHY_BYTE_LANE0_READ_FIFO_CLEAR_RESERVED0_ALIGN 0 1796 #define DDR23_PHY_BYTE_LANE0_READ_FIFO_CLEAR_RESERVED0_BITS 31 1797 #define DDR23_PHY_BYTE_LANE0_READ_FIFO_CLEAR_RESERVED0_SHIFT 1 1798 1799 /* DDR23_PHY_BYTE_LANE0 :: READ_FIFO_CLEAR :: clear [00:00] */ 1800 #define DDR23_PHY_BYTE_LANE0_READ_FIFO_CLEAR_CLEAR_MASK 0x00000001 1801 #define DDR23_PHY_BYTE_LANE0_READ_FIFO_CLEAR_CLEAR_ALIGN 0 1802 #define DDR23_PHY_BYTE_LANE0_READ_FIFO_CLEAR_CLEAR_BITS 1 1803 #define DDR23_PHY_BYTE_LANE0_READ_FIFO_CLEAR_CLEAR_SHIFT 0 1804 1805 1806 /**************************************************************************** 1807 * DDR23_PHY_BYTE_LANE0 :: IDLE_PAD_CONTROL 1808 */ 1809 /* DDR23_PHY_BYTE_LANE0 :: IDLE_PAD_CONTROL :: idle [31:31] */ 1810 #define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_IDLE_MASK 0x80000000 1811 #define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_IDLE_ALIGN 0 1812 #define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_IDLE_BITS 1 1813 #define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_IDLE_SHIFT 31 1814 1815 /* DDR23_PHY_BYTE_LANE0 :: IDLE_PAD_CONTROL :: reserved0 [30:20] */ 1816 #define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_RESERVED0_MASK 0x7ff00000 1817 #define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_RESERVED0_ALIGN 0 1818 #define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_RESERVED0_BITS 11 1819 #define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_RESERVED0_SHIFT 20 1820 1821 /* DDR23_PHY_BYTE_LANE0 :: IDLE_PAD_CONTROL :: dm_rxenb [19:19] */ 1822 #define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_DM_RXENB_MASK 0x00080000 1823 #define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_DM_RXENB_ALIGN 0 1824 #define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_DM_RXENB_BITS 1 1825 #define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_DM_RXENB_SHIFT 19 1826 1827 /* DDR23_PHY_BYTE_LANE0 :: IDLE_PAD_CONTROL :: dm_iddq [18:18] */ 1828 #define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_DM_IDDQ_MASK 0x00040000 1829 #define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_DM_IDDQ_ALIGN 0 1830 #define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_DM_IDDQ_BITS 1 1831 #define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_DM_IDDQ_SHIFT 18 1832 1833 /* DDR23_PHY_BYTE_LANE0 :: IDLE_PAD_CONTROL :: dm_reb [17:17] */ 1834 #define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_DM_REB_MASK 0x00020000 1835 #define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_DM_REB_ALIGN 0 1836 #define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_DM_REB_BITS 1 1837 #define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_DM_REB_SHIFT 17 1838 1839 /* DDR23_PHY_BYTE_LANE0 :: IDLE_PAD_CONTROL :: dm_oeb [16:16] */ 1840 #define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_DM_OEB_MASK 0x00010000 1841 #define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_DM_OEB_ALIGN 0 1842 #define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_DM_OEB_BITS 1 1843 #define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_DM_OEB_SHIFT 16 1844 1845 /* DDR23_PHY_BYTE_LANE0 :: IDLE_PAD_CONTROL :: dq_rxenb [15:15] */ 1846 #define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_DQ_RXENB_MASK 0x00008000 1847 #define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_DQ_RXENB_ALIGN 0 1848 #define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_DQ_RXENB_BITS 1 1849 #define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_DQ_RXENB_SHIFT 15 1850 1851 /* DDR23_PHY_BYTE_LANE0 :: IDLE_PAD_CONTROL :: dq_iddq [14:14] */ 1852 #define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_DQ_IDDQ_MASK 0x00004000 1853 #define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_DQ_IDDQ_ALIGN 0 1854 #define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_DQ_IDDQ_BITS 1 1855 #define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_DQ_IDDQ_SHIFT 14 1856 1857 /* DDR23_PHY_BYTE_LANE0 :: IDLE_PAD_CONTROL :: dq_reb [13:13] */ 1858 #define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_DQ_REB_MASK 0x00002000 1859 #define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_DQ_REB_ALIGN 0 1860 #define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_DQ_REB_BITS 1 1861 #define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_DQ_REB_SHIFT 13 1862 1863 /* DDR23_PHY_BYTE_LANE0 :: IDLE_PAD_CONTROL :: dq_oeb [12:12] */ 1864 #define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_DQ_OEB_MASK 0x00001000 1865 #define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_DQ_OEB_ALIGN 0 1866 #define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_DQ_OEB_BITS 1 1867 #define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_DQ_OEB_SHIFT 12 1868 1869 /* DDR23_PHY_BYTE_LANE0 :: IDLE_PAD_CONTROL :: read_enb_rxenb [11:11] */ 1870 #define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_READ_ENB_RXENB_MASK 0x00000800 1871 #define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_READ_ENB_RXENB_ALIGN 0 1872 #define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_READ_ENB_RXENB_BITS 1 1873 #define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_READ_ENB_RXENB_SHIFT 11 1874 1875 /* DDR23_PHY_BYTE_LANE0 :: IDLE_PAD_CONTROL :: read_enb_iddq [10:10] */ 1876 #define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_READ_ENB_IDDQ_MASK 0x00000400 1877 #define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_READ_ENB_IDDQ_ALIGN 0 1878 #define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_READ_ENB_IDDQ_BITS 1 1879 #define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_READ_ENB_IDDQ_SHIFT 10 1880 1881 /* DDR23_PHY_BYTE_LANE0 :: IDLE_PAD_CONTROL :: read_enb_reb [09:09] */ 1882 #define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_READ_ENB_REB_MASK 0x00000200 1883 #define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_READ_ENB_REB_ALIGN 0 1884 #define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_READ_ENB_REB_BITS 1 1885 #define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_READ_ENB_REB_SHIFT 9 1886 1887 /* DDR23_PHY_BYTE_LANE0 :: IDLE_PAD_CONTROL :: read_enb_oeb [08:08] */ 1888 #define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_READ_ENB_OEB_MASK 0x00000100 1889 #define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_READ_ENB_OEB_ALIGN 0 1890 #define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_READ_ENB_OEB_BITS 1 1891 #define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_READ_ENB_OEB_SHIFT 8 1892 1893 /* DDR23_PHY_BYTE_LANE0 :: IDLE_PAD_CONTROL :: dqs_rxenb [07:07] */ 1894 #define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_DQS_RXENB_MASK 0x00000080 1895 #define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_DQS_RXENB_ALIGN 0 1896 #define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_DQS_RXENB_BITS 1 1897 #define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_DQS_RXENB_SHIFT 7 1898 1899 /* DDR23_PHY_BYTE_LANE0 :: IDLE_PAD_CONTROL :: dqs_iddq [06:06] */ 1900 #define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_DQS_IDDQ_MASK 0x00000040 1901 #define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_DQS_IDDQ_ALIGN 0 1902 #define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_DQS_IDDQ_BITS 1 1903 #define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_DQS_IDDQ_SHIFT 6 1904 1905 /* DDR23_PHY_BYTE_LANE0 :: IDLE_PAD_CONTROL :: dqs_reb [05:05] */ 1906 #define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_DQS_REB_MASK 0x00000020 1907 #define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_DQS_REB_ALIGN 0 1908 #define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_DQS_REB_BITS 1 1909 #define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_DQS_REB_SHIFT 5 1910 1911 /* DDR23_PHY_BYTE_LANE0 :: IDLE_PAD_CONTROL :: dqs_oeb [04:04] */ 1912 #define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_DQS_OEB_MASK 0x00000010 1913 #define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_DQS_OEB_ALIGN 0 1914 #define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_DQS_OEB_BITS 1 1915 #define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_DQS_OEB_SHIFT 4 1916 1917 /* DDR23_PHY_BYTE_LANE0 :: IDLE_PAD_CONTROL :: clk_rxenb [03:03] */ 1918 #define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_CLK_RXENB_MASK 0x00000008 1919 #define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_CLK_RXENB_ALIGN 0 1920 #define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_CLK_RXENB_BITS 1 1921 #define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_CLK_RXENB_SHIFT 3 1922 1923 /* DDR23_PHY_BYTE_LANE0 :: IDLE_PAD_CONTROL :: clk_iddq [02:02] */ 1924 #define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_CLK_IDDQ_MASK 0x00000004 1925 #define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_CLK_IDDQ_ALIGN 0 1926 #define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_CLK_IDDQ_BITS 1 1927 #define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_CLK_IDDQ_SHIFT 2 1928 1929 /* DDR23_PHY_BYTE_LANE0 :: IDLE_PAD_CONTROL :: clk_reb [01:01] */ 1930 #define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_CLK_REB_MASK 0x00000002 1931 #define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_CLK_REB_ALIGN 0 1932 #define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_CLK_REB_BITS 1 1933 #define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_CLK_REB_SHIFT 1 1934 1935 /* DDR23_PHY_BYTE_LANE0 :: IDLE_PAD_CONTROL :: clk_oeb [00:00] */ 1936 #define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_CLK_OEB_MASK 0x00000001 1937 #define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_CLK_OEB_ALIGN 0 1938 #define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_CLK_OEB_BITS 1 1939 #define DDR23_PHY_BYTE_LANE0_IDLE_PAD_CONTROL_CLK_OEB_SHIFT 0 1940 1941 1942 /**************************************************************************** 1943 * DDR23_PHY_BYTE_LANE0 :: DRIVE_PAD_CTL 1944 */ 1945 /* DDR23_PHY_BYTE_LANE0 :: DRIVE_PAD_CTL :: reserved0 [31:06] */ 1946 #define DDR23_PHY_BYTE_LANE0_DRIVE_PAD_CTL_RESERVED0_MASK 0xffffffc0 1947 #define DDR23_PHY_BYTE_LANE0_DRIVE_PAD_CTL_RESERVED0_ALIGN 0 1948 #define DDR23_PHY_BYTE_LANE0_DRIVE_PAD_CTL_RESERVED0_BITS 26 1949 #define DDR23_PHY_BYTE_LANE0_DRIVE_PAD_CTL_RESERVED0_SHIFT 6 1950 1951 /* DDR23_PHY_BYTE_LANE0 :: DRIVE_PAD_CTL :: rt60b_ddr_read_enb [05:05] */ 1952 #define DDR23_PHY_BYTE_LANE0_DRIVE_PAD_CTL_RT60B_DDR_READ_ENB_MASK 0x00000020 1953 #define DDR23_PHY_BYTE_LANE0_DRIVE_PAD_CTL_RT60B_DDR_READ_ENB_ALIGN 0 1954 #define DDR23_PHY_BYTE_LANE0_DRIVE_PAD_CTL_RT60B_DDR_READ_ENB_BITS 1 1955 #define DDR23_PHY_BYTE_LANE0_DRIVE_PAD_CTL_RT60B_DDR_READ_ENB_SHIFT 5 1956 1957 /* DDR23_PHY_BYTE_LANE0 :: DRIVE_PAD_CTL :: rt60b [04:04] */ 1958 #define DDR23_PHY_BYTE_LANE0_DRIVE_PAD_CTL_RT60B_MASK 0x00000010 1959 #define DDR23_PHY_BYTE_LANE0_DRIVE_PAD_CTL_RT60B_ALIGN 0 1960 #define DDR23_PHY_BYTE_LANE0_DRIVE_PAD_CTL_RT60B_BITS 1 1961 #define DDR23_PHY_BYTE_LANE0_DRIVE_PAD_CTL_RT60B_SHIFT 4 1962 1963 /* DDR23_PHY_BYTE_LANE0 :: DRIVE_PAD_CTL :: sel_sstl18 [03:03] */ 1964 #define DDR23_PHY_BYTE_LANE0_DRIVE_PAD_CTL_SEL_SSTL18_MASK 0x00000008 1965 #define DDR23_PHY_BYTE_LANE0_DRIVE_PAD_CTL_SEL_SSTL18_ALIGN 0 1966 #define DDR23_PHY_BYTE_LANE0_DRIVE_PAD_CTL_SEL_SSTL18_BITS 1 1967 #define DDR23_PHY_BYTE_LANE0_DRIVE_PAD_CTL_SEL_SSTL18_SHIFT 3 1968 1969 /* DDR23_PHY_BYTE_LANE0 :: DRIVE_PAD_CTL :: seltxdrv_ci [02:02] */ 1970 #define DDR23_PHY_BYTE_LANE0_DRIVE_PAD_CTL_SELTXDRV_CI_MASK 0x00000004 1971 #define DDR23_PHY_BYTE_LANE0_DRIVE_PAD_CTL_SELTXDRV_CI_ALIGN 0 1972 #define DDR23_PHY_BYTE_LANE0_DRIVE_PAD_CTL_SELTXDRV_CI_BITS 1 1973 #define DDR23_PHY_BYTE_LANE0_DRIVE_PAD_CTL_SELTXDRV_CI_SHIFT 2 1974 1975 /* DDR23_PHY_BYTE_LANE0 :: DRIVE_PAD_CTL :: selrxdrv [01:01] */ 1976 #define DDR23_PHY_BYTE_LANE0_DRIVE_PAD_CTL_SELRXDRV_MASK 0x00000002 1977 #define DDR23_PHY_BYTE_LANE0_DRIVE_PAD_CTL_SELRXDRV_ALIGN 0 1978 #define DDR23_PHY_BYTE_LANE0_DRIVE_PAD_CTL_SELRXDRV_BITS 1 1979 #define DDR23_PHY_BYTE_LANE0_DRIVE_PAD_CTL_SELRXDRV_SHIFT 1 1980 1981 /* DDR23_PHY_BYTE_LANE0 :: DRIVE_PAD_CTL :: slew [00:00] */ 1982 #define DDR23_PHY_BYTE_LANE0_DRIVE_PAD_CTL_SLEW_MASK 0x00000001 1983 #define DDR23_PHY_BYTE_LANE0_DRIVE_PAD_CTL_SLEW_ALIGN 0 1984 #define DDR23_PHY_BYTE_LANE0_DRIVE_PAD_CTL_SLEW_BITS 1 1985 #define DDR23_PHY_BYTE_LANE0_DRIVE_PAD_CTL_SLEW_SHIFT 0 1986 1987 1988 /**************************************************************************** 1989 * DDR23_PHY_BYTE_LANE0 :: CLOCK_PAD_DISABLE 1990 */ 1991 /* DDR23_PHY_BYTE_LANE0 :: CLOCK_PAD_DISABLE :: reserved0 [31:01] */ 1992 #define DDR23_PHY_BYTE_LANE0_CLOCK_PAD_DISABLE_RESERVED0_MASK 0xfffffffe 1993 #define DDR23_PHY_BYTE_LANE0_CLOCK_PAD_DISABLE_RESERVED0_ALIGN 0 1994 #define DDR23_PHY_BYTE_LANE0_CLOCK_PAD_DISABLE_RESERVED0_BITS 31 1995 #define DDR23_PHY_BYTE_LANE0_CLOCK_PAD_DISABLE_RESERVED0_SHIFT 1 1996 1997 /* DDR23_PHY_BYTE_LANE0 :: CLOCK_PAD_DISABLE :: clk_pad_dis [00:00] */ 1998 #define DDR23_PHY_BYTE_LANE0_CLOCK_PAD_DISABLE_CLK_PAD_DIS_MASK 0x00000001 1999 #define DDR23_PHY_BYTE_LANE0_CLOCK_PAD_DISABLE_CLK_PAD_DIS_ALIGN 0 2000 #define DDR23_PHY_BYTE_LANE0_CLOCK_PAD_DISABLE_CLK_PAD_DIS_BITS 1 2001 #define DDR23_PHY_BYTE_LANE0_CLOCK_PAD_DISABLE_CLK_PAD_DIS_SHIFT 0 2002 2003 2004 /**************************************************************************** 2005 * DDR23_PHY_BYTE_LANE0 :: WR_PREAMBLE_MODE 2006 */ 2007 /* DDR23_PHY_BYTE_LANE0 :: WR_PREAMBLE_MODE :: reserved0 [31:01] */ 2008 #define DDR23_PHY_BYTE_LANE0_WR_PREAMBLE_MODE_RESERVED0_MASK 0xfffffffe 2009 #define DDR23_PHY_BYTE_LANE0_WR_PREAMBLE_MODE_RESERVED0_ALIGN 0 2010 #define DDR23_PHY_BYTE_LANE0_WR_PREAMBLE_MODE_RESERVED0_BITS 31 2011 #define DDR23_PHY_BYTE_LANE0_WR_PREAMBLE_MODE_RESERVED0_SHIFT 1 2012 2013 /* DDR23_PHY_BYTE_LANE0 :: WR_PREAMBLE_MODE :: mode [00:00] */ 2014 #define DDR23_PHY_BYTE_LANE0_WR_PREAMBLE_MODE_MODE_MASK 0x00000001 2015 #define DDR23_PHY_BYTE_LANE0_WR_PREAMBLE_MODE_MODE_ALIGN 0 2016 #define DDR23_PHY_BYTE_LANE0_WR_PREAMBLE_MODE_MODE_BITS 1 2017 #define DDR23_PHY_BYTE_LANE0_WR_PREAMBLE_MODE_MODE_SHIFT 0 2018 2019 2020 /**************************************************************************** 2021 * DDR23_PHY_BYTE_LANE0 :: CLOCK_REG_CONTROL 2022 */ 2023 /* DDR23_PHY_BYTE_LANE0 :: CLOCK_REG_CONTROL :: reserved0 [31:02] */ 2024 #define DDR23_PHY_BYTE_LANE0_CLOCK_REG_CONTROL_RESERVED0_MASK 0xfffffffc 2025 #define DDR23_PHY_BYTE_LANE0_CLOCK_REG_CONTROL_RESERVED0_ALIGN 0 2026 #define DDR23_PHY_BYTE_LANE0_CLOCK_REG_CONTROL_RESERVED0_BITS 30 2027 #define DDR23_PHY_BYTE_LANE0_CLOCK_REG_CONTROL_RESERVED0_SHIFT 2 2028 2029 /* DDR23_PHY_BYTE_LANE0 :: CLOCK_REG_CONTROL :: half_power [01:01] */ 2030 #define DDR23_PHY_BYTE_LANE0_CLOCK_REG_CONTROL_HALF_POWER_MASK 0x00000002 2031 #define DDR23_PHY_BYTE_LANE0_CLOCK_REG_CONTROL_HALF_POWER_ALIGN 0 2032 #define DDR23_PHY_BYTE_LANE0_CLOCK_REG_CONTROL_HALF_POWER_BITS 1 2033 #define DDR23_PHY_BYTE_LANE0_CLOCK_REG_CONTROL_HALF_POWER_SHIFT 1 2034 2035 /* DDR23_PHY_BYTE_LANE0 :: CLOCK_REG_CONTROL :: pwrdn [00:00] */ 2036 #define DDR23_PHY_BYTE_LANE0_CLOCK_REG_CONTROL_PWRDN_MASK 0x00000001 2037 #define DDR23_PHY_BYTE_LANE0_CLOCK_REG_CONTROL_PWRDN_ALIGN 0 2038 #define DDR23_PHY_BYTE_LANE0_CLOCK_REG_CONTROL_PWRDN_BITS 1 2039 #define DDR23_PHY_BYTE_LANE0_CLOCK_REG_CONTROL_PWRDN_SHIFT 0 2040 2041 2042 /**************************************************************************** 2043 * DDR23_PHY_DDR23_PHY_BYTE_LANE1 2044 */ 2045 /**************************************************************************** 2046 * DDR23_PHY_BYTE_LANE1 :: REVISION 2047 */ 2048 /* DDR23_PHY_BYTE_LANE1 :: REVISION :: reserved0 [31:16] */ 2049 #define DDR23_PHY_BYTE_LANE1_REVISION_RESERVED0_MASK 0xffff0000 2050 #define DDR23_PHY_BYTE_LANE1_REVISION_RESERVED0_ALIGN 0 2051 #define DDR23_PHY_BYTE_LANE1_REVISION_RESERVED0_BITS 16 2052 #define DDR23_PHY_BYTE_LANE1_REVISION_RESERVED0_SHIFT 16 2053 2054 /* DDR23_PHY_BYTE_LANE1 :: REVISION :: MAJOR [15:08] */ 2055 #define DDR23_PHY_BYTE_LANE1_REVISION_MAJOR_MASK 0x0000ff00 2056 #define DDR23_PHY_BYTE_LANE1_REVISION_MAJOR_ALIGN 0 2057 #define DDR23_PHY_BYTE_LANE1_REVISION_MAJOR_BITS 8 2058 #define DDR23_PHY_BYTE_LANE1_REVISION_MAJOR_SHIFT 8 2059 2060 /* DDR23_PHY_BYTE_LANE1 :: REVISION :: MINOR [07:00] */ 2061 #define DDR23_PHY_BYTE_LANE1_REVISION_MINOR_MASK 0x000000ff 2062 #define DDR23_PHY_BYTE_LANE1_REVISION_MINOR_ALIGN 0 2063 #define DDR23_PHY_BYTE_LANE1_REVISION_MINOR_BITS 8 2064 #define DDR23_PHY_BYTE_LANE1_REVISION_MINOR_SHIFT 0 2065 2066 2067 /**************************************************************************** 2068 * DDR23_PHY_BYTE_LANE1 :: VDL_CALIBRATE 2069 */ 2070 /* DDR23_PHY_BYTE_LANE1 :: VDL_CALIBRATE :: reserved0 [31:05] */ 2071 #define DDR23_PHY_BYTE_LANE1_VDL_CALIBRATE_RESERVED0_MASK 0xffffffe0 2072 #define DDR23_PHY_BYTE_LANE1_VDL_CALIBRATE_RESERVED0_ALIGN 0 2073 #define DDR23_PHY_BYTE_LANE1_VDL_CALIBRATE_RESERVED0_BITS 27 2074 #define DDR23_PHY_BYTE_LANE1_VDL_CALIBRATE_RESERVED0_SHIFT 5 2075 2076 /* DDR23_PHY_BYTE_LANE1 :: VDL_CALIBRATE :: calib_clocks [04:04] */ 2077 #define DDR23_PHY_BYTE_LANE1_VDL_CALIBRATE_CALIB_CLOCKS_MASK 0x00000010 2078 #define DDR23_PHY_BYTE_LANE1_VDL_CALIBRATE_CALIB_CLOCKS_ALIGN 0 2079 #define DDR23_PHY_BYTE_LANE1_VDL_CALIBRATE_CALIB_CLOCKS_BITS 1 2080 #define DDR23_PHY_BYTE_LANE1_VDL_CALIBRATE_CALIB_CLOCKS_SHIFT 4 2081 2082 /* DDR23_PHY_BYTE_LANE1 :: VDL_CALIBRATE :: calib_test [03:03] */ 2083 #define DDR23_PHY_BYTE_LANE1_VDL_CALIBRATE_CALIB_TEST_MASK 0x00000008 2084 #define DDR23_PHY_BYTE_LANE1_VDL_CALIBRATE_CALIB_TEST_ALIGN 0 2085 #define DDR23_PHY_BYTE_LANE1_VDL_CALIBRATE_CALIB_TEST_BITS 1 2086 #define DDR23_PHY_BYTE_LANE1_VDL_CALIBRATE_CALIB_TEST_SHIFT 3 2087 2088 /* DDR23_PHY_BYTE_LANE1 :: VDL_CALIBRATE :: calib_always [02:02] */ 2089 #define DDR23_PHY_BYTE_LANE1_VDL_CALIBRATE_CALIB_ALWAYS_MASK 0x00000004 2090 #define DDR23_PHY_BYTE_LANE1_VDL_CALIBRATE_CALIB_ALWAYS_ALIGN 0 2091 #define DDR23_PHY_BYTE_LANE1_VDL_CALIBRATE_CALIB_ALWAYS_BITS 1 2092 #define DDR23_PHY_BYTE_LANE1_VDL_CALIBRATE_CALIB_ALWAYS_SHIFT 2 2093 2094 /* DDR23_PHY_BYTE_LANE1 :: VDL_CALIBRATE :: calib_once [01:01] */ 2095 #define DDR23_PHY_BYTE_LANE1_VDL_CALIBRATE_CALIB_ONCE_MASK 0x00000002 2096 #define DDR23_PHY_BYTE_LANE1_VDL_CALIBRATE_CALIB_ONCE_ALIGN 0 2097 #define DDR23_PHY_BYTE_LANE1_VDL_CALIBRATE_CALIB_ONCE_BITS 1 2098 #define DDR23_PHY_BYTE_LANE1_VDL_CALIBRATE_CALIB_ONCE_SHIFT 1 2099 2100 /* DDR23_PHY_BYTE_LANE1 :: VDL_CALIBRATE :: calib_fast [00:00] */ 2101 #define DDR23_PHY_BYTE_LANE1_VDL_CALIBRATE_CALIB_FAST_MASK 0x00000001 2102 #define DDR23_PHY_BYTE_LANE1_VDL_CALIBRATE_CALIB_FAST_ALIGN 0 2103 #define DDR23_PHY_BYTE_LANE1_VDL_CALIBRATE_CALIB_FAST_BITS 1 2104 #define DDR23_PHY_BYTE_LANE1_VDL_CALIBRATE_CALIB_FAST_SHIFT 0 2105 2106 2107 /**************************************************************************** 2108 * DDR23_PHY_BYTE_LANE1 :: VDL_STATUS 2109 */ 2110 /* DDR23_PHY_BYTE_LANE1 :: VDL_STATUS :: reserved0 [31:14] */ 2111 #define DDR23_PHY_BYTE_LANE1_VDL_STATUS_RESERVED0_MASK 0xffffc000 2112 #define DDR23_PHY_BYTE_LANE1_VDL_STATUS_RESERVED0_ALIGN 0 2113 #define DDR23_PHY_BYTE_LANE1_VDL_STATUS_RESERVED0_BITS 18 2114 #define DDR23_PHY_BYTE_LANE1_VDL_STATUS_RESERVED0_SHIFT 14 2115 2116 /* DDR23_PHY_BYTE_LANE1 :: VDL_STATUS :: calib_total [13:04] */ 2117 #define DDR23_PHY_BYTE_LANE1_VDL_STATUS_CALIB_TOTAL_MASK 0x00003ff0 2118 #define DDR23_PHY_BYTE_LANE1_VDL_STATUS_CALIB_TOTAL_ALIGN 0 2119 #define DDR23_PHY_BYTE_LANE1_VDL_STATUS_CALIB_TOTAL_BITS 10 2120 #define DDR23_PHY_BYTE_LANE1_VDL_STATUS_CALIB_TOTAL_SHIFT 4 2121 2122 /* DDR23_PHY_BYTE_LANE1 :: VDL_STATUS :: reserved1 [03:02] */ 2123 #define DDR23_PHY_BYTE_LANE1_VDL_STATUS_RESERVED1_MASK 0x0000000c 2124 #define DDR23_PHY_BYTE_LANE1_VDL_STATUS_RESERVED1_ALIGN 0 2125 #define DDR23_PHY_BYTE_LANE1_VDL_STATUS_RESERVED1_BITS 2 2126 #define DDR23_PHY_BYTE_LANE1_VDL_STATUS_RESERVED1_SHIFT 2 2127 2128 /* DDR23_PHY_BYTE_LANE1 :: VDL_STATUS :: calib_lock [01:01] */ 2129 #define DDR23_PHY_BYTE_LANE1_VDL_STATUS_CALIB_LOCK_MASK 0x00000002 2130 #define DDR23_PHY_BYTE_LANE1_VDL_STATUS_CALIB_LOCK_ALIGN 0 2131 #define DDR23_PHY_BYTE_LANE1_VDL_STATUS_CALIB_LOCK_BITS 1 2132 #define DDR23_PHY_BYTE_LANE1_VDL_STATUS_CALIB_LOCK_SHIFT 1 2133 2134 /* DDR23_PHY_BYTE_LANE1 :: VDL_STATUS :: calib_idle [00:00] */ 2135 #define DDR23_PHY_BYTE_LANE1_VDL_STATUS_CALIB_IDLE_MASK 0x00000001 2136 #define DDR23_PHY_BYTE_LANE1_VDL_STATUS_CALIB_IDLE_ALIGN 0 2137 #define DDR23_PHY_BYTE_LANE1_VDL_STATUS_CALIB_IDLE_BITS 1 2138 #define DDR23_PHY_BYTE_LANE1_VDL_STATUS_CALIB_IDLE_SHIFT 0 2139 2140 2141 /**************************************************************************** 2142 * DDR23_PHY_BYTE_LANE1 :: VDL_OVERRIDE_0 2143 */ 2144 /* DDR23_PHY_BYTE_LANE1 :: VDL_OVERRIDE_0 :: reserved0 [31:17] */ 2145 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_0_RESERVED0_MASK 0xfffe0000 2146 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_0_RESERVED0_ALIGN 0 2147 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_0_RESERVED0_BITS 15 2148 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_0_RESERVED0_SHIFT 17 2149 2150 /* DDR23_PHY_BYTE_LANE1 :: VDL_OVERRIDE_0 :: ovr_en [16:16] */ 2151 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_0_OVR_EN_MASK 0x00010000 2152 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_0_OVR_EN_ALIGN 0 2153 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_0_OVR_EN_BITS 1 2154 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_0_OVR_EN_SHIFT 16 2155 2156 /* DDR23_PHY_BYTE_LANE1 :: VDL_OVERRIDE_0 :: reserved1 [15:14] */ 2157 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_0_RESERVED1_MASK 0x0000c000 2158 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_0_RESERVED1_ALIGN 0 2159 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_0_RESERVED1_BITS 2 2160 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_0_RESERVED1_SHIFT 14 2161 2162 /* DDR23_PHY_BYTE_LANE1 :: VDL_OVERRIDE_0 :: ovr_fine_fall [13:12] */ 2163 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_0_OVR_FINE_FALL_MASK 0x00003000 2164 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_0_OVR_FINE_FALL_ALIGN 0 2165 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_0_OVR_FINE_FALL_BITS 2 2166 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_0_OVR_FINE_FALL_SHIFT 12 2167 2168 /* DDR23_PHY_BYTE_LANE1 :: VDL_OVERRIDE_0 :: reserved2 [11:10] */ 2169 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_0_RESERVED2_MASK 0x00000c00 2170 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_0_RESERVED2_ALIGN 0 2171 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_0_RESERVED2_BITS 2 2172 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_0_RESERVED2_SHIFT 10 2173 2174 /* DDR23_PHY_BYTE_LANE1 :: VDL_OVERRIDE_0 :: ovr_fine_rise [09:08] */ 2175 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_0_OVR_FINE_RISE_MASK 0x00000300 2176 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_0_OVR_FINE_RISE_ALIGN 0 2177 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_0_OVR_FINE_RISE_BITS 2 2178 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_0_OVR_FINE_RISE_SHIFT 8 2179 2180 /* DDR23_PHY_BYTE_LANE1 :: VDL_OVERRIDE_0 :: reserved3 [07:06] */ 2181 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_0_RESERVED3_MASK 0x000000c0 2182 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_0_RESERVED3_ALIGN 0 2183 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_0_RESERVED3_BITS 2 2184 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_0_RESERVED3_SHIFT 6 2185 2186 /* DDR23_PHY_BYTE_LANE1 :: VDL_OVERRIDE_0 :: ovr_step [05:00] */ 2187 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_0_OVR_STEP_MASK 0x0000003f 2188 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_0_OVR_STEP_ALIGN 0 2189 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_0_OVR_STEP_BITS 6 2190 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_0_OVR_STEP_SHIFT 0 2191 2192 2193 /**************************************************************************** 2194 * DDR23_PHY_BYTE_LANE1 :: VDL_OVERRIDE_1 2195 */ 2196 /* DDR23_PHY_BYTE_LANE1 :: VDL_OVERRIDE_1 :: reserved0 [31:17] */ 2197 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_1_RESERVED0_MASK 0xfffe0000 2198 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_1_RESERVED0_ALIGN 0 2199 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_1_RESERVED0_BITS 15 2200 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_1_RESERVED0_SHIFT 17 2201 2202 /* DDR23_PHY_BYTE_LANE1 :: VDL_OVERRIDE_1 :: ovr_en [16:16] */ 2203 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_1_OVR_EN_MASK 0x00010000 2204 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_1_OVR_EN_ALIGN 0 2205 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_1_OVR_EN_BITS 1 2206 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_1_OVR_EN_SHIFT 16 2207 2208 /* DDR23_PHY_BYTE_LANE1 :: VDL_OVERRIDE_1 :: reserved1 [15:14] */ 2209 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_1_RESERVED1_MASK 0x0000c000 2210 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_1_RESERVED1_ALIGN 0 2211 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_1_RESERVED1_BITS 2 2212 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_1_RESERVED1_SHIFT 14 2213 2214 /* DDR23_PHY_BYTE_LANE1 :: VDL_OVERRIDE_1 :: ovr_fine_fall [13:12] */ 2215 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_1_OVR_FINE_FALL_MASK 0x00003000 2216 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_1_OVR_FINE_FALL_ALIGN 0 2217 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_1_OVR_FINE_FALL_BITS 2 2218 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_1_OVR_FINE_FALL_SHIFT 12 2219 2220 /* DDR23_PHY_BYTE_LANE1 :: VDL_OVERRIDE_1 :: reserved2 [11:10] */ 2221 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_1_RESERVED2_MASK 0x00000c00 2222 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_1_RESERVED2_ALIGN 0 2223 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_1_RESERVED2_BITS 2 2224 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_1_RESERVED2_SHIFT 10 2225 2226 /* DDR23_PHY_BYTE_LANE1 :: VDL_OVERRIDE_1 :: ovr_fine_rise [09:08] */ 2227 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_1_OVR_FINE_RISE_MASK 0x00000300 2228 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_1_OVR_FINE_RISE_ALIGN 0 2229 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_1_OVR_FINE_RISE_BITS 2 2230 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_1_OVR_FINE_RISE_SHIFT 8 2231 2232 /* DDR23_PHY_BYTE_LANE1 :: VDL_OVERRIDE_1 :: reserved3 [07:06] */ 2233 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_1_RESERVED3_MASK 0x000000c0 2234 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_1_RESERVED3_ALIGN 0 2235 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_1_RESERVED3_BITS 2 2236 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_1_RESERVED3_SHIFT 6 2237 2238 /* DDR23_PHY_BYTE_LANE1 :: VDL_OVERRIDE_1 :: ovr_step [05:00] */ 2239 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_1_OVR_STEP_MASK 0x0000003f 2240 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_1_OVR_STEP_ALIGN 0 2241 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_1_OVR_STEP_BITS 6 2242 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_1_OVR_STEP_SHIFT 0 2243 2244 2245 /**************************************************************************** 2246 * DDR23_PHY_BYTE_LANE1 :: VDL_OVERRIDE_2 2247 */ 2248 /* DDR23_PHY_BYTE_LANE1 :: VDL_OVERRIDE_2 :: reserved0 [31:17] */ 2249 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_2_RESERVED0_MASK 0xfffe0000 2250 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_2_RESERVED0_ALIGN 0 2251 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_2_RESERVED0_BITS 15 2252 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_2_RESERVED0_SHIFT 17 2253 2254 /* DDR23_PHY_BYTE_LANE1 :: VDL_OVERRIDE_2 :: ovr_en [16:16] */ 2255 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_2_OVR_EN_MASK 0x00010000 2256 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_2_OVR_EN_ALIGN 0 2257 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_2_OVR_EN_BITS 1 2258 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_2_OVR_EN_SHIFT 16 2259 2260 /* DDR23_PHY_BYTE_LANE1 :: VDL_OVERRIDE_2 :: reserved1 [15:14] */ 2261 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_2_RESERVED1_MASK 0x0000c000 2262 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_2_RESERVED1_ALIGN 0 2263 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_2_RESERVED1_BITS 2 2264 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_2_RESERVED1_SHIFT 14 2265 2266 /* DDR23_PHY_BYTE_LANE1 :: VDL_OVERRIDE_2 :: ovr_fine_fall [13:12] */ 2267 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_2_OVR_FINE_FALL_MASK 0x00003000 2268 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_2_OVR_FINE_FALL_ALIGN 0 2269 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_2_OVR_FINE_FALL_BITS 2 2270 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_2_OVR_FINE_FALL_SHIFT 12 2271 2272 /* DDR23_PHY_BYTE_LANE1 :: VDL_OVERRIDE_2 :: reserved2 [11:10] */ 2273 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_2_RESERVED2_MASK 0x00000c00 2274 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_2_RESERVED2_ALIGN 0 2275 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_2_RESERVED2_BITS 2 2276 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_2_RESERVED2_SHIFT 10 2277 2278 /* DDR23_PHY_BYTE_LANE1 :: VDL_OVERRIDE_2 :: ovr_fine_rise [09:08] */ 2279 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_2_OVR_FINE_RISE_MASK 0x00000300 2280 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_2_OVR_FINE_RISE_ALIGN 0 2281 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_2_OVR_FINE_RISE_BITS 2 2282 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_2_OVR_FINE_RISE_SHIFT 8 2283 2284 /* DDR23_PHY_BYTE_LANE1 :: VDL_OVERRIDE_2 :: reserved3 [07:06] */ 2285 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_2_RESERVED3_MASK 0x000000c0 2286 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_2_RESERVED3_ALIGN 0 2287 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_2_RESERVED3_BITS 2 2288 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_2_RESERVED3_SHIFT 6 2289 2290 /* DDR23_PHY_BYTE_LANE1 :: VDL_OVERRIDE_2 :: ovr_step [05:00] */ 2291 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_2_OVR_STEP_MASK 0x0000003f 2292 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_2_OVR_STEP_ALIGN 0 2293 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_2_OVR_STEP_BITS 6 2294 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_2_OVR_STEP_SHIFT 0 2295 2296 2297 /**************************************************************************** 2298 * DDR23_PHY_BYTE_LANE1 :: VDL_OVERRIDE_3 2299 */ 2300 /* DDR23_PHY_BYTE_LANE1 :: VDL_OVERRIDE_3 :: reserved0 [31:17] */ 2301 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_3_RESERVED0_MASK 0xfffe0000 2302 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_3_RESERVED0_ALIGN 0 2303 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_3_RESERVED0_BITS 15 2304 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_3_RESERVED0_SHIFT 17 2305 2306 /* DDR23_PHY_BYTE_LANE1 :: VDL_OVERRIDE_3 :: ovr_en [16:16] */ 2307 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_3_OVR_EN_MASK 0x00010000 2308 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_3_OVR_EN_ALIGN 0 2309 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_3_OVR_EN_BITS 1 2310 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_3_OVR_EN_SHIFT 16 2311 2312 /* DDR23_PHY_BYTE_LANE1 :: VDL_OVERRIDE_3 :: reserved1 [15:14] */ 2313 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_3_RESERVED1_MASK 0x0000c000 2314 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_3_RESERVED1_ALIGN 0 2315 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_3_RESERVED1_BITS 2 2316 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_3_RESERVED1_SHIFT 14 2317 2318 /* DDR23_PHY_BYTE_LANE1 :: VDL_OVERRIDE_3 :: ovr_fine_fall [13:12] */ 2319 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_3_OVR_FINE_FALL_MASK 0x00003000 2320 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_3_OVR_FINE_FALL_ALIGN 0 2321 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_3_OVR_FINE_FALL_BITS 2 2322 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_3_OVR_FINE_FALL_SHIFT 12 2323 2324 /* DDR23_PHY_BYTE_LANE1 :: VDL_OVERRIDE_3 :: reserved2 [11:10] */ 2325 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_3_RESERVED2_MASK 0x00000c00 2326 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_3_RESERVED2_ALIGN 0 2327 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_3_RESERVED2_BITS 2 2328 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_3_RESERVED2_SHIFT 10 2329 2330 /* DDR23_PHY_BYTE_LANE1 :: VDL_OVERRIDE_3 :: ovr_fine_rise [09:08] */ 2331 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_3_OVR_FINE_RISE_MASK 0x00000300 2332 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_3_OVR_FINE_RISE_ALIGN 0 2333 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_3_OVR_FINE_RISE_BITS 2 2334 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_3_OVR_FINE_RISE_SHIFT 8 2335 2336 /* DDR23_PHY_BYTE_LANE1 :: VDL_OVERRIDE_3 :: reserved3 [07:06] */ 2337 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_3_RESERVED3_MASK 0x000000c0 2338 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_3_RESERVED3_ALIGN 0 2339 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_3_RESERVED3_BITS 2 2340 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_3_RESERVED3_SHIFT 6 2341 2342 /* DDR23_PHY_BYTE_LANE1 :: VDL_OVERRIDE_3 :: ovr_step [05:00] */ 2343 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_3_OVR_STEP_MASK 0x0000003f 2344 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_3_OVR_STEP_ALIGN 0 2345 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_3_OVR_STEP_BITS 6 2346 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_3_OVR_STEP_SHIFT 0 2347 2348 2349 /**************************************************************************** 2350 * DDR23_PHY_BYTE_LANE1 :: VDL_OVERRIDE_4 2351 */ 2352 /* DDR23_PHY_BYTE_LANE1 :: VDL_OVERRIDE_4 :: reserved0 [31:17] */ 2353 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_4_RESERVED0_MASK 0xfffe0000 2354 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_4_RESERVED0_ALIGN 0 2355 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_4_RESERVED0_BITS 15 2356 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_4_RESERVED0_SHIFT 17 2357 2358 /* DDR23_PHY_BYTE_LANE1 :: VDL_OVERRIDE_4 :: ovr_en [16:16] */ 2359 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_4_OVR_EN_MASK 0x00010000 2360 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_4_OVR_EN_ALIGN 0 2361 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_4_OVR_EN_BITS 1 2362 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_4_OVR_EN_SHIFT 16 2363 2364 /* DDR23_PHY_BYTE_LANE1 :: VDL_OVERRIDE_4 :: reserved1 [15:14] */ 2365 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_4_RESERVED1_MASK 0x0000c000 2366 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_4_RESERVED1_ALIGN 0 2367 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_4_RESERVED1_BITS 2 2368 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_4_RESERVED1_SHIFT 14 2369 2370 /* DDR23_PHY_BYTE_LANE1 :: VDL_OVERRIDE_4 :: ovr_fine_fall [13:12] */ 2371 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_4_OVR_FINE_FALL_MASK 0x00003000 2372 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_4_OVR_FINE_FALL_ALIGN 0 2373 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_4_OVR_FINE_FALL_BITS 2 2374 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_4_OVR_FINE_FALL_SHIFT 12 2375 2376 /* DDR23_PHY_BYTE_LANE1 :: VDL_OVERRIDE_4 :: reserved2 [11:10] */ 2377 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_4_RESERVED2_MASK 0x00000c00 2378 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_4_RESERVED2_ALIGN 0 2379 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_4_RESERVED2_BITS 2 2380 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_4_RESERVED2_SHIFT 10 2381 2382 /* DDR23_PHY_BYTE_LANE1 :: VDL_OVERRIDE_4 :: ovr_fine_rise [09:08] */ 2383 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_4_OVR_FINE_RISE_MASK 0x00000300 2384 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_4_OVR_FINE_RISE_ALIGN 0 2385 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_4_OVR_FINE_RISE_BITS 2 2386 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_4_OVR_FINE_RISE_SHIFT 8 2387 2388 /* DDR23_PHY_BYTE_LANE1 :: VDL_OVERRIDE_4 :: reserved3 [07:06] */ 2389 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_4_RESERVED3_MASK 0x000000c0 2390 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_4_RESERVED3_ALIGN 0 2391 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_4_RESERVED3_BITS 2 2392 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_4_RESERVED3_SHIFT 6 2393 2394 /* DDR23_PHY_BYTE_LANE1 :: VDL_OVERRIDE_4 :: ovr_step [05:00] */ 2395 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_4_OVR_STEP_MASK 0x0000003f 2396 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_4_OVR_STEP_ALIGN 0 2397 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_4_OVR_STEP_BITS 6 2398 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_4_OVR_STEP_SHIFT 0 2399 2400 2401 /**************************************************************************** 2402 * DDR23_PHY_BYTE_LANE1 :: VDL_OVERRIDE_5 2403 */ 2404 /* DDR23_PHY_BYTE_LANE1 :: VDL_OVERRIDE_5 :: reserved0 [31:17] */ 2405 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_5_RESERVED0_MASK 0xfffe0000 2406 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_5_RESERVED0_ALIGN 0 2407 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_5_RESERVED0_BITS 15 2408 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_5_RESERVED0_SHIFT 17 2409 2410 /* DDR23_PHY_BYTE_LANE1 :: VDL_OVERRIDE_5 :: ovr_en [16:16] */ 2411 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_5_OVR_EN_MASK 0x00010000 2412 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_5_OVR_EN_ALIGN 0 2413 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_5_OVR_EN_BITS 1 2414 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_5_OVR_EN_SHIFT 16 2415 2416 /* DDR23_PHY_BYTE_LANE1 :: VDL_OVERRIDE_5 :: reserved1 [15:14] */ 2417 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_5_RESERVED1_MASK 0x0000c000 2418 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_5_RESERVED1_ALIGN 0 2419 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_5_RESERVED1_BITS 2 2420 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_5_RESERVED1_SHIFT 14 2421 2422 /* DDR23_PHY_BYTE_LANE1 :: VDL_OVERRIDE_5 :: ovr_fine_fall [13:12] */ 2423 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_5_OVR_FINE_FALL_MASK 0x00003000 2424 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_5_OVR_FINE_FALL_ALIGN 0 2425 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_5_OVR_FINE_FALL_BITS 2 2426 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_5_OVR_FINE_FALL_SHIFT 12 2427 2428 /* DDR23_PHY_BYTE_LANE1 :: VDL_OVERRIDE_5 :: reserved2 [11:10] */ 2429 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_5_RESERVED2_MASK 0x00000c00 2430 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_5_RESERVED2_ALIGN 0 2431 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_5_RESERVED2_BITS 2 2432 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_5_RESERVED2_SHIFT 10 2433 2434 /* DDR23_PHY_BYTE_LANE1 :: VDL_OVERRIDE_5 :: ovr_fine_rise [09:08] */ 2435 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_5_OVR_FINE_RISE_MASK 0x00000300 2436 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_5_OVR_FINE_RISE_ALIGN 0 2437 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_5_OVR_FINE_RISE_BITS 2 2438 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_5_OVR_FINE_RISE_SHIFT 8 2439 2440 /* DDR23_PHY_BYTE_LANE1 :: VDL_OVERRIDE_5 :: reserved3 [07:06] */ 2441 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_5_RESERVED3_MASK 0x000000c0 2442 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_5_RESERVED3_ALIGN 0 2443 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_5_RESERVED3_BITS 2 2444 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_5_RESERVED3_SHIFT 6 2445 2446 /* DDR23_PHY_BYTE_LANE1 :: VDL_OVERRIDE_5 :: ovr_step [05:00] */ 2447 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_5_OVR_STEP_MASK 0x0000003f 2448 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_5_OVR_STEP_ALIGN 0 2449 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_5_OVR_STEP_BITS 6 2450 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_5_OVR_STEP_SHIFT 0 2451 2452 2453 /**************************************************************************** 2454 * DDR23_PHY_BYTE_LANE1 :: VDL_OVERRIDE_6 2455 */ 2456 /* DDR23_PHY_BYTE_LANE1 :: VDL_OVERRIDE_6 :: reserved0 [31:17] */ 2457 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_6_RESERVED0_MASK 0xfffe0000 2458 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_6_RESERVED0_ALIGN 0 2459 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_6_RESERVED0_BITS 15 2460 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_6_RESERVED0_SHIFT 17 2461 2462 /* DDR23_PHY_BYTE_LANE1 :: VDL_OVERRIDE_6 :: ovr_en [16:16] */ 2463 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_6_OVR_EN_MASK 0x00010000 2464 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_6_OVR_EN_ALIGN 0 2465 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_6_OVR_EN_BITS 1 2466 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_6_OVR_EN_SHIFT 16 2467 2468 /* DDR23_PHY_BYTE_LANE1 :: VDL_OVERRIDE_6 :: reserved1 [15:14] */ 2469 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_6_RESERVED1_MASK 0x0000c000 2470 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_6_RESERVED1_ALIGN 0 2471 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_6_RESERVED1_BITS 2 2472 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_6_RESERVED1_SHIFT 14 2473 2474 /* DDR23_PHY_BYTE_LANE1 :: VDL_OVERRIDE_6 :: ovr_fine_fall [13:12] */ 2475 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_6_OVR_FINE_FALL_MASK 0x00003000 2476 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_6_OVR_FINE_FALL_ALIGN 0 2477 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_6_OVR_FINE_FALL_BITS 2 2478 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_6_OVR_FINE_FALL_SHIFT 12 2479 2480 /* DDR23_PHY_BYTE_LANE1 :: VDL_OVERRIDE_6 :: reserved2 [11:10] */ 2481 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_6_RESERVED2_MASK 0x00000c00 2482 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_6_RESERVED2_ALIGN 0 2483 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_6_RESERVED2_BITS 2 2484 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_6_RESERVED2_SHIFT 10 2485 2486 /* DDR23_PHY_BYTE_LANE1 :: VDL_OVERRIDE_6 :: ovr_fine_rise [09:08] */ 2487 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_6_OVR_FINE_RISE_MASK 0x00000300 2488 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_6_OVR_FINE_RISE_ALIGN 0 2489 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_6_OVR_FINE_RISE_BITS 2 2490 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_6_OVR_FINE_RISE_SHIFT 8 2491 2492 /* DDR23_PHY_BYTE_LANE1 :: VDL_OVERRIDE_6 :: reserved3 [07:06] */ 2493 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_6_RESERVED3_MASK 0x000000c0 2494 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_6_RESERVED3_ALIGN 0 2495 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_6_RESERVED3_BITS 2 2496 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_6_RESERVED3_SHIFT 6 2497 2498 /* DDR23_PHY_BYTE_LANE1 :: VDL_OVERRIDE_6 :: ovr_step [05:00] */ 2499 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_6_OVR_STEP_MASK 0x0000003f 2500 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_6_OVR_STEP_ALIGN 0 2501 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_6_OVR_STEP_BITS 6 2502 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_6_OVR_STEP_SHIFT 0 2503 2504 2505 /**************************************************************************** 2506 * DDR23_PHY_BYTE_LANE1 :: VDL_OVERRIDE_7 2507 */ 2508 /* DDR23_PHY_BYTE_LANE1 :: VDL_OVERRIDE_7 :: reserved0 [31:17] */ 2509 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_7_RESERVED0_MASK 0xfffe0000 2510 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_7_RESERVED0_ALIGN 0 2511 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_7_RESERVED0_BITS 15 2512 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_7_RESERVED0_SHIFT 17 2513 2514 /* DDR23_PHY_BYTE_LANE1 :: VDL_OVERRIDE_7 :: ovr_en [16:16] */ 2515 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_7_OVR_EN_MASK 0x00010000 2516 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_7_OVR_EN_ALIGN 0 2517 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_7_OVR_EN_BITS 1 2518 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_7_OVR_EN_SHIFT 16 2519 2520 /* DDR23_PHY_BYTE_LANE1 :: VDL_OVERRIDE_7 :: reserved1 [15:14] */ 2521 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_7_RESERVED1_MASK 0x0000c000 2522 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_7_RESERVED1_ALIGN 0 2523 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_7_RESERVED1_BITS 2 2524 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_7_RESERVED1_SHIFT 14 2525 2526 /* DDR23_PHY_BYTE_LANE1 :: VDL_OVERRIDE_7 :: ovr_fine_fall [13:12] */ 2527 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_7_OVR_FINE_FALL_MASK 0x00003000 2528 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_7_OVR_FINE_FALL_ALIGN 0 2529 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_7_OVR_FINE_FALL_BITS 2 2530 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_7_OVR_FINE_FALL_SHIFT 12 2531 2532 /* DDR23_PHY_BYTE_LANE1 :: VDL_OVERRIDE_7 :: reserved2 [11:10] */ 2533 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_7_RESERVED2_MASK 0x00000c00 2534 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_7_RESERVED2_ALIGN 0 2535 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_7_RESERVED2_BITS 2 2536 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_7_RESERVED2_SHIFT 10 2537 2538 /* DDR23_PHY_BYTE_LANE1 :: VDL_OVERRIDE_7 :: ovr_fine_rise [09:08] */ 2539 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_7_OVR_FINE_RISE_MASK 0x00000300 2540 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_7_OVR_FINE_RISE_ALIGN 0 2541 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_7_OVR_FINE_RISE_BITS 2 2542 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_7_OVR_FINE_RISE_SHIFT 8 2543 2544 /* DDR23_PHY_BYTE_LANE1 :: VDL_OVERRIDE_7 :: reserved3 [07:06] */ 2545 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_7_RESERVED3_MASK 0x000000c0 2546 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_7_RESERVED3_ALIGN 0 2547 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_7_RESERVED3_BITS 2 2548 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_7_RESERVED3_SHIFT 6 2549 2550 /* DDR23_PHY_BYTE_LANE1 :: VDL_OVERRIDE_7 :: ovr_step [05:00] */ 2551 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_7_OVR_STEP_MASK 0x0000003f 2552 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_7_OVR_STEP_ALIGN 0 2553 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_7_OVR_STEP_BITS 6 2554 #define DDR23_PHY_BYTE_LANE1_VDL_OVERRIDE_7_OVR_STEP_SHIFT 0 2555 2556 2557 /**************************************************************************** 2558 * DDR23_PHY_BYTE_LANE1 :: READ_CONTROL 2559 */ 2560 /* DDR23_PHY_BYTE_LANE1 :: READ_CONTROL :: reserved0 [31:10] */ 2561 #define DDR23_PHY_BYTE_LANE1_READ_CONTROL_RESERVED0_MASK 0xfffffc00 2562 #define DDR23_PHY_BYTE_LANE1_READ_CONTROL_RESERVED0_ALIGN 0 2563 #define DDR23_PHY_BYTE_LANE1_READ_CONTROL_RESERVED0_BITS 22 2564 #define DDR23_PHY_BYTE_LANE1_READ_CONTROL_RESERVED0_SHIFT 10 2565 2566 /* DDR23_PHY_BYTE_LANE1 :: READ_CONTROL :: rd_data_dly [09:08] */ 2567 #define DDR23_PHY_BYTE_LANE1_READ_CONTROL_RD_DATA_DLY_MASK 0x00000300 2568 #define DDR23_PHY_BYTE_LANE1_READ_CONTROL_RD_DATA_DLY_ALIGN 0 2569 #define DDR23_PHY_BYTE_LANE1_READ_CONTROL_RD_DATA_DLY_BITS 2 2570 #define DDR23_PHY_BYTE_LANE1_READ_CONTROL_RD_DATA_DLY_SHIFT 8 2571 2572 /* DDR23_PHY_BYTE_LANE1 :: READ_CONTROL :: reserved1 [07:04] */ 2573 #define DDR23_PHY_BYTE_LANE1_READ_CONTROL_RESERVED1_MASK 0x000000f0 2574 #define DDR23_PHY_BYTE_LANE1_READ_CONTROL_RESERVED1_ALIGN 0 2575 #define DDR23_PHY_BYTE_LANE1_READ_CONTROL_RESERVED1_BITS 4 2576 #define DDR23_PHY_BYTE_LANE1_READ_CONTROL_RESERVED1_SHIFT 4 2577 2578 /* DDR23_PHY_BYTE_LANE1 :: READ_CONTROL :: dq_odt_enable [03:03] */ 2579 #define DDR23_PHY_BYTE_LANE1_READ_CONTROL_DQ_ODT_ENABLE_MASK 0x00000008 2580 #define DDR23_PHY_BYTE_LANE1_READ_CONTROL_DQ_ODT_ENABLE_ALIGN 0 2581 #define DDR23_PHY_BYTE_LANE1_READ_CONTROL_DQ_ODT_ENABLE_BITS 1 2582 #define DDR23_PHY_BYTE_LANE1_READ_CONTROL_DQ_ODT_ENABLE_SHIFT 3 2583 2584 /* DDR23_PHY_BYTE_LANE1 :: READ_CONTROL :: dq_odt_adj [02:02] */ 2585 #define DDR23_PHY_BYTE_LANE1_READ_CONTROL_DQ_ODT_ADJ_MASK 0x00000004 2586 #define DDR23_PHY_BYTE_LANE1_READ_CONTROL_DQ_ODT_ADJ_ALIGN 0 2587 #define DDR23_PHY_BYTE_LANE1_READ_CONTROL_DQ_ODT_ADJ_BITS 1 2588 #define DDR23_PHY_BYTE_LANE1_READ_CONTROL_DQ_ODT_ADJ_SHIFT 2 2589 2590 /* DDR23_PHY_BYTE_LANE1 :: READ_CONTROL :: rd_enb_odt_enable [01:01] */ 2591 #define DDR23_PHY_BYTE_LANE1_READ_CONTROL_RD_ENB_ODT_ENABLE_MASK 0x00000002 2592 #define DDR23_PHY_BYTE_LANE1_READ_CONTROL_RD_ENB_ODT_ENABLE_ALIGN 0 2593 #define DDR23_PHY_BYTE_LANE1_READ_CONTROL_RD_ENB_ODT_ENABLE_BITS 1 2594 #define DDR23_PHY_BYTE_LANE1_READ_CONTROL_RD_ENB_ODT_ENABLE_SHIFT 1 2595 2596 /* DDR23_PHY_BYTE_LANE1 :: READ_CONTROL :: rd_enb_odt_adj [00:00] */ 2597 #define DDR23_PHY_BYTE_LANE1_READ_CONTROL_RD_ENB_ODT_ADJ_MASK 0x00000001 2598 #define DDR23_PHY_BYTE_LANE1_READ_CONTROL_RD_ENB_ODT_ADJ_ALIGN 0 2599 #define DDR23_PHY_BYTE_LANE1_READ_CONTROL_RD_ENB_ODT_ADJ_BITS 1 2600 #define DDR23_PHY_BYTE_LANE1_READ_CONTROL_RD_ENB_ODT_ADJ_SHIFT 0 2601 2602 2603 /**************************************************************************** 2604 * DDR23_PHY_BYTE_LANE1 :: READ_FIFO_STATUS 2605 */ 2606 /* DDR23_PHY_BYTE_LANE1 :: READ_FIFO_STATUS :: reserved0 [31:04] */ 2607 #define DDR23_PHY_BYTE_LANE1_READ_FIFO_STATUS_RESERVED0_MASK 0xfffffff0 2608 #define DDR23_PHY_BYTE_LANE1_READ_FIFO_STATUS_RESERVED0_ALIGN 0 2609 #define DDR23_PHY_BYTE_LANE1_READ_FIFO_STATUS_RESERVED0_BITS 28 2610 #define DDR23_PHY_BYTE_LANE1_READ_FIFO_STATUS_RESERVED0_SHIFT 4 2611 2612 /* DDR23_PHY_BYTE_LANE1 :: READ_FIFO_STATUS :: status [03:00] */ 2613 #define DDR23_PHY_BYTE_LANE1_READ_FIFO_STATUS_STATUS_MASK 0x0000000f 2614 #define DDR23_PHY_BYTE_LANE1_READ_FIFO_STATUS_STATUS_ALIGN 0 2615 #define DDR23_PHY_BYTE_LANE1_READ_FIFO_STATUS_STATUS_BITS 4 2616 #define DDR23_PHY_BYTE_LANE1_READ_FIFO_STATUS_STATUS_SHIFT 0 2617 2618 2619 /**************************************************************************** 2620 * DDR23_PHY_BYTE_LANE1 :: READ_FIFO_CLEAR 2621 */ 2622 /* DDR23_PHY_BYTE_LANE1 :: READ_FIFO_CLEAR :: reserved0 [31:01] */ 2623 #define DDR23_PHY_BYTE_LANE1_READ_FIFO_CLEAR_RESERVED0_MASK 0xfffffffe 2624 #define DDR23_PHY_BYTE_LANE1_READ_FIFO_CLEAR_RESERVED0_ALIGN 0 2625 #define DDR23_PHY_BYTE_LANE1_READ_FIFO_CLEAR_RESERVED0_BITS 31 2626 #define DDR23_PHY_BYTE_LANE1_READ_FIFO_CLEAR_RESERVED0_SHIFT 1 2627 2628 /* DDR23_PHY_BYTE_LANE1 :: READ_FIFO_CLEAR :: clear [00:00] */ 2629 #define DDR23_PHY_BYTE_LANE1_READ_FIFO_CLEAR_CLEAR_MASK 0x00000001 2630 #define DDR23_PHY_BYTE_LANE1_READ_FIFO_CLEAR_CLEAR_ALIGN 0 2631 #define DDR23_PHY_BYTE_LANE1_READ_FIFO_CLEAR_CLEAR_BITS 1 2632 #define DDR23_PHY_BYTE_LANE1_READ_FIFO_CLEAR_CLEAR_SHIFT 0 2633 2634 2635 /**************************************************************************** 2636 * DDR23_PHY_BYTE_LANE1 :: IDLE_PAD_CONTROL 2637 */ 2638 /* DDR23_PHY_BYTE_LANE1 :: IDLE_PAD_CONTROL :: idle [31:31] */ 2639 #define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_IDLE_MASK 0x80000000 2640 #define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_IDLE_ALIGN 0 2641 #define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_IDLE_BITS 1 2642 #define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_IDLE_SHIFT 31 2643 2644 /* DDR23_PHY_BYTE_LANE1 :: IDLE_PAD_CONTROL :: reserved0 [30:20] */ 2645 #define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_RESERVED0_MASK 0x7ff00000 2646 #define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_RESERVED0_ALIGN 0 2647 #define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_RESERVED0_BITS 11 2648 #define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_RESERVED0_SHIFT 20 2649 2650 /* DDR23_PHY_BYTE_LANE1 :: IDLE_PAD_CONTROL :: dm_rxenb [19:19] */ 2651 #define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_DM_RXENB_MASK 0x00080000 2652 #define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_DM_RXENB_ALIGN 0 2653 #define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_DM_RXENB_BITS 1 2654 #define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_DM_RXENB_SHIFT 19 2655 2656 /* DDR23_PHY_BYTE_LANE1 :: IDLE_PAD_CONTROL :: dm_iddq [18:18] */ 2657 #define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_DM_IDDQ_MASK 0x00040000 2658 #define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_DM_IDDQ_ALIGN 0 2659 #define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_DM_IDDQ_BITS 1 2660 #define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_DM_IDDQ_SHIFT 18 2661 2662 /* DDR23_PHY_BYTE_LANE1 :: IDLE_PAD_CONTROL :: dm_reb [17:17] */ 2663 #define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_DM_REB_MASK 0x00020000 2664 #define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_DM_REB_ALIGN 0 2665 #define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_DM_REB_BITS 1 2666 #define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_DM_REB_SHIFT 17 2667 2668 /* DDR23_PHY_BYTE_LANE1 :: IDLE_PAD_CONTROL :: dm_oeb [16:16] */ 2669 #define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_DM_OEB_MASK 0x00010000 2670 #define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_DM_OEB_ALIGN 0 2671 #define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_DM_OEB_BITS 1 2672 #define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_DM_OEB_SHIFT 16 2673 2674 /* DDR23_PHY_BYTE_LANE1 :: IDLE_PAD_CONTROL :: dq_rxenb [15:15] */ 2675 #define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_DQ_RXENB_MASK 0x00008000 2676 #define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_DQ_RXENB_ALIGN 0 2677 #define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_DQ_RXENB_BITS 1 2678 #define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_DQ_RXENB_SHIFT 15 2679 2680 /* DDR23_PHY_BYTE_LANE1 :: IDLE_PAD_CONTROL :: dq_iddq [14:14] */ 2681 #define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_DQ_IDDQ_MASK 0x00004000 2682 #define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_DQ_IDDQ_ALIGN 0 2683 #define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_DQ_IDDQ_BITS 1 2684 #define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_DQ_IDDQ_SHIFT 14 2685 2686 /* DDR23_PHY_BYTE_LANE1 :: IDLE_PAD_CONTROL :: dq_reb [13:13] */ 2687 #define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_DQ_REB_MASK 0x00002000 2688 #define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_DQ_REB_ALIGN 0 2689 #define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_DQ_REB_BITS 1 2690 #define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_DQ_REB_SHIFT 13 2691 2692 /* DDR23_PHY_BYTE_LANE1 :: IDLE_PAD_CONTROL :: dq_oeb [12:12] */ 2693 #define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_DQ_OEB_MASK 0x00001000 2694 #define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_DQ_OEB_ALIGN 0 2695 #define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_DQ_OEB_BITS 1 2696 #define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_DQ_OEB_SHIFT 12 2697 2698 /* DDR23_PHY_BYTE_LANE1 :: IDLE_PAD_CONTROL :: read_enb_rxenb [11:11] */ 2699 #define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_READ_ENB_RXENB_MASK 0x00000800 2700 #define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_READ_ENB_RXENB_ALIGN 0 2701 #define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_READ_ENB_RXENB_BITS 1 2702 #define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_READ_ENB_RXENB_SHIFT 11 2703 2704 /* DDR23_PHY_BYTE_LANE1 :: IDLE_PAD_CONTROL :: read_enb_iddq [10:10] */ 2705 #define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_READ_ENB_IDDQ_MASK 0x00000400 2706 #define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_READ_ENB_IDDQ_ALIGN 0 2707 #define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_READ_ENB_IDDQ_BITS 1 2708 #define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_READ_ENB_IDDQ_SHIFT 10 2709 2710 /* DDR23_PHY_BYTE_LANE1 :: IDLE_PAD_CONTROL :: read_enb_reb [09:09] */ 2711 #define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_READ_ENB_REB_MASK 0x00000200 2712 #define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_READ_ENB_REB_ALIGN 0 2713 #define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_READ_ENB_REB_BITS 1 2714 #define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_READ_ENB_REB_SHIFT 9 2715 2716 /* DDR23_PHY_BYTE_LANE1 :: IDLE_PAD_CONTROL :: read_enb_oeb [08:08] */ 2717 #define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_READ_ENB_OEB_MASK 0x00000100 2718 #define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_READ_ENB_OEB_ALIGN 0 2719 #define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_READ_ENB_OEB_BITS 1 2720 #define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_READ_ENB_OEB_SHIFT 8 2721 2722 /* DDR23_PHY_BYTE_LANE1 :: IDLE_PAD_CONTROL :: dqs_rxenb [07:07] */ 2723 #define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_DQS_RXENB_MASK 0x00000080 2724 #define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_DQS_RXENB_ALIGN 0 2725 #define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_DQS_RXENB_BITS 1 2726 #define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_DQS_RXENB_SHIFT 7 2727 2728 /* DDR23_PHY_BYTE_LANE1 :: IDLE_PAD_CONTROL :: dqs_iddq [06:06] */ 2729 #define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_DQS_IDDQ_MASK 0x00000040 2730 #define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_DQS_IDDQ_ALIGN 0 2731 #define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_DQS_IDDQ_BITS 1 2732 #define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_DQS_IDDQ_SHIFT 6 2733 2734 /* DDR23_PHY_BYTE_LANE1 :: IDLE_PAD_CONTROL :: dqs_reb [05:05] */ 2735 #define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_DQS_REB_MASK 0x00000020 2736 #define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_DQS_REB_ALIGN 0 2737 #define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_DQS_REB_BITS 1 2738 #define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_DQS_REB_SHIFT 5 2739 2740 /* DDR23_PHY_BYTE_LANE1 :: IDLE_PAD_CONTROL :: dqs_oeb [04:04] */ 2741 #define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_DQS_OEB_MASK 0x00000010 2742 #define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_DQS_OEB_ALIGN 0 2743 #define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_DQS_OEB_BITS 1 2744 #define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_DQS_OEB_SHIFT 4 2745 2746 /* DDR23_PHY_BYTE_LANE1 :: IDLE_PAD_CONTROL :: clk_rxenb [03:03] */ 2747 #define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_CLK_RXENB_MASK 0x00000008 2748 #define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_CLK_RXENB_ALIGN 0 2749 #define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_CLK_RXENB_BITS 1 2750 #define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_CLK_RXENB_SHIFT 3 2751 2752 /* DDR23_PHY_BYTE_LANE1 :: IDLE_PAD_CONTROL :: clk_iddq [02:02] */ 2753 #define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_CLK_IDDQ_MASK 0x00000004 2754 #define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_CLK_IDDQ_ALIGN 0 2755 #define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_CLK_IDDQ_BITS 1 2756 #define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_CLK_IDDQ_SHIFT 2 2757 2758 /* DDR23_PHY_BYTE_LANE1 :: IDLE_PAD_CONTROL :: clk_reb [01:01] */ 2759 #define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_CLK_REB_MASK 0x00000002 2760 #define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_CLK_REB_ALIGN 0 2761 #define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_CLK_REB_BITS 1 2762 #define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_CLK_REB_SHIFT 1 2763 2764 /* DDR23_PHY_BYTE_LANE1 :: IDLE_PAD_CONTROL :: clk_oeb [00:00] */ 2765 #define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_CLK_OEB_MASK 0x00000001 2766 #define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_CLK_OEB_ALIGN 0 2767 #define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_CLK_OEB_BITS 1 2768 #define DDR23_PHY_BYTE_LANE1_IDLE_PAD_CONTROL_CLK_OEB_SHIFT 0 2769 2770 2771 /**************************************************************************** 2772 * DDR23_PHY_BYTE_LANE1 :: DRIVE_PAD_CTL 2773 */ 2774 /* DDR23_PHY_BYTE_LANE1 :: DRIVE_PAD_CTL :: reserved0 [31:06] */ 2775 #define DDR23_PHY_BYTE_LANE1_DRIVE_PAD_CTL_RESERVED0_MASK 0xffffffc0 2776 #define DDR23_PHY_BYTE_LANE1_DRIVE_PAD_CTL_RESERVED0_ALIGN 0 2777 #define DDR23_PHY_BYTE_LANE1_DRIVE_PAD_CTL_RESERVED0_BITS 26 2778 #define DDR23_PHY_BYTE_LANE1_DRIVE_PAD_CTL_RESERVED0_SHIFT 6 2779 2780 /* DDR23_PHY_BYTE_LANE1 :: DRIVE_PAD_CTL :: rt60b_ddr_read_enb [05:05] */ 2781 #define DDR23_PHY_BYTE_LANE1_DRIVE_PAD_CTL_RT60B_DDR_READ_ENB_MASK 0x00000020 2782 #define DDR23_PHY_BYTE_LANE1_DRIVE_PAD_CTL_RT60B_DDR_READ_ENB_ALIGN 0 2783 #define DDR23_PHY_BYTE_LANE1_DRIVE_PAD_CTL_RT60B_DDR_READ_ENB_BITS 1 2784 #define DDR23_PHY_BYTE_LANE1_DRIVE_PAD_CTL_RT60B_DDR_READ_ENB_SHIFT 5 2785 2786 /* DDR23_PHY_BYTE_LANE1 :: DRIVE_PAD_CTL :: rt60b [04:04] */ 2787 #define DDR23_PHY_BYTE_LANE1_DRIVE_PAD_CTL_RT60B_MASK 0x00000010 2788 #define DDR23_PHY_BYTE_LANE1_DRIVE_PAD_CTL_RT60B_ALIGN 0 2789 #define DDR23_PHY_BYTE_LANE1_DRIVE_PAD_CTL_RT60B_BITS 1 2790 #define DDR23_PHY_BYTE_LANE1_DRIVE_PAD_CTL_RT60B_SHIFT 4 2791 2792 /* DDR23_PHY_BYTE_LANE1 :: DRIVE_PAD_CTL :: sel_sstl18 [03:03] */ 2793 #define DDR23_PHY_BYTE_LANE1_DRIVE_PAD_CTL_SEL_SSTL18_MASK 0x00000008 2794 #define DDR23_PHY_BYTE_LANE1_DRIVE_PAD_CTL_SEL_SSTL18_ALIGN 0 2795 #define DDR23_PHY_BYTE_LANE1_DRIVE_PAD_CTL_SEL_SSTL18_BITS 1 2796 #define DDR23_PHY_BYTE_LANE1_DRIVE_PAD_CTL_SEL_SSTL18_SHIFT 3 2797 2798 /* DDR23_PHY_BYTE_LANE1 :: DRIVE_PAD_CTL :: seltxdrv_ci [02:02] */ 2799 #define DDR23_PHY_BYTE_LANE1_DRIVE_PAD_CTL_SELTXDRV_CI_MASK 0x00000004 2800 #define DDR23_PHY_BYTE_LANE1_DRIVE_PAD_CTL_SELTXDRV_CI_ALIGN 0 2801 #define DDR23_PHY_BYTE_LANE1_DRIVE_PAD_CTL_SELTXDRV_CI_BITS 1 2802 #define DDR23_PHY_BYTE_LANE1_DRIVE_PAD_CTL_SELTXDRV_CI_SHIFT 2 2803 2804 /* DDR23_PHY_BYTE_LANE1 :: DRIVE_PAD_CTL :: selrxdrv [01:01] */ 2805 #define DDR23_PHY_BYTE_LANE1_DRIVE_PAD_CTL_SELRXDRV_MASK 0x00000002 2806 #define DDR23_PHY_BYTE_LANE1_DRIVE_PAD_CTL_SELRXDRV_ALIGN 0 2807 #define DDR23_PHY_BYTE_LANE1_DRIVE_PAD_CTL_SELRXDRV_BITS 1 2808 #define DDR23_PHY_BYTE_LANE1_DRIVE_PAD_CTL_SELRXDRV_SHIFT 1 2809 2810 /* DDR23_PHY_BYTE_LANE1 :: DRIVE_PAD_CTL :: slew [00:00] */ 2811 #define DDR23_PHY_BYTE_LANE1_DRIVE_PAD_CTL_SLEW_MASK 0x00000001 2812 #define DDR23_PHY_BYTE_LANE1_DRIVE_PAD_CTL_SLEW_ALIGN 0 2813 #define DDR23_PHY_BYTE_LANE1_DRIVE_PAD_CTL_SLEW_BITS 1 2814 #define DDR23_PHY_BYTE_LANE1_DRIVE_PAD_CTL_SLEW_SHIFT 0 2815 2816 2817 /**************************************************************************** 2818 * DDR23_PHY_BYTE_LANE1 :: CLOCK_PAD_DISABLE 2819 */ 2820 /* DDR23_PHY_BYTE_LANE1 :: CLOCK_PAD_DISABLE :: reserved0 [31:01] */ 2821 #define DDR23_PHY_BYTE_LANE1_CLOCK_PAD_DISABLE_RESERVED0_MASK 0xfffffffe 2822 #define DDR23_PHY_BYTE_LANE1_CLOCK_PAD_DISABLE_RESERVED0_ALIGN 0 2823 #define DDR23_PHY_BYTE_LANE1_CLOCK_PAD_DISABLE_RESERVED0_BITS 31 2824 #define DDR23_PHY_BYTE_LANE1_CLOCK_PAD_DISABLE_RESERVED0_SHIFT 1 2825 2826 /* DDR23_PHY_BYTE_LANE1 :: CLOCK_PAD_DISABLE :: clk_pad_dis [00:00] */ 2827 #define DDR23_PHY_BYTE_LANE1_CLOCK_PAD_DISABLE_CLK_PAD_DIS_MASK 0x00000001 2828 #define DDR23_PHY_BYTE_LANE1_CLOCK_PAD_DISABLE_CLK_PAD_DIS_ALIGN 0 2829 #define DDR23_PHY_BYTE_LANE1_CLOCK_PAD_DISABLE_CLK_PAD_DIS_BITS 1 2830 #define DDR23_PHY_BYTE_LANE1_CLOCK_PAD_DISABLE_CLK_PAD_DIS_SHIFT 0 2831 2832 2833 /**************************************************************************** 2834 * DDR23_PHY_BYTE_LANE1 :: WR_PREAMBLE_MODE 2835 */ 2836 /* DDR23_PHY_BYTE_LANE1 :: WR_PREAMBLE_MODE :: reserved0 [31:01] */ 2837 #define DDR23_PHY_BYTE_LANE1_WR_PREAMBLE_MODE_RESERVED0_MASK 0xfffffffe 2838 #define DDR23_PHY_BYTE_LANE1_WR_PREAMBLE_MODE_RESERVED0_ALIGN 0 2839 #define DDR23_PHY_BYTE_LANE1_WR_PREAMBLE_MODE_RESERVED0_BITS 31 2840 #define DDR23_PHY_BYTE_LANE1_WR_PREAMBLE_MODE_RESERVED0_SHIFT 1 2841 2842 /* DDR23_PHY_BYTE_LANE1 :: WR_PREAMBLE_MODE :: mode [00:00] */ 2843 #define DDR23_PHY_BYTE_LANE1_WR_PREAMBLE_MODE_MODE_MASK 0x00000001 2844 #define DDR23_PHY_BYTE_LANE1_WR_PREAMBLE_MODE_MODE_ALIGN 0 2845 #define DDR23_PHY_BYTE_LANE1_WR_PREAMBLE_MODE_MODE_BITS 1 2846 #define DDR23_PHY_BYTE_LANE1_WR_PREAMBLE_MODE_MODE_SHIFT 0 2847 2848 2849 /**************************************************************************** 2850 * DDR23_PHY_BYTE_LANE1 :: CLOCK_REG_CONTROL 2851 */ 2852 /* DDR23_PHY_BYTE_LANE1 :: CLOCK_REG_CONTROL :: reserved0 [31:02] */ 2853 #define DDR23_PHY_BYTE_LANE1_CLOCK_REG_CONTROL_RESERVED0_MASK 0xfffffffc 2854 #define DDR23_PHY_BYTE_LANE1_CLOCK_REG_CONTROL_RESERVED0_ALIGN 0 2855 #define DDR23_PHY_BYTE_LANE1_CLOCK_REG_CONTROL_RESERVED0_BITS 30 2856 #define DDR23_PHY_BYTE_LANE1_CLOCK_REG_CONTROL_RESERVED0_SHIFT 2 2857 2858 /* DDR23_PHY_BYTE_LANE1 :: CLOCK_REG_CONTROL :: half_power [01:01] */ 2859 #define DDR23_PHY_BYTE_LANE1_CLOCK_REG_CONTROL_HALF_POWER_MASK 0x00000002 2860 #define DDR23_PHY_BYTE_LANE1_CLOCK_REG_CONTROL_HALF_POWER_ALIGN 0 2861 #define DDR23_PHY_BYTE_LANE1_CLOCK_REG_CONTROL_HALF_POWER_BITS 1 2862 #define DDR23_PHY_BYTE_LANE1_CLOCK_REG_CONTROL_HALF_POWER_SHIFT 1 2863 2864 /* DDR23_PHY_BYTE_LANE1 :: CLOCK_REG_CONTROL :: pwrdn [00:00] */ 2865 #define DDR23_PHY_BYTE_LANE1_CLOCK_REG_CONTROL_PWRDN_MASK 0x00000001 2866 #define DDR23_PHY_BYTE_LANE1_CLOCK_REG_CONTROL_PWRDN_ALIGN 0 2867 #define DDR23_PHY_BYTE_LANE1_CLOCK_REG_CONTROL_PWRDN_BITS 1 2868 #define DDR23_PHY_BYTE_LANE1_CLOCK_REG_CONTROL_PWRDN_SHIFT 0 2869 2870 2871 /**************************************************************************** 2872 * Datatype Definitions. 2873 */ 2874 #endif /* #ifndef DDR23_H__ */ 2875 2876 /* End of File */ 2877