phy.h (26825B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * Useful constants and routines for PHY chips which 8 * run with Orion (10/100/1000 Mb/s enet) and use MII, GMII, 9 * or 8b/10b Serdes interfaces. 10 * 11 * See Also: IEEE 802.3 (1998) Local and Metropolitan Area Networks 12 * Sections 22.2.4-XX 13 */ 14 15 #ifndef _SOC_PHY_H 16 #define _SOC_PHY_H 17 18 #include <soc/phy/drv.h> 19 #undef BIT 20 #define BIT(_n_) (1U << (_n_)) 21 22 /* Standard MII Registers */ 23 24 #define MII_CTRL_REG 0x00 /* MII Control Register : r/w */ 25 #define MII_STAT_REG 0x01 /* MII Status Register: ro */ 26 #define MII_PHY_ID0_REG 0x02 /* MII PHY ID register: r/w */ 27 #define MII_PHY_ID1_REG 0x03 /* MII PHY ID register: r/w */ 28 #define MII_ANA_REG 0x04 /* MII Auto-Neg Advertisement: r/w */ 29 #define MII_ANP_REG 0x05 /* MII Auto-Neg Link Partner: ro */ 30 #define MII_AN_EXP_REG 0x06 /* MII Auto-Neg Expansion: ro */ 31 #define MII_GB_CTRL_REG 0x09 /* MII 1000Base-T control register */ 32 #define MII_GB_STAT_REG 0x0a /* MII 1000Base-T Status register */ 33 #define MII_ESR_REG 0x0f /* MII Extended Status register */ 34 35 /* Non-standard MII Registers */ 36 37 #define MII_ECR_REG 0x10 /* MII Extended Control Register */ 38 #define MII_AUX_REG 0x18 /* MII Auxiliary Control/Status Register */ 39 #define MII_ASSR_REG 0x19 /* MII Auxiliary Status Summary Reg */ 40 #define MII_GSR_REG 0x1c /* MII General status (BROADCOM) */ 41 #define MII_MSSEED_REG 0x1d /* MII Master/slave seed (BROADCOM) */ 42 #define MII_AUX_MULTI_PHY_REG 0x1e /* Auxiliary Multiple PHY (BROADCOM) */ 43 #define MII_TEST2_REG 0x1f /* MII Test reg (BROADCOM) */ 44 45 #define MII_SHA_CD_CTRL_REG 0x13 /*13h-0;13h-1;13h-2;13h-3; 46 *13h-4;13h-5;13h-6;13h-7 */ 47 #define MII_SHA_CD_SEL_REG 0x14 48 #define MII_SHA_AUX_STAT2_REG 0x1B 49 #define MII_BRCM_TEST_REG 0x1F 50 51 52 /* MII Control Register: bit definitions */ 53 54 #define MII_CTRL_FS_2500 (1 << 5) /* Force speed to 2500 Mbps */ 55 #define MII_CTRL_SS_MSB (1 << 6) /* Speed select, MSb */ 56 #define MII_CTRL_CST (1 << 7) /* Collision Signal test */ 57 #define MII_CTRL_FD (1 << 8) /* Full Duplex */ 58 #define MII_CTRL_RAN (1 << 9) /* Restart Autonegotiation */ 59 #define MII_CTRL_IP (1 << 10) /* Isolate Phy */ 60 #define MII_CTRL_PD (1 << 11) /* Power Down */ 61 #define MII_CTRL_AE (1 << 12) /* Autonegotiation enable */ 62 #define MII_CTRL_SS_LSB (1 << 13) /* Speed select, LSb */ 63 #define MII_CTRL_LE (1 << 14) /* Loopback enable */ 64 #define MII_CTRL_RESET (1 << 15) /* PHY reset */ 65 66 #define MII_CTRL_SS(_x) ((_x) & (MII_CTRL_SS_LSB|MII_CTRL_SS_MSB)) 67 #define MII_CTRL_SS_10 0 68 #define MII_CTRL_SS_100 (MII_CTRL_SS_LSB) 69 #define MII_CTRL_SS_1000 (MII_CTRL_SS_MSB) 70 #define MII_CTRL_SS_INVALID (MII_CTRL_SS_LSB | MII_CTRL_SS_MSB) 71 #define MII_CTRL_SS_MASK (MII_CTRL_SS_LSB | MII_CTRL_SS_MSB) 72 73 /* 74 * MII Status Register: See 802.3, 1998 pg 544 75 */ 76 #define MII_STAT_EXT (1 << 0) /* Extended Registers */ 77 #define MII_STAT_JBBR (1 << 1) /* Jabber Detected */ 78 #define MII_STAT_LA (1 << 2) /* Link Active */ 79 #define MII_STAT_AN_CAP (1 << 3) /* Autoneg capable */ 80 #define MII_STAT_RF (1 << 4) /* Remote Fault */ 81 #define MII_STAT_AN_DONE (1 << 5) /* Autoneg complete */ 82 #define MII_STAT_MF_PS (1 << 6) /* Preamble suppression */ 83 #define MII_STAT_ES (1 << 8) /* Extended status (R15) */ 84 #define MII_STAT_HD_100_T2 (1 << 9) /* Half duplex 100Mb/s supported */ 85 #define MII_STAT_FD_100_T2 (1 << 10)/* Full duplex 100Mb/s supported */ 86 #define MII_STAT_HD_10 (1 << 11)/* Half duplex 100Mb/s supported */ 87 #define MII_STAT_FD_10 (1 << 12)/* Full duplex 100Mb/s supported */ 88 #define MII_STAT_HD_100 (1 << 13)/* Half duplex 100Mb/s supported */ 89 #define MII_STAT_FD_100 (1 << 14)/* Full duplex 100Mb/s supported */ 90 #define MII_STAT_100_T4 (1 << 15)/* Full duplex 100Mb/s supported */ 91 92 /* 93 * MII Link Advertisment 94 */ 95 #define MII_ANA_ASF (1 << 0)/* Advertise Selector Field */ 96 #define MII_ANA_HD_10 (1 << 5)/* Half duplex 10Mb/s supported */ 97 #define MII_ANA_FD_10 (1 << 6)/* Full duplex 10Mb/s supported */ 98 #define MII_ANA_HD_100 (1 << 7)/* Half duplex 100Mb/s supported */ 99 #define MII_ANA_FD_100 (1 << 8)/* Full duplex 100Mb/s supported */ 100 #define MII_ANA_T4 (1 << 9)/* T4 */ 101 #define MII_ANA_PAUSE (1 << 10)/* Pause supported */ 102 #define MII_ANA_ASYM_PAUSE (1 << 11)/* Asymmetric pause supported */ 103 #define MII_ANA_RF (1 << 13)/* Remote fault */ 104 #define MII_ANA_NP (1 << 15)/* Next Page */ 105 106 #define MII_ANA_ASF_802_3 (1) /* 802.3 PHY */ 107 108 /* 109 * MII Link Advertisment (Clause 37) 110 */ 111 #define MII_ANA_C37_NP (1 << 15) /* Next Page */ 112 #define MII_ANA_C37_RF_OK (0 << 12) /* No error, link OK */ 113 #define MII_ANA_C37_RF_LINK_FAIL (1 << 12) /* Offline */ 114 #define MII_ANA_C37_RF_OFFLINE (2 << 12) /* Link failure */ 115 #define MII_ANA_C37_RF_AN_ERR (3 << 12) /* Auto-Negotiation Error */ 116 #define MII_ANA_C37_PAUSE (1 << 7) /* Symmetric Pause */ 117 #define MII_ANA_C37_ASYM_PAUSE (1 << 8) /* Asymmetric Pause */ 118 #define MII_ANA_C37_HD (1 << 6) /* Half duplex */ 119 #define MII_ANA_C37_FD (1 << 5) /* Full duplex */ 120 121 /* 122 * MII Link Partner Ability (Clause 37) 123 */ 124 #define MII_ANP_C37_NP (1 << 15) /* Next Page */ 125 #define MII_ANP_C37_ACK (1 << 14) /* Acknowledge */ 126 #define MII_ANP_C37_RF_OK (0 << 12) /* No error, link OK */ 127 #define MII_ANP_C37_RF_LINK_FAIL (1 << 12) /* Offline */ 128 #define MII_ANP_C37_RF_OFFLINE (2 << 12) /* Link failure */ 129 #define MII_ANP_C37_RF_AN_ERR (3 << 12) /* Auto-Negotiation Error */ 130 #define MII_ANP_C37_PAUSE (1 << 7) /* Symmetric Pause */ 131 #define MII_ANP_C37_ASYM_PAUSE (1 << 8) /* Asymmetric Pause */ 132 #define MII_ANP_C37_HD (1 << 6) /* Half duplex */ 133 #define MII_ANP_C37_FD (1 << 5) /* Full duplex */ 134 135 /* 136 * MII Link Partner Ability (SGMII) 137 */ 138 #define MII_ANP_SGMII_MODE (1 << 0) /* Link parneter in SGMII mode */ 139 #define MII_ANP_SGMII_FD (1 << 12) /* SGMII duplex */ 140 #define MII_ANP_SGMII_SS_10 (0 << 10) /* 10Mbps SGMII */ 141 #define MII_ANP_SGMII_SS_100 (1 << 10) /* 100Mbps SGMII */ 142 #define MII_ANP_SGMII_SS_1000 (2 << 10) /* 1000Mbps SGMII */ 143 #define MII_ANP_SGMII_SS_MASK (3 << 10) /* SGMII speed mask */ 144 #define MII_ANP_SGMII_ACK (1 << 14) /* SGMII Ackonwledge */ 145 #define MII_ANP_SGMII_LINK (1 << 15) /* SGMII Link */ 146 147 148 /* 149 * 1000Base-T Control Register 150 */ 151 #define MII_GB_CTRL_MS_MAN (1 << 12) /* Manual Master/Slave mode */ 152 #define MII_GB_CTRL_MS (1 << 11) /* Master/Slave negotiation mode */ 153 #define MII_GB_CTRL_PT (1 << 10) /* Port type */ 154 #define MII_GB_CTRL_ADV_1000FD (1 << 9) /* Advertise 1000Base-T FD */ 155 #define MII_GB_CTRL_ADV_1000HD (1 << 8) /* Advertise 1000Base-T HD */ 156 157 /* 158 * 1000Base-T Status Register 159 */ 160 #define MII_GB_STAT_MS_FAULT (1 << 15) /* Master/Slave Fault */ 161 #define MII_GB_STAT_MS (1 << 14) /* Master/Slave, 1 == Master */ 162 #define MII_GB_STAT_LRS (1 << 13) /* Local receiver status */ 163 #define MII_GB_STAT_RRS (1 << 12) /* Remote receiver status */ 164 #define MII_GB_STAT_LP_1000FD (1 << 11) /* Link partner 1000FD capable */ 165 #define MII_GB_STAT_LP_1000HD (1 << 10) /* Link partner 1000HD capable */ 166 #define MII_GB_STAT_IDE (0xff << 0) /* Idle error count */ 167 168 /* 169 * IEEE Extended Status Register 170 */ 171 #define MII_ESR_1000_X_FD (1 << 15) /* 1000Base-T FD capable */ 172 #define MII_ESR_1000_X_HD (1 << 14) /* 1000Base-T HD capable */ 173 #define MII_ESR_1000_T_FD (1 << 13) /* 1000Base-T FD capable */ 174 #define MII_ESR_1000_T_HD (1 << 12) /* 1000Base-T FD capable */ 175 176 /* 177 * MII Extended Control Register (BROADCOM) 178 */ 179 #define MII_ECR_FE (1 << 0) /* FIFO Elasticity */ 180 #define MII_ECR_TLLM (1 << 1) /* Three link LED mode */ 181 #define MII_ECR_ET_IPG (1 << 2) /* Extended XMIT IPG mode */ 182 #define MII_ECR_FLED_OFF (1 << 3) /* Force LED off */ 183 #define MII_ECR_FLED_ON (1 << 4) /* Force LED on */ 184 #define MII_ECR_ELT (1 << 5) /* Enable LED traffic */ 185 #define MII_ECR_RS (1 << 6) /* Reset Scrambler */ 186 #define MII_ECR_BRSA (1 << 7) /* Bypass Receive Sym. align */ 187 #define MII_ECR_BMLT3 (1 << 8) /* Bypass MLT3 Encoder/Decoder */ 188 #define MII_ECR_BSD (1 << 9) /* Bypass Scramble/Descramble */ 189 #define MII_ECR_B4B5B (1 << 10) /* Bypass 4B/5B Encode/Decode */ 190 #define MII_ECR_FI (1 << 11) /* Force Interrupt */ 191 #define MII_ECR_ID (1 << 12) /* Interrupt Disable */ 192 #define MII_ECR_TD (1 << 13) /* XMIT Disable */ 193 #define MII_ECR_DAMC (1 << 14) /* DIsable Auto-MDI Crossover */ 194 #define MII_ECR_10B (1 << 15) /* 1 == 10B, 0 == GMII */ 195 196 /* 197 * GSR (BROADCOM) 198 */ 199 #define MII_GSR_FD (1 << 0) /* Full duplex active */ 200 #define MII_GSR_SI (1 << 1) /* Speed 0-->10, 1 --> 100 */ 201 #define MII_GSR_FORCE (1 << 2) /* Force 0-->10, 1--> 100 */ 202 #define MII_GSR_AN (1 << 3) /* Autonegotiation enabled */ 203 204 /* 205 * Auxiliary Control/Status Register 206 */ 207 #define MII_AUX_LD (1<<14) /* Link Integrity test disabled in PHY */ 208 209 /* 210 * Auxiliary Status Summary Register (ASSR - Broadcom BCM5400) 211 */ 212 #define MII_ASSR_PRTD (1 << 0) /* Pause resolution/XMIT direction */ 213 #define MII_ASSR_PRRD (1 << 1) /* Pause resolution/RCV direction */ 214 #define MII_ASSR_LS (1 << 2) /* Link Status (1 == link up) */ 215 #define MII_ASSR_LPNPA (1 << 3) /* Link partner next page cap */ 216 #define MII_ASSR_LPANA (1 << 4) /* Link Partner AN capable */ 217 #define MII_ASSR_ANPR (1 << 5) /* Autoneg page received */ 218 #define MII_ASSR_RF (1 << 6) /* Remote Fault */ 219 #define MII_ASSR_PDF (1 << 7) /* Parallel detection fault */ 220 #define MII_ASSR_HCD (7 << 8) /* Current operating speed */ 221 #define MII_ASSR_ANNPW (1 << 11) /* Auto-neg next page wait */ 222 #define MII_ASSR_ANABD (1 << 12) /* Auto-neg Ability detected */ 223 #define MII_ASSR_ANAD (1 << 13) /* Auto-neg ACK detect */ 224 #define MII_ASSR_ANCA (1 << 14) /* Auto-neg complete ACK */ 225 #define MII_ASSR_ANC (1 << 15) /* AUto-neg complete */ 226 227 #define MII_ASSR_HCD_FD_1000 (7 << 8) 228 #define MII_ASSR_HCD_HD_1000 (6 << 8) 229 #define MII_ASSR_HCD_FD_100 (5 << 8) 230 #define MII_ASSR_HCD_T4_100 (4 << 8) 231 #define MII_ASSR_HCD_HD_100 (3 << 8) 232 #define MII_ASSR_HCD_FD_10 (2 << 8) 233 #define MII_ASSR_HCD_HD_10 (1 << 8) 234 #define MII_ASSR_HCD_NC (0 << 8) /* Not complete */ 235 236 #define MII_TEST2_MS_SEL (1 << 11) 237 238 /* 239 * MII Broadcom Test Register(MII_SHA_CD_CTRL_REG) 240 */ 241 #define MII_SHA_CD_CTRL_PB_STAT (0x3 << 12) /* 13-0 pair B status */ 242 #define MII_SHA_CD_CTRL_PA_STAT (0x3 << 10) /* 13-0 pair A status */ 243 #define MII_SHA_CD_CTRL_START (0x1 << 2) /* 13-0 start bit */ 244 #define MII_SHA_CD_CTRL_PB_LEN (0xFF << 8) /* 13-1 pair B length */ 245 #define MII_SHA_CD_CTRL_PA_LEN (0xFF) /* 13-1 pair A length */ 246 247 /* 248 * MII Broadcom Test Register(MII_SHA_AUX_STAT2_REG) 249 */ 250 #define MII_SHA_AUX_STAT2_LEN (0x7 << 12) /* Enable Shadow registers */ 251 252 /* 253 * MII Broadcom Test Register(MII_BRCM_TEST_REG): bit definitions 254 */ 255 #define MII_BRCM_TEST_ENSHA (1 << 7) /* Enable Shadow registers */ 256 #define MII_BRCM_TEST_REG_DEFAULT 0x000B /* Register's default value */ 257 258 /* 259 * MII Broadcom 260 * Auxiliary Multiple PHY Register(MII_AUX_MULTI_PHY_REG): bit definitions 261 */ 262 #define MII_BRCM_AUX_MULTI_PHY_SUPER_ISO (1 << 3) /* Super Isolate registers */ 263 #define MII_BRCM_AUX_MULTI_PHY_RAN (1 << 8) /* Restart-AN registers */ 264 265 #define GOOD_CABLE_LEN_TUNING 35 266 267 #define CABLE_FUZZY_LEN1 10 /* for established good link */ 268 #define CABLE_FUZZY_LEN2 1 269 270 #define MII_MSSEED_SEED 0x3ff 271 272 #define PHY_MIN_REG 0 273 #define PHY_MAX_REG 0x1f 274 275 /* Clause 45 MIIM */ 276 #define PHY_C45_DEV_RESERVED 0x00 277 #define PHY_C45_DEV_PMA_PMD 0x01 278 #define PHY_C45_DEV_WIS 0x02 279 #define PHY_C45_DEV_PCS 0x03 280 #define PHY_C45_DEV_PHYXS 0x04 281 #define PHY_C45_DEV_DTEXS 0x05 282 #define PHY_C45_DEV_AN 0x07 283 #define PHY_C45_DEV_USER 0x1e 284 285 /* LRE/BroadR-Reach (Broadcom) Registers */ 286 287 #define LRE_CTRL_REG 0x00 /* LRE Control Register (Addr 00h) */ 288 #define LRE_STAT_REG 0x01 /* LRE Status Register (ADDR 01h) */ 289 #define LRE_PHY_ID0_REG 0x02 /* LRE PHY Identifier Register (ADDR 02h) */ 290 #define LRE_PHY_ID1_REG 0x03 /* LRE PHY Identifier Register (ADDR 03h) */ 291 #define LDS_ADVA_REG 0x04 /* LDS Advertised Ability Register (ADDR 04h) */ 292 #define LDS_ADVC_REG 0x05 /* LDS Advertised Control Register (ADDR 05h) */ 293 #define LDS_ABNP_REG 0x06 /* LDS Ability Next Page Register (ADDR 06h) */ 294 #define LDS_LPAB_REG 0x07 /* LDS Link Partner Ability Register (ADDR 07h) */ 295 #define LDS_LPNP_REG 0x08 /* LDS Link Partner Next Page Message Register (ADDR 08h) */ 296 #define LDS_LPABNP_REG 0x09 /* LDS Ability Next Page Register (ADDR 09h) */ 297 #define LDS_EXP_REG 0x0a /* LDS Expansion Register (ADDR 0ah) */ 298 #define LDS_ACC_REG 0x0e /* LDS Access Register (ADDR 0eh) */ 299 #define LRE_EXTEN_REG 0x0f /* LRE Extended Status Register (ADDR 0fh) */ 300 301 /* LRE Control Register: bit definitions */ 302 303 #define LRE_CTRL_UE (1 << 2) /* Unidirectional Enable */ 304 #define LRE_CTRL_MS (1 << 3) /* Master Selection */ 305 306 #define LRE_CTRL_PS_MASK (0x3 << 4) /* Pair Selection Mask */ 307 #define LRE_CTRL_PS_1P (0x0 << 4) /* 1 Pair */ 308 #define LRE_CTRL_PS_2P (0x1 << 4) /* 2 Pairs */ 309 #define LRE_CTRL_PS_4P (0x2 << 4) /* 4 Pairs */ 310 311 #define LRE_CTRL_SS_MASK (0xf << 6) /* Speed Selection Mask */ 312 #define LRE_CTRL_SS_10 (0x0 << 6) /* 10Mbps */ 313 #define LRE_CTRL_SS_50 (0x1 << 6) /* 50Mbps */ 314 #define LRE_CTRL_SS_33 (0x2 << 6) /* 33Mbps */ 315 #define LRE_CTRL_SS_25 (0x3 << 6) /* 25Mbps */ 316 #define LRE_CTRL_SS_20 (0x4 << 6) /* 20Mbps */ 317 #define LRE_CTRL_SS_100 (0x8 << 6) /* 100Mbps */ 318 319 #define LRE_CTRL_IP (1 << 10) /* Isolate Phy */ 320 #define LRE_CTRL_PD (1 << 11) /* Power Down */ 321 #define LRE_CTRL_LDSE (1 << 12) /* LDS Enable */ 322 #define LRE_CTRL_RLDS (1 << 13) /* Restart LDS */ 323 #define LRE_CTRL_LE (1 << 14) /* Loopback Enable */ 324 #define LRE_CTRL_RESET (1 << 15) /* Reset */ 325 326 327 /* LRE Status Register: bit definitions */ 328 329 #define LRE_STAT_EXT (1 << 0) /* Extended Capability */ 330 #define LRE_STAT_JBBR (1 << 1) /* Jabber Detected */ 331 #define LRE_STAT_LA (1 << 2) /* Link Active */ 332 #define LRE_STAT_LDS_CAP (1 << 3) /* LDS capable */ 333 #define LRE_STAT_IEEE_CAP (1 << 4) /* Supports 802.3 PHY */ 334 #define LRE_STAT_LDS_DONE (1 << 5) /* LDS Done */ 335 #define LRE_STAT_MF_PS (1 << 6) /* Preamble Suppression */ 336 #define LRE_STAT_UA (1 << 7) /* Unidirectional Ability */ 337 #define LRE_STAT_ES (1 << 8) /* Extended Status */ 338 339 #define LRE_STAT_1_10 (1 << 9) /* 1 pair 10Mbps capable */ 340 #define LRE_STAT_2_10 (1 << 10) /* 2 pair 10Mbps capable */ 341 #define LRE_STAT_2_100 (1 << 11) /* 2 pair 100Mbps capable */ 342 #define LRE_STAT_4_100 (1 << 12) /* 4 pair 100Mbps capable */ 343 #define LRE_STAT_1_100 (1 << 13) /* 1 pair 100Mbps capable */ 344 345 346 /* LDS Advertised Ability Register: bit definitions */ 347 348 #define LDS_ADVA_1_10 (1 << 1) /* Supports 1 pair 10Mbps */ 349 #define LDS_ADVA_2_10 (1 << 2) /* Supports 2 pair 10Mbps */ 350 #define LDS_ADVA_2_100 (1 << 3) /* Supports 2 pair 100Mbps */ 351 #define LDS_ADVA_4_100 (1 << 4) /* Supports 4 pair 100Mbps */ 352 #define LDS_ADVA_1_100 (1 << 5) /* Supports 1 pair 100Mbps */ 353 #define LDS_ADVA_1_20 (1 << 6) /* Supports 1 pair 20Mbps */ 354 #define LDS_ADVA_1_25 (1 << 7) /* Supports 1 pair 25Mbps */ 355 #define LDS_ADVA_1_33 (1 << 8) /* Supports 1 pair 33Mbps */ 356 #define LDS_ADVA_1_50 (1 << 9) /* Supports 1 pair 33Mbps */ 357 #define LDS_ADVA_2_20 (1 << 10) /* Supports 2 pair 20Mbps */ 358 #define LDS_ADVA_2_25 (1 << 11) /* Supports 2 pair 25Mbps */ 359 #define LDS_ADVA_2_33 (1 << 12) /* Supports 2 pair 33Mbps */ 360 #define LDS_ADVA_2_50 (1 << 13) /* Supports 2 pair 33Mbps */ 361 362 #define LDS_ADVA_PAUSE (1 << 14) /* Supports Pause */ 363 #define LDS_ADVA_ASYM_PAUSE (1 << 15) /* Supports Asymetric Pause */ 364 365 /* LDS Advertised Control Register: bit definitions */ 366 367 #define LDS_ADVC_AFU (1 << 8) /* ADVA register updated */ 368 369 /* LDS Link Partner Ability Register: bit definitions */ 370 371 #define LDS_LPAB_1_10 (1 << 1) /* Supports 1 pair 10Mbps */ 372 #define LDS_LPAB_2_10 (1 << 2) /* Supports 2 pair 10Mbps */ 373 #define LDS_LPAB_2_100 (1 << 3) /* Supports 2 pair 100Mbps */ 374 #define LDS_LPAB_4_100 (1 << 4) /* Supports 4 pair 100Mbps */ 375 #define LDS_LPAB_1_100 (1 << 5) /* Supports 1 pair 100Mbps */ 376 #define LDS_LPAB_1_20 (1 << 6) /* Supports 1 pair 20Mbps */ 377 #define LDS_LPAB_1_25 (1 << 7) /* Supports 1 pair 25Mbps */ 378 #define LDS_LPAB_1_33 (1 << 8) /* Supports 1 pair 33Mbps */ 379 #define LDS_LPAB_1_50 (1 << 9) /* Supports 1 pair 33Mbps */ 380 #define LDS_LPAB_2_20 (1 << 10) /* Supports 2 pair 20Mbps */ 381 #define LDS_LPAB_2_25 (1 << 11) /* Supports 2 pair 25Mbps */ 382 #define LDS_LPAB_2_33 (1 << 12) /* Supports 2 pair 33Mbps */ 383 #define LDS_LPAB_2_50 (1 << 13) /* Supports 2 pair 33Mbps */ 384 #define LDS_LPAB_PAUSE (1 << 14) /* Supports Pause */ 385 #define LDS_LPAB_ASYM_PAUSE (1 << 15) /* Supports Asymetric Pause */ 386 387 388 /* LDS Access Register: bit definitions */ 389 390 #define LDS_ACC_STAT (1 << 0) /* LRE Register Acress Status */ 391 #define LDS_ACC_OVV (1 << 1) /* LRE Register Acress Override Value */ 392 #define LDS_ACC_OVR (1 << 2) /* LRE Register Acress Override */ 393 394 395 /* Initial BR mode settings */ 396 #define LR_INITIAL_MODE_LR_ENABLE (1 << 0) /* Enable BroadReach at init() */ 397 398 /* Initial BR ctrl settings */ 399 #define LR_INITIAL_CTRL_LDS_ENABLE (1 << 0) /* Enable LDS at init(), valid only in BR in enabled */ 400 #define LR_INITIAL_CTRL_LR_MS (1 << 1) /* Master Selection */ 401 #define LR_INITIAL_CTRL_LR_UE (1 << 2) /* Unidirectional enable */ 402 /* Initial BR pairs, valid only if LDS is disabled, but BR is enabled (3 bits) */ 403 #define LR_INITIAL_CTRL_LR_PS_MASK (0x7 << 3) 404 #define LR_INITIAL_CTRL_LR_PS_1P (0x0 << 3) /* 1 Pair */ 405 #define LR_INITIAL_CTRL_LR_PS_2P (0x1 << 3) /* 2 Pairs */ 406 #define LR_INITIAL_CTRL_LR_PS_4P (0x2 << 3) /* 4 Pairs */ 407 /* Initial BR speed, valid only if LDS is disabled, but BR is enabled (6 bits) */ 408 #define LR_INITIAL_CTRL_LR_SS_MASK (0x3f << 6) 409 #define LR_INITIAL_CTRL_LR_SS_10 (0x0 << 6) /* 10Mbps */ 410 #define LR_INITIAL_CTRL_LR_SS_20 (0x1 << 6) /* 20Mbps */ 411 #define LR_INITIAL_CTRL_LR_SS_25 (0x2 << 6) /* 25Mbps */ 412 #define LR_INITIAL_CTRL_LR_SS_33 (0x3 << 6) /* 33Mbps */ 413 #define LR_INITIAL_CTRL_LR_SS_50 (0x4 << 6) /* 50Mbps */ 414 #define LR_INITIAL_CTRL_LR_SS_100 (0x5 << 6) /* 100Mbps */ 415 416 /* Initial advert ability, valid only if LDS is enabled */ 417 #define LR_INITIAL_ADVA_1_10 (1 << 0) /* Advertise 1 pair 10Mbps */ 418 #define LR_INITIAL_ADVA_2_10 (1 << 1) /* Advertise 2 pair 10Mbps */ 419 #define LR_INITIAL_ADVA_1_20 (1 << 2) /* Advertise 1 pair 20Mbps */ 420 #define LR_INITIAL_ADVA_2_20 (1 << 3) /* Advertise 2 pair 20Mbps */ 421 #define LR_INITIAL_ADVA_1_25 (1 << 4) /* Advertise 1 pair 25Mbps */ 422 #define LR_INITIAL_ADVA_2_25 (1 << 5) /* Advertise 2 pair 25Mbps */ 423 #define LR_INITIAL_ADVA_1_33 (1 << 6) /* Advertise 1 pair 33Mbps */ 424 #define LR_INITIAL_ADVA_2_33 (1 << 7) /* Advertise 2 pair 33Mbps */ 425 #define LR_INITIAL_ADVA_1_50 (1 << 8) /* Advertise 1 pair 50Mbps */ 426 #define LR_INITIAL_ADVA_2_50 (1 << 9) /* Advertise 2 pair 50Mbps */ 427 #define LR_INITIAL_ADVA_1_100 (1 << 10) /* Advertise 1 pair 100Mbps */ 428 #define LR_INITIAL_ADVA_2_100 (1 << 11) /* Advertise 2 pair 100Mbps */ 429 #define LR_INITIAL_ADVA_4_100 (1 << 12) /* Advertise 4 pair 100Mbps */ 430 #define LR_INITIAL_ADVA_PAUSE_RX (1 << 13) /* Advertise Pause RX */ 431 #define LR_INITIAL_ADVA_PAUSE_TX (1 << 14) /* Advertise Pause TX */ 432 433 434 /* 435 * Enumeration of known PHYs 436 */ 437 typedef enum soc_known_phy_e { 438 _phy_id_unknown = 0, 439 _phy_id_BCM5218, 440 _phy_id_BCM5220, 441 _phy_id_BCM5226, 442 _phy_id_BCM5228, 443 _phy_id_BCM5238, 444 _phy_id_BCM5248, 445 _phy_id_BCM5400, 446 _phy_id_BCM5401, 447 _phy_id_BCM5402, 448 _phy_id_BCM5404, 449 _phy_id_BCM5411, 450 _phy_id_BCM5421, 451 _phy_id_BCM5424, 452 _phy_id_BCM5461, 453 _phy_id_BCM5464, 454 _phy_id_BCM5466, 455 _phy_id_BCM5478, 456 _phy_id_BCM5488, 457 _phy_id_BCM5482, 458 _phy_id_BCM5481, 459 _phy_id_BCM54680, 460 _phy_id_BCM54880, 461 _phy_id_BCM54680E, 462 _phy_id_BCM54880E, 463 _phy_id_BCM54881, 464 _phy_id_BCM54810, 465 _phy_id_BCM54811, 466 _phy_id_BCM54682, 467 _phy_id_BCM54684, 468 _phy_id_BCM54684E, 469 _phy_id_BCM54685, 470 _phy_id_BCM52681E, 471 _phy_id_BCM54640, 472 _phy_id_BCM54616, 473 _phy_id_BCM54618E, 474 _phy_id_BCM54618SE, 475 _phy_id_BCM84707, /* start BCM84728 family */ 476 _phy_id_BCM84073, 477 _phy_id_BCM84074, 478 _phy_id_BCM84728, 479 _phy_id_BCM84729 = _phy_id_BCM84728, 480 _phy_id_BCM84748, 481 _phy_id_BCM84727, 482 _phy_id_BCM84747, 483 _phy_id_BCM84762, 484 _phy_id_BCM84764, 485 _phy_id_BCM84042, 486 _phy_id_BCM84044, /* end BCM84728 family */ 487 _phy_id_BCM54584, 488 _phy_id_BCM54580, 489 _phy_id_BCM54540, 490 _phy_id_BCM54585, 491 _phy_id_BCM8729, 492 _phy_id_BCM84756, 493 _phy_id_BCM84757, 494 _phy_id_BCM84759, 495 _phy_id_BCM84749, 496 _phy_id_BCM54980, 497 _phy_id_BCM54980C, 498 _phy_id_BCM54980V, 499 _phy_id_BCM54980VC, 500 _phy_id_BCM8011, 501 _phy_id_BCM8703, 502 _phy_id_BCM8704, 503 _phy_id_BCM8705, 504 _phy_id_BCM8706, 505 _phy_id_BCM8072 = _phy_id_BCM8706, 506 _phy_id_BCMXGXS1, 507 _phy_id_BCMXGXS2, 508 _phy_id_BCMXGXS5, 509 _phy_id_BCMXGXS6, 510 _phy_id_BCM53314, 511 _phy_id_BCM53324, 512 _phy_id_SERDES, 513 _phy_id_SERDES100FX, 514 _phy_id_SERDES65LP, 515 _phy_id_XGXS_HL65 = _phy_id_SERDES65LP, 516 _phy_id_XGXS_HC65 = _phy_id_SERDES65LP, 517 _phy_id_XGXS_16G = _phy_id_SERDES65LP, 518 _phy_id_XGXS_WC40 = _phy_id_SERDES65LP, 519 _phy_id_XGXS_WL = _phy_id_SERDES65LP, 520 _phy_id_XGXS_QSGMIIE = _phy_id_SERDES65LP, 521 _phy_id_XGXS_TSC, 522 _phy_id_XGXS_VIPER, 523 _phy_id_SERDESCOMBO, 524 _phy_id_SERDESCOMBO65, 525 _phy_id_BCM8727, 526 _phy_id_BCM8073 = _phy_id_BCM8727, 527 _phy_id_BCM8074 = _phy_id_BCM8727, 528 _phy_id_BCM8040, 529 _phy_id_BCM8481x, 530 _phy_id_BCM84812ce, 531 _phy_id_BCM84821, 532 _phy_id_BCM84822, 533 _phy_id_BCM84823, 534 _phy_id_BCM84833, 535 _phy_id_BCM84333 = _phy_id_BCM84833, 536 _phy_id_BCM84834, 537 _phy_id_BCM84334 = _phy_id_BCM84834, 538 _phy_id_BCM84835, 539 _phy_id_BCM84836, 540 _phy_id_BCM84336 = _phy_id_BCM84836, 541 _phy_id_BCM84844, 542 _phy_id_BCM84846, 543 _phy_id_BCM84848, 544 _phy_id_BCM84858, 545 _phy_id_BCM84856, 546 _phy_id_BCM84860, 547 _phy_id_BCM84861, 548 _phy_id_BCM84864, 549 _phy_id_BCM84868, 550 _phy_id_BCM84888, 551 _phy_id_BCM84884, 552 _phy_id_BCM84888E, 553 _phy_id_BCM84884E, 554 _phy_id_BCM84881, 555 _phy_id_BCM84880, 556 _phy_id_BCM84888S, 557 _phy_id_BCM84885, 558 _phy_id_BCM84886, 559 _phy_id_BCM84887, 560 _phy_id_BCM8747, 561 _phy_id_BCM8750, 562 _phy_id_BCM8752, 563 _phy_id_BCM8754, 564 _phy_id_BCM84740, 565 _phy_id_BCM84780, 566 _phy_id_BCM84784, 567 _phy_id_BCM84758, 568 _phy_id_BCM84164, 569 _phy_id_BCM84168, 570 _phy_id_BCM54380, 571 _phy_id_BCM54382, 572 _phy_id_BCM54340, 573 _phy_id_BCM54385, 574 _phy_id_BCM54210, 575 _phy_id_BCM54220, 576 _phy_id_BCM54280, 577 _phy_id_BCM54282, 578 _phy_id_BCM54240, 579 _phy_id_BCM54285, 580 _phy_id_BCM84328, 581 _phy_id_BCM84793, 582 _phy_id_BCM54290, 583 _phy_id_BCM54182, 584 _phy_id_BCM54185, 585 _phy_id_BCM54180, 586 _phy_id_BCM54140, 587 _phy_id_BCM54192, 588 _phy_id_BCM54195, 589 _phy_id_BCM54190, 590 _phy_id_BCM54194, 591 _phy_id_BCM54292, 592 _phy_id_BCM54294, 593 _phy_id_BCM54295, 594 _phy_id_BCM54296, 595 _phy_id_BCM5428x, 596 _phy_id_BCM82328, 597 _phy_id_BCM84318, 598 _phy_id_BCM82381, 599 _phy_id_BCM82764, 600 _phy_id_BCM82780, 601 _phy_id_BCM56160_GPHY, 602 _phy_id_BCM53540, 603 _phy_id_BCM8806x, 604 _phy_id_BCM82864, 605 _phy_id_NULL, 606 _phy_id_SIMUL, 607 _phy_id_BCM82109, 608 _phy_id_numberKnown /* Always last, please */ 609 } soc_known_phy_t; 610 611 /* 612 uc description 613 */ 614 615 typedef struct soc_phy_wcmod_uc_desc_s{ 616 int pll_range; 617 int tx_pre_cursor; 618 int tx_main; 619 int tx_post_cursor; 620 char *vga_bias_reduced; 621 int postc_metric; 622 char pmd_mode_s[100]; 623 int pf_ctrl; 624 int vga_sum; 625 int dfe1_bin; 626 int dfe2_bin; 627 int dfe3_bin; 628 int dfe4_bin; 629 int dfe5_bin; 630 int integ_reg; 631 int integ_reg_xfer; 632 int clk90_offset; 633 int clkp1_offset; 634 int sd; 635 int lopf; 636 int p1_lvl; 637 int m1_lvl; 638 int tx_drvr; 639 int slicer_target; 640 int offset_pe; 641 int offset_ze; 642 int offset_me; 643 int offset_po; 644 int offset_zo; 645 int offset_mo; 646 int dsc_sm; 647 int temp; 648 int phy_ad; 649 int lane; 650 } soc_phy_wcmod_uc_desc_t; 651 652 /* Forward def */ 653 typedef struct soc_phy_table_s soc_phy_table_t; 654 typedef int (*soc_phy_ident_f)(int unit, soc_port_t port, 655 soc_phy_table_t *my_entry, 656 uint16 phy_id0, uint16 phy_id1, 657 soc_phy_info_t *pi); 658 659 /* For identifying phy */ 660 struct soc_phy_table_s { 661 soc_phy_ident_f checkphy; /* call back to check for this phy */ 662 soc_known_phy_t myNum; /* For known phys, its enum val */ 663 char *phy_name; /* Phy Name */ 664 phy_driver_t *driver; /* the driver for this phy */ 665 void *cookie; /* cookie for callback. */ 666 }; 667 668 extern int 669 soc_phy_add_entry(soc_phy_table_t *entry); 670 671 #endif /* !_SOC_PHY_H */