pbsmh.h (55674B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * File: pbsmh.h 8 */ 9 10 #ifndef CMICM_EMBEDDED 11 #include <soc/defs.h> 12 #endif 13 14 #ifndef _SOC_PBSMH_H 15 #define _SOC_PBSMH_H 16 17 #ifdef BCM_XGS3_SWITCH_SUPPORT 18 19 /**************************************************************************** 20 * PBS MH Header Format 21 * 22 * On XGS3 devices this is used to send a Packet Byte Stream out a port. 23 * 24 * ANSI only permits signed or unsigned int for bit field type. This 25 * structure will only work for compilers for which uint32 is unsigned 26 * int, and which completely pack bit fields beginning at the MSbit for 27 * big-endian machines and at the LSbit for little-endian machines. 28 * 29 * NOTE: these structures already put the the individual bytes in memory 30 * in big endian order for both big- and little-endian machines, so no 31 * further swapping is required. 32 */ 33 34 35 36 typedef struct soc_pbsmh_hdr_s { 37 #if defined(LE_HOST) 38 /* Byte # */ 39 uint32 start:8; /* 0 */ 40 uint32 _rsvd0:24; /* 1-3 */ 41 uint32 _rsvd1; /* 4-7 */ 42 uint32 _rsvd2:16; /* 8-9 */ 43 uint32 src_mod:6; /* 10 */ 44 uint32 _rsvd3:2; /* 10 */ 45 uint32 dst_port:5; /* 11 */ 46 uint32 cos:3; /* 11 */ 47 #else /* !LE_HOST */ 48 /* Byte # */ 49 uint32 start:8; /* 0 */ 50 uint32 _rsvd0:24; /* 1-3 */ 51 uint32 _rsvd1; /* 4-7 */ 52 uint32 _rsvd2:16; /* 8-10 */ 53 uint32 _rsvd3:2; /* 10 */ 54 uint32 src_mod:6; /* 10 */ 55 uint32 cos:3; /* 11 */ 56 uint32 dst_port:5; /* 11 */ 57 #endif /* !LE_HOST */ 58 } soc_pbsmh_hdr_t; 59 60 typedef struct soc_pbsmh_v2_hdr_s { 61 #if defined(LE_HOST) 62 /* Byte # */ 63 uint32 start:8; /* 0 */ 64 uint32 _rsvd0:24; /* 1-3 */ 65 uint32 _rsvd1; /* 4-7 */ 66 uint32 _rsvd2:8; /* 8 */ 67 uint32 src_mod:8; /* 9 */ 68 uint32 cos:4; /* 10 */ 69 uint32 pri:4; /* 10 */ 70 uint32 dst_port:7; /* 11 */ 71 uint32 l3pbm_sel:1; /* 11 */ 72 #else /* !LE_HOST */ 73 /* Byte # */ 74 uint32 start:8; /* 0 */ 75 uint32 _rsvd0:24; /* 1-3 */ 76 uint32 _rsvd1; /* 4-7 */ 77 uint32 _rsvd2:8; /* 8 */ 78 uint32 src_mod:8; /* 9 */ 79 uint32 pri:4; /* 10 */ 80 uint32 cos:4; /* 10 */ 81 uint32 l3pbm_sel:1; /* 11 */ 82 uint32 dst_port:7; /* 11 */ 83 #endif /* !LE_HOST */ 84 } soc_pbsmh_v2_hdr_t; 85 86 typedef struct soc_pbsmh_v3_hdr_s { 87 #if defined(LE_HOST) 88 /* Byte # */ 89 uint32 start:8; /* 0 */ 90 uint32 _rsvd0:24; /* 1-3 */ 91 uint32 _rsvd1; /* 4-7 */ 92 uint32 src_mod_hi:4; /* 8 */ 93 uint32 _rsvd2:4; /* 8 */ 94 uint32 pri:4; /* 9 */ 95 uint32 src_mod_lo:4; /* 9 */ 96 uint32 cos:6; /* 10 */ 97 uint32 _rsvd3:2; /* 10 */ 98 uint32 dst_port:7; /* 11 */ 99 uint32 l3pbm_sel:1; /* 11 */ 100 #else /* !LE_HOST */ 101 /* Byte # */ 102 uint32 start:8; /* 0 */ 103 uint32 _rsvd0:24; /* 1-3 */ 104 uint32 _rsvd1; /* 4-7 */ 105 uint32 _rsvd2:4; /* 8 */ 106 uint32 src_mod_hi:4; /* 8 */ 107 uint32 src_mod_lo:4; /* 9 */ 108 uint32 pri:4; /* 9 */ 109 uint32 _rsvd3:2; /* 10 */ 110 uint32 cos:6; /* 10 */ 111 uint32 l3pbm_sel:1; /* 11 */ 112 uint32 dst_port:7; /* 11 */ 113 #endif /* !LE_HOST */ 114 } soc_pbsmh_v3_hdr_t; 115 116 typedef struct soc_pbsmh_v4_hdr_s { 117 #if defined(LE_HOST) 118 /* Byte # */ 119 uint32 start:8; /* 0 */ 120 uint32 _rsvd0:24; /* 1-3 */ 121 uint32 _rsvd1; /* 4-7 */ 122 uint32 src_mod_hi:1; /* 8 */ 123 uint32 _rsvd2:7; /* 8 */ 124 uint32 pri_hi:1; /* 9 */ 125 uint32 src_mod_lo:7; /* 9 */ 126 uint32 cos:5; /* 10 */ 127 uint32 pri_lo:3; /* 10 */ 128 uint32 dst_port:7; /* 11 */ 129 uint32 l3pbm_sel:1; /* 11 */ 130 #else /* !LE_HOST */ 131 /* Byte # */ 132 uint32 start:8; /* 0 */ 133 uint32 _rsvd0:24; /* 1-3 */ 134 uint32 _rsvd1; /* 4-7 */ 135 uint32 _rsvd2:7; /* 8 */ 136 uint32 src_mod_hi:1; /* 8 */ 137 uint32 src_mod_lo:7; /* 9 */ 138 uint32 pri_hi:1; /* 9 */ 139 uint32 pri_lo:3; /* 10 */ 140 uint32 cos:5; /* 10 */ 141 uint32 l3pbm_sel:1; /* 11 */ 142 uint32 dst_port:7; /* 11 */ 143 #endif /* !LE_HOST */ 144 } soc_pbsmh_v4_hdr_t; 145 146 typedef struct soc_pbsmh_v5_hdr_s { 147 #if defined(LE_HOST) 148 /* Byte # */ 149 uint32 start:8; /* 0 */ 150 uint32 _rsvd0:24; /* 1-3 */ 151 uint32 ipcf_ptr:8; /* 4 */ 152 uint32 spid_override:1; /* 5 */ 153 uint32 _rsvd2:3; /* 5 */ 154 uint32 tx_ts:1; /* 5 */ 155 uint32 _rsvd1:3; /* 5 */ 156 uint32 unicast:1; /* 6 */ 157 uint32 set_l2bm:1; /* 6 */ 158 uint32 set_l3bm:1; /* 6 */ 159 uint32 _rsvd3:1; /* 6 */ 160 uint32 spap:2; /* 6 */ 161 uint32 spid:2; /* 6 */ 162 uint32 src_mod:8; /* 7 */ 163 uint32 input_pri:4; /* 8 */ 164 uint32 _rsvd4:4; /* 8 */ 165 uint32 queue_num:7; /* 9 */ 166 uint32 _rsvd5:1; /* 9 */ 167 uint32 cos:4; /* 10 */ 168 uint32 _rsvd6:4; /* 10 */ 169 uint32 dst_port:7; /* 11 */ 170 uint32 _rsvd7:1; /* 11 */ 171 #else /* !LE_HOST */ 172 /* Byte # */ 173 uint32 start:8; /* 0 */ 174 uint32 _rsvd0:24; /* 1-3 */ 175 uint32 ipcf_ptr:8; /* 4 */ 176 uint32 _rsvd1:3; /* 5 */ 177 uint32 tx_ts:1; /* 5 */ 178 uint32 _rsvd2:3; /* 5 */ 179 uint32 spid_override:1; /* 5 */ 180 uint32 spid:2; /* 6 */ 181 uint32 spap:2; /* 6 */ 182 uint32 _rsvd3:1; /* 6 */ 183 uint32 set_l3bm:1; /* 6 */ 184 uint32 set_l2bm:1; /* 6 */ 185 uint32 unicast:1; /* 6 */ 186 uint32 src_mod:8; /* 7 */ 187 uint32 _rsvd4:4; /* 8 */ 188 uint32 input_pri:4; /* 8 */ 189 uint32 _rsvd5:1; /* 9 */ 190 uint32 queue_num:7; /* 9 */ 191 uint32 _rsvd6:4; /* 10 */ 192 uint32 cos:4; /* 10 */ 193 uint32 _rsvd7:1; /* 11 */ 194 uint32 dst_port:7; /* 11 */ 195 #endif /* !LE_HOST */ 196 } soc_pbsmh_v5_hdr_t; 197 198 typedef struct soc_pbsmh_v6_hdr_s { 199 #if defined(LE_HOST) 200 /* Byte # */ 201 uint32 start:8; /* 0 */ 202 uint32 _rsvd0:8; /* 1 */ 203 uint32 hdr_offset_2:3; /* 2 */ 204 uint32 _rsvd1:5; /* 2 */ 205 uint32 osts:1; /* 3 */ 206 uint32 regen_upd_chksum:1; /* 3 */ 207 uint32 its_sign:1; /* 3 */ 208 uint32 hdr_offset_1:5; /* 3 */ 209 uint32 ipcf_ptr:8; /* 4 */ 210 uint32 spid_override:1; /* 5 */ 211 uint32 _rsvd3:3; /* 5 */ 212 uint32 tx_ts:1; /* 5 */ 213 uint32 _rsvd2:3; /* 5 */ 214 uint32 unicast:1; /* 6 */ 215 uint32 set_l2bm:1; /* 6 */ 216 uint32 set_l3bm:1; /* 6 */ 217 uint32 _rsvd4:1; /* 6 */ 218 uint32 spap:2; /* 6 */ 219 uint32 spid:2; /* 6 */ 220 uint32 src_mod:8; /* 7 */ 221 uint32 queue_num_3:2; /* 8 */ 222 uint32 input_pri:4; /* 8 */ 223 uint32 _rsvd5:2; /* 8 */ 224 uint32 queue_num_2:8; /* 9 */ 225 uint32 cos:6; /* 10 */ 226 uint32 queue_num_1:2; /* 10 */ 227 uint32 dst_port:7; /* 11 */ 228 uint32 _rsvd6:1; /* 11 */ 229 #else /* !LE_HOST */ 230 /* Byte # */ 231 uint32 start:8; /* 0 */ 232 uint32 _rsvd0:8; /* 1 */ 233 uint32 _rsvd1:5; /* 2 */ 234 uint32 hdr_offset_2:3; /* 2 */ 235 uint32 hdr_offset_1:5; /* 3 */ 236 uint32 its_sign:1; /* 3 */ 237 uint32 regen_upd_chksum:1; /* 3 */ 238 uint32 osts:1; /* 3 */ 239 uint32 ipcf_ptr:8; /* 4 */ 240 uint32 _rsvd2:3; /* 5 */ 241 uint32 tx_ts:1; /* 5 */ 242 uint32 _rsvd3:3; /* 5 */ 243 uint32 spid_override:1; /* 5 */ 244 uint32 spid:2; /* 6 */ 245 uint32 spap:2; /* 6 */ 246 uint32 _rsvd4:1; /* 6 */ 247 uint32 set_l3bm:1; /* 6 */ 248 uint32 set_l2bm:1; /* 6 */ 249 uint32 unicast:1; /* 6 */ 250 uint32 src_mod:8; /* 7 */ 251 uint32 _rsvd5:2; /* 8 */ 252 uint32 input_pri:4; /* 8 */ 253 uint32 queue_num_3:2; /* 8 */ 254 uint32 queue_num_2:8; /* 9 */ 255 uint32 queue_num_1:2; /* 10 */ 256 uint32 cos:6; /* 10 */ 257 uint32 _rsvd6:1; /* 11 */ 258 uint32 dst_port:7; /* 11 */ 259 #endif /* !LE_HOST */ 260 } soc_pbsmh_v6_hdr_t; 261 262 typedef union soc_pbsmh_v7_hdr_s { 263 #if defined(LE_HOST) 264 struct { /* Byte # */ 265 uint32 header_type:6; /* 0 */ 266 uint32 start:2; /* 0 */ 267 uint32 ep_cpu_reason_code_3:4; /* 1 ' */ 268 uint32 _rsvd5:4; /* 1 ' */ 269 uint32 ep_cpu_reason_code_2:8; /* 2 ' */ 270 uint32 ep_cpu_reason_code_1:8; /* 3 ' */ 271 uint32 oam_replacement_offset:6; /* 4 */ 272 uint32 queue_num_3:2; /* 4 */ 273 uint32 set_l3bm:1; /* 5 */ 274 uint32 tx_ts:1; /* 5 */ 275 uint32 its_sign:1; /* 5 */ 276 uint32 regen_udp_checksum:1; /* 5 */ 277 uint32 osts:1; /* 5 */ 278 uint32 oam_replacement_type:2; /* 5 */ 279 uint32 cell_error:1; /* 5 */ 280 uint32 hdr_offset:8; /* 6 */ 281 uint32 dst_port:7; /* 7 */ 282 uint32 set_l2bm:1; /* 7 */ 283 uint32 int_pri:4; /* 8 ' */ 284 uint32 input_pri:4; /* 8 */ 285 uint32 queue_num_2:2; /* 9 */ 286 uint32 nlf_port:6; /* 9 ' */ 287 uint32 queue_num_1:8; /* 10 */ 288 uint32 src_mod:8; /* 11 */ 289 } overlay1; 290 291 struct { /* Byte # */ 292 uint32 header_type:6; /* 0 */ 293 uint32 start:2; /* 0 */ 294 uint32 _rsvd3:8; /* 1 ' */ 295 uint32 lm_counter_index_2:8; /* 2 ' */ 296 uint32 lm_counter_index_1:8; /* 3 ' */ 297 uint32 oam_replacement_offset:6; /* 4 */ 298 uint32 queue_num_3:2; /* 4 */ 299 uint32 set_l3bm:1; /* 5 */ 300 uint32 tx_ts:1; /* 5 */ 301 uint32 its_sign:1; /* 5 */ 302 uint32 regen_udp_checksum:1; /* 5 */ 303 uint32 osts:1; /* 5 */ 304 uint32 oam_replacement_type:2; /* 5 */ 305 uint32 _rsvd1:1; /* 5 */ 306 uint32 hdr_offset:8; /* 6 */ 307 uint32 dst_port:7; /* 7 */ 308 uint32 set_l2bm:1; /* 7 */ 309 uint32 cos:4; /* 8 ' */ 310 uint32 input_pri:4; /* 8 */ 311 uint32 queue_num_2:2; /* 9 */ 312 uint32 unicast:1; /* 9 ' */ 313 uint32 spap:2; /* 9 ' */ 314 uint32 spid:2; /* 9 ' */ 315 uint32 spid_override:1; /* 9' */ 316 uint32 queue_num_1:8; /* 10 */ 317 uint32 src_mod:8; /* 11 */ 318 } overlay2; 319 #else /* !LE_HOST */ 320 321 struct { /* Byte # */ 322 uint32 start:2; /* 0 */ 323 uint32 header_type:6; /* 0 */ 324 uint32 _rsvd5:4; /* 1 ' */ 325 uint32 ep_cpu_reason_code_3:4; /* 1 ' */ 326 uint32 ep_cpu_reason_code_2:8; /* 2 ' */ 327 uint32 ep_cpu_reason_code_1:8; /* 3 ' */ 328 uint32 queue_num_3:2; /* 4 */ 329 uint32 oam_replacement_offset:6; /* 4 */ 330 uint32 cell_error:1; /* 5 */ 331 uint32 oam_replacement_type:2; /* 5 */ 332 uint32 osts:1; /* 5 */ 333 uint32 regen_udp_checksum:1; /* 5 */ 334 uint32 its_sign:1; /* 5 */ 335 uint32 tx_ts:1; /* 5 */ 336 uint32 set_l3bm:1; /* 5 */ 337 uint32 hdr_offset:8; /* 6 */ 338 uint32 set_l2bm:1; /* 7 */ 339 uint32 dst_port:7; /* 7 */ 340 uint32 input_pri:4; /* 8 */ 341 uint32 int_pri:4; /* 8 ' */ 342 uint32 nlf_port:6; /* 9 ' */ 343 uint32 queue_num_2:2; /* 9 */ 344 uint32 queue_num_1:8; /* 10 */ 345 uint32 src_mod:8; /* 11 */ 346 } overlay1; 347 348 struct { /* Byte # */ 349 uint32 start:2; /* 0 */ 350 uint32 header_type:6; /* 0 */ 351 uint32 _rsvd3:8; /* 1 ' */ 352 uint32 lm_counter_index_2:8; /* 2 ' */ 353 uint32 lm_counter_index_1:8; /* 3 ' */ 354 uint32 queue_num_3:2; /* 4 */ 355 uint32 oam_replacement_offset:6; /* 4 */ 356 uint32 _rsvd1:1; /* 5 */ 357 uint32 oam_replacement_type:2; /* 5 */ 358 uint32 osts:1; /* 5 */ 359 uint32 regen_udp_checksum:1; /* 5 */ 360 uint32 its_sign:1; /* 5 */ 361 uint32 tx_ts:1; /* 5 */ 362 uint32 set_l3bm:1; /* 5 */ 363 uint32 hdr_offset:8; /* 6 */ 364 uint32 set_l2bm:1; /* 7 */ 365 uint32 dst_port:7; /* 7 */ 366 uint32 input_pri:4; /* 8 */ 367 uint32 cos:4; /* 8 ' */ 368 uint32 spid_override:1; /* 9 ' */ 369 uint32 spid:2; /* 9 ' */ 370 uint32 spap:2; /* 9 ' */ 371 uint32 unicast:1; /* 9 ' */ 372 uint32 queue_num_2:2; /* 9 */ 373 uint32 queue_num_1:8; /* 10 */ 374 uint32 src_mod:8; /* 11 */ 375 } overlay2; 376 #endif /* !LE_HOST */ 377 } soc_pbsmh_v7_hdr_t; 378 379 380 #define PBS_MH_V7_HDR_TYPE_EP_COPY_TO_CPU 0 381 #define PBS_MH_V7_HDR_TYPE_FROM_CPU 1 382 #define PBS_MH_V7_HDR_TYPE_MIM 2 383 #define PBS_MH_V7_HDR_TYPE_MPLS_PMP 3 384 #define PBS_MH_V7_HDR_TYPE_TRILL_NW 4 385 #define PBS_MH_V7_HDR_TYPE_TRILL_AC 5 386 #define PBS_MH_V7_HDR_TYPE_WLAN_DECAP 6 387 #define PBS_MH_V7_HDR_TYPE_WLAN_ENCAP 7 388 #define PBS_MH_V7_HDR_TYPE_QCN 8 389 #define PBS_MH_V7_HDR_TYPE_SM_DPI 9 390 #define PBS_MH_V7_HDR_TYPE_EP_REDIER 0xA 391 #define PBS_MH_V7_HDR_TYPE_GENERIC 0xB 392 393 394 typedef union soc_pbsmh_v8_hdr_s { 395 #if defined(LE_HOST) 396 /* Overlay 1 : SOBMH_FROM_CPU */ 397 struct { /* Byte # */ 398 uint32 header_type:6; /* 0 */ 399 uint32 start:2; /* 0 */ 400 uint32 cos_msb_2:6; /* 1 */ 401 uint32 _rsvd1:2; /* 1 */ 402 uint32 lm_counter_index_2:6; /* 2 */ 403 uint32 cos_msb_1:2; /* 2 */ 404 uint32 cell_error:1; /* 3 */ 405 uint32 _rsvd2:1; /* 3 */ 406 uint32 lm_counter_index_1:6; /* 3 */ 407 uint32 oam_replacement_type:2; /* 4 */ 408 uint32 oam_replacement_offset:6; /* 4 */ 409 uint32 hdr_offset:8; /* 5 */ 410 uint32 input_pri:4; /* 6 */ 411 uint32 set_l2bm:1; /* 6 */ 412 uint32 its_sign:1; /* 6 */ 413 uint32 regen_udp_checksum:1; /* 6 */ 414 uint32 osts:1; /* 6 */ 415 uint32 dst_pp_port:8; /* 7 */ 416 uint32 cos_lsb:4; /* 8 */ 417 uint32 spid:2; /* 8 */ 418 uint32 set_l3bm:1; /* 8 */ 419 uint32 tx_ts:1; /* 8 */ 420 uint32 queue_num_2:4; /* 9 */ 421 uint32 unicast:1; /* 9 */ 422 uint32 spap:2; /* 9 */ 423 uint32 spid_override:1; /* 9 */ 424 uint32 queue_num_1:8; /* 10 */ 425 uint32 src_mod:8; /* 11 */ 426 } overlay1; 427 428 /* Overlay 2 : SOBMH_EP_COPY_TO_CPU */ 429 struct { /* Byte # */ 430 uint32 header_type:6; /* 0 */ 431 uint32 start:2; /* 0 */ 432 uint32 ep_cpu_reason_code_3:5; /* 1 */ 433 uint32 _rsvd1:3; /* 1 */ 434 uint32 ep_cpu_reason_code_2:8; /* 2 */ 435 uint32 cell_error:1; /* 3 */ 436 uint32 ep_cpu_reason_code_1:7; /* 3 */ 437 uint32 final_cpu_cos:6; /* 4 */ 438 uint32 _rsvd2:2; /* 4 */ 439 uint32 _rsvd3:8; /* 5 */ 440 uint32 _rsvd4:8; /* 6 */ 441 uint32 dst_pp_port:8; /* 7 */ 442 uint32 cos:4; /* 8 */ 443 uint32 input_pri:4; /* 8 */ 444 uint32 queue_num_2:4; /* 9 */ 445 uint32 unicast:1; /* 9 */ 446 uint32 _rsvd5:3; /* 9 */ 447 uint32 queue_num_1:8; /* 10 */ 448 uint32 src_mod:8; /* 11 */ 449 } overlay2; 450 451 /* Overlay 3 : SOBMH_OAM_DOWNMEP_TX */ 452 struct { /* Byte # */ 453 uint32 header_type:6; /* 0 */ 454 uint32 start:2; /* 0 */ 455 uint32 _rsvd0:8; /* 1 */ 456 uint32 ma_ptr_2:4; /* 2 */ 457 uint32 sample_rdi:1; /* 2 */ 458 uint32 ts_action:2; /* 2 */ 459 uint32 _rsvd1:1; /* 2 */ 460 uint32 cell_error:1; /* 3 */ 461 uint32 ma_ptr_1:7; /* 3 */ 462 uint32 _rsvd2:2; /* 4 */ 463 uint32 oam_replacement_offset:6; /* 4 */ 464 uint32 ctr2_action:2; /* 5 */ 465 uint32 olp_pkt_from_hg_port:1; /* 5 */ 466 uint32 source_olp:1; /* 5 */ 467 uint32 ctr1_location:1; /* 5 */ 468 uint32 ctr2_location:1; /* 5 */ 469 uint32 _rsvd3:2; /* 5 */ 470 uint32 ctr2_id_2:8; /* 6 */ 471 uint32 ctr1_id_2:3; /* 7 */ 472 uint32 ctr1_action:2; /* 7 */ 473 uint32 ctr2_id_1:3; /* 7 */ 474 uint32 ctr1_id_1:8; /* 8 */ 475 uint32 queue_num_2:4; /* 9 */ 476 uint32 input_pri:4; /* 9 */ 477 uint32 queue_num_1:8; /* 10 */ 478 uint32 pp_port:8; /* 11 */ 479 } overlay3; 480 481 /* Overlay 4 : SOBMH_OAM_UPMEP_TX */ 482 struct { /* Byte # */ 483 uint32 header_type:6; /* 0 */ 484 uint32 start:2; /* 0 */ 485 uint32 _rsvd1:8; /* 1 */ 486 uint32 ma_ptr_2:4; /* 2 */ 487 uint32 sample_rdi:1; /* 2 */ 488 uint32 ts_action:2; /* 2 */ 489 uint32 _rsvd2:1; /* 2 */ 490 uint32 _rsvd3:1; /* 3 */ 491 uint32 ma_ptr_1:7; /* 3 */ 492 uint32 _rsvd4:2; /* 4 */ 493 uint32 oam_replacement_offset:6; /* 4 */ 494 uint32 ctr2_action:2; /* 5 */ 495 uint32 olp_pkt_from_hg_port:1; /* 5 */ 496 uint32 source_olp:1; /* 5 */ 497 uint32 _rsvd5:4; /* 5 */ 498 uint32 ctr2_id_2:8; /* 6 */ 499 uint32 ctr1_id_2:3; /* 7 */ 500 uint32 ctr1_action:2; /* 7 */ 501 uint32 ctr2_id_1:3; /* 7 */ 502 uint32 ctr1_id_1:8; /* 8 */ 503 uint32 _rsvd6:8; /* 9 */ 504 uint32 int_pri:4; /* 10 */ 505 uint32 ctr1_location:1; /* 10 */ 506 uint32 ctr2_location:1; /* 10 */ 507 uint32 _rsvd7:2; /* 10 */ 508 uint32 pp_port:8; /* 11 */ 509 } overlay4; 510 511 /* Overlay 5 : SOBMH_OAM_DOWNMEP_TX for metrolite*/ 512 struct { /* Byte # */ 513 uint32 header_type:6; /* 0 */ 514 uint32 start:2; /* 0 */ 515 uint32 _rsvd0_1:8; /* 1 */ 516 uint32 ma_ptr_2:3; /* 2 */ 517 uint32 ma_ptr_rsvd:1; /* 2 */ 518 uint32 sample_rdi:1; /* 2 */ 519 uint32 ts_action:2; /* 2 */ 520 uint32 _rsvd0_2:1; /* 2 */ 521 uint32 cell_error:1; /* 3 */ 522 uint32 ma_ptr_1:7; /* 3 */ 523 uint32 _rsvd1_1:2; /* 4 */ 524 uint32 oam_replacement_offset:6; /* 4 */ 525 uint32 ctr1_location:1; /* 5 */ 526 uint32 ctr2_location:1; /* 5 */ 527 uint32 _rsvd1_2:6; /* 5 */ 528 uint32 ctr2_id_2:4; /* 6 */ 529 uint32 ctr2_action:2; /* 6 */ 530 uint32 olp_pkt_from_hg_port:1; /* 6 */ 531 uint32 source_olp:1; /* 6 */ 532 uint32 ctr1_id_2:1; /* 7 */ 533 uint32 ctr1_action:2; /* 7 */ 534 uint32 ctr2_id_1:5; /* 7 */ 535 uint32 ctr1_id_1:8; /* 8 */ 536 uint32 queue_num_2:1; /* 9 */ 537 uint32 _rsvd2:3; /* 9 */ 538 uint32 input_pri:4; /* 9 */ 539 uint32 queue_num_1:8; /* 10 */ 540 uint32 pp_port:5; /* 11 */ 541 uint32 reserved_pp_port:3; /* 11 */ 542 } overlay5; 543 544 /* Overlay 6 : SOBMH_OAM_UPMEP_TX for metrolite*/ 545 struct { /* Byte # */ 546 uint32 header_type:6; /* 0 */ 547 uint32 start:2; /* 0 */ 548 uint32 _rsvd0_1:8; /* 1 */ 549 uint32 ma_ptr_2:3; /* 2 */ 550 uint32 ma_ptr_rsvd:1; /* 2 */ 551 uint32 sample_rdi:1; /* 2 */ 552 uint32 ts_action:2; /* 2 */ 553 uint32 _rsvd0_2:1; /* 2 */ 554 uint32 _rsvd1:1; /* 3 */ 555 uint32 ma_ptr_1:7; /* 3 */ 556 uint32 _rsvd2_1:2; /* 4 */ 557 uint32 oam_replacement_offset:6; /* 4 */ 558 uint32 _rsvd2_2:8; /* 5 */ 559 uint32 ctr2_id_2:4; /* 6 */ 560 uint32 ctr2_action:2; /* 6 */ 561 uint32 olp_pkt_from_hg_port:1; /* 6 */ 562 uint32 source_olp:1; /* 6 */ 563 uint32 ctr1_id_2:1; /* 7 */ 564 uint32 ctr1_action:2; /* 7 */ 565 uint32 ctr2_id_1:5; /* 7 */ 566 uint32 ctr1_id_1:8; /* 8 */ 567 uint32 _rsvd3_1:8; /* 9 */ 568 uint32 int_pri:4; /* 10 */ 569 uint32 ctr1_location:1; /* 10 */ 570 uint32 ctr2_location:1; /* 10 */ 571 uint32 _rsvd3_2:2; /* 10 */ 572 uint32 pp_port:5; /* 11 */ 573 uint32 _rsvd4:3; /* 11 */ 574 } overlay6; 575 576 #else /* !LE_HOST */ 577 /* Overlay 1 : SOBMH_FROM_CPU */ 578 struct { /* Byte # */ 579 uint32 start:2; /* 0 */ 580 uint32 header_type:6; /* 0 */ 581 uint32 _rsvd1:2; /* 1 */ 582 uint32 cos_msb_2:6; /* 1 */ 583 uint32 cos_msb_1:2; /* 2 */ 584 uint32 lm_counter_index_2:6; /* 2 */ 585 uint32 lm_counter_index_1:6; /* 3 */ 586 uint32 _rsvd2:1; /* 3 */ 587 uint32 cell_error:1; /* 3 */ 588 uint32 oam_replacement_offset:6; /* 4 */ 589 uint32 oam_replacement_type:2; /* 4 */ 590 uint32 hdr_offset:8; /* 5 */ 591 uint32 osts:1; /* 6 */ 592 uint32 regen_udp_checksum:1; /* 6 */ 593 uint32 its_sign:1; /* 6 */ 594 uint32 set_l2bm:1; /* 6 */ 595 uint32 input_pri:4; /* 6 */ 596 uint32 dst_pp_port:8; /* 7 */ 597 uint32 tx_ts:1; /* 8 */ 598 uint32 set_l3bm:1; /* 8 */ 599 uint32 spid:2; /* 8 */ 600 uint32 cos_lsb:4; /* 8 */ 601 uint32 spid_override:1; /* 9 */ 602 uint32 spap:2; /* 9 */ 603 uint32 unicast:1; /* 9 */ 604 uint32 queue_num_2:4; /* 9 */ 605 uint32 queue_num_1:8; /* 10 */ 606 uint32 src_mod:8; /* 11 */ 607 } overlay1; 608 609 /* Overlay 2 : SOBMH_EP_COPY_TO_CPU */ 610 struct { /* Byte # */ 611 uint32 start:2; /* 0 */ 612 uint32 header_type:6; /* 0 */ 613 uint32 _rsvd1:3; /* 1 */ 614 uint32 ep_cpu_reason_code_3:5; /* 1 */ 615 uint32 ep_cpu_reason_code_2:8; /* 2 */ 616 uint32 ep_cpu_reason_code_1:7; /* 3 */ 617 uint32 cell_error:1; /* 3 */ 618 uint32 _rsvd2:2; /* 4 */ 619 uint32 final_cpu_cos:6; /* 4 */ 620 uint32 _rsvd3:8; /* 5 */ 621 uint32 _rsvd4:8; /* 6 */ 622 uint32 dst_pp_port:8; /* 7 */ 623 uint32 input_pri:4; /* 8 */ 624 uint32 cos:4; /* 8 */ 625 uint32 _rsvd5:3; /* 9 */ 626 uint32 unicast:1; /* 9 */ 627 uint32 queue_num_2:4; /* 9 */ 628 uint32 queue_num_1:8; /* 10 */ 629 uint32 src_mod:8; /* 11 */ 630 } overlay2; 631 632 /* Overlay 3 : SOBMH_OAM_DOWNMEP_TX */ 633 struct { /* Byte # */ 634 uint32 start:2; /* 0 */ 635 uint32 header_type:6; /* 0 */ 636 uint32 _rsvd0:8; /* 1 */ 637 uint32 _rsvd1:1; /* 2 */ 638 uint32 ts_action:2; /* 2 */ 639 uint32 sample_rdi:1; /* 2 */ 640 uint32 ma_ptr_2:4; /* 2 */ 641 uint32 ma_ptr_1:7; /* 3 */ 642 uint32 cell_error:1; /* 3 */ 643 uint32 oam_replacement_offset:6; /* 4 */ 644 uint32 _rsvd2:2; /* 4 */ 645 uint32 _rsvd3:2; /* 5 */ 646 uint32 ctr2_location:1; /* 5 */ 647 uint32 ctr1_location:1; /* 5 */ 648 uint32 source_olp:1; /* 5 */ 649 uint32 olp_pkt_from_hg_port:1; /* 5 */ 650 uint32 ctr2_action:2; /* 5 */ 651 uint32 ctr2_id_2:8; /* 6 */ 652 uint32 ctr2_id_1:3; /* 7 */ 653 uint32 ctr1_action:2; /* 7 */ 654 uint32 ctr1_id_2:3; /* 7 */ 655 uint32 ctr1_id_1:8; /* 8 */ 656 uint32 input_pri:4; /* 9 */ 657 uint32 queue_num_2:4; /* 9 */ 658 uint32 queue_num_1:8; /* 10 */ 659 uint32 pp_port:8; /* 11 */ 660 } overlay3; 661 662 /* Overlay 4 : SOBMH_OAM_UPMEP_TX */ 663 struct { /* Byte # */ 664 uint32 start:2; /* 0 */ 665 uint32 header_type:6; /* 0 */ 666 uint32 _rsvd1:8; /* 1 */ 667 uint32 _rsvd2:1; /* 2 */ 668 uint32 ts_action:2; /* 2 */ 669 uint32 sample_rdi:1; /* 2 */ 670 uint32 ma_ptr_2:4; /* 2 */ 671 uint32 ma_ptr_1:7; /* 3 */ 672 uint32 _rsvd3:1; /* 3 */ 673 uint32 oam_replacement_offset:6; /* 4 */ 674 uint32 _rsvd4:2; /* 4 */ 675 uint32 _rsvd5:4; /* 5 */ 676 uint32 source_olp:1; /* 5 */ 677 uint32 olp_pkt_from_hg_port:1; /* 5 */ 678 uint32 ctr2_action:2; /* 5 */ 679 uint32 ctr2_id_2:8; /* 6 */ 680 uint32 ctr2_id_1:3; /* 7 */ 681 uint32 ctr1_action:2; /* 7 */ 682 uint32 ctr1_id_2:3; /* 7 */ 683 uint32 ctr1_id_1:8; /* 8 */ 684 uint32 _rsvd6:8; /* 9 */ 685 uint32 _rsvd7:2; /* 10 */ 686 uint32 ctr2_location:1; /* 10 */ 687 uint32 ctr1_location:1; /* 10 */ 688 uint32 int_pri:4; /* 10 */ 689 uint32 pp_port:8; /* 11 */ 690 } overlay4; 691 692 /* Overlay 5 : SOBMH_OAM_DOWNMEP_TX for metrolite*/ 693 struct { /* Byte # */ 694 uint32 start:2; /* 0 */ 695 uint32 header_type:6; /* 0 */ 696 uint32 _rsvd0_1:8; /* 1 */ 697 uint32 _rsvd0_2:1; /* 2 */ 698 uint32 ts_action:2; /* 2 */ 699 uint32 sample_rdi:1; /* 2 */ 700 uint32 ma_ptr_rsvd:1; /* 2 */ 701 uint32 ma_ptr_2:3; /* 2 */ 702 uint32 ma_ptr_1:7; /* 3 */ 703 uint32 cell_error:1; /* 3 */ 704 uint32 oam_replacement_offset:6; /* 4 */ 705 uint32 _rsvd1_1:2; /* 4 */ 706 uint32 _rsvd1_2:6; /* 5 */ 707 uint32 ctr2_location:1; /* 5 */ 708 uint32 ctr1_location:1; /* 5 */ 709 uint32 source_olp:1; /* 6 */ 710 uint32 olp_pkt_from_hg_port:1; /* 6 */ 711 uint32 ctr2_action:2; /* 6 */ 712 uint32 ctr2_id_2:4; /* 6 */ 713 uint32 ctr2_id_1:5; /* 7 */ 714 uint32 ctr1_action:2; /* 7 */ 715 uint32 ctr1_id_2:1; /* 7 */ 716 uint32 ctr1_id_1:8; /* 8 */ 717 uint32 input_pri:4; /* 9 */ 718 uint32 _rsvd2:3; /* 9 */ 719 uint32 queue_num_2:1; /* 9 */ 720 uint32 queue_num_1:8; /* 10 */ 721 uint32 reserved_pp_port:3; /* 11 */ 722 uint32 pp_port:5; /* 11 */ 723 } overlay5; 724 725 /* Overlay 6 : SOBMH_OAM_UPMEP_TX for metrolite*/ 726 struct { /* Byte # */ 727 uint32 start:2; /* 0 */ 728 uint32 header_type:6; /* 0 */ 729 uint32 _rsvd0_1:8; /* 1 */ 730 uint32 _rsvd0_2:1; /* 2 */ 731 uint32 ts_action:2; /* 2 */ 732 uint32 sample_rdi:1; /* 2 */ 733 uint32 ma_ptr_rsvd:1; /* 2 */ 734 uint32 ma_ptr_2:3; /* 2 */ 735 uint32 ma_ptr_1:7; /* 3 */ 736 uint32 _rsvd1:1; /* 3 */ 737 uint32 oam_replacement_offset:6; /* 4 */ 738 uint32 _rsvd2_1:2; /* 4 */ 739 uint32 _rsvd2_2:8; /* 5 */ 740 uint32 source_olp:1; /* 6 */ 741 uint32 olp_pkt_from_hg_port:1; /* 6 */ 742 uint32 ctr2_action:2; /* 6 */ 743 uint32 ctr2_id_2:4; /* 6 */ 744 uint32 ctr2_id_1:5; /* 7 */ 745 uint32 ctr1_action:2; /* 7 */ 746 uint32 ctr1_id_2:1; /* 7 */ 747 uint32 ctr1_id_1:8; /* 8 */ 748 uint32 _rsvd3_1:8; /* 9 */ 749 uint32 _rsvd3_2:2; /* 10 */ 750 uint32 ctr2_location:1; /* 10 */ 751 uint32 ctr1_location:1; /* 10 */ 752 uint32 int_pri:4; /* 10 */ 753 uint32 _rsvd4:3; /* 11 */ 754 uint32 pp_port:5; /* 11 */ 755 } overlay6; 756 757 #endif /* !LE_HOST */ 758 } soc_pbsmh_v8_hdr_t; 759 760 /* Header types 0 to 0xb same as Type 7 */ 761 #define PBS_MH_V8_HDR_TYPE_OAM_DOWNMEP_TX 0xC 762 #define PBS_MH_V8_HDR_TYPE_OAM_UPMEP_TX 0xD 763 #define PBS_MH_V8_HDR_TYPE_OAM_DOWNMEP_CCM_RX 0xE 764 #define PBS_MH_V8_HDR_TYPE_OAM_UPMEP_CCM_RX 0xF 765 766 typedef struct soc_pbsmh_v9_hdr_s { 767 #if defined(LE_HOST) 768 /* Byte # */ 769 uint32 header_type:6; /* 0 */ 770 uint32 start:2; /* 0 */ 771 uint32 _rsvd3_3:4; /* 1 */ 772 uint32 _rsvd4:4; /* 1 */ 773 uint32 _rsvd3_2:8; /* 2 */ 774 uint32 _rsvd3_1:8; /* 3 */ 775 uint32 _rsvd2_2:8; /* 4 */ 776 uint32 tx_ts:1; /* 5 */ 777 uint32 its_sign:1; /* 5 */ 778 uint32 regen_udp_checksum:1; /* 5 */ 779 uint32 osts:1; /* 5 */ 780 uint32 cell_error:1; /* 5 */ 781 uint32 _rsvd2_1:3; /* 5 */ 782 uint32 hdr_offset:8; /* 6 */ 783 uint32 dst_port:8; /* 7 */ 784 uint32 spid_override:1; /* 8 */ 785 uint32 input_pri:4; /* 8 */ 786 uint32 _rsvd1:3; /* 8 */ 787 uint32 rqe_q_num:4; /* 9 */ 788 uint32 spap:2; /* 9 */ 789 uint32 spid:2; /* 9 */ 790 uint32 cos:6; /* 10 */ 791 uint32 unicast:1; /* 10 */ 792 uint32 set_l2bm:1; /* 10 */ 793 uint32 src_mod:8; /* 11 */ 794 #else /* !LE_HOST */ 795 /* Byte # */ 796 uint32 start:2; /* 0 */ 797 uint32 header_type:6; /* 0 */ 798 uint32 _rsvd4:4; /* 1 */ 799 uint32 _rsvd3_3:4; /* 1 */ 800 uint32 _rsvd3_2:8; /* 2 */ 801 uint32 _rsvd3_1:8; /* 3 */ 802 uint32 _rsvd2_2:8; /* 4 */ 803 uint32 _rsvd2_1:3; /* 5 */ 804 uint32 cell_error:1; /* 5 */ 805 uint32 osts:1; /* 5 */ 806 uint32 regen_udp_checksum:1; /* 5 */ 807 uint32 its_sign:1; /* 5 */ 808 uint32 tx_ts:1; /* 5 */ 809 uint32 hdr_offset:8; /* 6 */ 810 uint32 dst_port:8; /* 7 */ 811 uint32 _rsvd1:3; /* 8 */ 812 uint32 input_pri:4; /* 8 */ 813 uint32 spid_override:1; /* 8 */ 814 uint32 spid:2; /* 9 */ 815 uint32 spap:2; /* 9 */ 816 uint32 rqe_q_num:4; /* 9 */ 817 uint32 set_l2bm:1; /* 10 */ 818 uint32 unicast:1; /* 10 */ 819 uint32 cos:6; /* 10 */ 820 uint32 src_mod:8; /* 11 */ 821 #endif /* !LE_HOST */ 822 } soc_pbsmh_v9_hdr_t; 823 824 #define PBS_MH_V9_HDR_TYPE_FROM_CPU 1 825 826 /* Upper 3 words of the header */ 827 /* Used by Trident2+, Apache */ 828 typedef struct soc_pbsmh_v10_hdr_s { 829 uint32 hdr[3]; 830 } soc_pbsmh_v10_hdr_t; 831 832 typedef struct soc_pbsmh_v11_hdr_s { 833 #if defined(LE_HOST) 834 /* Byte # */ 835 uint32 header_type:6; /* 0 */ 836 uint32 start:2; /* 0 */ 837 uint32 _rsvd3_3:4; /* 1 */ 838 uint32 _rsvd4:4; /* 1 */ 839 uint32 _rsvd3_2:8; /* 2 */ 840 uint32 _rsvd3_1:8; /* 3 */ 841 uint32 _rsvd2_2:8; /* 4 */ 842 uint32 tx_ts:1; /* 5 */ 843 uint32 its_sign:1; /* 5 */ 844 uint32 regen_udp_checksum:1; /* 5 */ 845 uint32 osts:1; /* 5 */ 846 uint32 cell_error:1; /* 5 */ 847 uint32 amp_ts_act:1; /* 5 */ 848 uint32 _rsvd2_1:2; /* 5 */ 849 uint32 hdr_offset:8; /* 6 */ 850 uint32 dst_port:8; /* 7 */ 851 uint32 spid_0:1; /* 8 */ 852 uint32 spid_override:1; /* 8 */ 853 uint32 input_pri:4; /* 8 */ 854 uint32 _rsvd1:2; /* 8 */ 855 uint32 set_l2bm:1; /* 9 */ 856 uint32 rqe_q_num:4; /* 9 */ 857 uint32 spap:2; /* 9 */ 858 uint32 spid_1:1; /* 9 */ 859 uint32 src_mod_1:1; /* 10 */ 860 uint32 cos:6; /* 10 */ 861 uint32 unicast:1; /* 10 */ 862 uint32 src_mod_7:7; /* 11 */ 863 #else /* !LE_HOST */ 864 /* Byte # */ 865 uint32 start:2; /* 0 */ 866 uint32 header_type:6; /* 0 */ 867 uint32 _rsvd4:4; /* 1 */ 868 uint32 _rsvd3_3:4; /* 1 */ 869 uint32 _rsvd3_2:8; /* 2 */ 870 uint32 _rsvd3_1:8; /* 3 */ 871 uint32 _rsvd2_2:8; /* 4 */ 872 uint32 _rsvd2_1:2; /* 5 */ 873 uint32 amp_ts_act:1; /* 5 */ 874 uint32 cell_error:1; /* 5 */ 875 uint32 osts:1; /* 5 */ 876 uint32 regen_udp_checksum:1; /* 5 */ 877 uint32 its_sign:1; /* 5 */ 878 uint32 tx_ts:1; /* 5 */ 879 uint32 hdr_offset:8; /* 6 */ 880 uint32 dst_port:8; /* 7 */ 881 uint32 _rsvd1:2; /* 8 */ 882 uint32 input_pri:4; /* 8 */ 883 uint32 spid_override:1; /* 8 */ 884 uint32 spid_0:1; /* 8 */ 885 uint32 spid_1:1; /* 9 */ 886 uint32 spap:2; /* 9 */ 887 uint32 rqe_q_num:4; /* 9 */ 888 uint32 set_l2bm:1; /* 9 */ 889 uint32 unicast:1; /* 10 */ 890 uint32 cos:6; /* 10 */ 891 uint32 src_mod_1:1; /* 10 */ 892 uint32 src_mod_7:7; /* 11 */ 893 #endif /* !LE_HOST */ 894 } soc_pbsmh_v11_hdr_t; 895 896 typedef struct soc_pbsmh_field_attr { 897 /* use SOC_PBSMH_GET_BIT_POS to convert regsfile bit offset */ 898 unsigned int off; 899 unsigned int size; /* field's size 1 ... 31 */ 900 } soc_pbsmh_field_attr_t; 901 902 903 /* 904 * Fast macros to setup the PBSMH 905 */ 906 #if defined(LE_HOST) 907 #define PBS_MH_W0_START_SET(mh) (((uint32 *)(mh))[0] = 0x000000FF) 908 #define PBS_MH_W1_RSVD_SET(mh) (((uint32 *)(mh))[1] = 0x00000000) 909 910 #define PBS_MH_V1_W2_SMOD_DPORT_COS_SET(mh, smod, dport, cos, dc1, dc2) \ 911 (((uint32 *)(mh))[2] = (smod << 16) | (cos << 29) | (dport << 24)) 912 913 #define PBS_MH_V2_W2_SMOD_DPORT_COS_SET(mh, smod, dport, cos, ipri, l3pbm_sel) \ 914 (((uint32 *)(mh))[2] = (smod << 8) | (ipri << 20) | (cos << 16) | \ 915 (l3pbm_sel << 31) | (dport << 24)) 916 917 #define PBS_MH_V3_W2_SMOD_DPORT_COS_SET(mh, smod, dport, cos, ipri, l3pbm_sel) \ 918 (((uint32 *)(mh))[2] = ((smod >> 4) & 0xf) | ((smod & 0xf) << 12) | \ 919 (ipri << 8) | (cos << 16) | \ 920 (l3pbm_sel << 31) | (dport << 24)) 921 922 #define PBS_MH_V4_W2_SMOD_DPORT_COS_SET(mh, smod, dport, cos, ipri, l3pbm_sel) \ 923 (((uint32 *)(mh))[2] = ((smod >> 7) & 0x1) | ((smod & 0x7f) << 9) | \ 924 (((ipri >> 3) & 0x1) << 8) | \ 925 ((ipri & 0x7) << 21) | (cos << 16) | \ 926 (l3pbm_sel << 31) | (dport << 24)) 927 928 #define PBS_MH_V5_W1_SMOD_SET(mh, smod, unicast, set_l2bm, set_l3bm) \ 929 (((uint32 *)(mh))[1] = (((smod & 0xff) << 24) | \ 930 (unicast ? 0x10000 : 0) | \ 931 (set_l2bm ? 0x20000 : 0) | \ 932 (set_l3bm ? 0x40000 : 0))) 933 934 #define PBS_MH_V5_W2_DPORT_COS_SET(mh, dport, cos, ipri) \ 935 (((uint32 *)(mh))[2] = ((ipri & 0xf) | \ 936 ((cos & 0x7f) << 8) | \ 937 ((cos & 0xf) << 16) | \ 938 ((dport & 0x7f) << 24))) 939 940 #define PBS_MH_V6_W2_DPORT_COS_QNUM_SET(mh, dport, cos, qnum, ipri) \ 941 (((uint32 *)(mh))[2] = (((dport & 0x7f) << 24) | \ 942 ((cos & 0x3f) << 16) | \ 943 ((ipri & 0xf) << 2) | \ 944 ((qnum & 0x3) << 22) | \ 945 ((qnum & 0x3fc) << 6) | \ 946 ((qnum & 0xc00) >> 10))) 947 /* 43: Offset of soc_pbsmh_v6_hdr_t.tx_ts */ 948 #define PBS_MH_V6_TS_PKT_SET(mh) (((uint32 *)(mh))[1] |= (1 << 12)) 949 950 /* 26: Offset of soc_pbsmh_v6_hdr_t.its_sign */ 951 #define PBS_MH_V6_TS_ONE_STEP_INGRESS_SIGN_PKT_SET(mh) \ 952 (((uint32 *)(mh))[0] |= (1 << 26)) 953 /* 25: Offset of soc_pbsmh_v6_hdr_t.regen_udp_chksum */ 954 #define PBS_MH_V6_TS_ONE_STEP_HDR_START_REGEN_UDP_CHEKSUM_PKT_SET(mh) \ 955 (((uint32 *)(mh))[0] |= (1 << 25)) 956 957 /* 24: Offset of soc_pbsmh_v6_hdr_t.osts */ 958 #define PBS_MH_V6_TS_ONE_STEP_PKT_SET(mh) \ 959 (((uint32 *)(mh))[0] |= (1 << 24)) 960 961 /* 27: Offset of soc_pbsmh_v6_hdr_t.hdr_offset_1 */ 962 #define PBS_MH_V6_TS_ONE_STEP_HDR_START_OFFSET_PKT_SET(mh, offset) \ 963 (((uint32 *)(mh))[0] |= (((offset & 0x1f) << 27) | \ 964 ((offset & 0xe0) << 11))) 965 966 967 #define PBS_MH_V2_TS_PKT_SET(mh) (((uint32 *)(mh))[2] |= (1 << 4)) 968 #define PBS_MH_V3_TS_PKT_SET(mh) (((uint32 *)(mh))[2] |= (1 << 4)) 969 #define PBS_MH_V5_TS_PKT_SET(mh) (((uint32 *)(mh))[1] |= (1 << 12)) 970 971 #define PBS_MH_V7_W0_START_SET(mh) (((uint32 *)(mh))[0] = 0x00000081) 972 #define PBS_MH_V7_W1_DPORT_QNUM_SET(mh, dport, qnum) \ 973 (((uint32 *)(mh))[1] = (((dport & 0x7f) << 24) | ((qnum & 0xc00) >> 4))) 974 975 /* 40: Offset of soc_pbsmh_v7_hdr_t.tx_ts */ 976 #define PBS_MH_V7_TS_PKT_SET(mh) (((uint32 *)(mh))[1] |= (1 << 9)) 977 978 /* 41: Offset of soc_pbsmh_v7_hdr_t.its_sign */ 979 #define PBS_MH_V7_TS_ONE_STEP_INGRESS_SIGN_PKT_SET(mh) \ 980 (((uint32 *)(mh))[1] |= (1 << 10)) 981 982 /* 42: Offset of soc_pbsmh_v7_hdr_t.regen_udp_chksum */ 983 #define PBS_MH_V7_TS_ONE_STEP_HDR_START_REGEN_UDP_CHEKSUM_PKT_SET(mh) \ 984 (((uint32 *)(mh))[1] |= (1 << 11)) 985 986 /* 43: Offset of soc_pbsmh_v7_hdr_t.osts */ 987 #define PBS_MH_V7_TS_ONE_STEP_PKT_SET(mh) \ 988 (((uint32 *)(mh))[1] |= (1 << 12)) 989 990 /* 47: Offset of soc_pbsmh_v7_hdr_t.hdr_offset_1 */ 991 #define PBS_MH_V7_TS_ONE_STEP_HDR_START_OFFSET_PKT_SET(mh, offset) \ 992 (((uint32 *)(mh))[1] |= ((offset & 0xff) << 16)) 993 994 #define PBS_MH_V7_W2_SMOD_COS_QNUM_SET(mh, smod, unicast, cos, qnum, ipri) \ 995 (((uint32 *)(mh))[2] = (((smod & 0xff) << 24) | \ 996 ((qnum & 0xff) << 16) | \ 997 (qnum & 0x300) | \ 998 (unicast ? 0x400 : 0) | \ 999 ((ipri & 0xf) << 4) | \ 1000 (cos & 0xf))) 1001 1002 #define PBS_MH_V8_W1_DPORT_IPRI_SET(mh, dport,ipri) \ 1003 (((uint32 *)(mh))[1] = (((dport & 0xff) << 24) | \ 1004 ((ipri & 0xf) << 16))) 1005 #define PBS_MH_V8_W2_SMOD_COS_QNUM_SET(mh, smod, unicast, cos, qnum) \ 1006 (((uint32 *)(mh))[2] = (((smod & 0xff) << 24) | \ 1007 ((qnum & 0xff) << 16) | \ 1008 (qnum & 0xf00) | \ 1009 (unicast ? 0x1000 : 0) | \ 1010 (cos & 0xf))) 1011 1012 #define PBS_MH_V9_W0_START_SET(mh) (((uint32 *)(mh))[0] = 0x00000081) 1013 1014 #define PBS_MH_V9_W1_DPORT_SET(mh, dport) \ 1015 (((uint32 *)(mh))[1] = ((dport & 0xff) << 24)) 1016 1017 #define PBS_MH_V9_W2_SMOD_COS_SET(mh, smod, unicast, cos) \ 1018 (((uint32 *)(mh))[2] = (((smod & 0xff) << 24) | \ 1019 ((cos & 0x3f) << 16) | \ 1020 (unicast ? 0x400000 : 0))) 1021 1022 #define PBS_MH_V9_W2_SMOD_COS_L2BM_SET(mh, smod, unicast, cos, l2bm) \ 1023 (((uint32 *)(mh))[2] = (((smod & 0xff) << 24) | \ 1024 ((cos & 0x3f) << 16) | \ 1025 (unicast ? 0x400000 : 0) |\ 1026 (l2bm ? 0x800000 : 0))) 1027 1028 #define PBS_MH_V9_W2_RQE_SET(mh, rqe) \ 1029 (((uint32 *)(mh))[2] = ((rqe << 8 ))) 1030 #define PBS_MH_V11_W0_START_SET(mh) (((uint32 *)(mh))[0] = 0x00000081) 1031 1032 #define PBS_MH_V11_W1_DPORT_SET(mh, dport) \ 1033 (((uint32 *)(mh))[1] = ((dport & 0xff) << 24)) 1034 1035 #define PBS_MH_V11_W2_SMOD_COS_SET(mh, smod, unicast, cos) \ 1036 (((uint32 *)(mh))[2] = (((smod & 0xff) << 25) | \ 1037 ((cos & 0x3f) << 17) | \ 1038 (unicast ? 0x800000 : 0))) 1039 1040 #define PBS_MH_V11_W2_SMOD_COS_L2BM_SET(mh, smod, unicast, cos, l2bm) \ 1041 (((uint32 *)(mh))[2] = (((smod & 0xff) << 25) | \ 1042 ((cos & 0x3f) << 17) | \ 1043 (unicast ? 0x800000 : 0) |\ 1044 (l2bm ? 0x100 : 0))) 1045 1046 #define PBS_MH_START_IS_SET(mh) \ 1047 (SOC_IS_TRIUMPH3(unit) || SOC_IS_TD2_TT2(unit) || \ 1048 SOC_IS_HURRICANE2(unit) || SOC_IS_KATANA2(unit)|| \ 1049 SOC_IS_GREYHOUND(unit) || SOC_IS_HURRICANE3(unit) || \ 1050 SOC_IS_GREYHOUND2(unit) ? \ 1051 (((((uint32 *)(mh))[0]) & 0x000000C0) == 0x00000080) : \ 1052 (((((uint32 *)(mh))[0]) & 0x000000FF) == 0x000000FF)) 1053 1054 #define PBS_MH_V8_W0_OAM_UPMEP_START_SET(mh) \ 1055 (((uint32 *)(mh))[0] = 0x0000008d) 1056 #define PBS_MH_V8_W0_OAM_DOWNMEP_START_SET(mh) \ 1057 (((uint32 *)(mh))[0] = 0x0000008c) 1058 #define PBS_MH_V8_W0_OAM_DOWNMEP_CTR_LOCATION_SET(unit, mh) \ 1059 (SOC_IS_METROLITE(unit) ? (((uint32 *)(mh))[1] = 0x00000300) : \ 1060 (((uint32 *)(mh))[1] = 0x00003000)) 1061 1062 #else /* !LE_HOST */ 1063 #define PBS_MH_W0_START_SET(mh) (((uint32 *)(mh))[0] = 0xFF000000) 1064 #define PBS_MH_W1_RSVD_SET(mh) (((uint32 *)(mh))[1] = 0x00000000) 1065 1066 #define PBS_MH_V1_W2_SMOD_DPORT_COS_SET(mh, smod, dport, cos, dc1, dc2) \ 1067 (((uint32 *)(mh))[2] = (smod << 8) | (cos << 5) | (dport << 0)) 1068 1069 #define PBS_MH_V2_W2_SMOD_DPORT_COS_SET(mh, smod, dport, cos, ipri, l3pbm_sel) \ 1070 (((uint32 *)(mh))[2] = (smod << 16) | (ipri << 12) | (cos << 8) | \ 1071 (l3pbm_sel << 7) | (dport << 0)) 1072 1073 #define PBS_MH_V3_W2_SMOD_DPORT_COS_SET(mh, smod, dport, cos, ipri, l3pbm_sel) \ 1074 (((uint32 *)(mh))[2] = (smod << 20) | (ipri << 16) | (cos << 8) | \ 1075 (l3pbm_sel << 7) | (dport << 0)) 1076 1077 #define PBS_MH_V4_W2_SMOD_DPORT_COS_SET(mh, smod, dport, cos, ipri, l3pbm_sel) \ 1078 (((uint32 *)(mh))[2] = (smod << 17) | (ipri << 13) | (cos << 8) | \ 1079 (l3pbm_sel << 7) | (dport << 0)) 1080 1081 #define PBS_MH_V5_W1_SMOD_SET(mh, smod, unicast, set_l2bm, set_l3bm) \ 1082 (((uint32 *)(mh))[1] = ((smod & 0xff) | (unicast ? 0x0100 : 0) | \ 1083 (set_l2bm ? 0x0200 : 0) | \ 1084 (set_l3bm ? 0x0400 : 0))) 1085 1086 #define PBS_MH_V5_W2_DPORT_COS_SET(mh, dport, cos, ipri) \ 1087 (((uint32 *)(mh))[2] = (((ipri & 0xf) << 24) | \ 1088 ((cos & 0x7f) << 16) | \ 1089 ((cos & 0xf) << 8) | \ 1090 (dport & 0x7f))) 1091 1092 #define PBS_MH_V6_W2_DPORT_COS_QNUM_SET(mh, dport, cos, qnum, ipri) \ 1093 (((uint32 *)(mh))[2] = (((ipri & 0xf) << 26) | \ 1094 ((qnum & 0xfff) << 14) | \ 1095 ((cos & 0x3f) << 8) | \ 1096 (dport & 0x7f))) 1097 1098 /* 42: Offset of soc_pbsmh_v6_hdr_t.tx_ts */ 1099 #define PBS_MH_V6_TS_PKT_SET(mh) (((uint32 *)(mh))[1] |= (1 << 20)) 1100 1101 /* 29: Offset of soc_pbsmh_v6_hdr_t.its_sign */ 1102 #define PBS_MH_V6_TS_ONE_STEP_INGRESS_SIGN_PKT_SET(mh) \ 1103 (((uint32 *)(mh))[0] |= (1 << 2)) 1104 1105 /* 30: Offset of soc_pbsmh_v6_hdr_t.regen_udp_chksum */ 1106 #define PBS_MH_V6_TS_ONE_STEP_HDR_START_REGEN_UDP_CHEKSUM_PKT_SET(mh) \ 1107 (((uint32 *)(mh))[0] |= (1 << 1)) 1108 1109 /* 31: Offset of soc_pbsmh_v6_hdr_t.osts */ 1110 #define PBS_MH_V6_TS_ONE_STEP_PKT_SET(mh) \ 1111 (((uint32 *)(mh))[0] |= (1 << 0)) 1112 1113 /* 23: Offset of soc_pbsmh_v6_hdr_t.hdr_offset_1 */ 1114 #define PBS_MH_V6_TS_ONE_STEP_HDR_START_OFFSET_PKT_SET(mh, offset) \ 1115 (((uint32 *)(mh))[0] |= ((offset & 0xff) << 3)) 1116 1117 #define PBS_MH_V2_TS_PKT_SET(mh) (((uint32 *)(mh))[2] |= (1 << 28)) 1118 #define PBS_MH_V3_TS_PKT_SET(mh) (((uint32 *)(mh))[2] |= (1 << 28)) 1119 #define PBS_MH_V5_TS_PKT_SET(mh) (((uint32 *)(mh))[1] |= (1 << 20)) 1120 1121 #define PBS_MH_V7_W0_START_SET(mh) (((uint32 *)(mh))[0] = 0x81000000) 1122 #define PBS_MH_V7_W1_DPORT_QNUM_SET(mh, dport, qnum) \ 1123 (((uint32 *)(mh))[1] = (((qnum & 0xc00) << 20) | (dport & 0x7f))) 1124 1125 /* 47: Offset of soc_pbsmh_v7_hdr_t.tx_ts */ 1126 #define PBS_MH_V7_TS_PKT_SET(mh) (((uint32 *)(mh))[1] |= (1 << 17)) 1127 1128 /* 46: Offset of soc_pbsmh_v7_hdr_t.its_sign */ 1129 #define PBS_MH_V7_TS_ONE_STEP_INGRESS_SIGN_PKT_SET(mh) \ 1130 (((uint32 *)(mh))[1] |= (1 << 18)) 1131 1132 /* 45: Offset of soc_pbsmh_v7_hdr_t.regen_udp_chksum */ 1133 #define PBS_MH_V7_TS_ONE_STEP_HDR_START_REGEN_UDP_CHEKSUM_PKT_SET(mh) \ 1134 (((uint32 *)(mh))[1] |= (1 << 19)) 1135 1136 /* 41: Offset of soc_pbsmh_v7_hdr_t.osts */ 1137 #define PBS_MH_V7_TS_ONE_STEP_PKT_SET(mh) \ 1138 (((uint32 *)(mh))[1] |= (1 << 20)) 1139 1140 /* 49: Offset of soc_pbsmh_v7_hdr_t.hdr_offset_1 */ 1141 #define PBS_MH_V7_TS_ONE_STEP_HDR_START_OFFSET_PKT_SET(mh, offset) \ 1142 (((uint32 *)(mh))[1] |= ((offset & 0xff) << 8)) 1143 1144 #define PBS_MH_V7_W2_SMOD_COS_QNUM_SET(mh, smod, unicast, cos, qnum, ipri) \ 1145 (((uint32 *)(mh))[2] = (((ipri & 0xf) << 28) | \ 1146 ((cos & 0xf) << 24) | \ 1147 (unicast ? 0x40000 : 0) | \ 1148 ((qnum & 0x3ff) << 8) | \ 1149 (smod & 0xff))) 1150 1151 #define PBS_MH_V8_W1_DPORT_IPRI_SET(mh, dport,ipri) \ 1152 (((uint32 *)(mh))[1] = ((dport & 0xff) | \ 1153 ((ipri & 0xf) << 8))) 1154 #define PBS_MH_V8_W2_SMOD_COS_QNUM_SET(mh, smod, unicast, cos, qnum) \ 1155 (((uint32 *)(mh))[2] = (((cos & 0xf) << 24) | \ 1156 (unicast ? 0x100000 : 0) | \ 1157 ((qnum & 0xfff) << 8) | \ 1158 (smod & 0xff))) 1159 1160 #define PBS_MH_V9_W0_START_SET(mh) (((uint32 *)(mh))[0] = 0x81000000) 1161 1162 #define PBS_MH_V9_W1_DPORT_SET(mh, dport) \ 1163 (((uint32 *)(mh))[1] = (dport & 0xff)) 1164 1165 #define PBS_MH_V9_W2_SMOD_COS_SET(mh, smod, unicast, cos) \ 1166 (((uint32 *)(mh))[2] = ((smod & 0xff) | \ 1167 ((cos & 0x3f) << 8) | \ 1168 (unicast ? 0x4000 : 0))) 1169 1170 #define PBS_MH_V9_W2_SMOD_COS_L2BM_SET(mh, smod, unicast, cos, l2bm) \ 1171 (((uint32 *)(mh))[2] = ((smod & 0xff) | \ 1172 ((cos & 0x3f) << 8) | \ 1173 (unicast ? 0x4000 : 0) | \ 1174 (l2bm ? 0x8000 : 0))) 1175 1176 #define PBS_MH_V9_W2_RQE_SET(mh, rqe) \ 1177 (((uint32 *)(mh))[2] = ((rqe << 8 ))) 1178 1179 #define PBS_MH_V11_W0_START_SET(mh) (((uint32 *)(mh))[0] = 0x81000000) 1180 1181 #define PBS_MH_V11_W1_DPORT_SET(mh, dport) \ 1182 (((uint32 *)(mh))[1] = (dport & 0xff)) 1183 1184 #define PBS_MH_V11_W2_SMOD_COS_SET(mh, smod, unicast, cos) \ 1185 (((uint32 *)(mh))[2] = (((smod & 0xff) << 1) | \ 1186 ((cos & 0x3f) << 9) | \ 1187 (unicast ? 0x8000 : 0))) 1188 1189 #define PBS_MH_V11_W2_SMOD_COS_L2BM_SET(mh, smod, unicast, cos, l2bm) \ 1190 (((uint32 *)(mh))[2] = (((smod & 0xff) << 1) | \ 1191 ((cos & 0x3f) << 9) | \ 1192 (unicast ? 0x8000 : 0) | \ 1193 (l2bm ? 0x10000 : 0))) 1194 1195 #define PBS_MH_START_IS_SET(mh) \ 1196 (SOC_IS_TRIUMPH3(unit) || SOC_IS_TD2_TT2(unit) || \ 1197 SOC_IS_HURRICANE2(unit) || SOC_IS_KATANA2(unit) || \ 1198 SOC_IS_GREYHOUND(unit) || SOC_IS_HURRICANE3(unit) || \ 1199 SOC_IS_GREYHOUND2(unit) ? \ 1200 (((((uint32 *)(mh))[0]) & 0xC0000000) == 0x80000000) : \ 1201 (((((uint32 *)(mh))[0]) & 0xFF000000) == 0xFF000000)) 1202 1203 #define PBS_MH_V8_W0_OAM_UPMEP_START_SET(mh) \ 1204 (((uint32 *)(mh))[0] = 0x8d000000) 1205 #define PBS_MH_V8_W0_OAM_DOWNMEP_START_SET(mh) \ 1206 (((uint32 *)(mh))[0] = 0x8c000000) 1207 #define PBS_MH_V8_W0_OAM_DOWNMEP_CTR_LOCATION_SET(unit, mh) \ 1208 (SOC_IS_METROLITE(unit) ? (((uint32 *)(mh))[1] = 0x00030000) : \ 1209 (((uint32 *)(mh))[1] = 0x00300000)) 1210 1211 #endif /* !LE_HOST */ 1212 1213 #define SOC_PBSMH_HDR_SIZE ((int) sizeof(soc_pbsmh_hdr_t)) 1214 1215 /* 1216 * PBS MH Field Manipulation 1217 */ 1218 1219 typedef enum { 1220 /* NOTE: strings in soc_pbsmh_field_names[] must match */ 1221 PBSMH_invalid = -1, 1222 PBSMH_start = 0, 1223 PBSMH_src_mod, /* Source Modid to disable E2E checks */ 1224 PBSMH_dst_port, /* Destination port */ 1225 PBSMH_cos, /* COS queue */ 1226 PBSMH_pri, /* Input Priority */ 1227 PBSMH_l3pbm_sel, /* Use L3 PBM */ 1228 PBSMH_l2pbm_sel, /* Use L2 PBM */ 1229 PBSMH_unicast, /* Unicast */ 1230 PBSMH_tx_ts, /* Capture transmit timestamp */ 1231 PBSMH_spid_override, 1232 PBSMH_spid, /* Service pool ID */ 1233 PBSMH_spap, /* Service pool priority */ 1234 PBSMH_queue_num, /* Queue number */ 1235 PBSMH_osts, /* 1588-TS 1-step */ 1236 PBSMH_its_sign, /* 1588-TS Ingress timestamp sign (for 1-step) */ 1237 PBSMH_hdr_offset, /* 1588-TS header start offset (for 1-step) */ 1238 PBSMH_regen_udp_checksum, /* 588-TS UDP checksum update (for 1-step) */ 1239 PBSMH_int_pri, /* Internal Priority */ 1240 PBSMH_nlf_port, /* ? */ 1241 PBSMH_lm_ctr_index, /* ? */ 1242 PBSMH_oam_replacement_type, /* See OAM replacement types below */ 1243 PBSMH_oam_replacement_offset, /* OAM insertion point = 14 + (2 * val) */ 1244 PBSMH_ep_cpu_reasons, /* EP Copy to CPU reasons */ 1245 PBSMH_header_type, /* See PBSMH header types below */ 1246 PBSMH_cell_error, /* Force cell error status */ 1247 PBSMH_ipcf_ptr, /* Pointer to Cell Buffer */ 1248 PBSMH_oam_ma_ptr, /* OAM MA pointer */ 1249 PBSMH_ts_action, /* OAM DM timestamp action */ 1250 PBSMH_sample_rdi, /* OAM Sample RDI bit */ 1251 PBSMH_ctr1_action, /* OAM LM counter 1 action */ 1252 PBSMH_lm_ctr1_index,/* OAM 1st LM counter index */ 1253 PBSMH_ctr2_action, /* OAM LM counter 2 action */ 1254 PBSMH_lm_ctr2_index,/* OAM 2nd LM counter index */ 1255 PBSMH_pp_port, /* OAM-PP port */ 1256 PBSMH_amp_ts_act, /* Insert timestamp in EP for TWAMP/OWAMP */ 1257 PBSMH_COUNT 1258 } soc_pbsmh_field_t; 1259 1260 #ifndef CMICM_EMBEDDED 1261 1262 extern soc_pbsmh_field_t soc_pbsmh_name_to_field(int unit, char *name); 1263 extern char *soc_pbsmh_field_to_name(int unit, soc_pbsmh_field_t f); 1264 1265 extern uint32 soc_pbsmh_field_get(int unit, soc_pbsmh_hdr_t *mh, 1266 soc_pbsmh_field_t field); 1267 extern void soc_pbsmh_field_set(int unit, soc_pbsmh_hdr_t *mh, 1268 soc_pbsmh_field_t field, uint32 val); 1269 1270 extern void soc_pbsmh_dump(int unit, char *pfx, soc_pbsmh_hdr_t *mh); 1271 1272 #define soc_pbsmh_field_init(unit, mh) \ 1273 sal_memset((mh), 0, sizeof (soc_pbsmh_hdr_t)) 1274 1275 #endif 1276 1277 /* PBSMH field default values */ 1278 /* default SOP Symbol */ 1279 #define SOC_PBSMH_START 0xff /* PBS MH indicator */ 1280 #define SOC_PBSMH_START_INTERNAL 0x2 /* PBS MH internal header indicator */ 1281 1282 #define SOC_SOBMH_FROM_CPU 0x1 /* From CPU to Passthru NLF" */ 1283 1284 #endif /* BCM_XGS3_SWITCH_SUPPORT */ 1285 #endif /* !_SOC_PBSMH_H */