metrolite.h (7399B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * File: metrolite.h 8 */ 9 10 #ifndef _SOC_METROLITE_H_ 11 #define _SOC_METROLITE_H_ 12 13 #include <soc/drv.h> 14 #include <soc/mem.h> 15 #include <soc/error.h> 16 #include <soc/katana2.h> 17 #include <soc/saber2.h> 18 #include <soc/shmoo_and28.h> 19 #include <bcm/types.h> 20 21 extern int ml_max_linkphy_subports_per_port; 22 extern int ml_max_linkphy_streams_per_port; 23 extern int ml_max_linkphy_streams_per_slice; 24 25 #define ML_MAX_LOGICAL_PORTS 14 26 #define ML_MAX_PHYSICAL_PORTS 12 27 #define ML_MAX_PP_PORTS 32 28 #define ML_LPBK 13 29 #define ML_CMIC 0 30 #define ML_IDLE ML_MAX_LOGICAL_PORTS 31 #define ML_IDLE_1 ML_IDLE + 1 32 #define ML_MAX_BLOCKS 3 33 #define ML_MAX_PORTS_PER_BLOCK 4 34 35 /* Total available queues on Metrolite device */ 36 #define ML_MMU_MAX_EGRESS_QUEUE 512 37 38 /* Linkphy global variables */ 39 #define SOC_ML_LINKPHY_TX_DATA_BUF_START_ADDR_MAX 3392 40 #define SOC_ML_LINKPHY_TX_DATA_BUF_END_ADDR_MIN 31 41 #define SOC_ML_LINKPHY_TX_DATA_BUF_END_ADDR_MAX 3423 42 #define SOC_ML_LINKPHY_TX_STREAM_START_ADDR_OFFSET 0x80 43 #define SOC_ML_MAX_LINKPHY_BLOCK 1 44 #define SOC_ML_MAX_LINKPHY_PORTS 4 45 #define SOC_ML_MAX_LINKPHY_STREAMS_PER_SLICE ml_max_linkphy_streams_per_slice 46 #define SOC_ML_MAX_LINKPHY_STREAMS_PER_PORT ml_max_linkphy_streams_per_port 47 #define SOC_ML_MAX_LINKPHY_SUBPORTS_PER_PORT ml_max_linkphy_subports_per_port 48 #define SOC_ML_MAX_LINKPHY_STREAMS_PER_SUBPORT 1 49 50 #define SOC_ML_SUBPORT_GROUP_MAX 24 51 #define SOC_ML_MAX_SUBPORTS 24 52 #define SOC_ML_SUBPORT_PP_PORT_INDEX_MIN 0 53 #define SOC_ML_SUBPORT_PP_PORT_INDEX_MAX ML_MAX_PP_PORTS - 1 54 55 #define ML_PORT_MAC_MAX 32 56 57 #define ML_MAX_SERVICE_POOLS 4 58 #define ML_MAX_PRIORITY_GROUPS 8 59 60 61 #define BCM_ML_COSQ_WRED_DROP_MASK 0x006f 62 #define BCM_ML_COSQ_TOTAL_DROP_MASK 0x0000 63 #define BCM_ML_COSQ_DEFAULT_DROP_MASK 0x007f 64 65 66 const static uint32 ml_port_mapping[ML_MAX_LOGICAL_PORTS][2] = 67 { {0,0}, {1,15}, {2,23}, {3, 31}, {4, 39}, {5,47}, {6, 55}, 68 {7,63}, {8, 71}, {9, 79}, {21, 175}, {22, 183}, {23, 191}, {29,239}}; 69 70 #define ML_GET_THDI_PORT(p) ml_port_mapping[p][0] 71 #define ML_GET_THDI_PORT_PG(p) ml_port_mapping[p][1] 72 #define METROLITE_GET_REG_THDI_PORT(unit, port, reg, thdi_port) \ 73 if (SOC_IS_METROLITE(unit) && (block == MMU_BLOCK(unit)) && \ 74 ((SOC_REG_STAGE(unit, reg) == 2) || \ 75 (SOC_REG_STAGE(unit, reg) == 38)| \ 76 (SOC_REG_STAGE(unit, reg) == 40))) { \ 77 thdi_port = ML_GET_THDI_PORT(port);} 78 79 typedef struct ml_pbmp_s { 80 soc_pbmp_t *pbmp_gport_stack; 81 soc_pbmp_t *pbmp_mxq; 82 soc_pbmp_t *pbmp_mxq1g; 83 soc_pbmp_t *pbmp_mxq2p5g; 84 soc_pbmp_t *pbmp_mxq10g; 85 soc_pbmp_t *pbmp_xl; 86 soc_pbmp_t *pbmp_xl1g; 87 soc_pbmp_t *pbmp_xl2p5g; 88 soc_pbmp_t *pbmp_xl10g; 89 soc_pbmp_t *pbmp_xport_ge; 90 soc_pbmp_t *pbmp_xport_xe; 91 soc_pbmp_t *pbmp_valid; 92 soc_pbmp_t *pbmp_pp; 93 soc_pbmp_t *pbmp_linkphy; 94 }ml_pbmp_t; 95 96 typedef uint32 ml_port_speeds_t[ML_MAX_BLOCKS][ML_MAX_PORTS_PER_BLOCK]; 97 typedef uint32 ml_speed_t[ML_MAX_PHYSICAL_PORTS]; 98 typedef uint32 ml_port_to_block_t[ML_MAX_PHYSICAL_PORTS]; 99 typedef uint32 ml_port_to_block_subports_t[ML_MAX_PHYSICAL_PORTS]; 100 typedef uint32 ml_block_ports_t[ML_MAX_BLOCKS][ML_MAX_PORTS_PER_BLOCK]; 101 102 extern int soc_ml_linkphy_port_reg_blk_idx_get( 103 int unit, int port, int blktype, int *block, int *index); 104 extern int soc_ml_linkphy_port_blk_idx_get( 105 int unit, int port, int *block, int *index); 106 extern int soc_ml_linkphy_get_portid(int unit, int block, int index); 107 extern int soc_ml_pp_port_get_port(int unit, soc_port_t pp_port); 108 109 extern void _ml_phy_addr_default(int unit, int port, 110 uint16 *phy_addr, uint16 *phy_addr_int); 111 extern int soc_ml_mem_config(int unit, int dev_id); 112 extern int _soc_ml_mmu_reconfigure(int unit, int port); 113 extern int soc_metrolite_global_param_reconfigure(int unit); 114 extern void soc_metrolite_pbmp_init(int unit, 115 ml_pbmp_t ml_pbmp, 116 soc_pbmp_t *pbmp_pp_unsed); 117 extern void soc_metrolite_subport_init(int unit, 118 soc_pbmp_t *pbmp_pp_unsed); 119 extern int bcm_ml_flexio_pbmp_update(int unit, bcm_pbmp_t *pbmp); 120 extern soc_functions_t soc_metrolite_drv_funs; 121 extern ml_block_ports_t *ml_block_ports[SOC_MAX_NUM_DEVICES]; 122 extern ml_port_speeds_t *ml_port_speeds[SOC_MAX_NUM_DEVICES]; 123 extern int soc_ml_iecell_port_reg_blk_idx_get( 124 int unit, int port, int blktype, int *block, int *index); 125 extern int soc_metrolite_num_cosq_init(int unit); 126 extern void soc_metrolite_sbus_ring_map_config(int unit); 127 extern soc_error_t soc_metrolite_get_port_block( 128 int unit, soc_port_t port,uint8 *block); 129 extern soc_error_t soc_metrolite_reconfigure_tdm(int unit,uint32 new_tdm_size,uint32 *new_tdm); 130 extern void soc_metrolite_block_reset(int unit, uint8 block,int active_low); 131 extern int soc_metrolite_xl_port_speed_get(int unit, int port, int *speed); 132 133 extern int _soc_ml_flexio_scache_allocate(int unit); 134 extern int _soc_ml_flexio_scache_retrieve(int unit); 135 extern int _soc_ml_flexio_scache_sync(int unit); 136 137 extern soc_error_t soc_metrolite_get_mxq_phy_port_mode( 138 int unit, soc_port_t port,int speed, bcmMxqPhyPortMode_t *mode); 139 extern soc_error_t soc_metrolite_get_xl_phy_core_port_mode( 140 int unit, soc_port_t port, bcmXlPhyPortMode_t *phy_mode, 141 bcmXlCorePortMode_t *core_mode); 142 extern int _soc_metrolite_get_cfg_num(int unit, int skip_warmboot, int *new_cfg_num); 143 144 typedef struct bcm56270_tdm_info_s { 145 uint8 tdm_freq; 146 uint32 tdm_size; 147 148 /* Display purpose only */ 149 uint8 row; 150 uint8 col; 151 }bcm56270_tdm_info_t; 152 153 154 /* Configs for BCM56270 */ 155 #define BCM56270_DEVICE_ID_OFFSET_CFG 0 156 #define BCM56270_DEVICE_ID_DEFAULT_CFG 1 157 #define BCM56270_DEVICE_ID_MAX_CFG 1 158 159 /* Configs for BCM56271 */ 160 #define BCM56271_DEVICE_ID_OFFSET_CFG 1 161 #define BCM56271_DEVICE_ID_DEFAULT_CFG 2 162 #define BCM56271_DEVICE_ID_MAX_CFG 4 163 164 /* Configs for BCM56272 */ 165 #define BCM56272_DEVICE_ID_OFFSET_CFG 4 166 #define BCM56272_DEVICE_ID_DEFAULT_CFG 5 167 #define BCM56272_DEVICE_ID_MAX_CFG 6 168 169 typedef struct ml_tdm_pos_info_s { 170 uint16 total_slots; 171 int16 pos[180]; 172 } ml_tdm_pos_info_t; 173 174 #define ML_TDM_MAX_SIZE 204 175 176 extern uint32 ml_current_tdm[ML_TDM_MAX_SIZE]; 177 extern uint32 ml_current_tdm_size; 178 extern ml_tdm_pos_info_t ml_tdm_pos_info[ML_MAX_BLOCKS]; 179 180 extern uint32 ml_current_tdm[ML_TDM_MAX_SIZE]; 181 extern uint32 ml_current_tdm_size; 182 extern ml_tdm_pos_info_t ml_tdm_pos_info[ML_MAX_BLOCKS]; 183 extern void soc_ml_port_bitmap_add(int unit,soc_port_t port,int block, 184 int speed, int new_lanes); 185 extern int soc_metrolite_bond_info_init(int unit); 186 extern int soc_ml_get_max_buffer_size(int unit, int value); 187 #endif /* !_SOC_METROLITE_H_ */