memtune.h (14879B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * File: memtune.h 8 * Purpose: External memory interface tuning routines. 9 */ 10 11 #ifndef _SOC_MEMTUNE_H_ 12 #define _SOC_MEMTUNE_H_ 13 14 #include <soc/register.h> 15 16 /* Top-level routine */ 17 typedef enum soc_mem_interfaces_e { 18 SOC_MEM_INTERFACE_RLDRAM_CH0, 19 SOC_MEM_INTERFACE_RLDRAM_CH1, 20 SOC_MEM_INTERFACE_SRAM, 21 SOC_MEM_INTERFACE_QDR, 22 SOC_MEM_INTERFACE_TCAM, 23 SOC_MEM_INTERFACE_COUNT 24 } soc_mem_interfaces; 25 26 typedef struct soc_memtune_data_s { 27 struct soc_memtune_ctrl_s *mt_ctrl; 28 int interface; 29 int sub_interface; 30 int rseed; 31 int config; 32 int verbose; 33 int suppress_fail; 34 int summary; 35 int summary_header; 36 int show_setting; 37 int show_matrix; 38 int show_progress; 39 int test_count; 40 int max_fail_count; 41 uint32 slice_mask; 42 int do_pvt_comp; 43 int freq; 44 int phase_sel_ovrd; 45 int test_all_latency; 46 int do_txrx_first; 47 uint32 d0r_0; 48 uint32 d0r_1; 49 uint32 d0f_0; 50 uint32 d0f_1; 51 uint32 d1r_0; 52 uint32 d1r_1; 53 uint32 d1f_0; 54 uint32 d1f_1; 55 int adr0; 56 int adr1; 57 int adr_mode; 58 uint32 mask[8]; 59 uint32 data[8]; 60 int tcam_loop_count; 61 int bg_tcam_bist; 62 int bg_tcam_loop_count; 63 uint32 bg_tcam_data[32]; 64 uint32 bg_tcam_oemap; 65 int bg_sram_bist; 66 uint32 bg_d0r_0; 67 uint32 bg_d0r_1; 68 uint32 bg_d0f_0; 69 uint32 bg_d0f_1; 70 uint32 bg_d1r_0; 71 uint32 bg_d1r_1; 72 uint32 bg_d1f_0; 73 uint32 bg_d1f_1; 74 int bg_adr0; 75 int bg_adr1; 76 int bg_loop_mode; 77 int bg_adr_mode; 78 int manual_settings; /* =1 if manual settings */ 79 int man_phase_sel; /* user specified value */ 80 int man_em_latency; /* user specified value */ 81 int man_ddr_latency; /* user specified value */ 82 int man_tx_offset; /* user specified value */ 83 int man_rx_offset; /* user specified value */ 84 int man_w2r_nops; /* user specified value */ 85 int man_r2w_nops; /* user specified value */ 86 87 /* for extt2 */ 88 int loop_mode[2]; 89 int alt_adr; 90 int tcam_data_choice; 91 int sram_data_choice; 92 int delta[2]; 93 int tx_offset[2]; 94 int rx_offset[2]; 95 int *fail_array[2]; 96 int ok_on_both_pass; 97 int restore_txrx_after_test; 98 } soc_memtune_data_t; 99 100 /* Saved tx/rx matrix analysis results for a specific setting */ 101 typedef struct soc_memtune_result_s { 102 int width; 103 int height; 104 int phase_sel; 105 int em_latency; 106 int ddr_latency; 107 int tx_offset; 108 int rx_offset; 109 int invert_txclk; 110 int invert_rxclk; 111 int dpeo_sync_dly; 112 int fcd_dpeo; 113 int rbus_sync_dly; 114 int fcd_rbus; 115 int fail_count; 116 } soc_memtune_result_t; 117 118 #define SOC_MEMTUNE_CTRL_FLAGS_SHOW_TEST_NAME 0x0001 119 #define SOC_MEMTUNE_CTRL_FLAGS_SHOW_SUMMARY 0x0002 120 #define SOC_MEMTUNE_CTRL_FLAGS_SHOW_SUMMARY_HEADER 0x0004 121 #define SOC_MEMTUNE_CTRL_FLAGS_SHOW_FAIL_MATRIX 0x0008 122 #define SOC_MEMTUNE_CTRL_FLAGS_SHOW_ANALYSIS 0x0010 123 #define SOC_MEMTUNE_CTRL_FLAGS_SHOW_SELECTION 0x0020 124 #define SOC_MEMTUNE_CTRL_FLAGS_SHOW_FAIL 0x0040 125 #define SOC_MEMTUNE_CTRL_FLAGS_SHOW_PASS 0x0080 126 #define SOC_MEMTUNE_CTRL_FLAGS_SHOW_NOPS 0x0100 127 #define SOC_MEMTUNE_CTRL_FLAGS_SHOW_PROGRESS 0x0200 128 #define SOC_MEMTUNE_CTRL_FLAGS_SHOW_SETTING 0x0400 129 130 typedef struct soc_memtune_ctrl_s { 131 void *data; 132 void *sram_bist; 133 int unit; 134 char *intf_name; 135 uint32 flags; 136 int (*prog_hw1_fn)(soc_memtune_data_t *); 137 int (*prog_hw2_fn)(soc_memtune_data_t *); 138 int (*prog_hw3_fn)(soc_memtune_data_t *); 139 int (*prog_hw4_fn)(soc_memtune_data_t *); 140 int (*per_tx_fn)(soc_memtune_data_t *); 141 int (*per_rx_fn)(soc_memtune_data_t *); 142 int (*test_fn)(soc_memtune_data_t *); 143 144 /* for both SRAM and TCAM tuning */ 145 int tx_offset_cur; 146 int tx_offset_min; 147 int tx_offset_max; 148 int rx_offset_cur; 149 int rx_offset_min; 150 int rx_offset_max; 151 152 /* for SRAM tuning */ 153 int phase_sel_cur; 154 int phase_sel_min; 155 int phase_sel_max; 156 int em_latency_cur; 157 int em_latency_min; 158 int em_latency_max; 159 int ddr_latency_cur; 160 int ddr_latency_min; 161 int ddr_latency_max; 162 int w2r_nops_cur; 163 int w2r_nops_min; 164 int w2r_nops_max; 165 int r2w_nops_cur; 166 int r2w_nops_min; 167 int r2w_nops_max; 168 169 /* for TCAM tuning */ 170 int invert_txclk_cur; 171 int invert_txclk_min; 172 int invert_txclk_max; 173 int invert_rxclk_cur; 174 int invert_rxclk_min; 175 int invert_rxclk_max; 176 177 /* for TCAM DBUS_out (DPEO) tuning */ 178 int dpeo_sel_cur; 179 int dpeo_sync_dly_cur; 180 int dpeo_sync_dly_min; 181 int dpeo_sync_dly_max; 182 int fcd_dpeo_cur; 183 int fcd_dpeo_min; 184 int fcd_dpeo_max; 185 186 /* for TCAM RBUS tuning */ 187 int rbus_sync_dly_cur; 188 int rbus_sync_dly_min; 189 int rbus_sync_dly_max; 190 int fcd_rbus_cur; 191 int fcd_rbus_min; 192 int fcd_rbus_max; 193 int do_setup_for_rbus_test; 194 195 /* for both SRAM and TCAM tuning */ 196 int dac_value; 197 int ptr_dist; 198 int odtres_val; 199 int pdrive_val; 200 int ndrive_val; 201 int slew_val; 202 203 int tx_pass_threshold; 204 int rx_pass_threshold; 205 int bist_poll_count; 206 int cur_fail_count; 207 uint32 cur_fail_reason; 208 uint32 cur_fail_detail0; 209 uint32 cur_fail_detail1; 210 int *fail_array; 211 int result_count; 212 soc_memtune_result_t result[48]; 213 soc_memtune_result_t *ps_data[4]; 214 } soc_memtune_ctrl_t; 215 216 extern int soc_mem_interface_tune(int unit, soc_memtune_data_t *mt_data); 217 extern int soc_mem_interface_tune_lvl2(int unit, soc_memtune_data_t *mt_data); 218 219 /* Device specific implementations */ 220 221 typedef struct soc_er_memtune_data_s { 222 soc_reg_t ddr_reg1; 223 soc_reg_t ddr_reg2; 224 soc_reg_t ddr_reg3; 225 soc_reg_t timing_reg; 226 soc_reg_t req_cmd; 227 soc_reg_t bist_ctrl; 228 soc_mem_t write_mem; 229 int channel; 230 } soc_er_memtune_data_t; 231 232 typedef struct soc_tr_memtune_data_s { 233 soc_reg_t config_reg1; 234 soc_reg_t config_reg2; 235 soc_reg_t config_reg3; 236 soc_reg_t status_reg2; 237 soc_reg_t mode; 238 soc_reg_t tmode0; 239 soc_reg_t tmode0_other_sram; 240 soc_reg_t sram_ctl; 241 soc_reg_t etc_ctl; 242 soc_reg_t inst_status; 243 uint32 dbus_fail_mask; 244 uint32 rbus_fail_mask; 245 uint32 rbus_valid_mask; 246 } soc_tr_memtune_data_t; 247 248 #define SOC_ER_PHASE_SEL_MIN 0 249 #define SOC_ER_PHASE_SEL_MAX 3 250 #define SOC_ER_EM_LATENCY_MIN 7 251 #define SOC_ER_EM_LATENCY_MAX 8 252 #define SOC_ER_SEER_DDR_LATENCY_MIN 0 253 #define SOC_ER_RLDRAM_DDR_LATENCY_MIN 1 254 #define SOC_ER_DDR_LATENCY_MAX 2 255 #define SOC_ER_RLDRAM_TX_OFFSET_MIN 0 256 #define SOC_ER_RLDRAM_TX_OFFSET_MAX 7 257 #define SOC_ER_RLDRAM_RX_OFFSET_MIN 0 258 #define SOC_ER_RLDRAM_RX_OFFSET_MAX 7 259 #define SOC_ER_DDR_BIST_COUNT 10 260 #define SOC_ER_RLDRAM_BIST_POLL_COUNT 1000 261 #define SOC_ER_RLDRAM_BIST_POLL_INTERVAL 100 262 #define SOC_ER_RLDRAM_SLICE_MASK 0xf 263 #define SOC_ER_SRAM_SLICE_MASK 0xf 264 #define SOC_ER_QDR_SLICE_MASK 0x3 265 266 /* Triumph: SRAM */ 267 #define SOC_TR_PHASE_SEL_MIN 0 268 #define SOC_TR_PHASE_SEL_MAX 3 269 #define SOC_TR_EM_LATENCY_MIN 4 /* skip 0, 1, 2, 3 to save time */ 270 #define SOC_TR_EM_LATENCY_MAX 8 271 #define SOC_TR_DDR_LATENCY_MIN 0 272 #define SOC_TR_DDR_LATENCY_MAX 2 273 #define SOC_TR_SRAM_TX_OFFSET_MIN 0 274 #define SOC_TR_SRAM_TX_OFFSET_MAX 28 275 #define SOC_TR_SRAM_RX_OFFSET_MIN 0 276 #define SOC_TR_SRAM_RX_OFFSET_MAX 28 277 #define SOC_TR_SRAM_W2R_NOPS_MIN 0 278 #define SOC_TR_SRAM_W2R_NOPS_MAX 0 279 #define SOC_TR_SRAM_R2W_NOPS_MIN 3 280 #define SOC_TR_SRAM_R2W_NOPS_MAX 3 281 #define SOC_TR_SRAM_SLICE_MASK 0x3 282 283 /* Triumph: TCAM */ 284 #define SOC_TR_TCAM_INVERT_TXCLK_MIN 0 285 #define SOC_TR_TCAM_INVERT_TXCLK_MAX 1 286 #define SOC_TR_TCAM_INVERT_RXCLK_MIN 0 287 #define SOC_TR_TCAM_INVERT_RXCLK_MAX 1 288 #define SOC_TR_TCAM_TX_OFFSET_MIN 0 289 #define SOC_TR_TCAM_VCDL_TX_OFFSET_MAX 28 /* analog clock source */ 290 #define SOC_TR_TCAM_MIDL_TX_OFFSET_MAX 39 /* digital clock source */ 291 #define SOC_TR_TCAM_RX_OFFSET_MIN 0 292 #define SOC_TR_TCAM_VCDL_RX_OFFSET_MAX 28 /* analog clock source */ 293 #define SOC_TR_TCAM_MIDL_RX_OFFSET_MAX 39 /* digital clock source */ 294 295 /* Triumph: TCAM DBUS_out (DPEO) */ 296 #define SOC_TR_DPEO_SYNC_DLY_MIN 0 297 #define SOC_TR_DPEO_SYNC_DLY_MAX 31 298 #define SOC_TR_FCD_DPEO_MIN 0 299 #define SOC_TR_FCD_DPEO_MAX 1 300 301 /* Triumph: TCAM RBUS */ 302 #define SOC_TR_RBUS_SYNC_DLY_MIN 1 /* 0 means 32 */ 303 #define SOC_TR_RBUS_SYNC_DLY_MAX 31 304 #define SOC_TR_FCD_RBUS_MIN 0 305 #define SOC_TR_FCD_RBUS_MAX 1 /* only use 0 and 1 */ 306 307 308 /* Triumph: config variable encoding for both SRAM and TCAM tuning result */ 309 #define SOC_TR_MEMTUNE_CONFIG_VALID_MASK 0x1 310 311 /* Triumph: config variable encoding for SRAM tuning result */ 312 #define SOC_TR_MEMTUNE_OVRD_SM_MASK 0x1 313 #define SOC_TR_MEMTUNE_OVRD_SM_SHIFT 1 314 #define SOC_TR_MEMTUNE_PHASE_SEL_MASK 0x3 315 #define SOC_TR_MEMTUNE_PHASE_SEL_SHIFT 2 316 #define SOC_TR_MEMTUNE_EM_LATENCY_MASK 0x7 317 #define SOC_TR_MEMTUNE_EM_LATENCY_SHIFT 4 318 #define SOC_TR_MEMTUNE_DDR_LATENCY_MASK 0x3 319 #define SOC_TR_MEMTUNE_DDR_LATENCY_SHIFT 7 320 #define SOC_TR_MEMTUNE_DDR_TX_OFFSET_MASK 0x1f 321 #define SOC_TR_MEMTUNE_DDR_TX_OFFSET_SHIFT 9 322 #define SOC_TR_MEMTUNE_DDR_RX_OFFSET_MASK 0x1f 323 #define SOC_TR_MEMTUNE_DDR_RX_OFFSET_SHIFT 14 324 #define SOC_TR_MEMTUNE_W2R_NOPS_MASK 0x3 325 #define SOC_TR_MEMTUNE_W2R_NOPS_SHIFT 19 326 #define SOC_TR_MEMTUNE_R2W_NOPS_MASK 0x3 327 #define SOC_TR_MEMTUNE_R2W_NOPS_SHIFT 21 328 #define SOC_TR_MEMTUNE_DDR_FREQ_MASK 0x1ff 329 #define SOC_TR_MEMTUNE_DDR_FREQ_SHIFT 23 330 331 /* Triumph: config variable encoding for TCAM tuning result */ 332 #define SOC_TR_MEMTUNE_RBUS_SYNC_DLY_MASK 0x1f 333 #define SOC_TR_MEMTUNE_RBUS_SYNC_DLY_SHIFT 8 334 #define SOC_TR_MEMTUNE_DPEO_SYNC_DLY_MASK 0x1f 335 #define SOC_TR_MEMTUNE_DPEO_SYNC_DLY_SHIFT 13 336 #define SOC_TR_MEMTUNE_FCD_DPEO_MASK 0x1 337 #define SOC_TR_MEMTUNE_FCD_DPEO_SHIFT 18 338 #define SOC_TR_MEMTUNE_FCD_RBUS_MASK 0x3 339 #define SOC_TR_MEMTUNE_FCD_RBUS_SHIFT 22 340 #define SOC_TR_MEMTUNE_TCAM_TX_OFFSET_MASK 0x3f 341 #define SOC_TR_MEMTUNE_TCAM_TX_OFFSET_SHIFT 1 342 #define SOC_TR_MEMTUNE_TCAM_RX_OFFSET_MASK 0x3f 343 #define SOC_TR_MEMTUNE_TCAM_RX_OFFSET_SHIFT 7 344 #define SOC_TR_MEMTUNE_TCAM_FREQ_MASK 0x3ff 345 #define SOC_TR_MEMTUNE_TCAM_FREQ_SHIFT 13 346 #define SOC_TR_MEMTUNE_USE_MIDL_MASK 0x1 347 #define SOC_TR_MEMTUNE_USE_MIDL_SHIFT 23 348 #define SOC_TR_MEMTUNE_INVERT_TXCLK_MASK 0x1 349 #define SOC_TR_MEMTUNE_INVERT_TXCLK_SHIFT 24 350 #define SOC_TR_MEMTUNE_INVERT_RXCLK_MASK 0x1 351 #define SOC_TR_MEMTUNE_INVERT_RXCLK_SHIFT 25 352 353 /* Triumph: config variable encoding for PVT result */ 354 #define SOC_TR_MEMTUNE_OVRD_ODTRES_MASK 0x1 355 #define SOC_TR_MEMTUNE_OVRD_ODTRES_SHIFT 1 356 #define SOC_TR_MEMTUNE_ODTRES_MASK 0xf 357 #define SOC_TR_MEMTUNE_ODTRES_SHIFT 2 358 #define SOC_TR_MEMTUNE_OVRD_DRIVER_MASK 0x1 359 #define SOC_TR_MEMTUNE_OVRD_DRIVER_SHIFT 6 360 #define SOC_TR_MEMTUNE_PDRIVE_MASK 0xf 361 #define SOC_TR_MEMTUNE_PDRIVE_SHIFT 7 362 #define SOC_TR_MEMTUNE_NDRIVE_MASK 0xf 363 #define SOC_TR_MEMTUNE_NDRIVE_SHIFT 11 364 #define SOC_TR_MEMTUNE_OVRD_SLEW_MASK 0x1 365 #define SOC_TR_MEMTUNE_OVRD_SLEW_SHIFT 15 366 #define SOC_TR_MEMTUNE_SLEW_MASK 0xf 367 #define SOC_TR_MEMTUNE_SLEW_SHIFT 16 368 369 /* Triumph: config variable encoding for tuning stats */ 370 #define SOC_TR_MEMTUNE_STATS_WIDTH_MASK 0x3f 371 #define SOC_TR_MEMTUNE_STATS_WIDTH_SHIFT 1 372 #define SOC_TR_MEMTUNE_STATS_HEIGHT_MASK 0x3f 373 #define SOC_TR_MEMTUNE_STATS_HEIGHT_SHIFT 7 374 #define SOC_TR_MEMTUNE_STATS_FAIL_MASK 0x3ff 375 #define SOC_TR_MEMTUNE_STATS_FAIL_SHIFT 13 376 377 #endif /* _SOC_MEMTUNE_H_ */