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intr_cmicx.h (3804B)

      1 /*
      2  * DO NOT EDIT THIS FILE!
      3  * This file is auto-generated from the registers file.
      4  * Edits to this file will be lost when it is regenerated.
      5  *
      6  * 
      7  * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file.
      8  * 
      9  * Copyright 2007-2020 Broadcom Inc. All rights reserved.
     10  *
     11  * File:        intr_cmicx.h
     12  * Purpose:     CMICX interrupt include file.
     13  * Supports:    bcm88790_a0
     14  *              bcm88690_a0
     15  *              bcm88690_b0
     16  *              bcm56870_a0
     17  *              bcm56980_a0
     18  *              bcm56980_b0
     19  *              bcm56370_a0
     20  *              bcm56770_a0
     21  */
     22 
     23 /* Sorted on interrupt bit. Don't modify */
     24 typedef enum cmic_intr_num_type_e {
     25 CMC0_CH0_DESC_DONE=128,
     26 CMC0_CH0_CHAIN_DONE=129,
     27 CMC0_CH0_INTR_COALESCING_INTR=130,
     28 CMC0_CH0_DESC_CONTROLLED_INTR=131,
     29 CMC0_CH1_DESC_DONE=132,
     30 CMC0_CH1_CHAIN_DONE=133,
     31 CMC0_CH1_INTR_COALESCING_INTR=134,
     32 CMC0_CH1_DESC_CONTROLLED_INTR=135,
     33 CMC0_CH2_DESC_DONE=136,
     34 CMC0_CH2_CHAIN_DONE=137,
     35 CMC0_CH2_INTR_COALESCING_INTR=138,
     36 CMC0_CH2_DESC_CONTROLLED_INTR=139,
     37 CMC0_CH3_DESC_DONE=140,
     38 CMC0_CH3_CHAIN_DONE=141,
     39 CMC0_CH3_INTR_COALESCING_INTR=142,
     40 CMC0_CH3_DESC_CONTROLLED_INTR=143,
     41 CMC0_CH4_DESC_DONE=144,
     42 CMC0_CH4_CHAIN_DONE=145,
     43 CMC0_CH4_INTR_COALESCING_INTR=146,
     44 CMC0_CH4_DESC_CONTROLLED_INTR=147,
     45 CMC0_CH5_DESC_DONE=148,
     46 CMC0_CH5_CHAIN_DONE=149,
     47 CMC0_CH5_INTR_COALESCING_INTR=150,
     48 CMC0_CH5_DESC_CONTROLLED_INTR=151,
     49 CMC0_CH6_DESC_DONE=152,
     50 CMC0_CH6_CHAIN_DONE=153,
     51 CMC0_CH6_INTR_COALESCING_INTR=154,
     52 CMC0_CH6_DESC_CONTROLLED_INTR=155,
     53 CMC0_CH7_DESC_DONE=156,
     54 CMC0_CH7_CHAIN_DONE=157,
     55 CMC0_CH7_INTR_COALESCING_INTR=158,
     56 CMC0_CH7_DESC_CONTROLLED_INTR=159,
     57 CMC0_CROSS_COUPLED_MEMORYDMA_CH0_DONE=160,
     58 CMC0_CROSS_COUPLED_MEMORYDMA_CH1_DONE=161,
     59 CMC0_SBUSDMA_CH0_DONE=162,
     60 CMC0_SBUSDMA_CH1_DONE=163,
     61 CMC0_SBUSDMA_CH2_DONE=164,
     62 CMC0_SBUSDMA_CH3_DONE=165,
     63 CMC0_DOUBLE_BIT_ECCERR=166,
     64 CMC0_SINGLE_BIT_ECCERR=167,
     65 CMC1_CH0_DESC_DONE=176,
     66 CMC1_CH0_CHAIN_DONE=177,
     67 CMC1_CH0_INTR_COALESCING_INTR=178,
     68 CMC1_CH0_DESC_CONTROLLED_INTR=179,
     69 CMC1_CH1_DESC_DONE=180,
     70 CMC1_CH1_CHAIN_DONE=181,
     71 CMC1_CH1_INTR_COALESCING_INTR=182,
     72 CMC1_CH1_DESC_CONTROLLED_INTR=183,
     73 CMC1_CH2_DESC_DONE=184,
     74 CMC1_CH2_CHAIN_DONE=185,
     75 CMC1_CH2_INTR_COALESCING_INTR=186,
     76 CMC1_CH2_DESC_CONTROLLED_INTR=187,
     77 CMC1_CH3_DESC_DONE=188,
     78 CMC1_CH3_CHAIN_DONE=189,
     79 CMC1_CH3_INTR_COALESCING_INTR=190,
     80 CMC1_CH3_DESC_CONTROLLED_INTR=191,
     81 CMC1_CH4_DESC_DONE=192,
     82 CMC1_CH4_CHAIN_DONE=193,
     83 CMC1_CH4_INTR_COALESCING_INTR=194,
     84 CMC1_CH4_DESC_CONTROLLED_INTR=195,
     85 CMC1_CH5_DESC_DONE=196,
     86 CMC1_CH5_CHAIN_DONE=197,
     87 CMC1_CH5_INTR_COALESCING_INTR=198,
     88 CMC1_CH5_DESC_CONTROLLED_INTR=199,
     89 CMC1_CH6_DESC_DONE=200,
     90 CMC1_CH6_CHAIN_DONE=201,
     91 CMC1_CH6_INTR_COALESCING_INTR=202,
     92 CMC1_CH6_DESC_CONTROLLED_INTR=203,
     93 CMC1_CH7_DESC_DONE=204,
     94 CMC1_CH7_CHAIN_DONE=205,
     95 CMC1_CH7_INTR_COALESCING_INTR=206,
     96 CMC1_CH7_DESC_CONTROLLED_INTR=207,
     97 CMC1_CROSS_COUPLED_MEMORYDMA_CH0_DONE=208,
     98 CMC1_CROSS_COUPLED_MEMORYDMA_CH1_DONE=209,
     99 CMC1_SBUSDMA_CH0_DONE=210,
    100 CMC1_SBUSDMA_CH1_DONE=211,
    101 CMC1_SBUSDMA_CH2_DONE=212,
    102 CMC1_SBUSDMA_CH3_DONE=213,
    103 CMC1_DOUBLE_BIT_ECCERR=214,
    104 CMC1_SINGLE_BIT_ECCERR=215,
    105 FIFO_CH0_DMA_INTR=224,
    106 FIFO_CH1_DMA_INTR=225,
    107 FIFO_CH2_DMA_INTR=226,
    108 FIFO_CH3_DMA_INTR=227,
    109 FIFO_CH4_DMA_INTR=228,
    110 FIFO_CH5_DMA_INTR=229,
    111 FIFO_CH6_DMA_INTR=230,
    112 FIFO_CH7_DMA_INTR=231,
    113 FIFO_CH8_DMA_INTR=232,
    114 FIFO_CH9_DMA_INTR=233,
    115 FIFO_CH10_DMA_INTR=234,
    116 FIFO_CH11_DMA_INTR=235,
    117 SCHAN_CH0_OP_DONE=236,
    118 SCHAN_CH1_OP_DONE=237,
    119 SCHAN_CH2_OP_DONE=238,
    120 SCHAN_CH3_OP_DONE=239,
    121 SCHAN_CH4_OP_DONE=240,
    122 SCHAN_FIFO_CH0_DONE=241,
    123 SCHAN_FIFO_CH1_DONE=242,
    124 COMMON_POOL_2BIT_ECCERR=243,
    125 COMMON_POOL_1BIT_ECCERR=244,
    126 RPE_1BIT_ECCERR=248,
    127 RPE_2BIT_ECCERR=249,
    128 RPE_SCHAN_SBUSDMA_PKT_DROP=250,
    129 RPE_PIO_MEMDMA_PKT_DROP=251,
    130 RESERVED=255,
    131 CMIC_INTERRUPT_NUM_MAX
    132 } cmic_intr_num_type_t;