cmicx.h (263783B)
1 /* 2 * DO NOT EDIT THIS FILE! 3 * This file is auto-generated from the registers file. 4 * Edits to this file will be lost when it is regenerated. 5 * 6 * 7 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 8 * 9 * Copyright 2007-2020 Broadcom Inc. All rights reserved. 10 * 11 * File: cmicx.h 12 * Purpose: CMICX registers include file. 13 * Supports: bcm88790_a0 14 * bcm88690_a0 15 * bcm88690_b0 16 * bcm56870_a0 17 * bcm56980_a0 18 * bcm56980_b0 19 * bcm56370_a0 20 * bcm56770_a0 21 */ 22 23 /* This array is sorted on address. Don't modify */ 24 #define CMICX_REG_INIT { \ 25 { 0x00000000, "CMIC_TOP_SBUS_TIMEOUT", CMIC_TOP_SBUS_TIMEOUTr }, \ 26 { 0x00000004, "CMIC_TOP_EP_TO_CPU_HEADER_SIZE", CMIC_TOP_EP_TO_CPU_HEADER_SIZEr }, \ 27 { 0x00000008, "CMIC_TOP_CONFIG", CMIC_TOP_CONFIGr }, \ 28 { 0x0000000c, "CMIC_TOP_SBUS_RING_MAP_0_7", CMIC_TOP_SBUS_RING_MAP_0_7r }, \ 29 { 0x00000010, "CMIC_TOP_SBUS_RING_MAP_8_15", CMIC_TOP_SBUS_RING_MAP_8_15r }, \ 30 { 0x00000014, "CMIC_TOP_SBUS_RING_MAP_16_23", CMIC_TOP_SBUS_RING_MAP_16_23r }, \ 31 { 0x00000018, "CMIC_TOP_SBUS_RING_MAP_24_31", CMIC_TOP_SBUS_RING_MAP_24_31r }, \ 32 { 0x0000001c, "CMIC_TOP_SBUS_RING_MAP_32_39", CMIC_TOP_SBUS_RING_MAP_32_39r }, \ 33 { 0x00000020, "CMIC_TOP_SBUS_RING_MAP_40_47", CMIC_TOP_SBUS_RING_MAP_40_47r }, \ 34 { 0x00000024, "CMIC_TOP_SBUS_RING_MAP_48_55", CMIC_TOP_SBUS_RING_MAP_48_55r }, \ 35 { 0x00000028, "CMIC_TOP_SBUS_RING_MAP_56_63", CMIC_TOP_SBUS_RING_MAP_56_63r }, \ 36 { 0x0000002c, "CMIC_TOP_SBUS_RING_MAP_64_71", CMIC_TOP_SBUS_RING_MAP_64_71r }, \ 37 { 0x00000030, "CMIC_TOP_SBUS_RING_MAP_72_79", CMIC_TOP_SBUS_RING_MAP_72_79r }, \ 38 { 0x00000034, "CMIC_TOP_SBUS_RING_MAP_80_87", CMIC_TOP_SBUS_RING_MAP_80_87r }, \ 39 { 0x00000038, "CMIC_TOP_SBUS_RING_MAP_88_95", CMIC_TOP_SBUS_RING_MAP_88_95r }, \ 40 { 0x0000003c, "CMIC_TOP_SBUS_RING_MAP_96_103", CMIC_TOP_SBUS_RING_MAP_96_103r }, \ 41 { 0x00000040, "CMIC_TOP_SBUS_RING_MAP_104_111", CMIC_TOP_SBUS_RING_MAP_104_111r }, \ 42 { 0x00000044, "CMIC_TOP_SBUS_RING_MAP_112_119", CMIC_TOP_SBUS_RING_MAP_112_119r }, \ 43 { 0x00000048, "CMIC_TOP_SBUS_RING_MAP_120_127", CMIC_TOP_SBUS_RING_MAP_120_127r }, \ 44 { 0x0000004c, "CMIC_TOP_SBUS_RING_ARB_CTRL_SBUSDMA", CMIC_TOP_SBUS_RING_ARB_CTRL_SBUSDMAr }, \ 45 { 0x00000050, "CMIC_TOP_SBUS_RING_ARB_CTRL_SCHAN", CMIC_TOP_SBUS_RING_ARB_CTRL_SCHANr }, \ 46 { 0x00000054, "CMIC_TOP_SBUS_RING_ARB_CTRL_FIFODMA", CMIC_TOP_SBUS_RING_ARB_CTRL_FIFODMAr }, \ 47 { 0x00000058, "CMIC_TOP_SBUS_RING_ARB_CTRL_FIFODMA_1", CMIC_TOP_SBUS_RING_ARB_CTRL_FIFODMA_1r }, \ 48 { 0x0000005c, "CMIC_TOP_SBUS_RING_ARB_CTRL_RPE_SCHAN", CMIC_TOP_SBUS_RING_ARB_CTRL_RPE_SCHANr }, \ 49 { 0x00000060, "CMIC_TOP_IPINTF_WRR_ARB_CTRL", CMIC_TOP_IPINTF_WRR_ARB_CTRLr }, \ 50 { 0x00000064, "CMIC_TOP_IPINTF_BUF_DEPTH", CMIC_TOP_IPINTF_BUF_DEPTHr }, \ 51 { 0x00000068, "CMIC_TOP_IPINTF_INTERFACE_CREDITS", CMIC_TOP_IPINTF_INTERFACE_CREDITSr }, \ 52 { 0x0000006c, "CMIC_TOP_EPINTF_RELEASE_ALL_CREDITS", CMIC_TOP_EPINTF_RELEASE_ALL_CREDITSr }, \ 53 { 0x00000070, "CMIC_TOP_EPINTF_MAX_INTERFACE_CREDITS", CMIC_TOP_EPINTF_MAX_INTERFACE_CREDITSr }, \ 54 { 0x00000074, "CMIC_TOP_EPINTF_BUF_DEPTH", CMIC_TOP_EPINTF_BUF_DEPTHr }, \ 55 { 0x00000078, "CMIC_TOP_PKT_COUNT_RXPKT", CMIC_TOP_PKT_COUNT_RXPKTr }, \ 56 { 0x0000007c, "CMIC_TOP_PKT_COUNT_RXPKT_ERR", CMIC_TOP_PKT_COUNT_RXPKT_ERRr }, \ 57 { 0x00000080, "CMIC_TOP_PKT_COUNT_RXPKT_DROP", CMIC_TOP_PKT_COUNT_RXPKT_DROPr }, \ 58 { 0x00000084, "CMIC_TOP_PKT_COUNT_TXPKT", CMIC_TOP_PKT_COUNT_TXPKTr }, \ 59 { 0x00000088, "CMIC_TOP_PKT_COUNT_TXPKT_ERR", CMIC_TOP_PKT_COUNT_TXPKT_ERRr }, \ 60 { 0x0000008c, "CMIC_TOP_TO_MMU_COS_MASK_LSB_BITS", CMIC_TOP_TO_MMU_COS_MASK_LSB_BITSr }, \ 61 { 0x00000090, "CMIC_TOP_TO_MMU_COS_MASK_MSB_BITS", CMIC_TOP_TO_MMU_COS_MASK_MSB_BITSr }, \ 62 { 0x00000094, "CMIC_TOP_STATISTICS_COUNTER_CONTROL", CMIC_TOP_STATISTICS_COUNTER_CONTROLr }, \ 63 { 0x00000098, "CMIC_TOP_STATISTICS_COUNTER_STATUS", CMIC_TOP_STATISTICS_COUNTER_STATUSr }, \ 64 { 0x0000009c, "CMIC_TOP_STATISTICS_EP_PKT_COUNT", CMIC_TOP_STATISTICS_EP_PKT_COUNTr }, \ 65 { 0x000000a0, "CMIC_TOP_STATISTICS_IP_PKT_COUNT", CMIC_TOP_STATISTICS_IP_PKT_COUNTr }, \ 66 { 0x000000a4, "CMIC_TOP_STATISTICS_EP_BYTE_COUNT_LO", CMIC_TOP_STATISTICS_EP_BYTE_COUNT_LOr }, \ 67 { 0x000000a8, "CMIC_TOP_STATISTICS_IP_BYTE_COUNT_LO", CMIC_TOP_STATISTICS_IP_BYTE_COUNT_LOr }, \ 68 { 0x000000ac, "CMIC_TOP_STATISTICS_EP_BYTE_COUNT_HI", CMIC_TOP_STATISTICS_EP_BYTE_COUNT_HIr }, \ 69 { 0x000000b0, "CMIC_TOP_STATISTICS_IP_BYTE_COUNT_HI", CMIC_TOP_STATISTICS_IP_BYTE_COUNT_HIr }, \ 70 { 0x00001000, "CMIC_CMC0_SHARED_DMA_MASTER_TOTAL_OUTSTD_TRANS_LIMIT", CMIC_CMC0_SHARED_DMA_MASTER_TOTAL_OUTSTD_TRANS_LIMITr }, \ 71 { 0x00001004, "CMIC_CMC0_SHARED_DMA_MASTER_READ_PER_ID_OUTSTD_TRANS_LIMIT", CMIC_CMC0_SHARED_DMA_MASTER_READ_PER_ID_OUTSTD_TRANS_LIMITr }, \ 72 { 0x00001008, "CMIC_CMC0_SHARED_PACKET_DMA_READ_AXI_MAP_CTRL", CMIC_CMC0_SHARED_PACKET_DMA_READ_AXI_MAP_CTRLr }, \ 73 { 0x0000100c, "CMIC_CMC0_SHARED_PACKET_DMA_WRITE_AXI_MAP_CTRL0", CMIC_CMC0_SHARED_PACKET_DMA_WRITE_AXI_MAP_CTRL0r }, \ 74 { 0x00001010, "CMIC_CMC0_SHARED_PACKET_DMA_WRITE_AXI_MAP_CTRL1", CMIC_CMC0_SHARED_PACKET_DMA_WRITE_AXI_MAP_CTRL1r }, \ 75 { 0x00001014, "CMIC_CMC0_SHARED_PACKET_DMA_READ_ARB_CTRL", CMIC_CMC0_SHARED_PACKET_DMA_READ_ARB_CTRLr }, \ 76 { 0x00001018, "CMIC_CMC0_SHARED_PACKET_DMA_WRITE_ARB_CTRL", CMIC_CMC0_SHARED_PACKET_DMA_WRITE_ARB_CTRLr }, \ 77 { 0x0000101c, "CMIC_CMC0_SHARED_SBUS_DMA_READ_AXI_MAP_CTRL", CMIC_CMC0_SHARED_SBUS_DMA_READ_AXI_MAP_CTRLr }, \ 78 { 0x00001020, "CMIC_CMC0_SHARED_SBUS_DMA_WRITE_AXI_MAP_CTRL", CMIC_CMC0_SHARED_SBUS_DMA_WRITE_AXI_MAP_CTRLr }, \ 79 { 0x00001024, "CMIC_CMC0_SHARED_SBUS_DMA_READ_ARB_CTRL", CMIC_CMC0_SHARED_SBUS_DMA_READ_ARB_CTRLr }, \ 80 { 0x00001028, "CMIC_CMC0_SHARED_SBUS_DMA_WRITE_ARB_CTRL", CMIC_CMC0_SHARED_SBUS_DMA_WRITE_ARB_CTRLr }, \ 81 { 0x0000102c, "CMIC_CMC0_SHARED_CCMDMA_READ_AXI_MAP_CTRL", CMIC_CMC0_SHARED_CCMDMA_READ_AXI_MAP_CTRLr }, \ 82 { 0x00001030, "CMIC_CMC0_SHARED_CCMDMA_WRITE_AXI_MAP_CTRL", CMIC_CMC0_SHARED_CCMDMA_WRITE_AXI_MAP_CTRLr }, \ 83 { 0x00001034, "CMIC_CMC0_SHARED_CCMDMA_READ_ARB_CTRL", CMIC_CMC0_SHARED_CCMDMA_READ_ARB_CTRLr }, \ 84 { 0x00001038, "CMIC_CMC0_SHARED_CCMDMA_WRITE_ARB_CTRL", CMIC_CMC0_SHARED_CCMDMA_WRITE_ARB_CTRLr }, \ 85 { 0x0000103c, "CMIC_CMC0_SHARED_COMPLETION_BUF_MAX_FLIST_ENTRIES", CMIC_CMC0_SHARED_COMPLETION_BUF_MAX_FLIST_ENTRIESr }, \ 86 { 0x00001040, "CMIC_CMC0_SHARED_COMPLETION_BUF_STATUS_NUM_FREE_ENTRIES", CMIC_CMC0_SHARED_COMPLETION_BUF_STATUS_NUM_FREE_ENTRIESr }, \ 87 { 0x00001044, "CMIC_CMC0_SHARED_COMPLETION_BUF_ECC_STATUS", CMIC_CMC0_SHARED_COMPLETION_BUF_ECC_STATUSr }, \ 88 { 0x00001048, "CMIC_CMC0_SHARED_COMPLETION_BUF_ECC_CONTROL", CMIC_CMC0_SHARED_COMPLETION_BUF_ECC_CONTROLr }, \ 89 { 0x0000104c, "CMIC_CMC0_SHARED_COMPLETION_BUF_TM_CONTROL", CMIC_CMC0_SHARED_COMPLETION_BUF_TM_CONTROLr }, \ 90 { 0x00001050, "CMIC_CMC0_SHARED_PROGRAMMABLE_COS_MASK0", CMIC_CMC0_SHARED_PROGRAMMABLE_COS_MASK0r }, \ 91 { 0x00001054, "CMIC_CMC0_SHARED_PROGRAMMABLE_COS_MASK1", CMIC_CMC0_SHARED_PROGRAMMABLE_COS_MASK1r }, \ 92 { 0x00001058, "CMIC_CMC0_SHARED_RXBUF_THRESHOLD_CONFIG", CMIC_CMC0_SHARED_RXBUF_THRESHOLD_CONFIGr }, \ 93 { 0x0000105c, "CMIC_CMC0_SHARED_2BIT_ECC_ERROR_STATUS", CMIC_CMC0_SHARED_2BIT_ECC_ERROR_STATUSr }, \ 94 { 0x00001060, "CMIC_CMC0_SHARED_2BIT_ECC_ERROR_STATUS_ENABLE", CMIC_CMC0_SHARED_2BIT_ECC_ERROR_STATUS_ENABLEr }, \ 95 { 0x00001064, "CMIC_CMC0_SHARED_1BIT_ECC_ERROR_STATUS", CMIC_CMC0_SHARED_1BIT_ECC_ERROR_STATUSr }, \ 96 { 0x00001068, "CMIC_CMC0_SHARED_1BIT_ECC_ERROR_STATUS_ENABLE", CMIC_CMC0_SHARED_1BIT_ECC_ERROR_STATUS_ENABLEr }, \ 97 { 0x0000106c, "CMIC_CMC0_SHARED_IRQ_STAT0", CMIC_CMC0_SHARED_IRQ_STAT0r }, \ 98 { 0x00001070, "CMIC_CMC0_SHARED_IRQ_STAT1", CMIC_CMC0_SHARED_IRQ_STAT1r }, \ 99 { 0x00001074, "CMIC_CMC0_SHARED_IRQ_STAT_CLR0", CMIC_CMC0_SHARED_IRQ_STAT_CLR0r }, \ 100 { 0x00001078, "CMIC_CMC0_SHARED_CONFIG", CMIC_CMC0_SHARED_CONFIGr }, \ 101 { 0x0000107c, "CMIC_CMC0_SHARED_AXI_STAT", CMIC_CMC0_SHARED_AXI_STATr }, \ 102 { 0x00001080, "CMIC_CMC0_SHARED_AXI_PER_ID_STAT", CMIC_CMC0_SHARED_AXI_PER_ID_STATr }, \ 103 { 0x00001084, "CMIC_CMC0_SHARED_PKT_COUNT_RXPKT", CMIC_CMC0_SHARED_PKT_COUNT_RXPKTr }, \ 104 { 0x00001088, "CMIC_CMC0_SHARED_PKT_COUNT_RXPKT_ERR", CMIC_CMC0_SHARED_PKT_COUNT_RXPKT_ERRr }, \ 105 { 0x0000108c, "CMIC_CMC0_SHARED_PKT_COUNT_TXPKT", CMIC_CMC0_SHARED_PKT_COUNT_TXPKTr }, \ 106 { 0x00001090, "CMIC_CMC0_SHARED_PKT_COUNT_TXPKT_ERR", CMIC_CMC0_SHARED_PKT_COUNT_TXPKT_ERRr }, \ 107 { 0x00001094, "CMIC_CMC0_SHARED_AXI_AR_COUNT_TX", CMIC_CMC0_SHARED_AXI_AR_COUNT_TXr }, \ 108 { 0x00001098, "CMIC_CMC0_SHARED_AXI_AR_COUNT_SPLIT_TX", CMIC_CMC0_SHARED_AXI_AR_COUNT_SPLIT_TXr }, \ 109 { 0x00002000, "CMIC_CMC0_SHARED_TXBUF_MAX_BUF_LIMITS", CMIC_CMC0_SHARED_TXBUF_MAX_BUF_LIMITSr }, \ 110 { 0x00002004, "CMIC_CMC0_SHARED_TXBUF_MIN_BUF_LIMITS", CMIC_CMC0_SHARED_TXBUF_MIN_BUF_LIMITSr }, \ 111 { 0x00002008, "CMIC_CMC0_SHARED_TXBUF_RD_THRESHOLD_CONFIG", CMIC_CMC0_SHARED_TXBUF_RD_THRESHOLD_CONFIGr }, \ 112 { 0x0000200c, "CMIC_CMC0_SHARED_TXBUF_RD_WRR_ARB_CTRL", CMIC_CMC0_SHARED_TXBUF_RD_WRR_ARB_CTRLr }, \ 113 { 0x00002010, "CMIC_CMC0_SHARED_TXBUF_SLICE3_PKT_CNT", CMIC_CMC0_SHARED_TXBUF_SLICE3_PKT_CNTr }, \ 114 { 0x00002014, "CMIC_CMC0_SHARED_TXBUF_SLICE2_PKT_CNT", CMIC_CMC0_SHARED_TXBUF_SLICE2_PKT_CNTr }, \ 115 { 0x00002018, "CMIC_CMC0_SHARED_TXBUF_SLICE1_PKT_CNT", CMIC_CMC0_SHARED_TXBUF_SLICE1_PKT_CNTr }, \ 116 { 0x0000201c, "CMIC_CMC0_SHARED_TXBUF_SLICE0_PKT_CNT", CMIC_CMC0_SHARED_TXBUF_SLICE0_PKT_CNTr }, \ 117 { 0x00002020, "CMIC_CMC0_SHARED_TXBUF_DEBUG", CMIC_CMC0_SHARED_TXBUF_DEBUGr }, \ 118 { 0x00002024, "CMIC_CMC0_SHARED_TXBUF_DATABUF_NUM_FREE_ENTRIES", CMIC_CMC0_SHARED_TXBUF_DATABUF_NUM_FREE_ENTRIESr }, \ 119 { 0x00002028, "CMIC_CMC0_SHARED_TXBUF_DATABUF_MAX_FLIST_ENTRIES", CMIC_CMC0_SHARED_TXBUF_DATABUF_MAX_FLIST_ENTRIESr }, \ 120 { 0x0000202c, "CMIC_CMC0_SHARED_TXBUF_ECC_STATUS", CMIC_CMC0_SHARED_TXBUF_ECC_STATUSr }, \ 121 { 0x00002030, "CMIC_CMC0_SHARED_TXBUF_ECC_STATUS_CLR", CMIC_CMC0_SHARED_TXBUF_ECC_STATUS_CLRr }, \ 122 { 0x00002034, "CMIC_CMC0_SHARED_TXBUF_ECC_CONTROL", CMIC_CMC0_SHARED_TXBUF_ECC_CONTROLr }, \ 123 { 0x00002038, "CMIC_CMC0_SHARED_TXBUF_TM_CONTROL", CMIC_CMC0_SHARED_TXBUF_TM_CONTROLr }, \ 124 { 0x00002080, "CMIC_CMC0_SHARED_RXBUF_DATABUF_MAX_FLIST_ENTRIES", CMIC_CMC0_SHARED_RXBUF_DATABUF_MAX_FLIST_ENTRIESr }, \ 125 { 0x00002084, "CMIC_CMC0_SHARED_RXBUF_DATABUF_NUM_FREE_ENTRIES", CMIC_CMC0_SHARED_RXBUF_DATABUF_NUM_FREE_ENTRIESr }, \ 126 { 0x00002088, "CMIC_CMC0_SHARED_RXBUF_BLOCK_DATABUF_ALLOC", CMIC_CMC0_SHARED_RXBUF_BLOCK_DATABUF_ALLOCr }, \ 127 { 0x0000208c, "CMIC_CMC0_SHARED_RXBUF_CONFIG", CMIC_CMC0_SHARED_RXBUF_CONFIGr }, \ 128 { 0x00002090, "CMIC_CMC0_SHARED_RXBUF_ECC_CONTROL", CMIC_CMC0_SHARED_RXBUF_ECC_CONTROLr }, \ 129 { 0x00002094, "CMIC_CMC0_SHARED_RXBUF_TM_CONTROL", CMIC_CMC0_SHARED_RXBUF_TM_CONTROLr }, \ 130 { 0x00002098, "CMIC_CMC0_SHARED_RXBUF_ECC_STATUS", CMIC_CMC0_SHARED_RXBUF_ECC_STATUSr }, \ 131 { 0x0000209c, "CMIC_CMC0_SHARED_RXBUF_ECC_STATUS_CLR", CMIC_CMC0_SHARED_RXBUF_ECC_STATUS_CLRr }, \ 132 { 0x00002100, "CMIC_CMC0_PKTDMA_CH0_CTRL", CMIC_CMC0_PKTDMA_CH0_CTRLr }, \ 133 { 0x00002104, "CMIC_CMC0_PKTDMA_CH0_DESC_ADDR_LO", CMIC_CMC0_PKTDMA_CH0_DESC_ADDR_LOr }, \ 134 { 0x00002108, "CMIC_CMC0_PKTDMA_CH0_DESC_ADDR_HI", CMIC_CMC0_PKTDMA_CH0_DESC_ADDR_HIr }, \ 135 { 0x0000210c, "CMIC_CMC0_PKTDMA_CH0_DESC_HALT_ADDR_LO", CMIC_CMC0_PKTDMA_CH0_DESC_HALT_ADDR_LOr }, \ 136 { 0x00002110, "CMIC_CMC0_PKTDMA_CH0_DESC_HALT_ADDR_HI", CMIC_CMC0_PKTDMA_CH0_DESC_HALT_ADDR_HIr }, \ 137 { 0x00002114, "CMIC_CMC0_PKTDMA_CH0_STAT", CMIC_CMC0_PKTDMA_CH0_STATr }, \ 138 { 0x00002118, "CMIC_CMC0_PKTDMA_CH0_COS_CTRL_RX_0", CMIC_CMC0_PKTDMA_CH0_COS_CTRL_RX_0r }, \ 139 { 0x0000211c, "CMIC_CMC0_PKTDMA_CH0_COS_CTRL_RX_1", CMIC_CMC0_PKTDMA_CH0_COS_CTRL_RX_1r }, \ 140 { 0x00002120, "CMIC_CMC0_PKTDMA_CH0_INTR_COAL", CMIC_CMC0_PKTDMA_CH0_INTR_COALr }, \ 141 { 0x00002124, "CMIC_CMC0_PKTDMA_CH0_CURR_DESC_LO", CMIC_CMC0_PKTDMA_CH0_CURR_DESC_LOr }, \ 142 { 0x00002128, "CMIC_CMC0_PKTDMA_CH0_CURR_DESC_HI", CMIC_CMC0_PKTDMA_CH0_CURR_DESC_HIr }, \ 143 { 0x0000212c, "CMIC_CMC0_PKTDMA_CH0_RXBUF_THRESHOLD_CONFIG", CMIC_CMC0_PKTDMA_CH0_RXBUF_THRESHOLD_CONFIGr }, \ 144 { 0x00002130, "CMIC_CMC0_PKTDMA_CH0_DEBUG_CONTROL", CMIC_CMC0_PKTDMA_CH0_DEBUG_CONTROLr }, \ 145 { 0x00002134, "CMIC_CMC0_PKTDMA_CH0_DEBUG_SM_STATUS", CMIC_CMC0_PKTDMA_CH0_DEBUG_SM_STATUSr }, \ 146 { 0x00002138, "CMIC_CMC0_PKTDMA_CH0_DEBUG_STATUS", CMIC_CMC0_PKTDMA_CH0_DEBUG_STATUSr }, \ 147 { 0x0000213c, "CMIC_CMC0_PKTDMA_CH0_PKT_COUNT_RXPKT", CMIC_CMC0_PKTDMA_CH0_PKT_COUNT_RXPKTr }, \ 148 { 0x00002140, "CMIC_CMC0_PKTDMA_CH0_PKT_COUNT_TXPKT", CMIC_CMC0_PKTDMA_CH0_PKT_COUNT_TXPKTr }, \ 149 { 0x00002144, "CMIC_CMC0_PKTDMA_CH0_PKT_COUNT_RXPKT_DROP", CMIC_CMC0_PKTDMA_CH0_PKT_COUNT_RXPKT_DROPr }, \ 150 { 0x00002148, "CMIC_CMC0_PKTDMA_CH0_DESC_COUNT_REQ", CMIC_CMC0_PKTDMA_CH0_DESC_COUNT_REQr }, \ 151 { 0x0000214c, "CMIC_CMC0_PKTDMA_CH0_DESC_COUNT_RX", CMIC_CMC0_PKTDMA_CH0_DESC_COUNT_RXr }, \ 152 { 0x00002150, "CMIC_CMC0_PKTDMA_CH0_DESC_COUNT_STATUS_WR", CMIC_CMC0_PKTDMA_CH0_DESC_COUNT_STATUS_WRr }, \ 153 { 0x00002154, "CMIC_CMC0_PKTDMA_CH0_DESC_MEM_ECC_STATUS", CMIC_CMC0_PKTDMA_CH0_DESC_MEM_ECC_STATUSr }, \ 154 { 0x00002158, "CMIC_CMC0_PKTDMA_CH0_DESC_MEM_ECC_CONTROL", CMIC_CMC0_PKTDMA_CH0_DESC_MEM_ECC_CONTROLr }, \ 155 { 0x0000215c, "CMIC_CMC0_PKTDMA_CH0_DESC_MEM_TM_CONTROL", CMIC_CMC0_PKTDMA_CH0_DESC_MEM_TM_CONTROLr }, \ 156 { 0x00002180, "CMIC_CMC0_PKTDMA_CH1_CTRL", CMIC_CMC0_PKTDMA_CH1_CTRLr }, \ 157 { 0x00002184, "CMIC_CMC0_PKTDMA_CH1_DESC_ADDR_LO", CMIC_CMC0_PKTDMA_CH1_DESC_ADDR_LOr }, \ 158 { 0x00002188, "CMIC_CMC0_PKTDMA_CH1_DESC_ADDR_HI", CMIC_CMC0_PKTDMA_CH1_DESC_ADDR_HIr }, \ 159 { 0x0000218c, "CMIC_CMC0_PKTDMA_CH1_DESC_HALT_ADDR_LO", CMIC_CMC0_PKTDMA_CH1_DESC_HALT_ADDR_LOr }, \ 160 { 0x00002190, "CMIC_CMC0_PKTDMA_CH1_DESC_HALT_ADDR_HI", CMIC_CMC0_PKTDMA_CH1_DESC_HALT_ADDR_HIr }, \ 161 { 0x00002194, "CMIC_CMC0_PKTDMA_CH1_STAT", CMIC_CMC0_PKTDMA_CH1_STATr }, \ 162 { 0x00002198, "CMIC_CMC0_PKTDMA_CH1_COS_CTRL_RX_0", CMIC_CMC0_PKTDMA_CH1_COS_CTRL_RX_0r }, \ 163 { 0x0000219c, "CMIC_CMC0_PKTDMA_CH1_COS_CTRL_RX_1", CMIC_CMC0_PKTDMA_CH1_COS_CTRL_RX_1r }, \ 164 { 0x000021a0, "CMIC_CMC0_PKTDMA_CH1_INTR_COAL", CMIC_CMC0_PKTDMA_CH1_INTR_COALr }, \ 165 { 0x000021a4, "CMIC_CMC0_PKTDMA_CH1_CURR_DESC_LO", CMIC_CMC0_PKTDMA_CH1_CURR_DESC_LOr }, \ 166 { 0x000021a8, "CMIC_CMC0_PKTDMA_CH1_CURR_DESC_HI", CMIC_CMC0_PKTDMA_CH1_CURR_DESC_HIr }, \ 167 { 0x000021ac, "CMIC_CMC0_PKTDMA_CH1_RXBUF_THRESHOLD_CONFIG", CMIC_CMC0_PKTDMA_CH1_RXBUF_THRESHOLD_CONFIGr }, \ 168 { 0x000021b0, "CMIC_CMC0_PKTDMA_CH1_DEBUG_CONTROL", CMIC_CMC0_PKTDMA_CH1_DEBUG_CONTROLr }, \ 169 { 0x000021b4, "CMIC_CMC0_PKTDMA_CH1_DEBUG_SM_STATUS", CMIC_CMC0_PKTDMA_CH1_DEBUG_SM_STATUSr }, \ 170 { 0x000021b8, "CMIC_CMC0_PKTDMA_CH1_DEBUG_STATUS", CMIC_CMC0_PKTDMA_CH1_DEBUG_STATUSr }, \ 171 { 0x000021bc, "CMIC_CMC0_PKTDMA_CH1_PKT_COUNT_RXPKT", CMIC_CMC0_PKTDMA_CH1_PKT_COUNT_RXPKTr }, \ 172 { 0x000021c0, "CMIC_CMC0_PKTDMA_CH1_PKT_COUNT_TXPKT", CMIC_CMC0_PKTDMA_CH1_PKT_COUNT_TXPKTr }, \ 173 { 0x000021c4, "CMIC_CMC0_PKTDMA_CH1_PKT_COUNT_RXPKT_DROP", CMIC_CMC0_PKTDMA_CH1_PKT_COUNT_RXPKT_DROPr }, \ 174 { 0x000021c8, "CMIC_CMC0_PKTDMA_CH1_DESC_COUNT_REQ", CMIC_CMC0_PKTDMA_CH1_DESC_COUNT_REQr }, \ 175 { 0x000021cc, "CMIC_CMC0_PKTDMA_CH1_DESC_COUNT_RX", CMIC_CMC0_PKTDMA_CH1_DESC_COUNT_RXr }, \ 176 { 0x000021d0, "CMIC_CMC0_PKTDMA_CH1_DESC_COUNT_STATUS_WR", CMIC_CMC0_PKTDMA_CH1_DESC_COUNT_STATUS_WRr }, \ 177 { 0x000021d4, "CMIC_CMC0_PKTDMA_CH1_DESC_MEM_ECC_STATUS", CMIC_CMC0_PKTDMA_CH1_DESC_MEM_ECC_STATUSr }, \ 178 { 0x000021d8, "CMIC_CMC0_PKTDMA_CH1_DESC_MEM_ECC_CONTROL", CMIC_CMC0_PKTDMA_CH1_DESC_MEM_ECC_CONTROLr }, \ 179 { 0x000021dc, "CMIC_CMC0_PKTDMA_CH1_DESC_MEM_TM_CONTROL", CMIC_CMC0_PKTDMA_CH1_DESC_MEM_TM_CONTROLr }, \ 180 { 0x00002200, "CMIC_CMC0_PKTDMA_CH2_CTRL", CMIC_CMC0_PKTDMA_CH2_CTRLr }, \ 181 { 0x00002204, "CMIC_CMC0_PKTDMA_CH2_DESC_ADDR_LO", CMIC_CMC0_PKTDMA_CH2_DESC_ADDR_LOr }, \ 182 { 0x00002208, "CMIC_CMC0_PKTDMA_CH2_DESC_ADDR_HI", CMIC_CMC0_PKTDMA_CH2_DESC_ADDR_HIr }, \ 183 { 0x0000220c, "CMIC_CMC0_PKTDMA_CH2_DESC_HALT_ADDR_LO", CMIC_CMC0_PKTDMA_CH2_DESC_HALT_ADDR_LOr }, \ 184 { 0x00002210, "CMIC_CMC0_PKTDMA_CH2_DESC_HALT_ADDR_HI", CMIC_CMC0_PKTDMA_CH2_DESC_HALT_ADDR_HIr }, \ 185 { 0x00002214, "CMIC_CMC0_PKTDMA_CH2_STAT", CMIC_CMC0_PKTDMA_CH2_STATr }, \ 186 { 0x00002218, "CMIC_CMC0_PKTDMA_CH2_COS_CTRL_RX_0", CMIC_CMC0_PKTDMA_CH2_COS_CTRL_RX_0r }, \ 187 { 0x0000221c, "CMIC_CMC0_PKTDMA_CH2_COS_CTRL_RX_1", CMIC_CMC0_PKTDMA_CH2_COS_CTRL_RX_1r }, \ 188 { 0x00002220, "CMIC_CMC0_PKTDMA_CH2_INTR_COAL", CMIC_CMC0_PKTDMA_CH2_INTR_COALr }, \ 189 { 0x00002224, "CMIC_CMC0_PKTDMA_CH2_CURR_DESC_LO", CMIC_CMC0_PKTDMA_CH2_CURR_DESC_LOr }, \ 190 { 0x00002228, "CMIC_CMC0_PKTDMA_CH2_CURR_DESC_HI", CMIC_CMC0_PKTDMA_CH2_CURR_DESC_HIr }, \ 191 { 0x0000222c, "CMIC_CMC0_PKTDMA_CH2_RXBUF_THRESHOLD_CONFIG", CMIC_CMC0_PKTDMA_CH2_RXBUF_THRESHOLD_CONFIGr }, \ 192 { 0x00002230, "CMIC_CMC0_PKTDMA_CH2_DEBUG_CONTROL", CMIC_CMC0_PKTDMA_CH2_DEBUG_CONTROLr }, \ 193 { 0x00002234, "CMIC_CMC0_PKTDMA_CH2_DEBUG_SM_STATUS", CMIC_CMC0_PKTDMA_CH2_DEBUG_SM_STATUSr }, \ 194 { 0x00002238, "CMIC_CMC0_PKTDMA_CH2_DEBUG_STATUS", CMIC_CMC0_PKTDMA_CH2_DEBUG_STATUSr }, \ 195 { 0x0000223c, "CMIC_CMC0_PKTDMA_CH2_PKT_COUNT_RXPKT", CMIC_CMC0_PKTDMA_CH2_PKT_COUNT_RXPKTr }, \ 196 { 0x00002240, "CMIC_CMC0_PKTDMA_CH2_PKT_COUNT_TXPKT", CMIC_CMC0_PKTDMA_CH2_PKT_COUNT_TXPKTr }, \ 197 { 0x00002244, "CMIC_CMC0_PKTDMA_CH2_PKT_COUNT_RXPKT_DROP", CMIC_CMC0_PKTDMA_CH2_PKT_COUNT_RXPKT_DROPr }, \ 198 { 0x00002248, "CMIC_CMC0_PKTDMA_CH2_DESC_COUNT_REQ", CMIC_CMC0_PKTDMA_CH2_DESC_COUNT_REQr }, \ 199 { 0x0000224c, "CMIC_CMC0_PKTDMA_CH2_DESC_COUNT_RX", CMIC_CMC0_PKTDMA_CH2_DESC_COUNT_RXr }, \ 200 { 0x00002250, "CMIC_CMC0_PKTDMA_CH2_DESC_COUNT_STATUS_WR", CMIC_CMC0_PKTDMA_CH2_DESC_COUNT_STATUS_WRr }, \ 201 { 0x00002254, "CMIC_CMC0_PKTDMA_CH2_DESC_MEM_ECC_STATUS", CMIC_CMC0_PKTDMA_CH2_DESC_MEM_ECC_STATUSr }, \ 202 { 0x00002258, "CMIC_CMC0_PKTDMA_CH2_DESC_MEM_ECC_CONTROL", CMIC_CMC0_PKTDMA_CH2_DESC_MEM_ECC_CONTROLr }, \ 203 { 0x0000225c, "CMIC_CMC0_PKTDMA_CH2_DESC_MEM_TM_CONTROL", CMIC_CMC0_PKTDMA_CH2_DESC_MEM_TM_CONTROLr }, \ 204 { 0x00002280, "CMIC_CMC0_PKTDMA_CH3_CTRL", CMIC_CMC0_PKTDMA_CH3_CTRLr }, \ 205 { 0x00002284, "CMIC_CMC0_PKTDMA_CH3_DESC_ADDR_LO", CMIC_CMC0_PKTDMA_CH3_DESC_ADDR_LOr }, \ 206 { 0x00002288, "CMIC_CMC0_PKTDMA_CH3_DESC_ADDR_HI", CMIC_CMC0_PKTDMA_CH3_DESC_ADDR_HIr }, \ 207 { 0x0000228c, "CMIC_CMC0_PKTDMA_CH3_DESC_HALT_ADDR_LO", CMIC_CMC0_PKTDMA_CH3_DESC_HALT_ADDR_LOr }, \ 208 { 0x00002290, "CMIC_CMC0_PKTDMA_CH3_DESC_HALT_ADDR_HI", CMIC_CMC0_PKTDMA_CH3_DESC_HALT_ADDR_HIr }, \ 209 { 0x00002294, "CMIC_CMC0_PKTDMA_CH3_STAT", CMIC_CMC0_PKTDMA_CH3_STATr }, \ 210 { 0x00002298, "CMIC_CMC0_PKTDMA_CH3_COS_CTRL_RX_0", CMIC_CMC0_PKTDMA_CH3_COS_CTRL_RX_0r }, \ 211 { 0x0000229c, "CMIC_CMC0_PKTDMA_CH3_COS_CTRL_RX_1", CMIC_CMC0_PKTDMA_CH3_COS_CTRL_RX_1r }, \ 212 { 0x000022a0, "CMIC_CMC0_PKTDMA_CH3_INTR_COAL", CMIC_CMC0_PKTDMA_CH3_INTR_COALr }, \ 213 { 0x000022a4, "CMIC_CMC0_PKTDMA_CH3_CURR_DESC_LO", CMIC_CMC0_PKTDMA_CH3_CURR_DESC_LOr }, \ 214 { 0x000022a8, "CMIC_CMC0_PKTDMA_CH3_CURR_DESC_HI", CMIC_CMC0_PKTDMA_CH3_CURR_DESC_HIr }, \ 215 { 0x000022ac, "CMIC_CMC0_PKTDMA_CH3_RXBUF_THRESHOLD_CONFIG", CMIC_CMC0_PKTDMA_CH3_RXBUF_THRESHOLD_CONFIGr }, \ 216 { 0x000022b0, "CMIC_CMC0_PKTDMA_CH3_DEBUG_CONTROL", CMIC_CMC0_PKTDMA_CH3_DEBUG_CONTROLr }, \ 217 { 0x000022b4, "CMIC_CMC0_PKTDMA_CH3_DEBUG_SM_STATUS", CMIC_CMC0_PKTDMA_CH3_DEBUG_SM_STATUSr }, \ 218 { 0x000022b8, "CMIC_CMC0_PKTDMA_CH3_DEBUG_STATUS", CMIC_CMC0_PKTDMA_CH3_DEBUG_STATUSr }, \ 219 { 0x000022bc, "CMIC_CMC0_PKTDMA_CH3_PKT_COUNT_RXPKT", CMIC_CMC0_PKTDMA_CH3_PKT_COUNT_RXPKTr }, \ 220 { 0x000022c0, "CMIC_CMC0_PKTDMA_CH3_PKT_COUNT_TXPKT", CMIC_CMC0_PKTDMA_CH3_PKT_COUNT_TXPKTr }, \ 221 { 0x000022c4, "CMIC_CMC0_PKTDMA_CH3_PKT_COUNT_RXPKT_DROP", CMIC_CMC0_PKTDMA_CH3_PKT_COUNT_RXPKT_DROPr }, \ 222 { 0x000022c8, "CMIC_CMC0_PKTDMA_CH3_DESC_COUNT_REQ", CMIC_CMC0_PKTDMA_CH3_DESC_COUNT_REQr }, \ 223 { 0x000022cc, "CMIC_CMC0_PKTDMA_CH3_DESC_COUNT_RX", CMIC_CMC0_PKTDMA_CH3_DESC_COUNT_RXr }, \ 224 { 0x000022d0, "CMIC_CMC0_PKTDMA_CH3_DESC_COUNT_STATUS_WR", CMIC_CMC0_PKTDMA_CH3_DESC_COUNT_STATUS_WRr }, \ 225 { 0x000022d4, "CMIC_CMC0_PKTDMA_CH3_DESC_MEM_ECC_STATUS", CMIC_CMC0_PKTDMA_CH3_DESC_MEM_ECC_STATUSr }, \ 226 { 0x000022d8, "CMIC_CMC0_PKTDMA_CH3_DESC_MEM_ECC_CONTROL", CMIC_CMC0_PKTDMA_CH3_DESC_MEM_ECC_CONTROLr }, \ 227 { 0x000022dc, "CMIC_CMC0_PKTDMA_CH3_DESC_MEM_TM_CONTROL", CMIC_CMC0_PKTDMA_CH3_DESC_MEM_TM_CONTROLr }, \ 228 { 0x00002300, "CMIC_CMC0_PKTDMA_CH4_CTRL", CMIC_CMC0_PKTDMA_CH4_CTRLr }, \ 229 { 0x00002304, "CMIC_CMC0_PKTDMA_CH4_DESC_ADDR_LO", CMIC_CMC0_PKTDMA_CH4_DESC_ADDR_LOr }, \ 230 { 0x00002308, "CMIC_CMC0_PKTDMA_CH4_DESC_ADDR_HI", CMIC_CMC0_PKTDMA_CH4_DESC_ADDR_HIr }, \ 231 { 0x0000230c, "CMIC_CMC0_PKTDMA_CH4_DESC_HALT_ADDR_LO", CMIC_CMC0_PKTDMA_CH4_DESC_HALT_ADDR_LOr }, \ 232 { 0x00002310, "CMIC_CMC0_PKTDMA_CH4_DESC_HALT_ADDR_HI", CMIC_CMC0_PKTDMA_CH4_DESC_HALT_ADDR_HIr }, \ 233 { 0x00002314, "CMIC_CMC0_PKTDMA_CH4_STAT", CMIC_CMC0_PKTDMA_CH4_STATr }, \ 234 { 0x00002318, "CMIC_CMC0_PKTDMA_CH4_COS_CTRL_RX_0", CMIC_CMC0_PKTDMA_CH4_COS_CTRL_RX_0r }, \ 235 { 0x0000231c, "CMIC_CMC0_PKTDMA_CH4_COS_CTRL_RX_1", CMIC_CMC0_PKTDMA_CH4_COS_CTRL_RX_1r }, \ 236 { 0x00002320, "CMIC_CMC0_PKTDMA_CH4_INTR_COAL", CMIC_CMC0_PKTDMA_CH4_INTR_COALr }, \ 237 { 0x00002324, "CMIC_CMC0_PKTDMA_CH4_CURR_DESC_LO", CMIC_CMC0_PKTDMA_CH4_CURR_DESC_LOr }, \ 238 { 0x00002328, "CMIC_CMC0_PKTDMA_CH4_CURR_DESC_HI", CMIC_CMC0_PKTDMA_CH4_CURR_DESC_HIr }, \ 239 { 0x0000232c, "CMIC_CMC0_PKTDMA_CH4_RXBUF_THRESHOLD_CONFIG", CMIC_CMC0_PKTDMA_CH4_RXBUF_THRESHOLD_CONFIGr }, \ 240 { 0x00002330, "CMIC_CMC0_PKTDMA_CH4_DEBUG_CONTROL", CMIC_CMC0_PKTDMA_CH4_DEBUG_CONTROLr }, \ 241 { 0x00002334, "CMIC_CMC0_PKTDMA_CH4_DEBUG_SM_STATUS", CMIC_CMC0_PKTDMA_CH4_DEBUG_SM_STATUSr }, \ 242 { 0x00002338, "CMIC_CMC0_PKTDMA_CH4_DEBUG_STATUS", CMIC_CMC0_PKTDMA_CH4_DEBUG_STATUSr }, \ 243 { 0x0000233c, "CMIC_CMC0_PKTDMA_CH4_PKT_COUNT_RXPKT", CMIC_CMC0_PKTDMA_CH4_PKT_COUNT_RXPKTr }, \ 244 { 0x00002340, "CMIC_CMC0_PKTDMA_CH4_PKT_COUNT_TXPKT", CMIC_CMC0_PKTDMA_CH4_PKT_COUNT_TXPKTr }, \ 245 { 0x00002344, "CMIC_CMC0_PKTDMA_CH4_PKT_COUNT_RXPKT_DROP", CMIC_CMC0_PKTDMA_CH4_PKT_COUNT_RXPKT_DROPr }, \ 246 { 0x00002348, "CMIC_CMC0_PKTDMA_CH4_DESC_COUNT_REQ", CMIC_CMC0_PKTDMA_CH4_DESC_COUNT_REQr }, \ 247 { 0x0000234c, "CMIC_CMC0_PKTDMA_CH4_DESC_COUNT_RX", CMIC_CMC0_PKTDMA_CH4_DESC_COUNT_RXr }, \ 248 { 0x00002350, "CMIC_CMC0_PKTDMA_CH4_DESC_COUNT_STATUS_WR", CMIC_CMC0_PKTDMA_CH4_DESC_COUNT_STATUS_WRr }, \ 249 { 0x00002354, "CMIC_CMC0_PKTDMA_CH4_DESC_MEM_ECC_STATUS", CMIC_CMC0_PKTDMA_CH4_DESC_MEM_ECC_STATUSr }, \ 250 { 0x00002358, "CMIC_CMC0_PKTDMA_CH4_DESC_MEM_ECC_CONTROL", CMIC_CMC0_PKTDMA_CH4_DESC_MEM_ECC_CONTROLr }, \ 251 { 0x0000235c, "CMIC_CMC0_PKTDMA_CH4_DESC_MEM_TM_CONTROL", CMIC_CMC0_PKTDMA_CH4_DESC_MEM_TM_CONTROLr }, \ 252 { 0x00002380, "CMIC_CMC0_PKTDMA_CH5_CTRL", CMIC_CMC0_PKTDMA_CH5_CTRLr }, \ 253 { 0x00002384, "CMIC_CMC0_PKTDMA_CH5_DESC_ADDR_LO", CMIC_CMC0_PKTDMA_CH5_DESC_ADDR_LOr }, \ 254 { 0x00002388, "CMIC_CMC0_PKTDMA_CH5_DESC_ADDR_HI", CMIC_CMC0_PKTDMA_CH5_DESC_ADDR_HIr }, \ 255 { 0x0000238c, "CMIC_CMC0_PKTDMA_CH5_DESC_HALT_ADDR_LO", CMIC_CMC0_PKTDMA_CH5_DESC_HALT_ADDR_LOr }, \ 256 { 0x00002390, "CMIC_CMC0_PKTDMA_CH5_DESC_HALT_ADDR_HI", CMIC_CMC0_PKTDMA_CH5_DESC_HALT_ADDR_HIr }, \ 257 { 0x00002394, "CMIC_CMC0_PKTDMA_CH5_STAT", CMIC_CMC0_PKTDMA_CH5_STATr }, \ 258 { 0x00002398, "CMIC_CMC0_PKTDMA_CH5_COS_CTRL_RX_0", CMIC_CMC0_PKTDMA_CH5_COS_CTRL_RX_0r }, \ 259 { 0x0000239c, "CMIC_CMC0_PKTDMA_CH5_COS_CTRL_RX_1", CMIC_CMC0_PKTDMA_CH5_COS_CTRL_RX_1r }, \ 260 { 0x000023a0, "CMIC_CMC0_PKTDMA_CH5_INTR_COAL", CMIC_CMC0_PKTDMA_CH5_INTR_COALr }, \ 261 { 0x000023a4, "CMIC_CMC0_PKTDMA_CH5_CURR_DESC_LO", CMIC_CMC0_PKTDMA_CH5_CURR_DESC_LOr }, \ 262 { 0x000023a8, "CMIC_CMC0_PKTDMA_CH5_CURR_DESC_HI", CMIC_CMC0_PKTDMA_CH5_CURR_DESC_HIr }, \ 263 { 0x000023ac, "CMIC_CMC0_PKTDMA_CH5_RXBUF_THRESHOLD_CONFIG", CMIC_CMC0_PKTDMA_CH5_RXBUF_THRESHOLD_CONFIGr }, \ 264 { 0x000023b0, "CMIC_CMC0_PKTDMA_CH5_DEBUG_CONTROL", CMIC_CMC0_PKTDMA_CH5_DEBUG_CONTROLr }, \ 265 { 0x000023b4, "CMIC_CMC0_PKTDMA_CH5_DEBUG_SM_STATUS", CMIC_CMC0_PKTDMA_CH5_DEBUG_SM_STATUSr }, \ 266 { 0x000023b8, "CMIC_CMC0_PKTDMA_CH5_DEBUG_STATUS", CMIC_CMC0_PKTDMA_CH5_DEBUG_STATUSr }, \ 267 { 0x000023bc, "CMIC_CMC0_PKTDMA_CH5_PKT_COUNT_RXPKT", CMIC_CMC0_PKTDMA_CH5_PKT_COUNT_RXPKTr }, \ 268 { 0x000023c0, "CMIC_CMC0_PKTDMA_CH5_PKT_COUNT_TXPKT", CMIC_CMC0_PKTDMA_CH5_PKT_COUNT_TXPKTr }, \ 269 { 0x000023c4, "CMIC_CMC0_PKTDMA_CH5_PKT_COUNT_RXPKT_DROP", CMIC_CMC0_PKTDMA_CH5_PKT_COUNT_RXPKT_DROPr }, \ 270 { 0x000023c8, "CMIC_CMC0_PKTDMA_CH5_DESC_COUNT_REQ", CMIC_CMC0_PKTDMA_CH5_DESC_COUNT_REQr }, \ 271 { 0x000023cc, "CMIC_CMC0_PKTDMA_CH5_DESC_COUNT_RX", CMIC_CMC0_PKTDMA_CH5_DESC_COUNT_RXr }, \ 272 { 0x000023d0, "CMIC_CMC0_PKTDMA_CH5_DESC_COUNT_STATUS_WR", CMIC_CMC0_PKTDMA_CH5_DESC_COUNT_STATUS_WRr }, \ 273 { 0x000023d4, "CMIC_CMC0_PKTDMA_CH5_DESC_MEM_ECC_STATUS", CMIC_CMC0_PKTDMA_CH5_DESC_MEM_ECC_STATUSr }, \ 274 { 0x000023d8, "CMIC_CMC0_PKTDMA_CH5_DESC_MEM_ECC_CONTROL", CMIC_CMC0_PKTDMA_CH5_DESC_MEM_ECC_CONTROLr }, \ 275 { 0x000023dc, "CMIC_CMC0_PKTDMA_CH5_DESC_MEM_TM_CONTROL", CMIC_CMC0_PKTDMA_CH5_DESC_MEM_TM_CONTROLr }, \ 276 { 0x00002400, "CMIC_CMC0_PKTDMA_CH6_CTRL", CMIC_CMC0_PKTDMA_CH6_CTRLr }, \ 277 { 0x00002404, "CMIC_CMC0_PKTDMA_CH6_DESC_ADDR_LO", CMIC_CMC0_PKTDMA_CH6_DESC_ADDR_LOr }, \ 278 { 0x00002408, "CMIC_CMC0_PKTDMA_CH6_DESC_ADDR_HI", CMIC_CMC0_PKTDMA_CH6_DESC_ADDR_HIr }, \ 279 { 0x0000240c, "CMIC_CMC0_PKTDMA_CH6_DESC_HALT_ADDR_LO", CMIC_CMC0_PKTDMA_CH6_DESC_HALT_ADDR_LOr }, \ 280 { 0x00002410, "CMIC_CMC0_PKTDMA_CH6_DESC_HALT_ADDR_HI", CMIC_CMC0_PKTDMA_CH6_DESC_HALT_ADDR_HIr }, \ 281 { 0x00002414, "CMIC_CMC0_PKTDMA_CH6_STAT", CMIC_CMC0_PKTDMA_CH6_STATr }, \ 282 { 0x00002418, "CMIC_CMC0_PKTDMA_CH6_COS_CTRL_RX_0", CMIC_CMC0_PKTDMA_CH6_COS_CTRL_RX_0r }, \ 283 { 0x0000241c, "CMIC_CMC0_PKTDMA_CH6_COS_CTRL_RX_1", CMIC_CMC0_PKTDMA_CH6_COS_CTRL_RX_1r }, \ 284 { 0x00002420, "CMIC_CMC0_PKTDMA_CH6_INTR_COAL", CMIC_CMC0_PKTDMA_CH6_INTR_COALr }, \ 285 { 0x00002424, "CMIC_CMC0_PKTDMA_CH6_CURR_DESC_LO", CMIC_CMC0_PKTDMA_CH6_CURR_DESC_LOr }, \ 286 { 0x00002428, "CMIC_CMC0_PKTDMA_CH6_CURR_DESC_HI", CMIC_CMC0_PKTDMA_CH6_CURR_DESC_HIr }, \ 287 { 0x0000242c, "CMIC_CMC0_PKTDMA_CH6_RXBUF_THRESHOLD_CONFIG", CMIC_CMC0_PKTDMA_CH6_RXBUF_THRESHOLD_CONFIGr }, \ 288 { 0x00002430, "CMIC_CMC0_PKTDMA_CH6_DEBUG_CONTROL", CMIC_CMC0_PKTDMA_CH6_DEBUG_CONTROLr }, \ 289 { 0x00002434, "CMIC_CMC0_PKTDMA_CH6_DEBUG_SM_STATUS", CMIC_CMC0_PKTDMA_CH6_DEBUG_SM_STATUSr }, \ 290 { 0x00002438, "CMIC_CMC0_PKTDMA_CH6_DEBUG_STATUS", CMIC_CMC0_PKTDMA_CH6_DEBUG_STATUSr }, \ 291 { 0x0000243c, "CMIC_CMC0_PKTDMA_CH6_PKT_COUNT_RXPKT", CMIC_CMC0_PKTDMA_CH6_PKT_COUNT_RXPKTr }, \ 292 { 0x00002440, "CMIC_CMC0_PKTDMA_CH6_PKT_COUNT_TXPKT", CMIC_CMC0_PKTDMA_CH6_PKT_COUNT_TXPKTr }, \ 293 { 0x00002444, "CMIC_CMC0_PKTDMA_CH6_PKT_COUNT_RXPKT_DROP", CMIC_CMC0_PKTDMA_CH6_PKT_COUNT_RXPKT_DROPr }, \ 294 { 0x00002448, "CMIC_CMC0_PKTDMA_CH6_DESC_COUNT_REQ", CMIC_CMC0_PKTDMA_CH6_DESC_COUNT_REQr }, \ 295 { 0x0000244c, "CMIC_CMC0_PKTDMA_CH6_DESC_COUNT_RX", CMIC_CMC0_PKTDMA_CH6_DESC_COUNT_RXr }, \ 296 { 0x00002450, "CMIC_CMC0_PKTDMA_CH6_DESC_COUNT_STATUS_WR", CMIC_CMC0_PKTDMA_CH6_DESC_COUNT_STATUS_WRr }, \ 297 { 0x00002454, "CMIC_CMC0_PKTDMA_CH6_DESC_MEM_ECC_STATUS", CMIC_CMC0_PKTDMA_CH6_DESC_MEM_ECC_STATUSr }, \ 298 { 0x00002458, "CMIC_CMC0_PKTDMA_CH6_DESC_MEM_ECC_CONTROL", CMIC_CMC0_PKTDMA_CH6_DESC_MEM_ECC_CONTROLr }, \ 299 { 0x0000245c, "CMIC_CMC0_PKTDMA_CH6_DESC_MEM_TM_CONTROL", CMIC_CMC0_PKTDMA_CH6_DESC_MEM_TM_CONTROLr }, \ 300 { 0x00002480, "CMIC_CMC0_PKTDMA_CH7_CTRL", CMIC_CMC0_PKTDMA_CH7_CTRLr }, \ 301 { 0x00002484, "CMIC_CMC0_PKTDMA_CH7_DESC_ADDR_LO", CMIC_CMC0_PKTDMA_CH7_DESC_ADDR_LOr }, \ 302 { 0x00002488, "CMIC_CMC0_PKTDMA_CH7_DESC_ADDR_HI", CMIC_CMC0_PKTDMA_CH7_DESC_ADDR_HIr }, \ 303 { 0x0000248c, "CMIC_CMC0_PKTDMA_CH7_DESC_HALT_ADDR_LO", CMIC_CMC0_PKTDMA_CH7_DESC_HALT_ADDR_LOr }, \ 304 { 0x00002490, "CMIC_CMC0_PKTDMA_CH7_DESC_HALT_ADDR_HI", CMIC_CMC0_PKTDMA_CH7_DESC_HALT_ADDR_HIr }, \ 305 { 0x00002494, "CMIC_CMC0_PKTDMA_CH7_STAT", CMIC_CMC0_PKTDMA_CH7_STATr }, \ 306 { 0x00002498, "CMIC_CMC0_PKTDMA_CH7_COS_CTRL_RX_0", CMIC_CMC0_PKTDMA_CH7_COS_CTRL_RX_0r }, \ 307 { 0x0000249c, "CMIC_CMC0_PKTDMA_CH7_COS_CTRL_RX_1", CMIC_CMC0_PKTDMA_CH7_COS_CTRL_RX_1r }, \ 308 { 0x000024a0, "CMIC_CMC0_PKTDMA_CH7_INTR_COAL", CMIC_CMC0_PKTDMA_CH7_INTR_COALr }, \ 309 { 0x000024a4, "CMIC_CMC0_PKTDMA_CH7_CURR_DESC_LO", CMIC_CMC0_PKTDMA_CH7_CURR_DESC_LOr }, \ 310 { 0x000024a8, "CMIC_CMC0_PKTDMA_CH7_CURR_DESC_HI", CMIC_CMC0_PKTDMA_CH7_CURR_DESC_HIr }, \ 311 { 0x000024ac, "CMIC_CMC0_PKTDMA_CH7_RXBUF_THRESHOLD_CONFIG", CMIC_CMC0_PKTDMA_CH7_RXBUF_THRESHOLD_CONFIGr }, \ 312 { 0x000024b0, "CMIC_CMC0_PKTDMA_CH7_DEBUG_CONTROL", CMIC_CMC0_PKTDMA_CH7_DEBUG_CONTROLr }, \ 313 { 0x000024b4, "CMIC_CMC0_PKTDMA_CH7_DEBUG_SM_STATUS", CMIC_CMC0_PKTDMA_CH7_DEBUG_SM_STATUSr }, \ 314 { 0x000024b8, "CMIC_CMC0_PKTDMA_CH7_DEBUG_STATUS", CMIC_CMC0_PKTDMA_CH7_DEBUG_STATUSr }, \ 315 { 0x000024bc, "CMIC_CMC0_PKTDMA_CH7_PKT_COUNT_RXPKT", CMIC_CMC0_PKTDMA_CH7_PKT_COUNT_RXPKTr }, \ 316 { 0x000024c0, "CMIC_CMC0_PKTDMA_CH7_PKT_COUNT_TXPKT", CMIC_CMC0_PKTDMA_CH7_PKT_COUNT_TXPKTr }, \ 317 { 0x000024c4, "CMIC_CMC0_PKTDMA_CH7_PKT_COUNT_RXPKT_DROP", CMIC_CMC0_PKTDMA_CH7_PKT_COUNT_RXPKT_DROPr }, \ 318 { 0x000024c8, "CMIC_CMC0_PKTDMA_CH7_DESC_COUNT_REQ", CMIC_CMC0_PKTDMA_CH7_DESC_COUNT_REQr }, \ 319 { 0x000024cc, "CMIC_CMC0_PKTDMA_CH7_DESC_COUNT_RX", CMIC_CMC0_PKTDMA_CH7_DESC_COUNT_RXr }, \ 320 { 0x000024d0, "CMIC_CMC0_PKTDMA_CH7_DESC_COUNT_STATUS_WR", CMIC_CMC0_PKTDMA_CH7_DESC_COUNT_STATUS_WRr }, \ 321 { 0x000024d4, "CMIC_CMC0_PKTDMA_CH7_DESC_MEM_ECC_STATUS", CMIC_CMC0_PKTDMA_CH7_DESC_MEM_ECC_STATUSr }, \ 322 { 0x000024d8, "CMIC_CMC0_PKTDMA_CH7_DESC_MEM_ECC_CONTROL", CMIC_CMC0_PKTDMA_CH7_DESC_MEM_ECC_CONTROLr }, \ 323 { 0x000024dc, "CMIC_CMC0_PKTDMA_CH7_DESC_MEM_TM_CONTROL", CMIC_CMC0_PKTDMA_CH7_DESC_MEM_TM_CONTROLr }, \ 324 { 0x00003000, "CMIC_CMC0_SBUSDMA_CH0_CONTROL", CMIC_CMC0_SBUSDMA_CH0_CONTROLr }, \ 325 { 0x00003004, "CMIC_CMC0_SBUSDMA_CH0_REQUEST", CMIC_CMC0_SBUSDMA_CH0_REQUESTr }, \ 326 { 0x00003008, "CMIC_CMC0_SBUSDMA_CH0_COUNT", CMIC_CMC0_SBUSDMA_CH0_COUNTr }, \ 327 { 0x0000300c, "CMIC_CMC0_SBUSDMA_CH0_OPCODE", CMIC_CMC0_SBUSDMA_CH0_OPCODEr }, \ 328 { 0x00003010, "CMIC_CMC0_SBUSDMA_CH0_SBUS_START_ADDRESS", CMIC_CMC0_SBUSDMA_CH0_SBUS_START_ADDRESSr }, \ 329 { 0x00003014, "CMIC_CMC0_SBUSDMA_CH0_HOSTMEM_START_ADDRESS_LO", CMIC_CMC0_SBUSDMA_CH0_HOSTMEM_START_ADDRESS_LOr }, \ 330 { 0x00003018, "CMIC_CMC0_SBUSDMA_CH0_HOSTMEM_START_ADDRESS_HI", CMIC_CMC0_SBUSDMA_CH0_HOSTMEM_START_ADDRESS_HIr }, \ 331 { 0x0000301c, "CMIC_CMC0_SBUSDMA_CH0_DESC_START_ADDRESS_LO", CMIC_CMC0_SBUSDMA_CH0_DESC_START_ADDRESS_LOr }, \ 332 { 0x00003020, "CMIC_CMC0_SBUSDMA_CH0_DESC_START_ADDRESS_HI", CMIC_CMC0_SBUSDMA_CH0_DESC_START_ADDRESS_HIr }, \ 333 { 0x00003024, "CMIC_CMC0_SBUSDMA_CH0_STATUS", CMIC_CMC0_SBUSDMA_CH0_STATUSr }, \ 334 { 0x00003028, "CMIC_CMC0_SBUSDMA_CH0_CUR_HOSTMEM_ADDRESS_LO", CMIC_CMC0_SBUSDMA_CH0_CUR_HOSTMEM_ADDRESS_LOr }, \ 335 { 0x0000302c, "CMIC_CMC0_SBUSDMA_CH0_CUR_HOSTMEM_ADDRESS_HI", CMIC_CMC0_SBUSDMA_CH0_CUR_HOSTMEM_ADDRESS_HIr }, \ 336 { 0x00003030, "CMIC_CMC0_SBUSDMA_CH0_CUR_SBUS_ADDRESS", CMIC_CMC0_SBUSDMA_CH0_CUR_SBUS_ADDRESSr }, \ 337 { 0x00003034, "CMIC_CMC0_SBUSDMA_CH0_CUR_DESC_ADDRESS_LO", CMIC_CMC0_SBUSDMA_CH0_CUR_DESC_ADDRESS_LOr }, \ 338 { 0x00003038, "CMIC_CMC0_SBUSDMA_CH0_CUR_DESC_ADDRESS_HI", CMIC_CMC0_SBUSDMA_CH0_CUR_DESC_ADDRESS_HIr }, \ 339 { 0x0000303c, "CMIC_CMC0_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_REQUEST", CMIC_CMC0_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_REQUESTr }, \ 340 { 0x00003040, "CMIC_CMC0_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_OPCODE", CMIC_CMC0_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_OPCODEr }, \ 341 { 0x00003044, "CMIC_CMC0_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_SBUS_START_ADDRESS", CMIC_CMC0_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_SBUS_START_ADDRESSr }, \ 342 { 0x00003048, "CMIC_CMC0_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_LO", CMIC_CMC0_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_LOr }, \ 343 { 0x0000304c, "CMIC_CMC0_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_HI", CMIC_CMC0_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_HIr }, \ 344 { 0x00003050, "CMIC_CMC0_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_COUNT", CMIC_CMC0_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_COUNTr }, \ 345 { 0x00003054, "CMIC_CMC0_SBUSDMA_CH0_SBUSDMA_DEBUG", CMIC_CMC0_SBUSDMA_CH0_SBUSDMA_DEBUGr }, \ 346 { 0x00003058, "CMIC_CMC0_SBUSDMA_CH0_SBUSDMA_DEBUG_CLR", CMIC_CMC0_SBUSDMA_CH0_SBUSDMA_DEBUG_CLRr }, \ 347 { 0x0000305c, "CMIC_CMC0_SBUSDMA_CH0_SBUSDMA_ECCERR_ADDRESS_LO", CMIC_CMC0_SBUSDMA_CH0_SBUSDMA_ECCERR_ADDRESS_LOr }, \ 348 { 0x00003060, "CMIC_CMC0_SBUSDMA_CH0_SBUSDMA_ECCERR_ADDRESS_HI", CMIC_CMC0_SBUSDMA_CH0_SBUSDMA_ECCERR_ADDRESS_HIr }, \ 349 { 0x00003064, "CMIC_CMC0_SBUSDMA_CH0_ECC_CONTROL", CMIC_CMC0_SBUSDMA_CH0_ECC_CONTROLr }, \ 350 { 0x00003068, "CMIC_CMC0_SBUSDMA_CH0_ECC_STATUS", CMIC_CMC0_SBUSDMA_CH0_ECC_STATUSr }, \ 351 { 0x0000306c, "CMIC_CMC0_SBUSDMA_CH0_ECC_STATUS_CLR", CMIC_CMC0_SBUSDMA_CH0_ECC_STATUS_CLRr }, \ 352 { 0x00003070, "CMIC_CMC0_SBUSDMA_CH0_TIMER", CMIC_CMC0_SBUSDMA_CH0_TIMERr }, \ 353 { 0x00003074, "CMIC_CMC0_SBUSDMA_CH0_ITER_COUNT", CMIC_CMC0_SBUSDMA_CH0_ITER_COUNTr }, \ 354 { 0x00003078, "CMIC_CMC0_SBUSDMA_CH0_TM_CONTROL", CMIC_CMC0_SBUSDMA_CH0_TM_CONTROLr }, \ 355 { 0x00003100, "CMIC_CMC0_SBUSDMA_CH1_CONTROL", CMIC_CMC0_SBUSDMA_CH1_CONTROLr }, \ 356 { 0x00003104, "CMIC_CMC0_SBUSDMA_CH1_REQUEST", CMIC_CMC0_SBUSDMA_CH1_REQUESTr }, \ 357 { 0x00003108, "CMIC_CMC0_SBUSDMA_CH1_COUNT", CMIC_CMC0_SBUSDMA_CH1_COUNTr }, \ 358 { 0x0000310c, "CMIC_CMC0_SBUSDMA_CH1_OPCODE", CMIC_CMC0_SBUSDMA_CH1_OPCODEr }, \ 359 { 0x00003110, "CMIC_CMC0_SBUSDMA_CH1_SBUS_START_ADDRESS", CMIC_CMC0_SBUSDMA_CH1_SBUS_START_ADDRESSr }, \ 360 { 0x00003114, "CMIC_CMC0_SBUSDMA_CH1_HOSTMEM_START_ADDRESS_LO", CMIC_CMC0_SBUSDMA_CH1_HOSTMEM_START_ADDRESS_LOr }, \ 361 { 0x00003118, "CMIC_CMC0_SBUSDMA_CH1_HOSTMEM_START_ADDRESS_HI", CMIC_CMC0_SBUSDMA_CH1_HOSTMEM_START_ADDRESS_HIr }, \ 362 { 0x0000311c, "CMIC_CMC0_SBUSDMA_CH1_DESC_START_ADDRESS_LO", CMIC_CMC0_SBUSDMA_CH1_DESC_START_ADDRESS_LOr }, \ 363 { 0x00003120, "CMIC_CMC0_SBUSDMA_CH1_DESC_START_ADDRESS_HI", CMIC_CMC0_SBUSDMA_CH1_DESC_START_ADDRESS_HIr }, \ 364 { 0x00003124, "CMIC_CMC0_SBUSDMA_CH1_STATUS", CMIC_CMC0_SBUSDMA_CH1_STATUSr }, \ 365 { 0x00003128, "CMIC_CMC0_SBUSDMA_CH1_CUR_HOSTMEM_ADDRESS_LO", CMIC_CMC0_SBUSDMA_CH1_CUR_HOSTMEM_ADDRESS_LOr }, \ 366 { 0x0000312c, "CMIC_CMC0_SBUSDMA_CH1_CUR_HOSTMEM_ADDRESS_HI", CMIC_CMC0_SBUSDMA_CH1_CUR_HOSTMEM_ADDRESS_HIr }, \ 367 { 0x00003130, "CMIC_CMC0_SBUSDMA_CH1_CUR_SBUS_ADDRESS", CMIC_CMC0_SBUSDMA_CH1_CUR_SBUS_ADDRESSr }, \ 368 { 0x00003134, "CMIC_CMC0_SBUSDMA_CH1_CUR_DESC_ADDRESS_LO", CMIC_CMC0_SBUSDMA_CH1_CUR_DESC_ADDRESS_LOr }, \ 369 { 0x00003138, "CMIC_CMC0_SBUSDMA_CH1_CUR_DESC_ADDRESS_HI", CMIC_CMC0_SBUSDMA_CH1_CUR_DESC_ADDRESS_HIr }, \ 370 { 0x0000313c, "CMIC_CMC0_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_REQUEST", CMIC_CMC0_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_REQUESTr }, \ 371 { 0x00003140, "CMIC_CMC0_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_OPCODE", CMIC_CMC0_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_OPCODEr }, \ 372 { 0x00003144, "CMIC_CMC0_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_SBUS_START_ADDRESS", CMIC_CMC0_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_SBUS_START_ADDRESSr }, \ 373 { 0x00003148, "CMIC_CMC0_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_LO", CMIC_CMC0_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_LOr }, \ 374 { 0x0000314c, "CMIC_CMC0_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_HI", CMIC_CMC0_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_HIr }, \ 375 { 0x00003150, "CMIC_CMC0_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_COUNT", CMIC_CMC0_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_COUNTr }, \ 376 { 0x00003154, "CMIC_CMC0_SBUSDMA_CH1_SBUSDMA_DEBUG", CMIC_CMC0_SBUSDMA_CH1_SBUSDMA_DEBUGr }, \ 377 { 0x00003158, "CMIC_CMC0_SBUSDMA_CH1_SBUSDMA_DEBUG_CLR", CMIC_CMC0_SBUSDMA_CH1_SBUSDMA_DEBUG_CLRr }, \ 378 { 0x0000315c, "CMIC_CMC0_SBUSDMA_CH1_SBUSDMA_ECCERR_ADDRESS_LO", CMIC_CMC0_SBUSDMA_CH1_SBUSDMA_ECCERR_ADDRESS_LOr }, \ 379 { 0x00003160, "CMIC_CMC0_SBUSDMA_CH1_SBUSDMA_ECCERR_ADDRESS_HI", CMIC_CMC0_SBUSDMA_CH1_SBUSDMA_ECCERR_ADDRESS_HIr }, \ 380 { 0x00003164, "CMIC_CMC0_SBUSDMA_CH1_ECC_CONTROL", CMIC_CMC0_SBUSDMA_CH1_ECC_CONTROLr }, \ 381 { 0x00003168, "CMIC_CMC0_SBUSDMA_CH1_ECC_STATUS", CMIC_CMC0_SBUSDMA_CH1_ECC_STATUSr }, \ 382 { 0x0000316c, "CMIC_CMC0_SBUSDMA_CH1_ECC_STATUS_CLR", CMIC_CMC0_SBUSDMA_CH1_ECC_STATUS_CLRr }, \ 383 { 0x00003170, "CMIC_CMC0_SBUSDMA_CH1_TIMER", CMIC_CMC0_SBUSDMA_CH1_TIMERr }, \ 384 { 0x00003174, "CMIC_CMC0_SBUSDMA_CH1_ITER_COUNT", CMIC_CMC0_SBUSDMA_CH1_ITER_COUNTr }, \ 385 { 0x00003178, "CMIC_CMC0_SBUSDMA_CH1_TM_CONTROL", CMIC_CMC0_SBUSDMA_CH1_TM_CONTROLr }, \ 386 { 0x00003200, "CMIC_CMC0_SBUSDMA_CH2_CONTROL", CMIC_CMC0_SBUSDMA_CH2_CONTROLr }, \ 387 { 0x00003204, "CMIC_CMC0_SBUSDMA_CH2_REQUEST", CMIC_CMC0_SBUSDMA_CH2_REQUESTr }, \ 388 { 0x00003208, "CMIC_CMC0_SBUSDMA_CH2_COUNT", CMIC_CMC0_SBUSDMA_CH2_COUNTr }, \ 389 { 0x0000320c, "CMIC_CMC0_SBUSDMA_CH2_OPCODE", CMIC_CMC0_SBUSDMA_CH2_OPCODEr }, \ 390 { 0x00003210, "CMIC_CMC0_SBUSDMA_CH2_SBUS_START_ADDRESS", CMIC_CMC0_SBUSDMA_CH2_SBUS_START_ADDRESSr }, \ 391 { 0x00003214, "CMIC_CMC0_SBUSDMA_CH2_HOSTMEM_START_ADDRESS_LO", CMIC_CMC0_SBUSDMA_CH2_HOSTMEM_START_ADDRESS_LOr }, \ 392 { 0x00003218, "CMIC_CMC0_SBUSDMA_CH2_HOSTMEM_START_ADDRESS_HI", CMIC_CMC0_SBUSDMA_CH2_HOSTMEM_START_ADDRESS_HIr }, \ 393 { 0x0000321c, "CMIC_CMC0_SBUSDMA_CH2_DESC_START_ADDRESS_LO", CMIC_CMC0_SBUSDMA_CH2_DESC_START_ADDRESS_LOr }, \ 394 { 0x00003220, "CMIC_CMC0_SBUSDMA_CH2_DESC_START_ADDRESS_HI", CMIC_CMC0_SBUSDMA_CH2_DESC_START_ADDRESS_HIr }, \ 395 { 0x00003224, "CMIC_CMC0_SBUSDMA_CH2_STATUS", CMIC_CMC0_SBUSDMA_CH2_STATUSr }, \ 396 { 0x00003228, "CMIC_CMC0_SBUSDMA_CH2_CUR_HOSTMEM_ADDRESS_LO", CMIC_CMC0_SBUSDMA_CH2_CUR_HOSTMEM_ADDRESS_LOr }, \ 397 { 0x0000322c, "CMIC_CMC0_SBUSDMA_CH2_CUR_HOSTMEM_ADDRESS_HI", CMIC_CMC0_SBUSDMA_CH2_CUR_HOSTMEM_ADDRESS_HIr }, \ 398 { 0x00003230, "CMIC_CMC0_SBUSDMA_CH2_CUR_SBUS_ADDRESS", CMIC_CMC0_SBUSDMA_CH2_CUR_SBUS_ADDRESSr }, \ 399 { 0x00003234, "CMIC_CMC0_SBUSDMA_CH2_CUR_DESC_ADDRESS_LO", CMIC_CMC0_SBUSDMA_CH2_CUR_DESC_ADDRESS_LOr }, \ 400 { 0x00003238, "CMIC_CMC0_SBUSDMA_CH2_CUR_DESC_ADDRESS_HI", CMIC_CMC0_SBUSDMA_CH2_CUR_DESC_ADDRESS_HIr }, \ 401 { 0x0000323c, "CMIC_CMC0_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_REQUEST", CMIC_CMC0_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_REQUESTr }, \ 402 { 0x00003240, "CMIC_CMC0_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_OPCODE", CMIC_CMC0_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_OPCODEr }, \ 403 { 0x00003244, "CMIC_CMC0_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_SBUS_START_ADDRESS", CMIC_CMC0_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_SBUS_START_ADDRESSr }, \ 404 { 0x00003248, "CMIC_CMC0_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_LO", CMIC_CMC0_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_LOr }, \ 405 { 0x0000324c, "CMIC_CMC0_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_HI", CMIC_CMC0_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_HIr }, \ 406 { 0x00003250, "CMIC_CMC0_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_COUNT", CMIC_CMC0_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_COUNTr }, \ 407 { 0x00003254, "CMIC_CMC0_SBUSDMA_CH2_SBUSDMA_DEBUG", CMIC_CMC0_SBUSDMA_CH2_SBUSDMA_DEBUGr }, \ 408 { 0x00003258, "CMIC_CMC0_SBUSDMA_CH2_SBUSDMA_DEBUG_CLR", CMIC_CMC0_SBUSDMA_CH2_SBUSDMA_DEBUG_CLRr }, \ 409 { 0x0000325c, "CMIC_CMC0_SBUSDMA_CH2_SBUSDMA_ECCERR_ADDRESS_LO", CMIC_CMC0_SBUSDMA_CH2_SBUSDMA_ECCERR_ADDRESS_LOr }, \ 410 { 0x00003260, "CMIC_CMC0_SBUSDMA_CH2_SBUSDMA_ECCERR_ADDRESS_HI", CMIC_CMC0_SBUSDMA_CH2_SBUSDMA_ECCERR_ADDRESS_HIr }, \ 411 { 0x00003264, "CMIC_CMC0_SBUSDMA_CH2_ECC_CONTROL", CMIC_CMC0_SBUSDMA_CH2_ECC_CONTROLr }, \ 412 { 0x00003268, "CMIC_CMC0_SBUSDMA_CH2_ECC_STATUS", CMIC_CMC0_SBUSDMA_CH2_ECC_STATUSr }, \ 413 { 0x0000326c, "CMIC_CMC0_SBUSDMA_CH2_ECC_STATUS_CLR", CMIC_CMC0_SBUSDMA_CH2_ECC_STATUS_CLRr }, \ 414 { 0x00003270, "CMIC_CMC0_SBUSDMA_CH2_TIMER", CMIC_CMC0_SBUSDMA_CH2_TIMERr }, \ 415 { 0x00003274, "CMIC_CMC0_SBUSDMA_CH2_ITER_COUNT", CMIC_CMC0_SBUSDMA_CH2_ITER_COUNTr }, \ 416 { 0x00003278, "CMIC_CMC0_SBUSDMA_CH2_TM_CONTROL", CMIC_CMC0_SBUSDMA_CH2_TM_CONTROLr }, \ 417 { 0x00003300, "CMIC_CMC0_SBUSDMA_CH3_CONTROL", CMIC_CMC0_SBUSDMA_CH3_CONTROLr }, \ 418 { 0x00003304, "CMIC_CMC0_SBUSDMA_CH3_REQUEST", CMIC_CMC0_SBUSDMA_CH3_REQUESTr }, \ 419 { 0x00003308, "CMIC_CMC0_SBUSDMA_CH3_COUNT", CMIC_CMC0_SBUSDMA_CH3_COUNTr }, \ 420 { 0x0000330c, "CMIC_CMC0_SBUSDMA_CH3_OPCODE", CMIC_CMC0_SBUSDMA_CH3_OPCODEr }, \ 421 { 0x00003310, "CMIC_CMC0_SBUSDMA_CH3_SBUS_START_ADDRESS", CMIC_CMC0_SBUSDMA_CH3_SBUS_START_ADDRESSr }, \ 422 { 0x00003314, "CMIC_CMC0_SBUSDMA_CH3_HOSTMEM_START_ADDRESS_LO", CMIC_CMC0_SBUSDMA_CH3_HOSTMEM_START_ADDRESS_LOr }, \ 423 { 0x00003318, "CMIC_CMC0_SBUSDMA_CH3_HOSTMEM_START_ADDRESS_HI", CMIC_CMC0_SBUSDMA_CH3_HOSTMEM_START_ADDRESS_HIr }, \ 424 { 0x0000331c, "CMIC_CMC0_SBUSDMA_CH3_DESC_START_ADDRESS_LO", CMIC_CMC0_SBUSDMA_CH3_DESC_START_ADDRESS_LOr }, \ 425 { 0x00003320, "CMIC_CMC0_SBUSDMA_CH3_DESC_START_ADDRESS_HI", CMIC_CMC0_SBUSDMA_CH3_DESC_START_ADDRESS_HIr }, \ 426 { 0x00003324, "CMIC_CMC0_SBUSDMA_CH3_STATUS", CMIC_CMC0_SBUSDMA_CH3_STATUSr }, \ 427 { 0x00003328, "CMIC_CMC0_SBUSDMA_CH3_CUR_HOSTMEM_ADDRESS_LO", CMIC_CMC0_SBUSDMA_CH3_CUR_HOSTMEM_ADDRESS_LOr }, \ 428 { 0x0000332c, "CMIC_CMC0_SBUSDMA_CH3_CUR_HOSTMEM_ADDRESS_HI", CMIC_CMC0_SBUSDMA_CH3_CUR_HOSTMEM_ADDRESS_HIr }, \ 429 { 0x00003330, "CMIC_CMC0_SBUSDMA_CH3_CUR_SBUS_ADDRESS", CMIC_CMC0_SBUSDMA_CH3_CUR_SBUS_ADDRESSr }, \ 430 { 0x00003334, "CMIC_CMC0_SBUSDMA_CH3_CUR_DESC_ADDRESS_LO", CMIC_CMC0_SBUSDMA_CH3_CUR_DESC_ADDRESS_LOr }, \ 431 { 0x00003338, "CMIC_CMC0_SBUSDMA_CH3_CUR_DESC_ADDRESS_HI", CMIC_CMC0_SBUSDMA_CH3_CUR_DESC_ADDRESS_HIr }, \ 432 { 0x0000333c, "CMIC_CMC0_SBUSDMA_CH3_CUR_SBUSDMA_CONFIG_REQUEST", CMIC_CMC0_SBUSDMA_CH3_CUR_SBUSDMA_CONFIG_REQUESTr }, \ 433 { 0x00003340, "CMIC_CMC0_SBUSDMA_CH3_CUR_SBUSDMA_CONFIG_OPCODE", CMIC_CMC0_SBUSDMA_CH3_CUR_SBUSDMA_CONFIG_OPCODEr }, \ 434 { 0x00003344, "CMIC_CMC0_SBUSDMA_CH3_CUR_SBUSDMA_CONFIG_SBUS_START_ADDRESS", CMIC_CMC0_SBUSDMA_CH3_CUR_SBUSDMA_CONFIG_SBUS_START_ADDRESSr }, \ 435 { 0x00003348, "CMIC_CMC0_SBUSDMA_CH3_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_LO", CMIC_CMC0_SBUSDMA_CH3_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_LOr }, \ 436 { 0x0000334c, "CMIC_CMC0_SBUSDMA_CH3_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_HI", CMIC_CMC0_SBUSDMA_CH3_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_HIr }, \ 437 { 0x00003350, "CMIC_CMC0_SBUSDMA_CH3_CUR_SBUSDMA_CONFIG_COUNT", CMIC_CMC0_SBUSDMA_CH3_CUR_SBUSDMA_CONFIG_COUNTr }, \ 438 { 0x00003354, "CMIC_CMC0_SBUSDMA_CH3_SBUSDMA_DEBUG", CMIC_CMC0_SBUSDMA_CH3_SBUSDMA_DEBUGr }, \ 439 { 0x00003358, "CMIC_CMC0_SBUSDMA_CH3_SBUSDMA_DEBUG_CLR", CMIC_CMC0_SBUSDMA_CH3_SBUSDMA_DEBUG_CLRr }, \ 440 { 0x0000335c, "CMIC_CMC0_SBUSDMA_CH3_SBUSDMA_ECCERR_ADDRESS_LO", CMIC_CMC0_SBUSDMA_CH3_SBUSDMA_ECCERR_ADDRESS_LOr }, \ 441 { 0x00003360, "CMIC_CMC0_SBUSDMA_CH3_SBUSDMA_ECCERR_ADDRESS_HI", CMIC_CMC0_SBUSDMA_CH3_SBUSDMA_ECCERR_ADDRESS_HIr }, \ 442 { 0x00003364, "CMIC_CMC0_SBUSDMA_CH3_ECC_CONTROL", CMIC_CMC0_SBUSDMA_CH3_ECC_CONTROLr }, \ 443 { 0x00003368, "CMIC_CMC0_SBUSDMA_CH3_ECC_STATUS", CMIC_CMC0_SBUSDMA_CH3_ECC_STATUSr }, \ 444 { 0x0000336c, "CMIC_CMC0_SBUSDMA_CH3_ECC_STATUS_CLR", CMIC_CMC0_SBUSDMA_CH3_ECC_STATUS_CLRr }, \ 445 { 0x00003370, "CMIC_CMC0_SBUSDMA_CH3_TIMER", CMIC_CMC0_SBUSDMA_CH3_TIMERr }, \ 446 { 0x00003374, "CMIC_CMC0_SBUSDMA_CH3_ITER_COUNT", CMIC_CMC0_SBUSDMA_CH3_ITER_COUNTr }, \ 447 { 0x00003378, "CMIC_CMC0_SBUSDMA_CH3_TM_CONTROL", CMIC_CMC0_SBUSDMA_CH3_TM_CONTROLr }, \ 448 { 0x00003404, "CMIC_CMC0_CCMDMA_CH0_HOST0_MEM_START_ADDR_LO", CMIC_CMC0_CCMDMA_CH0_HOST0_MEM_START_ADDR_LOr }, \ 449 { 0x00003408, "CMIC_CMC0_CCMDMA_CH0_HOST0_MEM_START_ADDR_HI", CMIC_CMC0_CCMDMA_CH0_HOST0_MEM_START_ADDR_HIr }, \ 450 { 0x0000340c, "CMIC_CMC0_CCMDMA_CH0_HOST1_MEM_START_ADDR_LO", CMIC_CMC0_CCMDMA_CH0_HOST1_MEM_START_ADDR_LOr }, \ 451 { 0x00003410, "CMIC_CMC0_CCMDMA_CH0_HOST1_MEM_START_ADDR_HI", CMIC_CMC0_CCMDMA_CH0_HOST1_MEM_START_ADDR_HIr }, \ 452 { 0x00003414, "CMIC_CMC0_CCMDMA_CH0_ENTRY_COUNT", CMIC_CMC0_CCMDMA_CH0_ENTRY_COUNTr }, \ 453 { 0x00003418, "CMIC_CMC0_CCMDMA_CH0_CFG", CMIC_CMC0_CCMDMA_CH0_CFGr }, \ 454 { 0x0000341c, "CMIC_CMC0_CCMDMA_CH0_STAT", CMIC_CMC0_CCMDMA_CH0_STATr }, \ 455 { 0x00003420, "CMIC_CMC0_CCMDMA_CH0_CUR_HOST0_ADDR_LO", CMIC_CMC0_CCMDMA_CH0_CUR_HOST0_ADDR_LOr }, \ 456 { 0x00003424, "CMIC_CMC0_CCMDMA_CH0_CUR_HOST0_ADDR_HI", CMIC_CMC0_CCMDMA_CH0_CUR_HOST0_ADDR_HIr }, \ 457 { 0x00003428, "CMIC_CMC0_CCMDMA_CH0_CUR_HOST1_ADDR_LO", CMIC_CMC0_CCMDMA_CH0_CUR_HOST1_ADDR_LOr }, \ 458 { 0x0000342c, "CMIC_CMC0_CCMDMA_CH0_CUR_HOST1_ADDR_HI", CMIC_CMC0_CCMDMA_CH0_CUR_HOST1_ADDR_HIr }, \ 459 { 0x00003430, "CMIC_CMC0_CCMDMA_CH0_ECC_CONTROL", CMIC_CMC0_CCMDMA_CH0_ECC_CONTROLr }, \ 460 { 0x00003434, "CMIC_CMC0_CCMDMA_CH0_ECC_STATUS", CMIC_CMC0_CCMDMA_CH0_ECC_STATUSr }, \ 461 { 0x00003438, "CMIC_CMC0_CCMDMA_CH0_ECC_STATUS_CLR", CMIC_CMC0_CCMDMA_CH0_ECC_STATUS_CLRr }, \ 462 { 0x0000343c, "CMIC_CMC0_CCMDMA_CH0_TM_CONTROL", CMIC_CMC0_CCMDMA_CH0_TM_CONTROLr }, \ 463 { 0x00003484, "CMIC_CMC0_CCMDMA_CH1_HOST0_MEM_START_ADDR_LO", CMIC_CMC0_CCMDMA_CH1_HOST0_MEM_START_ADDR_LOr }, \ 464 { 0x00003488, "CMIC_CMC0_CCMDMA_CH1_HOST0_MEM_START_ADDR_HI", CMIC_CMC0_CCMDMA_CH1_HOST0_MEM_START_ADDR_HIr }, \ 465 { 0x0000348c, "CMIC_CMC0_CCMDMA_CH1_HOST1_MEM_START_ADDR_LO", CMIC_CMC0_CCMDMA_CH1_HOST1_MEM_START_ADDR_LOr }, \ 466 { 0x00003490, "CMIC_CMC0_CCMDMA_CH1_HOST1_MEM_START_ADDR_HI", CMIC_CMC0_CCMDMA_CH1_HOST1_MEM_START_ADDR_HIr }, \ 467 { 0x00003494, "CMIC_CMC0_CCMDMA_CH1_ENTRY_COUNT", CMIC_CMC0_CCMDMA_CH1_ENTRY_COUNTr }, \ 468 { 0x00003498, "CMIC_CMC0_CCMDMA_CH1_CFG", CMIC_CMC0_CCMDMA_CH1_CFGr }, \ 469 { 0x0000349c, "CMIC_CMC0_CCMDMA_CH1_STAT", CMIC_CMC0_CCMDMA_CH1_STATr }, \ 470 { 0x000034a0, "CMIC_CMC0_CCMDMA_CH1_CUR_HOST0_ADDR_LO", CMIC_CMC0_CCMDMA_CH1_CUR_HOST0_ADDR_LOr }, \ 471 { 0x000034a4, "CMIC_CMC0_CCMDMA_CH1_CUR_HOST0_ADDR_HI", CMIC_CMC0_CCMDMA_CH1_CUR_HOST0_ADDR_HIr }, \ 472 { 0x000034a8, "CMIC_CMC0_CCMDMA_CH1_CUR_HOST1_ADDR_LO", CMIC_CMC0_CCMDMA_CH1_CUR_HOST1_ADDR_LOr }, \ 473 { 0x000034ac, "CMIC_CMC0_CCMDMA_CH1_CUR_HOST1_ADDR_HI", CMIC_CMC0_CCMDMA_CH1_CUR_HOST1_ADDR_HIr }, \ 474 { 0x000034b0, "CMIC_CMC0_CCMDMA_CH1_ECC_CONTROL", CMIC_CMC0_CCMDMA_CH1_ECC_CONTROLr }, \ 475 { 0x000034b4, "CMIC_CMC0_CCMDMA_CH1_ECC_STATUS", CMIC_CMC0_CCMDMA_CH1_ECC_STATUSr }, \ 476 { 0x000034b8, "CMIC_CMC0_CCMDMA_CH1_ECC_STATUS_CLR", CMIC_CMC0_CCMDMA_CH1_ECC_STATUS_CLRr }, \ 477 { 0x000034bc, "CMIC_CMC0_CCMDMA_CH1_TM_CONTROL", CMIC_CMC0_CCMDMA_CH1_TM_CONTROLr }, \ 478 { 0x00004000, "CMIC_CMC1_SHARED_DMA_MASTER_TOTAL_OUTSTD_TRANS_LIMIT", CMIC_CMC1_SHARED_DMA_MASTER_TOTAL_OUTSTD_TRANS_LIMITr }, \ 479 { 0x00004004, "CMIC_CMC1_SHARED_DMA_MASTER_READ_PER_ID_OUTSTD_TRANS_LIMIT", CMIC_CMC1_SHARED_DMA_MASTER_READ_PER_ID_OUTSTD_TRANS_LIMITr }, \ 480 { 0x00004008, "CMIC_CMC1_SHARED_PACKET_DMA_READ_AXI_MAP_CTRL", CMIC_CMC1_SHARED_PACKET_DMA_READ_AXI_MAP_CTRLr }, \ 481 { 0x0000400c, "CMIC_CMC1_SHARED_PACKET_DMA_WRITE_AXI_MAP_CTRL0", CMIC_CMC1_SHARED_PACKET_DMA_WRITE_AXI_MAP_CTRL0r }, \ 482 { 0x00004010, "CMIC_CMC1_SHARED_PACKET_DMA_WRITE_AXI_MAP_CTRL1", CMIC_CMC1_SHARED_PACKET_DMA_WRITE_AXI_MAP_CTRL1r }, \ 483 { 0x00004014, "CMIC_CMC1_SHARED_PACKET_DMA_READ_ARB_CTRL", CMIC_CMC1_SHARED_PACKET_DMA_READ_ARB_CTRLr }, \ 484 { 0x00004018, "CMIC_CMC1_SHARED_PACKET_DMA_WRITE_ARB_CTRL", CMIC_CMC1_SHARED_PACKET_DMA_WRITE_ARB_CTRLr }, \ 485 { 0x0000401c, "CMIC_CMC1_SHARED_SBUS_DMA_READ_AXI_MAP_CTRL", CMIC_CMC1_SHARED_SBUS_DMA_READ_AXI_MAP_CTRLr }, \ 486 { 0x00004020, "CMIC_CMC1_SHARED_SBUS_DMA_WRITE_AXI_MAP_CTRL", CMIC_CMC1_SHARED_SBUS_DMA_WRITE_AXI_MAP_CTRLr }, \ 487 { 0x00004024, "CMIC_CMC1_SHARED_SBUS_DMA_READ_ARB_CTRL", CMIC_CMC1_SHARED_SBUS_DMA_READ_ARB_CTRLr }, \ 488 { 0x00004028, "CMIC_CMC1_SHARED_SBUS_DMA_WRITE_ARB_CTRL", CMIC_CMC1_SHARED_SBUS_DMA_WRITE_ARB_CTRLr }, \ 489 { 0x0000402c, "CMIC_CMC1_SHARED_CCMDMA_READ_AXI_MAP_CTRL", CMIC_CMC1_SHARED_CCMDMA_READ_AXI_MAP_CTRLr }, \ 490 { 0x00004030, "CMIC_CMC1_SHARED_CCMDMA_WRITE_AXI_MAP_CTRL", CMIC_CMC1_SHARED_CCMDMA_WRITE_AXI_MAP_CTRLr }, \ 491 { 0x00004034, "CMIC_CMC1_SHARED_CCMDMA_READ_ARB_CTRL", CMIC_CMC1_SHARED_CCMDMA_READ_ARB_CTRLr }, \ 492 { 0x00004038, "CMIC_CMC1_SHARED_CCMDMA_WRITE_ARB_CTRL", CMIC_CMC1_SHARED_CCMDMA_WRITE_ARB_CTRLr }, \ 493 { 0x0000403c, "CMIC_CMC1_SHARED_COMPLETION_BUF_MAX_FLIST_ENTRIES", CMIC_CMC1_SHARED_COMPLETION_BUF_MAX_FLIST_ENTRIESr }, \ 494 { 0x00004040, "CMIC_CMC1_SHARED_COMPLETION_BUF_STATUS_NUM_FREE_ENTRIES", CMIC_CMC1_SHARED_COMPLETION_BUF_STATUS_NUM_FREE_ENTRIESr }, \ 495 { 0x00004044, "CMIC_CMC1_SHARED_COMPLETION_BUF_ECC_STATUS", CMIC_CMC1_SHARED_COMPLETION_BUF_ECC_STATUSr }, \ 496 { 0x00004048, "CMIC_CMC1_SHARED_COMPLETION_BUF_ECC_CONTROL", CMIC_CMC1_SHARED_COMPLETION_BUF_ECC_CONTROLr }, \ 497 { 0x0000404c, "CMIC_CMC1_SHARED_COMPLETION_BUF_TM_CONTROL", CMIC_CMC1_SHARED_COMPLETION_BUF_TM_CONTROLr }, \ 498 { 0x00004050, "CMIC_CMC1_SHARED_PROGRAMMABLE_COS_MASK0", CMIC_CMC1_SHARED_PROGRAMMABLE_COS_MASK0r }, \ 499 { 0x00004054, "CMIC_CMC1_SHARED_PROGRAMMABLE_COS_MASK1", CMIC_CMC1_SHARED_PROGRAMMABLE_COS_MASK1r }, \ 500 { 0x00004058, "CMIC_CMC1_SHARED_RXBUF_THRESHOLD_CONFIG", CMIC_CMC1_SHARED_RXBUF_THRESHOLD_CONFIGr }, \ 501 { 0x0000405c, "CMIC_CMC1_SHARED_2BIT_ECC_ERROR_STATUS", CMIC_CMC1_SHARED_2BIT_ECC_ERROR_STATUSr }, \ 502 { 0x00004060, "CMIC_CMC1_SHARED_2BIT_ECC_ERROR_STATUS_ENABLE", CMIC_CMC1_SHARED_2BIT_ECC_ERROR_STATUS_ENABLEr }, \ 503 { 0x00004064, "CMIC_CMC1_SHARED_1BIT_ECC_ERROR_STATUS", CMIC_CMC1_SHARED_1BIT_ECC_ERROR_STATUSr }, \ 504 { 0x00004068, "CMIC_CMC1_SHARED_1BIT_ECC_ERROR_STATUS_ENABLE", CMIC_CMC1_SHARED_1BIT_ECC_ERROR_STATUS_ENABLEr }, \ 505 { 0x0000406c, "CMIC_CMC1_SHARED_IRQ_STAT0", CMIC_CMC1_SHARED_IRQ_STAT0r }, \ 506 { 0x00004070, "CMIC_CMC1_SHARED_IRQ_STAT1", CMIC_CMC1_SHARED_IRQ_STAT1r }, \ 507 { 0x00004074, "CMIC_CMC1_SHARED_IRQ_STAT_CLR0", CMIC_CMC1_SHARED_IRQ_STAT_CLR0r }, \ 508 { 0x00004078, "CMIC_CMC1_SHARED_CONFIG", CMIC_CMC1_SHARED_CONFIGr }, \ 509 { 0x0000407c, "CMIC_CMC1_SHARED_AXI_STAT", CMIC_CMC1_SHARED_AXI_STATr }, \ 510 { 0x00004080, "CMIC_CMC1_SHARED_AXI_PER_ID_STAT", CMIC_CMC1_SHARED_AXI_PER_ID_STATr }, \ 511 { 0x00004084, "CMIC_CMC1_SHARED_PKT_COUNT_RXPKT", CMIC_CMC1_SHARED_PKT_COUNT_RXPKTr }, \ 512 { 0x00004088, "CMIC_CMC1_SHARED_PKT_COUNT_RXPKT_ERR", CMIC_CMC1_SHARED_PKT_COUNT_RXPKT_ERRr }, \ 513 { 0x0000408c, "CMIC_CMC1_SHARED_PKT_COUNT_TXPKT", CMIC_CMC1_SHARED_PKT_COUNT_TXPKTr }, \ 514 { 0x00004090, "CMIC_CMC1_SHARED_PKT_COUNT_TXPKT_ERR", CMIC_CMC1_SHARED_PKT_COUNT_TXPKT_ERRr }, \ 515 { 0x00004094, "CMIC_CMC1_SHARED_AXI_AR_COUNT_TX", CMIC_CMC1_SHARED_AXI_AR_COUNT_TXr }, \ 516 { 0x00004098, "CMIC_CMC1_SHARED_AXI_AR_COUNT_SPLIT_TX", CMIC_CMC1_SHARED_AXI_AR_COUNT_SPLIT_TXr }, \ 517 { 0x00005000, "CMIC_CMC1_SHARED_TXBUF_MAX_BUF_LIMITS", CMIC_CMC1_SHARED_TXBUF_MAX_BUF_LIMITSr }, \ 518 { 0x00005004, "CMIC_CMC1_SHARED_TXBUF_MIN_BUF_LIMITS", CMIC_CMC1_SHARED_TXBUF_MIN_BUF_LIMITSr }, \ 519 { 0x00005008, "CMIC_CMC1_SHARED_TXBUF_RD_THRESHOLD_CONFIG", CMIC_CMC1_SHARED_TXBUF_RD_THRESHOLD_CONFIGr }, \ 520 { 0x0000500c, "CMIC_CMC1_SHARED_TXBUF_RD_WRR_ARB_CTRL", CMIC_CMC1_SHARED_TXBUF_RD_WRR_ARB_CTRLr }, \ 521 { 0x00005010, "CMIC_CMC1_SHARED_TXBUF_SLICE3_PKT_CNT", CMIC_CMC1_SHARED_TXBUF_SLICE3_PKT_CNTr }, \ 522 { 0x00005014, "CMIC_CMC1_SHARED_TXBUF_SLICE2_PKT_CNT", CMIC_CMC1_SHARED_TXBUF_SLICE2_PKT_CNTr }, \ 523 { 0x00005018, "CMIC_CMC1_SHARED_TXBUF_SLICE1_PKT_CNT", CMIC_CMC1_SHARED_TXBUF_SLICE1_PKT_CNTr }, \ 524 { 0x0000501c, "CMIC_CMC1_SHARED_TXBUF_SLICE0_PKT_CNT", CMIC_CMC1_SHARED_TXBUF_SLICE0_PKT_CNTr }, \ 525 { 0x00005020, "CMIC_CMC1_SHARED_TXBUF_DEBUG", CMIC_CMC1_SHARED_TXBUF_DEBUGr }, \ 526 { 0x00005024, "CMIC_CMC1_SHARED_TXBUF_DATABUF_NUM_FREE_ENTRIES", CMIC_CMC1_SHARED_TXBUF_DATABUF_NUM_FREE_ENTRIESr }, \ 527 { 0x00005028, "CMIC_CMC1_SHARED_TXBUF_DATABUF_MAX_FLIST_ENTRIES", CMIC_CMC1_SHARED_TXBUF_DATABUF_MAX_FLIST_ENTRIESr }, \ 528 { 0x0000502c, "CMIC_CMC1_SHARED_TXBUF_ECC_STATUS", CMIC_CMC1_SHARED_TXBUF_ECC_STATUSr }, \ 529 { 0x00005030, "CMIC_CMC1_SHARED_TXBUF_ECC_STATUS_CLR", CMIC_CMC1_SHARED_TXBUF_ECC_STATUS_CLRr }, \ 530 { 0x00005034, "CMIC_CMC1_SHARED_TXBUF_ECC_CONTROL", CMIC_CMC1_SHARED_TXBUF_ECC_CONTROLr }, \ 531 { 0x00005038, "CMIC_CMC1_SHARED_TXBUF_TM_CONTROL", CMIC_CMC1_SHARED_TXBUF_TM_CONTROLr }, \ 532 { 0x00005080, "CMIC_CMC1_SHARED_RXBUF_DATABUF_MAX_FLIST_ENTRIES", CMIC_CMC1_SHARED_RXBUF_DATABUF_MAX_FLIST_ENTRIESr }, \ 533 { 0x00005084, "CMIC_CMC1_SHARED_RXBUF_DATABUF_NUM_FREE_ENTRIES", CMIC_CMC1_SHARED_RXBUF_DATABUF_NUM_FREE_ENTRIESr }, \ 534 { 0x00005088, "CMIC_CMC1_SHARED_RXBUF_BLOCK_DATABUF_ALLOC", CMIC_CMC1_SHARED_RXBUF_BLOCK_DATABUF_ALLOCr }, \ 535 { 0x0000508c, "CMIC_CMC1_SHARED_RXBUF_CONFIG", CMIC_CMC1_SHARED_RXBUF_CONFIGr }, \ 536 { 0x00005090, "CMIC_CMC1_SHARED_RXBUF_ECC_CONTROL", CMIC_CMC1_SHARED_RXBUF_ECC_CONTROLr }, \ 537 { 0x00005094, "CMIC_CMC1_SHARED_RXBUF_TM_CONTROL", CMIC_CMC1_SHARED_RXBUF_TM_CONTROLr }, \ 538 { 0x00005098, "CMIC_CMC1_SHARED_RXBUF_ECC_STATUS", CMIC_CMC1_SHARED_RXBUF_ECC_STATUSr }, \ 539 { 0x0000509c, "CMIC_CMC1_SHARED_RXBUF_ECC_STATUS_CLR", CMIC_CMC1_SHARED_RXBUF_ECC_STATUS_CLRr }, \ 540 { 0x00005100, "CMIC_CMC1_PKTDMA_CH0_CTRL", CMIC_CMC1_PKTDMA_CH0_CTRLr }, \ 541 { 0x00005104, "CMIC_CMC1_PKTDMA_CH0_DESC_ADDR_LO", CMIC_CMC1_PKTDMA_CH0_DESC_ADDR_LOr }, \ 542 { 0x00005108, "CMIC_CMC1_PKTDMA_CH0_DESC_ADDR_HI", CMIC_CMC1_PKTDMA_CH0_DESC_ADDR_HIr }, \ 543 { 0x0000510c, "CMIC_CMC1_PKTDMA_CH0_DESC_HALT_ADDR_LO", CMIC_CMC1_PKTDMA_CH0_DESC_HALT_ADDR_LOr }, \ 544 { 0x00005110, "CMIC_CMC1_PKTDMA_CH0_DESC_HALT_ADDR_HI", CMIC_CMC1_PKTDMA_CH0_DESC_HALT_ADDR_HIr }, \ 545 { 0x00005114, "CMIC_CMC1_PKTDMA_CH0_STAT", CMIC_CMC1_PKTDMA_CH0_STATr }, \ 546 { 0x00005118, "CMIC_CMC1_PKTDMA_CH0_COS_CTRL_RX_0", CMIC_CMC1_PKTDMA_CH0_COS_CTRL_RX_0r }, \ 547 { 0x0000511c, "CMIC_CMC1_PKTDMA_CH0_COS_CTRL_RX_1", CMIC_CMC1_PKTDMA_CH0_COS_CTRL_RX_1r }, \ 548 { 0x00005120, "CMIC_CMC1_PKTDMA_CH0_INTR_COAL", CMIC_CMC1_PKTDMA_CH0_INTR_COALr }, \ 549 { 0x00005124, "CMIC_CMC1_PKTDMA_CH0_CURR_DESC_LO", CMIC_CMC1_PKTDMA_CH0_CURR_DESC_LOr }, \ 550 { 0x00005128, "CMIC_CMC1_PKTDMA_CH0_CURR_DESC_HI", CMIC_CMC1_PKTDMA_CH0_CURR_DESC_HIr }, \ 551 { 0x0000512c, "CMIC_CMC1_PKTDMA_CH0_RXBUF_THRESHOLD_CONFIG", CMIC_CMC1_PKTDMA_CH0_RXBUF_THRESHOLD_CONFIGr }, \ 552 { 0x00005130, "CMIC_CMC1_PKTDMA_CH0_DEBUG_CONTROL", CMIC_CMC1_PKTDMA_CH0_DEBUG_CONTROLr }, \ 553 { 0x00005134, "CMIC_CMC1_PKTDMA_CH0_DEBUG_SM_STATUS", CMIC_CMC1_PKTDMA_CH0_DEBUG_SM_STATUSr }, \ 554 { 0x00005138, "CMIC_CMC1_PKTDMA_CH0_DEBUG_STATUS", CMIC_CMC1_PKTDMA_CH0_DEBUG_STATUSr }, \ 555 { 0x0000513c, "CMIC_CMC1_PKTDMA_CH0_PKT_COUNT_RXPKT", CMIC_CMC1_PKTDMA_CH0_PKT_COUNT_RXPKTr }, \ 556 { 0x00005140, "CMIC_CMC1_PKTDMA_CH0_PKT_COUNT_TXPKT", CMIC_CMC1_PKTDMA_CH0_PKT_COUNT_TXPKTr }, \ 557 { 0x00005144, "CMIC_CMC1_PKTDMA_CH0_PKT_COUNT_RXPKT_DROP", CMIC_CMC1_PKTDMA_CH0_PKT_COUNT_RXPKT_DROPr }, \ 558 { 0x00005148, "CMIC_CMC1_PKTDMA_CH0_DESC_COUNT_REQ", CMIC_CMC1_PKTDMA_CH0_DESC_COUNT_REQr }, \ 559 { 0x0000514c, "CMIC_CMC1_PKTDMA_CH0_DESC_COUNT_RX", CMIC_CMC1_PKTDMA_CH0_DESC_COUNT_RXr }, \ 560 { 0x00005150, "CMIC_CMC1_PKTDMA_CH0_DESC_COUNT_STATUS_WR", CMIC_CMC1_PKTDMA_CH0_DESC_COUNT_STATUS_WRr }, \ 561 { 0x00005154, "CMIC_CMC1_PKTDMA_CH0_DESC_MEM_ECC_STATUS", CMIC_CMC1_PKTDMA_CH0_DESC_MEM_ECC_STATUSr }, \ 562 { 0x00005158, "CMIC_CMC1_PKTDMA_CH0_DESC_MEM_ECC_CONTROL", CMIC_CMC1_PKTDMA_CH0_DESC_MEM_ECC_CONTROLr }, \ 563 { 0x0000515c, "CMIC_CMC1_PKTDMA_CH0_DESC_MEM_TM_CONTROL", CMIC_CMC1_PKTDMA_CH0_DESC_MEM_TM_CONTROLr }, \ 564 { 0x00005180, "CMIC_CMC1_PKTDMA_CH1_CTRL", CMIC_CMC1_PKTDMA_CH1_CTRLr }, \ 565 { 0x00005184, "CMIC_CMC1_PKTDMA_CH1_DESC_ADDR_LO", CMIC_CMC1_PKTDMA_CH1_DESC_ADDR_LOr }, \ 566 { 0x00005188, "CMIC_CMC1_PKTDMA_CH1_DESC_ADDR_HI", CMIC_CMC1_PKTDMA_CH1_DESC_ADDR_HIr }, \ 567 { 0x0000518c, "CMIC_CMC1_PKTDMA_CH1_DESC_HALT_ADDR_LO", CMIC_CMC1_PKTDMA_CH1_DESC_HALT_ADDR_LOr }, \ 568 { 0x00005190, "CMIC_CMC1_PKTDMA_CH1_DESC_HALT_ADDR_HI", CMIC_CMC1_PKTDMA_CH1_DESC_HALT_ADDR_HIr }, \ 569 { 0x00005194, "CMIC_CMC1_PKTDMA_CH1_STAT", CMIC_CMC1_PKTDMA_CH1_STATr }, \ 570 { 0x00005198, "CMIC_CMC1_PKTDMA_CH1_COS_CTRL_RX_0", CMIC_CMC1_PKTDMA_CH1_COS_CTRL_RX_0r }, \ 571 { 0x0000519c, "CMIC_CMC1_PKTDMA_CH1_COS_CTRL_RX_1", CMIC_CMC1_PKTDMA_CH1_COS_CTRL_RX_1r }, \ 572 { 0x000051a0, "CMIC_CMC1_PKTDMA_CH1_INTR_COAL", CMIC_CMC1_PKTDMA_CH1_INTR_COALr }, \ 573 { 0x000051a4, "CMIC_CMC1_PKTDMA_CH1_CURR_DESC_LO", CMIC_CMC1_PKTDMA_CH1_CURR_DESC_LOr }, \ 574 { 0x000051a8, "CMIC_CMC1_PKTDMA_CH1_CURR_DESC_HI", CMIC_CMC1_PKTDMA_CH1_CURR_DESC_HIr }, \ 575 { 0x000051ac, "CMIC_CMC1_PKTDMA_CH1_RXBUF_THRESHOLD_CONFIG", CMIC_CMC1_PKTDMA_CH1_RXBUF_THRESHOLD_CONFIGr }, \ 576 { 0x000051b0, "CMIC_CMC1_PKTDMA_CH1_DEBUG_CONTROL", CMIC_CMC1_PKTDMA_CH1_DEBUG_CONTROLr }, \ 577 { 0x000051b4, "CMIC_CMC1_PKTDMA_CH1_DEBUG_SM_STATUS", CMIC_CMC1_PKTDMA_CH1_DEBUG_SM_STATUSr }, \ 578 { 0x000051b8, "CMIC_CMC1_PKTDMA_CH1_DEBUG_STATUS", CMIC_CMC1_PKTDMA_CH1_DEBUG_STATUSr }, \ 579 { 0x000051bc, "CMIC_CMC1_PKTDMA_CH1_PKT_COUNT_RXPKT", CMIC_CMC1_PKTDMA_CH1_PKT_COUNT_RXPKTr }, \ 580 { 0x000051c0, "CMIC_CMC1_PKTDMA_CH1_PKT_COUNT_TXPKT", CMIC_CMC1_PKTDMA_CH1_PKT_COUNT_TXPKTr }, \ 581 { 0x000051c4, "CMIC_CMC1_PKTDMA_CH1_PKT_COUNT_RXPKT_DROP", CMIC_CMC1_PKTDMA_CH1_PKT_COUNT_RXPKT_DROPr }, \ 582 { 0x000051c8, "CMIC_CMC1_PKTDMA_CH1_DESC_COUNT_REQ", CMIC_CMC1_PKTDMA_CH1_DESC_COUNT_REQr }, \ 583 { 0x000051cc, "CMIC_CMC1_PKTDMA_CH1_DESC_COUNT_RX", CMIC_CMC1_PKTDMA_CH1_DESC_COUNT_RXr }, \ 584 { 0x000051d0, "CMIC_CMC1_PKTDMA_CH1_DESC_COUNT_STATUS_WR", CMIC_CMC1_PKTDMA_CH1_DESC_COUNT_STATUS_WRr }, \ 585 { 0x000051d4, "CMIC_CMC1_PKTDMA_CH1_DESC_MEM_ECC_STATUS", CMIC_CMC1_PKTDMA_CH1_DESC_MEM_ECC_STATUSr }, \ 586 { 0x000051d8, "CMIC_CMC1_PKTDMA_CH1_DESC_MEM_ECC_CONTROL", CMIC_CMC1_PKTDMA_CH1_DESC_MEM_ECC_CONTROLr }, \ 587 { 0x000051dc, "CMIC_CMC1_PKTDMA_CH1_DESC_MEM_TM_CONTROL", CMIC_CMC1_PKTDMA_CH1_DESC_MEM_TM_CONTROLr }, \ 588 { 0x00005200, "CMIC_CMC1_PKTDMA_CH2_CTRL", CMIC_CMC1_PKTDMA_CH2_CTRLr }, \ 589 { 0x00005204, "CMIC_CMC1_PKTDMA_CH2_DESC_ADDR_LO", CMIC_CMC1_PKTDMA_CH2_DESC_ADDR_LOr }, \ 590 { 0x00005208, "CMIC_CMC1_PKTDMA_CH2_DESC_ADDR_HI", CMIC_CMC1_PKTDMA_CH2_DESC_ADDR_HIr }, \ 591 { 0x0000520c, "CMIC_CMC1_PKTDMA_CH2_DESC_HALT_ADDR_LO", CMIC_CMC1_PKTDMA_CH2_DESC_HALT_ADDR_LOr }, \ 592 { 0x00005210, "CMIC_CMC1_PKTDMA_CH2_DESC_HALT_ADDR_HI", CMIC_CMC1_PKTDMA_CH2_DESC_HALT_ADDR_HIr }, \ 593 { 0x00005214, "CMIC_CMC1_PKTDMA_CH2_STAT", CMIC_CMC1_PKTDMA_CH2_STATr }, \ 594 { 0x00005218, "CMIC_CMC1_PKTDMA_CH2_COS_CTRL_RX_0", CMIC_CMC1_PKTDMA_CH2_COS_CTRL_RX_0r }, \ 595 { 0x0000521c, "CMIC_CMC1_PKTDMA_CH2_COS_CTRL_RX_1", CMIC_CMC1_PKTDMA_CH2_COS_CTRL_RX_1r }, \ 596 { 0x00005220, "CMIC_CMC1_PKTDMA_CH2_INTR_COAL", CMIC_CMC1_PKTDMA_CH2_INTR_COALr }, \ 597 { 0x00005224, "CMIC_CMC1_PKTDMA_CH2_CURR_DESC_LO", CMIC_CMC1_PKTDMA_CH2_CURR_DESC_LOr }, \ 598 { 0x00005228, "CMIC_CMC1_PKTDMA_CH2_CURR_DESC_HI", CMIC_CMC1_PKTDMA_CH2_CURR_DESC_HIr }, \ 599 { 0x0000522c, "CMIC_CMC1_PKTDMA_CH2_RXBUF_THRESHOLD_CONFIG", CMIC_CMC1_PKTDMA_CH2_RXBUF_THRESHOLD_CONFIGr }, \ 600 { 0x00005230, "CMIC_CMC1_PKTDMA_CH2_DEBUG_CONTROL", CMIC_CMC1_PKTDMA_CH2_DEBUG_CONTROLr }, \ 601 { 0x00005234, "CMIC_CMC1_PKTDMA_CH2_DEBUG_SM_STATUS", CMIC_CMC1_PKTDMA_CH2_DEBUG_SM_STATUSr }, \ 602 { 0x00005238, "CMIC_CMC1_PKTDMA_CH2_DEBUG_STATUS", CMIC_CMC1_PKTDMA_CH2_DEBUG_STATUSr }, \ 603 { 0x0000523c, "CMIC_CMC1_PKTDMA_CH2_PKT_COUNT_RXPKT", CMIC_CMC1_PKTDMA_CH2_PKT_COUNT_RXPKTr }, \ 604 { 0x00005240, "CMIC_CMC1_PKTDMA_CH2_PKT_COUNT_TXPKT", CMIC_CMC1_PKTDMA_CH2_PKT_COUNT_TXPKTr }, \ 605 { 0x00005244, "CMIC_CMC1_PKTDMA_CH2_PKT_COUNT_RXPKT_DROP", CMIC_CMC1_PKTDMA_CH2_PKT_COUNT_RXPKT_DROPr }, \ 606 { 0x00005248, "CMIC_CMC1_PKTDMA_CH2_DESC_COUNT_REQ", CMIC_CMC1_PKTDMA_CH2_DESC_COUNT_REQr }, \ 607 { 0x0000524c, "CMIC_CMC1_PKTDMA_CH2_DESC_COUNT_RX", CMIC_CMC1_PKTDMA_CH2_DESC_COUNT_RXr }, \ 608 { 0x00005250, "CMIC_CMC1_PKTDMA_CH2_DESC_COUNT_STATUS_WR", CMIC_CMC1_PKTDMA_CH2_DESC_COUNT_STATUS_WRr }, \ 609 { 0x00005254, "CMIC_CMC1_PKTDMA_CH2_DESC_MEM_ECC_STATUS", CMIC_CMC1_PKTDMA_CH2_DESC_MEM_ECC_STATUSr }, \ 610 { 0x00005258, "CMIC_CMC1_PKTDMA_CH2_DESC_MEM_ECC_CONTROL", CMIC_CMC1_PKTDMA_CH2_DESC_MEM_ECC_CONTROLr }, \ 611 { 0x0000525c, "CMIC_CMC1_PKTDMA_CH2_DESC_MEM_TM_CONTROL", CMIC_CMC1_PKTDMA_CH2_DESC_MEM_TM_CONTROLr }, \ 612 { 0x00005280, "CMIC_CMC1_PKTDMA_CH3_CTRL", CMIC_CMC1_PKTDMA_CH3_CTRLr }, \ 613 { 0x00005284, "CMIC_CMC1_PKTDMA_CH3_DESC_ADDR_LO", CMIC_CMC1_PKTDMA_CH3_DESC_ADDR_LOr }, \ 614 { 0x00005288, "CMIC_CMC1_PKTDMA_CH3_DESC_ADDR_HI", CMIC_CMC1_PKTDMA_CH3_DESC_ADDR_HIr }, \ 615 { 0x0000528c, "CMIC_CMC1_PKTDMA_CH3_DESC_HALT_ADDR_LO", CMIC_CMC1_PKTDMA_CH3_DESC_HALT_ADDR_LOr }, \ 616 { 0x00005290, "CMIC_CMC1_PKTDMA_CH3_DESC_HALT_ADDR_HI", CMIC_CMC1_PKTDMA_CH3_DESC_HALT_ADDR_HIr }, \ 617 { 0x00005294, "CMIC_CMC1_PKTDMA_CH3_STAT", CMIC_CMC1_PKTDMA_CH3_STATr }, \ 618 { 0x00005298, "CMIC_CMC1_PKTDMA_CH3_COS_CTRL_RX_0", CMIC_CMC1_PKTDMA_CH3_COS_CTRL_RX_0r }, \ 619 { 0x0000529c, "CMIC_CMC1_PKTDMA_CH3_COS_CTRL_RX_1", CMIC_CMC1_PKTDMA_CH3_COS_CTRL_RX_1r }, \ 620 { 0x000052a0, "CMIC_CMC1_PKTDMA_CH3_INTR_COAL", CMIC_CMC1_PKTDMA_CH3_INTR_COALr }, \ 621 { 0x000052a4, "CMIC_CMC1_PKTDMA_CH3_CURR_DESC_LO", CMIC_CMC1_PKTDMA_CH3_CURR_DESC_LOr }, \ 622 { 0x000052a8, "CMIC_CMC1_PKTDMA_CH3_CURR_DESC_HI", CMIC_CMC1_PKTDMA_CH3_CURR_DESC_HIr }, \ 623 { 0x000052ac, "CMIC_CMC1_PKTDMA_CH3_RXBUF_THRESHOLD_CONFIG", CMIC_CMC1_PKTDMA_CH3_RXBUF_THRESHOLD_CONFIGr }, \ 624 { 0x000052b0, "CMIC_CMC1_PKTDMA_CH3_DEBUG_CONTROL", CMIC_CMC1_PKTDMA_CH3_DEBUG_CONTROLr }, \ 625 { 0x000052b4, "CMIC_CMC1_PKTDMA_CH3_DEBUG_SM_STATUS", CMIC_CMC1_PKTDMA_CH3_DEBUG_SM_STATUSr }, \ 626 { 0x000052b8, "CMIC_CMC1_PKTDMA_CH3_DEBUG_STATUS", CMIC_CMC1_PKTDMA_CH3_DEBUG_STATUSr }, \ 627 { 0x000052bc, "CMIC_CMC1_PKTDMA_CH3_PKT_COUNT_RXPKT", CMIC_CMC1_PKTDMA_CH3_PKT_COUNT_RXPKTr }, \ 628 { 0x000052c0, "CMIC_CMC1_PKTDMA_CH3_PKT_COUNT_TXPKT", CMIC_CMC1_PKTDMA_CH3_PKT_COUNT_TXPKTr }, \ 629 { 0x000052c4, "CMIC_CMC1_PKTDMA_CH3_PKT_COUNT_RXPKT_DROP", CMIC_CMC1_PKTDMA_CH3_PKT_COUNT_RXPKT_DROPr }, \ 630 { 0x000052c8, "CMIC_CMC1_PKTDMA_CH3_DESC_COUNT_REQ", CMIC_CMC1_PKTDMA_CH3_DESC_COUNT_REQr }, \ 631 { 0x000052cc, "CMIC_CMC1_PKTDMA_CH3_DESC_COUNT_RX", CMIC_CMC1_PKTDMA_CH3_DESC_COUNT_RXr }, \ 632 { 0x000052d0, "CMIC_CMC1_PKTDMA_CH3_DESC_COUNT_STATUS_WR", CMIC_CMC1_PKTDMA_CH3_DESC_COUNT_STATUS_WRr }, \ 633 { 0x000052d4, "CMIC_CMC1_PKTDMA_CH3_DESC_MEM_ECC_STATUS", CMIC_CMC1_PKTDMA_CH3_DESC_MEM_ECC_STATUSr }, \ 634 { 0x000052d8, "CMIC_CMC1_PKTDMA_CH3_DESC_MEM_ECC_CONTROL", CMIC_CMC1_PKTDMA_CH3_DESC_MEM_ECC_CONTROLr }, \ 635 { 0x000052dc, "CMIC_CMC1_PKTDMA_CH3_DESC_MEM_TM_CONTROL", CMIC_CMC1_PKTDMA_CH3_DESC_MEM_TM_CONTROLr }, \ 636 { 0x00005300, "CMIC_CMC1_PKTDMA_CH4_CTRL", CMIC_CMC1_PKTDMA_CH4_CTRLr }, \ 637 { 0x00005304, "CMIC_CMC1_PKTDMA_CH4_DESC_ADDR_LO", CMIC_CMC1_PKTDMA_CH4_DESC_ADDR_LOr }, \ 638 { 0x00005308, "CMIC_CMC1_PKTDMA_CH4_DESC_ADDR_HI", CMIC_CMC1_PKTDMA_CH4_DESC_ADDR_HIr }, \ 639 { 0x0000530c, "CMIC_CMC1_PKTDMA_CH4_DESC_HALT_ADDR_LO", CMIC_CMC1_PKTDMA_CH4_DESC_HALT_ADDR_LOr }, \ 640 { 0x00005310, "CMIC_CMC1_PKTDMA_CH4_DESC_HALT_ADDR_HI", CMIC_CMC1_PKTDMA_CH4_DESC_HALT_ADDR_HIr }, \ 641 { 0x00005314, "CMIC_CMC1_PKTDMA_CH4_STAT", CMIC_CMC1_PKTDMA_CH4_STATr }, \ 642 { 0x00005318, "CMIC_CMC1_PKTDMA_CH4_COS_CTRL_RX_0", CMIC_CMC1_PKTDMA_CH4_COS_CTRL_RX_0r }, \ 643 { 0x0000531c, "CMIC_CMC1_PKTDMA_CH4_COS_CTRL_RX_1", CMIC_CMC1_PKTDMA_CH4_COS_CTRL_RX_1r }, \ 644 { 0x00005320, "CMIC_CMC1_PKTDMA_CH4_INTR_COAL", CMIC_CMC1_PKTDMA_CH4_INTR_COALr }, \ 645 { 0x00005324, "CMIC_CMC1_PKTDMA_CH4_CURR_DESC_LO", CMIC_CMC1_PKTDMA_CH4_CURR_DESC_LOr }, \ 646 { 0x00005328, "CMIC_CMC1_PKTDMA_CH4_CURR_DESC_HI", CMIC_CMC1_PKTDMA_CH4_CURR_DESC_HIr }, \ 647 { 0x0000532c, "CMIC_CMC1_PKTDMA_CH4_RXBUF_THRESHOLD_CONFIG", CMIC_CMC1_PKTDMA_CH4_RXBUF_THRESHOLD_CONFIGr }, \ 648 { 0x00005330, "CMIC_CMC1_PKTDMA_CH4_DEBUG_CONTROL", CMIC_CMC1_PKTDMA_CH4_DEBUG_CONTROLr }, \ 649 { 0x00005334, "CMIC_CMC1_PKTDMA_CH4_DEBUG_SM_STATUS", CMIC_CMC1_PKTDMA_CH4_DEBUG_SM_STATUSr }, \ 650 { 0x00005338, "CMIC_CMC1_PKTDMA_CH4_DEBUG_STATUS", CMIC_CMC1_PKTDMA_CH4_DEBUG_STATUSr }, \ 651 { 0x0000533c, "CMIC_CMC1_PKTDMA_CH4_PKT_COUNT_RXPKT", CMIC_CMC1_PKTDMA_CH4_PKT_COUNT_RXPKTr }, \ 652 { 0x00005340, "CMIC_CMC1_PKTDMA_CH4_PKT_COUNT_TXPKT", CMIC_CMC1_PKTDMA_CH4_PKT_COUNT_TXPKTr }, \ 653 { 0x00005344, "CMIC_CMC1_PKTDMA_CH4_PKT_COUNT_RXPKT_DROP", CMIC_CMC1_PKTDMA_CH4_PKT_COUNT_RXPKT_DROPr }, \ 654 { 0x00005348, "CMIC_CMC1_PKTDMA_CH4_DESC_COUNT_REQ", CMIC_CMC1_PKTDMA_CH4_DESC_COUNT_REQr }, \ 655 { 0x0000534c, "CMIC_CMC1_PKTDMA_CH4_DESC_COUNT_RX", CMIC_CMC1_PKTDMA_CH4_DESC_COUNT_RXr }, \ 656 { 0x00005350, "CMIC_CMC1_PKTDMA_CH4_DESC_COUNT_STATUS_WR", CMIC_CMC1_PKTDMA_CH4_DESC_COUNT_STATUS_WRr }, \ 657 { 0x00005354, "CMIC_CMC1_PKTDMA_CH4_DESC_MEM_ECC_STATUS", CMIC_CMC1_PKTDMA_CH4_DESC_MEM_ECC_STATUSr }, \ 658 { 0x00005358, "CMIC_CMC1_PKTDMA_CH4_DESC_MEM_ECC_CONTROL", CMIC_CMC1_PKTDMA_CH4_DESC_MEM_ECC_CONTROLr }, \ 659 { 0x0000535c, "CMIC_CMC1_PKTDMA_CH4_DESC_MEM_TM_CONTROL", CMIC_CMC1_PKTDMA_CH4_DESC_MEM_TM_CONTROLr }, \ 660 { 0x00005380, "CMIC_CMC1_PKTDMA_CH5_CTRL", CMIC_CMC1_PKTDMA_CH5_CTRLr }, \ 661 { 0x00005384, "CMIC_CMC1_PKTDMA_CH5_DESC_ADDR_LO", CMIC_CMC1_PKTDMA_CH5_DESC_ADDR_LOr }, \ 662 { 0x00005388, "CMIC_CMC1_PKTDMA_CH5_DESC_ADDR_HI", CMIC_CMC1_PKTDMA_CH5_DESC_ADDR_HIr }, \ 663 { 0x0000538c, "CMIC_CMC1_PKTDMA_CH5_DESC_HALT_ADDR_LO", CMIC_CMC1_PKTDMA_CH5_DESC_HALT_ADDR_LOr }, \ 664 { 0x00005390, "CMIC_CMC1_PKTDMA_CH5_DESC_HALT_ADDR_HI", CMIC_CMC1_PKTDMA_CH5_DESC_HALT_ADDR_HIr }, \ 665 { 0x00005394, "CMIC_CMC1_PKTDMA_CH5_STAT", CMIC_CMC1_PKTDMA_CH5_STATr }, \ 666 { 0x00005398, "CMIC_CMC1_PKTDMA_CH5_COS_CTRL_RX_0", CMIC_CMC1_PKTDMA_CH5_COS_CTRL_RX_0r }, \ 667 { 0x0000539c, "CMIC_CMC1_PKTDMA_CH5_COS_CTRL_RX_1", CMIC_CMC1_PKTDMA_CH5_COS_CTRL_RX_1r }, \ 668 { 0x000053a0, "CMIC_CMC1_PKTDMA_CH5_INTR_COAL", CMIC_CMC1_PKTDMA_CH5_INTR_COALr }, \ 669 { 0x000053a4, "CMIC_CMC1_PKTDMA_CH5_CURR_DESC_LO", CMIC_CMC1_PKTDMA_CH5_CURR_DESC_LOr }, \ 670 { 0x000053a8, "CMIC_CMC1_PKTDMA_CH5_CURR_DESC_HI", CMIC_CMC1_PKTDMA_CH5_CURR_DESC_HIr }, \ 671 { 0x000053ac, "CMIC_CMC1_PKTDMA_CH5_RXBUF_THRESHOLD_CONFIG", CMIC_CMC1_PKTDMA_CH5_RXBUF_THRESHOLD_CONFIGr }, \ 672 { 0x000053b0, "CMIC_CMC1_PKTDMA_CH5_DEBUG_CONTROL", CMIC_CMC1_PKTDMA_CH5_DEBUG_CONTROLr }, \ 673 { 0x000053b4, "CMIC_CMC1_PKTDMA_CH5_DEBUG_SM_STATUS", CMIC_CMC1_PKTDMA_CH5_DEBUG_SM_STATUSr }, \ 674 { 0x000053b8, "CMIC_CMC1_PKTDMA_CH5_DEBUG_STATUS", CMIC_CMC1_PKTDMA_CH5_DEBUG_STATUSr }, \ 675 { 0x000053bc, "CMIC_CMC1_PKTDMA_CH5_PKT_COUNT_RXPKT", CMIC_CMC1_PKTDMA_CH5_PKT_COUNT_RXPKTr }, \ 676 { 0x000053c0, "CMIC_CMC1_PKTDMA_CH5_PKT_COUNT_TXPKT", CMIC_CMC1_PKTDMA_CH5_PKT_COUNT_TXPKTr }, \ 677 { 0x000053c4, "CMIC_CMC1_PKTDMA_CH5_PKT_COUNT_RXPKT_DROP", CMIC_CMC1_PKTDMA_CH5_PKT_COUNT_RXPKT_DROPr }, \ 678 { 0x000053c8, "CMIC_CMC1_PKTDMA_CH5_DESC_COUNT_REQ", CMIC_CMC1_PKTDMA_CH5_DESC_COUNT_REQr }, \ 679 { 0x000053cc, "CMIC_CMC1_PKTDMA_CH5_DESC_COUNT_RX", CMIC_CMC1_PKTDMA_CH5_DESC_COUNT_RXr }, \ 680 { 0x000053d0, "CMIC_CMC1_PKTDMA_CH5_DESC_COUNT_STATUS_WR", CMIC_CMC1_PKTDMA_CH5_DESC_COUNT_STATUS_WRr }, \ 681 { 0x000053d4, "CMIC_CMC1_PKTDMA_CH5_DESC_MEM_ECC_STATUS", CMIC_CMC1_PKTDMA_CH5_DESC_MEM_ECC_STATUSr }, \ 682 { 0x000053d8, "CMIC_CMC1_PKTDMA_CH5_DESC_MEM_ECC_CONTROL", CMIC_CMC1_PKTDMA_CH5_DESC_MEM_ECC_CONTROLr }, \ 683 { 0x000053dc, "CMIC_CMC1_PKTDMA_CH5_DESC_MEM_TM_CONTROL", CMIC_CMC1_PKTDMA_CH5_DESC_MEM_TM_CONTROLr }, \ 684 { 0x00005400, "CMIC_CMC1_PKTDMA_CH6_CTRL", CMIC_CMC1_PKTDMA_CH6_CTRLr }, \ 685 { 0x00005404, "CMIC_CMC1_PKTDMA_CH6_DESC_ADDR_LO", CMIC_CMC1_PKTDMA_CH6_DESC_ADDR_LOr }, \ 686 { 0x00005408, "CMIC_CMC1_PKTDMA_CH6_DESC_ADDR_HI", CMIC_CMC1_PKTDMA_CH6_DESC_ADDR_HIr }, \ 687 { 0x0000540c, "CMIC_CMC1_PKTDMA_CH6_DESC_HALT_ADDR_LO", CMIC_CMC1_PKTDMA_CH6_DESC_HALT_ADDR_LOr }, \ 688 { 0x00005410, "CMIC_CMC1_PKTDMA_CH6_DESC_HALT_ADDR_HI", CMIC_CMC1_PKTDMA_CH6_DESC_HALT_ADDR_HIr }, \ 689 { 0x00005414, "CMIC_CMC1_PKTDMA_CH6_STAT", CMIC_CMC1_PKTDMA_CH6_STATr }, \ 690 { 0x00005418, "CMIC_CMC1_PKTDMA_CH6_COS_CTRL_RX_0", CMIC_CMC1_PKTDMA_CH6_COS_CTRL_RX_0r }, \ 691 { 0x0000541c, "CMIC_CMC1_PKTDMA_CH6_COS_CTRL_RX_1", CMIC_CMC1_PKTDMA_CH6_COS_CTRL_RX_1r }, \ 692 { 0x00005420, "CMIC_CMC1_PKTDMA_CH6_INTR_COAL", CMIC_CMC1_PKTDMA_CH6_INTR_COALr }, \ 693 { 0x00005424, "CMIC_CMC1_PKTDMA_CH6_CURR_DESC_LO", CMIC_CMC1_PKTDMA_CH6_CURR_DESC_LOr }, \ 694 { 0x00005428, "CMIC_CMC1_PKTDMA_CH6_CURR_DESC_HI", CMIC_CMC1_PKTDMA_CH6_CURR_DESC_HIr }, \ 695 { 0x0000542c, "CMIC_CMC1_PKTDMA_CH6_RXBUF_THRESHOLD_CONFIG", CMIC_CMC1_PKTDMA_CH6_RXBUF_THRESHOLD_CONFIGr }, \ 696 { 0x00005430, "CMIC_CMC1_PKTDMA_CH6_DEBUG_CONTROL", CMIC_CMC1_PKTDMA_CH6_DEBUG_CONTROLr }, \ 697 { 0x00005434, "CMIC_CMC1_PKTDMA_CH6_DEBUG_SM_STATUS", CMIC_CMC1_PKTDMA_CH6_DEBUG_SM_STATUSr }, \ 698 { 0x00005438, "CMIC_CMC1_PKTDMA_CH6_DEBUG_STATUS", CMIC_CMC1_PKTDMA_CH6_DEBUG_STATUSr }, \ 699 { 0x0000543c, "CMIC_CMC1_PKTDMA_CH6_PKT_COUNT_RXPKT", CMIC_CMC1_PKTDMA_CH6_PKT_COUNT_RXPKTr }, \ 700 { 0x00005440, "CMIC_CMC1_PKTDMA_CH6_PKT_COUNT_TXPKT", CMIC_CMC1_PKTDMA_CH6_PKT_COUNT_TXPKTr }, \ 701 { 0x00005444, "CMIC_CMC1_PKTDMA_CH6_PKT_COUNT_RXPKT_DROP", CMIC_CMC1_PKTDMA_CH6_PKT_COUNT_RXPKT_DROPr }, \ 702 { 0x00005448, "CMIC_CMC1_PKTDMA_CH6_DESC_COUNT_REQ", CMIC_CMC1_PKTDMA_CH6_DESC_COUNT_REQr }, \ 703 { 0x0000544c, "CMIC_CMC1_PKTDMA_CH6_DESC_COUNT_RX", CMIC_CMC1_PKTDMA_CH6_DESC_COUNT_RXr }, \ 704 { 0x00005450, "CMIC_CMC1_PKTDMA_CH6_DESC_COUNT_STATUS_WR", CMIC_CMC1_PKTDMA_CH6_DESC_COUNT_STATUS_WRr }, \ 705 { 0x00005454, "CMIC_CMC1_PKTDMA_CH6_DESC_MEM_ECC_STATUS", CMIC_CMC1_PKTDMA_CH6_DESC_MEM_ECC_STATUSr }, \ 706 { 0x00005458, "CMIC_CMC1_PKTDMA_CH6_DESC_MEM_ECC_CONTROL", CMIC_CMC1_PKTDMA_CH6_DESC_MEM_ECC_CONTROLr }, \ 707 { 0x0000545c, "CMIC_CMC1_PKTDMA_CH6_DESC_MEM_TM_CONTROL", CMIC_CMC1_PKTDMA_CH6_DESC_MEM_TM_CONTROLr }, \ 708 { 0x00005480, "CMIC_CMC1_PKTDMA_CH7_CTRL", CMIC_CMC1_PKTDMA_CH7_CTRLr }, \ 709 { 0x00005484, "CMIC_CMC1_PKTDMA_CH7_DESC_ADDR_LO", CMIC_CMC1_PKTDMA_CH7_DESC_ADDR_LOr }, \ 710 { 0x00005488, "CMIC_CMC1_PKTDMA_CH7_DESC_ADDR_HI", CMIC_CMC1_PKTDMA_CH7_DESC_ADDR_HIr }, \ 711 { 0x0000548c, "CMIC_CMC1_PKTDMA_CH7_DESC_HALT_ADDR_LO", CMIC_CMC1_PKTDMA_CH7_DESC_HALT_ADDR_LOr }, \ 712 { 0x00005490, "CMIC_CMC1_PKTDMA_CH7_DESC_HALT_ADDR_HI", CMIC_CMC1_PKTDMA_CH7_DESC_HALT_ADDR_HIr }, \ 713 { 0x00005494, "CMIC_CMC1_PKTDMA_CH7_STAT", CMIC_CMC1_PKTDMA_CH7_STATr }, \ 714 { 0x00005498, "CMIC_CMC1_PKTDMA_CH7_COS_CTRL_RX_0", CMIC_CMC1_PKTDMA_CH7_COS_CTRL_RX_0r }, \ 715 { 0x0000549c, "CMIC_CMC1_PKTDMA_CH7_COS_CTRL_RX_1", CMIC_CMC1_PKTDMA_CH7_COS_CTRL_RX_1r }, \ 716 { 0x000054a0, "CMIC_CMC1_PKTDMA_CH7_INTR_COAL", CMIC_CMC1_PKTDMA_CH7_INTR_COALr }, \ 717 { 0x000054a4, "CMIC_CMC1_PKTDMA_CH7_CURR_DESC_LO", CMIC_CMC1_PKTDMA_CH7_CURR_DESC_LOr }, \ 718 { 0x000054a8, "CMIC_CMC1_PKTDMA_CH7_CURR_DESC_HI", CMIC_CMC1_PKTDMA_CH7_CURR_DESC_HIr }, \ 719 { 0x000054ac, "CMIC_CMC1_PKTDMA_CH7_RXBUF_THRESHOLD_CONFIG", CMIC_CMC1_PKTDMA_CH7_RXBUF_THRESHOLD_CONFIGr }, \ 720 { 0x000054b0, "CMIC_CMC1_PKTDMA_CH7_DEBUG_CONTROL", CMIC_CMC1_PKTDMA_CH7_DEBUG_CONTROLr }, \ 721 { 0x000054b4, "CMIC_CMC1_PKTDMA_CH7_DEBUG_SM_STATUS", CMIC_CMC1_PKTDMA_CH7_DEBUG_SM_STATUSr }, \ 722 { 0x000054b8, "CMIC_CMC1_PKTDMA_CH7_DEBUG_STATUS", CMIC_CMC1_PKTDMA_CH7_DEBUG_STATUSr }, \ 723 { 0x000054bc, "CMIC_CMC1_PKTDMA_CH7_PKT_COUNT_RXPKT", CMIC_CMC1_PKTDMA_CH7_PKT_COUNT_RXPKTr }, \ 724 { 0x000054c0, "CMIC_CMC1_PKTDMA_CH7_PKT_COUNT_TXPKT", CMIC_CMC1_PKTDMA_CH7_PKT_COUNT_TXPKTr }, \ 725 { 0x000054c4, "CMIC_CMC1_PKTDMA_CH7_PKT_COUNT_RXPKT_DROP", CMIC_CMC1_PKTDMA_CH7_PKT_COUNT_RXPKT_DROPr }, \ 726 { 0x000054c8, "CMIC_CMC1_PKTDMA_CH7_DESC_COUNT_REQ", CMIC_CMC1_PKTDMA_CH7_DESC_COUNT_REQr }, \ 727 { 0x000054cc, "CMIC_CMC1_PKTDMA_CH7_DESC_COUNT_RX", CMIC_CMC1_PKTDMA_CH7_DESC_COUNT_RXr }, \ 728 { 0x000054d0, "CMIC_CMC1_PKTDMA_CH7_DESC_COUNT_STATUS_WR", CMIC_CMC1_PKTDMA_CH7_DESC_COUNT_STATUS_WRr }, \ 729 { 0x000054d4, "CMIC_CMC1_PKTDMA_CH7_DESC_MEM_ECC_STATUS", CMIC_CMC1_PKTDMA_CH7_DESC_MEM_ECC_STATUSr }, \ 730 { 0x000054d8, "CMIC_CMC1_PKTDMA_CH7_DESC_MEM_ECC_CONTROL", CMIC_CMC1_PKTDMA_CH7_DESC_MEM_ECC_CONTROLr }, \ 731 { 0x000054dc, "CMIC_CMC1_PKTDMA_CH7_DESC_MEM_TM_CONTROL", CMIC_CMC1_PKTDMA_CH7_DESC_MEM_TM_CONTROLr }, \ 732 { 0x00006000, "CMIC_CMC1_SBUSDMA_CH0_CONTROL", CMIC_CMC1_SBUSDMA_CH0_CONTROLr }, \ 733 { 0x00006004, "CMIC_CMC1_SBUSDMA_CH0_REQUEST", CMIC_CMC1_SBUSDMA_CH0_REQUESTr }, \ 734 { 0x00006008, "CMIC_CMC1_SBUSDMA_CH0_COUNT", CMIC_CMC1_SBUSDMA_CH0_COUNTr }, \ 735 { 0x0000600c, "CMIC_CMC1_SBUSDMA_CH0_OPCODE", CMIC_CMC1_SBUSDMA_CH0_OPCODEr }, \ 736 { 0x00006010, "CMIC_CMC1_SBUSDMA_CH0_SBUS_START_ADDRESS", CMIC_CMC1_SBUSDMA_CH0_SBUS_START_ADDRESSr }, \ 737 { 0x00006014, "CMIC_CMC1_SBUSDMA_CH0_HOSTMEM_START_ADDRESS_LO", CMIC_CMC1_SBUSDMA_CH0_HOSTMEM_START_ADDRESS_LOr }, \ 738 { 0x00006018, "CMIC_CMC1_SBUSDMA_CH0_HOSTMEM_START_ADDRESS_HI", CMIC_CMC1_SBUSDMA_CH0_HOSTMEM_START_ADDRESS_HIr }, \ 739 { 0x0000601c, "CMIC_CMC1_SBUSDMA_CH0_DESC_START_ADDRESS_LO", CMIC_CMC1_SBUSDMA_CH0_DESC_START_ADDRESS_LOr }, \ 740 { 0x00006020, "CMIC_CMC1_SBUSDMA_CH0_DESC_START_ADDRESS_HI", CMIC_CMC1_SBUSDMA_CH0_DESC_START_ADDRESS_HIr }, \ 741 { 0x00006024, "CMIC_CMC1_SBUSDMA_CH0_STATUS", CMIC_CMC1_SBUSDMA_CH0_STATUSr }, \ 742 { 0x00006028, "CMIC_CMC1_SBUSDMA_CH0_CUR_HOSTMEM_ADDRESS_LO", CMIC_CMC1_SBUSDMA_CH0_CUR_HOSTMEM_ADDRESS_LOr }, \ 743 { 0x0000602c, "CMIC_CMC1_SBUSDMA_CH0_CUR_HOSTMEM_ADDRESS_HI", CMIC_CMC1_SBUSDMA_CH0_CUR_HOSTMEM_ADDRESS_HIr }, \ 744 { 0x00006030, "CMIC_CMC1_SBUSDMA_CH0_CUR_SBUS_ADDRESS", CMIC_CMC1_SBUSDMA_CH0_CUR_SBUS_ADDRESSr }, \ 745 { 0x00006034, "CMIC_CMC1_SBUSDMA_CH0_CUR_DESC_ADDRESS_LO", CMIC_CMC1_SBUSDMA_CH0_CUR_DESC_ADDRESS_LOr }, \ 746 { 0x00006038, "CMIC_CMC1_SBUSDMA_CH0_CUR_DESC_ADDRESS_HI", CMIC_CMC1_SBUSDMA_CH0_CUR_DESC_ADDRESS_HIr }, \ 747 { 0x0000603c, "CMIC_CMC1_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_REQUEST", CMIC_CMC1_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_REQUESTr }, \ 748 { 0x00006040, "CMIC_CMC1_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_OPCODE", CMIC_CMC1_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_OPCODEr }, \ 749 { 0x00006044, "CMIC_CMC1_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_SBUS_START_ADDRESS", CMIC_CMC1_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_SBUS_START_ADDRESSr }, \ 750 { 0x00006048, "CMIC_CMC1_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_LO", CMIC_CMC1_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_LOr }, \ 751 { 0x0000604c, "CMIC_CMC1_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_HI", CMIC_CMC1_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_HIr }, \ 752 { 0x00006050, "CMIC_CMC1_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_COUNT", CMIC_CMC1_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_COUNTr }, \ 753 { 0x00006054, "CMIC_CMC1_SBUSDMA_CH0_SBUSDMA_DEBUG", CMIC_CMC1_SBUSDMA_CH0_SBUSDMA_DEBUGr }, \ 754 { 0x00006058, "CMIC_CMC1_SBUSDMA_CH0_SBUSDMA_DEBUG_CLR", CMIC_CMC1_SBUSDMA_CH0_SBUSDMA_DEBUG_CLRr }, \ 755 { 0x0000605c, "CMIC_CMC1_SBUSDMA_CH0_SBUSDMA_ECCERR_ADDRESS_LO", CMIC_CMC1_SBUSDMA_CH0_SBUSDMA_ECCERR_ADDRESS_LOr }, \ 756 { 0x00006060, "CMIC_CMC1_SBUSDMA_CH0_SBUSDMA_ECCERR_ADDRESS_HI", CMIC_CMC1_SBUSDMA_CH0_SBUSDMA_ECCERR_ADDRESS_HIr }, \ 757 { 0x00006064, "CMIC_CMC1_SBUSDMA_CH0_ECC_CONTROL", CMIC_CMC1_SBUSDMA_CH0_ECC_CONTROLr }, \ 758 { 0x00006068, "CMIC_CMC1_SBUSDMA_CH0_ECC_STATUS", CMIC_CMC1_SBUSDMA_CH0_ECC_STATUSr }, \ 759 { 0x0000606c, "CMIC_CMC1_SBUSDMA_CH0_ECC_STATUS_CLR", CMIC_CMC1_SBUSDMA_CH0_ECC_STATUS_CLRr }, \ 760 { 0x00006070, "CMIC_CMC1_SBUSDMA_CH0_TIMER", CMIC_CMC1_SBUSDMA_CH0_TIMERr }, \ 761 { 0x00006074, "CMIC_CMC1_SBUSDMA_CH0_ITER_COUNT", CMIC_CMC1_SBUSDMA_CH0_ITER_COUNTr }, \ 762 { 0x00006078, "CMIC_CMC1_SBUSDMA_CH0_TM_CONTROL", CMIC_CMC1_SBUSDMA_CH0_TM_CONTROLr }, \ 763 { 0x00006100, "CMIC_CMC1_SBUSDMA_CH1_CONTROL", CMIC_CMC1_SBUSDMA_CH1_CONTROLr }, \ 764 { 0x00006104, "CMIC_CMC1_SBUSDMA_CH1_REQUEST", CMIC_CMC1_SBUSDMA_CH1_REQUESTr }, \ 765 { 0x00006108, "CMIC_CMC1_SBUSDMA_CH1_COUNT", CMIC_CMC1_SBUSDMA_CH1_COUNTr }, \ 766 { 0x0000610c, "CMIC_CMC1_SBUSDMA_CH1_OPCODE", CMIC_CMC1_SBUSDMA_CH1_OPCODEr }, \ 767 { 0x00006110, "CMIC_CMC1_SBUSDMA_CH1_SBUS_START_ADDRESS", CMIC_CMC1_SBUSDMA_CH1_SBUS_START_ADDRESSr }, \ 768 { 0x00006114, "CMIC_CMC1_SBUSDMA_CH1_HOSTMEM_START_ADDRESS_LO", CMIC_CMC1_SBUSDMA_CH1_HOSTMEM_START_ADDRESS_LOr }, \ 769 { 0x00006118, "CMIC_CMC1_SBUSDMA_CH1_HOSTMEM_START_ADDRESS_HI", CMIC_CMC1_SBUSDMA_CH1_HOSTMEM_START_ADDRESS_HIr }, \ 770 { 0x0000611c, "CMIC_CMC1_SBUSDMA_CH1_DESC_START_ADDRESS_LO", CMIC_CMC1_SBUSDMA_CH1_DESC_START_ADDRESS_LOr }, \ 771 { 0x00006120, "CMIC_CMC1_SBUSDMA_CH1_DESC_START_ADDRESS_HI", CMIC_CMC1_SBUSDMA_CH1_DESC_START_ADDRESS_HIr }, \ 772 { 0x00006124, "CMIC_CMC1_SBUSDMA_CH1_STATUS", CMIC_CMC1_SBUSDMA_CH1_STATUSr }, \ 773 { 0x00006128, "CMIC_CMC1_SBUSDMA_CH1_CUR_HOSTMEM_ADDRESS_LO", CMIC_CMC1_SBUSDMA_CH1_CUR_HOSTMEM_ADDRESS_LOr }, \ 774 { 0x0000612c, "CMIC_CMC1_SBUSDMA_CH1_CUR_HOSTMEM_ADDRESS_HI", CMIC_CMC1_SBUSDMA_CH1_CUR_HOSTMEM_ADDRESS_HIr }, \ 775 { 0x00006130, "CMIC_CMC1_SBUSDMA_CH1_CUR_SBUS_ADDRESS", CMIC_CMC1_SBUSDMA_CH1_CUR_SBUS_ADDRESSr }, \ 776 { 0x00006134, "CMIC_CMC1_SBUSDMA_CH1_CUR_DESC_ADDRESS_LO", CMIC_CMC1_SBUSDMA_CH1_CUR_DESC_ADDRESS_LOr }, \ 777 { 0x00006138, "CMIC_CMC1_SBUSDMA_CH1_CUR_DESC_ADDRESS_HI", CMIC_CMC1_SBUSDMA_CH1_CUR_DESC_ADDRESS_HIr }, \ 778 { 0x0000613c, "CMIC_CMC1_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_REQUEST", CMIC_CMC1_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_REQUESTr }, \ 779 { 0x00006140, "CMIC_CMC1_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_OPCODE", CMIC_CMC1_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_OPCODEr }, \ 780 { 0x00006144, "CMIC_CMC1_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_SBUS_START_ADDRESS", CMIC_CMC1_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_SBUS_START_ADDRESSr }, \ 781 { 0x00006148, "CMIC_CMC1_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_LO", CMIC_CMC1_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_LOr }, \ 782 { 0x0000614c, "CMIC_CMC1_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_HI", CMIC_CMC1_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_HIr }, \ 783 { 0x00006150, "CMIC_CMC1_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_COUNT", CMIC_CMC1_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_COUNTr }, \ 784 { 0x00006154, "CMIC_CMC1_SBUSDMA_CH1_SBUSDMA_DEBUG", CMIC_CMC1_SBUSDMA_CH1_SBUSDMA_DEBUGr }, \ 785 { 0x00006158, "CMIC_CMC1_SBUSDMA_CH1_SBUSDMA_DEBUG_CLR", CMIC_CMC1_SBUSDMA_CH1_SBUSDMA_DEBUG_CLRr }, \ 786 { 0x0000615c, "CMIC_CMC1_SBUSDMA_CH1_SBUSDMA_ECCERR_ADDRESS_LO", CMIC_CMC1_SBUSDMA_CH1_SBUSDMA_ECCERR_ADDRESS_LOr }, \ 787 { 0x00006160, "CMIC_CMC1_SBUSDMA_CH1_SBUSDMA_ECCERR_ADDRESS_HI", CMIC_CMC1_SBUSDMA_CH1_SBUSDMA_ECCERR_ADDRESS_HIr }, \ 788 { 0x00006164, "CMIC_CMC1_SBUSDMA_CH1_ECC_CONTROL", CMIC_CMC1_SBUSDMA_CH1_ECC_CONTROLr }, \ 789 { 0x00006168, "CMIC_CMC1_SBUSDMA_CH1_ECC_STATUS", CMIC_CMC1_SBUSDMA_CH1_ECC_STATUSr }, \ 790 { 0x0000616c, "CMIC_CMC1_SBUSDMA_CH1_ECC_STATUS_CLR", CMIC_CMC1_SBUSDMA_CH1_ECC_STATUS_CLRr }, \ 791 { 0x00006170, "CMIC_CMC1_SBUSDMA_CH1_TIMER", CMIC_CMC1_SBUSDMA_CH1_TIMERr }, \ 792 { 0x00006174, "CMIC_CMC1_SBUSDMA_CH1_ITER_COUNT", CMIC_CMC1_SBUSDMA_CH1_ITER_COUNTr }, \ 793 { 0x00006178, "CMIC_CMC1_SBUSDMA_CH1_TM_CONTROL", CMIC_CMC1_SBUSDMA_CH1_TM_CONTROLr }, \ 794 { 0x00006200, "CMIC_CMC1_SBUSDMA_CH2_CONTROL", CMIC_CMC1_SBUSDMA_CH2_CONTROLr }, \ 795 { 0x00006204, "CMIC_CMC1_SBUSDMA_CH2_REQUEST", CMIC_CMC1_SBUSDMA_CH2_REQUESTr }, \ 796 { 0x00006208, "CMIC_CMC1_SBUSDMA_CH2_COUNT", CMIC_CMC1_SBUSDMA_CH2_COUNTr }, \ 797 { 0x0000620c, "CMIC_CMC1_SBUSDMA_CH2_OPCODE", CMIC_CMC1_SBUSDMA_CH2_OPCODEr }, \ 798 { 0x00006210, "CMIC_CMC1_SBUSDMA_CH2_SBUS_START_ADDRESS", CMIC_CMC1_SBUSDMA_CH2_SBUS_START_ADDRESSr }, \ 799 { 0x00006214, "CMIC_CMC1_SBUSDMA_CH2_HOSTMEM_START_ADDRESS_LO", CMIC_CMC1_SBUSDMA_CH2_HOSTMEM_START_ADDRESS_LOr }, \ 800 { 0x00006218, "CMIC_CMC1_SBUSDMA_CH2_HOSTMEM_START_ADDRESS_HI", CMIC_CMC1_SBUSDMA_CH2_HOSTMEM_START_ADDRESS_HIr }, \ 801 { 0x0000621c, "CMIC_CMC1_SBUSDMA_CH2_DESC_START_ADDRESS_LO", CMIC_CMC1_SBUSDMA_CH2_DESC_START_ADDRESS_LOr }, \ 802 { 0x00006220, "CMIC_CMC1_SBUSDMA_CH2_DESC_START_ADDRESS_HI", CMIC_CMC1_SBUSDMA_CH2_DESC_START_ADDRESS_HIr }, \ 803 { 0x00006224, "CMIC_CMC1_SBUSDMA_CH2_STATUS", CMIC_CMC1_SBUSDMA_CH2_STATUSr }, \ 804 { 0x00006228, "CMIC_CMC1_SBUSDMA_CH2_CUR_HOSTMEM_ADDRESS_LO", CMIC_CMC1_SBUSDMA_CH2_CUR_HOSTMEM_ADDRESS_LOr }, \ 805 { 0x0000622c, "CMIC_CMC1_SBUSDMA_CH2_CUR_HOSTMEM_ADDRESS_HI", CMIC_CMC1_SBUSDMA_CH2_CUR_HOSTMEM_ADDRESS_HIr }, \ 806 { 0x00006230, "CMIC_CMC1_SBUSDMA_CH2_CUR_SBUS_ADDRESS", CMIC_CMC1_SBUSDMA_CH2_CUR_SBUS_ADDRESSr }, \ 807 { 0x00006234, "CMIC_CMC1_SBUSDMA_CH2_CUR_DESC_ADDRESS_LO", CMIC_CMC1_SBUSDMA_CH2_CUR_DESC_ADDRESS_LOr }, \ 808 { 0x00006238, "CMIC_CMC1_SBUSDMA_CH2_CUR_DESC_ADDRESS_HI", CMIC_CMC1_SBUSDMA_CH2_CUR_DESC_ADDRESS_HIr }, \ 809 { 0x0000623c, "CMIC_CMC1_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_REQUEST", CMIC_CMC1_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_REQUESTr }, \ 810 { 0x00006240, "CMIC_CMC1_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_OPCODE", CMIC_CMC1_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_OPCODEr }, \ 811 { 0x00006244, "CMIC_CMC1_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_SBUS_START_ADDRESS", CMIC_CMC1_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_SBUS_START_ADDRESSr }, \ 812 { 0x00006248, "CMIC_CMC1_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_LO", CMIC_CMC1_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_LOr }, \ 813 { 0x0000624c, "CMIC_CMC1_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_HI", CMIC_CMC1_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_HIr }, \ 814 { 0x00006250, "CMIC_CMC1_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_COUNT", CMIC_CMC1_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_COUNTr }, \ 815 { 0x00006254, "CMIC_CMC1_SBUSDMA_CH2_SBUSDMA_DEBUG", CMIC_CMC1_SBUSDMA_CH2_SBUSDMA_DEBUGr }, \ 816 { 0x00006258, "CMIC_CMC1_SBUSDMA_CH2_SBUSDMA_DEBUG_CLR", CMIC_CMC1_SBUSDMA_CH2_SBUSDMA_DEBUG_CLRr }, \ 817 { 0x0000625c, "CMIC_CMC1_SBUSDMA_CH2_SBUSDMA_ECCERR_ADDRESS_LO", CMIC_CMC1_SBUSDMA_CH2_SBUSDMA_ECCERR_ADDRESS_LOr }, \ 818 { 0x00006260, "CMIC_CMC1_SBUSDMA_CH2_SBUSDMA_ECCERR_ADDRESS_HI", CMIC_CMC1_SBUSDMA_CH2_SBUSDMA_ECCERR_ADDRESS_HIr }, \ 819 { 0x00006264, "CMIC_CMC1_SBUSDMA_CH2_ECC_CONTROL", CMIC_CMC1_SBUSDMA_CH2_ECC_CONTROLr }, \ 820 { 0x00006268, "CMIC_CMC1_SBUSDMA_CH2_ECC_STATUS", CMIC_CMC1_SBUSDMA_CH2_ECC_STATUSr }, \ 821 { 0x0000626c, "CMIC_CMC1_SBUSDMA_CH2_ECC_STATUS_CLR", CMIC_CMC1_SBUSDMA_CH2_ECC_STATUS_CLRr }, \ 822 { 0x00006270, "CMIC_CMC1_SBUSDMA_CH2_TIMER", CMIC_CMC1_SBUSDMA_CH2_TIMERr }, \ 823 { 0x00006274, "CMIC_CMC1_SBUSDMA_CH2_ITER_COUNT", CMIC_CMC1_SBUSDMA_CH2_ITER_COUNTr }, \ 824 { 0x00006278, "CMIC_CMC1_SBUSDMA_CH2_TM_CONTROL", CMIC_CMC1_SBUSDMA_CH2_TM_CONTROLr }, \ 825 { 0x00006300, "CMIC_CMC1_SBUSDMA_CH3_CONTROL", CMIC_CMC1_SBUSDMA_CH3_CONTROLr }, \ 826 { 0x00006304, "CMIC_CMC1_SBUSDMA_CH3_REQUEST", CMIC_CMC1_SBUSDMA_CH3_REQUESTr }, \ 827 { 0x00006308, "CMIC_CMC1_SBUSDMA_CH3_COUNT", CMIC_CMC1_SBUSDMA_CH3_COUNTr }, \ 828 { 0x0000630c, "CMIC_CMC1_SBUSDMA_CH3_OPCODE", CMIC_CMC1_SBUSDMA_CH3_OPCODEr }, \ 829 { 0x00006310, "CMIC_CMC1_SBUSDMA_CH3_SBUS_START_ADDRESS", CMIC_CMC1_SBUSDMA_CH3_SBUS_START_ADDRESSr }, \ 830 { 0x00006314, "CMIC_CMC1_SBUSDMA_CH3_HOSTMEM_START_ADDRESS_LO", CMIC_CMC1_SBUSDMA_CH3_HOSTMEM_START_ADDRESS_LOr }, \ 831 { 0x00006318, "CMIC_CMC1_SBUSDMA_CH3_HOSTMEM_START_ADDRESS_HI", CMIC_CMC1_SBUSDMA_CH3_HOSTMEM_START_ADDRESS_HIr }, \ 832 { 0x0000631c, "CMIC_CMC1_SBUSDMA_CH3_DESC_START_ADDRESS_LO", CMIC_CMC1_SBUSDMA_CH3_DESC_START_ADDRESS_LOr }, \ 833 { 0x00006320, "CMIC_CMC1_SBUSDMA_CH3_DESC_START_ADDRESS_HI", CMIC_CMC1_SBUSDMA_CH3_DESC_START_ADDRESS_HIr }, \ 834 { 0x00006324, "CMIC_CMC1_SBUSDMA_CH3_STATUS", CMIC_CMC1_SBUSDMA_CH3_STATUSr }, \ 835 { 0x00006328, "CMIC_CMC1_SBUSDMA_CH3_CUR_HOSTMEM_ADDRESS_LO", CMIC_CMC1_SBUSDMA_CH3_CUR_HOSTMEM_ADDRESS_LOr }, \ 836 { 0x0000632c, "CMIC_CMC1_SBUSDMA_CH3_CUR_HOSTMEM_ADDRESS_HI", CMIC_CMC1_SBUSDMA_CH3_CUR_HOSTMEM_ADDRESS_HIr }, \ 837 { 0x00006330, "CMIC_CMC1_SBUSDMA_CH3_CUR_SBUS_ADDRESS", CMIC_CMC1_SBUSDMA_CH3_CUR_SBUS_ADDRESSr }, \ 838 { 0x00006334, "CMIC_CMC1_SBUSDMA_CH3_CUR_DESC_ADDRESS_LO", CMIC_CMC1_SBUSDMA_CH3_CUR_DESC_ADDRESS_LOr }, \ 839 { 0x00006338, "CMIC_CMC1_SBUSDMA_CH3_CUR_DESC_ADDRESS_HI", CMIC_CMC1_SBUSDMA_CH3_CUR_DESC_ADDRESS_HIr }, \ 840 { 0x0000633c, "CMIC_CMC1_SBUSDMA_CH3_CUR_SBUSDMA_CONFIG_REQUEST", CMIC_CMC1_SBUSDMA_CH3_CUR_SBUSDMA_CONFIG_REQUESTr }, \ 841 { 0x00006340, "CMIC_CMC1_SBUSDMA_CH3_CUR_SBUSDMA_CONFIG_OPCODE", CMIC_CMC1_SBUSDMA_CH3_CUR_SBUSDMA_CONFIG_OPCODEr }, \ 842 { 0x00006344, "CMIC_CMC1_SBUSDMA_CH3_CUR_SBUSDMA_CONFIG_SBUS_START_ADDRESS", CMIC_CMC1_SBUSDMA_CH3_CUR_SBUSDMA_CONFIG_SBUS_START_ADDRESSr }, \ 843 { 0x00006348, "CMIC_CMC1_SBUSDMA_CH3_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_LO", CMIC_CMC1_SBUSDMA_CH3_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_LOr }, \ 844 { 0x0000634c, "CMIC_CMC1_SBUSDMA_CH3_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_HI", CMIC_CMC1_SBUSDMA_CH3_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_HIr }, \ 845 { 0x00006350, "CMIC_CMC1_SBUSDMA_CH3_CUR_SBUSDMA_CONFIG_COUNT", CMIC_CMC1_SBUSDMA_CH3_CUR_SBUSDMA_CONFIG_COUNTr }, \ 846 { 0x00006354, "CMIC_CMC1_SBUSDMA_CH3_SBUSDMA_DEBUG", CMIC_CMC1_SBUSDMA_CH3_SBUSDMA_DEBUGr }, \ 847 { 0x00006358, "CMIC_CMC1_SBUSDMA_CH3_SBUSDMA_DEBUG_CLR", CMIC_CMC1_SBUSDMA_CH3_SBUSDMA_DEBUG_CLRr }, \ 848 { 0x0000635c, "CMIC_CMC1_SBUSDMA_CH3_SBUSDMA_ECCERR_ADDRESS_LO", CMIC_CMC1_SBUSDMA_CH3_SBUSDMA_ECCERR_ADDRESS_LOr }, \ 849 { 0x00006360, "CMIC_CMC1_SBUSDMA_CH3_SBUSDMA_ECCERR_ADDRESS_HI", CMIC_CMC1_SBUSDMA_CH3_SBUSDMA_ECCERR_ADDRESS_HIr }, \ 850 { 0x00006364, "CMIC_CMC1_SBUSDMA_CH3_ECC_CONTROL", CMIC_CMC1_SBUSDMA_CH3_ECC_CONTROLr }, \ 851 { 0x00006368, "CMIC_CMC1_SBUSDMA_CH3_ECC_STATUS", CMIC_CMC1_SBUSDMA_CH3_ECC_STATUSr }, \ 852 { 0x0000636c, "CMIC_CMC1_SBUSDMA_CH3_ECC_STATUS_CLR", CMIC_CMC1_SBUSDMA_CH3_ECC_STATUS_CLRr }, \ 853 { 0x00006370, "CMIC_CMC1_SBUSDMA_CH3_TIMER", CMIC_CMC1_SBUSDMA_CH3_TIMERr }, \ 854 { 0x00006374, "CMIC_CMC1_SBUSDMA_CH3_ITER_COUNT", CMIC_CMC1_SBUSDMA_CH3_ITER_COUNTr }, \ 855 { 0x00006378, "CMIC_CMC1_SBUSDMA_CH3_TM_CONTROL", CMIC_CMC1_SBUSDMA_CH3_TM_CONTROLr }, \ 856 { 0x00006404, "CMIC_CMC1_CCMDMA_CH0_HOST0_MEM_START_ADDR_LO", CMIC_CMC1_CCMDMA_CH0_HOST0_MEM_START_ADDR_LOr }, \ 857 { 0x00006408, "CMIC_CMC1_CCMDMA_CH0_HOST0_MEM_START_ADDR_HI", CMIC_CMC1_CCMDMA_CH0_HOST0_MEM_START_ADDR_HIr }, \ 858 { 0x0000640c, "CMIC_CMC1_CCMDMA_CH0_HOST1_MEM_START_ADDR_LO", CMIC_CMC1_CCMDMA_CH0_HOST1_MEM_START_ADDR_LOr }, \ 859 { 0x00006410, "CMIC_CMC1_CCMDMA_CH0_HOST1_MEM_START_ADDR_HI", CMIC_CMC1_CCMDMA_CH0_HOST1_MEM_START_ADDR_HIr }, \ 860 { 0x00006414, "CMIC_CMC1_CCMDMA_CH0_ENTRY_COUNT", CMIC_CMC1_CCMDMA_CH0_ENTRY_COUNTr }, \ 861 { 0x00006418, "CMIC_CMC1_CCMDMA_CH0_CFG", CMIC_CMC1_CCMDMA_CH0_CFGr }, \ 862 { 0x0000641c, "CMIC_CMC1_CCMDMA_CH0_STAT", CMIC_CMC1_CCMDMA_CH0_STATr }, \ 863 { 0x00006420, "CMIC_CMC1_CCMDMA_CH0_CUR_HOST0_ADDR_LO", CMIC_CMC1_CCMDMA_CH0_CUR_HOST0_ADDR_LOr }, \ 864 { 0x00006424, "CMIC_CMC1_CCMDMA_CH0_CUR_HOST0_ADDR_HI", CMIC_CMC1_CCMDMA_CH0_CUR_HOST0_ADDR_HIr }, \ 865 { 0x00006428, "CMIC_CMC1_CCMDMA_CH0_CUR_HOST1_ADDR_LO", CMIC_CMC1_CCMDMA_CH0_CUR_HOST1_ADDR_LOr }, \ 866 { 0x0000642c, "CMIC_CMC1_CCMDMA_CH0_CUR_HOST1_ADDR_HI", CMIC_CMC1_CCMDMA_CH0_CUR_HOST1_ADDR_HIr }, \ 867 { 0x00006430, "CMIC_CMC1_CCMDMA_CH0_ECC_CONTROL", CMIC_CMC1_CCMDMA_CH0_ECC_CONTROLr }, \ 868 { 0x00006434, "CMIC_CMC1_CCMDMA_CH0_ECC_STATUS", CMIC_CMC1_CCMDMA_CH0_ECC_STATUSr }, \ 869 { 0x00006438, "CMIC_CMC1_CCMDMA_CH0_ECC_STATUS_CLR", CMIC_CMC1_CCMDMA_CH0_ECC_STATUS_CLRr }, \ 870 { 0x0000643c, "CMIC_CMC1_CCMDMA_CH0_TM_CONTROL", CMIC_CMC1_CCMDMA_CH0_TM_CONTROLr }, \ 871 { 0x00006484, "CMIC_CMC1_CCMDMA_CH1_HOST0_MEM_START_ADDR_LO", CMIC_CMC1_CCMDMA_CH1_HOST0_MEM_START_ADDR_LOr }, \ 872 { 0x00006488, "CMIC_CMC1_CCMDMA_CH1_HOST0_MEM_START_ADDR_HI", CMIC_CMC1_CCMDMA_CH1_HOST0_MEM_START_ADDR_HIr }, \ 873 { 0x0000648c, "CMIC_CMC1_CCMDMA_CH1_HOST1_MEM_START_ADDR_LO", CMIC_CMC1_CCMDMA_CH1_HOST1_MEM_START_ADDR_LOr }, \ 874 { 0x00006490, "CMIC_CMC1_CCMDMA_CH1_HOST1_MEM_START_ADDR_HI", CMIC_CMC1_CCMDMA_CH1_HOST1_MEM_START_ADDR_HIr }, \ 875 { 0x00006494, "CMIC_CMC1_CCMDMA_CH1_ENTRY_COUNT", CMIC_CMC1_CCMDMA_CH1_ENTRY_COUNTr }, \ 876 { 0x00006498, "CMIC_CMC1_CCMDMA_CH1_CFG", CMIC_CMC1_CCMDMA_CH1_CFGr }, \ 877 { 0x0000649c, "CMIC_CMC1_CCMDMA_CH1_STAT", CMIC_CMC1_CCMDMA_CH1_STATr }, \ 878 { 0x000064a0, "CMIC_CMC1_CCMDMA_CH1_CUR_HOST0_ADDR_LO", CMIC_CMC1_CCMDMA_CH1_CUR_HOST0_ADDR_LOr }, \ 879 { 0x000064a4, "CMIC_CMC1_CCMDMA_CH1_CUR_HOST0_ADDR_HI", CMIC_CMC1_CCMDMA_CH1_CUR_HOST0_ADDR_HIr }, \ 880 { 0x000064a8, "CMIC_CMC1_CCMDMA_CH1_CUR_HOST1_ADDR_LO", CMIC_CMC1_CCMDMA_CH1_CUR_HOST1_ADDR_LOr }, \ 881 { 0x000064ac, "CMIC_CMC1_CCMDMA_CH1_CUR_HOST1_ADDR_HI", CMIC_CMC1_CCMDMA_CH1_CUR_HOST1_ADDR_HIr }, \ 882 { 0x000064b0, "CMIC_CMC1_CCMDMA_CH1_ECC_CONTROL", CMIC_CMC1_CCMDMA_CH1_ECC_CONTROLr }, \ 883 { 0x000064b4, "CMIC_CMC1_CCMDMA_CH1_ECC_STATUS", CMIC_CMC1_CCMDMA_CH1_ECC_STATUSr }, \ 884 { 0x000064b8, "CMIC_CMC1_CCMDMA_CH1_ECC_STATUS_CLR", CMIC_CMC1_CCMDMA_CH1_ECC_STATUS_CLRr }, \ 885 { 0x000064bc, "CMIC_CMC1_CCMDMA_CH1_TM_CONTROL", CMIC_CMC1_CCMDMA_CH1_TM_CONTROLr }, \ 886 { 0x0000d000, "CMIC_COMMON_POOL_SHARED_FIFO_DMA_WRITE_AXI_MAP_CTRL", CMIC_COMMON_POOL_SHARED_FIFO_DMA_WRITE_AXI_MAP_CTRLr }, \ 887 { 0x0000d004, "CMIC_COMMON_POOL_SHARED_FIFO_DMA_WRITE_AXI_MAP_CTRL_1", CMIC_COMMON_POOL_SHARED_FIFO_DMA_WRITE_AXI_MAP_CTRL_1r }, \ 888 { 0x0000d008, "CMIC_COMMON_POOL_SHARED_FIFO_DMA_WRITE_ARB_CTRL", CMIC_COMMON_POOL_SHARED_FIFO_DMA_WRITE_ARB_CTRLr }, \ 889 { 0x0000d00c, "CMIC_COMMON_POOL_SHARED_SCHAN_FIFO_WRITE_ARB_CTRL", CMIC_COMMON_POOL_SHARED_SCHAN_FIFO_WRITE_ARB_CTRLr }, \ 890 { 0x0000d010, "CMIC_COMMON_POOL_SHARED_2BIT_ECC_ERROR_STATUS", CMIC_COMMON_POOL_SHARED_2BIT_ECC_ERROR_STATUSr }, \ 891 { 0x0000d014, "CMIC_COMMON_POOL_SHARED_2BIT_ECC_ERROR_STATUS_ENABLE", CMIC_COMMON_POOL_SHARED_2BIT_ECC_ERROR_STATUS_ENABLEr }, \ 892 { 0x0000d018, "CMIC_COMMON_POOL_SHARED_1BIT_ECC_ERROR_STATUS", CMIC_COMMON_POOL_SHARED_1BIT_ECC_ERROR_STATUSr }, \ 893 { 0x0000d01c, "CMIC_COMMON_POOL_SHARED_1BIT_ECC_ERROR_STATUS_ENABLE", CMIC_COMMON_POOL_SHARED_1BIT_ECC_ERROR_STATUS_ENABLEr }, \ 894 { 0x0000d020, "CMIC_COMMON_POOL_SHARED_IRQ_STAT0", CMIC_COMMON_POOL_SHARED_IRQ_STAT0r }, \ 895 { 0x0000d024, "CMIC_COMMON_POOL_SHARED_CONFIG", CMIC_COMMON_POOL_SHARED_CONFIGr }, \ 896 { 0x00010000, "CMIC_COMMON_POOL_SCHAN_CH0_CTRL", CMIC_COMMON_POOL_SCHAN_CH0_CTRLr }, \ 897 { 0x00010004, "CMIC_COMMON_POOL_SCHAN_CH0_ACK_DATA_BEAT_COUNT", CMIC_COMMON_POOL_SCHAN_CH0_ACK_DATA_BEAT_COUNTr }, \ 898 { 0x00010008, "CMIC_COMMON_POOL_SCHAN_CH0_ERR", CMIC_COMMON_POOL_SCHAN_CH0_ERRr }, \ 899 { 0x0001000c, "CMIC_COMMON_POOL_SCHAN_CH0_MESSAGE", CMIC_COMMON_POOL_SCHAN_CH0_MESSAGEr }, \ 900 { 0x00010100, "CMIC_COMMON_POOL_SCHAN_CH1_CTRL", CMIC_COMMON_POOL_SCHAN_CH1_CTRLr }, \ 901 { 0x00010104, "CMIC_COMMON_POOL_SCHAN_CH1_ACK_DATA_BEAT_COUNT", CMIC_COMMON_POOL_SCHAN_CH1_ACK_DATA_BEAT_COUNTr }, \ 902 { 0x00010108, "CMIC_COMMON_POOL_SCHAN_CH1_ERR", CMIC_COMMON_POOL_SCHAN_CH1_ERRr }, \ 903 { 0x0001010c, "CMIC_COMMON_POOL_SCHAN_CH1_MESSAGE", CMIC_COMMON_POOL_SCHAN_CH1_MESSAGEr }, \ 904 { 0x00010200, "CMIC_COMMON_POOL_SCHAN_CH2_CTRL", CMIC_COMMON_POOL_SCHAN_CH2_CTRLr }, \ 905 { 0x00010204, "CMIC_COMMON_POOL_SCHAN_CH2_ACK_DATA_BEAT_COUNT", CMIC_COMMON_POOL_SCHAN_CH2_ACK_DATA_BEAT_COUNTr }, \ 906 { 0x00010208, "CMIC_COMMON_POOL_SCHAN_CH2_ERR", CMIC_COMMON_POOL_SCHAN_CH2_ERRr }, \ 907 { 0x0001020c, "CMIC_COMMON_POOL_SCHAN_CH2_MESSAGE", CMIC_COMMON_POOL_SCHAN_CH2_MESSAGEr }, \ 908 { 0x00010300, "CMIC_COMMON_POOL_SCHAN_CH3_CTRL", CMIC_COMMON_POOL_SCHAN_CH3_CTRLr }, \ 909 { 0x00010304, "CMIC_COMMON_POOL_SCHAN_CH3_ACK_DATA_BEAT_COUNT", CMIC_COMMON_POOL_SCHAN_CH3_ACK_DATA_BEAT_COUNTr }, \ 910 { 0x00010308, "CMIC_COMMON_POOL_SCHAN_CH3_ERR", CMIC_COMMON_POOL_SCHAN_CH3_ERRr }, \ 911 { 0x0001030c, "CMIC_COMMON_POOL_SCHAN_CH3_MESSAGE", CMIC_COMMON_POOL_SCHAN_CH3_MESSAGEr }, \ 912 { 0x00010400, "CMIC_COMMON_POOL_SCHAN_CH4_CTRL", CMIC_COMMON_POOL_SCHAN_CH4_CTRLr }, \ 913 { 0x00010404, "CMIC_COMMON_POOL_SCHAN_CH4_ACK_DATA_BEAT_COUNT", CMIC_COMMON_POOL_SCHAN_CH4_ACK_DATA_BEAT_COUNTr }, \ 914 { 0x00010408, "CMIC_COMMON_POOL_SCHAN_CH4_ERR", CMIC_COMMON_POOL_SCHAN_CH4_ERRr }, \ 915 { 0x0001040c, "CMIC_COMMON_POOL_SCHAN_CH4_MESSAGE", CMIC_COMMON_POOL_SCHAN_CH4_MESSAGEr }, \ 916 { 0x00011000, "CMIC_COMMON_POOL_FIFO_CH0_RD_DMA_CFG", CMIC_COMMON_POOL_FIFO_CH0_RD_DMA_CFGr }, \ 917 { 0x00011004, "CMIC_COMMON_POOL_FIFO_CH0_RD_DMA_CFG_1", CMIC_COMMON_POOL_FIFO_CH0_RD_DMA_CFG_1r }, \ 918 { 0x00011008, "CMIC_COMMON_POOL_FIFO_CH0_RD_DMA_SBUS_START_ADDRESS", CMIC_COMMON_POOL_FIFO_CH0_RD_DMA_SBUS_START_ADDRESSr }, \ 919 { 0x0001100c, "CMIC_COMMON_POOL_FIFO_CH0_RD_DMA_HOSTMEM_START_ADDRESS_LO", CMIC_COMMON_POOL_FIFO_CH0_RD_DMA_HOSTMEM_START_ADDRESS_LOr }, \ 920 { 0x00011010, "CMIC_COMMON_POOL_FIFO_CH0_RD_DMA_HOSTMEM_START_ADDRESS_HI", CMIC_COMMON_POOL_FIFO_CH0_RD_DMA_HOSTMEM_START_ADDRESS_HIr }, \ 921 { 0x00011014, "CMIC_COMMON_POOL_FIFO_CH0_RD_DMA_NUM_OF_ENTRIES_READ_FRM_HOSTMEM", CMIC_COMMON_POOL_FIFO_CH0_RD_DMA_NUM_OF_ENTRIES_READ_FRM_HOSTMEMr }, \ 922 { 0x00011018, "CMIC_COMMON_POOL_FIFO_CH0_RD_DMA_NUM_OF_ENTRIES_VALID_IN_HOSTMEM", CMIC_COMMON_POOL_FIFO_CH0_RD_DMA_NUM_OF_ENTRIES_VALID_IN_HOSTMEMr }, \ 923 { 0x0001101c, "CMIC_COMMON_POOL_FIFO_CH0_RD_DMA_HOSTMEM_THRESHOLD", CMIC_COMMON_POOL_FIFO_CH0_RD_DMA_HOSTMEM_THRESHOLDr }, \ 924 { 0x00011020, "CMIC_COMMON_POOL_FIFO_CH0_RD_DMA_STAT", CMIC_COMMON_POOL_FIFO_CH0_RD_DMA_STATr }, \ 925 { 0x00011024, "CMIC_COMMON_POOL_FIFO_CH0_RD_DMA_STAT_CLR", CMIC_COMMON_POOL_FIFO_CH0_RD_DMA_STAT_CLRr }, \ 926 { 0x00011028, "CMIC_COMMON_POOL_FIFO_CH0_RD_DMA_OPCODE", CMIC_COMMON_POOL_FIFO_CH0_RD_DMA_OPCODEr }, \ 927 { 0x0001102c, "CMIC_COMMON_POOL_FIFO_CH0_RD_DMA_ECCERR_ADDRESS_LO", CMIC_COMMON_POOL_FIFO_CH0_RD_DMA_ECCERR_ADDRESS_LOr }, \ 928 { 0x00011030, "CMIC_COMMON_POOL_FIFO_CH0_RD_DMA_ECCERR_ADDRESS_HI", CMIC_COMMON_POOL_FIFO_CH0_RD_DMA_ECCERR_ADDRESS_HIr }, \ 929 { 0x00011034, "CMIC_COMMON_POOL_FIFO_CH0_RD_DMA_ECC_CONTROL", CMIC_COMMON_POOL_FIFO_CH0_RD_DMA_ECC_CONTROLr }, \ 930 { 0x00011038, "CMIC_COMMON_POOL_FIFO_CH0_RD_DMA_ECC_STATUS", CMIC_COMMON_POOL_FIFO_CH0_RD_DMA_ECC_STATUSr }, \ 931 { 0x0001103c, "CMIC_COMMON_POOL_FIFO_CH0_RD_DMA_ECC_STATUS_CLR", CMIC_COMMON_POOL_FIFO_CH0_RD_DMA_ECC_STATUS_CLRr }, \ 932 { 0x00011040, "CMIC_COMMON_POOL_FIFO_CH0_RD_DMA_TM_CONTROL", CMIC_COMMON_POOL_FIFO_CH0_RD_DMA_TM_CONTROLr }, \ 933 { 0x00011044, "CMIC_COMMON_POOL_FIFO_CH0_RD_DMA_CUR_HOSTMEM_WRITE_PTR_LO", CMIC_COMMON_POOL_FIFO_CH0_RD_DMA_CUR_HOSTMEM_WRITE_PTR_LOr }, \ 934 { 0x00011048, "CMIC_COMMON_POOL_FIFO_CH0_RD_DMA_CUR_HOSTMEM_WRITE_PTR_HI", CMIC_COMMON_POOL_FIFO_CH0_RD_DMA_CUR_HOSTMEM_WRITE_PTR_HIr }, \ 935 { 0x00011080, "CMIC_COMMON_POOL_FIFO_CH1_RD_DMA_CFG", CMIC_COMMON_POOL_FIFO_CH1_RD_DMA_CFGr }, \ 936 { 0x00011084, "CMIC_COMMON_POOL_FIFO_CH1_RD_DMA_CFG_1", CMIC_COMMON_POOL_FIFO_CH1_RD_DMA_CFG_1r }, \ 937 { 0x00011088, "CMIC_COMMON_POOL_FIFO_CH1_RD_DMA_SBUS_START_ADDRESS", CMIC_COMMON_POOL_FIFO_CH1_RD_DMA_SBUS_START_ADDRESSr }, \ 938 { 0x0001108c, "CMIC_COMMON_POOL_FIFO_CH1_RD_DMA_HOSTMEM_START_ADDRESS_LO", CMIC_COMMON_POOL_FIFO_CH1_RD_DMA_HOSTMEM_START_ADDRESS_LOr }, \ 939 { 0x00011090, "CMIC_COMMON_POOL_FIFO_CH1_RD_DMA_HOSTMEM_START_ADDRESS_HI", CMIC_COMMON_POOL_FIFO_CH1_RD_DMA_HOSTMEM_START_ADDRESS_HIr }, \ 940 { 0x00011094, "CMIC_COMMON_POOL_FIFO_CH1_RD_DMA_NUM_OF_ENTRIES_READ_FRM_HOSTMEM", CMIC_COMMON_POOL_FIFO_CH1_RD_DMA_NUM_OF_ENTRIES_READ_FRM_HOSTMEMr }, \ 941 { 0x00011098, "CMIC_COMMON_POOL_FIFO_CH1_RD_DMA_NUM_OF_ENTRIES_VALID_IN_HOSTMEM", CMIC_COMMON_POOL_FIFO_CH1_RD_DMA_NUM_OF_ENTRIES_VALID_IN_HOSTMEMr }, \ 942 { 0x0001109c, "CMIC_COMMON_POOL_FIFO_CH1_RD_DMA_HOSTMEM_THRESHOLD", CMIC_COMMON_POOL_FIFO_CH1_RD_DMA_HOSTMEM_THRESHOLDr }, \ 943 { 0x000110a0, "CMIC_COMMON_POOL_FIFO_CH1_RD_DMA_STAT", CMIC_COMMON_POOL_FIFO_CH1_RD_DMA_STATr }, \ 944 { 0x000110a4, "CMIC_COMMON_POOL_FIFO_CH1_RD_DMA_STAT_CLR", CMIC_COMMON_POOL_FIFO_CH1_RD_DMA_STAT_CLRr }, \ 945 { 0x000110a8, "CMIC_COMMON_POOL_FIFO_CH1_RD_DMA_OPCODE", CMIC_COMMON_POOL_FIFO_CH1_RD_DMA_OPCODEr }, \ 946 { 0x000110ac, "CMIC_COMMON_POOL_FIFO_CH1_RD_DMA_ECCERR_ADDRESS_LO", CMIC_COMMON_POOL_FIFO_CH1_RD_DMA_ECCERR_ADDRESS_LOr }, \ 947 { 0x000110b0, "CMIC_COMMON_POOL_FIFO_CH1_RD_DMA_ECCERR_ADDRESS_HI", CMIC_COMMON_POOL_FIFO_CH1_RD_DMA_ECCERR_ADDRESS_HIr }, \ 948 { 0x000110b4, "CMIC_COMMON_POOL_FIFO_CH1_RD_DMA_ECC_CONTROL", CMIC_COMMON_POOL_FIFO_CH1_RD_DMA_ECC_CONTROLr }, \ 949 { 0x000110b8, "CMIC_COMMON_POOL_FIFO_CH1_RD_DMA_ECC_STATUS", CMIC_COMMON_POOL_FIFO_CH1_RD_DMA_ECC_STATUSr }, \ 950 { 0x000110bc, "CMIC_COMMON_POOL_FIFO_CH1_RD_DMA_ECC_STATUS_CLR", CMIC_COMMON_POOL_FIFO_CH1_RD_DMA_ECC_STATUS_CLRr }, \ 951 { 0x000110c0, "CMIC_COMMON_POOL_FIFO_CH1_RD_DMA_TM_CONTROL", CMIC_COMMON_POOL_FIFO_CH1_RD_DMA_TM_CONTROLr }, \ 952 { 0x000110c4, "CMIC_COMMON_POOL_FIFO_CH1_RD_DMA_CUR_HOSTMEM_WRITE_PTR_LO", CMIC_COMMON_POOL_FIFO_CH1_RD_DMA_CUR_HOSTMEM_WRITE_PTR_LOr }, \ 953 { 0x000110c8, "CMIC_COMMON_POOL_FIFO_CH1_RD_DMA_CUR_HOSTMEM_WRITE_PTR_HI", CMIC_COMMON_POOL_FIFO_CH1_RD_DMA_CUR_HOSTMEM_WRITE_PTR_HIr }, \ 954 { 0x00011100, "CMIC_COMMON_POOL_FIFO_CH2_RD_DMA_CFG", CMIC_COMMON_POOL_FIFO_CH2_RD_DMA_CFGr }, \ 955 { 0x00011104, "CMIC_COMMON_POOL_FIFO_CH2_RD_DMA_CFG_1", CMIC_COMMON_POOL_FIFO_CH2_RD_DMA_CFG_1r }, \ 956 { 0x00011108, "CMIC_COMMON_POOL_FIFO_CH2_RD_DMA_SBUS_START_ADDRESS", CMIC_COMMON_POOL_FIFO_CH2_RD_DMA_SBUS_START_ADDRESSr }, \ 957 { 0x0001110c, "CMIC_COMMON_POOL_FIFO_CH2_RD_DMA_HOSTMEM_START_ADDRESS_LO", CMIC_COMMON_POOL_FIFO_CH2_RD_DMA_HOSTMEM_START_ADDRESS_LOr }, \ 958 { 0x00011110, "CMIC_COMMON_POOL_FIFO_CH2_RD_DMA_HOSTMEM_START_ADDRESS_HI", CMIC_COMMON_POOL_FIFO_CH2_RD_DMA_HOSTMEM_START_ADDRESS_HIr }, \ 959 { 0x00011114, "CMIC_COMMON_POOL_FIFO_CH2_RD_DMA_NUM_OF_ENTRIES_READ_FRM_HOSTMEM", CMIC_COMMON_POOL_FIFO_CH2_RD_DMA_NUM_OF_ENTRIES_READ_FRM_HOSTMEMr }, \ 960 { 0x00011118, "CMIC_COMMON_POOL_FIFO_CH2_RD_DMA_NUM_OF_ENTRIES_VALID_IN_HOSTMEM", CMIC_COMMON_POOL_FIFO_CH2_RD_DMA_NUM_OF_ENTRIES_VALID_IN_HOSTMEMr }, \ 961 { 0x0001111c, "CMIC_COMMON_POOL_FIFO_CH2_RD_DMA_HOSTMEM_THRESHOLD", CMIC_COMMON_POOL_FIFO_CH2_RD_DMA_HOSTMEM_THRESHOLDr }, \ 962 { 0x00011120, "CMIC_COMMON_POOL_FIFO_CH2_RD_DMA_STAT", CMIC_COMMON_POOL_FIFO_CH2_RD_DMA_STATr }, \ 963 { 0x00011124, "CMIC_COMMON_POOL_FIFO_CH2_RD_DMA_STAT_CLR", CMIC_COMMON_POOL_FIFO_CH2_RD_DMA_STAT_CLRr }, \ 964 { 0x00011128, "CMIC_COMMON_POOL_FIFO_CH2_RD_DMA_OPCODE", CMIC_COMMON_POOL_FIFO_CH2_RD_DMA_OPCODEr }, \ 965 { 0x0001112c, "CMIC_COMMON_POOL_FIFO_CH2_RD_DMA_ECCERR_ADDRESS_LO", CMIC_COMMON_POOL_FIFO_CH2_RD_DMA_ECCERR_ADDRESS_LOr }, \ 966 { 0x00011130, "CMIC_COMMON_POOL_FIFO_CH2_RD_DMA_ECCERR_ADDRESS_HI", CMIC_COMMON_POOL_FIFO_CH2_RD_DMA_ECCERR_ADDRESS_HIr }, \ 967 { 0x00011134, "CMIC_COMMON_POOL_FIFO_CH2_RD_DMA_ECC_CONTROL", CMIC_COMMON_POOL_FIFO_CH2_RD_DMA_ECC_CONTROLr }, \ 968 { 0x00011138, "CMIC_COMMON_POOL_FIFO_CH2_RD_DMA_ECC_STATUS", CMIC_COMMON_POOL_FIFO_CH2_RD_DMA_ECC_STATUSr }, \ 969 { 0x0001113c, "CMIC_COMMON_POOL_FIFO_CH2_RD_DMA_ECC_STATUS_CLR", CMIC_COMMON_POOL_FIFO_CH2_RD_DMA_ECC_STATUS_CLRr }, \ 970 { 0x00011140, "CMIC_COMMON_POOL_FIFO_CH2_RD_DMA_TM_CONTROL", CMIC_COMMON_POOL_FIFO_CH2_RD_DMA_TM_CONTROLr }, \ 971 { 0x00011144, "CMIC_COMMON_POOL_FIFO_CH2_RD_DMA_CUR_HOSTMEM_WRITE_PTR_LO", CMIC_COMMON_POOL_FIFO_CH2_RD_DMA_CUR_HOSTMEM_WRITE_PTR_LOr }, \ 972 { 0x00011148, "CMIC_COMMON_POOL_FIFO_CH2_RD_DMA_CUR_HOSTMEM_WRITE_PTR_HI", CMIC_COMMON_POOL_FIFO_CH2_RD_DMA_CUR_HOSTMEM_WRITE_PTR_HIr }, \ 973 { 0x00011180, "CMIC_COMMON_POOL_FIFO_CH3_RD_DMA_CFG", CMIC_COMMON_POOL_FIFO_CH3_RD_DMA_CFGr }, \ 974 { 0x00011184, "CMIC_COMMON_POOL_FIFO_CH3_RD_DMA_CFG_1", CMIC_COMMON_POOL_FIFO_CH3_RD_DMA_CFG_1r }, \ 975 { 0x00011188, "CMIC_COMMON_POOL_FIFO_CH3_RD_DMA_SBUS_START_ADDRESS", CMIC_COMMON_POOL_FIFO_CH3_RD_DMA_SBUS_START_ADDRESSr }, \ 976 { 0x0001118c, "CMIC_COMMON_POOL_FIFO_CH3_RD_DMA_HOSTMEM_START_ADDRESS_LO", CMIC_COMMON_POOL_FIFO_CH3_RD_DMA_HOSTMEM_START_ADDRESS_LOr }, \ 977 { 0x00011190, "CMIC_COMMON_POOL_FIFO_CH3_RD_DMA_HOSTMEM_START_ADDRESS_HI", CMIC_COMMON_POOL_FIFO_CH3_RD_DMA_HOSTMEM_START_ADDRESS_HIr }, \ 978 { 0x00011194, "CMIC_COMMON_POOL_FIFO_CH3_RD_DMA_NUM_OF_ENTRIES_READ_FRM_HOSTMEM", CMIC_COMMON_POOL_FIFO_CH3_RD_DMA_NUM_OF_ENTRIES_READ_FRM_HOSTMEMr }, \ 979 { 0x00011198, "CMIC_COMMON_POOL_FIFO_CH3_RD_DMA_NUM_OF_ENTRIES_VALID_IN_HOSTMEM", CMIC_COMMON_POOL_FIFO_CH3_RD_DMA_NUM_OF_ENTRIES_VALID_IN_HOSTMEMr }, \ 980 { 0x0001119c, "CMIC_COMMON_POOL_FIFO_CH3_RD_DMA_HOSTMEM_THRESHOLD", CMIC_COMMON_POOL_FIFO_CH3_RD_DMA_HOSTMEM_THRESHOLDr }, \ 981 { 0x000111a0, "CMIC_COMMON_POOL_FIFO_CH3_RD_DMA_STAT", CMIC_COMMON_POOL_FIFO_CH3_RD_DMA_STATr }, \ 982 { 0x000111a4, "CMIC_COMMON_POOL_FIFO_CH3_RD_DMA_STAT_CLR", CMIC_COMMON_POOL_FIFO_CH3_RD_DMA_STAT_CLRr }, \ 983 { 0x000111a8, "CMIC_COMMON_POOL_FIFO_CH3_RD_DMA_OPCODE", CMIC_COMMON_POOL_FIFO_CH3_RD_DMA_OPCODEr }, \ 984 { 0x000111ac, "CMIC_COMMON_POOL_FIFO_CH3_RD_DMA_ECCERR_ADDRESS_LO", CMIC_COMMON_POOL_FIFO_CH3_RD_DMA_ECCERR_ADDRESS_LOr }, \ 985 { 0x000111b0, "CMIC_COMMON_POOL_FIFO_CH3_RD_DMA_ECCERR_ADDRESS_HI", CMIC_COMMON_POOL_FIFO_CH3_RD_DMA_ECCERR_ADDRESS_HIr }, \ 986 { 0x000111b4, "CMIC_COMMON_POOL_FIFO_CH3_RD_DMA_ECC_CONTROL", CMIC_COMMON_POOL_FIFO_CH3_RD_DMA_ECC_CONTROLr }, \ 987 { 0x000111b8, "CMIC_COMMON_POOL_FIFO_CH3_RD_DMA_ECC_STATUS", CMIC_COMMON_POOL_FIFO_CH3_RD_DMA_ECC_STATUSr }, \ 988 { 0x000111bc, "CMIC_COMMON_POOL_FIFO_CH3_RD_DMA_ECC_STATUS_CLR", CMIC_COMMON_POOL_FIFO_CH3_RD_DMA_ECC_STATUS_CLRr }, \ 989 { 0x000111c0, "CMIC_COMMON_POOL_FIFO_CH3_RD_DMA_TM_CONTROL", CMIC_COMMON_POOL_FIFO_CH3_RD_DMA_TM_CONTROLr }, \ 990 { 0x000111c4, "CMIC_COMMON_POOL_FIFO_CH3_RD_DMA_CUR_HOSTMEM_WRITE_PTR_LO", CMIC_COMMON_POOL_FIFO_CH3_RD_DMA_CUR_HOSTMEM_WRITE_PTR_LOr }, \ 991 { 0x000111c8, "CMIC_COMMON_POOL_FIFO_CH3_RD_DMA_CUR_HOSTMEM_WRITE_PTR_HI", CMIC_COMMON_POOL_FIFO_CH3_RD_DMA_CUR_HOSTMEM_WRITE_PTR_HIr }, \ 992 { 0x00011200, "CMIC_COMMON_POOL_FIFO_CH4_RD_DMA_CFG", CMIC_COMMON_POOL_FIFO_CH4_RD_DMA_CFGr }, \ 993 { 0x00011204, "CMIC_COMMON_POOL_FIFO_CH4_RD_DMA_CFG_1", CMIC_COMMON_POOL_FIFO_CH4_RD_DMA_CFG_1r }, \ 994 { 0x00011208, "CMIC_COMMON_POOL_FIFO_CH4_RD_DMA_SBUS_START_ADDRESS", CMIC_COMMON_POOL_FIFO_CH4_RD_DMA_SBUS_START_ADDRESSr }, \ 995 { 0x0001120c, "CMIC_COMMON_POOL_FIFO_CH4_RD_DMA_HOSTMEM_START_ADDRESS_LO", CMIC_COMMON_POOL_FIFO_CH4_RD_DMA_HOSTMEM_START_ADDRESS_LOr }, \ 996 { 0x00011210, "CMIC_COMMON_POOL_FIFO_CH4_RD_DMA_HOSTMEM_START_ADDRESS_HI", CMIC_COMMON_POOL_FIFO_CH4_RD_DMA_HOSTMEM_START_ADDRESS_HIr }, \ 997 { 0x00011214, "CMIC_COMMON_POOL_FIFO_CH4_RD_DMA_NUM_OF_ENTRIES_READ_FRM_HOSTMEM", CMIC_COMMON_POOL_FIFO_CH4_RD_DMA_NUM_OF_ENTRIES_READ_FRM_HOSTMEMr }, \ 998 { 0x00011218, "CMIC_COMMON_POOL_FIFO_CH4_RD_DMA_NUM_OF_ENTRIES_VALID_IN_HOSTMEM", CMIC_COMMON_POOL_FIFO_CH4_RD_DMA_NUM_OF_ENTRIES_VALID_IN_HOSTMEMr }, \ 999 { 0x0001121c, "CMIC_COMMON_POOL_FIFO_CH4_RD_DMA_HOSTMEM_THRESHOLD", CMIC_COMMON_POOL_FIFO_CH4_RD_DMA_HOSTMEM_THRESHOLDr }, \ 1000 { 0x00011220, "CMIC_COMMON_POOL_FIFO_CH4_RD_DMA_STAT", CMIC_COMMON_POOL_FIFO_CH4_RD_DMA_STATr }, \ 1001 { 0x00011224, "CMIC_COMMON_POOL_FIFO_CH4_RD_DMA_STAT_CLR", CMIC_COMMON_POOL_FIFO_CH4_RD_DMA_STAT_CLRr }, \ 1002 { 0x00011228, "CMIC_COMMON_POOL_FIFO_CH4_RD_DMA_OPCODE", CMIC_COMMON_POOL_FIFO_CH4_RD_DMA_OPCODEr }, \ 1003 { 0x0001122c, "CMIC_COMMON_POOL_FIFO_CH4_RD_DMA_ECCERR_ADDRESS_LO", CMIC_COMMON_POOL_FIFO_CH4_RD_DMA_ECCERR_ADDRESS_LOr }, \ 1004 { 0x00011230, "CMIC_COMMON_POOL_FIFO_CH4_RD_DMA_ECCERR_ADDRESS_HI", CMIC_COMMON_POOL_FIFO_CH4_RD_DMA_ECCERR_ADDRESS_HIr }, \ 1005 { 0x00011234, "CMIC_COMMON_POOL_FIFO_CH4_RD_DMA_ECC_CONTROL", CMIC_COMMON_POOL_FIFO_CH4_RD_DMA_ECC_CONTROLr }, \ 1006 { 0x00011238, "CMIC_COMMON_POOL_FIFO_CH4_RD_DMA_ECC_STATUS", CMIC_COMMON_POOL_FIFO_CH4_RD_DMA_ECC_STATUSr }, \ 1007 { 0x0001123c, "CMIC_COMMON_POOL_FIFO_CH4_RD_DMA_ECC_STATUS_CLR", CMIC_COMMON_POOL_FIFO_CH4_RD_DMA_ECC_STATUS_CLRr }, \ 1008 { 0x00011240, "CMIC_COMMON_POOL_FIFO_CH4_RD_DMA_TM_CONTROL", CMIC_COMMON_POOL_FIFO_CH4_RD_DMA_TM_CONTROLr }, \ 1009 { 0x00011244, "CMIC_COMMON_POOL_FIFO_CH4_RD_DMA_CUR_HOSTMEM_WRITE_PTR_LO", CMIC_COMMON_POOL_FIFO_CH4_RD_DMA_CUR_HOSTMEM_WRITE_PTR_LOr }, \ 1010 { 0x00011248, "CMIC_COMMON_POOL_FIFO_CH4_RD_DMA_CUR_HOSTMEM_WRITE_PTR_HI", CMIC_COMMON_POOL_FIFO_CH4_RD_DMA_CUR_HOSTMEM_WRITE_PTR_HIr }, \ 1011 { 0x00011280, "CMIC_COMMON_POOL_FIFO_CH5_RD_DMA_CFG", CMIC_COMMON_POOL_FIFO_CH5_RD_DMA_CFGr }, \ 1012 { 0x00011284, "CMIC_COMMON_POOL_FIFO_CH5_RD_DMA_CFG_1", CMIC_COMMON_POOL_FIFO_CH5_RD_DMA_CFG_1r }, \ 1013 { 0x00011288, "CMIC_COMMON_POOL_FIFO_CH5_RD_DMA_SBUS_START_ADDRESS", CMIC_COMMON_POOL_FIFO_CH5_RD_DMA_SBUS_START_ADDRESSr }, \ 1014 { 0x0001128c, "CMIC_COMMON_POOL_FIFO_CH5_RD_DMA_HOSTMEM_START_ADDRESS_LO", CMIC_COMMON_POOL_FIFO_CH5_RD_DMA_HOSTMEM_START_ADDRESS_LOr }, \ 1015 { 0x00011290, "CMIC_COMMON_POOL_FIFO_CH5_RD_DMA_HOSTMEM_START_ADDRESS_HI", CMIC_COMMON_POOL_FIFO_CH5_RD_DMA_HOSTMEM_START_ADDRESS_HIr }, \ 1016 { 0x00011294, "CMIC_COMMON_POOL_FIFO_CH5_RD_DMA_NUM_OF_ENTRIES_READ_FRM_HOSTMEM", CMIC_COMMON_POOL_FIFO_CH5_RD_DMA_NUM_OF_ENTRIES_READ_FRM_HOSTMEMr }, \ 1017 { 0x00011298, "CMIC_COMMON_POOL_FIFO_CH5_RD_DMA_NUM_OF_ENTRIES_VALID_IN_HOSTMEM", CMIC_COMMON_POOL_FIFO_CH5_RD_DMA_NUM_OF_ENTRIES_VALID_IN_HOSTMEMr }, \ 1018 { 0x0001129c, "CMIC_COMMON_POOL_FIFO_CH5_RD_DMA_HOSTMEM_THRESHOLD", CMIC_COMMON_POOL_FIFO_CH5_RD_DMA_HOSTMEM_THRESHOLDr }, \ 1019 { 0x000112a0, "CMIC_COMMON_POOL_FIFO_CH5_RD_DMA_STAT", CMIC_COMMON_POOL_FIFO_CH5_RD_DMA_STATr }, \ 1020 { 0x000112a4, "CMIC_COMMON_POOL_FIFO_CH5_RD_DMA_STAT_CLR", CMIC_COMMON_POOL_FIFO_CH5_RD_DMA_STAT_CLRr }, \ 1021 { 0x000112a8, "CMIC_COMMON_POOL_FIFO_CH5_RD_DMA_OPCODE", CMIC_COMMON_POOL_FIFO_CH5_RD_DMA_OPCODEr }, \ 1022 { 0x000112ac, "CMIC_COMMON_POOL_FIFO_CH5_RD_DMA_ECCERR_ADDRESS_LO", CMIC_COMMON_POOL_FIFO_CH5_RD_DMA_ECCERR_ADDRESS_LOr }, \ 1023 { 0x000112b0, "CMIC_COMMON_POOL_FIFO_CH5_RD_DMA_ECCERR_ADDRESS_HI", CMIC_COMMON_POOL_FIFO_CH5_RD_DMA_ECCERR_ADDRESS_HIr }, \ 1024 { 0x000112b4, "CMIC_COMMON_POOL_FIFO_CH5_RD_DMA_ECC_CONTROL", CMIC_COMMON_POOL_FIFO_CH5_RD_DMA_ECC_CONTROLr }, \ 1025 { 0x000112b8, "CMIC_COMMON_POOL_FIFO_CH5_RD_DMA_ECC_STATUS", CMIC_COMMON_POOL_FIFO_CH5_RD_DMA_ECC_STATUSr }, \ 1026 { 0x000112bc, "CMIC_COMMON_POOL_FIFO_CH5_RD_DMA_ECC_STATUS_CLR", CMIC_COMMON_POOL_FIFO_CH5_RD_DMA_ECC_STATUS_CLRr }, \ 1027 { 0x000112c0, "CMIC_COMMON_POOL_FIFO_CH5_RD_DMA_TM_CONTROL", CMIC_COMMON_POOL_FIFO_CH5_RD_DMA_TM_CONTROLr }, \ 1028 { 0x000112c4, "CMIC_COMMON_POOL_FIFO_CH5_RD_DMA_CUR_HOSTMEM_WRITE_PTR_LO", CMIC_COMMON_POOL_FIFO_CH5_RD_DMA_CUR_HOSTMEM_WRITE_PTR_LOr }, \ 1029 { 0x000112c8, "CMIC_COMMON_POOL_FIFO_CH5_RD_DMA_CUR_HOSTMEM_WRITE_PTR_HI", CMIC_COMMON_POOL_FIFO_CH5_RD_DMA_CUR_HOSTMEM_WRITE_PTR_HIr }, \ 1030 { 0x00011300, "CMIC_COMMON_POOL_FIFO_CH6_RD_DMA_CFG", CMIC_COMMON_POOL_FIFO_CH6_RD_DMA_CFGr }, \ 1031 { 0x00011304, "CMIC_COMMON_POOL_FIFO_CH6_RD_DMA_CFG_1", CMIC_COMMON_POOL_FIFO_CH6_RD_DMA_CFG_1r }, \ 1032 { 0x00011308, "CMIC_COMMON_POOL_FIFO_CH6_RD_DMA_SBUS_START_ADDRESS", CMIC_COMMON_POOL_FIFO_CH6_RD_DMA_SBUS_START_ADDRESSr }, \ 1033 { 0x0001130c, "CMIC_COMMON_POOL_FIFO_CH6_RD_DMA_HOSTMEM_START_ADDRESS_LO", CMIC_COMMON_POOL_FIFO_CH6_RD_DMA_HOSTMEM_START_ADDRESS_LOr }, \ 1034 { 0x00011310, "CMIC_COMMON_POOL_FIFO_CH6_RD_DMA_HOSTMEM_START_ADDRESS_HI", CMIC_COMMON_POOL_FIFO_CH6_RD_DMA_HOSTMEM_START_ADDRESS_HIr }, \ 1035 { 0x00011314, "CMIC_COMMON_POOL_FIFO_CH6_RD_DMA_NUM_OF_ENTRIES_READ_FRM_HOSTMEM", CMIC_COMMON_POOL_FIFO_CH6_RD_DMA_NUM_OF_ENTRIES_READ_FRM_HOSTMEMr }, \ 1036 { 0x00011318, "CMIC_COMMON_POOL_FIFO_CH6_RD_DMA_NUM_OF_ENTRIES_VALID_IN_HOSTMEM", CMIC_COMMON_POOL_FIFO_CH6_RD_DMA_NUM_OF_ENTRIES_VALID_IN_HOSTMEMr }, \ 1037 { 0x0001131c, "CMIC_COMMON_POOL_FIFO_CH6_RD_DMA_HOSTMEM_THRESHOLD", CMIC_COMMON_POOL_FIFO_CH6_RD_DMA_HOSTMEM_THRESHOLDr }, \ 1038 { 0x00011320, "CMIC_COMMON_POOL_FIFO_CH6_RD_DMA_STAT", CMIC_COMMON_POOL_FIFO_CH6_RD_DMA_STATr }, \ 1039 { 0x00011324, "CMIC_COMMON_POOL_FIFO_CH6_RD_DMA_STAT_CLR", CMIC_COMMON_POOL_FIFO_CH6_RD_DMA_STAT_CLRr }, \ 1040 { 0x00011328, "CMIC_COMMON_POOL_FIFO_CH6_RD_DMA_OPCODE", CMIC_COMMON_POOL_FIFO_CH6_RD_DMA_OPCODEr }, \ 1041 { 0x0001132c, "CMIC_COMMON_POOL_FIFO_CH6_RD_DMA_ECCERR_ADDRESS_LO", CMIC_COMMON_POOL_FIFO_CH6_RD_DMA_ECCERR_ADDRESS_LOr }, \ 1042 { 0x00011330, "CMIC_COMMON_POOL_FIFO_CH6_RD_DMA_ECCERR_ADDRESS_HI", CMIC_COMMON_POOL_FIFO_CH6_RD_DMA_ECCERR_ADDRESS_HIr }, \ 1043 { 0x00011334, "CMIC_COMMON_POOL_FIFO_CH6_RD_DMA_ECC_CONTROL", CMIC_COMMON_POOL_FIFO_CH6_RD_DMA_ECC_CONTROLr }, \ 1044 { 0x00011338, "CMIC_COMMON_POOL_FIFO_CH6_RD_DMA_ECC_STATUS", CMIC_COMMON_POOL_FIFO_CH6_RD_DMA_ECC_STATUSr }, \ 1045 { 0x0001133c, "CMIC_COMMON_POOL_FIFO_CH6_RD_DMA_ECC_STATUS_CLR", CMIC_COMMON_POOL_FIFO_CH6_RD_DMA_ECC_STATUS_CLRr }, \ 1046 { 0x00011340, "CMIC_COMMON_POOL_FIFO_CH6_RD_DMA_TM_CONTROL", CMIC_COMMON_POOL_FIFO_CH6_RD_DMA_TM_CONTROLr }, \ 1047 { 0x00011344, "CMIC_COMMON_POOL_FIFO_CH6_RD_DMA_CUR_HOSTMEM_WRITE_PTR_LO", CMIC_COMMON_POOL_FIFO_CH6_RD_DMA_CUR_HOSTMEM_WRITE_PTR_LOr }, \ 1048 { 0x00011348, "CMIC_COMMON_POOL_FIFO_CH6_RD_DMA_CUR_HOSTMEM_WRITE_PTR_HI", CMIC_COMMON_POOL_FIFO_CH6_RD_DMA_CUR_HOSTMEM_WRITE_PTR_HIr }, \ 1049 { 0x00011380, "CMIC_COMMON_POOL_FIFO_CH7_RD_DMA_CFG", CMIC_COMMON_POOL_FIFO_CH7_RD_DMA_CFGr }, \ 1050 { 0x00011384, "CMIC_COMMON_POOL_FIFO_CH7_RD_DMA_CFG_1", CMIC_COMMON_POOL_FIFO_CH7_RD_DMA_CFG_1r }, \ 1051 { 0x00011388, "CMIC_COMMON_POOL_FIFO_CH7_RD_DMA_SBUS_START_ADDRESS", CMIC_COMMON_POOL_FIFO_CH7_RD_DMA_SBUS_START_ADDRESSr }, \ 1052 { 0x0001138c, "CMIC_COMMON_POOL_FIFO_CH7_RD_DMA_HOSTMEM_START_ADDRESS_LO", CMIC_COMMON_POOL_FIFO_CH7_RD_DMA_HOSTMEM_START_ADDRESS_LOr }, \ 1053 { 0x00011390, "CMIC_COMMON_POOL_FIFO_CH7_RD_DMA_HOSTMEM_START_ADDRESS_HI", CMIC_COMMON_POOL_FIFO_CH7_RD_DMA_HOSTMEM_START_ADDRESS_HIr }, \ 1054 { 0x00011394, "CMIC_COMMON_POOL_FIFO_CH7_RD_DMA_NUM_OF_ENTRIES_READ_FRM_HOSTMEM", CMIC_COMMON_POOL_FIFO_CH7_RD_DMA_NUM_OF_ENTRIES_READ_FRM_HOSTMEMr }, \ 1055 { 0x00011398, "CMIC_COMMON_POOL_FIFO_CH7_RD_DMA_NUM_OF_ENTRIES_VALID_IN_HOSTMEM", CMIC_COMMON_POOL_FIFO_CH7_RD_DMA_NUM_OF_ENTRIES_VALID_IN_HOSTMEMr }, \ 1056 { 0x0001139c, "CMIC_COMMON_POOL_FIFO_CH7_RD_DMA_HOSTMEM_THRESHOLD", CMIC_COMMON_POOL_FIFO_CH7_RD_DMA_HOSTMEM_THRESHOLDr }, \ 1057 { 0x000113a0, "CMIC_COMMON_POOL_FIFO_CH7_RD_DMA_STAT", CMIC_COMMON_POOL_FIFO_CH7_RD_DMA_STATr }, \ 1058 { 0x000113a4, "CMIC_COMMON_POOL_FIFO_CH7_RD_DMA_STAT_CLR", CMIC_COMMON_POOL_FIFO_CH7_RD_DMA_STAT_CLRr }, \ 1059 { 0x000113a8, "CMIC_COMMON_POOL_FIFO_CH7_RD_DMA_OPCODE", CMIC_COMMON_POOL_FIFO_CH7_RD_DMA_OPCODEr }, \ 1060 { 0x000113ac, "CMIC_COMMON_POOL_FIFO_CH7_RD_DMA_ECCERR_ADDRESS_LO", CMIC_COMMON_POOL_FIFO_CH7_RD_DMA_ECCERR_ADDRESS_LOr }, \ 1061 { 0x000113b0, "CMIC_COMMON_POOL_FIFO_CH7_RD_DMA_ECCERR_ADDRESS_HI", CMIC_COMMON_POOL_FIFO_CH7_RD_DMA_ECCERR_ADDRESS_HIr }, \ 1062 { 0x000113b4, "CMIC_COMMON_POOL_FIFO_CH7_RD_DMA_ECC_CONTROL", CMIC_COMMON_POOL_FIFO_CH7_RD_DMA_ECC_CONTROLr }, \ 1063 { 0x000113b8, "CMIC_COMMON_POOL_FIFO_CH7_RD_DMA_ECC_STATUS", CMIC_COMMON_POOL_FIFO_CH7_RD_DMA_ECC_STATUSr }, \ 1064 { 0x000113bc, "CMIC_COMMON_POOL_FIFO_CH7_RD_DMA_ECC_STATUS_CLR", CMIC_COMMON_POOL_FIFO_CH7_RD_DMA_ECC_STATUS_CLRr }, \ 1065 { 0x000113c0, "CMIC_COMMON_POOL_FIFO_CH7_RD_DMA_TM_CONTROL", CMIC_COMMON_POOL_FIFO_CH7_RD_DMA_TM_CONTROLr }, \ 1066 { 0x000113c4, "CMIC_COMMON_POOL_FIFO_CH7_RD_DMA_CUR_HOSTMEM_WRITE_PTR_LO", CMIC_COMMON_POOL_FIFO_CH7_RD_DMA_CUR_HOSTMEM_WRITE_PTR_LOr }, \ 1067 { 0x000113c8, "CMIC_COMMON_POOL_FIFO_CH7_RD_DMA_CUR_HOSTMEM_WRITE_PTR_HI", CMIC_COMMON_POOL_FIFO_CH7_RD_DMA_CUR_HOSTMEM_WRITE_PTR_HIr }, \ 1068 { 0x00011400, "CMIC_COMMON_POOL_FIFO_CH8_RD_DMA_CFG", CMIC_COMMON_POOL_FIFO_CH8_RD_DMA_CFGr }, \ 1069 { 0x00011404, "CMIC_COMMON_POOL_FIFO_CH8_RD_DMA_CFG_1", CMIC_COMMON_POOL_FIFO_CH8_RD_DMA_CFG_1r }, \ 1070 { 0x00011408, "CMIC_COMMON_POOL_FIFO_CH8_RD_DMA_SBUS_START_ADDRESS", CMIC_COMMON_POOL_FIFO_CH8_RD_DMA_SBUS_START_ADDRESSr }, \ 1071 { 0x0001140c, "CMIC_COMMON_POOL_FIFO_CH8_RD_DMA_HOSTMEM_START_ADDRESS_LO", CMIC_COMMON_POOL_FIFO_CH8_RD_DMA_HOSTMEM_START_ADDRESS_LOr }, \ 1072 { 0x00011410, "CMIC_COMMON_POOL_FIFO_CH8_RD_DMA_HOSTMEM_START_ADDRESS_HI", CMIC_COMMON_POOL_FIFO_CH8_RD_DMA_HOSTMEM_START_ADDRESS_HIr }, \ 1073 { 0x00011414, "CMIC_COMMON_POOL_FIFO_CH8_RD_DMA_NUM_OF_ENTRIES_READ_FRM_HOSTMEM", CMIC_COMMON_POOL_FIFO_CH8_RD_DMA_NUM_OF_ENTRIES_READ_FRM_HOSTMEMr }, \ 1074 { 0x00011418, "CMIC_COMMON_POOL_FIFO_CH8_RD_DMA_NUM_OF_ENTRIES_VALID_IN_HOSTMEM", CMIC_COMMON_POOL_FIFO_CH8_RD_DMA_NUM_OF_ENTRIES_VALID_IN_HOSTMEMr }, \ 1075 { 0x0001141c, "CMIC_COMMON_POOL_FIFO_CH8_RD_DMA_HOSTMEM_THRESHOLD", CMIC_COMMON_POOL_FIFO_CH8_RD_DMA_HOSTMEM_THRESHOLDr }, \ 1076 { 0x00011420, "CMIC_COMMON_POOL_FIFO_CH8_RD_DMA_STAT", CMIC_COMMON_POOL_FIFO_CH8_RD_DMA_STATr }, \ 1077 { 0x00011424, "CMIC_COMMON_POOL_FIFO_CH8_RD_DMA_STAT_CLR", CMIC_COMMON_POOL_FIFO_CH8_RD_DMA_STAT_CLRr }, \ 1078 { 0x00011428, "CMIC_COMMON_POOL_FIFO_CH8_RD_DMA_OPCODE", CMIC_COMMON_POOL_FIFO_CH8_RD_DMA_OPCODEr }, \ 1079 { 0x0001142c, "CMIC_COMMON_POOL_FIFO_CH8_RD_DMA_ECCERR_ADDRESS_LO", CMIC_COMMON_POOL_FIFO_CH8_RD_DMA_ECCERR_ADDRESS_LOr }, \ 1080 { 0x00011430, "CMIC_COMMON_POOL_FIFO_CH8_RD_DMA_ECCERR_ADDRESS_HI", CMIC_COMMON_POOL_FIFO_CH8_RD_DMA_ECCERR_ADDRESS_HIr }, \ 1081 { 0x00011434, "CMIC_COMMON_POOL_FIFO_CH8_RD_DMA_ECC_CONTROL", CMIC_COMMON_POOL_FIFO_CH8_RD_DMA_ECC_CONTROLr }, \ 1082 { 0x00011438, "CMIC_COMMON_POOL_FIFO_CH8_RD_DMA_ECC_STATUS", CMIC_COMMON_POOL_FIFO_CH8_RD_DMA_ECC_STATUSr }, \ 1083 { 0x0001143c, "CMIC_COMMON_POOL_FIFO_CH8_RD_DMA_ECC_STATUS_CLR", CMIC_COMMON_POOL_FIFO_CH8_RD_DMA_ECC_STATUS_CLRr }, \ 1084 { 0x00011440, "CMIC_COMMON_POOL_FIFO_CH8_RD_DMA_TM_CONTROL", CMIC_COMMON_POOL_FIFO_CH8_RD_DMA_TM_CONTROLr }, \ 1085 { 0x00011444, "CMIC_COMMON_POOL_FIFO_CH8_RD_DMA_CUR_HOSTMEM_WRITE_PTR_LO", CMIC_COMMON_POOL_FIFO_CH8_RD_DMA_CUR_HOSTMEM_WRITE_PTR_LOr }, \ 1086 { 0x00011448, "CMIC_COMMON_POOL_FIFO_CH8_RD_DMA_CUR_HOSTMEM_WRITE_PTR_HI", CMIC_COMMON_POOL_FIFO_CH8_RD_DMA_CUR_HOSTMEM_WRITE_PTR_HIr }, \ 1087 { 0x00011480, "CMIC_COMMON_POOL_FIFO_CH9_RD_DMA_CFG", CMIC_COMMON_POOL_FIFO_CH9_RD_DMA_CFGr }, \ 1088 { 0x00011484, "CMIC_COMMON_POOL_FIFO_CH9_RD_DMA_CFG_1", CMIC_COMMON_POOL_FIFO_CH9_RD_DMA_CFG_1r }, \ 1089 { 0x00011488, "CMIC_COMMON_POOL_FIFO_CH9_RD_DMA_SBUS_START_ADDRESS", CMIC_COMMON_POOL_FIFO_CH9_RD_DMA_SBUS_START_ADDRESSr }, \ 1090 { 0x0001148c, "CMIC_COMMON_POOL_FIFO_CH9_RD_DMA_HOSTMEM_START_ADDRESS_LO", CMIC_COMMON_POOL_FIFO_CH9_RD_DMA_HOSTMEM_START_ADDRESS_LOr }, \ 1091 { 0x00011490, "CMIC_COMMON_POOL_FIFO_CH9_RD_DMA_HOSTMEM_START_ADDRESS_HI", CMIC_COMMON_POOL_FIFO_CH9_RD_DMA_HOSTMEM_START_ADDRESS_HIr }, \ 1092 { 0x00011494, "CMIC_COMMON_POOL_FIFO_CH9_RD_DMA_NUM_OF_ENTRIES_READ_FRM_HOSTMEM", CMIC_COMMON_POOL_FIFO_CH9_RD_DMA_NUM_OF_ENTRIES_READ_FRM_HOSTMEMr }, \ 1093 { 0x00011498, "CMIC_COMMON_POOL_FIFO_CH9_RD_DMA_NUM_OF_ENTRIES_VALID_IN_HOSTMEM", CMIC_COMMON_POOL_FIFO_CH9_RD_DMA_NUM_OF_ENTRIES_VALID_IN_HOSTMEMr }, \ 1094 { 0x0001149c, "CMIC_COMMON_POOL_FIFO_CH9_RD_DMA_HOSTMEM_THRESHOLD", CMIC_COMMON_POOL_FIFO_CH9_RD_DMA_HOSTMEM_THRESHOLDr }, \ 1095 { 0x000114a0, "CMIC_COMMON_POOL_FIFO_CH9_RD_DMA_STAT", CMIC_COMMON_POOL_FIFO_CH9_RD_DMA_STATr }, \ 1096 { 0x000114a4, "CMIC_COMMON_POOL_FIFO_CH9_RD_DMA_STAT_CLR", CMIC_COMMON_POOL_FIFO_CH9_RD_DMA_STAT_CLRr }, \ 1097 { 0x000114a8, "CMIC_COMMON_POOL_FIFO_CH9_RD_DMA_OPCODE", CMIC_COMMON_POOL_FIFO_CH9_RD_DMA_OPCODEr }, \ 1098 { 0x000114ac, "CMIC_COMMON_POOL_FIFO_CH9_RD_DMA_ECCERR_ADDRESS_LO", CMIC_COMMON_POOL_FIFO_CH9_RD_DMA_ECCERR_ADDRESS_LOr }, \ 1099 { 0x000114b0, "CMIC_COMMON_POOL_FIFO_CH9_RD_DMA_ECCERR_ADDRESS_HI", CMIC_COMMON_POOL_FIFO_CH9_RD_DMA_ECCERR_ADDRESS_HIr }, \ 1100 { 0x000114b4, "CMIC_COMMON_POOL_FIFO_CH9_RD_DMA_ECC_CONTROL", CMIC_COMMON_POOL_FIFO_CH9_RD_DMA_ECC_CONTROLr }, \ 1101 { 0x000114b8, "CMIC_COMMON_POOL_FIFO_CH9_RD_DMA_ECC_STATUS", CMIC_COMMON_POOL_FIFO_CH9_RD_DMA_ECC_STATUSr }, \ 1102 { 0x000114bc, "CMIC_COMMON_POOL_FIFO_CH9_RD_DMA_ECC_STATUS_CLR", CMIC_COMMON_POOL_FIFO_CH9_RD_DMA_ECC_STATUS_CLRr }, \ 1103 { 0x000114c0, "CMIC_COMMON_POOL_FIFO_CH9_RD_DMA_TM_CONTROL", CMIC_COMMON_POOL_FIFO_CH9_RD_DMA_TM_CONTROLr }, \ 1104 { 0x000114c4, "CMIC_COMMON_POOL_FIFO_CH9_RD_DMA_CUR_HOSTMEM_WRITE_PTR_LO", CMIC_COMMON_POOL_FIFO_CH9_RD_DMA_CUR_HOSTMEM_WRITE_PTR_LOr }, \ 1105 { 0x000114c8, "CMIC_COMMON_POOL_FIFO_CH9_RD_DMA_CUR_HOSTMEM_WRITE_PTR_HI", CMIC_COMMON_POOL_FIFO_CH9_RD_DMA_CUR_HOSTMEM_WRITE_PTR_HIr }, \ 1106 { 0x00011500, "CMIC_COMMON_POOL_FIFO_CH10_RD_DMA_CFG", CMIC_COMMON_POOL_FIFO_CH10_RD_DMA_CFGr }, \ 1107 { 0x00011504, "CMIC_COMMON_POOL_FIFO_CH10_RD_DMA_CFG_1", CMIC_COMMON_POOL_FIFO_CH10_RD_DMA_CFG_1r }, \ 1108 { 0x00011508, "CMIC_COMMON_POOL_FIFO_CH10_RD_DMA_SBUS_START_ADDRESS", CMIC_COMMON_POOL_FIFO_CH10_RD_DMA_SBUS_START_ADDRESSr }, \ 1109 { 0x0001150c, "CMIC_COMMON_POOL_FIFO_CH10_RD_DMA_HOSTMEM_START_ADDRESS_LO", CMIC_COMMON_POOL_FIFO_CH10_RD_DMA_HOSTMEM_START_ADDRESS_LOr }, \ 1110 { 0x00011510, "CMIC_COMMON_POOL_FIFO_CH10_RD_DMA_HOSTMEM_START_ADDRESS_HI", CMIC_COMMON_POOL_FIFO_CH10_RD_DMA_HOSTMEM_START_ADDRESS_HIr }, \ 1111 { 0x00011514, "CMIC_COMMON_POOL_FIFO_CH10_RD_DMA_NUM_OF_ENTRIES_READ_FRM_HOSTMEM", CMIC_COMMON_POOL_FIFO_CH10_RD_DMA_NUM_OF_ENTRIES_READ_FRM_HOSTMEMr }, \ 1112 { 0x00011518, "CMIC_COMMON_POOL_FIFO_CH10_RD_DMA_NUM_OF_ENTRIES_VALID_IN_HOSTMEM", CMIC_COMMON_POOL_FIFO_CH10_RD_DMA_NUM_OF_ENTRIES_VALID_IN_HOSTMEMr }, \ 1113 { 0x0001151c, "CMIC_COMMON_POOL_FIFO_CH10_RD_DMA_HOSTMEM_THRESHOLD", CMIC_COMMON_POOL_FIFO_CH10_RD_DMA_HOSTMEM_THRESHOLDr }, \ 1114 { 0x00011520, "CMIC_COMMON_POOL_FIFO_CH10_RD_DMA_STAT", CMIC_COMMON_POOL_FIFO_CH10_RD_DMA_STATr }, \ 1115 { 0x00011524, "CMIC_COMMON_POOL_FIFO_CH10_RD_DMA_STAT_CLR", CMIC_COMMON_POOL_FIFO_CH10_RD_DMA_STAT_CLRr }, \ 1116 { 0x00011528, "CMIC_COMMON_POOL_FIFO_CH10_RD_DMA_OPCODE", CMIC_COMMON_POOL_FIFO_CH10_RD_DMA_OPCODEr }, \ 1117 { 0x0001152c, "CMIC_COMMON_POOL_FIFO_CH10_RD_DMA_ECCERR_ADDRESS_LO", CMIC_COMMON_POOL_FIFO_CH10_RD_DMA_ECCERR_ADDRESS_LOr }, \ 1118 { 0x00011530, "CMIC_COMMON_POOL_FIFO_CH10_RD_DMA_ECCERR_ADDRESS_HI", CMIC_COMMON_POOL_FIFO_CH10_RD_DMA_ECCERR_ADDRESS_HIr }, \ 1119 { 0x00011534, "CMIC_COMMON_POOL_FIFO_CH10_RD_DMA_ECC_CONTROL", CMIC_COMMON_POOL_FIFO_CH10_RD_DMA_ECC_CONTROLr }, \ 1120 { 0x00011538, "CMIC_COMMON_POOL_FIFO_CH10_RD_DMA_ECC_STATUS", CMIC_COMMON_POOL_FIFO_CH10_RD_DMA_ECC_STATUSr }, \ 1121 { 0x0001153c, "CMIC_COMMON_POOL_FIFO_CH10_RD_DMA_ECC_STATUS_CLR", CMIC_COMMON_POOL_FIFO_CH10_RD_DMA_ECC_STATUS_CLRr }, \ 1122 { 0x00011540, "CMIC_COMMON_POOL_FIFO_CH10_RD_DMA_TM_CONTROL", CMIC_COMMON_POOL_FIFO_CH10_RD_DMA_TM_CONTROLr }, \ 1123 { 0x00011544, "CMIC_COMMON_POOL_FIFO_CH10_RD_DMA_CUR_HOSTMEM_WRITE_PTR_LO", CMIC_COMMON_POOL_FIFO_CH10_RD_DMA_CUR_HOSTMEM_WRITE_PTR_LOr }, \ 1124 { 0x00011548, "CMIC_COMMON_POOL_FIFO_CH10_RD_DMA_CUR_HOSTMEM_WRITE_PTR_HI", CMIC_COMMON_POOL_FIFO_CH10_RD_DMA_CUR_HOSTMEM_WRITE_PTR_HIr }, \ 1125 { 0x00011580, "CMIC_COMMON_POOL_FIFO_CH11_RD_DMA_CFG", CMIC_COMMON_POOL_FIFO_CH11_RD_DMA_CFGr }, \ 1126 { 0x00011584, "CMIC_COMMON_POOL_FIFO_CH11_RD_DMA_CFG_1", CMIC_COMMON_POOL_FIFO_CH11_RD_DMA_CFG_1r }, \ 1127 { 0x00011588, "CMIC_COMMON_POOL_FIFO_CH11_RD_DMA_SBUS_START_ADDRESS", CMIC_COMMON_POOL_FIFO_CH11_RD_DMA_SBUS_START_ADDRESSr }, \ 1128 { 0x0001158c, "CMIC_COMMON_POOL_FIFO_CH11_RD_DMA_HOSTMEM_START_ADDRESS_LO", CMIC_COMMON_POOL_FIFO_CH11_RD_DMA_HOSTMEM_START_ADDRESS_LOr }, \ 1129 { 0x00011590, "CMIC_COMMON_POOL_FIFO_CH11_RD_DMA_HOSTMEM_START_ADDRESS_HI", CMIC_COMMON_POOL_FIFO_CH11_RD_DMA_HOSTMEM_START_ADDRESS_HIr }, \ 1130 { 0x00011594, "CMIC_COMMON_POOL_FIFO_CH11_RD_DMA_NUM_OF_ENTRIES_READ_FRM_HOSTMEM", CMIC_COMMON_POOL_FIFO_CH11_RD_DMA_NUM_OF_ENTRIES_READ_FRM_HOSTMEMr }, \ 1131 { 0x00011598, "CMIC_COMMON_POOL_FIFO_CH11_RD_DMA_NUM_OF_ENTRIES_VALID_IN_HOSTMEM", CMIC_COMMON_POOL_FIFO_CH11_RD_DMA_NUM_OF_ENTRIES_VALID_IN_HOSTMEMr }, \ 1132 { 0x0001159c, "CMIC_COMMON_POOL_FIFO_CH11_RD_DMA_HOSTMEM_THRESHOLD", CMIC_COMMON_POOL_FIFO_CH11_RD_DMA_HOSTMEM_THRESHOLDr }, \ 1133 { 0x000115a0, "CMIC_COMMON_POOL_FIFO_CH11_RD_DMA_STAT", CMIC_COMMON_POOL_FIFO_CH11_RD_DMA_STATr }, \ 1134 { 0x000115a4, "CMIC_COMMON_POOL_FIFO_CH11_RD_DMA_STAT_CLR", CMIC_COMMON_POOL_FIFO_CH11_RD_DMA_STAT_CLRr }, \ 1135 { 0x000115a8, "CMIC_COMMON_POOL_FIFO_CH11_RD_DMA_OPCODE", CMIC_COMMON_POOL_FIFO_CH11_RD_DMA_OPCODEr }, \ 1136 { 0x000115ac, "CMIC_COMMON_POOL_FIFO_CH11_RD_DMA_ECCERR_ADDRESS_LO", CMIC_COMMON_POOL_FIFO_CH11_RD_DMA_ECCERR_ADDRESS_LOr }, \ 1137 { 0x000115b0, "CMIC_COMMON_POOL_FIFO_CH11_RD_DMA_ECCERR_ADDRESS_HI", CMIC_COMMON_POOL_FIFO_CH11_RD_DMA_ECCERR_ADDRESS_HIr }, \ 1138 { 0x000115b4, "CMIC_COMMON_POOL_FIFO_CH11_RD_DMA_ECC_CONTROL", CMIC_COMMON_POOL_FIFO_CH11_RD_DMA_ECC_CONTROLr }, \ 1139 { 0x000115b8, "CMIC_COMMON_POOL_FIFO_CH11_RD_DMA_ECC_STATUS", CMIC_COMMON_POOL_FIFO_CH11_RD_DMA_ECC_STATUSr }, \ 1140 { 0x000115bc, "CMIC_COMMON_POOL_FIFO_CH11_RD_DMA_ECC_STATUS_CLR", CMIC_COMMON_POOL_FIFO_CH11_RD_DMA_ECC_STATUS_CLRr }, \ 1141 { 0x000115c0, "CMIC_COMMON_POOL_FIFO_CH11_RD_DMA_TM_CONTROL", CMIC_COMMON_POOL_FIFO_CH11_RD_DMA_TM_CONTROLr }, \ 1142 { 0x000115c4, "CMIC_COMMON_POOL_FIFO_CH11_RD_DMA_CUR_HOSTMEM_WRITE_PTR_LO", CMIC_COMMON_POOL_FIFO_CH11_RD_DMA_CUR_HOSTMEM_WRITE_PTR_LOr }, \ 1143 { 0x000115c8, "CMIC_COMMON_POOL_FIFO_CH11_RD_DMA_CUR_HOSTMEM_WRITE_PTR_HI", CMIC_COMMON_POOL_FIFO_CH11_RD_DMA_CUR_HOSTMEM_WRITE_PTR_HIr }, \ 1144 { 0x00012000, "CMIC_COMMON_POOL_SCHAN_FIFO_0_ECC_CTRL", CMIC_COMMON_POOL_SCHAN_FIFO_0_ECC_CTRLr }, \ 1145 { 0x00012004, "CMIC_COMMON_POOL_SCHAN_FIFO_0_ECC_STATUS", CMIC_COMMON_POOL_SCHAN_FIFO_0_ECC_STATUSr }, \ 1146 { 0x00012008, "CMIC_COMMON_POOL_SCHAN_FIFO_0_TM_CTRL", CMIC_COMMON_POOL_SCHAN_FIFO_0_TM_CTRLr }, \ 1147 { 0x0001200c, "CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_CTRL", CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_CTRLr }, \ 1148 { 0x00012010, "CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_RESP_HOSTMEM_START_ADDR_UPPER", CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_RESP_HOSTMEM_START_ADDR_UPPERr }, \ 1149 { 0x00012014, "CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_RESP_HOSTMEM_START_ADDR_LOWER", CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_RESP_HOSTMEM_START_ADDR_LOWERr }, \ 1150 { 0x00012018, "CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_SUMMARY_HOSTMEM_START_ADDR_UPPER", CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_SUMMARY_HOSTMEM_START_ADDR_UPPERr }, \ 1151 { 0x0001201c, "CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_SUMMARY_HOSTMEM_START_ADDR_LOWER", CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_SUMMARY_HOSTMEM_START_ADDR_LOWERr }, \ 1152 { 0x00012020, "CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_STATUS", CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_STATUSr }, \ 1153 { 0x00012024, "CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_CTRL", CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_CTRLr }, \ 1154 { 0x00012028, "CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_RESP_HOSTMEM_START_ADDR_UPPER", CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_RESP_HOSTMEM_START_ADDR_UPPERr }, \ 1155 { 0x0001202c, "CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_RESP_HOSTMEM_START_ADDR_LOWER", CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_RESP_HOSTMEM_START_ADDR_LOWERr }, \ 1156 { 0x00012030, "CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_SUMMARY_HOSTMEM_START_ADDR_UPPER", CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_SUMMARY_HOSTMEM_START_ADDR_UPPERr }, \ 1157 { 0x00012034, "CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_SUMMARY_HOSTMEM_START_ADDR_LOWER", CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_SUMMARY_HOSTMEM_START_ADDR_LOWERr }, \ 1158 { 0x00012038, "CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_STATUS", CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_STATUSr }, \ 1159 { 0x00012100, "CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY", CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORYr }, \ 1160 { 0x00012680, "CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY", CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORYr }, \ 1161 { 0x00016000, "CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_0", CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_0r }, \ 1162 { 0x00016004, "CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_1", CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_1r }, \ 1163 { 0x00016008, "CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_2", CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_2r }, \ 1164 { 0x0001600c, "CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_3", CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_3r }, \ 1165 { 0x00016010, "CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_4", CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_4r }, \ 1166 { 0x00016014, "CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_5", CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_5r }, \ 1167 { 0x00016018, "CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_6", CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_6r }, \ 1168 { 0x0001601c, "CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_7", CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_7r }, \ 1169 { 0x00016020, "CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_8", CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_8r }, \ 1170 { 0x00016024, "CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_9", CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_9r }, \ 1171 { 0x00016028, "CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_10", CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_10r }, \ 1172 { 0x0001602c, "CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_11", CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_11r }, \ 1173 { 0x00016030, "CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_12", CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_12r }, \ 1174 { 0x00016034, "CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_13", CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_13r }, \ 1175 { 0x00016038, "CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_14", CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_14r }, \ 1176 { 0x0001603c, "CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_15", CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_15r }, \ 1177 { 0x00016040, "CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_16", CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_16r }, \ 1178 { 0x00016044, "CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_17", CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_17r }, \ 1179 { 0x00016048, "CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_18", CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_18r }, \ 1180 { 0x0001604c, "CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_19", CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_19r }, \ 1181 { 0x00016050, "CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_20", CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_20r }, \ 1182 { 0x00016054, "CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_21", CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_21r }, \ 1183 { 0x00016058, "CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_22", CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_22r }, \ 1184 { 0x0001605c, "CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_23", CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_23r }, \ 1185 { 0x00016060, "CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_24", CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_24r }, \ 1186 { 0x00016064, "CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_25", CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_25r }, \ 1187 { 0x00016068, "CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_26", CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_26r }, \ 1188 { 0x0001606c, "CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_27", CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_27r }, \ 1189 { 0x00016070, "CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_28", CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_28r }, \ 1190 { 0x00016074, "CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_29", CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_29r }, \ 1191 { 0x00016078, "CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_30", CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_30r }, \ 1192 { 0x0001607c, "CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_31", CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_31r }, \ 1193 { 0x00016080, "CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_32", CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_32r }, \ 1194 { 0x00016084, "CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_33", CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_33r }, \ 1195 { 0x00016088, "CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_34", CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_34r }, \ 1196 { 0x0001608c, "CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_35", CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_35r }, \ 1197 { 0x00016090, "CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_36", CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_36r }, \ 1198 { 0x00016094, "CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_37", CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_37r }, \ 1199 { 0x00016098, "CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_38", CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_38r }, \ 1200 { 0x0001609c, "CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_39", CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_39r }, \ 1201 { 0x000160a0, "CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_40", CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_40r }, \ 1202 { 0x000160a4, "CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_41", CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_41r }, \ 1203 { 0x000160a8, "CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_42", CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_42r }, \ 1204 { 0x000160ac, "CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_43", CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_43r }, \ 1205 { 0x000160b0, "CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_44", CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_44r }, \ 1206 { 0x000160b4, "CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_45", CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_45r }, \ 1207 { 0x000160b8, "CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_46", CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_46r }, \ 1208 { 0x000160bc, "CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_47", CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_47r }, \ 1209 { 0x000160c0, "CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_48", CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_48r }, \ 1210 { 0x000160c4, "CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_49", CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_49r }, \ 1211 { 0x000160c8, "CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_50", CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_50r }, \ 1212 { 0x000160cc, "CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_51", CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_51r }, \ 1213 { 0x000160d0, "CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_52", CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_52r }, \ 1214 { 0x000160d4, "CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_53", CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_53r }, \ 1215 { 0x000160d8, "CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_54", CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_54r }, \ 1216 { 0x000160dc, "CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_55", CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_55r }, \ 1217 { 0x000160e0, "CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_56", CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_56r }, \ 1218 { 0x000160e4, "CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_57", CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_57r }, \ 1219 { 0x000160e8, "CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_58", CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_58r }, \ 1220 { 0x000160ec, "CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_59", CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_59r }, \ 1221 { 0x000160f0, "CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_60", CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_60r }, \ 1222 { 0x000160f4, "CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_61", CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_61r }, \ 1223 { 0x000160f8, "CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_62", CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_62r }, \ 1224 { 0x000160fc, "CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_63", CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_63r }, \ 1225 { 0x00016100, "CMIC_RPE_PKT_CTRL", CMIC_RPE_PKT_CTRLr }, \ 1226 { 0x00016104, "CMIC_RPE_PKT_LMAC0_HI", CMIC_RPE_PKT_LMAC0_HIr }, \ 1227 { 0x00016108, "CMIC_RPE_PKT_LMAC0_LO", CMIC_RPE_PKT_LMAC0_LOr }, \ 1228 { 0x0001610c, "CMIC_RPE_PKT_LMAC1_HI", CMIC_RPE_PKT_LMAC1_HIr }, \ 1229 { 0x00016110, "CMIC_RPE_PKT_LMAC1_LO", CMIC_RPE_PKT_LMAC1_LOr }, \ 1230 { 0x00016114, "CMIC_RPE_PKT_VLAN", CMIC_RPE_PKT_VLANr }, \ 1231 { 0x00016118, "CMIC_RPE_PKT_ETHER_SIG", CMIC_RPE_PKT_ETHER_SIGr }, \ 1232 { 0x0001611c, "CMIC_RPE_PKTDMA_COS_0", CMIC_RPE_PKTDMA_COS_0r }, \ 1233 { 0x00016120, "CMIC_RPE_PKTDMA_COS_1", CMIC_RPE_PKTDMA_COS_1r }, \ 1234 { 0x00016124, "CMIC_RPE_SCHAN_SBUSDMA_COS_0", CMIC_RPE_SCHAN_SBUSDMA_COS_0r }, \ 1235 { 0x00016128, "CMIC_RPE_SCHAN_SBUSDMA_COS_1", CMIC_RPE_SCHAN_SBUSDMA_COS_1r }, \ 1236 { 0x0001612c, "CMIC_RPE_PIO_MEMDMA_COS_0", CMIC_RPE_PIO_MEMDMA_COS_0r }, \ 1237 { 0x00016130, "CMIC_RPE_PIO_MEMDMA_COS_1", CMIC_RPE_PIO_MEMDMA_COS_1r }, \ 1238 { 0x00016134, "CMIC_RPE_SHARED_PROGRAMMABLE_COS_MASK0", CMIC_RPE_SHARED_PROGRAMMABLE_COS_MASK0r }, \ 1239 { 0x00016138, "CMIC_RPE_SHARED_PROGRAMMABLE_COS_MASK1", CMIC_RPE_SHARED_PROGRAMMABLE_COS_MASK1r }, \ 1240 { 0x0001613c, "CMIC_RPE_SHARED_RXBUF_THRESHOLD_CONFIG", CMIC_RPE_SHARED_RXBUF_THRESHOLD_CONFIGr }, \ 1241 { 0x00016140, "CMIC_RPE_PKT_PORTS_0", CMIC_RPE_PKT_PORTS_0r }, \ 1242 { 0x00016144, "CMIC_RPE_PKT_PORTS_1", CMIC_RPE_PKT_PORTS_1r }, \ 1243 { 0x00016148, "CMIC_RPE_PKT_PORTS_2", CMIC_RPE_PKT_PORTS_2r }, \ 1244 { 0x0001614c, "CMIC_RPE_PKT_PORTS_3", CMIC_RPE_PKT_PORTS_3r }, \ 1245 { 0x00016150, "CMIC_RPE_PKT_PORTS_4", CMIC_RPE_PKT_PORTS_4r }, \ 1246 { 0x00016154, "CMIC_RPE_PKT_PORTS_5", CMIC_RPE_PKT_PORTS_5r }, \ 1247 { 0x00016158, "CMIC_RPE_PKT_PORTS_6", CMIC_RPE_PKT_PORTS_6r }, \ 1248 { 0x0001615c, "CMIC_RPE_PKT_PORTS_7", CMIC_RPE_PKT_PORTS_7r }, \ 1249 { 0x00016160, "CMIC_RPE_PKT_RMAC", CMIC_RPE_PKT_RMACr }, \ 1250 { 0x00016164, "CMIC_RPE_PKT_RMAC_HI", CMIC_RPE_PKT_RMAC_HIr }, \ 1251 { 0x00016168, "CMIC_RPE_PKT_RMH0", CMIC_RPE_PKT_RMH0r }, \ 1252 { 0x0001616c, "CMIC_RPE_PKT_RMH1", CMIC_RPE_PKT_RMH1r }, \ 1253 { 0x00016170, "CMIC_RPE_PKT_RMH2", CMIC_RPE_PKT_RMH2r }, \ 1254 { 0x00016174, "CMIC_RPE_PKT_RMH3", CMIC_RPE_PKT_RMH3r }, \ 1255 { 0x00016178, "CMIC_RPE_INTR_PKT_PACING_DELAY", CMIC_RPE_INTR_PKT_PACING_DELAYr }, \ 1256 { 0x0001617c, "CMIC_RPE_PKT_COS_QUEUES_HI", CMIC_RPE_PKT_COS_QUEUES_HIr }, \ 1257 { 0x00016180, "CMIC_RPE_PKT_COS_QUEUES_LO", CMIC_RPE_PKT_COS_QUEUES_LOr }, \ 1258 { 0x00016184, "CMIC_RPE_IRQ_STAT", CMIC_RPE_IRQ_STATr }, \ 1259 { 0x00016188, "CMIC_RPE_IRQ_STAT_CLR", CMIC_RPE_IRQ_STAT_CLRr }, \ 1260 { 0x0001618c, "CMIC_RPE_2BIT_ECC_ERROR_STATUS", CMIC_RPE_2BIT_ECC_ERROR_STATUSr }, \ 1261 { 0x00016190, "CMIC_RPE_2BIT_ECC_ERROR_STATUS_ENABLE", CMIC_RPE_2BIT_ECC_ERROR_STATUS_ENABLEr }, \ 1262 { 0x00016194, "CMIC_RPE_1BIT_ECC_ERROR_STATUS", CMIC_RPE_1BIT_ECC_ERROR_STATUSr }, \ 1263 { 0x00016198, "CMIC_RPE_1BIT_ECC_ERROR_STATUS_ENABLE", CMIC_RPE_1BIT_ECC_ERROR_STATUS_ENABLEr }, \ 1264 { 0x0001619c, "CMIC_RPE_PKT_COUNT_SCHAN", CMIC_RPE_PKT_COUNT_SCHANr }, \ 1265 { 0x000161a0, "CMIC_RPE_PKT_COUNT_SCHAN_REP", CMIC_RPE_PKT_COUNT_SCHAN_REPr }, \ 1266 { 0x000161a4, "CMIC_RPE_PKT_COUNT_FROMCPU_MH", CMIC_RPE_PKT_COUNT_FROMCPU_MHr }, \ 1267 { 0x000161a8, "CMIC_RPE_PKT_COUNT_FROMCPU", CMIC_RPE_PKT_COUNT_FROMCPUr }, \ 1268 { 0x000161ac, "CMIC_RPE_PKT_COUNT_TOCPUDM", CMIC_RPE_PKT_COUNT_TOCPUDMr }, \ 1269 { 0x000161b0, "CMIC_RPE_PKT_COUNT_TOCPUD", CMIC_RPE_PKT_COUNT_TOCPUDr }, \ 1270 { 0x000161b4, "CMIC_RPE_PKT_COUNT_TOCPUEM", CMIC_RPE_PKT_COUNT_TOCPUEMr }, \ 1271 { 0x000161b8, "CMIC_RPE_PKT_COUNT_TOCPUE", CMIC_RPE_PKT_COUNT_TOCPUEr }, \ 1272 { 0x000161bc, "CMIC_RPE_PKT_COUNT_PIO_REPLY", CMIC_RPE_PKT_COUNT_PIO_REPLYr }, \ 1273 { 0x000161c0, "CMIC_RPE_PKT_COUNT_PIO", CMIC_RPE_PKT_COUNT_PIOr }, \ 1274 { 0x000161c4, "CMIC_RPE_PKT_COUNT_SBUSDMA_REPLY", CMIC_RPE_PKT_COUNT_SBUSDMA_REPLYr }, \ 1275 { 0x000161c8, "CMIC_RPE_PKT_COUNT_SBUSDMA", CMIC_RPE_PKT_COUNT_SBUSDMAr }, \ 1276 { 0x000161cc, "CMIC_RPE_PKT_COUNT_MEMDMA_REPLY", CMIC_RPE_PKT_COUNT_MEMDMA_REPLYr }, \ 1277 { 0x000161d0, "CMIC_RPE_PKT_COUNT_MEMDMA", CMIC_RPE_PKT_COUNT_MEMDMAr }, \ 1278 { 0x000161d4, "CMIC_RPE_PKT_COUNT_INTR", CMIC_RPE_PKT_COUNT_INTRr }, \ 1279 { 0x000161d8, "CMIC_RPE_PKT_COUNT_SCHAN_SBUSDMA_DROP", CMIC_RPE_PKT_COUNT_SCHAN_SBUSDMA_DROPr }, \ 1280 { 0x000161dc, "CMIC_RPE_PKT_COUNT_PIO_MEMDMA_DROP", CMIC_RPE_PKT_COUNT_PIO_MEMDMA_DROPr }, \ 1281 { 0x000161e0, "CMIC_RPE_PKT_COUNT_RXPKT", CMIC_RPE_PKT_COUNT_RXPKTr }, \ 1282 { 0x000161e4, "CMIC_RPE_PKT_COUNT_RXPKT_ERR", CMIC_RPE_PKT_COUNT_RXPKT_ERRr }, \ 1283 { 0x000161e8, "CMIC_RPE_PKT_COUNT_TXPKT", CMIC_RPE_PKT_COUNT_TXPKTr }, \ 1284 { 0x000161ec, "CMIC_RPE_PKT_COUNT_TXPKT_ERR", CMIC_RPE_PKT_COUNT_TXPKT_ERRr }, \ 1285 { 0x000161f0, "CMIC_RPE_AXI_AR_COUNT_TX", CMIC_RPE_AXI_AR_COUNT_TXr }, \ 1286 { 0x000161f4, "CMIC_RPE_AXI_AR_COUNT_SPLIT_TX", CMIC_RPE_AXI_AR_COUNT_SPLIT_TXr }, \ 1287 { 0x000161f8, "CMIC_IPROC_TO_RCPU_IRQ_STAT0", CMIC_IPROC_TO_RCPU_IRQ_STAT0r }, \ 1288 { 0x000161fc, "CMIC_IPROC_TO_RCPU_IRQ_STAT1", CMIC_IPROC_TO_RCPU_IRQ_STAT1r }, \ 1289 { 0x00016200, "CMIC_IPROC_TO_RCPU_IRQ_STAT2", CMIC_IPROC_TO_RCPU_IRQ_STAT2r }, \ 1290 { 0x00016204, "CMIC_IPROC_TO_RCPU_IRQ_STAT3", CMIC_IPROC_TO_RCPU_IRQ_STAT3r }, \ 1291 { 0x00016208, "CMIC_IPROC_TO_RCPU_IRQ_STAT4", CMIC_IPROC_TO_RCPU_IRQ_STAT4r }, \ 1292 { 0x0001620c, "CMIC_IPROC_TO_RCPU_IRQ_STAT5", CMIC_IPROC_TO_RCPU_IRQ_STAT5r }, \ 1293 { 0x00016210, "CMIC_IPROC_TO_RCPU_IRQ_STAT6", CMIC_IPROC_TO_RCPU_IRQ_STAT6r }, \ 1294 { 0x00016214, "CMIC_IPROC_TO_RCPU_IRQ_STAT7", CMIC_IPROC_TO_RCPU_IRQ_STAT7r }, \ 1295 { 0x00016218, "CMIC_IPROC_TO_RCPU_IRQ_ENABLE0", CMIC_IPROC_TO_RCPU_IRQ_ENABLE0r }, \ 1296 { 0x0001621c, "CMIC_IPROC_TO_RCPU_IRQ_ENABLE1", CMIC_IPROC_TO_RCPU_IRQ_ENABLE1r }, \ 1297 { 0x00016220, "CMIC_IPROC_TO_RCPU_IRQ_ENABLE2", CMIC_IPROC_TO_RCPU_IRQ_ENABLE2r }, \ 1298 { 0x00016224, "CMIC_IPROC_TO_RCPU_IRQ_ENABLE3", CMIC_IPROC_TO_RCPU_IRQ_ENABLE3r }, \ 1299 { 0x00016228, "CMIC_IPROC_TO_RCPU_IRQ_ENABLE4", CMIC_IPROC_TO_RCPU_IRQ_ENABLE4r }, \ 1300 { 0x0001622c, "CMIC_IPROC_TO_RCPU_IRQ_ENABLE5", CMIC_IPROC_TO_RCPU_IRQ_ENABLE5r }, \ 1301 { 0x00016230, "CMIC_IPROC_TO_RCPU_IRQ_ENABLE6", CMIC_IPROC_TO_RCPU_IRQ_ENABLE6r }, \ 1302 { 0x00016234, "CMIC_IPROC_TO_RCPU_IRQ_ENABLE7", CMIC_IPROC_TO_RCPU_IRQ_ENABLE7r }, \ 1303 { 0x00016238, "CMIC_RPE_PKTDMA_RXBUF_THRESHOLD_CONFIG", CMIC_RPE_PKTDMA_RXBUF_THRESHOLD_CONFIGr }, \ 1304 { 0x0001623c, "CMIC_RPE_PIO_MEMDMA_RXBUF_THRESHOLD_CONFIG", CMIC_RPE_PIO_MEMDMA_RXBUF_THRESHOLD_CONFIGr }, \ 1305 { 0x00016240, "CMIC_RPE_SCHAN_SBUSDMA_RXBUF_THRESHOLD_CONFIG", CMIC_RPE_SCHAN_SBUSDMA_RXBUF_THRESHOLD_CONFIGr }, \ 1306 { 0x00016244, "CMIC_RPE_SCHAN_SBUSDMA_MEM_ECC_CONTROL", CMIC_RPE_SCHAN_SBUSDMA_MEM_ECC_CONTROLr }, \ 1307 { 0x00016248, "CMIC_RPE_SCHAN_SBUSDMA_MEM_TM_CONTROL", CMIC_RPE_SCHAN_SBUSDMA_MEM_TM_CONTROLr }, \ 1308 { 0x0001624c, "CMIC_RPE_SCHAN_SBUSDMA_MEM_ECC_STATUS", CMIC_RPE_SCHAN_SBUSDMA_MEM_ECC_STATUSr }, \ 1309 { 0x00016250, "CMIC_RPE_PIO_MEMDMA_MEM_ECC_CONTROL", CMIC_RPE_PIO_MEMDMA_MEM_ECC_CONTROLr }, \ 1310 { 0x00016254, "CMIC_RPE_PIO_MEMDMA_MEM_TM_CONTROL", CMIC_RPE_PIO_MEMDMA_MEM_TM_CONTROLr }, \ 1311 { 0x00016258, "CMIC_RPE_PIO_MEMDMA_MEM_ECC_STATUS", CMIC_RPE_PIO_MEMDMA_MEM_ECC_STATUSr }, \ 1312 { 0x0001625c, "CMIC_RPE_DMA_MASTER_TOTAL_OUTSTD_TRANS_LIMIT", CMIC_RPE_DMA_MASTER_TOTAL_OUTSTD_TRANS_LIMITr }, \ 1313 { 0x00016260, "CMIC_RPE_COMPLETION_BUF_MAX_FLIST_ENTRIES", CMIC_RPE_COMPLETION_BUF_MAX_FLIST_ENTRIESr }, \ 1314 { 0x00016264, "CMIC_RPE_COMPLETION_BUF_STATUS_NUM_FREE_ENTRIES", CMIC_RPE_COMPLETION_BUF_STATUS_NUM_FREE_ENTRIESr }, \ 1315 { 0x00016268, "CMIC_RPE_COMPLETION_BUF_ECC_STATUS", CMIC_RPE_COMPLETION_BUF_ECC_STATUSr }, \ 1316 { 0x0001626c, "CMIC_RPE_COMPLETION_BUF_ECC_CONTROL", CMIC_RPE_COMPLETION_BUF_ECC_CONTROLr }, \ 1317 { 0x00016270, "CMIC_RPE_COMPLETION_BUF_TM_CONTROL", CMIC_RPE_COMPLETION_BUF_TM_CONTROLr }, \ 1318 { 0x00016274, "CMIC_RPE_AXI_STAT", CMIC_RPE_AXI_STATr }, \ 1319 { 0x00016400, "CMIC_RPE_SHARED_TXBUF_MAX_BUF_LIMITS", CMIC_RPE_SHARED_TXBUF_MAX_BUF_LIMITSr }, \ 1320 { 0x00016404, "CMIC_RPE_SHARED_TXBUF_MIN_BUF_LIMITS", CMIC_RPE_SHARED_TXBUF_MIN_BUF_LIMITSr }, \ 1321 { 0x00016408, "CMIC_RPE_SHARED_TXBUF_RD_THRESHOLD_CONFIG", CMIC_RPE_SHARED_TXBUF_RD_THRESHOLD_CONFIGr }, \ 1322 { 0x0001640c, "CMIC_RPE_SHARED_TXBUF_RD_WRR_ARB_CTRL", CMIC_RPE_SHARED_TXBUF_RD_WRR_ARB_CTRLr }, \ 1323 { 0x00016410, "CMIC_RPE_SHARED_TXBUF_SLICE3_PKT_CNT", CMIC_RPE_SHARED_TXBUF_SLICE3_PKT_CNTr }, \ 1324 { 0x00016414, "CMIC_RPE_SHARED_TXBUF_SLICE2_PKT_CNT", CMIC_RPE_SHARED_TXBUF_SLICE2_PKT_CNTr }, \ 1325 { 0x00016418, "CMIC_RPE_SHARED_TXBUF_SLICE1_PKT_CNT", CMIC_RPE_SHARED_TXBUF_SLICE1_PKT_CNTr }, \ 1326 { 0x0001641c, "CMIC_RPE_SHARED_TXBUF_SLICE0_PKT_CNT", CMIC_RPE_SHARED_TXBUF_SLICE0_PKT_CNTr }, \ 1327 { 0x00016420, "CMIC_RPE_SHARED_TXBUF_DEBUG", CMIC_RPE_SHARED_TXBUF_DEBUGr }, \ 1328 { 0x00016424, "CMIC_RPE_SHARED_TXBUF_DATABUF_NUM_FREE_ENTRIES", CMIC_RPE_SHARED_TXBUF_DATABUF_NUM_FREE_ENTRIESr }, \ 1329 { 0x00016428, "CMIC_RPE_SHARED_TXBUF_DATABUF_MAX_FLIST_ENTRIES", CMIC_RPE_SHARED_TXBUF_DATABUF_MAX_FLIST_ENTRIESr }, \ 1330 { 0x0001642c, "CMIC_RPE_SHARED_TXBUF_ECC_STATUS", CMIC_RPE_SHARED_TXBUF_ECC_STATUSr }, \ 1331 { 0x00016430, "CMIC_RPE_SHARED_TXBUF_ECC_STATUS_CLR", CMIC_RPE_SHARED_TXBUF_ECC_STATUS_CLRr }, \ 1332 { 0x00016434, "CMIC_RPE_SHARED_TXBUF_ECC_CONTROL", CMIC_RPE_SHARED_TXBUF_ECC_CONTROLr }, \ 1333 { 0x00016438, "CMIC_RPE_SHARED_TXBUF_TM_CONTROL", CMIC_RPE_SHARED_TXBUF_TM_CONTROLr }, \ 1334 { 0x00016480, "CMIC_RPE_SHARED_RXBUF_DATABUF_MAX_FLIST_ENTRIES", CMIC_RPE_SHARED_RXBUF_DATABUF_MAX_FLIST_ENTRIESr }, \ 1335 { 0x00016484, "CMIC_RPE_SHARED_RXBUF_DATABUF_NUM_FREE_ENTRIES", CMIC_RPE_SHARED_RXBUF_DATABUF_NUM_FREE_ENTRIESr }, \ 1336 { 0x00016488, "CMIC_RPE_SHARED_RXBUF_BLOCK_DATABUF_ALLOC", CMIC_RPE_SHARED_RXBUF_BLOCK_DATABUF_ALLOCr }, \ 1337 { 0x0001648c, "CMIC_RPE_SHARED_RXBUF_CONFIG", CMIC_RPE_SHARED_RXBUF_CONFIGr }, \ 1338 { 0x00016490, "CMIC_RPE_SHARED_RXBUF_ECC_CONTROL", CMIC_RPE_SHARED_RXBUF_ECC_CONTROLr }, \ 1339 { 0x00016494, "CMIC_RPE_SHARED_RXBUF_TM_CONTROL", CMIC_RPE_SHARED_RXBUF_TM_CONTROLr }, \ 1340 { 0x00016498, "CMIC_RPE_SHARED_RXBUF_ECC_STATUS", CMIC_RPE_SHARED_RXBUF_ECC_STATUSr }, \ 1341 { 0x0001649c, "CMIC_RPE_SHARED_RXBUF_ECC_STATUS_CLR", CMIC_RPE_SHARED_RXBUF_ECC_STATUS_CLRr }, \ 1342 { 0x00016500, "CMIC_RPE_PKT_REASON_0_TYPE", CMIC_RPE_PKT_REASON_0_TYPEr }, \ 1343 { 0x00016540, "CMIC_RPE_PKT_REASON_1_TYPE", CMIC_RPE_PKT_REASON_1_TYPEr }, \ 1344 { 0x00016580, "CMIC_RPE_PKT_REASON_DIRECT_0_TYPE", CMIC_RPE_PKT_REASON_DIRECT_0_TYPEr }, \ 1345 { 0x000165c0, "CMIC_RPE_PKT_REASON_DIRECT_1_TYPE", CMIC_RPE_PKT_REASON_DIRECT_1_TYPEr }, \ 1346 { 0x00016600, "CMIC_RPE_PKT_REASON_MINI_0_TYPE", CMIC_RPE_PKT_REASON_MINI_0_TYPEr }, \ 1347 { 0x00016640, "CMIC_RPE_PKT_REASON_MINI_1_TYPE", CMIC_RPE_PKT_REASON_MINI_1_TYPEr }, \ 1348 { 0x00016680, "CMIC_RPE_PKT_REASON_2_TYPE", CMIC_RPE_PKT_REASON_2_TYPEr }, \ 1349 { 0x000166c0, "CMIC_RPE_PKT_REASON_DIRECT_2_TYPE", CMIC_RPE_PKT_REASON_DIRECT_2_TYPEr }, \ 1350 { 0x00016700, "CMIC_RPE_PKT_REASON_MINI_2_TYPE", CMIC_RPE_PKT_REASON_MINI_2_TYPEr }, \ 1351 } 1352 1353 #define CMICX_OFFSET_MIN (0) 1354 #define CMICX_OFFSET_MAX (0x00016700) 1355 #define NUM_CMICX_REGS (1326) 1356 1357 #define CMIC_CMC0_CCMDMA_CH0_CFG_OFFSET (0x3418) 1358 #define CMIC_CMC1_CCMDMA_CH0_CFG_OFFSET (0x6418) 1359 #define CMIC_CMCx_CCMDMA_CH0_CFG_OFFSET(x) (0x3418 + (0x3000 * x)) 1360 #define CMIC_CMC0_CCMDMA_CH0_CUR_HOST0_ADDR_HI_OFFSET (0x3424) 1361 #define CMIC_CMC1_CCMDMA_CH0_CUR_HOST0_ADDR_HI_OFFSET (0x6424) 1362 #define CMIC_CMCx_CCMDMA_CH0_CUR_HOST0_ADDR_HI_OFFSET(x) (0x3424 + (0x3000 * x)) 1363 #define CMIC_CMC0_CCMDMA_CH0_CUR_HOST0_ADDR_LO_OFFSET (0x3420) 1364 #define CMIC_CMC1_CCMDMA_CH0_CUR_HOST0_ADDR_LO_OFFSET (0x6420) 1365 #define CMIC_CMCx_CCMDMA_CH0_CUR_HOST0_ADDR_LO_OFFSET(x) (0x3420 + (0x3000 * x)) 1366 #define CMIC_CMC0_CCMDMA_CH0_CUR_HOST1_ADDR_HI_OFFSET (0x342c) 1367 #define CMIC_CMC1_CCMDMA_CH0_CUR_HOST1_ADDR_HI_OFFSET (0x642c) 1368 #define CMIC_CMCx_CCMDMA_CH0_CUR_HOST1_ADDR_HI_OFFSET(x) (0x342c + (0x3000 * x)) 1369 #define CMIC_CMC0_CCMDMA_CH0_CUR_HOST1_ADDR_LO_OFFSET (0x3428) 1370 #define CMIC_CMC1_CCMDMA_CH0_CUR_HOST1_ADDR_LO_OFFSET (0x6428) 1371 #define CMIC_CMCx_CCMDMA_CH0_CUR_HOST1_ADDR_LO_OFFSET(x) (0x3428 + (0x3000 * x)) 1372 #define CMIC_CMC0_CCMDMA_CH0_ECC_CONTROL_OFFSET (0x3430) 1373 #define CMIC_CMC1_CCMDMA_CH0_ECC_CONTROL_OFFSET (0x6430) 1374 #define CMIC_CMCx_CCMDMA_CH0_ECC_CONTROL_OFFSET(x) (0x3430 + (0x3000 * x)) 1375 #define CMIC_CMC0_CCMDMA_CH0_ECC_STATUS_OFFSET (0x3434) 1376 #define CMIC_CMC1_CCMDMA_CH0_ECC_STATUS_OFFSET (0x6434) 1377 #define CMIC_CMCx_CCMDMA_CH0_ECC_STATUS_OFFSET(x) (0x3434 + (0x3000 * x)) 1378 #define CMIC_CMC0_CCMDMA_CH0_ECC_STATUS_CLR_OFFSET (0x3438) 1379 #define CMIC_CMC1_CCMDMA_CH0_ECC_STATUS_CLR_OFFSET (0x6438) 1380 #define CMIC_CMCx_CCMDMA_CH0_ECC_STATUS_CLR_OFFSET(x) (0x3438 + (0x3000 * x)) 1381 #define CMIC_CMC0_CCMDMA_CH0_ENTRY_COUNT_OFFSET (0x3414) 1382 #define CMIC_CMC1_CCMDMA_CH0_ENTRY_COUNT_OFFSET (0x6414) 1383 #define CMIC_CMCx_CCMDMA_CH0_ENTRY_COUNT_OFFSET(x) (0x3414 + (0x3000 * x)) 1384 #define CMIC_CMC0_CCMDMA_CH0_HOST0_MEM_START_ADDR_HI_OFFSET (0x3408) 1385 #define CMIC_CMC1_CCMDMA_CH0_HOST0_MEM_START_ADDR_HI_OFFSET (0x6408) 1386 #define CMIC_CMCx_CCMDMA_CH0_HOST0_MEM_START_ADDR_HI_OFFSET(x) (0x3408 + (0x3000 * x)) 1387 #define CMIC_CMC0_CCMDMA_CH0_HOST0_MEM_START_ADDR_LO_OFFSET (0x3404) 1388 #define CMIC_CMC1_CCMDMA_CH0_HOST0_MEM_START_ADDR_LO_OFFSET (0x6404) 1389 #define CMIC_CMCx_CCMDMA_CH0_HOST0_MEM_START_ADDR_LO_OFFSET(x) (0x3404 + (0x3000 * x)) 1390 #define CMIC_CMC0_CCMDMA_CH0_HOST1_MEM_START_ADDR_HI_OFFSET (0x3410) 1391 #define CMIC_CMC1_CCMDMA_CH0_HOST1_MEM_START_ADDR_HI_OFFSET (0x6410) 1392 #define CMIC_CMCx_CCMDMA_CH0_HOST1_MEM_START_ADDR_HI_OFFSET(x) (0x3410 + (0x3000 * x)) 1393 #define CMIC_CMC0_CCMDMA_CH0_HOST1_MEM_START_ADDR_LO_OFFSET (0x340c) 1394 #define CMIC_CMC1_CCMDMA_CH0_HOST1_MEM_START_ADDR_LO_OFFSET (0x640c) 1395 #define CMIC_CMCx_CCMDMA_CH0_HOST1_MEM_START_ADDR_LO_OFFSET(x) (0x340c + (0x3000 * x)) 1396 #define CMIC_CMC0_CCMDMA_CH0_STAT_OFFSET (0x341c) 1397 #define CMIC_CMC1_CCMDMA_CH0_STAT_OFFSET (0x641c) 1398 #define CMIC_CMCx_CCMDMA_CH0_STAT_OFFSET(x) (0x341c + (0x3000 * x)) 1399 #define CMIC_CMC0_CCMDMA_CH0_TM_CONTROL_OFFSET (0x343c) 1400 #define CMIC_CMC1_CCMDMA_CH0_TM_CONTROL_OFFSET (0x643c) 1401 #define CMIC_CMCx_CCMDMA_CH0_TM_CONTROL_OFFSET(x) (0x343c + (0x3000 * x)) 1402 #define CMIC_CMC0_CCMDMA_CH1_CFG_OFFSET (0x3498) 1403 #define CMIC_CMC1_CCMDMA_CH1_CFG_OFFSET (0x6498) 1404 #define CMIC_CMCx_CCMDMA_CH1_CFG_OFFSET(x) (0x3498 + (0x3000 * x)) 1405 #define CMIC_CMC0_CCMDMA_CH1_CUR_HOST0_ADDR_HI_OFFSET (0x34a4) 1406 #define CMIC_CMC1_CCMDMA_CH1_CUR_HOST0_ADDR_HI_OFFSET (0x64a4) 1407 #define CMIC_CMCx_CCMDMA_CH1_CUR_HOST0_ADDR_HI_OFFSET(x) (0x34a4 + (0x3000 * x)) 1408 #define CMIC_CMC0_CCMDMA_CH1_CUR_HOST0_ADDR_LO_OFFSET (0x34a0) 1409 #define CMIC_CMC1_CCMDMA_CH1_CUR_HOST0_ADDR_LO_OFFSET (0x64a0) 1410 #define CMIC_CMCx_CCMDMA_CH1_CUR_HOST0_ADDR_LO_OFFSET(x) (0x34a0 + (0x3000 * x)) 1411 #define CMIC_CMC0_CCMDMA_CH1_CUR_HOST1_ADDR_HI_OFFSET (0x34ac) 1412 #define CMIC_CMC1_CCMDMA_CH1_CUR_HOST1_ADDR_HI_OFFSET (0x64ac) 1413 #define CMIC_CMCx_CCMDMA_CH1_CUR_HOST1_ADDR_HI_OFFSET(x) (0x34ac + (0x3000 * x)) 1414 #define CMIC_CMC0_CCMDMA_CH1_CUR_HOST1_ADDR_LO_OFFSET (0x34a8) 1415 #define CMIC_CMC1_CCMDMA_CH1_CUR_HOST1_ADDR_LO_OFFSET (0x64a8) 1416 #define CMIC_CMCx_CCMDMA_CH1_CUR_HOST1_ADDR_LO_OFFSET(x) (0x34a8 + (0x3000 * x)) 1417 #define CMIC_CMC0_CCMDMA_CH1_ECC_CONTROL_OFFSET (0x34b0) 1418 #define CMIC_CMC1_CCMDMA_CH1_ECC_CONTROL_OFFSET (0x64b0) 1419 #define CMIC_CMCx_CCMDMA_CH1_ECC_CONTROL_OFFSET(x) (0x34b0 + (0x3000 * x)) 1420 #define CMIC_CMC0_CCMDMA_CH1_ECC_STATUS_OFFSET (0x34b4) 1421 #define CMIC_CMC1_CCMDMA_CH1_ECC_STATUS_OFFSET (0x64b4) 1422 #define CMIC_CMCx_CCMDMA_CH1_ECC_STATUS_OFFSET(x) (0x34b4 + (0x3000 * x)) 1423 #define CMIC_CMC0_CCMDMA_CH1_ECC_STATUS_CLR_OFFSET (0x34b8) 1424 #define CMIC_CMC1_CCMDMA_CH1_ECC_STATUS_CLR_OFFSET (0x64b8) 1425 #define CMIC_CMCx_CCMDMA_CH1_ECC_STATUS_CLR_OFFSET(x) (0x34b8 + (0x3000 * x)) 1426 #define CMIC_CMC0_CCMDMA_CH1_ENTRY_COUNT_OFFSET (0x3494) 1427 #define CMIC_CMC1_CCMDMA_CH1_ENTRY_COUNT_OFFSET (0x6494) 1428 #define CMIC_CMCx_CCMDMA_CH1_ENTRY_COUNT_OFFSET(x) (0x3494 + (0x3000 * x)) 1429 #define CMIC_CMC0_CCMDMA_CH1_HOST0_MEM_START_ADDR_HI_OFFSET (0x3488) 1430 #define CMIC_CMC1_CCMDMA_CH1_HOST0_MEM_START_ADDR_HI_OFFSET (0x6488) 1431 #define CMIC_CMCx_CCMDMA_CH1_HOST0_MEM_START_ADDR_HI_OFFSET(x) (0x3488 + (0x3000 * x)) 1432 #define CMIC_CMC0_CCMDMA_CH1_HOST0_MEM_START_ADDR_LO_OFFSET (0x3484) 1433 #define CMIC_CMC1_CCMDMA_CH1_HOST0_MEM_START_ADDR_LO_OFFSET (0x6484) 1434 #define CMIC_CMCx_CCMDMA_CH1_HOST0_MEM_START_ADDR_LO_OFFSET(x) (0x3484 + (0x3000 * x)) 1435 #define CMIC_CMC0_CCMDMA_CH1_HOST1_MEM_START_ADDR_HI_OFFSET (0x3490) 1436 #define CMIC_CMC1_CCMDMA_CH1_HOST1_MEM_START_ADDR_HI_OFFSET (0x6490) 1437 #define CMIC_CMCx_CCMDMA_CH1_HOST1_MEM_START_ADDR_HI_OFFSET(x) (0x3490 + (0x3000 * x)) 1438 #define CMIC_CMC0_CCMDMA_CH1_HOST1_MEM_START_ADDR_LO_OFFSET (0x348c) 1439 #define CMIC_CMC1_CCMDMA_CH1_HOST1_MEM_START_ADDR_LO_OFFSET (0x648c) 1440 #define CMIC_CMCx_CCMDMA_CH1_HOST1_MEM_START_ADDR_LO_OFFSET(x) (0x348c + (0x3000 * x)) 1441 #define CMIC_CMC0_CCMDMA_CH1_STAT_OFFSET (0x349c) 1442 #define CMIC_CMC1_CCMDMA_CH1_STAT_OFFSET (0x649c) 1443 #define CMIC_CMCx_CCMDMA_CH1_STAT_OFFSET(x) (0x349c + (0x3000 * x)) 1444 #define CMIC_CMC0_CCMDMA_CH1_TM_CONTROL_OFFSET (0x34bc) 1445 #define CMIC_CMC1_CCMDMA_CH1_TM_CONTROL_OFFSET (0x64bc) 1446 #define CMIC_CMCx_CCMDMA_CH1_TM_CONTROL_OFFSET(x) (0x34bc + (0x3000 * x)) 1447 #define CMIC_CMC0_PKTDMA_CH0_COS_CTRL_RX_0_OFFSET (0x2118) 1448 #define CMIC_CMC1_PKTDMA_CH0_COS_CTRL_RX_0_OFFSET (0x5118) 1449 #define CMIC_CMCx_PKTDMA_CH0_COS_CTRL_RX_0_OFFSET(x) (0x2118 + (0x3000 * x)) 1450 #define CMIC_CMC0_PKTDMA_CH0_COS_CTRL_RX_1_OFFSET (0x211c) 1451 #define CMIC_CMC1_PKTDMA_CH0_COS_CTRL_RX_1_OFFSET (0x511c) 1452 #define CMIC_CMCx_PKTDMA_CH0_COS_CTRL_RX_1_OFFSET(x) (0x211c + (0x3000 * x)) 1453 #define CMIC_CMC0_PKTDMA_CH0_CTRL_OFFSET (0x2100) 1454 #define CMIC_CMC1_PKTDMA_CH0_CTRL_OFFSET (0x5100) 1455 #define CMIC_CMCx_PKTDMA_CH0_CTRL_OFFSET(x) (0x2100 + (0x3000 * x)) 1456 #define CMIC_CMC0_PKTDMA_CH0_CURR_DESC_HI_OFFSET (0x2128) 1457 #define CMIC_CMC1_PKTDMA_CH0_CURR_DESC_HI_OFFSET (0x5128) 1458 #define CMIC_CMCx_PKTDMA_CH0_CURR_DESC_HI_OFFSET(x) (0x2128 + (0x3000 * x)) 1459 #define CMIC_CMC0_PKTDMA_CH0_CURR_DESC_LO_OFFSET (0x2124) 1460 #define CMIC_CMC1_PKTDMA_CH0_CURR_DESC_LO_OFFSET (0x5124) 1461 #define CMIC_CMCx_PKTDMA_CH0_CURR_DESC_LO_OFFSET(x) (0x2124 + (0x3000 * x)) 1462 #define CMIC_CMC0_PKTDMA_CH0_DEBUG_CONTROL_OFFSET (0x2130) 1463 #define CMIC_CMC1_PKTDMA_CH0_DEBUG_CONTROL_OFFSET (0x5130) 1464 #define CMIC_CMCx_PKTDMA_CH0_DEBUG_CONTROL_OFFSET(x) (0x2130 + (0x3000 * x)) 1465 #define CMIC_CMC0_PKTDMA_CH0_DEBUG_SM_STATUS_OFFSET (0x2134) 1466 #define CMIC_CMC1_PKTDMA_CH0_DEBUG_SM_STATUS_OFFSET (0x5134) 1467 #define CMIC_CMCx_PKTDMA_CH0_DEBUG_SM_STATUS_OFFSET(x) (0x2134 + (0x3000 * x)) 1468 #define CMIC_CMC0_PKTDMA_CH0_DEBUG_STATUS_OFFSET (0x2138) 1469 #define CMIC_CMC1_PKTDMA_CH0_DEBUG_STATUS_OFFSET (0x5138) 1470 #define CMIC_CMCx_PKTDMA_CH0_DEBUG_STATUS_OFFSET(x) (0x2138 + (0x3000 * x)) 1471 #define CMIC_CMC0_PKTDMA_CH0_DESC_ADDR_HI_OFFSET (0x2108) 1472 #define CMIC_CMC1_PKTDMA_CH0_DESC_ADDR_HI_OFFSET (0x5108) 1473 #define CMIC_CMCx_PKTDMA_CH0_DESC_ADDR_HI_OFFSET(x) (0x2108 + (0x3000 * x)) 1474 #define CMIC_CMC0_PKTDMA_CH0_DESC_ADDR_LO_OFFSET (0x2104) 1475 #define CMIC_CMC1_PKTDMA_CH0_DESC_ADDR_LO_OFFSET (0x5104) 1476 #define CMIC_CMCx_PKTDMA_CH0_DESC_ADDR_LO_OFFSET(x) (0x2104 + (0x3000 * x)) 1477 #define CMIC_CMC0_PKTDMA_CH0_DESC_COUNT_REQ_OFFSET (0x2148) 1478 #define CMIC_CMC1_PKTDMA_CH0_DESC_COUNT_REQ_OFFSET (0x5148) 1479 #define CMIC_CMCx_PKTDMA_CH0_DESC_COUNT_REQ_OFFSET(x) (0x2148 + (0x3000 * x)) 1480 #define CMIC_CMC0_PKTDMA_CH0_DESC_COUNT_RX_OFFSET (0x214c) 1481 #define CMIC_CMC1_PKTDMA_CH0_DESC_COUNT_RX_OFFSET (0x514c) 1482 #define CMIC_CMCx_PKTDMA_CH0_DESC_COUNT_RX_OFFSET(x) (0x214c + (0x3000 * x)) 1483 #define CMIC_CMC0_PKTDMA_CH0_DESC_COUNT_STATUS_WR_OFFSET (0x2150) 1484 #define CMIC_CMC1_PKTDMA_CH0_DESC_COUNT_STATUS_WR_OFFSET (0x5150) 1485 #define CMIC_CMCx_PKTDMA_CH0_DESC_COUNT_STATUS_WR_OFFSET(x) (0x2150 + (0x3000 * x)) 1486 #define CMIC_CMC0_PKTDMA_CH0_DESC_HALT_ADDR_HI_OFFSET (0x2110) 1487 #define CMIC_CMC1_PKTDMA_CH0_DESC_HALT_ADDR_HI_OFFSET (0x5110) 1488 #define CMIC_CMCx_PKTDMA_CH0_DESC_HALT_ADDR_HI_OFFSET(x) (0x2110 + (0x3000 * x)) 1489 #define CMIC_CMC0_PKTDMA_CH0_DESC_HALT_ADDR_LO_OFFSET (0x210c) 1490 #define CMIC_CMC1_PKTDMA_CH0_DESC_HALT_ADDR_LO_OFFSET (0x510c) 1491 #define CMIC_CMCx_PKTDMA_CH0_DESC_HALT_ADDR_LO_OFFSET(x) (0x210c + (0x3000 * x)) 1492 #define CMIC_CMC0_PKTDMA_CH0_DESC_MEM_ECC_CONTROL_OFFSET (0x2158) 1493 #define CMIC_CMC1_PKTDMA_CH0_DESC_MEM_ECC_CONTROL_OFFSET (0x5158) 1494 #define CMIC_CMCx_PKTDMA_CH0_DESC_MEM_ECC_CONTROL_OFFSET(x) (0x2158 + (0x3000 * x)) 1495 #define CMIC_CMC0_PKTDMA_CH0_DESC_MEM_ECC_STATUS_OFFSET (0x2154) 1496 #define CMIC_CMC1_PKTDMA_CH0_DESC_MEM_ECC_STATUS_OFFSET (0x5154) 1497 #define CMIC_CMCx_PKTDMA_CH0_DESC_MEM_ECC_STATUS_OFFSET(x) (0x2154 + (0x3000 * x)) 1498 #define CMIC_CMC0_PKTDMA_CH0_DESC_MEM_TM_CONTROL_OFFSET (0x215c) 1499 #define CMIC_CMC1_PKTDMA_CH0_DESC_MEM_TM_CONTROL_OFFSET (0x515c) 1500 #define CMIC_CMCx_PKTDMA_CH0_DESC_MEM_TM_CONTROL_OFFSET(x) (0x215c + (0x3000 * x)) 1501 #define CMIC_CMC0_PKTDMA_CH0_INTR_COAL_OFFSET (0x2120) 1502 #define CMIC_CMC1_PKTDMA_CH0_INTR_COAL_OFFSET (0x5120) 1503 #define CMIC_CMCx_PKTDMA_CH0_INTR_COAL_OFFSET(x) (0x2120 + (0x3000 * x)) 1504 #define CMIC_CMC0_PKTDMA_CH0_PKT_COUNT_RXPKT_OFFSET (0x213c) 1505 #define CMIC_CMC1_PKTDMA_CH0_PKT_COUNT_RXPKT_OFFSET (0x513c) 1506 #define CMIC_CMCx_PKTDMA_CH0_PKT_COUNT_RXPKT_OFFSET(x) (0x213c + (0x3000 * x)) 1507 #define CMIC_CMC0_PKTDMA_CH0_PKT_COUNT_RXPKT_DROP_OFFSET (0x2144) 1508 #define CMIC_CMC1_PKTDMA_CH0_PKT_COUNT_RXPKT_DROP_OFFSET (0x5144) 1509 #define CMIC_CMCx_PKTDMA_CH0_PKT_COUNT_RXPKT_DROP_OFFSET(x) (0x2144 + (0x3000 * x)) 1510 #define CMIC_CMC0_PKTDMA_CH0_PKT_COUNT_TXPKT_OFFSET (0x2140) 1511 #define CMIC_CMC1_PKTDMA_CH0_PKT_COUNT_TXPKT_OFFSET (0x5140) 1512 #define CMIC_CMCx_PKTDMA_CH0_PKT_COUNT_TXPKT_OFFSET(x) (0x2140 + (0x3000 * x)) 1513 #define CMIC_CMC0_PKTDMA_CH0_RXBUF_THRESHOLD_CONFIG_OFFSET (0x212c) 1514 #define CMIC_CMC1_PKTDMA_CH0_RXBUF_THRESHOLD_CONFIG_OFFSET (0x512c) 1515 #define CMIC_CMCx_PKTDMA_CH0_RXBUF_THRESHOLD_CONFIG_OFFSET(x) (0x212c + (0x3000 * x)) 1516 #define CMIC_CMC0_PKTDMA_CH0_STAT_OFFSET (0x2114) 1517 #define CMIC_CMC1_PKTDMA_CH0_STAT_OFFSET (0x5114) 1518 #define CMIC_CMCx_PKTDMA_CH0_STAT_OFFSET(x) (0x2114 + (0x3000 * x)) 1519 #define CMIC_CMC0_PKTDMA_CH1_COS_CTRL_RX_0_OFFSET (0x2198) 1520 #define CMIC_CMC1_PKTDMA_CH1_COS_CTRL_RX_0_OFFSET (0x5198) 1521 #define CMIC_CMCx_PKTDMA_CH1_COS_CTRL_RX_0_OFFSET(x) (0x2198 + (0x3000 * x)) 1522 #define CMIC_CMC0_PKTDMA_CH1_COS_CTRL_RX_1_OFFSET (0x219c) 1523 #define CMIC_CMC1_PKTDMA_CH1_COS_CTRL_RX_1_OFFSET (0x519c) 1524 #define CMIC_CMCx_PKTDMA_CH1_COS_CTRL_RX_1_OFFSET(x) (0x219c + (0x3000 * x)) 1525 #define CMIC_CMC0_PKTDMA_CH1_CTRL_OFFSET (0x2180) 1526 #define CMIC_CMC1_PKTDMA_CH1_CTRL_OFFSET (0x5180) 1527 #define CMIC_CMCx_PKTDMA_CH1_CTRL_OFFSET(x) (0x2180 + (0x3000 * x)) 1528 #define CMIC_CMC0_PKTDMA_CH1_CURR_DESC_HI_OFFSET (0x21a8) 1529 #define CMIC_CMC1_PKTDMA_CH1_CURR_DESC_HI_OFFSET (0x51a8) 1530 #define CMIC_CMCx_PKTDMA_CH1_CURR_DESC_HI_OFFSET(x) (0x21a8 + (0x3000 * x)) 1531 #define CMIC_CMC0_PKTDMA_CH1_CURR_DESC_LO_OFFSET (0x21a4) 1532 #define CMIC_CMC1_PKTDMA_CH1_CURR_DESC_LO_OFFSET (0x51a4) 1533 #define CMIC_CMCx_PKTDMA_CH1_CURR_DESC_LO_OFFSET(x) (0x21a4 + (0x3000 * x)) 1534 #define CMIC_CMC0_PKTDMA_CH1_DEBUG_CONTROL_OFFSET (0x21b0) 1535 #define CMIC_CMC1_PKTDMA_CH1_DEBUG_CONTROL_OFFSET (0x51b0) 1536 #define CMIC_CMCx_PKTDMA_CH1_DEBUG_CONTROL_OFFSET(x) (0x21b0 + (0x3000 * x)) 1537 #define CMIC_CMC0_PKTDMA_CH1_DEBUG_SM_STATUS_OFFSET (0x21b4) 1538 #define CMIC_CMC1_PKTDMA_CH1_DEBUG_SM_STATUS_OFFSET (0x51b4) 1539 #define CMIC_CMCx_PKTDMA_CH1_DEBUG_SM_STATUS_OFFSET(x) (0x21b4 + (0x3000 * x)) 1540 #define CMIC_CMC0_PKTDMA_CH1_DEBUG_STATUS_OFFSET (0x21b8) 1541 #define CMIC_CMC1_PKTDMA_CH1_DEBUG_STATUS_OFFSET (0x51b8) 1542 #define CMIC_CMCx_PKTDMA_CH1_DEBUG_STATUS_OFFSET(x) (0x21b8 + (0x3000 * x)) 1543 #define CMIC_CMC0_PKTDMA_CH1_DESC_ADDR_HI_OFFSET (0x2188) 1544 #define CMIC_CMC1_PKTDMA_CH1_DESC_ADDR_HI_OFFSET (0x5188) 1545 #define CMIC_CMCx_PKTDMA_CH1_DESC_ADDR_HI_OFFSET(x) (0x2188 + (0x3000 * x)) 1546 #define CMIC_CMC0_PKTDMA_CH1_DESC_ADDR_LO_OFFSET (0x2184) 1547 #define CMIC_CMC1_PKTDMA_CH1_DESC_ADDR_LO_OFFSET (0x5184) 1548 #define CMIC_CMCx_PKTDMA_CH1_DESC_ADDR_LO_OFFSET(x) (0x2184 + (0x3000 * x)) 1549 #define CMIC_CMC0_PKTDMA_CH1_DESC_COUNT_REQ_OFFSET (0x21c8) 1550 #define CMIC_CMC1_PKTDMA_CH1_DESC_COUNT_REQ_OFFSET (0x51c8) 1551 #define CMIC_CMCx_PKTDMA_CH1_DESC_COUNT_REQ_OFFSET(x) (0x21c8 + (0x3000 * x)) 1552 #define CMIC_CMC0_PKTDMA_CH1_DESC_COUNT_RX_OFFSET (0x21cc) 1553 #define CMIC_CMC1_PKTDMA_CH1_DESC_COUNT_RX_OFFSET (0x51cc) 1554 #define CMIC_CMCx_PKTDMA_CH1_DESC_COUNT_RX_OFFSET(x) (0x21cc + (0x3000 * x)) 1555 #define CMIC_CMC0_PKTDMA_CH1_DESC_COUNT_STATUS_WR_OFFSET (0x21d0) 1556 #define CMIC_CMC1_PKTDMA_CH1_DESC_COUNT_STATUS_WR_OFFSET (0x51d0) 1557 #define CMIC_CMCx_PKTDMA_CH1_DESC_COUNT_STATUS_WR_OFFSET(x) (0x21d0 + (0x3000 * x)) 1558 #define CMIC_CMC0_PKTDMA_CH1_DESC_HALT_ADDR_HI_OFFSET (0x2190) 1559 #define CMIC_CMC1_PKTDMA_CH1_DESC_HALT_ADDR_HI_OFFSET (0x5190) 1560 #define CMIC_CMCx_PKTDMA_CH1_DESC_HALT_ADDR_HI_OFFSET(x) (0x2190 + (0x3000 * x)) 1561 #define CMIC_CMC0_PKTDMA_CH1_DESC_HALT_ADDR_LO_OFFSET (0x218c) 1562 #define CMIC_CMC1_PKTDMA_CH1_DESC_HALT_ADDR_LO_OFFSET (0x518c) 1563 #define CMIC_CMCx_PKTDMA_CH1_DESC_HALT_ADDR_LO_OFFSET(x) (0x218c + (0x3000 * x)) 1564 #define CMIC_CMC0_PKTDMA_CH1_DESC_MEM_ECC_CONTROL_OFFSET (0x21d8) 1565 #define CMIC_CMC1_PKTDMA_CH1_DESC_MEM_ECC_CONTROL_OFFSET (0x51d8) 1566 #define CMIC_CMCx_PKTDMA_CH1_DESC_MEM_ECC_CONTROL_OFFSET(x) (0x21d8 + (0x3000 * x)) 1567 #define CMIC_CMC0_PKTDMA_CH1_DESC_MEM_ECC_STATUS_OFFSET (0x21d4) 1568 #define CMIC_CMC1_PKTDMA_CH1_DESC_MEM_ECC_STATUS_OFFSET (0x51d4) 1569 #define CMIC_CMCx_PKTDMA_CH1_DESC_MEM_ECC_STATUS_OFFSET(x) (0x21d4 + (0x3000 * x)) 1570 #define CMIC_CMC0_PKTDMA_CH1_DESC_MEM_TM_CONTROL_OFFSET (0x21dc) 1571 #define CMIC_CMC1_PKTDMA_CH1_DESC_MEM_TM_CONTROL_OFFSET (0x51dc) 1572 #define CMIC_CMCx_PKTDMA_CH1_DESC_MEM_TM_CONTROL_OFFSET(x) (0x21dc + (0x3000 * x)) 1573 #define CMIC_CMC0_PKTDMA_CH1_INTR_COAL_OFFSET (0x21a0) 1574 #define CMIC_CMC1_PKTDMA_CH1_INTR_COAL_OFFSET (0x51a0) 1575 #define CMIC_CMCx_PKTDMA_CH1_INTR_COAL_OFFSET(x) (0x21a0 + (0x3000 * x)) 1576 #define CMIC_CMC0_PKTDMA_CH1_PKT_COUNT_RXPKT_OFFSET (0x21bc) 1577 #define CMIC_CMC1_PKTDMA_CH1_PKT_COUNT_RXPKT_OFFSET (0x51bc) 1578 #define CMIC_CMCx_PKTDMA_CH1_PKT_COUNT_RXPKT_OFFSET(x) (0x21bc + (0x3000 * x)) 1579 #define CMIC_CMC0_PKTDMA_CH1_PKT_COUNT_RXPKT_DROP_OFFSET (0x21c4) 1580 #define CMIC_CMC1_PKTDMA_CH1_PKT_COUNT_RXPKT_DROP_OFFSET (0x51c4) 1581 #define CMIC_CMCx_PKTDMA_CH1_PKT_COUNT_RXPKT_DROP_OFFSET(x) (0x21c4 + (0x3000 * x)) 1582 #define CMIC_CMC0_PKTDMA_CH1_PKT_COUNT_TXPKT_OFFSET (0x21c0) 1583 #define CMIC_CMC1_PKTDMA_CH1_PKT_COUNT_TXPKT_OFFSET (0x51c0) 1584 #define CMIC_CMCx_PKTDMA_CH1_PKT_COUNT_TXPKT_OFFSET(x) (0x21c0 + (0x3000 * x)) 1585 #define CMIC_CMC0_PKTDMA_CH1_RXBUF_THRESHOLD_CONFIG_OFFSET (0x21ac) 1586 #define CMIC_CMC1_PKTDMA_CH1_RXBUF_THRESHOLD_CONFIG_OFFSET (0x51ac) 1587 #define CMIC_CMCx_PKTDMA_CH1_RXBUF_THRESHOLD_CONFIG_OFFSET(x) (0x21ac + (0x3000 * x)) 1588 #define CMIC_CMC0_PKTDMA_CH1_STAT_OFFSET (0x2194) 1589 #define CMIC_CMC1_PKTDMA_CH1_STAT_OFFSET (0x5194) 1590 #define CMIC_CMCx_PKTDMA_CH1_STAT_OFFSET(x) (0x2194 + (0x3000 * x)) 1591 #define CMIC_CMC0_PKTDMA_CH2_COS_CTRL_RX_0_OFFSET (0x2218) 1592 #define CMIC_CMC1_PKTDMA_CH2_COS_CTRL_RX_0_OFFSET (0x5218) 1593 #define CMIC_CMCx_PKTDMA_CH2_COS_CTRL_RX_0_OFFSET(x) (0x2218 + (0x3000 * x)) 1594 #define CMIC_CMC0_PKTDMA_CH2_COS_CTRL_RX_1_OFFSET (0x221c) 1595 #define CMIC_CMC1_PKTDMA_CH2_COS_CTRL_RX_1_OFFSET (0x521c) 1596 #define CMIC_CMCx_PKTDMA_CH2_COS_CTRL_RX_1_OFFSET(x) (0x221c + (0x3000 * x)) 1597 #define CMIC_CMC0_PKTDMA_CH2_CTRL_OFFSET (0x2200) 1598 #define CMIC_CMC1_PKTDMA_CH2_CTRL_OFFSET (0x5200) 1599 #define CMIC_CMCx_PKTDMA_CH2_CTRL_OFFSET(x) (0x2200 + (0x3000 * x)) 1600 #define CMIC_CMC0_PKTDMA_CH2_CURR_DESC_HI_OFFSET (0x2228) 1601 #define CMIC_CMC1_PKTDMA_CH2_CURR_DESC_HI_OFFSET (0x5228) 1602 #define CMIC_CMCx_PKTDMA_CH2_CURR_DESC_HI_OFFSET(x) (0x2228 + (0x3000 * x)) 1603 #define CMIC_CMC0_PKTDMA_CH2_CURR_DESC_LO_OFFSET (0x2224) 1604 #define CMIC_CMC1_PKTDMA_CH2_CURR_DESC_LO_OFFSET (0x5224) 1605 #define CMIC_CMCx_PKTDMA_CH2_CURR_DESC_LO_OFFSET(x) (0x2224 + (0x3000 * x)) 1606 #define CMIC_CMC0_PKTDMA_CH2_DEBUG_CONTROL_OFFSET (0x2230) 1607 #define CMIC_CMC1_PKTDMA_CH2_DEBUG_CONTROL_OFFSET (0x5230) 1608 #define CMIC_CMCx_PKTDMA_CH2_DEBUG_CONTROL_OFFSET(x) (0x2230 + (0x3000 * x)) 1609 #define CMIC_CMC0_PKTDMA_CH2_DEBUG_SM_STATUS_OFFSET (0x2234) 1610 #define CMIC_CMC1_PKTDMA_CH2_DEBUG_SM_STATUS_OFFSET (0x5234) 1611 #define CMIC_CMCx_PKTDMA_CH2_DEBUG_SM_STATUS_OFFSET(x) (0x2234 + (0x3000 * x)) 1612 #define CMIC_CMC0_PKTDMA_CH2_DEBUG_STATUS_OFFSET (0x2238) 1613 #define CMIC_CMC1_PKTDMA_CH2_DEBUG_STATUS_OFFSET (0x5238) 1614 #define CMIC_CMCx_PKTDMA_CH2_DEBUG_STATUS_OFFSET(x) (0x2238 + (0x3000 * x)) 1615 #define CMIC_CMC0_PKTDMA_CH2_DESC_ADDR_HI_OFFSET (0x2208) 1616 #define CMIC_CMC1_PKTDMA_CH2_DESC_ADDR_HI_OFFSET (0x5208) 1617 #define CMIC_CMCx_PKTDMA_CH2_DESC_ADDR_HI_OFFSET(x) (0x2208 + (0x3000 * x)) 1618 #define CMIC_CMC0_PKTDMA_CH2_DESC_ADDR_LO_OFFSET (0x2204) 1619 #define CMIC_CMC1_PKTDMA_CH2_DESC_ADDR_LO_OFFSET (0x5204) 1620 #define CMIC_CMCx_PKTDMA_CH2_DESC_ADDR_LO_OFFSET(x) (0x2204 + (0x3000 * x)) 1621 #define CMIC_CMC0_PKTDMA_CH2_DESC_COUNT_REQ_OFFSET (0x2248) 1622 #define CMIC_CMC1_PKTDMA_CH2_DESC_COUNT_REQ_OFFSET (0x5248) 1623 #define CMIC_CMCx_PKTDMA_CH2_DESC_COUNT_REQ_OFFSET(x) (0x2248 + (0x3000 * x)) 1624 #define CMIC_CMC0_PKTDMA_CH2_DESC_COUNT_RX_OFFSET (0x224c) 1625 #define CMIC_CMC1_PKTDMA_CH2_DESC_COUNT_RX_OFFSET (0x524c) 1626 #define CMIC_CMCx_PKTDMA_CH2_DESC_COUNT_RX_OFFSET(x) (0x224c + (0x3000 * x)) 1627 #define CMIC_CMC0_PKTDMA_CH2_DESC_COUNT_STATUS_WR_OFFSET (0x2250) 1628 #define CMIC_CMC1_PKTDMA_CH2_DESC_COUNT_STATUS_WR_OFFSET (0x5250) 1629 #define CMIC_CMCx_PKTDMA_CH2_DESC_COUNT_STATUS_WR_OFFSET(x) (0x2250 + (0x3000 * x)) 1630 #define CMIC_CMC0_PKTDMA_CH2_DESC_HALT_ADDR_HI_OFFSET (0x2210) 1631 #define CMIC_CMC1_PKTDMA_CH2_DESC_HALT_ADDR_HI_OFFSET (0x5210) 1632 #define CMIC_CMCx_PKTDMA_CH2_DESC_HALT_ADDR_HI_OFFSET(x) (0x2210 + (0x3000 * x)) 1633 #define CMIC_CMC0_PKTDMA_CH2_DESC_HALT_ADDR_LO_OFFSET (0x220c) 1634 #define CMIC_CMC1_PKTDMA_CH2_DESC_HALT_ADDR_LO_OFFSET (0x520c) 1635 #define CMIC_CMCx_PKTDMA_CH2_DESC_HALT_ADDR_LO_OFFSET(x) (0x220c + (0x3000 * x)) 1636 #define CMIC_CMC0_PKTDMA_CH2_DESC_MEM_ECC_CONTROL_OFFSET (0x2258) 1637 #define CMIC_CMC1_PKTDMA_CH2_DESC_MEM_ECC_CONTROL_OFFSET (0x5258) 1638 #define CMIC_CMCx_PKTDMA_CH2_DESC_MEM_ECC_CONTROL_OFFSET(x) (0x2258 + (0x3000 * x)) 1639 #define CMIC_CMC0_PKTDMA_CH2_DESC_MEM_ECC_STATUS_OFFSET (0x2254) 1640 #define CMIC_CMC1_PKTDMA_CH2_DESC_MEM_ECC_STATUS_OFFSET (0x5254) 1641 #define CMIC_CMCx_PKTDMA_CH2_DESC_MEM_ECC_STATUS_OFFSET(x) (0x2254 + (0x3000 * x)) 1642 #define CMIC_CMC0_PKTDMA_CH2_DESC_MEM_TM_CONTROL_OFFSET (0x225c) 1643 #define CMIC_CMC1_PKTDMA_CH2_DESC_MEM_TM_CONTROL_OFFSET (0x525c) 1644 #define CMIC_CMCx_PKTDMA_CH2_DESC_MEM_TM_CONTROL_OFFSET(x) (0x225c + (0x3000 * x)) 1645 #define CMIC_CMC0_PKTDMA_CH2_INTR_COAL_OFFSET (0x2220) 1646 #define CMIC_CMC1_PKTDMA_CH2_INTR_COAL_OFFSET (0x5220) 1647 #define CMIC_CMCx_PKTDMA_CH2_INTR_COAL_OFFSET(x) (0x2220 + (0x3000 * x)) 1648 #define CMIC_CMC0_PKTDMA_CH2_PKT_COUNT_RXPKT_OFFSET (0x223c) 1649 #define CMIC_CMC1_PKTDMA_CH2_PKT_COUNT_RXPKT_OFFSET (0x523c) 1650 #define CMIC_CMCx_PKTDMA_CH2_PKT_COUNT_RXPKT_OFFSET(x) (0x223c + (0x3000 * x)) 1651 #define CMIC_CMC0_PKTDMA_CH2_PKT_COUNT_RXPKT_DROP_OFFSET (0x2244) 1652 #define CMIC_CMC1_PKTDMA_CH2_PKT_COUNT_RXPKT_DROP_OFFSET (0x5244) 1653 #define CMIC_CMCx_PKTDMA_CH2_PKT_COUNT_RXPKT_DROP_OFFSET(x) (0x2244 + (0x3000 * x)) 1654 #define CMIC_CMC0_PKTDMA_CH2_PKT_COUNT_TXPKT_OFFSET (0x2240) 1655 #define CMIC_CMC1_PKTDMA_CH2_PKT_COUNT_TXPKT_OFFSET (0x5240) 1656 #define CMIC_CMCx_PKTDMA_CH2_PKT_COUNT_TXPKT_OFFSET(x) (0x2240 + (0x3000 * x)) 1657 #define CMIC_CMC0_PKTDMA_CH2_RXBUF_THRESHOLD_CONFIG_OFFSET (0x222c) 1658 #define CMIC_CMC1_PKTDMA_CH2_RXBUF_THRESHOLD_CONFIG_OFFSET (0x522c) 1659 #define CMIC_CMCx_PKTDMA_CH2_RXBUF_THRESHOLD_CONFIG_OFFSET(x) (0x222c + (0x3000 * x)) 1660 #define CMIC_CMC0_PKTDMA_CH2_STAT_OFFSET (0x2214) 1661 #define CMIC_CMC1_PKTDMA_CH2_STAT_OFFSET (0x5214) 1662 #define CMIC_CMCx_PKTDMA_CH2_STAT_OFFSET(x) (0x2214 + (0x3000 * x)) 1663 #define CMIC_CMC0_PKTDMA_CH3_COS_CTRL_RX_0_OFFSET (0x2298) 1664 #define CMIC_CMC1_PKTDMA_CH3_COS_CTRL_RX_0_OFFSET (0x5298) 1665 #define CMIC_CMCx_PKTDMA_CH3_COS_CTRL_RX_0_OFFSET(x) (0x2298 + (0x3000 * x)) 1666 #define CMIC_CMC0_PKTDMA_CH3_COS_CTRL_RX_1_OFFSET (0x229c) 1667 #define CMIC_CMC1_PKTDMA_CH3_COS_CTRL_RX_1_OFFSET (0x529c) 1668 #define CMIC_CMCx_PKTDMA_CH3_COS_CTRL_RX_1_OFFSET(x) (0x229c + (0x3000 * x)) 1669 #define CMIC_CMC0_PKTDMA_CH3_CTRL_OFFSET (0x2280) 1670 #define CMIC_CMC1_PKTDMA_CH3_CTRL_OFFSET (0x5280) 1671 #define CMIC_CMCx_PKTDMA_CH3_CTRL_OFFSET(x) (0x2280 + (0x3000 * x)) 1672 #define CMIC_CMC0_PKTDMA_CH3_CURR_DESC_HI_OFFSET (0x22a8) 1673 #define CMIC_CMC1_PKTDMA_CH3_CURR_DESC_HI_OFFSET (0x52a8) 1674 #define CMIC_CMCx_PKTDMA_CH3_CURR_DESC_HI_OFFSET(x) (0x22a8 + (0x3000 * x)) 1675 #define CMIC_CMC0_PKTDMA_CH3_CURR_DESC_LO_OFFSET (0x22a4) 1676 #define CMIC_CMC1_PKTDMA_CH3_CURR_DESC_LO_OFFSET (0x52a4) 1677 #define CMIC_CMCx_PKTDMA_CH3_CURR_DESC_LO_OFFSET(x) (0x22a4 + (0x3000 * x)) 1678 #define CMIC_CMC0_PKTDMA_CH3_DEBUG_CONTROL_OFFSET (0x22b0) 1679 #define CMIC_CMC1_PKTDMA_CH3_DEBUG_CONTROL_OFFSET (0x52b0) 1680 #define CMIC_CMCx_PKTDMA_CH3_DEBUG_CONTROL_OFFSET(x) (0x22b0 + (0x3000 * x)) 1681 #define CMIC_CMC0_PKTDMA_CH3_DEBUG_SM_STATUS_OFFSET (0x22b4) 1682 #define CMIC_CMC1_PKTDMA_CH3_DEBUG_SM_STATUS_OFFSET (0x52b4) 1683 #define CMIC_CMCx_PKTDMA_CH3_DEBUG_SM_STATUS_OFFSET(x) (0x22b4 + (0x3000 * x)) 1684 #define CMIC_CMC0_PKTDMA_CH3_DEBUG_STATUS_OFFSET (0x22b8) 1685 #define CMIC_CMC1_PKTDMA_CH3_DEBUG_STATUS_OFFSET (0x52b8) 1686 #define CMIC_CMCx_PKTDMA_CH3_DEBUG_STATUS_OFFSET(x) (0x22b8 + (0x3000 * x)) 1687 #define CMIC_CMC0_PKTDMA_CH3_DESC_ADDR_HI_OFFSET (0x2288) 1688 #define CMIC_CMC1_PKTDMA_CH3_DESC_ADDR_HI_OFFSET (0x5288) 1689 #define CMIC_CMCx_PKTDMA_CH3_DESC_ADDR_HI_OFFSET(x) (0x2288 + (0x3000 * x)) 1690 #define CMIC_CMC0_PKTDMA_CH3_DESC_ADDR_LO_OFFSET (0x2284) 1691 #define CMIC_CMC1_PKTDMA_CH3_DESC_ADDR_LO_OFFSET (0x5284) 1692 #define CMIC_CMCx_PKTDMA_CH3_DESC_ADDR_LO_OFFSET(x) (0x2284 + (0x3000 * x)) 1693 #define CMIC_CMC0_PKTDMA_CH3_DESC_COUNT_REQ_OFFSET (0x22c8) 1694 #define CMIC_CMC1_PKTDMA_CH3_DESC_COUNT_REQ_OFFSET (0x52c8) 1695 #define CMIC_CMCx_PKTDMA_CH3_DESC_COUNT_REQ_OFFSET(x) (0x22c8 + (0x3000 * x)) 1696 #define CMIC_CMC0_PKTDMA_CH3_DESC_COUNT_RX_OFFSET (0x22cc) 1697 #define CMIC_CMC1_PKTDMA_CH3_DESC_COUNT_RX_OFFSET (0x52cc) 1698 #define CMIC_CMCx_PKTDMA_CH3_DESC_COUNT_RX_OFFSET(x) (0x22cc + (0x3000 * x)) 1699 #define CMIC_CMC0_PKTDMA_CH3_DESC_COUNT_STATUS_WR_OFFSET (0x22d0) 1700 #define CMIC_CMC1_PKTDMA_CH3_DESC_COUNT_STATUS_WR_OFFSET (0x52d0) 1701 #define CMIC_CMCx_PKTDMA_CH3_DESC_COUNT_STATUS_WR_OFFSET(x) (0x22d0 + (0x3000 * x)) 1702 #define CMIC_CMC0_PKTDMA_CH3_DESC_HALT_ADDR_HI_OFFSET (0x2290) 1703 #define CMIC_CMC1_PKTDMA_CH3_DESC_HALT_ADDR_HI_OFFSET (0x5290) 1704 #define CMIC_CMCx_PKTDMA_CH3_DESC_HALT_ADDR_HI_OFFSET(x) (0x2290 + (0x3000 * x)) 1705 #define CMIC_CMC0_PKTDMA_CH3_DESC_HALT_ADDR_LO_OFFSET (0x228c) 1706 #define CMIC_CMC1_PKTDMA_CH3_DESC_HALT_ADDR_LO_OFFSET (0x528c) 1707 #define CMIC_CMCx_PKTDMA_CH3_DESC_HALT_ADDR_LO_OFFSET(x) (0x228c + (0x3000 * x)) 1708 #define CMIC_CMC0_PKTDMA_CH3_DESC_MEM_ECC_CONTROL_OFFSET (0x22d8) 1709 #define CMIC_CMC1_PKTDMA_CH3_DESC_MEM_ECC_CONTROL_OFFSET (0x52d8) 1710 #define CMIC_CMCx_PKTDMA_CH3_DESC_MEM_ECC_CONTROL_OFFSET(x) (0x22d8 + (0x3000 * x)) 1711 #define CMIC_CMC0_PKTDMA_CH3_DESC_MEM_ECC_STATUS_OFFSET (0x22d4) 1712 #define CMIC_CMC1_PKTDMA_CH3_DESC_MEM_ECC_STATUS_OFFSET (0x52d4) 1713 #define CMIC_CMCx_PKTDMA_CH3_DESC_MEM_ECC_STATUS_OFFSET(x) (0x22d4 + (0x3000 * x)) 1714 #define CMIC_CMC0_PKTDMA_CH3_DESC_MEM_TM_CONTROL_OFFSET (0x22dc) 1715 #define CMIC_CMC1_PKTDMA_CH3_DESC_MEM_TM_CONTROL_OFFSET (0x52dc) 1716 #define CMIC_CMCx_PKTDMA_CH3_DESC_MEM_TM_CONTROL_OFFSET(x) (0x22dc + (0x3000 * x)) 1717 #define CMIC_CMC0_PKTDMA_CH3_INTR_COAL_OFFSET (0x22a0) 1718 #define CMIC_CMC1_PKTDMA_CH3_INTR_COAL_OFFSET (0x52a0) 1719 #define CMIC_CMCx_PKTDMA_CH3_INTR_COAL_OFFSET(x) (0x22a0 + (0x3000 * x)) 1720 #define CMIC_CMC0_PKTDMA_CH3_PKT_COUNT_RXPKT_OFFSET (0x22bc) 1721 #define CMIC_CMC1_PKTDMA_CH3_PKT_COUNT_RXPKT_OFFSET (0x52bc) 1722 #define CMIC_CMCx_PKTDMA_CH3_PKT_COUNT_RXPKT_OFFSET(x) (0x22bc + (0x3000 * x)) 1723 #define CMIC_CMC0_PKTDMA_CH3_PKT_COUNT_RXPKT_DROP_OFFSET (0x22c4) 1724 #define CMIC_CMC1_PKTDMA_CH3_PKT_COUNT_RXPKT_DROP_OFFSET (0x52c4) 1725 #define CMIC_CMCx_PKTDMA_CH3_PKT_COUNT_RXPKT_DROP_OFFSET(x) (0x22c4 + (0x3000 * x)) 1726 #define CMIC_CMC0_PKTDMA_CH3_PKT_COUNT_TXPKT_OFFSET (0x22c0) 1727 #define CMIC_CMC1_PKTDMA_CH3_PKT_COUNT_TXPKT_OFFSET (0x52c0) 1728 #define CMIC_CMCx_PKTDMA_CH3_PKT_COUNT_TXPKT_OFFSET(x) (0x22c0 + (0x3000 * x)) 1729 #define CMIC_CMC0_PKTDMA_CH3_RXBUF_THRESHOLD_CONFIG_OFFSET (0x22ac) 1730 #define CMIC_CMC1_PKTDMA_CH3_RXBUF_THRESHOLD_CONFIG_OFFSET (0x52ac) 1731 #define CMIC_CMCx_PKTDMA_CH3_RXBUF_THRESHOLD_CONFIG_OFFSET(x) (0x22ac + (0x3000 * x)) 1732 #define CMIC_CMC0_PKTDMA_CH3_STAT_OFFSET (0x2294) 1733 #define CMIC_CMC1_PKTDMA_CH3_STAT_OFFSET (0x5294) 1734 #define CMIC_CMCx_PKTDMA_CH3_STAT_OFFSET(x) (0x2294 + (0x3000 * x)) 1735 #define CMIC_CMC0_PKTDMA_CH4_COS_CTRL_RX_0_OFFSET (0x2318) 1736 #define CMIC_CMC1_PKTDMA_CH4_COS_CTRL_RX_0_OFFSET (0x5318) 1737 #define CMIC_CMCx_PKTDMA_CH4_COS_CTRL_RX_0_OFFSET(x) (0x2318 + (0x3000 * x)) 1738 #define CMIC_CMC0_PKTDMA_CH4_COS_CTRL_RX_1_OFFSET (0x231c) 1739 #define CMIC_CMC1_PKTDMA_CH4_COS_CTRL_RX_1_OFFSET (0x531c) 1740 #define CMIC_CMCx_PKTDMA_CH4_COS_CTRL_RX_1_OFFSET(x) (0x231c + (0x3000 * x)) 1741 #define CMIC_CMC0_PKTDMA_CH4_CTRL_OFFSET (0x2300) 1742 #define CMIC_CMC1_PKTDMA_CH4_CTRL_OFFSET (0x5300) 1743 #define CMIC_CMCx_PKTDMA_CH4_CTRL_OFFSET(x) (0x2300 + (0x3000 * x)) 1744 #define CMIC_CMC0_PKTDMA_CH4_CURR_DESC_HI_OFFSET (0x2328) 1745 #define CMIC_CMC1_PKTDMA_CH4_CURR_DESC_HI_OFFSET (0x5328) 1746 #define CMIC_CMCx_PKTDMA_CH4_CURR_DESC_HI_OFFSET(x) (0x2328 + (0x3000 * x)) 1747 #define CMIC_CMC0_PKTDMA_CH4_CURR_DESC_LO_OFFSET (0x2324) 1748 #define CMIC_CMC1_PKTDMA_CH4_CURR_DESC_LO_OFFSET (0x5324) 1749 #define CMIC_CMCx_PKTDMA_CH4_CURR_DESC_LO_OFFSET(x) (0x2324 + (0x3000 * x)) 1750 #define CMIC_CMC0_PKTDMA_CH4_DEBUG_CONTROL_OFFSET (0x2330) 1751 #define CMIC_CMC1_PKTDMA_CH4_DEBUG_CONTROL_OFFSET (0x5330) 1752 #define CMIC_CMCx_PKTDMA_CH4_DEBUG_CONTROL_OFFSET(x) (0x2330 + (0x3000 * x)) 1753 #define CMIC_CMC0_PKTDMA_CH4_DEBUG_SM_STATUS_OFFSET (0x2334) 1754 #define CMIC_CMC1_PKTDMA_CH4_DEBUG_SM_STATUS_OFFSET (0x5334) 1755 #define CMIC_CMCx_PKTDMA_CH4_DEBUG_SM_STATUS_OFFSET(x) (0x2334 + (0x3000 * x)) 1756 #define CMIC_CMC0_PKTDMA_CH4_DEBUG_STATUS_OFFSET (0x2338) 1757 #define CMIC_CMC1_PKTDMA_CH4_DEBUG_STATUS_OFFSET (0x5338) 1758 #define CMIC_CMCx_PKTDMA_CH4_DEBUG_STATUS_OFFSET(x) (0x2338 + (0x3000 * x)) 1759 #define CMIC_CMC0_PKTDMA_CH4_DESC_ADDR_HI_OFFSET (0x2308) 1760 #define CMIC_CMC1_PKTDMA_CH4_DESC_ADDR_HI_OFFSET (0x5308) 1761 #define CMIC_CMCx_PKTDMA_CH4_DESC_ADDR_HI_OFFSET(x) (0x2308 + (0x3000 * x)) 1762 #define CMIC_CMC0_PKTDMA_CH4_DESC_ADDR_LO_OFFSET (0x2304) 1763 #define CMIC_CMC1_PKTDMA_CH4_DESC_ADDR_LO_OFFSET (0x5304) 1764 #define CMIC_CMCx_PKTDMA_CH4_DESC_ADDR_LO_OFFSET(x) (0x2304 + (0x3000 * x)) 1765 #define CMIC_CMC0_PKTDMA_CH4_DESC_COUNT_REQ_OFFSET (0x2348) 1766 #define CMIC_CMC1_PKTDMA_CH4_DESC_COUNT_REQ_OFFSET (0x5348) 1767 #define CMIC_CMCx_PKTDMA_CH4_DESC_COUNT_REQ_OFFSET(x) (0x2348 + (0x3000 * x)) 1768 #define CMIC_CMC0_PKTDMA_CH4_DESC_COUNT_RX_OFFSET (0x234c) 1769 #define CMIC_CMC1_PKTDMA_CH4_DESC_COUNT_RX_OFFSET (0x534c) 1770 #define CMIC_CMCx_PKTDMA_CH4_DESC_COUNT_RX_OFFSET(x) (0x234c + (0x3000 * x)) 1771 #define CMIC_CMC0_PKTDMA_CH4_DESC_COUNT_STATUS_WR_OFFSET (0x2350) 1772 #define CMIC_CMC1_PKTDMA_CH4_DESC_COUNT_STATUS_WR_OFFSET (0x5350) 1773 #define CMIC_CMCx_PKTDMA_CH4_DESC_COUNT_STATUS_WR_OFFSET(x) (0x2350 + (0x3000 * x)) 1774 #define CMIC_CMC0_PKTDMA_CH4_DESC_HALT_ADDR_HI_OFFSET (0x2310) 1775 #define CMIC_CMC1_PKTDMA_CH4_DESC_HALT_ADDR_HI_OFFSET (0x5310) 1776 #define CMIC_CMCx_PKTDMA_CH4_DESC_HALT_ADDR_HI_OFFSET(x) (0x2310 + (0x3000 * x)) 1777 #define CMIC_CMC0_PKTDMA_CH4_DESC_HALT_ADDR_LO_OFFSET (0x230c) 1778 #define CMIC_CMC1_PKTDMA_CH4_DESC_HALT_ADDR_LO_OFFSET (0x530c) 1779 #define CMIC_CMCx_PKTDMA_CH4_DESC_HALT_ADDR_LO_OFFSET(x) (0x230c + (0x3000 * x)) 1780 #define CMIC_CMC0_PKTDMA_CH4_DESC_MEM_ECC_CONTROL_OFFSET (0x2358) 1781 #define CMIC_CMC1_PKTDMA_CH4_DESC_MEM_ECC_CONTROL_OFFSET (0x5358) 1782 #define CMIC_CMCx_PKTDMA_CH4_DESC_MEM_ECC_CONTROL_OFFSET(x) (0x2358 + (0x3000 * x)) 1783 #define CMIC_CMC0_PKTDMA_CH4_DESC_MEM_ECC_STATUS_OFFSET (0x2354) 1784 #define CMIC_CMC1_PKTDMA_CH4_DESC_MEM_ECC_STATUS_OFFSET (0x5354) 1785 #define CMIC_CMCx_PKTDMA_CH4_DESC_MEM_ECC_STATUS_OFFSET(x) (0x2354 + (0x3000 * x)) 1786 #define CMIC_CMC0_PKTDMA_CH4_DESC_MEM_TM_CONTROL_OFFSET (0x235c) 1787 #define CMIC_CMC1_PKTDMA_CH4_DESC_MEM_TM_CONTROL_OFFSET (0x535c) 1788 #define CMIC_CMCx_PKTDMA_CH4_DESC_MEM_TM_CONTROL_OFFSET(x) (0x235c + (0x3000 * x)) 1789 #define CMIC_CMC0_PKTDMA_CH4_INTR_COAL_OFFSET (0x2320) 1790 #define CMIC_CMC1_PKTDMA_CH4_INTR_COAL_OFFSET (0x5320) 1791 #define CMIC_CMCx_PKTDMA_CH4_INTR_COAL_OFFSET(x) (0x2320 + (0x3000 * x)) 1792 #define CMIC_CMC0_PKTDMA_CH4_PKT_COUNT_RXPKT_OFFSET (0x233c) 1793 #define CMIC_CMC1_PKTDMA_CH4_PKT_COUNT_RXPKT_OFFSET (0x533c) 1794 #define CMIC_CMCx_PKTDMA_CH4_PKT_COUNT_RXPKT_OFFSET(x) (0x233c + (0x3000 * x)) 1795 #define CMIC_CMC0_PKTDMA_CH4_PKT_COUNT_RXPKT_DROP_OFFSET (0x2344) 1796 #define CMIC_CMC1_PKTDMA_CH4_PKT_COUNT_RXPKT_DROP_OFFSET (0x5344) 1797 #define CMIC_CMCx_PKTDMA_CH4_PKT_COUNT_RXPKT_DROP_OFFSET(x) (0x2344 + (0x3000 * x)) 1798 #define CMIC_CMC0_PKTDMA_CH4_PKT_COUNT_TXPKT_OFFSET (0x2340) 1799 #define CMIC_CMC1_PKTDMA_CH4_PKT_COUNT_TXPKT_OFFSET (0x5340) 1800 #define CMIC_CMCx_PKTDMA_CH4_PKT_COUNT_TXPKT_OFFSET(x) (0x2340 + (0x3000 * x)) 1801 #define CMIC_CMC0_PKTDMA_CH4_RXBUF_THRESHOLD_CONFIG_OFFSET (0x232c) 1802 #define CMIC_CMC1_PKTDMA_CH4_RXBUF_THRESHOLD_CONFIG_OFFSET (0x532c) 1803 #define CMIC_CMCx_PKTDMA_CH4_RXBUF_THRESHOLD_CONFIG_OFFSET(x) (0x232c + (0x3000 * x)) 1804 #define CMIC_CMC0_PKTDMA_CH4_STAT_OFFSET (0x2314) 1805 #define CMIC_CMC1_PKTDMA_CH4_STAT_OFFSET (0x5314) 1806 #define CMIC_CMCx_PKTDMA_CH4_STAT_OFFSET(x) (0x2314 + (0x3000 * x)) 1807 #define CMIC_CMC0_PKTDMA_CH5_COS_CTRL_RX_0_OFFSET (0x2398) 1808 #define CMIC_CMC1_PKTDMA_CH5_COS_CTRL_RX_0_OFFSET (0x5398) 1809 #define CMIC_CMCx_PKTDMA_CH5_COS_CTRL_RX_0_OFFSET(x) (0x2398 + (0x3000 * x)) 1810 #define CMIC_CMC0_PKTDMA_CH5_COS_CTRL_RX_1_OFFSET (0x239c) 1811 #define CMIC_CMC1_PKTDMA_CH5_COS_CTRL_RX_1_OFFSET (0x539c) 1812 #define CMIC_CMCx_PKTDMA_CH5_COS_CTRL_RX_1_OFFSET(x) (0x239c + (0x3000 * x)) 1813 #define CMIC_CMC0_PKTDMA_CH5_CTRL_OFFSET (0x2380) 1814 #define CMIC_CMC1_PKTDMA_CH5_CTRL_OFFSET (0x5380) 1815 #define CMIC_CMCx_PKTDMA_CH5_CTRL_OFFSET(x) (0x2380 + (0x3000 * x)) 1816 #define CMIC_CMC0_PKTDMA_CH5_CURR_DESC_HI_OFFSET (0x23a8) 1817 #define CMIC_CMC1_PKTDMA_CH5_CURR_DESC_HI_OFFSET (0x53a8) 1818 #define CMIC_CMCx_PKTDMA_CH5_CURR_DESC_HI_OFFSET(x) (0x23a8 + (0x3000 * x)) 1819 #define CMIC_CMC0_PKTDMA_CH5_CURR_DESC_LO_OFFSET (0x23a4) 1820 #define CMIC_CMC1_PKTDMA_CH5_CURR_DESC_LO_OFFSET (0x53a4) 1821 #define CMIC_CMCx_PKTDMA_CH5_CURR_DESC_LO_OFFSET(x) (0x23a4 + (0x3000 * x)) 1822 #define CMIC_CMC0_PKTDMA_CH5_DEBUG_CONTROL_OFFSET (0x23b0) 1823 #define CMIC_CMC1_PKTDMA_CH5_DEBUG_CONTROL_OFFSET (0x53b0) 1824 #define CMIC_CMCx_PKTDMA_CH5_DEBUG_CONTROL_OFFSET(x) (0x23b0 + (0x3000 * x)) 1825 #define CMIC_CMC0_PKTDMA_CH5_DEBUG_SM_STATUS_OFFSET (0x23b4) 1826 #define CMIC_CMC1_PKTDMA_CH5_DEBUG_SM_STATUS_OFFSET (0x53b4) 1827 #define CMIC_CMCx_PKTDMA_CH5_DEBUG_SM_STATUS_OFFSET(x) (0x23b4 + (0x3000 * x)) 1828 #define CMIC_CMC0_PKTDMA_CH5_DEBUG_STATUS_OFFSET (0x23b8) 1829 #define CMIC_CMC1_PKTDMA_CH5_DEBUG_STATUS_OFFSET (0x53b8) 1830 #define CMIC_CMCx_PKTDMA_CH5_DEBUG_STATUS_OFFSET(x) (0x23b8 + (0x3000 * x)) 1831 #define CMIC_CMC0_PKTDMA_CH5_DESC_ADDR_HI_OFFSET (0x2388) 1832 #define CMIC_CMC1_PKTDMA_CH5_DESC_ADDR_HI_OFFSET (0x5388) 1833 #define CMIC_CMCx_PKTDMA_CH5_DESC_ADDR_HI_OFFSET(x) (0x2388 + (0x3000 * x)) 1834 #define CMIC_CMC0_PKTDMA_CH5_DESC_ADDR_LO_OFFSET (0x2384) 1835 #define CMIC_CMC1_PKTDMA_CH5_DESC_ADDR_LO_OFFSET (0x5384) 1836 #define CMIC_CMCx_PKTDMA_CH5_DESC_ADDR_LO_OFFSET(x) (0x2384 + (0x3000 * x)) 1837 #define CMIC_CMC0_PKTDMA_CH5_DESC_COUNT_REQ_OFFSET (0x23c8) 1838 #define CMIC_CMC1_PKTDMA_CH5_DESC_COUNT_REQ_OFFSET (0x53c8) 1839 #define CMIC_CMCx_PKTDMA_CH5_DESC_COUNT_REQ_OFFSET(x) (0x23c8 + (0x3000 * x)) 1840 #define CMIC_CMC0_PKTDMA_CH5_DESC_COUNT_RX_OFFSET (0x23cc) 1841 #define CMIC_CMC1_PKTDMA_CH5_DESC_COUNT_RX_OFFSET (0x53cc) 1842 #define CMIC_CMCx_PKTDMA_CH5_DESC_COUNT_RX_OFFSET(x) (0x23cc + (0x3000 * x)) 1843 #define CMIC_CMC0_PKTDMA_CH5_DESC_COUNT_STATUS_WR_OFFSET (0x23d0) 1844 #define CMIC_CMC1_PKTDMA_CH5_DESC_COUNT_STATUS_WR_OFFSET (0x53d0) 1845 #define CMIC_CMCx_PKTDMA_CH5_DESC_COUNT_STATUS_WR_OFFSET(x) (0x23d0 + (0x3000 * x)) 1846 #define CMIC_CMC0_PKTDMA_CH5_DESC_HALT_ADDR_HI_OFFSET (0x2390) 1847 #define CMIC_CMC1_PKTDMA_CH5_DESC_HALT_ADDR_HI_OFFSET (0x5390) 1848 #define CMIC_CMCx_PKTDMA_CH5_DESC_HALT_ADDR_HI_OFFSET(x) (0x2390 + (0x3000 * x)) 1849 #define CMIC_CMC0_PKTDMA_CH5_DESC_HALT_ADDR_LO_OFFSET (0x238c) 1850 #define CMIC_CMC1_PKTDMA_CH5_DESC_HALT_ADDR_LO_OFFSET (0x538c) 1851 #define CMIC_CMCx_PKTDMA_CH5_DESC_HALT_ADDR_LO_OFFSET(x) (0x238c + (0x3000 * x)) 1852 #define CMIC_CMC0_PKTDMA_CH5_DESC_MEM_ECC_CONTROL_OFFSET (0x23d8) 1853 #define CMIC_CMC1_PKTDMA_CH5_DESC_MEM_ECC_CONTROL_OFFSET (0x53d8) 1854 #define CMIC_CMCx_PKTDMA_CH5_DESC_MEM_ECC_CONTROL_OFFSET(x) (0x23d8 + (0x3000 * x)) 1855 #define CMIC_CMC0_PKTDMA_CH5_DESC_MEM_ECC_STATUS_OFFSET (0x23d4) 1856 #define CMIC_CMC1_PKTDMA_CH5_DESC_MEM_ECC_STATUS_OFFSET (0x53d4) 1857 #define CMIC_CMCx_PKTDMA_CH5_DESC_MEM_ECC_STATUS_OFFSET(x) (0x23d4 + (0x3000 * x)) 1858 #define CMIC_CMC0_PKTDMA_CH5_DESC_MEM_TM_CONTROL_OFFSET (0x23dc) 1859 #define CMIC_CMC1_PKTDMA_CH5_DESC_MEM_TM_CONTROL_OFFSET (0x53dc) 1860 #define CMIC_CMCx_PKTDMA_CH5_DESC_MEM_TM_CONTROL_OFFSET(x) (0x23dc + (0x3000 * x)) 1861 #define CMIC_CMC0_PKTDMA_CH5_INTR_COAL_OFFSET (0x23a0) 1862 #define CMIC_CMC1_PKTDMA_CH5_INTR_COAL_OFFSET (0x53a0) 1863 #define CMIC_CMCx_PKTDMA_CH5_INTR_COAL_OFFSET(x) (0x23a0 + (0x3000 * x)) 1864 #define CMIC_CMC0_PKTDMA_CH5_PKT_COUNT_RXPKT_OFFSET (0x23bc) 1865 #define CMIC_CMC1_PKTDMA_CH5_PKT_COUNT_RXPKT_OFFSET (0x53bc) 1866 #define CMIC_CMCx_PKTDMA_CH5_PKT_COUNT_RXPKT_OFFSET(x) (0x23bc + (0x3000 * x)) 1867 #define CMIC_CMC0_PKTDMA_CH5_PKT_COUNT_RXPKT_DROP_OFFSET (0x23c4) 1868 #define CMIC_CMC1_PKTDMA_CH5_PKT_COUNT_RXPKT_DROP_OFFSET (0x53c4) 1869 #define CMIC_CMCx_PKTDMA_CH5_PKT_COUNT_RXPKT_DROP_OFFSET(x) (0x23c4 + (0x3000 * x)) 1870 #define CMIC_CMC0_PKTDMA_CH5_PKT_COUNT_TXPKT_OFFSET (0x23c0) 1871 #define CMIC_CMC1_PKTDMA_CH5_PKT_COUNT_TXPKT_OFFSET (0x53c0) 1872 #define CMIC_CMCx_PKTDMA_CH5_PKT_COUNT_TXPKT_OFFSET(x) (0x23c0 + (0x3000 * x)) 1873 #define CMIC_CMC0_PKTDMA_CH5_RXBUF_THRESHOLD_CONFIG_OFFSET (0x23ac) 1874 #define CMIC_CMC1_PKTDMA_CH5_RXBUF_THRESHOLD_CONFIG_OFFSET (0x53ac) 1875 #define CMIC_CMCx_PKTDMA_CH5_RXBUF_THRESHOLD_CONFIG_OFFSET(x) (0x23ac + (0x3000 * x)) 1876 #define CMIC_CMC0_PKTDMA_CH5_STAT_OFFSET (0x2394) 1877 #define CMIC_CMC1_PKTDMA_CH5_STAT_OFFSET (0x5394) 1878 #define CMIC_CMCx_PKTDMA_CH5_STAT_OFFSET(x) (0x2394 + (0x3000 * x)) 1879 #define CMIC_CMC0_PKTDMA_CH6_COS_CTRL_RX_0_OFFSET (0x2418) 1880 #define CMIC_CMC1_PKTDMA_CH6_COS_CTRL_RX_0_OFFSET (0x5418) 1881 #define CMIC_CMCx_PKTDMA_CH6_COS_CTRL_RX_0_OFFSET(x) (0x2418 + (0x3000 * x)) 1882 #define CMIC_CMC0_PKTDMA_CH6_COS_CTRL_RX_1_OFFSET (0x241c) 1883 #define CMIC_CMC1_PKTDMA_CH6_COS_CTRL_RX_1_OFFSET (0x541c) 1884 #define CMIC_CMCx_PKTDMA_CH6_COS_CTRL_RX_1_OFFSET(x) (0x241c + (0x3000 * x)) 1885 #define CMIC_CMC0_PKTDMA_CH6_CTRL_OFFSET (0x2400) 1886 #define CMIC_CMC1_PKTDMA_CH6_CTRL_OFFSET (0x5400) 1887 #define CMIC_CMCx_PKTDMA_CH6_CTRL_OFFSET(x) (0x2400 + (0x3000 * x)) 1888 #define CMIC_CMC0_PKTDMA_CH6_CURR_DESC_HI_OFFSET (0x2428) 1889 #define CMIC_CMC1_PKTDMA_CH6_CURR_DESC_HI_OFFSET (0x5428) 1890 #define CMIC_CMCx_PKTDMA_CH6_CURR_DESC_HI_OFFSET(x) (0x2428 + (0x3000 * x)) 1891 #define CMIC_CMC0_PKTDMA_CH6_CURR_DESC_LO_OFFSET (0x2424) 1892 #define CMIC_CMC1_PKTDMA_CH6_CURR_DESC_LO_OFFSET (0x5424) 1893 #define CMIC_CMCx_PKTDMA_CH6_CURR_DESC_LO_OFFSET(x) (0x2424 + (0x3000 * x)) 1894 #define CMIC_CMC0_PKTDMA_CH6_DEBUG_CONTROL_OFFSET (0x2430) 1895 #define CMIC_CMC1_PKTDMA_CH6_DEBUG_CONTROL_OFFSET (0x5430) 1896 #define CMIC_CMCx_PKTDMA_CH6_DEBUG_CONTROL_OFFSET(x) (0x2430 + (0x3000 * x)) 1897 #define CMIC_CMC0_PKTDMA_CH6_DEBUG_SM_STATUS_OFFSET (0x2434) 1898 #define CMIC_CMC1_PKTDMA_CH6_DEBUG_SM_STATUS_OFFSET (0x5434) 1899 #define CMIC_CMCx_PKTDMA_CH6_DEBUG_SM_STATUS_OFFSET(x) (0x2434 + (0x3000 * x)) 1900 #define CMIC_CMC0_PKTDMA_CH6_DEBUG_STATUS_OFFSET (0x2438) 1901 #define CMIC_CMC1_PKTDMA_CH6_DEBUG_STATUS_OFFSET (0x5438) 1902 #define CMIC_CMCx_PKTDMA_CH6_DEBUG_STATUS_OFFSET(x) (0x2438 + (0x3000 * x)) 1903 #define CMIC_CMC0_PKTDMA_CH6_DESC_ADDR_HI_OFFSET (0x2408) 1904 #define CMIC_CMC1_PKTDMA_CH6_DESC_ADDR_HI_OFFSET (0x5408) 1905 #define CMIC_CMCx_PKTDMA_CH6_DESC_ADDR_HI_OFFSET(x) (0x2408 + (0x3000 * x)) 1906 #define CMIC_CMC0_PKTDMA_CH6_DESC_ADDR_LO_OFFSET (0x2404) 1907 #define CMIC_CMC1_PKTDMA_CH6_DESC_ADDR_LO_OFFSET (0x5404) 1908 #define CMIC_CMCx_PKTDMA_CH6_DESC_ADDR_LO_OFFSET(x) (0x2404 + (0x3000 * x)) 1909 #define CMIC_CMC0_PKTDMA_CH6_DESC_COUNT_REQ_OFFSET (0x2448) 1910 #define CMIC_CMC1_PKTDMA_CH6_DESC_COUNT_REQ_OFFSET (0x5448) 1911 #define CMIC_CMCx_PKTDMA_CH6_DESC_COUNT_REQ_OFFSET(x) (0x2448 + (0x3000 * x)) 1912 #define CMIC_CMC0_PKTDMA_CH6_DESC_COUNT_RX_OFFSET (0x244c) 1913 #define CMIC_CMC1_PKTDMA_CH6_DESC_COUNT_RX_OFFSET (0x544c) 1914 #define CMIC_CMCx_PKTDMA_CH6_DESC_COUNT_RX_OFFSET(x) (0x244c + (0x3000 * x)) 1915 #define CMIC_CMC0_PKTDMA_CH6_DESC_COUNT_STATUS_WR_OFFSET (0x2450) 1916 #define CMIC_CMC1_PKTDMA_CH6_DESC_COUNT_STATUS_WR_OFFSET (0x5450) 1917 #define CMIC_CMCx_PKTDMA_CH6_DESC_COUNT_STATUS_WR_OFFSET(x) (0x2450 + (0x3000 * x)) 1918 #define CMIC_CMC0_PKTDMA_CH6_DESC_HALT_ADDR_HI_OFFSET (0x2410) 1919 #define CMIC_CMC1_PKTDMA_CH6_DESC_HALT_ADDR_HI_OFFSET (0x5410) 1920 #define CMIC_CMCx_PKTDMA_CH6_DESC_HALT_ADDR_HI_OFFSET(x) (0x2410 + (0x3000 * x)) 1921 #define CMIC_CMC0_PKTDMA_CH6_DESC_HALT_ADDR_LO_OFFSET (0x240c) 1922 #define CMIC_CMC1_PKTDMA_CH6_DESC_HALT_ADDR_LO_OFFSET (0x540c) 1923 #define CMIC_CMCx_PKTDMA_CH6_DESC_HALT_ADDR_LO_OFFSET(x) (0x240c + (0x3000 * x)) 1924 #define CMIC_CMC0_PKTDMA_CH6_DESC_MEM_ECC_CONTROL_OFFSET (0x2458) 1925 #define CMIC_CMC1_PKTDMA_CH6_DESC_MEM_ECC_CONTROL_OFFSET (0x5458) 1926 #define CMIC_CMCx_PKTDMA_CH6_DESC_MEM_ECC_CONTROL_OFFSET(x) (0x2458 + (0x3000 * x)) 1927 #define CMIC_CMC0_PKTDMA_CH6_DESC_MEM_ECC_STATUS_OFFSET (0x2454) 1928 #define CMIC_CMC1_PKTDMA_CH6_DESC_MEM_ECC_STATUS_OFFSET (0x5454) 1929 #define CMIC_CMCx_PKTDMA_CH6_DESC_MEM_ECC_STATUS_OFFSET(x) (0x2454 + (0x3000 * x)) 1930 #define CMIC_CMC0_PKTDMA_CH6_DESC_MEM_TM_CONTROL_OFFSET (0x245c) 1931 #define CMIC_CMC1_PKTDMA_CH6_DESC_MEM_TM_CONTROL_OFFSET (0x545c) 1932 #define CMIC_CMCx_PKTDMA_CH6_DESC_MEM_TM_CONTROL_OFFSET(x) (0x245c + (0x3000 * x)) 1933 #define CMIC_CMC0_PKTDMA_CH6_INTR_COAL_OFFSET (0x2420) 1934 #define CMIC_CMC1_PKTDMA_CH6_INTR_COAL_OFFSET (0x5420) 1935 #define CMIC_CMCx_PKTDMA_CH6_INTR_COAL_OFFSET(x) (0x2420 + (0x3000 * x)) 1936 #define CMIC_CMC0_PKTDMA_CH6_PKT_COUNT_RXPKT_OFFSET (0x243c) 1937 #define CMIC_CMC1_PKTDMA_CH6_PKT_COUNT_RXPKT_OFFSET (0x543c) 1938 #define CMIC_CMCx_PKTDMA_CH6_PKT_COUNT_RXPKT_OFFSET(x) (0x243c + (0x3000 * x)) 1939 #define CMIC_CMC0_PKTDMA_CH6_PKT_COUNT_RXPKT_DROP_OFFSET (0x2444) 1940 #define CMIC_CMC1_PKTDMA_CH6_PKT_COUNT_RXPKT_DROP_OFFSET (0x5444) 1941 #define CMIC_CMCx_PKTDMA_CH6_PKT_COUNT_RXPKT_DROP_OFFSET(x) (0x2444 + (0x3000 * x)) 1942 #define CMIC_CMC0_PKTDMA_CH6_PKT_COUNT_TXPKT_OFFSET (0x2440) 1943 #define CMIC_CMC1_PKTDMA_CH6_PKT_COUNT_TXPKT_OFFSET (0x5440) 1944 #define CMIC_CMCx_PKTDMA_CH6_PKT_COUNT_TXPKT_OFFSET(x) (0x2440 + (0x3000 * x)) 1945 #define CMIC_CMC0_PKTDMA_CH6_RXBUF_THRESHOLD_CONFIG_OFFSET (0x242c) 1946 #define CMIC_CMC1_PKTDMA_CH6_RXBUF_THRESHOLD_CONFIG_OFFSET (0x542c) 1947 #define CMIC_CMCx_PKTDMA_CH6_RXBUF_THRESHOLD_CONFIG_OFFSET(x) (0x242c + (0x3000 * x)) 1948 #define CMIC_CMC0_PKTDMA_CH6_STAT_OFFSET (0x2414) 1949 #define CMIC_CMC1_PKTDMA_CH6_STAT_OFFSET (0x5414) 1950 #define CMIC_CMCx_PKTDMA_CH6_STAT_OFFSET(x) (0x2414 + (0x3000 * x)) 1951 #define CMIC_CMC0_PKTDMA_CH7_COS_CTRL_RX_0_OFFSET (0x2498) 1952 #define CMIC_CMC1_PKTDMA_CH7_COS_CTRL_RX_0_OFFSET (0x5498) 1953 #define CMIC_CMCx_PKTDMA_CH7_COS_CTRL_RX_0_OFFSET(x) (0x2498 + (0x3000 * x)) 1954 #define CMIC_CMC0_PKTDMA_CH7_COS_CTRL_RX_1_OFFSET (0x249c) 1955 #define CMIC_CMC1_PKTDMA_CH7_COS_CTRL_RX_1_OFFSET (0x549c) 1956 #define CMIC_CMCx_PKTDMA_CH7_COS_CTRL_RX_1_OFFSET(x) (0x249c + (0x3000 * x)) 1957 #define CMIC_CMC0_PKTDMA_CH7_CTRL_OFFSET (0x2480) 1958 #define CMIC_CMC1_PKTDMA_CH7_CTRL_OFFSET (0x5480) 1959 #define CMIC_CMCx_PKTDMA_CH7_CTRL_OFFSET(x) (0x2480 + (0x3000 * x)) 1960 #define CMIC_CMC0_PKTDMA_CH7_CURR_DESC_HI_OFFSET (0x24a8) 1961 #define CMIC_CMC1_PKTDMA_CH7_CURR_DESC_HI_OFFSET (0x54a8) 1962 #define CMIC_CMCx_PKTDMA_CH7_CURR_DESC_HI_OFFSET(x) (0x24a8 + (0x3000 * x)) 1963 #define CMIC_CMC0_PKTDMA_CH7_CURR_DESC_LO_OFFSET (0x24a4) 1964 #define CMIC_CMC1_PKTDMA_CH7_CURR_DESC_LO_OFFSET (0x54a4) 1965 #define CMIC_CMCx_PKTDMA_CH7_CURR_DESC_LO_OFFSET(x) (0x24a4 + (0x3000 * x)) 1966 #define CMIC_CMC0_PKTDMA_CH7_DEBUG_CONTROL_OFFSET (0x24b0) 1967 #define CMIC_CMC1_PKTDMA_CH7_DEBUG_CONTROL_OFFSET (0x54b0) 1968 #define CMIC_CMCx_PKTDMA_CH7_DEBUG_CONTROL_OFFSET(x) (0x24b0 + (0x3000 * x)) 1969 #define CMIC_CMC0_PKTDMA_CH7_DEBUG_SM_STATUS_OFFSET (0x24b4) 1970 #define CMIC_CMC1_PKTDMA_CH7_DEBUG_SM_STATUS_OFFSET (0x54b4) 1971 #define CMIC_CMCx_PKTDMA_CH7_DEBUG_SM_STATUS_OFFSET(x) (0x24b4 + (0x3000 * x)) 1972 #define CMIC_CMC0_PKTDMA_CH7_DEBUG_STATUS_OFFSET (0x24b8) 1973 #define CMIC_CMC1_PKTDMA_CH7_DEBUG_STATUS_OFFSET (0x54b8) 1974 #define CMIC_CMCx_PKTDMA_CH7_DEBUG_STATUS_OFFSET(x) (0x24b8 + (0x3000 * x)) 1975 #define CMIC_CMC0_PKTDMA_CH7_DESC_ADDR_HI_OFFSET (0x2488) 1976 #define CMIC_CMC1_PKTDMA_CH7_DESC_ADDR_HI_OFFSET (0x5488) 1977 #define CMIC_CMCx_PKTDMA_CH7_DESC_ADDR_HI_OFFSET(x) (0x2488 + (0x3000 * x)) 1978 #define CMIC_CMC0_PKTDMA_CH7_DESC_ADDR_LO_OFFSET (0x2484) 1979 #define CMIC_CMC1_PKTDMA_CH7_DESC_ADDR_LO_OFFSET (0x5484) 1980 #define CMIC_CMCx_PKTDMA_CH7_DESC_ADDR_LO_OFFSET(x) (0x2484 + (0x3000 * x)) 1981 #define CMIC_CMC0_PKTDMA_CH7_DESC_COUNT_REQ_OFFSET (0x24c8) 1982 #define CMIC_CMC1_PKTDMA_CH7_DESC_COUNT_REQ_OFFSET (0x54c8) 1983 #define CMIC_CMCx_PKTDMA_CH7_DESC_COUNT_REQ_OFFSET(x) (0x24c8 + (0x3000 * x)) 1984 #define CMIC_CMC0_PKTDMA_CH7_DESC_COUNT_RX_OFFSET (0x24cc) 1985 #define CMIC_CMC1_PKTDMA_CH7_DESC_COUNT_RX_OFFSET (0x54cc) 1986 #define CMIC_CMCx_PKTDMA_CH7_DESC_COUNT_RX_OFFSET(x) (0x24cc + (0x3000 * x)) 1987 #define CMIC_CMC0_PKTDMA_CH7_DESC_COUNT_STATUS_WR_OFFSET (0x24d0) 1988 #define CMIC_CMC1_PKTDMA_CH7_DESC_COUNT_STATUS_WR_OFFSET (0x54d0) 1989 #define CMIC_CMCx_PKTDMA_CH7_DESC_COUNT_STATUS_WR_OFFSET(x) (0x24d0 + (0x3000 * x)) 1990 #define CMIC_CMC0_PKTDMA_CH7_DESC_HALT_ADDR_HI_OFFSET (0x2490) 1991 #define CMIC_CMC1_PKTDMA_CH7_DESC_HALT_ADDR_HI_OFFSET (0x5490) 1992 #define CMIC_CMCx_PKTDMA_CH7_DESC_HALT_ADDR_HI_OFFSET(x) (0x2490 + (0x3000 * x)) 1993 #define CMIC_CMC0_PKTDMA_CH7_DESC_HALT_ADDR_LO_OFFSET (0x248c) 1994 #define CMIC_CMC1_PKTDMA_CH7_DESC_HALT_ADDR_LO_OFFSET (0x548c) 1995 #define CMIC_CMCx_PKTDMA_CH7_DESC_HALT_ADDR_LO_OFFSET(x) (0x248c + (0x3000 * x)) 1996 #define CMIC_CMC0_PKTDMA_CH7_DESC_MEM_ECC_CONTROL_OFFSET (0x24d8) 1997 #define CMIC_CMC1_PKTDMA_CH7_DESC_MEM_ECC_CONTROL_OFFSET (0x54d8) 1998 #define CMIC_CMCx_PKTDMA_CH7_DESC_MEM_ECC_CONTROL_OFFSET(x) (0x24d8 + (0x3000 * x)) 1999 #define CMIC_CMC0_PKTDMA_CH7_DESC_MEM_ECC_STATUS_OFFSET (0x24d4) 2000 #define CMIC_CMC1_PKTDMA_CH7_DESC_MEM_ECC_STATUS_OFFSET (0x54d4) 2001 #define CMIC_CMCx_PKTDMA_CH7_DESC_MEM_ECC_STATUS_OFFSET(x) (0x24d4 + (0x3000 * x)) 2002 #define CMIC_CMC0_PKTDMA_CH7_DESC_MEM_TM_CONTROL_OFFSET (0x24dc) 2003 #define CMIC_CMC1_PKTDMA_CH7_DESC_MEM_TM_CONTROL_OFFSET (0x54dc) 2004 #define CMIC_CMCx_PKTDMA_CH7_DESC_MEM_TM_CONTROL_OFFSET(x) (0x24dc + (0x3000 * x)) 2005 #define CMIC_CMC0_PKTDMA_CH7_INTR_COAL_OFFSET (0x24a0) 2006 #define CMIC_CMC1_PKTDMA_CH7_INTR_COAL_OFFSET (0x54a0) 2007 #define CMIC_CMCx_PKTDMA_CH7_INTR_COAL_OFFSET(x) (0x24a0 + (0x3000 * x)) 2008 #define CMIC_CMC0_PKTDMA_CH7_PKT_COUNT_RXPKT_OFFSET (0x24bc) 2009 #define CMIC_CMC1_PKTDMA_CH7_PKT_COUNT_RXPKT_OFFSET (0x54bc) 2010 #define CMIC_CMCx_PKTDMA_CH7_PKT_COUNT_RXPKT_OFFSET(x) (0x24bc + (0x3000 * x)) 2011 #define CMIC_CMC0_PKTDMA_CH7_PKT_COUNT_RXPKT_DROP_OFFSET (0x24c4) 2012 #define CMIC_CMC1_PKTDMA_CH7_PKT_COUNT_RXPKT_DROP_OFFSET (0x54c4) 2013 #define CMIC_CMCx_PKTDMA_CH7_PKT_COUNT_RXPKT_DROP_OFFSET(x) (0x24c4 + (0x3000 * x)) 2014 #define CMIC_CMC0_PKTDMA_CH7_PKT_COUNT_TXPKT_OFFSET (0x24c0) 2015 #define CMIC_CMC1_PKTDMA_CH7_PKT_COUNT_TXPKT_OFFSET (0x54c0) 2016 #define CMIC_CMCx_PKTDMA_CH7_PKT_COUNT_TXPKT_OFFSET(x) (0x24c0 + (0x3000 * x)) 2017 #define CMIC_CMC0_PKTDMA_CH7_RXBUF_THRESHOLD_CONFIG_OFFSET (0x24ac) 2018 #define CMIC_CMC1_PKTDMA_CH7_RXBUF_THRESHOLD_CONFIG_OFFSET (0x54ac) 2019 #define CMIC_CMCx_PKTDMA_CH7_RXBUF_THRESHOLD_CONFIG_OFFSET(x) (0x24ac + (0x3000 * x)) 2020 #define CMIC_CMC0_PKTDMA_CH7_STAT_OFFSET (0x2494) 2021 #define CMIC_CMC1_PKTDMA_CH7_STAT_OFFSET (0x5494) 2022 #define CMIC_CMCx_PKTDMA_CH7_STAT_OFFSET(x) (0x2494 + (0x3000 * x)) 2023 #define CMIC_CMC0_SBUSDMA_CH0_CONTROL_OFFSET (0x3000) 2024 #define CMIC_CMC1_SBUSDMA_CH0_CONTROL_OFFSET (0x6000) 2025 #define CMIC_CMCx_SBUSDMA_CH0_CONTROL_OFFSET(x) (0x3000 + (0x3000 * x)) 2026 #define CMIC_CMC0_SBUSDMA_CH0_COUNT_OFFSET (0x3008) 2027 #define CMIC_CMC1_SBUSDMA_CH0_COUNT_OFFSET (0x6008) 2028 #define CMIC_CMCx_SBUSDMA_CH0_COUNT_OFFSET(x) (0x3008 + (0x3000 * x)) 2029 #define CMIC_CMC0_SBUSDMA_CH0_CUR_DESC_ADDRESS_HI_OFFSET (0x3038) 2030 #define CMIC_CMC1_SBUSDMA_CH0_CUR_DESC_ADDRESS_HI_OFFSET (0x6038) 2031 #define CMIC_CMCx_SBUSDMA_CH0_CUR_DESC_ADDRESS_HI_OFFSET(x) (0x3038 + (0x3000 * x)) 2032 #define CMIC_CMC0_SBUSDMA_CH0_CUR_DESC_ADDRESS_LO_OFFSET (0x3034) 2033 #define CMIC_CMC1_SBUSDMA_CH0_CUR_DESC_ADDRESS_LO_OFFSET (0x6034) 2034 #define CMIC_CMCx_SBUSDMA_CH0_CUR_DESC_ADDRESS_LO_OFFSET(x) (0x3034 + (0x3000 * x)) 2035 #define CMIC_CMC0_SBUSDMA_CH0_CUR_HOSTMEM_ADDRESS_HI_OFFSET (0x302c) 2036 #define CMIC_CMC1_SBUSDMA_CH0_CUR_HOSTMEM_ADDRESS_HI_OFFSET (0x602c) 2037 #define CMIC_CMCx_SBUSDMA_CH0_CUR_HOSTMEM_ADDRESS_HI_OFFSET(x) (0x302c + (0x3000 * x)) 2038 #define CMIC_CMC0_SBUSDMA_CH0_CUR_HOSTMEM_ADDRESS_LO_OFFSET (0x3028) 2039 #define CMIC_CMC1_SBUSDMA_CH0_CUR_HOSTMEM_ADDRESS_LO_OFFSET (0x6028) 2040 #define CMIC_CMCx_SBUSDMA_CH0_CUR_HOSTMEM_ADDRESS_LO_OFFSET(x) (0x3028 + (0x3000 * x)) 2041 #define CMIC_CMC0_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_COUNT_OFFSET (0x3050) 2042 #define CMIC_CMC1_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_COUNT_OFFSET (0x6050) 2043 #define CMIC_CMCx_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_COUNT_OFFSET(x) (0x3050 + (0x3000 * x)) 2044 #define CMIC_CMC0_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_HI_OFFSET (0x304c) 2045 #define CMIC_CMC1_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_HI_OFFSET (0x604c) 2046 #define CMIC_CMCx_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_HI_OFFSET(x) (0x304c + (0x3000 * x)) 2047 #define CMIC_CMC0_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_LO_OFFSET (0x3048) 2048 #define CMIC_CMC1_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_LO_OFFSET (0x6048) 2049 #define CMIC_CMCx_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_LO_OFFSET(x) (0x3048 + (0x3000 * x)) 2050 #define CMIC_CMC0_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_OPCODE_OFFSET (0x3040) 2051 #define CMIC_CMC1_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_OPCODE_OFFSET (0x6040) 2052 #define CMIC_CMCx_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_OPCODE_OFFSET(x) (0x3040 + (0x3000 * x)) 2053 #define CMIC_CMC0_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_REQUEST_OFFSET (0x303c) 2054 #define CMIC_CMC1_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_REQUEST_OFFSET (0x603c) 2055 #define CMIC_CMCx_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_REQUEST_OFFSET(x) (0x303c + (0x3000 * x)) 2056 #define CMIC_CMC0_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_SBUS_START_ADDRESS_OFFSET (0x3044) 2057 #define CMIC_CMC1_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_SBUS_START_ADDRESS_OFFSET (0x6044) 2058 #define CMIC_CMCx_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_SBUS_START_ADDRESS_OFFSET(x) (0x3044 + (0x3000 * x)) 2059 #define CMIC_CMC0_SBUSDMA_CH0_CUR_SBUS_ADDRESS_OFFSET (0x3030) 2060 #define CMIC_CMC1_SBUSDMA_CH0_CUR_SBUS_ADDRESS_OFFSET (0x6030) 2061 #define CMIC_CMCx_SBUSDMA_CH0_CUR_SBUS_ADDRESS_OFFSET(x) (0x3030 + (0x3000 * x)) 2062 #define CMIC_CMC0_SBUSDMA_CH0_DESC_START_ADDRESS_HI_OFFSET (0x3020) 2063 #define CMIC_CMC1_SBUSDMA_CH0_DESC_START_ADDRESS_HI_OFFSET (0x6020) 2064 #define CMIC_CMCx_SBUSDMA_CH0_DESC_START_ADDRESS_HI_OFFSET(x) (0x3020 + (0x3000 * x)) 2065 #define CMIC_CMC0_SBUSDMA_CH0_DESC_START_ADDRESS_LO_OFFSET (0x301c) 2066 #define CMIC_CMC1_SBUSDMA_CH0_DESC_START_ADDRESS_LO_OFFSET (0x601c) 2067 #define CMIC_CMCx_SBUSDMA_CH0_DESC_START_ADDRESS_LO_OFFSET(x) (0x301c + (0x3000 * x)) 2068 #define CMIC_CMC0_SBUSDMA_CH0_ECC_CONTROL_OFFSET (0x3064) 2069 #define CMIC_CMC1_SBUSDMA_CH0_ECC_CONTROL_OFFSET (0x6064) 2070 #define CMIC_CMCx_SBUSDMA_CH0_ECC_CONTROL_OFFSET(x) (0x3064 + (0x3000 * x)) 2071 #define CMIC_CMC0_SBUSDMA_CH0_ECC_STATUS_OFFSET (0x3068) 2072 #define CMIC_CMC1_SBUSDMA_CH0_ECC_STATUS_OFFSET (0x6068) 2073 #define CMIC_CMCx_SBUSDMA_CH0_ECC_STATUS_OFFSET(x) (0x3068 + (0x3000 * x)) 2074 #define CMIC_CMC0_SBUSDMA_CH0_ECC_STATUS_CLR_OFFSET (0x306c) 2075 #define CMIC_CMC1_SBUSDMA_CH0_ECC_STATUS_CLR_OFFSET (0x606c) 2076 #define CMIC_CMCx_SBUSDMA_CH0_ECC_STATUS_CLR_OFFSET(x) (0x306c + (0x3000 * x)) 2077 #define CMIC_CMC0_SBUSDMA_CH0_HOSTMEM_START_ADDRESS_HI_OFFSET (0x3018) 2078 #define CMIC_CMC1_SBUSDMA_CH0_HOSTMEM_START_ADDRESS_HI_OFFSET (0x6018) 2079 #define CMIC_CMCx_SBUSDMA_CH0_HOSTMEM_START_ADDRESS_HI_OFFSET(x) (0x3018 + (0x3000 * x)) 2080 #define CMIC_CMC0_SBUSDMA_CH0_HOSTMEM_START_ADDRESS_LO_OFFSET (0x3014) 2081 #define CMIC_CMC1_SBUSDMA_CH0_HOSTMEM_START_ADDRESS_LO_OFFSET (0x6014) 2082 #define CMIC_CMCx_SBUSDMA_CH0_HOSTMEM_START_ADDRESS_LO_OFFSET(x) (0x3014 + (0x3000 * x)) 2083 #define CMIC_CMC0_SBUSDMA_CH0_ITER_COUNT_OFFSET (0x3074) 2084 #define CMIC_CMC1_SBUSDMA_CH0_ITER_COUNT_OFFSET (0x6074) 2085 #define CMIC_CMCx_SBUSDMA_CH0_ITER_COUNT_OFFSET(x) (0x3074 + (0x3000 * x)) 2086 #define CMIC_CMC0_SBUSDMA_CH0_OPCODE_OFFSET (0x300c) 2087 #define CMIC_CMC1_SBUSDMA_CH0_OPCODE_OFFSET (0x600c) 2088 #define CMIC_CMCx_SBUSDMA_CH0_OPCODE_OFFSET(x) (0x300c + (0x3000 * x)) 2089 #define CMIC_CMC0_SBUSDMA_CH0_REQUEST_OFFSET (0x3004) 2090 #define CMIC_CMC1_SBUSDMA_CH0_REQUEST_OFFSET (0x6004) 2091 #define CMIC_CMCx_SBUSDMA_CH0_REQUEST_OFFSET(x) (0x3004 + (0x3000 * x)) 2092 #define CMIC_CMC0_SBUSDMA_CH0_SBUSDMA_DEBUG_OFFSET (0x3054) 2093 #define CMIC_CMC1_SBUSDMA_CH0_SBUSDMA_DEBUG_OFFSET (0x6054) 2094 #define CMIC_CMCx_SBUSDMA_CH0_SBUSDMA_DEBUG_OFFSET(x) (0x3054 + (0x3000 * x)) 2095 #define CMIC_CMC0_SBUSDMA_CH0_SBUSDMA_DEBUG_CLR_OFFSET (0x3058) 2096 #define CMIC_CMC1_SBUSDMA_CH0_SBUSDMA_DEBUG_CLR_OFFSET (0x6058) 2097 #define CMIC_CMCx_SBUSDMA_CH0_SBUSDMA_DEBUG_CLR_OFFSET(x) (0x3058 + (0x3000 * x)) 2098 #define CMIC_CMC0_SBUSDMA_CH0_SBUSDMA_ECCERR_ADDRESS_HI_OFFSET (0x3060) 2099 #define CMIC_CMC1_SBUSDMA_CH0_SBUSDMA_ECCERR_ADDRESS_HI_OFFSET (0x6060) 2100 #define CMIC_CMCx_SBUSDMA_CH0_SBUSDMA_ECCERR_ADDRESS_HI_OFFSET(x) (0x3060 + (0x3000 * x)) 2101 #define CMIC_CMC0_SBUSDMA_CH0_SBUSDMA_ECCERR_ADDRESS_LO_OFFSET (0x305c) 2102 #define CMIC_CMC1_SBUSDMA_CH0_SBUSDMA_ECCERR_ADDRESS_LO_OFFSET (0x605c) 2103 #define CMIC_CMCx_SBUSDMA_CH0_SBUSDMA_ECCERR_ADDRESS_LO_OFFSET(x) (0x305c + (0x3000 * x)) 2104 #define CMIC_CMC0_SBUSDMA_CH0_SBUS_START_ADDRESS_OFFSET (0x3010) 2105 #define CMIC_CMC1_SBUSDMA_CH0_SBUS_START_ADDRESS_OFFSET (0x6010) 2106 #define CMIC_CMCx_SBUSDMA_CH0_SBUS_START_ADDRESS_OFFSET(x) (0x3010 + (0x3000 * x)) 2107 #define CMIC_CMC0_SBUSDMA_CH0_STATUS_OFFSET (0x3024) 2108 #define CMIC_CMC1_SBUSDMA_CH0_STATUS_OFFSET (0x6024) 2109 #define CMIC_CMCx_SBUSDMA_CH0_STATUS_OFFSET(x) (0x3024 + (0x3000 * x)) 2110 #define CMIC_CMC0_SBUSDMA_CH0_TIMER_OFFSET (0x3070) 2111 #define CMIC_CMC1_SBUSDMA_CH0_TIMER_OFFSET (0x6070) 2112 #define CMIC_CMCx_SBUSDMA_CH0_TIMER_OFFSET(x) (0x3070 + (0x3000 * x)) 2113 #define CMIC_CMC0_SBUSDMA_CH0_TM_CONTROL_OFFSET (0x3078) 2114 #define CMIC_CMC1_SBUSDMA_CH0_TM_CONTROL_OFFSET (0x6078) 2115 #define CMIC_CMCx_SBUSDMA_CH0_TM_CONTROL_OFFSET(x) (0x3078 + (0x3000 * x)) 2116 #define CMIC_CMC0_SBUSDMA_CH1_CONTROL_OFFSET (0x3100) 2117 #define CMIC_CMC1_SBUSDMA_CH1_CONTROL_OFFSET (0x6100) 2118 #define CMIC_CMCx_SBUSDMA_CH1_CONTROL_OFFSET(x) (0x3100 + (0x3000 * x)) 2119 #define CMIC_CMC0_SBUSDMA_CH1_COUNT_OFFSET (0x3108) 2120 #define CMIC_CMC1_SBUSDMA_CH1_COUNT_OFFSET (0x6108) 2121 #define CMIC_CMCx_SBUSDMA_CH1_COUNT_OFFSET(x) (0x3108 + (0x3000 * x)) 2122 #define CMIC_CMC0_SBUSDMA_CH1_CUR_DESC_ADDRESS_HI_OFFSET (0x3138) 2123 #define CMIC_CMC1_SBUSDMA_CH1_CUR_DESC_ADDRESS_HI_OFFSET (0x6138) 2124 #define CMIC_CMCx_SBUSDMA_CH1_CUR_DESC_ADDRESS_HI_OFFSET(x) (0x3138 + (0x3000 * x)) 2125 #define CMIC_CMC0_SBUSDMA_CH1_CUR_DESC_ADDRESS_LO_OFFSET (0x3134) 2126 #define CMIC_CMC1_SBUSDMA_CH1_CUR_DESC_ADDRESS_LO_OFFSET (0x6134) 2127 #define CMIC_CMCx_SBUSDMA_CH1_CUR_DESC_ADDRESS_LO_OFFSET(x) (0x3134 + (0x3000 * x)) 2128 #define CMIC_CMC0_SBUSDMA_CH1_CUR_HOSTMEM_ADDRESS_HI_OFFSET (0x312c) 2129 #define CMIC_CMC1_SBUSDMA_CH1_CUR_HOSTMEM_ADDRESS_HI_OFFSET (0x612c) 2130 #define CMIC_CMCx_SBUSDMA_CH1_CUR_HOSTMEM_ADDRESS_HI_OFFSET(x) (0x312c + (0x3000 * x)) 2131 #define CMIC_CMC0_SBUSDMA_CH1_CUR_HOSTMEM_ADDRESS_LO_OFFSET (0x3128) 2132 #define CMIC_CMC1_SBUSDMA_CH1_CUR_HOSTMEM_ADDRESS_LO_OFFSET (0x6128) 2133 #define CMIC_CMCx_SBUSDMA_CH1_CUR_HOSTMEM_ADDRESS_LO_OFFSET(x) (0x3128 + (0x3000 * x)) 2134 #define CMIC_CMC0_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_COUNT_OFFSET (0x3150) 2135 #define CMIC_CMC1_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_COUNT_OFFSET (0x6150) 2136 #define CMIC_CMCx_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_COUNT_OFFSET(x) (0x3150 + (0x3000 * x)) 2137 #define CMIC_CMC0_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_HI_OFFSET (0x314c) 2138 #define CMIC_CMC1_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_HI_OFFSET (0x614c) 2139 #define CMIC_CMCx_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_HI_OFFSET(x) (0x314c + (0x3000 * x)) 2140 #define CMIC_CMC0_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_LO_OFFSET (0x3148) 2141 #define CMIC_CMC1_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_LO_OFFSET (0x6148) 2142 #define CMIC_CMCx_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_LO_OFFSET(x) (0x3148 + (0x3000 * x)) 2143 #define CMIC_CMC0_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_OPCODE_OFFSET (0x3140) 2144 #define CMIC_CMC1_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_OPCODE_OFFSET (0x6140) 2145 #define CMIC_CMCx_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_OPCODE_OFFSET(x) (0x3140 + (0x3000 * x)) 2146 #define CMIC_CMC0_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_REQUEST_OFFSET (0x313c) 2147 #define CMIC_CMC1_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_REQUEST_OFFSET (0x613c) 2148 #define CMIC_CMCx_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_REQUEST_OFFSET(x) (0x313c + (0x3000 * x)) 2149 #define CMIC_CMC0_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_SBUS_START_ADDRESS_OFFSET (0x3144) 2150 #define CMIC_CMC1_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_SBUS_START_ADDRESS_OFFSET (0x6144) 2151 #define CMIC_CMCx_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_SBUS_START_ADDRESS_OFFSET(x) (0x3144 + (0x3000 * x)) 2152 #define CMIC_CMC0_SBUSDMA_CH1_CUR_SBUS_ADDRESS_OFFSET (0x3130) 2153 #define CMIC_CMC1_SBUSDMA_CH1_CUR_SBUS_ADDRESS_OFFSET (0x6130) 2154 #define CMIC_CMCx_SBUSDMA_CH1_CUR_SBUS_ADDRESS_OFFSET(x) (0x3130 + (0x3000 * x)) 2155 #define CMIC_CMC0_SBUSDMA_CH1_DESC_START_ADDRESS_HI_OFFSET (0x3120) 2156 #define CMIC_CMC1_SBUSDMA_CH1_DESC_START_ADDRESS_HI_OFFSET (0x6120) 2157 #define CMIC_CMCx_SBUSDMA_CH1_DESC_START_ADDRESS_HI_OFFSET(x) (0x3120 + (0x3000 * x)) 2158 #define CMIC_CMC0_SBUSDMA_CH1_DESC_START_ADDRESS_LO_OFFSET (0x311c) 2159 #define CMIC_CMC1_SBUSDMA_CH1_DESC_START_ADDRESS_LO_OFFSET (0x611c) 2160 #define CMIC_CMCx_SBUSDMA_CH1_DESC_START_ADDRESS_LO_OFFSET(x) (0x311c + (0x3000 * x)) 2161 #define CMIC_CMC0_SBUSDMA_CH1_ECC_CONTROL_OFFSET (0x3164) 2162 #define CMIC_CMC1_SBUSDMA_CH1_ECC_CONTROL_OFFSET (0x6164) 2163 #define CMIC_CMCx_SBUSDMA_CH1_ECC_CONTROL_OFFSET(x) (0x3164 + (0x3000 * x)) 2164 #define CMIC_CMC0_SBUSDMA_CH1_ECC_STATUS_OFFSET (0x3168) 2165 #define CMIC_CMC1_SBUSDMA_CH1_ECC_STATUS_OFFSET (0x6168) 2166 #define CMIC_CMCx_SBUSDMA_CH1_ECC_STATUS_OFFSET(x) (0x3168 + (0x3000 * x)) 2167 #define CMIC_CMC0_SBUSDMA_CH1_ECC_STATUS_CLR_OFFSET (0x316c) 2168 #define CMIC_CMC1_SBUSDMA_CH1_ECC_STATUS_CLR_OFFSET (0x616c) 2169 #define CMIC_CMCx_SBUSDMA_CH1_ECC_STATUS_CLR_OFFSET(x) (0x316c + (0x3000 * x)) 2170 #define CMIC_CMC0_SBUSDMA_CH1_HOSTMEM_START_ADDRESS_HI_OFFSET (0x3118) 2171 #define CMIC_CMC1_SBUSDMA_CH1_HOSTMEM_START_ADDRESS_HI_OFFSET (0x6118) 2172 #define CMIC_CMCx_SBUSDMA_CH1_HOSTMEM_START_ADDRESS_HI_OFFSET(x) (0x3118 + (0x3000 * x)) 2173 #define CMIC_CMC0_SBUSDMA_CH1_HOSTMEM_START_ADDRESS_LO_OFFSET (0x3114) 2174 #define CMIC_CMC1_SBUSDMA_CH1_HOSTMEM_START_ADDRESS_LO_OFFSET (0x6114) 2175 #define CMIC_CMCx_SBUSDMA_CH1_HOSTMEM_START_ADDRESS_LO_OFFSET(x) (0x3114 + (0x3000 * x)) 2176 #define CMIC_CMC0_SBUSDMA_CH1_ITER_COUNT_OFFSET (0x3174) 2177 #define CMIC_CMC1_SBUSDMA_CH1_ITER_COUNT_OFFSET (0x6174) 2178 #define CMIC_CMCx_SBUSDMA_CH1_ITER_COUNT_OFFSET(x) (0x3174 + (0x3000 * x)) 2179 #define CMIC_CMC0_SBUSDMA_CH1_OPCODE_OFFSET (0x310c) 2180 #define CMIC_CMC1_SBUSDMA_CH1_OPCODE_OFFSET (0x610c) 2181 #define CMIC_CMCx_SBUSDMA_CH1_OPCODE_OFFSET(x) (0x310c + (0x3000 * x)) 2182 #define CMIC_CMC0_SBUSDMA_CH1_REQUEST_OFFSET (0x3104) 2183 #define CMIC_CMC1_SBUSDMA_CH1_REQUEST_OFFSET (0x6104) 2184 #define CMIC_CMCx_SBUSDMA_CH1_REQUEST_OFFSET(x) (0x3104 + (0x3000 * x)) 2185 #define CMIC_CMC0_SBUSDMA_CH1_SBUSDMA_DEBUG_OFFSET (0x3154) 2186 #define CMIC_CMC1_SBUSDMA_CH1_SBUSDMA_DEBUG_OFFSET (0x6154) 2187 #define CMIC_CMCx_SBUSDMA_CH1_SBUSDMA_DEBUG_OFFSET(x) (0x3154 + (0x3000 * x)) 2188 #define CMIC_CMC0_SBUSDMA_CH1_SBUSDMA_DEBUG_CLR_OFFSET (0x3158) 2189 #define CMIC_CMC1_SBUSDMA_CH1_SBUSDMA_DEBUG_CLR_OFFSET (0x6158) 2190 #define CMIC_CMCx_SBUSDMA_CH1_SBUSDMA_DEBUG_CLR_OFFSET(x) (0x3158 + (0x3000 * x)) 2191 #define CMIC_CMC0_SBUSDMA_CH1_SBUSDMA_ECCERR_ADDRESS_HI_OFFSET (0x3160) 2192 #define CMIC_CMC1_SBUSDMA_CH1_SBUSDMA_ECCERR_ADDRESS_HI_OFFSET (0x6160) 2193 #define CMIC_CMCx_SBUSDMA_CH1_SBUSDMA_ECCERR_ADDRESS_HI_OFFSET(x) (0x3160 + (0x3000 * x)) 2194 #define CMIC_CMC0_SBUSDMA_CH1_SBUSDMA_ECCERR_ADDRESS_LO_OFFSET (0x315c) 2195 #define CMIC_CMC1_SBUSDMA_CH1_SBUSDMA_ECCERR_ADDRESS_LO_OFFSET (0x615c) 2196 #define CMIC_CMCx_SBUSDMA_CH1_SBUSDMA_ECCERR_ADDRESS_LO_OFFSET(x) (0x315c + (0x3000 * x)) 2197 #define CMIC_CMC0_SBUSDMA_CH1_SBUS_START_ADDRESS_OFFSET (0x3110) 2198 #define CMIC_CMC1_SBUSDMA_CH1_SBUS_START_ADDRESS_OFFSET (0x6110) 2199 #define CMIC_CMCx_SBUSDMA_CH1_SBUS_START_ADDRESS_OFFSET(x) (0x3110 + (0x3000 * x)) 2200 #define CMIC_CMC0_SBUSDMA_CH1_STATUS_OFFSET (0x3124) 2201 #define CMIC_CMC1_SBUSDMA_CH1_STATUS_OFFSET (0x6124) 2202 #define CMIC_CMCx_SBUSDMA_CH1_STATUS_OFFSET(x) (0x3124 + (0x3000 * x)) 2203 #define CMIC_CMC0_SBUSDMA_CH1_TIMER_OFFSET (0x3170) 2204 #define CMIC_CMC1_SBUSDMA_CH1_TIMER_OFFSET (0x6170) 2205 #define CMIC_CMCx_SBUSDMA_CH1_TIMER_OFFSET(x) (0x3170 + (0x3000 * x)) 2206 #define CMIC_CMC0_SBUSDMA_CH1_TM_CONTROL_OFFSET (0x3178) 2207 #define CMIC_CMC1_SBUSDMA_CH1_TM_CONTROL_OFFSET (0x6178) 2208 #define CMIC_CMCx_SBUSDMA_CH1_TM_CONTROL_OFFSET(x) (0x3178 + (0x3000 * x)) 2209 #define CMIC_CMC0_SBUSDMA_CH2_CONTROL_OFFSET (0x3200) 2210 #define CMIC_CMC1_SBUSDMA_CH2_CONTROL_OFFSET (0x6200) 2211 #define CMIC_CMCx_SBUSDMA_CH2_CONTROL_OFFSET(x) (0x3200 + (0x3000 * x)) 2212 #define CMIC_CMC0_SBUSDMA_CH2_COUNT_OFFSET (0x3208) 2213 #define CMIC_CMC1_SBUSDMA_CH2_COUNT_OFFSET (0x6208) 2214 #define CMIC_CMCx_SBUSDMA_CH2_COUNT_OFFSET(x) (0x3208 + (0x3000 * x)) 2215 #define CMIC_CMC0_SBUSDMA_CH2_CUR_DESC_ADDRESS_HI_OFFSET (0x3238) 2216 #define CMIC_CMC1_SBUSDMA_CH2_CUR_DESC_ADDRESS_HI_OFFSET (0x6238) 2217 #define CMIC_CMCx_SBUSDMA_CH2_CUR_DESC_ADDRESS_HI_OFFSET(x) (0x3238 + (0x3000 * x)) 2218 #define CMIC_CMC0_SBUSDMA_CH2_CUR_DESC_ADDRESS_LO_OFFSET (0x3234) 2219 #define CMIC_CMC1_SBUSDMA_CH2_CUR_DESC_ADDRESS_LO_OFFSET (0x6234) 2220 #define CMIC_CMCx_SBUSDMA_CH2_CUR_DESC_ADDRESS_LO_OFFSET(x) (0x3234 + (0x3000 * x)) 2221 #define CMIC_CMC0_SBUSDMA_CH2_CUR_HOSTMEM_ADDRESS_HI_OFFSET (0x322c) 2222 #define CMIC_CMC1_SBUSDMA_CH2_CUR_HOSTMEM_ADDRESS_HI_OFFSET (0x622c) 2223 #define CMIC_CMCx_SBUSDMA_CH2_CUR_HOSTMEM_ADDRESS_HI_OFFSET(x) (0x322c + (0x3000 * x)) 2224 #define CMIC_CMC0_SBUSDMA_CH2_CUR_HOSTMEM_ADDRESS_LO_OFFSET (0x3228) 2225 #define CMIC_CMC1_SBUSDMA_CH2_CUR_HOSTMEM_ADDRESS_LO_OFFSET (0x6228) 2226 #define CMIC_CMCx_SBUSDMA_CH2_CUR_HOSTMEM_ADDRESS_LO_OFFSET(x) (0x3228 + (0x3000 * x)) 2227 #define CMIC_CMC0_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_COUNT_OFFSET (0x3250) 2228 #define CMIC_CMC1_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_COUNT_OFFSET (0x6250) 2229 #define CMIC_CMCx_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_COUNT_OFFSET(x) (0x3250 + (0x3000 * x)) 2230 #define CMIC_CMC0_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_HI_OFFSET (0x324c) 2231 #define CMIC_CMC1_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_HI_OFFSET (0x624c) 2232 #define CMIC_CMCx_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_HI_OFFSET(x) (0x324c + (0x3000 * x)) 2233 #define CMIC_CMC0_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_LO_OFFSET (0x3248) 2234 #define CMIC_CMC1_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_LO_OFFSET (0x6248) 2235 #define CMIC_CMCx_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_LO_OFFSET(x) (0x3248 + (0x3000 * x)) 2236 #define CMIC_CMC0_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_OPCODE_OFFSET (0x3240) 2237 #define CMIC_CMC1_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_OPCODE_OFFSET (0x6240) 2238 #define CMIC_CMCx_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_OPCODE_OFFSET(x) (0x3240 + (0x3000 * x)) 2239 #define CMIC_CMC0_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_REQUEST_OFFSET (0x323c) 2240 #define CMIC_CMC1_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_REQUEST_OFFSET (0x623c) 2241 #define CMIC_CMCx_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_REQUEST_OFFSET(x) (0x323c + (0x3000 * x)) 2242 #define CMIC_CMC0_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_SBUS_START_ADDRESS_OFFSET (0x3244) 2243 #define CMIC_CMC1_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_SBUS_START_ADDRESS_OFFSET (0x6244) 2244 #define CMIC_CMCx_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_SBUS_START_ADDRESS_OFFSET(x) (0x3244 + (0x3000 * x)) 2245 #define CMIC_CMC0_SBUSDMA_CH2_CUR_SBUS_ADDRESS_OFFSET (0x3230) 2246 #define CMIC_CMC1_SBUSDMA_CH2_CUR_SBUS_ADDRESS_OFFSET (0x6230) 2247 #define CMIC_CMCx_SBUSDMA_CH2_CUR_SBUS_ADDRESS_OFFSET(x) (0x3230 + (0x3000 * x)) 2248 #define CMIC_CMC0_SBUSDMA_CH2_DESC_START_ADDRESS_HI_OFFSET (0x3220) 2249 #define CMIC_CMC1_SBUSDMA_CH2_DESC_START_ADDRESS_HI_OFFSET (0x6220) 2250 #define CMIC_CMCx_SBUSDMA_CH2_DESC_START_ADDRESS_HI_OFFSET(x) (0x3220 + (0x3000 * x)) 2251 #define CMIC_CMC0_SBUSDMA_CH2_DESC_START_ADDRESS_LO_OFFSET (0x321c) 2252 #define CMIC_CMC1_SBUSDMA_CH2_DESC_START_ADDRESS_LO_OFFSET (0x621c) 2253 #define CMIC_CMCx_SBUSDMA_CH2_DESC_START_ADDRESS_LO_OFFSET(x) (0x321c + (0x3000 * x)) 2254 #define CMIC_CMC0_SBUSDMA_CH2_ECC_CONTROL_OFFSET (0x3264) 2255 #define CMIC_CMC1_SBUSDMA_CH2_ECC_CONTROL_OFFSET (0x6264) 2256 #define CMIC_CMCx_SBUSDMA_CH2_ECC_CONTROL_OFFSET(x) (0x3264 + (0x3000 * x)) 2257 #define CMIC_CMC0_SBUSDMA_CH2_ECC_STATUS_OFFSET (0x3268) 2258 #define CMIC_CMC1_SBUSDMA_CH2_ECC_STATUS_OFFSET (0x6268) 2259 #define CMIC_CMCx_SBUSDMA_CH2_ECC_STATUS_OFFSET(x) (0x3268 + (0x3000 * x)) 2260 #define CMIC_CMC0_SBUSDMA_CH2_ECC_STATUS_CLR_OFFSET (0x326c) 2261 #define CMIC_CMC1_SBUSDMA_CH2_ECC_STATUS_CLR_OFFSET (0x626c) 2262 #define CMIC_CMCx_SBUSDMA_CH2_ECC_STATUS_CLR_OFFSET(x) (0x326c + (0x3000 * x)) 2263 #define CMIC_CMC0_SBUSDMA_CH2_HOSTMEM_START_ADDRESS_HI_OFFSET (0x3218) 2264 #define CMIC_CMC1_SBUSDMA_CH2_HOSTMEM_START_ADDRESS_HI_OFFSET (0x6218) 2265 #define CMIC_CMCx_SBUSDMA_CH2_HOSTMEM_START_ADDRESS_HI_OFFSET(x) (0x3218 + (0x3000 * x)) 2266 #define CMIC_CMC0_SBUSDMA_CH2_HOSTMEM_START_ADDRESS_LO_OFFSET (0x3214) 2267 #define CMIC_CMC1_SBUSDMA_CH2_HOSTMEM_START_ADDRESS_LO_OFFSET (0x6214) 2268 #define CMIC_CMCx_SBUSDMA_CH2_HOSTMEM_START_ADDRESS_LO_OFFSET(x) (0x3214 + (0x3000 * x)) 2269 #define CMIC_CMC0_SBUSDMA_CH2_ITER_COUNT_OFFSET (0x3274) 2270 #define CMIC_CMC1_SBUSDMA_CH2_ITER_COUNT_OFFSET (0x6274) 2271 #define CMIC_CMCx_SBUSDMA_CH2_ITER_COUNT_OFFSET(x) (0x3274 + (0x3000 * x)) 2272 #define CMIC_CMC0_SBUSDMA_CH2_OPCODE_OFFSET (0x320c) 2273 #define CMIC_CMC1_SBUSDMA_CH2_OPCODE_OFFSET (0x620c) 2274 #define CMIC_CMCx_SBUSDMA_CH2_OPCODE_OFFSET(x) (0x320c + (0x3000 * x)) 2275 #define CMIC_CMC0_SBUSDMA_CH2_REQUEST_OFFSET (0x3204) 2276 #define CMIC_CMC1_SBUSDMA_CH2_REQUEST_OFFSET (0x6204) 2277 #define CMIC_CMCx_SBUSDMA_CH2_REQUEST_OFFSET(x) (0x3204 + (0x3000 * x)) 2278 #define CMIC_CMC0_SBUSDMA_CH2_SBUSDMA_DEBUG_OFFSET (0x3254) 2279 #define CMIC_CMC1_SBUSDMA_CH2_SBUSDMA_DEBUG_OFFSET (0x6254) 2280 #define CMIC_CMCx_SBUSDMA_CH2_SBUSDMA_DEBUG_OFFSET(x) (0x3254 + (0x3000 * x)) 2281 #define CMIC_CMC0_SBUSDMA_CH2_SBUSDMA_DEBUG_CLR_OFFSET (0x3258) 2282 #define CMIC_CMC1_SBUSDMA_CH2_SBUSDMA_DEBUG_CLR_OFFSET (0x6258) 2283 #define CMIC_CMCx_SBUSDMA_CH2_SBUSDMA_DEBUG_CLR_OFFSET(x) (0x3258 + (0x3000 * x)) 2284 #define CMIC_CMC0_SBUSDMA_CH2_SBUSDMA_ECCERR_ADDRESS_HI_OFFSET (0x3260) 2285 #define CMIC_CMC1_SBUSDMA_CH2_SBUSDMA_ECCERR_ADDRESS_HI_OFFSET (0x6260) 2286 #define CMIC_CMCx_SBUSDMA_CH2_SBUSDMA_ECCERR_ADDRESS_HI_OFFSET(x) (0x3260 + (0x3000 * x)) 2287 #define CMIC_CMC0_SBUSDMA_CH2_SBUSDMA_ECCERR_ADDRESS_LO_OFFSET (0x325c) 2288 #define CMIC_CMC1_SBUSDMA_CH2_SBUSDMA_ECCERR_ADDRESS_LO_OFFSET (0x625c) 2289 #define CMIC_CMCx_SBUSDMA_CH2_SBUSDMA_ECCERR_ADDRESS_LO_OFFSET(x) (0x325c + (0x3000 * x)) 2290 #define CMIC_CMC0_SBUSDMA_CH2_SBUS_START_ADDRESS_OFFSET (0x3210) 2291 #define CMIC_CMC1_SBUSDMA_CH2_SBUS_START_ADDRESS_OFFSET (0x6210) 2292 #define CMIC_CMCx_SBUSDMA_CH2_SBUS_START_ADDRESS_OFFSET(x) (0x3210 + (0x3000 * x)) 2293 #define CMIC_CMC0_SBUSDMA_CH2_STATUS_OFFSET (0x3224) 2294 #define CMIC_CMC1_SBUSDMA_CH2_STATUS_OFFSET (0x6224) 2295 #define CMIC_CMCx_SBUSDMA_CH2_STATUS_OFFSET(x) (0x3224 + (0x3000 * x)) 2296 #define CMIC_CMC0_SBUSDMA_CH2_TIMER_OFFSET (0x3270) 2297 #define CMIC_CMC1_SBUSDMA_CH2_TIMER_OFFSET (0x6270) 2298 #define CMIC_CMCx_SBUSDMA_CH2_TIMER_OFFSET(x) (0x3270 + (0x3000 * x)) 2299 #define CMIC_CMC0_SBUSDMA_CH2_TM_CONTROL_OFFSET (0x3278) 2300 #define CMIC_CMC1_SBUSDMA_CH2_TM_CONTROL_OFFSET (0x6278) 2301 #define CMIC_CMCx_SBUSDMA_CH2_TM_CONTROL_OFFSET(x) (0x3278 + (0x3000 * x)) 2302 #define CMIC_CMC0_SBUSDMA_CH3_CONTROL_OFFSET (0x3300) 2303 #define CMIC_CMC1_SBUSDMA_CH3_CONTROL_OFFSET (0x6300) 2304 #define CMIC_CMCx_SBUSDMA_CH3_CONTROL_OFFSET(x) (0x3300 + (0x3000 * x)) 2305 #define CMIC_CMC0_SBUSDMA_CH3_COUNT_OFFSET (0x3308) 2306 #define CMIC_CMC1_SBUSDMA_CH3_COUNT_OFFSET (0x6308) 2307 #define CMIC_CMCx_SBUSDMA_CH3_COUNT_OFFSET(x) (0x3308 + (0x3000 * x)) 2308 #define CMIC_CMC0_SBUSDMA_CH3_CUR_DESC_ADDRESS_HI_OFFSET (0x3338) 2309 #define CMIC_CMC1_SBUSDMA_CH3_CUR_DESC_ADDRESS_HI_OFFSET (0x6338) 2310 #define CMIC_CMCx_SBUSDMA_CH3_CUR_DESC_ADDRESS_HI_OFFSET(x) (0x3338 + (0x3000 * x)) 2311 #define CMIC_CMC0_SBUSDMA_CH3_CUR_DESC_ADDRESS_LO_OFFSET (0x3334) 2312 #define CMIC_CMC1_SBUSDMA_CH3_CUR_DESC_ADDRESS_LO_OFFSET (0x6334) 2313 #define CMIC_CMCx_SBUSDMA_CH3_CUR_DESC_ADDRESS_LO_OFFSET(x) (0x3334 + (0x3000 * x)) 2314 #define CMIC_CMC0_SBUSDMA_CH3_CUR_HOSTMEM_ADDRESS_HI_OFFSET (0x332c) 2315 #define CMIC_CMC1_SBUSDMA_CH3_CUR_HOSTMEM_ADDRESS_HI_OFFSET (0x632c) 2316 #define CMIC_CMCx_SBUSDMA_CH3_CUR_HOSTMEM_ADDRESS_HI_OFFSET(x) (0x332c + (0x3000 * x)) 2317 #define CMIC_CMC0_SBUSDMA_CH3_CUR_HOSTMEM_ADDRESS_LO_OFFSET (0x3328) 2318 #define CMIC_CMC1_SBUSDMA_CH3_CUR_HOSTMEM_ADDRESS_LO_OFFSET (0x6328) 2319 #define CMIC_CMCx_SBUSDMA_CH3_CUR_HOSTMEM_ADDRESS_LO_OFFSET(x) (0x3328 + (0x3000 * x)) 2320 #define CMIC_CMC0_SBUSDMA_CH3_CUR_SBUSDMA_CONFIG_COUNT_OFFSET (0x3350) 2321 #define CMIC_CMC1_SBUSDMA_CH3_CUR_SBUSDMA_CONFIG_COUNT_OFFSET (0x6350) 2322 #define CMIC_CMCx_SBUSDMA_CH3_CUR_SBUSDMA_CONFIG_COUNT_OFFSET(x) (0x3350 + (0x3000 * x)) 2323 #define CMIC_CMC0_SBUSDMA_CH3_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_HI_OFFSET (0x334c) 2324 #define CMIC_CMC1_SBUSDMA_CH3_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_HI_OFFSET (0x634c) 2325 #define CMIC_CMCx_SBUSDMA_CH3_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_HI_OFFSET(x) (0x334c + (0x3000 * x)) 2326 #define CMIC_CMC0_SBUSDMA_CH3_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_LO_OFFSET (0x3348) 2327 #define CMIC_CMC1_SBUSDMA_CH3_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_LO_OFFSET (0x6348) 2328 #define CMIC_CMCx_SBUSDMA_CH3_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_LO_OFFSET(x) (0x3348 + (0x3000 * x)) 2329 #define CMIC_CMC0_SBUSDMA_CH3_CUR_SBUSDMA_CONFIG_OPCODE_OFFSET (0x3340) 2330 #define CMIC_CMC1_SBUSDMA_CH3_CUR_SBUSDMA_CONFIG_OPCODE_OFFSET (0x6340) 2331 #define CMIC_CMCx_SBUSDMA_CH3_CUR_SBUSDMA_CONFIG_OPCODE_OFFSET(x) (0x3340 + (0x3000 * x)) 2332 #define CMIC_CMC0_SBUSDMA_CH3_CUR_SBUSDMA_CONFIG_REQUEST_OFFSET (0x333c) 2333 #define CMIC_CMC1_SBUSDMA_CH3_CUR_SBUSDMA_CONFIG_REQUEST_OFFSET (0x633c) 2334 #define CMIC_CMCx_SBUSDMA_CH3_CUR_SBUSDMA_CONFIG_REQUEST_OFFSET(x) (0x333c + (0x3000 * x)) 2335 #define CMIC_CMC0_SBUSDMA_CH3_CUR_SBUSDMA_CONFIG_SBUS_START_ADDRESS_OFFSET (0x3344) 2336 #define CMIC_CMC1_SBUSDMA_CH3_CUR_SBUSDMA_CONFIG_SBUS_START_ADDRESS_OFFSET (0x6344) 2337 #define CMIC_CMCx_SBUSDMA_CH3_CUR_SBUSDMA_CONFIG_SBUS_START_ADDRESS_OFFSET(x) (0x3344 + (0x3000 * x)) 2338 #define CMIC_CMC0_SBUSDMA_CH3_CUR_SBUS_ADDRESS_OFFSET (0x3330) 2339 #define CMIC_CMC1_SBUSDMA_CH3_CUR_SBUS_ADDRESS_OFFSET (0x6330) 2340 #define CMIC_CMCx_SBUSDMA_CH3_CUR_SBUS_ADDRESS_OFFSET(x) (0x3330 + (0x3000 * x)) 2341 #define CMIC_CMC0_SBUSDMA_CH3_DESC_START_ADDRESS_HI_OFFSET (0x3320) 2342 #define CMIC_CMC1_SBUSDMA_CH3_DESC_START_ADDRESS_HI_OFFSET (0x6320) 2343 #define CMIC_CMCx_SBUSDMA_CH3_DESC_START_ADDRESS_HI_OFFSET(x) (0x3320 + (0x3000 * x)) 2344 #define CMIC_CMC0_SBUSDMA_CH3_DESC_START_ADDRESS_LO_OFFSET (0x331c) 2345 #define CMIC_CMC1_SBUSDMA_CH3_DESC_START_ADDRESS_LO_OFFSET (0x631c) 2346 #define CMIC_CMCx_SBUSDMA_CH3_DESC_START_ADDRESS_LO_OFFSET(x) (0x331c + (0x3000 * x)) 2347 #define CMIC_CMC0_SBUSDMA_CH3_ECC_CONTROL_OFFSET (0x3364) 2348 #define CMIC_CMC1_SBUSDMA_CH3_ECC_CONTROL_OFFSET (0x6364) 2349 #define CMIC_CMCx_SBUSDMA_CH3_ECC_CONTROL_OFFSET(x) (0x3364 + (0x3000 * x)) 2350 #define CMIC_CMC0_SBUSDMA_CH3_ECC_STATUS_OFFSET (0x3368) 2351 #define CMIC_CMC1_SBUSDMA_CH3_ECC_STATUS_OFFSET (0x6368) 2352 #define CMIC_CMCx_SBUSDMA_CH3_ECC_STATUS_OFFSET(x) (0x3368 + (0x3000 * x)) 2353 #define CMIC_CMC0_SBUSDMA_CH3_ECC_STATUS_CLR_OFFSET (0x336c) 2354 #define CMIC_CMC1_SBUSDMA_CH3_ECC_STATUS_CLR_OFFSET (0x636c) 2355 #define CMIC_CMCx_SBUSDMA_CH3_ECC_STATUS_CLR_OFFSET(x) (0x336c + (0x3000 * x)) 2356 #define CMIC_CMC0_SBUSDMA_CH3_HOSTMEM_START_ADDRESS_HI_OFFSET (0x3318) 2357 #define CMIC_CMC1_SBUSDMA_CH3_HOSTMEM_START_ADDRESS_HI_OFFSET (0x6318) 2358 #define CMIC_CMCx_SBUSDMA_CH3_HOSTMEM_START_ADDRESS_HI_OFFSET(x) (0x3318 + (0x3000 * x)) 2359 #define CMIC_CMC0_SBUSDMA_CH3_HOSTMEM_START_ADDRESS_LO_OFFSET (0x3314) 2360 #define CMIC_CMC1_SBUSDMA_CH3_HOSTMEM_START_ADDRESS_LO_OFFSET (0x6314) 2361 #define CMIC_CMCx_SBUSDMA_CH3_HOSTMEM_START_ADDRESS_LO_OFFSET(x) (0x3314 + (0x3000 * x)) 2362 #define CMIC_CMC0_SBUSDMA_CH3_ITER_COUNT_OFFSET (0x3374) 2363 #define CMIC_CMC1_SBUSDMA_CH3_ITER_COUNT_OFFSET (0x6374) 2364 #define CMIC_CMCx_SBUSDMA_CH3_ITER_COUNT_OFFSET(x) (0x3374 + (0x3000 * x)) 2365 #define CMIC_CMC0_SBUSDMA_CH3_OPCODE_OFFSET (0x330c) 2366 #define CMIC_CMC1_SBUSDMA_CH3_OPCODE_OFFSET (0x630c) 2367 #define CMIC_CMCx_SBUSDMA_CH3_OPCODE_OFFSET(x) (0x330c + (0x3000 * x)) 2368 #define CMIC_CMC0_SBUSDMA_CH3_REQUEST_OFFSET (0x3304) 2369 #define CMIC_CMC1_SBUSDMA_CH3_REQUEST_OFFSET (0x6304) 2370 #define CMIC_CMCx_SBUSDMA_CH3_REQUEST_OFFSET(x) (0x3304 + (0x3000 * x)) 2371 #define CMIC_CMC0_SBUSDMA_CH3_SBUSDMA_DEBUG_OFFSET (0x3354) 2372 #define CMIC_CMC1_SBUSDMA_CH3_SBUSDMA_DEBUG_OFFSET (0x6354) 2373 #define CMIC_CMCx_SBUSDMA_CH3_SBUSDMA_DEBUG_OFFSET(x) (0x3354 + (0x3000 * x)) 2374 #define CMIC_CMC0_SBUSDMA_CH3_SBUSDMA_DEBUG_CLR_OFFSET (0x3358) 2375 #define CMIC_CMC1_SBUSDMA_CH3_SBUSDMA_DEBUG_CLR_OFFSET (0x6358) 2376 #define CMIC_CMCx_SBUSDMA_CH3_SBUSDMA_DEBUG_CLR_OFFSET(x) (0x3358 + (0x3000 * x)) 2377 #define CMIC_CMC0_SBUSDMA_CH3_SBUSDMA_ECCERR_ADDRESS_HI_OFFSET (0x3360) 2378 #define CMIC_CMC1_SBUSDMA_CH3_SBUSDMA_ECCERR_ADDRESS_HI_OFFSET (0x6360) 2379 #define CMIC_CMCx_SBUSDMA_CH3_SBUSDMA_ECCERR_ADDRESS_HI_OFFSET(x) (0x3360 + (0x3000 * x)) 2380 #define CMIC_CMC0_SBUSDMA_CH3_SBUSDMA_ECCERR_ADDRESS_LO_OFFSET (0x335c) 2381 #define CMIC_CMC1_SBUSDMA_CH3_SBUSDMA_ECCERR_ADDRESS_LO_OFFSET (0x635c) 2382 #define CMIC_CMCx_SBUSDMA_CH3_SBUSDMA_ECCERR_ADDRESS_LO_OFFSET(x) (0x335c + (0x3000 * x)) 2383 #define CMIC_CMC0_SBUSDMA_CH3_SBUS_START_ADDRESS_OFFSET (0x3310) 2384 #define CMIC_CMC1_SBUSDMA_CH3_SBUS_START_ADDRESS_OFFSET (0x6310) 2385 #define CMIC_CMCx_SBUSDMA_CH3_SBUS_START_ADDRESS_OFFSET(x) (0x3310 + (0x3000 * x)) 2386 #define CMIC_CMC0_SBUSDMA_CH3_STATUS_OFFSET (0x3324) 2387 #define CMIC_CMC1_SBUSDMA_CH3_STATUS_OFFSET (0x6324) 2388 #define CMIC_CMCx_SBUSDMA_CH3_STATUS_OFFSET(x) (0x3324 + (0x3000 * x)) 2389 #define CMIC_CMC0_SBUSDMA_CH3_TIMER_OFFSET (0x3370) 2390 #define CMIC_CMC1_SBUSDMA_CH3_TIMER_OFFSET (0x6370) 2391 #define CMIC_CMCx_SBUSDMA_CH3_TIMER_OFFSET(x) (0x3370 + (0x3000 * x)) 2392 #define CMIC_CMC0_SBUSDMA_CH3_TM_CONTROL_OFFSET (0x3378) 2393 #define CMIC_CMC1_SBUSDMA_CH3_TM_CONTROL_OFFSET (0x6378) 2394 #define CMIC_CMCx_SBUSDMA_CH3_TM_CONTROL_OFFSET(x) (0x3378 + (0x3000 * x)) 2395 #define CMIC_CMC0_SHARED_1BIT_ECC_ERROR_STATUS_OFFSET (0x1064) 2396 #define CMIC_CMC1_SHARED_1BIT_ECC_ERROR_STATUS_OFFSET (0x4064) 2397 #define CMIC_CMCx_SHARED_1BIT_ECC_ERROR_STATUS_OFFSET(x) (0x1064 + (0x3000 * x)) 2398 #define CMIC_CMC0_SHARED_1BIT_ECC_ERROR_STATUS_ENABLE_OFFSET (0x1068) 2399 #define CMIC_CMC1_SHARED_1BIT_ECC_ERROR_STATUS_ENABLE_OFFSET (0x4068) 2400 #define CMIC_CMCx_SHARED_1BIT_ECC_ERROR_STATUS_ENABLE_OFFSET(x) (0x1068 + (0x3000 * x)) 2401 #define CMIC_CMC0_SHARED_2BIT_ECC_ERROR_STATUS_OFFSET (0x105c) 2402 #define CMIC_CMC1_SHARED_2BIT_ECC_ERROR_STATUS_OFFSET (0x405c) 2403 #define CMIC_CMCx_SHARED_2BIT_ECC_ERROR_STATUS_OFFSET(x) (0x105c + (0x3000 * x)) 2404 #define CMIC_CMC0_SHARED_2BIT_ECC_ERROR_STATUS_ENABLE_OFFSET (0x1060) 2405 #define CMIC_CMC1_SHARED_2BIT_ECC_ERROR_STATUS_ENABLE_OFFSET (0x4060) 2406 #define CMIC_CMCx_SHARED_2BIT_ECC_ERROR_STATUS_ENABLE_OFFSET(x) (0x1060 + (0x3000 * x)) 2407 #define CMIC_CMC0_SHARED_AXI_AR_COUNT_SPLIT_TX_OFFSET (0x1098) 2408 #define CMIC_CMC1_SHARED_AXI_AR_COUNT_SPLIT_TX_OFFSET (0x4098) 2409 #define CMIC_CMCx_SHARED_AXI_AR_COUNT_SPLIT_TX_OFFSET(x) (0x1098 + (0x3000 * x)) 2410 #define CMIC_CMC0_SHARED_AXI_AR_COUNT_TX_OFFSET (0x1094) 2411 #define CMIC_CMC1_SHARED_AXI_AR_COUNT_TX_OFFSET (0x4094) 2412 #define CMIC_CMCx_SHARED_AXI_AR_COUNT_TX_OFFSET(x) (0x1094 + (0x3000 * x)) 2413 #define CMIC_CMC0_SHARED_AXI_PER_ID_STAT_OFFSET (0x1080) 2414 #define CMIC_CMC1_SHARED_AXI_PER_ID_STAT_OFFSET (0x4080) 2415 #define CMIC_CMCx_SHARED_AXI_PER_ID_STAT_OFFSET(x) (0x1080 + (0x3000 * x)) 2416 #define CMIC_CMC0_SHARED_AXI_STAT_OFFSET (0x107c) 2417 #define CMIC_CMC1_SHARED_AXI_STAT_OFFSET (0x407c) 2418 #define CMIC_CMCx_SHARED_AXI_STAT_OFFSET(x) (0x107c + (0x3000 * x)) 2419 #define CMIC_CMC0_SHARED_CCMDMA_READ_ARB_CTRL_OFFSET (0x1034) 2420 #define CMIC_CMC1_SHARED_CCMDMA_READ_ARB_CTRL_OFFSET (0x4034) 2421 #define CMIC_CMCx_SHARED_CCMDMA_READ_ARB_CTRL_OFFSET(x) (0x1034 + (0x3000 * x)) 2422 #define CMIC_CMC0_SHARED_CCMDMA_READ_AXI_MAP_CTRL_OFFSET (0x102c) 2423 #define CMIC_CMC1_SHARED_CCMDMA_READ_AXI_MAP_CTRL_OFFSET (0x402c) 2424 #define CMIC_CMCx_SHARED_CCMDMA_READ_AXI_MAP_CTRL_OFFSET(x) (0x102c + (0x3000 * x)) 2425 #define CMIC_CMC0_SHARED_CCMDMA_WRITE_ARB_CTRL_OFFSET (0x1038) 2426 #define CMIC_CMC1_SHARED_CCMDMA_WRITE_ARB_CTRL_OFFSET (0x4038) 2427 #define CMIC_CMCx_SHARED_CCMDMA_WRITE_ARB_CTRL_OFFSET(x) (0x1038 + (0x3000 * x)) 2428 #define CMIC_CMC0_SHARED_CCMDMA_WRITE_AXI_MAP_CTRL_OFFSET (0x1030) 2429 #define CMIC_CMC1_SHARED_CCMDMA_WRITE_AXI_MAP_CTRL_OFFSET (0x4030) 2430 #define CMIC_CMCx_SHARED_CCMDMA_WRITE_AXI_MAP_CTRL_OFFSET(x) (0x1030 + (0x3000 * x)) 2431 #define CMIC_CMC0_SHARED_COMPLETION_BUF_ECC_CONTROL_OFFSET (0x1048) 2432 #define CMIC_CMC1_SHARED_COMPLETION_BUF_ECC_CONTROL_OFFSET (0x4048) 2433 #define CMIC_CMCx_SHARED_COMPLETION_BUF_ECC_CONTROL_OFFSET(x) (0x1048 + (0x3000 * x)) 2434 #define CMIC_CMC0_SHARED_COMPLETION_BUF_ECC_STATUS_OFFSET (0x1044) 2435 #define CMIC_CMC1_SHARED_COMPLETION_BUF_ECC_STATUS_OFFSET (0x4044) 2436 #define CMIC_CMCx_SHARED_COMPLETION_BUF_ECC_STATUS_OFFSET(x) (0x1044 + (0x3000 * x)) 2437 #define CMIC_CMC0_SHARED_COMPLETION_BUF_MAX_FLIST_ENTRIES_OFFSET (0x103c) 2438 #define CMIC_CMC1_SHARED_COMPLETION_BUF_MAX_FLIST_ENTRIES_OFFSET (0x403c) 2439 #define CMIC_CMCx_SHARED_COMPLETION_BUF_MAX_FLIST_ENTRIES_OFFSET(x) (0x103c + (0x3000 * x)) 2440 #define CMIC_CMC0_SHARED_COMPLETION_BUF_STATUS_NUM_FREE_ENTRIES_OFFSET (0x1040) 2441 #define CMIC_CMC1_SHARED_COMPLETION_BUF_STATUS_NUM_FREE_ENTRIES_OFFSET (0x4040) 2442 #define CMIC_CMCx_SHARED_COMPLETION_BUF_STATUS_NUM_FREE_ENTRIES_OFFSET(x) (0x1040 + (0x3000 * x)) 2443 #define CMIC_CMC0_SHARED_COMPLETION_BUF_TM_CONTROL_OFFSET (0x104c) 2444 #define CMIC_CMC1_SHARED_COMPLETION_BUF_TM_CONTROL_OFFSET (0x404c) 2445 #define CMIC_CMCx_SHARED_COMPLETION_BUF_TM_CONTROL_OFFSET(x) (0x104c + (0x3000 * x)) 2446 #define CMIC_CMC0_SHARED_CONFIG_OFFSET (0x1078) 2447 #define CMIC_CMC1_SHARED_CONFIG_OFFSET (0x4078) 2448 #define CMIC_CMCx_SHARED_CONFIG_OFFSET(x) (0x1078 + (0x3000 * x)) 2449 #define CMIC_CMC0_SHARED_DMA_MASTER_READ_PER_ID_OUTSTD_TRANS_LIMIT_OFFSET (0x1004) 2450 #define CMIC_CMC1_SHARED_DMA_MASTER_READ_PER_ID_OUTSTD_TRANS_LIMIT_OFFSET (0x4004) 2451 #define CMIC_CMCx_SHARED_DMA_MASTER_READ_PER_ID_OUTSTD_TRANS_LIMIT_OFFSET(x) (0x1004 + (0x3000 * x)) 2452 #define CMIC_CMC0_SHARED_DMA_MASTER_TOTAL_OUTSTD_TRANS_LIMIT_OFFSET (0x1000) 2453 #define CMIC_CMC1_SHARED_DMA_MASTER_TOTAL_OUTSTD_TRANS_LIMIT_OFFSET (0x4000) 2454 #define CMIC_CMCx_SHARED_DMA_MASTER_TOTAL_OUTSTD_TRANS_LIMIT_OFFSET(x) (0x1000 + (0x3000 * x)) 2455 #define CMIC_CMC0_SHARED_IRQ_STAT0_OFFSET (0x106c) 2456 #define CMIC_CMC1_SHARED_IRQ_STAT0_OFFSET (0x406c) 2457 #define CMIC_CMCx_SHARED_IRQ_STAT0_OFFSET(x) (0x106c + (0x3000 * x)) 2458 #define CMIC_CMC0_SHARED_IRQ_STAT1_OFFSET (0x1070) 2459 #define CMIC_CMC1_SHARED_IRQ_STAT1_OFFSET (0x4070) 2460 #define CMIC_CMCx_SHARED_IRQ_STAT1_OFFSET(x) (0x1070 + (0x3000 * x)) 2461 #define CMIC_CMC0_SHARED_IRQ_STAT_CLR0_OFFSET (0x1074) 2462 #define CMIC_CMC1_SHARED_IRQ_STAT_CLR0_OFFSET (0x4074) 2463 #define CMIC_CMCx_SHARED_IRQ_STAT_CLR0_OFFSET(x) (0x1074 + (0x3000 * x)) 2464 #define CMIC_CMC0_SHARED_PACKET_DMA_READ_ARB_CTRL_OFFSET (0x1014) 2465 #define CMIC_CMC1_SHARED_PACKET_DMA_READ_ARB_CTRL_OFFSET (0x4014) 2466 #define CMIC_CMCx_SHARED_PACKET_DMA_READ_ARB_CTRL_OFFSET(x) (0x1014 + (0x3000 * x)) 2467 #define CMIC_CMC0_SHARED_PACKET_DMA_READ_AXI_MAP_CTRL_OFFSET (0x1008) 2468 #define CMIC_CMC1_SHARED_PACKET_DMA_READ_AXI_MAP_CTRL_OFFSET (0x4008) 2469 #define CMIC_CMCx_SHARED_PACKET_DMA_READ_AXI_MAP_CTRL_OFFSET(x) (0x1008 + (0x3000 * x)) 2470 #define CMIC_CMC0_SHARED_PACKET_DMA_WRITE_ARB_CTRL_OFFSET (0x1018) 2471 #define CMIC_CMC1_SHARED_PACKET_DMA_WRITE_ARB_CTRL_OFFSET (0x4018) 2472 #define CMIC_CMCx_SHARED_PACKET_DMA_WRITE_ARB_CTRL_OFFSET(x) (0x1018 + (0x3000 * x)) 2473 #define CMIC_CMC0_SHARED_PACKET_DMA_WRITE_AXI_MAP_CTRL0_OFFSET (0x100c) 2474 #define CMIC_CMC1_SHARED_PACKET_DMA_WRITE_AXI_MAP_CTRL0_OFFSET (0x400c) 2475 #define CMIC_CMCx_SHARED_PACKET_DMA_WRITE_AXI_MAP_CTRL0_OFFSET(x) (0x100c + (0x3000 * x)) 2476 #define CMIC_CMC0_SHARED_PACKET_DMA_WRITE_AXI_MAP_CTRL1_OFFSET (0x1010) 2477 #define CMIC_CMC1_SHARED_PACKET_DMA_WRITE_AXI_MAP_CTRL1_OFFSET (0x4010) 2478 #define CMIC_CMCx_SHARED_PACKET_DMA_WRITE_AXI_MAP_CTRL1_OFFSET(x) (0x1010 + (0x3000 * x)) 2479 #define CMIC_CMC0_SHARED_PKT_COUNT_RXPKT_OFFSET (0x1084) 2480 #define CMIC_CMC1_SHARED_PKT_COUNT_RXPKT_OFFSET (0x4084) 2481 #define CMIC_CMCx_SHARED_PKT_COUNT_RXPKT_OFFSET(x) (0x1084 + (0x3000 * x)) 2482 #define CMIC_CMC0_SHARED_PKT_COUNT_RXPKT_ERR_OFFSET (0x1088) 2483 #define CMIC_CMC1_SHARED_PKT_COUNT_RXPKT_ERR_OFFSET (0x4088) 2484 #define CMIC_CMCx_SHARED_PKT_COUNT_RXPKT_ERR_OFFSET(x) (0x1088 + (0x3000 * x)) 2485 #define CMIC_CMC0_SHARED_PKT_COUNT_TXPKT_OFFSET (0x108c) 2486 #define CMIC_CMC1_SHARED_PKT_COUNT_TXPKT_OFFSET (0x408c) 2487 #define CMIC_CMCx_SHARED_PKT_COUNT_TXPKT_OFFSET(x) (0x108c + (0x3000 * x)) 2488 #define CMIC_CMC0_SHARED_PKT_COUNT_TXPKT_ERR_OFFSET (0x1090) 2489 #define CMIC_CMC1_SHARED_PKT_COUNT_TXPKT_ERR_OFFSET (0x4090) 2490 #define CMIC_CMCx_SHARED_PKT_COUNT_TXPKT_ERR_OFFSET(x) (0x1090 + (0x3000 * x)) 2491 #define CMIC_CMC0_SHARED_PROGRAMMABLE_COS_MASK0_OFFSET (0x1050) 2492 #define CMIC_CMC1_SHARED_PROGRAMMABLE_COS_MASK0_OFFSET (0x4050) 2493 #define CMIC_CMCx_SHARED_PROGRAMMABLE_COS_MASK0_OFFSET(x) (0x1050 + (0x3000 * x)) 2494 #define CMIC_CMC0_SHARED_PROGRAMMABLE_COS_MASK1_OFFSET (0x1054) 2495 #define CMIC_CMC1_SHARED_PROGRAMMABLE_COS_MASK1_OFFSET (0x4054) 2496 #define CMIC_CMCx_SHARED_PROGRAMMABLE_COS_MASK1_OFFSET(x) (0x1054 + (0x3000 * x)) 2497 #define CMIC_CMC0_SHARED_RXBUF_BLOCK_DATABUF_ALLOC_OFFSET (0x2088) 2498 #define CMIC_CMC1_SHARED_RXBUF_BLOCK_DATABUF_ALLOC_OFFSET (0x5088) 2499 #define CMIC_CMCx_SHARED_RXBUF_BLOCK_DATABUF_ALLOC_OFFSET(x) (0x2088 + (0x3000 * x)) 2500 #define CMIC_CMC0_SHARED_RXBUF_CONFIG_OFFSET (0x208c) 2501 #define CMIC_CMC1_SHARED_RXBUF_CONFIG_OFFSET (0x508c) 2502 #define CMIC_CMCx_SHARED_RXBUF_CONFIG_OFFSET(x) (0x208c + (0x3000 * x)) 2503 #define CMIC_CMC0_SHARED_RXBUF_DATABUF_MAX_FLIST_ENTRIES_OFFSET (0x2080) 2504 #define CMIC_CMC1_SHARED_RXBUF_DATABUF_MAX_FLIST_ENTRIES_OFFSET (0x5080) 2505 #define CMIC_CMCx_SHARED_RXBUF_DATABUF_MAX_FLIST_ENTRIES_OFFSET(x) (0x2080 + (0x3000 * x)) 2506 #define CMIC_CMC0_SHARED_RXBUF_DATABUF_NUM_FREE_ENTRIES_OFFSET (0x2084) 2507 #define CMIC_CMC1_SHARED_RXBUF_DATABUF_NUM_FREE_ENTRIES_OFFSET (0x5084) 2508 #define CMIC_CMCx_SHARED_RXBUF_DATABUF_NUM_FREE_ENTRIES_OFFSET(x) (0x2084 + (0x3000 * x)) 2509 #define CMIC_CMC0_SHARED_RXBUF_ECC_CONTROL_OFFSET (0x2090) 2510 #define CMIC_CMC1_SHARED_RXBUF_ECC_CONTROL_OFFSET (0x5090) 2511 #define CMIC_CMCx_SHARED_RXBUF_ECC_CONTROL_OFFSET(x) (0x2090 + (0x3000 * x)) 2512 #define CMIC_CMC0_SHARED_RXBUF_ECC_STATUS_OFFSET (0x2098) 2513 #define CMIC_CMC1_SHARED_RXBUF_ECC_STATUS_OFFSET (0x5098) 2514 #define CMIC_CMCx_SHARED_RXBUF_ECC_STATUS_OFFSET(x) (0x2098 + (0x3000 * x)) 2515 #define CMIC_CMC0_SHARED_RXBUF_ECC_STATUS_CLR_OFFSET (0x209c) 2516 #define CMIC_CMC1_SHARED_RXBUF_ECC_STATUS_CLR_OFFSET (0x509c) 2517 #define CMIC_CMCx_SHARED_RXBUF_ECC_STATUS_CLR_OFFSET(x) (0x209c + (0x3000 * x)) 2518 #define CMIC_CMC0_SHARED_RXBUF_THRESHOLD_CONFIG_OFFSET (0x1058) 2519 #define CMIC_CMC1_SHARED_RXBUF_THRESHOLD_CONFIG_OFFSET (0x4058) 2520 #define CMIC_CMCx_SHARED_RXBUF_THRESHOLD_CONFIG_OFFSET(x) (0x1058 + (0x3000 * x)) 2521 #define CMIC_CMC0_SHARED_RXBUF_TM_CONTROL_OFFSET (0x2094) 2522 #define CMIC_CMC1_SHARED_RXBUF_TM_CONTROL_OFFSET (0x5094) 2523 #define CMIC_CMCx_SHARED_RXBUF_TM_CONTROL_OFFSET(x) (0x2094 + (0x3000 * x)) 2524 #define CMIC_CMC0_SHARED_SBUS_DMA_READ_ARB_CTRL_OFFSET (0x1024) 2525 #define CMIC_CMC1_SHARED_SBUS_DMA_READ_ARB_CTRL_OFFSET (0x4024) 2526 #define CMIC_CMCx_SHARED_SBUS_DMA_READ_ARB_CTRL_OFFSET(x) (0x1024 + (0x3000 * x)) 2527 #define CMIC_CMC0_SHARED_SBUS_DMA_READ_AXI_MAP_CTRL_OFFSET (0x101c) 2528 #define CMIC_CMC1_SHARED_SBUS_DMA_READ_AXI_MAP_CTRL_OFFSET (0x401c) 2529 #define CMIC_CMCx_SHARED_SBUS_DMA_READ_AXI_MAP_CTRL_OFFSET(x) (0x101c + (0x3000 * x)) 2530 #define CMIC_CMC0_SHARED_SBUS_DMA_WRITE_ARB_CTRL_OFFSET (0x1028) 2531 #define CMIC_CMC1_SHARED_SBUS_DMA_WRITE_ARB_CTRL_OFFSET (0x4028) 2532 #define CMIC_CMCx_SHARED_SBUS_DMA_WRITE_ARB_CTRL_OFFSET(x) (0x1028 + (0x3000 * x)) 2533 #define CMIC_CMC0_SHARED_SBUS_DMA_WRITE_AXI_MAP_CTRL_OFFSET (0x1020) 2534 #define CMIC_CMC1_SHARED_SBUS_DMA_WRITE_AXI_MAP_CTRL_OFFSET (0x4020) 2535 #define CMIC_CMCx_SHARED_SBUS_DMA_WRITE_AXI_MAP_CTRL_OFFSET(x) (0x1020 + (0x3000 * x)) 2536 #define CMIC_CMC0_SHARED_TXBUF_DATABUF_MAX_FLIST_ENTRIES_OFFSET (0x2028) 2537 #define CMIC_CMC1_SHARED_TXBUF_DATABUF_MAX_FLIST_ENTRIES_OFFSET (0x5028) 2538 #define CMIC_CMCx_SHARED_TXBUF_DATABUF_MAX_FLIST_ENTRIES_OFFSET(x) (0x2028 + (0x3000 * x)) 2539 #define CMIC_CMC0_SHARED_TXBUF_DATABUF_NUM_FREE_ENTRIES_OFFSET (0x2024) 2540 #define CMIC_CMC1_SHARED_TXBUF_DATABUF_NUM_FREE_ENTRIES_OFFSET (0x5024) 2541 #define CMIC_CMCx_SHARED_TXBUF_DATABUF_NUM_FREE_ENTRIES_OFFSET(x) (0x2024 + (0x3000 * x)) 2542 #define CMIC_CMC0_SHARED_TXBUF_DEBUG_OFFSET (0x2020) 2543 #define CMIC_CMC1_SHARED_TXBUF_DEBUG_OFFSET (0x5020) 2544 #define CMIC_CMCx_SHARED_TXBUF_DEBUG_OFFSET(x) (0x2020 + (0x3000 * x)) 2545 #define CMIC_CMC0_SHARED_TXBUF_ECC_CONTROL_OFFSET (0x2034) 2546 #define CMIC_CMC1_SHARED_TXBUF_ECC_CONTROL_OFFSET (0x5034) 2547 #define CMIC_CMCx_SHARED_TXBUF_ECC_CONTROL_OFFSET(x) (0x2034 + (0x3000 * x)) 2548 #define CMIC_CMC0_SHARED_TXBUF_ECC_STATUS_OFFSET (0x202c) 2549 #define CMIC_CMC1_SHARED_TXBUF_ECC_STATUS_OFFSET (0x502c) 2550 #define CMIC_CMCx_SHARED_TXBUF_ECC_STATUS_OFFSET(x) (0x202c + (0x3000 * x)) 2551 #define CMIC_CMC0_SHARED_TXBUF_ECC_STATUS_CLR_OFFSET (0x2030) 2552 #define CMIC_CMC1_SHARED_TXBUF_ECC_STATUS_CLR_OFFSET (0x5030) 2553 #define CMIC_CMCx_SHARED_TXBUF_ECC_STATUS_CLR_OFFSET(x) (0x2030 + (0x3000 * x)) 2554 #define CMIC_CMC0_SHARED_TXBUF_MAX_BUF_LIMITS_OFFSET (0x2000) 2555 #define CMIC_CMC1_SHARED_TXBUF_MAX_BUF_LIMITS_OFFSET (0x5000) 2556 #define CMIC_CMCx_SHARED_TXBUF_MAX_BUF_LIMITS_OFFSET(x) (0x2000 + (0x3000 * x)) 2557 #define CMIC_CMC0_SHARED_TXBUF_MIN_BUF_LIMITS_OFFSET (0x2004) 2558 #define CMIC_CMC1_SHARED_TXBUF_MIN_BUF_LIMITS_OFFSET (0x5004) 2559 #define CMIC_CMCx_SHARED_TXBUF_MIN_BUF_LIMITS_OFFSET(x) (0x2004 + (0x3000 * x)) 2560 #define CMIC_CMC0_SHARED_TXBUF_RD_THRESHOLD_CONFIG_OFFSET (0x2008) 2561 #define CMIC_CMC1_SHARED_TXBUF_RD_THRESHOLD_CONFIG_OFFSET (0x5008) 2562 #define CMIC_CMCx_SHARED_TXBUF_RD_THRESHOLD_CONFIG_OFFSET(x) (0x2008 + (0x3000 * x)) 2563 #define CMIC_CMC0_SHARED_TXBUF_RD_WRR_ARB_CTRL_OFFSET (0x200c) 2564 #define CMIC_CMC1_SHARED_TXBUF_RD_WRR_ARB_CTRL_OFFSET (0x500c) 2565 #define CMIC_CMCx_SHARED_TXBUF_RD_WRR_ARB_CTRL_OFFSET(x) (0x200c + (0x3000 * x)) 2566 #define CMIC_CMC0_SHARED_TXBUF_SLICE0_PKT_CNT_OFFSET (0x201c) 2567 #define CMIC_CMC1_SHARED_TXBUF_SLICE0_PKT_CNT_OFFSET (0x501c) 2568 #define CMIC_CMCx_SHARED_TXBUF_SLICE0_PKT_CNT_OFFSET(x) (0x201c + (0x3000 * x)) 2569 #define CMIC_CMC0_SHARED_TXBUF_SLICE1_PKT_CNT_OFFSET (0x2018) 2570 #define CMIC_CMC1_SHARED_TXBUF_SLICE1_PKT_CNT_OFFSET (0x5018) 2571 #define CMIC_CMCx_SHARED_TXBUF_SLICE1_PKT_CNT_OFFSET(x) (0x2018 + (0x3000 * x)) 2572 #define CMIC_CMC0_SHARED_TXBUF_SLICE2_PKT_CNT_OFFSET (0x2014) 2573 #define CMIC_CMC1_SHARED_TXBUF_SLICE2_PKT_CNT_OFFSET (0x5014) 2574 #define CMIC_CMCx_SHARED_TXBUF_SLICE2_PKT_CNT_OFFSET(x) (0x2014 + (0x3000 * x)) 2575 #define CMIC_CMC0_SHARED_TXBUF_SLICE3_PKT_CNT_OFFSET (0x2010) 2576 #define CMIC_CMC1_SHARED_TXBUF_SLICE3_PKT_CNT_OFFSET (0x5010) 2577 #define CMIC_CMCx_SHARED_TXBUF_SLICE3_PKT_CNT_OFFSET(x) (0x2010 + (0x3000 * x)) 2578 #define CMIC_CMC0_SHARED_TXBUF_TM_CONTROL_OFFSET (0x2038) 2579 #define CMIC_CMC1_SHARED_TXBUF_TM_CONTROL_OFFSET (0x5038) 2580 #define CMIC_CMCx_SHARED_TXBUF_TM_CONTROL_OFFSET(x) (0x2038 + (0x3000 * x)) 2581 #define CMIC_COMMON_POOL_FIFO_CH0_RD_DMA_CFG_OFFSET (0x11000) 2582 #define CMIC_COMMON_POOL_FIFO_CH0_RD_DMA_CFG_1_OFFSET (0x11004) 2583 #define CMIC_COMMON_POOL_FIFO_CH0_RD_DMA_CUR_HOSTMEM_WRITE_PTR_HI_OFFSET (0x11048) 2584 #define CMIC_COMMON_POOL_FIFO_CH0_RD_DMA_CUR_HOSTMEM_WRITE_PTR_LO_OFFSET (0x11044) 2585 #define CMIC_COMMON_POOL_FIFO_CH0_RD_DMA_ECCERR_ADDRESS_HI_OFFSET (0x11030) 2586 #define CMIC_COMMON_POOL_FIFO_CH0_RD_DMA_ECCERR_ADDRESS_LO_OFFSET (0x1102c) 2587 #define CMIC_COMMON_POOL_FIFO_CH0_RD_DMA_ECC_CONTROL_OFFSET (0x11034) 2588 #define CMIC_COMMON_POOL_FIFO_CH0_RD_DMA_ECC_STATUS_OFFSET (0x11038) 2589 #define CMIC_COMMON_POOL_FIFO_CH0_RD_DMA_ECC_STATUS_CLR_OFFSET (0x1103c) 2590 #define CMIC_COMMON_POOL_FIFO_CH0_RD_DMA_HOSTMEM_START_ADDRESS_HI_OFFSET (0x11010) 2591 #define CMIC_COMMON_POOL_FIFO_CH0_RD_DMA_HOSTMEM_START_ADDRESS_LO_OFFSET (0x1100c) 2592 #define CMIC_COMMON_POOL_FIFO_CH0_RD_DMA_HOSTMEM_THRESHOLD_OFFSET (0x1101c) 2593 #define CMIC_COMMON_POOL_FIFO_CH0_RD_DMA_NUM_OF_ENTRIES_READ_FRM_HOSTMEM_OFFSET (0x11014) 2594 #define CMIC_COMMON_POOL_FIFO_CH0_RD_DMA_NUM_OF_ENTRIES_VALID_IN_HOSTMEM_OFFSET (0x11018) 2595 #define CMIC_COMMON_POOL_FIFO_CH0_RD_DMA_OPCODE_OFFSET (0x11028) 2596 #define CMIC_COMMON_POOL_FIFO_CH0_RD_DMA_SBUS_START_ADDRESS_OFFSET (0x11008) 2597 #define CMIC_COMMON_POOL_FIFO_CH0_RD_DMA_STAT_OFFSET (0x11020) 2598 #define CMIC_COMMON_POOL_FIFO_CH0_RD_DMA_STAT_CLR_OFFSET (0x11024) 2599 #define CMIC_COMMON_POOL_FIFO_CH0_RD_DMA_TM_CONTROL_OFFSET (0x11040) 2600 #define CMIC_COMMON_POOL_FIFO_CH10_RD_DMA_CFG_OFFSET (0x11500) 2601 #define CMIC_COMMON_POOL_FIFO_CH10_RD_DMA_CFG_1_OFFSET (0x11504) 2602 #define CMIC_COMMON_POOL_FIFO_CH10_RD_DMA_CUR_HOSTMEM_WRITE_PTR_HI_OFFSET (0x11548) 2603 #define CMIC_COMMON_POOL_FIFO_CH10_RD_DMA_CUR_HOSTMEM_WRITE_PTR_LO_OFFSET (0x11544) 2604 #define CMIC_COMMON_POOL_FIFO_CH10_RD_DMA_ECCERR_ADDRESS_HI_OFFSET (0x11530) 2605 #define CMIC_COMMON_POOL_FIFO_CH10_RD_DMA_ECCERR_ADDRESS_LO_OFFSET (0x1152c) 2606 #define CMIC_COMMON_POOL_FIFO_CH10_RD_DMA_ECC_CONTROL_OFFSET (0x11534) 2607 #define CMIC_COMMON_POOL_FIFO_CH10_RD_DMA_ECC_STATUS_OFFSET (0x11538) 2608 #define CMIC_COMMON_POOL_FIFO_CH10_RD_DMA_ECC_STATUS_CLR_OFFSET (0x1153c) 2609 #define CMIC_COMMON_POOL_FIFO_CH10_RD_DMA_HOSTMEM_START_ADDRESS_HI_OFFSET (0x11510) 2610 #define CMIC_COMMON_POOL_FIFO_CH10_RD_DMA_HOSTMEM_START_ADDRESS_LO_OFFSET (0x1150c) 2611 #define CMIC_COMMON_POOL_FIFO_CH10_RD_DMA_HOSTMEM_THRESHOLD_OFFSET (0x1151c) 2612 #define CMIC_COMMON_POOL_FIFO_CH10_RD_DMA_NUM_OF_ENTRIES_READ_FRM_HOSTMEM_OFFSET (0x11514) 2613 #define CMIC_COMMON_POOL_FIFO_CH10_RD_DMA_NUM_OF_ENTRIES_VALID_IN_HOSTMEM_OFFSET (0x11518) 2614 #define CMIC_COMMON_POOL_FIFO_CH10_RD_DMA_OPCODE_OFFSET (0x11528) 2615 #define CMIC_COMMON_POOL_FIFO_CH10_RD_DMA_SBUS_START_ADDRESS_OFFSET (0x11508) 2616 #define CMIC_COMMON_POOL_FIFO_CH10_RD_DMA_STAT_OFFSET (0x11520) 2617 #define CMIC_COMMON_POOL_FIFO_CH10_RD_DMA_STAT_CLR_OFFSET (0x11524) 2618 #define CMIC_COMMON_POOL_FIFO_CH10_RD_DMA_TM_CONTROL_OFFSET (0x11540) 2619 #define CMIC_COMMON_POOL_FIFO_CH11_RD_DMA_CFG_OFFSET (0x11580) 2620 #define CMIC_COMMON_POOL_FIFO_CH11_RD_DMA_CFG_1_OFFSET (0x11584) 2621 #define CMIC_COMMON_POOL_FIFO_CH11_RD_DMA_CUR_HOSTMEM_WRITE_PTR_HI_OFFSET (0x115c8) 2622 #define CMIC_COMMON_POOL_FIFO_CH11_RD_DMA_CUR_HOSTMEM_WRITE_PTR_LO_OFFSET (0x115c4) 2623 #define CMIC_COMMON_POOL_FIFO_CH11_RD_DMA_ECCERR_ADDRESS_HI_OFFSET (0x115b0) 2624 #define CMIC_COMMON_POOL_FIFO_CH11_RD_DMA_ECCERR_ADDRESS_LO_OFFSET (0x115ac) 2625 #define CMIC_COMMON_POOL_FIFO_CH11_RD_DMA_ECC_CONTROL_OFFSET (0x115b4) 2626 #define CMIC_COMMON_POOL_FIFO_CH11_RD_DMA_ECC_STATUS_OFFSET (0x115b8) 2627 #define CMIC_COMMON_POOL_FIFO_CH11_RD_DMA_ECC_STATUS_CLR_OFFSET (0x115bc) 2628 #define CMIC_COMMON_POOL_FIFO_CH11_RD_DMA_HOSTMEM_START_ADDRESS_HI_OFFSET (0x11590) 2629 #define CMIC_COMMON_POOL_FIFO_CH11_RD_DMA_HOSTMEM_START_ADDRESS_LO_OFFSET (0x1158c) 2630 #define CMIC_COMMON_POOL_FIFO_CH11_RD_DMA_HOSTMEM_THRESHOLD_OFFSET (0x1159c) 2631 #define CMIC_COMMON_POOL_FIFO_CH11_RD_DMA_NUM_OF_ENTRIES_READ_FRM_HOSTMEM_OFFSET (0x11594) 2632 #define CMIC_COMMON_POOL_FIFO_CH11_RD_DMA_NUM_OF_ENTRIES_VALID_IN_HOSTMEM_OFFSET (0x11598) 2633 #define CMIC_COMMON_POOL_FIFO_CH11_RD_DMA_OPCODE_OFFSET (0x115a8) 2634 #define CMIC_COMMON_POOL_FIFO_CH11_RD_DMA_SBUS_START_ADDRESS_OFFSET (0x11588) 2635 #define CMIC_COMMON_POOL_FIFO_CH11_RD_DMA_STAT_OFFSET (0x115a0) 2636 #define CMIC_COMMON_POOL_FIFO_CH11_RD_DMA_STAT_CLR_OFFSET (0x115a4) 2637 #define CMIC_COMMON_POOL_FIFO_CH11_RD_DMA_TM_CONTROL_OFFSET (0x115c0) 2638 #define CMIC_COMMON_POOL_FIFO_CH1_RD_DMA_CFG_OFFSET (0x11080) 2639 #define CMIC_COMMON_POOL_FIFO_CH1_RD_DMA_CFG_1_OFFSET (0x11084) 2640 #define CMIC_COMMON_POOL_FIFO_CH1_RD_DMA_CUR_HOSTMEM_WRITE_PTR_HI_OFFSET (0x110c8) 2641 #define CMIC_COMMON_POOL_FIFO_CH1_RD_DMA_CUR_HOSTMEM_WRITE_PTR_LO_OFFSET (0x110c4) 2642 #define CMIC_COMMON_POOL_FIFO_CH1_RD_DMA_ECCERR_ADDRESS_HI_OFFSET (0x110b0) 2643 #define CMIC_COMMON_POOL_FIFO_CH1_RD_DMA_ECCERR_ADDRESS_LO_OFFSET (0x110ac) 2644 #define CMIC_COMMON_POOL_FIFO_CH1_RD_DMA_ECC_CONTROL_OFFSET (0x110b4) 2645 #define CMIC_COMMON_POOL_FIFO_CH1_RD_DMA_ECC_STATUS_OFFSET (0x110b8) 2646 #define CMIC_COMMON_POOL_FIFO_CH1_RD_DMA_ECC_STATUS_CLR_OFFSET (0x110bc) 2647 #define CMIC_COMMON_POOL_FIFO_CH1_RD_DMA_HOSTMEM_START_ADDRESS_HI_OFFSET (0x11090) 2648 #define CMIC_COMMON_POOL_FIFO_CH1_RD_DMA_HOSTMEM_START_ADDRESS_LO_OFFSET (0x1108c) 2649 #define CMIC_COMMON_POOL_FIFO_CH1_RD_DMA_HOSTMEM_THRESHOLD_OFFSET (0x1109c) 2650 #define CMIC_COMMON_POOL_FIFO_CH1_RD_DMA_NUM_OF_ENTRIES_READ_FRM_HOSTMEM_OFFSET (0x11094) 2651 #define CMIC_COMMON_POOL_FIFO_CH1_RD_DMA_NUM_OF_ENTRIES_VALID_IN_HOSTMEM_OFFSET (0x11098) 2652 #define CMIC_COMMON_POOL_FIFO_CH1_RD_DMA_OPCODE_OFFSET (0x110a8) 2653 #define CMIC_COMMON_POOL_FIFO_CH1_RD_DMA_SBUS_START_ADDRESS_OFFSET (0x11088) 2654 #define CMIC_COMMON_POOL_FIFO_CH1_RD_DMA_STAT_OFFSET (0x110a0) 2655 #define CMIC_COMMON_POOL_FIFO_CH1_RD_DMA_STAT_CLR_OFFSET (0x110a4) 2656 #define CMIC_COMMON_POOL_FIFO_CH1_RD_DMA_TM_CONTROL_OFFSET (0x110c0) 2657 #define CMIC_COMMON_POOL_FIFO_CH2_RD_DMA_CFG_OFFSET (0x11100) 2658 #define CMIC_COMMON_POOL_FIFO_CH2_RD_DMA_CFG_1_OFFSET (0x11104) 2659 #define CMIC_COMMON_POOL_FIFO_CH2_RD_DMA_CUR_HOSTMEM_WRITE_PTR_HI_OFFSET (0x11148) 2660 #define CMIC_COMMON_POOL_FIFO_CH2_RD_DMA_CUR_HOSTMEM_WRITE_PTR_LO_OFFSET (0x11144) 2661 #define CMIC_COMMON_POOL_FIFO_CH2_RD_DMA_ECCERR_ADDRESS_HI_OFFSET (0x11130) 2662 #define CMIC_COMMON_POOL_FIFO_CH2_RD_DMA_ECCERR_ADDRESS_LO_OFFSET (0x1112c) 2663 #define CMIC_COMMON_POOL_FIFO_CH2_RD_DMA_ECC_CONTROL_OFFSET (0x11134) 2664 #define CMIC_COMMON_POOL_FIFO_CH2_RD_DMA_ECC_STATUS_OFFSET (0x11138) 2665 #define CMIC_COMMON_POOL_FIFO_CH2_RD_DMA_ECC_STATUS_CLR_OFFSET (0x1113c) 2666 #define CMIC_COMMON_POOL_FIFO_CH2_RD_DMA_HOSTMEM_START_ADDRESS_HI_OFFSET (0x11110) 2667 #define CMIC_COMMON_POOL_FIFO_CH2_RD_DMA_HOSTMEM_START_ADDRESS_LO_OFFSET (0x1110c) 2668 #define CMIC_COMMON_POOL_FIFO_CH2_RD_DMA_HOSTMEM_THRESHOLD_OFFSET (0x1111c) 2669 #define CMIC_COMMON_POOL_FIFO_CH2_RD_DMA_NUM_OF_ENTRIES_READ_FRM_HOSTMEM_OFFSET (0x11114) 2670 #define CMIC_COMMON_POOL_FIFO_CH2_RD_DMA_NUM_OF_ENTRIES_VALID_IN_HOSTMEM_OFFSET (0x11118) 2671 #define CMIC_COMMON_POOL_FIFO_CH2_RD_DMA_OPCODE_OFFSET (0x11128) 2672 #define CMIC_COMMON_POOL_FIFO_CH2_RD_DMA_SBUS_START_ADDRESS_OFFSET (0x11108) 2673 #define CMIC_COMMON_POOL_FIFO_CH2_RD_DMA_STAT_OFFSET (0x11120) 2674 #define CMIC_COMMON_POOL_FIFO_CH2_RD_DMA_STAT_CLR_OFFSET (0x11124) 2675 #define CMIC_COMMON_POOL_FIFO_CH2_RD_DMA_TM_CONTROL_OFFSET (0x11140) 2676 #define CMIC_COMMON_POOL_FIFO_CH3_RD_DMA_CFG_OFFSET (0x11180) 2677 #define CMIC_COMMON_POOL_FIFO_CH3_RD_DMA_CFG_1_OFFSET (0x11184) 2678 #define CMIC_COMMON_POOL_FIFO_CH3_RD_DMA_CUR_HOSTMEM_WRITE_PTR_HI_OFFSET (0x111c8) 2679 #define CMIC_COMMON_POOL_FIFO_CH3_RD_DMA_CUR_HOSTMEM_WRITE_PTR_LO_OFFSET (0x111c4) 2680 #define CMIC_COMMON_POOL_FIFO_CH3_RD_DMA_ECCERR_ADDRESS_HI_OFFSET (0x111b0) 2681 #define CMIC_COMMON_POOL_FIFO_CH3_RD_DMA_ECCERR_ADDRESS_LO_OFFSET (0x111ac) 2682 #define CMIC_COMMON_POOL_FIFO_CH3_RD_DMA_ECC_CONTROL_OFFSET (0x111b4) 2683 #define CMIC_COMMON_POOL_FIFO_CH3_RD_DMA_ECC_STATUS_OFFSET (0x111b8) 2684 #define CMIC_COMMON_POOL_FIFO_CH3_RD_DMA_ECC_STATUS_CLR_OFFSET (0x111bc) 2685 #define CMIC_COMMON_POOL_FIFO_CH3_RD_DMA_HOSTMEM_START_ADDRESS_HI_OFFSET (0x11190) 2686 #define CMIC_COMMON_POOL_FIFO_CH3_RD_DMA_HOSTMEM_START_ADDRESS_LO_OFFSET (0x1118c) 2687 #define CMIC_COMMON_POOL_FIFO_CH3_RD_DMA_HOSTMEM_THRESHOLD_OFFSET (0x1119c) 2688 #define CMIC_COMMON_POOL_FIFO_CH3_RD_DMA_NUM_OF_ENTRIES_READ_FRM_HOSTMEM_OFFSET (0x11194) 2689 #define CMIC_COMMON_POOL_FIFO_CH3_RD_DMA_NUM_OF_ENTRIES_VALID_IN_HOSTMEM_OFFSET (0x11198) 2690 #define CMIC_COMMON_POOL_FIFO_CH3_RD_DMA_OPCODE_OFFSET (0x111a8) 2691 #define CMIC_COMMON_POOL_FIFO_CH3_RD_DMA_SBUS_START_ADDRESS_OFFSET (0x11188) 2692 #define CMIC_COMMON_POOL_FIFO_CH3_RD_DMA_STAT_OFFSET (0x111a0) 2693 #define CMIC_COMMON_POOL_FIFO_CH3_RD_DMA_STAT_CLR_OFFSET (0x111a4) 2694 #define CMIC_COMMON_POOL_FIFO_CH3_RD_DMA_TM_CONTROL_OFFSET (0x111c0) 2695 #define CMIC_COMMON_POOL_FIFO_CH4_RD_DMA_CFG_OFFSET (0x11200) 2696 #define CMIC_COMMON_POOL_FIFO_CH4_RD_DMA_CFG_1_OFFSET (0x11204) 2697 #define CMIC_COMMON_POOL_FIFO_CH4_RD_DMA_CUR_HOSTMEM_WRITE_PTR_HI_OFFSET (0x11248) 2698 #define CMIC_COMMON_POOL_FIFO_CH4_RD_DMA_CUR_HOSTMEM_WRITE_PTR_LO_OFFSET (0x11244) 2699 #define CMIC_COMMON_POOL_FIFO_CH4_RD_DMA_ECCERR_ADDRESS_HI_OFFSET (0x11230) 2700 #define CMIC_COMMON_POOL_FIFO_CH4_RD_DMA_ECCERR_ADDRESS_LO_OFFSET (0x1122c) 2701 #define CMIC_COMMON_POOL_FIFO_CH4_RD_DMA_ECC_CONTROL_OFFSET (0x11234) 2702 #define CMIC_COMMON_POOL_FIFO_CH4_RD_DMA_ECC_STATUS_OFFSET (0x11238) 2703 #define CMIC_COMMON_POOL_FIFO_CH4_RD_DMA_ECC_STATUS_CLR_OFFSET (0x1123c) 2704 #define CMIC_COMMON_POOL_FIFO_CH4_RD_DMA_HOSTMEM_START_ADDRESS_HI_OFFSET (0x11210) 2705 #define CMIC_COMMON_POOL_FIFO_CH4_RD_DMA_HOSTMEM_START_ADDRESS_LO_OFFSET (0x1120c) 2706 #define CMIC_COMMON_POOL_FIFO_CH4_RD_DMA_HOSTMEM_THRESHOLD_OFFSET (0x1121c) 2707 #define CMIC_COMMON_POOL_FIFO_CH4_RD_DMA_NUM_OF_ENTRIES_READ_FRM_HOSTMEM_OFFSET (0x11214) 2708 #define CMIC_COMMON_POOL_FIFO_CH4_RD_DMA_NUM_OF_ENTRIES_VALID_IN_HOSTMEM_OFFSET (0x11218) 2709 #define CMIC_COMMON_POOL_FIFO_CH4_RD_DMA_OPCODE_OFFSET (0x11228) 2710 #define CMIC_COMMON_POOL_FIFO_CH4_RD_DMA_SBUS_START_ADDRESS_OFFSET (0x11208) 2711 #define CMIC_COMMON_POOL_FIFO_CH4_RD_DMA_STAT_OFFSET (0x11220) 2712 #define CMIC_COMMON_POOL_FIFO_CH4_RD_DMA_STAT_CLR_OFFSET (0x11224) 2713 #define CMIC_COMMON_POOL_FIFO_CH4_RD_DMA_TM_CONTROL_OFFSET (0x11240) 2714 #define CMIC_COMMON_POOL_FIFO_CH5_RD_DMA_CFG_OFFSET (0x11280) 2715 #define CMIC_COMMON_POOL_FIFO_CH5_RD_DMA_CFG_1_OFFSET (0x11284) 2716 #define CMIC_COMMON_POOL_FIFO_CH5_RD_DMA_CUR_HOSTMEM_WRITE_PTR_HI_OFFSET (0x112c8) 2717 #define CMIC_COMMON_POOL_FIFO_CH5_RD_DMA_CUR_HOSTMEM_WRITE_PTR_LO_OFFSET (0x112c4) 2718 #define CMIC_COMMON_POOL_FIFO_CH5_RD_DMA_ECCERR_ADDRESS_HI_OFFSET (0x112b0) 2719 #define CMIC_COMMON_POOL_FIFO_CH5_RD_DMA_ECCERR_ADDRESS_LO_OFFSET (0x112ac) 2720 #define CMIC_COMMON_POOL_FIFO_CH5_RD_DMA_ECC_CONTROL_OFFSET (0x112b4) 2721 #define CMIC_COMMON_POOL_FIFO_CH5_RD_DMA_ECC_STATUS_OFFSET (0x112b8) 2722 #define CMIC_COMMON_POOL_FIFO_CH5_RD_DMA_ECC_STATUS_CLR_OFFSET (0x112bc) 2723 #define CMIC_COMMON_POOL_FIFO_CH5_RD_DMA_HOSTMEM_START_ADDRESS_HI_OFFSET (0x11290) 2724 #define CMIC_COMMON_POOL_FIFO_CH5_RD_DMA_HOSTMEM_START_ADDRESS_LO_OFFSET (0x1128c) 2725 #define CMIC_COMMON_POOL_FIFO_CH5_RD_DMA_HOSTMEM_THRESHOLD_OFFSET (0x1129c) 2726 #define CMIC_COMMON_POOL_FIFO_CH5_RD_DMA_NUM_OF_ENTRIES_READ_FRM_HOSTMEM_OFFSET (0x11294) 2727 #define CMIC_COMMON_POOL_FIFO_CH5_RD_DMA_NUM_OF_ENTRIES_VALID_IN_HOSTMEM_OFFSET (0x11298) 2728 #define CMIC_COMMON_POOL_FIFO_CH5_RD_DMA_OPCODE_OFFSET (0x112a8) 2729 #define CMIC_COMMON_POOL_FIFO_CH5_RD_DMA_SBUS_START_ADDRESS_OFFSET (0x11288) 2730 #define CMIC_COMMON_POOL_FIFO_CH5_RD_DMA_STAT_OFFSET (0x112a0) 2731 #define CMIC_COMMON_POOL_FIFO_CH5_RD_DMA_STAT_CLR_OFFSET (0x112a4) 2732 #define CMIC_COMMON_POOL_FIFO_CH5_RD_DMA_TM_CONTROL_OFFSET (0x112c0) 2733 #define CMIC_COMMON_POOL_FIFO_CH6_RD_DMA_CFG_OFFSET (0x11300) 2734 #define CMIC_COMMON_POOL_FIFO_CH6_RD_DMA_CFG_1_OFFSET (0x11304) 2735 #define CMIC_COMMON_POOL_FIFO_CH6_RD_DMA_CUR_HOSTMEM_WRITE_PTR_HI_OFFSET (0x11348) 2736 #define CMIC_COMMON_POOL_FIFO_CH6_RD_DMA_CUR_HOSTMEM_WRITE_PTR_LO_OFFSET (0x11344) 2737 #define CMIC_COMMON_POOL_FIFO_CH6_RD_DMA_ECCERR_ADDRESS_HI_OFFSET (0x11330) 2738 #define CMIC_COMMON_POOL_FIFO_CH6_RD_DMA_ECCERR_ADDRESS_LO_OFFSET (0x1132c) 2739 #define CMIC_COMMON_POOL_FIFO_CH6_RD_DMA_ECC_CONTROL_OFFSET (0x11334) 2740 #define CMIC_COMMON_POOL_FIFO_CH6_RD_DMA_ECC_STATUS_OFFSET (0x11338) 2741 #define CMIC_COMMON_POOL_FIFO_CH6_RD_DMA_ECC_STATUS_CLR_OFFSET (0x1133c) 2742 #define CMIC_COMMON_POOL_FIFO_CH6_RD_DMA_HOSTMEM_START_ADDRESS_HI_OFFSET (0x11310) 2743 #define CMIC_COMMON_POOL_FIFO_CH6_RD_DMA_HOSTMEM_START_ADDRESS_LO_OFFSET (0x1130c) 2744 #define CMIC_COMMON_POOL_FIFO_CH6_RD_DMA_HOSTMEM_THRESHOLD_OFFSET (0x1131c) 2745 #define CMIC_COMMON_POOL_FIFO_CH6_RD_DMA_NUM_OF_ENTRIES_READ_FRM_HOSTMEM_OFFSET (0x11314) 2746 #define CMIC_COMMON_POOL_FIFO_CH6_RD_DMA_NUM_OF_ENTRIES_VALID_IN_HOSTMEM_OFFSET (0x11318) 2747 #define CMIC_COMMON_POOL_FIFO_CH6_RD_DMA_OPCODE_OFFSET (0x11328) 2748 #define CMIC_COMMON_POOL_FIFO_CH6_RD_DMA_SBUS_START_ADDRESS_OFFSET (0x11308) 2749 #define CMIC_COMMON_POOL_FIFO_CH6_RD_DMA_STAT_OFFSET (0x11320) 2750 #define CMIC_COMMON_POOL_FIFO_CH6_RD_DMA_STAT_CLR_OFFSET (0x11324) 2751 #define CMIC_COMMON_POOL_FIFO_CH6_RD_DMA_TM_CONTROL_OFFSET (0x11340) 2752 #define CMIC_COMMON_POOL_FIFO_CH7_RD_DMA_CFG_OFFSET (0x11380) 2753 #define CMIC_COMMON_POOL_FIFO_CH7_RD_DMA_CFG_1_OFFSET (0x11384) 2754 #define CMIC_COMMON_POOL_FIFO_CH7_RD_DMA_CUR_HOSTMEM_WRITE_PTR_HI_OFFSET (0x113c8) 2755 #define CMIC_COMMON_POOL_FIFO_CH7_RD_DMA_CUR_HOSTMEM_WRITE_PTR_LO_OFFSET (0x113c4) 2756 #define CMIC_COMMON_POOL_FIFO_CH7_RD_DMA_ECCERR_ADDRESS_HI_OFFSET (0x113b0) 2757 #define CMIC_COMMON_POOL_FIFO_CH7_RD_DMA_ECCERR_ADDRESS_LO_OFFSET (0x113ac) 2758 #define CMIC_COMMON_POOL_FIFO_CH7_RD_DMA_ECC_CONTROL_OFFSET (0x113b4) 2759 #define CMIC_COMMON_POOL_FIFO_CH7_RD_DMA_ECC_STATUS_OFFSET (0x113b8) 2760 #define CMIC_COMMON_POOL_FIFO_CH7_RD_DMA_ECC_STATUS_CLR_OFFSET (0x113bc) 2761 #define CMIC_COMMON_POOL_FIFO_CH7_RD_DMA_HOSTMEM_START_ADDRESS_HI_OFFSET (0x11390) 2762 #define CMIC_COMMON_POOL_FIFO_CH7_RD_DMA_HOSTMEM_START_ADDRESS_LO_OFFSET (0x1138c) 2763 #define CMIC_COMMON_POOL_FIFO_CH7_RD_DMA_HOSTMEM_THRESHOLD_OFFSET (0x1139c) 2764 #define CMIC_COMMON_POOL_FIFO_CH7_RD_DMA_NUM_OF_ENTRIES_READ_FRM_HOSTMEM_OFFSET (0x11394) 2765 #define CMIC_COMMON_POOL_FIFO_CH7_RD_DMA_NUM_OF_ENTRIES_VALID_IN_HOSTMEM_OFFSET (0x11398) 2766 #define CMIC_COMMON_POOL_FIFO_CH7_RD_DMA_OPCODE_OFFSET (0x113a8) 2767 #define CMIC_COMMON_POOL_FIFO_CH7_RD_DMA_SBUS_START_ADDRESS_OFFSET (0x11388) 2768 #define CMIC_COMMON_POOL_FIFO_CH7_RD_DMA_STAT_OFFSET (0x113a0) 2769 #define CMIC_COMMON_POOL_FIFO_CH7_RD_DMA_STAT_CLR_OFFSET (0x113a4) 2770 #define CMIC_COMMON_POOL_FIFO_CH7_RD_DMA_TM_CONTROL_OFFSET (0x113c0) 2771 #define CMIC_COMMON_POOL_FIFO_CH8_RD_DMA_CFG_OFFSET (0x11400) 2772 #define CMIC_COMMON_POOL_FIFO_CH8_RD_DMA_CFG_1_OFFSET (0x11404) 2773 #define CMIC_COMMON_POOL_FIFO_CH8_RD_DMA_CUR_HOSTMEM_WRITE_PTR_HI_OFFSET (0x11448) 2774 #define CMIC_COMMON_POOL_FIFO_CH8_RD_DMA_CUR_HOSTMEM_WRITE_PTR_LO_OFFSET (0x11444) 2775 #define CMIC_COMMON_POOL_FIFO_CH8_RD_DMA_ECCERR_ADDRESS_HI_OFFSET (0x11430) 2776 #define CMIC_COMMON_POOL_FIFO_CH8_RD_DMA_ECCERR_ADDRESS_LO_OFFSET (0x1142c) 2777 #define CMIC_COMMON_POOL_FIFO_CH8_RD_DMA_ECC_CONTROL_OFFSET (0x11434) 2778 #define CMIC_COMMON_POOL_FIFO_CH8_RD_DMA_ECC_STATUS_OFFSET (0x11438) 2779 #define CMIC_COMMON_POOL_FIFO_CH8_RD_DMA_ECC_STATUS_CLR_OFFSET (0x1143c) 2780 #define CMIC_COMMON_POOL_FIFO_CH8_RD_DMA_HOSTMEM_START_ADDRESS_HI_OFFSET (0x11410) 2781 #define CMIC_COMMON_POOL_FIFO_CH8_RD_DMA_HOSTMEM_START_ADDRESS_LO_OFFSET (0x1140c) 2782 #define CMIC_COMMON_POOL_FIFO_CH8_RD_DMA_HOSTMEM_THRESHOLD_OFFSET (0x1141c) 2783 #define CMIC_COMMON_POOL_FIFO_CH8_RD_DMA_NUM_OF_ENTRIES_READ_FRM_HOSTMEM_OFFSET (0x11414) 2784 #define CMIC_COMMON_POOL_FIFO_CH8_RD_DMA_NUM_OF_ENTRIES_VALID_IN_HOSTMEM_OFFSET (0x11418) 2785 #define CMIC_COMMON_POOL_FIFO_CH8_RD_DMA_OPCODE_OFFSET (0x11428) 2786 #define CMIC_COMMON_POOL_FIFO_CH8_RD_DMA_SBUS_START_ADDRESS_OFFSET (0x11408) 2787 #define CMIC_COMMON_POOL_FIFO_CH8_RD_DMA_STAT_OFFSET (0x11420) 2788 #define CMIC_COMMON_POOL_FIFO_CH8_RD_DMA_STAT_CLR_OFFSET (0x11424) 2789 #define CMIC_COMMON_POOL_FIFO_CH8_RD_DMA_TM_CONTROL_OFFSET (0x11440) 2790 #define CMIC_COMMON_POOL_FIFO_CH9_RD_DMA_CFG_OFFSET (0x11480) 2791 #define CMIC_COMMON_POOL_FIFO_CH9_RD_DMA_CFG_1_OFFSET (0x11484) 2792 #define CMIC_COMMON_POOL_FIFO_CH9_RD_DMA_CUR_HOSTMEM_WRITE_PTR_HI_OFFSET (0x114c8) 2793 #define CMIC_COMMON_POOL_FIFO_CH9_RD_DMA_CUR_HOSTMEM_WRITE_PTR_LO_OFFSET (0x114c4) 2794 #define CMIC_COMMON_POOL_FIFO_CH9_RD_DMA_ECCERR_ADDRESS_HI_OFFSET (0x114b0) 2795 #define CMIC_COMMON_POOL_FIFO_CH9_RD_DMA_ECCERR_ADDRESS_LO_OFFSET (0x114ac) 2796 #define CMIC_COMMON_POOL_FIFO_CH9_RD_DMA_ECC_CONTROL_OFFSET (0x114b4) 2797 #define CMIC_COMMON_POOL_FIFO_CH9_RD_DMA_ECC_STATUS_OFFSET (0x114b8) 2798 #define CMIC_COMMON_POOL_FIFO_CH9_RD_DMA_ECC_STATUS_CLR_OFFSET (0x114bc) 2799 #define CMIC_COMMON_POOL_FIFO_CH9_RD_DMA_HOSTMEM_START_ADDRESS_HI_OFFSET (0x11490) 2800 #define CMIC_COMMON_POOL_FIFO_CH9_RD_DMA_HOSTMEM_START_ADDRESS_LO_OFFSET (0x1148c) 2801 #define CMIC_COMMON_POOL_FIFO_CH9_RD_DMA_HOSTMEM_THRESHOLD_OFFSET (0x1149c) 2802 #define CMIC_COMMON_POOL_FIFO_CH9_RD_DMA_NUM_OF_ENTRIES_READ_FRM_HOSTMEM_OFFSET (0x11494) 2803 #define CMIC_COMMON_POOL_FIFO_CH9_RD_DMA_NUM_OF_ENTRIES_VALID_IN_HOSTMEM_OFFSET (0x11498) 2804 #define CMIC_COMMON_POOL_FIFO_CH9_RD_DMA_OPCODE_OFFSET (0x114a8) 2805 #define CMIC_COMMON_POOL_FIFO_CH9_RD_DMA_SBUS_START_ADDRESS_OFFSET (0x11488) 2806 #define CMIC_COMMON_POOL_FIFO_CH9_RD_DMA_STAT_OFFSET (0x114a0) 2807 #define CMIC_COMMON_POOL_FIFO_CH9_RD_DMA_STAT_CLR_OFFSET (0x114a4) 2808 #define CMIC_COMMON_POOL_FIFO_CH9_RD_DMA_TM_CONTROL_OFFSET (0x114c0) 2809 #define CMIC_COMMON_POOL_SCHAN_CH0_ACK_DATA_BEAT_COUNT_OFFSET (0x10004) 2810 #define CMIC_COMMON_POOL_SCHAN_CH0_CTRL_OFFSET (0x10000) 2811 #define CMIC_COMMON_POOL_SCHAN_CH0_ERR_OFFSET (0x10008) 2812 #define CMIC_COMMON_POOL_SCHAN_CH0_MESSAGE_OFFSET (0x1000c) 2813 #define CMIC_COMMON_POOL_SCHAN_CH1_ACK_DATA_BEAT_COUNT_OFFSET (0x10104) 2814 #define CMIC_COMMON_POOL_SCHAN_CH1_CTRL_OFFSET (0x10100) 2815 #define CMIC_COMMON_POOL_SCHAN_CH1_ERR_OFFSET (0x10108) 2816 #define CMIC_COMMON_POOL_SCHAN_CH1_MESSAGE_OFFSET (0x1010c) 2817 #define CMIC_COMMON_POOL_SCHAN_CH2_ACK_DATA_BEAT_COUNT_OFFSET (0x10204) 2818 #define CMIC_COMMON_POOL_SCHAN_CH2_CTRL_OFFSET (0x10200) 2819 #define CMIC_COMMON_POOL_SCHAN_CH2_ERR_OFFSET (0x10208) 2820 #define CMIC_COMMON_POOL_SCHAN_CH2_MESSAGE_OFFSET (0x1020c) 2821 #define CMIC_COMMON_POOL_SCHAN_CH3_ACK_DATA_BEAT_COUNT_OFFSET (0x10304) 2822 #define CMIC_COMMON_POOL_SCHAN_CH3_CTRL_OFFSET (0x10300) 2823 #define CMIC_COMMON_POOL_SCHAN_CH3_ERR_OFFSET (0x10308) 2824 #define CMIC_COMMON_POOL_SCHAN_CH3_MESSAGE_OFFSET (0x1030c) 2825 #define CMIC_COMMON_POOL_SCHAN_CH4_ACK_DATA_BEAT_COUNT_OFFSET (0x10404) 2826 #define CMIC_COMMON_POOL_SCHAN_CH4_CTRL_OFFSET (0x10400) 2827 #define CMIC_COMMON_POOL_SCHAN_CH4_ERR_OFFSET (0x10408) 2828 #define CMIC_COMMON_POOL_SCHAN_CH4_MESSAGE_OFFSET (0x1040c) 2829 #define CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY_OFFSET (0x12100) 2830 #define CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_CTRL_OFFSET (0x1200c) 2831 #define CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_RESP_HOSTMEM_START_ADDR_LOWER_OFFSET (0x12014) 2832 #define CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_RESP_HOSTMEM_START_ADDR_UPPER_OFFSET (0x12010) 2833 #define CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_STATUS_OFFSET (0x12020) 2834 #define CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_SUMMARY_HOSTMEM_START_ADDR_LOWER_OFFSET (0x1201c) 2835 #define CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_SUMMARY_HOSTMEM_START_ADDR_UPPER_OFFSET (0x12018) 2836 #define CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY_OFFSET (0x12680) 2837 #define CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_CTRL_OFFSET (0x12024) 2838 #define CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_RESP_HOSTMEM_START_ADDR_LOWER_OFFSET (0x1202c) 2839 #define CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_RESP_HOSTMEM_START_ADDR_UPPER_OFFSET (0x12028) 2840 #define CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_STATUS_OFFSET (0x12038) 2841 #define CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_SUMMARY_HOSTMEM_START_ADDR_LOWER_OFFSET (0x12034) 2842 #define CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_SUMMARY_HOSTMEM_START_ADDR_UPPER_OFFSET (0x12030) 2843 #define CMIC_COMMON_POOL_SCHAN_FIFO_0_ECC_CTRL_OFFSET (0x12000) 2844 #define CMIC_COMMON_POOL_SCHAN_FIFO_0_ECC_STATUS_OFFSET (0x12004) 2845 #define CMIC_COMMON_POOL_SCHAN_FIFO_0_TM_CTRL_OFFSET (0x12008) 2846 #define CMIC_COMMON_POOL_SHARED_1BIT_ECC_ERROR_STATUS_OFFSET (0xd018) 2847 #define CMIC_COMMON_POOL_SHARED_1BIT_ECC_ERROR_STATUS_ENABLE_OFFSET (0xd01c) 2848 #define CMIC_COMMON_POOL_SHARED_2BIT_ECC_ERROR_STATUS_OFFSET (0xd010) 2849 #define CMIC_COMMON_POOL_SHARED_2BIT_ECC_ERROR_STATUS_ENABLE_OFFSET (0xd014) 2850 #define CMIC_COMMON_POOL_SHARED_CONFIG_OFFSET (0xd024) 2851 #define CMIC_COMMON_POOL_SHARED_FIFO_DMA_WRITE_ARB_CTRL_OFFSET (0xd008) 2852 #define CMIC_COMMON_POOL_SHARED_FIFO_DMA_WRITE_AXI_MAP_CTRL_OFFSET (0xd000) 2853 #define CMIC_COMMON_POOL_SHARED_FIFO_DMA_WRITE_AXI_MAP_CTRL_1_OFFSET (0xd004) 2854 #define CMIC_COMMON_POOL_SHARED_IRQ_STAT0_OFFSET (0xd020) 2855 #define CMIC_COMMON_POOL_SHARED_SCHAN_FIFO_WRITE_ARB_CTRL_OFFSET (0xd00c) 2856 #define CMIC_IPROC_TO_RCPU_IRQ_ENABLE0_OFFSET (0x16218) 2857 #define CMIC_IPROC_TO_RCPU_IRQ_ENABLE1_OFFSET (0x1621c) 2858 #define CMIC_IPROC_TO_RCPU_IRQ_ENABLE2_OFFSET (0x16220) 2859 #define CMIC_IPROC_TO_RCPU_IRQ_ENABLE3_OFFSET (0x16224) 2860 #define CMIC_IPROC_TO_RCPU_IRQ_ENABLE4_OFFSET (0x16228) 2861 #define CMIC_IPROC_TO_RCPU_IRQ_ENABLE5_OFFSET (0x1622c) 2862 #define CMIC_IPROC_TO_RCPU_IRQ_ENABLE6_OFFSET (0x16230) 2863 #define CMIC_IPROC_TO_RCPU_IRQ_ENABLE7_OFFSET (0x16234) 2864 #define CMIC_IPROC_TO_RCPU_IRQ_STAT0_OFFSET (0x161f8) 2865 #define CMIC_IPROC_TO_RCPU_IRQ_STAT1_OFFSET (0x161fc) 2866 #define CMIC_IPROC_TO_RCPU_IRQ_STAT2_OFFSET (0x16200) 2867 #define CMIC_IPROC_TO_RCPU_IRQ_STAT3_OFFSET (0x16204) 2868 #define CMIC_IPROC_TO_RCPU_IRQ_STAT4_OFFSET (0x16208) 2869 #define CMIC_IPROC_TO_RCPU_IRQ_STAT5_OFFSET (0x1620c) 2870 #define CMIC_IPROC_TO_RCPU_IRQ_STAT6_OFFSET (0x16210) 2871 #define CMIC_IPROC_TO_RCPU_IRQ_STAT7_OFFSET (0x16214) 2872 #define CMIC_RPE_1BIT_ECC_ERROR_STATUS_OFFSET (0x16194) 2873 #define CMIC_RPE_1BIT_ECC_ERROR_STATUS_ENABLE_OFFSET (0x16198) 2874 #define CMIC_RPE_2BIT_ECC_ERROR_STATUS_OFFSET (0x1618c) 2875 #define CMIC_RPE_2BIT_ECC_ERROR_STATUS_ENABLE_OFFSET (0x16190) 2876 #define CMIC_RPE_AXI_AR_COUNT_SPLIT_TX_OFFSET (0x161f4) 2877 #define CMIC_RPE_AXI_AR_COUNT_TX_OFFSET (0x161f0) 2878 #define CMIC_RPE_AXI_STAT_OFFSET (0x16274) 2879 #define CMIC_RPE_COMPLETION_BUF_ECC_CONTROL_OFFSET (0x1626c) 2880 #define CMIC_RPE_COMPLETION_BUF_ECC_STATUS_OFFSET (0x16268) 2881 #define CMIC_RPE_COMPLETION_BUF_MAX_FLIST_ENTRIES_OFFSET (0x16260) 2882 #define CMIC_RPE_COMPLETION_BUF_STATUS_NUM_FREE_ENTRIES_OFFSET (0x16264) 2883 #define CMIC_RPE_COMPLETION_BUF_TM_CONTROL_OFFSET (0x16270) 2884 #define CMIC_RPE_DMA_MASTER_TOTAL_OUTSTD_TRANS_LIMIT_OFFSET (0x1625c) 2885 #define CMIC_RPE_INTR_PKT_PACING_DELAY_OFFSET (0x16178) 2886 #define CMIC_RPE_IRQ_STAT_OFFSET (0x16184) 2887 #define CMIC_RPE_IRQ_STAT_CLR_OFFSET (0x16188) 2888 #define CMIC_RPE_PIO_MEMDMA_COS_0_OFFSET (0x1612c) 2889 #define CMIC_RPE_PIO_MEMDMA_COS_1_OFFSET (0x16130) 2890 #define CMIC_RPE_PIO_MEMDMA_MEM_ECC_CONTROL_OFFSET (0x16250) 2891 #define CMIC_RPE_PIO_MEMDMA_MEM_ECC_STATUS_OFFSET (0x16258) 2892 #define CMIC_RPE_PIO_MEMDMA_MEM_TM_CONTROL_OFFSET (0x16254) 2893 #define CMIC_RPE_PIO_MEMDMA_RXBUF_THRESHOLD_CONFIG_OFFSET (0x1623c) 2894 #define CMIC_RPE_PKTDMA_COS_0_OFFSET (0x1611c) 2895 #define CMIC_RPE_PKTDMA_COS_1_OFFSET (0x16120) 2896 #define CMIC_RPE_PKTDMA_RXBUF_THRESHOLD_CONFIG_OFFSET (0x16238) 2897 #define CMIC_RPE_PKT_COS_QUEUES_HI_OFFSET (0x1617c) 2898 #define CMIC_RPE_PKT_COS_QUEUES_LO_OFFSET (0x16180) 2899 #define CMIC_RPE_PKT_COUNT_FROMCPU_OFFSET (0x161a8) 2900 #define CMIC_RPE_PKT_COUNT_FROMCPU_MH_OFFSET (0x161a4) 2901 #define CMIC_RPE_PKT_COUNT_INTR_OFFSET (0x161d4) 2902 #define CMIC_RPE_PKT_COUNT_MEMDMA_OFFSET (0x161d0) 2903 #define CMIC_RPE_PKT_COUNT_MEMDMA_REPLY_OFFSET (0x161cc) 2904 #define CMIC_RPE_PKT_COUNT_PIO_OFFSET (0x161c0) 2905 #define CMIC_RPE_PKT_COUNT_PIO_MEMDMA_DROP_OFFSET (0x161dc) 2906 #define CMIC_RPE_PKT_COUNT_PIO_REPLY_OFFSET (0x161bc) 2907 #define CMIC_RPE_PKT_COUNT_RXPKT_OFFSET (0x161e0) 2908 #define CMIC_RPE_PKT_COUNT_RXPKT_ERR_OFFSET (0x161e4) 2909 #define CMIC_RPE_PKT_COUNT_SBUSDMA_OFFSET (0x161c8) 2910 #define CMIC_RPE_PKT_COUNT_SBUSDMA_REPLY_OFFSET (0x161c4) 2911 #define CMIC_RPE_PKT_COUNT_SCHAN_OFFSET (0x1619c) 2912 #define CMIC_RPE_PKT_COUNT_SCHAN_REP_OFFSET (0x161a0) 2913 #define CMIC_RPE_PKT_COUNT_SCHAN_SBUSDMA_DROP_OFFSET (0x161d8) 2914 #define CMIC_RPE_PKT_COUNT_TOCPUD_OFFSET (0x161b0) 2915 #define CMIC_RPE_PKT_COUNT_TOCPUDM_OFFSET (0x161ac) 2916 #define CMIC_RPE_PKT_COUNT_TOCPUE_OFFSET (0x161b8) 2917 #define CMIC_RPE_PKT_COUNT_TOCPUEM_OFFSET (0x161b4) 2918 #define CMIC_RPE_PKT_COUNT_TXPKT_OFFSET (0x161e8) 2919 #define CMIC_RPE_PKT_COUNT_TXPKT_ERR_OFFSET (0x161ec) 2920 #define CMIC_RPE_PKT_CTRL_OFFSET (0x16100) 2921 #define CMIC_RPE_PKT_ETHER_SIG_OFFSET (0x16118) 2922 #define CMIC_RPE_PKT_LMAC0_HI_OFFSET (0x16104) 2923 #define CMIC_RPE_PKT_LMAC0_LO_OFFSET (0x16108) 2924 #define CMIC_RPE_PKT_LMAC1_HI_OFFSET (0x1610c) 2925 #define CMIC_RPE_PKT_LMAC1_LO_OFFSET (0x16110) 2926 #define CMIC_RPE_PKT_PORTS_0_OFFSET (0x16140) 2927 #define CMIC_RPE_PKT_PORTS_1_OFFSET (0x16144) 2928 #define CMIC_RPE_PKT_PORTS_2_OFFSET (0x16148) 2929 #define CMIC_RPE_PKT_PORTS_3_OFFSET (0x1614c) 2930 #define CMIC_RPE_PKT_PORTS_4_OFFSET (0x16150) 2931 #define CMIC_RPE_PKT_PORTS_5_OFFSET (0x16154) 2932 #define CMIC_RPE_PKT_PORTS_6_OFFSET (0x16158) 2933 #define CMIC_RPE_PKT_PORTS_7_OFFSET (0x1615c) 2934 #define CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_0_OFFSET (0x16000) 2935 #define CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_1_OFFSET (0x16004) 2936 #define CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_10_OFFSET (0x16028) 2937 #define CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_11_OFFSET (0x1602c) 2938 #define CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_12_OFFSET (0x16030) 2939 #define CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_13_OFFSET (0x16034) 2940 #define CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_14_OFFSET (0x16038) 2941 #define CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_15_OFFSET (0x1603c) 2942 #define CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_16_OFFSET (0x16040) 2943 #define CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_17_OFFSET (0x16044) 2944 #define CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_18_OFFSET (0x16048) 2945 #define CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_19_OFFSET (0x1604c) 2946 #define CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_2_OFFSET (0x16008) 2947 #define CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_20_OFFSET (0x16050) 2948 #define CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_21_OFFSET (0x16054) 2949 #define CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_22_OFFSET (0x16058) 2950 #define CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_23_OFFSET (0x1605c) 2951 #define CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_24_OFFSET (0x16060) 2952 #define CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_25_OFFSET (0x16064) 2953 #define CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_26_OFFSET (0x16068) 2954 #define CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_27_OFFSET (0x1606c) 2955 #define CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_28_OFFSET (0x16070) 2956 #define CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_29_OFFSET (0x16074) 2957 #define CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_3_OFFSET (0x1600c) 2958 #define CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_30_OFFSET (0x16078) 2959 #define CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_31_OFFSET (0x1607c) 2960 #define CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_32_OFFSET (0x16080) 2961 #define CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_33_OFFSET (0x16084) 2962 #define CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_34_OFFSET (0x16088) 2963 #define CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_35_OFFSET (0x1608c) 2964 #define CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_36_OFFSET (0x16090) 2965 #define CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_37_OFFSET (0x16094) 2966 #define CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_38_OFFSET (0x16098) 2967 #define CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_39_OFFSET (0x1609c) 2968 #define CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_4_OFFSET (0x16010) 2969 #define CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_40_OFFSET (0x160a0) 2970 #define CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_41_OFFSET (0x160a4) 2971 #define CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_42_OFFSET (0x160a8) 2972 #define CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_43_OFFSET (0x160ac) 2973 #define CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_44_OFFSET (0x160b0) 2974 #define CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_45_OFFSET (0x160b4) 2975 #define CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_46_OFFSET (0x160b8) 2976 #define CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_47_OFFSET (0x160bc) 2977 #define CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_48_OFFSET (0x160c0) 2978 #define CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_49_OFFSET (0x160c4) 2979 #define CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_5_OFFSET (0x16014) 2980 #define CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_50_OFFSET (0x160c8) 2981 #define CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_51_OFFSET (0x160cc) 2982 #define CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_52_OFFSET (0x160d0) 2983 #define CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_53_OFFSET (0x160d4) 2984 #define CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_54_OFFSET (0x160d8) 2985 #define CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_55_OFFSET (0x160dc) 2986 #define CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_56_OFFSET (0x160e0) 2987 #define CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_57_OFFSET (0x160e4) 2988 #define CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_58_OFFSET (0x160e8) 2989 #define CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_59_OFFSET (0x160ec) 2990 #define CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_6_OFFSET (0x16018) 2991 #define CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_60_OFFSET (0x160f0) 2992 #define CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_61_OFFSET (0x160f4) 2993 #define CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_62_OFFSET (0x160f8) 2994 #define CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_63_OFFSET (0x160fc) 2995 #define CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_7_OFFSET (0x1601c) 2996 #define CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_8_OFFSET (0x16020) 2997 #define CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_9_OFFSET (0x16024) 2998 #define CMIC_RPE_PKT_REASON_0_TYPE_OFFSET (0x16500) 2999 #define CMIC_RPE_PKT_REASON_1_TYPE_OFFSET (0x16540) 3000 #define CMIC_RPE_PKT_REASON_2_TYPE_OFFSET (0x16680) 3001 #define CMIC_RPE_PKT_REASON_DIRECT_0_TYPE_OFFSET (0x16580) 3002 #define CMIC_RPE_PKT_REASON_DIRECT_1_TYPE_OFFSET (0x165c0) 3003 #define CMIC_RPE_PKT_REASON_DIRECT_2_TYPE_OFFSET (0x166c0) 3004 #define CMIC_RPE_PKT_REASON_MINI_0_TYPE_OFFSET (0x16600) 3005 #define CMIC_RPE_PKT_REASON_MINI_1_TYPE_OFFSET (0x16640) 3006 #define CMIC_RPE_PKT_REASON_MINI_2_TYPE_OFFSET (0x16700) 3007 #define CMIC_RPE_PKT_RMAC_OFFSET (0x16160) 3008 #define CMIC_RPE_PKT_RMAC_HI_OFFSET (0x16164) 3009 #define CMIC_RPE_PKT_RMH0_OFFSET (0x16168) 3010 #define CMIC_RPE_PKT_RMH1_OFFSET (0x1616c) 3011 #define CMIC_RPE_PKT_RMH2_OFFSET (0x16170) 3012 #define CMIC_RPE_PKT_RMH3_OFFSET (0x16174) 3013 #define CMIC_RPE_PKT_VLAN_OFFSET (0x16114) 3014 #define CMIC_RPE_SCHAN_SBUSDMA_COS_0_OFFSET (0x16124) 3015 #define CMIC_RPE_SCHAN_SBUSDMA_COS_1_OFFSET (0x16128) 3016 #define CMIC_RPE_SCHAN_SBUSDMA_MEM_ECC_CONTROL_OFFSET (0x16244) 3017 #define CMIC_RPE_SCHAN_SBUSDMA_MEM_ECC_STATUS_OFFSET (0x1624c) 3018 #define CMIC_RPE_SCHAN_SBUSDMA_MEM_TM_CONTROL_OFFSET (0x16248) 3019 #define CMIC_RPE_SCHAN_SBUSDMA_RXBUF_THRESHOLD_CONFIG_OFFSET (0x16240) 3020 #define CMIC_RPE_SHARED_PROGRAMMABLE_COS_MASK0_OFFSET (0x16134) 3021 #define CMIC_RPE_SHARED_PROGRAMMABLE_COS_MASK1_OFFSET (0x16138) 3022 #define CMIC_RPE_SHARED_RXBUF_BLOCK_DATABUF_ALLOC_OFFSET (0x16488) 3023 #define CMIC_RPE_SHARED_RXBUF_CONFIG_OFFSET (0x1648c) 3024 #define CMIC_RPE_SHARED_RXBUF_DATABUF_MAX_FLIST_ENTRIES_OFFSET (0x16480) 3025 #define CMIC_RPE_SHARED_RXBUF_DATABUF_NUM_FREE_ENTRIES_OFFSET (0x16484) 3026 #define CMIC_RPE_SHARED_RXBUF_ECC_CONTROL_OFFSET (0x16490) 3027 #define CMIC_RPE_SHARED_RXBUF_ECC_STATUS_OFFSET (0x16498) 3028 #define CMIC_RPE_SHARED_RXBUF_ECC_STATUS_CLR_OFFSET (0x1649c) 3029 #define CMIC_RPE_SHARED_RXBUF_THRESHOLD_CONFIG_OFFSET (0x1613c) 3030 #define CMIC_RPE_SHARED_RXBUF_TM_CONTROL_OFFSET (0x16494) 3031 #define CMIC_RPE_SHARED_TXBUF_DATABUF_MAX_FLIST_ENTRIES_OFFSET (0x16428) 3032 #define CMIC_RPE_SHARED_TXBUF_DATABUF_NUM_FREE_ENTRIES_OFFSET (0x16424) 3033 #define CMIC_RPE_SHARED_TXBUF_DEBUG_OFFSET (0x16420) 3034 #define CMIC_RPE_SHARED_TXBUF_ECC_CONTROL_OFFSET (0x16434) 3035 #define CMIC_RPE_SHARED_TXBUF_ECC_STATUS_OFFSET (0x1642c) 3036 #define CMIC_RPE_SHARED_TXBUF_ECC_STATUS_CLR_OFFSET (0x16430) 3037 #define CMIC_RPE_SHARED_TXBUF_MAX_BUF_LIMITS_OFFSET (0x16400) 3038 #define CMIC_RPE_SHARED_TXBUF_MIN_BUF_LIMITS_OFFSET (0x16404) 3039 #define CMIC_RPE_SHARED_TXBUF_RD_THRESHOLD_CONFIG_OFFSET (0x16408) 3040 #define CMIC_RPE_SHARED_TXBUF_RD_WRR_ARB_CTRL_OFFSET (0x1640c) 3041 #define CMIC_RPE_SHARED_TXBUF_SLICE0_PKT_CNT_OFFSET (0x1641c) 3042 #define CMIC_RPE_SHARED_TXBUF_SLICE1_PKT_CNT_OFFSET (0x16418) 3043 #define CMIC_RPE_SHARED_TXBUF_SLICE2_PKT_CNT_OFFSET (0x16414) 3044 #define CMIC_RPE_SHARED_TXBUF_SLICE3_PKT_CNT_OFFSET (0x16410) 3045 #define CMIC_RPE_SHARED_TXBUF_TM_CONTROL_OFFSET (0x16438) 3046 #define CMIC_TOP_CONFIG_OFFSET (0x8) 3047 #define CMIC_TOP_EPINTF_BUF_DEPTH_OFFSET (0x74) 3048 #define CMIC_TOP_EPINTF_MAX_INTERFACE_CREDITS_OFFSET (0x70) 3049 #define CMIC_TOP_EPINTF_RELEASE_ALL_CREDITS_OFFSET (0x6c) 3050 #define CMIC_TOP_EP_TO_CPU_HEADER_SIZE_OFFSET (0x4) 3051 #define CMIC_TOP_IPINTF_BUF_DEPTH_OFFSET (0x64) 3052 #define CMIC_TOP_IPINTF_INTERFACE_CREDITS_OFFSET (0x68) 3053 #define CMIC_TOP_IPINTF_WRR_ARB_CTRL_OFFSET (0x60) 3054 #define CMIC_TOP_PKT_COUNT_RXPKT_OFFSET (0x78) 3055 #define CMIC_TOP_PKT_COUNT_RXPKT_DROP_OFFSET (0x80) 3056 #define CMIC_TOP_PKT_COUNT_RXPKT_ERR_OFFSET (0x7c) 3057 #define CMIC_TOP_PKT_COUNT_TXPKT_OFFSET (0x84) 3058 #define CMIC_TOP_PKT_COUNT_TXPKT_ERR_OFFSET (0x88) 3059 #define CMIC_TOP_SBUS_RING_ARB_CTRL_FIFODMA_OFFSET (0x54) 3060 #define CMIC_TOP_SBUS_RING_ARB_CTRL_FIFODMA_1_OFFSET (0x58) 3061 #define CMIC_TOP_SBUS_RING_ARB_CTRL_RPE_SCHAN_OFFSET (0x5c) 3062 #define CMIC_TOP_SBUS_RING_ARB_CTRL_SBUSDMA_OFFSET (0x4c) 3063 #define CMIC_TOP_SBUS_RING_ARB_CTRL_SCHAN_OFFSET (0x50) 3064 #define CMIC_TOP_SBUS_RING_MAP_0_7_OFFSET (0xc) 3065 #define CMIC_TOP_SBUS_RING_MAP_104_111_OFFSET (0x40) 3066 #define CMIC_TOP_SBUS_RING_MAP_112_119_OFFSET (0x44) 3067 #define CMIC_TOP_SBUS_RING_MAP_120_127_OFFSET (0x48) 3068 #define CMIC_TOP_SBUS_RING_MAP_16_23_OFFSET (0x14) 3069 #define CMIC_TOP_SBUS_RING_MAP_24_31_OFFSET (0x18) 3070 #define CMIC_TOP_SBUS_RING_MAP_32_39_OFFSET (0x1c) 3071 #define CMIC_TOP_SBUS_RING_MAP_40_47_OFFSET (0x20) 3072 #define CMIC_TOP_SBUS_RING_MAP_48_55_OFFSET (0x24) 3073 #define CMIC_TOP_SBUS_RING_MAP_56_63_OFFSET (0x28) 3074 #define CMIC_TOP_SBUS_RING_MAP_64_71_OFFSET (0x2c) 3075 #define CMIC_TOP_SBUS_RING_MAP_72_79_OFFSET (0x30) 3076 #define CMIC_TOP_SBUS_RING_MAP_80_87_OFFSET (0x34) 3077 #define CMIC_TOP_SBUS_RING_MAP_88_95_OFFSET (0x38) 3078 #define CMIC_TOP_SBUS_RING_MAP_8_15_OFFSET (0x10) 3079 #define CMIC_TOP_SBUS_RING_MAP_96_103_OFFSET (0x3c) 3080 #define CMIC_TOP_SBUS_TIMEOUT_OFFSET (0x0) 3081 #define CMIC_TOP_STATISTICS_COUNTER_CONTROL_OFFSET (0x94) 3082 #define CMIC_TOP_STATISTICS_COUNTER_STATUS_OFFSET (0x98) 3083 #define CMIC_TOP_STATISTICS_EP_BYTE_COUNT_HI_OFFSET (0xac) 3084 #define CMIC_TOP_STATISTICS_EP_BYTE_COUNT_LO_OFFSET (0xa4) 3085 #define CMIC_TOP_STATISTICS_EP_PKT_COUNT_OFFSET (0x9c) 3086 #define CMIC_TOP_STATISTICS_IP_BYTE_COUNT_HI_OFFSET (0xb0) 3087 #define CMIC_TOP_STATISTICS_IP_BYTE_COUNT_LO_OFFSET (0xa8) 3088 #define CMIC_TOP_STATISTICS_IP_PKT_COUNT_OFFSET (0xa0) 3089 #define CMIC_TOP_TO_MMU_COS_MASK_LSB_BITS_OFFSET (0x8c) 3090 #define CMIC_TOP_TO_MMU_COS_MASK_MSB_BITS_OFFSET (0x90)