cmicm.h (651973B)
1 /* 2 * DO NOT EDIT THIS FILE! 3 * This file is auto-generated from the registers file. 4 * Edits to this file will be lost when it is regenerated. 5 * 6 * 7 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 8 * 9 * Copyright 2007-2020 Broadcom Inc. All rights reserved. 10 * 11 * File: cmicm.h 12 * Purpose: CMICM registers include file. 13 * Supports: bcm88650_a0 14 * bcm88650_b0 15 * bcm88660_a0 16 * bcm2801pm_a0 17 * bcm88202_a0 18 * bcm88675_a0 19 * bcm83207_a0 20 * bcm83208_a0 21 * bcm56440_a0 22 * bcm56440_b0 23 * bcm56640_a0 24 * bcm56850_a0 25 * bcm56450_a0 26 * bcm56450_b0 27 * bcm56450_b1 28 * bcm56340_a0 29 * bcm56150_a0 30 * bcm53400_a0 31 * bcm56960_a0 32 * bcm56860_a0 33 * bcm56560_a0 34 * bcm56560_b0 35 * bcm56260_a0 36 * bcm56260_b0 37 * bcm88375_a0 38 * bcm88470_a0 39 * bcm88470_b0 40 * bcm88270_a0 41 * bcm8206_a0 42 * bcm88675_b0 43 * bcm88375_b0 44 * bcm88680_a0 45 * bcm56160_a0 46 * bcm56270_a0 47 * bcm56965_a0 48 * bcm56970_a0 49 * bcm53570_a0 50 * bcm53570_b0 51 * bcm53540_a0 52 * bcm56670_a0 53 * bcm56670_b0 54 */ 55 56 /* This array is sorted on address. Don't modify */ 57 #define CMICM_REG_INIT { \ 58 { 0x00000000, "CMIC_I2CM_SMBUS_CONFIG", CMIC_I2CM_SMBUS_CONFIGr }, \ 59 { 0x00000004, "CMIC_I2CM_SMBUS_TIMING_CONFIG", CMIC_I2CM_SMBUS_TIMING_CONFIGr }, \ 60 { 0x00000008, "CMIC_I2CM_SMBUS_ADDRESS", CMIC_I2CM_SMBUS_ADDRESSr }, \ 61 { 0x0000000c, "CMIC_I2CM_SMBUS_MASTER_FIFO_CONTROL", CMIC_I2CM_SMBUS_MASTER_FIFO_CONTROLr }, \ 62 { 0x00000010, "CMIC_I2CM_SMBUS_SLAVE_FIFO_CONTROL", CMIC_I2CM_SMBUS_SLAVE_FIFO_CONTROLr }, \ 63 { 0x00000014, "CMIC_I2CM_SMBUS_BIT_BANG_CONTROL", CMIC_I2CM_SMBUS_BIT_BANG_CONTROLr }, \ 64 { 0x00000030, "CMIC_I2CM_SMBUS_MASTER_COMMAND", CMIC_I2CM_SMBUS_MASTER_COMMANDr }, \ 65 { 0x00000034, "CMIC_I2CM_SMBUS_SLAVE_COMMAND", CMIC_I2CM_SMBUS_SLAVE_COMMANDr }, \ 66 { 0x00000038, "CMIC_I2CM_SMBUS_EVENT_ENABLE", CMIC_I2CM_SMBUS_EVENT_ENABLEr }, \ 67 { 0x0000003c, "CMIC_I2CM_SMBUS_EVENT_STATUS", CMIC_I2CM_SMBUS_EVENT_STATUSr }, \ 68 { 0x00000040, "CMIC_I2CM_SMBUS_MASTER_DATA_WRITE", CMIC_I2CM_SMBUS_MASTER_DATA_WRITEr }, \ 69 { 0x00000044, "CMIC_I2CM_SMBUS_MASTER_DATA_READ", CMIC_I2CM_SMBUS_MASTER_DATA_READr }, \ 70 { 0x00000048, "CMIC_I2CM_SMBUS_SLAVE_DATA_WRITE", CMIC_I2CM_SMBUS_SLAVE_DATA_WRITEr }, \ 71 { 0x0000004c, "CMIC_I2CM_SMBUS_SLAVE_DATA_READ", CMIC_I2CM_SMBUS_SLAVE_DATA_READr }, \ 72 { 0x000000b0, "SMBUS_TIMING_CONFIG_2", SMBUS_TIMING_CONFIG_2r }, \ 73 { 0x00001500, "MSPI_SPCR0_LSB", MSPI_SPCR0_LSBr }, \ 74 { 0x00001504, "MSPI_SPCR0_MSB", MSPI_SPCR0_MSBr }, \ 75 { 0x00001508, "MSPI_SPCR1_LSB", MSPI_SPCR1_LSBr }, \ 76 { 0x0000150c, "MSPI_SPCR1_MSB", MSPI_SPCR1_MSBr }, \ 77 { 0x00001510, "MSPI_NEWQP", MSPI_NEWQPr }, \ 78 { 0x00001514, "MSPI_ENDQP", MSPI_ENDQPr }, \ 79 { 0x00001518, "MSPI_SPCR2", MSPI_SPCR2r }, \ 80 { 0x00001520, "MSPI_STATUS", MSPI_STATUSr }, \ 81 { 0x00001524, "MSPI_CPTQP", MSPI_CPTQPr }, \ 82 { 0x00001540, "MSPI_TXRAM_00", MSPI_TXRAM_00r }, \ 83 { 0x00001544, "MSPI_TXRAM_01", MSPI_TXRAM_01r }, \ 84 { 0x00001548, "MSPI_TXRAM_02", MSPI_TXRAM_02r }, \ 85 { 0x0000154c, "MSPI_TXRAM_03", MSPI_TXRAM_03r }, \ 86 { 0x00001550, "MSPI_TXRAM_04", MSPI_TXRAM_04r }, \ 87 { 0x00001554, "MSPI_TXRAM_05", MSPI_TXRAM_05r }, \ 88 { 0x00001558, "MSPI_TXRAM_06", MSPI_TXRAM_06r }, \ 89 { 0x0000155c, "MSPI_TXRAM_07", MSPI_TXRAM_07r }, \ 90 { 0x00001560, "MSPI_TXRAM_08", MSPI_TXRAM_08r }, \ 91 { 0x00001564, "MSPI_TXRAM_09", MSPI_TXRAM_09r }, \ 92 { 0x00001568, "MSPI_TXRAM_10", MSPI_TXRAM_10r }, \ 93 { 0x0000156c, "MSPI_TXRAM_11", MSPI_TXRAM_11r }, \ 94 { 0x00001570, "MSPI_TXRAM_12", MSPI_TXRAM_12r }, \ 95 { 0x00001574, "MSPI_TXRAM_13", MSPI_TXRAM_13r }, \ 96 { 0x00001578, "MSPI_TXRAM_14", MSPI_TXRAM_14r }, \ 97 { 0x0000157c, "MSPI_TXRAM_15", MSPI_TXRAM_15r }, \ 98 { 0x00001580, "MSPI_TXRAM_16", MSPI_TXRAM_16r }, \ 99 { 0x00001584, "MSPI_TXRAM_17", MSPI_TXRAM_17r }, \ 100 { 0x00001588, "MSPI_TXRAM_18", MSPI_TXRAM_18r }, \ 101 { 0x0000158c, "MSPI_TXRAM_19", MSPI_TXRAM_19r }, \ 102 { 0x00001590, "MSPI_TXRAM_20", MSPI_TXRAM_20r }, \ 103 { 0x00001594, "MSPI_TXRAM_21", MSPI_TXRAM_21r }, \ 104 { 0x00001598, "MSPI_TXRAM_22", MSPI_TXRAM_22r }, \ 105 { 0x0000159c, "MSPI_TXRAM_23", MSPI_TXRAM_23r }, \ 106 { 0x000015a0, "MSPI_TXRAM_24", MSPI_TXRAM_24r }, \ 107 { 0x000015a4, "MSPI_TXRAM_25", MSPI_TXRAM_25r }, \ 108 { 0x000015a8, "MSPI_TXRAM_26", MSPI_TXRAM_26r }, \ 109 { 0x000015ac, "MSPI_TXRAM_27", MSPI_TXRAM_27r }, \ 110 { 0x000015b0, "MSPI_TXRAM_28", MSPI_TXRAM_28r }, \ 111 { 0x000015b4, "MSPI_TXRAM_29", MSPI_TXRAM_29r }, \ 112 { 0x000015b8, "MSPI_TXRAM_30", MSPI_TXRAM_30r }, \ 113 { 0x000015bc, "MSPI_TXRAM_31", MSPI_TXRAM_31r }, \ 114 { 0x000015c0, "MSPI_RXRAM_00", MSPI_RXRAM_00r }, \ 115 { 0x000015c4, "MSPI_RXRAM_01", MSPI_RXRAM_01r }, \ 116 { 0x000015c8, "MSPI_RXRAM_02", MSPI_RXRAM_02r }, \ 117 { 0x000015cc, "MSPI_RXRAM_03", MSPI_RXRAM_03r }, \ 118 { 0x000015d0, "MSPI_RXRAM_04", MSPI_RXRAM_04r }, \ 119 { 0x000015d4, "MSPI_RXRAM_05", MSPI_RXRAM_05r }, \ 120 { 0x000015d8, "MSPI_RXRAM_06", MSPI_RXRAM_06r }, \ 121 { 0x000015dc, "MSPI_RXRAM_07", MSPI_RXRAM_07r }, \ 122 { 0x000015e0, "MSPI_RXRAM_08", MSPI_RXRAM_08r }, \ 123 { 0x000015e4, "MSPI_RXRAM_09", MSPI_RXRAM_09r }, \ 124 { 0x000015e8, "MSPI_RXRAM_10", MSPI_RXRAM_10r }, \ 125 { 0x000015ec, "MSPI_RXRAM_11", MSPI_RXRAM_11r }, \ 126 { 0x000015f0, "MSPI_RXRAM_12", MSPI_RXRAM_12r }, \ 127 { 0x000015f4, "MSPI_RXRAM_13", MSPI_RXRAM_13r }, \ 128 { 0x000015f8, "MSPI_RXRAM_14", MSPI_RXRAM_14r }, \ 129 { 0x000015fc, "MSPI_RXRAM_15", MSPI_RXRAM_15r }, \ 130 { 0x00001600, "MSPI_RXRAM_16", MSPI_RXRAM_16r }, \ 131 { 0x00001604, "MSPI_RXRAM_17", MSPI_RXRAM_17r }, \ 132 { 0x00001608, "MSPI_RXRAM_18", MSPI_RXRAM_18r }, \ 133 { 0x0000160c, "MSPI_RXRAM_19", MSPI_RXRAM_19r }, \ 134 { 0x00001610, "MSPI_RXRAM_20", MSPI_RXRAM_20r }, \ 135 { 0x00001614, "MSPI_RXRAM_21", MSPI_RXRAM_21r }, \ 136 { 0x00001618, "MSPI_RXRAM_22", MSPI_RXRAM_22r }, \ 137 { 0x0000161c, "MSPI_RXRAM_23", MSPI_RXRAM_23r }, \ 138 { 0x00001620, "MSPI_RXRAM_24", MSPI_RXRAM_24r }, \ 139 { 0x00001624, "MSPI_RXRAM_25", MSPI_RXRAM_25r }, \ 140 { 0x00001628, "MSPI_RXRAM_26", MSPI_RXRAM_26r }, \ 141 { 0x0000162c, "MSPI_RXRAM_27", MSPI_RXRAM_27r }, \ 142 { 0x00001630, "MSPI_RXRAM_28", MSPI_RXRAM_28r }, \ 143 { 0x00001634, "MSPI_RXRAM_29", MSPI_RXRAM_29r }, \ 144 { 0x00001638, "MSPI_RXRAM_30", MSPI_RXRAM_30r }, \ 145 { 0x0000163c, "MSPI_RXRAM_31", MSPI_RXRAM_31r }, \ 146 { 0x00001640, "MSPI_CDRAM_00", MSPI_CDRAM_00r }, \ 147 { 0x00001644, "MSPI_CDRAM_01", MSPI_CDRAM_01r }, \ 148 { 0x00001648, "MSPI_CDRAM_02", MSPI_CDRAM_02r }, \ 149 { 0x0000164c, "MSPI_CDRAM_03", MSPI_CDRAM_03r }, \ 150 { 0x00001650, "MSPI_CDRAM_04", MSPI_CDRAM_04r }, \ 151 { 0x00001654, "MSPI_CDRAM_05", MSPI_CDRAM_05r }, \ 152 { 0x00001658, "MSPI_CDRAM_06", MSPI_CDRAM_06r }, \ 153 { 0x0000165c, "MSPI_CDRAM_07", MSPI_CDRAM_07r }, \ 154 { 0x00001660, "MSPI_CDRAM_08", MSPI_CDRAM_08r }, \ 155 { 0x00001664, "MSPI_CDRAM_09", MSPI_CDRAM_09r }, \ 156 { 0x00001668, "MSPI_CDRAM_10", MSPI_CDRAM_10r }, \ 157 { 0x0000166c, "MSPI_CDRAM_11", MSPI_CDRAM_11r }, \ 158 { 0x00001670, "MSPI_CDRAM_12", MSPI_CDRAM_12r }, \ 159 { 0x00001674, "MSPI_CDRAM_13", MSPI_CDRAM_13r }, \ 160 { 0x00001678, "MSPI_CDRAM_14", MSPI_CDRAM_14r }, \ 161 { 0x0000167c, "MSPI_CDRAM_15", MSPI_CDRAM_15r }, \ 162 { 0x00001680, "CMICM_BSPI_MAST_N_BOOT", CMICM_BSPI_MAST_N_BOOTr }, \ 163 { 0x00001684, "CMICM_BSPI_BUSY_STATUS", CMICM_BSPI_BUSY_STATUSr }, \ 164 { 0x00001688, "CMICM_BSPI_INTR_STATUS", CMICM_BSPI_INTR_STATUSr }, \ 165 { 0x0000168c, "CMICM_BSPI_B0_STATUS", CMICM_BSPI_B0_STATUSr }, \ 166 { 0x00001690, "CMICM_BSPI_B0_CNTRL", CMICM_BSPI_B0_CNTRLr }, \ 167 { 0x00001694, "CMICM_BSPI_B1_STATUS", CMICM_BSPI_B1_STATUSr }, \ 168 { 0x00001698, "CMICM_BSPI_B1_CNTRL", CMICM_BSPI_B1_CNTRLr }, \ 169 { 0x00002000, "CMIC_GP_DATA_IN", CMIC_GP_DATA_INr }, \ 170 { 0x00002004, "CMIC_GP_DATA_OUT", CMIC_GP_DATA_OUTr }, \ 171 { 0x00002008, "CMIC_GP_OUT_EN", CMIC_GP_OUT_ENr }, \ 172 { 0x0000200c, "CMIC_GP_INT_TYPE", CMIC_GP_INT_TYPEr }, \ 173 { 0x00002010, "CMIC_GP_INT_DE", CMIC_GP_INT_DEr }, \ 174 { 0x00002014, "CMIC_GP_INT_EDGE", CMIC_GP_INT_EDGEr }, \ 175 { 0x00002018, "CMIC_GP_INT_MSK", CMIC_GP_INT_MSKr }, \ 176 { 0x0000201c, "CMIC_GP_INT_STAT", CMIC_GP_INT_STATr }, \ 177 { 0x00002020, "CMIC_GP_INT_MSTAT", CMIC_GP_INT_MSTATr }, \ 178 { 0x00002024, "CMIC_GP_INT_CLR", CMIC_GP_INT_CLRr }, \ 179 { 0x00002028, "CMIC_GP_AUX_SEL", CMIC_GP_AUX_SELr }, \ 180 { 0x00002030, "CMIC_GP_INIT_VAL", CMIC_GP_INIT_VALr }, \ 181 { 0x00002034, "CMIC_GP_PAD_RES", CMIC_GP_PAD_RESr }, \ 182 { 0x00002038, "CMIC_GP_RES_EN", CMIC_GP_RES_ENr }, \ 183 { 0x0000203c, "CMIC_GP_TEST_INPUT", CMIC_GP_TEST_INPUTr }, \ 184 { 0x00002040, "CMIC_GP_TEST_OUTPUT", CMIC_GP_TEST_OUTPUTr }, \ 185 { 0x00002044, "CMIC_GP_TEST_ENABLE", CMIC_GP_TEST_ENABLEr }, \ 186 { 0x00002048, "CMIC_GP_PRB_ENABLE", CMIC_GP_PRB_ENABLEr }, \ 187 { 0x0000204c, "CMIC_GP_PRB_OE", CMIC_GP_PRB_OEr }, \ 188 { 0x00003000, "CMIC_UART0_RBR_THR_DLL", CMIC_UART0_RBR_THR_DLLr }, \ 189 { 0x00003004, "CMIC_UART0_DLH_IER", CMIC_UART0_DLH_IERr }, \ 190 { 0x00003008, "CMIC_UART0_IIR_FCR", CMIC_UART0_IIR_FCRr }, \ 191 { 0x0000300c, "CMIC_UART0_LCR", CMIC_UART0_LCRr }, \ 192 { 0x00003010, "CMIC_UART0_MCR", CMIC_UART0_MCRr }, \ 193 { 0x00003014, "CMIC_UART0_LSR", CMIC_UART0_LSRr }, \ 194 { 0x00003018, "CMIC_UART0_MSR", CMIC_UART0_MSRr }, \ 195 { 0x0000301c, "CMIC_UART0_SCR", CMIC_UART0_SCRr }, \ 196 { 0x00003020, "CMIC_UART0_LPDLL", CMIC_UART0_LPDLLr }, \ 197 { 0x00003024, "CMIC_UART0_LPDLH", CMIC_UART0_LPDLHr }, \ 198 { 0x00003030, "CMIC_UART0_SRBR_STHR", CMIC_UART0_SRBR_STHRr }, \ 199 { 0x00003070, "CMIC_UART0_FAR", CMIC_UART0_FARr }, \ 200 { 0x00003074, "CMIC_UART0_TFR", CMIC_UART0_TFRr }, \ 201 { 0x00003078, "CMIC_UART0_RFW", CMIC_UART0_RFWr }, \ 202 { 0x0000307c, "CMIC_UART0_USR", CMIC_UART0_USRr }, \ 203 { 0x00003080, "CMIC_UART0_TFL", CMIC_UART0_TFLr }, \ 204 { 0x00003084, "CMIC_UART0_RFL", CMIC_UART0_RFLr }, \ 205 { 0x00003088, "CMIC_UART0_SRR", CMIC_UART0_SRRr }, \ 206 { 0x0000308c, "CMIC_UART0_SRTS", CMIC_UART0_SRTSr }, \ 207 { 0x00003090, "CMIC_UART0_SBCR", CMIC_UART0_SBCRr }, \ 208 { 0x00003094, "CMIC_UART0_SDMAM", CMIC_UART0_SDMAMr }, \ 209 { 0x00003098, "CMIC_UART0_SFE", CMIC_UART0_SFEr }, \ 210 { 0x0000309c, "CMIC_UART0_SRT", CMIC_UART0_SRTr }, \ 211 { 0x000030a0, "CMIC_UART0_STET", CMIC_UART0_STETr }, \ 212 { 0x000030a4, "CMIC_UART0_HTX", CMIC_UART0_HTXr }, \ 213 { 0x000030a8, "CMIC_UART0_DMASA", CMIC_UART0_DMASAr }, \ 214 { 0x000030f4, "CMIC_UART0_CPR", CMIC_UART0_CPRr }, \ 215 { 0x000030f8, "CMIC_UART0_UCV", CMIC_UART0_UCVr }, \ 216 { 0x000030fc, "CMIC_UART0_CTR", CMIC_UART0_CTRr }, \ 217 { 0x00004000, "CMIC_UART1_RBR_THR_DLL", CMIC_UART1_RBR_THR_DLLr }, \ 218 { 0x00004004, "CMIC_UART1_DLH_IER", CMIC_UART1_DLH_IERr }, \ 219 { 0x00004008, "CMIC_UART1_IIR_FCR", CMIC_UART1_IIR_FCRr }, \ 220 { 0x0000400c, "CMIC_UART1_LCR", CMIC_UART1_LCRr }, \ 221 { 0x00004010, "CMIC_UART1_MCR", CMIC_UART1_MCRr }, \ 222 { 0x00004014, "CMIC_UART1_LSR", CMIC_UART1_LSRr }, \ 223 { 0x00004018, "CMIC_UART1_MSR", CMIC_UART1_MSRr }, \ 224 { 0x0000401c, "CMIC_UART1_SCR", CMIC_UART1_SCRr }, \ 225 { 0x00004020, "CMIC_UART1_LPDLL", CMIC_UART1_LPDLLr }, \ 226 { 0x00004024, "CMIC_UART1_LPDLH", CMIC_UART1_LPDLHr }, \ 227 { 0x00004030, "CMIC_UART1_SRBR_STHR", CMIC_UART1_SRBR_STHRr }, \ 228 { 0x00004070, "CMIC_UART1_FAR", CMIC_UART1_FARr }, \ 229 { 0x00004074, "CMIC_UART1_TFR", CMIC_UART1_TFRr }, \ 230 { 0x00004078, "CMIC_UART1_RFW", CMIC_UART1_RFWr }, \ 231 { 0x0000407c, "CMIC_UART1_USR", CMIC_UART1_USRr }, \ 232 { 0x00004080, "CMIC_UART1_TFL", CMIC_UART1_TFLr }, \ 233 { 0x00004084, "CMIC_UART1_RFL", CMIC_UART1_RFLr }, \ 234 { 0x00004088, "CMIC_UART1_SRR", CMIC_UART1_SRRr }, \ 235 { 0x0000408c, "CMIC_UART1_SRTS", CMIC_UART1_SRTSr }, \ 236 { 0x00004090, "CMIC_UART1_SBCR", CMIC_UART1_SBCRr }, \ 237 { 0x00004094, "CMIC_UART1_SDMAM", CMIC_UART1_SDMAMr }, \ 238 { 0x00004098, "CMIC_UART1_SFE", CMIC_UART1_SFEr }, \ 239 { 0x0000409c, "CMIC_UART1_SRT", CMIC_UART1_SRTr }, \ 240 { 0x000040a0, "CMIC_UART1_STET", CMIC_UART1_STETr }, \ 241 { 0x000040a4, "CMIC_UART1_HTX", CMIC_UART1_HTXr }, \ 242 { 0x000040a8, "CMIC_UART1_DMASA", CMIC_UART1_DMASAr }, \ 243 { 0x000040f4, "CMIC_UART1_CPR", CMIC_UART1_CPRr }, \ 244 { 0x000040f8, "CMIC_UART1_UCV", CMIC_UART1_UCVr }, \ 245 { 0x000040fc, "CMIC_UART1_CTR", CMIC_UART1_CTRr }, \ 246 { 0x00010000, "CMIC_COMMON_SCHAN_CTRL", CMIC_COMMON_SCHAN_CTRLr }, \ 247 { 0x00010004, "CMIC_COMMON_SCHAN_ACK_DATA_BEAT_COUNT", CMIC_COMMON_SCHAN_ACK_DATA_BEAT_COUNTr }, \ 248 { 0x00010008, "CMIC_COMMON_SCHAN_ERR", CMIC_COMMON_SCHAN_ERRr }, \ 249 { 0x0001000c, "CMIC_COMMON_SCHAN_MESSAGE", CMIC_COMMON_SCHAN_MESSAGEr }, \ 250 { 0x0001000c, "CMIC_COMMON_SCHAN_MESSAGE0", CMIC_COMMON_SCHAN_MESSAGE0r }, \ 251 { 0x00010010, "CMIC_COMMON_SCHAN_MESSAGE1", CMIC_COMMON_SCHAN_MESSAGE1r }, \ 252 { 0x00010014, "CMIC_COMMON_SCHAN_MESSAGE2", CMIC_COMMON_SCHAN_MESSAGE2r }, \ 253 { 0x00010018, "CMIC_COMMON_SCHAN_MESSAGE3", CMIC_COMMON_SCHAN_MESSAGE3r }, \ 254 { 0x0001001c, "CMIC_COMMON_SCHAN_MESSAGE4", CMIC_COMMON_SCHAN_MESSAGE4r }, \ 255 { 0x00010020, "CMIC_COMMON_SCHAN_MESSAGE5", CMIC_COMMON_SCHAN_MESSAGE5r }, \ 256 { 0x00010024, "CMIC_COMMON_SCHAN_MESSAGE6", CMIC_COMMON_SCHAN_MESSAGE6r }, \ 257 { 0x00010028, "CMIC_COMMON_SCHAN_MESSAGE7", CMIC_COMMON_SCHAN_MESSAGE7r }, \ 258 { 0x0001002c, "CMIC_COMMON_SCHAN_MESSAGE8", CMIC_COMMON_SCHAN_MESSAGE8r }, \ 259 { 0x00010030, "CMIC_COMMON_SCHAN_MESSAGE9", CMIC_COMMON_SCHAN_MESSAGE9r }, \ 260 { 0x00010034, "CMIC_COMMON_SCHAN_MESSAGE10", CMIC_COMMON_SCHAN_MESSAGE10r }, \ 261 { 0x00010038, "CMIC_COMMON_SCHAN_MESSAGE11", CMIC_COMMON_SCHAN_MESSAGE11r }, \ 262 { 0x0001003c, "CMIC_COMMON_SCHAN_MESSAGE12", CMIC_COMMON_SCHAN_MESSAGE12r }, \ 263 { 0x00010040, "CMIC_COMMON_SCHAN_MESSAGE13", CMIC_COMMON_SCHAN_MESSAGE13r }, \ 264 { 0x00010044, "CMIC_COMMON_SCHAN_MESSAGE14", CMIC_COMMON_SCHAN_MESSAGE14r }, \ 265 { 0x00010048, "CMIC_COMMON_SCHAN_MESSAGE15", CMIC_COMMON_SCHAN_MESSAGE15r }, \ 266 { 0x0001004c, "CMIC_COMMON_SCHAN_MESSAGE16", CMIC_COMMON_SCHAN_MESSAGE16r }, \ 267 { 0x00010050, "CMIC_COMMON_SCHAN_MESSAGE17", CMIC_COMMON_SCHAN_MESSAGE17r }, \ 268 { 0x00010054, "CMIC_COMMON_SCHAN_MESSAGE18", CMIC_COMMON_SCHAN_MESSAGE18r }, \ 269 { 0x00010058, "CMIC_COMMON_SCHAN_MESSAGE19", CMIC_COMMON_SCHAN_MESSAGE19r }, \ 270 { 0x0001005c, "CMIC_COMMON_SCHAN_MESSAGE20", CMIC_COMMON_SCHAN_MESSAGE20r }, \ 271 { 0x00010060, "CMIC_COMMON_SCHAN_MESSAGE21", CMIC_COMMON_SCHAN_MESSAGE21r }, \ 272 { 0x00010080, "CMIC_COMMON_MIIM_PARAM", CMIC_COMMON_MIIM_PARAMr }, \ 273 { 0x00010084, "CMIC_COMMON_MIIM_READ_DATA", CMIC_COMMON_MIIM_READ_DATAr }, \ 274 { 0x00010088, "CMIC_COMMON_MIIM_ADDRESS", CMIC_COMMON_MIIM_ADDRESSr }, \ 275 { 0x0001008c, "CMIC_COMMON_MIIM_CTRL", CMIC_COMMON_MIIM_CTRLr }, \ 276 { 0x00010090, "CMIC_COMMON_MIIM_STAT", CMIC_COMMON_MIIM_STATr }, \ 277 { 0x00010094, "CMIC_SBUS_TIMEOUT", CMIC_SBUS_TIMEOUTr }, \ 278 { 0x00010098, "CMIC_SBUS_RING_MAP_0_7", CMIC_SBUS_RING_MAP_0_7r }, \ 279 { 0x0001009c, "CMIC_SBUS_RING_MAP_8_15", CMIC_SBUS_RING_MAP_8_15r }, \ 280 { 0x000100a0, "CMIC_SBUS_RING_MAP_16_23", CMIC_SBUS_RING_MAP_16_23r }, \ 281 { 0x000100a4, "CMIC_SBUS_RING_MAP_24_31", CMIC_SBUS_RING_MAP_24_31r }, \ 282 { 0x000100a8, "CMIC_SBUS_RING_MAP_32_39", CMIC_SBUS_RING_MAP_32_39r }, \ 283 { 0x000100ac, "CMIC_SBUS_RING_MAP_40_47", CMIC_SBUS_RING_MAP_40_47r }, \ 284 { 0x000100b0, "CMIC_SBUS_RING_MAP_48_55", CMIC_SBUS_RING_MAP_48_55r }, \ 285 { 0x000100b4, "CMIC_SBUS_RING_MAP_56_63", CMIC_SBUS_RING_MAP_56_63r }, \ 286 { 0x000100b8, "CMIC_STAT_DMA_PORT_TYPE_MAP_0", CMIC_STAT_DMA_PORT_TYPE_MAP_0r }, \ 287 { 0x000100b8, "CMIC_SBUS_RING_MAP_64_71", CMIC_SBUS_RING_MAP_64_71r }, \ 288 { 0x000100bc, "CMIC_STAT_DMA_PORT_TYPE_MAP_1", CMIC_STAT_DMA_PORT_TYPE_MAP_1r }, \ 289 { 0x000100bc, "CMIC_SBUS_RING_MAP_72_79", CMIC_SBUS_RING_MAP_72_79r }, \ 290 { 0x000100c0, "CMIC_STAT_DMA_PORT_TYPE_MAP_2", CMIC_STAT_DMA_PORT_TYPE_MAP_2r }, \ 291 { 0x000100c0, "CMIC_SBUS_RING_MAP_80_87", CMIC_SBUS_RING_MAP_80_87r }, \ 292 { 0x000100c4, "CMIC_STAT_DMA_BLKNUM_MAP_4_0", CMIC_STAT_DMA_BLKNUM_MAP_4_0r }, \ 293 { 0x000100c4, "CMIC_SBUS_RING_MAP_88_95", CMIC_SBUS_RING_MAP_88_95r }, \ 294 { 0x000100c8, "CMIC_STAT_DMA_BLKNUM_MAP_9_5", CMIC_STAT_DMA_BLKNUM_MAP_9_5r }, \ 295 { 0x000100c8, "CMIC_SBUS_RING_MAP_96_103", CMIC_SBUS_RING_MAP_96_103r }, \ 296 { 0x000100cc, "CMIC_SBUS_RING_MAP_104_111", CMIC_SBUS_RING_MAP_104_111r }, \ 297 { 0x000100cc, "CMIC_STAT_DMA_BLKNUM_MAP_14_10", CMIC_STAT_DMA_BLKNUM_MAP_14_10r }, \ 298 { 0x000100d0, "CMIC_SBUS_RING_MAP_112_119", CMIC_SBUS_RING_MAP_112_119r }, \ 299 { 0x000100d0, "CMIC_STAT_DMA_BLKNUM_MAP_19_15", CMIC_STAT_DMA_BLKNUM_MAP_19_15r }, \ 300 { 0x000100d4, "CMIC_STAT_DMA_BLKNUM_MAP_24_20", CMIC_STAT_DMA_BLKNUM_MAP_24_20r }, \ 301 { 0x000100d4, "CMIC_SBUS_RING_MAP_120_127", CMIC_SBUS_RING_MAP_120_127r }, \ 302 { 0x000100d8, "CMIC_STAT_DMA_BLKNUM_MAP_29_25", CMIC_STAT_DMA_BLKNUM_MAP_29_25r }, \ 303 { 0x000100dc, "CMIC_STAT_DMA_BLKNUM_MAP_34_30", CMIC_STAT_DMA_BLKNUM_MAP_34_30r }, \ 304 { 0x000100e0, "CMIC_STAT_DMA_BLKNUM_MAP_39_35", CMIC_STAT_DMA_BLKNUM_MAP_39_35r }, \ 305 { 0x000100e4, "CMIC_STAT_DMA_BLKNUM_MAP_44_40", CMIC_STAT_DMA_BLKNUM_MAP_44_40r }, \ 306 { 0x000100e8, "CMIC_STAT_DMA_BLKNUM_MAP_49_45", CMIC_STAT_DMA_BLKNUM_MAP_49_45r }, \ 307 { 0x000100ec, "CMIC_STAT_DMA_BLKNUM_MAP_54_50", CMIC_STAT_DMA_BLKNUM_MAP_54_50r }, \ 308 { 0x000100f0, "CMIC_STAT_DMA_BLKNUM_MAP_59_55", CMIC_STAT_DMA_BLKNUM_MAP_59_55r }, \ 309 { 0x000100f4, "CMIC_STAT_DMA_BLKNUM_MAP_64_60", CMIC_STAT_DMA_BLKNUM_MAP_64_60r }, \ 310 { 0x000100f8, "CMIC_STAT_DMA_BLKNUM_MAP_69_65", CMIC_STAT_DMA_BLKNUM_MAP_69_65r }, \ 311 { 0x000100fc, "CMIC_STAT_DMA_BLKNUM_MAP_74_70", CMIC_STAT_DMA_BLKNUM_MAP_74_70r }, \ 312 { 0x00010100, "CMIC_STAT_DMA_BLKNUM_MAP_79_75", CMIC_STAT_DMA_BLKNUM_MAP_79_75r }, \ 313 { 0x00010104, "CMIC_STAT_DMA_BLKNUM_MAP_84_80", CMIC_STAT_DMA_BLKNUM_MAP_84_80r }, \ 314 { 0x00010108, "CMIC_STAT_DMA_BLKNUM_MAP_89_85", CMIC_STAT_DMA_BLKNUM_MAP_89_85r }, \ 315 { 0x0001010c, "CMIC_STAT_DMA_BLKNUM_MAP_94_90", CMIC_STAT_DMA_BLKNUM_MAP_94_90r }, \ 316 { 0x00010110, "CMIC_STAT_DMA_BLKNUM_MAP_95", CMIC_STAT_DMA_BLKNUM_MAP_95r }, \ 317 { 0x00010114, "CMIC_STAT_DMA_ING_STATS_CFG", CMIC_STAT_DMA_ING_STATS_CFGr }, \ 318 { 0x00010118, "CMIC_STAT_DMA_EGR_STATS_CFG", CMIC_STAT_DMA_EGR_STATS_CFGr }, \ 319 { 0x0001011c, "CMIC_STAT_DMA_MAC_STATS_CFG", CMIC_STAT_DMA_MAC_STATS_CFGr }, \ 320 { 0x00010120, "CMIC_STAT_DMA_PORTNUM_MAP_3_0", CMIC_STAT_DMA_PORTNUM_MAP_3_0r }, \ 321 { 0x00010124, "CMIC_STAT_DMA_PORTNUM_MAP_7_4", CMIC_STAT_DMA_PORTNUM_MAP_7_4r }, \ 322 { 0x00010128, "CMIC_STAT_DMA_PORTNUM_MAP_11_8", CMIC_STAT_DMA_PORTNUM_MAP_11_8r }, \ 323 { 0x0001012c, "CMIC_STAT_DMA_PORTNUM_MAP_15_12", CMIC_STAT_DMA_PORTNUM_MAP_15_12r }, \ 324 { 0x00010130, "CMIC_STAT_DMA_PORTNUM_MAP_19_16", CMIC_STAT_DMA_PORTNUM_MAP_19_16r }, \ 325 { 0x00010134, "CMIC_STAT_DMA_PORTNUM_MAP_23_20", CMIC_STAT_DMA_PORTNUM_MAP_23_20r }, \ 326 { 0x00010138, "CMIC_STAT_DMA_PORTNUM_MAP_27_24", CMIC_STAT_DMA_PORTNUM_MAP_27_24r }, \ 327 { 0x0001013c, "CMIC_STAT_DMA_PORTNUM_MAP_31_28", CMIC_STAT_DMA_PORTNUM_MAP_31_28r }, \ 328 { 0x00010140, "CMIC_STAT_DMA_PORTNUM_MAP_35_32", CMIC_STAT_DMA_PORTNUM_MAP_35_32r }, \ 329 { 0x00010144, "CMIC_STAT_DMA_PORTNUM_MAP_39_36", CMIC_STAT_DMA_PORTNUM_MAP_39_36r }, \ 330 { 0x00010148, "CMIC_STAT_DMA_PORTNUM_MAP_43_40", CMIC_STAT_DMA_PORTNUM_MAP_43_40r }, \ 331 { 0x0001014c, "CMIC_STAT_DMA_PORTNUM_MAP_47_44", CMIC_STAT_DMA_PORTNUM_MAP_47_44r }, \ 332 { 0x00010150, "CMIC_STAT_DMA_PORTNUM_MAP_51_48", CMIC_STAT_DMA_PORTNUM_MAP_51_48r }, \ 333 { 0x00010154, "CMIC_STAT_DMA_PORTNUM_MAP_55_52", CMIC_STAT_DMA_PORTNUM_MAP_55_52r }, \ 334 { 0x00010158, "CMIC_STAT_DMA_PORTNUM_MAP_59_56", CMIC_STAT_DMA_PORTNUM_MAP_59_56r }, \ 335 { 0x0001015c, "CMIC_STAT_DMA_PORTNUM_MAP_63_60", CMIC_STAT_DMA_PORTNUM_MAP_63_60r }, \ 336 { 0x00010160, "CMIC_STAT_DMA_PORTNUM_MAP_67_64", CMIC_STAT_DMA_PORTNUM_MAP_67_64r }, \ 337 { 0x00010164, "CMIC_STAT_DMA_PORTNUM_MAP_71_68", CMIC_STAT_DMA_PORTNUM_MAP_71_68r }, \ 338 { 0x00010168, "CMIC_STAT_DMA_PORTNUM_MAP_75_72", CMIC_STAT_DMA_PORTNUM_MAP_75_72r }, \ 339 { 0x0001016c, "CMIC_STAT_DMA_PORTNUM_MAP_79_76", CMIC_STAT_DMA_PORTNUM_MAP_79_76r }, \ 340 { 0x00010170, "CMIC_STAT_DMA_PORTNUM_MAP_83_80", CMIC_STAT_DMA_PORTNUM_MAP_83_80r }, \ 341 { 0x00010174, "CMIC_STAT_DMA_PORTNUM_MAP_87_84", CMIC_STAT_DMA_PORTNUM_MAP_87_84r }, \ 342 { 0x00010178, "CMIC_STAT_DMA_PORTNUM_MAP_91_88", CMIC_STAT_DMA_PORTNUM_MAP_91_88r }, \ 343 { 0x0001017c, "CMIC_STAT_DMA_PORTNUM_MAP_95_92", CMIC_STAT_DMA_PORTNUM_MAP_95_92r }, \ 344 { 0x00010188, "CMIC_SRAM_TM0_CONTROL", CMIC_SRAM_TM0_CONTROLr }, \ 345 { 0x0001018c, "CMIC_SRAM_TM1_CONTROL", CMIC_SRAM_TM1_CONTROLr }, \ 346 { 0x00010190, "CMIC_SRAM_TM2_CONTROL", CMIC_SRAM_TM2_CONTROLr }, \ 347 { 0x00010194, "CMICM_COMMON_CONFIG", CMICM_COMMON_CONFIGr }, \ 348 { 0x00010198, "CMIC_MISC_CONTROL", CMIC_MISC_CONTROLr }, \ 349 { 0x0001019c, "CMIC_MISC_STATUS", CMIC_MISC_STATUSr }, \ 350 { 0x000101a0, "CMIC_SRAM_TM3_CONTROL", CMIC_SRAM_TM3_CONTROLr }, \ 351 { 0x000101ec, "CMIC_COMMON_PCIE_PIO_ENDIANESS", CMIC_COMMON_PCIE_PIO_ENDIANESSr }, \ 352 { 0x000101f0, "CMIC_COMMON_UC0_PIO_ENDIANESS", CMIC_COMMON_UC0_PIO_ENDIANESSr }, \ 353 { 0x000101f4, "CMIC_COMMON_UC1_PIO_ENDIANESS", CMIC_COMMON_UC1_PIO_ENDIANESSr }, \ 354 { 0x000101f8, "CMIC_COMMON_SPI_PIO_ENDIANESS", CMIC_COMMON_SPI_PIO_ENDIANESSr }, \ 355 { 0x000101fc, "CMIC_COMMON_I2C_PIO_ENDIANESS", CMIC_COMMON_I2C_PIO_ENDIANESSr }, \ 356 { 0x00010200, "CMIC_COMMON_RPE_PIO_ENDIANESS", CMIC_COMMON_RPE_PIO_ENDIANESSr }, \ 357 { 0x00010204, "CMIC_PIO_MCS_ACCESS_PAGE", CMIC_PIO_MCS_ACCESS_PAGEr }, \ 358 { 0x00010208, "CMIC_PCIE_CONFIG", CMIC_PCIE_CONFIGr }, \ 359 { 0x0001020c, "CMIC_UC0_CONFIG", CMIC_UC0_CONFIGr }, \ 360 { 0x00010210, "CMIC_UC1_CONFIG", CMIC_UC1_CONFIGr }, \ 361 { 0x00010214, "CMIC_PCIE_ERROR_STATUS", CMIC_PCIE_ERROR_STATUSr }, \ 362 { 0x00010218, "CMIC_PCIE_ERROR_STATUS_CLR", CMIC_PCIE_ERROR_STATUS_CLRr }, \ 363 { 0x0001021c, "CMIC_SW_RST", CMIC_SW_RSTr }, \ 364 { 0x00010220, "CMIC_CPS_RESET", CMIC_CPS_RESETr }, \ 365 { 0x00010224, "CMIC_DEV_REV_ID", CMIC_DEV_REV_IDr }, \ 366 { 0x00010228, "CMICM_REVID", CMICM_REVIDr }, \ 367 { 0x00010230, "PCIE_RST_CONTROL", PCIE_RST_CONTROLr }, \ 368 { 0x00010234, "CMIC_OVERRIDE_STRAP", CMIC_OVERRIDE_STRAPr }, \ 369 { 0x00010238, "CMIC_COMMON_BSPI_BIGENDIAN", CMIC_COMMON_BSPI_BIGENDIANr }, \ 370 { 0x00010240, "CMIC_COMMON_STRAP_STATUS_0", CMIC_COMMON_STRAP_STATUS_0r }, \ 371 { 0x00010244, "CMIC_COMMON_STRAP_STATUS_1", CMIC_COMMON_STRAP_STATUS_1r }, \ 372 { 0x00010248, "CMIC_FSRF_STBY_CONTROL", CMIC_FSRF_STBY_CONTROLr }, \ 373 { 0x00010250, "CMIC_PCIE_USERIF_TIMEOUT", CMIC_PCIE_USERIF_TIMEOUTr }, \ 374 { 0x00010254, "CMIC_PCIE_USERIF_STATUS", CMIC_PCIE_USERIF_STATUSr }, \ 375 { 0x00010258, "CMIC_PCIE_USERIF_STATUS_CLR", CMIC_PCIE_USERIF_STATUS_CLRr }, \ 376 { 0x0001025c, "CMIC_PCIE_USERIF_STATUS_MASK", CMIC_PCIE_USERIF_STATUS_MASKr }, \ 377 { 0x00010260, "CMIC_PCIE_USERIF_PURGE_CONTROL", CMIC_PCIE_USERIF_PURGE_CONTROLr }, \ 378 { 0x00010264, "CMIC_PCIE_USERIF_PURGE_STATUS", CMIC_PCIE_USERIF_PURGE_STATUSr }, \ 379 { 0x00010268, "DMA_PCIE_BUF_MEM_CONTROL", DMA_PCIE_BUF_MEM_CONTROLr }, \ 380 { 0x0001026c, "DMA_MCS_BUF_MEM_CONTROL", DMA_MCS_BUF_MEM_CONTROLr }, \ 381 { 0x00010270, "PCIE_ADDR_MSB_63_TO_32", PCIE_ADDR_MSB_63_TO_32r }, \ 382 { 0x00010300, "CMIC_SEMAPHORE_1", CMIC_SEMAPHORE_1r }, \ 383 { 0x00010304, "CMIC_SEMAPHORE_1_SHADOW", CMIC_SEMAPHORE_1_SHADOWr }, \ 384 { 0x00010308, "CMIC_SEMAPHORE_2", CMIC_SEMAPHORE_2r }, \ 385 { 0x0001030c, "CMIC_SEMAPHORE_2_SHADOW", CMIC_SEMAPHORE_2_SHADOWr }, \ 386 { 0x00010310, "CMIC_SEMAPHORE_3", CMIC_SEMAPHORE_3r }, \ 387 { 0x00010314, "CMIC_SEMAPHORE_3_SHADOW", CMIC_SEMAPHORE_3_SHADOWr }, \ 388 { 0x00010318, "CMIC_SEMAPHORE_4", CMIC_SEMAPHORE_4r }, \ 389 { 0x0001031c, "CMIC_SEMAPHORE_4_SHADOW", CMIC_SEMAPHORE_4_SHADOWr }, \ 390 { 0x00010320, "CMIC_SEMAPHORE_5", CMIC_SEMAPHORE_5r }, \ 391 { 0x00010324, "CMIC_SEMAPHORE_5_SHADOW", CMIC_SEMAPHORE_5_SHADOWr }, \ 392 { 0x00010328, "CMIC_SEMAPHORE_6", CMIC_SEMAPHORE_6r }, \ 393 { 0x0001032c, "CMIC_SEMAPHORE_6_SHADOW", CMIC_SEMAPHORE_6_SHADOWr }, \ 394 { 0x00010330, "CMIC_SEMAPHORE_7", CMIC_SEMAPHORE_7r }, \ 395 { 0x00010334, "CMIC_SEMAPHORE_7_SHADOW", CMIC_SEMAPHORE_7_SHADOWr }, \ 396 { 0x00010338, "CMIC_SEMAPHORE_8", CMIC_SEMAPHORE_8r }, \ 397 { 0x0001033c, "CMIC_SEMAPHORE_8_SHADOW", CMIC_SEMAPHORE_8_SHADOWr }, \ 398 { 0x00010340, "CMIC_SEMAPHORE_9", CMIC_SEMAPHORE_9r }, \ 399 { 0x00010344, "CMIC_SEMAPHORE_9_SHADOW", CMIC_SEMAPHORE_9_SHADOWr }, \ 400 { 0x00010348, "CMIC_SEMAPHORE_10", CMIC_SEMAPHORE_10r }, \ 401 { 0x0001034c, "CMIC_SEMAPHORE_10_SHADOW", CMIC_SEMAPHORE_10_SHADOWr }, \ 402 { 0x00010350, "CMIC_SEMAPHORE_11", CMIC_SEMAPHORE_11r }, \ 403 { 0x00010354, "CMIC_SEMAPHORE_11_SHADOW", CMIC_SEMAPHORE_11_SHADOWr }, \ 404 { 0x00010358, "CMIC_SEMAPHORE_12", CMIC_SEMAPHORE_12r }, \ 405 { 0x0001035c, "CMIC_SEMAPHORE_12_SHADOW", CMIC_SEMAPHORE_12_SHADOWr }, \ 406 { 0x00010360, "CMIC_SEMAPHORE_13", CMIC_SEMAPHORE_13r }, \ 407 { 0x00010364, "CMIC_SEMAPHORE_13_SHADOW", CMIC_SEMAPHORE_13_SHADOWr }, \ 408 { 0x00010368, "CMIC_SEMAPHORE_14", CMIC_SEMAPHORE_14r }, \ 409 { 0x0001036c, "CMIC_SEMAPHORE_14_SHADOW", CMIC_SEMAPHORE_14_SHADOWr }, \ 410 { 0x00010370, "CMIC_SEMAPHORE_15", CMIC_SEMAPHORE_15r }, \ 411 { 0x00010374, "CMIC_SEMAPHORE_15_SHADOW", CMIC_SEMAPHORE_15_SHADOWr }, \ 412 { 0x00010378, "CMIC_SEMAPHORE_16", CMIC_SEMAPHORE_16r }, \ 413 { 0x0001037c, "CMIC_SEMAPHORE_16_SHADOW", CMIC_SEMAPHORE_16_SHADOWr }, \ 414 { 0x00010380, "CMIC_SEMAPHORE_17", CMIC_SEMAPHORE_17r }, \ 415 { 0x00010384, "CMIC_SEMAPHORE_17_SHADOW", CMIC_SEMAPHORE_17_SHADOWr }, \ 416 { 0x00010388, "CMIC_SEMAPHORE_18", CMIC_SEMAPHORE_18r }, \ 417 { 0x0001038c, "CMIC_SEMAPHORE_18_SHADOW", CMIC_SEMAPHORE_18_SHADOWr }, \ 418 { 0x00010390, "CMIC_SEMAPHORE_19", CMIC_SEMAPHORE_19r }, \ 419 { 0x00010394, "CMIC_SEMAPHORE_19_SHADOW", CMIC_SEMAPHORE_19_SHADOWr }, \ 420 { 0x00010398, "CMIC_SEMAPHORE_20", CMIC_SEMAPHORE_20r }, \ 421 { 0x0001039c, "CMIC_SEMAPHORE_20_SHADOW", CMIC_SEMAPHORE_20_SHADOWr }, \ 422 { 0x000103a0, "CMIC_SEMAPHORE_21", CMIC_SEMAPHORE_21r }, \ 423 { 0x000103a4, "CMIC_SEMAPHORE_21_SHADOW", CMIC_SEMAPHORE_21_SHADOWr }, \ 424 { 0x000103a8, "CMIC_SEMAPHORE_22", CMIC_SEMAPHORE_22r }, \ 425 { 0x000103ac, "CMIC_SEMAPHORE_22_SHADOW", CMIC_SEMAPHORE_22_SHADOWr }, \ 426 { 0x000103b0, "CMIC_SEMAPHORE_23", CMIC_SEMAPHORE_23r }, \ 427 { 0x000103b4, "CMIC_SEMAPHORE_23_SHADOW", CMIC_SEMAPHORE_23_SHADOWr }, \ 428 { 0x000103b8, "CMIC_SEMAPHORE_24", CMIC_SEMAPHORE_24r }, \ 429 { 0x000103bc, "CMIC_SEMAPHORE_24_SHADOW", CMIC_SEMAPHORE_24_SHADOWr }, \ 430 { 0x000103c0, "CMIC_SEMAPHORE_25", CMIC_SEMAPHORE_25r }, \ 431 { 0x000103c4, "CMIC_SEMAPHORE_25_SHADOW", CMIC_SEMAPHORE_25_SHADOWr }, \ 432 { 0x000103c8, "CMIC_SEMAPHORE_26", CMIC_SEMAPHORE_26r }, \ 433 { 0x000103cc, "CMIC_SEMAPHORE_26_SHADOW", CMIC_SEMAPHORE_26_SHADOWr }, \ 434 { 0x000103d0, "CMIC_SEMAPHORE_27", CMIC_SEMAPHORE_27r }, \ 435 { 0x000103d4, "CMIC_SEMAPHORE_27_SHADOW", CMIC_SEMAPHORE_27_SHADOWr }, \ 436 { 0x000103d8, "CMIC_SEMAPHORE_28", CMIC_SEMAPHORE_28r }, \ 437 { 0x000103dc, "CMIC_SEMAPHORE_28_SHADOW", CMIC_SEMAPHORE_28_SHADOWr }, \ 438 { 0x000103e0, "CMIC_SEMAPHORE_29", CMIC_SEMAPHORE_29r }, \ 439 { 0x000103e4, "CMIC_SEMAPHORE_29_SHADOW", CMIC_SEMAPHORE_29_SHADOWr }, \ 440 { 0x000103e8, "CMIC_SEMAPHORE_30", CMIC_SEMAPHORE_30r }, \ 441 { 0x000103ec, "CMIC_SEMAPHORE_30_SHADOW", CMIC_SEMAPHORE_30_SHADOWr }, \ 442 { 0x000103f0, "CMIC_SEMAPHORE_31", CMIC_SEMAPHORE_31r }, \ 443 { 0x000103f4, "CMIC_SEMAPHORE_31_SHADOW", CMIC_SEMAPHORE_31_SHADOWr }, \ 444 { 0x000103f8, "CMIC_SEMAPHORE_32", CMIC_SEMAPHORE_32r }, \ 445 { 0x000103fc, "CMIC_SEMAPHORE_32_SHADOW", CMIC_SEMAPHORE_32_SHADOWr }, \ 446 { 0x00010400, "CMIC_TS_FREQ_CTRL_LOWER", CMIC_TS_FREQ_CTRL_LOWERr }, \ 447 { 0x00010404, "CMIC_TS_FREQ_CTRL_UPPER", CMIC_TS_FREQ_CTRL_UPPERr }, \ 448 { 0x00010408, "CMIC_TS_TIME_CAPTURE_CTRL", CMIC_TS_TIME_CAPTURE_CTRLr }, \ 449 { 0x0001040c, "CMIC_TS_INPUT_TIME_FIFO_TS", CMIC_TS_INPUT_TIME_FIFO_TSr }, \ 450 { 0x00010410, "CMIC_TS_INPUT_TIME_FIFO_ID", CMIC_TS_INPUT_TIME_FIFO_IDr }, \ 451 { 0x00010414, "CMIC_TS_CAPTURE_STATUS", CMIC_TS_CAPTURE_STATUSr }, \ 452 { 0x00010418, "CMIC_TS_CAPTURE_STATUS_CLR", CMIC_TS_CAPTURE_STATUS_CLRr }, \ 453 { 0x0001041c, "CMIC_TS_FIFO_STATUS", CMIC_TS_FIFO_STATUSr }, \ 454 { 0x00010420, "CMIC_TS_GPIO_1_CTRL", CMIC_TS_GPIO_1_CTRLr }, \ 455 { 0x00010424, "CMIC_TS_GPIO_1_UP_EVENT_CTRL", CMIC_TS_GPIO_1_UP_EVENT_CTRLr }, \ 456 { 0x00010428, "CMIC_TS_GPIO_1_DOWN_EVENT_CTRL", CMIC_TS_GPIO_1_DOWN_EVENT_CTRLr }, \ 457 { 0x0001042c, "CMIC_TS_GPIO_2_CTRL", CMIC_TS_GPIO_2_CTRLr }, \ 458 { 0x00010430, "CMIC_TS_GPIO_2_UP_EVENT_CTRL", CMIC_TS_GPIO_2_UP_EVENT_CTRLr }, \ 459 { 0x00010434, "CMIC_TS_GPIO_2_DOWN_EVENT_CTRL", CMIC_TS_GPIO_2_DOWN_EVENT_CTRLr }, \ 460 { 0x00010438, "CMIC_TS_GPIO_3_CTRL", CMIC_TS_GPIO_3_CTRLr }, \ 461 { 0x0001043c, "CMIC_TS_GPIO_3_UP_EVENT_CTRL", CMIC_TS_GPIO_3_UP_EVENT_CTRLr }, \ 462 { 0x00010440, "CMIC_TS_GPIO_3_DOWN_EVENT_CTRL", CMIC_TS_GPIO_3_DOWN_EVENT_CTRLr }, \ 463 { 0x00010444, "CMIC_TS_GPIO_4_CTRL", CMIC_TS_GPIO_4_CTRLr }, \ 464 { 0x00010448, "CMIC_TS_GPIO_4_UP_EVENT_CTRL", CMIC_TS_GPIO_4_UP_EVENT_CTRLr }, \ 465 { 0x0001044c, "CMIC_TS_GPIO_4_DOWN_EVENT_CTRL", CMIC_TS_GPIO_4_DOWN_EVENT_CTRLr }, \ 466 { 0x00010450, "CMIC_TS_GPIO_5_CTRL", CMIC_TS_GPIO_5_CTRLr }, \ 467 { 0x00010454, "CMIC_TS_GPIO_5_UP_EVENT_CTRL", CMIC_TS_GPIO_5_UP_EVENT_CTRLr }, \ 468 { 0x00010458, "CMIC_TS_GPIO_5_DOWN_EVENT_CTRL", CMIC_TS_GPIO_5_DOWN_EVENT_CTRLr }, \ 469 { 0x0001045c, "CMIC_TS_GPIO_6_CTRL", CMIC_TS_GPIO_6_CTRLr }, \ 470 { 0x00010460, "CMIC_TS_GPIO_6_UP_EVENT_CTRL", CMIC_TS_GPIO_6_UP_EVENT_CTRLr }, \ 471 { 0x00010464, "CMIC_TS_GPIO_6_DOWN_EVENT_CTRL", CMIC_TS_GPIO_6_DOWN_EVENT_CTRLr }, \ 472 { 0x00010468, "CMIC_TS_L1_CLK_RECOVERED_CLK_COUNT_CTRL", CMIC_TS_L1_CLK_RECOVERED_CLK_COUNT_CTRLr }, \ 473 { 0x0001046c, "CMIC_TS_L1_CLK_RECOVERED_CLK_BKUP_COUNT_CTRL", CMIC_TS_L1_CLK_RECOVERED_CLK_BKUP_COUNT_CTRLr }, \ 474 { 0x00010470, "CMIC_TS_LCPLL_CLK_COUNT_CTRL", CMIC_TS_LCPLL_CLK_COUNT_CTRLr }, \ 475 { 0x00010474, "CMIC_BS_REF_CLK_GEN_CTRL", CMIC_BS_REF_CLK_GEN_CTRLr }, \ 476 { 0x00010478, "CMIC_TS_GPIO_1_OUTPUT_ENABLE", CMIC_TS_GPIO_1_OUTPUT_ENABLEr }, \ 477 { 0x0001047c, "CMIC_TS_GPIO_1_PHASE_ADJUST", CMIC_TS_GPIO_1_PHASE_ADJUSTr }, \ 478 { 0x00010480, "CMIC_TS_GPIO_2_OUTPUT_ENABLE", CMIC_TS_GPIO_2_OUTPUT_ENABLEr }, \ 479 { 0x00010484, "CMIC_TS_GPIO_2_PHASE_ADJUST", CMIC_TS_GPIO_2_PHASE_ADJUSTr }, \ 480 { 0x00010488, "CMIC_TS_GPIO_3_OUTPUT_ENABLE", CMIC_TS_GPIO_3_OUTPUT_ENABLEr }, \ 481 { 0x0001048c, "CMIC_TS_GPIO_3_PHASE_ADJUST", CMIC_TS_GPIO_3_PHASE_ADJUSTr }, \ 482 { 0x00010490, "CMIC_TS_GPIO_4_OUTPUT_ENABLE", CMIC_TS_GPIO_4_OUTPUT_ENABLEr }, \ 483 { 0x00010494, "CMIC_TS_GPIO_4_PHASE_ADJUST", CMIC_TS_GPIO_4_PHASE_ADJUSTr }, \ 484 { 0x00010498, "CMIC_TS_GPIO_5_OUTPUT_ENABLE", CMIC_TS_GPIO_5_OUTPUT_ENABLEr }, \ 485 { 0x0001049c, "CMIC_TS_GPIO_5_PHASE_ADJUST", CMIC_TS_GPIO_5_PHASE_ADJUSTr }, \ 486 { 0x000104a0, "CMIC_TS_GPIO_6_OUTPUT_ENABLE", CMIC_TS_GPIO_6_OUTPUT_ENABLEr }, \ 487 { 0x000104a4, "CMIC_TS_GPIO_6_PHASE_ADJUST", CMIC_TS_GPIO_6_PHASE_ADJUSTr }, \ 488 { 0x000104b0, "TD2P_CMIC_TIMESYNC_TM", TD2P_CMIC_TIMESYNC_TMr }, \ 489 { 0x00010500, "CMIC_BS_CONFIG", CMIC_BS_CONFIGr }, \ 490 { 0x00010504, "CMIC_BS_CLK_CTRL", CMIC_BS_CLK_CTRLr }, \ 491 { 0x00010508, "CMIC_BS_HEARTBEAT_CTRL", CMIC_BS_HEARTBEAT_CTRLr }, \ 492 { 0x0001050c, "CMIC_BS_HEARTBEAT_UP_DURATION", CMIC_BS_HEARTBEAT_UP_DURATIONr }, \ 493 { 0x00010510, "CMIC_BS_HEARTBEAT_DOWN_DURATION", CMIC_BS_HEARTBEAT_DOWN_DURATIONr }, \ 494 { 0x00010514, "CMIC_BS_OUTPUT_TIME_0", CMIC_BS_OUTPUT_TIME_0r }, \ 495 { 0x00010518, "CMIC_BS_OUTPUT_TIME_1", CMIC_BS_OUTPUT_TIME_1r }, \ 496 { 0x0001051c, "CMIC_BS_OUTPUT_TIME_2", CMIC_BS_OUTPUT_TIME_2r }, \ 497 { 0x00010520, "CMIC_BS_INPUT_TIME_0", CMIC_BS_INPUT_TIME_0r }, \ 498 { 0x00010524, "CMIC_BS_INPUT_TIME_1", CMIC_BS_INPUT_TIME_1r }, \ 499 { 0x00010528, "CMIC_BS_INPUT_TIME_2", CMIC_BS_INPUT_TIME_2r }, \ 500 { 0x0001052c, "CMIC_BS_INITIAL_CRC", CMIC_BS_INITIAL_CRCr }, \ 501 { 0x00010600, "CMIC_TIMESYNC_COUNTER_CONFIG_SELECT", CMIC_TIMESYNC_COUNTER_CONFIG_SELECTr }, \ 502 { 0x00010604, "CMIC_TIMESYNC_TS0_COUNTER_ENABLE", CMIC_TIMESYNC_TS0_COUNTER_ENABLEr }, \ 503 { 0x00010608, "CMIC_TIMESYNC_TS0_FREQ_CTRL_FRAC", CMIC_TIMESYNC_TS0_FREQ_CTRL_FRACr }, \ 504 { 0x0001060c, "CMIC_TIMESYNC_TS0_FREQ_CTRL_LOWER", CMIC_TIMESYNC_TS0_FREQ_CTRL_LOWERr }, \ 505 { 0x00010610, "CMIC_TIMESYNC_TS0_FREQ_CTRL_UPPER", CMIC_TIMESYNC_TS0_FREQ_CTRL_UPPERr }, \ 506 { 0x00010614, "CMIC_TIMESYNC_TS1_COUNTER_ENABLE", CMIC_TIMESYNC_TS1_COUNTER_ENABLEr }, \ 507 { 0x00010618, "CMIC_TIMESYNC_TS1_FREQ_CTRL_FRAC", CMIC_TIMESYNC_TS1_FREQ_CTRL_FRACr }, \ 508 { 0x0001061c, "CMIC_TIMESYNC_TS1_FREQ_CTRL_LOWER", CMIC_TIMESYNC_TS1_FREQ_CTRL_LOWERr }, \ 509 { 0x00010620, "CMIC_TIMESYNC_TS1_FREQ_CTRL_UPPER", CMIC_TIMESYNC_TS1_FREQ_CTRL_UPPERr }, \ 510 { 0x00010624, "CMIC_TIMESYNC_TIME_CAPTURE_MODE", CMIC_TIMESYNC_TIME_CAPTURE_MODEr }, \ 511 { 0x0001062c, "CMIC_TIMESYNC_INPUT_TIME_FIFO_TS_LOWER", CMIC_TIMESYNC_INPUT_TIME_FIFO_TS_LOWERr }, \ 512 { 0x00010630, "CMIC_TIMESYNC_INPUT_TIME_FIFO_TS_UPPER", CMIC_TIMESYNC_INPUT_TIME_FIFO_TS_UPPERr }, \ 513 { 0x0001063c, "CMIC_TIMESYNC_FIFO_STATUS", CMIC_TIMESYNC_FIFO_STATUSr }, \ 514 { 0x00010640, "CMIC_TIMESYNC_GPIO_0_CTRL", CMIC_TIMESYNC_GPIO_0_CTRLr }, \ 515 { 0x00010644, "CMIC_TIMESYNC_GPIO_0_OUTPUT_ENABLE", CMIC_TIMESYNC_GPIO_0_OUTPUT_ENABLEr }, \ 516 { 0x00010648, "CMIC_TIMESYNC_GPIO_0_UP_EVENT_CTRL", CMIC_TIMESYNC_GPIO_0_UP_EVENT_CTRLr }, \ 517 { 0x0001064c, "CMIC_TIMESYNC_GPIO_0_DOWN_EVENT_CTRL", CMIC_TIMESYNC_GPIO_0_DOWN_EVENT_CTRLr }, \ 518 { 0x00010650, "CMIC_TIMESYNC_GPIO_0_PHASE_ADJUST_LOWER", CMIC_TIMESYNC_GPIO_0_PHASE_ADJUST_LOWERr }, \ 519 { 0x00010654, "CMIC_TIMESYNC_GPIO_0_PHASE_ADJUST_UPPER", CMIC_TIMESYNC_GPIO_0_PHASE_ADJUST_UPPERr }, \ 520 { 0x00010658, "CMIC_TIMESYNC_GPIO_0_INPUT_DIVISOR", CMIC_TIMESYNC_GPIO_0_INPUT_DIVISORr }, \ 521 { 0x0001065c, "CMIC_TIMESYNC_GPIO_1_CTRL", CMIC_TIMESYNC_GPIO_1_CTRLr }, \ 522 { 0x00010660, "CMIC_TIMESYNC_GPIO_1_OUTPUT_ENABLE", CMIC_TIMESYNC_GPIO_1_OUTPUT_ENABLEr }, \ 523 { 0x00010664, "CMIC_TIMESYNC_GPIO_1_UP_EVENT_CTRL", CMIC_TIMESYNC_GPIO_1_UP_EVENT_CTRLr }, \ 524 { 0x00010668, "CMIC_TIMESYNC_GPIO_1_DOWN_EVENT_CTRL", CMIC_TIMESYNC_GPIO_1_DOWN_EVENT_CTRLr }, \ 525 { 0x0001066c, "CMIC_TIMESYNC_GPIO_1_PHASE_ADJUST_LOWER", CMIC_TIMESYNC_GPIO_1_PHASE_ADJUST_LOWERr }, \ 526 { 0x00010670, "CMIC_TIMESYNC_GPIO_1_PHASE_ADJUST_UPPER", CMIC_TIMESYNC_GPIO_1_PHASE_ADJUST_UPPERr }, \ 527 { 0x00010674, "CMIC_TIMESYNC_GPIO_1_INPUT_DIVISOR", CMIC_TIMESYNC_GPIO_1_INPUT_DIVISORr }, \ 528 { 0x00010678, "CMIC_TIMESYNC_GPIO_2_CTRL", CMIC_TIMESYNC_GPIO_2_CTRLr }, \ 529 { 0x0001067c, "CMIC_TIMESYNC_GPIO_2_OUTPUT_ENABLE", CMIC_TIMESYNC_GPIO_2_OUTPUT_ENABLEr }, \ 530 { 0x00010680, "CMIC_TIMESYNC_GPIO_2_UP_EVENT_CTRL", CMIC_TIMESYNC_GPIO_2_UP_EVENT_CTRLr }, \ 531 { 0x00010684, "CMIC_TIMESYNC_GPIO_2_DOWN_EVENT_CTRL", CMIC_TIMESYNC_GPIO_2_DOWN_EVENT_CTRLr }, \ 532 { 0x00010688, "CMIC_TIMESYNC_GPIO_2_PHASE_ADJUST_LOWER", CMIC_TIMESYNC_GPIO_2_PHASE_ADJUST_LOWERr }, \ 533 { 0x0001068c, "CMIC_TIMESYNC_GPIO_2_PHASE_ADJUST_UPPER", CMIC_TIMESYNC_GPIO_2_PHASE_ADJUST_UPPERr }, \ 534 { 0x00010690, "CMIC_TIMESYNC_GPIO_2_INPUT_DIVISOR", CMIC_TIMESYNC_GPIO_2_INPUT_DIVISORr }, \ 535 { 0x00010694, "CMIC_TIMESYNC_GPIO_3_CTRL", CMIC_TIMESYNC_GPIO_3_CTRLr }, \ 536 { 0x00010698, "CMIC_TIMESYNC_GPIO_3_OUTPUT_ENABLE", CMIC_TIMESYNC_GPIO_3_OUTPUT_ENABLEr }, \ 537 { 0x0001069c, "CMIC_TIMESYNC_GPIO_3_UP_EVENT_CTRL", CMIC_TIMESYNC_GPIO_3_UP_EVENT_CTRLr }, \ 538 { 0x000106a0, "CMIC_TIMESYNC_GPIO_3_DOWN_EVENT_CTRL", CMIC_TIMESYNC_GPIO_3_DOWN_EVENT_CTRLr }, \ 539 { 0x000106a4, "CMIC_TIMESYNC_GPIO_3_PHASE_ADJUST_LOWER", CMIC_TIMESYNC_GPIO_3_PHASE_ADJUST_LOWERr }, \ 540 { 0x000106a8, "CMIC_TIMESYNC_GPIO_3_PHASE_ADJUST_UPPER", CMIC_TIMESYNC_GPIO_3_PHASE_ADJUST_UPPERr }, \ 541 { 0x000106ac, "CMIC_TIMESYNC_GPIO_3_INPUT_DIVISOR", CMIC_TIMESYNC_GPIO_3_INPUT_DIVISORr }, \ 542 { 0x000106b0, "CMIC_TIMESYNC_GPIO_4_CTRL", CMIC_TIMESYNC_GPIO_4_CTRLr }, \ 543 { 0x000106b4, "CMIC_TIMESYNC_GPIO_4_OUTPUT_ENABLE", CMIC_TIMESYNC_GPIO_4_OUTPUT_ENABLEr }, \ 544 { 0x000106b8, "CMIC_TIMESYNC_GPIO_4_UP_EVENT_CTRL", CMIC_TIMESYNC_GPIO_4_UP_EVENT_CTRLr }, \ 545 { 0x000106bc, "CMIC_TIMESYNC_GPIO_4_DOWN_EVENT_CTRL", CMIC_TIMESYNC_GPIO_4_DOWN_EVENT_CTRLr }, \ 546 { 0x000106c0, "CMIC_TIMESYNC_GPIO_4_PHASE_ADJUST_LOWER", CMIC_TIMESYNC_GPIO_4_PHASE_ADJUST_LOWERr }, \ 547 { 0x000106c4, "CMIC_TIMESYNC_GPIO_4_PHASE_ADJUST_UPPER", CMIC_TIMESYNC_GPIO_4_PHASE_ADJUST_UPPERr }, \ 548 { 0x000106c8, "CMIC_TIMESYNC_GPIO_4_INPUT_DIVISOR", CMIC_TIMESYNC_GPIO_4_INPUT_DIVISORr }, \ 549 { 0x000106cc, "CMIC_TIMESYNC_GPIO_5_CTRL", CMIC_TIMESYNC_GPIO_5_CTRLr }, \ 550 { 0x000106d0, "CMIC_TIMESYNC_GPIO_5_OUTPUT_ENABLE", CMIC_TIMESYNC_GPIO_5_OUTPUT_ENABLEr }, \ 551 { 0x000106d4, "CMIC_TIMESYNC_GPIO_5_UP_EVENT_CTRL", CMIC_TIMESYNC_GPIO_5_UP_EVENT_CTRLr }, \ 552 { 0x000106d8, "CMIC_TIMESYNC_GPIO_5_DOWN_EVENT_CTRL", CMIC_TIMESYNC_GPIO_5_DOWN_EVENT_CTRLr }, \ 553 { 0x000106dc, "CMIC_TIMESYNC_GPIO_5_PHASE_ADJUST_LOWER", CMIC_TIMESYNC_GPIO_5_PHASE_ADJUST_LOWERr }, \ 554 { 0x000106e0, "CMIC_TIMESYNC_GPIO_5_PHASE_ADJUST_UPPER", CMIC_TIMESYNC_GPIO_5_PHASE_ADJUST_UPPERr }, \ 555 { 0x000106e4, "CMIC_TIMESYNC_GPIO_5_INPUT_DIVISOR", CMIC_TIMESYNC_GPIO_5_INPUT_DIVISORr }, \ 556 { 0x000106e8, "CMIC_TIMESYNC_SYNCE_CLK1_COUNT_CTRL", CMIC_TIMESYNC_SYNCE_CLK1_COUNT_CTRLr }, \ 557 { 0x000106ec, "CMIC_TIMESYNC_SYNCE_CLK2_COUNT_CTRL", CMIC_TIMESYNC_SYNCE_CLK2_COUNT_CTRLr }, \ 558 { 0x000106f0, "CMIC_TIMESYNC_SYNCE_CLK3_COUNT_CTRL", CMIC_TIMESYNC_SYNCE_CLK3_COUNT_CTRLr }, \ 559 { 0x000106f4, "CMIC_TIMESYNC_SYNCE_CLK4_COUNT_CTRL", CMIC_TIMESYNC_SYNCE_CLK4_COUNT_CTRLr }, \ 560 { 0x000106f8, "CMIC_TIMESYNC_SYNCE_CLK5_COUNT_CTRL", CMIC_TIMESYNC_SYNCE_CLK5_COUNT_CTRLr }, \ 561 { 0x000106fc, "CMIC_BROADSYNC_REF_CLK_GEN_CTRL", CMIC_BROADSYNC_REF_CLK_GEN_CTRLr }, \ 562 { 0x00010700, "CMIC_BS0_CONFIG", CMIC_BS0_CONFIGr }, \ 563 { 0x00010704, "CMIC_BS0_CLK_CTRL", CMIC_BS0_CLK_CTRLr }, \ 564 { 0x00010708, "CMIC_BS0_HEARTBEAT_CTRL", CMIC_BS0_HEARTBEAT_CTRLr }, \ 565 { 0x0001070c, "CMIC_BS0_HEARTBEAT_UP_DURATION", CMIC_BS0_HEARTBEAT_UP_DURATIONr }, \ 566 { 0x00010710, "CMIC_BS0_HEARTBEAT_DOWN_DURATION", CMIC_BS0_HEARTBEAT_DOWN_DURATIONr }, \ 567 { 0x00010714, "CMIC_BS0_OUTPUT_TIME_0", CMIC_BS0_OUTPUT_TIME_0r }, \ 568 { 0x00010718, "CMIC_BS0_OUTPUT_TIME_1", CMIC_BS0_OUTPUT_TIME_1r }, \ 569 { 0x0001071c, "CMIC_BS0_OUTPUT_TIME_2", CMIC_BS0_OUTPUT_TIME_2r }, \ 570 { 0x00010720, "CMIC_BS0_INPUT_TIME_0", CMIC_BS0_INPUT_TIME_0r }, \ 571 { 0x00010724, "CMIC_BS0_INPUT_TIME_1", CMIC_BS0_INPUT_TIME_1r }, \ 572 { 0x00010728, "CMIC_BS0_INPUT_TIME_2", CMIC_BS0_INPUT_TIME_2r }, \ 573 { 0x0001072c, "CMIC_BS0_INITIAL_CRC", CMIC_BS0_INITIAL_CRCr }, \ 574 { 0x00010800, "CMIC_BS1_CONFIG", CMIC_BS1_CONFIGr }, \ 575 { 0x00010804, "CMIC_BS1_CLK_CTRL", CMIC_BS1_CLK_CTRLr }, \ 576 { 0x00010808, "CMIC_BS1_HEARTBEAT_CTRL", CMIC_BS1_HEARTBEAT_CTRLr }, \ 577 { 0x0001080c, "CMIC_BS1_HEARTBEAT_UP_DURATION", CMIC_BS1_HEARTBEAT_UP_DURATIONr }, \ 578 { 0x00010810, "CMIC_BS1_HEARTBEAT_DOWN_DURATION", CMIC_BS1_HEARTBEAT_DOWN_DURATIONr }, \ 579 { 0x00010814, "CMIC_BS1_OUTPUT_TIME_0", CMIC_BS1_OUTPUT_TIME_0r }, \ 580 { 0x00010818, "CMIC_BS1_OUTPUT_TIME_1", CMIC_BS1_OUTPUT_TIME_1r }, \ 581 { 0x0001081c, "CMIC_BS1_OUTPUT_TIME_2", CMIC_BS1_OUTPUT_TIME_2r }, \ 582 { 0x00010820, "CMIC_BS1_INPUT_TIME_0", CMIC_BS1_INPUT_TIME_0r }, \ 583 { 0x00010824, "CMIC_BS1_INPUT_TIME_1", CMIC_BS1_INPUT_TIME_1r }, \ 584 { 0x00010828, "CMIC_BS1_INPUT_TIME_2", CMIC_BS1_INPUT_TIME_2r }, \ 585 { 0x0001082c, "CMIC_BS1_INITIAL_CRC", CMIC_BS1_INITIAL_CRCr }, \ 586 { 0x00010900, "CMIC_TIMESYNC_BROADSYNC0_CLK_COUNT_CTRL", CMIC_TIMESYNC_BROADSYNC0_CLK_COUNT_CTRLr }, \ 587 { 0x00010904, "CMIC_TIMESYNC_BROADSYNC1_CLK_COUNT_CTRL", CMIC_TIMESYNC_BROADSYNC1_CLK_COUNT_CTRLr }, \ 588 { 0x00010908, "CMIC_TIMESYNC_TIME_CAPTURE_CONTROL", CMIC_TIMESYNC_TIME_CAPTURE_CONTROLr }, \ 589 { 0x0001090c, "CMIC_TIMESYNC_CAPTURE_STATUS_1", CMIC_TIMESYNC_CAPTURE_STATUS_1r }, \ 590 { 0x00010910, "CMIC_TIMESYNC_CAPTURE_STATUS_CLR_1", CMIC_TIMESYNC_CAPTURE_STATUS_CLR_1r }, \ 591 { 0x00010914, "CMIC_TIMESYNC_INTERRUPT_ENABLE", CMIC_TIMESYNC_INTERRUPT_ENABLEr }, \ 592 { 0x00010918, "CMIC_TIMESYNC_INTERRUPT_STATUS", CMIC_TIMESYNC_INTERRUPT_STATUSr }, \ 593 { 0x0001091c, "CMIC_TIMESYNC_INTERRUPT_CLR", CMIC_TIMESYNC_INTERRUPT_CLRr }, \ 594 { 0x00010920, "CMIC_TIMESYNC_TM", CMIC_TIMESYNC_TMr }, \ 595 { 0x00010924, "CMIC_TIMESYNC_FIFO_ECC_CONFIG", CMIC_TIMESYNC_FIFO_ECC_CONFIGr }, \ 596 { 0x00010928, "CMIC_TIMESYNC_FIFO_ECC_STATUS", CMIC_TIMESYNC_FIFO_ECC_STATUSr }, \ 597 { 0x00011000, "CMIC_RATE_ADJUST_EXT_MDIO", CMIC_RATE_ADJUST_EXT_MDIOr }, \ 598 { 0x00011000, "CMIC_RATE_ADJUST", CMIC_RATE_ADJUSTr }, \ 599 { 0x00011004, "CMIC_RATE_ADJUST_INT_MDIO", CMIC_RATE_ADJUST_INT_MDIOr }, \ 600 { 0x00011008, "CMIC_MIIM_SCAN_CTRL", CMIC_MIIM_SCAN_CTRLr }, \ 601 { 0x0001100c, "CMIC_MIIM_SCAN_STATUS", CMIC_MIIM_SCAN_STATUSr }, \ 602 { 0x00011010, "CMIC_MIIM_AUTO_SCAN_ADDRESS", CMIC_MIIM_AUTO_SCAN_ADDRESSr }, \ 603 { 0x00011014, "CMIC_MIIM_PAUSE_MIIM_ADDRESS", CMIC_MIIM_PAUSE_MIIM_ADDRESSr }, \ 604 { 0x00011018, "CMIC_MIIM_LINK_STATUS_0", CMIC_MIIM_LINK_STATUS_0r }, \ 605 { 0x0001101c, "CMIC_MIIM_LINK_STATUS_1", CMIC_MIIM_LINK_STATUS_1r }, \ 606 { 0x00011020, "CMIC_MIIM_LINK_STATUS_2", CMIC_MIIM_LINK_STATUS_2r }, \ 607 { 0x00011024, "CMIC_MIIM_RX_PAUSE_STATUS_0", CMIC_MIIM_RX_PAUSE_STATUS_0r }, \ 608 { 0x00011028, "CMIC_MIIM_RX_PAUSE_STATUS_1", CMIC_MIIM_RX_PAUSE_STATUS_1r }, \ 609 { 0x0001102c, "CMIC_MIIM_RX_PAUSE_STATUS_2", CMIC_MIIM_RX_PAUSE_STATUS_2r }, \ 610 { 0x00011030, "CMIC_MIIM_TX_PAUSE_STATUS_0", CMIC_MIIM_TX_PAUSE_STATUS_0r }, \ 611 { 0x00011034, "CMIC_MIIM_TX_PAUSE_STATUS_1", CMIC_MIIM_TX_PAUSE_STATUS_1r }, \ 612 { 0x00011038, "CMIC_MIIM_TX_PAUSE_STATUS_2", CMIC_MIIM_TX_PAUSE_STATUS_2r }, \ 613 { 0x0001103c, "CMIC_MIIM_SCAN_PORTS_0", CMIC_MIIM_SCAN_PORTS_0r }, \ 614 { 0x00011040, "CMIC_MIIM_SCAN_PORTS_1", CMIC_MIIM_SCAN_PORTS_1r }, \ 615 { 0x00011044, "CMIC_MIIM_SCAN_PORTS_2", CMIC_MIIM_SCAN_PORTS_2r }, \ 616 { 0x00011048, "CMIC_MIIM_PAUSE_SCAN_PORTS_0", CMIC_MIIM_PAUSE_SCAN_PORTS_0r }, \ 617 { 0x0001104c, "CMIC_MIIM_PAUSE_SCAN_PORTS_1", CMIC_MIIM_PAUSE_SCAN_PORTS_1r }, \ 618 { 0x00011050, "CMIC_MIIM_PAUSE_SCAN_PORTS_2", CMIC_MIIM_PAUSE_SCAN_PORTS_2r }, \ 619 { 0x00011054, "CMIC_MIIM_PROTOCOL_MAP_0", CMIC_MIIM_PROTOCOL_MAP_0r }, \ 620 { 0x00011058, "CMIC_MIIM_PROTOCOL_MAP_1", CMIC_MIIM_PROTOCOL_MAP_1r }, \ 621 { 0x0001105c, "CMIC_MIIM_PROTOCOL_MAP_2", CMIC_MIIM_PROTOCOL_MAP_2r }, \ 622 { 0x00011060, "CMIC_MIIM_INT_SEL_MAP_0", CMIC_MIIM_INT_SEL_MAP_0r }, \ 623 { 0x00011064, "CMIC_MIIM_INT_SEL_MAP_1", CMIC_MIIM_INT_SEL_MAP_1r }, \ 624 { 0x00011068, "CMIC_MIIM_INT_SEL_MAP_2", CMIC_MIIM_INT_SEL_MAP_2r }, \ 625 { 0x0001106c, "CMIC_MIIM_BUS_SEL_MAP_7_0", CMIC_MIIM_BUS_SEL_MAP_7_0r }, \ 626 { 0x0001106c, "CMIC_MIIM_BUS_SEL_MAP_9_0", CMIC_MIIM_BUS_SEL_MAP_9_0r }, \ 627 { 0x00011070, "CMIC_MIIM_BUS_SEL_MAP_19_10", CMIC_MIIM_BUS_SEL_MAP_19_10r }, \ 628 { 0x00011070, "CMIC_MIIM_BUS_SEL_MAP_15_8", CMIC_MIIM_BUS_SEL_MAP_15_8r }, \ 629 { 0x00011074, "CMIC_MIIM_BUS_SEL_MAP_29_20", CMIC_MIIM_BUS_SEL_MAP_29_20r }, \ 630 { 0x00011074, "CMIC_MIIM_BUS_SEL_MAP_23_16", CMIC_MIIM_BUS_SEL_MAP_23_16r }, \ 631 { 0x00011078, "CMIC_MIIM_BUS_SEL_MAP_31_24", CMIC_MIIM_BUS_SEL_MAP_31_24r }, \ 632 { 0x00011078, "CMIC_MIIM_BUS_SEL_MAP_39_30", CMIC_MIIM_BUS_SEL_MAP_39_30r }, \ 633 { 0x0001107c, "CMIC_MIIM_BUS_SEL_MAP_49_40", CMIC_MIIM_BUS_SEL_MAP_49_40r }, \ 634 { 0x0001107c, "CMIC_MIIM_BUS_SEL_MAP_39_32", CMIC_MIIM_BUS_SEL_MAP_39_32r }, \ 635 { 0x00011080, "CMIC_MIIM_BUS_SEL_MAP_59_50", CMIC_MIIM_BUS_SEL_MAP_59_50r }, \ 636 { 0x00011080, "CMIC_MIIM_BUS_SEL_MAP_47_40", CMIC_MIIM_BUS_SEL_MAP_47_40r }, \ 637 { 0x00011084, "CMIC_MIIM_BUS_SEL_MAP_55_48", CMIC_MIIM_BUS_SEL_MAP_55_48r }, \ 638 { 0x00011084, "CMIC_MIIM_BUS_SEL_MAP_69_60", CMIC_MIIM_BUS_SEL_MAP_69_60r }, \ 639 { 0x00011088, "CMIC_MIIM_BUS_SEL_MAP_63_56", CMIC_MIIM_BUS_SEL_MAP_63_56r }, \ 640 { 0x00011088, "CMIC_MIIM_BUS_SEL_MAP_79_70", CMIC_MIIM_BUS_SEL_MAP_79_70r }, \ 641 { 0x0001108c, "CMIC_MIIM_BUS_SEL_MAP_89_80", CMIC_MIIM_BUS_SEL_MAP_89_80r }, \ 642 { 0x0001108c, "CMIC_MIIM_BUS_SEL_MAP_71_64", CMIC_MIIM_BUS_SEL_MAP_71_64r }, \ 643 { 0x00011090, "CMIC_MIIM_BUS_SEL_MAP_95_90", CMIC_MIIM_BUS_SEL_MAP_95_90r }, \ 644 { 0x00011090, "CMIC_MIIM_BUS_SEL_MAP_79_72", CMIC_MIIM_BUS_SEL_MAP_79_72r }, \ 645 { 0x00011094, "CMIC_MIIM_EXT_PHY_ADDR_MAP_3_0", CMIC_MIIM_EXT_PHY_ADDR_MAP_3_0r }, \ 646 { 0x00011098, "CMIC_MIIM_EXT_PHY_ADDR_MAP_7_4", CMIC_MIIM_EXT_PHY_ADDR_MAP_7_4r }, \ 647 { 0x0001109c, "CMIC_MIIM_EXT_PHY_ADDR_MAP_11_8", CMIC_MIIM_EXT_PHY_ADDR_MAP_11_8r }, \ 648 { 0x000110a0, "CMIC_MIIM_EXT_PHY_ADDR_MAP_15_12", CMIC_MIIM_EXT_PHY_ADDR_MAP_15_12r }, \ 649 { 0x000110a4, "CMIC_MIIM_EXT_PHY_ADDR_MAP_19_16", CMIC_MIIM_EXT_PHY_ADDR_MAP_19_16r }, \ 650 { 0x000110a8, "CMIC_MIIM_EXT_PHY_ADDR_MAP_23_20", CMIC_MIIM_EXT_PHY_ADDR_MAP_23_20r }, \ 651 { 0x000110ac, "CMIC_MIIM_EXT_PHY_ADDR_MAP_27_24", CMIC_MIIM_EXT_PHY_ADDR_MAP_27_24r }, \ 652 { 0x000110b0, "CMIC_MIIM_EXT_PHY_ADDR_MAP_31_28", CMIC_MIIM_EXT_PHY_ADDR_MAP_31_28r }, \ 653 { 0x000110b4, "CMIC_MIIM_EXT_PHY_ADDR_MAP_35_32", CMIC_MIIM_EXT_PHY_ADDR_MAP_35_32r }, \ 654 { 0x000110b8, "CMIC_MIIM_EXT_PHY_ADDR_MAP_39_36", CMIC_MIIM_EXT_PHY_ADDR_MAP_39_36r }, \ 655 { 0x000110bc, "CMIC_MIIM_EXT_PHY_ADDR_MAP_43_40", CMIC_MIIM_EXT_PHY_ADDR_MAP_43_40r }, \ 656 { 0x000110c0, "CMIC_MIIM_EXT_PHY_ADDR_MAP_47_44", CMIC_MIIM_EXT_PHY_ADDR_MAP_47_44r }, \ 657 { 0x000110c4, "CMIC_MIIM_EXT_PHY_ADDR_MAP_51_48", CMIC_MIIM_EXT_PHY_ADDR_MAP_51_48r }, \ 658 { 0x000110c8, "CMIC_MIIM_EXT_PHY_ADDR_MAP_55_52", CMIC_MIIM_EXT_PHY_ADDR_MAP_55_52r }, \ 659 { 0x000110cc, "CMIC_MIIM_EXT_PHY_ADDR_MAP_59_56", CMIC_MIIM_EXT_PHY_ADDR_MAP_59_56r }, \ 660 { 0x000110d0, "CMIC_MIIM_EXT_PHY_ADDR_MAP_63_60", CMIC_MIIM_EXT_PHY_ADDR_MAP_63_60r }, \ 661 { 0x000110d4, "CMIC_MIIM_EXT_PHY_ADDR_MAP_67_64", CMIC_MIIM_EXT_PHY_ADDR_MAP_67_64r }, \ 662 { 0x000110d8, "CMIC_MIIM_EXT_PHY_ADDR_MAP_71_68", CMIC_MIIM_EXT_PHY_ADDR_MAP_71_68r }, \ 663 { 0x000110dc, "CMIC_MIIM_EXT_PHY_ADDR_MAP_75_72", CMIC_MIIM_EXT_PHY_ADDR_MAP_75_72r }, \ 664 { 0x000110e0, "CMIC_MIIM_EXT_PHY_ADDR_MAP_79_76", CMIC_MIIM_EXT_PHY_ADDR_MAP_79_76r }, \ 665 { 0x000110e4, "CMIC_MIIM_EXT_PHY_ADDR_MAP_83_80", CMIC_MIIM_EXT_PHY_ADDR_MAP_83_80r }, \ 666 { 0x000110e8, "CMIC_MIIM_EXT_PHY_ADDR_MAP_87_84", CMIC_MIIM_EXT_PHY_ADDR_MAP_87_84r }, \ 667 { 0x000110ec, "CMIC_MIIM_EXT_PHY_ADDR_MAP_91_88", CMIC_MIIM_EXT_PHY_ADDR_MAP_91_88r }, \ 668 { 0x000110f0, "CMIC_MIIM_EXT_PHY_ADDR_MAP_95_92", CMIC_MIIM_EXT_PHY_ADDR_MAP_95_92r }, \ 669 { 0x000110f4, "CMIC_MIIM_RX_PAUSE_CAPABILITY_0", CMIC_MIIM_RX_PAUSE_CAPABILITY_0r }, \ 670 { 0x000110f8, "CMIC_MIIM_RX_PAUSE_CAPABILITY_1", CMIC_MIIM_RX_PAUSE_CAPABILITY_1r }, \ 671 { 0x000110fc, "CMIC_MIIM_RX_PAUSE_CAPABILITY_2", CMIC_MIIM_RX_PAUSE_CAPABILITY_2r }, \ 672 { 0x00011100, "CMIC_MIIM_RX_PAUSE_OVERRIDE_CONTROL_0", CMIC_MIIM_RX_PAUSE_OVERRIDE_CONTROL_0r }, \ 673 { 0x00011104, "CMIC_MIIM_RX_PAUSE_OVERRIDE_CONTROL_1", CMIC_MIIM_RX_PAUSE_OVERRIDE_CONTROL_1r }, \ 674 { 0x00011108, "CMIC_MIIM_RX_PAUSE_OVERRIDE_CONTROL_2", CMIC_MIIM_RX_PAUSE_OVERRIDE_CONTROL_2r }, \ 675 { 0x0001110c, "CMIC_MIIM_TX_PAUSE_CAPABILITY_0", CMIC_MIIM_TX_PAUSE_CAPABILITY_0r }, \ 676 { 0x00011110, "CMIC_MIIM_TX_PAUSE_CAPABILITY_1", CMIC_MIIM_TX_PAUSE_CAPABILITY_1r }, \ 677 { 0x00011114, "CMIC_MIIM_TX_PAUSE_CAPABILITY_2", CMIC_MIIM_TX_PAUSE_CAPABILITY_2r }, \ 678 { 0x00011118, "CMIC_MIIM_TX_PAUSE_OVERRIDE_CONTROL_0", CMIC_MIIM_TX_PAUSE_OVERRIDE_CONTROL_0r }, \ 679 { 0x0001111c, "CMIC_MIIM_TX_PAUSE_OVERRIDE_CONTROL_1", CMIC_MIIM_TX_PAUSE_OVERRIDE_CONTROL_1r }, \ 680 { 0x00011120, "CMIC_MIIM_TX_PAUSE_OVERRIDE_CONTROL_2", CMIC_MIIM_TX_PAUSE_OVERRIDE_CONTROL_2r }, \ 681 { 0x00011124, "CMIC_MIIM_CLR_SCAN_STATUS", CMIC_MIIM_CLR_SCAN_STATUSr }, \ 682 { 0x00011128, "CMIC_MIIM_LINK_STATUS_3", CMIC_MIIM_LINK_STATUS_3r }, \ 683 { 0x0001112c, "CMIC_MIIM_RX_PAUSE_STATUS_3", CMIC_MIIM_RX_PAUSE_STATUS_3r }, \ 684 { 0x00011130, "CMIC_MIIM_TX_PAUSE_STATUS_3", CMIC_MIIM_TX_PAUSE_STATUS_3r }, \ 685 { 0x00011134, "CMIC_MIIM_SCAN_PORTS_3", CMIC_MIIM_SCAN_PORTS_3r }, \ 686 { 0x00011138, "CMIC_MIIM_PAUSE_SCAN_PORTS_3", CMIC_MIIM_PAUSE_SCAN_PORTS_3r }, \ 687 { 0x0001113c, "CMIC_MIIM_PROTOCOL_MAP_3", CMIC_MIIM_PROTOCOL_MAP_3r }, \ 688 { 0x00011140, "CMIC_MIIM_INT_SEL_MAP_3", CMIC_MIIM_INT_SEL_MAP_3r }, \ 689 { 0x00011144, "CMIC_MIIM_BUS_SEL_MAP_99_90", CMIC_MIIM_BUS_SEL_MAP_99_90r }, \ 690 { 0x00011144, "CMIC_MIIM_BUS_SEL_MAP_87_80", CMIC_MIIM_BUS_SEL_MAP_87_80r }, \ 691 { 0x00011148, "CMIC_MIIM_BUS_SEL_MAP_109_100", CMIC_MIIM_BUS_SEL_MAP_109_100r }, \ 692 { 0x00011148, "CMIC_MIIM_BUS_SEL_MAP_95_88", CMIC_MIIM_BUS_SEL_MAP_95_88r }, \ 693 { 0x0001114c, "CMIC_MIIM_BUS_SEL_MAP_119_110", CMIC_MIIM_BUS_SEL_MAP_119_110r }, \ 694 { 0x0001114c, "CMIC_MIIM_BUS_SEL_MAP_103_96", CMIC_MIIM_BUS_SEL_MAP_103_96r }, \ 695 { 0x00011150, "CMIC_MIIM_BUS_SEL_MAP_111_104", CMIC_MIIM_BUS_SEL_MAP_111_104r }, \ 696 { 0x00011150, "CMIC_MIIM_BUS_SEL_MAP_129_120", CMIC_MIIM_BUS_SEL_MAP_129_120r }, \ 697 { 0x00011150, "CMIC_MIIM_BUS_SEL_MAP_127_120", CMIC_MIIM_BUS_SEL_MAP_127_120r }, \ 698 { 0x00011154, "CMIC_MIIM_EXT_PHY_ADDR_MAP_99_96", CMIC_MIIM_EXT_PHY_ADDR_MAP_99_96r }, \ 699 { 0x00011158, "CMIC_MIIM_EXT_PHY_ADDR_MAP_103_100", CMIC_MIIM_EXT_PHY_ADDR_MAP_103_100r }, \ 700 { 0x0001115c, "CMIC_MIIM_EXT_PHY_ADDR_MAP_107_104", CMIC_MIIM_EXT_PHY_ADDR_MAP_107_104r }, \ 701 { 0x00011160, "CMIC_MIIM_EXT_PHY_ADDR_MAP_111_108", CMIC_MIIM_EXT_PHY_ADDR_MAP_111_108r }, \ 702 { 0x00011164, "CMIC_MIIM_EXT_PHY_ADDR_MAP_115_112", CMIC_MIIM_EXT_PHY_ADDR_MAP_115_112r }, \ 703 { 0x00011168, "CMIC_MIIM_EXT_PHY_ADDR_MAP_119_116", CMIC_MIIM_EXT_PHY_ADDR_MAP_119_116r }, \ 704 { 0x0001116c, "CMIC_MIIM_EXT_PHY_ADDR_MAP_123_120", CMIC_MIIM_EXT_PHY_ADDR_MAP_123_120r }, \ 705 { 0x00011170, "CMIC_MIIM_EXT_PHY_ADDR_MAP_127_124", CMIC_MIIM_EXT_PHY_ADDR_MAP_127_124r }, \ 706 { 0x00011174, "CMIC_MIIM_RX_PAUSE_CAPABILITY_3", CMIC_MIIM_RX_PAUSE_CAPABILITY_3r }, \ 707 { 0x00011178, "CMIC_MIIM_RX_PAUSE_OVERRIDE_CONTROL_3", CMIC_MIIM_RX_PAUSE_OVERRIDE_CONTROL_3r }, \ 708 { 0x0001117c, "CMIC_MIIM_TX_PAUSE_CAPABILITY_3", CMIC_MIIM_TX_PAUSE_CAPABILITY_3r }, \ 709 { 0x00011180, "CMIC_MIIM_TX_PAUSE_OVERRIDE_CONTROL_3", CMIC_MIIM_TX_PAUSE_OVERRIDE_CONTROL_3r }, \ 710 { 0x00011184, "CMIC_MIIM_CONFIG", CMIC_MIIM_CONFIGr }, \ 711 { 0x00011188, "CMIC_MIIM_LINK_STATUS_4", CMIC_MIIM_LINK_STATUS_4r }, \ 712 { 0x0001118c, "CMIC_MIIM_LINK_STATUS_5", CMIC_MIIM_LINK_STATUS_5r }, \ 713 { 0x00011190, "CMIC_MIIM_RX_PAUSE_STATUS_4", CMIC_MIIM_RX_PAUSE_STATUS_4r }, \ 714 { 0x00011194, "CMIC_MIIM_RX_PAUSE_STATUS_5", CMIC_MIIM_RX_PAUSE_STATUS_5r }, \ 715 { 0x00011198, "CMIC_MIIM_TX_PAUSE_STATUS_4", CMIC_MIIM_TX_PAUSE_STATUS_4r }, \ 716 { 0x0001119c, "CMIC_MIIM_TX_PAUSE_STATUS_5", CMIC_MIIM_TX_PAUSE_STATUS_5r }, \ 717 { 0x000111a0, "CMIC_MIIM_SCAN_PORTS_4", CMIC_MIIM_SCAN_PORTS_4r }, \ 718 { 0x000111a4, "CMIC_MIIM_SCAN_PORTS_5", CMIC_MIIM_SCAN_PORTS_5r }, \ 719 { 0x000111a8, "CMIC_MIIM_PAUSE_SCAN_PORTS_4", CMIC_MIIM_PAUSE_SCAN_PORTS_4r }, \ 720 { 0x000111ac, "CMIC_MIIM_PAUSE_SCAN_PORTS_5", CMIC_MIIM_PAUSE_SCAN_PORTS_5r }, \ 721 { 0x000111b0, "CMIC_MIIM_PROTOCOL_MAP_4", CMIC_MIIM_PROTOCOL_MAP_4r }, \ 722 { 0x000111b4, "CMIC_MIIM_PROTOCOL_MAP_5", CMIC_MIIM_PROTOCOL_MAP_5r }, \ 723 { 0x000111b8, "CMIC_MIIM_INT_SEL_MAP_4", CMIC_MIIM_INT_SEL_MAP_4r }, \ 724 { 0x000111bc, "CMIC_MIIM_INT_SEL_MAP_5", CMIC_MIIM_INT_SEL_MAP_5r }, \ 725 { 0x000111c0, "CMIC_MIIM_BUS_SEL_MAP_119_112", CMIC_MIIM_BUS_SEL_MAP_119_112r }, \ 726 { 0x000111c0, "CMIC_MIIM_BUS_SEL_MAP_139_130", CMIC_MIIM_BUS_SEL_MAP_139_130r }, \ 727 { 0x000111c4, "CMIC_V3_MIIM_BUS_SEL_MAP_127_120", CMIC_V3_MIIM_BUS_SEL_MAP_127_120r }, \ 728 { 0x000111c4, "CMIC_MIIM_BUS_SEL_MAP_149_140", CMIC_MIIM_BUS_SEL_MAP_149_140r }, \ 729 { 0x000111c8, "CMIC_MIIM_BUS_SEL_MAP_135_128", CMIC_MIIM_BUS_SEL_MAP_135_128r }, \ 730 { 0x000111c8, "CMIC_MIIM_BUS_SEL_MAP_159_150", CMIC_MIIM_BUS_SEL_MAP_159_150r }, \ 731 { 0x000111cc, "CMIC_MIIM_BUS_SEL_MAP_143_136", CMIC_MIIM_BUS_SEL_MAP_143_136r }, \ 732 { 0x000111cc, "CMIC_MIIM_BUS_SEL_MAP_169_160", CMIC_MIIM_BUS_SEL_MAP_169_160r }, \ 733 { 0x000111d0, "CMIC_MIIM_BUS_SEL_MAP_179_170", CMIC_MIIM_BUS_SEL_MAP_179_170r }, \ 734 { 0x000111d0, "CMIC_MIIM_BUS_SEL_MAP_151_144", CMIC_MIIM_BUS_SEL_MAP_151_144r }, \ 735 { 0x000111d4, "CMIC_MIIM_BUS_SEL_MAP_189_180", CMIC_MIIM_BUS_SEL_MAP_189_180r }, \ 736 { 0x000111d4, "CMIC_MIIM_BUS_SEL_MAP_159_152", CMIC_MIIM_BUS_SEL_MAP_159_152r }, \ 737 { 0x000111d8, "CMIC_MIIM_BUS_SEL_MAP_167_160", CMIC_MIIM_BUS_SEL_MAP_167_160r }, \ 738 { 0x000111d8, "CMIC_MIIM_BUS_SEL_MAP_191_190", CMIC_MIIM_BUS_SEL_MAP_191_190r }, \ 739 { 0x000111dc, "CMIC_MIIM_EXT_PHY_ADDR_MAP_131_128", CMIC_MIIM_EXT_PHY_ADDR_MAP_131_128r }, \ 740 { 0x000111e0, "CMIC_MIIM_EXT_PHY_ADDR_MAP_135_132", CMIC_MIIM_EXT_PHY_ADDR_MAP_135_132r }, \ 741 { 0x000111e4, "CMIC_MIIM_EXT_PHY_ADDR_MAP_139_136", CMIC_MIIM_EXT_PHY_ADDR_MAP_139_136r }, \ 742 { 0x000111e8, "CMIC_MIIM_EXT_PHY_ADDR_MAP_143_140", CMIC_MIIM_EXT_PHY_ADDR_MAP_143_140r }, \ 743 { 0x000111ec, "CMIC_MIIM_EXT_PHY_ADDR_MAP_147_144", CMIC_MIIM_EXT_PHY_ADDR_MAP_147_144r }, \ 744 { 0x000111f0, "CMIC_MIIM_EXT_PHY_ADDR_MAP_151_148", CMIC_MIIM_EXT_PHY_ADDR_MAP_151_148r }, \ 745 { 0x000111f4, "CMIC_MIIM_EXT_PHY_ADDR_MAP_155_152", CMIC_MIIM_EXT_PHY_ADDR_MAP_155_152r }, \ 746 { 0x000111f8, "CMIC_MIIM_EXT_PHY_ADDR_MAP_159_156", CMIC_MIIM_EXT_PHY_ADDR_MAP_159_156r }, \ 747 { 0x000111fc, "CMIC_MIIM_EXT_PHY_ADDR_MAP_163_160", CMIC_MIIM_EXT_PHY_ADDR_MAP_163_160r }, \ 748 { 0x00011200, "CMIC_MIIM_EXT_PHY_ADDR_MAP_167_164", CMIC_MIIM_EXT_PHY_ADDR_MAP_167_164r }, \ 749 { 0x00011204, "CMIC_MIIM_EXT_PHY_ADDR_MAP_171_168", CMIC_MIIM_EXT_PHY_ADDR_MAP_171_168r }, \ 750 { 0x00011208, "CMIC_MIIM_EXT_PHY_ADDR_MAP_175_172", CMIC_MIIM_EXT_PHY_ADDR_MAP_175_172r }, \ 751 { 0x0001120c, "CMIC_MIIM_EXT_PHY_ADDR_MAP_179_176", CMIC_MIIM_EXT_PHY_ADDR_MAP_179_176r }, \ 752 { 0x00011210, "CMIC_MIIM_EXT_PHY_ADDR_MAP_183_180", CMIC_MIIM_EXT_PHY_ADDR_MAP_183_180r }, \ 753 { 0x00011214, "CMIC_MIIM_EXT_PHY_ADDR_MAP_187_184", CMIC_MIIM_EXT_PHY_ADDR_MAP_187_184r }, \ 754 { 0x00011218, "CMIC_MIIM_EXT_PHY_ADDR_MAP_191_188", CMIC_MIIM_EXT_PHY_ADDR_MAP_191_188r }, \ 755 { 0x0001121c, "CMIC_MIIM_RX_PAUSE_CAPABILITY_4", CMIC_MIIM_RX_PAUSE_CAPABILITY_4r }, \ 756 { 0x00011220, "CMIC_MIIM_RX_PAUSE_CAPABILITY_5", CMIC_MIIM_RX_PAUSE_CAPABILITY_5r }, \ 757 { 0x00011224, "CMIC_MIIM_RX_PAUSE_OVERRIDE_CONTROL_4", CMIC_MIIM_RX_PAUSE_OVERRIDE_CONTROL_4r }, \ 758 { 0x00011228, "CMIC_MIIM_RX_PAUSE_OVERRIDE_CONTROL_5", CMIC_MIIM_RX_PAUSE_OVERRIDE_CONTROL_5r }, \ 759 { 0x0001122c, "CMIC_MIIM_TX_PAUSE_CAPABILITY_4", CMIC_MIIM_TX_PAUSE_CAPABILITY_4r }, \ 760 { 0x00011230, "CMIC_MIIM_TX_PAUSE_CAPABILITY_5", CMIC_MIIM_TX_PAUSE_CAPABILITY_5r }, \ 761 { 0x00011234, "CMIC_MIIM_TX_PAUSE_OVERRIDE_CONTROL_4", CMIC_MIIM_TX_PAUSE_OVERRIDE_CONTROL_4r }, \ 762 { 0x00011238, "CMIC_MIIM_TX_PAUSE_OVERRIDE_CONTROL_5", CMIC_MIIM_TX_PAUSE_OVERRIDE_CONTROL_5r }, \ 763 { 0x0001123c, "CMIC_MIIM_BUS_SEL_MAP_175_168", CMIC_MIIM_BUS_SEL_MAP_175_168r }, \ 764 { 0x00011240, "CMIC_MIIM_BUS_SEL_MAP_183_176", CMIC_MIIM_BUS_SEL_MAP_183_176r }, \ 765 { 0x00011244, "CMIC_MIIM_BUS_SEL_MAP_191_184", CMIC_MIIM_BUS_SEL_MAP_191_184r }, \ 766 { 0x00011248, "CMIC_MIIM_BUS_SEL_MAP_199_192", CMIC_MIIM_BUS_SEL_MAP_199_192r }, \ 767 { 0x0001124c, "CMIC_MIIM_BUS_SEL_MAP_207_200", CMIC_MIIM_BUS_SEL_MAP_207_200r }, \ 768 { 0x00011250, "CMIC_MIIM_BUS_SEL_MAP_215_208", CMIC_MIIM_BUS_SEL_MAP_215_208r }, \ 769 { 0x00011254, "CMIC_MIIM_BUS_SEL_MAP_223_216", CMIC_MIIM_BUS_SEL_MAP_223_216r }, \ 770 { 0x00011258, "CMIC_MIIM_BUS_SEL_MAP_231_224", CMIC_MIIM_BUS_SEL_MAP_231_224r }, \ 771 { 0x0001125c, "CMIC_MIIM_BUS_SEL_MAP_239_232", CMIC_MIIM_BUS_SEL_MAP_239_232r }, \ 772 { 0x00011260, "CMIC_MIIM_BUS_SEL_MAP_247_240", CMIC_MIIM_BUS_SEL_MAP_247_240r }, \ 773 { 0x00011264, "CMIC_MIIM_BUS_SEL_MAP_255_248", CMIC_MIIM_BUS_SEL_MAP_255_248r }, \ 774 { 0x00011268, "CMIC_MIIM_BUS_SEL_MAP_263_256", CMIC_MIIM_BUS_SEL_MAP_263_256r }, \ 775 { 0x0001126c, "CMIC_MIIM_BUS_SEL_MAP_271_264", CMIC_MIIM_BUS_SEL_MAP_271_264r }, \ 776 { 0x00011270, "CMIC_MIIM_BUS_SEL_MAP_279_272", CMIC_MIIM_BUS_SEL_MAP_279_272r }, \ 777 { 0x00011274, "CMIC_MIIM_BUS_SEL_MAP_287_280", CMIC_MIIM_BUS_SEL_MAP_287_280r }, \ 778 { 0x00011278, "CMIC_MIIM_BUS_SEL_MAP_295_288", CMIC_MIIM_BUS_SEL_MAP_295_288r }, \ 779 { 0x0001127c, "CMIC_MIIM_BUS_SEL_MAP_303_296", CMIC_MIIM_BUS_SEL_MAP_303_296r }, \ 780 { 0x00011280, "CMIC_MIIM_BUS_SEL_MAP_311_304", CMIC_MIIM_BUS_SEL_MAP_311_304r }, \ 781 { 0x00011284, "CMIC_MIIM_BUS_SEL_MAP_319_312", CMIC_MIIM_BUS_SEL_MAP_319_312r }, \ 782 { 0x00011288, "CMIC_MIIM_EXT_PHY_ADDR_MAP_195_192", CMIC_MIIM_EXT_PHY_ADDR_MAP_195_192r }, \ 783 { 0x0001128c, "CMIC_MIIM_EXT_PHY_ADDR_MAP_199_196", CMIC_MIIM_EXT_PHY_ADDR_MAP_199_196r }, \ 784 { 0x00011290, "CMIC_MIIM_EXT_PHY_ADDR_MAP_203_200", CMIC_MIIM_EXT_PHY_ADDR_MAP_203_200r }, \ 785 { 0x00011294, "CMIC_MIIM_EXT_PHY_ADDR_MAP_207_204", CMIC_MIIM_EXT_PHY_ADDR_MAP_207_204r }, \ 786 { 0x00011298, "CMIC_MIIM_EXT_PHY_ADDR_MAP_211_208", CMIC_MIIM_EXT_PHY_ADDR_MAP_211_208r }, \ 787 { 0x0001129c, "CMIC_MIIM_EXT_PHY_ADDR_MAP_215_212", CMIC_MIIM_EXT_PHY_ADDR_MAP_215_212r }, \ 788 { 0x000112a0, "CMIC_MIIM_EXT_PHY_ADDR_MAP_219_216", CMIC_MIIM_EXT_PHY_ADDR_MAP_219_216r }, \ 789 { 0x000112a4, "CMIC_MIIM_EXT_PHY_ADDR_MAP_223_220", CMIC_MIIM_EXT_PHY_ADDR_MAP_223_220r }, \ 790 { 0x000112a8, "CMIC_MIIM_EXT_PHY_ADDR_MAP_227_224", CMIC_MIIM_EXT_PHY_ADDR_MAP_227_224r }, \ 791 { 0x000112ac, "CMIC_MIIM_EXT_PHY_ADDR_MAP_231_228", CMIC_MIIM_EXT_PHY_ADDR_MAP_231_228r }, \ 792 { 0x000112b0, "CMIC_MIIM_EXT_PHY_ADDR_MAP_235_232", CMIC_MIIM_EXT_PHY_ADDR_MAP_235_232r }, \ 793 { 0x000112b4, "CMIC_MIIM_EXT_PHY_ADDR_MAP_239_236", CMIC_MIIM_EXT_PHY_ADDR_MAP_239_236r }, \ 794 { 0x000112b8, "CMIC_MIIM_EXT_PHY_ADDR_MAP_243_240", CMIC_MIIM_EXT_PHY_ADDR_MAP_243_240r }, \ 795 { 0x000112bc, "CMIC_MIIM_EXT_PHY_ADDR_MAP_247_244", CMIC_MIIM_EXT_PHY_ADDR_MAP_247_244r }, \ 796 { 0x000112c0, "CMIC_MIIM_EXT_PHY_ADDR_MAP_251_248", CMIC_MIIM_EXT_PHY_ADDR_MAP_251_248r }, \ 797 { 0x000112c4, "CMIC_MIIM_EXT_PHY_ADDR_MAP_255_252", CMIC_MIIM_EXT_PHY_ADDR_MAP_255_252r }, \ 798 { 0x000112c8, "CMIC_MIIM_EXT_PHY_ADDR_MAP_259_256", CMIC_MIIM_EXT_PHY_ADDR_MAP_259_256r }, \ 799 { 0x000112cc, "CMIC_MIIM_EXT_PHY_ADDR_MAP_263_260", CMIC_MIIM_EXT_PHY_ADDR_MAP_263_260r }, \ 800 { 0x000112d0, "CMIC_MIIM_EXT_PHY_ADDR_MAP_267_264", CMIC_MIIM_EXT_PHY_ADDR_MAP_267_264r }, \ 801 { 0x000112d4, "CMIC_MIIM_EXT_PHY_ADDR_MAP_271_268", CMIC_MIIM_EXT_PHY_ADDR_MAP_271_268r }, \ 802 { 0x000112d8, "CMIC_MIIM_EXT_PHY_ADDR_MAP_275_272", CMIC_MIIM_EXT_PHY_ADDR_MAP_275_272r }, \ 803 { 0x000112dc, "CMIC_MIIM_EXT_PHY_ADDR_MAP_279_276", CMIC_MIIM_EXT_PHY_ADDR_MAP_279_276r }, \ 804 { 0x000112e0, "CMIC_MIIM_EXT_PHY_ADDR_MAP_283_280", CMIC_MIIM_EXT_PHY_ADDR_MAP_283_280r }, \ 805 { 0x000112e4, "CMIC_MIIM_EXT_PHY_ADDR_MAP_287_284", CMIC_MIIM_EXT_PHY_ADDR_MAP_287_284r }, \ 806 { 0x000112e8, "CMIC_MIIM_EXT_PHY_ADDR_MAP_291_288", CMIC_MIIM_EXT_PHY_ADDR_MAP_291_288r }, \ 807 { 0x000112ec, "CMIC_MIIM_EXT_PHY_ADDR_MAP_295_292", CMIC_MIIM_EXT_PHY_ADDR_MAP_295_292r }, \ 808 { 0x000112f0, "CMIC_MIIM_EXT_PHY_ADDR_MAP_299_296", CMIC_MIIM_EXT_PHY_ADDR_MAP_299_296r }, \ 809 { 0x000112f4, "CMIC_MIIM_EXT_PHY_ADDR_MAP_303_300", CMIC_MIIM_EXT_PHY_ADDR_MAP_303_300r }, \ 810 { 0x000112f8, "CMIC_MIIM_EXT_PHY_ADDR_MAP_307_304", CMIC_MIIM_EXT_PHY_ADDR_MAP_307_304r }, \ 811 { 0x000112fc, "CMIC_MIIM_EXT_PHY_ADDR_MAP_311_308", CMIC_MIIM_EXT_PHY_ADDR_MAP_311_308r }, \ 812 { 0x00011300, "CMIC_MIIM_EXT_PHY_ADDR_MAP_315_312", CMIC_MIIM_EXT_PHY_ADDR_MAP_315_312r }, \ 813 { 0x00011304, "CMIC_MIIM_EXT_PHY_ADDR_MAP_319_316", CMIC_MIIM_EXT_PHY_ADDR_MAP_319_316r }, \ 814 { 0x00011308, "CMIC_MIIM_LINK_STATUS_6", CMIC_MIIM_LINK_STATUS_6r }, \ 815 { 0x0001130c, "CMIC_MIIM_LINK_STATUS_7", CMIC_MIIM_LINK_STATUS_7r }, \ 816 { 0x00011310, "CMIC_MIIM_LINK_STATUS_8", CMIC_MIIM_LINK_STATUS_8r }, \ 817 { 0x00011314, "CMIC_MIIM_LINK_STATUS_9", CMIC_MIIM_LINK_STATUS_9r }, \ 818 { 0x00011318, "CMIC_MIIM_RX_PAUSE_STATUS_6", CMIC_MIIM_RX_PAUSE_STATUS_6r }, \ 819 { 0x0001131c, "CMIC_MIIM_RX_PAUSE_STATUS_7", CMIC_MIIM_RX_PAUSE_STATUS_7r }, \ 820 { 0x00011320, "CMIC_MIIM_RX_PAUSE_STATUS_8", CMIC_MIIM_RX_PAUSE_STATUS_8r }, \ 821 { 0x00011324, "CMIC_MIIM_RX_PAUSE_STATUS_9", CMIC_MIIM_RX_PAUSE_STATUS_9r }, \ 822 { 0x00011328, "CMIC_MIIM_TX_PAUSE_STATUS_6", CMIC_MIIM_TX_PAUSE_STATUS_6r }, \ 823 { 0x0001132c, "CMIC_MIIM_TX_PAUSE_STATUS_7", CMIC_MIIM_TX_PAUSE_STATUS_7r }, \ 824 { 0x00011330, "CMIC_MIIM_TX_PAUSE_STATUS_8", CMIC_MIIM_TX_PAUSE_STATUS_8r }, \ 825 { 0x00011334, "CMIC_MIIM_TX_PAUSE_STATUS_9", CMIC_MIIM_TX_PAUSE_STATUS_9r }, \ 826 { 0x00011338, "CMIC_MIIM_SCAN_PORTS_6", CMIC_MIIM_SCAN_PORTS_6r }, \ 827 { 0x0001133c, "CMIC_MIIM_SCAN_PORTS_7", CMIC_MIIM_SCAN_PORTS_7r }, \ 828 { 0x00011340, "CMIC_MIIM_SCAN_PORTS_8", CMIC_MIIM_SCAN_PORTS_8r }, \ 829 { 0x00011344, "CMIC_MIIM_SCAN_PORTS_9", CMIC_MIIM_SCAN_PORTS_9r }, \ 830 { 0x00011348, "CMIC_MIIM_PAUSE_SCAN_PORTS_6", CMIC_MIIM_PAUSE_SCAN_PORTS_6r }, \ 831 { 0x0001134c, "CMIC_MIIM_PAUSE_SCAN_PORTS_7", CMIC_MIIM_PAUSE_SCAN_PORTS_7r }, \ 832 { 0x00011350, "CMIC_MIIM_PAUSE_SCAN_PORTS_8", CMIC_MIIM_PAUSE_SCAN_PORTS_8r }, \ 833 { 0x00011354, "CMIC_MIIM_PAUSE_SCAN_PORTS_9", CMIC_MIIM_PAUSE_SCAN_PORTS_9r }, \ 834 { 0x00011358, "CMIC_MIIM_PROTOCOL_MAP_6", CMIC_MIIM_PROTOCOL_MAP_6r }, \ 835 { 0x0001135c, "CMIC_MIIM_PROTOCOL_MAP_7", CMIC_MIIM_PROTOCOL_MAP_7r }, \ 836 { 0x00011360, "CMIC_MIIM_PROTOCOL_MAP_8", CMIC_MIIM_PROTOCOL_MAP_8r }, \ 837 { 0x00011364, "CMIC_MIIM_PROTOCOL_MAP_9", CMIC_MIIM_PROTOCOL_MAP_9r }, \ 838 { 0x00011368, "CMIC_MIIM_INT_SEL_MAP_6", CMIC_MIIM_INT_SEL_MAP_6r }, \ 839 { 0x0001136c, "CMIC_MIIM_INT_SEL_MAP_7", CMIC_MIIM_INT_SEL_MAP_7r }, \ 840 { 0x00011370, "CMIC_MIIM_INT_SEL_MAP_8", CMIC_MIIM_INT_SEL_MAP_8r }, \ 841 { 0x00011374, "CMIC_MIIM_INT_SEL_MAP_9", CMIC_MIIM_INT_SEL_MAP_9r }, \ 842 { 0x00011378, "CMIC_MIIM_RX_PAUSE_CAPABILITY_6", CMIC_MIIM_RX_PAUSE_CAPABILITY_6r }, \ 843 { 0x0001137c, "CMIC_MIIM_RX_PAUSE_CAPABILITY_7", CMIC_MIIM_RX_PAUSE_CAPABILITY_7r }, \ 844 { 0x00011380, "CMIC_MIIM_RX_PAUSE_CAPABILITY_8", CMIC_MIIM_RX_PAUSE_CAPABILITY_8r }, \ 845 { 0x00011384, "CMIC_MIIM_RX_PAUSE_CAPABILITY_9", CMIC_MIIM_RX_PAUSE_CAPABILITY_9r }, \ 846 { 0x00011388, "CMIC_MIIM_RX_PAUSE_OVERRIDE_CONTROL_6", CMIC_MIIM_RX_PAUSE_OVERRIDE_CONTROL_6r }, \ 847 { 0x0001138c, "CMIC_MIIM_RX_PAUSE_OVERRIDE_CONTROL_7", CMIC_MIIM_RX_PAUSE_OVERRIDE_CONTROL_7r }, \ 848 { 0x00011390, "CMIC_MIIM_RX_PAUSE_OVERRIDE_CONTROL_8", CMIC_MIIM_RX_PAUSE_OVERRIDE_CONTROL_8r }, \ 849 { 0x00011394, "CMIC_MIIM_RX_PAUSE_OVERRIDE_CONTROL_9", CMIC_MIIM_RX_PAUSE_OVERRIDE_CONTROL_9r }, \ 850 { 0x00011398, "CMIC_MIIM_TX_PAUSE_CAPABILITY_6", CMIC_MIIM_TX_PAUSE_CAPABILITY_6r }, \ 851 { 0x0001139c, "CMIC_MIIM_TX_PAUSE_CAPABILITY_7", CMIC_MIIM_TX_PAUSE_CAPABILITY_7r }, \ 852 { 0x000113a0, "CMIC_MIIM_TX_PAUSE_CAPABILITY_8", CMIC_MIIM_TX_PAUSE_CAPABILITY_8r }, \ 853 { 0x000113a4, "CMIC_MIIM_TX_PAUSE_CAPABILITY_9", CMIC_MIIM_TX_PAUSE_CAPABILITY_9r }, \ 854 { 0x000113a8, "CMIC_MIIM_TX_PAUSE_OVERRIDE_CONTROL_6", CMIC_MIIM_TX_PAUSE_OVERRIDE_CONTROL_6r }, \ 855 { 0x000113ac, "CMIC_MIIM_TX_PAUSE_OVERRIDE_CONTROL_7", CMIC_MIIM_TX_PAUSE_OVERRIDE_CONTROL_7r }, \ 856 { 0x000113b0, "CMIC_MIIM_TX_PAUSE_OVERRIDE_CONTROL_8", CMIC_MIIM_TX_PAUSE_OVERRIDE_CONTROL_8r }, \ 857 { 0x000113b4, "CMIC_MIIM_TX_PAUSE_OVERRIDE_CONTROL_9", CMIC_MIIM_TX_PAUSE_OVERRIDE_CONTROL_9r }, \ 858 { 0x00012000, "CMIC_SER0_START_ADDR_0", CMIC_SER0_START_ADDR_0r }, \ 859 { 0x00012000, "CMIC_SER_START_ADDR_0", CMIC_SER_START_ADDR_0r }, \ 860 { 0x00012004, "CMIC_SER_END_ADDR_0", CMIC_SER_END_ADDR_0r }, \ 861 { 0x00012004, "CMIC_SER0_END_ADDR_0", CMIC_SER0_END_ADDR_0r }, \ 862 { 0x00012008, "CMIC_SER_MEM_ADDR_0", CMIC_SER_MEM_ADDR_0r }, \ 863 { 0x00012008, "CMIC_SER0_MEM_ADDR_0", CMIC_SER0_MEM_ADDR_0r }, \ 864 { 0x0001200c, "CMIC_SER0_RANGE0_DATAENTRY_LEN", CMIC_SER0_RANGE0_DATAENTRY_LENr }, \ 865 { 0x0001200c, "CMIC_SER_RANGE0_DATAENTRY_LEN", CMIC_SER_RANGE0_DATAENTRY_LENr }, \ 866 { 0x00012010, "CMIC_SER_START_ADDR_1", CMIC_SER_START_ADDR_1r }, \ 867 { 0x00012010, "CMIC_SER0_START_ADDR_1", CMIC_SER0_START_ADDR_1r }, \ 868 { 0x00012014, "CMIC_SER_END_ADDR_1", CMIC_SER_END_ADDR_1r }, \ 869 { 0x00012014, "CMIC_SER0_END_ADDR_1", CMIC_SER0_END_ADDR_1r }, \ 870 { 0x00012018, "CMIC_SER_MEM_ADDR_1", CMIC_SER_MEM_ADDR_1r }, \ 871 { 0x00012018, "CMIC_SER0_MEM_ADDR_1", CMIC_SER0_MEM_ADDR_1r }, \ 872 { 0x0001201c, "CMIC_SER_RANGE1_DATAENTRY_LEN", CMIC_SER_RANGE1_DATAENTRY_LENr }, \ 873 { 0x0001201c, "CMIC_SER0_RANGE1_DATAENTRY_LEN", CMIC_SER0_RANGE1_DATAENTRY_LENr }, \ 874 { 0x00012020, "CMIC_SER_START_ADDR_2", CMIC_SER_START_ADDR_2r }, \ 875 { 0x00012020, "CMIC_SER0_START_ADDR_2", CMIC_SER0_START_ADDR_2r }, \ 876 { 0x00012024, "CMIC_SER0_END_ADDR_2", CMIC_SER0_END_ADDR_2r }, \ 877 { 0x00012024, "CMIC_SER_END_ADDR_2", CMIC_SER_END_ADDR_2r }, \ 878 { 0x00012028, "CMIC_SER_MEM_ADDR_2", CMIC_SER_MEM_ADDR_2r }, \ 879 { 0x00012028, "CMIC_SER0_MEM_ADDR_2", CMIC_SER0_MEM_ADDR_2r }, \ 880 { 0x0001202c, "CMIC_SER_RANGE2_DATAENTRY_LEN", CMIC_SER_RANGE2_DATAENTRY_LENr }, \ 881 { 0x0001202c, "CMIC_SER0_RANGE2_DATAENTRY_LEN", CMIC_SER0_RANGE2_DATAENTRY_LENr }, \ 882 { 0x00012030, "CMIC_SER0_START_ADDR_3", CMIC_SER0_START_ADDR_3r }, \ 883 { 0x00012030, "CMIC_SER_START_ADDR_3", CMIC_SER_START_ADDR_3r }, \ 884 { 0x00012034, "CMIC_SER0_END_ADDR_3", CMIC_SER0_END_ADDR_3r }, \ 885 { 0x00012034, "CMIC_SER_END_ADDR_3", CMIC_SER_END_ADDR_3r }, \ 886 { 0x00012038, "CMIC_SER_MEM_ADDR_3", CMIC_SER_MEM_ADDR_3r }, \ 887 { 0x00012038, "CMIC_SER0_MEM_ADDR_3", CMIC_SER0_MEM_ADDR_3r }, \ 888 { 0x0001203c, "CMIC_SER_RANGE3_DATAENTRY_LEN", CMIC_SER_RANGE3_DATAENTRY_LENr }, \ 889 { 0x0001203c, "CMIC_SER0_RANGE3_DATAENTRY_LEN", CMIC_SER0_RANGE3_DATAENTRY_LENr }, \ 890 { 0x00012040, "CMIC_SER0_START_ADDR_4", CMIC_SER0_START_ADDR_4r }, \ 891 { 0x00012040, "CMIC_SER_START_ADDR_4", CMIC_SER_START_ADDR_4r }, \ 892 { 0x00012044, "CMIC_SER0_END_ADDR_4", CMIC_SER0_END_ADDR_4r }, \ 893 { 0x00012044, "CMIC_SER_END_ADDR_4", CMIC_SER_END_ADDR_4r }, \ 894 { 0x00012048, "CMIC_SER_MEM_ADDR_4", CMIC_SER_MEM_ADDR_4r }, \ 895 { 0x00012048, "CMIC_SER0_MEM_ADDR_4", CMIC_SER0_MEM_ADDR_4r }, \ 896 { 0x0001204c, "CMIC_SER_RANGE4_DATAENTRY_LEN", CMIC_SER_RANGE4_DATAENTRY_LENr }, \ 897 { 0x0001204c, "CMIC_SER0_RANGE4_DATAENTRY_LEN", CMIC_SER0_RANGE4_DATAENTRY_LENr }, \ 898 { 0x00012050, "CMIC_SER0_START_ADDR_5", CMIC_SER0_START_ADDR_5r }, \ 899 { 0x00012050, "CMIC_SER_START_ADDR_5", CMIC_SER_START_ADDR_5r }, \ 900 { 0x00012054, "CMIC_SER0_END_ADDR_5", CMIC_SER0_END_ADDR_5r }, \ 901 { 0x00012054, "CMIC_SER_END_ADDR_5", CMIC_SER_END_ADDR_5r }, \ 902 { 0x00012058, "CMIC_SER_MEM_ADDR_5", CMIC_SER_MEM_ADDR_5r }, \ 903 { 0x00012058, "CMIC_SER0_MEM_ADDR_5", CMIC_SER0_MEM_ADDR_5r }, \ 904 { 0x0001205c, "CMIC_SER_RANGE5_DATAENTRY_LEN", CMIC_SER_RANGE5_DATAENTRY_LENr }, \ 905 { 0x0001205c, "CMIC_SER0_RANGE5_DATAENTRY_LEN", CMIC_SER0_RANGE5_DATAENTRY_LENr }, \ 906 { 0x00012060, "CMIC_SER_START_ADDR_6", CMIC_SER_START_ADDR_6r }, \ 907 { 0x00012060, "CMIC_SER0_START_ADDR_6", CMIC_SER0_START_ADDR_6r }, \ 908 { 0x00012064, "CMIC_SER0_END_ADDR_6", CMIC_SER0_END_ADDR_6r }, \ 909 { 0x00012064, "CMIC_SER_END_ADDR_6", CMIC_SER_END_ADDR_6r }, \ 910 { 0x00012068, "CMIC_SER0_MEM_ADDR_6", CMIC_SER0_MEM_ADDR_6r }, \ 911 { 0x00012068, "CMIC_SER_MEM_ADDR_6", CMIC_SER_MEM_ADDR_6r }, \ 912 { 0x0001206c, "CMIC_SER_RANGE6_DATAENTRY_LEN", CMIC_SER_RANGE6_DATAENTRY_LENr }, \ 913 { 0x0001206c, "CMIC_SER0_RANGE6_DATAENTRY_LEN", CMIC_SER0_RANGE6_DATAENTRY_LENr }, \ 914 { 0x00012070, "CMIC_SER_START_ADDR_7", CMIC_SER_START_ADDR_7r }, \ 915 { 0x00012070, "CMIC_SER0_START_ADDR_7", CMIC_SER0_START_ADDR_7r }, \ 916 { 0x00012074, "CMIC_SER_END_ADDR_7", CMIC_SER_END_ADDR_7r }, \ 917 { 0x00012074, "CMIC_SER0_END_ADDR_7", CMIC_SER0_END_ADDR_7r }, \ 918 { 0x00012078, "CMIC_SER0_MEM_ADDR_7", CMIC_SER0_MEM_ADDR_7r }, \ 919 { 0x00012078, "CMIC_SER_MEM_ADDR_7", CMIC_SER_MEM_ADDR_7r }, \ 920 { 0x0001207c, "CMIC_SER_RANGE7_DATAENTRY_LEN", CMIC_SER_RANGE7_DATAENTRY_LENr }, \ 921 { 0x0001207c, "CMIC_SER0_RANGE7_DATAENTRY_LEN", CMIC_SER0_RANGE7_DATAENTRY_LENr }, \ 922 { 0x00012080, "CMIC_SER_START_ADDR_8", CMIC_SER_START_ADDR_8r }, \ 923 { 0x00012080, "CMIC_SER0_START_ADDR_8", CMIC_SER0_START_ADDR_8r }, \ 924 { 0x00012084, "CMIC_SER_END_ADDR_8", CMIC_SER_END_ADDR_8r }, \ 925 { 0x00012084, "CMIC_SER0_END_ADDR_8", CMIC_SER0_END_ADDR_8r }, \ 926 { 0x00012088, "CMIC_SER0_MEM_ADDR_8", CMIC_SER0_MEM_ADDR_8r }, \ 927 { 0x00012088, "CMIC_SER_MEM_ADDR_8", CMIC_SER_MEM_ADDR_8r }, \ 928 { 0x0001208c, "CMIC_SER_RANGE8_DATAENTRY_LEN", CMIC_SER_RANGE8_DATAENTRY_LENr }, \ 929 { 0x0001208c, "CMIC_SER0_RANGE8_DATAENTRY_LEN", CMIC_SER0_RANGE8_DATAENTRY_LENr }, \ 930 { 0x00012090, "CMIC_SER_START_ADDR_9", CMIC_SER_START_ADDR_9r }, \ 931 { 0x00012090, "CMIC_SER0_START_ADDR_9", CMIC_SER0_START_ADDR_9r }, \ 932 { 0x00012094, "CMIC_SER_END_ADDR_9", CMIC_SER_END_ADDR_9r }, \ 933 { 0x00012094, "CMIC_SER0_END_ADDR_9", CMIC_SER0_END_ADDR_9r }, \ 934 { 0x00012098, "CMIC_SER0_MEM_ADDR_9", CMIC_SER0_MEM_ADDR_9r }, \ 935 { 0x00012098, "CMIC_SER_MEM_ADDR_9", CMIC_SER_MEM_ADDR_9r }, \ 936 { 0x0001209c, "CMIC_SER0_RANGE9_DATAENTRY_LEN", CMIC_SER0_RANGE9_DATAENTRY_LENr }, \ 937 { 0x0001209c, "CMIC_SER_RANGE9_DATAENTRY_LEN", CMIC_SER_RANGE9_DATAENTRY_LENr }, \ 938 { 0x000120a0, "CMIC_SER0_START_ADDR_10", CMIC_SER0_START_ADDR_10r }, \ 939 { 0x000120a0, "CMIC_SER_START_ADDR_10", CMIC_SER_START_ADDR_10r }, \ 940 { 0x000120a4, "CMIC_SER0_END_ADDR_10", CMIC_SER0_END_ADDR_10r }, \ 941 { 0x000120a4, "CMIC_SER_END_ADDR_10", CMIC_SER_END_ADDR_10r }, \ 942 { 0x000120a8, "CMIC_SER0_MEM_ADDR_10", CMIC_SER0_MEM_ADDR_10r }, \ 943 { 0x000120a8, "CMIC_SER_MEM_ADDR_10", CMIC_SER_MEM_ADDR_10r }, \ 944 { 0x000120ac, "CMIC_SER0_RANGE10_DATAENTRY_LEN", CMIC_SER0_RANGE10_DATAENTRY_LENr }, \ 945 { 0x000120ac, "CMIC_SER_RANGE10_DATAENTRY_LEN", CMIC_SER_RANGE10_DATAENTRY_LENr }, \ 946 { 0x000120b0, "CMIC_SER0_START_ADDR_11", CMIC_SER0_START_ADDR_11r }, \ 947 { 0x000120b0, "CMIC_SER_START_ADDR_11", CMIC_SER_START_ADDR_11r }, \ 948 { 0x000120b4, "CMIC_SER_END_ADDR_11", CMIC_SER_END_ADDR_11r }, \ 949 { 0x000120b4, "CMIC_SER0_END_ADDR_11", CMIC_SER0_END_ADDR_11r }, \ 950 { 0x000120b8, "CMIC_SER0_MEM_ADDR_11", CMIC_SER0_MEM_ADDR_11r }, \ 951 { 0x000120b8, "CMIC_SER_MEM_ADDR_11", CMIC_SER_MEM_ADDR_11r }, \ 952 { 0x000120bc, "CMIC_SER_RANGE11_DATAENTRY_LEN", CMIC_SER_RANGE11_DATAENTRY_LENr }, \ 953 { 0x000120bc, "CMIC_SER0_RANGE11_DATAENTRY_LEN", CMIC_SER0_RANGE11_DATAENTRY_LENr }, \ 954 { 0x000120c0, "CMIC_SER_START_ADDR_12", CMIC_SER_START_ADDR_12r }, \ 955 { 0x000120c0, "CMIC_SER0_START_ADDR_12", CMIC_SER0_START_ADDR_12r }, \ 956 { 0x000120c4, "CMIC_SER_END_ADDR_12", CMIC_SER_END_ADDR_12r }, \ 957 { 0x000120c4, "CMIC_SER0_END_ADDR_12", CMIC_SER0_END_ADDR_12r }, \ 958 { 0x000120c8, "CMIC_SER0_MEM_ADDR_12", CMIC_SER0_MEM_ADDR_12r }, \ 959 { 0x000120c8, "CMIC_SER_MEM_ADDR_12", CMIC_SER_MEM_ADDR_12r }, \ 960 { 0x000120cc, "CMIC_SER0_RANGE12_DATAENTRY_LEN", CMIC_SER0_RANGE12_DATAENTRY_LENr }, \ 961 { 0x000120cc, "CMIC_SER_RANGE12_DATAENTRY_LEN", CMIC_SER_RANGE12_DATAENTRY_LENr }, \ 962 { 0x000120d0, "CMIC_SER_START_ADDR_13", CMIC_SER_START_ADDR_13r }, \ 963 { 0x000120d0, "CMIC_SER0_START_ADDR_13", CMIC_SER0_START_ADDR_13r }, \ 964 { 0x000120d4, "CMIC_SER0_END_ADDR_13", CMIC_SER0_END_ADDR_13r }, \ 965 { 0x000120d4, "CMIC_SER_END_ADDR_13", CMIC_SER_END_ADDR_13r }, \ 966 { 0x000120d8, "CMIC_SER0_MEM_ADDR_13", CMIC_SER0_MEM_ADDR_13r }, \ 967 { 0x000120d8, "CMIC_SER_MEM_ADDR_13", CMIC_SER_MEM_ADDR_13r }, \ 968 { 0x000120dc, "CMIC_SER0_RANGE13_DATAENTRY_LEN", CMIC_SER0_RANGE13_DATAENTRY_LENr }, \ 969 { 0x000120dc, "CMIC_SER_RANGE13_DATAENTRY_LEN", CMIC_SER_RANGE13_DATAENTRY_LENr }, \ 970 { 0x000120e0, "CMIC_SER_START_ADDR_14", CMIC_SER_START_ADDR_14r }, \ 971 { 0x000120e0, "CMIC_SER0_START_ADDR_14", CMIC_SER0_START_ADDR_14r }, \ 972 { 0x000120e4, "CMIC_SER0_END_ADDR_14", CMIC_SER0_END_ADDR_14r }, \ 973 { 0x000120e4, "CMIC_SER_END_ADDR_14", CMIC_SER_END_ADDR_14r }, \ 974 { 0x000120e8, "CMIC_SER0_MEM_ADDR_14", CMIC_SER0_MEM_ADDR_14r }, \ 975 { 0x000120e8, "CMIC_SER_MEM_ADDR_14", CMIC_SER_MEM_ADDR_14r }, \ 976 { 0x000120ec, "CMIC_SER_RANGE14_DATAENTRY_LEN", CMIC_SER_RANGE14_DATAENTRY_LENr }, \ 977 { 0x000120ec, "CMIC_SER0_RANGE14_DATAENTRY_LEN", CMIC_SER0_RANGE14_DATAENTRY_LENr }, \ 978 { 0x000120f0, "CMIC_SER_START_ADDR_15", CMIC_SER_START_ADDR_15r }, \ 979 { 0x000120f0, "CMIC_SER0_START_ADDR_15", CMIC_SER0_START_ADDR_15r }, \ 980 { 0x000120f4, "CMIC_SER0_END_ADDR_15", CMIC_SER0_END_ADDR_15r }, \ 981 { 0x000120f4, "CMIC_SER_END_ADDR_15", CMIC_SER_END_ADDR_15r }, \ 982 { 0x000120f8, "CMIC_SER0_MEM_ADDR_15", CMIC_SER0_MEM_ADDR_15r }, \ 983 { 0x000120f8, "CMIC_SER_MEM_ADDR_15", CMIC_SER_MEM_ADDR_15r }, \ 984 { 0x000120fc, "CMIC_SER_RANGE15_DATAENTRY_LEN", CMIC_SER_RANGE15_DATAENTRY_LENr }, \ 985 { 0x000120fc, "CMIC_SER0_RANGE15_DATAENTRY_LEN", CMIC_SER0_RANGE15_DATAENTRY_LENr }, \ 986 { 0x00012100, "CMIC_SER_START_ADDR_16", CMIC_SER_START_ADDR_16r }, \ 987 { 0x00012100, "CMIC_SER0_START_ADDR_16", CMIC_SER0_START_ADDR_16r }, \ 988 { 0x00012104, "CMIC_SER_END_ADDR_16", CMIC_SER_END_ADDR_16r }, \ 989 { 0x00012104, "CMIC_SER0_END_ADDR_16", CMIC_SER0_END_ADDR_16r }, \ 990 { 0x00012108, "CMIC_SER0_MEM_ADDR_16", CMIC_SER0_MEM_ADDR_16r }, \ 991 { 0x00012108, "CMIC_SER_MEM_ADDR_16", CMIC_SER_MEM_ADDR_16r }, \ 992 { 0x0001210c, "CMIC_SER_RANGE16_DATAENTRY_LEN", CMIC_SER_RANGE16_DATAENTRY_LENr }, \ 993 { 0x0001210c, "CMIC_SER0_RANGE16_DATAENTRY_LEN", CMIC_SER0_RANGE16_DATAENTRY_LENr }, \ 994 { 0x00012110, "CMIC_SER0_START_ADDR_17", CMIC_SER0_START_ADDR_17r }, \ 995 { 0x00012110, "CMIC_SER_START_ADDR_17", CMIC_SER_START_ADDR_17r }, \ 996 { 0x00012114, "CMIC_SER0_END_ADDR_17", CMIC_SER0_END_ADDR_17r }, \ 997 { 0x00012114, "CMIC_SER_END_ADDR_17", CMIC_SER_END_ADDR_17r }, \ 998 { 0x00012118, "CMIC_SER_MEM_ADDR_17", CMIC_SER_MEM_ADDR_17r }, \ 999 { 0x00012118, "CMIC_SER0_MEM_ADDR_17", CMIC_SER0_MEM_ADDR_17r }, \ 1000 { 0x0001211c, "CMIC_SER_RANGE17_DATAENTRY_LEN", CMIC_SER_RANGE17_DATAENTRY_LENr }, \ 1001 { 0x0001211c, "CMIC_SER0_RANGE17_DATAENTRY_LEN", CMIC_SER0_RANGE17_DATAENTRY_LENr }, \ 1002 { 0x00012120, "CMIC_SER0_START_ADDR_18", CMIC_SER0_START_ADDR_18r }, \ 1003 { 0x00012120, "CMIC_SER_START_ADDR_18", CMIC_SER_START_ADDR_18r }, \ 1004 { 0x00012124, "CMIC_SER0_END_ADDR_18", CMIC_SER0_END_ADDR_18r }, \ 1005 { 0x00012124, "CMIC_SER_END_ADDR_18", CMIC_SER_END_ADDR_18r }, \ 1006 { 0x00012128, "CMIC_SER_MEM_ADDR_18", CMIC_SER_MEM_ADDR_18r }, \ 1007 { 0x00012128, "CMIC_SER0_MEM_ADDR_18", CMIC_SER0_MEM_ADDR_18r }, \ 1008 { 0x0001212c, "CMIC_SER0_RANGE18_DATAENTRY_LEN", CMIC_SER0_RANGE18_DATAENTRY_LENr }, \ 1009 { 0x0001212c, "CMIC_SER_RANGE18_DATAENTRY_LEN", CMIC_SER_RANGE18_DATAENTRY_LENr }, \ 1010 { 0x00012130, "CMIC_SER0_START_ADDR_19", CMIC_SER0_START_ADDR_19r }, \ 1011 { 0x00012130, "CMIC_SER_START_ADDR_19", CMIC_SER_START_ADDR_19r }, \ 1012 { 0x00012134, "CMIC_SER0_END_ADDR_19", CMIC_SER0_END_ADDR_19r }, \ 1013 { 0x00012134, "CMIC_SER_END_ADDR_19", CMIC_SER_END_ADDR_19r }, \ 1014 { 0x00012138, "CMIC_SER_MEM_ADDR_19", CMIC_SER_MEM_ADDR_19r }, \ 1015 { 0x00012138, "CMIC_SER0_MEM_ADDR_19", CMIC_SER0_MEM_ADDR_19r }, \ 1016 { 0x0001213c, "CMIC_SER0_RANGE19_DATAENTRY_LEN", CMIC_SER0_RANGE19_DATAENTRY_LENr }, \ 1017 { 0x0001213c, "CMIC_SER_RANGE19_DATAENTRY_LEN", CMIC_SER_RANGE19_DATAENTRY_LENr }, \ 1018 { 0x00012140, "CMIC_SER0_START_ADDR_20", CMIC_SER0_START_ADDR_20r }, \ 1019 { 0x00012140, "CMIC_SER_START_ADDR_20", CMIC_SER_START_ADDR_20r }, \ 1020 { 0x00012144, "CMIC_SER0_END_ADDR_20", CMIC_SER0_END_ADDR_20r }, \ 1021 { 0x00012144, "CMIC_SER_END_ADDR_20", CMIC_SER_END_ADDR_20r }, \ 1022 { 0x00012148, "CMIC_SER0_MEM_ADDR_20", CMIC_SER0_MEM_ADDR_20r }, \ 1023 { 0x00012148, "CMIC_SER_MEM_ADDR_20", CMIC_SER_MEM_ADDR_20r }, \ 1024 { 0x0001214c, "CMIC_SER_RANGE20_DATAENTRY_LEN", CMIC_SER_RANGE20_DATAENTRY_LENr }, \ 1025 { 0x0001214c, "CMIC_SER0_RANGE20_DATAENTRY_LEN", CMIC_SER0_RANGE20_DATAENTRY_LENr }, \ 1026 { 0x00012150, "CMIC_SER_START_ADDR_21", CMIC_SER_START_ADDR_21r }, \ 1027 { 0x00012150, "CMIC_SER0_START_ADDR_21", CMIC_SER0_START_ADDR_21r }, \ 1028 { 0x00012154, "CMIC_SER0_END_ADDR_21", CMIC_SER0_END_ADDR_21r }, \ 1029 { 0x00012154, "CMIC_SER_END_ADDR_21", CMIC_SER_END_ADDR_21r }, \ 1030 { 0x00012158, "CMIC_SER0_MEM_ADDR_21", CMIC_SER0_MEM_ADDR_21r }, \ 1031 { 0x00012158, "CMIC_SER_MEM_ADDR_21", CMIC_SER_MEM_ADDR_21r }, \ 1032 { 0x0001215c, "CMIC_SER0_RANGE21_DATAENTRY_LEN", CMIC_SER0_RANGE21_DATAENTRY_LENr }, \ 1033 { 0x0001215c, "CMIC_SER_RANGE21_DATAENTRY_LEN", CMIC_SER_RANGE21_DATAENTRY_LENr }, \ 1034 { 0x00012160, "CMIC_SER0_START_ADDR_22", CMIC_SER0_START_ADDR_22r }, \ 1035 { 0x00012160, "CMIC_SER_START_ADDR_22", CMIC_SER_START_ADDR_22r }, \ 1036 { 0x00012164, "CMIC_SER0_END_ADDR_22", CMIC_SER0_END_ADDR_22r }, \ 1037 { 0x00012164, "CMIC_SER_END_ADDR_22", CMIC_SER_END_ADDR_22r }, \ 1038 { 0x00012168, "CMIC_SER0_MEM_ADDR_22", CMIC_SER0_MEM_ADDR_22r }, \ 1039 { 0x00012168, "CMIC_SER_MEM_ADDR_22", CMIC_SER_MEM_ADDR_22r }, \ 1040 { 0x0001216c, "CMIC_SER_RANGE22_DATAENTRY_LEN", CMIC_SER_RANGE22_DATAENTRY_LENr }, \ 1041 { 0x0001216c, "CMIC_SER0_RANGE22_DATAENTRY_LEN", CMIC_SER0_RANGE22_DATAENTRY_LENr }, \ 1042 { 0x00012170, "CMIC_SER0_START_ADDR_23", CMIC_SER0_START_ADDR_23r }, \ 1043 { 0x00012170, "CMIC_SER_START_ADDR_23", CMIC_SER_START_ADDR_23r }, \ 1044 { 0x00012174, "CMIC_SER0_END_ADDR_23", CMIC_SER0_END_ADDR_23r }, \ 1045 { 0x00012174, "CMIC_SER_END_ADDR_23", CMIC_SER_END_ADDR_23r }, \ 1046 { 0x00012178, "CMIC_SER_MEM_ADDR_23", CMIC_SER_MEM_ADDR_23r }, \ 1047 { 0x00012178, "CMIC_SER0_MEM_ADDR_23", CMIC_SER0_MEM_ADDR_23r }, \ 1048 { 0x0001217c, "CMIC_SER_RANGE23_DATAENTRY_LEN", CMIC_SER_RANGE23_DATAENTRY_LENr }, \ 1049 { 0x0001217c, "CMIC_SER0_RANGE23_DATAENTRY_LEN", CMIC_SER0_RANGE23_DATAENTRY_LENr }, \ 1050 { 0x00012180, "CMIC_SER0_START_ADDR_24", CMIC_SER0_START_ADDR_24r }, \ 1051 { 0x00012180, "CMIC_SER_START_ADDR_24", CMIC_SER_START_ADDR_24r }, \ 1052 { 0x00012184, "CMIC_SER_END_ADDR_24", CMIC_SER_END_ADDR_24r }, \ 1053 { 0x00012184, "CMIC_SER0_END_ADDR_24", CMIC_SER0_END_ADDR_24r }, \ 1054 { 0x00012188, "CMIC_SER_MEM_ADDR_24", CMIC_SER_MEM_ADDR_24r }, \ 1055 { 0x00012188, "CMIC_SER0_MEM_ADDR_24", CMIC_SER0_MEM_ADDR_24r }, \ 1056 { 0x0001218c, "CMIC_SER_RANGE24_DATAENTRY_LEN", CMIC_SER_RANGE24_DATAENTRY_LENr }, \ 1057 { 0x0001218c, "CMIC_SER0_RANGE24_DATAENTRY_LEN", CMIC_SER0_RANGE24_DATAENTRY_LENr }, \ 1058 { 0x00012190, "CMIC_SER0_START_ADDR_25", CMIC_SER0_START_ADDR_25r }, \ 1059 { 0x00012190, "CMIC_SER_START_ADDR_25", CMIC_SER_START_ADDR_25r }, \ 1060 { 0x00012194, "CMIC_SER0_END_ADDR_25", CMIC_SER0_END_ADDR_25r }, \ 1061 { 0x00012194, "CMIC_SER_END_ADDR_25", CMIC_SER_END_ADDR_25r }, \ 1062 { 0x00012198, "CMIC_SER_MEM_ADDR_25", CMIC_SER_MEM_ADDR_25r }, \ 1063 { 0x00012198, "CMIC_SER0_MEM_ADDR_25", CMIC_SER0_MEM_ADDR_25r }, \ 1064 { 0x0001219c, "CMIC_SER_RANGE25_DATAENTRY_LEN", CMIC_SER_RANGE25_DATAENTRY_LENr }, \ 1065 { 0x0001219c, "CMIC_SER0_RANGE25_DATAENTRY_LEN", CMIC_SER0_RANGE25_DATAENTRY_LENr }, \ 1066 { 0x000121a0, "CMIC_SER0_START_ADDR_26", CMIC_SER0_START_ADDR_26r }, \ 1067 { 0x000121a0, "CMIC_SER_START_ADDR_26", CMIC_SER_START_ADDR_26r }, \ 1068 { 0x000121a4, "CMIC_SER_END_ADDR_26", CMIC_SER_END_ADDR_26r }, \ 1069 { 0x000121a4, "CMIC_SER0_END_ADDR_26", CMIC_SER0_END_ADDR_26r }, \ 1070 { 0x000121a8, "CMIC_SER0_MEM_ADDR_26", CMIC_SER0_MEM_ADDR_26r }, \ 1071 { 0x000121a8, "CMIC_SER_MEM_ADDR_26", CMIC_SER_MEM_ADDR_26r }, \ 1072 { 0x000121ac, "CMIC_SER0_RANGE26_DATAENTRY_LEN", CMIC_SER0_RANGE26_DATAENTRY_LENr }, \ 1073 { 0x000121ac, "CMIC_SER_RANGE26_DATAENTRY_LEN", CMIC_SER_RANGE26_DATAENTRY_LENr }, \ 1074 { 0x000121b0, "CMIC_SER_START_ADDR_27", CMIC_SER_START_ADDR_27r }, \ 1075 { 0x000121b0, "CMIC_SER0_START_ADDR_27", CMIC_SER0_START_ADDR_27r }, \ 1076 { 0x000121b4, "CMIC_SER_END_ADDR_27", CMIC_SER_END_ADDR_27r }, \ 1077 { 0x000121b4, "CMIC_SER0_END_ADDR_27", CMIC_SER0_END_ADDR_27r }, \ 1078 { 0x000121b8, "CMIC_SER_MEM_ADDR_27", CMIC_SER_MEM_ADDR_27r }, \ 1079 { 0x000121b8, "CMIC_SER0_MEM_ADDR_27", CMIC_SER0_MEM_ADDR_27r }, \ 1080 { 0x000121bc, "CMIC_SER0_RANGE27_DATAENTRY_LEN", CMIC_SER0_RANGE27_DATAENTRY_LENr }, \ 1081 { 0x000121bc, "CMIC_SER_RANGE27_DATAENTRY_LEN", CMIC_SER_RANGE27_DATAENTRY_LENr }, \ 1082 { 0x000121c0, "CMIC_SER0_START_ADDR_28", CMIC_SER0_START_ADDR_28r }, \ 1083 { 0x000121c0, "CMIC_SER_START_ADDR_28", CMIC_SER_START_ADDR_28r }, \ 1084 { 0x000121c4, "CMIC_SER_END_ADDR_28", CMIC_SER_END_ADDR_28r }, \ 1085 { 0x000121c4, "CMIC_SER0_END_ADDR_28", CMIC_SER0_END_ADDR_28r }, \ 1086 { 0x000121c8, "CMIC_SER_MEM_ADDR_28", CMIC_SER_MEM_ADDR_28r }, \ 1087 { 0x000121c8, "CMIC_SER0_MEM_ADDR_28", CMIC_SER0_MEM_ADDR_28r }, \ 1088 { 0x000121cc, "CMIC_SER_RANGE28_DATAENTRY_LEN", CMIC_SER_RANGE28_DATAENTRY_LENr }, \ 1089 { 0x000121cc, "CMIC_SER0_RANGE28_DATAENTRY_LEN", CMIC_SER0_RANGE28_DATAENTRY_LENr }, \ 1090 { 0x000121d0, "CMIC_SER_START_ADDR_29", CMIC_SER_START_ADDR_29r }, \ 1091 { 0x000121d0, "CMIC_SER0_START_ADDR_29", CMIC_SER0_START_ADDR_29r }, \ 1092 { 0x000121d4, "CMIC_SER_END_ADDR_29", CMIC_SER_END_ADDR_29r }, \ 1093 { 0x000121d4, "CMIC_SER0_END_ADDR_29", CMIC_SER0_END_ADDR_29r }, \ 1094 { 0x000121d8, "CMIC_SER0_MEM_ADDR_29", CMIC_SER0_MEM_ADDR_29r }, \ 1095 { 0x000121d8, "CMIC_SER_MEM_ADDR_29", CMIC_SER_MEM_ADDR_29r }, \ 1096 { 0x000121dc, "CMIC_SER_RANGE29_DATAENTRY_LEN", CMIC_SER_RANGE29_DATAENTRY_LENr }, \ 1097 { 0x000121dc, "CMIC_SER0_RANGE29_DATAENTRY_LEN", CMIC_SER0_RANGE29_DATAENTRY_LENr }, \ 1098 { 0x000121e0, "CMIC_SER0_START_ADDR_30", CMIC_SER0_START_ADDR_30r }, \ 1099 { 0x000121e0, "CMIC_SER_START_ADDR_30", CMIC_SER_START_ADDR_30r }, \ 1100 { 0x000121e4, "CMIC_SER0_END_ADDR_30", CMIC_SER0_END_ADDR_30r }, \ 1101 { 0x000121e4, "CMIC_SER_END_ADDR_30", CMIC_SER_END_ADDR_30r }, \ 1102 { 0x000121e8, "CMIC_SER0_MEM_ADDR_30", CMIC_SER0_MEM_ADDR_30r }, \ 1103 { 0x000121e8, "CMIC_SER_MEM_ADDR_30", CMIC_SER_MEM_ADDR_30r }, \ 1104 { 0x000121ec, "CMIC_SER_RANGE30_DATAENTRY_LEN", CMIC_SER_RANGE30_DATAENTRY_LENr }, \ 1105 { 0x000121ec, "CMIC_SER0_RANGE30_DATAENTRY_LEN", CMIC_SER0_RANGE30_DATAENTRY_LENr }, \ 1106 { 0x000121f0, "CMIC_SER_START_ADDR_31", CMIC_SER_START_ADDR_31r }, \ 1107 { 0x000121f0, "CMIC_SER0_START_ADDR_31", CMIC_SER0_START_ADDR_31r }, \ 1108 { 0x000121f4, "CMIC_SER0_END_ADDR_31", CMIC_SER0_END_ADDR_31r }, \ 1109 { 0x000121f4, "CMIC_SER_END_ADDR_31", CMIC_SER_END_ADDR_31r }, \ 1110 { 0x000121f8, "CMIC_SER_MEM_ADDR_31", CMIC_SER_MEM_ADDR_31r }, \ 1111 { 0x000121f8, "CMIC_SER0_MEM_ADDR_31", CMIC_SER0_MEM_ADDR_31r }, \ 1112 { 0x000121fc, "CMIC_SER0_RANGE31_DATAENTRY_LEN", CMIC_SER0_RANGE31_DATAENTRY_LENr }, \ 1113 { 0x000121fc, "CMIC_SER_RANGE31_DATAENTRY_LEN", CMIC_SER_RANGE31_DATAENTRY_LENr }, \ 1114 { 0x00012200, "CMIC_SER0_FAIL_CNT", CMIC_SER0_FAIL_CNTr }, \ 1115 { 0x00012200, "CMIC_SER_FAIL_CNT", CMIC_SER_FAIL_CNTr }, \ 1116 { 0x00012204, "CMIC_SER0_FAIL_ENTRY", CMIC_SER0_FAIL_ENTRYr }, \ 1117 { 0x00012204, "CMIC_SER_FAIL_ENTRY", CMIC_SER_FAIL_ENTRYr }, \ 1118 { 0x00012208, "CMIC_SER0_MEM_DATA", CMIC_SER0_MEM_DATAr }, \ 1119 { 0x00012208, "CMIC_SER_MEM_DATA", CMIC_SER_MEM_DATAr }, \ 1120 { 0x0001220c, "CMIC_SER_MEM_ADDR", CMIC_SER_MEM_ADDRr }, \ 1121 { 0x0001220c, "CMIC_SER0_MEM_ADDR", CMIC_SER0_MEM_ADDRr }, \ 1122 { 0x00012210, "CMIC_SER_PROTECT_ADDR_RANGE_VALID", CMIC_SER_PROTECT_ADDR_RANGE_VALIDr }, \ 1123 { 0x00012210, "CMIC_SER0_PROTECT_ADDR_RANGE_VALID", CMIC_SER0_PROTECT_ADDR_RANGE_VALIDr }, \ 1124 { 0x00012214, "CMIC_SER0_INTERLEAVE_PARITY", CMIC_SER0_INTERLEAVE_PARITYr }, \ 1125 { 0x00012214, "CMIC_SER_INTERLEAVE_PARITY", CMIC_SER_INTERLEAVE_PARITYr }, \ 1126 { 0x00012218, "CMIC_SER_PARITY_MODE_SEL_15_0", CMIC_SER_PARITY_MODE_SEL_15_0r }, \ 1127 { 0x00012218, "CMIC_SER0_PARITY_MODE_SEL_15_0", CMIC_SER0_PARITY_MODE_SEL_15_0r }, \ 1128 { 0x0001221c, "CMIC_SER_PARITY_MODE_SEL_31_16", CMIC_SER_PARITY_MODE_SEL_31_16r }, \ 1129 { 0x0001221c, "CMIC_SER0_PARITY_MODE_SEL_31_16", CMIC_SER0_PARITY_MODE_SEL_31_16r }, \ 1130 { 0x00012220, "CMIC_SER0_POWER_DOWN_MEM_LOWER", CMIC_SER0_POWER_DOWN_MEM_LOWERr }, \ 1131 { 0x00012220, "CMIC_SER_POWER_DOWN_MEM_LOWER", CMIC_SER_POWER_DOWN_MEM_LOWERr }, \ 1132 { 0x00012224, "CMIC_SER0_POWER_DOWN_MEM_UPPER", CMIC_SER0_POWER_DOWN_MEM_UPPERr }, \ 1133 { 0x00012224, "CMIC_SER_POWER_DOWN_MEM_UPPER", CMIC_SER_POWER_DOWN_MEM_UPPERr }, \ 1134 { 0x00013000, "CMIC_SER1_START_ADDR_0", CMIC_SER1_START_ADDR_0r }, \ 1135 { 0x00013004, "CMIC_SER1_END_ADDR_0", CMIC_SER1_END_ADDR_0r }, \ 1136 { 0x00013008, "CMIC_SER1_MEM_ADDR_0", CMIC_SER1_MEM_ADDR_0r }, \ 1137 { 0x0001300c, "CMIC_SER1_RANGE0_DATAENTRY_LEN", CMIC_SER1_RANGE0_DATAENTRY_LENr }, \ 1138 { 0x00013010, "CMIC_SER1_START_ADDR_1", CMIC_SER1_START_ADDR_1r }, \ 1139 { 0x00013014, "CMIC_SER1_END_ADDR_1", CMIC_SER1_END_ADDR_1r }, \ 1140 { 0x00013018, "CMIC_SER1_MEM_ADDR_1", CMIC_SER1_MEM_ADDR_1r }, \ 1141 { 0x0001301c, "CMIC_SER1_RANGE1_DATAENTRY_LEN", CMIC_SER1_RANGE1_DATAENTRY_LENr }, \ 1142 { 0x00013020, "CMIC_SER1_START_ADDR_2", CMIC_SER1_START_ADDR_2r }, \ 1143 { 0x00013024, "CMIC_SER1_END_ADDR_2", CMIC_SER1_END_ADDR_2r }, \ 1144 { 0x00013028, "CMIC_SER1_MEM_ADDR_2", CMIC_SER1_MEM_ADDR_2r }, \ 1145 { 0x0001302c, "CMIC_SER1_RANGE2_DATAENTRY_LEN", CMIC_SER1_RANGE2_DATAENTRY_LENr }, \ 1146 { 0x00013030, "CMIC_SER1_START_ADDR_3", CMIC_SER1_START_ADDR_3r }, \ 1147 { 0x00013034, "CMIC_SER1_END_ADDR_3", CMIC_SER1_END_ADDR_3r }, \ 1148 { 0x00013038, "CMIC_SER1_MEM_ADDR_3", CMIC_SER1_MEM_ADDR_3r }, \ 1149 { 0x0001303c, "CMIC_SER1_RANGE3_DATAENTRY_LEN", CMIC_SER1_RANGE3_DATAENTRY_LENr }, \ 1150 { 0x00013040, "CMIC_SER1_START_ADDR_4", CMIC_SER1_START_ADDR_4r }, \ 1151 { 0x00013044, "CMIC_SER1_END_ADDR_4", CMIC_SER1_END_ADDR_4r }, \ 1152 { 0x00013048, "CMIC_SER1_MEM_ADDR_4", CMIC_SER1_MEM_ADDR_4r }, \ 1153 { 0x0001304c, "CMIC_SER1_RANGE4_DATAENTRY_LEN", CMIC_SER1_RANGE4_DATAENTRY_LENr }, \ 1154 { 0x00013050, "CMIC_SER1_START_ADDR_5", CMIC_SER1_START_ADDR_5r }, \ 1155 { 0x00013054, "CMIC_SER1_END_ADDR_5", CMIC_SER1_END_ADDR_5r }, \ 1156 { 0x00013058, "CMIC_SER1_MEM_ADDR_5", CMIC_SER1_MEM_ADDR_5r }, \ 1157 { 0x0001305c, "CMIC_SER1_RANGE5_DATAENTRY_LEN", CMIC_SER1_RANGE5_DATAENTRY_LENr }, \ 1158 { 0x00013060, "CMIC_SER1_START_ADDR_6", CMIC_SER1_START_ADDR_6r }, \ 1159 { 0x00013064, "CMIC_SER1_END_ADDR_6", CMIC_SER1_END_ADDR_6r }, \ 1160 { 0x00013068, "CMIC_SER1_MEM_ADDR_6", CMIC_SER1_MEM_ADDR_6r }, \ 1161 { 0x0001306c, "CMIC_SER1_RANGE6_DATAENTRY_LEN", CMIC_SER1_RANGE6_DATAENTRY_LENr }, \ 1162 { 0x00013070, "CMIC_SER1_START_ADDR_7", CMIC_SER1_START_ADDR_7r }, \ 1163 { 0x00013074, "CMIC_SER1_END_ADDR_7", CMIC_SER1_END_ADDR_7r }, \ 1164 { 0x00013078, "CMIC_SER1_MEM_ADDR_7", CMIC_SER1_MEM_ADDR_7r }, \ 1165 { 0x0001307c, "CMIC_SER1_RANGE7_DATAENTRY_LEN", CMIC_SER1_RANGE7_DATAENTRY_LENr }, \ 1166 { 0x00013080, "CMIC_SER1_START_ADDR_8", CMIC_SER1_START_ADDR_8r }, \ 1167 { 0x00013084, "CMIC_SER1_END_ADDR_8", CMIC_SER1_END_ADDR_8r }, \ 1168 { 0x00013088, "CMIC_SER1_MEM_ADDR_8", CMIC_SER1_MEM_ADDR_8r }, \ 1169 { 0x0001308c, "CMIC_SER1_RANGE8_DATAENTRY_LEN", CMIC_SER1_RANGE8_DATAENTRY_LENr }, \ 1170 { 0x00013090, "CMIC_SER1_START_ADDR_9", CMIC_SER1_START_ADDR_9r }, \ 1171 { 0x00013094, "CMIC_SER1_END_ADDR_9", CMIC_SER1_END_ADDR_9r }, \ 1172 { 0x00013098, "CMIC_SER1_MEM_ADDR_9", CMIC_SER1_MEM_ADDR_9r }, \ 1173 { 0x0001309c, "CMIC_SER1_RANGE9_DATAENTRY_LEN", CMIC_SER1_RANGE9_DATAENTRY_LENr }, \ 1174 { 0x000130a0, "CMIC_SER1_START_ADDR_10", CMIC_SER1_START_ADDR_10r }, \ 1175 { 0x000130a4, "CMIC_SER1_END_ADDR_10", CMIC_SER1_END_ADDR_10r }, \ 1176 { 0x000130a8, "CMIC_SER1_MEM_ADDR_10", CMIC_SER1_MEM_ADDR_10r }, \ 1177 { 0x000130ac, "CMIC_SER1_RANGE10_DATAENTRY_LEN", CMIC_SER1_RANGE10_DATAENTRY_LENr }, \ 1178 { 0x000130b0, "CMIC_SER1_START_ADDR_11", CMIC_SER1_START_ADDR_11r }, \ 1179 { 0x000130b4, "CMIC_SER1_END_ADDR_11", CMIC_SER1_END_ADDR_11r }, \ 1180 { 0x000130b8, "CMIC_SER1_MEM_ADDR_11", CMIC_SER1_MEM_ADDR_11r }, \ 1181 { 0x000130bc, "CMIC_SER1_RANGE11_DATAENTRY_LEN", CMIC_SER1_RANGE11_DATAENTRY_LENr }, \ 1182 { 0x000130c0, "CMIC_SER1_START_ADDR_12", CMIC_SER1_START_ADDR_12r }, \ 1183 { 0x000130c4, "CMIC_SER1_END_ADDR_12", CMIC_SER1_END_ADDR_12r }, \ 1184 { 0x000130c8, "CMIC_SER1_MEM_ADDR_12", CMIC_SER1_MEM_ADDR_12r }, \ 1185 { 0x000130cc, "CMIC_SER1_RANGE12_DATAENTRY_LEN", CMIC_SER1_RANGE12_DATAENTRY_LENr }, \ 1186 { 0x000130d0, "CMIC_SER1_START_ADDR_13", CMIC_SER1_START_ADDR_13r }, \ 1187 { 0x000130d4, "CMIC_SER1_END_ADDR_13", CMIC_SER1_END_ADDR_13r }, \ 1188 { 0x000130d8, "CMIC_SER1_MEM_ADDR_13", CMIC_SER1_MEM_ADDR_13r }, \ 1189 { 0x000130dc, "CMIC_SER1_RANGE13_DATAENTRY_LEN", CMIC_SER1_RANGE13_DATAENTRY_LENr }, \ 1190 { 0x000130e0, "CMIC_SER1_START_ADDR_14", CMIC_SER1_START_ADDR_14r }, \ 1191 { 0x000130e4, "CMIC_SER1_END_ADDR_14", CMIC_SER1_END_ADDR_14r }, \ 1192 { 0x000130e8, "CMIC_SER1_MEM_ADDR_14", CMIC_SER1_MEM_ADDR_14r }, \ 1193 { 0x000130ec, "CMIC_SER1_RANGE14_DATAENTRY_LEN", CMIC_SER1_RANGE14_DATAENTRY_LENr }, \ 1194 { 0x000130f0, "CMIC_SER1_START_ADDR_15", CMIC_SER1_START_ADDR_15r }, \ 1195 { 0x000130f4, "CMIC_SER1_END_ADDR_15", CMIC_SER1_END_ADDR_15r }, \ 1196 { 0x000130f8, "CMIC_SER1_MEM_ADDR_15", CMIC_SER1_MEM_ADDR_15r }, \ 1197 { 0x000130fc, "CMIC_SER1_RANGE15_DATAENTRY_LEN", CMIC_SER1_RANGE15_DATAENTRY_LENr }, \ 1198 { 0x00013100, "CMIC_SER1_START_ADDR_16", CMIC_SER1_START_ADDR_16r }, \ 1199 { 0x00013104, "CMIC_SER1_END_ADDR_16", CMIC_SER1_END_ADDR_16r }, \ 1200 { 0x00013108, "CMIC_SER1_MEM_ADDR_16", CMIC_SER1_MEM_ADDR_16r }, \ 1201 { 0x0001310c, "CMIC_SER1_RANGE16_DATAENTRY_LEN", CMIC_SER1_RANGE16_DATAENTRY_LENr }, \ 1202 { 0x00013110, "CMIC_SER1_START_ADDR_17", CMIC_SER1_START_ADDR_17r }, \ 1203 { 0x00013114, "CMIC_SER1_END_ADDR_17", CMIC_SER1_END_ADDR_17r }, \ 1204 { 0x00013118, "CMIC_SER1_MEM_ADDR_17", CMIC_SER1_MEM_ADDR_17r }, \ 1205 { 0x0001311c, "CMIC_SER1_RANGE17_DATAENTRY_LEN", CMIC_SER1_RANGE17_DATAENTRY_LENr }, \ 1206 { 0x00013120, "CMIC_SER1_START_ADDR_18", CMIC_SER1_START_ADDR_18r }, \ 1207 { 0x00013124, "CMIC_SER1_END_ADDR_18", CMIC_SER1_END_ADDR_18r }, \ 1208 { 0x00013128, "CMIC_SER1_MEM_ADDR_18", CMIC_SER1_MEM_ADDR_18r }, \ 1209 { 0x0001312c, "CMIC_SER1_RANGE18_DATAENTRY_LEN", CMIC_SER1_RANGE18_DATAENTRY_LENr }, \ 1210 { 0x00013130, "CMIC_SER1_START_ADDR_19", CMIC_SER1_START_ADDR_19r }, \ 1211 { 0x00013134, "CMIC_SER1_END_ADDR_19", CMIC_SER1_END_ADDR_19r }, \ 1212 { 0x00013138, "CMIC_SER1_MEM_ADDR_19", CMIC_SER1_MEM_ADDR_19r }, \ 1213 { 0x0001313c, "CMIC_SER1_RANGE19_DATAENTRY_LEN", CMIC_SER1_RANGE19_DATAENTRY_LENr }, \ 1214 { 0x00013140, "CMIC_SER1_START_ADDR_20", CMIC_SER1_START_ADDR_20r }, \ 1215 { 0x00013144, "CMIC_SER1_END_ADDR_20", CMIC_SER1_END_ADDR_20r }, \ 1216 { 0x00013148, "CMIC_SER1_MEM_ADDR_20", CMIC_SER1_MEM_ADDR_20r }, \ 1217 { 0x0001314c, "CMIC_SER1_RANGE20_DATAENTRY_LEN", CMIC_SER1_RANGE20_DATAENTRY_LENr }, \ 1218 { 0x00013150, "CMIC_SER1_START_ADDR_21", CMIC_SER1_START_ADDR_21r }, \ 1219 { 0x00013154, "CMIC_SER1_END_ADDR_21", CMIC_SER1_END_ADDR_21r }, \ 1220 { 0x00013158, "CMIC_SER1_MEM_ADDR_21", CMIC_SER1_MEM_ADDR_21r }, \ 1221 { 0x0001315c, "CMIC_SER1_RANGE21_DATAENTRY_LEN", CMIC_SER1_RANGE21_DATAENTRY_LENr }, \ 1222 { 0x00013160, "CMIC_SER1_START_ADDR_22", CMIC_SER1_START_ADDR_22r }, \ 1223 { 0x00013164, "CMIC_SER1_END_ADDR_22", CMIC_SER1_END_ADDR_22r }, \ 1224 { 0x00013168, "CMIC_SER1_MEM_ADDR_22", CMIC_SER1_MEM_ADDR_22r }, \ 1225 { 0x0001316c, "CMIC_SER1_RANGE22_DATAENTRY_LEN", CMIC_SER1_RANGE22_DATAENTRY_LENr }, \ 1226 { 0x00013170, "CMIC_SER1_START_ADDR_23", CMIC_SER1_START_ADDR_23r }, \ 1227 { 0x00013174, "CMIC_SER1_END_ADDR_23", CMIC_SER1_END_ADDR_23r }, \ 1228 { 0x00013178, "CMIC_SER1_MEM_ADDR_23", CMIC_SER1_MEM_ADDR_23r }, \ 1229 { 0x0001317c, "CMIC_SER1_RANGE23_DATAENTRY_LEN", CMIC_SER1_RANGE23_DATAENTRY_LENr }, \ 1230 { 0x00013180, "CMIC_SER1_START_ADDR_24", CMIC_SER1_START_ADDR_24r }, \ 1231 { 0x00013184, "CMIC_SER1_END_ADDR_24", CMIC_SER1_END_ADDR_24r }, \ 1232 { 0x00013188, "CMIC_SER1_MEM_ADDR_24", CMIC_SER1_MEM_ADDR_24r }, \ 1233 { 0x0001318c, "CMIC_SER1_RANGE24_DATAENTRY_LEN", CMIC_SER1_RANGE24_DATAENTRY_LENr }, \ 1234 { 0x00013190, "CMIC_SER1_START_ADDR_25", CMIC_SER1_START_ADDR_25r }, \ 1235 { 0x00013194, "CMIC_SER1_END_ADDR_25", CMIC_SER1_END_ADDR_25r }, \ 1236 { 0x00013198, "CMIC_SER1_MEM_ADDR_25", CMIC_SER1_MEM_ADDR_25r }, \ 1237 { 0x0001319c, "CMIC_SER1_RANGE25_DATAENTRY_LEN", CMIC_SER1_RANGE25_DATAENTRY_LENr }, \ 1238 { 0x000131a0, "CMIC_SER1_START_ADDR_26", CMIC_SER1_START_ADDR_26r }, \ 1239 { 0x000131a4, "CMIC_SER1_END_ADDR_26", CMIC_SER1_END_ADDR_26r }, \ 1240 { 0x000131a8, "CMIC_SER1_MEM_ADDR_26", CMIC_SER1_MEM_ADDR_26r }, \ 1241 { 0x000131ac, "CMIC_SER1_RANGE26_DATAENTRY_LEN", CMIC_SER1_RANGE26_DATAENTRY_LENr }, \ 1242 { 0x000131b0, "CMIC_SER1_START_ADDR_27", CMIC_SER1_START_ADDR_27r }, \ 1243 { 0x000131b4, "CMIC_SER1_END_ADDR_27", CMIC_SER1_END_ADDR_27r }, \ 1244 { 0x000131b8, "CMIC_SER1_MEM_ADDR_27", CMIC_SER1_MEM_ADDR_27r }, \ 1245 { 0x000131bc, "CMIC_SER1_RANGE27_DATAENTRY_LEN", CMIC_SER1_RANGE27_DATAENTRY_LENr }, \ 1246 { 0x000131c0, "CMIC_SER1_START_ADDR_28", CMIC_SER1_START_ADDR_28r }, \ 1247 { 0x000131c4, "CMIC_SER1_END_ADDR_28", CMIC_SER1_END_ADDR_28r }, \ 1248 { 0x000131c8, "CMIC_SER1_MEM_ADDR_28", CMIC_SER1_MEM_ADDR_28r }, \ 1249 { 0x000131cc, "CMIC_SER1_RANGE28_DATAENTRY_LEN", CMIC_SER1_RANGE28_DATAENTRY_LENr }, \ 1250 { 0x000131d0, "CMIC_SER1_START_ADDR_29", CMIC_SER1_START_ADDR_29r }, \ 1251 { 0x000131d4, "CMIC_SER1_END_ADDR_29", CMIC_SER1_END_ADDR_29r }, \ 1252 { 0x000131d8, "CMIC_SER1_MEM_ADDR_29", CMIC_SER1_MEM_ADDR_29r }, \ 1253 { 0x000131dc, "CMIC_SER1_RANGE29_DATAENTRY_LEN", CMIC_SER1_RANGE29_DATAENTRY_LENr }, \ 1254 { 0x000131e0, "CMIC_SER1_START_ADDR_30", CMIC_SER1_START_ADDR_30r }, \ 1255 { 0x000131e4, "CMIC_SER1_END_ADDR_30", CMIC_SER1_END_ADDR_30r }, \ 1256 { 0x000131e8, "CMIC_SER1_MEM_ADDR_30", CMIC_SER1_MEM_ADDR_30r }, \ 1257 { 0x000131ec, "CMIC_SER1_RANGE30_DATAENTRY_LEN", CMIC_SER1_RANGE30_DATAENTRY_LENr }, \ 1258 { 0x000131f0, "CMIC_SER1_START_ADDR_31", CMIC_SER1_START_ADDR_31r }, \ 1259 { 0x000131f4, "CMIC_SER1_END_ADDR_31", CMIC_SER1_END_ADDR_31r }, \ 1260 { 0x000131f8, "CMIC_SER1_MEM_ADDR_31", CMIC_SER1_MEM_ADDR_31r }, \ 1261 { 0x000131fc, "CMIC_SER1_RANGE31_DATAENTRY_LEN", CMIC_SER1_RANGE31_DATAENTRY_LENr }, \ 1262 { 0x00013200, "CMIC_SER1_FAIL_CNT", CMIC_SER1_FAIL_CNTr }, \ 1263 { 0x00013204, "CMIC_SER1_FAIL_ENTRY", CMIC_SER1_FAIL_ENTRYr }, \ 1264 { 0x00013208, "CMIC_SER1_MEM_DATA", CMIC_SER1_MEM_DATAr }, \ 1265 { 0x0001320c, "CMIC_SER1_MEM_ADDR", CMIC_SER1_MEM_ADDRr }, \ 1266 { 0x00013210, "CMIC_SER1_PROTECT_ADDR_RANGE_VALID", CMIC_SER1_PROTECT_ADDR_RANGE_VALIDr }, \ 1267 { 0x00013214, "CMIC_SER1_INTERLEAVE_PARITY", CMIC_SER1_INTERLEAVE_PARITYr }, \ 1268 { 0x00013218, "CMIC_SER1_PARITY_MODE_SEL_15_0", CMIC_SER1_PARITY_MODE_SEL_15_0r }, \ 1269 { 0x0001321c, "CMIC_SER1_PARITY_MODE_SEL_31_16", CMIC_SER1_PARITY_MODE_SEL_31_16r }, \ 1270 { 0x00013220, "CMIC_SER1_POWER_DOWN_MEM_LOWER", CMIC_SER1_POWER_DOWN_MEM_LOWERr }, \ 1271 { 0x00013224, "CMIC_SER1_POWER_DOWN_MEM_UPPER", CMIC_SER1_POWER_DOWN_MEM_UPPERr }, \ 1272 { 0x0001a000, "CMIC_RXBUF_EPINTF_RELEASE_ALL_CREDITS", CMIC_RXBUF_EPINTF_RELEASE_ALL_CREDITSr }, \ 1273 { 0x0001a004, "CMIC_RXBUF_EPINTF_MAX_INTERFACE_CREDITS", CMIC_RXBUF_EPINTF_MAX_INTERFACE_CREDITSr }, \ 1274 { 0x0001a008, "CMIC_RXBUF_STATUSBUF_MAX_FLIST_ENTRIES", CMIC_RXBUF_STATUSBUF_MAX_FLIST_ENTRIESr }, \ 1275 { 0x0001a00c, "CMIC_RXBUF_DATABUF_MAX_FLIST_ENTRIES", CMIC_RXBUF_DATABUF_MAX_FLIST_ENTRIESr }, \ 1276 { 0x0001a010, "CMIC_RXBUF_STATUSBUF_NUM_FREE_ENTRIES", CMIC_RXBUF_STATUSBUF_NUM_FREE_ENTRIESr }, \ 1277 { 0x0001a014, "CMIC_RXBUF_DATABUF_NUM_FREE_ENTRIES", CMIC_RXBUF_DATABUF_NUM_FREE_ENTRIESr }, \ 1278 { 0x0001a018, "CMIC_RXBUF_BLOCK_STATUSBUF_ALLOC", CMIC_RXBUF_BLOCK_STATUSBUF_ALLOCr }, \ 1279 { 0x0001a01c, "CMIC_RXBUF_BLOCK_DATABUF_ALLOC", CMIC_RXBUF_BLOCK_DATABUF_ALLOCr }, \ 1280 { 0x0001a020, "CMIC_RXBUF_EPINTF_BUF_DEPTH", CMIC_RXBUF_EPINTF_BUF_DEPTHr }, \ 1281 { 0x0001a024, "CMIC_RXBUF_CONFIG", CMIC_RXBUF_CONFIGr }, \ 1282 { 0x0001a028, "CMIC_RXBUF_ECCERR_CONTROL", CMIC_RXBUF_ECCERR_CONTROLr }, \ 1283 { 0x0001a02c, "CMIC_RXBUF_MEM_CONTROL_0", CMIC_RXBUF_MEM_CONTROL_0r }, \ 1284 { 0x0001a02c, "CMIC_RXBUF_DATABUF_TM_0", CMIC_RXBUF_DATABUF_TM_0r }, \ 1285 { 0x0001a030, "CMIC_RXBUF_DATABUF_TM_1", CMIC_RXBUF_DATABUF_TM_1r }, \ 1286 { 0x0001a034, "CMIC_RXBUF_DATABUF_TM_2", CMIC_RXBUF_DATABUF_TM_2r }, \ 1287 { 0x0001a038, "CMIC_RXBUF_STATBUF_TM_0", CMIC_RXBUF_STATBUF_TM_0r }, \ 1288 { 0x0001a03c, "CMIC_RXBUF_STATBUF_TM_1", CMIC_RXBUF_STATBUF_TM_1r }, \ 1289 { 0x0001b000, "CMIC_TXBUF_MAX_BUF_LIMITS", CMIC_TXBUF_MAX_BUF_LIMITSr }, \ 1290 { 0x0001b004, "CMIC_TXBUF_MIN_BUF_LIMITS", CMIC_TXBUF_MIN_BUF_LIMITSr }, \ 1291 { 0x0001b00c, "CMIC_TXBUF_RPE_PKT_CNT", CMIC_TXBUF_RPE_PKT_CNTr }, \ 1292 { 0x0001b010, "CMIC_TXBUF_CMC0_PKT_CNT", CMIC_TXBUF_CMC0_PKT_CNTr }, \ 1293 { 0x0001b014, "CMIC_TXBUF_CMC1_PKT_CNT", CMIC_TXBUF_CMC1_PKT_CNTr }, \ 1294 { 0x0001b018, "CMIC_TXBUF_CMC2_PKT_CNT", CMIC_TXBUF_CMC2_PKT_CNTr }, \ 1295 { 0x0001b01c, "CMIC_TXBUF_DEBUG", CMIC_TXBUF_DEBUGr }, \ 1296 { 0x0001b024, "CMIC_TXBUF_IPINTF_BUF_DEPTH", CMIC_TXBUF_IPINTF_BUF_DEPTHr }, \ 1297 { 0x0001b028, "CMIC_TXBUF_DATABUF_NUM_FREE_ENTRIES", CMIC_TXBUF_DATABUF_NUM_FREE_ENTRIESr }, \ 1298 { 0x0001b02c, "CMIC_TXBUF_IPINTF_INTERFACE_CREDITS", CMIC_TXBUF_IPINTF_INTERFACE_CREDITSr }, \ 1299 { 0x0001b030, "CMIC_TXBUF_DATABUF_MAX_FLIST_ENTRIES", CMIC_TXBUF_DATABUF_MAX_FLIST_ENTRIESr }, \ 1300 { 0x0001b034, "CMIC_TXBUF_CONFIG", CMIC_TXBUF_CONFIGr }, \ 1301 { 0x0001b038, "CMIC_TXBUF_STAT", CMIC_TXBUF_STATr }, \ 1302 { 0x0001b03c, "CMIC_TXBUF_STAT_CLR", CMIC_TXBUF_STAT_CLRr }, \ 1303 { 0x0001b040, "CMIC_TXBUF_ECCERR_CONTROL", CMIC_TXBUF_ECCERR_CONTROLr }, \ 1304 { 0x0001b044, "CMIC_TXBUF_DATABUF_TM_0", CMIC_TXBUF_DATABUF_TM_0r }, \ 1305 { 0x0001b044, "CMIC_TXBUF_TM_CONTROL", CMIC_TXBUF_TM_CONTROLr }, \ 1306 { 0x0001b048, "CMIC_TXBUF_TM_CONTROL_1", CMIC_TXBUF_TM_CONTROL_1r }, \ 1307 { 0x0001b048, "CMIC_TXBUF_DATABUF_TM_1", CMIC_TXBUF_DATABUF_TM_1r }, \ 1308 { 0x0001b04c, "CMIC_TXBUF_MHDRBUF_TM_0", CMIC_TXBUF_MHDRBUF_TM_0r }, \ 1309 { 0x0001c408, "CMIC_PIO_IC_AR_ARB_MI0", CMIC_PIO_IC_AR_ARB_MI0r }, \ 1310 { 0x0001c40c, "CMIC_PIO_IC_AW_ARB_MI0", CMIC_PIO_IC_AW_ARB_MI0r }, \ 1311 { 0x0001c428, "CMIC_PIO_IC_AR_ARB_MI1", CMIC_PIO_IC_AR_ARB_MI1r }, \ 1312 { 0x0001c42c, "CMIC_PIO_IC_AW_ARB_MI1", CMIC_PIO_IC_AW_ARB_MI1r }, \ 1313 { 0x0001c448, "CMIC_PIO_IC_AR_ARB_MI2", CMIC_PIO_IC_AR_ARB_MI2r }, \ 1314 { 0x0001c44c, "CMIC_PIO_IC_AW_ARB_MI2", CMIC_PIO_IC_AW_ARB_MI2r }, \ 1315 { 0x0001c468, "CMIC_PIO_IC_AR_ARB_MI3", CMIC_PIO_IC_AR_ARB_MI3r }, \ 1316 { 0x0001c46c, "CMIC_PIO_IC_AW_ARB_MI3", CMIC_PIO_IC_AW_ARB_MI3r }, \ 1317 { 0x0001c488, "CMIC_PIO_IC_AR_ARB_MI4", CMIC_PIO_IC_AR_ARB_MI4r }, \ 1318 { 0x0001c48c, "CMIC_PIO_IC_AW_ARB_MI4", CMIC_PIO_IC_AW_ARB_MI4r }, \ 1319 { 0x0001c4a8, "CMIC_PIO_IC_AR_ARB_MI5", CMIC_PIO_IC_AR_ARB_MI5r }, \ 1320 { 0x0001c4ac, "CMIC_PIO_IC_AW_ARB_MI5", CMIC_PIO_IC_AW_ARB_MI5r }, \ 1321 { 0x0001c4c8, "CMIC_PIO_IC_AR_ARB_MI6", CMIC_PIO_IC_AR_ARB_MI6r }, \ 1322 { 0x0001c4cc, "CMIC_PIO_IC_AW_ARB_MI6", CMIC_PIO_IC_AW_ARB_MI6r }, \ 1323 { 0x0001c4e8, "CMIC_PIO_IC_AR_ARB_MI7", CMIC_PIO_IC_AR_ARB_MI7r }, \ 1324 { 0x0001c4ec, "CMIC_PIO_IC_AW_ARB_MI7", CMIC_PIO_IC_AW_ARB_MI7r }, \ 1325 { 0x0001cfc0, "CMIC_PIO_IC_CFG_REG_0", CMIC_PIO_IC_CFG_REG_0r }, \ 1326 { 0x0001cfc4, "CMIC_PIO_IC_CFG_REG_1", CMIC_PIO_IC_CFG_REG_1r }, \ 1327 { 0x0001cfcc, "CMIC_PIO_IC_CFG_REG_2", CMIC_PIO_IC_CFG_REG_2r }, \ 1328 { 0x0001cfe0, "CMIC_PIO_IC_PER_REG_0", CMIC_PIO_IC_PER_REG_0r }, \ 1329 { 0x0001cfe4, "CMIC_PIO_IC_PER_REG_1", CMIC_PIO_IC_PER_REG_1r }, \ 1330 { 0x0001cfe8, "CMIC_PIO_IC_PER_REG_2", CMIC_PIO_IC_PER_REG_2r }, \ 1331 { 0x0001cfec, "CMIC_PIO_IC_PER_REG_3", CMIC_PIO_IC_PER_REG_3r }, \ 1332 { 0x0001cff0, "CMIC_PIO_IC_ID_REG_0", CMIC_PIO_IC_ID_REG_0r }, \ 1333 { 0x0001cff4, "CMIC_PIO_IC_ID_REG_1", CMIC_PIO_IC_ID_REG_1r }, \ 1334 { 0x0001cff8, "CMIC_PIO_IC_ID_REG_2", CMIC_PIO_IC_ID_REG_2r }, \ 1335 { 0x0001cffc, "CMIC_PIO_IC_ID_REG_3", CMIC_PIO_IC_ID_REG_3r }, \ 1336 { 0x0001d408, "CMIC_DMA_IC_AR_ARB_MI0", CMIC_DMA_IC_AR_ARB_MI0r }, \ 1337 { 0x0001d40c, "CMIC_DMA_IC_AW_ARB_MI0", CMIC_DMA_IC_AW_ARB_MI0r }, \ 1338 { 0x0001d428, "CMIC_DMA_IC_AR_ARB_MI1", CMIC_DMA_IC_AR_ARB_MI1r }, \ 1339 { 0x0001d42c, "CMIC_DMA_IC_AW_ARB_MI1", CMIC_DMA_IC_AW_ARB_MI1r }, \ 1340 { 0x0001dfc0, "CMIC_DMA_IC_CFG_REG_0", CMIC_DMA_IC_CFG_REG_0r }, \ 1341 { 0x0001dfc4, "CMIC_DMA_IC_CFG_REG_1", CMIC_DMA_IC_CFG_REG_1r }, \ 1342 { 0x0001dfcc, "CMIC_DMA_IC_CFG_REG_2", CMIC_DMA_IC_CFG_REG_2r }, \ 1343 { 0x0001dfe0, "CMIC_DMA_IC_PER_REG_0", CMIC_DMA_IC_PER_REG_0r }, \ 1344 { 0x0001dfe4, "CMIC_DMA_IC_PER_REG_1", CMIC_DMA_IC_PER_REG_1r }, \ 1345 { 0x0001dfe8, "CMIC_DMA_IC_PER_REG_2", CMIC_DMA_IC_PER_REG_2r }, \ 1346 { 0x0001dfec, "CMIC_DMA_IC_PER_REG_3", CMIC_DMA_IC_PER_REG_3r }, \ 1347 { 0x0001dff0, "CMIC_DMA_IC_ID_REG_0", CMIC_DMA_IC_ID_REG_0r }, \ 1348 { 0x0001dff4, "CMIC_DMA_IC_ID_REG_1", CMIC_DMA_IC_ID_REG_1r }, \ 1349 { 0x0001dff8, "CMIC_DMA_IC_ID_REG_2", CMIC_DMA_IC_ID_REG_2r }, \ 1350 { 0x0001dffc, "CMIC_DMA_IC_ID_REG_3", CMIC_DMA_IC_ID_REG_3r }, \ 1351 { 0x00020000, "CMIC_LEDUP0_CTRL", CMIC_LEDUP0_CTRLr }, \ 1352 { 0x00020004, "CMIC_LEDUP0_STATUS", CMIC_LEDUP0_STATUSr }, \ 1353 { 0x00020008, "CMIC_LEDUP0_SCANCHAIN_ASSEMBLY_ST_ADDR", CMIC_LEDUP0_SCANCHAIN_ASSEMBLY_ST_ADDRr }, \ 1354 { 0x00020010, "CMIC_LEDUP0_PORT_ORDER_REMAP_0_3", CMIC_LEDUP0_PORT_ORDER_REMAP_0_3r }, \ 1355 { 0x00020014, "CMIC_LEDUP0_PORT_ORDER_REMAP_4_7", CMIC_LEDUP0_PORT_ORDER_REMAP_4_7r }, \ 1356 { 0x00020018, "CMIC_LEDUP0_PORT_ORDER_REMAP_8_11", CMIC_LEDUP0_PORT_ORDER_REMAP_8_11r }, \ 1357 { 0x0002001c, "CMIC_LEDUP0_PORT_ORDER_REMAP_12_15", CMIC_LEDUP0_PORT_ORDER_REMAP_12_15r }, \ 1358 { 0x00020020, "CMIC_LEDUP0_PORT_ORDER_REMAP_16_19", CMIC_LEDUP0_PORT_ORDER_REMAP_16_19r }, \ 1359 { 0x00020024, "CMIC_LEDUP0_PORT_ORDER_REMAP_20_23", CMIC_LEDUP0_PORT_ORDER_REMAP_20_23r }, \ 1360 { 0x00020028, "CMIC_LEDUP0_PORT_ORDER_REMAP_24_27", CMIC_LEDUP0_PORT_ORDER_REMAP_24_27r }, \ 1361 { 0x0002002c, "CMIC_LEDUP0_PORT_ORDER_REMAP_28_31", CMIC_LEDUP0_PORT_ORDER_REMAP_28_31r }, \ 1362 { 0x00020030, "CMIC_LEDUP0_PORT_ORDER_REMAP_32_35", CMIC_LEDUP0_PORT_ORDER_REMAP_32_35r }, \ 1363 { 0x00020034, "CMIC_LEDUP0_PORT_ORDER_REMAP_36_39", CMIC_LEDUP0_PORT_ORDER_REMAP_36_39r }, \ 1364 { 0x00020038, "CMIC_LEDUP0_PORT_ORDER_REMAP_40_43", CMIC_LEDUP0_PORT_ORDER_REMAP_40_43r }, \ 1365 { 0x0002003c, "CMIC_LEDUP0_PORT_ORDER_REMAP_44_47", CMIC_LEDUP0_PORT_ORDER_REMAP_44_47r }, \ 1366 { 0x00020040, "CMIC_LEDUP0_PORT_ORDER_REMAP_48_51", CMIC_LEDUP0_PORT_ORDER_REMAP_48_51r }, \ 1367 { 0x00020044, "CMIC_LEDUP0_PORT_ORDER_REMAP_52_55", CMIC_LEDUP0_PORT_ORDER_REMAP_52_55r }, \ 1368 { 0x00020048, "CMIC_LEDUP0_PORT_ORDER_REMAP_56_59", CMIC_LEDUP0_PORT_ORDER_REMAP_56_59r }, \ 1369 { 0x0002004c, "CMIC_LEDUP0_PORT_ORDER_REMAP_60_63", CMIC_LEDUP0_PORT_ORDER_REMAP_60_63r }, \ 1370 { 0x00020050, "CMIC_LEDUP0_CLK_PARAMS", CMIC_LEDUP0_CLK_PARAMSr }, \ 1371 { 0x00020054, "CMIC_LEDUP0_SCANOUT_COUNT_UPPER", CMIC_LEDUP0_SCANOUT_COUNT_UPPERr }, \ 1372 { 0x00020058, "CMIC_LEDUP0_TM_CONTROL", CMIC_LEDUP0_TM_CONTROLr }, \ 1373 { 0x0002005c, "CMIC_LEDUP0_CLK_DIV", CMIC_LEDUP0_CLK_DIVr }, \ 1374 { 0x00020060, "CMIC_LEDUP0_ECC_CONFIG", CMIC_LEDUP0_ECC_CONFIGr }, \ 1375 { 0x00020064, "CMIC_LEDUP0_ECC_STATUS", CMIC_LEDUP0_ECC_STATUSr }, \ 1376 { 0x00020068, "CMIC_LEDUP0_ECC_INTR_ENABLE", CMIC_LEDUP0_ECC_INTR_ENABLEr }, \ 1377 { 0x0002006c, "CMIC_LEDUP0_ECC_INTR", CMIC_LEDUP0_ECC_INTRr }, \ 1378 { 0x00020070, "CMIC_LEDUP0_ECC_INTR_CLR", CMIC_LEDUP0_ECC_INTR_CLRr }, \ 1379 { 0x00020400, "CMIC_LEDUP0_DATA_RAM0", CMIC_LEDUP0_DATA_RAM0r }, \ 1380 { 0x00020400, "CMIC_LEDUP0_DATA_RAM", CMIC_LEDUP0_DATA_RAMr }, \ 1381 { 0x00020404, "CMIC_LEDUP0_DATA_RAM1", CMIC_LEDUP0_DATA_RAM1r }, \ 1382 { 0x00020408, "CMIC_LEDUP0_DATA_RAM2", CMIC_LEDUP0_DATA_RAM2r }, \ 1383 { 0x0002040c, "CMIC_LEDUP0_DATA_RAM3", CMIC_LEDUP0_DATA_RAM3r }, \ 1384 { 0x00020410, "CMIC_LEDUP0_DATA_RAM4", CMIC_LEDUP0_DATA_RAM4r }, \ 1385 { 0x00020414, "CMIC_LEDUP0_DATA_RAM5", CMIC_LEDUP0_DATA_RAM5r }, \ 1386 { 0x00020418, "CMIC_LEDUP0_DATA_RAM6", CMIC_LEDUP0_DATA_RAM6r }, \ 1387 { 0x0002041c, "CMIC_LEDUP0_DATA_RAM7", CMIC_LEDUP0_DATA_RAM7r }, \ 1388 { 0x00020420, "CMIC_LEDUP0_DATA_RAM8", CMIC_LEDUP0_DATA_RAM8r }, \ 1389 { 0x00020424, "CMIC_LEDUP0_DATA_RAM9", CMIC_LEDUP0_DATA_RAM9r }, \ 1390 { 0x00020428, "CMIC_LEDUP0_DATA_RAM10", CMIC_LEDUP0_DATA_RAM10r }, \ 1391 { 0x0002042c, "CMIC_LEDUP0_DATA_RAM11", CMIC_LEDUP0_DATA_RAM11r }, \ 1392 { 0x00020430, "CMIC_LEDUP0_DATA_RAM12", CMIC_LEDUP0_DATA_RAM12r }, \ 1393 { 0x00020434, "CMIC_LEDUP0_DATA_RAM13", CMIC_LEDUP0_DATA_RAM13r }, \ 1394 { 0x00020438, "CMIC_LEDUP0_DATA_RAM14", CMIC_LEDUP0_DATA_RAM14r }, \ 1395 { 0x0002043c, "CMIC_LEDUP0_DATA_RAM15", CMIC_LEDUP0_DATA_RAM15r }, \ 1396 { 0x00020440, "CMIC_LEDUP0_DATA_RAM16", CMIC_LEDUP0_DATA_RAM16r }, \ 1397 { 0x00020444, "CMIC_LEDUP0_DATA_RAM17", CMIC_LEDUP0_DATA_RAM17r }, \ 1398 { 0x00020448, "CMIC_LEDUP0_DATA_RAM18", CMIC_LEDUP0_DATA_RAM18r }, \ 1399 { 0x0002044c, "CMIC_LEDUP0_DATA_RAM19", CMIC_LEDUP0_DATA_RAM19r }, \ 1400 { 0x00020450, "CMIC_LEDUP0_DATA_RAM20", CMIC_LEDUP0_DATA_RAM20r }, \ 1401 { 0x00020454, "CMIC_LEDUP0_DATA_RAM21", CMIC_LEDUP0_DATA_RAM21r }, \ 1402 { 0x00020458, "CMIC_LEDUP0_DATA_RAM22", CMIC_LEDUP0_DATA_RAM22r }, \ 1403 { 0x0002045c, "CMIC_LEDUP0_DATA_RAM23", CMIC_LEDUP0_DATA_RAM23r }, \ 1404 { 0x00020460, "CMIC_LEDUP0_DATA_RAM24", CMIC_LEDUP0_DATA_RAM24r }, \ 1405 { 0x00020464, "CMIC_LEDUP0_DATA_RAM25", CMIC_LEDUP0_DATA_RAM25r }, \ 1406 { 0x00020468, "CMIC_LEDUP0_DATA_RAM26", CMIC_LEDUP0_DATA_RAM26r }, \ 1407 { 0x0002046c, "CMIC_LEDUP0_DATA_RAM27", CMIC_LEDUP0_DATA_RAM27r }, \ 1408 { 0x00020470, "CMIC_LEDUP0_DATA_RAM28", CMIC_LEDUP0_DATA_RAM28r }, \ 1409 { 0x00020474, "CMIC_LEDUP0_DATA_RAM29", CMIC_LEDUP0_DATA_RAM29r }, \ 1410 { 0x00020478, "CMIC_LEDUP0_DATA_RAM30", CMIC_LEDUP0_DATA_RAM30r }, \ 1411 { 0x0002047c, "CMIC_LEDUP0_DATA_RAM31", CMIC_LEDUP0_DATA_RAM31r }, \ 1412 { 0x00020480, "CMIC_LEDUP0_DATA_RAM32", CMIC_LEDUP0_DATA_RAM32r }, \ 1413 { 0x00020484, "CMIC_LEDUP0_DATA_RAM33", CMIC_LEDUP0_DATA_RAM33r }, \ 1414 { 0x00020488, "CMIC_LEDUP0_DATA_RAM34", CMIC_LEDUP0_DATA_RAM34r }, \ 1415 { 0x0002048c, "CMIC_LEDUP0_DATA_RAM35", CMIC_LEDUP0_DATA_RAM35r }, \ 1416 { 0x00020490, "CMIC_LEDUP0_DATA_RAM36", CMIC_LEDUP0_DATA_RAM36r }, \ 1417 { 0x00020494, "CMIC_LEDUP0_DATA_RAM37", CMIC_LEDUP0_DATA_RAM37r }, \ 1418 { 0x00020498, "CMIC_LEDUP0_DATA_RAM38", CMIC_LEDUP0_DATA_RAM38r }, \ 1419 { 0x0002049c, "CMIC_LEDUP0_DATA_RAM39", CMIC_LEDUP0_DATA_RAM39r }, \ 1420 { 0x000204a0, "CMIC_LEDUP0_DATA_RAM40", CMIC_LEDUP0_DATA_RAM40r }, \ 1421 { 0x000204a4, "CMIC_LEDUP0_DATA_RAM41", CMIC_LEDUP0_DATA_RAM41r }, \ 1422 { 0x000204a8, "CMIC_LEDUP0_DATA_RAM42", CMIC_LEDUP0_DATA_RAM42r }, \ 1423 { 0x000204ac, "CMIC_LEDUP0_DATA_RAM43", CMIC_LEDUP0_DATA_RAM43r }, \ 1424 { 0x000204b0, "CMIC_LEDUP0_DATA_RAM44", CMIC_LEDUP0_DATA_RAM44r }, \ 1425 { 0x000204b4, "CMIC_LEDUP0_DATA_RAM45", CMIC_LEDUP0_DATA_RAM45r }, \ 1426 { 0x000204b8, "CMIC_LEDUP0_DATA_RAM46", CMIC_LEDUP0_DATA_RAM46r }, \ 1427 { 0x000204bc, "CMIC_LEDUP0_DATA_RAM47", CMIC_LEDUP0_DATA_RAM47r }, \ 1428 { 0x000204c0, "CMIC_LEDUP0_DATA_RAM48", CMIC_LEDUP0_DATA_RAM48r }, \ 1429 { 0x000204c4, "CMIC_LEDUP0_DATA_RAM49", CMIC_LEDUP0_DATA_RAM49r }, \ 1430 { 0x000204c8, "CMIC_LEDUP0_DATA_RAM50", CMIC_LEDUP0_DATA_RAM50r }, \ 1431 { 0x000204cc, "CMIC_LEDUP0_DATA_RAM51", CMIC_LEDUP0_DATA_RAM51r }, \ 1432 { 0x000204d0, "CMIC_LEDUP0_DATA_RAM52", CMIC_LEDUP0_DATA_RAM52r }, \ 1433 { 0x000204d4, "CMIC_LEDUP0_DATA_RAM53", CMIC_LEDUP0_DATA_RAM53r }, \ 1434 { 0x000204d8, "CMIC_LEDUP0_DATA_RAM54", CMIC_LEDUP0_DATA_RAM54r }, \ 1435 { 0x000204dc, "CMIC_LEDUP0_DATA_RAM55", CMIC_LEDUP0_DATA_RAM55r }, \ 1436 { 0x000204e0, "CMIC_LEDUP0_DATA_RAM56", CMIC_LEDUP0_DATA_RAM56r }, \ 1437 { 0x000204e4, "CMIC_LEDUP0_DATA_RAM57", CMIC_LEDUP0_DATA_RAM57r }, \ 1438 { 0x000204e8, "CMIC_LEDUP0_DATA_RAM58", CMIC_LEDUP0_DATA_RAM58r }, \ 1439 { 0x000204ec, "CMIC_LEDUP0_DATA_RAM59", CMIC_LEDUP0_DATA_RAM59r }, \ 1440 { 0x000204f0, "CMIC_LEDUP0_DATA_RAM60", CMIC_LEDUP0_DATA_RAM60r }, \ 1441 { 0x000204f4, "CMIC_LEDUP0_DATA_RAM61", CMIC_LEDUP0_DATA_RAM61r }, \ 1442 { 0x000204f8, "CMIC_LEDUP0_DATA_RAM62", CMIC_LEDUP0_DATA_RAM62r }, \ 1443 { 0x000204fc, "CMIC_LEDUP0_DATA_RAM63", CMIC_LEDUP0_DATA_RAM63r }, \ 1444 { 0x00020500, "CMIC_LEDUP0_DATA_RAM64", CMIC_LEDUP0_DATA_RAM64r }, \ 1445 { 0x00020504, "CMIC_LEDUP0_DATA_RAM65", CMIC_LEDUP0_DATA_RAM65r }, \ 1446 { 0x00020508, "CMIC_LEDUP0_DATA_RAM66", CMIC_LEDUP0_DATA_RAM66r }, \ 1447 { 0x0002050c, "CMIC_LEDUP0_DATA_RAM67", CMIC_LEDUP0_DATA_RAM67r }, \ 1448 { 0x00020510, "CMIC_LEDUP0_DATA_RAM68", CMIC_LEDUP0_DATA_RAM68r }, \ 1449 { 0x00020514, "CMIC_LEDUP0_DATA_RAM69", CMIC_LEDUP0_DATA_RAM69r }, \ 1450 { 0x00020518, "CMIC_LEDUP0_DATA_RAM70", CMIC_LEDUP0_DATA_RAM70r }, \ 1451 { 0x0002051c, "CMIC_LEDUP0_DATA_RAM71", CMIC_LEDUP0_DATA_RAM71r }, \ 1452 { 0x00020520, "CMIC_LEDUP0_DATA_RAM72", CMIC_LEDUP0_DATA_RAM72r }, \ 1453 { 0x00020524, "CMIC_LEDUP0_DATA_RAM73", CMIC_LEDUP0_DATA_RAM73r }, \ 1454 { 0x00020528, "CMIC_LEDUP0_DATA_RAM74", CMIC_LEDUP0_DATA_RAM74r }, \ 1455 { 0x0002052c, "CMIC_LEDUP0_DATA_RAM75", CMIC_LEDUP0_DATA_RAM75r }, \ 1456 { 0x00020530, "CMIC_LEDUP0_DATA_RAM76", CMIC_LEDUP0_DATA_RAM76r }, \ 1457 { 0x00020534, "CMIC_LEDUP0_DATA_RAM77", CMIC_LEDUP0_DATA_RAM77r }, \ 1458 { 0x00020538, "CMIC_LEDUP0_DATA_RAM78", CMIC_LEDUP0_DATA_RAM78r }, \ 1459 { 0x0002053c, "CMIC_LEDUP0_DATA_RAM79", CMIC_LEDUP0_DATA_RAM79r }, \ 1460 { 0x00020540, "CMIC_LEDUP0_DATA_RAM80", CMIC_LEDUP0_DATA_RAM80r }, \ 1461 { 0x00020544, "CMIC_LEDUP0_DATA_RAM81", CMIC_LEDUP0_DATA_RAM81r }, \ 1462 { 0x00020548, "CMIC_LEDUP0_DATA_RAM82", CMIC_LEDUP0_DATA_RAM82r }, \ 1463 { 0x0002054c, "CMIC_LEDUP0_DATA_RAM83", CMIC_LEDUP0_DATA_RAM83r }, \ 1464 { 0x00020550, "CMIC_LEDUP0_DATA_RAM84", CMIC_LEDUP0_DATA_RAM84r }, \ 1465 { 0x00020554, "CMIC_LEDUP0_DATA_RAM85", CMIC_LEDUP0_DATA_RAM85r }, \ 1466 { 0x00020558, "CMIC_LEDUP0_DATA_RAM86", CMIC_LEDUP0_DATA_RAM86r }, \ 1467 { 0x0002055c, "CMIC_LEDUP0_DATA_RAM87", CMIC_LEDUP0_DATA_RAM87r }, \ 1468 { 0x00020560, "CMIC_LEDUP0_DATA_RAM88", CMIC_LEDUP0_DATA_RAM88r }, \ 1469 { 0x00020564, "CMIC_LEDUP0_DATA_RAM89", CMIC_LEDUP0_DATA_RAM89r }, \ 1470 { 0x00020568, "CMIC_LEDUP0_DATA_RAM90", CMIC_LEDUP0_DATA_RAM90r }, \ 1471 { 0x0002056c, "CMIC_LEDUP0_DATA_RAM91", CMIC_LEDUP0_DATA_RAM91r }, \ 1472 { 0x00020570, "CMIC_LEDUP0_DATA_RAM92", CMIC_LEDUP0_DATA_RAM92r }, \ 1473 { 0x00020574, "CMIC_LEDUP0_DATA_RAM93", CMIC_LEDUP0_DATA_RAM93r }, \ 1474 { 0x00020578, "CMIC_LEDUP0_DATA_RAM94", CMIC_LEDUP0_DATA_RAM94r }, \ 1475 { 0x0002057c, "CMIC_LEDUP0_DATA_RAM95", CMIC_LEDUP0_DATA_RAM95r }, \ 1476 { 0x00020580, "CMIC_LEDUP0_DATA_RAM96", CMIC_LEDUP0_DATA_RAM96r }, \ 1477 { 0x00020584, "CMIC_LEDUP0_DATA_RAM97", CMIC_LEDUP0_DATA_RAM97r }, \ 1478 { 0x00020588, "CMIC_LEDUP0_DATA_RAM98", CMIC_LEDUP0_DATA_RAM98r }, \ 1479 { 0x0002058c, "CMIC_LEDUP0_DATA_RAM99", CMIC_LEDUP0_DATA_RAM99r }, \ 1480 { 0x00020590, "CMIC_LEDUP0_DATA_RAM100", CMIC_LEDUP0_DATA_RAM100r }, \ 1481 { 0x00020594, "CMIC_LEDUP0_DATA_RAM101", CMIC_LEDUP0_DATA_RAM101r }, \ 1482 { 0x00020598, "CMIC_LEDUP0_DATA_RAM102", CMIC_LEDUP0_DATA_RAM102r }, \ 1483 { 0x0002059c, "CMIC_LEDUP0_DATA_RAM103", CMIC_LEDUP0_DATA_RAM103r }, \ 1484 { 0x000205a0, "CMIC_LEDUP0_DATA_RAM104", CMIC_LEDUP0_DATA_RAM104r }, \ 1485 { 0x000205a4, "CMIC_LEDUP0_DATA_RAM105", CMIC_LEDUP0_DATA_RAM105r }, \ 1486 { 0x000205a8, "CMIC_LEDUP0_DATA_RAM106", CMIC_LEDUP0_DATA_RAM106r }, \ 1487 { 0x000205ac, "CMIC_LEDUP0_DATA_RAM107", CMIC_LEDUP0_DATA_RAM107r }, \ 1488 { 0x000205b0, "CMIC_LEDUP0_DATA_RAM108", CMIC_LEDUP0_DATA_RAM108r }, \ 1489 { 0x000205b4, "CMIC_LEDUP0_DATA_RAM109", CMIC_LEDUP0_DATA_RAM109r }, \ 1490 { 0x000205b8, "CMIC_LEDUP0_DATA_RAM110", CMIC_LEDUP0_DATA_RAM110r }, \ 1491 { 0x000205bc, "CMIC_LEDUP0_DATA_RAM111", CMIC_LEDUP0_DATA_RAM111r }, \ 1492 { 0x000205c0, "CMIC_LEDUP0_DATA_RAM112", CMIC_LEDUP0_DATA_RAM112r }, \ 1493 { 0x000205c4, "CMIC_LEDUP0_DATA_RAM113", CMIC_LEDUP0_DATA_RAM113r }, \ 1494 { 0x000205c8, "CMIC_LEDUP0_DATA_RAM114", CMIC_LEDUP0_DATA_RAM114r }, \ 1495 { 0x000205cc, "CMIC_LEDUP0_DATA_RAM115", CMIC_LEDUP0_DATA_RAM115r }, \ 1496 { 0x000205d0, "CMIC_LEDUP0_DATA_RAM116", CMIC_LEDUP0_DATA_RAM116r }, \ 1497 { 0x000205d4, "CMIC_LEDUP0_DATA_RAM117", CMIC_LEDUP0_DATA_RAM117r }, \ 1498 { 0x000205d8, "CMIC_LEDUP0_DATA_RAM118", CMIC_LEDUP0_DATA_RAM118r }, \ 1499 { 0x000205dc, "CMIC_LEDUP0_DATA_RAM119", CMIC_LEDUP0_DATA_RAM119r }, \ 1500 { 0x000205e0, "CMIC_LEDUP0_DATA_RAM120", CMIC_LEDUP0_DATA_RAM120r }, \ 1501 { 0x000205e4, "CMIC_LEDUP0_DATA_RAM121", CMIC_LEDUP0_DATA_RAM121r }, \ 1502 { 0x000205e8, "CMIC_LEDUP0_DATA_RAM122", CMIC_LEDUP0_DATA_RAM122r }, \ 1503 { 0x000205ec, "CMIC_LEDUP0_DATA_RAM123", CMIC_LEDUP0_DATA_RAM123r }, \ 1504 { 0x000205f0, "CMIC_LEDUP0_DATA_RAM124", CMIC_LEDUP0_DATA_RAM124r }, \ 1505 { 0x000205f4, "CMIC_LEDUP0_DATA_RAM125", CMIC_LEDUP0_DATA_RAM125r }, \ 1506 { 0x000205f8, "CMIC_LEDUP0_DATA_RAM126", CMIC_LEDUP0_DATA_RAM126r }, \ 1507 { 0x000205fc, "CMIC_LEDUP0_DATA_RAM127", CMIC_LEDUP0_DATA_RAM127r }, \ 1508 { 0x00020600, "CMIC_LEDUP0_DATA_RAM128", CMIC_LEDUP0_DATA_RAM128r }, \ 1509 { 0x00020604, "CMIC_LEDUP0_DATA_RAM129", CMIC_LEDUP0_DATA_RAM129r }, \ 1510 { 0x00020608, "CMIC_LEDUP0_DATA_RAM130", CMIC_LEDUP0_DATA_RAM130r }, \ 1511 { 0x0002060c, "CMIC_LEDUP0_DATA_RAM131", CMIC_LEDUP0_DATA_RAM131r }, \ 1512 { 0x00020610, "CMIC_LEDUP0_DATA_RAM132", CMIC_LEDUP0_DATA_RAM132r }, \ 1513 { 0x00020614, "CMIC_LEDUP0_DATA_RAM133", CMIC_LEDUP0_DATA_RAM133r }, \ 1514 { 0x00020618, "CMIC_LEDUP0_DATA_RAM134", CMIC_LEDUP0_DATA_RAM134r }, \ 1515 { 0x0002061c, "CMIC_LEDUP0_DATA_RAM135", CMIC_LEDUP0_DATA_RAM135r }, \ 1516 { 0x00020620, "CMIC_LEDUP0_DATA_RAM136", CMIC_LEDUP0_DATA_RAM136r }, \ 1517 { 0x00020624, "CMIC_LEDUP0_DATA_RAM137", CMIC_LEDUP0_DATA_RAM137r }, \ 1518 { 0x00020628, "CMIC_LEDUP0_DATA_RAM138", CMIC_LEDUP0_DATA_RAM138r }, \ 1519 { 0x0002062c, "CMIC_LEDUP0_DATA_RAM139", CMIC_LEDUP0_DATA_RAM139r }, \ 1520 { 0x00020630, "CMIC_LEDUP0_DATA_RAM140", CMIC_LEDUP0_DATA_RAM140r }, \ 1521 { 0x00020634, "CMIC_LEDUP0_DATA_RAM141", CMIC_LEDUP0_DATA_RAM141r }, \ 1522 { 0x00020638, "CMIC_LEDUP0_DATA_RAM142", CMIC_LEDUP0_DATA_RAM142r }, \ 1523 { 0x0002063c, "CMIC_LEDUP0_DATA_RAM143", CMIC_LEDUP0_DATA_RAM143r }, \ 1524 { 0x00020640, "CMIC_LEDUP0_DATA_RAM144", CMIC_LEDUP0_DATA_RAM144r }, \ 1525 { 0x00020644, "CMIC_LEDUP0_DATA_RAM145", CMIC_LEDUP0_DATA_RAM145r }, \ 1526 { 0x00020648, "CMIC_LEDUP0_DATA_RAM146", CMIC_LEDUP0_DATA_RAM146r }, \ 1527 { 0x0002064c, "CMIC_LEDUP0_DATA_RAM147", CMIC_LEDUP0_DATA_RAM147r }, \ 1528 { 0x00020650, "CMIC_LEDUP0_DATA_RAM148", CMIC_LEDUP0_DATA_RAM148r }, \ 1529 { 0x00020654, "CMIC_LEDUP0_DATA_RAM149", CMIC_LEDUP0_DATA_RAM149r }, \ 1530 { 0x00020658, "CMIC_LEDUP0_DATA_RAM150", CMIC_LEDUP0_DATA_RAM150r }, \ 1531 { 0x0002065c, "CMIC_LEDUP0_DATA_RAM151", CMIC_LEDUP0_DATA_RAM151r }, \ 1532 { 0x00020660, "CMIC_LEDUP0_DATA_RAM152", CMIC_LEDUP0_DATA_RAM152r }, \ 1533 { 0x00020664, "CMIC_LEDUP0_DATA_RAM153", CMIC_LEDUP0_DATA_RAM153r }, \ 1534 { 0x00020668, "CMIC_LEDUP0_DATA_RAM154", CMIC_LEDUP0_DATA_RAM154r }, \ 1535 { 0x0002066c, "CMIC_LEDUP0_DATA_RAM155", CMIC_LEDUP0_DATA_RAM155r }, \ 1536 { 0x00020670, "CMIC_LEDUP0_DATA_RAM156", CMIC_LEDUP0_DATA_RAM156r }, \ 1537 { 0x00020674, "CMIC_LEDUP0_DATA_RAM157", CMIC_LEDUP0_DATA_RAM157r }, \ 1538 { 0x00020678, "CMIC_LEDUP0_DATA_RAM158", CMIC_LEDUP0_DATA_RAM158r }, \ 1539 { 0x0002067c, "CMIC_LEDUP0_DATA_RAM159", CMIC_LEDUP0_DATA_RAM159r }, \ 1540 { 0x00020680, "CMIC_LEDUP0_DATA_RAM160", CMIC_LEDUP0_DATA_RAM160r }, \ 1541 { 0x00020684, "CMIC_LEDUP0_DATA_RAM161", CMIC_LEDUP0_DATA_RAM161r }, \ 1542 { 0x00020688, "CMIC_LEDUP0_DATA_RAM162", CMIC_LEDUP0_DATA_RAM162r }, \ 1543 { 0x0002068c, "CMIC_LEDUP0_DATA_RAM163", CMIC_LEDUP0_DATA_RAM163r }, \ 1544 { 0x00020690, "CMIC_LEDUP0_DATA_RAM164", CMIC_LEDUP0_DATA_RAM164r }, \ 1545 { 0x00020694, "CMIC_LEDUP0_DATA_RAM165", CMIC_LEDUP0_DATA_RAM165r }, \ 1546 { 0x00020698, "CMIC_LEDUP0_DATA_RAM166", CMIC_LEDUP0_DATA_RAM166r }, \ 1547 { 0x0002069c, "CMIC_LEDUP0_DATA_RAM167", CMIC_LEDUP0_DATA_RAM167r }, \ 1548 { 0x000206a0, "CMIC_LEDUP0_DATA_RAM168", CMIC_LEDUP0_DATA_RAM168r }, \ 1549 { 0x000206a4, "CMIC_LEDUP0_DATA_RAM169", CMIC_LEDUP0_DATA_RAM169r }, \ 1550 { 0x000206a8, "CMIC_LEDUP0_DATA_RAM170", CMIC_LEDUP0_DATA_RAM170r }, \ 1551 { 0x000206ac, "CMIC_LEDUP0_DATA_RAM171", CMIC_LEDUP0_DATA_RAM171r }, \ 1552 { 0x000206b0, "CMIC_LEDUP0_DATA_RAM172", CMIC_LEDUP0_DATA_RAM172r }, \ 1553 { 0x000206b4, "CMIC_LEDUP0_DATA_RAM173", CMIC_LEDUP0_DATA_RAM173r }, \ 1554 { 0x000206b8, "CMIC_LEDUP0_DATA_RAM174", CMIC_LEDUP0_DATA_RAM174r }, \ 1555 { 0x000206bc, "CMIC_LEDUP0_DATA_RAM175", CMIC_LEDUP0_DATA_RAM175r }, \ 1556 { 0x000206c0, "CMIC_LEDUP0_DATA_RAM176", CMIC_LEDUP0_DATA_RAM176r }, \ 1557 { 0x000206c4, "CMIC_LEDUP0_DATA_RAM177", CMIC_LEDUP0_DATA_RAM177r }, \ 1558 { 0x000206c8, "CMIC_LEDUP0_DATA_RAM178", CMIC_LEDUP0_DATA_RAM178r }, \ 1559 { 0x000206cc, "CMIC_LEDUP0_DATA_RAM179", CMIC_LEDUP0_DATA_RAM179r }, \ 1560 { 0x000206d0, "CMIC_LEDUP0_DATA_RAM180", CMIC_LEDUP0_DATA_RAM180r }, \ 1561 { 0x000206d4, "CMIC_LEDUP0_DATA_RAM181", CMIC_LEDUP0_DATA_RAM181r }, \ 1562 { 0x000206d8, "CMIC_LEDUP0_DATA_RAM182", CMIC_LEDUP0_DATA_RAM182r }, \ 1563 { 0x000206dc, "CMIC_LEDUP0_DATA_RAM183", CMIC_LEDUP0_DATA_RAM183r }, \ 1564 { 0x000206e0, "CMIC_LEDUP0_DATA_RAM184", CMIC_LEDUP0_DATA_RAM184r }, \ 1565 { 0x000206e4, "CMIC_LEDUP0_DATA_RAM185", CMIC_LEDUP0_DATA_RAM185r }, \ 1566 { 0x000206e8, "CMIC_LEDUP0_DATA_RAM186", CMIC_LEDUP0_DATA_RAM186r }, \ 1567 { 0x000206ec, "CMIC_LEDUP0_DATA_RAM187", CMIC_LEDUP0_DATA_RAM187r }, \ 1568 { 0x000206f0, "CMIC_LEDUP0_DATA_RAM188", CMIC_LEDUP0_DATA_RAM188r }, \ 1569 { 0x000206f4, "CMIC_LEDUP0_DATA_RAM189", CMIC_LEDUP0_DATA_RAM189r }, \ 1570 { 0x000206f8, "CMIC_LEDUP0_DATA_RAM190", CMIC_LEDUP0_DATA_RAM190r }, \ 1571 { 0x000206fc, "CMIC_LEDUP0_DATA_RAM191", CMIC_LEDUP0_DATA_RAM191r }, \ 1572 { 0x00020700, "CMIC_LEDUP0_DATA_RAM192", CMIC_LEDUP0_DATA_RAM192r }, \ 1573 { 0x00020704, "CMIC_LEDUP0_DATA_RAM193", CMIC_LEDUP0_DATA_RAM193r }, \ 1574 { 0x00020708, "CMIC_LEDUP0_DATA_RAM194", CMIC_LEDUP0_DATA_RAM194r }, \ 1575 { 0x0002070c, "CMIC_LEDUP0_DATA_RAM195", CMIC_LEDUP0_DATA_RAM195r }, \ 1576 { 0x00020710, "CMIC_LEDUP0_DATA_RAM196", CMIC_LEDUP0_DATA_RAM196r }, \ 1577 { 0x00020714, "CMIC_LEDUP0_DATA_RAM197", CMIC_LEDUP0_DATA_RAM197r }, \ 1578 { 0x00020718, "CMIC_LEDUP0_DATA_RAM198", CMIC_LEDUP0_DATA_RAM198r }, \ 1579 { 0x0002071c, "CMIC_LEDUP0_DATA_RAM199", CMIC_LEDUP0_DATA_RAM199r }, \ 1580 { 0x00020720, "CMIC_LEDUP0_DATA_RAM200", CMIC_LEDUP0_DATA_RAM200r }, \ 1581 { 0x00020724, "CMIC_LEDUP0_DATA_RAM201", CMIC_LEDUP0_DATA_RAM201r }, \ 1582 { 0x00020728, "CMIC_LEDUP0_DATA_RAM202", CMIC_LEDUP0_DATA_RAM202r }, \ 1583 { 0x0002072c, "CMIC_LEDUP0_DATA_RAM203", CMIC_LEDUP0_DATA_RAM203r }, \ 1584 { 0x00020730, "CMIC_LEDUP0_DATA_RAM204", CMIC_LEDUP0_DATA_RAM204r }, \ 1585 { 0x00020734, "CMIC_LEDUP0_DATA_RAM205", CMIC_LEDUP0_DATA_RAM205r }, \ 1586 { 0x00020738, "CMIC_LEDUP0_DATA_RAM206", CMIC_LEDUP0_DATA_RAM206r }, \ 1587 { 0x0002073c, "CMIC_LEDUP0_DATA_RAM207", CMIC_LEDUP0_DATA_RAM207r }, \ 1588 { 0x00020740, "CMIC_LEDUP0_DATA_RAM208", CMIC_LEDUP0_DATA_RAM208r }, \ 1589 { 0x00020744, "CMIC_LEDUP0_DATA_RAM209", CMIC_LEDUP0_DATA_RAM209r }, \ 1590 { 0x00020748, "CMIC_LEDUP0_DATA_RAM210", CMIC_LEDUP0_DATA_RAM210r }, \ 1591 { 0x0002074c, "CMIC_LEDUP0_DATA_RAM211", CMIC_LEDUP0_DATA_RAM211r }, \ 1592 { 0x00020750, "CMIC_LEDUP0_DATA_RAM212", CMIC_LEDUP0_DATA_RAM212r }, \ 1593 { 0x00020754, "CMIC_LEDUP0_DATA_RAM213", CMIC_LEDUP0_DATA_RAM213r }, \ 1594 { 0x00020758, "CMIC_LEDUP0_DATA_RAM214", CMIC_LEDUP0_DATA_RAM214r }, \ 1595 { 0x0002075c, "CMIC_LEDUP0_DATA_RAM215", CMIC_LEDUP0_DATA_RAM215r }, \ 1596 { 0x00020760, "CMIC_LEDUP0_DATA_RAM216", CMIC_LEDUP0_DATA_RAM216r }, \ 1597 { 0x00020764, "CMIC_LEDUP0_DATA_RAM217", CMIC_LEDUP0_DATA_RAM217r }, \ 1598 { 0x00020768, "CMIC_LEDUP0_DATA_RAM218", CMIC_LEDUP0_DATA_RAM218r }, \ 1599 { 0x0002076c, "CMIC_LEDUP0_DATA_RAM219", CMIC_LEDUP0_DATA_RAM219r }, \ 1600 { 0x00020770, "CMIC_LEDUP0_DATA_RAM220", CMIC_LEDUP0_DATA_RAM220r }, \ 1601 { 0x00020774, "CMIC_LEDUP0_DATA_RAM221", CMIC_LEDUP0_DATA_RAM221r }, \ 1602 { 0x00020778, "CMIC_LEDUP0_DATA_RAM222", CMIC_LEDUP0_DATA_RAM222r }, \ 1603 { 0x0002077c, "CMIC_LEDUP0_DATA_RAM223", CMIC_LEDUP0_DATA_RAM223r }, \ 1604 { 0x00020780, "CMIC_LEDUP0_DATA_RAM224", CMIC_LEDUP0_DATA_RAM224r }, \ 1605 { 0x00020784, "CMIC_LEDUP0_DATA_RAM225", CMIC_LEDUP0_DATA_RAM225r }, \ 1606 { 0x00020788, "CMIC_LEDUP0_DATA_RAM226", CMIC_LEDUP0_DATA_RAM226r }, \ 1607 { 0x0002078c, "CMIC_LEDUP0_DATA_RAM227", CMIC_LEDUP0_DATA_RAM227r }, \ 1608 { 0x00020790, "CMIC_LEDUP0_DATA_RAM228", CMIC_LEDUP0_DATA_RAM228r }, \ 1609 { 0x00020794, "CMIC_LEDUP0_DATA_RAM229", CMIC_LEDUP0_DATA_RAM229r }, \ 1610 { 0x00020798, "CMIC_LEDUP0_DATA_RAM230", CMIC_LEDUP0_DATA_RAM230r }, \ 1611 { 0x0002079c, "CMIC_LEDUP0_DATA_RAM231", CMIC_LEDUP0_DATA_RAM231r }, \ 1612 { 0x000207a0, "CMIC_LEDUP0_DATA_RAM232", CMIC_LEDUP0_DATA_RAM232r }, \ 1613 { 0x000207a4, "CMIC_LEDUP0_DATA_RAM233", CMIC_LEDUP0_DATA_RAM233r }, \ 1614 { 0x000207a8, "CMIC_LEDUP0_DATA_RAM234", CMIC_LEDUP0_DATA_RAM234r }, \ 1615 { 0x000207ac, "CMIC_LEDUP0_DATA_RAM235", CMIC_LEDUP0_DATA_RAM235r }, \ 1616 { 0x000207b0, "CMIC_LEDUP0_DATA_RAM236", CMIC_LEDUP0_DATA_RAM236r }, \ 1617 { 0x000207b4, "CMIC_LEDUP0_DATA_RAM237", CMIC_LEDUP0_DATA_RAM237r }, \ 1618 { 0x000207b8, "CMIC_LEDUP0_DATA_RAM238", CMIC_LEDUP0_DATA_RAM238r }, \ 1619 { 0x000207bc, "CMIC_LEDUP0_DATA_RAM239", CMIC_LEDUP0_DATA_RAM239r }, \ 1620 { 0x000207c0, "CMIC_LEDUP0_DATA_RAM240", CMIC_LEDUP0_DATA_RAM240r }, \ 1621 { 0x000207c4, "CMIC_LEDUP0_DATA_RAM241", CMIC_LEDUP0_DATA_RAM241r }, \ 1622 { 0x000207c8, "CMIC_LEDUP0_DATA_RAM242", CMIC_LEDUP0_DATA_RAM242r }, \ 1623 { 0x000207cc, "CMIC_LEDUP0_DATA_RAM243", CMIC_LEDUP0_DATA_RAM243r }, \ 1624 { 0x000207d0, "CMIC_LEDUP0_DATA_RAM244", CMIC_LEDUP0_DATA_RAM244r }, \ 1625 { 0x000207d4, "CMIC_LEDUP0_DATA_RAM245", CMIC_LEDUP0_DATA_RAM245r }, \ 1626 { 0x000207d8, "CMIC_LEDUP0_DATA_RAM246", CMIC_LEDUP0_DATA_RAM246r }, \ 1627 { 0x000207dc, "CMIC_LEDUP0_DATA_RAM247", CMIC_LEDUP0_DATA_RAM247r }, \ 1628 { 0x000207e0, "CMIC_LEDUP0_DATA_RAM248", CMIC_LEDUP0_DATA_RAM248r }, \ 1629 { 0x000207e4, "CMIC_LEDUP0_DATA_RAM249", CMIC_LEDUP0_DATA_RAM249r }, \ 1630 { 0x000207e8, "CMIC_LEDUP0_DATA_RAM250", CMIC_LEDUP0_DATA_RAM250r }, \ 1631 { 0x000207ec, "CMIC_LEDUP0_DATA_RAM251", CMIC_LEDUP0_DATA_RAM251r }, \ 1632 { 0x000207f0, "CMIC_LEDUP0_DATA_RAM252", CMIC_LEDUP0_DATA_RAM252r }, \ 1633 { 0x000207f4, "CMIC_LEDUP0_DATA_RAM253", CMIC_LEDUP0_DATA_RAM253r }, \ 1634 { 0x000207f8, "CMIC_LEDUP0_DATA_RAM254", CMIC_LEDUP0_DATA_RAM254r }, \ 1635 { 0x000207fc, "CMIC_LEDUP0_DATA_RAM255", CMIC_LEDUP0_DATA_RAM255r }, \ 1636 { 0x00020800, "CMIC_LEDUP0_PROGRAM_RAM0", CMIC_LEDUP0_PROGRAM_RAM0r }, \ 1637 { 0x00020800, "CMIC_LEDUP0_PROGRAM_RAM", CMIC_LEDUP0_PROGRAM_RAMr }, \ 1638 { 0x00020804, "CMIC_LEDUP0_PROGRAM_RAM1", CMIC_LEDUP0_PROGRAM_RAM1r }, \ 1639 { 0x00020808, "CMIC_LEDUP0_PROGRAM_RAM2", CMIC_LEDUP0_PROGRAM_RAM2r }, \ 1640 { 0x0002080c, "CMIC_LEDUP0_PROGRAM_RAM3", CMIC_LEDUP0_PROGRAM_RAM3r }, \ 1641 { 0x00020810, "CMIC_LEDUP0_PROGRAM_RAM4", CMIC_LEDUP0_PROGRAM_RAM4r }, \ 1642 { 0x00020814, "CMIC_LEDUP0_PROGRAM_RAM5", CMIC_LEDUP0_PROGRAM_RAM5r }, \ 1643 { 0x00020818, "CMIC_LEDUP0_PROGRAM_RAM6", CMIC_LEDUP0_PROGRAM_RAM6r }, \ 1644 { 0x0002081c, "CMIC_LEDUP0_PROGRAM_RAM7", CMIC_LEDUP0_PROGRAM_RAM7r }, \ 1645 { 0x00020820, "CMIC_LEDUP0_PROGRAM_RAM8", CMIC_LEDUP0_PROGRAM_RAM8r }, \ 1646 { 0x00020824, "CMIC_LEDUP0_PROGRAM_RAM9", CMIC_LEDUP0_PROGRAM_RAM9r }, \ 1647 { 0x00020828, "CMIC_LEDUP0_PROGRAM_RAM10", CMIC_LEDUP0_PROGRAM_RAM10r }, \ 1648 { 0x0002082c, "CMIC_LEDUP0_PROGRAM_RAM11", CMIC_LEDUP0_PROGRAM_RAM11r }, \ 1649 { 0x00020830, "CMIC_LEDUP0_PROGRAM_RAM12", CMIC_LEDUP0_PROGRAM_RAM12r }, \ 1650 { 0x00020834, "CMIC_LEDUP0_PROGRAM_RAM13", CMIC_LEDUP0_PROGRAM_RAM13r }, \ 1651 { 0x00020838, "CMIC_LEDUP0_PROGRAM_RAM14", CMIC_LEDUP0_PROGRAM_RAM14r }, \ 1652 { 0x0002083c, "CMIC_LEDUP0_PROGRAM_RAM15", CMIC_LEDUP0_PROGRAM_RAM15r }, \ 1653 { 0x00020840, "CMIC_LEDUP0_PROGRAM_RAM16", CMIC_LEDUP0_PROGRAM_RAM16r }, \ 1654 { 0x00020844, "CMIC_LEDUP0_PROGRAM_RAM17", CMIC_LEDUP0_PROGRAM_RAM17r }, \ 1655 { 0x00020848, "CMIC_LEDUP0_PROGRAM_RAM18", CMIC_LEDUP0_PROGRAM_RAM18r }, \ 1656 { 0x0002084c, "CMIC_LEDUP0_PROGRAM_RAM19", CMIC_LEDUP0_PROGRAM_RAM19r }, \ 1657 { 0x00020850, "CMIC_LEDUP0_PROGRAM_RAM20", CMIC_LEDUP0_PROGRAM_RAM20r }, \ 1658 { 0x00020854, "CMIC_LEDUP0_PROGRAM_RAM21", CMIC_LEDUP0_PROGRAM_RAM21r }, \ 1659 { 0x00020858, "CMIC_LEDUP0_PROGRAM_RAM22", CMIC_LEDUP0_PROGRAM_RAM22r }, \ 1660 { 0x0002085c, "CMIC_LEDUP0_PROGRAM_RAM23", CMIC_LEDUP0_PROGRAM_RAM23r }, \ 1661 { 0x00020860, "CMIC_LEDUP0_PROGRAM_RAM24", CMIC_LEDUP0_PROGRAM_RAM24r }, \ 1662 { 0x00020864, "CMIC_LEDUP0_PROGRAM_RAM25", CMIC_LEDUP0_PROGRAM_RAM25r }, \ 1663 { 0x00020868, "CMIC_LEDUP0_PROGRAM_RAM26", CMIC_LEDUP0_PROGRAM_RAM26r }, \ 1664 { 0x0002086c, "CMIC_LEDUP0_PROGRAM_RAM27", CMIC_LEDUP0_PROGRAM_RAM27r }, \ 1665 { 0x00020870, "CMIC_LEDUP0_PROGRAM_RAM28", CMIC_LEDUP0_PROGRAM_RAM28r }, \ 1666 { 0x00020874, "CMIC_LEDUP0_PROGRAM_RAM29", CMIC_LEDUP0_PROGRAM_RAM29r }, \ 1667 { 0x00020878, "CMIC_LEDUP0_PROGRAM_RAM30", CMIC_LEDUP0_PROGRAM_RAM30r }, \ 1668 { 0x0002087c, "CMIC_LEDUP0_PROGRAM_RAM31", CMIC_LEDUP0_PROGRAM_RAM31r }, \ 1669 { 0x00020880, "CMIC_LEDUP0_PROGRAM_RAM32", CMIC_LEDUP0_PROGRAM_RAM32r }, \ 1670 { 0x00020884, "CMIC_LEDUP0_PROGRAM_RAM33", CMIC_LEDUP0_PROGRAM_RAM33r }, \ 1671 { 0x00020888, "CMIC_LEDUP0_PROGRAM_RAM34", CMIC_LEDUP0_PROGRAM_RAM34r }, \ 1672 { 0x0002088c, "CMIC_LEDUP0_PROGRAM_RAM35", CMIC_LEDUP0_PROGRAM_RAM35r }, \ 1673 { 0x00020890, "CMIC_LEDUP0_PROGRAM_RAM36", CMIC_LEDUP0_PROGRAM_RAM36r }, \ 1674 { 0x00020894, "CMIC_LEDUP0_PROGRAM_RAM37", CMIC_LEDUP0_PROGRAM_RAM37r }, \ 1675 { 0x00020898, "CMIC_LEDUP0_PROGRAM_RAM38", CMIC_LEDUP0_PROGRAM_RAM38r }, \ 1676 { 0x0002089c, "CMIC_LEDUP0_PROGRAM_RAM39", CMIC_LEDUP0_PROGRAM_RAM39r }, \ 1677 { 0x000208a0, "CMIC_LEDUP0_PROGRAM_RAM40", CMIC_LEDUP0_PROGRAM_RAM40r }, \ 1678 { 0x000208a4, "CMIC_LEDUP0_PROGRAM_RAM41", CMIC_LEDUP0_PROGRAM_RAM41r }, \ 1679 { 0x000208a8, "CMIC_LEDUP0_PROGRAM_RAM42", CMIC_LEDUP0_PROGRAM_RAM42r }, \ 1680 { 0x000208ac, "CMIC_LEDUP0_PROGRAM_RAM43", CMIC_LEDUP0_PROGRAM_RAM43r }, \ 1681 { 0x000208b0, "CMIC_LEDUP0_PROGRAM_RAM44", CMIC_LEDUP0_PROGRAM_RAM44r }, \ 1682 { 0x000208b4, "CMIC_LEDUP0_PROGRAM_RAM45", CMIC_LEDUP0_PROGRAM_RAM45r }, \ 1683 { 0x000208b8, "CMIC_LEDUP0_PROGRAM_RAM46", CMIC_LEDUP0_PROGRAM_RAM46r }, \ 1684 { 0x000208bc, "CMIC_LEDUP0_PROGRAM_RAM47", CMIC_LEDUP0_PROGRAM_RAM47r }, \ 1685 { 0x000208c0, "CMIC_LEDUP0_PROGRAM_RAM48", CMIC_LEDUP0_PROGRAM_RAM48r }, \ 1686 { 0x000208c4, "CMIC_LEDUP0_PROGRAM_RAM49", CMIC_LEDUP0_PROGRAM_RAM49r }, \ 1687 { 0x000208c8, "CMIC_LEDUP0_PROGRAM_RAM50", CMIC_LEDUP0_PROGRAM_RAM50r }, \ 1688 { 0x000208cc, "CMIC_LEDUP0_PROGRAM_RAM51", CMIC_LEDUP0_PROGRAM_RAM51r }, \ 1689 { 0x000208d0, "CMIC_LEDUP0_PROGRAM_RAM52", CMIC_LEDUP0_PROGRAM_RAM52r }, \ 1690 { 0x000208d4, "CMIC_LEDUP0_PROGRAM_RAM53", CMIC_LEDUP0_PROGRAM_RAM53r }, \ 1691 { 0x000208d8, "CMIC_LEDUP0_PROGRAM_RAM54", CMIC_LEDUP0_PROGRAM_RAM54r }, \ 1692 { 0x000208dc, "CMIC_LEDUP0_PROGRAM_RAM55", CMIC_LEDUP0_PROGRAM_RAM55r }, \ 1693 { 0x000208e0, "CMIC_LEDUP0_PROGRAM_RAM56", CMIC_LEDUP0_PROGRAM_RAM56r }, \ 1694 { 0x000208e4, "CMIC_LEDUP0_PROGRAM_RAM57", CMIC_LEDUP0_PROGRAM_RAM57r }, \ 1695 { 0x000208e8, "CMIC_LEDUP0_PROGRAM_RAM58", CMIC_LEDUP0_PROGRAM_RAM58r }, \ 1696 { 0x000208ec, "CMIC_LEDUP0_PROGRAM_RAM59", CMIC_LEDUP0_PROGRAM_RAM59r }, \ 1697 { 0x000208f0, "CMIC_LEDUP0_PROGRAM_RAM60", CMIC_LEDUP0_PROGRAM_RAM60r }, \ 1698 { 0x000208f4, "CMIC_LEDUP0_PROGRAM_RAM61", CMIC_LEDUP0_PROGRAM_RAM61r }, \ 1699 { 0x000208f8, "CMIC_LEDUP0_PROGRAM_RAM62", CMIC_LEDUP0_PROGRAM_RAM62r }, \ 1700 { 0x000208fc, "CMIC_LEDUP0_PROGRAM_RAM63", CMIC_LEDUP0_PROGRAM_RAM63r }, \ 1701 { 0x00020900, "CMIC_LEDUP0_PROGRAM_RAM64", CMIC_LEDUP0_PROGRAM_RAM64r }, \ 1702 { 0x00020904, "CMIC_LEDUP0_PROGRAM_RAM65", CMIC_LEDUP0_PROGRAM_RAM65r }, \ 1703 { 0x00020908, "CMIC_LEDUP0_PROGRAM_RAM66", CMIC_LEDUP0_PROGRAM_RAM66r }, \ 1704 { 0x0002090c, "CMIC_LEDUP0_PROGRAM_RAM67", CMIC_LEDUP0_PROGRAM_RAM67r }, \ 1705 { 0x00020910, "CMIC_LEDUP0_PROGRAM_RAM68", CMIC_LEDUP0_PROGRAM_RAM68r }, \ 1706 { 0x00020914, "CMIC_LEDUP0_PROGRAM_RAM69", CMIC_LEDUP0_PROGRAM_RAM69r }, \ 1707 { 0x00020918, "CMIC_LEDUP0_PROGRAM_RAM70", CMIC_LEDUP0_PROGRAM_RAM70r }, \ 1708 { 0x0002091c, "CMIC_LEDUP0_PROGRAM_RAM71", CMIC_LEDUP0_PROGRAM_RAM71r }, \ 1709 { 0x00020920, "CMIC_LEDUP0_PROGRAM_RAM72", CMIC_LEDUP0_PROGRAM_RAM72r }, \ 1710 { 0x00020924, "CMIC_LEDUP0_PROGRAM_RAM73", CMIC_LEDUP0_PROGRAM_RAM73r }, \ 1711 { 0x00020928, "CMIC_LEDUP0_PROGRAM_RAM74", CMIC_LEDUP0_PROGRAM_RAM74r }, \ 1712 { 0x0002092c, "CMIC_LEDUP0_PROGRAM_RAM75", CMIC_LEDUP0_PROGRAM_RAM75r }, \ 1713 { 0x00020930, "CMIC_LEDUP0_PROGRAM_RAM76", CMIC_LEDUP0_PROGRAM_RAM76r }, \ 1714 { 0x00020934, "CMIC_LEDUP0_PROGRAM_RAM77", CMIC_LEDUP0_PROGRAM_RAM77r }, \ 1715 { 0x00020938, "CMIC_LEDUP0_PROGRAM_RAM78", CMIC_LEDUP0_PROGRAM_RAM78r }, \ 1716 { 0x0002093c, "CMIC_LEDUP0_PROGRAM_RAM79", CMIC_LEDUP0_PROGRAM_RAM79r }, \ 1717 { 0x00020940, "CMIC_LEDUP0_PROGRAM_RAM80", CMIC_LEDUP0_PROGRAM_RAM80r }, \ 1718 { 0x00020944, "CMIC_LEDUP0_PROGRAM_RAM81", CMIC_LEDUP0_PROGRAM_RAM81r }, \ 1719 { 0x00020948, "CMIC_LEDUP0_PROGRAM_RAM82", CMIC_LEDUP0_PROGRAM_RAM82r }, \ 1720 { 0x0002094c, "CMIC_LEDUP0_PROGRAM_RAM83", CMIC_LEDUP0_PROGRAM_RAM83r }, \ 1721 { 0x00020950, "CMIC_LEDUP0_PROGRAM_RAM84", CMIC_LEDUP0_PROGRAM_RAM84r }, \ 1722 { 0x00020954, "CMIC_LEDUP0_PROGRAM_RAM85", CMIC_LEDUP0_PROGRAM_RAM85r }, \ 1723 { 0x00020958, "CMIC_LEDUP0_PROGRAM_RAM86", CMIC_LEDUP0_PROGRAM_RAM86r }, \ 1724 { 0x0002095c, "CMIC_LEDUP0_PROGRAM_RAM87", CMIC_LEDUP0_PROGRAM_RAM87r }, \ 1725 { 0x00020960, "CMIC_LEDUP0_PROGRAM_RAM88", CMIC_LEDUP0_PROGRAM_RAM88r }, \ 1726 { 0x00020964, "CMIC_LEDUP0_PROGRAM_RAM89", CMIC_LEDUP0_PROGRAM_RAM89r }, \ 1727 { 0x00020968, "CMIC_LEDUP0_PROGRAM_RAM90", CMIC_LEDUP0_PROGRAM_RAM90r }, \ 1728 { 0x0002096c, "CMIC_LEDUP0_PROGRAM_RAM91", CMIC_LEDUP0_PROGRAM_RAM91r }, \ 1729 { 0x00020970, "CMIC_LEDUP0_PROGRAM_RAM92", CMIC_LEDUP0_PROGRAM_RAM92r }, \ 1730 { 0x00020974, "CMIC_LEDUP0_PROGRAM_RAM93", CMIC_LEDUP0_PROGRAM_RAM93r }, \ 1731 { 0x00020978, "CMIC_LEDUP0_PROGRAM_RAM94", CMIC_LEDUP0_PROGRAM_RAM94r }, \ 1732 { 0x0002097c, "CMIC_LEDUP0_PROGRAM_RAM95", CMIC_LEDUP0_PROGRAM_RAM95r }, \ 1733 { 0x00020980, "CMIC_LEDUP0_PROGRAM_RAM96", CMIC_LEDUP0_PROGRAM_RAM96r }, \ 1734 { 0x00020984, "CMIC_LEDUP0_PROGRAM_RAM97", CMIC_LEDUP0_PROGRAM_RAM97r }, \ 1735 { 0x00020988, "CMIC_LEDUP0_PROGRAM_RAM98", CMIC_LEDUP0_PROGRAM_RAM98r }, \ 1736 { 0x0002098c, "CMIC_LEDUP0_PROGRAM_RAM99", CMIC_LEDUP0_PROGRAM_RAM99r }, \ 1737 { 0x00020990, "CMIC_LEDUP0_PROGRAM_RAM100", CMIC_LEDUP0_PROGRAM_RAM100r }, \ 1738 { 0x00020994, "CMIC_LEDUP0_PROGRAM_RAM101", CMIC_LEDUP0_PROGRAM_RAM101r }, \ 1739 { 0x00020998, "CMIC_LEDUP0_PROGRAM_RAM102", CMIC_LEDUP0_PROGRAM_RAM102r }, \ 1740 { 0x0002099c, "CMIC_LEDUP0_PROGRAM_RAM103", CMIC_LEDUP0_PROGRAM_RAM103r }, \ 1741 { 0x000209a0, "CMIC_LEDUP0_PROGRAM_RAM104", CMIC_LEDUP0_PROGRAM_RAM104r }, \ 1742 { 0x000209a4, "CMIC_LEDUP0_PROGRAM_RAM105", CMIC_LEDUP0_PROGRAM_RAM105r }, \ 1743 { 0x000209a8, "CMIC_LEDUP0_PROGRAM_RAM106", CMIC_LEDUP0_PROGRAM_RAM106r }, \ 1744 { 0x000209ac, "CMIC_LEDUP0_PROGRAM_RAM107", CMIC_LEDUP0_PROGRAM_RAM107r }, \ 1745 { 0x000209b0, "CMIC_LEDUP0_PROGRAM_RAM108", CMIC_LEDUP0_PROGRAM_RAM108r }, \ 1746 { 0x000209b4, "CMIC_LEDUP0_PROGRAM_RAM109", CMIC_LEDUP0_PROGRAM_RAM109r }, \ 1747 { 0x000209b8, "CMIC_LEDUP0_PROGRAM_RAM110", CMIC_LEDUP0_PROGRAM_RAM110r }, \ 1748 { 0x000209bc, "CMIC_LEDUP0_PROGRAM_RAM111", CMIC_LEDUP0_PROGRAM_RAM111r }, \ 1749 { 0x000209c0, "CMIC_LEDUP0_PROGRAM_RAM112", CMIC_LEDUP0_PROGRAM_RAM112r }, \ 1750 { 0x000209c4, "CMIC_LEDUP0_PROGRAM_RAM113", CMIC_LEDUP0_PROGRAM_RAM113r }, \ 1751 { 0x000209c8, "CMIC_LEDUP0_PROGRAM_RAM114", CMIC_LEDUP0_PROGRAM_RAM114r }, \ 1752 { 0x000209cc, "CMIC_LEDUP0_PROGRAM_RAM115", CMIC_LEDUP0_PROGRAM_RAM115r }, \ 1753 { 0x000209d0, "CMIC_LEDUP0_PROGRAM_RAM116", CMIC_LEDUP0_PROGRAM_RAM116r }, \ 1754 { 0x000209d4, "CMIC_LEDUP0_PROGRAM_RAM117", CMIC_LEDUP0_PROGRAM_RAM117r }, \ 1755 { 0x000209d8, "CMIC_LEDUP0_PROGRAM_RAM118", CMIC_LEDUP0_PROGRAM_RAM118r }, \ 1756 { 0x000209dc, "CMIC_LEDUP0_PROGRAM_RAM119", CMIC_LEDUP0_PROGRAM_RAM119r }, \ 1757 { 0x000209e0, "CMIC_LEDUP0_PROGRAM_RAM120", CMIC_LEDUP0_PROGRAM_RAM120r }, \ 1758 { 0x000209e4, "CMIC_LEDUP0_PROGRAM_RAM121", CMIC_LEDUP0_PROGRAM_RAM121r }, \ 1759 { 0x000209e8, "CMIC_LEDUP0_PROGRAM_RAM122", CMIC_LEDUP0_PROGRAM_RAM122r }, \ 1760 { 0x000209ec, "CMIC_LEDUP0_PROGRAM_RAM123", CMIC_LEDUP0_PROGRAM_RAM123r }, \ 1761 { 0x000209f0, "CMIC_LEDUP0_PROGRAM_RAM124", CMIC_LEDUP0_PROGRAM_RAM124r }, \ 1762 { 0x000209f4, "CMIC_LEDUP0_PROGRAM_RAM125", CMIC_LEDUP0_PROGRAM_RAM125r }, \ 1763 { 0x000209f8, "CMIC_LEDUP0_PROGRAM_RAM126", CMIC_LEDUP0_PROGRAM_RAM126r }, \ 1764 { 0x000209fc, "CMIC_LEDUP0_PROGRAM_RAM127", CMIC_LEDUP0_PROGRAM_RAM127r }, \ 1765 { 0x00020a00, "CMIC_LEDUP0_PROGRAM_RAM128", CMIC_LEDUP0_PROGRAM_RAM128r }, \ 1766 { 0x00020a04, "CMIC_LEDUP0_PROGRAM_RAM129", CMIC_LEDUP0_PROGRAM_RAM129r }, \ 1767 { 0x00020a08, "CMIC_LEDUP0_PROGRAM_RAM130", CMIC_LEDUP0_PROGRAM_RAM130r }, \ 1768 { 0x00020a0c, "CMIC_LEDUP0_PROGRAM_RAM131", CMIC_LEDUP0_PROGRAM_RAM131r }, \ 1769 { 0x00020a10, "CMIC_LEDUP0_PROGRAM_RAM132", CMIC_LEDUP0_PROGRAM_RAM132r }, \ 1770 { 0x00020a14, "CMIC_LEDUP0_PROGRAM_RAM133", CMIC_LEDUP0_PROGRAM_RAM133r }, \ 1771 { 0x00020a18, "CMIC_LEDUP0_PROGRAM_RAM134", CMIC_LEDUP0_PROGRAM_RAM134r }, \ 1772 { 0x00020a1c, "CMIC_LEDUP0_PROGRAM_RAM135", CMIC_LEDUP0_PROGRAM_RAM135r }, \ 1773 { 0x00020a20, "CMIC_LEDUP0_PROGRAM_RAM136", CMIC_LEDUP0_PROGRAM_RAM136r }, \ 1774 { 0x00020a24, "CMIC_LEDUP0_PROGRAM_RAM137", CMIC_LEDUP0_PROGRAM_RAM137r }, \ 1775 { 0x00020a28, "CMIC_LEDUP0_PROGRAM_RAM138", CMIC_LEDUP0_PROGRAM_RAM138r }, \ 1776 { 0x00020a2c, "CMIC_LEDUP0_PROGRAM_RAM139", CMIC_LEDUP0_PROGRAM_RAM139r }, \ 1777 { 0x00020a30, "CMIC_LEDUP0_PROGRAM_RAM140", CMIC_LEDUP0_PROGRAM_RAM140r }, \ 1778 { 0x00020a34, "CMIC_LEDUP0_PROGRAM_RAM141", CMIC_LEDUP0_PROGRAM_RAM141r }, \ 1779 { 0x00020a38, "CMIC_LEDUP0_PROGRAM_RAM142", CMIC_LEDUP0_PROGRAM_RAM142r }, \ 1780 { 0x00020a3c, "CMIC_LEDUP0_PROGRAM_RAM143", CMIC_LEDUP0_PROGRAM_RAM143r }, \ 1781 { 0x00020a40, "CMIC_LEDUP0_PROGRAM_RAM144", CMIC_LEDUP0_PROGRAM_RAM144r }, \ 1782 { 0x00020a44, "CMIC_LEDUP0_PROGRAM_RAM145", CMIC_LEDUP0_PROGRAM_RAM145r }, \ 1783 { 0x00020a48, "CMIC_LEDUP0_PROGRAM_RAM146", CMIC_LEDUP0_PROGRAM_RAM146r }, \ 1784 { 0x00020a4c, "CMIC_LEDUP0_PROGRAM_RAM147", CMIC_LEDUP0_PROGRAM_RAM147r }, \ 1785 { 0x00020a50, "CMIC_LEDUP0_PROGRAM_RAM148", CMIC_LEDUP0_PROGRAM_RAM148r }, \ 1786 { 0x00020a54, "CMIC_LEDUP0_PROGRAM_RAM149", CMIC_LEDUP0_PROGRAM_RAM149r }, \ 1787 { 0x00020a58, "CMIC_LEDUP0_PROGRAM_RAM150", CMIC_LEDUP0_PROGRAM_RAM150r }, \ 1788 { 0x00020a5c, "CMIC_LEDUP0_PROGRAM_RAM151", CMIC_LEDUP0_PROGRAM_RAM151r }, \ 1789 { 0x00020a60, "CMIC_LEDUP0_PROGRAM_RAM152", CMIC_LEDUP0_PROGRAM_RAM152r }, \ 1790 { 0x00020a64, "CMIC_LEDUP0_PROGRAM_RAM153", CMIC_LEDUP0_PROGRAM_RAM153r }, \ 1791 { 0x00020a68, "CMIC_LEDUP0_PROGRAM_RAM154", CMIC_LEDUP0_PROGRAM_RAM154r }, \ 1792 { 0x00020a6c, "CMIC_LEDUP0_PROGRAM_RAM155", CMIC_LEDUP0_PROGRAM_RAM155r }, \ 1793 { 0x00020a70, "CMIC_LEDUP0_PROGRAM_RAM156", CMIC_LEDUP0_PROGRAM_RAM156r }, \ 1794 { 0x00020a74, "CMIC_LEDUP0_PROGRAM_RAM157", CMIC_LEDUP0_PROGRAM_RAM157r }, \ 1795 { 0x00020a78, "CMIC_LEDUP0_PROGRAM_RAM158", CMIC_LEDUP0_PROGRAM_RAM158r }, \ 1796 { 0x00020a7c, "CMIC_LEDUP0_PROGRAM_RAM159", CMIC_LEDUP0_PROGRAM_RAM159r }, \ 1797 { 0x00020a80, "CMIC_LEDUP0_PROGRAM_RAM160", CMIC_LEDUP0_PROGRAM_RAM160r }, \ 1798 { 0x00020a84, "CMIC_LEDUP0_PROGRAM_RAM161", CMIC_LEDUP0_PROGRAM_RAM161r }, \ 1799 { 0x00020a88, "CMIC_LEDUP0_PROGRAM_RAM162", CMIC_LEDUP0_PROGRAM_RAM162r }, \ 1800 { 0x00020a8c, "CMIC_LEDUP0_PROGRAM_RAM163", CMIC_LEDUP0_PROGRAM_RAM163r }, \ 1801 { 0x00020a90, "CMIC_LEDUP0_PROGRAM_RAM164", CMIC_LEDUP0_PROGRAM_RAM164r }, \ 1802 { 0x00020a94, "CMIC_LEDUP0_PROGRAM_RAM165", CMIC_LEDUP0_PROGRAM_RAM165r }, \ 1803 { 0x00020a98, "CMIC_LEDUP0_PROGRAM_RAM166", CMIC_LEDUP0_PROGRAM_RAM166r }, \ 1804 { 0x00020a9c, "CMIC_LEDUP0_PROGRAM_RAM167", CMIC_LEDUP0_PROGRAM_RAM167r }, \ 1805 { 0x00020aa0, "CMIC_LEDUP0_PROGRAM_RAM168", CMIC_LEDUP0_PROGRAM_RAM168r }, \ 1806 { 0x00020aa4, "CMIC_LEDUP0_PROGRAM_RAM169", CMIC_LEDUP0_PROGRAM_RAM169r }, \ 1807 { 0x00020aa8, "CMIC_LEDUP0_PROGRAM_RAM170", CMIC_LEDUP0_PROGRAM_RAM170r }, \ 1808 { 0x00020aac, "CMIC_LEDUP0_PROGRAM_RAM171", CMIC_LEDUP0_PROGRAM_RAM171r }, \ 1809 { 0x00020ab0, "CMIC_LEDUP0_PROGRAM_RAM172", CMIC_LEDUP0_PROGRAM_RAM172r }, \ 1810 { 0x00020ab4, "CMIC_LEDUP0_PROGRAM_RAM173", CMIC_LEDUP0_PROGRAM_RAM173r }, \ 1811 { 0x00020ab8, "CMIC_LEDUP0_PROGRAM_RAM174", CMIC_LEDUP0_PROGRAM_RAM174r }, \ 1812 { 0x00020abc, "CMIC_LEDUP0_PROGRAM_RAM175", CMIC_LEDUP0_PROGRAM_RAM175r }, \ 1813 { 0x00020ac0, "CMIC_LEDUP0_PROGRAM_RAM176", CMIC_LEDUP0_PROGRAM_RAM176r }, \ 1814 { 0x00020ac4, "CMIC_LEDUP0_PROGRAM_RAM177", CMIC_LEDUP0_PROGRAM_RAM177r }, \ 1815 { 0x00020ac8, "CMIC_LEDUP0_PROGRAM_RAM178", CMIC_LEDUP0_PROGRAM_RAM178r }, \ 1816 { 0x00020acc, "CMIC_LEDUP0_PROGRAM_RAM179", CMIC_LEDUP0_PROGRAM_RAM179r }, \ 1817 { 0x00020ad0, "CMIC_LEDUP0_PROGRAM_RAM180", CMIC_LEDUP0_PROGRAM_RAM180r }, \ 1818 { 0x00020ad4, "CMIC_LEDUP0_PROGRAM_RAM181", CMIC_LEDUP0_PROGRAM_RAM181r }, \ 1819 { 0x00020ad8, "CMIC_LEDUP0_PROGRAM_RAM182", CMIC_LEDUP0_PROGRAM_RAM182r }, \ 1820 { 0x00020adc, "CMIC_LEDUP0_PROGRAM_RAM183", CMIC_LEDUP0_PROGRAM_RAM183r }, \ 1821 { 0x00020ae0, "CMIC_LEDUP0_PROGRAM_RAM184", CMIC_LEDUP0_PROGRAM_RAM184r }, \ 1822 { 0x00020ae4, "CMIC_LEDUP0_PROGRAM_RAM185", CMIC_LEDUP0_PROGRAM_RAM185r }, \ 1823 { 0x00020ae8, "CMIC_LEDUP0_PROGRAM_RAM186", CMIC_LEDUP0_PROGRAM_RAM186r }, \ 1824 { 0x00020aec, "CMIC_LEDUP0_PROGRAM_RAM187", CMIC_LEDUP0_PROGRAM_RAM187r }, \ 1825 { 0x00020af0, "CMIC_LEDUP0_PROGRAM_RAM188", CMIC_LEDUP0_PROGRAM_RAM188r }, \ 1826 { 0x00020af4, "CMIC_LEDUP0_PROGRAM_RAM189", CMIC_LEDUP0_PROGRAM_RAM189r }, \ 1827 { 0x00020af8, "CMIC_LEDUP0_PROGRAM_RAM190", CMIC_LEDUP0_PROGRAM_RAM190r }, \ 1828 { 0x00020afc, "CMIC_LEDUP0_PROGRAM_RAM191", CMIC_LEDUP0_PROGRAM_RAM191r }, \ 1829 { 0x00020b00, "CMIC_LEDUP0_PROGRAM_RAM192", CMIC_LEDUP0_PROGRAM_RAM192r }, \ 1830 { 0x00020b04, "CMIC_LEDUP0_PROGRAM_RAM193", CMIC_LEDUP0_PROGRAM_RAM193r }, \ 1831 { 0x00020b08, "CMIC_LEDUP0_PROGRAM_RAM194", CMIC_LEDUP0_PROGRAM_RAM194r }, \ 1832 { 0x00020b0c, "CMIC_LEDUP0_PROGRAM_RAM195", CMIC_LEDUP0_PROGRAM_RAM195r }, \ 1833 { 0x00020b10, "CMIC_LEDUP0_PROGRAM_RAM196", CMIC_LEDUP0_PROGRAM_RAM196r }, \ 1834 { 0x00020b14, "CMIC_LEDUP0_PROGRAM_RAM197", CMIC_LEDUP0_PROGRAM_RAM197r }, \ 1835 { 0x00020b18, "CMIC_LEDUP0_PROGRAM_RAM198", CMIC_LEDUP0_PROGRAM_RAM198r }, \ 1836 { 0x00020b1c, "CMIC_LEDUP0_PROGRAM_RAM199", CMIC_LEDUP0_PROGRAM_RAM199r }, \ 1837 { 0x00020b20, "CMIC_LEDUP0_PROGRAM_RAM200", CMIC_LEDUP0_PROGRAM_RAM200r }, \ 1838 { 0x00020b24, "CMIC_LEDUP0_PROGRAM_RAM201", CMIC_LEDUP0_PROGRAM_RAM201r }, \ 1839 { 0x00020b28, "CMIC_LEDUP0_PROGRAM_RAM202", CMIC_LEDUP0_PROGRAM_RAM202r }, \ 1840 { 0x00020b2c, "CMIC_LEDUP0_PROGRAM_RAM203", CMIC_LEDUP0_PROGRAM_RAM203r }, \ 1841 { 0x00020b30, "CMIC_LEDUP0_PROGRAM_RAM204", CMIC_LEDUP0_PROGRAM_RAM204r }, \ 1842 { 0x00020b34, "CMIC_LEDUP0_PROGRAM_RAM205", CMIC_LEDUP0_PROGRAM_RAM205r }, \ 1843 { 0x00020b38, "CMIC_LEDUP0_PROGRAM_RAM206", CMIC_LEDUP0_PROGRAM_RAM206r }, \ 1844 { 0x00020b3c, "CMIC_LEDUP0_PROGRAM_RAM207", CMIC_LEDUP0_PROGRAM_RAM207r }, \ 1845 { 0x00020b40, "CMIC_LEDUP0_PROGRAM_RAM208", CMIC_LEDUP0_PROGRAM_RAM208r }, \ 1846 { 0x00020b44, "CMIC_LEDUP0_PROGRAM_RAM209", CMIC_LEDUP0_PROGRAM_RAM209r }, \ 1847 { 0x00020b48, "CMIC_LEDUP0_PROGRAM_RAM210", CMIC_LEDUP0_PROGRAM_RAM210r }, \ 1848 { 0x00020b4c, "CMIC_LEDUP0_PROGRAM_RAM211", CMIC_LEDUP0_PROGRAM_RAM211r }, \ 1849 { 0x00020b50, "CMIC_LEDUP0_PROGRAM_RAM212", CMIC_LEDUP0_PROGRAM_RAM212r }, \ 1850 { 0x00020b54, "CMIC_LEDUP0_PROGRAM_RAM213", CMIC_LEDUP0_PROGRAM_RAM213r }, \ 1851 { 0x00020b58, "CMIC_LEDUP0_PROGRAM_RAM214", CMIC_LEDUP0_PROGRAM_RAM214r }, \ 1852 { 0x00020b5c, "CMIC_LEDUP0_PROGRAM_RAM215", CMIC_LEDUP0_PROGRAM_RAM215r }, \ 1853 { 0x00020b60, "CMIC_LEDUP0_PROGRAM_RAM216", CMIC_LEDUP0_PROGRAM_RAM216r }, \ 1854 { 0x00020b64, "CMIC_LEDUP0_PROGRAM_RAM217", CMIC_LEDUP0_PROGRAM_RAM217r }, \ 1855 { 0x00020b68, "CMIC_LEDUP0_PROGRAM_RAM218", CMIC_LEDUP0_PROGRAM_RAM218r }, \ 1856 { 0x00020b6c, "CMIC_LEDUP0_PROGRAM_RAM219", CMIC_LEDUP0_PROGRAM_RAM219r }, \ 1857 { 0x00020b70, "CMIC_LEDUP0_PROGRAM_RAM220", CMIC_LEDUP0_PROGRAM_RAM220r }, \ 1858 { 0x00020b74, "CMIC_LEDUP0_PROGRAM_RAM221", CMIC_LEDUP0_PROGRAM_RAM221r }, \ 1859 { 0x00020b78, "CMIC_LEDUP0_PROGRAM_RAM222", CMIC_LEDUP0_PROGRAM_RAM222r }, \ 1860 { 0x00020b7c, "CMIC_LEDUP0_PROGRAM_RAM223", CMIC_LEDUP0_PROGRAM_RAM223r }, \ 1861 { 0x00020b80, "CMIC_LEDUP0_PROGRAM_RAM224", CMIC_LEDUP0_PROGRAM_RAM224r }, \ 1862 { 0x00020b84, "CMIC_LEDUP0_PROGRAM_RAM225", CMIC_LEDUP0_PROGRAM_RAM225r }, \ 1863 { 0x00020b88, "CMIC_LEDUP0_PROGRAM_RAM226", CMIC_LEDUP0_PROGRAM_RAM226r }, \ 1864 { 0x00020b8c, "CMIC_LEDUP0_PROGRAM_RAM227", CMIC_LEDUP0_PROGRAM_RAM227r }, \ 1865 { 0x00020b90, "CMIC_LEDUP0_PROGRAM_RAM228", CMIC_LEDUP0_PROGRAM_RAM228r }, \ 1866 { 0x00020b94, "CMIC_LEDUP0_PROGRAM_RAM229", CMIC_LEDUP0_PROGRAM_RAM229r }, \ 1867 { 0x00020b98, "CMIC_LEDUP0_PROGRAM_RAM230", CMIC_LEDUP0_PROGRAM_RAM230r }, \ 1868 { 0x00020b9c, "CMIC_LEDUP0_PROGRAM_RAM231", CMIC_LEDUP0_PROGRAM_RAM231r }, \ 1869 { 0x00020ba0, "CMIC_LEDUP0_PROGRAM_RAM232", CMIC_LEDUP0_PROGRAM_RAM232r }, \ 1870 { 0x00020ba4, "CMIC_LEDUP0_PROGRAM_RAM233", CMIC_LEDUP0_PROGRAM_RAM233r }, \ 1871 { 0x00020ba8, "CMIC_LEDUP0_PROGRAM_RAM234", CMIC_LEDUP0_PROGRAM_RAM234r }, \ 1872 { 0x00020bac, "CMIC_LEDUP0_PROGRAM_RAM235", CMIC_LEDUP0_PROGRAM_RAM235r }, \ 1873 { 0x00020bb0, "CMIC_LEDUP0_PROGRAM_RAM236", CMIC_LEDUP0_PROGRAM_RAM236r }, \ 1874 { 0x00020bb4, "CMIC_LEDUP0_PROGRAM_RAM237", CMIC_LEDUP0_PROGRAM_RAM237r }, \ 1875 { 0x00020bb8, "CMIC_LEDUP0_PROGRAM_RAM238", CMIC_LEDUP0_PROGRAM_RAM238r }, \ 1876 { 0x00020bbc, "CMIC_LEDUP0_PROGRAM_RAM239", CMIC_LEDUP0_PROGRAM_RAM239r }, \ 1877 { 0x00020bc0, "CMIC_LEDUP0_PROGRAM_RAM240", CMIC_LEDUP0_PROGRAM_RAM240r }, \ 1878 { 0x00020bc4, "CMIC_LEDUP0_PROGRAM_RAM241", CMIC_LEDUP0_PROGRAM_RAM241r }, \ 1879 { 0x00020bc8, "CMIC_LEDUP0_PROGRAM_RAM242", CMIC_LEDUP0_PROGRAM_RAM242r }, \ 1880 { 0x00020bcc, "CMIC_LEDUP0_PROGRAM_RAM243", CMIC_LEDUP0_PROGRAM_RAM243r }, \ 1881 { 0x00020bd0, "CMIC_LEDUP0_PROGRAM_RAM244", CMIC_LEDUP0_PROGRAM_RAM244r }, \ 1882 { 0x00020bd4, "CMIC_LEDUP0_PROGRAM_RAM245", CMIC_LEDUP0_PROGRAM_RAM245r }, \ 1883 { 0x00020bd8, "CMIC_LEDUP0_PROGRAM_RAM246", CMIC_LEDUP0_PROGRAM_RAM246r }, \ 1884 { 0x00020bdc, "CMIC_LEDUP0_PROGRAM_RAM247", CMIC_LEDUP0_PROGRAM_RAM247r }, \ 1885 { 0x00020be0, "CMIC_LEDUP0_PROGRAM_RAM248", CMIC_LEDUP0_PROGRAM_RAM248r }, \ 1886 { 0x00020be4, "CMIC_LEDUP0_PROGRAM_RAM249", CMIC_LEDUP0_PROGRAM_RAM249r }, \ 1887 { 0x00020be8, "CMIC_LEDUP0_PROGRAM_RAM250", CMIC_LEDUP0_PROGRAM_RAM250r }, \ 1888 { 0x00020bec, "CMIC_LEDUP0_PROGRAM_RAM251", CMIC_LEDUP0_PROGRAM_RAM251r }, \ 1889 { 0x00020bf0, "CMIC_LEDUP0_PROGRAM_RAM252", CMIC_LEDUP0_PROGRAM_RAM252r }, \ 1890 { 0x00020bf4, "CMIC_LEDUP0_PROGRAM_RAM253", CMIC_LEDUP0_PROGRAM_RAM253r }, \ 1891 { 0x00020bf8, "CMIC_LEDUP0_PROGRAM_RAM254", CMIC_LEDUP0_PROGRAM_RAM254r }, \ 1892 { 0x00020bfc, "CMIC_LEDUP0_PROGRAM_RAM255", CMIC_LEDUP0_PROGRAM_RAM255r }, \ 1893 { 0x00021000, "CMIC_LEDUP1_CTRL", CMIC_LEDUP1_CTRLr }, \ 1894 { 0x00021004, "CMIC_LEDUP1_STATUS", CMIC_LEDUP1_STATUSr }, \ 1895 { 0x00021008, "CMIC_LEDUP1_SCANCHAIN_ASSEMBLY_ST_ADDR", CMIC_LEDUP1_SCANCHAIN_ASSEMBLY_ST_ADDRr }, \ 1896 { 0x00021010, "CMIC_LEDUP1_PORT_ORDER_REMAP_0_3", CMIC_LEDUP1_PORT_ORDER_REMAP_0_3r }, \ 1897 { 0x00021014, "CMIC_LEDUP1_PORT_ORDER_REMAP_4_7", CMIC_LEDUP1_PORT_ORDER_REMAP_4_7r }, \ 1898 { 0x00021018, "CMIC_LEDUP1_PORT_ORDER_REMAP_8_11", CMIC_LEDUP1_PORT_ORDER_REMAP_8_11r }, \ 1899 { 0x0002101c, "CMIC_LEDUP1_PORT_ORDER_REMAP_12_15", CMIC_LEDUP1_PORT_ORDER_REMAP_12_15r }, \ 1900 { 0x00021020, "CMIC_LEDUP1_PORT_ORDER_REMAP_16_19", CMIC_LEDUP1_PORT_ORDER_REMAP_16_19r }, \ 1901 { 0x00021024, "CMIC_LEDUP1_PORT_ORDER_REMAP_20_23", CMIC_LEDUP1_PORT_ORDER_REMAP_20_23r }, \ 1902 { 0x00021028, "CMIC_LEDUP1_PORT_ORDER_REMAP_24_27", CMIC_LEDUP1_PORT_ORDER_REMAP_24_27r }, \ 1903 { 0x0002102c, "CMIC_LEDUP1_PORT_ORDER_REMAP_28_31", CMIC_LEDUP1_PORT_ORDER_REMAP_28_31r }, \ 1904 { 0x00021030, "CMIC_LEDUP1_PORT_ORDER_REMAP_32_35", CMIC_LEDUP1_PORT_ORDER_REMAP_32_35r }, \ 1905 { 0x00021034, "CMIC_LEDUP1_PORT_ORDER_REMAP_36_39", CMIC_LEDUP1_PORT_ORDER_REMAP_36_39r }, \ 1906 { 0x00021038, "CMIC_LEDUP1_PORT_ORDER_REMAP_40_43", CMIC_LEDUP1_PORT_ORDER_REMAP_40_43r }, \ 1907 { 0x0002103c, "CMIC_LEDUP1_PORT_ORDER_REMAP_44_47", CMIC_LEDUP1_PORT_ORDER_REMAP_44_47r }, \ 1908 { 0x00021040, "CMIC_LEDUP1_PORT_ORDER_REMAP_48_51", CMIC_LEDUP1_PORT_ORDER_REMAP_48_51r }, \ 1909 { 0x00021044, "CMIC_LEDUP1_PORT_ORDER_REMAP_52_55", CMIC_LEDUP1_PORT_ORDER_REMAP_52_55r }, \ 1910 { 0x00021048, "CMIC_LEDUP1_PORT_ORDER_REMAP_56_59", CMIC_LEDUP1_PORT_ORDER_REMAP_56_59r }, \ 1911 { 0x0002104c, "CMIC_LEDUP1_PORT_ORDER_REMAP_60_63", CMIC_LEDUP1_PORT_ORDER_REMAP_60_63r }, \ 1912 { 0x00021050, "CMIC_LEDUP1_CLK_PARAMS", CMIC_LEDUP1_CLK_PARAMSr }, \ 1913 { 0x00021054, "CMIC_LEDUP1_SCANOUT_COUNT_UPPER", CMIC_LEDUP1_SCANOUT_COUNT_UPPERr }, \ 1914 { 0x00021058, "CMIC_LEDUP1_TM_CONTROL", CMIC_LEDUP1_TM_CONTROLr }, \ 1915 { 0x0002105c, "CMIC_LEDUP1_CLK_DIV", CMIC_LEDUP1_CLK_DIVr }, \ 1916 { 0x00021060, "CMIC_LEDUP1_ECC_CONFIG", CMIC_LEDUP1_ECC_CONFIGr }, \ 1917 { 0x00021064, "CMIC_LEDUP1_ECC_STATUS", CMIC_LEDUP1_ECC_STATUSr }, \ 1918 { 0x00021068, "CMIC_LEDUP1_ECC_INTR_ENABLE", CMIC_LEDUP1_ECC_INTR_ENABLEr }, \ 1919 { 0x0002106c, "CMIC_LEDUP1_ECC_INTR", CMIC_LEDUP1_ECC_INTRr }, \ 1920 { 0x00021070, "CMIC_LEDUP1_ECC_INTR_CLR", CMIC_LEDUP1_ECC_INTR_CLRr }, \ 1921 { 0x00021400, "CMIC_LEDUP1_DATA_RAM0", CMIC_LEDUP1_DATA_RAM0r }, \ 1922 { 0x00021400, "CMIC_LEDUP1_DATA_RAM", CMIC_LEDUP1_DATA_RAMr }, \ 1923 { 0x00021404, "CMIC_LEDUP1_DATA_RAM1", CMIC_LEDUP1_DATA_RAM1r }, \ 1924 { 0x00021408, "CMIC_LEDUP1_DATA_RAM2", CMIC_LEDUP1_DATA_RAM2r }, \ 1925 { 0x0002140c, "CMIC_LEDUP1_DATA_RAM3", CMIC_LEDUP1_DATA_RAM3r }, \ 1926 { 0x00021410, "CMIC_LEDUP1_DATA_RAM4", CMIC_LEDUP1_DATA_RAM4r }, \ 1927 { 0x00021414, "CMIC_LEDUP1_DATA_RAM5", CMIC_LEDUP1_DATA_RAM5r }, \ 1928 { 0x00021418, "CMIC_LEDUP1_DATA_RAM6", CMIC_LEDUP1_DATA_RAM6r }, \ 1929 { 0x0002141c, "CMIC_LEDUP1_DATA_RAM7", CMIC_LEDUP1_DATA_RAM7r }, \ 1930 { 0x00021420, "CMIC_LEDUP1_DATA_RAM8", CMIC_LEDUP1_DATA_RAM8r }, \ 1931 { 0x00021424, "CMIC_LEDUP1_DATA_RAM9", CMIC_LEDUP1_DATA_RAM9r }, \ 1932 { 0x00021428, "CMIC_LEDUP1_DATA_RAM10", CMIC_LEDUP1_DATA_RAM10r }, \ 1933 { 0x0002142c, "CMIC_LEDUP1_DATA_RAM11", CMIC_LEDUP1_DATA_RAM11r }, \ 1934 { 0x00021430, "CMIC_LEDUP1_DATA_RAM12", CMIC_LEDUP1_DATA_RAM12r }, \ 1935 { 0x00021434, "CMIC_LEDUP1_DATA_RAM13", CMIC_LEDUP1_DATA_RAM13r }, \ 1936 { 0x00021438, "CMIC_LEDUP1_DATA_RAM14", CMIC_LEDUP1_DATA_RAM14r }, \ 1937 { 0x0002143c, "CMIC_LEDUP1_DATA_RAM15", CMIC_LEDUP1_DATA_RAM15r }, \ 1938 { 0x00021440, "CMIC_LEDUP1_DATA_RAM16", CMIC_LEDUP1_DATA_RAM16r }, \ 1939 { 0x00021444, "CMIC_LEDUP1_DATA_RAM17", CMIC_LEDUP1_DATA_RAM17r }, \ 1940 { 0x00021448, "CMIC_LEDUP1_DATA_RAM18", CMIC_LEDUP1_DATA_RAM18r }, \ 1941 { 0x0002144c, "CMIC_LEDUP1_DATA_RAM19", CMIC_LEDUP1_DATA_RAM19r }, \ 1942 { 0x00021450, "CMIC_LEDUP1_DATA_RAM20", CMIC_LEDUP1_DATA_RAM20r }, \ 1943 { 0x00021454, "CMIC_LEDUP1_DATA_RAM21", CMIC_LEDUP1_DATA_RAM21r }, \ 1944 { 0x00021458, "CMIC_LEDUP1_DATA_RAM22", CMIC_LEDUP1_DATA_RAM22r }, \ 1945 { 0x0002145c, "CMIC_LEDUP1_DATA_RAM23", CMIC_LEDUP1_DATA_RAM23r }, \ 1946 { 0x00021460, "CMIC_LEDUP1_DATA_RAM24", CMIC_LEDUP1_DATA_RAM24r }, \ 1947 { 0x00021464, "CMIC_LEDUP1_DATA_RAM25", CMIC_LEDUP1_DATA_RAM25r }, \ 1948 { 0x00021468, "CMIC_LEDUP1_DATA_RAM26", CMIC_LEDUP1_DATA_RAM26r }, \ 1949 { 0x0002146c, "CMIC_LEDUP1_DATA_RAM27", CMIC_LEDUP1_DATA_RAM27r }, \ 1950 { 0x00021470, "CMIC_LEDUP1_DATA_RAM28", CMIC_LEDUP1_DATA_RAM28r }, \ 1951 { 0x00021474, "CMIC_LEDUP1_DATA_RAM29", CMIC_LEDUP1_DATA_RAM29r }, \ 1952 { 0x00021478, "CMIC_LEDUP1_DATA_RAM30", CMIC_LEDUP1_DATA_RAM30r }, \ 1953 { 0x0002147c, "CMIC_LEDUP1_DATA_RAM31", CMIC_LEDUP1_DATA_RAM31r }, \ 1954 { 0x00021480, "CMIC_LEDUP1_DATA_RAM32", CMIC_LEDUP1_DATA_RAM32r }, \ 1955 { 0x00021484, "CMIC_LEDUP1_DATA_RAM33", CMIC_LEDUP1_DATA_RAM33r }, \ 1956 { 0x00021488, "CMIC_LEDUP1_DATA_RAM34", CMIC_LEDUP1_DATA_RAM34r }, \ 1957 { 0x0002148c, "CMIC_LEDUP1_DATA_RAM35", CMIC_LEDUP1_DATA_RAM35r }, \ 1958 { 0x00021490, "CMIC_LEDUP1_DATA_RAM36", CMIC_LEDUP1_DATA_RAM36r }, \ 1959 { 0x00021494, "CMIC_LEDUP1_DATA_RAM37", CMIC_LEDUP1_DATA_RAM37r }, \ 1960 { 0x00021498, "CMIC_LEDUP1_DATA_RAM38", CMIC_LEDUP1_DATA_RAM38r }, \ 1961 { 0x0002149c, "CMIC_LEDUP1_DATA_RAM39", CMIC_LEDUP1_DATA_RAM39r }, \ 1962 { 0x000214a0, "CMIC_LEDUP1_DATA_RAM40", CMIC_LEDUP1_DATA_RAM40r }, \ 1963 { 0x000214a4, "CMIC_LEDUP1_DATA_RAM41", CMIC_LEDUP1_DATA_RAM41r }, \ 1964 { 0x000214a8, "CMIC_LEDUP1_DATA_RAM42", CMIC_LEDUP1_DATA_RAM42r }, \ 1965 { 0x000214ac, "CMIC_LEDUP1_DATA_RAM43", CMIC_LEDUP1_DATA_RAM43r }, \ 1966 { 0x000214b0, "CMIC_LEDUP1_DATA_RAM44", CMIC_LEDUP1_DATA_RAM44r }, \ 1967 { 0x000214b4, "CMIC_LEDUP1_DATA_RAM45", CMIC_LEDUP1_DATA_RAM45r }, \ 1968 { 0x000214b8, "CMIC_LEDUP1_DATA_RAM46", CMIC_LEDUP1_DATA_RAM46r }, \ 1969 { 0x000214bc, "CMIC_LEDUP1_DATA_RAM47", CMIC_LEDUP1_DATA_RAM47r }, \ 1970 { 0x000214c0, "CMIC_LEDUP1_DATA_RAM48", CMIC_LEDUP1_DATA_RAM48r }, \ 1971 { 0x000214c4, "CMIC_LEDUP1_DATA_RAM49", CMIC_LEDUP1_DATA_RAM49r }, \ 1972 { 0x000214c8, "CMIC_LEDUP1_DATA_RAM50", CMIC_LEDUP1_DATA_RAM50r }, \ 1973 { 0x000214cc, "CMIC_LEDUP1_DATA_RAM51", CMIC_LEDUP1_DATA_RAM51r }, \ 1974 { 0x000214d0, "CMIC_LEDUP1_DATA_RAM52", CMIC_LEDUP1_DATA_RAM52r }, \ 1975 { 0x000214d4, "CMIC_LEDUP1_DATA_RAM53", CMIC_LEDUP1_DATA_RAM53r }, \ 1976 { 0x000214d8, "CMIC_LEDUP1_DATA_RAM54", CMIC_LEDUP1_DATA_RAM54r }, \ 1977 { 0x000214dc, "CMIC_LEDUP1_DATA_RAM55", CMIC_LEDUP1_DATA_RAM55r }, \ 1978 { 0x000214e0, "CMIC_LEDUP1_DATA_RAM56", CMIC_LEDUP1_DATA_RAM56r }, \ 1979 { 0x000214e4, "CMIC_LEDUP1_DATA_RAM57", CMIC_LEDUP1_DATA_RAM57r }, \ 1980 { 0x000214e8, "CMIC_LEDUP1_DATA_RAM58", CMIC_LEDUP1_DATA_RAM58r }, \ 1981 { 0x000214ec, "CMIC_LEDUP1_DATA_RAM59", CMIC_LEDUP1_DATA_RAM59r }, \ 1982 { 0x000214f0, "CMIC_LEDUP1_DATA_RAM60", CMIC_LEDUP1_DATA_RAM60r }, \ 1983 { 0x000214f4, "CMIC_LEDUP1_DATA_RAM61", CMIC_LEDUP1_DATA_RAM61r }, \ 1984 { 0x000214f8, "CMIC_LEDUP1_DATA_RAM62", CMIC_LEDUP1_DATA_RAM62r }, \ 1985 { 0x000214fc, "CMIC_LEDUP1_DATA_RAM63", CMIC_LEDUP1_DATA_RAM63r }, \ 1986 { 0x00021500, "CMIC_LEDUP1_DATA_RAM64", CMIC_LEDUP1_DATA_RAM64r }, \ 1987 { 0x00021504, "CMIC_LEDUP1_DATA_RAM65", CMIC_LEDUP1_DATA_RAM65r }, \ 1988 { 0x00021508, "CMIC_LEDUP1_DATA_RAM66", CMIC_LEDUP1_DATA_RAM66r }, \ 1989 { 0x0002150c, "CMIC_LEDUP1_DATA_RAM67", CMIC_LEDUP1_DATA_RAM67r }, \ 1990 { 0x00021510, "CMIC_LEDUP1_DATA_RAM68", CMIC_LEDUP1_DATA_RAM68r }, \ 1991 { 0x00021514, "CMIC_LEDUP1_DATA_RAM69", CMIC_LEDUP1_DATA_RAM69r }, \ 1992 { 0x00021518, "CMIC_LEDUP1_DATA_RAM70", CMIC_LEDUP1_DATA_RAM70r }, \ 1993 { 0x0002151c, "CMIC_LEDUP1_DATA_RAM71", CMIC_LEDUP1_DATA_RAM71r }, \ 1994 { 0x00021520, "CMIC_LEDUP1_DATA_RAM72", CMIC_LEDUP1_DATA_RAM72r }, \ 1995 { 0x00021524, "CMIC_LEDUP1_DATA_RAM73", CMIC_LEDUP1_DATA_RAM73r }, \ 1996 { 0x00021528, "CMIC_LEDUP1_DATA_RAM74", CMIC_LEDUP1_DATA_RAM74r }, \ 1997 { 0x0002152c, "CMIC_LEDUP1_DATA_RAM75", CMIC_LEDUP1_DATA_RAM75r }, \ 1998 { 0x00021530, "CMIC_LEDUP1_DATA_RAM76", CMIC_LEDUP1_DATA_RAM76r }, \ 1999 { 0x00021534, "CMIC_LEDUP1_DATA_RAM77", CMIC_LEDUP1_DATA_RAM77r }, \ 2000 { 0x00021538, "CMIC_LEDUP1_DATA_RAM78", CMIC_LEDUP1_DATA_RAM78r }, \ 2001 { 0x0002153c, "CMIC_LEDUP1_DATA_RAM79", CMIC_LEDUP1_DATA_RAM79r }, \ 2002 { 0x00021540, "CMIC_LEDUP1_DATA_RAM80", CMIC_LEDUP1_DATA_RAM80r }, \ 2003 { 0x00021544, "CMIC_LEDUP1_DATA_RAM81", CMIC_LEDUP1_DATA_RAM81r }, \ 2004 { 0x00021548, "CMIC_LEDUP1_DATA_RAM82", CMIC_LEDUP1_DATA_RAM82r }, \ 2005 { 0x0002154c, "CMIC_LEDUP1_DATA_RAM83", CMIC_LEDUP1_DATA_RAM83r }, \ 2006 { 0x00021550, "CMIC_LEDUP1_DATA_RAM84", CMIC_LEDUP1_DATA_RAM84r }, \ 2007 { 0x00021554, "CMIC_LEDUP1_DATA_RAM85", CMIC_LEDUP1_DATA_RAM85r }, \ 2008 { 0x00021558, "CMIC_LEDUP1_DATA_RAM86", CMIC_LEDUP1_DATA_RAM86r }, \ 2009 { 0x0002155c, "CMIC_LEDUP1_DATA_RAM87", CMIC_LEDUP1_DATA_RAM87r }, \ 2010 { 0x00021560, "CMIC_LEDUP1_DATA_RAM88", CMIC_LEDUP1_DATA_RAM88r }, \ 2011 { 0x00021564, "CMIC_LEDUP1_DATA_RAM89", CMIC_LEDUP1_DATA_RAM89r }, \ 2012 { 0x00021568, "CMIC_LEDUP1_DATA_RAM90", CMIC_LEDUP1_DATA_RAM90r }, \ 2013 { 0x0002156c, "CMIC_LEDUP1_DATA_RAM91", CMIC_LEDUP1_DATA_RAM91r }, \ 2014 { 0x00021570, "CMIC_LEDUP1_DATA_RAM92", CMIC_LEDUP1_DATA_RAM92r }, \ 2015 { 0x00021574, "CMIC_LEDUP1_DATA_RAM93", CMIC_LEDUP1_DATA_RAM93r }, \ 2016 { 0x00021578, "CMIC_LEDUP1_DATA_RAM94", CMIC_LEDUP1_DATA_RAM94r }, \ 2017 { 0x0002157c, "CMIC_LEDUP1_DATA_RAM95", CMIC_LEDUP1_DATA_RAM95r }, \ 2018 { 0x00021580, "CMIC_LEDUP1_DATA_RAM96", CMIC_LEDUP1_DATA_RAM96r }, \ 2019 { 0x00021584, "CMIC_LEDUP1_DATA_RAM97", CMIC_LEDUP1_DATA_RAM97r }, \ 2020 { 0x00021588, "CMIC_LEDUP1_DATA_RAM98", CMIC_LEDUP1_DATA_RAM98r }, \ 2021 { 0x0002158c, "CMIC_LEDUP1_DATA_RAM99", CMIC_LEDUP1_DATA_RAM99r }, \ 2022 { 0x00021590, "CMIC_LEDUP1_DATA_RAM100", CMIC_LEDUP1_DATA_RAM100r }, \ 2023 { 0x00021594, "CMIC_LEDUP1_DATA_RAM101", CMIC_LEDUP1_DATA_RAM101r }, \ 2024 { 0x00021598, "CMIC_LEDUP1_DATA_RAM102", CMIC_LEDUP1_DATA_RAM102r }, \ 2025 { 0x0002159c, "CMIC_LEDUP1_DATA_RAM103", CMIC_LEDUP1_DATA_RAM103r }, \ 2026 { 0x000215a0, "CMIC_LEDUP1_DATA_RAM104", CMIC_LEDUP1_DATA_RAM104r }, \ 2027 { 0x000215a4, "CMIC_LEDUP1_DATA_RAM105", CMIC_LEDUP1_DATA_RAM105r }, \ 2028 { 0x000215a8, "CMIC_LEDUP1_DATA_RAM106", CMIC_LEDUP1_DATA_RAM106r }, \ 2029 { 0x000215ac, "CMIC_LEDUP1_DATA_RAM107", CMIC_LEDUP1_DATA_RAM107r }, \ 2030 { 0x000215b0, "CMIC_LEDUP1_DATA_RAM108", CMIC_LEDUP1_DATA_RAM108r }, \ 2031 { 0x000215b4, "CMIC_LEDUP1_DATA_RAM109", CMIC_LEDUP1_DATA_RAM109r }, \ 2032 { 0x000215b8, "CMIC_LEDUP1_DATA_RAM110", CMIC_LEDUP1_DATA_RAM110r }, \ 2033 { 0x000215bc, "CMIC_LEDUP1_DATA_RAM111", CMIC_LEDUP1_DATA_RAM111r }, \ 2034 { 0x000215c0, "CMIC_LEDUP1_DATA_RAM112", CMIC_LEDUP1_DATA_RAM112r }, \ 2035 { 0x000215c4, "CMIC_LEDUP1_DATA_RAM113", CMIC_LEDUP1_DATA_RAM113r }, \ 2036 { 0x000215c8, "CMIC_LEDUP1_DATA_RAM114", CMIC_LEDUP1_DATA_RAM114r }, \ 2037 { 0x000215cc, "CMIC_LEDUP1_DATA_RAM115", CMIC_LEDUP1_DATA_RAM115r }, \ 2038 { 0x000215d0, "CMIC_LEDUP1_DATA_RAM116", CMIC_LEDUP1_DATA_RAM116r }, \ 2039 { 0x000215d4, "CMIC_LEDUP1_DATA_RAM117", CMIC_LEDUP1_DATA_RAM117r }, \ 2040 { 0x000215d8, "CMIC_LEDUP1_DATA_RAM118", CMIC_LEDUP1_DATA_RAM118r }, \ 2041 { 0x000215dc, "CMIC_LEDUP1_DATA_RAM119", CMIC_LEDUP1_DATA_RAM119r }, \ 2042 { 0x000215e0, "CMIC_LEDUP1_DATA_RAM120", CMIC_LEDUP1_DATA_RAM120r }, \ 2043 { 0x000215e4, "CMIC_LEDUP1_DATA_RAM121", CMIC_LEDUP1_DATA_RAM121r }, \ 2044 { 0x000215e8, "CMIC_LEDUP1_DATA_RAM122", CMIC_LEDUP1_DATA_RAM122r }, \ 2045 { 0x000215ec, "CMIC_LEDUP1_DATA_RAM123", CMIC_LEDUP1_DATA_RAM123r }, \ 2046 { 0x000215f0, "CMIC_LEDUP1_DATA_RAM124", CMIC_LEDUP1_DATA_RAM124r }, \ 2047 { 0x000215f4, "CMIC_LEDUP1_DATA_RAM125", CMIC_LEDUP1_DATA_RAM125r }, \ 2048 { 0x000215f8, "CMIC_LEDUP1_DATA_RAM126", CMIC_LEDUP1_DATA_RAM126r }, \ 2049 { 0x000215fc, "CMIC_LEDUP1_DATA_RAM127", CMIC_LEDUP1_DATA_RAM127r }, \ 2050 { 0x00021600, "CMIC_LEDUP1_DATA_RAM128", CMIC_LEDUP1_DATA_RAM128r }, \ 2051 { 0x00021604, "CMIC_LEDUP1_DATA_RAM129", CMIC_LEDUP1_DATA_RAM129r }, \ 2052 { 0x00021608, "CMIC_LEDUP1_DATA_RAM130", CMIC_LEDUP1_DATA_RAM130r }, \ 2053 { 0x0002160c, "CMIC_LEDUP1_DATA_RAM131", CMIC_LEDUP1_DATA_RAM131r }, \ 2054 { 0x00021610, "CMIC_LEDUP1_DATA_RAM132", CMIC_LEDUP1_DATA_RAM132r }, \ 2055 { 0x00021614, "CMIC_LEDUP1_DATA_RAM133", CMIC_LEDUP1_DATA_RAM133r }, \ 2056 { 0x00021618, "CMIC_LEDUP1_DATA_RAM134", CMIC_LEDUP1_DATA_RAM134r }, \ 2057 { 0x0002161c, "CMIC_LEDUP1_DATA_RAM135", CMIC_LEDUP1_DATA_RAM135r }, \ 2058 { 0x00021620, "CMIC_LEDUP1_DATA_RAM136", CMIC_LEDUP1_DATA_RAM136r }, \ 2059 { 0x00021624, "CMIC_LEDUP1_DATA_RAM137", CMIC_LEDUP1_DATA_RAM137r }, \ 2060 { 0x00021628, "CMIC_LEDUP1_DATA_RAM138", CMIC_LEDUP1_DATA_RAM138r }, \ 2061 { 0x0002162c, "CMIC_LEDUP1_DATA_RAM139", CMIC_LEDUP1_DATA_RAM139r }, \ 2062 { 0x00021630, "CMIC_LEDUP1_DATA_RAM140", CMIC_LEDUP1_DATA_RAM140r }, \ 2063 { 0x00021634, "CMIC_LEDUP1_DATA_RAM141", CMIC_LEDUP1_DATA_RAM141r }, \ 2064 { 0x00021638, "CMIC_LEDUP1_DATA_RAM142", CMIC_LEDUP1_DATA_RAM142r }, \ 2065 { 0x0002163c, "CMIC_LEDUP1_DATA_RAM143", CMIC_LEDUP1_DATA_RAM143r }, \ 2066 { 0x00021640, "CMIC_LEDUP1_DATA_RAM144", CMIC_LEDUP1_DATA_RAM144r }, \ 2067 { 0x00021644, "CMIC_LEDUP1_DATA_RAM145", CMIC_LEDUP1_DATA_RAM145r }, \ 2068 { 0x00021648, "CMIC_LEDUP1_DATA_RAM146", CMIC_LEDUP1_DATA_RAM146r }, \ 2069 { 0x0002164c, "CMIC_LEDUP1_DATA_RAM147", CMIC_LEDUP1_DATA_RAM147r }, \ 2070 { 0x00021650, "CMIC_LEDUP1_DATA_RAM148", CMIC_LEDUP1_DATA_RAM148r }, \ 2071 { 0x00021654, "CMIC_LEDUP1_DATA_RAM149", CMIC_LEDUP1_DATA_RAM149r }, \ 2072 { 0x00021658, "CMIC_LEDUP1_DATA_RAM150", CMIC_LEDUP1_DATA_RAM150r }, \ 2073 { 0x0002165c, "CMIC_LEDUP1_DATA_RAM151", CMIC_LEDUP1_DATA_RAM151r }, \ 2074 { 0x00021660, "CMIC_LEDUP1_DATA_RAM152", CMIC_LEDUP1_DATA_RAM152r }, \ 2075 { 0x00021664, "CMIC_LEDUP1_DATA_RAM153", CMIC_LEDUP1_DATA_RAM153r }, \ 2076 { 0x00021668, "CMIC_LEDUP1_DATA_RAM154", CMIC_LEDUP1_DATA_RAM154r }, \ 2077 { 0x0002166c, "CMIC_LEDUP1_DATA_RAM155", CMIC_LEDUP1_DATA_RAM155r }, \ 2078 { 0x00021670, "CMIC_LEDUP1_DATA_RAM156", CMIC_LEDUP1_DATA_RAM156r }, \ 2079 { 0x00021674, "CMIC_LEDUP1_DATA_RAM157", CMIC_LEDUP1_DATA_RAM157r }, \ 2080 { 0x00021678, "CMIC_LEDUP1_DATA_RAM158", CMIC_LEDUP1_DATA_RAM158r }, \ 2081 { 0x0002167c, "CMIC_LEDUP1_DATA_RAM159", CMIC_LEDUP1_DATA_RAM159r }, \ 2082 { 0x00021680, "CMIC_LEDUP1_DATA_RAM160", CMIC_LEDUP1_DATA_RAM160r }, \ 2083 { 0x00021684, "CMIC_LEDUP1_DATA_RAM161", CMIC_LEDUP1_DATA_RAM161r }, \ 2084 { 0x00021688, "CMIC_LEDUP1_DATA_RAM162", CMIC_LEDUP1_DATA_RAM162r }, \ 2085 { 0x0002168c, "CMIC_LEDUP1_DATA_RAM163", CMIC_LEDUP1_DATA_RAM163r }, \ 2086 { 0x00021690, "CMIC_LEDUP1_DATA_RAM164", CMIC_LEDUP1_DATA_RAM164r }, \ 2087 { 0x00021694, "CMIC_LEDUP1_DATA_RAM165", CMIC_LEDUP1_DATA_RAM165r }, \ 2088 { 0x00021698, "CMIC_LEDUP1_DATA_RAM166", CMIC_LEDUP1_DATA_RAM166r }, \ 2089 { 0x0002169c, "CMIC_LEDUP1_DATA_RAM167", CMIC_LEDUP1_DATA_RAM167r }, \ 2090 { 0x000216a0, "CMIC_LEDUP1_DATA_RAM168", CMIC_LEDUP1_DATA_RAM168r }, \ 2091 { 0x000216a4, "CMIC_LEDUP1_DATA_RAM169", CMIC_LEDUP1_DATA_RAM169r }, \ 2092 { 0x000216a8, "CMIC_LEDUP1_DATA_RAM170", CMIC_LEDUP1_DATA_RAM170r }, \ 2093 { 0x000216ac, "CMIC_LEDUP1_DATA_RAM171", CMIC_LEDUP1_DATA_RAM171r }, \ 2094 { 0x000216b0, "CMIC_LEDUP1_DATA_RAM172", CMIC_LEDUP1_DATA_RAM172r }, \ 2095 { 0x000216b4, "CMIC_LEDUP1_DATA_RAM173", CMIC_LEDUP1_DATA_RAM173r }, \ 2096 { 0x000216b8, "CMIC_LEDUP1_DATA_RAM174", CMIC_LEDUP1_DATA_RAM174r }, \ 2097 { 0x000216bc, "CMIC_LEDUP1_DATA_RAM175", CMIC_LEDUP1_DATA_RAM175r }, \ 2098 { 0x000216c0, "CMIC_LEDUP1_DATA_RAM176", CMIC_LEDUP1_DATA_RAM176r }, \ 2099 { 0x000216c4, "CMIC_LEDUP1_DATA_RAM177", CMIC_LEDUP1_DATA_RAM177r }, \ 2100 { 0x000216c8, "CMIC_LEDUP1_DATA_RAM178", CMIC_LEDUP1_DATA_RAM178r }, \ 2101 { 0x000216cc, "CMIC_LEDUP1_DATA_RAM179", CMIC_LEDUP1_DATA_RAM179r }, \ 2102 { 0x000216d0, "CMIC_LEDUP1_DATA_RAM180", CMIC_LEDUP1_DATA_RAM180r }, \ 2103 { 0x000216d4, "CMIC_LEDUP1_DATA_RAM181", CMIC_LEDUP1_DATA_RAM181r }, \ 2104 { 0x000216d8, "CMIC_LEDUP1_DATA_RAM182", CMIC_LEDUP1_DATA_RAM182r }, \ 2105 { 0x000216dc, "CMIC_LEDUP1_DATA_RAM183", CMIC_LEDUP1_DATA_RAM183r }, \ 2106 { 0x000216e0, "CMIC_LEDUP1_DATA_RAM184", CMIC_LEDUP1_DATA_RAM184r }, \ 2107 { 0x000216e4, "CMIC_LEDUP1_DATA_RAM185", CMIC_LEDUP1_DATA_RAM185r }, \ 2108 { 0x000216e8, "CMIC_LEDUP1_DATA_RAM186", CMIC_LEDUP1_DATA_RAM186r }, \ 2109 { 0x000216ec, "CMIC_LEDUP1_DATA_RAM187", CMIC_LEDUP1_DATA_RAM187r }, \ 2110 { 0x000216f0, "CMIC_LEDUP1_DATA_RAM188", CMIC_LEDUP1_DATA_RAM188r }, \ 2111 { 0x000216f4, "CMIC_LEDUP1_DATA_RAM189", CMIC_LEDUP1_DATA_RAM189r }, \ 2112 { 0x000216f8, "CMIC_LEDUP1_DATA_RAM190", CMIC_LEDUP1_DATA_RAM190r }, \ 2113 { 0x000216fc, "CMIC_LEDUP1_DATA_RAM191", CMIC_LEDUP1_DATA_RAM191r }, \ 2114 { 0x00021700, "CMIC_LEDUP1_DATA_RAM192", CMIC_LEDUP1_DATA_RAM192r }, \ 2115 { 0x00021704, "CMIC_LEDUP1_DATA_RAM193", CMIC_LEDUP1_DATA_RAM193r }, \ 2116 { 0x00021708, "CMIC_LEDUP1_DATA_RAM194", CMIC_LEDUP1_DATA_RAM194r }, \ 2117 { 0x0002170c, "CMIC_LEDUP1_DATA_RAM195", CMIC_LEDUP1_DATA_RAM195r }, \ 2118 { 0x00021710, "CMIC_LEDUP1_DATA_RAM196", CMIC_LEDUP1_DATA_RAM196r }, \ 2119 { 0x00021714, "CMIC_LEDUP1_DATA_RAM197", CMIC_LEDUP1_DATA_RAM197r }, \ 2120 { 0x00021718, "CMIC_LEDUP1_DATA_RAM198", CMIC_LEDUP1_DATA_RAM198r }, \ 2121 { 0x0002171c, "CMIC_LEDUP1_DATA_RAM199", CMIC_LEDUP1_DATA_RAM199r }, \ 2122 { 0x00021720, "CMIC_LEDUP1_DATA_RAM200", CMIC_LEDUP1_DATA_RAM200r }, \ 2123 { 0x00021724, "CMIC_LEDUP1_DATA_RAM201", CMIC_LEDUP1_DATA_RAM201r }, \ 2124 { 0x00021728, "CMIC_LEDUP1_DATA_RAM202", CMIC_LEDUP1_DATA_RAM202r }, \ 2125 { 0x0002172c, "CMIC_LEDUP1_DATA_RAM203", CMIC_LEDUP1_DATA_RAM203r }, \ 2126 { 0x00021730, "CMIC_LEDUP1_DATA_RAM204", CMIC_LEDUP1_DATA_RAM204r }, \ 2127 { 0x00021734, "CMIC_LEDUP1_DATA_RAM205", CMIC_LEDUP1_DATA_RAM205r }, \ 2128 { 0x00021738, "CMIC_LEDUP1_DATA_RAM206", CMIC_LEDUP1_DATA_RAM206r }, \ 2129 { 0x0002173c, "CMIC_LEDUP1_DATA_RAM207", CMIC_LEDUP1_DATA_RAM207r }, \ 2130 { 0x00021740, "CMIC_LEDUP1_DATA_RAM208", CMIC_LEDUP1_DATA_RAM208r }, \ 2131 { 0x00021744, "CMIC_LEDUP1_DATA_RAM209", CMIC_LEDUP1_DATA_RAM209r }, \ 2132 { 0x00021748, "CMIC_LEDUP1_DATA_RAM210", CMIC_LEDUP1_DATA_RAM210r }, \ 2133 { 0x0002174c, "CMIC_LEDUP1_DATA_RAM211", CMIC_LEDUP1_DATA_RAM211r }, \ 2134 { 0x00021750, "CMIC_LEDUP1_DATA_RAM212", CMIC_LEDUP1_DATA_RAM212r }, \ 2135 { 0x00021754, "CMIC_LEDUP1_DATA_RAM213", CMIC_LEDUP1_DATA_RAM213r }, \ 2136 { 0x00021758, "CMIC_LEDUP1_DATA_RAM214", CMIC_LEDUP1_DATA_RAM214r }, \ 2137 { 0x0002175c, "CMIC_LEDUP1_DATA_RAM215", CMIC_LEDUP1_DATA_RAM215r }, \ 2138 { 0x00021760, "CMIC_LEDUP1_DATA_RAM216", CMIC_LEDUP1_DATA_RAM216r }, \ 2139 { 0x00021764, "CMIC_LEDUP1_DATA_RAM217", CMIC_LEDUP1_DATA_RAM217r }, \ 2140 { 0x00021768, "CMIC_LEDUP1_DATA_RAM218", CMIC_LEDUP1_DATA_RAM218r }, \ 2141 { 0x0002176c, "CMIC_LEDUP1_DATA_RAM219", CMIC_LEDUP1_DATA_RAM219r }, \ 2142 { 0x00021770, "CMIC_LEDUP1_DATA_RAM220", CMIC_LEDUP1_DATA_RAM220r }, \ 2143 { 0x00021774, "CMIC_LEDUP1_DATA_RAM221", CMIC_LEDUP1_DATA_RAM221r }, \ 2144 { 0x00021778, "CMIC_LEDUP1_DATA_RAM222", CMIC_LEDUP1_DATA_RAM222r }, \ 2145 { 0x0002177c, "CMIC_LEDUP1_DATA_RAM223", CMIC_LEDUP1_DATA_RAM223r }, \ 2146 { 0x00021780, "CMIC_LEDUP1_DATA_RAM224", CMIC_LEDUP1_DATA_RAM224r }, \ 2147 { 0x00021784, "CMIC_LEDUP1_DATA_RAM225", CMIC_LEDUP1_DATA_RAM225r }, \ 2148 { 0x00021788, "CMIC_LEDUP1_DATA_RAM226", CMIC_LEDUP1_DATA_RAM226r }, \ 2149 { 0x0002178c, "CMIC_LEDUP1_DATA_RAM227", CMIC_LEDUP1_DATA_RAM227r }, \ 2150 { 0x00021790, "CMIC_LEDUP1_DATA_RAM228", CMIC_LEDUP1_DATA_RAM228r }, \ 2151 { 0x00021794, "CMIC_LEDUP1_DATA_RAM229", CMIC_LEDUP1_DATA_RAM229r }, \ 2152 { 0x00021798, "CMIC_LEDUP1_DATA_RAM230", CMIC_LEDUP1_DATA_RAM230r }, \ 2153 { 0x0002179c, "CMIC_LEDUP1_DATA_RAM231", CMIC_LEDUP1_DATA_RAM231r }, \ 2154 { 0x000217a0, "CMIC_LEDUP1_DATA_RAM232", CMIC_LEDUP1_DATA_RAM232r }, \ 2155 { 0x000217a4, "CMIC_LEDUP1_DATA_RAM233", CMIC_LEDUP1_DATA_RAM233r }, \ 2156 { 0x000217a8, "CMIC_LEDUP1_DATA_RAM234", CMIC_LEDUP1_DATA_RAM234r }, \ 2157 { 0x000217ac, "CMIC_LEDUP1_DATA_RAM235", CMIC_LEDUP1_DATA_RAM235r }, \ 2158 { 0x000217b0, "CMIC_LEDUP1_DATA_RAM236", CMIC_LEDUP1_DATA_RAM236r }, \ 2159 { 0x000217b4, "CMIC_LEDUP1_DATA_RAM237", CMIC_LEDUP1_DATA_RAM237r }, \ 2160 { 0x000217b8, "CMIC_LEDUP1_DATA_RAM238", CMIC_LEDUP1_DATA_RAM238r }, \ 2161 { 0x000217bc, "CMIC_LEDUP1_DATA_RAM239", CMIC_LEDUP1_DATA_RAM239r }, \ 2162 { 0x000217c0, "CMIC_LEDUP1_DATA_RAM240", CMIC_LEDUP1_DATA_RAM240r }, \ 2163 { 0x000217c4, "CMIC_LEDUP1_DATA_RAM241", CMIC_LEDUP1_DATA_RAM241r }, \ 2164 { 0x000217c8, "CMIC_LEDUP1_DATA_RAM242", CMIC_LEDUP1_DATA_RAM242r }, \ 2165 { 0x000217cc, "CMIC_LEDUP1_DATA_RAM243", CMIC_LEDUP1_DATA_RAM243r }, \ 2166 { 0x000217d0, "CMIC_LEDUP1_DATA_RAM244", CMIC_LEDUP1_DATA_RAM244r }, \ 2167 { 0x000217d4, "CMIC_LEDUP1_DATA_RAM245", CMIC_LEDUP1_DATA_RAM245r }, \ 2168 { 0x000217d8, "CMIC_LEDUP1_DATA_RAM246", CMIC_LEDUP1_DATA_RAM246r }, \ 2169 { 0x000217dc, "CMIC_LEDUP1_DATA_RAM247", CMIC_LEDUP1_DATA_RAM247r }, \ 2170 { 0x000217e0, "CMIC_LEDUP1_DATA_RAM248", CMIC_LEDUP1_DATA_RAM248r }, \ 2171 { 0x000217e4, "CMIC_LEDUP1_DATA_RAM249", CMIC_LEDUP1_DATA_RAM249r }, \ 2172 { 0x000217e8, "CMIC_LEDUP1_DATA_RAM250", CMIC_LEDUP1_DATA_RAM250r }, \ 2173 { 0x000217ec, "CMIC_LEDUP1_DATA_RAM251", CMIC_LEDUP1_DATA_RAM251r }, \ 2174 { 0x000217f0, "CMIC_LEDUP1_DATA_RAM252", CMIC_LEDUP1_DATA_RAM252r }, \ 2175 { 0x000217f4, "CMIC_LEDUP1_DATA_RAM253", CMIC_LEDUP1_DATA_RAM253r }, \ 2176 { 0x000217f8, "CMIC_LEDUP1_DATA_RAM254", CMIC_LEDUP1_DATA_RAM254r }, \ 2177 { 0x000217fc, "CMIC_LEDUP1_DATA_RAM255", CMIC_LEDUP1_DATA_RAM255r }, \ 2178 { 0x00021800, "CMIC_LEDUP1_PROGRAM_RAM0", CMIC_LEDUP1_PROGRAM_RAM0r }, \ 2179 { 0x00021800, "CMIC_LEDUP1_PROGRAM_RAM", CMIC_LEDUP1_PROGRAM_RAMr }, \ 2180 { 0x00021804, "CMIC_LEDUP1_PROGRAM_RAM1", CMIC_LEDUP1_PROGRAM_RAM1r }, \ 2181 { 0x00021808, "CMIC_LEDUP1_PROGRAM_RAM2", CMIC_LEDUP1_PROGRAM_RAM2r }, \ 2182 { 0x0002180c, "CMIC_LEDUP1_PROGRAM_RAM3", CMIC_LEDUP1_PROGRAM_RAM3r }, \ 2183 { 0x00021810, "CMIC_LEDUP1_PROGRAM_RAM4", CMIC_LEDUP1_PROGRAM_RAM4r }, \ 2184 { 0x00021814, "CMIC_LEDUP1_PROGRAM_RAM5", CMIC_LEDUP1_PROGRAM_RAM5r }, \ 2185 { 0x00021818, "CMIC_LEDUP1_PROGRAM_RAM6", CMIC_LEDUP1_PROGRAM_RAM6r }, \ 2186 { 0x0002181c, "CMIC_LEDUP1_PROGRAM_RAM7", CMIC_LEDUP1_PROGRAM_RAM7r }, \ 2187 { 0x00021820, "CMIC_LEDUP1_PROGRAM_RAM8", CMIC_LEDUP1_PROGRAM_RAM8r }, \ 2188 { 0x00021824, "CMIC_LEDUP1_PROGRAM_RAM9", CMIC_LEDUP1_PROGRAM_RAM9r }, \ 2189 { 0x00021828, "CMIC_LEDUP1_PROGRAM_RAM10", CMIC_LEDUP1_PROGRAM_RAM10r }, \ 2190 { 0x0002182c, "CMIC_LEDUP1_PROGRAM_RAM11", CMIC_LEDUP1_PROGRAM_RAM11r }, \ 2191 { 0x00021830, "CMIC_LEDUP1_PROGRAM_RAM12", CMIC_LEDUP1_PROGRAM_RAM12r }, \ 2192 { 0x00021834, "CMIC_LEDUP1_PROGRAM_RAM13", CMIC_LEDUP1_PROGRAM_RAM13r }, \ 2193 { 0x00021838, "CMIC_LEDUP1_PROGRAM_RAM14", CMIC_LEDUP1_PROGRAM_RAM14r }, \ 2194 { 0x0002183c, "CMIC_LEDUP1_PROGRAM_RAM15", CMIC_LEDUP1_PROGRAM_RAM15r }, \ 2195 { 0x00021840, "CMIC_LEDUP1_PROGRAM_RAM16", CMIC_LEDUP1_PROGRAM_RAM16r }, \ 2196 { 0x00021844, "CMIC_LEDUP1_PROGRAM_RAM17", CMIC_LEDUP1_PROGRAM_RAM17r }, \ 2197 { 0x00021848, "CMIC_LEDUP1_PROGRAM_RAM18", CMIC_LEDUP1_PROGRAM_RAM18r }, \ 2198 { 0x0002184c, "CMIC_LEDUP1_PROGRAM_RAM19", CMIC_LEDUP1_PROGRAM_RAM19r }, \ 2199 { 0x00021850, "CMIC_LEDUP1_PROGRAM_RAM20", CMIC_LEDUP1_PROGRAM_RAM20r }, \ 2200 { 0x00021854, "CMIC_LEDUP1_PROGRAM_RAM21", CMIC_LEDUP1_PROGRAM_RAM21r }, \ 2201 { 0x00021858, "CMIC_LEDUP1_PROGRAM_RAM22", CMIC_LEDUP1_PROGRAM_RAM22r }, \ 2202 { 0x0002185c, "CMIC_LEDUP1_PROGRAM_RAM23", CMIC_LEDUP1_PROGRAM_RAM23r }, \ 2203 { 0x00021860, "CMIC_LEDUP1_PROGRAM_RAM24", CMIC_LEDUP1_PROGRAM_RAM24r }, \ 2204 { 0x00021864, "CMIC_LEDUP1_PROGRAM_RAM25", CMIC_LEDUP1_PROGRAM_RAM25r }, \ 2205 { 0x00021868, "CMIC_LEDUP1_PROGRAM_RAM26", CMIC_LEDUP1_PROGRAM_RAM26r }, \ 2206 { 0x0002186c, "CMIC_LEDUP1_PROGRAM_RAM27", CMIC_LEDUP1_PROGRAM_RAM27r }, \ 2207 { 0x00021870, "CMIC_LEDUP1_PROGRAM_RAM28", CMIC_LEDUP1_PROGRAM_RAM28r }, \ 2208 { 0x00021874, "CMIC_LEDUP1_PROGRAM_RAM29", CMIC_LEDUP1_PROGRAM_RAM29r }, \ 2209 { 0x00021878, "CMIC_LEDUP1_PROGRAM_RAM30", CMIC_LEDUP1_PROGRAM_RAM30r }, \ 2210 { 0x0002187c, "CMIC_LEDUP1_PROGRAM_RAM31", CMIC_LEDUP1_PROGRAM_RAM31r }, \ 2211 { 0x00021880, "CMIC_LEDUP1_PROGRAM_RAM32", CMIC_LEDUP1_PROGRAM_RAM32r }, \ 2212 { 0x00021884, "CMIC_LEDUP1_PROGRAM_RAM33", CMIC_LEDUP1_PROGRAM_RAM33r }, \ 2213 { 0x00021888, "CMIC_LEDUP1_PROGRAM_RAM34", CMIC_LEDUP1_PROGRAM_RAM34r }, \ 2214 { 0x0002188c, "CMIC_LEDUP1_PROGRAM_RAM35", CMIC_LEDUP1_PROGRAM_RAM35r }, \ 2215 { 0x00021890, "CMIC_LEDUP1_PROGRAM_RAM36", CMIC_LEDUP1_PROGRAM_RAM36r }, \ 2216 { 0x00021894, "CMIC_LEDUP1_PROGRAM_RAM37", CMIC_LEDUP1_PROGRAM_RAM37r }, \ 2217 { 0x00021898, "CMIC_LEDUP1_PROGRAM_RAM38", CMIC_LEDUP1_PROGRAM_RAM38r }, \ 2218 { 0x0002189c, "CMIC_LEDUP1_PROGRAM_RAM39", CMIC_LEDUP1_PROGRAM_RAM39r }, \ 2219 { 0x000218a0, "CMIC_LEDUP1_PROGRAM_RAM40", CMIC_LEDUP1_PROGRAM_RAM40r }, \ 2220 { 0x000218a4, "CMIC_LEDUP1_PROGRAM_RAM41", CMIC_LEDUP1_PROGRAM_RAM41r }, \ 2221 { 0x000218a8, "CMIC_LEDUP1_PROGRAM_RAM42", CMIC_LEDUP1_PROGRAM_RAM42r }, \ 2222 { 0x000218ac, "CMIC_LEDUP1_PROGRAM_RAM43", CMIC_LEDUP1_PROGRAM_RAM43r }, \ 2223 { 0x000218b0, "CMIC_LEDUP1_PROGRAM_RAM44", CMIC_LEDUP1_PROGRAM_RAM44r }, \ 2224 { 0x000218b4, "CMIC_LEDUP1_PROGRAM_RAM45", CMIC_LEDUP1_PROGRAM_RAM45r }, \ 2225 { 0x000218b8, "CMIC_LEDUP1_PROGRAM_RAM46", CMIC_LEDUP1_PROGRAM_RAM46r }, \ 2226 { 0x000218bc, "CMIC_LEDUP1_PROGRAM_RAM47", CMIC_LEDUP1_PROGRAM_RAM47r }, \ 2227 { 0x000218c0, "CMIC_LEDUP1_PROGRAM_RAM48", CMIC_LEDUP1_PROGRAM_RAM48r }, \ 2228 { 0x000218c4, "CMIC_LEDUP1_PROGRAM_RAM49", CMIC_LEDUP1_PROGRAM_RAM49r }, \ 2229 { 0x000218c8, "CMIC_LEDUP1_PROGRAM_RAM50", CMIC_LEDUP1_PROGRAM_RAM50r }, \ 2230 { 0x000218cc, "CMIC_LEDUP1_PROGRAM_RAM51", CMIC_LEDUP1_PROGRAM_RAM51r }, \ 2231 { 0x000218d0, "CMIC_LEDUP1_PROGRAM_RAM52", CMIC_LEDUP1_PROGRAM_RAM52r }, \ 2232 { 0x000218d4, "CMIC_LEDUP1_PROGRAM_RAM53", CMIC_LEDUP1_PROGRAM_RAM53r }, \ 2233 { 0x000218d8, "CMIC_LEDUP1_PROGRAM_RAM54", CMIC_LEDUP1_PROGRAM_RAM54r }, \ 2234 { 0x000218dc, "CMIC_LEDUP1_PROGRAM_RAM55", CMIC_LEDUP1_PROGRAM_RAM55r }, \ 2235 { 0x000218e0, "CMIC_LEDUP1_PROGRAM_RAM56", CMIC_LEDUP1_PROGRAM_RAM56r }, \ 2236 { 0x000218e4, "CMIC_LEDUP1_PROGRAM_RAM57", CMIC_LEDUP1_PROGRAM_RAM57r }, \ 2237 { 0x000218e8, "CMIC_LEDUP1_PROGRAM_RAM58", CMIC_LEDUP1_PROGRAM_RAM58r }, \ 2238 { 0x000218ec, "CMIC_LEDUP1_PROGRAM_RAM59", CMIC_LEDUP1_PROGRAM_RAM59r }, \ 2239 { 0x000218f0, "CMIC_LEDUP1_PROGRAM_RAM60", CMIC_LEDUP1_PROGRAM_RAM60r }, \ 2240 { 0x000218f4, "CMIC_LEDUP1_PROGRAM_RAM61", CMIC_LEDUP1_PROGRAM_RAM61r }, \ 2241 { 0x000218f8, "CMIC_LEDUP1_PROGRAM_RAM62", CMIC_LEDUP1_PROGRAM_RAM62r }, \ 2242 { 0x000218fc, "CMIC_LEDUP1_PROGRAM_RAM63", CMIC_LEDUP1_PROGRAM_RAM63r }, \ 2243 { 0x00021900, "CMIC_LEDUP1_PROGRAM_RAM64", CMIC_LEDUP1_PROGRAM_RAM64r }, \ 2244 { 0x00021904, "CMIC_LEDUP1_PROGRAM_RAM65", CMIC_LEDUP1_PROGRAM_RAM65r }, \ 2245 { 0x00021908, "CMIC_LEDUP1_PROGRAM_RAM66", CMIC_LEDUP1_PROGRAM_RAM66r }, \ 2246 { 0x0002190c, "CMIC_LEDUP1_PROGRAM_RAM67", CMIC_LEDUP1_PROGRAM_RAM67r }, \ 2247 { 0x00021910, "CMIC_LEDUP1_PROGRAM_RAM68", CMIC_LEDUP1_PROGRAM_RAM68r }, \ 2248 { 0x00021914, "CMIC_LEDUP1_PROGRAM_RAM69", CMIC_LEDUP1_PROGRAM_RAM69r }, \ 2249 { 0x00021918, "CMIC_LEDUP1_PROGRAM_RAM70", CMIC_LEDUP1_PROGRAM_RAM70r }, \ 2250 { 0x0002191c, "CMIC_LEDUP1_PROGRAM_RAM71", CMIC_LEDUP1_PROGRAM_RAM71r }, \ 2251 { 0x00021920, "CMIC_LEDUP1_PROGRAM_RAM72", CMIC_LEDUP1_PROGRAM_RAM72r }, \ 2252 { 0x00021924, "CMIC_LEDUP1_PROGRAM_RAM73", CMIC_LEDUP1_PROGRAM_RAM73r }, \ 2253 { 0x00021928, "CMIC_LEDUP1_PROGRAM_RAM74", CMIC_LEDUP1_PROGRAM_RAM74r }, \ 2254 { 0x0002192c, "CMIC_LEDUP1_PROGRAM_RAM75", CMIC_LEDUP1_PROGRAM_RAM75r }, \ 2255 { 0x00021930, "CMIC_LEDUP1_PROGRAM_RAM76", CMIC_LEDUP1_PROGRAM_RAM76r }, \ 2256 { 0x00021934, "CMIC_LEDUP1_PROGRAM_RAM77", CMIC_LEDUP1_PROGRAM_RAM77r }, \ 2257 { 0x00021938, "CMIC_LEDUP1_PROGRAM_RAM78", CMIC_LEDUP1_PROGRAM_RAM78r }, \ 2258 { 0x0002193c, "CMIC_LEDUP1_PROGRAM_RAM79", CMIC_LEDUP1_PROGRAM_RAM79r }, \ 2259 { 0x00021940, "CMIC_LEDUP1_PROGRAM_RAM80", CMIC_LEDUP1_PROGRAM_RAM80r }, \ 2260 { 0x00021944, "CMIC_LEDUP1_PROGRAM_RAM81", CMIC_LEDUP1_PROGRAM_RAM81r }, \ 2261 { 0x00021948, "CMIC_LEDUP1_PROGRAM_RAM82", CMIC_LEDUP1_PROGRAM_RAM82r }, \ 2262 { 0x0002194c, "CMIC_LEDUP1_PROGRAM_RAM83", CMIC_LEDUP1_PROGRAM_RAM83r }, \ 2263 { 0x00021950, "CMIC_LEDUP1_PROGRAM_RAM84", CMIC_LEDUP1_PROGRAM_RAM84r }, \ 2264 { 0x00021954, "CMIC_LEDUP1_PROGRAM_RAM85", CMIC_LEDUP1_PROGRAM_RAM85r }, \ 2265 { 0x00021958, "CMIC_LEDUP1_PROGRAM_RAM86", CMIC_LEDUP1_PROGRAM_RAM86r }, \ 2266 { 0x0002195c, "CMIC_LEDUP1_PROGRAM_RAM87", CMIC_LEDUP1_PROGRAM_RAM87r }, \ 2267 { 0x00021960, "CMIC_LEDUP1_PROGRAM_RAM88", CMIC_LEDUP1_PROGRAM_RAM88r }, \ 2268 { 0x00021964, "CMIC_LEDUP1_PROGRAM_RAM89", CMIC_LEDUP1_PROGRAM_RAM89r }, \ 2269 { 0x00021968, "CMIC_LEDUP1_PROGRAM_RAM90", CMIC_LEDUP1_PROGRAM_RAM90r }, \ 2270 { 0x0002196c, "CMIC_LEDUP1_PROGRAM_RAM91", CMIC_LEDUP1_PROGRAM_RAM91r }, \ 2271 { 0x00021970, "CMIC_LEDUP1_PROGRAM_RAM92", CMIC_LEDUP1_PROGRAM_RAM92r }, \ 2272 { 0x00021974, "CMIC_LEDUP1_PROGRAM_RAM93", CMIC_LEDUP1_PROGRAM_RAM93r }, \ 2273 { 0x00021978, "CMIC_LEDUP1_PROGRAM_RAM94", CMIC_LEDUP1_PROGRAM_RAM94r }, \ 2274 { 0x0002197c, "CMIC_LEDUP1_PROGRAM_RAM95", CMIC_LEDUP1_PROGRAM_RAM95r }, \ 2275 { 0x00021980, "CMIC_LEDUP1_PROGRAM_RAM96", CMIC_LEDUP1_PROGRAM_RAM96r }, \ 2276 { 0x00021984, "CMIC_LEDUP1_PROGRAM_RAM97", CMIC_LEDUP1_PROGRAM_RAM97r }, \ 2277 { 0x00021988, "CMIC_LEDUP1_PROGRAM_RAM98", CMIC_LEDUP1_PROGRAM_RAM98r }, \ 2278 { 0x0002198c, "CMIC_LEDUP1_PROGRAM_RAM99", CMIC_LEDUP1_PROGRAM_RAM99r }, \ 2279 { 0x00021990, "CMIC_LEDUP1_PROGRAM_RAM100", CMIC_LEDUP1_PROGRAM_RAM100r }, \ 2280 { 0x00021994, "CMIC_LEDUP1_PROGRAM_RAM101", CMIC_LEDUP1_PROGRAM_RAM101r }, \ 2281 { 0x00021998, "CMIC_LEDUP1_PROGRAM_RAM102", CMIC_LEDUP1_PROGRAM_RAM102r }, \ 2282 { 0x0002199c, "CMIC_LEDUP1_PROGRAM_RAM103", CMIC_LEDUP1_PROGRAM_RAM103r }, \ 2283 { 0x000219a0, "CMIC_LEDUP1_PROGRAM_RAM104", CMIC_LEDUP1_PROGRAM_RAM104r }, \ 2284 { 0x000219a4, "CMIC_LEDUP1_PROGRAM_RAM105", CMIC_LEDUP1_PROGRAM_RAM105r }, \ 2285 { 0x000219a8, "CMIC_LEDUP1_PROGRAM_RAM106", CMIC_LEDUP1_PROGRAM_RAM106r }, \ 2286 { 0x000219ac, "CMIC_LEDUP1_PROGRAM_RAM107", CMIC_LEDUP1_PROGRAM_RAM107r }, \ 2287 { 0x000219b0, "CMIC_LEDUP1_PROGRAM_RAM108", CMIC_LEDUP1_PROGRAM_RAM108r }, \ 2288 { 0x000219b4, "CMIC_LEDUP1_PROGRAM_RAM109", CMIC_LEDUP1_PROGRAM_RAM109r }, \ 2289 { 0x000219b8, "CMIC_LEDUP1_PROGRAM_RAM110", CMIC_LEDUP1_PROGRAM_RAM110r }, \ 2290 { 0x000219bc, "CMIC_LEDUP1_PROGRAM_RAM111", CMIC_LEDUP1_PROGRAM_RAM111r }, \ 2291 { 0x000219c0, "CMIC_LEDUP1_PROGRAM_RAM112", CMIC_LEDUP1_PROGRAM_RAM112r }, \ 2292 { 0x000219c4, "CMIC_LEDUP1_PROGRAM_RAM113", CMIC_LEDUP1_PROGRAM_RAM113r }, \ 2293 { 0x000219c8, "CMIC_LEDUP1_PROGRAM_RAM114", CMIC_LEDUP1_PROGRAM_RAM114r }, \ 2294 { 0x000219cc, "CMIC_LEDUP1_PROGRAM_RAM115", CMIC_LEDUP1_PROGRAM_RAM115r }, \ 2295 { 0x000219d0, "CMIC_LEDUP1_PROGRAM_RAM116", CMIC_LEDUP1_PROGRAM_RAM116r }, \ 2296 { 0x000219d4, "CMIC_LEDUP1_PROGRAM_RAM117", CMIC_LEDUP1_PROGRAM_RAM117r }, \ 2297 { 0x000219d8, "CMIC_LEDUP1_PROGRAM_RAM118", CMIC_LEDUP1_PROGRAM_RAM118r }, \ 2298 { 0x000219dc, "CMIC_LEDUP1_PROGRAM_RAM119", CMIC_LEDUP1_PROGRAM_RAM119r }, \ 2299 { 0x000219e0, "CMIC_LEDUP1_PROGRAM_RAM120", CMIC_LEDUP1_PROGRAM_RAM120r }, \ 2300 { 0x000219e4, "CMIC_LEDUP1_PROGRAM_RAM121", CMIC_LEDUP1_PROGRAM_RAM121r }, \ 2301 { 0x000219e8, "CMIC_LEDUP1_PROGRAM_RAM122", CMIC_LEDUP1_PROGRAM_RAM122r }, \ 2302 { 0x000219ec, "CMIC_LEDUP1_PROGRAM_RAM123", CMIC_LEDUP1_PROGRAM_RAM123r }, \ 2303 { 0x000219f0, "CMIC_LEDUP1_PROGRAM_RAM124", CMIC_LEDUP1_PROGRAM_RAM124r }, \ 2304 { 0x000219f4, "CMIC_LEDUP1_PROGRAM_RAM125", CMIC_LEDUP1_PROGRAM_RAM125r }, \ 2305 { 0x000219f8, "CMIC_LEDUP1_PROGRAM_RAM126", CMIC_LEDUP1_PROGRAM_RAM126r }, \ 2306 { 0x000219fc, "CMIC_LEDUP1_PROGRAM_RAM127", CMIC_LEDUP1_PROGRAM_RAM127r }, \ 2307 { 0x00021a00, "CMIC_LEDUP1_PROGRAM_RAM128", CMIC_LEDUP1_PROGRAM_RAM128r }, \ 2308 { 0x00021a04, "CMIC_LEDUP1_PROGRAM_RAM129", CMIC_LEDUP1_PROGRAM_RAM129r }, \ 2309 { 0x00021a08, "CMIC_LEDUP1_PROGRAM_RAM130", CMIC_LEDUP1_PROGRAM_RAM130r }, \ 2310 { 0x00021a0c, "CMIC_LEDUP1_PROGRAM_RAM131", CMIC_LEDUP1_PROGRAM_RAM131r }, \ 2311 { 0x00021a10, "CMIC_LEDUP1_PROGRAM_RAM132", CMIC_LEDUP1_PROGRAM_RAM132r }, \ 2312 { 0x00021a14, "CMIC_LEDUP1_PROGRAM_RAM133", CMIC_LEDUP1_PROGRAM_RAM133r }, \ 2313 { 0x00021a18, "CMIC_LEDUP1_PROGRAM_RAM134", CMIC_LEDUP1_PROGRAM_RAM134r }, \ 2314 { 0x00021a1c, "CMIC_LEDUP1_PROGRAM_RAM135", CMIC_LEDUP1_PROGRAM_RAM135r }, \ 2315 { 0x00021a20, "CMIC_LEDUP1_PROGRAM_RAM136", CMIC_LEDUP1_PROGRAM_RAM136r }, \ 2316 { 0x00021a24, "CMIC_LEDUP1_PROGRAM_RAM137", CMIC_LEDUP1_PROGRAM_RAM137r }, \ 2317 { 0x00021a28, "CMIC_LEDUP1_PROGRAM_RAM138", CMIC_LEDUP1_PROGRAM_RAM138r }, \ 2318 { 0x00021a2c, "CMIC_LEDUP1_PROGRAM_RAM139", CMIC_LEDUP1_PROGRAM_RAM139r }, \ 2319 { 0x00021a30, "CMIC_LEDUP1_PROGRAM_RAM140", CMIC_LEDUP1_PROGRAM_RAM140r }, \ 2320 { 0x00021a34, "CMIC_LEDUP1_PROGRAM_RAM141", CMIC_LEDUP1_PROGRAM_RAM141r }, \ 2321 { 0x00021a38, "CMIC_LEDUP1_PROGRAM_RAM142", CMIC_LEDUP1_PROGRAM_RAM142r }, \ 2322 { 0x00021a3c, "CMIC_LEDUP1_PROGRAM_RAM143", CMIC_LEDUP1_PROGRAM_RAM143r }, \ 2323 { 0x00021a40, "CMIC_LEDUP1_PROGRAM_RAM144", CMIC_LEDUP1_PROGRAM_RAM144r }, \ 2324 { 0x00021a44, "CMIC_LEDUP1_PROGRAM_RAM145", CMIC_LEDUP1_PROGRAM_RAM145r }, \ 2325 { 0x00021a48, "CMIC_LEDUP1_PROGRAM_RAM146", CMIC_LEDUP1_PROGRAM_RAM146r }, \ 2326 { 0x00021a4c, "CMIC_LEDUP1_PROGRAM_RAM147", CMIC_LEDUP1_PROGRAM_RAM147r }, \ 2327 { 0x00021a50, "CMIC_LEDUP1_PROGRAM_RAM148", CMIC_LEDUP1_PROGRAM_RAM148r }, \ 2328 { 0x00021a54, "CMIC_LEDUP1_PROGRAM_RAM149", CMIC_LEDUP1_PROGRAM_RAM149r }, \ 2329 { 0x00021a58, "CMIC_LEDUP1_PROGRAM_RAM150", CMIC_LEDUP1_PROGRAM_RAM150r }, \ 2330 { 0x00021a5c, "CMIC_LEDUP1_PROGRAM_RAM151", CMIC_LEDUP1_PROGRAM_RAM151r }, \ 2331 { 0x00021a60, "CMIC_LEDUP1_PROGRAM_RAM152", CMIC_LEDUP1_PROGRAM_RAM152r }, \ 2332 { 0x00021a64, "CMIC_LEDUP1_PROGRAM_RAM153", CMIC_LEDUP1_PROGRAM_RAM153r }, \ 2333 { 0x00021a68, "CMIC_LEDUP1_PROGRAM_RAM154", CMIC_LEDUP1_PROGRAM_RAM154r }, \ 2334 { 0x00021a6c, "CMIC_LEDUP1_PROGRAM_RAM155", CMIC_LEDUP1_PROGRAM_RAM155r }, \ 2335 { 0x00021a70, "CMIC_LEDUP1_PROGRAM_RAM156", CMIC_LEDUP1_PROGRAM_RAM156r }, \ 2336 { 0x00021a74, "CMIC_LEDUP1_PROGRAM_RAM157", CMIC_LEDUP1_PROGRAM_RAM157r }, \ 2337 { 0x00021a78, "CMIC_LEDUP1_PROGRAM_RAM158", CMIC_LEDUP1_PROGRAM_RAM158r }, \ 2338 { 0x00021a7c, "CMIC_LEDUP1_PROGRAM_RAM159", CMIC_LEDUP1_PROGRAM_RAM159r }, \ 2339 { 0x00021a80, "CMIC_LEDUP1_PROGRAM_RAM160", CMIC_LEDUP1_PROGRAM_RAM160r }, \ 2340 { 0x00021a84, "CMIC_LEDUP1_PROGRAM_RAM161", CMIC_LEDUP1_PROGRAM_RAM161r }, \ 2341 { 0x00021a88, "CMIC_LEDUP1_PROGRAM_RAM162", CMIC_LEDUP1_PROGRAM_RAM162r }, \ 2342 { 0x00021a8c, "CMIC_LEDUP1_PROGRAM_RAM163", CMIC_LEDUP1_PROGRAM_RAM163r }, \ 2343 { 0x00021a90, "CMIC_LEDUP1_PROGRAM_RAM164", CMIC_LEDUP1_PROGRAM_RAM164r }, \ 2344 { 0x00021a94, "CMIC_LEDUP1_PROGRAM_RAM165", CMIC_LEDUP1_PROGRAM_RAM165r }, \ 2345 { 0x00021a98, "CMIC_LEDUP1_PROGRAM_RAM166", CMIC_LEDUP1_PROGRAM_RAM166r }, \ 2346 { 0x00021a9c, "CMIC_LEDUP1_PROGRAM_RAM167", CMIC_LEDUP1_PROGRAM_RAM167r }, \ 2347 { 0x00021aa0, "CMIC_LEDUP1_PROGRAM_RAM168", CMIC_LEDUP1_PROGRAM_RAM168r }, \ 2348 { 0x00021aa4, "CMIC_LEDUP1_PROGRAM_RAM169", CMIC_LEDUP1_PROGRAM_RAM169r }, \ 2349 { 0x00021aa8, "CMIC_LEDUP1_PROGRAM_RAM170", CMIC_LEDUP1_PROGRAM_RAM170r }, \ 2350 { 0x00021aac, "CMIC_LEDUP1_PROGRAM_RAM171", CMIC_LEDUP1_PROGRAM_RAM171r }, \ 2351 { 0x00021ab0, "CMIC_LEDUP1_PROGRAM_RAM172", CMIC_LEDUP1_PROGRAM_RAM172r }, \ 2352 { 0x00021ab4, "CMIC_LEDUP1_PROGRAM_RAM173", CMIC_LEDUP1_PROGRAM_RAM173r }, \ 2353 { 0x00021ab8, "CMIC_LEDUP1_PROGRAM_RAM174", CMIC_LEDUP1_PROGRAM_RAM174r }, \ 2354 { 0x00021abc, "CMIC_LEDUP1_PROGRAM_RAM175", CMIC_LEDUP1_PROGRAM_RAM175r }, \ 2355 { 0x00021ac0, "CMIC_LEDUP1_PROGRAM_RAM176", CMIC_LEDUP1_PROGRAM_RAM176r }, \ 2356 { 0x00021ac4, "CMIC_LEDUP1_PROGRAM_RAM177", CMIC_LEDUP1_PROGRAM_RAM177r }, \ 2357 { 0x00021ac8, "CMIC_LEDUP1_PROGRAM_RAM178", CMIC_LEDUP1_PROGRAM_RAM178r }, \ 2358 { 0x00021acc, "CMIC_LEDUP1_PROGRAM_RAM179", CMIC_LEDUP1_PROGRAM_RAM179r }, \ 2359 { 0x00021ad0, "CMIC_LEDUP1_PROGRAM_RAM180", CMIC_LEDUP1_PROGRAM_RAM180r }, \ 2360 { 0x00021ad4, "CMIC_LEDUP1_PROGRAM_RAM181", CMIC_LEDUP1_PROGRAM_RAM181r }, \ 2361 { 0x00021ad8, "CMIC_LEDUP1_PROGRAM_RAM182", CMIC_LEDUP1_PROGRAM_RAM182r }, \ 2362 { 0x00021adc, "CMIC_LEDUP1_PROGRAM_RAM183", CMIC_LEDUP1_PROGRAM_RAM183r }, \ 2363 { 0x00021ae0, "CMIC_LEDUP1_PROGRAM_RAM184", CMIC_LEDUP1_PROGRAM_RAM184r }, \ 2364 { 0x00021ae4, "CMIC_LEDUP1_PROGRAM_RAM185", CMIC_LEDUP1_PROGRAM_RAM185r }, \ 2365 { 0x00021ae8, "CMIC_LEDUP1_PROGRAM_RAM186", CMIC_LEDUP1_PROGRAM_RAM186r }, \ 2366 { 0x00021aec, "CMIC_LEDUP1_PROGRAM_RAM187", CMIC_LEDUP1_PROGRAM_RAM187r }, \ 2367 { 0x00021af0, "CMIC_LEDUP1_PROGRAM_RAM188", CMIC_LEDUP1_PROGRAM_RAM188r }, \ 2368 { 0x00021af4, "CMIC_LEDUP1_PROGRAM_RAM189", CMIC_LEDUP1_PROGRAM_RAM189r }, \ 2369 { 0x00021af8, "CMIC_LEDUP1_PROGRAM_RAM190", CMIC_LEDUP1_PROGRAM_RAM190r }, \ 2370 { 0x00021afc, "CMIC_LEDUP1_PROGRAM_RAM191", CMIC_LEDUP1_PROGRAM_RAM191r }, \ 2371 { 0x00021b00, "CMIC_LEDUP1_PROGRAM_RAM192", CMIC_LEDUP1_PROGRAM_RAM192r }, \ 2372 { 0x00021b04, "CMIC_LEDUP1_PROGRAM_RAM193", CMIC_LEDUP1_PROGRAM_RAM193r }, \ 2373 { 0x00021b08, "CMIC_LEDUP1_PROGRAM_RAM194", CMIC_LEDUP1_PROGRAM_RAM194r }, \ 2374 { 0x00021b0c, "CMIC_LEDUP1_PROGRAM_RAM195", CMIC_LEDUP1_PROGRAM_RAM195r }, \ 2375 { 0x00021b10, "CMIC_LEDUP1_PROGRAM_RAM196", CMIC_LEDUP1_PROGRAM_RAM196r }, \ 2376 { 0x00021b14, "CMIC_LEDUP1_PROGRAM_RAM197", CMIC_LEDUP1_PROGRAM_RAM197r }, \ 2377 { 0x00021b18, "CMIC_LEDUP1_PROGRAM_RAM198", CMIC_LEDUP1_PROGRAM_RAM198r }, \ 2378 { 0x00021b1c, "CMIC_LEDUP1_PROGRAM_RAM199", CMIC_LEDUP1_PROGRAM_RAM199r }, \ 2379 { 0x00021b20, "CMIC_LEDUP1_PROGRAM_RAM200", CMIC_LEDUP1_PROGRAM_RAM200r }, \ 2380 { 0x00021b24, "CMIC_LEDUP1_PROGRAM_RAM201", CMIC_LEDUP1_PROGRAM_RAM201r }, \ 2381 { 0x00021b28, "CMIC_LEDUP1_PROGRAM_RAM202", CMIC_LEDUP1_PROGRAM_RAM202r }, \ 2382 { 0x00021b2c, "CMIC_LEDUP1_PROGRAM_RAM203", CMIC_LEDUP1_PROGRAM_RAM203r }, \ 2383 { 0x00021b30, "CMIC_LEDUP1_PROGRAM_RAM204", CMIC_LEDUP1_PROGRAM_RAM204r }, \ 2384 { 0x00021b34, "CMIC_LEDUP1_PROGRAM_RAM205", CMIC_LEDUP1_PROGRAM_RAM205r }, \ 2385 { 0x00021b38, "CMIC_LEDUP1_PROGRAM_RAM206", CMIC_LEDUP1_PROGRAM_RAM206r }, \ 2386 { 0x00021b3c, "CMIC_LEDUP1_PROGRAM_RAM207", CMIC_LEDUP1_PROGRAM_RAM207r }, \ 2387 { 0x00021b40, "CMIC_LEDUP1_PROGRAM_RAM208", CMIC_LEDUP1_PROGRAM_RAM208r }, \ 2388 { 0x00021b44, "CMIC_LEDUP1_PROGRAM_RAM209", CMIC_LEDUP1_PROGRAM_RAM209r }, \ 2389 { 0x00021b48, "CMIC_LEDUP1_PROGRAM_RAM210", CMIC_LEDUP1_PROGRAM_RAM210r }, \ 2390 { 0x00021b4c, "CMIC_LEDUP1_PROGRAM_RAM211", CMIC_LEDUP1_PROGRAM_RAM211r }, \ 2391 { 0x00021b50, "CMIC_LEDUP1_PROGRAM_RAM212", CMIC_LEDUP1_PROGRAM_RAM212r }, \ 2392 { 0x00021b54, "CMIC_LEDUP1_PROGRAM_RAM213", CMIC_LEDUP1_PROGRAM_RAM213r }, \ 2393 { 0x00021b58, "CMIC_LEDUP1_PROGRAM_RAM214", CMIC_LEDUP1_PROGRAM_RAM214r }, \ 2394 { 0x00021b5c, "CMIC_LEDUP1_PROGRAM_RAM215", CMIC_LEDUP1_PROGRAM_RAM215r }, \ 2395 { 0x00021b60, "CMIC_LEDUP1_PROGRAM_RAM216", CMIC_LEDUP1_PROGRAM_RAM216r }, \ 2396 { 0x00021b64, "CMIC_LEDUP1_PROGRAM_RAM217", CMIC_LEDUP1_PROGRAM_RAM217r }, \ 2397 { 0x00021b68, "CMIC_LEDUP1_PROGRAM_RAM218", CMIC_LEDUP1_PROGRAM_RAM218r }, \ 2398 { 0x00021b6c, "CMIC_LEDUP1_PROGRAM_RAM219", CMIC_LEDUP1_PROGRAM_RAM219r }, \ 2399 { 0x00021b70, "CMIC_LEDUP1_PROGRAM_RAM220", CMIC_LEDUP1_PROGRAM_RAM220r }, \ 2400 { 0x00021b74, "CMIC_LEDUP1_PROGRAM_RAM221", CMIC_LEDUP1_PROGRAM_RAM221r }, \ 2401 { 0x00021b78, "CMIC_LEDUP1_PROGRAM_RAM222", CMIC_LEDUP1_PROGRAM_RAM222r }, \ 2402 { 0x00021b7c, "CMIC_LEDUP1_PROGRAM_RAM223", CMIC_LEDUP1_PROGRAM_RAM223r }, \ 2403 { 0x00021b80, "CMIC_LEDUP1_PROGRAM_RAM224", CMIC_LEDUP1_PROGRAM_RAM224r }, \ 2404 { 0x00021b84, "CMIC_LEDUP1_PROGRAM_RAM225", CMIC_LEDUP1_PROGRAM_RAM225r }, \ 2405 { 0x00021b88, "CMIC_LEDUP1_PROGRAM_RAM226", CMIC_LEDUP1_PROGRAM_RAM226r }, \ 2406 { 0x00021b8c, "CMIC_LEDUP1_PROGRAM_RAM227", CMIC_LEDUP1_PROGRAM_RAM227r }, \ 2407 { 0x00021b90, "CMIC_LEDUP1_PROGRAM_RAM228", CMIC_LEDUP1_PROGRAM_RAM228r }, \ 2408 { 0x00021b94, "CMIC_LEDUP1_PROGRAM_RAM229", CMIC_LEDUP1_PROGRAM_RAM229r }, \ 2409 { 0x00021b98, "CMIC_LEDUP1_PROGRAM_RAM230", CMIC_LEDUP1_PROGRAM_RAM230r }, \ 2410 { 0x00021b9c, "CMIC_LEDUP1_PROGRAM_RAM231", CMIC_LEDUP1_PROGRAM_RAM231r }, \ 2411 { 0x00021ba0, "CMIC_LEDUP1_PROGRAM_RAM232", CMIC_LEDUP1_PROGRAM_RAM232r }, \ 2412 { 0x00021ba4, "CMIC_LEDUP1_PROGRAM_RAM233", CMIC_LEDUP1_PROGRAM_RAM233r }, \ 2413 { 0x00021ba8, "CMIC_LEDUP1_PROGRAM_RAM234", CMIC_LEDUP1_PROGRAM_RAM234r }, \ 2414 { 0x00021bac, "CMIC_LEDUP1_PROGRAM_RAM235", CMIC_LEDUP1_PROGRAM_RAM235r }, \ 2415 { 0x00021bb0, "CMIC_LEDUP1_PROGRAM_RAM236", CMIC_LEDUP1_PROGRAM_RAM236r }, \ 2416 { 0x00021bb4, "CMIC_LEDUP1_PROGRAM_RAM237", CMIC_LEDUP1_PROGRAM_RAM237r }, \ 2417 { 0x00021bb8, "CMIC_LEDUP1_PROGRAM_RAM238", CMIC_LEDUP1_PROGRAM_RAM238r }, \ 2418 { 0x00021bbc, "CMIC_LEDUP1_PROGRAM_RAM239", CMIC_LEDUP1_PROGRAM_RAM239r }, \ 2419 { 0x00021bc0, "CMIC_LEDUP1_PROGRAM_RAM240", CMIC_LEDUP1_PROGRAM_RAM240r }, \ 2420 { 0x00021bc4, "CMIC_LEDUP1_PROGRAM_RAM241", CMIC_LEDUP1_PROGRAM_RAM241r }, \ 2421 { 0x00021bc8, "CMIC_LEDUP1_PROGRAM_RAM242", CMIC_LEDUP1_PROGRAM_RAM242r }, \ 2422 { 0x00021bcc, "CMIC_LEDUP1_PROGRAM_RAM243", CMIC_LEDUP1_PROGRAM_RAM243r }, \ 2423 { 0x00021bd0, "CMIC_LEDUP1_PROGRAM_RAM244", CMIC_LEDUP1_PROGRAM_RAM244r }, \ 2424 { 0x00021bd4, "CMIC_LEDUP1_PROGRAM_RAM245", CMIC_LEDUP1_PROGRAM_RAM245r }, \ 2425 { 0x00021bd8, "CMIC_LEDUP1_PROGRAM_RAM246", CMIC_LEDUP1_PROGRAM_RAM246r }, \ 2426 { 0x00021bdc, "CMIC_LEDUP1_PROGRAM_RAM247", CMIC_LEDUP1_PROGRAM_RAM247r }, \ 2427 { 0x00021be0, "CMIC_LEDUP1_PROGRAM_RAM248", CMIC_LEDUP1_PROGRAM_RAM248r }, \ 2428 { 0x00021be4, "CMIC_LEDUP1_PROGRAM_RAM249", CMIC_LEDUP1_PROGRAM_RAM249r }, \ 2429 { 0x00021be8, "CMIC_LEDUP1_PROGRAM_RAM250", CMIC_LEDUP1_PROGRAM_RAM250r }, \ 2430 { 0x00021bec, "CMIC_LEDUP1_PROGRAM_RAM251", CMIC_LEDUP1_PROGRAM_RAM251r }, \ 2431 { 0x00021bf0, "CMIC_LEDUP1_PROGRAM_RAM252", CMIC_LEDUP1_PROGRAM_RAM252r }, \ 2432 { 0x00021bf4, "CMIC_LEDUP1_PROGRAM_RAM253", CMIC_LEDUP1_PROGRAM_RAM253r }, \ 2433 { 0x00021bf8, "CMIC_LEDUP1_PROGRAM_RAM254", CMIC_LEDUP1_PROGRAM_RAM254r }, \ 2434 { 0x00021bfc, "CMIC_LEDUP1_PROGRAM_RAM255", CMIC_LEDUP1_PROGRAM_RAM255r }, \ 2435 { 0x00022080, "CMIC_RPE_MIIM_PARAM", CMIC_RPE_MIIM_PARAMr }, \ 2436 { 0x00022084, "CMIC_RPE_MIIM_READ_DATA", CMIC_RPE_MIIM_READ_DATAr }, \ 2437 { 0x00022088, "CMIC_RPE_MIIM_ADDRESS", CMIC_RPE_MIIM_ADDRESSr }, \ 2438 { 0x0002208c, "CMIC_RPE_MIIM_CTRL", CMIC_RPE_MIIM_CTRLr }, \ 2439 { 0x00022090, "CMIC_RPE_MIIM_STAT", CMIC_RPE_MIIM_STATr }, \ 2440 { 0x00022100, "CMIC_PKT_PRI_MAP_TABLE_ENTRY_0", CMIC_PKT_PRI_MAP_TABLE_ENTRY_0r }, \ 2441 { 0x00022104, "CMIC_PKT_PRI_MAP_TABLE_ENTRY_1", CMIC_PKT_PRI_MAP_TABLE_ENTRY_1r }, \ 2442 { 0x00022108, "CMIC_PKT_PRI_MAP_TABLE_ENTRY_2", CMIC_PKT_PRI_MAP_TABLE_ENTRY_2r }, \ 2443 { 0x0002210c, "CMIC_PKT_PRI_MAP_TABLE_ENTRY_3", CMIC_PKT_PRI_MAP_TABLE_ENTRY_3r }, \ 2444 { 0x00022110, "CMIC_PKT_PRI_MAP_TABLE_ENTRY_4", CMIC_PKT_PRI_MAP_TABLE_ENTRY_4r }, \ 2445 { 0x00022114, "CMIC_PKT_PRI_MAP_TABLE_ENTRY_5", CMIC_PKT_PRI_MAP_TABLE_ENTRY_5r }, \ 2446 { 0x00022118, "CMIC_PKT_PRI_MAP_TABLE_ENTRY_6", CMIC_PKT_PRI_MAP_TABLE_ENTRY_6r }, \ 2447 { 0x0002211c, "CMIC_PKT_PRI_MAP_TABLE_ENTRY_7", CMIC_PKT_PRI_MAP_TABLE_ENTRY_7r }, \ 2448 { 0x00022120, "CMIC_PKT_PRI_MAP_TABLE_ENTRY_8", CMIC_PKT_PRI_MAP_TABLE_ENTRY_8r }, \ 2449 { 0x00022124, "CMIC_PKT_PRI_MAP_TABLE_ENTRY_9", CMIC_PKT_PRI_MAP_TABLE_ENTRY_9r }, \ 2450 { 0x00022128, "CMIC_PKT_PRI_MAP_TABLE_ENTRY_10", CMIC_PKT_PRI_MAP_TABLE_ENTRY_10r }, \ 2451 { 0x0002212c, "CMIC_PKT_PRI_MAP_TABLE_ENTRY_11", CMIC_PKT_PRI_MAP_TABLE_ENTRY_11r }, \ 2452 { 0x00022130, "CMIC_PKT_PRI_MAP_TABLE_ENTRY_12", CMIC_PKT_PRI_MAP_TABLE_ENTRY_12r }, \ 2453 { 0x00022134, "CMIC_PKT_PRI_MAP_TABLE_ENTRY_13", CMIC_PKT_PRI_MAP_TABLE_ENTRY_13r }, \ 2454 { 0x00022138, "CMIC_PKT_PRI_MAP_TABLE_ENTRY_14", CMIC_PKT_PRI_MAP_TABLE_ENTRY_14r }, \ 2455 { 0x0002213c, "CMIC_PKT_PRI_MAP_TABLE_ENTRY_15", CMIC_PKT_PRI_MAP_TABLE_ENTRY_15r }, \ 2456 { 0x00022140, "CMIC_PKT_PRI_MAP_TABLE_ENTRY_16", CMIC_PKT_PRI_MAP_TABLE_ENTRY_16r }, \ 2457 { 0x00022144, "CMIC_PKT_PRI_MAP_TABLE_ENTRY_17", CMIC_PKT_PRI_MAP_TABLE_ENTRY_17r }, \ 2458 { 0x00022148, "CMIC_PKT_PRI_MAP_TABLE_ENTRY_18", CMIC_PKT_PRI_MAP_TABLE_ENTRY_18r }, \ 2459 { 0x0002214c, "CMIC_PKT_PRI_MAP_TABLE_ENTRY_19", CMIC_PKT_PRI_MAP_TABLE_ENTRY_19r }, \ 2460 { 0x00022150, "CMIC_PKT_PRI_MAP_TABLE_ENTRY_20", CMIC_PKT_PRI_MAP_TABLE_ENTRY_20r }, \ 2461 { 0x00022154, "CMIC_PKT_PRI_MAP_TABLE_ENTRY_21", CMIC_PKT_PRI_MAP_TABLE_ENTRY_21r }, \ 2462 { 0x00022158, "CMIC_PKT_PRI_MAP_TABLE_ENTRY_22", CMIC_PKT_PRI_MAP_TABLE_ENTRY_22r }, \ 2463 { 0x0002215c, "CMIC_PKT_PRI_MAP_TABLE_ENTRY_23", CMIC_PKT_PRI_MAP_TABLE_ENTRY_23r }, \ 2464 { 0x00022160, "CMIC_PKT_PRI_MAP_TABLE_ENTRY_24", CMIC_PKT_PRI_MAP_TABLE_ENTRY_24r }, \ 2465 { 0x00022164, "CMIC_PKT_PRI_MAP_TABLE_ENTRY_25", CMIC_PKT_PRI_MAP_TABLE_ENTRY_25r }, \ 2466 { 0x00022168, "CMIC_PKT_PRI_MAP_TABLE_ENTRY_26", CMIC_PKT_PRI_MAP_TABLE_ENTRY_26r }, \ 2467 { 0x0002216c, "CMIC_PKT_PRI_MAP_TABLE_ENTRY_27", CMIC_PKT_PRI_MAP_TABLE_ENTRY_27r }, \ 2468 { 0x00022170, "CMIC_PKT_PRI_MAP_TABLE_ENTRY_28", CMIC_PKT_PRI_MAP_TABLE_ENTRY_28r }, \ 2469 { 0x00022174, "CMIC_PKT_PRI_MAP_TABLE_ENTRY_29", CMIC_PKT_PRI_MAP_TABLE_ENTRY_29r }, \ 2470 { 0x00022178, "CMIC_PKT_PRI_MAP_TABLE_ENTRY_30", CMIC_PKT_PRI_MAP_TABLE_ENTRY_30r }, \ 2471 { 0x0002217c, "CMIC_PKT_PRI_MAP_TABLE_ENTRY_31", CMIC_PKT_PRI_MAP_TABLE_ENTRY_31r }, \ 2472 { 0x00022180, "CMIC_PKT_PRI_MAP_TABLE_ENTRY_32", CMIC_PKT_PRI_MAP_TABLE_ENTRY_32r }, \ 2473 { 0x00022184, "CMIC_PKT_PRI_MAP_TABLE_ENTRY_33", CMIC_PKT_PRI_MAP_TABLE_ENTRY_33r }, \ 2474 { 0x00022188, "CMIC_PKT_PRI_MAP_TABLE_ENTRY_34", CMIC_PKT_PRI_MAP_TABLE_ENTRY_34r }, \ 2475 { 0x0002218c, "CMIC_PKT_PRI_MAP_TABLE_ENTRY_35", CMIC_PKT_PRI_MAP_TABLE_ENTRY_35r }, \ 2476 { 0x00022190, "CMIC_PKT_PRI_MAP_TABLE_ENTRY_36", CMIC_PKT_PRI_MAP_TABLE_ENTRY_36r }, \ 2477 { 0x00022194, "CMIC_PKT_PRI_MAP_TABLE_ENTRY_37", CMIC_PKT_PRI_MAP_TABLE_ENTRY_37r }, \ 2478 { 0x00022198, "CMIC_PKT_PRI_MAP_TABLE_ENTRY_38", CMIC_PKT_PRI_MAP_TABLE_ENTRY_38r }, \ 2479 { 0x0002219c, "CMIC_PKT_PRI_MAP_TABLE_ENTRY_39", CMIC_PKT_PRI_MAP_TABLE_ENTRY_39r }, \ 2480 { 0x000221a0, "CMIC_PKT_PRI_MAP_TABLE_ENTRY_40", CMIC_PKT_PRI_MAP_TABLE_ENTRY_40r }, \ 2481 { 0x000221a4, "CMIC_PKT_PRI_MAP_TABLE_ENTRY_41", CMIC_PKT_PRI_MAP_TABLE_ENTRY_41r }, \ 2482 { 0x000221a8, "CMIC_PKT_PRI_MAP_TABLE_ENTRY_42", CMIC_PKT_PRI_MAP_TABLE_ENTRY_42r }, \ 2483 { 0x000221ac, "CMIC_PKT_PRI_MAP_TABLE_ENTRY_43", CMIC_PKT_PRI_MAP_TABLE_ENTRY_43r }, \ 2484 { 0x000221b0, "CMIC_PKT_PRI_MAP_TABLE_ENTRY_44", CMIC_PKT_PRI_MAP_TABLE_ENTRY_44r }, \ 2485 { 0x000221b4, "CMIC_PKT_PRI_MAP_TABLE_ENTRY_45", CMIC_PKT_PRI_MAP_TABLE_ENTRY_45r }, \ 2486 { 0x000221b8, "CMIC_PKT_PRI_MAP_TABLE_ENTRY_46", CMIC_PKT_PRI_MAP_TABLE_ENTRY_46r }, \ 2487 { 0x000221bc, "CMIC_PKT_PRI_MAP_TABLE_ENTRY_47", CMIC_PKT_PRI_MAP_TABLE_ENTRY_47r }, \ 2488 { 0x000221c0, "CMIC_PKT_PRI_MAP_TABLE_ENTRY_48", CMIC_PKT_PRI_MAP_TABLE_ENTRY_48r }, \ 2489 { 0x000221c4, "CMIC_PKT_PRI_MAP_TABLE_ENTRY_49", CMIC_PKT_PRI_MAP_TABLE_ENTRY_49r }, \ 2490 { 0x000221c8, "CMIC_PKT_PRI_MAP_TABLE_ENTRY_50", CMIC_PKT_PRI_MAP_TABLE_ENTRY_50r }, \ 2491 { 0x000221cc, "CMIC_PKT_PRI_MAP_TABLE_ENTRY_51", CMIC_PKT_PRI_MAP_TABLE_ENTRY_51r }, \ 2492 { 0x000221d0, "CMIC_PKT_PRI_MAP_TABLE_ENTRY_52", CMIC_PKT_PRI_MAP_TABLE_ENTRY_52r }, \ 2493 { 0x000221d4, "CMIC_PKT_PRI_MAP_TABLE_ENTRY_53", CMIC_PKT_PRI_MAP_TABLE_ENTRY_53r }, \ 2494 { 0x000221d8, "CMIC_PKT_PRI_MAP_TABLE_ENTRY_54", CMIC_PKT_PRI_MAP_TABLE_ENTRY_54r }, \ 2495 { 0x000221dc, "CMIC_PKT_PRI_MAP_TABLE_ENTRY_55", CMIC_PKT_PRI_MAP_TABLE_ENTRY_55r }, \ 2496 { 0x000221e0, "CMIC_PKT_PRI_MAP_TABLE_ENTRY_56", CMIC_PKT_PRI_MAP_TABLE_ENTRY_56r }, \ 2497 { 0x000221e4, "CMIC_PKT_PRI_MAP_TABLE_ENTRY_57", CMIC_PKT_PRI_MAP_TABLE_ENTRY_57r }, \ 2498 { 0x000221e8, "CMIC_PKT_PRI_MAP_TABLE_ENTRY_58", CMIC_PKT_PRI_MAP_TABLE_ENTRY_58r }, \ 2499 { 0x000221ec, "CMIC_PKT_PRI_MAP_TABLE_ENTRY_59", CMIC_PKT_PRI_MAP_TABLE_ENTRY_59r }, \ 2500 { 0x000221f0, "CMIC_PKT_PRI_MAP_TABLE_ENTRY_60", CMIC_PKT_PRI_MAP_TABLE_ENTRY_60r }, \ 2501 { 0x000221f4, "CMIC_PKT_PRI_MAP_TABLE_ENTRY_61", CMIC_PKT_PRI_MAP_TABLE_ENTRY_61r }, \ 2502 { 0x000221f8, "CMIC_PKT_PRI_MAP_TABLE_ENTRY_62", CMIC_PKT_PRI_MAP_TABLE_ENTRY_62r }, \ 2503 { 0x000221fc, "CMIC_PKT_PRI_MAP_TABLE_ENTRY_63", CMIC_PKT_PRI_MAP_TABLE_ENTRY_63r }, \ 2504 { 0x00022200, "CMIC_PKT_CTRL", CMIC_PKT_CTRLr }, \ 2505 { 0x00022204, "CMIC_PKT_LMAC0_HI", CMIC_PKT_LMAC0_HIr }, \ 2506 { 0x00022208, "CMIC_PKT_LMAC0_LO", CMIC_PKT_LMAC0_LOr }, \ 2507 { 0x0002220c, "CMIC_PKT_LMAC1_HI", CMIC_PKT_LMAC1_HIr }, \ 2508 { 0x00022210, "CMIC_PKT_LMAC1_LO", CMIC_PKT_LMAC1_LOr }, \ 2509 { 0x00022214, "CMIC_PKT_VLAN", CMIC_PKT_VLANr }, \ 2510 { 0x00022218, "CMIC_PKT_ETHER_SIG", CMIC_PKT_ETHER_SIGr }, \ 2511 { 0x0002221c, "CMIC_PKT_COS_0", CMIC_PKT_COS_0r }, \ 2512 { 0x00022220, "CMIC_PKT_COS_1", CMIC_PKT_COS_1r }, \ 2513 { 0x00022224, "CMIC_PKT_PORTS_0", CMIC_PKT_PORTS_0r }, \ 2514 { 0x00022228, "CMIC_PKT_PORTS_1", CMIC_PKT_PORTS_1r }, \ 2515 { 0x0002222c, "CMIC_PKT_PORTS_2", CMIC_PKT_PORTS_2r }, \ 2516 { 0x00022230, "CMIC_PKT_RMAC", CMIC_PKT_RMACr }, \ 2517 { 0x00022234, "CMIC_PKT_RMAC_HI", CMIC_PKT_RMAC_HIr }, \ 2518 { 0x00022238, "CMIC_PKT_RMH0", CMIC_PKT_RMH0r }, \ 2519 { 0x0002223c, "CMIC_PKT_RMH1", CMIC_PKT_RMH1r }, \ 2520 { 0x00022240, "CMIC_PKT_RMH2", CMIC_PKT_RMH2r }, \ 2521 { 0x00022244, "CMIC_INTR_PKT_PACING_DELAY", CMIC_INTR_PKT_PACING_DELAYr }, \ 2522 { 0x00022248, "CMIC_RPE_STAT", CMIC_RPE_STATr }, \ 2523 { 0x0002224c, "CMIC_RPE_STAT_CLR", CMIC_RPE_STAT_CLRr }, \ 2524 { 0x00022250, "CMIC_PKT_PORTS_3", CMIC_PKT_PORTS_3r }, \ 2525 { 0x00022254, "CMIC_PKT_PORTS_4", CMIC_PKT_PORTS_4r }, \ 2526 { 0x00022258, "CMIC_PKT_PORTS_5", CMIC_PKT_PORTS_5r }, \ 2527 { 0x0002225c, "CMIC_PKT_PORTS_6", CMIC_PKT_PORTS_6r }, \ 2528 { 0x00022260, "CMIC_PKT_PORTS_7", CMIC_PKT_PORTS_7r }, \ 2529 { 0x000222a4, "CMIC_PKT_COS_QUEUES_HI", CMIC_PKT_COS_QUEUES_HIr }, \ 2530 { 0x000222a8, "CMIC_PKT_COS_QUEUES_LO", CMIC_PKT_COS_QUEUES_LOr }, \ 2531 { 0x000222ac, "CMIC_PKT_COUNT_SCHAN", CMIC_PKT_COUNT_SCHANr }, \ 2532 { 0x000222b0, "CMIC_PKT_COUNT_SCHAN_REP", CMIC_PKT_COUNT_SCHAN_REPr }, \ 2533 { 0x000222b4, "CMIC_PKT_COUNT_FROMCPU_MH", CMIC_PKT_COUNT_FROMCPU_MHr }, \ 2534 { 0x000222b8, "CMIC_PKT_COUNT_FROMCPU", CMIC_PKT_COUNT_FROMCPUr }, \ 2535 { 0x000222bc, "CMIC_PKT_COUNT_TOCPUDM", CMIC_PKT_COUNT_TOCPUDMr }, \ 2536 { 0x000222c0, "CMIC_PKT_COUNT_TOCPUD", CMIC_PKT_COUNT_TOCPUDr }, \ 2537 { 0x000222c4, "CMIC_PKT_COUNT_TOCPUEM", CMIC_PKT_COUNT_TOCPUEMr }, \ 2538 { 0x000222c8, "CMIC_PKT_COUNT_TOCPUE", CMIC_PKT_COUNT_TOCPUEr }, \ 2539 { 0x000222cc, "CMIC_PKT_COUNT_PIO_REPLY", CMIC_PKT_COUNT_PIO_REPLYr }, \ 2540 { 0x000222d0, "CMIC_PKT_COUNT_PIO", CMIC_PKT_COUNT_PIOr }, \ 2541 { 0x000222d4, "CMIC_PKT_COUNT_INTR", CMIC_PKT_COUNT_INTRr }, \ 2542 { 0x000222d8, "CMIC_SCHAN_RCPU_RPIO_MESSAGE", CMIC_SCHAN_RCPU_RPIO_MESSAGEr }, \ 2543 { 0x000222d8, "CMIC_SCHAN_RCPU_RPIO_MESSAGE0", CMIC_SCHAN_RCPU_RPIO_MESSAGE0r }, \ 2544 { 0x000222dc, "CMIC_SCHAN_RCPU_RPIO_MESSAGE1", CMIC_SCHAN_RCPU_RPIO_MESSAGE1r }, \ 2545 { 0x000222e0, "CMIC_SCHAN_RCPU_RPIO_MESSAGE2", CMIC_SCHAN_RCPU_RPIO_MESSAGE2r }, \ 2546 { 0x000222e4, "CMIC_SCHAN_RCPU_RPIO_MESSAGE3", CMIC_SCHAN_RCPU_RPIO_MESSAGE3r }, \ 2547 { 0x000222e8, "CMIC_SCHAN_RCPU_RPIO_MESSAGE4", CMIC_SCHAN_RCPU_RPIO_MESSAGE4r }, \ 2548 { 0x000222ec, "CMIC_SCHAN_RCPU_RPIO_MESSAGE5", CMIC_SCHAN_RCPU_RPIO_MESSAGE5r }, \ 2549 { 0x000222f0, "CMIC_SCHAN_RCPU_RPIO_MESSAGE6", CMIC_SCHAN_RCPU_RPIO_MESSAGE6r }, \ 2550 { 0x000222f4, "CMIC_SCHAN_RCPU_RPIO_MESSAGE7", CMIC_SCHAN_RCPU_RPIO_MESSAGE7r }, \ 2551 { 0x000222f8, "CMIC_SCHAN_RCPU_RPIO_MESSAGE8", CMIC_SCHAN_RCPU_RPIO_MESSAGE8r }, \ 2552 { 0x000222fc, "CMIC_SCHAN_RCPU_RPIO_MESSAGE9", CMIC_SCHAN_RCPU_RPIO_MESSAGE9r }, \ 2553 { 0x00022300, "CMIC_SCHAN_RCPU_RPIO_MESSAGE10", CMIC_SCHAN_RCPU_RPIO_MESSAGE10r }, \ 2554 { 0x00022304, "CMIC_SCHAN_RCPU_RPIO_MESSAGE11", CMIC_SCHAN_RCPU_RPIO_MESSAGE11r }, \ 2555 { 0x00022308, "CMIC_SCHAN_RCPU_RPIO_MESSAGE12", CMIC_SCHAN_RCPU_RPIO_MESSAGE12r }, \ 2556 { 0x0002230c, "CMIC_SCHAN_RCPU_RPIO_MESSAGE13", CMIC_SCHAN_RCPU_RPIO_MESSAGE13r }, \ 2557 { 0x00022310, "CMIC_SCHAN_RCPU_RPIO_MESSAGE14", CMIC_SCHAN_RCPU_RPIO_MESSAGE14r }, \ 2558 { 0x00022314, "CMIC_SCHAN_RCPU_RPIO_MESSAGE15", CMIC_SCHAN_RCPU_RPIO_MESSAGE15r }, \ 2559 { 0x00022318, "CMIC_SCHAN_RCPU_RPIO_MESSAGE16", CMIC_SCHAN_RCPU_RPIO_MESSAGE16r }, \ 2560 { 0x0002231c, "CMIC_SCHAN_RCPU_RPIO_MESSAGE17", CMIC_SCHAN_RCPU_RPIO_MESSAGE17r }, \ 2561 { 0x00022320, "CMIC_SCHAN_RCPU_RPIO_MESSAGE18", CMIC_SCHAN_RCPU_RPIO_MESSAGE18r }, \ 2562 { 0x00022324, "CMIC_SCHAN_RCPU_RPIO_MESSAGE19", CMIC_SCHAN_RCPU_RPIO_MESSAGE19r }, \ 2563 { 0x00022328, "CMIC_SCHAN_RCPU_RPIO_MESSAGE20", CMIC_SCHAN_RCPU_RPIO_MESSAGE20r }, \ 2564 { 0x0002232c, "CMIC_SCHAN_RCPU_RPIO_MESSAGE21", CMIC_SCHAN_RCPU_RPIO_MESSAGE21r }, \ 2565 { 0x00022330, "CMIC_RPE_IRQ_STAT0", CMIC_RPE_IRQ_STAT0r }, \ 2566 { 0x00022334, "CMIC_RPE_IRQ_STAT1", CMIC_RPE_IRQ_STAT1r }, \ 2567 { 0x00022338, "CMIC_RPE_IRQ_STAT2", CMIC_RPE_IRQ_STAT2r }, \ 2568 { 0x0002233c, "CMIC_RPE_IRQ_STAT3", CMIC_RPE_IRQ_STAT3r }, \ 2569 { 0x00022340, "CMIC_RPE_IRQ_STAT4", CMIC_RPE_IRQ_STAT4r }, \ 2570 { 0x00022344, "CMIC_RPE_RCPU_IRQ_MASK0", CMIC_RPE_RCPU_IRQ_MASK0r }, \ 2571 { 0x00022348, "CMIC_RPE_RCPU_IRQ_MASK1", CMIC_RPE_RCPU_IRQ_MASK1r }, \ 2572 { 0x0002234c, "CMIC_RPE_RCPU_IRQ_MASK2", CMIC_RPE_RCPU_IRQ_MASK2r }, \ 2573 { 0x00022350, "CMIC_RPE_RCPU_IRQ_MASK3", CMIC_RPE_RCPU_IRQ_MASK3r }, \ 2574 { 0x00022354, "CMIC_RPE_RCPU_IRQ_MASK4", CMIC_RPE_RCPU_IRQ_MASK4r }, \ 2575 { 0x00022358, "CMIC_RPE_PCIE_IRQ_MASK0", CMIC_RPE_PCIE_IRQ_MASK0r }, \ 2576 { 0x0002235c, "CMIC_RPE_UC0_IRQ_MASK0", CMIC_RPE_UC0_IRQ_MASK0r }, \ 2577 { 0x00022360, "CMIC_RPE_UC1_IRQ_MASK0", CMIC_RPE_UC1_IRQ_MASK0r }, \ 2578 { 0x00022364, "CMIC_PKT_RMH3", CMIC_PKT_RMH3r }, \ 2579 { 0x00022368, "CMIC_RPE_MAX_CELL_LIMIT", CMIC_RPE_MAX_CELL_LIMITr }, \ 2580 { 0x0002236c, "CMIC_RPE_SW_INTR_CONFIG", CMIC_RPE_SW_INTR_CONFIGr }, \ 2581 { 0x00022370, "CMIC_PKT_REASON_0_TYPE", CMIC_PKT_REASON_0_TYPEr }, \ 2582 { 0x00022370, "CMIC_PKT_REASON_0_TYPE0", CMIC_PKT_REASON_0_TYPE0r }, \ 2583 { 0x00022374, "CMIC_PKT_REASON_0_TYPE1", CMIC_PKT_REASON_0_TYPE1r }, \ 2584 { 0x00022378, "CMIC_PKT_REASON_0_TYPE2", CMIC_PKT_REASON_0_TYPE2r }, \ 2585 { 0x0002237c, "CMIC_PKT_REASON_0_TYPE3", CMIC_PKT_REASON_0_TYPE3r }, \ 2586 { 0x00022380, "CMIC_PKT_REASON_0_TYPE4", CMIC_PKT_REASON_0_TYPE4r }, \ 2587 { 0x00022384, "CMIC_PKT_REASON_0_TYPE5", CMIC_PKT_REASON_0_TYPE5r }, \ 2588 { 0x00022388, "CMIC_PKT_REASON_0_TYPE6", CMIC_PKT_REASON_0_TYPE6r }, \ 2589 { 0x0002238c, "CMIC_PKT_REASON_0_TYPE7", CMIC_PKT_REASON_0_TYPE7r }, \ 2590 { 0x00022390, "CMIC_PKT_REASON_0_TYPE8", CMIC_PKT_REASON_0_TYPE8r }, \ 2591 { 0x00022394, "CMIC_PKT_REASON_0_TYPE9", CMIC_PKT_REASON_0_TYPE9r }, \ 2592 { 0x00022398, "CMIC_PKT_REASON_0_TYPE10", CMIC_PKT_REASON_0_TYPE10r }, \ 2593 { 0x0002239c, "CMIC_PKT_REASON_0_TYPE11", CMIC_PKT_REASON_0_TYPE11r }, \ 2594 { 0x000223a0, "CMIC_PKT_REASON_0_TYPE12", CMIC_PKT_REASON_0_TYPE12r }, \ 2595 { 0x000223a4, "CMIC_PKT_REASON_0_TYPE13", CMIC_PKT_REASON_0_TYPE13r }, \ 2596 { 0x000223a8, "CMIC_PKT_REASON_0_TYPE14", CMIC_PKT_REASON_0_TYPE14r }, \ 2597 { 0x000223ac, "CMIC_PKT_REASON_0_TYPE15", CMIC_PKT_REASON_0_TYPE15r }, \ 2598 { 0x000223b0, "CMIC_PKT_REASON_1_TYPE0", CMIC_PKT_REASON_1_TYPE0r }, \ 2599 { 0x000223b0, "CMIC_PKT_REASON_1_TYPE", CMIC_PKT_REASON_1_TYPEr }, \ 2600 { 0x000223b4, "CMIC_PKT_REASON_1_TYPE1", CMIC_PKT_REASON_1_TYPE1r }, \ 2601 { 0x000223b8, "CMIC_PKT_REASON_1_TYPE2", CMIC_PKT_REASON_1_TYPE2r }, \ 2602 { 0x000223bc, "CMIC_PKT_REASON_1_TYPE3", CMIC_PKT_REASON_1_TYPE3r }, \ 2603 { 0x000223c0, "CMIC_PKT_REASON_1_TYPE4", CMIC_PKT_REASON_1_TYPE4r }, \ 2604 { 0x000223c4, "CMIC_PKT_REASON_1_TYPE5", CMIC_PKT_REASON_1_TYPE5r }, \ 2605 { 0x000223c8, "CMIC_PKT_REASON_1_TYPE6", CMIC_PKT_REASON_1_TYPE6r }, \ 2606 { 0x000223cc, "CMIC_PKT_REASON_1_TYPE7", CMIC_PKT_REASON_1_TYPE7r }, \ 2607 { 0x000223d0, "CMIC_PKT_REASON_1_TYPE8", CMIC_PKT_REASON_1_TYPE8r }, \ 2608 { 0x000223d4, "CMIC_PKT_REASON_1_TYPE9", CMIC_PKT_REASON_1_TYPE9r }, \ 2609 { 0x000223d8, "CMIC_PKT_REASON_1_TYPE10", CMIC_PKT_REASON_1_TYPE10r }, \ 2610 { 0x000223dc, "CMIC_PKT_REASON_1_TYPE11", CMIC_PKT_REASON_1_TYPE11r }, \ 2611 { 0x000223e0, "CMIC_PKT_REASON_1_TYPE12", CMIC_PKT_REASON_1_TYPE12r }, \ 2612 { 0x000223e4, "CMIC_PKT_REASON_1_TYPE13", CMIC_PKT_REASON_1_TYPE13r }, \ 2613 { 0x000223e8, "CMIC_PKT_REASON_1_TYPE14", CMIC_PKT_REASON_1_TYPE14r }, \ 2614 { 0x000223ec, "CMIC_PKT_REASON_1_TYPE15", CMIC_PKT_REASON_1_TYPE15r }, \ 2615 { 0x000223f0, "CMIC_PKT_REASON_DIRECT_0_TYPE", CMIC_PKT_REASON_DIRECT_0_TYPEr }, \ 2616 { 0x000223f0, "CMIC_PKT_REASON_DIRECT_0_TYPE0", CMIC_PKT_REASON_DIRECT_0_TYPE0r }, \ 2617 { 0x000223f4, "CMIC_PKT_REASON_DIRECT_0_TYPE1", CMIC_PKT_REASON_DIRECT_0_TYPE1r }, \ 2618 { 0x000223f8, "CMIC_PKT_REASON_DIRECT_0_TYPE2", CMIC_PKT_REASON_DIRECT_0_TYPE2r }, \ 2619 { 0x000223fc, "CMIC_PKT_REASON_DIRECT_0_TYPE3", CMIC_PKT_REASON_DIRECT_0_TYPE3r }, \ 2620 { 0x00022400, "CMIC_PKT_REASON_DIRECT_0_TYPE4", CMIC_PKT_REASON_DIRECT_0_TYPE4r }, \ 2621 { 0x00022404, "CMIC_PKT_REASON_DIRECT_0_TYPE5", CMIC_PKT_REASON_DIRECT_0_TYPE5r }, \ 2622 { 0x00022408, "CMIC_PKT_REASON_DIRECT_0_TYPE6", CMIC_PKT_REASON_DIRECT_0_TYPE6r }, \ 2623 { 0x0002240c, "CMIC_PKT_REASON_DIRECT_0_TYPE7", CMIC_PKT_REASON_DIRECT_0_TYPE7r }, \ 2624 { 0x00022410, "CMIC_PKT_REASON_DIRECT_0_TYPE8", CMIC_PKT_REASON_DIRECT_0_TYPE8r }, \ 2625 { 0x00022414, "CMIC_PKT_REASON_DIRECT_0_TYPE9", CMIC_PKT_REASON_DIRECT_0_TYPE9r }, \ 2626 { 0x00022418, "CMIC_PKT_REASON_DIRECT_0_TYPE10", CMIC_PKT_REASON_DIRECT_0_TYPE10r }, \ 2627 { 0x0002241c, "CMIC_PKT_REASON_DIRECT_0_TYPE11", CMIC_PKT_REASON_DIRECT_0_TYPE11r }, \ 2628 { 0x00022420, "CMIC_PKT_REASON_DIRECT_0_TYPE12", CMIC_PKT_REASON_DIRECT_0_TYPE12r }, \ 2629 { 0x00022424, "CMIC_PKT_REASON_DIRECT_0_TYPE13", CMIC_PKT_REASON_DIRECT_0_TYPE13r }, \ 2630 { 0x00022428, "CMIC_PKT_REASON_DIRECT_0_TYPE14", CMIC_PKT_REASON_DIRECT_0_TYPE14r }, \ 2631 { 0x0002242c, "CMIC_PKT_REASON_DIRECT_0_TYPE15", CMIC_PKT_REASON_DIRECT_0_TYPE15r }, \ 2632 { 0x00022430, "CMIC_PKT_REASON_DIRECT_1_TYPE0", CMIC_PKT_REASON_DIRECT_1_TYPE0r }, \ 2633 { 0x00022430, "CMIC_PKT_REASON_DIRECT_1_TYPE", CMIC_PKT_REASON_DIRECT_1_TYPEr }, \ 2634 { 0x00022434, "CMIC_PKT_REASON_DIRECT_1_TYPE1", CMIC_PKT_REASON_DIRECT_1_TYPE1r }, \ 2635 { 0x00022438, "CMIC_PKT_REASON_DIRECT_1_TYPE2", CMIC_PKT_REASON_DIRECT_1_TYPE2r }, \ 2636 { 0x0002243c, "CMIC_PKT_REASON_DIRECT_1_TYPE3", CMIC_PKT_REASON_DIRECT_1_TYPE3r }, \ 2637 { 0x00022440, "CMIC_PKT_REASON_DIRECT_1_TYPE4", CMIC_PKT_REASON_DIRECT_1_TYPE4r }, \ 2638 { 0x00022444, "CMIC_PKT_REASON_DIRECT_1_TYPE5", CMIC_PKT_REASON_DIRECT_1_TYPE5r }, \ 2639 { 0x00022448, "CMIC_PKT_REASON_DIRECT_1_TYPE6", CMIC_PKT_REASON_DIRECT_1_TYPE6r }, \ 2640 { 0x0002244c, "CMIC_PKT_REASON_DIRECT_1_TYPE7", CMIC_PKT_REASON_DIRECT_1_TYPE7r }, \ 2641 { 0x00022450, "CMIC_PKT_REASON_DIRECT_1_TYPE8", CMIC_PKT_REASON_DIRECT_1_TYPE8r }, \ 2642 { 0x00022454, "CMIC_PKT_REASON_DIRECT_1_TYPE9", CMIC_PKT_REASON_DIRECT_1_TYPE9r }, \ 2643 { 0x00022458, "CMIC_PKT_REASON_DIRECT_1_TYPE10", CMIC_PKT_REASON_DIRECT_1_TYPE10r }, \ 2644 { 0x0002245c, "CMIC_PKT_REASON_DIRECT_1_TYPE11", CMIC_PKT_REASON_DIRECT_1_TYPE11r }, \ 2645 { 0x00022460, "CMIC_PKT_REASON_DIRECT_1_TYPE12", CMIC_PKT_REASON_DIRECT_1_TYPE12r }, \ 2646 { 0x00022464, "CMIC_PKT_REASON_DIRECT_1_TYPE13", CMIC_PKT_REASON_DIRECT_1_TYPE13r }, \ 2647 { 0x00022468, "CMIC_PKT_REASON_DIRECT_1_TYPE14", CMIC_PKT_REASON_DIRECT_1_TYPE14r }, \ 2648 { 0x0002246c, "CMIC_PKT_REASON_DIRECT_1_TYPE15", CMIC_PKT_REASON_DIRECT_1_TYPE15r }, \ 2649 { 0x00022470, "CMIC_PKT_REASON_MINI_0_TYPE", CMIC_PKT_REASON_MINI_0_TYPEr }, \ 2650 { 0x00022470, "CMIC_PKT_REASON_MINI_0_TYPE0", CMIC_PKT_REASON_MINI_0_TYPE0r }, \ 2651 { 0x00022474, "CMIC_PKT_REASON_MINI_0_TYPE1", CMIC_PKT_REASON_MINI_0_TYPE1r }, \ 2652 { 0x00022478, "CMIC_PKT_REASON_MINI_0_TYPE2", CMIC_PKT_REASON_MINI_0_TYPE2r }, \ 2653 { 0x0002247c, "CMIC_PKT_REASON_MINI_0_TYPE3", CMIC_PKT_REASON_MINI_0_TYPE3r }, \ 2654 { 0x00022480, "CMIC_PKT_REASON_MINI_0_TYPE4", CMIC_PKT_REASON_MINI_0_TYPE4r }, \ 2655 { 0x00022484, "CMIC_PKT_REASON_MINI_0_TYPE5", CMIC_PKT_REASON_MINI_0_TYPE5r }, \ 2656 { 0x00022488, "CMIC_PKT_REASON_MINI_0_TYPE6", CMIC_PKT_REASON_MINI_0_TYPE6r }, \ 2657 { 0x0002248c, "CMIC_PKT_REASON_MINI_0_TYPE7", CMIC_PKT_REASON_MINI_0_TYPE7r }, \ 2658 { 0x00022490, "CMIC_PKT_REASON_MINI_0_TYPE8", CMIC_PKT_REASON_MINI_0_TYPE8r }, \ 2659 { 0x00022494, "CMIC_PKT_REASON_MINI_0_TYPE9", CMIC_PKT_REASON_MINI_0_TYPE9r }, \ 2660 { 0x00022498, "CMIC_PKT_REASON_MINI_0_TYPE10", CMIC_PKT_REASON_MINI_0_TYPE10r }, \ 2661 { 0x0002249c, "CMIC_PKT_REASON_MINI_0_TYPE11", CMIC_PKT_REASON_MINI_0_TYPE11r }, \ 2662 { 0x000224a0, "CMIC_PKT_REASON_MINI_0_TYPE12", CMIC_PKT_REASON_MINI_0_TYPE12r }, \ 2663 { 0x000224a4, "CMIC_PKT_REASON_MINI_0_TYPE13", CMIC_PKT_REASON_MINI_0_TYPE13r }, \ 2664 { 0x000224a8, "CMIC_PKT_REASON_MINI_0_TYPE14", CMIC_PKT_REASON_MINI_0_TYPE14r }, \ 2665 { 0x000224ac, "CMIC_PKT_REASON_MINI_0_TYPE15", CMIC_PKT_REASON_MINI_0_TYPE15r }, \ 2666 { 0x000224b0, "CMIC_PKT_REASON_MINI_1_TYPE", CMIC_PKT_REASON_MINI_1_TYPEr }, \ 2667 { 0x000224b0, "CMIC_PKT_REASON_MINI_1_TYPE0", CMIC_PKT_REASON_MINI_1_TYPE0r }, \ 2668 { 0x000224b4, "CMIC_PKT_REASON_MINI_1_TYPE1", CMIC_PKT_REASON_MINI_1_TYPE1r }, \ 2669 { 0x000224b8, "CMIC_PKT_REASON_MINI_1_TYPE2", CMIC_PKT_REASON_MINI_1_TYPE2r }, \ 2670 { 0x000224bc, "CMIC_PKT_REASON_MINI_1_TYPE3", CMIC_PKT_REASON_MINI_1_TYPE3r }, \ 2671 { 0x000224c0, "CMIC_PKT_REASON_MINI_1_TYPE4", CMIC_PKT_REASON_MINI_1_TYPE4r }, \ 2672 { 0x000224c4, "CMIC_PKT_REASON_MINI_1_TYPE5", CMIC_PKT_REASON_MINI_1_TYPE5r }, \ 2673 { 0x000224c8, "CMIC_PKT_REASON_MINI_1_TYPE6", CMIC_PKT_REASON_MINI_1_TYPE6r }, \ 2674 { 0x000224cc, "CMIC_PKT_REASON_MINI_1_TYPE7", CMIC_PKT_REASON_MINI_1_TYPE7r }, \ 2675 { 0x000224d0, "CMIC_PKT_REASON_MINI_1_TYPE8", CMIC_PKT_REASON_MINI_1_TYPE8r }, \ 2676 { 0x000224d4, "CMIC_PKT_REASON_MINI_1_TYPE9", CMIC_PKT_REASON_MINI_1_TYPE9r }, \ 2677 { 0x000224d8, "CMIC_PKT_REASON_MINI_1_TYPE10", CMIC_PKT_REASON_MINI_1_TYPE10r }, \ 2678 { 0x000224dc, "CMIC_PKT_REASON_MINI_1_TYPE11", CMIC_PKT_REASON_MINI_1_TYPE11r }, \ 2679 { 0x000224e0, "CMIC_PKT_REASON_MINI_1_TYPE12", CMIC_PKT_REASON_MINI_1_TYPE12r }, \ 2680 { 0x000224e4, "CMIC_PKT_REASON_MINI_1_TYPE13", CMIC_PKT_REASON_MINI_1_TYPE13r }, \ 2681 { 0x000224e8, "CMIC_PKT_REASON_MINI_1_TYPE14", CMIC_PKT_REASON_MINI_1_TYPE14r }, \ 2682 { 0x000224ec, "CMIC_PKT_REASON_MINI_1_TYPE15", CMIC_PKT_REASON_MINI_1_TYPE15r }, \ 2683 { 0x000224f0, "CMIC_PKT_REASON_2_TYPE0", CMIC_PKT_REASON_2_TYPE0r }, \ 2684 { 0x000224f0, "CMIC_PKT_REASON_2_TYPE", CMIC_PKT_REASON_2_TYPEr }, \ 2685 { 0x000224f4, "CMIC_PKT_REASON_2_TYPE1", CMIC_PKT_REASON_2_TYPE1r }, \ 2686 { 0x000224f8, "CMIC_PKT_REASON_2_TYPE2", CMIC_PKT_REASON_2_TYPE2r }, \ 2687 { 0x000224fc, "CMIC_PKT_REASON_2_TYPE3", CMIC_PKT_REASON_2_TYPE3r }, \ 2688 { 0x00022500, "CMIC_PKT_REASON_2_TYPE4", CMIC_PKT_REASON_2_TYPE4r }, \ 2689 { 0x00022504, "CMIC_PKT_REASON_2_TYPE5", CMIC_PKT_REASON_2_TYPE5r }, \ 2690 { 0x00022508, "CMIC_PKT_REASON_2_TYPE6", CMIC_PKT_REASON_2_TYPE6r }, \ 2691 { 0x0002250c, "CMIC_PKT_REASON_2_TYPE7", CMIC_PKT_REASON_2_TYPE7r }, \ 2692 { 0x00022510, "CMIC_PKT_REASON_2_TYPE8", CMIC_PKT_REASON_2_TYPE8r }, \ 2693 { 0x00022514, "CMIC_PKT_REASON_2_TYPE9", CMIC_PKT_REASON_2_TYPE9r }, \ 2694 { 0x00022518, "CMIC_PKT_REASON_2_TYPE10", CMIC_PKT_REASON_2_TYPE10r }, \ 2695 { 0x0002251c, "CMIC_PKT_REASON_2_TYPE11", CMIC_PKT_REASON_2_TYPE11r }, \ 2696 { 0x00022520, "CMIC_PKT_REASON_2_TYPE12", CMIC_PKT_REASON_2_TYPE12r }, \ 2697 { 0x00022524, "CMIC_PKT_REASON_2_TYPE13", CMIC_PKT_REASON_2_TYPE13r }, \ 2698 { 0x00022528, "CMIC_PKT_REASON_2_TYPE14", CMIC_PKT_REASON_2_TYPE14r }, \ 2699 { 0x0002252c, "CMIC_PKT_REASON_2_TYPE15", CMIC_PKT_REASON_2_TYPE15r }, \ 2700 { 0x00022530, "CMIC_PKT_REASON_DIRECT_2_TYPE", CMIC_PKT_REASON_DIRECT_2_TYPEr }, \ 2701 { 0x00022530, "CMIC_PKT_REASON_DIRECT_2_TYPE0", CMIC_PKT_REASON_DIRECT_2_TYPE0r }, \ 2702 { 0x00022534, "CMIC_PKT_REASON_DIRECT_2_TYPE1", CMIC_PKT_REASON_DIRECT_2_TYPE1r }, \ 2703 { 0x00022538, "CMIC_PKT_REASON_DIRECT_2_TYPE2", CMIC_PKT_REASON_DIRECT_2_TYPE2r }, \ 2704 { 0x0002253c, "CMIC_PKT_REASON_DIRECT_2_TYPE3", CMIC_PKT_REASON_DIRECT_2_TYPE3r }, \ 2705 { 0x00022540, "CMIC_PKT_REASON_DIRECT_2_TYPE4", CMIC_PKT_REASON_DIRECT_2_TYPE4r }, \ 2706 { 0x00022544, "CMIC_PKT_REASON_DIRECT_2_TYPE5", CMIC_PKT_REASON_DIRECT_2_TYPE5r }, \ 2707 { 0x00022548, "CMIC_PKT_REASON_DIRECT_2_TYPE6", CMIC_PKT_REASON_DIRECT_2_TYPE6r }, \ 2708 { 0x0002254c, "CMIC_PKT_REASON_DIRECT_2_TYPE7", CMIC_PKT_REASON_DIRECT_2_TYPE7r }, \ 2709 { 0x00022550, "CMIC_PKT_REASON_DIRECT_2_TYPE8", CMIC_PKT_REASON_DIRECT_2_TYPE8r }, \ 2710 { 0x00022554, "CMIC_PKT_REASON_DIRECT_2_TYPE9", CMIC_PKT_REASON_DIRECT_2_TYPE9r }, \ 2711 { 0x00022558, "CMIC_PKT_REASON_DIRECT_2_TYPE10", CMIC_PKT_REASON_DIRECT_2_TYPE10r }, \ 2712 { 0x0002255c, "CMIC_PKT_REASON_DIRECT_2_TYPE11", CMIC_PKT_REASON_DIRECT_2_TYPE11r }, \ 2713 { 0x00022560, "CMIC_PKT_REASON_DIRECT_2_TYPE12", CMIC_PKT_REASON_DIRECT_2_TYPE12r }, \ 2714 { 0x00022564, "CMIC_PKT_REASON_DIRECT_2_TYPE13", CMIC_PKT_REASON_DIRECT_2_TYPE13r }, \ 2715 { 0x00022568, "CMIC_PKT_REASON_DIRECT_2_TYPE14", CMIC_PKT_REASON_DIRECT_2_TYPE14r }, \ 2716 { 0x0002256c, "CMIC_PKT_REASON_DIRECT_2_TYPE15", CMIC_PKT_REASON_DIRECT_2_TYPE15r }, \ 2717 { 0x00022570, "CMIC_PKT_REASON_MINI_2_TYPE0", CMIC_PKT_REASON_MINI_2_TYPE0r }, \ 2718 { 0x00022570, "CMIC_PKT_REASON_MINI_2_TYPE", CMIC_PKT_REASON_MINI_2_TYPEr }, \ 2719 { 0x00022574, "CMIC_PKT_REASON_MINI_2_TYPE1", CMIC_PKT_REASON_MINI_2_TYPE1r }, \ 2720 { 0x00022578, "CMIC_PKT_REASON_MINI_2_TYPE2", CMIC_PKT_REASON_MINI_2_TYPE2r }, \ 2721 { 0x0002257c, "CMIC_PKT_REASON_MINI_2_TYPE3", CMIC_PKT_REASON_MINI_2_TYPE3r }, \ 2722 { 0x00022580, "CMIC_PKT_REASON_MINI_2_TYPE4", CMIC_PKT_REASON_MINI_2_TYPE4r }, \ 2723 { 0x00022584, "CMIC_PKT_REASON_MINI_2_TYPE5", CMIC_PKT_REASON_MINI_2_TYPE5r }, \ 2724 { 0x00022588, "CMIC_PKT_REASON_MINI_2_TYPE6", CMIC_PKT_REASON_MINI_2_TYPE6r }, \ 2725 { 0x0002258c, "CMIC_PKT_REASON_MINI_2_TYPE7", CMIC_PKT_REASON_MINI_2_TYPE7r }, \ 2726 { 0x00022590, "CMIC_PKT_REASON_MINI_2_TYPE8", CMIC_PKT_REASON_MINI_2_TYPE8r }, \ 2727 { 0x00022594, "CMIC_PKT_REASON_MINI_2_TYPE9", CMIC_PKT_REASON_MINI_2_TYPE9r }, \ 2728 { 0x00022598, "CMIC_PKT_REASON_MINI_2_TYPE10", CMIC_PKT_REASON_MINI_2_TYPE10r }, \ 2729 { 0x0002259c, "CMIC_PKT_REASON_MINI_2_TYPE11", CMIC_PKT_REASON_MINI_2_TYPE11r }, \ 2730 { 0x000225a0, "CMIC_PKT_REASON_MINI_2_TYPE12", CMIC_PKT_REASON_MINI_2_TYPE12r }, \ 2731 { 0x000225a4, "CMIC_PKT_REASON_MINI_2_TYPE13", CMIC_PKT_REASON_MINI_2_TYPE13r }, \ 2732 { 0x000225a8, "CMIC_PKT_REASON_MINI_2_TYPE14", CMIC_PKT_REASON_MINI_2_TYPE14r }, \ 2733 { 0x000225ac, "CMIC_PKT_REASON_MINI_2_TYPE15", CMIC_PKT_REASON_MINI_2_TYPE15r }, \ 2734 { 0x00022600, "CMIC_RPE1_MAX_CELL_LIMIT", CMIC_RPE1_MAX_CELL_LIMITr }, \ 2735 { 0x00022604, "CMIC_RPE0_MAX_CELL_LIMIT", CMIC_RPE0_MAX_CELL_LIMITr }, \ 2736 { 0x00022610, "CMIC_RPE_DEBUG", CMIC_RPE_DEBUGr }, \ 2737 { 0x000226b0, "CMIC_RPE_IRQ_STAT5", CMIC_RPE_IRQ_STAT5r }, \ 2738 { 0x000226b4, "CMIC_RPE_IRQ_STAT6", CMIC_RPE_IRQ_STAT6r }, \ 2739 { 0x000226b8, "CMIC_RPE_RCPU_IRQ_MASK5", CMIC_RPE_RCPU_IRQ_MASK5r }, \ 2740 { 0x000226bc, "CMIC_RPE_RCPU_IRQ_MASK6", CMIC_RPE_RCPU_IRQ_MASK6r }, \ 2741 { 0x00023000, "CMIC_MMU_COSLC_COUNT_ADDR", CMIC_MMU_COSLC_COUNT_ADDRr }, \ 2742 { 0x00023004, "CMIC_MMU_COSLC_COUNT_DATA", CMIC_MMU_COSLC_COUNT_DATAr }, \ 2743 { 0x00024000, "CMIC_TIM0_TIMER1LOAD", CMIC_TIM0_TIMER1LOADr }, \ 2744 { 0x00024004, "CMIC_TIM0_TIMER1VALUE", CMIC_TIM0_TIMER1VALUEr }, \ 2745 { 0x00024008, "CMIC_TIM0_TIMER1CONTROL", CMIC_TIM0_TIMER1CONTROLr }, \ 2746 { 0x0002400c, "CMIC_TIM0_TIMER1INTCLR", CMIC_TIM0_TIMER1INTCLRr }, \ 2747 { 0x00024010, "CMIC_TIM0_TIMER1RIS", CMIC_TIM0_TIMER1RISr }, \ 2748 { 0x00024014, "CMIC_TIM0_TIMER1MIS", CMIC_TIM0_TIMER1MISr }, \ 2749 { 0x00024018, "CMIC_TIM0_TIMER1BGLOAD", CMIC_TIM0_TIMER1BGLOADr }, \ 2750 { 0x00024020, "CMIC_TIM0_TIMER2LOAD", CMIC_TIM0_TIMER2LOADr }, \ 2751 { 0x00024024, "CMIC_TIM0_TIMER2VALUE", CMIC_TIM0_TIMER2VALUEr }, \ 2752 { 0x00024028, "CMIC_TIM0_TIMER2CONTROL", CMIC_TIM0_TIMER2CONTROLr }, \ 2753 { 0x0002402c, "CMIC_TIM0_TIMER2INTCLR", CMIC_TIM0_TIMER2INTCLRr }, \ 2754 { 0x00024030, "CMIC_TIM0_TIMER2RIS", CMIC_TIM0_TIMER2RISr }, \ 2755 { 0x00024034, "CMIC_TIM0_TIMER2MIS", CMIC_TIM0_TIMER2MISr }, \ 2756 { 0x00024038, "CMIC_TIM0_TIMER2BGLOAD", CMIC_TIM0_TIMER2BGLOADr }, \ 2757 { 0x00024f00, "CMIC_TIM0_TIMERITCR", CMIC_TIM0_TIMERITCRr }, \ 2758 { 0x00024f04, "CMIC_TIM0_TIMERITOP", CMIC_TIM0_TIMERITOPr }, \ 2759 { 0x00024fe0, "CMIC_TIM0_TIMERPERIPHID0", CMIC_TIM0_TIMERPERIPHID0r }, \ 2760 { 0x00024fe4, "CMIC_TIM0_TIMERPERIPHID1", CMIC_TIM0_TIMERPERIPHID1r }, \ 2761 { 0x00024fe8, "CMIC_TIM0_TIMERPERIPHID2", CMIC_TIM0_TIMERPERIPHID2r }, \ 2762 { 0x00024fec, "CMIC_TIM0_TIMERPERIPHID3", CMIC_TIM0_TIMERPERIPHID3r }, \ 2763 { 0x00024ff0, "CMIC_TIM0_TIMERPCELLID0", CMIC_TIM0_TIMERPCELLID0r }, \ 2764 { 0x00024ff4, "CMIC_TIM0_TIMERPCELLID1", CMIC_TIM0_TIMERPCELLID1r }, \ 2765 { 0x00024ff8, "CMIC_TIM0_TIMERPCELLID2", CMIC_TIM0_TIMERPCELLID2r }, \ 2766 { 0x00024ffc, "CMIC_TIM0_TIMERPCELLID3", CMIC_TIM0_TIMERPCELLID3r }, \ 2767 { 0x00025000, "CMIC_FINE_GRAIN_COUNTERS_CTRL", CMIC_FINE_GRAIN_COUNTERS_CTRLr }, \ 2768 { 0x00025004, "CMIC_FINE_GRAIN_COUNTERS_NS_VALUE", CMIC_FINE_GRAIN_COUNTERS_NS_VALUEr }, \ 2769 { 0x00025008, "CMIC_FINE_GRAIN_COUNTERS_SECOND_VALUE", CMIC_FINE_GRAIN_COUNTERS_SECOND_VALUEr }, \ 2770 { 0x00026000, "CMIC_TIM1_TIMER1LOAD", CMIC_TIM1_TIMER1LOADr }, \ 2771 { 0x00026004, "CMIC_TIM1_TIMER1VALUE", CMIC_TIM1_TIMER1VALUEr }, \ 2772 { 0x00026008, "CMIC_TIM1_TIMER1CONTROL", CMIC_TIM1_TIMER1CONTROLr }, \ 2773 { 0x0002600c, "CMIC_TIM1_TIMER1INTCLR", CMIC_TIM1_TIMER1INTCLRr }, \ 2774 { 0x00026010, "CMIC_TIM1_TIMER1RIS", CMIC_TIM1_TIMER1RISr }, \ 2775 { 0x00026014, "CMIC_TIM1_TIMER1MIS", CMIC_TIM1_TIMER1MISr }, \ 2776 { 0x00026018, "CMIC_TIM1_TIMER1BGLOAD", CMIC_TIM1_TIMER1BGLOADr }, \ 2777 { 0x00026020, "CMIC_TIM1_TIMER2LOAD", CMIC_TIM1_TIMER2LOADr }, \ 2778 { 0x00026024, "CMIC_TIM1_TIMER2VALUE", CMIC_TIM1_TIMER2VALUEr }, \ 2779 { 0x00026028, "CMIC_TIM1_TIMER2CONTROL", CMIC_TIM1_TIMER2CONTROLr }, \ 2780 { 0x0002602c, "CMIC_TIM1_TIMER2INTCLR", CMIC_TIM1_TIMER2INTCLRr }, \ 2781 { 0x00026030, "CMIC_TIM1_TIMER2RIS", CMIC_TIM1_TIMER2RISr }, \ 2782 { 0x00026034, "CMIC_TIM1_TIMER2MIS", CMIC_TIM1_TIMER2MISr }, \ 2783 { 0x00026038, "CMIC_TIM1_TIMER2BGLOAD", CMIC_TIM1_TIMER2BGLOADr }, \ 2784 { 0x00026f00, "CMIC_TIM1_TIMERITCR", CMIC_TIM1_TIMERITCRr }, \ 2785 { 0x00026f04, "CMIC_TIM1_TIMERITOP", CMIC_TIM1_TIMERITOPr }, \ 2786 { 0x00026fe0, "CMIC_TIM1_TIMERPERIPHID0", CMIC_TIM1_TIMERPERIPHID0r }, \ 2787 { 0x00026fe4, "CMIC_TIM1_TIMERPERIPHID1", CMIC_TIM1_TIMERPERIPHID1r }, \ 2788 { 0x00026fe8, "CMIC_TIM1_TIMERPERIPHID2", CMIC_TIM1_TIMERPERIPHID2r }, \ 2789 { 0x00026fec, "CMIC_TIM1_TIMERPERIPHID3", CMIC_TIM1_TIMERPERIPHID3r }, \ 2790 { 0x00026ff0, "CMIC_TIM1_TIMERPCELLID0", CMIC_TIM1_TIMERPCELLID0r }, \ 2791 { 0x00026ff4, "CMIC_TIM1_TIMERPCELLID1", CMIC_TIM1_TIMERPCELLID1r }, \ 2792 { 0x00026ff8, "CMIC_TIM1_TIMERPCELLID2", CMIC_TIM1_TIMERPCELLID2r }, \ 2793 { 0x00026ffc, "CMIC_TIM1_TIMERPCELLID3", CMIC_TIM1_TIMERPCELLID3r }, \ 2794 { 0x00027000, "CMIC_PCIE_CFG_ADDRESS", CMIC_PCIE_CFG_ADDRESSr }, \ 2795 { 0x00027004, "CMIC_PCIE_CFG_WRITE_DATA", CMIC_PCIE_CFG_WRITE_DATAr }, \ 2796 { 0x00027008, "CMIC_PCIE_CFG_READ_DATA", CMIC_PCIE_CFG_READ_DATAr }, \ 2797 { 0x00029000, "CMIC_LEDUP2_CTRL", CMIC_LEDUP2_CTRLr }, \ 2798 { 0x00029004, "CMIC_LEDUP2_STATUS", CMIC_LEDUP2_STATUSr }, \ 2799 { 0x00029008, "CMIC_LEDUP2_SCANCHAIN_ASSEMBLY_ST_ADDR", CMIC_LEDUP2_SCANCHAIN_ASSEMBLY_ST_ADDRr }, \ 2800 { 0x00029010, "CMIC_LEDUP2_PORT_ORDER_REMAP_0_3", CMIC_LEDUP2_PORT_ORDER_REMAP_0_3r }, \ 2801 { 0x00029014, "CMIC_LEDUP2_PORT_ORDER_REMAP_4_7", CMIC_LEDUP2_PORT_ORDER_REMAP_4_7r }, \ 2802 { 0x00029018, "CMIC_LEDUP2_PORT_ORDER_REMAP_8_11", CMIC_LEDUP2_PORT_ORDER_REMAP_8_11r }, \ 2803 { 0x0002901c, "CMIC_LEDUP2_PORT_ORDER_REMAP_12_15", CMIC_LEDUP2_PORT_ORDER_REMAP_12_15r }, \ 2804 { 0x00029020, "CMIC_LEDUP2_PORT_ORDER_REMAP_16_19", CMIC_LEDUP2_PORT_ORDER_REMAP_16_19r }, \ 2805 { 0x00029024, "CMIC_LEDUP2_PORT_ORDER_REMAP_20_23", CMIC_LEDUP2_PORT_ORDER_REMAP_20_23r }, \ 2806 { 0x00029028, "CMIC_LEDUP2_PORT_ORDER_REMAP_24_27", CMIC_LEDUP2_PORT_ORDER_REMAP_24_27r }, \ 2807 { 0x0002902c, "CMIC_LEDUP2_PORT_ORDER_REMAP_28_31", CMIC_LEDUP2_PORT_ORDER_REMAP_28_31r }, \ 2808 { 0x00029030, "CMIC_LEDUP2_PORT_ORDER_REMAP_32_35", CMIC_LEDUP2_PORT_ORDER_REMAP_32_35r }, \ 2809 { 0x00029034, "CMIC_LEDUP2_PORT_ORDER_REMAP_36_39", CMIC_LEDUP2_PORT_ORDER_REMAP_36_39r }, \ 2810 { 0x00029038, "CMIC_LEDUP2_PORT_ORDER_REMAP_40_43", CMIC_LEDUP2_PORT_ORDER_REMAP_40_43r }, \ 2811 { 0x0002903c, "CMIC_LEDUP2_PORT_ORDER_REMAP_44_47", CMIC_LEDUP2_PORT_ORDER_REMAP_44_47r }, \ 2812 { 0x00029040, "CMIC_LEDUP2_PORT_ORDER_REMAP_48_51", CMIC_LEDUP2_PORT_ORDER_REMAP_48_51r }, \ 2813 { 0x00029044, "CMIC_LEDUP2_PORT_ORDER_REMAP_52_55", CMIC_LEDUP2_PORT_ORDER_REMAP_52_55r }, \ 2814 { 0x00029048, "CMIC_LEDUP2_PORT_ORDER_REMAP_56_59", CMIC_LEDUP2_PORT_ORDER_REMAP_56_59r }, \ 2815 { 0x0002904c, "CMIC_LEDUP2_PORT_ORDER_REMAP_60_63", CMIC_LEDUP2_PORT_ORDER_REMAP_60_63r }, \ 2816 { 0x00029050, "CMIC_LEDUP2_CLK_PARAMS", CMIC_LEDUP2_CLK_PARAMSr }, \ 2817 { 0x00029054, "CMIC_LEDUP2_SCANOUT_COUNT_UPPER", CMIC_LEDUP2_SCANOUT_COUNT_UPPERr }, \ 2818 { 0x00029058, "CMIC_LEDUP2_TM_CONTROL", CMIC_LEDUP2_TM_CONTROLr }, \ 2819 { 0x0002905c, "CMIC_LEDUP2_CLK_DIV", CMIC_LEDUP2_CLK_DIVr }, \ 2820 { 0x00029060, "CMIC_LEDUP2_ECC_CONFIG", CMIC_LEDUP2_ECC_CONFIGr }, \ 2821 { 0x00029064, "CMIC_LEDUP2_ECC_STATUS", CMIC_LEDUP2_ECC_STATUSr }, \ 2822 { 0x00029068, "CMIC_LEDUP2_ECC_INTR_ENABLE", CMIC_LEDUP2_ECC_INTR_ENABLEr }, \ 2823 { 0x0002906c, "CMIC_LEDUP2_ECC_INTR", CMIC_LEDUP2_ECC_INTRr }, \ 2824 { 0x00029070, "CMIC_LEDUP2_ECC_INTR_CLR", CMIC_LEDUP2_ECC_INTR_CLRr }, \ 2825 { 0x00029400, "CMIC_LEDUP2_DATA_RAM", CMIC_LEDUP2_DATA_RAMr }, \ 2826 { 0x00029400, "CMIC_LEDUP2_DATA_RAM0", CMIC_LEDUP2_DATA_RAM0r }, \ 2827 { 0x00029404, "CMIC_LEDUP2_DATA_RAM1", CMIC_LEDUP2_DATA_RAM1r }, \ 2828 { 0x00029408, "CMIC_LEDUP2_DATA_RAM2", CMIC_LEDUP2_DATA_RAM2r }, \ 2829 { 0x0002940c, "CMIC_LEDUP2_DATA_RAM3", CMIC_LEDUP2_DATA_RAM3r }, \ 2830 { 0x00029410, "CMIC_LEDUP2_DATA_RAM4", CMIC_LEDUP2_DATA_RAM4r }, \ 2831 { 0x00029414, "CMIC_LEDUP2_DATA_RAM5", CMIC_LEDUP2_DATA_RAM5r }, \ 2832 { 0x00029418, "CMIC_LEDUP2_DATA_RAM6", CMIC_LEDUP2_DATA_RAM6r }, \ 2833 { 0x0002941c, "CMIC_LEDUP2_DATA_RAM7", CMIC_LEDUP2_DATA_RAM7r }, \ 2834 { 0x00029420, "CMIC_LEDUP2_DATA_RAM8", CMIC_LEDUP2_DATA_RAM8r }, \ 2835 { 0x00029424, "CMIC_LEDUP2_DATA_RAM9", CMIC_LEDUP2_DATA_RAM9r }, \ 2836 { 0x00029428, "CMIC_LEDUP2_DATA_RAM10", CMIC_LEDUP2_DATA_RAM10r }, \ 2837 { 0x0002942c, "CMIC_LEDUP2_DATA_RAM11", CMIC_LEDUP2_DATA_RAM11r }, \ 2838 { 0x00029430, "CMIC_LEDUP2_DATA_RAM12", CMIC_LEDUP2_DATA_RAM12r }, \ 2839 { 0x00029434, "CMIC_LEDUP2_DATA_RAM13", CMIC_LEDUP2_DATA_RAM13r }, \ 2840 { 0x00029438, "CMIC_LEDUP2_DATA_RAM14", CMIC_LEDUP2_DATA_RAM14r }, \ 2841 { 0x0002943c, "CMIC_LEDUP2_DATA_RAM15", CMIC_LEDUP2_DATA_RAM15r }, \ 2842 { 0x00029440, "CMIC_LEDUP2_DATA_RAM16", CMIC_LEDUP2_DATA_RAM16r }, \ 2843 { 0x00029444, "CMIC_LEDUP2_DATA_RAM17", CMIC_LEDUP2_DATA_RAM17r }, \ 2844 { 0x00029448, "CMIC_LEDUP2_DATA_RAM18", CMIC_LEDUP2_DATA_RAM18r }, \ 2845 { 0x0002944c, "CMIC_LEDUP2_DATA_RAM19", CMIC_LEDUP2_DATA_RAM19r }, \ 2846 { 0x00029450, "CMIC_LEDUP2_DATA_RAM20", CMIC_LEDUP2_DATA_RAM20r }, \ 2847 { 0x00029454, "CMIC_LEDUP2_DATA_RAM21", CMIC_LEDUP2_DATA_RAM21r }, \ 2848 { 0x00029458, "CMIC_LEDUP2_DATA_RAM22", CMIC_LEDUP2_DATA_RAM22r }, \ 2849 { 0x0002945c, "CMIC_LEDUP2_DATA_RAM23", CMIC_LEDUP2_DATA_RAM23r }, \ 2850 { 0x00029460, "CMIC_LEDUP2_DATA_RAM24", CMIC_LEDUP2_DATA_RAM24r }, \ 2851 { 0x00029464, "CMIC_LEDUP2_DATA_RAM25", CMIC_LEDUP2_DATA_RAM25r }, \ 2852 { 0x00029468, "CMIC_LEDUP2_DATA_RAM26", CMIC_LEDUP2_DATA_RAM26r }, \ 2853 { 0x0002946c, "CMIC_LEDUP2_DATA_RAM27", CMIC_LEDUP2_DATA_RAM27r }, \ 2854 { 0x00029470, "CMIC_LEDUP2_DATA_RAM28", CMIC_LEDUP2_DATA_RAM28r }, \ 2855 { 0x00029474, "CMIC_LEDUP2_DATA_RAM29", CMIC_LEDUP2_DATA_RAM29r }, \ 2856 { 0x00029478, "CMIC_LEDUP2_DATA_RAM30", CMIC_LEDUP2_DATA_RAM30r }, \ 2857 { 0x0002947c, "CMIC_LEDUP2_DATA_RAM31", CMIC_LEDUP2_DATA_RAM31r }, \ 2858 { 0x00029480, "CMIC_LEDUP2_DATA_RAM32", CMIC_LEDUP2_DATA_RAM32r }, \ 2859 { 0x00029484, "CMIC_LEDUP2_DATA_RAM33", CMIC_LEDUP2_DATA_RAM33r }, \ 2860 { 0x00029488, "CMIC_LEDUP2_DATA_RAM34", CMIC_LEDUP2_DATA_RAM34r }, \ 2861 { 0x0002948c, "CMIC_LEDUP2_DATA_RAM35", CMIC_LEDUP2_DATA_RAM35r }, \ 2862 { 0x00029490, "CMIC_LEDUP2_DATA_RAM36", CMIC_LEDUP2_DATA_RAM36r }, \ 2863 { 0x00029494, "CMIC_LEDUP2_DATA_RAM37", CMIC_LEDUP2_DATA_RAM37r }, \ 2864 { 0x00029498, "CMIC_LEDUP2_DATA_RAM38", CMIC_LEDUP2_DATA_RAM38r }, \ 2865 { 0x0002949c, "CMIC_LEDUP2_DATA_RAM39", CMIC_LEDUP2_DATA_RAM39r }, \ 2866 { 0x000294a0, "CMIC_LEDUP2_DATA_RAM40", CMIC_LEDUP2_DATA_RAM40r }, \ 2867 { 0x000294a4, "CMIC_LEDUP2_DATA_RAM41", CMIC_LEDUP2_DATA_RAM41r }, \ 2868 { 0x000294a8, "CMIC_LEDUP2_DATA_RAM42", CMIC_LEDUP2_DATA_RAM42r }, \ 2869 { 0x000294ac, "CMIC_LEDUP2_DATA_RAM43", CMIC_LEDUP2_DATA_RAM43r }, \ 2870 { 0x000294b0, "CMIC_LEDUP2_DATA_RAM44", CMIC_LEDUP2_DATA_RAM44r }, \ 2871 { 0x000294b4, "CMIC_LEDUP2_DATA_RAM45", CMIC_LEDUP2_DATA_RAM45r }, \ 2872 { 0x000294b8, "CMIC_LEDUP2_DATA_RAM46", CMIC_LEDUP2_DATA_RAM46r }, \ 2873 { 0x000294bc, "CMIC_LEDUP2_DATA_RAM47", CMIC_LEDUP2_DATA_RAM47r }, \ 2874 { 0x000294c0, "CMIC_LEDUP2_DATA_RAM48", CMIC_LEDUP2_DATA_RAM48r }, \ 2875 { 0x000294c4, "CMIC_LEDUP2_DATA_RAM49", CMIC_LEDUP2_DATA_RAM49r }, \ 2876 { 0x000294c8, "CMIC_LEDUP2_DATA_RAM50", CMIC_LEDUP2_DATA_RAM50r }, \ 2877 { 0x000294cc, "CMIC_LEDUP2_DATA_RAM51", CMIC_LEDUP2_DATA_RAM51r }, \ 2878 { 0x000294d0, "CMIC_LEDUP2_DATA_RAM52", CMIC_LEDUP2_DATA_RAM52r }, \ 2879 { 0x000294d4, "CMIC_LEDUP2_DATA_RAM53", CMIC_LEDUP2_DATA_RAM53r }, \ 2880 { 0x000294d8, "CMIC_LEDUP2_DATA_RAM54", CMIC_LEDUP2_DATA_RAM54r }, \ 2881 { 0x000294dc, "CMIC_LEDUP2_DATA_RAM55", CMIC_LEDUP2_DATA_RAM55r }, \ 2882 { 0x000294e0, "CMIC_LEDUP2_DATA_RAM56", CMIC_LEDUP2_DATA_RAM56r }, \ 2883 { 0x000294e4, "CMIC_LEDUP2_DATA_RAM57", CMIC_LEDUP2_DATA_RAM57r }, \ 2884 { 0x000294e8, "CMIC_LEDUP2_DATA_RAM58", CMIC_LEDUP2_DATA_RAM58r }, \ 2885 { 0x000294ec, "CMIC_LEDUP2_DATA_RAM59", CMIC_LEDUP2_DATA_RAM59r }, \ 2886 { 0x000294f0, "CMIC_LEDUP2_DATA_RAM60", CMIC_LEDUP2_DATA_RAM60r }, \ 2887 { 0x000294f4, "CMIC_LEDUP2_DATA_RAM61", CMIC_LEDUP2_DATA_RAM61r }, \ 2888 { 0x000294f8, "CMIC_LEDUP2_DATA_RAM62", CMIC_LEDUP2_DATA_RAM62r }, \ 2889 { 0x000294fc, "CMIC_LEDUP2_DATA_RAM63", CMIC_LEDUP2_DATA_RAM63r }, \ 2890 { 0x00029500, "CMIC_LEDUP2_DATA_RAM64", CMIC_LEDUP2_DATA_RAM64r }, \ 2891 { 0x00029504, "CMIC_LEDUP2_DATA_RAM65", CMIC_LEDUP2_DATA_RAM65r }, \ 2892 { 0x00029508, "CMIC_LEDUP2_DATA_RAM66", CMIC_LEDUP2_DATA_RAM66r }, \ 2893 { 0x0002950c, "CMIC_LEDUP2_DATA_RAM67", CMIC_LEDUP2_DATA_RAM67r }, \ 2894 { 0x00029510, "CMIC_LEDUP2_DATA_RAM68", CMIC_LEDUP2_DATA_RAM68r }, \ 2895 { 0x00029514, "CMIC_LEDUP2_DATA_RAM69", CMIC_LEDUP2_DATA_RAM69r }, \ 2896 { 0x00029518, "CMIC_LEDUP2_DATA_RAM70", CMIC_LEDUP2_DATA_RAM70r }, \ 2897 { 0x0002951c, "CMIC_LEDUP2_DATA_RAM71", CMIC_LEDUP2_DATA_RAM71r }, \ 2898 { 0x00029520, "CMIC_LEDUP2_DATA_RAM72", CMIC_LEDUP2_DATA_RAM72r }, \ 2899 { 0x00029524, "CMIC_LEDUP2_DATA_RAM73", CMIC_LEDUP2_DATA_RAM73r }, \ 2900 { 0x00029528, "CMIC_LEDUP2_DATA_RAM74", CMIC_LEDUP2_DATA_RAM74r }, \ 2901 { 0x0002952c, "CMIC_LEDUP2_DATA_RAM75", CMIC_LEDUP2_DATA_RAM75r }, \ 2902 { 0x00029530, "CMIC_LEDUP2_DATA_RAM76", CMIC_LEDUP2_DATA_RAM76r }, \ 2903 { 0x00029534, "CMIC_LEDUP2_DATA_RAM77", CMIC_LEDUP2_DATA_RAM77r }, \ 2904 { 0x00029538, "CMIC_LEDUP2_DATA_RAM78", CMIC_LEDUP2_DATA_RAM78r }, \ 2905 { 0x0002953c, "CMIC_LEDUP2_DATA_RAM79", CMIC_LEDUP2_DATA_RAM79r }, \ 2906 { 0x00029540, "CMIC_LEDUP2_DATA_RAM80", CMIC_LEDUP2_DATA_RAM80r }, \ 2907 { 0x00029544, "CMIC_LEDUP2_DATA_RAM81", CMIC_LEDUP2_DATA_RAM81r }, \ 2908 { 0x00029548, "CMIC_LEDUP2_DATA_RAM82", CMIC_LEDUP2_DATA_RAM82r }, \ 2909 { 0x0002954c, "CMIC_LEDUP2_DATA_RAM83", CMIC_LEDUP2_DATA_RAM83r }, \ 2910 { 0x00029550, "CMIC_LEDUP2_DATA_RAM84", CMIC_LEDUP2_DATA_RAM84r }, \ 2911 { 0x00029554, "CMIC_LEDUP2_DATA_RAM85", CMIC_LEDUP2_DATA_RAM85r }, \ 2912 { 0x00029558, "CMIC_LEDUP2_DATA_RAM86", CMIC_LEDUP2_DATA_RAM86r }, \ 2913 { 0x0002955c, "CMIC_LEDUP2_DATA_RAM87", CMIC_LEDUP2_DATA_RAM87r }, \ 2914 { 0x00029560, "CMIC_LEDUP2_DATA_RAM88", CMIC_LEDUP2_DATA_RAM88r }, \ 2915 { 0x00029564, "CMIC_LEDUP2_DATA_RAM89", CMIC_LEDUP2_DATA_RAM89r }, \ 2916 { 0x00029568, "CMIC_LEDUP2_DATA_RAM90", CMIC_LEDUP2_DATA_RAM90r }, \ 2917 { 0x0002956c, "CMIC_LEDUP2_DATA_RAM91", CMIC_LEDUP2_DATA_RAM91r }, \ 2918 { 0x00029570, "CMIC_LEDUP2_DATA_RAM92", CMIC_LEDUP2_DATA_RAM92r }, \ 2919 { 0x00029574, "CMIC_LEDUP2_DATA_RAM93", CMIC_LEDUP2_DATA_RAM93r }, \ 2920 { 0x00029578, "CMIC_LEDUP2_DATA_RAM94", CMIC_LEDUP2_DATA_RAM94r }, \ 2921 { 0x0002957c, "CMIC_LEDUP2_DATA_RAM95", CMIC_LEDUP2_DATA_RAM95r }, \ 2922 { 0x00029580, "CMIC_LEDUP2_DATA_RAM96", CMIC_LEDUP2_DATA_RAM96r }, \ 2923 { 0x00029584, "CMIC_LEDUP2_DATA_RAM97", CMIC_LEDUP2_DATA_RAM97r }, \ 2924 { 0x00029588, "CMIC_LEDUP2_DATA_RAM98", CMIC_LEDUP2_DATA_RAM98r }, \ 2925 { 0x0002958c, "CMIC_LEDUP2_DATA_RAM99", CMIC_LEDUP2_DATA_RAM99r }, \ 2926 { 0x00029590, "CMIC_LEDUP2_DATA_RAM100", CMIC_LEDUP2_DATA_RAM100r }, \ 2927 { 0x00029594, "CMIC_LEDUP2_DATA_RAM101", CMIC_LEDUP2_DATA_RAM101r }, \ 2928 { 0x00029598, "CMIC_LEDUP2_DATA_RAM102", CMIC_LEDUP2_DATA_RAM102r }, \ 2929 { 0x0002959c, "CMIC_LEDUP2_DATA_RAM103", CMIC_LEDUP2_DATA_RAM103r }, \ 2930 { 0x000295a0, "CMIC_LEDUP2_DATA_RAM104", CMIC_LEDUP2_DATA_RAM104r }, \ 2931 { 0x000295a4, "CMIC_LEDUP2_DATA_RAM105", CMIC_LEDUP2_DATA_RAM105r }, \ 2932 { 0x000295a8, "CMIC_LEDUP2_DATA_RAM106", CMIC_LEDUP2_DATA_RAM106r }, \ 2933 { 0x000295ac, "CMIC_LEDUP2_DATA_RAM107", CMIC_LEDUP2_DATA_RAM107r }, \ 2934 { 0x000295b0, "CMIC_LEDUP2_DATA_RAM108", CMIC_LEDUP2_DATA_RAM108r }, \ 2935 { 0x000295b4, "CMIC_LEDUP2_DATA_RAM109", CMIC_LEDUP2_DATA_RAM109r }, \ 2936 { 0x000295b8, "CMIC_LEDUP2_DATA_RAM110", CMIC_LEDUP2_DATA_RAM110r }, \ 2937 { 0x000295bc, "CMIC_LEDUP2_DATA_RAM111", CMIC_LEDUP2_DATA_RAM111r }, \ 2938 { 0x000295c0, "CMIC_LEDUP2_DATA_RAM112", CMIC_LEDUP2_DATA_RAM112r }, \ 2939 { 0x000295c4, "CMIC_LEDUP2_DATA_RAM113", CMIC_LEDUP2_DATA_RAM113r }, \ 2940 { 0x000295c8, "CMIC_LEDUP2_DATA_RAM114", CMIC_LEDUP2_DATA_RAM114r }, \ 2941 { 0x000295cc, "CMIC_LEDUP2_DATA_RAM115", CMIC_LEDUP2_DATA_RAM115r }, \ 2942 { 0x000295d0, "CMIC_LEDUP2_DATA_RAM116", CMIC_LEDUP2_DATA_RAM116r }, \ 2943 { 0x000295d4, "CMIC_LEDUP2_DATA_RAM117", CMIC_LEDUP2_DATA_RAM117r }, \ 2944 { 0x000295d8, "CMIC_LEDUP2_DATA_RAM118", CMIC_LEDUP2_DATA_RAM118r }, \ 2945 { 0x000295dc, "CMIC_LEDUP2_DATA_RAM119", CMIC_LEDUP2_DATA_RAM119r }, \ 2946 { 0x000295e0, "CMIC_LEDUP2_DATA_RAM120", CMIC_LEDUP2_DATA_RAM120r }, \ 2947 { 0x000295e4, "CMIC_LEDUP2_DATA_RAM121", CMIC_LEDUP2_DATA_RAM121r }, \ 2948 { 0x000295e8, "CMIC_LEDUP2_DATA_RAM122", CMIC_LEDUP2_DATA_RAM122r }, \ 2949 { 0x000295ec, "CMIC_LEDUP2_DATA_RAM123", CMIC_LEDUP2_DATA_RAM123r }, \ 2950 { 0x000295f0, "CMIC_LEDUP2_DATA_RAM124", CMIC_LEDUP2_DATA_RAM124r }, \ 2951 { 0x000295f4, "CMIC_LEDUP2_DATA_RAM125", CMIC_LEDUP2_DATA_RAM125r }, \ 2952 { 0x000295f8, "CMIC_LEDUP2_DATA_RAM126", CMIC_LEDUP2_DATA_RAM126r }, \ 2953 { 0x000295fc, "CMIC_LEDUP2_DATA_RAM127", CMIC_LEDUP2_DATA_RAM127r }, \ 2954 { 0x00029600, "CMIC_LEDUP2_DATA_RAM128", CMIC_LEDUP2_DATA_RAM128r }, \ 2955 { 0x00029604, "CMIC_LEDUP2_DATA_RAM129", CMIC_LEDUP2_DATA_RAM129r }, \ 2956 { 0x00029608, "CMIC_LEDUP2_DATA_RAM130", CMIC_LEDUP2_DATA_RAM130r }, \ 2957 { 0x0002960c, "CMIC_LEDUP2_DATA_RAM131", CMIC_LEDUP2_DATA_RAM131r }, \ 2958 { 0x00029610, "CMIC_LEDUP2_DATA_RAM132", CMIC_LEDUP2_DATA_RAM132r }, \ 2959 { 0x00029614, "CMIC_LEDUP2_DATA_RAM133", CMIC_LEDUP2_DATA_RAM133r }, \ 2960 { 0x00029618, "CMIC_LEDUP2_DATA_RAM134", CMIC_LEDUP2_DATA_RAM134r }, \ 2961 { 0x0002961c, "CMIC_LEDUP2_DATA_RAM135", CMIC_LEDUP2_DATA_RAM135r }, \ 2962 { 0x00029620, "CMIC_LEDUP2_DATA_RAM136", CMIC_LEDUP2_DATA_RAM136r }, \ 2963 { 0x00029624, "CMIC_LEDUP2_DATA_RAM137", CMIC_LEDUP2_DATA_RAM137r }, \ 2964 { 0x00029628, "CMIC_LEDUP2_DATA_RAM138", CMIC_LEDUP2_DATA_RAM138r }, \ 2965 { 0x0002962c, "CMIC_LEDUP2_DATA_RAM139", CMIC_LEDUP2_DATA_RAM139r }, \ 2966 { 0x00029630, "CMIC_LEDUP2_DATA_RAM140", CMIC_LEDUP2_DATA_RAM140r }, \ 2967 { 0x00029634, "CMIC_LEDUP2_DATA_RAM141", CMIC_LEDUP2_DATA_RAM141r }, \ 2968 { 0x00029638, "CMIC_LEDUP2_DATA_RAM142", CMIC_LEDUP2_DATA_RAM142r }, \ 2969 { 0x0002963c, "CMIC_LEDUP2_DATA_RAM143", CMIC_LEDUP2_DATA_RAM143r }, \ 2970 { 0x00029640, "CMIC_LEDUP2_DATA_RAM144", CMIC_LEDUP2_DATA_RAM144r }, \ 2971 { 0x00029644, "CMIC_LEDUP2_DATA_RAM145", CMIC_LEDUP2_DATA_RAM145r }, \ 2972 { 0x00029648, "CMIC_LEDUP2_DATA_RAM146", CMIC_LEDUP2_DATA_RAM146r }, \ 2973 { 0x0002964c, "CMIC_LEDUP2_DATA_RAM147", CMIC_LEDUP2_DATA_RAM147r }, \ 2974 { 0x00029650, "CMIC_LEDUP2_DATA_RAM148", CMIC_LEDUP2_DATA_RAM148r }, \ 2975 { 0x00029654, "CMIC_LEDUP2_DATA_RAM149", CMIC_LEDUP2_DATA_RAM149r }, \ 2976 { 0x00029658, "CMIC_LEDUP2_DATA_RAM150", CMIC_LEDUP2_DATA_RAM150r }, \ 2977 { 0x0002965c, "CMIC_LEDUP2_DATA_RAM151", CMIC_LEDUP2_DATA_RAM151r }, \ 2978 { 0x00029660, "CMIC_LEDUP2_DATA_RAM152", CMIC_LEDUP2_DATA_RAM152r }, \ 2979 { 0x00029664, "CMIC_LEDUP2_DATA_RAM153", CMIC_LEDUP2_DATA_RAM153r }, \ 2980 { 0x00029668, "CMIC_LEDUP2_DATA_RAM154", CMIC_LEDUP2_DATA_RAM154r }, \ 2981 { 0x0002966c, "CMIC_LEDUP2_DATA_RAM155", CMIC_LEDUP2_DATA_RAM155r }, \ 2982 { 0x00029670, "CMIC_LEDUP2_DATA_RAM156", CMIC_LEDUP2_DATA_RAM156r }, \ 2983 { 0x00029674, "CMIC_LEDUP2_DATA_RAM157", CMIC_LEDUP2_DATA_RAM157r }, \ 2984 { 0x00029678, "CMIC_LEDUP2_DATA_RAM158", CMIC_LEDUP2_DATA_RAM158r }, \ 2985 { 0x0002967c, "CMIC_LEDUP2_DATA_RAM159", CMIC_LEDUP2_DATA_RAM159r }, \ 2986 { 0x00029680, "CMIC_LEDUP2_DATA_RAM160", CMIC_LEDUP2_DATA_RAM160r }, \ 2987 { 0x00029684, "CMIC_LEDUP2_DATA_RAM161", CMIC_LEDUP2_DATA_RAM161r }, \ 2988 { 0x00029688, "CMIC_LEDUP2_DATA_RAM162", CMIC_LEDUP2_DATA_RAM162r }, \ 2989 { 0x0002968c, "CMIC_LEDUP2_DATA_RAM163", CMIC_LEDUP2_DATA_RAM163r }, \ 2990 { 0x00029690, "CMIC_LEDUP2_DATA_RAM164", CMIC_LEDUP2_DATA_RAM164r }, \ 2991 { 0x00029694, "CMIC_LEDUP2_DATA_RAM165", CMIC_LEDUP2_DATA_RAM165r }, \ 2992 { 0x00029698, "CMIC_LEDUP2_DATA_RAM166", CMIC_LEDUP2_DATA_RAM166r }, \ 2993 { 0x0002969c, "CMIC_LEDUP2_DATA_RAM167", CMIC_LEDUP2_DATA_RAM167r }, \ 2994 { 0x000296a0, "CMIC_LEDUP2_DATA_RAM168", CMIC_LEDUP2_DATA_RAM168r }, \ 2995 { 0x000296a4, "CMIC_LEDUP2_DATA_RAM169", CMIC_LEDUP2_DATA_RAM169r }, \ 2996 { 0x000296a8, "CMIC_LEDUP2_DATA_RAM170", CMIC_LEDUP2_DATA_RAM170r }, \ 2997 { 0x000296ac, "CMIC_LEDUP2_DATA_RAM171", CMIC_LEDUP2_DATA_RAM171r }, \ 2998 { 0x000296b0, "CMIC_LEDUP2_DATA_RAM172", CMIC_LEDUP2_DATA_RAM172r }, \ 2999 { 0x000296b4, "CMIC_LEDUP2_DATA_RAM173", CMIC_LEDUP2_DATA_RAM173r }, \ 3000 { 0x000296b8, "CMIC_LEDUP2_DATA_RAM174", CMIC_LEDUP2_DATA_RAM174r }, \ 3001 { 0x000296bc, "CMIC_LEDUP2_DATA_RAM175", CMIC_LEDUP2_DATA_RAM175r }, \ 3002 { 0x000296c0, "CMIC_LEDUP2_DATA_RAM176", CMIC_LEDUP2_DATA_RAM176r }, \ 3003 { 0x000296c4, "CMIC_LEDUP2_DATA_RAM177", CMIC_LEDUP2_DATA_RAM177r }, \ 3004 { 0x000296c8, "CMIC_LEDUP2_DATA_RAM178", CMIC_LEDUP2_DATA_RAM178r }, \ 3005 { 0x000296cc, "CMIC_LEDUP2_DATA_RAM179", CMIC_LEDUP2_DATA_RAM179r }, \ 3006 { 0x000296d0, "CMIC_LEDUP2_DATA_RAM180", CMIC_LEDUP2_DATA_RAM180r }, \ 3007 { 0x000296d4, "CMIC_LEDUP2_DATA_RAM181", CMIC_LEDUP2_DATA_RAM181r }, \ 3008 { 0x000296d8, "CMIC_LEDUP2_DATA_RAM182", CMIC_LEDUP2_DATA_RAM182r }, \ 3009 { 0x000296dc, "CMIC_LEDUP2_DATA_RAM183", CMIC_LEDUP2_DATA_RAM183r }, \ 3010 { 0x000296e0, "CMIC_LEDUP2_DATA_RAM184", CMIC_LEDUP2_DATA_RAM184r }, \ 3011 { 0x000296e4, "CMIC_LEDUP2_DATA_RAM185", CMIC_LEDUP2_DATA_RAM185r }, \ 3012 { 0x000296e8, "CMIC_LEDUP2_DATA_RAM186", CMIC_LEDUP2_DATA_RAM186r }, \ 3013 { 0x000296ec, "CMIC_LEDUP2_DATA_RAM187", CMIC_LEDUP2_DATA_RAM187r }, \ 3014 { 0x000296f0, "CMIC_LEDUP2_DATA_RAM188", CMIC_LEDUP2_DATA_RAM188r }, \ 3015 { 0x000296f4, "CMIC_LEDUP2_DATA_RAM189", CMIC_LEDUP2_DATA_RAM189r }, \ 3016 { 0x000296f8, "CMIC_LEDUP2_DATA_RAM190", CMIC_LEDUP2_DATA_RAM190r }, \ 3017 { 0x000296fc, "CMIC_LEDUP2_DATA_RAM191", CMIC_LEDUP2_DATA_RAM191r }, \ 3018 { 0x00029700, "CMIC_LEDUP2_DATA_RAM192", CMIC_LEDUP2_DATA_RAM192r }, \ 3019 { 0x00029704, "CMIC_LEDUP2_DATA_RAM193", CMIC_LEDUP2_DATA_RAM193r }, \ 3020 { 0x00029708, "CMIC_LEDUP2_DATA_RAM194", CMIC_LEDUP2_DATA_RAM194r }, \ 3021 { 0x0002970c, "CMIC_LEDUP2_DATA_RAM195", CMIC_LEDUP2_DATA_RAM195r }, \ 3022 { 0x00029710, "CMIC_LEDUP2_DATA_RAM196", CMIC_LEDUP2_DATA_RAM196r }, \ 3023 { 0x00029714, "CMIC_LEDUP2_DATA_RAM197", CMIC_LEDUP2_DATA_RAM197r }, \ 3024 { 0x00029718, "CMIC_LEDUP2_DATA_RAM198", CMIC_LEDUP2_DATA_RAM198r }, \ 3025 { 0x0002971c, "CMIC_LEDUP2_DATA_RAM199", CMIC_LEDUP2_DATA_RAM199r }, \ 3026 { 0x00029720, "CMIC_LEDUP2_DATA_RAM200", CMIC_LEDUP2_DATA_RAM200r }, \ 3027 { 0x00029724, "CMIC_LEDUP2_DATA_RAM201", CMIC_LEDUP2_DATA_RAM201r }, \ 3028 { 0x00029728, "CMIC_LEDUP2_DATA_RAM202", CMIC_LEDUP2_DATA_RAM202r }, \ 3029 { 0x0002972c, "CMIC_LEDUP2_DATA_RAM203", CMIC_LEDUP2_DATA_RAM203r }, \ 3030 { 0x00029730, "CMIC_LEDUP2_DATA_RAM204", CMIC_LEDUP2_DATA_RAM204r }, \ 3031 { 0x00029734, "CMIC_LEDUP2_DATA_RAM205", CMIC_LEDUP2_DATA_RAM205r }, \ 3032 { 0x00029738, "CMIC_LEDUP2_DATA_RAM206", CMIC_LEDUP2_DATA_RAM206r }, \ 3033 { 0x0002973c, "CMIC_LEDUP2_DATA_RAM207", CMIC_LEDUP2_DATA_RAM207r }, \ 3034 { 0x00029740, "CMIC_LEDUP2_DATA_RAM208", CMIC_LEDUP2_DATA_RAM208r }, \ 3035 { 0x00029744, "CMIC_LEDUP2_DATA_RAM209", CMIC_LEDUP2_DATA_RAM209r }, \ 3036 { 0x00029748, "CMIC_LEDUP2_DATA_RAM210", CMIC_LEDUP2_DATA_RAM210r }, \ 3037 { 0x0002974c, "CMIC_LEDUP2_DATA_RAM211", CMIC_LEDUP2_DATA_RAM211r }, \ 3038 { 0x00029750, "CMIC_LEDUP2_DATA_RAM212", CMIC_LEDUP2_DATA_RAM212r }, \ 3039 { 0x00029754, "CMIC_LEDUP2_DATA_RAM213", CMIC_LEDUP2_DATA_RAM213r }, \ 3040 { 0x00029758, "CMIC_LEDUP2_DATA_RAM214", CMIC_LEDUP2_DATA_RAM214r }, \ 3041 { 0x0002975c, "CMIC_LEDUP2_DATA_RAM215", CMIC_LEDUP2_DATA_RAM215r }, \ 3042 { 0x00029760, "CMIC_LEDUP2_DATA_RAM216", CMIC_LEDUP2_DATA_RAM216r }, \ 3043 { 0x00029764, "CMIC_LEDUP2_DATA_RAM217", CMIC_LEDUP2_DATA_RAM217r }, \ 3044 { 0x00029768, "CMIC_LEDUP2_DATA_RAM218", CMIC_LEDUP2_DATA_RAM218r }, \ 3045 { 0x0002976c, "CMIC_LEDUP2_DATA_RAM219", CMIC_LEDUP2_DATA_RAM219r }, \ 3046 { 0x00029770, "CMIC_LEDUP2_DATA_RAM220", CMIC_LEDUP2_DATA_RAM220r }, \ 3047 { 0x00029774, "CMIC_LEDUP2_DATA_RAM221", CMIC_LEDUP2_DATA_RAM221r }, \ 3048 { 0x00029778, "CMIC_LEDUP2_DATA_RAM222", CMIC_LEDUP2_DATA_RAM222r }, \ 3049 { 0x0002977c, "CMIC_LEDUP2_DATA_RAM223", CMIC_LEDUP2_DATA_RAM223r }, \ 3050 { 0x00029780, "CMIC_LEDUP2_DATA_RAM224", CMIC_LEDUP2_DATA_RAM224r }, \ 3051 { 0x00029784, "CMIC_LEDUP2_DATA_RAM225", CMIC_LEDUP2_DATA_RAM225r }, \ 3052 { 0x00029788, "CMIC_LEDUP2_DATA_RAM226", CMIC_LEDUP2_DATA_RAM226r }, \ 3053 { 0x0002978c, "CMIC_LEDUP2_DATA_RAM227", CMIC_LEDUP2_DATA_RAM227r }, \ 3054 { 0x00029790, "CMIC_LEDUP2_DATA_RAM228", CMIC_LEDUP2_DATA_RAM228r }, \ 3055 { 0x00029794, "CMIC_LEDUP2_DATA_RAM229", CMIC_LEDUP2_DATA_RAM229r }, \ 3056 { 0x00029798, "CMIC_LEDUP2_DATA_RAM230", CMIC_LEDUP2_DATA_RAM230r }, \ 3057 { 0x0002979c, "CMIC_LEDUP2_DATA_RAM231", CMIC_LEDUP2_DATA_RAM231r }, \ 3058 { 0x000297a0, "CMIC_LEDUP2_DATA_RAM232", CMIC_LEDUP2_DATA_RAM232r }, \ 3059 { 0x000297a4, "CMIC_LEDUP2_DATA_RAM233", CMIC_LEDUP2_DATA_RAM233r }, \ 3060 { 0x000297a8, "CMIC_LEDUP2_DATA_RAM234", CMIC_LEDUP2_DATA_RAM234r }, \ 3061 { 0x000297ac, "CMIC_LEDUP2_DATA_RAM235", CMIC_LEDUP2_DATA_RAM235r }, \ 3062 { 0x000297b0, "CMIC_LEDUP2_DATA_RAM236", CMIC_LEDUP2_DATA_RAM236r }, \ 3063 { 0x000297b4, "CMIC_LEDUP2_DATA_RAM237", CMIC_LEDUP2_DATA_RAM237r }, \ 3064 { 0x000297b8, "CMIC_LEDUP2_DATA_RAM238", CMIC_LEDUP2_DATA_RAM238r }, \ 3065 { 0x000297bc, "CMIC_LEDUP2_DATA_RAM239", CMIC_LEDUP2_DATA_RAM239r }, \ 3066 { 0x000297c0, "CMIC_LEDUP2_DATA_RAM240", CMIC_LEDUP2_DATA_RAM240r }, \ 3067 { 0x000297c4, "CMIC_LEDUP2_DATA_RAM241", CMIC_LEDUP2_DATA_RAM241r }, \ 3068 { 0x000297c8, "CMIC_LEDUP2_DATA_RAM242", CMIC_LEDUP2_DATA_RAM242r }, \ 3069 { 0x000297cc, "CMIC_LEDUP2_DATA_RAM243", CMIC_LEDUP2_DATA_RAM243r }, \ 3070 { 0x000297d0, "CMIC_LEDUP2_DATA_RAM244", CMIC_LEDUP2_DATA_RAM244r }, \ 3071 { 0x000297d4, "CMIC_LEDUP2_DATA_RAM245", CMIC_LEDUP2_DATA_RAM245r }, \ 3072 { 0x000297d8, "CMIC_LEDUP2_DATA_RAM246", CMIC_LEDUP2_DATA_RAM246r }, \ 3073 { 0x000297dc, "CMIC_LEDUP2_DATA_RAM247", CMIC_LEDUP2_DATA_RAM247r }, \ 3074 { 0x000297e0, "CMIC_LEDUP2_DATA_RAM248", CMIC_LEDUP2_DATA_RAM248r }, \ 3075 { 0x000297e4, "CMIC_LEDUP2_DATA_RAM249", CMIC_LEDUP2_DATA_RAM249r }, \ 3076 { 0x000297e8, "CMIC_LEDUP2_DATA_RAM250", CMIC_LEDUP2_DATA_RAM250r }, \ 3077 { 0x000297ec, "CMIC_LEDUP2_DATA_RAM251", CMIC_LEDUP2_DATA_RAM251r }, \ 3078 { 0x000297f0, "CMIC_LEDUP2_DATA_RAM252", CMIC_LEDUP2_DATA_RAM252r }, \ 3079 { 0x000297f4, "CMIC_LEDUP2_DATA_RAM253", CMIC_LEDUP2_DATA_RAM253r }, \ 3080 { 0x000297f8, "CMIC_LEDUP2_DATA_RAM254", CMIC_LEDUP2_DATA_RAM254r }, \ 3081 { 0x000297fc, "CMIC_LEDUP2_DATA_RAM255", CMIC_LEDUP2_DATA_RAM255r }, \ 3082 { 0x00029800, "CMIC_LEDUP2_PROGRAM_RAM", CMIC_LEDUP2_PROGRAM_RAMr }, \ 3083 { 0x00029800, "CMIC_LEDUP2_PROGRAM_RAM0", CMIC_LEDUP2_PROGRAM_RAM0r }, \ 3084 { 0x00029804, "CMIC_LEDUP2_PROGRAM_RAM1", CMIC_LEDUP2_PROGRAM_RAM1r }, \ 3085 { 0x00029808, "CMIC_LEDUP2_PROGRAM_RAM2", CMIC_LEDUP2_PROGRAM_RAM2r }, \ 3086 { 0x0002980c, "CMIC_LEDUP2_PROGRAM_RAM3", CMIC_LEDUP2_PROGRAM_RAM3r }, \ 3087 { 0x00029810, "CMIC_LEDUP2_PROGRAM_RAM4", CMIC_LEDUP2_PROGRAM_RAM4r }, \ 3088 { 0x00029814, "CMIC_LEDUP2_PROGRAM_RAM5", CMIC_LEDUP2_PROGRAM_RAM5r }, \ 3089 { 0x00029818, "CMIC_LEDUP2_PROGRAM_RAM6", CMIC_LEDUP2_PROGRAM_RAM6r }, \ 3090 { 0x0002981c, "CMIC_LEDUP2_PROGRAM_RAM7", CMIC_LEDUP2_PROGRAM_RAM7r }, \ 3091 { 0x00029820, "CMIC_LEDUP2_PROGRAM_RAM8", CMIC_LEDUP2_PROGRAM_RAM8r }, \ 3092 { 0x00029824, "CMIC_LEDUP2_PROGRAM_RAM9", CMIC_LEDUP2_PROGRAM_RAM9r }, \ 3093 { 0x00029828, "CMIC_LEDUP2_PROGRAM_RAM10", CMIC_LEDUP2_PROGRAM_RAM10r }, \ 3094 { 0x0002982c, "CMIC_LEDUP2_PROGRAM_RAM11", CMIC_LEDUP2_PROGRAM_RAM11r }, \ 3095 { 0x00029830, "CMIC_LEDUP2_PROGRAM_RAM12", CMIC_LEDUP2_PROGRAM_RAM12r }, \ 3096 { 0x00029834, "CMIC_LEDUP2_PROGRAM_RAM13", CMIC_LEDUP2_PROGRAM_RAM13r }, \ 3097 { 0x00029838, "CMIC_LEDUP2_PROGRAM_RAM14", CMIC_LEDUP2_PROGRAM_RAM14r }, \ 3098 { 0x0002983c, "CMIC_LEDUP2_PROGRAM_RAM15", CMIC_LEDUP2_PROGRAM_RAM15r }, \ 3099 { 0x00029840, "CMIC_LEDUP2_PROGRAM_RAM16", CMIC_LEDUP2_PROGRAM_RAM16r }, \ 3100 { 0x00029844, "CMIC_LEDUP2_PROGRAM_RAM17", CMIC_LEDUP2_PROGRAM_RAM17r }, \ 3101 { 0x00029848, "CMIC_LEDUP2_PROGRAM_RAM18", CMIC_LEDUP2_PROGRAM_RAM18r }, \ 3102 { 0x0002984c, "CMIC_LEDUP2_PROGRAM_RAM19", CMIC_LEDUP2_PROGRAM_RAM19r }, \ 3103 { 0x00029850, "CMIC_LEDUP2_PROGRAM_RAM20", CMIC_LEDUP2_PROGRAM_RAM20r }, \ 3104 { 0x00029854, "CMIC_LEDUP2_PROGRAM_RAM21", CMIC_LEDUP2_PROGRAM_RAM21r }, \ 3105 { 0x00029858, "CMIC_LEDUP2_PROGRAM_RAM22", CMIC_LEDUP2_PROGRAM_RAM22r }, \ 3106 { 0x0002985c, "CMIC_LEDUP2_PROGRAM_RAM23", CMIC_LEDUP2_PROGRAM_RAM23r }, \ 3107 { 0x00029860, "CMIC_LEDUP2_PROGRAM_RAM24", CMIC_LEDUP2_PROGRAM_RAM24r }, \ 3108 { 0x00029864, "CMIC_LEDUP2_PROGRAM_RAM25", CMIC_LEDUP2_PROGRAM_RAM25r }, \ 3109 { 0x00029868, "CMIC_LEDUP2_PROGRAM_RAM26", CMIC_LEDUP2_PROGRAM_RAM26r }, \ 3110 { 0x0002986c, "CMIC_LEDUP2_PROGRAM_RAM27", CMIC_LEDUP2_PROGRAM_RAM27r }, \ 3111 { 0x00029870, "CMIC_LEDUP2_PROGRAM_RAM28", CMIC_LEDUP2_PROGRAM_RAM28r }, \ 3112 { 0x00029874, "CMIC_LEDUP2_PROGRAM_RAM29", CMIC_LEDUP2_PROGRAM_RAM29r }, \ 3113 { 0x00029878, "CMIC_LEDUP2_PROGRAM_RAM30", CMIC_LEDUP2_PROGRAM_RAM30r }, \ 3114 { 0x0002987c, "CMIC_LEDUP2_PROGRAM_RAM31", CMIC_LEDUP2_PROGRAM_RAM31r }, \ 3115 { 0x00029880, "CMIC_LEDUP2_PROGRAM_RAM32", CMIC_LEDUP2_PROGRAM_RAM32r }, \ 3116 { 0x00029884, "CMIC_LEDUP2_PROGRAM_RAM33", CMIC_LEDUP2_PROGRAM_RAM33r }, \ 3117 { 0x00029888, "CMIC_LEDUP2_PROGRAM_RAM34", CMIC_LEDUP2_PROGRAM_RAM34r }, \ 3118 { 0x0002988c, "CMIC_LEDUP2_PROGRAM_RAM35", CMIC_LEDUP2_PROGRAM_RAM35r }, \ 3119 { 0x00029890, "CMIC_LEDUP2_PROGRAM_RAM36", CMIC_LEDUP2_PROGRAM_RAM36r }, \ 3120 { 0x00029894, "CMIC_LEDUP2_PROGRAM_RAM37", CMIC_LEDUP2_PROGRAM_RAM37r }, \ 3121 { 0x00029898, "CMIC_LEDUP2_PROGRAM_RAM38", CMIC_LEDUP2_PROGRAM_RAM38r }, \ 3122 { 0x0002989c, "CMIC_LEDUP2_PROGRAM_RAM39", CMIC_LEDUP2_PROGRAM_RAM39r }, \ 3123 { 0x000298a0, "CMIC_LEDUP2_PROGRAM_RAM40", CMIC_LEDUP2_PROGRAM_RAM40r }, \ 3124 { 0x000298a4, "CMIC_LEDUP2_PROGRAM_RAM41", CMIC_LEDUP2_PROGRAM_RAM41r }, \ 3125 { 0x000298a8, "CMIC_LEDUP2_PROGRAM_RAM42", CMIC_LEDUP2_PROGRAM_RAM42r }, \ 3126 { 0x000298ac, "CMIC_LEDUP2_PROGRAM_RAM43", CMIC_LEDUP2_PROGRAM_RAM43r }, \ 3127 { 0x000298b0, "CMIC_LEDUP2_PROGRAM_RAM44", CMIC_LEDUP2_PROGRAM_RAM44r }, \ 3128 { 0x000298b4, "CMIC_LEDUP2_PROGRAM_RAM45", CMIC_LEDUP2_PROGRAM_RAM45r }, \ 3129 { 0x000298b8, "CMIC_LEDUP2_PROGRAM_RAM46", CMIC_LEDUP2_PROGRAM_RAM46r }, \ 3130 { 0x000298bc, "CMIC_LEDUP2_PROGRAM_RAM47", CMIC_LEDUP2_PROGRAM_RAM47r }, \ 3131 { 0x000298c0, "CMIC_LEDUP2_PROGRAM_RAM48", CMIC_LEDUP2_PROGRAM_RAM48r }, \ 3132 { 0x000298c4, "CMIC_LEDUP2_PROGRAM_RAM49", CMIC_LEDUP2_PROGRAM_RAM49r }, \ 3133 { 0x000298c8, "CMIC_LEDUP2_PROGRAM_RAM50", CMIC_LEDUP2_PROGRAM_RAM50r }, \ 3134 { 0x000298cc, "CMIC_LEDUP2_PROGRAM_RAM51", CMIC_LEDUP2_PROGRAM_RAM51r }, \ 3135 { 0x000298d0, "CMIC_LEDUP2_PROGRAM_RAM52", CMIC_LEDUP2_PROGRAM_RAM52r }, \ 3136 { 0x000298d4, "CMIC_LEDUP2_PROGRAM_RAM53", CMIC_LEDUP2_PROGRAM_RAM53r }, \ 3137 { 0x000298d8, "CMIC_LEDUP2_PROGRAM_RAM54", CMIC_LEDUP2_PROGRAM_RAM54r }, \ 3138 { 0x000298dc, "CMIC_LEDUP2_PROGRAM_RAM55", CMIC_LEDUP2_PROGRAM_RAM55r }, \ 3139 { 0x000298e0, "CMIC_LEDUP2_PROGRAM_RAM56", CMIC_LEDUP2_PROGRAM_RAM56r }, \ 3140 { 0x000298e4, "CMIC_LEDUP2_PROGRAM_RAM57", CMIC_LEDUP2_PROGRAM_RAM57r }, \ 3141 { 0x000298e8, "CMIC_LEDUP2_PROGRAM_RAM58", CMIC_LEDUP2_PROGRAM_RAM58r }, \ 3142 { 0x000298ec, "CMIC_LEDUP2_PROGRAM_RAM59", CMIC_LEDUP2_PROGRAM_RAM59r }, \ 3143 { 0x000298f0, "CMIC_LEDUP2_PROGRAM_RAM60", CMIC_LEDUP2_PROGRAM_RAM60r }, \ 3144 { 0x000298f4, "CMIC_LEDUP2_PROGRAM_RAM61", CMIC_LEDUP2_PROGRAM_RAM61r }, \ 3145 { 0x000298f8, "CMIC_LEDUP2_PROGRAM_RAM62", CMIC_LEDUP2_PROGRAM_RAM62r }, \ 3146 { 0x000298fc, "CMIC_LEDUP2_PROGRAM_RAM63", CMIC_LEDUP2_PROGRAM_RAM63r }, \ 3147 { 0x00029900, "CMIC_LEDUP2_PROGRAM_RAM64", CMIC_LEDUP2_PROGRAM_RAM64r }, \ 3148 { 0x00029904, "CMIC_LEDUP2_PROGRAM_RAM65", CMIC_LEDUP2_PROGRAM_RAM65r }, \ 3149 { 0x00029908, "CMIC_LEDUP2_PROGRAM_RAM66", CMIC_LEDUP2_PROGRAM_RAM66r }, \ 3150 { 0x0002990c, "CMIC_LEDUP2_PROGRAM_RAM67", CMIC_LEDUP2_PROGRAM_RAM67r }, \ 3151 { 0x00029910, "CMIC_LEDUP2_PROGRAM_RAM68", CMIC_LEDUP2_PROGRAM_RAM68r }, \ 3152 { 0x00029914, "CMIC_LEDUP2_PROGRAM_RAM69", CMIC_LEDUP2_PROGRAM_RAM69r }, \ 3153 { 0x00029918, "CMIC_LEDUP2_PROGRAM_RAM70", CMIC_LEDUP2_PROGRAM_RAM70r }, \ 3154 { 0x0002991c, "CMIC_LEDUP2_PROGRAM_RAM71", CMIC_LEDUP2_PROGRAM_RAM71r }, \ 3155 { 0x00029920, "CMIC_LEDUP2_PROGRAM_RAM72", CMIC_LEDUP2_PROGRAM_RAM72r }, \ 3156 { 0x00029924, "CMIC_LEDUP2_PROGRAM_RAM73", CMIC_LEDUP2_PROGRAM_RAM73r }, \ 3157 { 0x00029928, "CMIC_LEDUP2_PROGRAM_RAM74", CMIC_LEDUP2_PROGRAM_RAM74r }, \ 3158 { 0x0002992c, "CMIC_LEDUP2_PROGRAM_RAM75", CMIC_LEDUP2_PROGRAM_RAM75r }, \ 3159 { 0x00029930, "CMIC_LEDUP2_PROGRAM_RAM76", CMIC_LEDUP2_PROGRAM_RAM76r }, \ 3160 { 0x00029934, "CMIC_LEDUP2_PROGRAM_RAM77", CMIC_LEDUP2_PROGRAM_RAM77r }, \ 3161 { 0x00029938, "CMIC_LEDUP2_PROGRAM_RAM78", CMIC_LEDUP2_PROGRAM_RAM78r }, \ 3162 { 0x0002993c, "CMIC_LEDUP2_PROGRAM_RAM79", CMIC_LEDUP2_PROGRAM_RAM79r }, \ 3163 { 0x00029940, "CMIC_LEDUP2_PROGRAM_RAM80", CMIC_LEDUP2_PROGRAM_RAM80r }, \ 3164 { 0x00029944, "CMIC_LEDUP2_PROGRAM_RAM81", CMIC_LEDUP2_PROGRAM_RAM81r }, \ 3165 { 0x00029948, "CMIC_LEDUP2_PROGRAM_RAM82", CMIC_LEDUP2_PROGRAM_RAM82r }, \ 3166 { 0x0002994c, "CMIC_LEDUP2_PROGRAM_RAM83", CMIC_LEDUP2_PROGRAM_RAM83r }, \ 3167 { 0x00029950, "CMIC_LEDUP2_PROGRAM_RAM84", CMIC_LEDUP2_PROGRAM_RAM84r }, \ 3168 { 0x00029954, "CMIC_LEDUP2_PROGRAM_RAM85", CMIC_LEDUP2_PROGRAM_RAM85r }, \ 3169 { 0x00029958, "CMIC_LEDUP2_PROGRAM_RAM86", CMIC_LEDUP2_PROGRAM_RAM86r }, \ 3170 { 0x0002995c, "CMIC_LEDUP2_PROGRAM_RAM87", CMIC_LEDUP2_PROGRAM_RAM87r }, \ 3171 { 0x00029960, "CMIC_LEDUP2_PROGRAM_RAM88", CMIC_LEDUP2_PROGRAM_RAM88r }, \ 3172 { 0x00029964, "CMIC_LEDUP2_PROGRAM_RAM89", CMIC_LEDUP2_PROGRAM_RAM89r }, \ 3173 { 0x00029968, "CMIC_LEDUP2_PROGRAM_RAM90", CMIC_LEDUP2_PROGRAM_RAM90r }, \ 3174 { 0x0002996c, "CMIC_LEDUP2_PROGRAM_RAM91", CMIC_LEDUP2_PROGRAM_RAM91r }, \ 3175 { 0x00029970, "CMIC_LEDUP2_PROGRAM_RAM92", CMIC_LEDUP2_PROGRAM_RAM92r }, \ 3176 { 0x00029974, "CMIC_LEDUP2_PROGRAM_RAM93", CMIC_LEDUP2_PROGRAM_RAM93r }, \ 3177 { 0x00029978, "CMIC_LEDUP2_PROGRAM_RAM94", CMIC_LEDUP2_PROGRAM_RAM94r }, \ 3178 { 0x0002997c, "CMIC_LEDUP2_PROGRAM_RAM95", CMIC_LEDUP2_PROGRAM_RAM95r }, \ 3179 { 0x00029980, "CMIC_LEDUP2_PROGRAM_RAM96", CMIC_LEDUP2_PROGRAM_RAM96r }, \ 3180 { 0x00029984, "CMIC_LEDUP2_PROGRAM_RAM97", CMIC_LEDUP2_PROGRAM_RAM97r }, \ 3181 { 0x00029988, "CMIC_LEDUP2_PROGRAM_RAM98", CMIC_LEDUP2_PROGRAM_RAM98r }, \ 3182 { 0x0002998c, "CMIC_LEDUP2_PROGRAM_RAM99", CMIC_LEDUP2_PROGRAM_RAM99r }, \ 3183 { 0x00029990, "CMIC_LEDUP2_PROGRAM_RAM100", CMIC_LEDUP2_PROGRAM_RAM100r }, \ 3184 { 0x00029994, "CMIC_LEDUP2_PROGRAM_RAM101", CMIC_LEDUP2_PROGRAM_RAM101r }, \ 3185 { 0x00029998, "CMIC_LEDUP2_PROGRAM_RAM102", CMIC_LEDUP2_PROGRAM_RAM102r }, \ 3186 { 0x0002999c, "CMIC_LEDUP2_PROGRAM_RAM103", CMIC_LEDUP2_PROGRAM_RAM103r }, \ 3187 { 0x000299a0, "CMIC_LEDUP2_PROGRAM_RAM104", CMIC_LEDUP2_PROGRAM_RAM104r }, \ 3188 { 0x000299a4, "CMIC_LEDUP2_PROGRAM_RAM105", CMIC_LEDUP2_PROGRAM_RAM105r }, \ 3189 { 0x000299a8, "CMIC_LEDUP2_PROGRAM_RAM106", CMIC_LEDUP2_PROGRAM_RAM106r }, \ 3190 { 0x000299ac, "CMIC_LEDUP2_PROGRAM_RAM107", CMIC_LEDUP2_PROGRAM_RAM107r }, \ 3191 { 0x000299b0, "CMIC_LEDUP2_PROGRAM_RAM108", CMIC_LEDUP2_PROGRAM_RAM108r }, \ 3192 { 0x000299b4, "CMIC_LEDUP2_PROGRAM_RAM109", CMIC_LEDUP2_PROGRAM_RAM109r }, \ 3193 { 0x000299b8, "CMIC_LEDUP2_PROGRAM_RAM110", CMIC_LEDUP2_PROGRAM_RAM110r }, \ 3194 { 0x000299bc, "CMIC_LEDUP2_PROGRAM_RAM111", CMIC_LEDUP2_PROGRAM_RAM111r }, \ 3195 { 0x000299c0, "CMIC_LEDUP2_PROGRAM_RAM112", CMIC_LEDUP2_PROGRAM_RAM112r }, \ 3196 { 0x000299c4, "CMIC_LEDUP2_PROGRAM_RAM113", CMIC_LEDUP2_PROGRAM_RAM113r }, \ 3197 { 0x000299c8, "CMIC_LEDUP2_PROGRAM_RAM114", CMIC_LEDUP2_PROGRAM_RAM114r }, \ 3198 { 0x000299cc, "CMIC_LEDUP2_PROGRAM_RAM115", CMIC_LEDUP2_PROGRAM_RAM115r }, \ 3199 { 0x000299d0, "CMIC_LEDUP2_PROGRAM_RAM116", CMIC_LEDUP2_PROGRAM_RAM116r }, \ 3200 { 0x000299d4, "CMIC_LEDUP2_PROGRAM_RAM117", CMIC_LEDUP2_PROGRAM_RAM117r }, \ 3201 { 0x000299d8, "CMIC_LEDUP2_PROGRAM_RAM118", CMIC_LEDUP2_PROGRAM_RAM118r }, \ 3202 { 0x000299dc, "CMIC_LEDUP2_PROGRAM_RAM119", CMIC_LEDUP2_PROGRAM_RAM119r }, \ 3203 { 0x000299e0, "CMIC_LEDUP2_PROGRAM_RAM120", CMIC_LEDUP2_PROGRAM_RAM120r }, \ 3204 { 0x000299e4, "CMIC_LEDUP2_PROGRAM_RAM121", CMIC_LEDUP2_PROGRAM_RAM121r }, \ 3205 { 0x000299e8, "CMIC_LEDUP2_PROGRAM_RAM122", CMIC_LEDUP2_PROGRAM_RAM122r }, \ 3206 { 0x000299ec, "CMIC_LEDUP2_PROGRAM_RAM123", CMIC_LEDUP2_PROGRAM_RAM123r }, \ 3207 { 0x000299f0, "CMIC_LEDUP2_PROGRAM_RAM124", CMIC_LEDUP2_PROGRAM_RAM124r }, \ 3208 { 0x000299f4, "CMIC_LEDUP2_PROGRAM_RAM125", CMIC_LEDUP2_PROGRAM_RAM125r }, \ 3209 { 0x000299f8, "CMIC_LEDUP2_PROGRAM_RAM126", CMIC_LEDUP2_PROGRAM_RAM126r }, \ 3210 { 0x000299fc, "CMIC_LEDUP2_PROGRAM_RAM127", CMIC_LEDUP2_PROGRAM_RAM127r }, \ 3211 { 0x00029a00, "CMIC_LEDUP2_PROGRAM_RAM128", CMIC_LEDUP2_PROGRAM_RAM128r }, \ 3212 { 0x00029a04, "CMIC_LEDUP2_PROGRAM_RAM129", CMIC_LEDUP2_PROGRAM_RAM129r }, \ 3213 { 0x00029a08, "CMIC_LEDUP2_PROGRAM_RAM130", CMIC_LEDUP2_PROGRAM_RAM130r }, \ 3214 { 0x00029a0c, "CMIC_LEDUP2_PROGRAM_RAM131", CMIC_LEDUP2_PROGRAM_RAM131r }, \ 3215 { 0x00029a10, "CMIC_LEDUP2_PROGRAM_RAM132", CMIC_LEDUP2_PROGRAM_RAM132r }, \ 3216 { 0x00029a14, "CMIC_LEDUP2_PROGRAM_RAM133", CMIC_LEDUP2_PROGRAM_RAM133r }, \ 3217 { 0x00029a18, "CMIC_LEDUP2_PROGRAM_RAM134", CMIC_LEDUP2_PROGRAM_RAM134r }, \ 3218 { 0x00029a1c, "CMIC_LEDUP2_PROGRAM_RAM135", CMIC_LEDUP2_PROGRAM_RAM135r }, \ 3219 { 0x00029a20, "CMIC_LEDUP2_PROGRAM_RAM136", CMIC_LEDUP2_PROGRAM_RAM136r }, \ 3220 { 0x00029a24, "CMIC_LEDUP2_PROGRAM_RAM137", CMIC_LEDUP2_PROGRAM_RAM137r }, \ 3221 { 0x00029a28, "CMIC_LEDUP2_PROGRAM_RAM138", CMIC_LEDUP2_PROGRAM_RAM138r }, \ 3222 { 0x00029a2c, "CMIC_LEDUP2_PROGRAM_RAM139", CMIC_LEDUP2_PROGRAM_RAM139r }, \ 3223 { 0x00029a30, "CMIC_LEDUP2_PROGRAM_RAM140", CMIC_LEDUP2_PROGRAM_RAM140r }, \ 3224 { 0x00029a34, "CMIC_LEDUP2_PROGRAM_RAM141", CMIC_LEDUP2_PROGRAM_RAM141r }, \ 3225 { 0x00029a38, "CMIC_LEDUP2_PROGRAM_RAM142", CMIC_LEDUP2_PROGRAM_RAM142r }, \ 3226 { 0x00029a3c, "CMIC_LEDUP2_PROGRAM_RAM143", CMIC_LEDUP2_PROGRAM_RAM143r }, \ 3227 { 0x00029a40, "CMIC_LEDUP2_PROGRAM_RAM144", CMIC_LEDUP2_PROGRAM_RAM144r }, \ 3228 { 0x00029a44, "CMIC_LEDUP2_PROGRAM_RAM145", CMIC_LEDUP2_PROGRAM_RAM145r }, \ 3229 { 0x00029a48, "CMIC_LEDUP2_PROGRAM_RAM146", CMIC_LEDUP2_PROGRAM_RAM146r }, \ 3230 { 0x00029a4c, "CMIC_LEDUP2_PROGRAM_RAM147", CMIC_LEDUP2_PROGRAM_RAM147r }, \ 3231 { 0x00029a50, "CMIC_LEDUP2_PROGRAM_RAM148", CMIC_LEDUP2_PROGRAM_RAM148r }, \ 3232 { 0x00029a54, "CMIC_LEDUP2_PROGRAM_RAM149", CMIC_LEDUP2_PROGRAM_RAM149r }, \ 3233 { 0x00029a58, "CMIC_LEDUP2_PROGRAM_RAM150", CMIC_LEDUP2_PROGRAM_RAM150r }, \ 3234 { 0x00029a5c, "CMIC_LEDUP2_PROGRAM_RAM151", CMIC_LEDUP2_PROGRAM_RAM151r }, \ 3235 { 0x00029a60, "CMIC_LEDUP2_PROGRAM_RAM152", CMIC_LEDUP2_PROGRAM_RAM152r }, \ 3236 { 0x00029a64, "CMIC_LEDUP2_PROGRAM_RAM153", CMIC_LEDUP2_PROGRAM_RAM153r }, \ 3237 { 0x00029a68, "CMIC_LEDUP2_PROGRAM_RAM154", CMIC_LEDUP2_PROGRAM_RAM154r }, \ 3238 { 0x00029a6c, "CMIC_LEDUP2_PROGRAM_RAM155", CMIC_LEDUP2_PROGRAM_RAM155r }, \ 3239 { 0x00029a70, "CMIC_LEDUP2_PROGRAM_RAM156", CMIC_LEDUP2_PROGRAM_RAM156r }, \ 3240 { 0x00029a74, "CMIC_LEDUP2_PROGRAM_RAM157", CMIC_LEDUP2_PROGRAM_RAM157r }, \ 3241 { 0x00029a78, "CMIC_LEDUP2_PROGRAM_RAM158", CMIC_LEDUP2_PROGRAM_RAM158r }, \ 3242 { 0x00029a7c, "CMIC_LEDUP2_PROGRAM_RAM159", CMIC_LEDUP2_PROGRAM_RAM159r }, \ 3243 { 0x00029a80, "CMIC_LEDUP2_PROGRAM_RAM160", CMIC_LEDUP2_PROGRAM_RAM160r }, \ 3244 { 0x00029a84, "CMIC_LEDUP2_PROGRAM_RAM161", CMIC_LEDUP2_PROGRAM_RAM161r }, \ 3245 { 0x00029a88, "CMIC_LEDUP2_PROGRAM_RAM162", CMIC_LEDUP2_PROGRAM_RAM162r }, \ 3246 { 0x00029a8c, "CMIC_LEDUP2_PROGRAM_RAM163", CMIC_LEDUP2_PROGRAM_RAM163r }, \ 3247 { 0x00029a90, "CMIC_LEDUP2_PROGRAM_RAM164", CMIC_LEDUP2_PROGRAM_RAM164r }, \ 3248 { 0x00029a94, "CMIC_LEDUP2_PROGRAM_RAM165", CMIC_LEDUP2_PROGRAM_RAM165r }, \ 3249 { 0x00029a98, "CMIC_LEDUP2_PROGRAM_RAM166", CMIC_LEDUP2_PROGRAM_RAM166r }, \ 3250 { 0x00029a9c, "CMIC_LEDUP2_PROGRAM_RAM167", CMIC_LEDUP2_PROGRAM_RAM167r }, \ 3251 { 0x00029aa0, "CMIC_LEDUP2_PROGRAM_RAM168", CMIC_LEDUP2_PROGRAM_RAM168r }, \ 3252 { 0x00029aa4, "CMIC_LEDUP2_PROGRAM_RAM169", CMIC_LEDUP2_PROGRAM_RAM169r }, \ 3253 { 0x00029aa8, "CMIC_LEDUP2_PROGRAM_RAM170", CMIC_LEDUP2_PROGRAM_RAM170r }, \ 3254 { 0x00029aac, "CMIC_LEDUP2_PROGRAM_RAM171", CMIC_LEDUP2_PROGRAM_RAM171r }, \ 3255 { 0x00029ab0, "CMIC_LEDUP2_PROGRAM_RAM172", CMIC_LEDUP2_PROGRAM_RAM172r }, \ 3256 { 0x00029ab4, "CMIC_LEDUP2_PROGRAM_RAM173", CMIC_LEDUP2_PROGRAM_RAM173r }, \ 3257 { 0x00029ab8, "CMIC_LEDUP2_PROGRAM_RAM174", CMIC_LEDUP2_PROGRAM_RAM174r }, \ 3258 { 0x00029abc, "CMIC_LEDUP2_PROGRAM_RAM175", CMIC_LEDUP2_PROGRAM_RAM175r }, \ 3259 { 0x00029ac0, "CMIC_LEDUP2_PROGRAM_RAM176", CMIC_LEDUP2_PROGRAM_RAM176r }, \ 3260 { 0x00029ac4, "CMIC_LEDUP2_PROGRAM_RAM177", CMIC_LEDUP2_PROGRAM_RAM177r }, \ 3261 { 0x00029ac8, "CMIC_LEDUP2_PROGRAM_RAM178", CMIC_LEDUP2_PROGRAM_RAM178r }, \ 3262 { 0x00029acc, "CMIC_LEDUP2_PROGRAM_RAM179", CMIC_LEDUP2_PROGRAM_RAM179r }, \ 3263 { 0x00029ad0, "CMIC_LEDUP2_PROGRAM_RAM180", CMIC_LEDUP2_PROGRAM_RAM180r }, \ 3264 { 0x00029ad4, "CMIC_LEDUP2_PROGRAM_RAM181", CMIC_LEDUP2_PROGRAM_RAM181r }, \ 3265 { 0x00029ad8, "CMIC_LEDUP2_PROGRAM_RAM182", CMIC_LEDUP2_PROGRAM_RAM182r }, \ 3266 { 0x00029adc, "CMIC_LEDUP2_PROGRAM_RAM183", CMIC_LEDUP2_PROGRAM_RAM183r }, \ 3267 { 0x00029ae0, "CMIC_LEDUP2_PROGRAM_RAM184", CMIC_LEDUP2_PROGRAM_RAM184r }, \ 3268 { 0x00029ae4, "CMIC_LEDUP2_PROGRAM_RAM185", CMIC_LEDUP2_PROGRAM_RAM185r }, \ 3269 { 0x00029ae8, "CMIC_LEDUP2_PROGRAM_RAM186", CMIC_LEDUP2_PROGRAM_RAM186r }, \ 3270 { 0x00029aec, "CMIC_LEDUP2_PROGRAM_RAM187", CMIC_LEDUP2_PROGRAM_RAM187r }, \ 3271 { 0x00029af0, "CMIC_LEDUP2_PROGRAM_RAM188", CMIC_LEDUP2_PROGRAM_RAM188r }, \ 3272 { 0x00029af4, "CMIC_LEDUP2_PROGRAM_RAM189", CMIC_LEDUP2_PROGRAM_RAM189r }, \ 3273 { 0x00029af8, "CMIC_LEDUP2_PROGRAM_RAM190", CMIC_LEDUP2_PROGRAM_RAM190r }, \ 3274 { 0x00029afc, "CMIC_LEDUP2_PROGRAM_RAM191", CMIC_LEDUP2_PROGRAM_RAM191r }, \ 3275 { 0x00029b00, "CMIC_LEDUP2_PROGRAM_RAM192", CMIC_LEDUP2_PROGRAM_RAM192r }, \ 3276 { 0x00029b04, "CMIC_LEDUP2_PROGRAM_RAM193", CMIC_LEDUP2_PROGRAM_RAM193r }, \ 3277 { 0x00029b08, "CMIC_LEDUP2_PROGRAM_RAM194", CMIC_LEDUP2_PROGRAM_RAM194r }, \ 3278 { 0x00029b0c, "CMIC_LEDUP2_PROGRAM_RAM195", CMIC_LEDUP2_PROGRAM_RAM195r }, \ 3279 { 0x00029b10, "CMIC_LEDUP2_PROGRAM_RAM196", CMIC_LEDUP2_PROGRAM_RAM196r }, \ 3280 { 0x00029b14, "CMIC_LEDUP2_PROGRAM_RAM197", CMIC_LEDUP2_PROGRAM_RAM197r }, \ 3281 { 0x00029b18, "CMIC_LEDUP2_PROGRAM_RAM198", CMIC_LEDUP2_PROGRAM_RAM198r }, \ 3282 { 0x00029b1c, "CMIC_LEDUP2_PROGRAM_RAM199", CMIC_LEDUP2_PROGRAM_RAM199r }, \ 3283 { 0x00029b20, "CMIC_LEDUP2_PROGRAM_RAM200", CMIC_LEDUP2_PROGRAM_RAM200r }, \ 3284 { 0x00029b24, "CMIC_LEDUP2_PROGRAM_RAM201", CMIC_LEDUP2_PROGRAM_RAM201r }, \ 3285 { 0x00029b28, "CMIC_LEDUP2_PROGRAM_RAM202", CMIC_LEDUP2_PROGRAM_RAM202r }, \ 3286 { 0x00029b2c, "CMIC_LEDUP2_PROGRAM_RAM203", CMIC_LEDUP2_PROGRAM_RAM203r }, \ 3287 { 0x00029b30, "CMIC_LEDUP2_PROGRAM_RAM204", CMIC_LEDUP2_PROGRAM_RAM204r }, \ 3288 { 0x00029b34, "CMIC_LEDUP2_PROGRAM_RAM205", CMIC_LEDUP2_PROGRAM_RAM205r }, \ 3289 { 0x00029b38, "CMIC_LEDUP2_PROGRAM_RAM206", CMIC_LEDUP2_PROGRAM_RAM206r }, \ 3290 { 0x00029b3c, "CMIC_LEDUP2_PROGRAM_RAM207", CMIC_LEDUP2_PROGRAM_RAM207r }, \ 3291 { 0x00029b40, "CMIC_LEDUP2_PROGRAM_RAM208", CMIC_LEDUP2_PROGRAM_RAM208r }, \ 3292 { 0x00029b44, "CMIC_LEDUP2_PROGRAM_RAM209", CMIC_LEDUP2_PROGRAM_RAM209r }, \ 3293 { 0x00029b48, "CMIC_LEDUP2_PROGRAM_RAM210", CMIC_LEDUP2_PROGRAM_RAM210r }, \ 3294 { 0x00029b4c, "CMIC_LEDUP2_PROGRAM_RAM211", CMIC_LEDUP2_PROGRAM_RAM211r }, \ 3295 { 0x00029b50, "CMIC_LEDUP2_PROGRAM_RAM212", CMIC_LEDUP2_PROGRAM_RAM212r }, \ 3296 { 0x00029b54, "CMIC_LEDUP2_PROGRAM_RAM213", CMIC_LEDUP2_PROGRAM_RAM213r }, \ 3297 { 0x00029b58, "CMIC_LEDUP2_PROGRAM_RAM214", CMIC_LEDUP2_PROGRAM_RAM214r }, \ 3298 { 0x00029b5c, "CMIC_LEDUP2_PROGRAM_RAM215", CMIC_LEDUP2_PROGRAM_RAM215r }, \ 3299 { 0x00029b60, "CMIC_LEDUP2_PROGRAM_RAM216", CMIC_LEDUP2_PROGRAM_RAM216r }, \ 3300 { 0x00029b64, "CMIC_LEDUP2_PROGRAM_RAM217", CMIC_LEDUP2_PROGRAM_RAM217r }, \ 3301 { 0x00029b68, "CMIC_LEDUP2_PROGRAM_RAM218", CMIC_LEDUP2_PROGRAM_RAM218r }, \ 3302 { 0x00029b6c, "CMIC_LEDUP2_PROGRAM_RAM219", CMIC_LEDUP2_PROGRAM_RAM219r }, \ 3303 { 0x00029b70, "CMIC_LEDUP2_PROGRAM_RAM220", CMIC_LEDUP2_PROGRAM_RAM220r }, \ 3304 { 0x00029b74, "CMIC_LEDUP2_PROGRAM_RAM221", CMIC_LEDUP2_PROGRAM_RAM221r }, \ 3305 { 0x00029b78, "CMIC_LEDUP2_PROGRAM_RAM222", CMIC_LEDUP2_PROGRAM_RAM222r }, \ 3306 { 0x00029b7c, "CMIC_LEDUP2_PROGRAM_RAM223", CMIC_LEDUP2_PROGRAM_RAM223r }, \ 3307 { 0x00029b80, "CMIC_LEDUP2_PROGRAM_RAM224", CMIC_LEDUP2_PROGRAM_RAM224r }, \ 3308 { 0x00029b84, "CMIC_LEDUP2_PROGRAM_RAM225", CMIC_LEDUP2_PROGRAM_RAM225r }, \ 3309 { 0x00029b88, "CMIC_LEDUP2_PROGRAM_RAM226", CMIC_LEDUP2_PROGRAM_RAM226r }, \ 3310 { 0x00029b8c, "CMIC_LEDUP2_PROGRAM_RAM227", CMIC_LEDUP2_PROGRAM_RAM227r }, \ 3311 { 0x00029b90, "CMIC_LEDUP2_PROGRAM_RAM228", CMIC_LEDUP2_PROGRAM_RAM228r }, \ 3312 { 0x00029b94, "CMIC_LEDUP2_PROGRAM_RAM229", CMIC_LEDUP2_PROGRAM_RAM229r }, \ 3313 { 0x00029b98, "CMIC_LEDUP2_PROGRAM_RAM230", CMIC_LEDUP2_PROGRAM_RAM230r }, \ 3314 { 0x00029b9c, "CMIC_LEDUP2_PROGRAM_RAM231", CMIC_LEDUP2_PROGRAM_RAM231r }, \ 3315 { 0x00029ba0, "CMIC_LEDUP2_PROGRAM_RAM232", CMIC_LEDUP2_PROGRAM_RAM232r }, \ 3316 { 0x00029ba4, "CMIC_LEDUP2_PROGRAM_RAM233", CMIC_LEDUP2_PROGRAM_RAM233r }, \ 3317 { 0x00029ba8, "CMIC_LEDUP2_PROGRAM_RAM234", CMIC_LEDUP2_PROGRAM_RAM234r }, \ 3318 { 0x00029bac, "CMIC_LEDUP2_PROGRAM_RAM235", CMIC_LEDUP2_PROGRAM_RAM235r }, \ 3319 { 0x00029bb0, "CMIC_LEDUP2_PROGRAM_RAM236", CMIC_LEDUP2_PROGRAM_RAM236r }, \ 3320 { 0x00029bb4, "CMIC_LEDUP2_PROGRAM_RAM237", CMIC_LEDUP2_PROGRAM_RAM237r }, \ 3321 { 0x00029bb8, "CMIC_LEDUP2_PROGRAM_RAM238", CMIC_LEDUP2_PROGRAM_RAM238r }, \ 3322 { 0x00029bbc, "CMIC_LEDUP2_PROGRAM_RAM239", CMIC_LEDUP2_PROGRAM_RAM239r }, \ 3323 { 0x00029bc0, "CMIC_LEDUP2_PROGRAM_RAM240", CMIC_LEDUP2_PROGRAM_RAM240r }, \ 3324 { 0x00029bc4, "CMIC_LEDUP2_PROGRAM_RAM241", CMIC_LEDUP2_PROGRAM_RAM241r }, \ 3325 { 0x00029bc8, "CMIC_LEDUP2_PROGRAM_RAM242", CMIC_LEDUP2_PROGRAM_RAM242r }, \ 3326 { 0x00029bcc, "CMIC_LEDUP2_PROGRAM_RAM243", CMIC_LEDUP2_PROGRAM_RAM243r }, \ 3327 { 0x00029bd0, "CMIC_LEDUP2_PROGRAM_RAM244", CMIC_LEDUP2_PROGRAM_RAM244r }, \ 3328 { 0x00029bd4, "CMIC_LEDUP2_PROGRAM_RAM245", CMIC_LEDUP2_PROGRAM_RAM245r }, \ 3329 { 0x00029bd8, "CMIC_LEDUP2_PROGRAM_RAM246", CMIC_LEDUP2_PROGRAM_RAM246r }, \ 3330 { 0x00029bdc, "CMIC_LEDUP2_PROGRAM_RAM247", CMIC_LEDUP2_PROGRAM_RAM247r }, \ 3331 { 0x00029be0, "CMIC_LEDUP2_PROGRAM_RAM248", CMIC_LEDUP2_PROGRAM_RAM248r }, \ 3332 { 0x00029be4, "CMIC_LEDUP2_PROGRAM_RAM249", CMIC_LEDUP2_PROGRAM_RAM249r }, \ 3333 { 0x00029be8, "CMIC_LEDUP2_PROGRAM_RAM250", CMIC_LEDUP2_PROGRAM_RAM250r }, \ 3334 { 0x00029bec, "CMIC_LEDUP2_PROGRAM_RAM251", CMIC_LEDUP2_PROGRAM_RAM251r }, \ 3335 { 0x00029bf0, "CMIC_LEDUP2_PROGRAM_RAM252", CMIC_LEDUP2_PROGRAM_RAM252r }, \ 3336 { 0x00029bf4, "CMIC_LEDUP2_PROGRAM_RAM253", CMIC_LEDUP2_PROGRAM_RAM253r }, \ 3337 { 0x00029bf8, "CMIC_LEDUP2_PROGRAM_RAM254", CMIC_LEDUP2_PROGRAM_RAM254r }, \ 3338 { 0x00029bfc, "CMIC_LEDUP2_PROGRAM_RAM255", CMIC_LEDUP2_PROGRAM_RAM255r }, \ 3339 { 0x0002a000, "CMIC_LEDUP3_CTRL", CMIC_LEDUP3_CTRLr }, \ 3340 { 0x0002a004, "CMIC_LEDUP3_STATUS", CMIC_LEDUP3_STATUSr }, \ 3341 { 0x0002a008, "CMIC_LEDUP3_SCANCHAIN_ASSEMBLY_ST_ADDR", CMIC_LEDUP3_SCANCHAIN_ASSEMBLY_ST_ADDRr }, \ 3342 { 0x0002a010, "CMIC_LEDUP3_PORT_ORDER_REMAP_0_3", CMIC_LEDUP3_PORT_ORDER_REMAP_0_3r }, \ 3343 { 0x0002a014, "CMIC_LEDUP3_PORT_ORDER_REMAP_4_7", CMIC_LEDUP3_PORT_ORDER_REMAP_4_7r }, \ 3344 { 0x0002a018, "CMIC_LEDUP3_PORT_ORDER_REMAP_8_11", CMIC_LEDUP3_PORT_ORDER_REMAP_8_11r }, \ 3345 { 0x0002a01c, "CMIC_LEDUP3_PORT_ORDER_REMAP_12_15", CMIC_LEDUP3_PORT_ORDER_REMAP_12_15r }, \ 3346 { 0x0002a020, "CMIC_LEDUP3_PORT_ORDER_REMAP_16_19", CMIC_LEDUP3_PORT_ORDER_REMAP_16_19r }, \ 3347 { 0x0002a024, "CMIC_LEDUP3_PORT_ORDER_REMAP_20_23", CMIC_LEDUP3_PORT_ORDER_REMAP_20_23r }, \ 3348 { 0x0002a028, "CMIC_LEDUP3_PORT_ORDER_REMAP_24_27", CMIC_LEDUP3_PORT_ORDER_REMAP_24_27r }, \ 3349 { 0x0002a02c, "CMIC_LEDUP3_PORT_ORDER_REMAP_28_31", CMIC_LEDUP3_PORT_ORDER_REMAP_28_31r }, \ 3350 { 0x0002a030, "CMIC_LEDUP3_PORT_ORDER_REMAP_32_35", CMIC_LEDUP3_PORT_ORDER_REMAP_32_35r }, \ 3351 { 0x0002a034, "CMIC_LEDUP3_PORT_ORDER_REMAP_36_39", CMIC_LEDUP3_PORT_ORDER_REMAP_36_39r }, \ 3352 { 0x0002a038, "CMIC_LEDUP3_PORT_ORDER_REMAP_40_43", CMIC_LEDUP3_PORT_ORDER_REMAP_40_43r }, \ 3353 { 0x0002a03c, "CMIC_LEDUP3_PORT_ORDER_REMAP_44_47", CMIC_LEDUP3_PORT_ORDER_REMAP_44_47r }, \ 3354 { 0x0002a040, "CMIC_LEDUP3_PORT_ORDER_REMAP_48_51", CMIC_LEDUP3_PORT_ORDER_REMAP_48_51r }, \ 3355 { 0x0002a044, "CMIC_LEDUP3_PORT_ORDER_REMAP_52_55", CMIC_LEDUP3_PORT_ORDER_REMAP_52_55r }, \ 3356 { 0x0002a048, "CMIC_LEDUP3_PORT_ORDER_REMAP_56_59", CMIC_LEDUP3_PORT_ORDER_REMAP_56_59r }, \ 3357 { 0x0002a04c, "CMIC_LEDUP3_PORT_ORDER_REMAP_60_63", CMIC_LEDUP3_PORT_ORDER_REMAP_60_63r }, \ 3358 { 0x0002a050, "CMIC_LEDUP3_CLK_PARAMS", CMIC_LEDUP3_CLK_PARAMSr }, \ 3359 { 0x0002a054, "CMIC_LEDUP3_SCANOUT_COUNT_UPPER", CMIC_LEDUP3_SCANOUT_COUNT_UPPERr }, \ 3360 { 0x0002a058, "CMIC_LEDUP3_TM_CONTROL", CMIC_LEDUP3_TM_CONTROLr }, \ 3361 { 0x0002a05c, "CMIC_LEDUP3_CLK_DIV", CMIC_LEDUP3_CLK_DIVr }, \ 3362 { 0x0002a060, "CMIC_LEDUP3_ECC_CONFIG", CMIC_LEDUP3_ECC_CONFIGr }, \ 3363 { 0x0002a064, "CMIC_LEDUP3_ECC_STATUS", CMIC_LEDUP3_ECC_STATUSr }, \ 3364 { 0x0002a068, "CMIC_LEDUP3_ECC_INTR_ENABLE", CMIC_LEDUP3_ECC_INTR_ENABLEr }, \ 3365 { 0x0002a06c, "CMIC_LEDUP3_ECC_INTR", CMIC_LEDUP3_ECC_INTRr }, \ 3366 { 0x0002a070, "CMIC_LEDUP3_ECC_INTR_CLR", CMIC_LEDUP3_ECC_INTR_CLRr }, \ 3367 { 0x0002a400, "CMIC_LEDUP3_DATA_RAM", CMIC_LEDUP3_DATA_RAMr }, \ 3368 { 0x0002a800, "CMIC_LEDUP3_PROGRAM_RAM", CMIC_LEDUP3_PROGRAM_RAMr }, \ 3369 { 0x0002b000, "CMIC_LEDUP4_CTRL", CMIC_LEDUP4_CTRLr }, \ 3370 { 0x0002b004, "CMIC_LEDUP4_STATUS", CMIC_LEDUP4_STATUSr }, \ 3371 { 0x0002b008, "CMIC_LEDUP4_SCANCHAIN_ASSEMBLY_ST_ADDR", CMIC_LEDUP4_SCANCHAIN_ASSEMBLY_ST_ADDRr }, \ 3372 { 0x0002b010, "CMIC_LEDUP4_PORT_ORDER_REMAP_0_3", CMIC_LEDUP4_PORT_ORDER_REMAP_0_3r }, \ 3373 { 0x0002b014, "CMIC_LEDUP4_PORT_ORDER_REMAP_4_7", CMIC_LEDUP4_PORT_ORDER_REMAP_4_7r }, \ 3374 { 0x0002b018, "CMIC_LEDUP4_PORT_ORDER_REMAP_8_11", CMIC_LEDUP4_PORT_ORDER_REMAP_8_11r }, \ 3375 { 0x0002b01c, "CMIC_LEDUP4_PORT_ORDER_REMAP_12_15", CMIC_LEDUP4_PORT_ORDER_REMAP_12_15r }, \ 3376 { 0x0002b020, "CMIC_LEDUP4_PORT_ORDER_REMAP_16_19", CMIC_LEDUP4_PORT_ORDER_REMAP_16_19r }, \ 3377 { 0x0002b024, "CMIC_LEDUP4_PORT_ORDER_REMAP_20_23", CMIC_LEDUP4_PORT_ORDER_REMAP_20_23r }, \ 3378 { 0x0002b028, "CMIC_LEDUP4_PORT_ORDER_REMAP_24_27", CMIC_LEDUP4_PORT_ORDER_REMAP_24_27r }, \ 3379 { 0x0002b02c, "CMIC_LEDUP4_PORT_ORDER_REMAP_28_31", CMIC_LEDUP4_PORT_ORDER_REMAP_28_31r }, \ 3380 { 0x0002b030, "CMIC_LEDUP4_PORT_ORDER_REMAP_32_35", CMIC_LEDUP4_PORT_ORDER_REMAP_32_35r }, \ 3381 { 0x0002b034, "CMIC_LEDUP4_PORT_ORDER_REMAP_36_39", CMIC_LEDUP4_PORT_ORDER_REMAP_36_39r }, \ 3382 { 0x0002b038, "CMIC_LEDUP4_PORT_ORDER_REMAP_40_43", CMIC_LEDUP4_PORT_ORDER_REMAP_40_43r }, \ 3383 { 0x0002b03c, "CMIC_LEDUP4_PORT_ORDER_REMAP_44_47", CMIC_LEDUP4_PORT_ORDER_REMAP_44_47r }, \ 3384 { 0x0002b040, "CMIC_LEDUP4_PORT_ORDER_REMAP_48_51", CMIC_LEDUP4_PORT_ORDER_REMAP_48_51r }, \ 3385 { 0x0002b044, "CMIC_LEDUP4_PORT_ORDER_REMAP_52_55", CMIC_LEDUP4_PORT_ORDER_REMAP_52_55r }, \ 3386 { 0x0002b048, "CMIC_LEDUP4_PORT_ORDER_REMAP_56_59", CMIC_LEDUP4_PORT_ORDER_REMAP_56_59r }, \ 3387 { 0x0002b04c, "CMIC_LEDUP4_PORT_ORDER_REMAP_60_63", CMIC_LEDUP4_PORT_ORDER_REMAP_60_63r }, \ 3388 { 0x0002b050, "CMIC_LEDUP4_CLK_PARAMS", CMIC_LEDUP4_CLK_PARAMSr }, \ 3389 { 0x0002b054, "CMIC_LEDUP4_SCANOUT_COUNT_UPPER", CMIC_LEDUP4_SCANOUT_COUNT_UPPERr }, \ 3390 { 0x0002b058, "CMIC_LEDUP4_TM_CONTROL", CMIC_LEDUP4_TM_CONTROLr }, \ 3391 { 0x0002b05c, "CMIC_LEDUP4_CLK_DIV", CMIC_LEDUP4_CLK_DIVr }, \ 3392 { 0x0002b060, "CMIC_LEDUP4_ECC_CONFIG", CMIC_LEDUP4_ECC_CONFIGr }, \ 3393 { 0x0002b064, "CMIC_LEDUP4_ECC_STATUS", CMIC_LEDUP4_ECC_STATUSr }, \ 3394 { 0x0002b068, "CMIC_LEDUP4_ECC_INTR_ENABLE", CMIC_LEDUP4_ECC_INTR_ENABLEr }, \ 3395 { 0x0002b06c, "CMIC_LEDUP4_ECC_INTR", CMIC_LEDUP4_ECC_INTRr }, \ 3396 { 0x0002b070, "CMIC_LEDUP4_ECC_INTR_CLR", CMIC_LEDUP4_ECC_INTR_CLRr }, \ 3397 { 0x0002b400, "CMIC_LEDUP4_DATA_RAM", CMIC_LEDUP4_DATA_RAMr }, \ 3398 { 0x0002b800, "CMIC_LEDUP4_PROGRAM_RAM", CMIC_LEDUP4_PROGRAM_RAMr }, \ 3399 { 0x00030064, "CMIC_FSCHAN_ENABLE_PROGRAMMABLE_OPCODE", CMIC_FSCHAN_ENABLE_PROGRAMMABLE_OPCODEr }, \ 3400 { 0x00030068, "CMIC_FSCHAN_STATUS", CMIC_FSCHAN_STATUSr }, \ 3401 { 0x0003006c, "CMIC_FSCHAN_OPCODE", CMIC_FSCHAN_OPCODEr }, \ 3402 { 0x00030070, "CMIC_FSCHAN_ADDRESS", CMIC_FSCHAN_ADDRESSr }, \ 3403 { 0x00030074, "CMIC_FSCHAN_DATA32", CMIC_FSCHAN_DATA32r }, \ 3404 { 0x00030078, "CMIC_FSCHAN_DATA64_LO", CMIC_FSCHAN_DATA64_LOr }, \ 3405 { 0x0003007c, "CMIC_FSCHAN_DATA64_HI", CMIC_FSCHAN_DATA64_HIr }, \ 3406 { 0x00031000, "CMIC_CMC0_SCHAN_CTRL", CMIC_CMC0_SCHAN_CTRLr }, \ 3407 { 0x00031004, "CMIC_CMC0_SCHAN_ACK_DATA_BEAT_COUNT", CMIC_CMC0_SCHAN_ACK_DATA_BEAT_COUNTr }, \ 3408 { 0x00031008, "CMIC_CMC0_SCHAN_ERR", CMIC_CMC0_SCHAN_ERRr }, \ 3409 { 0x0003100c, "CMIC_CMC0_SCHAN_MESSAGE0", CMIC_CMC0_SCHAN_MESSAGE0r }, \ 3410 { 0x0003100c, "CMIC_CMC0_SCHAN_MESSAGE", CMIC_CMC0_SCHAN_MESSAGEr }, \ 3411 { 0x00031010, "CMIC_CMC0_SCHAN_MESSAGE1", CMIC_CMC0_SCHAN_MESSAGE1r }, \ 3412 { 0x00031014, "CMIC_CMC0_SCHAN_MESSAGE2", CMIC_CMC0_SCHAN_MESSAGE2r }, \ 3413 { 0x00031018, "CMIC_CMC0_SCHAN_MESSAGE3", CMIC_CMC0_SCHAN_MESSAGE3r }, \ 3414 { 0x0003101c, "CMIC_CMC0_SCHAN_MESSAGE4", CMIC_CMC0_SCHAN_MESSAGE4r }, \ 3415 { 0x00031020, "CMIC_CMC0_SCHAN_MESSAGE5", CMIC_CMC0_SCHAN_MESSAGE5r }, \ 3416 { 0x00031024, "CMIC_CMC0_SCHAN_MESSAGE6", CMIC_CMC0_SCHAN_MESSAGE6r }, \ 3417 { 0x00031028, "CMIC_CMC0_SCHAN_MESSAGE7", CMIC_CMC0_SCHAN_MESSAGE7r }, \ 3418 { 0x0003102c, "CMIC_CMC0_SCHAN_MESSAGE8", CMIC_CMC0_SCHAN_MESSAGE8r }, \ 3419 { 0x00031030, "CMIC_CMC0_SCHAN_MESSAGE9", CMIC_CMC0_SCHAN_MESSAGE9r }, \ 3420 { 0x00031034, "CMIC_CMC0_SCHAN_MESSAGE10", CMIC_CMC0_SCHAN_MESSAGE10r }, \ 3421 { 0x00031038, "CMIC_CMC0_SCHAN_MESSAGE11", CMIC_CMC0_SCHAN_MESSAGE11r }, \ 3422 { 0x0003103c, "CMIC_CMC0_SCHAN_MESSAGE12", CMIC_CMC0_SCHAN_MESSAGE12r }, \ 3423 { 0x00031040, "CMIC_CMC0_SCHAN_MESSAGE13", CMIC_CMC0_SCHAN_MESSAGE13r }, \ 3424 { 0x00031044, "CMIC_CMC0_SCHAN_MESSAGE14", CMIC_CMC0_SCHAN_MESSAGE14r }, \ 3425 { 0x00031048, "CMIC_CMC0_SCHAN_MESSAGE15", CMIC_CMC0_SCHAN_MESSAGE15r }, \ 3426 { 0x0003104c, "CMIC_CMC0_SCHAN_MESSAGE16", CMIC_CMC0_SCHAN_MESSAGE16r }, \ 3427 { 0x00031050, "CMIC_CMC0_SCHAN_MESSAGE17", CMIC_CMC0_SCHAN_MESSAGE17r }, \ 3428 { 0x00031054, "CMIC_CMC0_SCHAN_MESSAGE18", CMIC_CMC0_SCHAN_MESSAGE18r }, \ 3429 { 0x00031058, "CMIC_CMC0_SCHAN_MESSAGE19", CMIC_CMC0_SCHAN_MESSAGE19r }, \ 3430 { 0x0003105c, "CMIC_CMC0_SCHAN_MESSAGE20", CMIC_CMC0_SCHAN_MESSAGE20r }, \ 3431 { 0x00031060, "CMIC_CMC0_SCHAN_MESSAGE21", CMIC_CMC0_SCHAN_MESSAGE21r }, \ 3432 { 0x00031064, "CMIC_CMC0_FSCHAN_ENABLE_PROGRAMMABLE_OPCODE", CMIC_CMC0_FSCHAN_ENABLE_PROGRAMMABLE_OPCODEr }, \ 3433 { 0x00031068, "CMIC_CMC0_FSCHAN_STATUS", CMIC_CMC0_FSCHAN_STATUSr }, \ 3434 { 0x0003106c, "CMIC_CMC0_FSCHAN_OPCODE", CMIC_CMC0_FSCHAN_OPCODEr }, \ 3435 { 0x00031070, "CMIC_CMC0_FSCHAN_ADDRESS", CMIC_CMC0_FSCHAN_ADDRESSr }, \ 3436 { 0x00031074, "CMIC_CMC0_FSCHAN_DATA32", CMIC_CMC0_FSCHAN_DATA32r }, \ 3437 { 0x00031078, "CMIC_CMC0_FSCHAN_DATA64_LO", CMIC_CMC0_FSCHAN_DATA64_LOr }, \ 3438 { 0x0003107c, "CMIC_CMC0_FSCHAN_DATA64_HI", CMIC_CMC0_FSCHAN_DATA64_HIr }, \ 3439 { 0x00031080, "CMIC_CMC0_MIIM_PARAM", CMIC_CMC0_MIIM_PARAMr }, \ 3440 { 0x00031084, "CMIC_CMC0_MIIM_READ_DATA", CMIC_CMC0_MIIM_READ_DATAr }, \ 3441 { 0x00031088, "CMIC_CMC0_MIIM_ADDRESS", CMIC_CMC0_MIIM_ADDRESSr }, \ 3442 { 0x0003108c, "CMIC_CMC0_MIIM_CTRL", CMIC_CMC0_MIIM_CTRLr }, \ 3443 { 0x00031090, "CMIC_CMC0_MIIM_STAT", CMIC_CMC0_MIIM_STATr }, \ 3444 { 0x00031100, "CMIC_CMC0_TM_CONTROL_0", CMIC_CMC0_TM_CONTROL_0r }, \ 3445 { 0x00031104, "CMIC_CMC0_TM_CONTROL_1", CMIC_CMC0_TM_CONTROL_1r }, \ 3446 { 0x00031108, "CMIC_CMC0_CONFIG", CMIC_CMC0_CONFIGr }, \ 3447 { 0x0003110c, "CMIC_CMC0_STAT", CMIC_CMC0_STATr }, \ 3448 { 0x00031110, "CMIC_CMC0_CH0_RXBUF_THRESHOLD_CONFIG", CMIC_CMC0_CH0_RXBUF_THRESHOLD_CONFIGr }, \ 3449 { 0x00031114, "CMIC_CMC0_CH1_RXBUF_THRESHOLD_CONFIG", CMIC_CMC0_CH1_RXBUF_THRESHOLD_CONFIGr }, \ 3450 { 0x00031118, "CMIC_CMC0_CH2_RXBUF_THRESHOLD_CONFIG", CMIC_CMC0_CH2_RXBUF_THRESHOLD_CONFIGr }, \ 3451 { 0x0003111c, "CMIC_CMC0_CH3_RXBUF_THRESHOLD_CONFIG", CMIC_CMC0_CH3_RXBUF_THRESHOLD_CONFIGr }, \ 3452 { 0x00031120, "CMIC_CMC0_DMA_CH0_DESC_HALT_ADDR", CMIC_CMC0_DMA_CH0_DESC_HALT_ADDRr }, \ 3453 { 0x00031124, "CMIC_CMC0_DMA_CH1_DESC_HALT_ADDR", CMIC_CMC0_DMA_CH1_DESC_HALT_ADDRr }, \ 3454 { 0x00031128, "CMIC_CMC0_DMA_CH2_DESC_HALT_ADDR", CMIC_CMC0_DMA_CH2_DESC_HALT_ADDRr }, \ 3455 { 0x0003112c, "CMIC_CMC0_DMA_CH3_DESC_HALT_ADDR", CMIC_CMC0_DMA_CH3_DESC_HALT_ADDRr }, \ 3456 { 0x00031130, "CMIC_CMC0_DMA_STAT_HI", CMIC_CMC0_DMA_STAT_HIr }, \ 3457 { 0x00031140, "CMIC_CMC0_CH0_DMA_CTRL", CMIC_CMC0_CH0_DMA_CTRLr }, \ 3458 { 0x00031144, "CMIC_CMC0_CH1_DMA_CTRL", CMIC_CMC0_CH1_DMA_CTRLr }, \ 3459 { 0x00031148, "CMIC_CMC0_CH2_DMA_CTRL", CMIC_CMC0_CH2_DMA_CTRLr }, \ 3460 { 0x0003114c, "CMIC_CMC0_CH3_DMA_CTRL", CMIC_CMC0_CH3_DMA_CTRLr }, \ 3461 { 0x00031150, "CMIC_CMC0_DMA_STAT", CMIC_CMC0_DMA_STATr }, \ 3462 { 0x00031158, "CMIC_CMC0_DMA_DESC0", CMIC_CMC0_DMA_DESC0r }, \ 3463 { 0x0003115c, "CMIC_CMC0_DMA_DESC1", CMIC_CMC0_DMA_DESC1r }, \ 3464 { 0x00031160, "CMIC_CMC0_DMA_DESC2", CMIC_CMC0_DMA_DESC2r }, \ 3465 { 0x00031164, "CMIC_CMC0_DMA_DESC3", CMIC_CMC0_DMA_DESC3r }, \ 3466 { 0x00031168, "CMIC_CMC0_CH0_COS_CTRL_RX_0", CMIC_CMC0_CH0_COS_CTRL_RX_0r }, \ 3467 { 0x0003116c, "CMIC_CMC0_CH0_COS_CTRL_RX_1", CMIC_CMC0_CH0_COS_CTRL_RX_1r }, \ 3468 { 0x00031170, "CMIC_CMC0_CH1_COS_CTRL_RX_0", CMIC_CMC0_CH1_COS_CTRL_RX_0r }, \ 3469 { 0x00031174, "CMIC_CMC0_CH1_COS_CTRL_RX_1", CMIC_CMC0_CH1_COS_CTRL_RX_1r }, \ 3470 { 0x00031178, "CMIC_CMC0_CH2_COS_CTRL_RX_0", CMIC_CMC0_CH2_COS_CTRL_RX_0r }, \ 3471 { 0x0003117c, "CMIC_CMC0_CH2_COS_CTRL_RX_1", CMIC_CMC0_CH2_COS_CTRL_RX_1r }, \ 3472 { 0x00031180, "CMIC_CMC0_CH3_COS_CTRL_RX_0", CMIC_CMC0_CH3_COS_CTRL_RX_0r }, \ 3473 { 0x00031184, "CMIC_CMC0_CH3_COS_CTRL_RX_1", CMIC_CMC0_CH3_COS_CTRL_RX_1r }, \ 3474 { 0x00031188, "CMIC_CMC0_DMA_CH0_INTR_COAL", CMIC_CMC0_DMA_CH0_INTR_COALr }, \ 3475 { 0x0003118c, "CMIC_CMC0_DMA_CH1_INTR_COAL", CMIC_CMC0_DMA_CH1_INTR_COALr }, \ 3476 { 0x00031190, "CMIC_CMC0_DMA_CH2_INTR_COAL", CMIC_CMC0_DMA_CH2_INTR_COALr }, \ 3477 { 0x00031194, "CMIC_CMC0_DMA_CH3_INTR_COAL", CMIC_CMC0_DMA_CH3_INTR_COALr }, \ 3478 { 0x00031198, "CMIC_CMC0_RXBUF_THRESHOLD_CONFIG", CMIC_CMC0_RXBUF_THRESHOLD_CONFIGr }, \ 3479 { 0x0003119c, "CMIC_CMC0_PROGRAMMABLE_COS_MASK0", CMIC_CMC0_PROGRAMMABLE_COS_MASK0r }, \ 3480 { 0x000311a0, "CMIC_CMC0_PROGRAMMABLE_COS_MASK1", CMIC_CMC0_PROGRAMMABLE_COS_MASK1r }, \ 3481 { 0x000311a4, "CMIC_CMC0_DMA_STAT_CLR", CMIC_CMC0_DMA_STAT_CLRr }, \ 3482 { 0x000311a8, "CMIC_CMC0_CH0_DMA_CURR_DESC", CMIC_CMC0_CH0_DMA_CURR_DESCr }, \ 3483 { 0x000311ac, "CMIC_CMC0_CH1_DMA_CURR_DESC", CMIC_CMC0_CH1_DMA_CURR_DESCr }, \ 3484 { 0x000311b0, "CMIC_CMC0_CH2_DMA_CURR_DESC", CMIC_CMC0_CH2_DMA_CURR_DESCr }, \ 3485 { 0x000311b4, "CMIC_CMC0_CH3_DMA_CURR_DESC", CMIC_CMC0_CH3_DMA_CURR_DESCr }, \ 3486 { 0x000311c0, "CMIC_CMC0_STAT_DMA_ADDR", CMIC_CMC0_STAT_DMA_ADDRr }, \ 3487 { 0x000311c4, "CMIC_CMC0_STAT_DMA_CFG", CMIC_CMC0_STAT_DMA_CFGr }, \ 3488 { 0x000311c8, "CMIC_CMC0_STAT_DMA_PORTS_0", CMIC_CMC0_STAT_DMA_PORTS_0r }, \ 3489 { 0x000311cc, "CMIC_CMC0_STAT_DMA_PORTS_1", CMIC_CMC0_STAT_DMA_PORTS_1r }, \ 3490 { 0x000311d0, "CMIC_CMC0_STAT_DMA_PORTS_2", CMIC_CMC0_STAT_DMA_PORTS_2r }, \ 3491 { 0x000311d4, "CMIC_CMC0_STAT_DMA_CURRENT", CMIC_CMC0_STAT_DMA_CURRENTr }, \ 3492 { 0x000311d8, "CMIC_CMC0_STAT_DMA_SBUS_START_ADDRESS", CMIC_CMC0_STAT_DMA_SBUS_START_ADDRESSr }, \ 3493 { 0x000311dc, "CMIC_CMC0_STAT_DMA_STAT", CMIC_CMC0_STAT_DMA_STATr }, \ 3494 { 0x00031200, "CMIC_CMC0_SLAM_DMA_PCIMEM_START_ADDR", CMIC_CMC0_SLAM_DMA_PCIMEM_START_ADDRr }, \ 3495 { 0x00031204, "CMIC_CMC0_SLAM_DMA_SBUS_START_ADDR", CMIC_CMC0_SLAM_DMA_SBUS_START_ADDRr }, \ 3496 { 0x00031208, "CMIC_CMC0_SLAM_DMA_ENTRY_COUNT", CMIC_CMC0_SLAM_DMA_ENTRY_COUNTr }, \ 3497 { 0x0003120c, "CMIC_CMC0_SLAM_DMA_CFG", CMIC_CMC0_SLAM_DMA_CFGr }, \ 3498 { 0x00031210, "CMIC_CMC0_SLAM_DMA_STAT", CMIC_CMC0_SLAM_DMA_STATr }, \ 3499 { 0x00031214, "CMIC_CMC0_SLAM_DMA_CUR_ENTRY_SBUS_ADDR", CMIC_CMC0_SLAM_DMA_CUR_ENTRY_SBUS_ADDRr }, \ 3500 { 0x00031218, "CMIC_CMC0_SLAM_DMA_SBUS_CMD_CONFIG", CMIC_CMC0_SLAM_DMA_SBUS_CMD_CONFIGr }, \ 3501 { 0x00031240, "CMIC_CMC0_TABLE_DMA_PCIMEM_START_ADDR", CMIC_CMC0_TABLE_DMA_PCIMEM_START_ADDRr }, \ 3502 { 0x00031244, "CMIC_CMC0_TABLE_DMA_SBUS_START_ADDR", CMIC_CMC0_TABLE_DMA_SBUS_START_ADDRr }, \ 3503 { 0x00031248, "CMIC_CMC0_TABLE_DMA_ENTRY_COUNT", CMIC_CMC0_TABLE_DMA_ENTRY_COUNTr }, \ 3504 { 0x0003124c, "CMIC_CMC0_TABLE_DMA_CFG", CMIC_CMC0_TABLE_DMA_CFGr }, \ 3505 { 0x00031250, "CMIC_CMC0_TABLE_DMA_STAT", CMIC_CMC0_TABLE_DMA_STATr }, \ 3506 { 0x00031254, "CMIC_CMC0_TABLE_DMA_CUR_ENTRY_SBUS_ADDR", CMIC_CMC0_TABLE_DMA_CUR_ENTRY_SBUS_ADDRr }, \ 3507 { 0x00031258, "CMIC_CMC0_TABLE_DMA_SBUS_CMD_CONFIG", CMIC_CMC0_TABLE_DMA_SBUS_CMD_CONFIGr }, \ 3508 { 0x000312c0, "CMIC_CMC0_FIFO_CH0_RD_DMA_CFG", CMIC_CMC0_FIFO_CH0_RD_DMA_CFGr }, \ 3509 { 0x000312c4, "CMIC_CMC0_FIFO_CH1_RD_DMA_CFG", CMIC_CMC0_FIFO_CH1_RD_DMA_CFGr }, \ 3510 { 0x000312c8, "CMIC_CMC0_FIFO_CH2_RD_DMA_CFG", CMIC_CMC0_FIFO_CH2_RD_DMA_CFGr }, \ 3511 { 0x000312cc, "CMIC_CMC0_FIFO_CH3_RD_DMA_CFG", CMIC_CMC0_FIFO_CH3_RD_DMA_CFGr }, \ 3512 { 0x000312d0, "CMIC_CMC0_FIFO_CH0_RD_DMA_SBUS_START_ADDRESS", CMIC_CMC0_FIFO_CH0_RD_DMA_SBUS_START_ADDRESSr }, \ 3513 { 0x000312d4, "CMIC_CMC0_FIFO_CH1_RD_DMA_SBUS_START_ADDRESS", CMIC_CMC0_FIFO_CH1_RD_DMA_SBUS_START_ADDRESSr }, \ 3514 { 0x000312d8, "CMIC_CMC0_FIFO_CH2_RD_DMA_SBUS_START_ADDRESS", CMIC_CMC0_FIFO_CH2_RD_DMA_SBUS_START_ADDRESSr }, \ 3515 { 0x000312dc, "CMIC_CMC0_FIFO_CH3_RD_DMA_SBUS_START_ADDRESS", CMIC_CMC0_FIFO_CH3_RD_DMA_SBUS_START_ADDRESSr }, \ 3516 { 0x000312e0, "CMIC_CMC0_FIFO_CH0_RD_DMA_HOSTMEM_START_ADDRESS", CMIC_CMC0_FIFO_CH0_RD_DMA_HOSTMEM_START_ADDRESSr }, \ 3517 { 0x000312e4, "CMIC_CMC0_FIFO_CH1_RD_DMA_HOSTMEM_START_ADDRESS", CMIC_CMC0_FIFO_CH1_RD_DMA_HOSTMEM_START_ADDRESSr }, \ 3518 { 0x000312e8, "CMIC_CMC0_FIFO_CH2_RD_DMA_HOSTMEM_START_ADDRESS", CMIC_CMC0_FIFO_CH2_RD_DMA_HOSTMEM_START_ADDRESSr }, \ 3519 { 0x000312ec, "CMIC_CMC0_FIFO_CH3_RD_DMA_HOSTMEM_START_ADDRESS", CMIC_CMC0_FIFO_CH3_RD_DMA_HOSTMEM_START_ADDRESSr }, \ 3520 { 0x000312f0, "CMIC_CMC0_FIFO_CH0_RD_DMA_HOSTMEM_READ_PTR", CMIC_CMC0_FIFO_CH0_RD_DMA_HOSTMEM_READ_PTRr }, \ 3521 { 0x000312f0, "CMIC_CMC0_FIFO_CH0_RD_DMA_NUM_OF_ENTRIES_READ_FRM_HOSTMEM", CMIC_CMC0_FIFO_CH0_RD_DMA_NUM_OF_ENTRIES_READ_FRM_HOSTMEMr }, \ 3522 { 0x000312f4, "CMIC_CMC0_FIFO_CH0_RD_DMA_HOSTMEM_WRITE_PTR", CMIC_CMC0_FIFO_CH0_RD_DMA_HOSTMEM_WRITE_PTRr }, \ 3523 { 0x000312f4, "CMIC_CMC0_FIFO_CH0_RD_DMA_NUM_OF_ENTRIES_VALID_IN_HOSTMEM", CMIC_CMC0_FIFO_CH0_RD_DMA_NUM_OF_ENTRIES_VALID_IN_HOSTMEMr }, \ 3524 { 0x000312f8, "CMIC_CMC0_FIFO_CH1_RD_DMA_HOSTMEM_READ_PTR", CMIC_CMC0_FIFO_CH1_RD_DMA_HOSTMEM_READ_PTRr }, \ 3525 { 0x000312f8, "CMIC_CMC0_FIFO_CH1_RD_DMA_NUM_OF_ENTRIES_READ_FRM_HOSTMEM", CMIC_CMC0_FIFO_CH1_RD_DMA_NUM_OF_ENTRIES_READ_FRM_HOSTMEMr }, \ 3526 { 0x000312fc, "CMIC_CMC0_FIFO_CH1_RD_DMA_NUM_OF_ENTRIES_VALID_IN_HOSTMEM", CMIC_CMC0_FIFO_CH1_RD_DMA_NUM_OF_ENTRIES_VALID_IN_HOSTMEMr }, \ 3527 { 0x000312fc, "CMIC_CMC0_FIFO_CH1_RD_DMA_HOSTMEM_WRITE_PTR", CMIC_CMC0_FIFO_CH1_RD_DMA_HOSTMEM_WRITE_PTRr }, \ 3528 { 0x00031300, "CMIC_CMC0_FIFO_CH2_RD_DMA_NUM_OF_ENTRIES_READ_FRM_HOSTMEM", CMIC_CMC0_FIFO_CH2_RD_DMA_NUM_OF_ENTRIES_READ_FRM_HOSTMEMr }, \ 3529 { 0x00031300, "CMIC_CMC0_FIFO_CH2_RD_DMA_HOSTMEM_READ_PTR", CMIC_CMC0_FIFO_CH2_RD_DMA_HOSTMEM_READ_PTRr }, \ 3530 { 0x00031304, "CMIC_CMC0_FIFO_CH2_RD_DMA_NUM_OF_ENTRIES_VALID_IN_HOSTMEM", CMIC_CMC0_FIFO_CH2_RD_DMA_NUM_OF_ENTRIES_VALID_IN_HOSTMEMr }, \ 3531 { 0x00031304, "CMIC_CMC0_FIFO_CH2_RD_DMA_HOSTMEM_WRITE_PTR", CMIC_CMC0_FIFO_CH2_RD_DMA_HOSTMEM_WRITE_PTRr }, \ 3532 { 0x00031308, "CMIC_CMC0_FIFO_CH3_RD_DMA_HOSTMEM_READ_PTR", CMIC_CMC0_FIFO_CH3_RD_DMA_HOSTMEM_READ_PTRr }, \ 3533 { 0x00031308, "CMIC_CMC0_FIFO_CH3_RD_DMA_NUM_OF_ENTRIES_READ_FRM_HOSTMEM", CMIC_CMC0_FIFO_CH3_RD_DMA_NUM_OF_ENTRIES_READ_FRM_HOSTMEMr }, \ 3534 { 0x0003130c, "CMIC_CMC0_FIFO_CH3_RD_DMA_HOSTMEM_WRITE_PTR", CMIC_CMC0_FIFO_CH3_RD_DMA_HOSTMEM_WRITE_PTRr }, \ 3535 { 0x0003130c, "CMIC_CMC0_FIFO_CH3_RD_DMA_NUM_OF_ENTRIES_VALID_IN_HOSTMEM", CMIC_CMC0_FIFO_CH3_RD_DMA_NUM_OF_ENTRIES_VALID_IN_HOSTMEMr }, \ 3536 { 0x00031310, "CMIC_CMC0_FIFO_CH0_RD_DMA_ECCERR_ADDRESS", CMIC_CMC0_FIFO_CH0_RD_DMA_ECCERR_ADDRESSr }, \ 3537 { 0x00031314, "CMIC_CMC0_FIFO_CH1_RD_DMA_ECCERR_ADDRESS", CMIC_CMC0_FIFO_CH1_RD_DMA_ECCERR_ADDRESSr }, \ 3538 { 0x00031318, "CMIC_CMC0_FIFO_CH2_RD_DMA_ECCERR_ADDRESS", CMIC_CMC0_FIFO_CH2_RD_DMA_ECCERR_ADDRESSr }, \ 3539 { 0x0003131c, "CMIC_CMC0_FIFO_CH3_RD_DMA_ECCERR_ADDRESS", CMIC_CMC0_FIFO_CH3_RD_DMA_ECCERR_ADDRESSr }, \ 3540 { 0x00031320, "CMIC_CMC0_FIFO_CH0_RD_DMA_ECCERR_CONTROL", CMIC_CMC0_FIFO_CH0_RD_DMA_ECCERR_CONTROLr }, \ 3541 { 0x00031324, "CMIC_CMC0_FIFO_CH1_RD_DMA_ECCERR_CONTROL", CMIC_CMC0_FIFO_CH1_RD_DMA_ECCERR_CONTROLr }, \ 3542 { 0x00031328, "CMIC_CMC0_FIFO_CH2_RD_DMA_ECCERR_CONTROL", CMIC_CMC0_FIFO_CH2_RD_DMA_ECCERR_CONTROLr }, \ 3543 { 0x0003132c, "CMIC_CMC0_FIFO_CH3_RD_DMA_ECCERR_CONTROL", CMIC_CMC0_FIFO_CH3_RD_DMA_ECCERR_CONTROLr }, \ 3544 { 0x00031330, "CMIC_CMC0_FIFO_CH0_RD_DMA_CUR_HOSTMEM_WRITE_PTR", CMIC_CMC0_FIFO_CH0_RD_DMA_CUR_HOSTMEM_WRITE_PTRr }, \ 3545 { 0x00031334, "CMIC_CMC0_FIFO_CH1_RD_DMA_CUR_HOSTMEM_WRITE_PTR", CMIC_CMC0_FIFO_CH1_RD_DMA_CUR_HOSTMEM_WRITE_PTRr }, \ 3546 { 0x00031338, "CMIC_CMC0_FIFO_CH2_RD_DMA_CUR_HOSTMEM_WRITE_PTR", CMIC_CMC0_FIFO_CH2_RD_DMA_CUR_HOSTMEM_WRITE_PTRr }, \ 3547 { 0x0003133c, "CMIC_CMC0_FIFO_CH3_RD_DMA_CUR_HOSTMEM_WRITE_PTR", CMIC_CMC0_FIFO_CH3_RD_DMA_CUR_HOSTMEM_WRITE_PTRr }, \ 3548 { 0x00031354, "CMIC_CMC0_FIFO_CH0_RD_DMA_HOSTMEM_THRESHOLD", CMIC_CMC0_FIFO_CH0_RD_DMA_HOSTMEM_THRESHOLDr }, \ 3549 { 0x00031358, "CMIC_CMC0_FIFO_CH1_RD_DMA_HOSTMEM_THRESHOLD", CMIC_CMC0_FIFO_CH1_RD_DMA_HOSTMEM_THRESHOLDr }, \ 3550 { 0x0003135c, "CMIC_CMC0_FIFO_CH2_RD_DMA_HOSTMEM_THRESHOLD", CMIC_CMC0_FIFO_CH2_RD_DMA_HOSTMEM_THRESHOLDr }, \ 3551 { 0x00031360, "CMIC_CMC0_FIFO_CH3_RD_DMA_HOSTMEM_THRESHOLD", CMIC_CMC0_FIFO_CH3_RD_DMA_HOSTMEM_THRESHOLDr }, \ 3552 { 0x00031364, "CMIC_CMC0_FIFO_CH0_RD_DMA_STAT", CMIC_CMC0_FIFO_CH0_RD_DMA_STATr }, \ 3553 { 0x00031368, "CMIC_CMC0_FIFO_CH1_RD_DMA_STAT", CMIC_CMC0_FIFO_CH1_RD_DMA_STATr }, \ 3554 { 0x0003136c, "CMIC_CMC0_FIFO_CH2_RD_DMA_STAT", CMIC_CMC0_FIFO_CH2_RD_DMA_STATr }, \ 3555 { 0x00031370, "CMIC_CMC0_FIFO_CH3_RD_DMA_STAT", CMIC_CMC0_FIFO_CH3_RD_DMA_STATr }, \ 3556 { 0x00031374, "CMIC_CMC0_FIFO_CH0_RD_DMA_STAT_CLR", CMIC_CMC0_FIFO_CH0_RD_DMA_STAT_CLRr }, \ 3557 { 0x00031378, "CMIC_CMC0_FIFO_CH1_RD_DMA_STAT_CLR", CMIC_CMC0_FIFO_CH1_RD_DMA_STAT_CLRr }, \ 3558 { 0x0003137c, "CMIC_CMC0_FIFO_CH2_RD_DMA_STAT_CLR", CMIC_CMC0_FIFO_CH2_RD_DMA_STAT_CLRr }, \ 3559 { 0x00031380, "CMIC_CMC0_FIFO_CH3_RD_DMA_STAT_CLR", CMIC_CMC0_FIFO_CH3_RD_DMA_STAT_CLRr }, \ 3560 { 0x00031384, "CMIC_CMC0_FIFO_CH0_RD_DMA_SBUS_CMD_CONFIG", CMIC_CMC0_FIFO_CH0_RD_DMA_SBUS_CMD_CONFIGr }, \ 3561 { 0x00031384, "CMIC_CMC0_FIFO_CH0_RD_DMA_OPCODE", CMIC_CMC0_FIFO_CH0_RD_DMA_OPCODEr }, \ 3562 { 0x00031388, "CMIC_CMC0_FIFO_CH1_RD_DMA_SBUS_CMD_CONFIG", CMIC_CMC0_FIFO_CH1_RD_DMA_SBUS_CMD_CONFIGr }, \ 3563 { 0x00031388, "CMIC_CMC0_FIFO_CH1_RD_DMA_OPCODE", CMIC_CMC0_FIFO_CH1_RD_DMA_OPCODEr }, \ 3564 { 0x0003138c, "CMIC_CMC0_FIFO_CH2_RD_DMA_OPCODE", CMIC_CMC0_FIFO_CH2_RD_DMA_OPCODEr }, \ 3565 { 0x0003138c, "CMIC_CMC0_FIFO_CH2_RD_DMA_SBUS_CMD_CONFIG", CMIC_CMC0_FIFO_CH2_RD_DMA_SBUS_CMD_CONFIGr }, \ 3566 { 0x00031390, "CMIC_CMC0_FIFO_CH3_RD_DMA_OPCODE", CMIC_CMC0_FIFO_CH3_RD_DMA_OPCODEr }, \ 3567 { 0x00031390, "CMIC_CMC0_FIFO_CH3_RD_DMA_SBUS_CMD_CONFIG", CMIC_CMC0_FIFO_CH3_RD_DMA_SBUS_CMD_CONFIGr }, \ 3568 { 0x00031394, "CMIC_CMC0_FIFO_RD_DMA_DEBUG", CMIC_CMC0_FIFO_RD_DMA_DEBUGr }, \ 3569 { 0x000313a0, "CMIC_CMC0_CCM_DMA_HOST0_MEM_START_ADDR", CMIC_CMC0_CCM_DMA_HOST0_MEM_START_ADDRr }, \ 3570 { 0x000313a4, "CMIC_CMC0_CCM_DMA_HOST1_MEM_START_ADDR", CMIC_CMC0_CCM_DMA_HOST1_MEM_START_ADDRr }, \ 3571 { 0x000313a8, "CMIC_CMC0_CCM_DMA_ENTRY_COUNT", CMIC_CMC0_CCM_DMA_ENTRY_COUNTr }, \ 3572 { 0x000313ac, "CMIC_CMC0_CCM_DMA_CFG", CMIC_CMC0_CCM_DMA_CFGr }, \ 3573 { 0x000313b0, "CMIC_CMC0_CCM_DMA_STAT", CMIC_CMC0_CCM_DMA_STATr }, \ 3574 { 0x000313b4, "CMIC_CMC0_CCM_DMA_CUR_HOST0_ADDR", CMIC_CMC0_CCM_DMA_CUR_HOST0_ADDRr }, \ 3575 { 0x000313b8, "CMIC_CMC0_CCM_DMA_CUR_HOST1_ADDR", CMIC_CMC0_CCM_DMA_CUR_HOST1_ADDRr }, \ 3576 { 0x000313bc, "CMIC_CMC0_CCM_DMA_ECCERR_ADDR", CMIC_CMC0_CCM_DMA_ECCERR_ADDRr }, \ 3577 { 0x000313c0, "CMIC_CMC0_CCM_DMA_STATUS_CLR", CMIC_CMC0_CCM_DMA_STATUS_CLRr }, \ 3578 { 0x000313c4, "CMIC_CMC0_CCM_DMA_ECCERR_CONTROL", CMIC_CMC0_CCM_DMA_ECCERR_CONTROLr }, \ 3579 { 0x00031400, "CMIC_CMC0_IRQ_STAT0", CMIC_CMC0_IRQ_STAT0r }, \ 3580 { 0x00031404, "CMIC_CMC0_IRQ_STAT1", CMIC_CMC0_IRQ_STAT1r }, \ 3581 { 0x00031408, "CMIC_CMC0_IRQ_STAT2", CMIC_CMC0_IRQ_STAT2r }, \ 3582 { 0x0003140c, "CMIC_CMC0_IRQ_STAT3", CMIC_CMC0_IRQ_STAT3r }, \ 3583 { 0x00031410, "CMIC_CMC0_IRQ_STAT4", CMIC_CMC0_IRQ_STAT4r }, \ 3584 { 0x00031414, "CMIC_CMC0_PCIE_IRQ_MASK0", CMIC_CMC0_PCIE_IRQ_MASK0r }, \ 3585 { 0x00031418, "CMIC_CMC0_PCIE_IRQ_MASK1", CMIC_CMC0_PCIE_IRQ_MASK1r }, \ 3586 { 0x0003141c, "CMIC_CMC0_PCIE_IRQ_MASK2", CMIC_CMC0_PCIE_IRQ_MASK2r }, \ 3587 { 0x00031420, "CMIC_CMC0_PCIE_IRQ_MASK3", CMIC_CMC0_PCIE_IRQ_MASK3r }, \ 3588 { 0x00031424, "CMIC_CMC0_PCIE_IRQ_MASK4", CMIC_CMC0_PCIE_IRQ_MASK4r }, \ 3589 { 0x00031428, "CMIC_CMC0_UC0_IRQ_MASK0", CMIC_CMC0_UC0_IRQ_MASK0r }, \ 3590 { 0x0003142c, "CMIC_CMC0_UC0_IRQ_MASK1", CMIC_CMC0_UC0_IRQ_MASK1r }, \ 3591 { 0x00031430, "CMIC_CMC0_UC0_IRQ_MASK2", CMIC_CMC0_UC0_IRQ_MASK2r }, \ 3592 { 0x00031434, "CMIC_CMC0_UC0_IRQ_MASK3", CMIC_CMC0_UC0_IRQ_MASK3r }, \ 3593 { 0x00031438, "CMIC_CMC0_UC0_IRQ_MASK4", CMIC_CMC0_UC0_IRQ_MASK4r }, \ 3594 { 0x0003143c, "CMIC_CMC0_UC1_IRQ_MASK0", CMIC_CMC0_UC1_IRQ_MASK0r }, \ 3595 { 0x00031440, "CMIC_CMC0_UC1_IRQ_MASK1", CMIC_CMC0_UC1_IRQ_MASK1r }, \ 3596 { 0x00031444, "CMIC_CMC0_UC1_IRQ_MASK2", CMIC_CMC0_UC1_IRQ_MASK2r }, \ 3597 { 0x00031448, "CMIC_CMC0_UC1_IRQ_MASK3", CMIC_CMC0_UC1_IRQ_MASK3r }, \ 3598 { 0x0003144c, "CMIC_CMC0_UC1_IRQ_MASK4", CMIC_CMC0_UC1_IRQ_MASK4r }, \ 3599 { 0x00031450, "CMIC_CMC0_RCPU_IRQ_MASK0", CMIC_CMC0_RCPU_IRQ_MASK0r }, \ 3600 { 0x00031454, "CMIC_CMC0_2BIT_ECC_ERROR_STATUS", CMIC_CMC0_2BIT_ECC_ERROR_STATUSr }, \ 3601 { 0x00031458, "CMIC_CMC0_2BIT_ECC_ERROR_STATUS_MASK", CMIC_CMC0_2BIT_ECC_ERROR_STATUS_MASKr }, \ 3602 { 0x00031470, "CMIC_CMC0_PCIE_MISCEL", CMIC_CMC0_PCIE_MISCELr }, \ 3603 { 0x00031474, "CMIC_CMC0_HOSTMEM_ADDR_REMAP_0", CMIC_CMC0_HOSTMEM_ADDR_REMAP_0r }, \ 3604 { 0x00031478, "CMIC_CMC0_HOSTMEM_ADDR_REMAP_1", CMIC_CMC0_HOSTMEM_ADDR_REMAP_1r }, \ 3605 { 0x0003147c, "CMIC_CMC0_HOSTMEM_ADDR_REMAP_2", CMIC_CMC0_HOSTMEM_ADDR_REMAP_2r }, \ 3606 { 0x00031480, "CMIC_CMC0_PKT_COUNT_CH0_RXPKT", CMIC_CMC0_PKT_COUNT_CH0_RXPKTr }, \ 3607 { 0x00031484, "CMIC_CMC0_PKT_COUNT_CH0_TXPKT", CMIC_CMC0_PKT_COUNT_CH0_TXPKTr }, \ 3608 { 0x00031488, "CMIC_CMC0_PKT_COUNT_CH1_RXPKT", CMIC_CMC0_PKT_COUNT_CH1_RXPKTr }, \ 3609 { 0x0003148c, "CMIC_CMC0_PKT_COUNT_CH1_TXPKT", CMIC_CMC0_PKT_COUNT_CH1_TXPKTr }, \ 3610 { 0x00031490, "CMIC_CMC0_PKT_COUNT_CH2_RXPKT", CMIC_CMC0_PKT_COUNT_CH2_RXPKTr }, \ 3611 { 0x00031494, "CMIC_CMC0_PKT_COUNT_CH2_TXPKT", CMIC_CMC0_PKT_COUNT_CH2_TXPKTr }, \ 3612 { 0x00031498, "CMIC_CMC0_PKT_COUNT_CH3_RXPKT", CMIC_CMC0_PKT_COUNT_CH3_RXPKTr }, \ 3613 { 0x0003149c, "CMIC_CMC0_PKT_COUNT_CH3_TXPKT", CMIC_CMC0_PKT_COUNT_CH3_TXPKTr }, \ 3614 { 0x000314a0, "CMIC_CMC0_PKT_COUNT_RXPKT", CMIC_CMC0_PKT_COUNT_RXPKTr }, \ 3615 { 0x000314a4, "CMIC_CMC0_PKT_COUNT_TXPKT", CMIC_CMC0_PKT_COUNT_TXPKTr }, \ 3616 { 0x000314a8, "CMIC_CMC0_SW_INTR_CONFIG", CMIC_CMC0_SW_INTR_CONFIGr }, \ 3617 { 0x000314ac, "CMIC_CMC0_HOSTMEM_ADDR_REMAP_3", CMIC_CMC0_HOSTMEM_ADDR_REMAP_3r }, \ 3618 { 0x000314b0, "CMIC_CMC0_IRQ_STAT5", CMIC_CMC0_IRQ_STAT5r }, \ 3619 { 0x000314b4, "CMIC_CMC0_IRQ_STAT6", CMIC_CMC0_IRQ_STAT6r }, \ 3620 { 0x000314b8, "CMIC_CMC0_PCIE_IRQ_MASK5", CMIC_CMC0_PCIE_IRQ_MASK5r }, \ 3621 { 0x000314bc, "CMIC_CMC0_PCIE_IRQ_MASK6", CMIC_CMC0_PCIE_IRQ_MASK6r }, \ 3622 { 0x000314c0, "CMIC_CMC0_UC0_IRQ_MASK5", CMIC_CMC0_UC0_IRQ_MASK5r }, \ 3623 { 0x000314c4, "CMIC_CMC0_UC0_IRQ_MASK6", CMIC_CMC0_UC0_IRQ_MASK6r }, \ 3624 { 0x000314c8, "CMIC_CMC0_UC1_IRQ_MASK5", CMIC_CMC0_UC1_IRQ_MASK5r }, \ 3625 { 0x000314cc, "CMIC_CMC0_UC1_IRQ_MASK6", CMIC_CMC0_UC1_IRQ_MASK6r }, \ 3626 { 0x000314d0, "CMIC_CMC0_AXIIC_DMA_ECC_INTR_ENABLE", CMIC_CMC0_AXIIC_DMA_ECC_INTR_ENABLEr }, \ 3627 { 0x000314d4, "CMIC_CMC0_AXIIC_DMA_ECC_INTR", CMIC_CMC0_AXIIC_DMA_ECC_INTRr }, \ 3628 { 0x000314d8, "CMIC_CMC0_AXIIC_DMA_ECC_INTR_CLR", CMIC_CMC0_AXIIC_DMA_ECC_INTR_CLRr }, \ 3629 { 0x00031600, "CMIC_CMC0_SBUSDMA_CH0_CONTROL", CMIC_CMC0_SBUSDMA_CH0_CONTROLr }, \ 3630 { 0x00031604, "CMIC_CMC0_SBUSDMA_CH0_REQUEST", CMIC_CMC0_SBUSDMA_CH0_REQUESTr }, \ 3631 { 0x00031608, "CMIC_CMC0_SBUSDMA_CH0_COUNT", CMIC_CMC0_SBUSDMA_CH0_COUNTr }, \ 3632 { 0x0003160c, "CMIC_CMC0_SBUSDMA_CH0_OPCODE", CMIC_CMC0_SBUSDMA_CH0_OPCODEr }, \ 3633 { 0x00031610, "CMIC_CMC0_SBUSDMA_CH0_SBUS_START_ADDRESS", CMIC_CMC0_SBUSDMA_CH0_SBUS_START_ADDRESSr }, \ 3634 { 0x00031614, "CMIC_CMC0_SBUSDMA_CH0_HOSTMEM_START_ADDRESS", CMIC_CMC0_SBUSDMA_CH0_HOSTMEM_START_ADDRESSr }, \ 3635 { 0x00031618, "CMIC_CMC0_SBUSDMA_CH0_DESC_START_ADDRESS", CMIC_CMC0_SBUSDMA_CH0_DESC_START_ADDRESSr }, \ 3636 { 0x0003161c, "CMIC_CMC0_SBUSDMA_CH0_STATUS", CMIC_CMC0_SBUSDMA_CH0_STATUSr }, \ 3637 { 0x00031620, "CMIC_CMC0_SBUSDMA_CH0_CUR_HOSTMEM_ADDRESS", CMIC_CMC0_SBUSDMA_CH0_CUR_HOSTMEM_ADDRESSr }, \ 3638 { 0x00031624, "CMIC_CMC0_SBUSDMA_CH0_CUR_SBUS_ADDRESS", CMIC_CMC0_SBUSDMA_CH0_CUR_SBUS_ADDRESSr }, \ 3639 { 0x00031628, "CMIC_CMC0_SBUSDMA_CH0_CUR_DESC_ADDRESS", CMIC_CMC0_SBUSDMA_CH0_CUR_DESC_ADDRESSr }, \ 3640 { 0x0003162c, "CMIC_CMC0_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_REQUEST", CMIC_CMC0_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_REQUESTr }, \ 3641 { 0x00031630, "CMIC_CMC0_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_COUNT", CMIC_CMC0_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_COUNTr }, \ 3642 { 0x00031634, "CMIC_CMC0_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_SBUS_START_ADDRESS", CMIC_CMC0_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_SBUS_START_ADDRESSr }, \ 3643 { 0x00031638, "CMIC_CMC0_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS", CMIC_CMC0_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESSr }, \ 3644 { 0x0003163c, "CMIC_CMC0_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_OPCODE", CMIC_CMC0_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_OPCODEr }, \ 3645 { 0x00031640, "CMIC_CMC0_SBUSDMA_CH0_SBUSDMA_DEBUG", CMIC_CMC0_SBUSDMA_CH0_SBUSDMA_DEBUGr }, \ 3646 { 0x00031644, "CMIC_CMC0_SBUSDMA_CH0_SBUSDMA_DEBUG_CLR", CMIC_CMC0_SBUSDMA_CH0_SBUSDMA_DEBUG_CLRr }, \ 3647 { 0x00031648, "CMIC_CMC0_SBUSDMA_CH0_SBUSDMA_ECCERR_ADDRESS", CMIC_CMC0_SBUSDMA_CH0_SBUSDMA_ECCERR_ADDRESSr }, \ 3648 { 0x0003164c, "CMIC_CMC0_SBUSDMA_CH0_SBUSDMA_ECCERR_CONTROL", CMIC_CMC0_SBUSDMA_CH0_SBUSDMA_ECCERR_CONTROLr }, \ 3649 { 0x00031650, "CMIC_CMC0_SBUSDMA_CH1_CONTROL", CMIC_CMC0_SBUSDMA_CH1_CONTROLr }, \ 3650 { 0x00031654, "CMIC_CMC0_SBUSDMA_CH1_REQUEST", CMIC_CMC0_SBUSDMA_CH1_REQUESTr }, \ 3651 { 0x00031658, "CMIC_CMC0_SBUSDMA_CH1_COUNT", CMIC_CMC0_SBUSDMA_CH1_COUNTr }, \ 3652 { 0x0003165c, "CMIC_CMC0_SBUSDMA_CH1_OPCODE", CMIC_CMC0_SBUSDMA_CH1_OPCODEr }, \ 3653 { 0x00031660, "CMIC_CMC0_SBUSDMA_CH1_SBUS_START_ADDRESS", CMIC_CMC0_SBUSDMA_CH1_SBUS_START_ADDRESSr }, \ 3654 { 0x00031664, "CMIC_CMC0_SBUSDMA_CH1_HOSTMEM_START_ADDRESS", CMIC_CMC0_SBUSDMA_CH1_HOSTMEM_START_ADDRESSr }, \ 3655 { 0x00031668, "CMIC_CMC0_SBUSDMA_CH1_DESC_START_ADDRESS", CMIC_CMC0_SBUSDMA_CH1_DESC_START_ADDRESSr }, \ 3656 { 0x0003166c, "CMIC_CMC0_SBUSDMA_CH1_STATUS", CMIC_CMC0_SBUSDMA_CH1_STATUSr }, \ 3657 { 0x00031670, "CMIC_CMC0_SBUSDMA_CH1_CUR_HOSTMEM_ADDRESS", CMIC_CMC0_SBUSDMA_CH1_CUR_HOSTMEM_ADDRESSr }, \ 3658 { 0x00031674, "CMIC_CMC0_SBUSDMA_CH1_CUR_SBUS_ADDRESS", CMIC_CMC0_SBUSDMA_CH1_CUR_SBUS_ADDRESSr }, \ 3659 { 0x00031678, "CMIC_CMC0_SBUSDMA_CH1_CUR_DESC_ADDRESS", CMIC_CMC0_SBUSDMA_CH1_CUR_DESC_ADDRESSr }, \ 3660 { 0x0003167c, "CMIC_CMC0_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_REQUEST", CMIC_CMC0_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_REQUESTr }, \ 3661 { 0x00031680, "CMIC_CMC0_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_COUNT", CMIC_CMC0_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_COUNTr }, \ 3662 { 0x00031684, "CMIC_CMC0_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_SBUS_START_ADDRESS", CMIC_CMC0_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_SBUS_START_ADDRESSr }, \ 3663 { 0x00031688, "CMIC_CMC0_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS", CMIC_CMC0_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESSr }, \ 3664 { 0x0003168c, "CMIC_CMC0_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_OPCODE", CMIC_CMC0_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_OPCODEr }, \ 3665 { 0x00031690, "CMIC_CMC0_SBUSDMA_CH1_SBUSDMA_DEBUG", CMIC_CMC0_SBUSDMA_CH1_SBUSDMA_DEBUGr }, \ 3666 { 0x00031694, "CMIC_CMC0_SBUSDMA_CH1_SBUSDMA_DEBUG_CLR", CMIC_CMC0_SBUSDMA_CH1_SBUSDMA_DEBUG_CLRr }, \ 3667 { 0x00031698, "CMIC_CMC0_SBUSDMA_CH1_SBUSDMA_ECCERR_ADDRESS", CMIC_CMC0_SBUSDMA_CH1_SBUSDMA_ECCERR_ADDRESSr }, \ 3668 { 0x0003169c, "CMIC_CMC0_SBUSDMA_CH1_SBUSDMA_ECCERR_CONTROL", CMIC_CMC0_SBUSDMA_CH1_SBUSDMA_ECCERR_CONTROLr }, \ 3669 { 0x000316a0, "CMIC_CMC0_SBUSDMA_CH2_CONTROL", CMIC_CMC0_SBUSDMA_CH2_CONTROLr }, \ 3670 { 0x000316a4, "CMIC_CMC0_SBUSDMA_CH2_REQUEST", CMIC_CMC0_SBUSDMA_CH2_REQUESTr }, \ 3671 { 0x000316a8, "CMIC_CMC0_SBUSDMA_CH2_COUNT", CMIC_CMC0_SBUSDMA_CH2_COUNTr }, \ 3672 { 0x000316ac, "CMIC_CMC0_SBUSDMA_CH2_OPCODE", CMIC_CMC0_SBUSDMA_CH2_OPCODEr }, \ 3673 { 0x000316b0, "CMIC_CMC0_SBUSDMA_CH2_SBUS_START_ADDRESS", CMIC_CMC0_SBUSDMA_CH2_SBUS_START_ADDRESSr }, \ 3674 { 0x000316b4, "CMIC_CMC0_SBUSDMA_CH2_HOSTMEM_START_ADDRESS", CMIC_CMC0_SBUSDMA_CH2_HOSTMEM_START_ADDRESSr }, \ 3675 { 0x000316b8, "CMIC_CMC0_SBUSDMA_CH2_DESC_START_ADDRESS", CMIC_CMC0_SBUSDMA_CH2_DESC_START_ADDRESSr }, \ 3676 { 0x000316bc, "CMIC_CMC0_SBUSDMA_CH2_STATUS", CMIC_CMC0_SBUSDMA_CH2_STATUSr }, \ 3677 { 0x000316c0, "CMIC_CMC0_SBUSDMA_CH2_CUR_HOSTMEM_ADDRESS", CMIC_CMC0_SBUSDMA_CH2_CUR_HOSTMEM_ADDRESSr }, \ 3678 { 0x000316c4, "CMIC_CMC0_SBUSDMA_CH2_CUR_SBUS_ADDRESS", CMIC_CMC0_SBUSDMA_CH2_CUR_SBUS_ADDRESSr }, \ 3679 { 0x000316c8, "CMIC_CMC0_SBUSDMA_CH2_CUR_DESC_ADDRESS", CMIC_CMC0_SBUSDMA_CH2_CUR_DESC_ADDRESSr }, \ 3680 { 0x000316cc, "CMIC_CMC0_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_REQUEST", CMIC_CMC0_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_REQUESTr }, \ 3681 { 0x000316d0, "CMIC_CMC0_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_COUNT", CMIC_CMC0_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_COUNTr }, \ 3682 { 0x000316d4, "CMIC_CMC0_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_SBUS_START_ADDRESS", CMIC_CMC0_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_SBUS_START_ADDRESSr }, \ 3683 { 0x000316d8, "CMIC_CMC0_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS", CMIC_CMC0_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESSr }, \ 3684 { 0x000316dc, "CMIC_CMC0_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_OPCODE", CMIC_CMC0_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_OPCODEr }, \ 3685 { 0x000316e0, "CMIC_CMC0_SBUSDMA_CH2_SBUSDMA_DEBUG", CMIC_CMC0_SBUSDMA_CH2_SBUSDMA_DEBUGr }, \ 3686 { 0x000316e4, "CMIC_CMC0_SBUSDMA_CH2_SBUSDMA_DEBUG_CLR", CMIC_CMC0_SBUSDMA_CH2_SBUSDMA_DEBUG_CLRr }, \ 3687 { 0x000316e8, "CMIC_CMC0_SBUSDMA_CH2_SBUSDMA_ECCERR_ADDRESS", CMIC_CMC0_SBUSDMA_CH2_SBUSDMA_ECCERR_ADDRESSr }, \ 3688 { 0x000316ec, "CMIC_CMC0_SBUSDMA_CH2_SBUSDMA_ECCERR_CONTROL", CMIC_CMC0_SBUSDMA_CH2_SBUSDMA_ECCERR_CONTROLr }, \ 3689 { 0x000316f0, "CMIC_CMC0_SBUSDMA_CH0_TIMER", CMIC_CMC0_SBUSDMA_CH0_TIMERr }, \ 3690 { 0x000316f4, "CMIC_CMC0_SBUSDMA_CH1_TIMER", CMIC_CMC0_SBUSDMA_CH1_TIMERr }, \ 3691 { 0x000316f8, "CMIC_CMC0_SBUSDMA_CH2_TIMER", CMIC_CMC0_SBUSDMA_CH2_TIMERr }, \ 3692 { 0x000316fc, "CMIC_CMC0_SBUSDMA_CH0_ITER_COUNT", CMIC_CMC0_SBUSDMA_CH0_ITER_COUNTr }, \ 3693 { 0x00031700, "CMIC_CMC0_SBUSDMA_CH1_ITER_COUNT", CMIC_CMC0_SBUSDMA_CH1_ITER_COUNTr }, \ 3694 { 0x00031704, "CMIC_CMC0_SBUSDMA_CH2_ITER_COUNT", CMIC_CMC0_SBUSDMA_CH2_ITER_COUNTr }, \ 3695 { 0x00031800, "CMIC_CMC0_SBUSDMA_CH0_TM_CONTROL_0", CMIC_CMC0_SBUSDMA_CH0_TM_CONTROL_0r }, \ 3696 { 0x00031804, "CMIC_CMC0_SBUSDMA_CH0_TM_CONTROL_1", CMIC_CMC0_SBUSDMA_CH0_TM_CONTROL_1r }, \ 3697 { 0x0003180c, "CMIC_CMC0_SBUSDMA_CH0_TM_CONTROL_2", CMIC_CMC0_SBUSDMA_CH0_TM_CONTROL_2r }, \ 3698 { 0x00031810, "CMIC_CMC0_SBUSDMA_CH1_TM_CONTROL_0", CMIC_CMC0_SBUSDMA_CH1_TM_CONTROL_0r }, \ 3699 { 0x00031814, "CMIC_CMC0_SBUSDMA_CH1_TM_CONTROL_1", CMIC_CMC0_SBUSDMA_CH1_TM_CONTROL_1r }, \ 3700 { 0x00031818, "CMIC_CMC0_SBUSDMA_CH1_TM_CONTROL_2", CMIC_CMC0_SBUSDMA_CH1_TM_CONTROL_2r }, \ 3701 { 0x0003181c, "CMIC_CMC0_SBUSDMA_CH2_TM_CONTROL_0", CMIC_CMC0_SBUSDMA_CH2_TM_CONTROL_0r }, \ 3702 { 0x00031820, "CMIC_CMC0_SBUSDMA_CH2_TM_CONTROL_1", CMIC_CMC0_SBUSDMA_CH2_TM_CONTROL_1r }, \ 3703 { 0x00031824, "CMIC_CMC0_SBUSDMA_CH2_TM_CONTROL_2", CMIC_CMC0_SBUSDMA_CH2_TM_CONTROL_2r }, \ 3704 { 0x00031828, "CMIC_CMC0_FIFORDDMA_CH0_TM_CONTROL_0", CMIC_CMC0_FIFORDDMA_CH0_TM_CONTROL_0r }, \ 3705 { 0x0003182c, "CMIC_CMC0_FIFORDDMA_CH0_TM_CONTROL_1", CMIC_CMC0_FIFORDDMA_CH0_TM_CONTROL_1r }, \ 3706 { 0x00031830, "CMIC_CMC0_FIFORDDMA_CH1_TM_CONTROL_0", CMIC_CMC0_FIFORDDMA_CH1_TM_CONTROL_0r }, \ 3707 { 0x00031834, "CMIC_CMC0_FIFORDDMA_CH1_TM_CONTROL_1", CMIC_CMC0_FIFORDDMA_CH1_TM_CONTROL_1r }, \ 3708 { 0x00031838, "CMIC_CMC0_FIFORDDMA_CH2_TM_CONTROL_0", CMIC_CMC0_FIFORDDMA_CH2_TM_CONTROL_0r }, \ 3709 { 0x0003183c, "CMIC_CMC0_FIFORDDMA_CH2_TM_CONTROL_1", CMIC_CMC0_FIFORDDMA_CH2_TM_CONTROL_1r }, \ 3710 { 0x00031840, "CMIC_CMC0_FIFORDDMA_CH3_TM_CONTROL_0", CMIC_CMC0_FIFORDDMA_CH3_TM_CONTROL_0r }, \ 3711 { 0x00031844, "CMIC_CMC0_FIFORDDMA_CH3_TM_CONTROL_1", CMIC_CMC0_FIFORDDMA_CH3_TM_CONTROL_1r }, \ 3712 { 0x00031848, "CMIC_CMC0_CCMDMA_TM_CONTROL_0", CMIC_CMC0_CCMDMA_TM_CONTROL_0r }, \ 3713 { 0x0003184c, "CMIC_CMC0_CCMDMA_TM_CONTROL_1", CMIC_CMC0_CCMDMA_TM_CONTROL_1r }, \ 3714 { 0x00031850, "CMIC_CMC0_AXIIC_TM_CONTROL_0", CMIC_CMC0_AXIIC_TM_CONTROL_0r }, \ 3715 { 0x00031854, "CMIC_CMC0_AXIIC_TM_CONTROL_1", CMIC_CMC0_AXIIC_TM_CONTROL_1r }, \ 3716 { 0x00031858, "CMIC_CMC0_AXIIC_TM_CONTROL_2", CMIC_CMC0_AXIIC_TM_CONTROL_2r }, \ 3717 { 0x00032000, "CMIC_CMC1_SCHAN_CTRL", CMIC_CMC1_SCHAN_CTRLr }, \ 3718 { 0x00032004, "CMIC_CMC1_SCHAN_ACK_DATA_BEAT_COUNT", CMIC_CMC1_SCHAN_ACK_DATA_BEAT_COUNTr }, \ 3719 { 0x00032008, "CMIC_CMC1_SCHAN_ERR", CMIC_CMC1_SCHAN_ERRr }, \ 3720 { 0x0003200c, "CMIC_CMC1_SCHAN_MESSAGE", CMIC_CMC1_SCHAN_MESSAGEr }, \ 3721 { 0x0003200c, "CMIC_CMC1_SCHAN_MESSAGE0", CMIC_CMC1_SCHAN_MESSAGE0r }, \ 3722 { 0x00032010, "CMIC_CMC1_SCHAN_MESSAGE1", CMIC_CMC1_SCHAN_MESSAGE1r }, \ 3723 { 0x00032014, "CMIC_CMC1_SCHAN_MESSAGE2", CMIC_CMC1_SCHAN_MESSAGE2r }, \ 3724 { 0x00032018, "CMIC_CMC1_SCHAN_MESSAGE3", CMIC_CMC1_SCHAN_MESSAGE3r }, \ 3725 { 0x0003201c, "CMIC_CMC1_SCHAN_MESSAGE4", CMIC_CMC1_SCHAN_MESSAGE4r }, \ 3726 { 0x00032020, "CMIC_CMC1_SCHAN_MESSAGE5", CMIC_CMC1_SCHAN_MESSAGE5r }, \ 3727 { 0x00032024, "CMIC_CMC1_SCHAN_MESSAGE6", CMIC_CMC1_SCHAN_MESSAGE6r }, \ 3728 { 0x00032028, "CMIC_CMC1_SCHAN_MESSAGE7", CMIC_CMC1_SCHAN_MESSAGE7r }, \ 3729 { 0x0003202c, "CMIC_CMC1_SCHAN_MESSAGE8", CMIC_CMC1_SCHAN_MESSAGE8r }, \ 3730 { 0x00032030, "CMIC_CMC1_SCHAN_MESSAGE9", CMIC_CMC1_SCHAN_MESSAGE9r }, \ 3731 { 0x00032034, "CMIC_CMC1_SCHAN_MESSAGE10", CMIC_CMC1_SCHAN_MESSAGE10r }, \ 3732 { 0x00032038, "CMIC_CMC1_SCHAN_MESSAGE11", CMIC_CMC1_SCHAN_MESSAGE11r }, \ 3733 { 0x0003203c, "CMIC_CMC1_SCHAN_MESSAGE12", CMIC_CMC1_SCHAN_MESSAGE12r }, \ 3734 { 0x00032040, "CMIC_CMC1_SCHAN_MESSAGE13", CMIC_CMC1_SCHAN_MESSAGE13r }, \ 3735 { 0x00032044, "CMIC_CMC1_SCHAN_MESSAGE14", CMIC_CMC1_SCHAN_MESSAGE14r }, \ 3736 { 0x00032048, "CMIC_CMC1_SCHAN_MESSAGE15", CMIC_CMC1_SCHAN_MESSAGE15r }, \ 3737 { 0x0003204c, "CMIC_CMC1_SCHAN_MESSAGE16", CMIC_CMC1_SCHAN_MESSAGE16r }, \ 3738 { 0x00032050, "CMIC_CMC1_SCHAN_MESSAGE17", CMIC_CMC1_SCHAN_MESSAGE17r }, \ 3739 { 0x00032054, "CMIC_CMC1_SCHAN_MESSAGE18", CMIC_CMC1_SCHAN_MESSAGE18r }, \ 3740 { 0x00032058, "CMIC_CMC1_SCHAN_MESSAGE19", CMIC_CMC1_SCHAN_MESSAGE19r }, \ 3741 { 0x0003205c, "CMIC_CMC1_SCHAN_MESSAGE20", CMIC_CMC1_SCHAN_MESSAGE20r }, \ 3742 { 0x00032060, "CMIC_CMC1_SCHAN_MESSAGE21", CMIC_CMC1_SCHAN_MESSAGE21r }, \ 3743 { 0x00032064, "CMIC_CMC1_FSCHAN_ENABLE_PROGRAMMABLE_OPCODE", CMIC_CMC1_FSCHAN_ENABLE_PROGRAMMABLE_OPCODEr }, \ 3744 { 0x00032068, "CMIC_CMC1_FSCHAN_STATUS", CMIC_CMC1_FSCHAN_STATUSr }, \ 3745 { 0x0003206c, "CMIC_CMC1_FSCHAN_OPCODE", CMIC_CMC1_FSCHAN_OPCODEr }, \ 3746 { 0x00032070, "CMIC_CMC1_FSCHAN_ADDRESS", CMIC_CMC1_FSCHAN_ADDRESSr }, \ 3747 { 0x00032074, "CMIC_CMC1_FSCHAN_DATA32", CMIC_CMC1_FSCHAN_DATA32r }, \ 3748 { 0x00032078, "CMIC_CMC1_FSCHAN_DATA64_LO", CMIC_CMC1_FSCHAN_DATA64_LOr }, \ 3749 { 0x0003207c, "CMIC_CMC1_FSCHAN_DATA64_HI", CMIC_CMC1_FSCHAN_DATA64_HIr }, \ 3750 { 0x00032080, "CMIC_CMC1_MIIM_PARAM", CMIC_CMC1_MIIM_PARAMr }, \ 3751 { 0x00032084, "CMIC_CMC1_MIIM_READ_DATA", CMIC_CMC1_MIIM_READ_DATAr }, \ 3752 { 0x00032088, "CMIC_CMC1_MIIM_ADDRESS", CMIC_CMC1_MIIM_ADDRESSr }, \ 3753 { 0x0003208c, "CMIC_CMC1_MIIM_CTRL", CMIC_CMC1_MIIM_CTRLr }, \ 3754 { 0x00032090, "CMIC_CMC1_MIIM_STAT", CMIC_CMC1_MIIM_STATr }, \ 3755 { 0x00032100, "CMIC_CMC1_TM_CONTROL_0", CMIC_CMC1_TM_CONTROL_0r }, \ 3756 { 0x00032104, "CMIC_CMC1_TM_CONTROL_1", CMIC_CMC1_TM_CONTROL_1r }, \ 3757 { 0x00032108, "CMIC_CMC1_CONFIG", CMIC_CMC1_CONFIGr }, \ 3758 { 0x0003210c, "CMIC_CMC1_STAT", CMIC_CMC1_STATr }, \ 3759 { 0x00032110, "CMIC_CMC1_CH0_RXBUF_THRESHOLD_CONFIG", CMIC_CMC1_CH0_RXBUF_THRESHOLD_CONFIGr }, \ 3760 { 0x00032114, "CMIC_CMC1_CH1_RXBUF_THRESHOLD_CONFIG", CMIC_CMC1_CH1_RXBUF_THRESHOLD_CONFIGr }, \ 3761 { 0x00032118, "CMIC_CMC1_CH2_RXBUF_THRESHOLD_CONFIG", CMIC_CMC1_CH2_RXBUF_THRESHOLD_CONFIGr }, \ 3762 { 0x0003211c, "CMIC_CMC1_CH3_RXBUF_THRESHOLD_CONFIG", CMIC_CMC1_CH3_RXBUF_THRESHOLD_CONFIGr }, \ 3763 { 0x00032120, "CMIC_CMC1_DMA_CH0_DESC_HALT_ADDR", CMIC_CMC1_DMA_CH0_DESC_HALT_ADDRr }, \ 3764 { 0x00032124, "CMIC_CMC1_DMA_CH1_DESC_HALT_ADDR", CMIC_CMC1_DMA_CH1_DESC_HALT_ADDRr }, \ 3765 { 0x00032128, "CMIC_CMC1_DMA_CH2_DESC_HALT_ADDR", CMIC_CMC1_DMA_CH2_DESC_HALT_ADDRr }, \ 3766 { 0x0003212c, "CMIC_CMC1_DMA_CH3_DESC_HALT_ADDR", CMIC_CMC1_DMA_CH3_DESC_HALT_ADDRr }, \ 3767 { 0x00032130, "CMIC_CMC1_DMA_STAT_HI", CMIC_CMC1_DMA_STAT_HIr }, \ 3768 { 0x00032140, "CMIC_CMC1_CH0_DMA_CTRL", CMIC_CMC1_CH0_DMA_CTRLr }, \ 3769 { 0x00032144, "CMIC_CMC1_CH1_DMA_CTRL", CMIC_CMC1_CH1_DMA_CTRLr }, \ 3770 { 0x00032148, "CMIC_CMC1_CH2_DMA_CTRL", CMIC_CMC1_CH2_DMA_CTRLr }, \ 3771 { 0x0003214c, "CMIC_CMC1_CH3_DMA_CTRL", CMIC_CMC1_CH3_DMA_CTRLr }, \ 3772 { 0x00032150, "CMIC_CMC1_DMA_STAT", CMIC_CMC1_DMA_STATr }, \ 3773 { 0x00032158, "CMIC_CMC1_DMA_DESC0", CMIC_CMC1_DMA_DESC0r }, \ 3774 { 0x0003215c, "CMIC_CMC1_DMA_DESC1", CMIC_CMC1_DMA_DESC1r }, \ 3775 { 0x00032160, "CMIC_CMC1_DMA_DESC2", CMIC_CMC1_DMA_DESC2r }, \ 3776 { 0x00032164, "CMIC_CMC1_DMA_DESC3", CMIC_CMC1_DMA_DESC3r }, \ 3777 { 0x00032168, "CMIC_CMC1_CH0_COS_CTRL_RX_0", CMIC_CMC1_CH0_COS_CTRL_RX_0r }, \ 3778 { 0x0003216c, "CMIC_CMC1_CH0_COS_CTRL_RX_1", CMIC_CMC1_CH0_COS_CTRL_RX_1r }, \ 3779 { 0x00032170, "CMIC_CMC1_CH1_COS_CTRL_RX_0", CMIC_CMC1_CH1_COS_CTRL_RX_0r }, \ 3780 { 0x00032174, "CMIC_CMC1_CH1_COS_CTRL_RX_1", CMIC_CMC1_CH1_COS_CTRL_RX_1r }, \ 3781 { 0x00032178, "CMIC_CMC1_CH2_COS_CTRL_RX_0", CMIC_CMC1_CH2_COS_CTRL_RX_0r }, \ 3782 { 0x0003217c, "CMIC_CMC1_CH2_COS_CTRL_RX_1", CMIC_CMC1_CH2_COS_CTRL_RX_1r }, \ 3783 { 0x00032180, "CMIC_CMC1_CH3_COS_CTRL_RX_0", CMIC_CMC1_CH3_COS_CTRL_RX_0r }, \ 3784 { 0x00032184, "CMIC_CMC1_CH3_COS_CTRL_RX_1", CMIC_CMC1_CH3_COS_CTRL_RX_1r }, \ 3785 { 0x00032188, "CMIC_CMC1_DMA_CH0_INTR_COAL", CMIC_CMC1_DMA_CH0_INTR_COALr }, \ 3786 { 0x0003218c, "CMIC_CMC1_DMA_CH1_INTR_COAL", CMIC_CMC1_DMA_CH1_INTR_COALr }, \ 3787 { 0x00032190, "CMIC_CMC1_DMA_CH2_INTR_COAL", CMIC_CMC1_DMA_CH2_INTR_COALr }, \ 3788 { 0x00032194, "CMIC_CMC1_DMA_CH3_INTR_COAL", CMIC_CMC1_DMA_CH3_INTR_COALr }, \ 3789 { 0x00032198, "CMIC_CMC1_RXBUF_THRESHOLD_CONFIG", CMIC_CMC1_RXBUF_THRESHOLD_CONFIGr }, \ 3790 { 0x0003219c, "CMIC_CMC1_PROGRAMMABLE_COS_MASK0", CMIC_CMC1_PROGRAMMABLE_COS_MASK0r }, \ 3791 { 0x000321a0, "CMIC_CMC1_PROGRAMMABLE_COS_MASK1", CMIC_CMC1_PROGRAMMABLE_COS_MASK1r }, \ 3792 { 0x000321a4, "CMIC_CMC1_DMA_STAT_CLR", CMIC_CMC1_DMA_STAT_CLRr }, \ 3793 { 0x000321a8, "CMIC_CMC1_CH0_DMA_CURR_DESC", CMIC_CMC1_CH0_DMA_CURR_DESCr }, \ 3794 { 0x000321ac, "CMIC_CMC1_CH1_DMA_CURR_DESC", CMIC_CMC1_CH1_DMA_CURR_DESCr }, \ 3795 { 0x000321b0, "CMIC_CMC1_CH2_DMA_CURR_DESC", CMIC_CMC1_CH2_DMA_CURR_DESCr }, \ 3796 { 0x000321b4, "CMIC_CMC1_CH3_DMA_CURR_DESC", CMIC_CMC1_CH3_DMA_CURR_DESCr }, \ 3797 { 0x000321c0, "CMIC_CMC1_STAT_DMA_ADDR", CMIC_CMC1_STAT_DMA_ADDRr }, \ 3798 { 0x000321c4, "CMIC_CMC1_STAT_DMA_CFG", CMIC_CMC1_STAT_DMA_CFGr }, \ 3799 { 0x000321c8, "CMIC_CMC1_STAT_DMA_PORTS_0", CMIC_CMC1_STAT_DMA_PORTS_0r }, \ 3800 { 0x000321cc, "CMIC_CMC1_STAT_DMA_PORTS_1", CMIC_CMC1_STAT_DMA_PORTS_1r }, \ 3801 { 0x000321d0, "CMIC_CMC1_STAT_DMA_PORTS_2", CMIC_CMC1_STAT_DMA_PORTS_2r }, \ 3802 { 0x000321d4, "CMIC_CMC1_STAT_DMA_CURRENT", CMIC_CMC1_STAT_DMA_CURRENTr }, \ 3803 { 0x000321d8, "CMIC_CMC1_STAT_DMA_SBUS_START_ADDRESS", CMIC_CMC1_STAT_DMA_SBUS_START_ADDRESSr }, \ 3804 { 0x000321dc, "CMIC_CMC1_STAT_DMA_STAT", CMIC_CMC1_STAT_DMA_STATr }, \ 3805 { 0x00032200, "CMIC_CMC1_SLAM_DMA_PCIMEM_START_ADDR", CMIC_CMC1_SLAM_DMA_PCIMEM_START_ADDRr }, \ 3806 { 0x00032204, "CMIC_CMC1_SLAM_DMA_SBUS_START_ADDR", CMIC_CMC1_SLAM_DMA_SBUS_START_ADDRr }, \ 3807 { 0x00032208, "CMIC_CMC1_SLAM_DMA_ENTRY_COUNT", CMIC_CMC1_SLAM_DMA_ENTRY_COUNTr }, \ 3808 { 0x0003220c, "CMIC_CMC1_SLAM_DMA_CFG", CMIC_CMC1_SLAM_DMA_CFGr }, \ 3809 { 0x00032210, "CMIC_CMC1_SLAM_DMA_STAT", CMIC_CMC1_SLAM_DMA_STATr }, \ 3810 { 0x00032214, "CMIC_CMC1_SLAM_DMA_CUR_ENTRY_SBUS_ADDR", CMIC_CMC1_SLAM_DMA_CUR_ENTRY_SBUS_ADDRr }, \ 3811 { 0x00032218, "CMIC_CMC1_SLAM_DMA_SBUS_CMD_CONFIG", CMIC_CMC1_SLAM_DMA_SBUS_CMD_CONFIGr }, \ 3812 { 0x00032240, "CMIC_CMC1_TABLE_DMA_PCIMEM_START_ADDR", CMIC_CMC1_TABLE_DMA_PCIMEM_START_ADDRr }, \ 3813 { 0x00032244, "CMIC_CMC1_TABLE_DMA_SBUS_START_ADDR", CMIC_CMC1_TABLE_DMA_SBUS_START_ADDRr }, \ 3814 { 0x00032248, "CMIC_CMC1_TABLE_DMA_ENTRY_COUNT", CMIC_CMC1_TABLE_DMA_ENTRY_COUNTr }, \ 3815 { 0x0003224c, "CMIC_CMC1_TABLE_DMA_CFG", CMIC_CMC1_TABLE_DMA_CFGr }, \ 3816 { 0x00032250, "CMIC_CMC1_TABLE_DMA_STAT", CMIC_CMC1_TABLE_DMA_STATr }, \ 3817 { 0x00032254, "CMIC_CMC1_TABLE_DMA_CUR_ENTRY_SBUS_ADDR", CMIC_CMC1_TABLE_DMA_CUR_ENTRY_SBUS_ADDRr }, \ 3818 { 0x00032258, "CMIC_CMC1_TABLE_DMA_SBUS_CMD_CONFIG", CMIC_CMC1_TABLE_DMA_SBUS_CMD_CONFIGr }, \ 3819 { 0x000322c0, "CMIC_CMC1_FIFO_CH0_RD_DMA_CFG", CMIC_CMC1_FIFO_CH0_RD_DMA_CFGr }, \ 3820 { 0x000322c4, "CMIC_CMC1_FIFO_CH1_RD_DMA_CFG", CMIC_CMC1_FIFO_CH1_RD_DMA_CFGr }, \ 3821 { 0x000322c8, "CMIC_CMC1_FIFO_CH2_RD_DMA_CFG", CMIC_CMC1_FIFO_CH2_RD_DMA_CFGr }, \ 3822 { 0x000322cc, "CMIC_CMC1_FIFO_CH3_RD_DMA_CFG", CMIC_CMC1_FIFO_CH3_RD_DMA_CFGr }, \ 3823 { 0x000322d0, "CMIC_CMC1_FIFO_CH0_RD_DMA_SBUS_START_ADDRESS", CMIC_CMC1_FIFO_CH0_RD_DMA_SBUS_START_ADDRESSr }, \ 3824 { 0x000322d4, "CMIC_CMC1_FIFO_CH1_RD_DMA_SBUS_START_ADDRESS", CMIC_CMC1_FIFO_CH1_RD_DMA_SBUS_START_ADDRESSr }, \ 3825 { 0x000322d8, "CMIC_CMC1_FIFO_CH2_RD_DMA_SBUS_START_ADDRESS", CMIC_CMC1_FIFO_CH2_RD_DMA_SBUS_START_ADDRESSr }, \ 3826 { 0x000322dc, "CMIC_CMC1_FIFO_CH3_RD_DMA_SBUS_START_ADDRESS", CMIC_CMC1_FIFO_CH3_RD_DMA_SBUS_START_ADDRESSr }, \ 3827 { 0x000322e0, "CMIC_CMC1_FIFO_CH0_RD_DMA_HOSTMEM_START_ADDRESS", CMIC_CMC1_FIFO_CH0_RD_DMA_HOSTMEM_START_ADDRESSr }, \ 3828 { 0x000322e4, "CMIC_CMC1_FIFO_CH1_RD_DMA_HOSTMEM_START_ADDRESS", CMIC_CMC1_FIFO_CH1_RD_DMA_HOSTMEM_START_ADDRESSr }, \ 3829 { 0x000322e8, "CMIC_CMC1_FIFO_CH2_RD_DMA_HOSTMEM_START_ADDRESS", CMIC_CMC1_FIFO_CH2_RD_DMA_HOSTMEM_START_ADDRESSr }, \ 3830 { 0x000322ec, "CMIC_CMC1_FIFO_CH3_RD_DMA_HOSTMEM_START_ADDRESS", CMIC_CMC1_FIFO_CH3_RD_DMA_HOSTMEM_START_ADDRESSr }, \ 3831 { 0x000322f0, "CMIC_CMC1_FIFO_CH0_RD_DMA_HOSTMEM_READ_PTR", CMIC_CMC1_FIFO_CH0_RD_DMA_HOSTMEM_READ_PTRr }, \ 3832 { 0x000322f0, "CMIC_CMC1_FIFO_CH0_RD_DMA_NUM_OF_ENTRIES_READ_FRM_HOSTMEM", CMIC_CMC1_FIFO_CH0_RD_DMA_NUM_OF_ENTRIES_READ_FRM_HOSTMEMr }, \ 3833 { 0x000322f4, "CMIC_CMC1_FIFO_CH0_RD_DMA_HOSTMEM_WRITE_PTR", CMIC_CMC1_FIFO_CH0_RD_DMA_HOSTMEM_WRITE_PTRr }, \ 3834 { 0x000322f4, "CMIC_CMC1_FIFO_CH0_RD_DMA_NUM_OF_ENTRIES_VALID_IN_HOSTMEM", CMIC_CMC1_FIFO_CH0_RD_DMA_NUM_OF_ENTRIES_VALID_IN_HOSTMEMr }, \ 3835 { 0x000322f8, "CMIC_CMC1_FIFO_CH1_RD_DMA_NUM_OF_ENTRIES_READ_FRM_HOSTMEM", CMIC_CMC1_FIFO_CH1_RD_DMA_NUM_OF_ENTRIES_READ_FRM_HOSTMEMr }, \ 3836 { 0x000322f8, "CMIC_CMC1_FIFO_CH1_RD_DMA_HOSTMEM_READ_PTR", CMIC_CMC1_FIFO_CH1_RD_DMA_HOSTMEM_READ_PTRr }, \ 3837 { 0x000322fc, "CMIC_CMC1_FIFO_CH1_RD_DMA_NUM_OF_ENTRIES_VALID_IN_HOSTMEM", CMIC_CMC1_FIFO_CH1_RD_DMA_NUM_OF_ENTRIES_VALID_IN_HOSTMEMr }, \ 3838 { 0x000322fc, "CMIC_CMC1_FIFO_CH1_RD_DMA_HOSTMEM_WRITE_PTR", CMIC_CMC1_FIFO_CH1_RD_DMA_HOSTMEM_WRITE_PTRr }, \ 3839 { 0x00032300, "CMIC_CMC1_FIFO_CH2_RD_DMA_NUM_OF_ENTRIES_READ_FRM_HOSTMEM", CMIC_CMC1_FIFO_CH2_RD_DMA_NUM_OF_ENTRIES_READ_FRM_HOSTMEMr }, \ 3840 { 0x00032300, "CMIC_CMC1_FIFO_CH2_RD_DMA_HOSTMEM_READ_PTR", CMIC_CMC1_FIFO_CH2_RD_DMA_HOSTMEM_READ_PTRr }, \ 3841 { 0x00032304, "CMIC_CMC1_FIFO_CH2_RD_DMA_NUM_OF_ENTRIES_VALID_IN_HOSTMEM", CMIC_CMC1_FIFO_CH2_RD_DMA_NUM_OF_ENTRIES_VALID_IN_HOSTMEMr }, \ 3842 { 0x00032304, "CMIC_CMC1_FIFO_CH2_RD_DMA_HOSTMEM_WRITE_PTR", CMIC_CMC1_FIFO_CH2_RD_DMA_HOSTMEM_WRITE_PTRr }, \ 3843 { 0x00032308, "CMIC_CMC1_FIFO_CH3_RD_DMA_HOSTMEM_READ_PTR", CMIC_CMC1_FIFO_CH3_RD_DMA_HOSTMEM_READ_PTRr }, \ 3844 { 0x00032308, "CMIC_CMC1_FIFO_CH3_RD_DMA_NUM_OF_ENTRIES_READ_FRM_HOSTMEM", CMIC_CMC1_FIFO_CH3_RD_DMA_NUM_OF_ENTRIES_READ_FRM_HOSTMEMr }, \ 3845 { 0x0003230c, "CMIC_CMC1_FIFO_CH3_RD_DMA_HOSTMEM_WRITE_PTR", CMIC_CMC1_FIFO_CH3_RD_DMA_HOSTMEM_WRITE_PTRr }, \ 3846 { 0x0003230c, "CMIC_CMC1_FIFO_CH3_RD_DMA_NUM_OF_ENTRIES_VALID_IN_HOSTMEM", CMIC_CMC1_FIFO_CH3_RD_DMA_NUM_OF_ENTRIES_VALID_IN_HOSTMEMr }, \ 3847 { 0x00032310, "CMIC_CMC1_FIFO_CH0_RD_DMA_ECCERR_ADDRESS", CMIC_CMC1_FIFO_CH0_RD_DMA_ECCERR_ADDRESSr }, \ 3848 { 0x00032314, "CMIC_CMC1_FIFO_CH1_RD_DMA_ECCERR_ADDRESS", CMIC_CMC1_FIFO_CH1_RD_DMA_ECCERR_ADDRESSr }, \ 3849 { 0x00032318, "CMIC_CMC1_FIFO_CH2_RD_DMA_ECCERR_ADDRESS", CMIC_CMC1_FIFO_CH2_RD_DMA_ECCERR_ADDRESSr }, \ 3850 { 0x0003231c, "CMIC_CMC1_FIFO_CH3_RD_DMA_ECCERR_ADDRESS", CMIC_CMC1_FIFO_CH3_RD_DMA_ECCERR_ADDRESSr }, \ 3851 { 0x00032320, "CMIC_CMC1_FIFO_CH0_RD_DMA_ECCERR_CONTROL", CMIC_CMC1_FIFO_CH0_RD_DMA_ECCERR_CONTROLr }, \ 3852 { 0x00032324, "CMIC_CMC1_FIFO_CH1_RD_DMA_ECCERR_CONTROL", CMIC_CMC1_FIFO_CH1_RD_DMA_ECCERR_CONTROLr }, \ 3853 { 0x00032328, "CMIC_CMC1_FIFO_CH2_RD_DMA_ECCERR_CONTROL", CMIC_CMC1_FIFO_CH2_RD_DMA_ECCERR_CONTROLr }, \ 3854 { 0x0003232c, "CMIC_CMC1_FIFO_CH3_RD_DMA_ECCERR_CONTROL", CMIC_CMC1_FIFO_CH3_RD_DMA_ECCERR_CONTROLr }, \ 3855 { 0x00032330, "CMIC_CMC1_FIFO_CH0_RD_DMA_CUR_HOSTMEM_WRITE_PTR", CMIC_CMC1_FIFO_CH0_RD_DMA_CUR_HOSTMEM_WRITE_PTRr }, \ 3856 { 0x00032334, "CMIC_CMC1_FIFO_CH1_RD_DMA_CUR_HOSTMEM_WRITE_PTR", CMIC_CMC1_FIFO_CH1_RD_DMA_CUR_HOSTMEM_WRITE_PTRr }, \ 3857 { 0x00032338, "CMIC_CMC1_FIFO_CH2_RD_DMA_CUR_HOSTMEM_WRITE_PTR", CMIC_CMC1_FIFO_CH2_RD_DMA_CUR_HOSTMEM_WRITE_PTRr }, \ 3858 { 0x0003233c, "CMIC_CMC1_FIFO_CH3_RD_DMA_CUR_HOSTMEM_WRITE_PTR", CMIC_CMC1_FIFO_CH3_RD_DMA_CUR_HOSTMEM_WRITE_PTRr }, \ 3859 { 0x00032354, "CMIC_CMC1_FIFO_CH0_RD_DMA_HOSTMEM_THRESHOLD", CMIC_CMC1_FIFO_CH0_RD_DMA_HOSTMEM_THRESHOLDr }, \ 3860 { 0x00032358, "CMIC_CMC1_FIFO_CH1_RD_DMA_HOSTMEM_THRESHOLD", CMIC_CMC1_FIFO_CH1_RD_DMA_HOSTMEM_THRESHOLDr }, \ 3861 { 0x0003235c, "CMIC_CMC1_FIFO_CH2_RD_DMA_HOSTMEM_THRESHOLD", CMIC_CMC1_FIFO_CH2_RD_DMA_HOSTMEM_THRESHOLDr }, \ 3862 { 0x00032360, "CMIC_CMC1_FIFO_CH3_RD_DMA_HOSTMEM_THRESHOLD", CMIC_CMC1_FIFO_CH3_RD_DMA_HOSTMEM_THRESHOLDr }, \ 3863 { 0x00032364, "CMIC_CMC1_FIFO_CH0_RD_DMA_STAT", CMIC_CMC1_FIFO_CH0_RD_DMA_STATr }, \ 3864 { 0x00032368, "CMIC_CMC1_FIFO_CH1_RD_DMA_STAT", CMIC_CMC1_FIFO_CH1_RD_DMA_STATr }, \ 3865 { 0x0003236c, "CMIC_CMC1_FIFO_CH2_RD_DMA_STAT", CMIC_CMC1_FIFO_CH2_RD_DMA_STATr }, \ 3866 { 0x00032370, "CMIC_CMC1_FIFO_CH3_RD_DMA_STAT", CMIC_CMC1_FIFO_CH3_RD_DMA_STATr }, \ 3867 { 0x00032374, "CMIC_CMC1_FIFO_CH0_RD_DMA_STAT_CLR", CMIC_CMC1_FIFO_CH0_RD_DMA_STAT_CLRr }, \ 3868 { 0x00032378, "CMIC_CMC1_FIFO_CH1_RD_DMA_STAT_CLR", CMIC_CMC1_FIFO_CH1_RD_DMA_STAT_CLRr }, \ 3869 { 0x0003237c, "CMIC_CMC1_FIFO_CH2_RD_DMA_STAT_CLR", CMIC_CMC1_FIFO_CH2_RD_DMA_STAT_CLRr }, \ 3870 { 0x00032380, "CMIC_CMC1_FIFO_CH3_RD_DMA_STAT_CLR", CMIC_CMC1_FIFO_CH3_RD_DMA_STAT_CLRr }, \ 3871 { 0x00032384, "CMIC_CMC1_FIFO_CH0_RD_DMA_SBUS_CMD_CONFIG", CMIC_CMC1_FIFO_CH0_RD_DMA_SBUS_CMD_CONFIGr }, \ 3872 { 0x00032384, "CMIC_CMC1_FIFO_CH0_RD_DMA_OPCODE", CMIC_CMC1_FIFO_CH0_RD_DMA_OPCODEr }, \ 3873 { 0x00032388, "CMIC_CMC1_FIFO_CH1_RD_DMA_SBUS_CMD_CONFIG", CMIC_CMC1_FIFO_CH1_RD_DMA_SBUS_CMD_CONFIGr }, \ 3874 { 0x00032388, "CMIC_CMC1_FIFO_CH1_RD_DMA_OPCODE", CMIC_CMC1_FIFO_CH1_RD_DMA_OPCODEr }, \ 3875 { 0x0003238c, "CMIC_CMC1_FIFO_CH2_RD_DMA_SBUS_CMD_CONFIG", CMIC_CMC1_FIFO_CH2_RD_DMA_SBUS_CMD_CONFIGr }, \ 3876 { 0x0003238c, "CMIC_CMC1_FIFO_CH2_RD_DMA_OPCODE", CMIC_CMC1_FIFO_CH2_RD_DMA_OPCODEr }, \ 3877 { 0x00032390, "CMIC_CMC1_FIFO_CH3_RD_DMA_SBUS_CMD_CONFIG", CMIC_CMC1_FIFO_CH3_RD_DMA_SBUS_CMD_CONFIGr }, \ 3878 { 0x00032390, "CMIC_CMC1_FIFO_CH3_RD_DMA_OPCODE", CMIC_CMC1_FIFO_CH3_RD_DMA_OPCODEr }, \ 3879 { 0x00032394, "CMIC_CMC1_FIFO_RD_DMA_DEBUG", CMIC_CMC1_FIFO_RD_DMA_DEBUGr }, \ 3880 { 0x000323a0, "CMIC_CMC1_CCM_DMA_HOST0_MEM_START_ADDR", CMIC_CMC1_CCM_DMA_HOST0_MEM_START_ADDRr }, \ 3881 { 0x000323a4, "CMIC_CMC1_CCM_DMA_HOST1_MEM_START_ADDR", CMIC_CMC1_CCM_DMA_HOST1_MEM_START_ADDRr }, \ 3882 { 0x000323a8, "CMIC_CMC1_CCM_DMA_ENTRY_COUNT", CMIC_CMC1_CCM_DMA_ENTRY_COUNTr }, \ 3883 { 0x000323ac, "CMIC_CMC1_CCM_DMA_CFG", CMIC_CMC1_CCM_DMA_CFGr }, \ 3884 { 0x000323b0, "CMIC_CMC1_CCM_DMA_STAT", CMIC_CMC1_CCM_DMA_STATr }, \ 3885 { 0x000323b4, "CMIC_CMC1_CCM_DMA_CUR_HOST0_ADDR", CMIC_CMC1_CCM_DMA_CUR_HOST0_ADDRr }, \ 3886 { 0x000323b8, "CMIC_CMC1_CCM_DMA_CUR_HOST1_ADDR", CMIC_CMC1_CCM_DMA_CUR_HOST1_ADDRr }, \ 3887 { 0x000323bc, "CMIC_CMC1_CCM_DMA_ECCERR_ADDR", CMIC_CMC1_CCM_DMA_ECCERR_ADDRr }, \ 3888 { 0x000323c0, "CMIC_CMC1_CCM_DMA_STATUS_CLR", CMIC_CMC1_CCM_DMA_STATUS_CLRr }, \ 3889 { 0x000323c4, "CMIC_CMC1_CCM_DMA_ECCERR_CONTROL", CMIC_CMC1_CCM_DMA_ECCERR_CONTROLr }, \ 3890 { 0x00032400, "CMIC_CMC1_IRQ_STAT0", CMIC_CMC1_IRQ_STAT0r }, \ 3891 { 0x00032404, "CMIC_CMC1_IRQ_STAT1", CMIC_CMC1_IRQ_STAT1r }, \ 3892 { 0x00032408, "CMIC_CMC1_IRQ_STAT2", CMIC_CMC1_IRQ_STAT2r }, \ 3893 { 0x0003240c, "CMIC_CMC1_IRQ_STAT3", CMIC_CMC1_IRQ_STAT3r }, \ 3894 { 0x00032410, "CMIC_CMC1_IRQ_STAT4", CMIC_CMC1_IRQ_STAT4r }, \ 3895 { 0x00032414, "CMIC_CMC1_PCIE_IRQ_MASK0", CMIC_CMC1_PCIE_IRQ_MASK0r }, \ 3896 { 0x00032418, "CMIC_CMC1_PCIE_IRQ_MASK1", CMIC_CMC1_PCIE_IRQ_MASK1r }, \ 3897 { 0x0003241c, "CMIC_CMC1_PCIE_IRQ_MASK2", CMIC_CMC1_PCIE_IRQ_MASK2r }, \ 3898 { 0x00032420, "CMIC_CMC1_PCIE_IRQ_MASK3", CMIC_CMC1_PCIE_IRQ_MASK3r }, \ 3899 { 0x00032424, "CMIC_CMC1_PCIE_IRQ_MASK4", CMIC_CMC1_PCIE_IRQ_MASK4r }, \ 3900 { 0x00032428, "CMIC_CMC1_UC0_IRQ_MASK0", CMIC_CMC1_UC0_IRQ_MASK0r }, \ 3901 { 0x0003242c, "CMIC_CMC1_UC0_IRQ_MASK1", CMIC_CMC1_UC0_IRQ_MASK1r }, \ 3902 { 0x00032430, "CMIC_CMC1_UC0_IRQ_MASK2", CMIC_CMC1_UC0_IRQ_MASK2r }, \ 3903 { 0x00032434, "CMIC_CMC1_UC0_IRQ_MASK3", CMIC_CMC1_UC0_IRQ_MASK3r }, \ 3904 { 0x00032438, "CMIC_CMC1_UC0_IRQ_MASK4", CMIC_CMC1_UC0_IRQ_MASK4r }, \ 3905 { 0x0003243c, "CMIC_CMC1_UC1_IRQ_MASK0", CMIC_CMC1_UC1_IRQ_MASK0r }, \ 3906 { 0x00032440, "CMIC_CMC1_UC1_IRQ_MASK1", CMIC_CMC1_UC1_IRQ_MASK1r }, \ 3907 { 0x00032444, "CMIC_CMC1_UC1_IRQ_MASK2", CMIC_CMC1_UC1_IRQ_MASK2r }, \ 3908 { 0x00032448, "CMIC_CMC1_UC1_IRQ_MASK3", CMIC_CMC1_UC1_IRQ_MASK3r }, \ 3909 { 0x0003244c, "CMIC_CMC1_UC1_IRQ_MASK4", CMIC_CMC1_UC1_IRQ_MASK4r }, \ 3910 { 0x00032450, "CMIC_CMC1_RCPU_IRQ_MASK0", CMIC_CMC1_RCPU_IRQ_MASK0r }, \ 3911 { 0x00032454, "CMIC_CMC1_2BIT_ECC_ERROR_STATUS", CMIC_CMC1_2BIT_ECC_ERROR_STATUSr }, \ 3912 { 0x00032458, "CMIC_CMC1_2BIT_ECC_ERROR_STATUS_MASK", CMIC_CMC1_2BIT_ECC_ERROR_STATUS_MASKr }, \ 3913 { 0x00032470, "CMIC_CMC1_PCIE_MISCEL", CMIC_CMC1_PCIE_MISCELr }, \ 3914 { 0x00032474, "CMIC_CMC1_HOSTMEM_ADDR_REMAP_0", CMIC_CMC1_HOSTMEM_ADDR_REMAP_0r }, \ 3915 { 0x00032478, "CMIC_CMC1_HOSTMEM_ADDR_REMAP_1", CMIC_CMC1_HOSTMEM_ADDR_REMAP_1r }, \ 3916 { 0x0003247c, "CMIC_CMC1_HOSTMEM_ADDR_REMAP_2", CMIC_CMC1_HOSTMEM_ADDR_REMAP_2r }, \ 3917 { 0x00032480, "CMIC_CMC1_PKT_COUNT_CH0_RXPKT", CMIC_CMC1_PKT_COUNT_CH0_RXPKTr }, \ 3918 { 0x00032484, "CMIC_CMC1_PKT_COUNT_CH0_TXPKT", CMIC_CMC1_PKT_COUNT_CH0_TXPKTr }, \ 3919 { 0x00032488, "CMIC_CMC1_PKT_COUNT_CH1_RXPKT", CMIC_CMC1_PKT_COUNT_CH1_RXPKTr }, \ 3920 { 0x0003248c, "CMIC_CMC1_PKT_COUNT_CH1_TXPKT", CMIC_CMC1_PKT_COUNT_CH1_TXPKTr }, \ 3921 { 0x00032490, "CMIC_CMC1_PKT_COUNT_CH2_RXPKT", CMIC_CMC1_PKT_COUNT_CH2_RXPKTr }, \ 3922 { 0x00032494, "CMIC_CMC1_PKT_COUNT_CH2_TXPKT", CMIC_CMC1_PKT_COUNT_CH2_TXPKTr }, \ 3923 { 0x00032498, "CMIC_CMC1_PKT_COUNT_CH3_RXPKT", CMIC_CMC1_PKT_COUNT_CH3_RXPKTr }, \ 3924 { 0x0003249c, "CMIC_CMC1_PKT_COUNT_CH3_TXPKT", CMIC_CMC1_PKT_COUNT_CH3_TXPKTr }, \ 3925 { 0x000324a0, "CMIC_CMC1_PKT_COUNT_RXPKT", CMIC_CMC1_PKT_COUNT_RXPKTr }, \ 3926 { 0x000324a4, "CMIC_CMC1_PKT_COUNT_TXPKT", CMIC_CMC1_PKT_COUNT_TXPKTr }, \ 3927 { 0x000324a8, "CMIC_CMC1_SW_INTR_CONFIG", CMIC_CMC1_SW_INTR_CONFIGr }, \ 3928 { 0x000324ac, "CMIC_CMC1_HOSTMEM_ADDR_REMAP_3", CMIC_CMC1_HOSTMEM_ADDR_REMAP_3r }, \ 3929 { 0x000324b0, "CMIC_CMC1_IRQ_STAT5", CMIC_CMC1_IRQ_STAT5r }, \ 3930 { 0x000324b4, "CMIC_CMC1_IRQ_STAT6", CMIC_CMC1_IRQ_STAT6r }, \ 3931 { 0x000324b8, "CMIC_CMC1_PCIE_IRQ_MASK5", CMIC_CMC1_PCIE_IRQ_MASK5r }, \ 3932 { 0x000324bc, "CMIC_CMC1_PCIE_IRQ_MASK6", CMIC_CMC1_PCIE_IRQ_MASK6r }, \ 3933 { 0x000324c0, "CMIC_CMC1_UC0_IRQ_MASK5", CMIC_CMC1_UC0_IRQ_MASK5r }, \ 3934 { 0x000324c4, "CMIC_CMC1_UC0_IRQ_MASK6", CMIC_CMC1_UC0_IRQ_MASK6r }, \ 3935 { 0x000324c8, "CMIC_CMC1_UC1_IRQ_MASK5", CMIC_CMC1_UC1_IRQ_MASK5r }, \ 3936 { 0x000324cc, "CMIC_CMC1_UC1_IRQ_MASK6", CMIC_CMC1_UC1_IRQ_MASK6r }, \ 3937 { 0x000324d0, "CMIC_CMC1_AXIIC_DMA_ECC_INTR_ENABLE", CMIC_CMC1_AXIIC_DMA_ECC_INTR_ENABLEr }, \ 3938 { 0x000324d4, "CMIC_CMC1_AXIIC_DMA_ECC_INTR", CMIC_CMC1_AXIIC_DMA_ECC_INTRr }, \ 3939 { 0x000324d8, "CMIC_CMC1_AXIIC_DMA_ECC_INTR_CLR", CMIC_CMC1_AXIIC_DMA_ECC_INTR_CLRr }, \ 3940 { 0x00032600, "CMIC_CMC1_SBUSDMA_CH0_CONTROL", CMIC_CMC1_SBUSDMA_CH0_CONTROLr }, \ 3941 { 0x00032604, "CMIC_CMC1_SBUSDMA_CH0_REQUEST", CMIC_CMC1_SBUSDMA_CH0_REQUESTr }, \ 3942 { 0x00032608, "CMIC_CMC1_SBUSDMA_CH0_COUNT", CMIC_CMC1_SBUSDMA_CH0_COUNTr }, \ 3943 { 0x0003260c, "CMIC_CMC1_SBUSDMA_CH0_OPCODE", CMIC_CMC1_SBUSDMA_CH0_OPCODEr }, \ 3944 { 0x00032610, "CMIC_CMC1_SBUSDMA_CH0_SBUS_START_ADDRESS", CMIC_CMC1_SBUSDMA_CH0_SBUS_START_ADDRESSr }, \ 3945 { 0x00032614, "CMIC_CMC1_SBUSDMA_CH0_HOSTMEM_START_ADDRESS", CMIC_CMC1_SBUSDMA_CH0_HOSTMEM_START_ADDRESSr }, \ 3946 { 0x00032618, "CMIC_CMC1_SBUSDMA_CH0_DESC_START_ADDRESS", CMIC_CMC1_SBUSDMA_CH0_DESC_START_ADDRESSr }, \ 3947 { 0x0003261c, "CMIC_CMC1_SBUSDMA_CH0_STATUS", CMIC_CMC1_SBUSDMA_CH0_STATUSr }, \ 3948 { 0x00032620, "CMIC_CMC1_SBUSDMA_CH0_CUR_HOSTMEM_ADDRESS", CMIC_CMC1_SBUSDMA_CH0_CUR_HOSTMEM_ADDRESSr }, \ 3949 { 0x00032624, "CMIC_CMC1_SBUSDMA_CH0_CUR_SBUS_ADDRESS", CMIC_CMC1_SBUSDMA_CH0_CUR_SBUS_ADDRESSr }, \ 3950 { 0x00032628, "CMIC_CMC1_SBUSDMA_CH0_CUR_DESC_ADDRESS", CMIC_CMC1_SBUSDMA_CH0_CUR_DESC_ADDRESSr }, \ 3951 { 0x0003262c, "CMIC_CMC1_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_REQUEST", CMIC_CMC1_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_REQUESTr }, \ 3952 { 0x00032630, "CMIC_CMC1_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_COUNT", CMIC_CMC1_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_COUNTr }, \ 3953 { 0x00032634, "CMIC_CMC1_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_SBUS_START_ADDRESS", CMIC_CMC1_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_SBUS_START_ADDRESSr }, \ 3954 { 0x00032638, "CMIC_CMC1_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS", CMIC_CMC1_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESSr }, \ 3955 { 0x0003263c, "CMIC_CMC1_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_OPCODE", CMIC_CMC1_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_OPCODEr }, \ 3956 { 0x00032640, "CMIC_CMC1_SBUSDMA_CH0_SBUSDMA_DEBUG", CMIC_CMC1_SBUSDMA_CH0_SBUSDMA_DEBUGr }, \ 3957 { 0x00032644, "CMIC_CMC1_SBUSDMA_CH0_SBUSDMA_DEBUG_CLR", CMIC_CMC1_SBUSDMA_CH0_SBUSDMA_DEBUG_CLRr }, \ 3958 { 0x00032648, "CMIC_CMC1_SBUSDMA_CH0_SBUSDMA_ECCERR_ADDRESS", CMIC_CMC1_SBUSDMA_CH0_SBUSDMA_ECCERR_ADDRESSr }, \ 3959 { 0x0003264c, "CMIC_CMC1_SBUSDMA_CH0_SBUSDMA_ECCERR_CONTROL", CMIC_CMC1_SBUSDMA_CH0_SBUSDMA_ECCERR_CONTROLr }, \ 3960 { 0x00032650, "CMIC_CMC1_SBUSDMA_CH1_CONTROL", CMIC_CMC1_SBUSDMA_CH1_CONTROLr }, \ 3961 { 0x00032654, "CMIC_CMC1_SBUSDMA_CH1_REQUEST", CMIC_CMC1_SBUSDMA_CH1_REQUESTr }, \ 3962 { 0x00032658, "CMIC_CMC1_SBUSDMA_CH1_COUNT", CMIC_CMC1_SBUSDMA_CH1_COUNTr }, \ 3963 { 0x0003265c, "CMIC_CMC1_SBUSDMA_CH1_OPCODE", CMIC_CMC1_SBUSDMA_CH1_OPCODEr }, \ 3964 { 0x00032660, "CMIC_CMC1_SBUSDMA_CH1_SBUS_START_ADDRESS", CMIC_CMC1_SBUSDMA_CH1_SBUS_START_ADDRESSr }, \ 3965 { 0x00032664, "CMIC_CMC1_SBUSDMA_CH1_HOSTMEM_START_ADDRESS", CMIC_CMC1_SBUSDMA_CH1_HOSTMEM_START_ADDRESSr }, \ 3966 { 0x00032668, "CMIC_CMC1_SBUSDMA_CH1_DESC_START_ADDRESS", CMIC_CMC1_SBUSDMA_CH1_DESC_START_ADDRESSr }, \ 3967 { 0x0003266c, "CMIC_CMC1_SBUSDMA_CH1_STATUS", CMIC_CMC1_SBUSDMA_CH1_STATUSr }, \ 3968 { 0x00032670, "CMIC_CMC1_SBUSDMA_CH1_CUR_HOSTMEM_ADDRESS", CMIC_CMC1_SBUSDMA_CH1_CUR_HOSTMEM_ADDRESSr }, \ 3969 { 0x00032674, "CMIC_CMC1_SBUSDMA_CH1_CUR_SBUS_ADDRESS", CMIC_CMC1_SBUSDMA_CH1_CUR_SBUS_ADDRESSr }, \ 3970 { 0x00032678, "CMIC_CMC1_SBUSDMA_CH1_CUR_DESC_ADDRESS", CMIC_CMC1_SBUSDMA_CH1_CUR_DESC_ADDRESSr }, \ 3971 { 0x0003267c, "CMIC_CMC1_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_REQUEST", CMIC_CMC1_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_REQUESTr }, \ 3972 { 0x00032680, "CMIC_CMC1_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_COUNT", CMIC_CMC1_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_COUNTr }, \ 3973 { 0x00032684, "CMIC_CMC1_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_SBUS_START_ADDRESS", CMIC_CMC1_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_SBUS_START_ADDRESSr }, \ 3974 { 0x00032688, "CMIC_CMC1_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS", CMIC_CMC1_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESSr }, \ 3975 { 0x0003268c, "CMIC_CMC1_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_OPCODE", CMIC_CMC1_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_OPCODEr }, \ 3976 { 0x00032690, "CMIC_CMC1_SBUSDMA_CH1_SBUSDMA_DEBUG", CMIC_CMC1_SBUSDMA_CH1_SBUSDMA_DEBUGr }, \ 3977 { 0x00032694, "CMIC_CMC1_SBUSDMA_CH1_SBUSDMA_DEBUG_CLR", CMIC_CMC1_SBUSDMA_CH1_SBUSDMA_DEBUG_CLRr }, \ 3978 { 0x00032698, "CMIC_CMC1_SBUSDMA_CH1_SBUSDMA_ECCERR_ADDRESS", CMIC_CMC1_SBUSDMA_CH1_SBUSDMA_ECCERR_ADDRESSr }, \ 3979 { 0x0003269c, "CMIC_CMC1_SBUSDMA_CH1_SBUSDMA_ECCERR_CONTROL", CMIC_CMC1_SBUSDMA_CH1_SBUSDMA_ECCERR_CONTROLr }, \ 3980 { 0x000326a0, "CMIC_CMC1_SBUSDMA_CH2_CONTROL", CMIC_CMC1_SBUSDMA_CH2_CONTROLr }, \ 3981 { 0x000326a4, "CMIC_CMC1_SBUSDMA_CH2_REQUEST", CMIC_CMC1_SBUSDMA_CH2_REQUESTr }, \ 3982 { 0x000326a8, "CMIC_CMC1_SBUSDMA_CH2_COUNT", CMIC_CMC1_SBUSDMA_CH2_COUNTr }, \ 3983 { 0x000326ac, "CMIC_CMC1_SBUSDMA_CH2_OPCODE", CMIC_CMC1_SBUSDMA_CH2_OPCODEr }, \ 3984 { 0x000326b0, "CMIC_CMC1_SBUSDMA_CH2_SBUS_START_ADDRESS", CMIC_CMC1_SBUSDMA_CH2_SBUS_START_ADDRESSr }, \ 3985 { 0x000326b4, "CMIC_CMC1_SBUSDMA_CH2_HOSTMEM_START_ADDRESS", CMIC_CMC1_SBUSDMA_CH2_HOSTMEM_START_ADDRESSr }, \ 3986 { 0x000326b8, "CMIC_CMC1_SBUSDMA_CH2_DESC_START_ADDRESS", CMIC_CMC1_SBUSDMA_CH2_DESC_START_ADDRESSr }, \ 3987 { 0x000326bc, "CMIC_CMC1_SBUSDMA_CH2_STATUS", CMIC_CMC1_SBUSDMA_CH2_STATUSr }, \ 3988 { 0x000326c0, "CMIC_CMC1_SBUSDMA_CH2_CUR_HOSTMEM_ADDRESS", CMIC_CMC1_SBUSDMA_CH2_CUR_HOSTMEM_ADDRESSr }, \ 3989 { 0x000326c4, "CMIC_CMC1_SBUSDMA_CH2_CUR_SBUS_ADDRESS", CMIC_CMC1_SBUSDMA_CH2_CUR_SBUS_ADDRESSr }, \ 3990 { 0x000326c8, "CMIC_CMC1_SBUSDMA_CH2_CUR_DESC_ADDRESS", CMIC_CMC1_SBUSDMA_CH2_CUR_DESC_ADDRESSr }, \ 3991 { 0x000326cc, "CMIC_CMC1_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_REQUEST", CMIC_CMC1_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_REQUESTr }, \ 3992 { 0x000326d0, "CMIC_CMC1_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_COUNT", CMIC_CMC1_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_COUNTr }, \ 3993 { 0x000326d4, "CMIC_CMC1_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_SBUS_START_ADDRESS", CMIC_CMC1_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_SBUS_START_ADDRESSr }, \ 3994 { 0x000326d8, "CMIC_CMC1_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS", CMIC_CMC1_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESSr }, \ 3995 { 0x000326dc, "CMIC_CMC1_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_OPCODE", CMIC_CMC1_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_OPCODEr }, \ 3996 { 0x000326e0, "CMIC_CMC1_SBUSDMA_CH2_SBUSDMA_DEBUG", CMIC_CMC1_SBUSDMA_CH2_SBUSDMA_DEBUGr }, \ 3997 { 0x000326e4, "CMIC_CMC1_SBUSDMA_CH2_SBUSDMA_DEBUG_CLR", CMIC_CMC1_SBUSDMA_CH2_SBUSDMA_DEBUG_CLRr }, \ 3998 { 0x000326e8, "CMIC_CMC1_SBUSDMA_CH2_SBUSDMA_ECCERR_ADDRESS", CMIC_CMC1_SBUSDMA_CH2_SBUSDMA_ECCERR_ADDRESSr }, \ 3999 { 0x000326ec, "CMIC_CMC1_SBUSDMA_CH2_SBUSDMA_ECCERR_CONTROL", CMIC_CMC1_SBUSDMA_CH2_SBUSDMA_ECCERR_CONTROLr }, \ 4000 { 0x000326f0, "CMIC_CMC1_SBUSDMA_CH0_TIMER", CMIC_CMC1_SBUSDMA_CH0_TIMERr }, \ 4001 { 0x000326f4, "CMIC_CMC1_SBUSDMA_CH1_TIMER", CMIC_CMC1_SBUSDMA_CH1_TIMERr }, \ 4002 { 0x000326f8, "CMIC_CMC1_SBUSDMA_CH2_TIMER", CMIC_CMC1_SBUSDMA_CH2_TIMERr }, \ 4003 { 0x000326fc, "CMIC_CMC1_SBUSDMA_CH0_ITER_COUNT", CMIC_CMC1_SBUSDMA_CH0_ITER_COUNTr }, \ 4004 { 0x00032700, "CMIC_CMC1_SBUSDMA_CH1_ITER_COUNT", CMIC_CMC1_SBUSDMA_CH1_ITER_COUNTr }, \ 4005 { 0x00032704, "CMIC_CMC1_SBUSDMA_CH2_ITER_COUNT", CMIC_CMC1_SBUSDMA_CH2_ITER_COUNTr }, \ 4006 { 0x00032800, "CMIC_CMC1_SBUSDMA_CH0_TM_CONTROL_0", CMIC_CMC1_SBUSDMA_CH0_TM_CONTROL_0r }, \ 4007 { 0x00032804, "CMIC_CMC1_SBUSDMA_CH0_TM_CONTROL_1", CMIC_CMC1_SBUSDMA_CH0_TM_CONTROL_1r }, \ 4008 { 0x0003280c, "CMIC_CMC1_SBUSDMA_CH0_TM_CONTROL_2", CMIC_CMC1_SBUSDMA_CH0_TM_CONTROL_2r }, \ 4009 { 0x00032810, "CMIC_CMC1_SBUSDMA_CH1_TM_CONTROL_0", CMIC_CMC1_SBUSDMA_CH1_TM_CONTROL_0r }, \ 4010 { 0x00032814, "CMIC_CMC1_SBUSDMA_CH1_TM_CONTROL_1", CMIC_CMC1_SBUSDMA_CH1_TM_CONTROL_1r }, \ 4011 { 0x00032818, "CMIC_CMC1_SBUSDMA_CH1_TM_CONTROL_2", CMIC_CMC1_SBUSDMA_CH1_TM_CONTROL_2r }, \ 4012 { 0x0003281c, "CMIC_CMC1_SBUSDMA_CH2_TM_CONTROL_0", CMIC_CMC1_SBUSDMA_CH2_TM_CONTROL_0r }, \ 4013 { 0x00032820, "CMIC_CMC1_SBUSDMA_CH2_TM_CONTROL_1", CMIC_CMC1_SBUSDMA_CH2_TM_CONTROL_1r }, \ 4014 { 0x00032824, "CMIC_CMC1_SBUSDMA_CH2_TM_CONTROL_2", CMIC_CMC1_SBUSDMA_CH2_TM_CONTROL_2r }, \ 4015 { 0x00032828, "CMIC_CMC1_FIFORDDMA_CH0_TM_CONTROL_0", CMIC_CMC1_FIFORDDMA_CH0_TM_CONTROL_0r }, \ 4016 { 0x0003282c, "CMIC_CMC1_FIFORDDMA_CH0_TM_CONTROL_1", CMIC_CMC1_FIFORDDMA_CH0_TM_CONTROL_1r }, \ 4017 { 0x00032830, "CMIC_CMC1_FIFORDDMA_CH1_TM_CONTROL_0", CMIC_CMC1_FIFORDDMA_CH1_TM_CONTROL_0r }, \ 4018 { 0x00032834, "CMIC_CMC1_FIFORDDMA_CH1_TM_CONTROL_1", CMIC_CMC1_FIFORDDMA_CH1_TM_CONTROL_1r }, \ 4019 { 0x00032838, "CMIC_CMC1_FIFORDDMA_CH2_TM_CONTROL_0", CMIC_CMC1_FIFORDDMA_CH2_TM_CONTROL_0r }, \ 4020 { 0x0003283c, "CMIC_CMC1_FIFORDDMA_CH2_TM_CONTROL_1", CMIC_CMC1_FIFORDDMA_CH2_TM_CONTROL_1r }, \ 4021 { 0x00032840, "CMIC_CMC1_FIFORDDMA_CH3_TM_CONTROL_0", CMIC_CMC1_FIFORDDMA_CH3_TM_CONTROL_0r }, \ 4022 { 0x00032844, "CMIC_CMC1_FIFORDDMA_CH3_TM_CONTROL_1", CMIC_CMC1_FIFORDDMA_CH3_TM_CONTROL_1r }, \ 4023 { 0x00032848, "CMIC_CMC1_CCMDMA_TM_CONTROL_0", CMIC_CMC1_CCMDMA_TM_CONTROL_0r }, \ 4024 { 0x0003284c, "CMIC_CMC1_CCMDMA_TM_CONTROL_1", CMIC_CMC1_CCMDMA_TM_CONTROL_1r }, \ 4025 { 0x00032850, "CMIC_CMC1_AXIIC_TM_CONTROL_0", CMIC_CMC1_AXIIC_TM_CONTROL_0r }, \ 4026 { 0x00032854, "CMIC_CMC1_AXIIC_TM_CONTROL_1", CMIC_CMC1_AXIIC_TM_CONTROL_1r }, \ 4027 { 0x00032858, "CMIC_CMC1_AXIIC_TM_CONTROL_2", CMIC_CMC1_AXIIC_TM_CONTROL_2r }, \ 4028 { 0x00033000, "CMIC_CMC2_SCHAN_CTRL", CMIC_CMC2_SCHAN_CTRLr }, \ 4029 { 0x00033004, "CMIC_CMC2_SCHAN_ACK_DATA_BEAT_COUNT", CMIC_CMC2_SCHAN_ACK_DATA_BEAT_COUNTr }, \ 4030 { 0x00033008, "CMIC_CMC2_SCHAN_ERR", CMIC_CMC2_SCHAN_ERRr }, \ 4031 { 0x0003300c, "CMIC_CMC2_SCHAN_MESSAGE0", CMIC_CMC2_SCHAN_MESSAGE0r }, \ 4032 { 0x0003300c, "CMIC_CMC2_SCHAN_MESSAGE", CMIC_CMC2_SCHAN_MESSAGEr }, \ 4033 { 0x00033010, "CMIC_CMC2_SCHAN_MESSAGE1", CMIC_CMC2_SCHAN_MESSAGE1r }, \ 4034 { 0x00033014, "CMIC_CMC2_SCHAN_MESSAGE2", CMIC_CMC2_SCHAN_MESSAGE2r }, \ 4035 { 0x00033018, "CMIC_CMC2_SCHAN_MESSAGE3", CMIC_CMC2_SCHAN_MESSAGE3r }, \ 4036 { 0x0003301c, "CMIC_CMC2_SCHAN_MESSAGE4", CMIC_CMC2_SCHAN_MESSAGE4r }, \ 4037 { 0x00033020, "CMIC_CMC2_SCHAN_MESSAGE5", CMIC_CMC2_SCHAN_MESSAGE5r }, \ 4038 { 0x00033024, "CMIC_CMC2_SCHAN_MESSAGE6", CMIC_CMC2_SCHAN_MESSAGE6r }, \ 4039 { 0x00033028, "CMIC_CMC2_SCHAN_MESSAGE7", CMIC_CMC2_SCHAN_MESSAGE7r }, \ 4040 { 0x0003302c, "CMIC_CMC2_SCHAN_MESSAGE8", CMIC_CMC2_SCHAN_MESSAGE8r }, \ 4041 { 0x00033030, "CMIC_CMC2_SCHAN_MESSAGE9", CMIC_CMC2_SCHAN_MESSAGE9r }, \ 4042 { 0x00033034, "CMIC_CMC2_SCHAN_MESSAGE10", CMIC_CMC2_SCHAN_MESSAGE10r }, \ 4043 { 0x00033038, "CMIC_CMC2_SCHAN_MESSAGE11", CMIC_CMC2_SCHAN_MESSAGE11r }, \ 4044 { 0x0003303c, "CMIC_CMC2_SCHAN_MESSAGE12", CMIC_CMC2_SCHAN_MESSAGE12r }, \ 4045 { 0x00033040, "CMIC_CMC2_SCHAN_MESSAGE13", CMIC_CMC2_SCHAN_MESSAGE13r }, \ 4046 { 0x00033044, "CMIC_CMC2_SCHAN_MESSAGE14", CMIC_CMC2_SCHAN_MESSAGE14r }, \ 4047 { 0x00033048, "CMIC_CMC2_SCHAN_MESSAGE15", CMIC_CMC2_SCHAN_MESSAGE15r }, \ 4048 { 0x0003304c, "CMIC_CMC2_SCHAN_MESSAGE16", CMIC_CMC2_SCHAN_MESSAGE16r }, \ 4049 { 0x00033050, "CMIC_CMC2_SCHAN_MESSAGE17", CMIC_CMC2_SCHAN_MESSAGE17r }, \ 4050 { 0x00033054, "CMIC_CMC2_SCHAN_MESSAGE18", CMIC_CMC2_SCHAN_MESSAGE18r }, \ 4051 { 0x00033058, "CMIC_CMC2_SCHAN_MESSAGE19", CMIC_CMC2_SCHAN_MESSAGE19r }, \ 4052 { 0x0003305c, "CMIC_CMC2_SCHAN_MESSAGE20", CMIC_CMC2_SCHAN_MESSAGE20r }, \ 4053 { 0x00033060, "CMIC_CMC2_SCHAN_MESSAGE21", CMIC_CMC2_SCHAN_MESSAGE21r }, \ 4054 { 0x00033064, "CMIC_CMC2_FSCHAN_ENABLE_PROGRAMMABLE_OPCODE", CMIC_CMC2_FSCHAN_ENABLE_PROGRAMMABLE_OPCODEr }, \ 4055 { 0x00033068, "CMIC_CMC2_FSCHAN_STATUS", CMIC_CMC2_FSCHAN_STATUSr }, \ 4056 { 0x0003306c, "CMIC_CMC2_FSCHAN_OPCODE", CMIC_CMC2_FSCHAN_OPCODEr }, \ 4057 { 0x00033070, "CMIC_CMC2_FSCHAN_ADDRESS", CMIC_CMC2_FSCHAN_ADDRESSr }, \ 4058 { 0x00033074, "CMIC_CMC2_FSCHAN_DATA32", CMIC_CMC2_FSCHAN_DATA32r }, \ 4059 { 0x00033078, "CMIC_CMC2_FSCHAN_DATA64_LO", CMIC_CMC2_FSCHAN_DATA64_LOr }, \ 4060 { 0x0003307c, "CMIC_CMC2_FSCHAN_DATA64_HI", CMIC_CMC2_FSCHAN_DATA64_HIr }, \ 4061 { 0x00033080, "CMIC_CMC2_MIIM_PARAM", CMIC_CMC2_MIIM_PARAMr }, \ 4062 { 0x00033084, "CMIC_CMC2_MIIM_READ_DATA", CMIC_CMC2_MIIM_READ_DATAr }, \ 4063 { 0x00033088, "CMIC_CMC2_MIIM_ADDRESS", CMIC_CMC2_MIIM_ADDRESSr }, \ 4064 { 0x0003308c, "CMIC_CMC2_MIIM_CTRL", CMIC_CMC2_MIIM_CTRLr }, \ 4065 { 0x00033090, "CMIC_CMC2_MIIM_STAT", CMIC_CMC2_MIIM_STATr }, \ 4066 { 0x00033100, "CMIC_CMC2_TM_CONTROL_0", CMIC_CMC2_TM_CONTROL_0r }, \ 4067 { 0x00033104, "CMIC_CMC2_TM_CONTROL_1", CMIC_CMC2_TM_CONTROL_1r }, \ 4068 { 0x00033108, "CMIC_CMC2_CONFIG", CMIC_CMC2_CONFIGr }, \ 4069 { 0x0003310c, "CMIC_CMC2_STAT", CMIC_CMC2_STATr }, \ 4070 { 0x00033110, "CMIC_CMC2_CH0_RXBUF_THRESHOLD_CONFIG", CMIC_CMC2_CH0_RXBUF_THRESHOLD_CONFIGr }, \ 4071 { 0x00033114, "CMIC_CMC2_CH1_RXBUF_THRESHOLD_CONFIG", CMIC_CMC2_CH1_RXBUF_THRESHOLD_CONFIGr }, \ 4072 { 0x00033118, "CMIC_CMC2_CH2_RXBUF_THRESHOLD_CONFIG", CMIC_CMC2_CH2_RXBUF_THRESHOLD_CONFIGr }, \ 4073 { 0x0003311c, "CMIC_CMC2_CH3_RXBUF_THRESHOLD_CONFIG", CMIC_CMC2_CH3_RXBUF_THRESHOLD_CONFIGr }, \ 4074 { 0x00033120, "CMIC_CMC2_DMA_CH0_DESC_HALT_ADDR", CMIC_CMC2_DMA_CH0_DESC_HALT_ADDRr }, \ 4075 { 0x00033124, "CMIC_CMC2_DMA_CH1_DESC_HALT_ADDR", CMIC_CMC2_DMA_CH1_DESC_HALT_ADDRr }, \ 4076 { 0x00033128, "CMIC_CMC2_DMA_CH2_DESC_HALT_ADDR", CMIC_CMC2_DMA_CH2_DESC_HALT_ADDRr }, \ 4077 { 0x0003312c, "CMIC_CMC2_DMA_CH3_DESC_HALT_ADDR", CMIC_CMC2_DMA_CH3_DESC_HALT_ADDRr }, \ 4078 { 0x00033130, "CMIC_CMC2_DMA_STAT_HI", CMIC_CMC2_DMA_STAT_HIr }, \ 4079 { 0x00033140, "CMIC_CMC2_CH0_DMA_CTRL", CMIC_CMC2_CH0_DMA_CTRLr }, \ 4080 { 0x00033144, "CMIC_CMC2_CH1_DMA_CTRL", CMIC_CMC2_CH1_DMA_CTRLr }, \ 4081 { 0x00033148, "CMIC_CMC2_CH2_DMA_CTRL", CMIC_CMC2_CH2_DMA_CTRLr }, \ 4082 { 0x0003314c, "CMIC_CMC2_CH3_DMA_CTRL", CMIC_CMC2_CH3_DMA_CTRLr }, \ 4083 { 0x00033150, "CMIC_CMC2_DMA_STAT", CMIC_CMC2_DMA_STATr }, \ 4084 { 0x00033158, "CMIC_CMC2_DMA_DESC0", CMIC_CMC2_DMA_DESC0r }, \ 4085 { 0x0003315c, "CMIC_CMC2_DMA_DESC1", CMIC_CMC2_DMA_DESC1r }, \ 4086 { 0x00033160, "CMIC_CMC2_DMA_DESC2", CMIC_CMC2_DMA_DESC2r }, \ 4087 { 0x00033164, "CMIC_CMC2_DMA_DESC3", CMIC_CMC2_DMA_DESC3r }, \ 4088 { 0x00033168, "CMIC_CMC2_CH0_COS_CTRL_RX_0", CMIC_CMC2_CH0_COS_CTRL_RX_0r }, \ 4089 { 0x0003316c, "CMIC_CMC2_CH0_COS_CTRL_RX_1", CMIC_CMC2_CH0_COS_CTRL_RX_1r }, \ 4090 { 0x00033170, "CMIC_CMC2_CH1_COS_CTRL_RX_0", CMIC_CMC2_CH1_COS_CTRL_RX_0r }, \ 4091 { 0x00033174, "CMIC_CMC2_CH1_COS_CTRL_RX_1", CMIC_CMC2_CH1_COS_CTRL_RX_1r }, \ 4092 { 0x00033178, "CMIC_CMC2_CH2_COS_CTRL_RX_0", CMIC_CMC2_CH2_COS_CTRL_RX_0r }, \ 4093 { 0x0003317c, "CMIC_CMC2_CH2_COS_CTRL_RX_1", CMIC_CMC2_CH2_COS_CTRL_RX_1r }, \ 4094 { 0x00033180, "CMIC_CMC2_CH3_COS_CTRL_RX_0", CMIC_CMC2_CH3_COS_CTRL_RX_0r }, \ 4095 { 0x00033184, "CMIC_CMC2_CH3_COS_CTRL_RX_1", CMIC_CMC2_CH3_COS_CTRL_RX_1r }, \ 4096 { 0x00033188, "CMIC_CMC2_DMA_CH0_INTR_COAL", CMIC_CMC2_DMA_CH0_INTR_COALr }, \ 4097 { 0x0003318c, "CMIC_CMC2_DMA_CH1_INTR_COAL", CMIC_CMC2_DMA_CH1_INTR_COALr }, \ 4098 { 0x00033190, "CMIC_CMC2_DMA_CH2_INTR_COAL", CMIC_CMC2_DMA_CH2_INTR_COALr }, \ 4099 { 0x00033194, "CMIC_CMC2_DMA_CH3_INTR_COAL", CMIC_CMC2_DMA_CH3_INTR_COALr }, \ 4100 { 0x00033198, "CMIC_CMC2_RXBUF_THRESHOLD_CONFIG", CMIC_CMC2_RXBUF_THRESHOLD_CONFIGr }, \ 4101 { 0x0003319c, "CMIC_CMC2_PROGRAMMABLE_COS_MASK0", CMIC_CMC2_PROGRAMMABLE_COS_MASK0r }, \ 4102 { 0x000331a0, "CMIC_CMC2_PROGRAMMABLE_COS_MASK1", CMIC_CMC2_PROGRAMMABLE_COS_MASK1r }, \ 4103 { 0x000331a4, "CMIC_CMC2_DMA_STAT_CLR", CMIC_CMC2_DMA_STAT_CLRr }, \ 4104 { 0x000331a8, "CMIC_CMC2_CH0_DMA_CURR_DESC", CMIC_CMC2_CH0_DMA_CURR_DESCr }, \ 4105 { 0x000331ac, "CMIC_CMC2_CH1_DMA_CURR_DESC", CMIC_CMC2_CH1_DMA_CURR_DESCr }, \ 4106 { 0x000331b0, "CMIC_CMC2_CH2_DMA_CURR_DESC", CMIC_CMC2_CH2_DMA_CURR_DESCr }, \ 4107 { 0x000331b4, "CMIC_CMC2_CH3_DMA_CURR_DESC", CMIC_CMC2_CH3_DMA_CURR_DESCr }, \ 4108 { 0x000331c0, "CMIC_CMC2_STAT_DMA_ADDR", CMIC_CMC2_STAT_DMA_ADDRr }, \ 4109 { 0x000331c4, "CMIC_CMC2_STAT_DMA_CFG", CMIC_CMC2_STAT_DMA_CFGr }, \ 4110 { 0x000331c8, "CMIC_CMC2_STAT_DMA_PORTS_0", CMIC_CMC2_STAT_DMA_PORTS_0r }, \ 4111 { 0x000331cc, "CMIC_CMC2_STAT_DMA_PORTS_1", CMIC_CMC2_STAT_DMA_PORTS_1r }, \ 4112 { 0x000331d0, "CMIC_CMC2_STAT_DMA_PORTS_2", CMIC_CMC2_STAT_DMA_PORTS_2r }, \ 4113 { 0x000331d4, "CMIC_CMC2_STAT_DMA_CURRENT", CMIC_CMC2_STAT_DMA_CURRENTr }, \ 4114 { 0x000331d8, "CMIC_CMC2_STAT_DMA_SBUS_START_ADDRESS", CMIC_CMC2_STAT_DMA_SBUS_START_ADDRESSr }, \ 4115 { 0x000331dc, "CMIC_CMC2_STAT_DMA_STAT", CMIC_CMC2_STAT_DMA_STATr }, \ 4116 { 0x00033200, "CMIC_CMC2_SLAM_DMA_PCIMEM_START_ADDR", CMIC_CMC2_SLAM_DMA_PCIMEM_START_ADDRr }, \ 4117 { 0x00033204, "CMIC_CMC2_SLAM_DMA_SBUS_START_ADDR", CMIC_CMC2_SLAM_DMA_SBUS_START_ADDRr }, \ 4118 { 0x00033208, "CMIC_CMC2_SLAM_DMA_ENTRY_COUNT", CMIC_CMC2_SLAM_DMA_ENTRY_COUNTr }, \ 4119 { 0x0003320c, "CMIC_CMC2_SLAM_DMA_CFG", CMIC_CMC2_SLAM_DMA_CFGr }, \ 4120 { 0x00033210, "CMIC_CMC2_SLAM_DMA_STAT", CMIC_CMC2_SLAM_DMA_STATr }, \ 4121 { 0x00033214, "CMIC_CMC2_SLAM_DMA_CUR_ENTRY_SBUS_ADDR", CMIC_CMC2_SLAM_DMA_CUR_ENTRY_SBUS_ADDRr }, \ 4122 { 0x00033218, "CMIC_CMC2_SLAM_DMA_SBUS_CMD_CONFIG", CMIC_CMC2_SLAM_DMA_SBUS_CMD_CONFIGr }, \ 4123 { 0x00033240, "CMIC_CMC2_TABLE_DMA_PCIMEM_START_ADDR", CMIC_CMC2_TABLE_DMA_PCIMEM_START_ADDRr }, \ 4124 { 0x00033244, "CMIC_CMC2_TABLE_DMA_SBUS_START_ADDR", CMIC_CMC2_TABLE_DMA_SBUS_START_ADDRr }, \ 4125 { 0x00033248, "CMIC_CMC2_TABLE_DMA_ENTRY_COUNT", CMIC_CMC2_TABLE_DMA_ENTRY_COUNTr }, \ 4126 { 0x0003324c, "CMIC_CMC2_TABLE_DMA_CFG", CMIC_CMC2_TABLE_DMA_CFGr }, \ 4127 { 0x00033250, "CMIC_CMC2_TABLE_DMA_STAT", CMIC_CMC2_TABLE_DMA_STATr }, \ 4128 { 0x00033254, "CMIC_CMC2_TABLE_DMA_CUR_ENTRY_SBUS_ADDR", CMIC_CMC2_TABLE_DMA_CUR_ENTRY_SBUS_ADDRr }, \ 4129 { 0x00033258, "CMIC_CMC2_TABLE_DMA_SBUS_CMD_CONFIG", CMIC_CMC2_TABLE_DMA_SBUS_CMD_CONFIGr }, \ 4130 { 0x000332c0, "CMIC_CMC2_FIFO_CH0_RD_DMA_CFG", CMIC_CMC2_FIFO_CH0_RD_DMA_CFGr }, \ 4131 { 0x000332c4, "CMIC_CMC2_FIFO_CH1_RD_DMA_CFG", CMIC_CMC2_FIFO_CH1_RD_DMA_CFGr }, \ 4132 { 0x000332c8, "CMIC_CMC2_FIFO_CH2_RD_DMA_CFG", CMIC_CMC2_FIFO_CH2_RD_DMA_CFGr }, \ 4133 { 0x000332cc, "CMIC_CMC2_FIFO_CH3_RD_DMA_CFG", CMIC_CMC2_FIFO_CH3_RD_DMA_CFGr }, \ 4134 { 0x000332d0, "CMIC_CMC2_FIFO_CH0_RD_DMA_SBUS_START_ADDRESS", CMIC_CMC2_FIFO_CH0_RD_DMA_SBUS_START_ADDRESSr }, \ 4135 { 0x000332d4, "CMIC_CMC2_FIFO_CH1_RD_DMA_SBUS_START_ADDRESS", CMIC_CMC2_FIFO_CH1_RD_DMA_SBUS_START_ADDRESSr }, \ 4136 { 0x000332d8, "CMIC_CMC2_FIFO_CH2_RD_DMA_SBUS_START_ADDRESS", CMIC_CMC2_FIFO_CH2_RD_DMA_SBUS_START_ADDRESSr }, \ 4137 { 0x000332dc, "CMIC_CMC2_FIFO_CH3_RD_DMA_SBUS_START_ADDRESS", CMIC_CMC2_FIFO_CH3_RD_DMA_SBUS_START_ADDRESSr }, \ 4138 { 0x000332e0, "CMIC_CMC2_FIFO_CH0_RD_DMA_HOSTMEM_START_ADDRESS", CMIC_CMC2_FIFO_CH0_RD_DMA_HOSTMEM_START_ADDRESSr }, \ 4139 { 0x000332e4, "CMIC_CMC2_FIFO_CH1_RD_DMA_HOSTMEM_START_ADDRESS", CMIC_CMC2_FIFO_CH1_RD_DMA_HOSTMEM_START_ADDRESSr }, \ 4140 { 0x000332e8, "CMIC_CMC2_FIFO_CH2_RD_DMA_HOSTMEM_START_ADDRESS", CMIC_CMC2_FIFO_CH2_RD_DMA_HOSTMEM_START_ADDRESSr }, \ 4141 { 0x000332ec, "CMIC_CMC2_FIFO_CH3_RD_DMA_HOSTMEM_START_ADDRESS", CMIC_CMC2_FIFO_CH3_RD_DMA_HOSTMEM_START_ADDRESSr }, \ 4142 { 0x000332f0, "CMIC_CMC2_FIFO_CH0_RD_DMA_NUM_OF_ENTRIES_READ_FRM_HOSTMEM", CMIC_CMC2_FIFO_CH0_RD_DMA_NUM_OF_ENTRIES_READ_FRM_HOSTMEMr }, \ 4143 { 0x000332f0, "CMIC_CMC2_FIFO_CH0_RD_DMA_HOSTMEM_READ_PTR", CMIC_CMC2_FIFO_CH0_RD_DMA_HOSTMEM_READ_PTRr }, \ 4144 { 0x000332f4, "CMIC_CMC2_FIFO_CH0_RD_DMA_HOSTMEM_WRITE_PTR", CMIC_CMC2_FIFO_CH0_RD_DMA_HOSTMEM_WRITE_PTRr }, \ 4145 { 0x000332f4, "CMIC_CMC2_FIFO_CH0_RD_DMA_NUM_OF_ENTRIES_VALID_IN_HOSTMEM", CMIC_CMC2_FIFO_CH0_RD_DMA_NUM_OF_ENTRIES_VALID_IN_HOSTMEMr }, \ 4146 { 0x000332f8, "CMIC_CMC2_FIFO_CH1_RD_DMA_HOSTMEM_READ_PTR", CMIC_CMC2_FIFO_CH1_RD_DMA_HOSTMEM_READ_PTRr }, \ 4147 { 0x000332f8, "CMIC_CMC2_FIFO_CH1_RD_DMA_NUM_OF_ENTRIES_READ_FRM_HOSTMEM", CMIC_CMC2_FIFO_CH1_RD_DMA_NUM_OF_ENTRIES_READ_FRM_HOSTMEMr }, \ 4148 { 0x000332fc, "CMIC_CMC2_FIFO_CH1_RD_DMA_HOSTMEM_WRITE_PTR", CMIC_CMC2_FIFO_CH1_RD_DMA_HOSTMEM_WRITE_PTRr }, \ 4149 { 0x000332fc, "CMIC_CMC2_FIFO_CH1_RD_DMA_NUM_OF_ENTRIES_VALID_IN_HOSTMEM", CMIC_CMC2_FIFO_CH1_RD_DMA_NUM_OF_ENTRIES_VALID_IN_HOSTMEMr }, \ 4150 { 0x00033300, "CMIC_CMC2_FIFO_CH2_RD_DMA_HOSTMEM_READ_PTR", CMIC_CMC2_FIFO_CH2_RD_DMA_HOSTMEM_READ_PTRr }, \ 4151 { 0x00033300, "CMIC_CMC2_FIFO_CH2_RD_DMA_NUM_OF_ENTRIES_READ_FRM_HOSTMEM", CMIC_CMC2_FIFO_CH2_RD_DMA_NUM_OF_ENTRIES_READ_FRM_HOSTMEMr }, \ 4152 { 0x00033304, "CMIC_CMC2_FIFO_CH2_RD_DMA_NUM_OF_ENTRIES_VALID_IN_HOSTMEM", CMIC_CMC2_FIFO_CH2_RD_DMA_NUM_OF_ENTRIES_VALID_IN_HOSTMEMr }, \ 4153 { 0x00033304, "CMIC_CMC2_FIFO_CH2_RD_DMA_HOSTMEM_WRITE_PTR", CMIC_CMC2_FIFO_CH2_RD_DMA_HOSTMEM_WRITE_PTRr }, \ 4154 { 0x00033308, "CMIC_CMC2_FIFO_CH3_RD_DMA_HOSTMEM_READ_PTR", CMIC_CMC2_FIFO_CH3_RD_DMA_HOSTMEM_READ_PTRr }, \ 4155 { 0x00033308, "CMIC_CMC2_FIFO_CH3_RD_DMA_NUM_OF_ENTRIES_READ_FRM_HOSTMEM", CMIC_CMC2_FIFO_CH3_RD_DMA_NUM_OF_ENTRIES_READ_FRM_HOSTMEMr }, \ 4156 { 0x0003330c, "CMIC_CMC2_FIFO_CH3_RD_DMA_HOSTMEM_WRITE_PTR", CMIC_CMC2_FIFO_CH3_RD_DMA_HOSTMEM_WRITE_PTRr }, \ 4157 { 0x0003330c, "CMIC_CMC2_FIFO_CH3_RD_DMA_NUM_OF_ENTRIES_VALID_IN_HOSTMEM", CMIC_CMC2_FIFO_CH3_RD_DMA_NUM_OF_ENTRIES_VALID_IN_HOSTMEMr }, \ 4158 { 0x00033310, "CMIC_CMC2_FIFO_CH0_RD_DMA_ECCERR_ADDRESS", CMIC_CMC2_FIFO_CH0_RD_DMA_ECCERR_ADDRESSr }, \ 4159 { 0x00033314, "CMIC_CMC2_FIFO_CH1_RD_DMA_ECCERR_ADDRESS", CMIC_CMC2_FIFO_CH1_RD_DMA_ECCERR_ADDRESSr }, \ 4160 { 0x00033318, "CMIC_CMC2_FIFO_CH2_RD_DMA_ECCERR_ADDRESS", CMIC_CMC2_FIFO_CH2_RD_DMA_ECCERR_ADDRESSr }, \ 4161 { 0x0003331c, "CMIC_CMC2_FIFO_CH3_RD_DMA_ECCERR_ADDRESS", CMIC_CMC2_FIFO_CH3_RD_DMA_ECCERR_ADDRESSr }, \ 4162 { 0x00033320, "CMIC_CMC2_FIFO_CH0_RD_DMA_ECCERR_CONTROL", CMIC_CMC2_FIFO_CH0_RD_DMA_ECCERR_CONTROLr }, \ 4163 { 0x00033324, "CMIC_CMC2_FIFO_CH1_RD_DMA_ECCERR_CONTROL", CMIC_CMC2_FIFO_CH1_RD_DMA_ECCERR_CONTROLr }, \ 4164 { 0x00033328, "CMIC_CMC2_FIFO_CH2_RD_DMA_ECCERR_CONTROL", CMIC_CMC2_FIFO_CH2_RD_DMA_ECCERR_CONTROLr }, \ 4165 { 0x0003332c, "CMIC_CMC2_FIFO_CH3_RD_DMA_ECCERR_CONTROL", CMIC_CMC2_FIFO_CH3_RD_DMA_ECCERR_CONTROLr }, \ 4166 { 0x00033330, "CMIC_CMC2_FIFO_CH0_RD_DMA_CUR_HOSTMEM_WRITE_PTR", CMIC_CMC2_FIFO_CH0_RD_DMA_CUR_HOSTMEM_WRITE_PTRr }, \ 4167 { 0x00033334, "CMIC_CMC2_FIFO_CH1_RD_DMA_CUR_HOSTMEM_WRITE_PTR", CMIC_CMC2_FIFO_CH1_RD_DMA_CUR_HOSTMEM_WRITE_PTRr }, \ 4168 { 0x00033338, "CMIC_CMC2_FIFO_CH2_RD_DMA_CUR_HOSTMEM_WRITE_PTR", CMIC_CMC2_FIFO_CH2_RD_DMA_CUR_HOSTMEM_WRITE_PTRr }, \ 4169 { 0x0003333c, "CMIC_CMC2_FIFO_CH3_RD_DMA_CUR_HOSTMEM_WRITE_PTR", CMIC_CMC2_FIFO_CH3_RD_DMA_CUR_HOSTMEM_WRITE_PTRr }, \ 4170 { 0x00033354, "CMIC_CMC2_FIFO_CH0_RD_DMA_HOSTMEM_THRESHOLD", CMIC_CMC2_FIFO_CH0_RD_DMA_HOSTMEM_THRESHOLDr }, \ 4171 { 0x00033358, "CMIC_CMC2_FIFO_CH1_RD_DMA_HOSTMEM_THRESHOLD", CMIC_CMC2_FIFO_CH1_RD_DMA_HOSTMEM_THRESHOLDr }, \ 4172 { 0x0003335c, "CMIC_CMC2_FIFO_CH2_RD_DMA_HOSTMEM_THRESHOLD", CMIC_CMC2_FIFO_CH2_RD_DMA_HOSTMEM_THRESHOLDr }, \ 4173 { 0x00033360, "CMIC_CMC2_FIFO_CH3_RD_DMA_HOSTMEM_THRESHOLD", CMIC_CMC2_FIFO_CH3_RD_DMA_HOSTMEM_THRESHOLDr }, \ 4174 { 0x00033364, "CMIC_CMC2_FIFO_CH0_RD_DMA_STAT", CMIC_CMC2_FIFO_CH0_RD_DMA_STATr }, \ 4175 { 0x00033368, "CMIC_CMC2_FIFO_CH1_RD_DMA_STAT", CMIC_CMC2_FIFO_CH1_RD_DMA_STATr }, \ 4176 { 0x0003336c, "CMIC_CMC2_FIFO_CH2_RD_DMA_STAT", CMIC_CMC2_FIFO_CH2_RD_DMA_STATr }, \ 4177 { 0x00033370, "CMIC_CMC2_FIFO_CH3_RD_DMA_STAT", CMIC_CMC2_FIFO_CH3_RD_DMA_STATr }, \ 4178 { 0x00033374, "CMIC_CMC2_FIFO_CH0_RD_DMA_STAT_CLR", CMIC_CMC2_FIFO_CH0_RD_DMA_STAT_CLRr }, \ 4179 { 0x00033378, "CMIC_CMC2_FIFO_CH1_RD_DMA_STAT_CLR", CMIC_CMC2_FIFO_CH1_RD_DMA_STAT_CLRr }, \ 4180 { 0x0003337c, "CMIC_CMC2_FIFO_CH2_RD_DMA_STAT_CLR", CMIC_CMC2_FIFO_CH2_RD_DMA_STAT_CLRr }, \ 4181 { 0x00033380, "CMIC_CMC2_FIFO_CH3_RD_DMA_STAT_CLR", CMIC_CMC2_FIFO_CH3_RD_DMA_STAT_CLRr }, \ 4182 { 0x00033384, "CMIC_CMC2_FIFO_CH0_RD_DMA_SBUS_CMD_CONFIG", CMIC_CMC2_FIFO_CH0_RD_DMA_SBUS_CMD_CONFIGr }, \ 4183 { 0x00033384, "CMIC_CMC2_FIFO_CH0_RD_DMA_OPCODE", CMIC_CMC2_FIFO_CH0_RD_DMA_OPCODEr }, \ 4184 { 0x00033388, "CMIC_CMC2_FIFO_CH1_RD_DMA_SBUS_CMD_CONFIG", CMIC_CMC2_FIFO_CH1_RD_DMA_SBUS_CMD_CONFIGr }, \ 4185 { 0x00033388, "CMIC_CMC2_FIFO_CH1_RD_DMA_OPCODE", CMIC_CMC2_FIFO_CH1_RD_DMA_OPCODEr }, \ 4186 { 0x0003338c, "CMIC_CMC2_FIFO_CH2_RD_DMA_SBUS_CMD_CONFIG", CMIC_CMC2_FIFO_CH2_RD_DMA_SBUS_CMD_CONFIGr }, \ 4187 { 0x0003338c, "CMIC_CMC2_FIFO_CH2_RD_DMA_OPCODE", CMIC_CMC2_FIFO_CH2_RD_DMA_OPCODEr }, \ 4188 { 0x00033390, "CMIC_CMC2_FIFO_CH3_RD_DMA_SBUS_CMD_CONFIG", CMIC_CMC2_FIFO_CH3_RD_DMA_SBUS_CMD_CONFIGr }, \ 4189 { 0x00033390, "CMIC_CMC2_FIFO_CH3_RD_DMA_OPCODE", CMIC_CMC2_FIFO_CH3_RD_DMA_OPCODEr }, \ 4190 { 0x00033394, "CMIC_CMC2_FIFO_RD_DMA_DEBUG", CMIC_CMC2_FIFO_RD_DMA_DEBUGr }, \ 4191 { 0x000333a0, "CMIC_CMC2_CCM_DMA_HOST0_MEM_START_ADDR", CMIC_CMC2_CCM_DMA_HOST0_MEM_START_ADDRr }, \ 4192 { 0x000333a4, "CMIC_CMC2_CCM_DMA_HOST1_MEM_START_ADDR", CMIC_CMC2_CCM_DMA_HOST1_MEM_START_ADDRr }, \ 4193 { 0x000333a8, "CMIC_CMC2_CCM_DMA_ENTRY_COUNT", CMIC_CMC2_CCM_DMA_ENTRY_COUNTr }, \ 4194 { 0x000333ac, "CMIC_CMC2_CCM_DMA_CFG", CMIC_CMC2_CCM_DMA_CFGr }, \ 4195 { 0x000333b0, "CMIC_CMC2_CCM_DMA_STAT", CMIC_CMC2_CCM_DMA_STATr }, \ 4196 { 0x000333b4, "CMIC_CMC2_CCM_DMA_CUR_HOST0_ADDR", CMIC_CMC2_CCM_DMA_CUR_HOST0_ADDRr }, \ 4197 { 0x000333b8, "CMIC_CMC2_CCM_DMA_CUR_HOST1_ADDR", CMIC_CMC2_CCM_DMA_CUR_HOST1_ADDRr }, \ 4198 { 0x000333bc, "CMIC_CMC2_CCM_DMA_ECCERR_ADDR", CMIC_CMC2_CCM_DMA_ECCERR_ADDRr }, \ 4199 { 0x000333c0, "CMIC_CMC2_CCM_DMA_STATUS_CLR", CMIC_CMC2_CCM_DMA_STATUS_CLRr }, \ 4200 { 0x000333c4, "CMIC_CMC2_CCM_DMA_ECCERR_CONTROL", CMIC_CMC2_CCM_DMA_ECCERR_CONTROLr }, \ 4201 { 0x00033400, "CMIC_CMC2_IRQ_STAT0", CMIC_CMC2_IRQ_STAT0r }, \ 4202 { 0x00033404, "CMIC_CMC2_IRQ_STAT1", CMIC_CMC2_IRQ_STAT1r }, \ 4203 { 0x00033408, "CMIC_CMC2_IRQ_STAT2", CMIC_CMC2_IRQ_STAT2r }, \ 4204 { 0x0003340c, "CMIC_CMC2_IRQ_STAT3", CMIC_CMC2_IRQ_STAT3r }, \ 4205 { 0x00033410, "CMIC_CMC2_IRQ_STAT4", CMIC_CMC2_IRQ_STAT4r }, \ 4206 { 0x00033414, "CMIC_CMC2_PCIE_IRQ_MASK0", CMIC_CMC2_PCIE_IRQ_MASK0r }, \ 4207 { 0x00033418, "CMIC_CMC2_PCIE_IRQ_MASK1", CMIC_CMC2_PCIE_IRQ_MASK1r }, \ 4208 { 0x0003341c, "CMIC_CMC2_PCIE_IRQ_MASK2", CMIC_CMC2_PCIE_IRQ_MASK2r }, \ 4209 { 0x00033420, "CMIC_CMC2_PCIE_IRQ_MASK3", CMIC_CMC2_PCIE_IRQ_MASK3r }, \ 4210 { 0x00033424, "CMIC_CMC2_PCIE_IRQ_MASK4", CMIC_CMC2_PCIE_IRQ_MASK4r }, \ 4211 { 0x00033428, "CMIC_CMC2_UC0_IRQ_MASK0", CMIC_CMC2_UC0_IRQ_MASK0r }, \ 4212 { 0x0003342c, "CMIC_CMC2_UC0_IRQ_MASK1", CMIC_CMC2_UC0_IRQ_MASK1r }, \ 4213 { 0x00033430, "CMIC_CMC2_UC0_IRQ_MASK2", CMIC_CMC2_UC0_IRQ_MASK2r }, \ 4214 { 0x00033434, "CMIC_CMC2_UC0_IRQ_MASK3", CMIC_CMC2_UC0_IRQ_MASK3r }, \ 4215 { 0x00033438, "CMIC_CMC2_UC0_IRQ_MASK4", CMIC_CMC2_UC0_IRQ_MASK4r }, \ 4216 { 0x0003343c, "CMIC_CMC2_UC1_IRQ_MASK0", CMIC_CMC2_UC1_IRQ_MASK0r }, \ 4217 { 0x00033440, "CMIC_CMC2_UC1_IRQ_MASK1", CMIC_CMC2_UC1_IRQ_MASK1r }, \ 4218 { 0x00033444, "CMIC_CMC2_UC1_IRQ_MASK2", CMIC_CMC2_UC1_IRQ_MASK2r }, \ 4219 { 0x00033448, "CMIC_CMC2_UC1_IRQ_MASK3", CMIC_CMC2_UC1_IRQ_MASK3r }, \ 4220 { 0x0003344c, "CMIC_CMC2_UC1_IRQ_MASK4", CMIC_CMC2_UC1_IRQ_MASK4r }, \ 4221 { 0x00033450, "CMIC_CMC2_RCPU_IRQ_MASK0", CMIC_CMC2_RCPU_IRQ_MASK0r }, \ 4222 { 0x00033454, "CMIC_CMC2_2BIT_ECC_ERROR_STATUS", CMIC_CMC2_2BIT_ECC_ERROR_STATUSr }, \ 4223 { 0x00033458, "CMIC_CMC2_2BIT_ECC_ERROR_STATUS_MASK", CMIC_CMC2_2BIT_ECC_ERROR_STATUS_MASKr }, \ 4224 { 0x00033470, "CMIC_CMC2_PCIE_MISCEL", CMIC_CMC2_PCIE_MISCELr }, \ 4225 { 0x00033474, "CMIC_CMC2_HOSTMEM_ADDR_REMAP_0", CMIC_CMC2_HOSTMEM_ADDR_REMAP_0r }, \ 4226 { 0x00033478, "CMIC_CMC2_HOSTMEM_ADDR_REMAP_1", CMIC_CMC2_HOSTMEM_ADDR_REMAP_1r }, \ 4227 { 0x0003347c, "CMIC_CMC2_HOSTMEM_ADDR_REMAP_2", CMIC_CMC2_HOSTMEM_ADDR_REMAP_2r }, \ 4228 { 0x00033480, "CMIC_CMC2_PKT_COUNT_CH0_RXPKT", CMIC_CMC2_PKT_COUNT_CH0_RXPKTr }, \ 4229 { 0x00033484, "CMIC_CMC2_PKT_COUNT_CH0_TXPKT", CMIC_CMC2_PKT_COUNT_CH0_TXPKTr }, \ 4230 { 0x00033488, "CMIC_CMC2_PKT_COUNT_CH1_RXPKT", CMIC_CMC2_PKT_COUNT_CH1_RXPKTr }, \ 4231 { 0x0003348c, "CMIC_CMC2_PKT_COUNT_CH1_TXPKT", CMIC_CMC2_PKT_COUNT_CH1_TXPKTr }, \ 4232 { 0x00033490, "CMIC_CMC2_PKT_COUNT_CH2_RXPKT", CMIC_CMC2_PKT_COUNT_CH2_RXPKTr }, \ 4233 { 0x00033494, "CMIC_CMC2_PKT_COUNT_CH2_TXPKT", CMIC_CMC2_PKT_COUNT_CH2_TXPKTr }, \ 4234 { 0x00033498, "CMIC_CMC2_PKT_COUNT_CH3_RXPKT", CMIC_CMC2_PKT_COUNT_CH3_RXPKTr }, \ 4235 { 0x0003349c, "CMIC_CMC2_PKT_COUNT_CH3_TXPKT", CMIC_CMC2_PKT_COUNT_CH3_TXPKTr }, \ 4236 { 0x000334a0, "CMIC_CMC2_PKT_COUNT_RXPKT", CMIC_CMC2_PKT_COUNT_RXPKTr }, \ 4237 { 0x000334a4, "CMIC_CMC2_PKT_COUNT_TXPKT", CMIC_CMC2_PKT_COUNT_TXPKTr }, \ 4238 { 0x000334a8, "CMIC_CMC2_SW_INTR_CONFIG", CMIC_CMC2_SW_INTR_CONFIGr }, \ 4239 { 0x000334ac, "CMIC_CMC2_HOSTMEM_ADDR_REMAP_3", CMIC_CMC2_HOSTMEM_ADDR_REMAP_3r }, \ 4240 { 0x000334b0, "CMIC_CMC2_IRQ_STAT5", CMIC_CMC2_IRQ_STAT5r }, \ 4241 { 0x000334b4, "CMIC_CMC2_IRQ_STAT6", CMIC_CMC2_IRQ_STAT6r }, \ 4242 { 0x000334b8, "CMIC_CMC2_PCIE_IRQ_MASK5", CMIC_CMC2_PCIE_IRQ_MASK5r }, \ 4243 { 0x000334bc, "CMIC_CMC2_PCIE_IRQ_MASK6", CMIC_CMC2_PCIE_IRQ_MASK6r }, \ 4244 { 0x000334c0, "CMIC_CMC2_UC0_IRQ_MASK5", CMIC_CMC2_UC0_IRQ_MASK5r }, \ 4245 { 0x000334c4, "CMIC_CMC2_UC0_IRQ_MASK6", CMIC_CMC2_UC0_IRQ_MASK6r }, \ 4246 { 0x000334c8, "CMIC_CMC2_UC1_IRQ_MASK5", CMIC_CMC2_UC1_IRQ_MASK5r }, \ 4247 { 0x000334cc, "CMIC_CMC2_UC1_IRQ_MASK6", CMIC_CMC2_UC1_IRQ_MASK6r }, \ 4248 { 0x000334d0, "CMIC_CMC2_AXIIC_DMA_ECC_INTR_ENABLE", CMIC_CMC2_AXIIC_DMA_ECC_INTR_ENABLEr }, \ 4249 { 0x000334d4, "CMIC_CMC2_AXIIC_DMA_ECC_INTR", CMIC_CMC2_AXIIC_DMA_ECC_INTRr }, \ 4250 { 0x000334d8, "CMIC_CMC2_AXIIC_DMA_ECC_INTR_CLR", CMIC_CMC2_AXIIC_DMA_ECC_INTR_CLRr }, \ 4251 { 0x00033600, "CMIC_CMC2_SBUSDMA_CH0_CONTROL", CMIC_CMC2_SBUSDMA_CH0_CONTROLr }, \ 4252 { 0x00033604, "CMIC_CMC2_SBUSDMA_CH0_REQUEST", CMIC_CMC2_SBUSDMA_CH0_REQUESTr }, \ 4253 { 0x00033608, "CMIC_CMC2_SBUSDMA_CH0_COUNT", CMIC_CMC2_SBUSDMA_CH0_COUNTr }, \ 4254 { 0x0003360c, "CMIC_CMC2_SBUSDMA_CH0_OPCODE", CMIC_CMC2_SBUSDMA_CH0_OPCODEr }, \ 4255 { 0x00033610, "CMIC_CMC2_SBUSDMA_CH0_SBUS_START_ADDRESS", CMIC_CMC2_SBUSDMA_CH0_SBUS_START_ADDRESSr }, \ 4256 { 0x00033614, "CMIC_CMC2_SBUSDMA_CH0_HOSTMEM_START_ADDRESS", CMIC_CMC2_SBUSDMA_CH0_HOSTMEM_START_ADDRESSr }, \ 4257 { 0x00033618, "CMIC_CMC2_SBUSDMA_CH0_DESC_START_ADDRESS", CMIC_CMC2_SBUSDMA_CH0_DESC_START_ADDRESSr }, \ 4258 { 0x0003361c, "CMIC_CMC2_SBUSDMA_CH0_STATUS", CMIC_CMC2_SBUSDMA_CH0_STATUSr }, \ 4259 { 0x00033620, "CMIC_CMC2_SBUSDMA_CH0_CUR_HOSTMEM_ADDRESS", CMIC_CMC2_SBUSDMA_CH0_CUR_HOSTMEM_ADDRESSr }, \ 4260 { 0x00033624, "CMIC_CMC2_SBUSDMA_CH0_CUR_SBUS_ADDRESS", CMIC_CMC2_SBUSDMA_CH0_CUR_SBUS_ADDRESSr }, \ 4261 { 0x00033628, "CMIC_CMC2_SBUSDMA_CH0_CUR_DESC_ADDRESS", CMIC_CMC2_SBUSDMA_CH0_CUR_DESC_ADDRESSr }, \ 4262 { 0x0003362c, "CMIC_CMC2_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_REQUEST", CMIC_CMC2_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_REQUESTr }, \ 4263 { 0x00033630, "CMIC_CMC2_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_COUNT", CMIC_CMC2_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_COUNTr }, \ 4264 { 0x00033634, "CMIC_CMC2_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_SBUS_START_ADDRESS", CMIC_CMC2_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_SBUS_START_ADDRESSr }, \ 4265 { 0x00033638, "CMIC_CMC2_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS", CMIC_CMC2_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESSr }, \ 4266 { 0x0003363c, "CMIC_CMC2_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_OPCODE", CMIC_CMC2_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_OPCODEr }, \ 4267 { 0x00033640, "CMIC_CMC2_SBUSDMA_CH0_SBUSDMA_DEBUG", CMIC_CMC2_SBUSDMA_CH0_SBUSDMA_DEBUGr }, \ 4268 { 0x00033644, "CMIC_CMC2_SBUSDMA_CH0_SBUSDMA_DEBUG_CLR", CMIC_CMC2_SBUSDMA_CH0_SBUSDMA_DEBUG_CLRr }, \ 4269 { 0x00033648, "CMIC_CMC2_SBUSDMA_CH0_SBUSDMA_ECCERR_ADDRESS", CMIC_CMC2_SBUSDMA_CH0_SBUSDMA_ECCERR_ADDRESSr }, \ 4270 { 0x0003364c, "CMIC_CMC2_SBUSDMA_CH0_SBUSDMA_ECCERR_CONTROL", CMIC_CMC2_SBUSDMA_CH0_SBUSDMA_ECCERR_CONTROLr }, \ 4271 { 0x00033650, "CMIC_CMC2_SBUSDMA_CH1_CONTROL", CMIC_CMC2_SBUSDMA_CH1_CONTROLr }, \ 4272 { 0x00033654, "CMIC_CMC2_SBUSDMA_CH1_REQUEST", CMIC_CMC2_SBUSDMA_CH1_REQUESTr }, \ 4273 { 0x00033658, "CMIC_CMC2_SBUSDMA_CH1_COUNT", CMIC_CMC2_SBUSDMA_CH1_COUNTr }, \ 4274 { 0x0003365c, "CMIC_CMC2_SBUSDMA_CH1_OPCODE", CMIC_CMC2_SBUSDMA_CH1_OPCODEr }, \ 4275 { 0x00033660, "CMIC_CMC2_SBUSDMA_CH1_SBUS_START_ADDRESS", CMIC_CMC2_SBUSDMA_CH1_SBUS_START_ADDRESSr }, \ 4276 { 0x00033664, "CMIC_CMC2_SBUSDMA_CH1_HOSTMEM_START_ADDRESS", CMIC_CMC2_SBUSDMA_CH1_HOSTMEM_START_ADDRESSr }, \ 4277 { 0x00033668, "CMIC_CMC2_SBUSDMA_CH1_DESC_START_ADDRESS", CMIC_CMC2_SBUSDMA_CH1_DESC_START_ADDRESSr }, \ 4278 { 0x0003366c, "CMIC_CMC2_SBUSDMA_CH1_STATUS", CMIC_CMC2_SBUSDMA_CH1_STATUSr }, \ 4279 { 0x00033670, "CMIC_CMC2_SBUSDMA_CH1_CUR_HOSTMEM_ADDRESS", CMIC_CMC2_SBUSDMA_CH1_CUR_HOSTMEM_ADDRESSr }, \ 4280 { 0x00033674, "CMIC_CMC2_SBUSDMA_CH1_CUR_SBUS_ADDRESS", CMIC_CMC2_SBUSDMA_CH1_CUR_SBUS_ADDRESSr }, \ 4281 { 0x00033678, "CMIC_CMC2_SBUSDMA_CH1_CUR_DESC_ADDRESS", CMIC_CMC2_SBUSDMA_CH1_CUR_DESC_ADDRESSr }, \ 4282 { 0x0003367c, "CMIC_CMC2_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_REQUEST", CMIC_CMC2_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_REQUESTr }, \ 4283 { 0x00033680, "CMIC_CMC2_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_COUNT", CMIC_CMC2_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_COUNTr }, \ 4284 { 0x00033684, "CMIC_CMC2_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_SBUS_START_ADDRESS", CMIC_CMC2_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_SBUS_START_ADDRESSr }, \ 4285 { 0x00033688, "CMIC_CMC2_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS", CMIC_CMC2_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESSr }, \ 4286 { 0x0003368c, "CMIC_CMC2_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_OPCODE", CMIC_CMC2_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_OPCODEr }, \ 4287 { 0x00033690, "CMIC_CMC2_SBUSDMA_CH1_SBUSDMA_DEBUG", CMIC_CMC2_SBUSDMA_CH1_SBUSDMA_DEBUGr }, \ 4288 { 0x00033694, "CMIC_CMC2_SBUSDMA_CH1_SBUSDMA_DEBUG_CLR", CMIC_CMC2_SBUSDMA_CH1_SBUSDMA_DEBUG_CLRr }, \ 4289 { 0x00033698, "CMIC_CMC2_SBUSDMA_CH1_SBUSDMA_ECCERR_ADDRESS", CMIC_CMC2_SBUSDMA_CH1_SBUSDMA_ECCERR_ADDRESSr }, \ 4290 { 0x0003369c, "CMIC_CMC2_SBUSDMA_CH1_SBUSDMA_ECCERR_CONTROL", CMIC_CMC2_SBUSDMA_CH1_SBUSDMA_ECCERR_CONTROLr }, \ 4291 { 0x000336a0, "CMIC_CMC2_SBUSDMA_CH2_CONTROL", CMIC_CMC2_SBUSDMA_CH2_CONTROLr }, \ 4292 { 0x000336a4, "CMIC_CMC2_SBUSDMA_CH2_REQUEST", CMIC_CMC2_SBUSDMA_CH2_REQUESTr }, \ 4293 { 0x000336a8, "CMIC_CMC2_SBUSDMA_CH2_COUNT", CMIC_CMC2_SBUSDMA_CH2_COUNTr }, \ 4294 { 0x000336ac, "CMIC_CMC2_SBUSDMA_CH2_OPCODE", CMIC_CMC2_SBUSDMA_CH2_OPCODEr }, \ 4295 { 0x000336b0, "CMIC_CMC2_SBUSDMA_CH2_SBUS_START_ADDRESS", CMIC_CMC2_SBUSDMA_CH2_SBUS_START_ADDRESSr }, \ 4296 { 0x000336b4, "CMIC_CMC2_SBUSDMA_CH2_HOSTMEM_START_ADDRESS", CMIC_CMC2_SBUSDMA_CH2_HOSTMEM_START_ADDRESSr }, \ 4297 { 0x000336b8, "CMIC_CMC2_SBUSDMA_CH2_DESC_START_ADDRESS", CMIC_CMC2_SBUSDMA_CH2_DESC_START_ADDRESSr }, \ 4298 { 0x000336bc, "CMIC_CMC2_SBUSDMA_CH2_STATUS", CMIC_CMC2_SBUSDMA_CH2_STATUSr }, \ 4299 { 0x000336c0, "CMIC_CMC2_SBUSDMA_CH2_CUR_HOSTMEM_ADDRESS", CMIC_CMC2_SBUSDMA_CH2_CUR_HOSTMEM_ADDRESSr }, \ 4300 { 0x000336c4, "CMIC_CMC2_SBUSDMA_CH2_CUR_SBUS_ADDRESS", CMIC_CMC2_SBUSDMA_CH2_CUR_SBUS_ADDRESSr }, \ 4301 { 0x000336c8, "CMIC_CMC2_SBUSDMA_CH2_CUR_DESC_ADDRESS", CMIC_CMC2_SBUSDMA_CH2_CUR_DESC_ADDRESSr }, \ 4302 { 0x000336cc, "CMIC_CMC2_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_REQUEST", CMIC_CMC2_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_REQUESTr }, \ 4303 { 0x000336d0, "CMIC_CMC2_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_COUNT", CMIC_CMC2_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_COUNTr }, \ 4304 { 0x000336d4, "CMIC_CMC2_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_SBUS_START_ADDRESS", CMIC_CMC2_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_SBUS_START_ADDRESSr }, \ 4305 { 0x000336d8, "CMIC_CMC2_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS", CMIC_CMC2_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESSr }, \ 4306 { 0x000336dc, "CMIC_CMC2_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_OPCODE", CMIC_CMC2_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_OPCODEr }, \ 4307 { 0x000336e0, "CMIC_CMC2_SBUSDMA_CH2_SBUSDMA_DEBUG", CMIC_CMC2_SBUSDMA_CH2_SBUSDMA_DEBUGr }, \ 4308 { 0x000336e4, "CMIC_CMC2_SBUSDMA_CH2_SBUSDMA_DEBUG_CLR", CMIC_CMC2_SBUSDMA_CH2_SBUSDMA_DEBUG_CLRr }, \ 4309 { 0x000336e8, "CMIC_CMC2_SBUSDMA_CH2_SBUSDMA_ECCERR_ADDRESS", CMIC_CMC2_SBUSDMA_CH2_SBUSDMA_ECCERR_ADDRESSr }, \ 4310 { 0x000336ec, "CMIC_CMC2_SBUSDMA_CH2_SBUSDMA_ECCERR_CONTROL", CMIC_CMC2_SBUSDMA_CH2_SBUSDMA_ECCERR_CONTROLr }, \ 4311 { 0x000336f0, "CMIC_CMC2_SBUSDMA_CH0_TIMER", CMIC_CMC2_SBUSDMA_CH0_TIMERr }, \ 4312 { 0x000336f4, "CMIC_CMC2_SBUSDMA_CH1_TIMER", CMIC_CMC2_SBUSDMA_CH1_TIMERr }, \ 4313 { 0x000336f8, "CMIC_CMC2_SBUSDMA_CH2_TIMER", CMIC_CMC2_SBUSDMA_CH2_TIMERr }, \ 4314 { 0x000336fc, "CMIC_CMC2_SBUSDMA_CH0_ITER_COUNT", CMIC_CMC2_SBUSDMA_CH0_ITER_COUNTr }, \ 4315 { 0x00033700, "CMIC_CMC2_SBUSDMA_CH1_ITER_COUNT", CMIC_CMC2_SBUSDMA_CH1_ITER_COUNTr }, \ 4316 { 0x00033704, "CMIC_CMC2_SBUSDMA_CH2_ITER_COUNT", CMIC_CMC2_SBUSDMA_CH2_ITER_COUNTr }, \ 4317 { 0x00033800, "CMIC_CMC2_SBUSDMA_CH0_TM_CONTROL_0", CMIC_CMC2_SBUSDMA_CH0_TM_CONTROL_0r }, \ 4318 { 0x00033804, "CMIC_CMC2_SBUSDMA_CH0_TM_CONTROL_1", CMIC_CMC2_SBUSDMA_CH0_TM_CONTROL_1r }, \ 4319 { 0x0003380c, "CMIC_CMC2_SBUSDMA_CH0_TM_CONTROL_2", CMIC_CMC2_SBUSDMA_CH0_TM_CONTROL_2r }, \ 4320 { 0x00033810, "CMIC_CMC2_SBUSDMA_CH1_TM_CONTROL_0", CMIC_CMC2_SBUSDMA_CH1_TM_CONTROL_0r }, \ 4321 { 0x00033814, "CMIC_CMC2_SBUSDMA_CH1_TM_CONTROL_1", CMIC_CMC2_SBUSDMA_CH1_TM_CONTROL_1r }, \ 4322 { 0x00033818, "CMIC_CMC2_SBUSDMA_CH1_TM_CONTROL_2", CMIC_CMC2_SBUSDMA_CH1_TM_CONTROL_2r }, \ 4323 { 0x0003381c, "CMIC_CMC2_SBUSDMA_CH2_TM_CONTROL_0", CMIC_CMC2_SBUSDMA_CH2_TM_CONTROL_0r }, \ 4324 { 0x00033820, "CMIC_CMC2_SBUSDMA_CH2_TM_CONTROL_1", CMIC_CMC2_SBUSDMA_CH2_TM_CONTROL_1r }, \ 4325 { 0x00033824, "CMIC_CMC2_SBUSDMA_CH2_TM_CONTROL_2", CMIC_CMC2_SBUSDMA_CH2_TM_CONTROL_2r }, \ 4326 { 0x00033828, "CMIC_CMC2_FIFORDDMA_CH0_TM_CONTROL_0", CMIC_CMC2_FIFORDDMA_CH0_TM_CONTROL_0r }, \ 4327 { 0x0003382c, "CMIC_CMC2_FIFORDDMA_CH0_TM_CONTROL_1", CMIC_CMC2_FIFORDDMA_CH0_TM_CONTROL_1r }, \ 4328 { 0x00033830, "CMIC_CMC2_FIFORDDMA_CH1_TM_CONTROL_0", CMIC_CMC2_FIFORDDMA_CH1_TM_CONTROL_0r }, \ 4329 { 0x00033834, "CMIC_CMC2_FIFORDDMA_CH1_TM_CONTROL_1", CMIC_CMC2_FIFORDDMA_CH1_TM_CONTROL_1r }, \ 4330 { 0x00033838, "CMIC_CMC2_FIFORDDMA_CH2_TM_CONTROL_0", CMIC_CMC2_FIFORDDMA_CH2_TM_CONTROL_0r }, \ 4331 { 0x0003383c, "CMIC_CMC2_FIFORDDMA_CH2_TM_CONTROL_1", CMIC_CMC2_FIFORDDMA_CH2_TM_CONTROL_1r }, \ 4332 { 0x00033840, "CMIC_CMC2_FIFORDDMA_CH3_TM_CONTROL_0", CMIC_CMC2_FIFORDDMA_CH3_TM_CONTROL_0r }, \ 4333 { 0x00033844, "CMIC_CMC2_FIFORDDMA_CH3_TM_CONTROL_1", CMIC_CMC2_FIFORDDMA_CH3_TM_CONTROL_1r }, \ 4334 { 0x00033848, "CMIC_CMC2_CCMDMA_TM_CONTROL_0", CMIC_CMC2_CCMDMA_TM_CONTROL_0r }, \ 4335 { 0x0003384c, "CMIC_CMC2_CCMDMA_TM_CONTROL_1", CMIC_CMC2_CCMDMA_TM_CONTROL_1r }, \ 4336 { 0x00033850, "CMIC_CMC2_AXIIC_TM_CONTROL_0", CMIC_CMC2_AXIIC_TM_CONTROL_0r }, \ 4337 { 0x00033854, "CMIC_CMC2_AXIIC_TM_CONTROL_1", CMIC_CMC2_AXIIC_TM_CONTROL_1r }, \ 4338 { 0x00033858, "CMIC_CMC2_AXIIC_TM_CONTROL_2", CMIC_CMC2_AXIIC_TM_CONTROL_2r }, \ 4339 } 4340 4341 #define CMICM_OFFSET_MIN (0) 4342 #define CMICM_OFFSET_MAX (0x00033858) 4343 #define NUM_CMICM_REGS (4281) 4344 4345 #define CMICM_BSPI_B0_CNTRL_OFFSET (0x1690) 4346 #define CMICM_BSPI_B0_STATUS_OFFSET (0x168c) 4347 #define CMICM_BSPI_B1_CNTRL_OFFSET (0x1698) 4348 #define CMICM_BSPI_B1_STATUS_OFFSET (0x1694) 4349 #define CMICM_BSPI_BUSY_STATUS_OFFSET (0x1684) 4350 #define CMICM_BSPI_INTR_STATUS_OFFSET (0x1688) 4351 #define CMICM_BSPI_MAST_N_BOOT_OFFSET (0x1680) 4352 #define CMICM_COMMON_CONFIG_OFFSET (0x10194) 4353 #define CMICM_REVID_OFFSET (0x10228) 4354 #define CMIC_BROADSYNC_REF_CLK_GEN_CTRL_OFFSET (0x106fc) 4355 #define CMIC_BS0_CLK_CTRL_OFFSET (0x10704) 4356 #define CMIC_BS0_CONFIG_OFFSET (0x10700) 4357 #define CMIC_BS0_HEARTBEAT_CTRL_OFFSET (0x10708) 4358 #define CMIC_BS0_HEARTBEAT_DOWN_DURATION_OFFSET (0x10710) 4359 #define CMIC_BS0_HEARTBEAT_UP_DURATION_OFFSET (0x1070c) 4360 #define CMIC_BS0_INITIAL_CRC_OFFSET (0x1072c) 4361 #define CMIC_BS0_INPUT_TIME_0_OFFSET (0x10720) 4362 #define CMIC_BS0_INPUT_TIME_1_OFFSET (0x10724) 4363 #define CMIC_BS0_INPUT_TIME_2_OFFSET (0x10728) 4364 #define CMIC_BS0_OUTPUT_TIME_0_OFFSET (0x10714) 4365 #define CMIC_BS0_OUTPUT_TIME_1_OFFSET (0x10718) 4366 #define CMIC_BS0_OUTPUT_TIME_2_OFFSET (0x1071c) 4367 #define CMIC_BS1_CLK_CTRL_OFFSET (0x10804) 4368 #define CMIC_BS1_CONFIG_OFFSET (0x10800) 4369 #define CMIC_BS1_HEARTBEAT_CTRL_OFFSET (0x10808) 4370 #define CMIC_BS1_HEARTBEAT_DOWN_DURATION_OFFSET (0x10810) 4371 #define CMIC_BS1_HEARTBEAT_UP_DURATION_OFFSET (0x1080c) 4372 #define CMIC_BS1_INITIAL_CRC_OFFSET (0x1082c) 4373 #define CMIC_BS1_INPUT_TIME_0_OFFSET (0x10820) 4374 #define CMIC_BS1_INPUT_TIME_1_OFFSET (0x10824) 4375 #define CMIC_BS1_INPUT_TIME_2_OFFSET (0x10828) 4376 #define CMIC_BS1_OUTPUT_TIME_0_OFFSET (0x10814) 4377 #define CMIC_BS1_OUTPUT_TIME_1_OFFSET (0x10818) 4378 #define CMIC_BS1_OUTPUT_TIME_2_OFFSET (0x1081c) 4379 #define CMIC_BS_CLK_CTRL_OFFSET (0x10504) 4380 #define CMIC_BS_CONFIG_OFFSET (0x10500) 4381 #define CMIC_BS_HEARTBEAT_CTRL_OFFSET (0x10508) 4382 #define CMIC_BS_HEARTBEAT_DOWN_DURATION_OFFSET (0x10510) 4383 #define CMIC_BS_HEARTBEAT_UP_DURATION_OFFSET (0x1050c) 4384 #define CMIC_BS_INITIAL_CRC_OFFSET (0x1052c) 4385 #define CMIC_BS_INPUT_TIME_0_OFFSET (0x10520) 4386 #define CMIC_BS_INPUT_TIME_1_OFFSET (0x10524) 4387 #define CMIC_BS_INPUT_TIME_2_OFFSET (0x10528) 4388 #define CMIC_BS_OUTPUT_TIME_0_OFFSET (0x10514) 4389 #define CMIC_BS_OUTPUT_TIME_1_OFFSET (0x10518) 4390 #define CMIC_BS_OUTPUT_TIME_2_OFFSET (0x1051c) 4391 #define CMIC_BS_REF_CLK_GEN_CTRL_OFFSET (0x10474) 4392 #define CMIC_CMC0_2BIT_ECC_ERROR_STATUS_OFFSET (0x31454) 4393 #define CMIC_CMC1_2BIT_ECC_ERROR_STATUS_OFFSET (0x32454) 4394 #define CMIC_CMC2_2BIT_ECC_ERROR_STATUS_OFFSET (0x33454) 4395 #define CMIC_CMCx_2BIT_ECC_ERROR_STATUS_OFFSET(x) (0x31454 + (0x1000 * x)) 4396 #define CMIC_CMC0_2BIT_ECC_ERROR_STATUS_MASK_OFFSET (0x31458) 4397 #define CMIC_CMC1_2BIT_ECC_ERROR_STATUS_MASK_OFFSET (0x32458) 4398 #define CMIC_CMC2_2BIT_ECC_ERROR_STATUS_MASK_OFFSET (0x33458) 4399 #define CMIC_CMCx_2BIT_ECC_ERROR_STATUS_MASK_OFFSET(x) (0x31458 + (0x1000 * x)) 4400 #define CMIC_CMC0_AXIIC_DMA_ECC_INTR_OFFSET (0x314d4) 4401 #define CMIC_CMC1_AXIIC_DMA_ECC_INTR_OFFSET (0x324d4) 4402 #define CMIC_CMC2_AXIIC_DMA_ECC_INTR_OFFSET (0x334d4) 4403 #define CMIC_CMCx_AXIIC_DMA_ECC_INTR_OFFSET(x) (0x314d4 + (0x1000 * x)) 4404 #define CMIC_CMC0_AXIIC_DMA_ECC_INTR_CLR_OFFSET (0x314d8) 4405 #define CMIC_CMC1_AXIIC_DMA_ECC_INTR_CLR_OFFSET (0x324d8) 4406 #define CMIC_CMC2_AXIIC_DMA_ECC_INTR_CLR_OFFSET (0x334d8) 4407 #define CMIC_CMCx_AXIIC_DMA_ECC_INTR_CLR_OFFSET(x) (0x314d8 + (0x1000 * x)) 4408 #define CMIC_CMC0_AXIIC_DMA_ECC_INTR_ENABLE_OFFSET (0x314d0) 4409 #define CMIC_CMC1_AXIIC_DMA_ECC_INTR_ENABLE_OFFSET (0x324d0) 4410 #define CMIC_CMC2_AXIIC_DMA_ECC_INTR_ENABLE_OFFSET (0x334d0) 4411 #define CMIC_CMCx_AXIIC_DMA_ECC_INTR_ENABLE_OFFSET(x) (0x314d0 + (0x1000 * x)) 4412 #define CMIC_CMC0_AXIIC_TM_CONTROL_0_OFFSET (0x31850) 4413 #define CMIC_CMC1_AXIIC_TM_CONTROL_0_OFFSET (0x32850) 4414 #define CMIC_CMC2_AXIIC_TM_CONTROL_0_OFFSET (0x33850) 4415 #define CMIC_CMCx_AXIIC_TM_CONTROL_0_OFFSET(x) (0x31850 + (0x1000 * x)) 4416 #define CMIC_CMC0_AXIIC_TM_CONTROL_1_OFFSET (0x31854) 4417 #define CMIC_CMC1_AXIIC_TM_CONTROL_1_OFFSET (0x32854) 4418 #define CMIC_CMC2_AXIIC_TM_CONTROL_1_OFFSET (0x33854) 4419 #define CMIC_CMCx_AXIIC_TM_CONTROL_1_OFFSET(x) (0x31854 + (0x1000 * x)) 4420 #define CMIC_CMC0_AXIIC_TM_CONTROL_2_OFFSET (0x31858) 4421 #define CMIC_CMC1_AXIIC_TM_CONTROL_2_OFFSET (0x32858) 4422 #define CMIC_CMC2_AXIIC_TM_CONTROL_2_OFFSET (0x33858) 4423 #define CMIC_CMCx_AXIIC_TM_CONTROL_2_OFFSET(x) (0x31858 + (0x1000 * x)) 4424 #define CMIC_CMC0_CCMDMA_TM_CONTROL_0_OFFSET (0x31848) 4425 #define CMIC_CMC1_CCMDMA_TM_CONTROL_0_OFFSET (0x32848) 4426 #define CMIC_CMC2_CCMDMA_TM_CONTROL_0_OFFSET (0x33848) 4427 #define CMIC_CMCx_CCMDMA_TM_CONTROL_0_OFFSET(x) (0x31848 + (0x1000 * x)) 4428 #define CMIC_CMC0_CCMDMA_TM_CONTROL_1_OFFSET (0x3184c) 4429 #define CMIC_CMC1_CCMDMA_TM_CONTROL_1_OFFSET (0x3284c) 4430 #define CMIC_CMC2_CCMDMA_TM_CONTROL_1_OFFSET (0x3384c) 4431 #define CMIC_CMCx_CCMDMA_TM_CONTROL_1_OFFSET(x) (0x3184c + (0x1000 * x)) 4432 #define CMIC_CMC0_CCM_DMA_CFG_OFFSET (0x313ac) 4433 #define CMIC_CMC1_CCM_DMA_CFG_OFFSET (0x323ac) 4434 #define CMIC_CMC2_CCM_DMA_CFG_OFFSET (0x333ac) 4435 #define CMIC_CMCx_CCM_DMA_CFG_OFFSET(x) (0x313ac + (0x1000 * x)) 4436 #define CMIC_CMC0_CCM_DMA_CUR_HOST0_ADDR_OFFSET (0x313b4) 4437 #define CMIC_CMC1_CCM_DMA_CUR_HOST0_ADDR_OFFSET (0x323b4) 4438 #define CMIC_CMC2_CCM_DMA_CUR_HOST0_ADDR_OFFSET (0x333b4) 4439 #define CMIC_CMCx_CCM_DMA_CUR_HOST0_ADDR_OFFSET(x) (0x313b4 + (0x1000 * x)) 4440 #define CMIC_CMC0_CCM_DMA_CUR_HOST1_ADDR_OFFSET (0x313b8) 4441 #define CMIC_CMC1_CCM_DMA_CUR_HOST1_ADDR_OFFSET (0x323b8) 4442 #define CMIC_CMC2_CCM_DMA_CUR_HOST1_ADDR_OFFSET (0x333b8) 4443 #define CMIC_CMCx_CCM_DMA_CUR_HOST1_ADDR_OFFSET(x) (0x313b8 + (0x1000 * x)) 4444 #define CMIC_CMC0_CCM_DMA_ECCERR_ADDR_OFFSET (0x313bc) 4445 #define CMIC_CMC1_CCM_DMA_ECCERR_ADDR_OFFSET (0x323bc) 4446 #define CMIC_CMC2_CCM_DMA_ECCERR_ADDR_OFFSET (0x333bc) 4447 #define CMIC_CMCx_CCM_DMA_ECCERR_ADDR_OFFSET(x) (0x313bc + (0x1000 * x)) 4448 #define CMIC_CMC0_CCM_DMA_ECCERR_CONTROL_OFFSET (0x313c4) 4449 #define CMIC_CMC1_CCM_DMA_ECCERR_CONTROL_OFFSET (0x323c4) 4450 #define CMIC_CMC2_CCM_DMA_ECCERR_CONTROL_OFFSET (0x333c4) 4451 #define CMIC_CMCx_CCM_DMA_ECCERR_CONTROL_OFFSET(x) (0x313c4 + (0x1000 * x)) 4452 #define CMIC_CMC0_CCM_DMA_ENTRY_COUNT_OFFSET (0x313a8) 4453 #define CMIC_CMC1_CCM_DMA_ENTRY_COUNT_OFFSET (0x323a8) 4454 #define CMIC_CMC2_CCM_DMA_ENTRY_COUNT_OFFSET (0x333a8) 4455 #define CMIC_CMCx_CCM_DMA_ENTRY_COUNT_OFFSET(x) (0x313a8 + (0x1000 * x)) 4456 #define CMIC_CMC0_CCM_DMA_HOST0_MEM_START_ADDR_OFFSET (0x313a0) 4457 #define CMIC_CMC1_CCM_DMA_HOST0_MEM_START_ADDR_OFFSET (0x323a0) 4458 #define CMIC_CMC2_CCM_DMA_HOST0_MEM_START_ADDR_OFFSET (0x333a0) 4459 #define CMIC_CMCx_CCM_DMA_HOST0_MEM_START_ADDR_OFFSET(x) (0x313a0 + (0x1000 * x)) 4460 #define CMIC_CMC0_CCM_DMA_HOST1_MEM_START_ADDR_OFFSET (0x313a4) 4461 #define CMIC_CMC1_CCM_DMA_HOST1_MEM_START_ADDR_OFFSET (0x323a4) 4462 #define CMIC_CMC2_CCM_DMA_HOST1_MEM_START_ADDR_OFFSET (0x333a4) 4463 #define CMIC_CMCx_CCM_DMA_HOST1_MEM_START_ADDR_OFFSET(x) (0x313a4 + (0x1000 * x)) 4464 #define CMIC_CMC0_CCM_DMA_STAT_OFFSET (0x313b0) 4465 #define CMIC_CMC1_CCM_DMA_STAT_OFFSET (0x323b0) 4466 #define CMIC_CMC2_CCM_DMA_STAT_OFFSET (0x333b0) 4467 #define CMIC_CMCx_CCM_DMA_STAT_OFFSET(x) (0x313b0 + (0x1000 * x)) 4468 #define CMIC_CMC0_CCM_DMA_STATUS_CLR_OFFSET (0x313c0) 4469 #define CMIC_CMC1_CCM_DMA_STATUS_CLR_OFFSET (0x323c0) 4470 #define CMIC_CMC2_CCM_DMA_STATUS_CLR_OFFSET (0x333c0) 4471 #define CMIC_CMCx_CCM_DMA_STATUS_CLR_OFFSET(x) (0x313c0 + (0x1000 * x)) 4472 #define CMIC_CMC0_CH0_COS_CTRL_RX_0_OFFSET (0x31168) 4473 #define CMIC_CMC1_CH0_COS_CTRL_RX_0_OFFSET (0x32168) 4474 #define CMIC_CMC2_CH0_COS_CTRL_RX_0_OFFSET (0x33168) 4475 #define CMIC_CMCx_CH0_COS_CTRL_RX_0_OFFSET(x) (0x31168 + (0x1000 * x)) 4476 #define CMIC_CMC0_CH0_COS_CTRL_RX_1_OFFSET (0x3116c) 4477 #define CMIC_CMC1_CH0_COS_CTRL_RX_1_OFFSET (0x3216c) 4478 #define CMIC_CMC2_CH0_COS_CTRL_RX_1_OFFSET (0x3316c) 4479 #define CMIC_CMCx_CH0_COS_CTRL_RX_1_OFFSET(x) (0x3116c + (0x1000 * x)) 4480 #define CMIC_CMC0_CH0_DMA_CTRL_OFFSET (0x31140) 4481 #define CMIC_CMC1_CH0_DMA_CTRL_OFFSET (0x32140) 4482 #define CMIC_CMC2_CH0_DMA_CTRL_OFFSET (0x33140) 4483 #define CMIC_CMCx_CH0_DMA_CTRL_OFFSET(x) (0x31140 + (0x1000 * x)) 4484 #define CMIC_CMC0_CH0_DMA_CURR_DESC_OFFSET (0x311a8) 4485 #define CMIC_CMC1_CH0_DMA_CURR_DESC_OFFSET (0x321a8) 4486 #define CMIC_CMC2_CH0_DMA_CURR_DESC_OFFSET (0x331a8) 4487 #define CMIC_CMCx_CH0_DMA_CURR_DESC_OFFSET(x) (0x311a8 + (0x1000 * x)) 4488 #define CMIC_CMC0_CH0_RXBUF_THRESHOLD_CONFIG_OFFSET (0x31110) 4489 #define CMIC_CMC1_CH0_RXBUF_THRESHOLD_CONFIG_OFFSET (0x32110) 4490 #define CMIC_CMC2_CH0_RXBUF_THRESHOLD_CONFIG_OFFSET (0x33110) 4491 #define CMIC_CMCx_CH0_RXBUF_THRESHOLD_CONFIG_OFFSET(x) (0x31110 + (0x1000 * x)) 4492 #define CMIC_CMC0_CH1_COS_CTRL_RX_0_OFFSET (0x31170) 4493 #define CMIC_CMC1_CH1_COS_CTRL_RX_0_OFFSET (0x32170) 4494 #define CMIC_CMC2_CH1_COS_CTRL_RX_0_OFFSET (0x33170) 4495 #define CMIC_CMCx_CH1_COS_CTRL_RX_0_OFFSET(x) (0x31170 + (0x1000 * x)) 4496 #define CMIC_CMC0_CH1_COS_CTRL_RX_1_OFFSET (0x31174) 4497 #define CMIC_CMC1_CH1_COS_CTRL_RX_1_OFFSET (0x32174) 4498 #define CMIC_CMC2_CH1_COS_CTRL_RX_1_OFFSET (0x33174) 4499 #define CMIC_CMCx_CH1_COS_CTRL_RX_1_OFFSET(x) (0x31174 + (0x1000 * x)) 4500 #define CMIC_CMC0_CH1_DMA_CTRL_OFFSET (0x31144) 4501 #define CMIC_CMC1_CH1_DMA_CTRL_OFFSET (0x32144) 4502 #define CMIC_CMC2_CH1_DMA_CTRL_OFFSET (0x33144) 4503 #define CMIC_CMCx_CH1_DMA_CTRL_OFFSET(x) (0x31144 + (0x1000 * x)) 4504 #define CMIC_CMC0_CH1_DMA_CURR_DESC_OFFSET (0x311ac) 4505 #define CMIC_CMC1_CH1_DMA_CURR_DESC_OFFSET (0x321ac) 4506 #define CMIC_CMC2_CH1_DMA_CURR_DESC_OFFSET (0x331ac) 4507 #define CMIC_CMCx_CH1_DMA_CURR_DESC_OFFSET(x) (0x311ac + (0x1000 * x)) 4508 #define CMIC_CMC0_CH1_RXBUF_THRESHOLD_CONFIG_OFFSET (0x31114) 4509 #define CMIC_CMC1_CH1_RXBUF_THRESHOLD_CONFIG_OFFSET (0x32114) 4510 #define CMIC_CMC2_CH1_RXBUF_THRESHOLD_CONFIG_OFFSET (0x33114) 4511 #define CMIC_CMCx_CH1_RXBUF_THRESHOLD_CONFIG_OFFSET(x) (0x31114 + (0x1000 * x)) 4512 #define CMIC_CMC0_CH2_COS_CTRL_RX_0_OFFSET (0x31178) 4513 #define CMIC_CMC1_CH2_COS_CTRL_RX_0_OFFSET (0x32178) 4514 #define CMIC_CMC2_CH2_COS_CTRL_RX_0_OFFSET (0x33178) 4515 #define CMIC_CMCx_CH2_COS_CTRL_RX_0_OFFSET(x) (0x31178 + (0x1000 * x)) 4516 #define CMIC_CMC0_CH2_COS_CTRL_RX_1_OFFSET (0x3117c) 4517 #define CMIC_CMC1_CH2_COS_CTRL_RX_1_OFFSET (0x3217c) 4518 #define CMIC_CMC2_CH2_COS_CTRL_RX_1_OFFSET (0x3317c) 4519 #define CMIC_CMCx_CH2_COS_CTRL_RX_1_OFFSET(x) (0x3117c + (0x1000 * x)) 4520 #define CMIC_CMC0_CH2_DMA_CTRL_OFFSET (0x31148) 4521 #define CMIC_CMC1_CH2_DMA_CTRL_OFFSET (0x32148) 4522 #define CMIC_CMC2_CH2_DMA_CTRL_OFFSET (0x33148) 4523 #define CMIC_CMCx_CH2_DMA_CTRL_OFFSET(x) (0x31148 + (0x1000 * x)) 4524 #define CMIC_CMC0_CH2_DMA_CURR_DESC_OFFSET (0x311b0) 4525 #define CMIC_CMC1_CH2_DMA_CURR_DESC_OFFSET (0x321b0) 4526 #define CMIC_CMC2_CH2_DMA_CURR_DESC_OFFSET (0x331b0) 4527 #define CMIC_CMCx_CH2_DMA_CURR_DESC_OFFSET(x) (0x311b0 + (0x1000 * x)) 4528 #define CMIC_CMC0_CH2_RXBUF_THRESHOLD_CONFIG_OFFSET (0x31118) 4529 #define CMIC_CMC1_CH2_RXBUF_THRESHOLD_CONFIG_OFFSET (0x32118) 4530 #define CMIC_CMC2_CH2_RXBUF_THRESHOLD_CONFIG_OFFSET (0x33118) 4531 #define CMIC_CMCx_CH2_RXBUF_THRESHOLD_CONFIG_OFFSET(x) (0x31118 + (0x1000 * x)) 4532 #define CMIC_CMC0_CH3_COS_CTRL_RX_0_OFFSET (0x31180) 4533 #define CMIC_CMC1_CH3_COS_CTRL_RX_0_OFFSET (0x32180) 4534 #define CMIC_CMC2_CH3_COS_CTRL_RX_0_OFFSET (0x33180) 4535 #define CMIC_CMCx_CH3_COS_CTRL_RX_0_OFFSET(x) (0x31180 + (0x1000 * x)) 4536 #define CMIC_CMC0_CH3_COS_CTRL_RX_1_OFFSET (0x31184) 4537 #define CMIC_CMC1_CH3_COS_CTRL_RX_1_OFFSET (0x32184) 4538 #define CMIC_CMC2_CH3_COS_CTRL_RX_1_OFFSET (0x33184) 4539 #define CMIC_CMCx_CH3_COS_CTRL_RX_1_OFFSET(x) (0x31184 + (0x1000 * x)) 4540 #define CMIC_CMC0_CH3_DMA_CTRL_OFFSET (0x3114c) 4541 #define CMIC_CMC1_CH3_DMA_CTRL_OFFSET (0x3214c) 4542 #define CMIC_CMC2_CH3_DMA_CTRL_OFFSET (0x3314c) 4543 #define CMIC_CMCx_CH3_DMA_CTRL_OFFSET(x) (0x3114c + (0x1000 * x)) 4544 #define CMIC_CMC0_CH3_DMA_CURR_DESC_OFFSET (0x311b4) 4545 #define CMIC_CMC1_CH3_DMA_CURR_DESC_OFFSET (0x321b4) 4546 #define CMIC_CMC2_CH3_DMA_CURR_DESC_OFFSET (0x331b4) 4547 #define CMIC_CMCx_CH3_DMA_CURR_DESC_OFFSET(x) (0x311b4 + (0x1000 * x)) 4548 #define CMIC_CMC0_CH3_RXBUF_THRESHOLD_CONFIG_OFFSET (0x3111c) 4549 #define CMIC_CMC1_CH3_RXBUF_THRESHOLD_CONFIG_OFFSET (0x3211c) 4550 #define CMIC_CMC2_CH3_RXBUF_THRESHOLD_CONFIG_OFFSET (0x3311c) 4551 #define CMIC_CMCx_CH3_RXBUF_THRESHOLD_CONFIG_OFFSET(x) (0x3111c + (0x1000 * x)) 4552 #define CMIC_CMC0_CONFIG_OFFSET (0x31108) 4553 #define CMIC_CMC1_CONFIG_OFFSET (0x32108) 4554 #define CMIC_CMC2_CONFIG_OFFSET (0x33108) 4555 #define CMIC_CMCx_CONFIG_OFFSET(x) (0x31108 + (0x1000 * x)) 4556 #define CMIC_CMC0_DMA_CH0_DESC_HALT_ADDR_OFFSET (0x31120) 4557 #define CMIC_CMC1_DMA_CH0_DESC_HALT_ADDR_OFFSET (0x32120) 4558 #define CMIC_CMC2_DMA_CH0_DESC_HALT_ADDR_OFFSET (0x33120) 4559 #define CMIC_CMCx_DMA_CH0_DESC_HALT_ADDR_OFFSET(x) (0x31120 + (0x1000 * x)) 4560 #define CMIC_CMC0_DMA_CH0_INTR_COAL_OFFSET (0x31188) 4561 #define CMIC_CMC1_DMA_CH0_INTR_COAL_OFFSET (0x32188) 4562 #define CMIC_CMC2_DMA_CH0_INTR_COAL_OFFSET (0x33188) 4563 #define CMIC_CMCx_DMA_CH0_INTR_COAL_OFFSET(x) (0x31188 + (0x1000 * x)) 4564 #define CMIC_CMC0_DMA_CH1_DESC_HALT_ADDR_OFFSET (0x31124) 4565 #define CMIC_CMC1_DMA_CH1_DESC_HALT_ADDR_OFFSET (0x32124) 4566 #define CMIC_CMC2_DMA_CH1_DESC_HALT_ADDR_OFFSET (0x33124) 4567 #define CMIC_CMCx_DMA_CH1_DESC_HALT_ADDR_OFFSET(x) (0x31124 + (0x1000 * x)) 4568 #define CMIC_CMC0_DMA_CH1_INTR_COAL_OFFSET (0x3118c) 4569 #define CMIC_CMC1_DMA_CH1_INTR_COAL_OFFSET (0x3218c) 4570 #define CMIC_CMC2_DMA_CH1_INTR_COAL_OFFSET (0x3318c) 4571 #define CMIC_CMCx_DMA_CH1_INTR_COAL_OFFSET(x) (0x3118c + (0x1000 * x)) 4572 #define CMIC_CMC0_DMA_CH2_DESC_HALT_ADDR_OFFSET (0x31128) 4573 #define CMIC_CMC1_DMA_CH2_DESC_HALT_ADDR_OFFSET (0x32128) 4574 #define CMIC_CMC2_DMA_CH2_DESC_HALT_ADDR_OFFSET (0x33128) 4575 #define CMIC_CMCx_DMA_CH2_DESC_HALT_ADDR_OFFSET(x) (0x31128 + (0x1000 * x)) 4576 #define CMIC_CMC0_DMA_CH2_INTR_COAL_OFFSET (0x31190) 4577 #define CMIC_CMC1_DMA_CH2_INTR_COAL_OFFSET (0x32190) 4578 #define CMIC_CMC2_DMA_CH2_INTR_COAL_OFFSET (0x33190) 4579 #define CMIC_CMCx_DMA_CH2_INTR_COAL_OFFSET(x) (0x31190 + (0x1000 * x)) 4580 #define CMIC_CMC0_DMA_CH3_DESC_HALT_ADDR_OFFSET (0x3112c) 4581 #define CMIC_CMC1_DMA_CH3_DESC_HALT_ADDR_OFFSET (0x3212c) 4582 #define CMIC_CMC2_DMA_CH3_DESC_HALT_ADDR_OFFSET (0x3312c) 4583 #define CMIC_CMCx_DMA_CH3_DESC_HALT_ADDR_OFFSET(x) (0x3112c + (0x1000 * x)) 4584 #define CMIC_CMC0_DMA_CH3_INTR_COAL_OFFSET (0x31194) 4585 #define CMIC_CMC1_DMA_CH3_INTR_COAL_OFFSET (0x32194) 4586 #define CMIC_CMC2_DMA_CH3_INTR_COAL_OFFSET (0x33194) 4587 #define CMIC_CMCx_DMA_CH3_INTR_COAL_OFFSET(x) (0x31194 + (0x1000 * x)) 4588 #define CMIC_CMC0_DMA_DESC0_OFFSET (0x31158) 4589 #define CMIC_CMC1_DMA_DESC0_OFFSET (0x32158) 4590 #define CMIC_CMC2_DMA_DESC0_OFFSET (0x33158) 4591 #define CMIC_CMCx_DMA_DESC0_OFFSET(x) (0x31158 + (0x1000 * x)) 4592 #define CMIC_CMC0_DMA_DESC1_OFFSET (0x3115c) 4593 #define CMIC_CMC1_DMA_DESC1_OFFSET (0x3215c) 4594 #define CMIC_CMC2_DMA_DESC1_OFFSET (0x3315c) 4595 #define CMIC_CMCx_DMA_DESC1_OFFSET(x) (0x3115c + (0x1000 * x)) 4596 #define CMIC_CMC0_DMA_DESC2_OFFSET (0x31160) 4597 #define CMIC_CMC1_DMA_DESC2_OFFSET (0x32160) 4598 #define CMIC_CMC2_DMA_DESC2_OFFSET (0x33160) 4599 #define CMIC_CMCx_DMA_DESC2_OFFSET(x) (0x31160 + (0x1000 * x)) 4600 #define CMIC_CMC0_DMA_DESC3_OFFSET (0x31164) 4601 #define CMIC_CMC1_DMA_DESC3_OFFSET (0x32164) 4602 #define CMIC_CMC2_DMA_DESC3_OFFSET (0x33164) 4603 #define CMIC_CMCx_DMA_DESC3_OFFSET(x) (0x31164 + (0x1000 * x)) 4604 #define CMIC_CMC0_DMA_STAT_OFFSET (0x31150) 4605 #define CMIC_CMC1_DMA_STAT_OFFSET (0x32150) 4606 #define CMIC_CMC2_DMA_STAT_OFFSET (0x33150) 4607 #define CMIC_CMCx_DMA_STAT_OFFSET(x) (0x31150 + (0x1000 * x)) 4608 #define CMIC_CMC0_DMA_STAT_CLR_OFFSET (0x311a4) 4609 #define CMIC_CMC1_DMA_STAT_CLR_OFFSET (0x321a4) 4610 #define CMIC_CMC2_DMA_STAT_CLR_OFFSET (0x331a4) 4611 #define CMIC_CMCx_DMA_STAT_CLR_OFFSET(x) (0x311a4 + (0x1000 * x)) 4612 #define CMIC_CMC0_DMA_STAT_HI_OFFSET (0x31130) 4613 #define CMIC_CMC1_DMA_STAT_HI_OFFSET (0x32130) 4614 #define CMIC_CMC2_DMA_STAT_HI_OFFSET (0x33130) 4615 #define CMIC_CMCx_DMA_STAT_HI_OFFSET(x) (0x31130 + (0x1000 * x)) 4616 #define CMIC_CMC0_FIFORDDMA_CH0_TM_CONTROL_0_OFFSET (0x31828) 4617 #define CMIC_CMC1_FIFORDDMA_CH0_TM_CONTROL_0_OFFSET (0x32828) 4618 #define CMIC_CMC2_FIFORDDMA_CH0_TM_CONTROL_0_OFFSET (0x33828) 4619 #define CMIC_CMCx_FIFORDDMA_CH0_TM_CONTROL_0_OFFSET(x) (0x31828 + (0x1000 * x)) 4620 #define CMIC_CMC0_FIFORDDMA_CH0_TM_CONTROL_1_OFFSET (0x3182c) 4621 #define CMIC_CMC1_FIFORDDMA_CH0_TM_CONTROL_1_OFFSET (0x3282c) 4622 #define CMIC_CMC2_FIFORDDMA_CH0_TM_CONTROL_1_OFFSET (0x3382c) 4623 #define CMIC_CMCx_FIFORDDMA_CH0_TM_CONTROL_1_OFFSET(x) (0x3182c + (0x1000 * x)) 4624 #define CMIC_CMC0_FIFORDDMA_CH1_TM_CONTROL_0_OFFSET (0x31830) 4625 #define CMIC_CMC1_FIFORDDMA_CH1_TM_CONTROL_0_OFFSET (0x32830) 4626 #define CMIC_CMC2_FIFORDDMA_CH1_TM_CONTROL_0_OFFSET (0x33830) 4627 #define CMIC_CMCx_FIFORDDMA_CH1_TM_CONTROL_0_OFFSET(x) (0x31830 + (0x1000 * x)) 4628 #define CMIC_CMC0_FIFORDDMA_CH1_TM_CONTROL_1_OFFSET (0x31834) 4629 #define CMIC_CMC1_FIFORDDMA_CH1_TM_CONTROL_1_OFFSET (0x32834) 4630 #define CMIC_CMC2_FIFORDDMA_CH1_TM_CONTROL_1_OFFSET (0x33834) 4631 #define CMIC_CMCx_FIFORDDMA_CH1_TM_CONTROL_1_OFFSET(x) (0x31834 + (0x1000 * x)) 4632 #define CMIC_CMC0_FIFORDDMA_CH2_TM_CONTROL_0_OFFSET (0x31838) 4633 #define CMIC_CMC1_FIFORDDMA_CH2_TM_CONTROL_0_OFFSET (0x32838) 4634 #define CMIC_CMC2_FIFORDDMA_CH2_TM_CONTROL_0_OFFSET (0x33838) 4635 #define CMIC_CMCx_FIFORDDMA_CH2_TM_CONTROL_0_OFFSET(x) (0x31838 + (0x1000 * x)) 4636 #define CMIC_CMC0_FIFORDDMA_CH2_TM_CONTROL_1_OFFSET (0x3183c) 4637 #define CMIC_CMC1_FIFORDDMA_CH2_TM_CONTROL_1_OFFSET (0x3283c) 4638 #define CMIC_CMC2_FIFORDDMA_CH2_TM_CONTROL_1_OFFSET (0x3383c) 4639 #define CMIC_CMCx_FIFORDDMA_CH2_TM_CONTROL_1_OFFSET(x) (0x3183c + (0x1000 * x)) 4640 #define CMIC_CMC0_FIFORDDMA_CH3_TM_CONTROL_0_OFFSET (0x31840) 4641 #define CMIC_CMC1_FIFORDDMA_CH3_TM_CONTROL_0_OFFSET (0x32840) 4642 #define CMIC_CMC2_FIFORDDMA_CH3_TM_CONTROL_0_OFFSET (0x33840) 4643 #define CMIC_CMCx_FIFORDDMA_CH3_TM_CONTROL_0_OFFSET(x) (0x31840 + (0x1000 * x)) 4644 #define CMIC_CMC0_FIFORDDMA_CH3_TM_CONTROL_1_OFFSET (0x31844) 4645 #define CMIC_CMC1_FIFORDDMA_CH3_TM_CONTROL_1_OFFSET (0x32844) 4646 #define CMIC_CMC2_FIFORDDMA_CH3_TM_CONTROL_1_OFFSET (0x33844) 4647 #define CMIC_CMCx_FIFORDDMA_CH3_TM_CONTROL_1_OFFSET(x) (0x31844 + (0x1000 * x)) 4648 #define CMIC_CMC0_FIFO_CH0_RD_DMA_CFG_OFFSET (0x312c0) 4649 #define CMIC_CMC1_FIFO_CH0_RD_DMA_CFG_OFFSET (0x322c0) 4650 #define CMIC_CMC2_FIFO_CH0_RD_DMA_CFG_OFFSET (0x332c0) 4651 #define CMIC_CMCx_FIFO_CH0_RD_DMA_CFG_OFFSET(x) (0x312c0 + (0x1000 * x)) 4652 #define CMIC_CMC0_FIFO_CH0_RD_DMA_CUR_HOSTMEM_WRITE_PTR_OFFSET (0x31330) 4653 #define CMIC_CMC1_FIFO_CH0_RD_DMA_CUR_HOSTMEM_WRITE_PTR_OFFSET (0x32330) 4654 #define CMIC_CMC2_FIFO_CH0_RD_DMA_CUR_HOSTMEM_WRITE_PTR_OFFSET (0x33330) 4655 #define CMIC_CMCx_FIFO_CH0_RD_DMA_CUR_HOSTMEM_WRITE_PTR_OFFSET(x) (0x31330 + (0x1000 * x)) 4656 #define CMIC_CMC0_FIFO_CH0_RD_DMA_ECCERR_ADDRESS_OFFSET (0x31310) 4657 #define CMIC_CMC1_FIFO_CH0_RD_DMA_ECCERR_ADDRESS_OFFSET (0x32310) 4658 #define CMIC_CMC2_FIFO_CH0_RD_DMA_ECCERR_ADDRESS_OFFSET (0x33310) 4659 #define CMIC_CMCx_FIFO_CH0_RD_DMA_ECCERR_ADDRESS_OFFSET(x) (0x31310 + (0x1000 * x)) 4660 #define CMIC_CMC0_FIFO_CH0_RD_DMA_ECCERR_CONTROL_OFFSET (0x31320) 4661 #define CMIC_CMC1_FIFO_CH0_RD_DMA_ECCERR_CONTROL_OFFSET (0x32320) 4662 #define CMIC_CMC2_FIFO_CH0_RD_DMA_ECCERR_CONTROL_OFFSET (0x33320) 4663 #define CMIC_CMCx_FIFO_CH0_RD_DMA_ECCERR_CONTROL_OFFSET(x) (0x31320 + (0x1000 * x)) 4664 #define CMIC_CMC0_FIFO_CH0_RD_DMA_HOSTMEM_READ_PTR_OFFSET (0x312f0) 4665 #define CMIC_CMC1_FIFO_CH0_RD_DMA_HOSTMEM_READ_PTR_OFFSET (0x322f0) 4666 #define CMIC_CMC2_FIFO_CH0_RD_DMA_HOSTMEM_READ_PTR_OFFSET (0x332f0) 4667 #define CMIC_CMCx_FIFO_CH0_RD_DMA_HOSTMEM_READ_PTR_OFFSET(x) (0x312f0 + (0x1000 * x)) 4668 #define CMIC_CMC0_FIFO_CH0_RD_DMA_HOSTMEM_START_ADDRESS_OFFSET (0x312e0) 4669 #define CMIC_CMC1_FIFO_CH0_RD_DMA_HOSTMEM_START_ADDRESS_OFFSET (0x322e0) 4670 #define CMIC_CMC2_FIFO_CH0_RD_DMA_HOSTMEM_START_ADDRESS_OFFSET (0x332e0) 4671 #define CMIC_CMCx_FIFO_CH0_RD_DMA_HOSTMEM_START_ADDRESS_OFFSET(x) (0x312e0 + (0x1000 * x)) 4672 #define CMIC_CMC0_FIFO_CH0_RD_DMA_HOSTMEM_THRESHOLD_OFFSET (0x31354) 4673 #define CMIC_CMC1_FIFO_CH0_RD_DMA_HOSTMEM_THRESHOLD_OFFSET (0x32354) 4674 #define CMIC_CMC2_FIFO_CH0_RD_DMA_HOSTMEM_THRESHOLD_OFFSET (0x33354) 4675 #define CMIC_CMCx_FIFO_CH0_RD_DMA_HOSTMEM_THRESHOLD_OFFSET(x) (0x31354 + (0x1000 * x)) 4676 #define CMIC_CMC0_FIFO_CH0_RD_DMA_HOSTMEM_WRITE_PTR_OFFSET (0x312f4) 4677 #define CMIC_CMC1_FIFO_CH0_RD_DMA_HOSTMEM_WRITE_PTR_OFFSET (0x322f4) 4678 #define CMIC_CMC2_FIFO_CH0_RD_DMA_HOSTMEM_WRITE_PTR_OFFSET (0x332f4) 4679 #define CMIC_CMCx_FIFO_CH0_RD_DMA_HOSTMEM_WRITE_PTR_OFFSET(x) (0x312f4 + (0x1000 * x)) 4680 #define CMIC_CMC0_FIFO_CH0_RD_DMA_NUM_OF_ENTRIES_READ_FRM_HOSTMEM_OFFSET (0x312f0) 4681 #define CMIC_CMC1_FIFO_CH0_RD_DMA_NUM_OF_ENTRIES_READ_FRM_HOSTMEM_OFFSET (0x322f0) 4682 #define CMIC_CMC2_FIFO_CH0_RD_DMA_NUM_OF_ENTRIES_READ_FRM_HOSTMEM_OFFSET (0x332f0) 4683 #define CMIC_CMCx_FIFO_CH0_RD_DMA_NUM_OF_ENTRIES_READ_FRM_HOSTMEM_OFFSET(x) (0x312f0 + (0x1000 * x)) 4684 #define CMIC_CMC0_FIFO_CH0_RD_DMA_NUM_OF_ENTRIES_VALID_IN_HOSTMEM_OFFSET (0x312f4) 4685 #define CMIC_CMC1_FIFO_CH0_RD_DMA_NUM_OF_ENTRIES_VALID_IN_HOSTMEM_OFFSET (0x322f4) 4686 #define CMIC_CMC2_FIFO_CH0_RD_DMA_NUM_OF_ENTRIES_VALID_IN_HOSTMEM_OFFSET (0x332f4) 4687 #define CMIC_CMCx_FIFO_CH0_RD_DMA_NUM_OF_ENTRIES_VALID_IN_HOSTMEM_OFFSET(x) (0x312f4 + (0x1000 * x)) 4688 #define CMIC_CMC0_FIFO_CH0_RD_DMA_OPCODE_OFFSET (0x31384) 4689 #define CMIC_CMC1_FIFO_CH0_RD_DMA_OPCODE_OFFSET (0x32384) 4690 #define CMIC_CMC2_FIFO_CH0_RD_DMA_OPCODE_OFFSET (0x33384) 4691 #define CMIC_CMCx_FIFO_CH0_RD_DMA_OPCODE_OFFSET(x) (0x31384 + (0x1000 * x)) 4692 #define CMIC_CMC0_FIFO_CH0_RD_DMA_SBUS_CMD_CONFIG_OFFSET (0x31384) 4693 #define CMIC_CMC1_FIFO_CH0_RD_DMA_SBUS_CMD_CONFIG_OFFSET (0x32384) 4694 #define CMIC_CMC2_FIFO_CH0_RD_DMA_SBUS_CMD_CONFIG_OFFSET (0x33384) 4695 #define CMIC_CMCx_FIFO_CH0_RD_DMA_SBUS_CMD_CONFIG_OFFSET(x) (0x31384 + (0x1000 * x)) 4696 #define CMIC_CMC0_FIFO_CH0_RD_DMA_SBUS_START_ADDRESS_OFFSET (0x312d0) 4697 #define CMIC_CMC1_FIFO_CH0_RD_DMA_SBUS_START_ADDRESS_OFFSET (0x322d0) 4698 #define CMIC_CMC2_FIFO_CH0_RD_DMA_SBUS_START_ADDRESS_OFFSET (0x332d0) 4699 #define CMIC_CMCx_FIFO_CH0_RD_DMA_SBUS_START_ADDRESS_OFFSET(x) (0x312d0 + (0x1000 * x)) 4700 #define CMIC_CMC0_FIFO_CH0_RD_DMA_STAT_OFFSET (0x31364) 4701 #define CMIC_CMC1_FIFO_CH0_RD_DMA_STAT_OFFSET (0x32364) 4702 #define CMIC_CMC2_FIFO_CH0_RD_DMA_STAT_OFFSET (0x33364) 4703 #define CMIC_CMCx_FIFO_CH0_RD_DMA_STAT_OFFSET(x) (0x31364 + (0x1000 * x)) 4704 #define CMIC_CMC0_FIFO_CH0_RD_DMA_STAT_CLR_OFFSET (0x31374) 4705 #define CMIC_CMC1_FIFO_CH0_RD_DMA_STAT_CLR_OFFSET (0x32374) 4706 #define CMIC_CMC2_FIFO_CH0_RD_DMA_STAT_CLR_OFFSET (0x33374) 4707 #define CMIC_CMCx_FIFO_CH0_RD_DMA_STAT_CLR_OFFSET(x) (0x31374 + (0x1000 * x)) 4708 #define CMIC_CMC0_FIFO_CH1_RD_DMA_CFG_OFFSET (0x312c4) 4709 #define CMIC_CMC1_FIFO_CH1_RD_DMA_CFG_OFFSET (0x322c4) 4710 #define CMIC_CMC2_FIFO_CH1_RD_DMA_CFG_OFFSET (0x332c4) 4711 #define CMIC_CMCx_FIFO_CH1_RD_DMA_CFG_OFFSET(x) (0x312c4 + (0x1000 * x)) 4712 #define CMIC_CMC0_FIFO_CH1_RD_DMA_CUR_HOSTMEM_WRITE_PTR_OFFSET (0x31334) 4713 #define CMIC_CMC1_FIFO_CH1_RD_DMA_CUR_HOSTMEM_WRITE_PTR_OFFSET (0x32334) 4714 #define CMIC_CMC2_FIFO_CH1_RD_DMA_CUR_HOSTMEM_WRITE_PTR_OFFSET (0x33334) 4715 #define CMIC_CMCx_FIFO_CH1_RD_DMA_CUR_HOSTMEM_WRITE_PTR_OFFSET(x) (0x31334 + (0x1000 * x)) 4716 #define CMIC_CMC0_FIFO_CH1_RD_DMA_ECCERR_ADDRESS_OFFSET (0x31314) 4717 #define CMIC_CMC1_FIFO_CH1_RD_DMA_ECCERR_ADDRESS_OFFSET (0x32314) 4718 #define CMIC_CMC2_FIFO_CH1_RD_DMA_ECCERR_ADDRESS_OFFSET (0x33314) 4719 #define CMIC_CMCx_FIFO_CH1_RD_DMA_ECCERR_ADDRESS_OFFSET(x) (0x31314 + (0x1000 * x)) 4720 #define CMIC_CMC0_FIFO_CH1_RD_DMA_ECCERR_CONTROL_OFFSET (0x31324) 4721 #define CMIC_CMC1_FIFO_CH1_RD_DMA_ECCERR_CONTROL_OFFSET (0x32324) 4722 #define CMIC_CMC2_FIFO_CH1_RD_DMA_ECCERR_CONTROL_OFFSET (0x33324) 4723 #define CMIC_CMCx_FIFO_CH1_RD_DMA_ECCERR_CONTROL_OFFSET(x) (0x31324 + (0x1000 * x)) 4724 #define CMIC_CMC0_FIFO_CH1_RD_DMA_HOSTMEM_READ_PTR_OFFSET (0x312f8) 4725 #define CMIC_CMC1_FIFO_CH1_RD_DMA_HOSTMEM_READ_PTR_OFFSET (0x322f8) 4726 #define CMIC_CMC2_FIFO_CH1_RD_DMA_HOSTMEM_READ_PTR_OFFSET (0x332f8) 4727 #define CMIC_CMCx_FIFO_CH1_RD_DMA_HOSTMEM_READ_PTR_OFFSET(x) (0x312f8 + (0x1000 * x)) 4728 #define CMIC_CMC0_FIFO_CH1_RD_DMA_HOSTMEM_START_ADDRESS_OFFSET (0x312e4) 4729 #define CMIC_CMC1_FIFO_CH1_RD_DMA_HOSTMEM_START_ADDRESS_OFFSET (0x322e4) 4730 #define CMIC_CMC2_FIFO_CH1_RD_DMA_HOSTMEM_START_ADDRESS_OFFSET (0x332e4) 4731 #define CMIC_CMCx_FIFO_CH1_RD_DMA_HOSTMEM_START_ADDRESS_OFFSET(x) (0x312e4 + (0x1000 * x)) 4732 #define CMIC_CMC0_FIFO_CH1_RD_DMA_HOSTMEM_THRESHOLD_OFFSET (0x31358) 4733 #define CMIC_CMC1_FIFO_CH1_RD_DMA_HOSTMEM_THRESHOLD_OFFSET (0x32358) 4734 #define CMIC_CMC2_FIFO_CH1_RD_DMA_HOSTMEM_THRESHOLD_OFFSET (0x33358) 4735 #define CMIC_CMCx_FIFO_CH1_RD_DMA_HOSTMEM_THRESHOLD_OFFSET(x) (0x31358 + (0x1000 * x)) 4736 #define CMIC_CMC0_FIFO_CH1_RD_DMA_HOSTMEM_WRITE_PTR_OFFSET (0x312fc) 4737 #define CMIC_CMC1_FIFO_CH1_RD_DMA_HOSTMEM_WRITE_PTR_OFFSET (0x322fc) 4738 #define CMIC_CMC2_FIFO_CH1_RD_DMA_HOSTMEM_WRITE_PTR_OFFSET (0x332fc) 4739 #define CMIC_CMCx_FIFO_CH1_RD_DMA_HOSTMEM_WRITE_PTR_OFFSET(x) (0x312fc + (0x1000 * x)) 4740 #define CMIC_CMC0_FIFO_CH1_RD_DMA_NUM_OF_ENTRIES_READ_FRM_HOSTMEM_OFFSET (0x312f8) 4741 #define CMIC_CMC1_FIFO_CH1_RD_DMA_NUM_OF_ENTRIES_READ_FRM_HOSTMEM_OFFSET (0x322f8) 4742 #define CMIC_CMC2_FIFO_CH1_RD_DMA_NUM_OF_ENTRIES_READ_FRM_HOSTMEM_OFFSET (0x332f8) 4743 #define CMIC_CMCx_FIFO_CH1_RD_DMA_NUM_OF_ENTRIES_READ_FRM_HOSTMEM_OFFSET(x) (0x312f8 + (0x1000 * x)) 4744 #define CMIC_CMC0_FIFO_CH1_RD_DMA_NUM_OF_ENTRIES_VALID_IN_HOSTMEM_OFFSET (0x312fc) 4745 #define CMIC_CMC1_FIFO_CH1_RD_DMA_NUM_OF_ENTRIES_VALID_IN_HOSTMEM_OFFSET (0x322fc) 4746 #define CMIC_CMC2_FIFO_CH1_RD_DMA_NUM_OF_ENTRIES_VALID_IN_HOSTMEM_OFFSET (0x332fc) 4747 #define CMIC_CMCx_FIFO_CH1_RD_DMA_NUM_OF_ENTRIES_VALID_IN_HOSTMEM_OFFSET(x) (0x312fc + (0x1000 * x)) 4748 #define CMIC_CMC0_FIFO_CH1_RD_DMA_OPCODE_OFFSET (0x31388) 4749 #define CMIC_CMC1_FIFO_CH1_RD_DMA_OPCODE_OFFSET (0x32388) 4750 #define CMIC_CMC2_FIFO_CH1_RD_DMA_OPCODE_OFFSET (0x33388) 4751 #define CMIC_CMCx_FIFO_CH1_RD_DMA_OPCODE_OFFSET(x) (0x31388 + (0x1000 * x)) 4752 #define CMIC_CMC0_FIFO_CH1_RD_DMA_SBUS_CMD_CONFIG_OFFSET (0x31388) 4753 #define CMIC_CMC1_FIFO_CH1_RD_DMA_SBUS_CMD_CONFIG_OFFSET (0x32388) 4754 #define CMIC_CMC2_FIFO_CH1_RD_DMA_SBUS_CMD_CONFIG_OFFSET (0x33388) 4755 #define CMIC_CMCx_FIFO_CH1_RD_DMA_SBUS_CMD_CONFIG_OFFSET(x) (0x31388 + (0x1000 * x)) 4756 #define CMIC_CMC0_FIFO_CH1_RD_DMA_SBUS_START_ADDRESS_OFFSET (0x312d4) 4757 #define CMIC_CMC1_FIFO_CH1_RD_DMA_SBUS_START_ADDRESS_OFFSET (0x322d4) 4758 #define CMIC_CMC2_FIFO_CH1_RD_DMA_SBUS_START_ADDRESS_OFFSET (0x332d4) 4759 #define CMIC_CMCx_FIFO_CH1_RD_DMA_SBUS_START_ADDRESS_OFFSET(x) (0x312d4 + (0x1000 * x)) 4760 #define CMIC_CMC0_FIFO_CH1_RD_DMA_STAT_OFFSET (0x31368) 4761 #define CMIC_CMC1_FIFO_CH1_RD_DMA_STAT_OFFSET (0x32368) 4762 #define CMIC_CMC2_FIFO_CH1_RD_DMA_STAT_OFFSET (0x33368) 4763 #define CMIC_CMCx_FIFO_CH1_RD_DMA_STAT_OFFSET(x) (0x31368 + (0x1000 * x)) 4764 #define CMIC_CMC0_FIFO_CH1_RD_DMA_STAT_CLR_OFFSET (0x31378) 4765 #define CMIC_CMC1_FIFO_CH1_RD_DMA_STAT_CLR_OFFSET (0x32378) 4766 #define CMIC_CMC2_FIFO_CH1_RD_DMA_STAT_CLR_OFFSET (0x33378) 4767 #define CMIC_CMCx_FIFO_CH1_RD_DMA_STAT_CLR_OFFSET(x) (0x31378 + (0x1000 * x)) 4768 #define CMIC_CMC0_FIFO_CH2_RD_DMA_CFG_OFFSET (0x312c8) 4769 #define CMIC_CMC1_FIFO_CH2_RD_DMA_CFG_OFFSET (0x322c8) 4770 #define CMIC_CMC2_FIFO_CH2_RD_DMA_CFG_OFFSET (0x332c8) 4771 #define CMIC_CMCx_FIFO_CH2_RD_DMA_CFG_OFFSET(x) (0x312c8 + (0x1000 * x)) 4772 #define CMIC_CMC0_FIFO_CH2_RD_DMA_CUR_HOSTMEM_WRITE_PTR_OFFSET (0x31338) 4773 #define CMIC_CMC1_FIFO_CH2_RD_DMA_CUR_HOSTMEM_WRITE_PTR_OFFSET (0x32338) 4774 #define CMIC_CMC2_FIFO_CH2_RD_DMA_CUR_HOSTMEM_WRITE_PTR_OFFSET (0x33338) 4775 #define CMIC_CMCx_FIFO_CH2_RD_DMA_CUR_HOSTMEM_WRITE_PTR_OFFSET(x) (0x31338 + (0x1000 * x)) 4776 #define CMIC_CMC0_FIFO_CH2_RD_DMA_ECCERR_ADDRESS_OFFSET (0x31318) 4777 #define CMIC_CMC1_FIFO_CH2_RD_DMA_ECCERR_ADDRESS_OFFSET (0x32318) 4778 #define CMIC_CMC2_FIFO_CH2_RD_DMA_ECCERR_ADDRESS_OFFSET (0x33318) 4779 #define CMIC_CMCx_FIFO_CH2_RD_DMA_ECCERR_ADDRESS_OFFSET(x) (0x31318 + (0x1000 * x)) 4780 #define CMIC_CMC0_FIFO_CH2_RD_DMA_ECCERR_CONTROL_OFFSET (0x31328) 4781 #define CMIC_CMC1_FIFO_CH2_RD_DMA_ECCERR_CONTROL_OFFSET (0x32328) 4782 #define CMIC_CMC2_FIFO_CH2_RD_DMA_ECCERR_CONTROL_OFFSET (0x33328) 4783 #define CMIC_CMCx_FIFO_CH2_RD_DMA_ECCERR_CONTROL_OFFSET(x) (0x31328 + (0x1000 * x)) 4784 #define CMIC_CMC0_FIFO_CH2_RD_DMA_HOSTMEM_READ_PTR_OFFSET (0x31300) 4785 #define CMIC_CMC1_FIFO_CH2_RD_DMA_HOSTMEM_READ_PTR_OFFSET (0x32300) 4786 #define CMIC_CMC2_FIFO_CH2_RD_DMA_HOSTMEM_READ_PTR_OFFSET (0x33300) 4787 #define CMIC_CMCx_FIFO_CH2_RD_DMA_HOSTMEM_READ_PTR_OFFSET(x) (0x31300 + (0x1000 * x)) 4788 #define CMIC_CMC0_FIFO_CH2_RD_DMA_HOSTMEM_START_ADDRESS_OFFSET (0x312e8) 4789 #define CMIC_CMC1_FIFO_CH2_RD_DMA_HOSTMEM_START_ADDRESS_OFFSET (0x322e8) 4790 #define CMIC_CMC2_FIFO_CH2_RD_DMA_HOSTMEM_START_ADDRESS_OFFSET (0x332e8) 4791 #define CMIC_CMCx_FIFO_CH2_RD_DMA_HOSTMEM_START_ADDRESS_OFFSET(x) (0x312e8 + (0x1000 * x)) 4792 #define CMIC_CMC0_FIFO_CH2_RD_DMA_HOSTMEM_THRESHOLD_OFFSET (0x3135c) 4793 #define CMIC_CMC1_FIFO_CH2_RD_DMA_HOSTMEM_THRESHOLD_OFFSET (0x3235c) 4794 #define CMIC_CMC2_FIFO_CH2_RD_DMA_HOSTMEM_THRESHOLD_OFFSET (0x3335c) 4795 #define CMIC_CMCx_FIFO_CH2_RD_DMA_HOSTMEM_THRESHOLD_OFFSET(x) (0x3135c + (0x1000 * x)) 4796 #define CMIC_CMC0_FIFO_CH2_RD_DMA_HOSTMEM_WRITE_PTR_OFFSET (0x31304) 4797 #define CMIC_CMC1_FIFO_CH2_RD_DMA_HOSTMEM_WRITE_PTR_OFFSET (0x32304) 4798 #define CMIC_CMC2_FIFO_CH2_RD_DMA_HOSTMEM_WRITE_PTR_OFFSET (0x33304) 4799 #define CMIC_CMCx_FIFO_CH2_RD_DMA_HOSTMEM_WRITE_PTR_OFFSET(x) (0x31304 + (0x1000 * x)) 4800 #define CMIC_CMC0_FIFO_CH2_RD_DMA_NUM_OF_ENTRIES_READ_FRM_HOSTMEM_OFFSET (0x31300) 4801 #define CMIC_CMC1_FIFO_CH2_RD_DMA_NUM_OF_ENTRIES_READ_FRM_HOSTMEM_OFFSET (0x32300) 4802 #define CMIC_CMC2_FIFO_CH2_RD_DMA_NUM_OF_ENTRIES_READ_FRM_HOSTMEM_OFFSET (0x33300) 4803 #define CMIC_CMCx_FIFO_CH2_RD_DMA_NUM_OF_ENTRIES_READ_FRM_HOSTMEM_OFFSET(x) (0x31300 + (0x1000 * x)) 4804 #define CMIC_CMC0_FIFO_CH2_RD_DMA_NUM_OF_ENTRIES_VALID_IN_HOSTMEM_OFFSET (0x31304) 4805 #define CMIC_CMC1_FIFO_CH2_RD_DMA_NUM_OF_ENTRIES_VALID_IN_HOSTMEM_OFFSET (0x32304) 4806 #define CMIC_CMC2_FIFO_CH2_RD_DMA_NUM_OF_ENTRIES_VALID_IN_HOSTMEM_OFFSET (0x33304) 4807 #define CMIC_CMCx_FIFO_CH2_RD_DMA_NUM_OF_ENTRIES_VALID_IN_HOSTMEM_OFFSET(x) (0x31304 + (0x1000 * x)) 4808 #define CMIC_CMC0_FIFO_CH2_RD_DMA_OPCODE_OFFSET (0x3138c) 4809 #define CMIC_CMC1_FIFO_CH2_RD_DMA_OPCODE_OFFSET (0x3238c) 4810 #define CMIC_CMC2_FIFO_CH2_RD_DMA_OPCODE_OFFSET (0x3338c) 4811 #define CMIC_CMCx_FIFO_CH2_RD_DMA_OPCODE_OFFSET(x) (0x3138c + (0x1000 * x)) 4812 #define CMIC_CMC0_FIFO_CH2_RD_DMA_SBUS_CMD_CONFIG_OFFSET (0x3138c) 4813 #define CMIC_CMC1_FIFO_CH2_RD_DMA_SBUS_CMD_CONFIG_OFFSET (0x3238c) 4814 #define CMIC_CMC2_FIFO_CH2_RD_DMA_SBUS_CMD_CONFIG_OFFSET (0x3338c) 4815 #define CMIC_CMCx_FIFO_CH2_RD_DMA_SBUS_CMD_CONFIG_OFFSET(x) (0x3138c + (0x1000 * x)) 4816 #define CMIC_CMC0_FIFO_CH2_RD_DMA_SBUS_START_ADDRESS_OFFSET (0x312d8) 4817 #define CMIC_CMC1_FIFO_CH2_RD_DMA_SBUS_START_ADDRESS_OFFSET (0x322d8) 4818 #define CMIC_CMC2_FIFO_CH2_RD_DMA_SBUS_START_ADDRESS_OFFSET (0x332d8) 4819 #define CMIC_CMCx_FIFO_CH2_RD_DMA_SBUS_START_ADDRESS_OFFSET(x) (0x312d8 + (0x1000 * x)) 4820 #define CMIC_CMC0_FIFO_CH2_RD_DMA_STAT_OFFSET (0x3136c) 4821 #define CMIC_CMC1_FIFO_CH2_RD_DMA_STAT_OFFSET (0x3236c) 4822 #define CMIC_CMC2_FIFO_CH2_RD_DMA_STAT_OFFSET (0x3336c) 4823 #define CMIC_CMCx_FIFO_CH2_RD_DMA_STAT_OFFSET(x) (0x3136c + (0x1000 * x)) 4824 #define CMIC_CMC0_FIFO_CH2_RD_DMA_STAT_CLR_OFFSET (0x3137c) 4825 #define CMIC_CMC1_FIFO_CH2_RD_DMA_STAT_CLR_OFFSET (0x3237c) 4826 #define CMIC_CMC2_FIFO_CH2_RD_DMA_STAT_CLR_OFFSET (0x3337c) 4827 #define CMIC_CMCx_FIFO_CH2_RD_DMA_STAT_CLR_OFFSET(x) (0x3137c + (0x1000 * x)) 4828 #define CMIC_CMC0_FIFO_CH3_RD_DMA_CFG_OFFSET (0x312cc) 4829 #define CMIC_CMC1_FIFO_CH3_RD_DMA_CFG_OFFSET (0x322cc) 4830 #define CMIC_CMC2_FIFO_CH3_RD_DMA_CFG_OFFSET (0x332cc) 4831 #define CMIC_CMCx_FIFO_CH3_RD_DMA_CFG_OFFSET(x) (0x312cc + (0x1000 * x)) 4832 #define CMIC_CMC0_FIFO_CH3_RD_DMA_CUR_HOSTMEM_WRITE_PTR_OFFSET (0x3133c) 4833 #define CMIC_CMC1_FIFO_CH3_RD_DMA_CUR_HOSTMEM_WRITE_PTR_OFFSET (0x3233c) 4834 #define CMIC_CMC2_FIFO_CH3_RD_DMA_CUR_HOSTMEM_WRITE_PTR_OFFSET (0x3333c) 4835 #define CMIC_CMCx_FIFO_CH3_RD_DMA_CUR_HOSTMEM_WRITE_PTR_OFFSET(x) (0x3133c + (0x1000 * x)) 4836 #define CMIC_CMC0_FIFO_CH3_RD_DMA_ECCERR_ADDRESS_OFFSET (0x3131c) 4837 #define CMIC_CMC1_FIFO_CH3_RD_DMA_ECCERR_ADDRESS_OFFSET (0x3231c) 4838 #define CMIC_CMC2_FIFO_CH3_RD_DMA_ECCERR_ADDRESS_OFFSET (0x3331c) 4839 #define CMIC_CMCx_FIFO_CH3_RD_DMA_ECCERR_ADDRESS_OFFSET(x) (0x3131c + (0x1000 * x)) 4840 #define CMIC_CMC0_FIFO_CH3_RD_DMA_ECCERR_CONTROL_OFFSET (0x3132c) 4841 #define CMIC_CMC1_FIFO_CH3_RD_DMA_ECCERR_CONTROL_OFFSET (0x3232c) 4842 #define CMIC_CMC2_FIFO_CH3_RD_DMA_ECCERR_CONTROL_OFFSET (0x3332c) 4843 #define CMIC_CMCx_FIFO_CH3_RD_DMA_ECCERR_CONTROL_OFFSET(x) (0x3132c + (0x1000 * x)) 4844 #define CMIC_CMC0_FIFO_CH3_RD_DMA_HOSTMEM_READ_PTR_OFFSET (0x31308) 4845 #define CMIC_CMC1_FIFO_CH3_RD_DMA_HOSTMEM_READ_PTR_OFFSET (0x32308) 4846 #define CMIC_CMC2_FIFO_CH3_RD_DMA_HOSTMEM_READ_PTR_OFFSET (0x33308) 4847 #define CMIC_CMCx_FIFO_CH3_RD_DMA_HOSTMEM_READ_PTR_OFFSET(x) (0x31308 + (0x1000 * x)) 4848 #define CMIC_CMC0_FIFO_CH3_RD_DMA_HOSTMEM_START_ADDRESS_OFFSET (0x312ec) 4849 #define CMIC_CMC1_FIFO_CH3_RD_DMA_HOSTMEM_START_ADDRESS_OFFSET (0x322ec) 4850 #define CMIC_CMC2_FIFO_CH3_RD_DMA_HOSTMEM_START_ADDRESS_OFFSET (0x332ec) 4851 #define CMIC_CMCx_FIFO_CH3_RD_DMA_HOSTMEM_START_ADDRESS_OFFSET(x) (0x312ec + (0x1000 * x)) 4852 #define CMIC_CMC0_FIFO_CH3_RD_DMA_HOSTMEM_THRESHOLD_OFFSET (0x31360) 4853 #define CMIC_CMC1_FIFO_CH3_RD_DMA_HOSTMEM_THRESHOLD_OFFSET (0x32360) 4854 #define CMIC_CMC2_FIFO_CH3_RD_DMA_HOSTMEM_THRESHOLD_OFFSET (0x33360) 4855 #define CMIC_CMCx_FIFO_CH3_RD_DMA_HOSTMEM_THRESHOLD_OFFSET(x) (0x31360 + (0x1000 * x)) 4856 #define CMIC_CMC0_FIFO_CH3_RD_DMA_HOSTMEM_WRITE_PTR_OFFSET (0x3130c) 4857 #define CMIC_CMC1_FIFO_CH3_RD_DMA_HOSTMEM_WRITE_PTR_OFFSET (0x3230c) 4858 #define CMIC_CMC2_FIFO_CH3_RD_DMA_HOSTMEM_WRITE_PTR_OFFSET (0x3330c) 4859 #define CMIC_CMCx_FIFO_CH3_RD_DMA_HOSTMEM_WRITE_PTR_OFFSET(x) (0x3130c + (0x1000 * x)) 4860 #define CMIC_CMC0_FIFO_CH3_RD_DMA_NUM_OF_ENTRIES_READ_FRM_HOSTMEM_OFFSET (0x31308) 4861 #define CMIC_CMC1_FIFO_CH3_RD_DMA_NUM_OF_ENTRIES_READ_FRM_HOSTMEM_OFFSET (0x32308) 4862 #define CMIC_CMC2_FIFO_CH3_RD_DMA_NUM_OF_ENTRIES_READ_FRM_HOSTMEM_OFFSET (0x33308) 4863 #define CMIC_CMCx_FIFO_CH3_RD_DMA_NUM_OF_ENTRIES_READ_FRM_HOSTMEM_OFFSET(x) (0x31308 + (0x1000 * x)) 4864 #define CMIC_CMC0_FIFO_CH3_RD_DMA_NUM_OF_ENTRIES_VALID_IN_HOSTMEM_OFFSET (0x3130c) 4865 #define CMIC_CMC1_FIFO_CH3_RD_DMA_NUM_OF_ENTRIES_VALID_IN_HOSTMEM_OFFSET (0x3230c) 4866 #define CMIC_CMC2_FIFO_CH3_RD_DMA_NUM_OF_ENTRIES_VALID_IN_HOSTMEM_OFFSET (0x3330c) 4867 #define CMIC_CMCx_FIFO_CH3_RD_DMA_NUM_OF_ENTRIES_VALID_IN_HOSTMEM_OFFSET(x) (0x3130c + (0x1000 * x)) 4868 #define CMIC_CMC0_FIFO_CH3_RD_DMA_OPCODE_OFFSET (0x31390) 4869 #define CMIC_CMC1_FIFO_CH3_RD_DMA_OPCODE_OFFSET (0x32390) 4870 #define CMIC_CMC2_FIFO_CH3_RD_DMA_OPCODE_OFFSET (0x33390) 4871 #define CMIC_CMCx_FIFO_CH3_RD_DMA_OPCODE_OFFSET(x) (0x31390 + (0x1000 * x)) 4872 #define CMIC_CMC0_FIFO_CH3_RD_DMA_SBUS_CMD_CONFIG_OFFSET (0x31390) 4873 #define CMIC_CMC1_FIFO_CH3_RD_DMA_SBUS_CMD_CONFIG_OFFSET (0x32390) 4874 #define CMIC_CMC2_FIFO_CH3_RD_DMA_SBUS_CMD_CONFIG_OFFSET (0x33390) 4875 #define CMIC_CMCx_FIFO_CH3_RD_DMA_SBUS_CMD_CONFIG_OFFSET(x) (0x31390 + (0x1000 * x)) 4876 #define CMIC_CMC0_FIFO_CH3_RD_DMA_SBUS_START_ADDRESS_OFFSET (0x312dc) 4877 #define CMIC_CMC1_FIFO_CH3_RD_DMA_SBUS_START_ADDRESS_OFFSET (0x322dc) 4878 #define CMIC_CMC2_FIFO_CH3_RD_DMA_SBUS_START_ADDRESS_OFFSET (0x332dc) 4879 #define CMIC_CMCx_FIFO_CH3_RD_DMA_SBUS_START_ADDRESS_OFFSET(x) (0x312dc + (0x1000 * x)) 4880 #define CMIC_CMC0_FIFO_CH3_RD_DMA_STAT_OFFSET (0x31370) 4881 #define CMIC_CMC1_FIFO_CH3_RD_DMA_STAT_OFFSET (0x32370) 4882 #define CMIC_CMC2_FIFO_CH3_RD_DMA_STAT_OFFSET (0x33370) 4883 #define CMIC_CMCx_FIFO_CH3_RD_DMA_STAT_OFFSET(x) (0x31370 + (0x1000 * x)) 4884 #define CMIC_CMC0_FIFO_CH3_RD_DMA_STAT_CLR_OFFSET (0x31380) 4885 #define CMIC_CMC1_FIFO_CH3_RD_DMA_STAT_CLR_OFFSET (0x32380) 4886 #define CMIC_CMC2_FIFO_CH3_RD_DMA_STAT_CLR_OFFSET (0x33380) 4887 #define CMIC_CMCx_FIFO_CH3_RD_DMA_STAT_CLR_OFFSET(x) (0x31380 + (0x1000 * x)) 4888 #define CMIC_CMC0_FIFO_RD_DMA_DEBUG_OFFSET (0x31394) 4889 #define CMIC_CMC1_FIFO_RD_DMA_DEBUG_OFFSET (0x32394) 4890 #define CMIC_CMC2_FIFO_RD_DMA_DEBUG_OFFSET (0x33394) 4891 #define CMIC_CMCx_FIFO_RD_DMA_DEBUG_OFFSET(x) (0x31394 + (0x1000 * x)) 4892 #define CMIC_CMC0_FSCHAN_ADDRESS_OFFSET (0x31070) 4893 #define CMIC_CMC1_FSCHAN_ADDRESS_OFFSET (0x32070) 4894 #define CMIC_CMC2_FSCHAN_ADDRESS_OFFSET (0x33070) 4895 #define CMIC_CMCx_FSCHAN_ADDRESS_OFFSET(x) (0x31070 + (0x1000 * x)) 4896 #define CMIC_CMC0_FSCHAN_DATA32_OFFSET (0x31074) 4897 #define CMIC_CMC1_FSCHAN_DATA32_OFFSET (0x32074) 4898 #define CMIC_CMC2_FSCHAN_DATA32_OFFSET (0x33074) 4899 #define CMIC_CMCx_FSCHAN_DATA32_OFFSET(x) (0x31074 + (0x1000 * x)) 4900 #define CMIC_CMC0_FSCHAN_DATA64_HI_OFFSET (0x3107c) 4901 #define CMIC_CMC1_FSCHAN_DATA64_HI_OFFSET (0x3207c) 4902 #define CMIC_CMC2_FSCHAN_DATA64_HI_OFFSET (0x3307c) 4903 #define CMIC_CMCx_FSCHAN_DATA64_HI_OFFSET(x) (0x3107c + (0x1000 * x)) 4904 #define CMIC_CMC0_FSCHAN_DATA64_LO_OFFSET (0x31078) 4905 #define CMIC_CMC1_FSCHAN_DATA64_LO_OFFSET (0x32078) 4906 #define CMIC_CMC2_FSCHAN_DATA64_LO_OFFSET (0x33078) 4907 #define CMIC_CMCx_FSCHAN_DATA64_LO_OFFSET(x) (0x31078 + (0x1000 * x)) 4908 #define CMIC_CMC0_FSCHAN_ENABLE_PROGRAMMABLE_OPCODE_OFFSET (0x31064) 4909 #define CMIC_CMC1_FSCHAN_ENABLE_PROGRAMMABLE_OPCODE_OFFSET (0x32064) 4910 #define CMIC_CMC2_FSCHAN_ENABLE_PROGRAMMABLE_OPCODE_OFFSET (0x33064) 4911 #define CMIC_CMCx_FSCHAN_ENABLE_PROGRAMMABLE_OPCODE_OFFSET(x) (0x31064 + (0x1000 * x)) 4912 #define CMIC_CMC0_FSCHAN_OPCODE_OFFSET (0x3106c) 4913 #define CMIC_CMC1_FSCHAN_OPCODE_OFFSET (0x3206c) 4914 #define CMIC_CMC2_FSCHAN_OPCODE_OFFSET (0x3306c) 4915 #define CMIC_CMCx_FSCHAN_OPCODE_OFFSET(x) (0x3106c + (0x1000 * x)) 4916 #define CMIC_CMC0_FSCHAN_STATUS_OFFSET (0x31068) 4917 #define CMIC_CMC1_FSCHAN_STATUS_OFFSET (0x32068) 4918 #define CMIC_CMC2_FSCHAN_STATUS_OFFSET (0x33068) 4919 #define CMIC_CMCx_FSCHAN_STATUS_OFFSET(x) (0x31068 + (0x1000 * x)) 4920 #define CMIC_CMC0_HOSTMEM_ADDR_REMAP_0_OFFSET (0x31474) 4921 #define CMIC_CMC1_HOSTMEM_ADDR_REMAP_0_OFFSET (0x32474) 4922 #define CMIC_CMC2_HOSTMEM_ADDR_REMAP_0_OFFSET (0x33474) 4923 #define CMIC_CMCx_HOSTMEM_ADDR_REMAP_0_OFFSET(x) (0x31474 + (0x1000 * x)) 4924 #define CMIC_CMC0_HOSTMEM_ADDR_REMAP_1_OFFSET (0x31478) 4925 #define CMIC_CMC1_HOSTMEM_ADDR_REMAP_1_OFFSET (0x32478) 4926 #define CMIC_CMC2_HOSTMEM_ADDR_REMAP_1_OFFSET (0x33478) 4927 #define CMIC_CMCx_HOSTMEM_ADDR_REMAP_1_OFFSET(x) (0x31478 + (0x1000 * x)) 4928 #define CMIC_CMC0_HOSTMEM_ADDR_REMAP_2_OFFSET (0x3147c) 4929 #define CMIC_CMC1_HOSTMEM_ADDR_REMAP_2_OFFSET (0x3247c) 4930 #define CMIC_CMC2_HOSTMEM_ADDR_REMAP_2_OFFSET (0x3347c) 4931 #define CMIC_CMCx_HOSTMEM_ADDR_REMAP_2_OFFSET(x) (0x3147c + (0x1000 * x)) 4932 #define CMIC_CMC0_HOSTMEM_ADDR_REMAP_3_OFFSET (0x314ac) 4933 #define CMIC_CMC1_HOSTMEM_ADDR_REMAP_3_OFFSET (0x324ac) 4934 #define CMIC_CMC2_HOSTMEM_ADDR_REMAP_3_OFFSET (0x334ac) 4935 #define CMIC_CMCx_HOSTMEM_ADDR_REMAP_3_OFFSET(x) (0x314ac + (0x1000 * x)) 4936 #define CMIC_CMC0_IRQ_STAT0_OFFSET (0x31400) 4937 #define CMIC_CMC1_IRQ_STAT0_OFFSET (0x32400) 4938 #define CMIC_CMC2_IRQ_STAT0_OFFSET (0x33400) 4939 #define CMIC_CMCx_IRQ_STAT0_OFFSET(x) (0x31400 + (0x1000 * x)) 4940 #define CMIC_CMC0_IRQ_STAT1_OFFSET (0x31404) 4941 #define CMIC_CMC1_IRQ_STAT1_OFFSET (0x32404) 4942 #define CMIC_CMC2_IRQ_STAT1_OFFSET (0x33404) 4943 #define CMIC_CMCx_IRQ_STAT1_OFFSET(x) (0x31404 + (0x1000 * x)) 4944 #define CMIC_CMC0_IRQ_STAT2_OFFSET (0x31408) 4945 #define CMIC_CMC1_IRQ_STAT2_OFFSET (0x32408) 4946 #define CMIC_CMC2_IRQ_STAT2_OFFSET (0x33408) 4947 #define CMIC_CMCx_IRQ_STAT2_OFFSET(x) (0x31408 + (0x1000 * x)) 4948 #define CMIC_CMC0_IRQ_STAT3_OFFSET (0x3140c) 4949 #define CMIC_CMC1_IRQ_STAT3_OFFSET (0x3240c) 4950 #define CMIC_CMC2_IRQ_STAT3_OFFSET (0x3340c) 4951 #define CMIC_CMCx_IRQ_STAT3_OFFSET(x) (0x3140c + (0x1000 * x)) 4952 #define CMIC_CMC0_IRQ_STAT4_OFFSET (0x31410) 4953 #define CMIC_CMC1_IRQ_STAT4_OFFSET (0x32410) 4954 #define CMIC_CMC2_IRQ_STAT4_OFFSET (0x33410) 4955 #define CMIC_CMCx_IRQ_STAT4_OFFSET(x) (0x31410 + (0x1000 * x)) 4956 #define CMIC_CMC0_IRQ_STAT5_OFFSET (0x314b0) 4957 #define CMIC_CMC1_IRQ_STAT5_OFFSET (0x324b0) 4958 #define CMIC_CMC2_IRQ_STAT5_OFFSET (0x334b0) 4959 #define CMIC_CMCx_IRQ_STAT5_OFFSET(x) (0x314b0 + (0x1000 * x)) 4960 #define CMIC_CMC0_IRQ_STAT6_OFFSET (0x314b4) 4961 #define CMIC_CMC1_IRQ_STAT6_OFFSET (0x324b4) 4962 #define CMIC_CMC2_IRQ_STAT6_OFFSET (0x334b4) 4963 #define CMIC_CMCx_IRQ_STAT6_OFFSET(x) (0x314b4 + (0x1000 * x)) 4964 #define CMIC_CMC0_MIIM_ADDRESS_OFFSET (0x31088) 4965 #define CMIC_CMC1_MIIM_ADDRESS_OFFSET (0x32088) 4966 #define CMIC_CMC2_MIIM_ADDRESS_OFFSET (0x33088) 4967 #define CMIC_CMCx_MIIM_ADDRESS_OFFSET(x) (0x31088 + (0x1000 * x)) 4968 #define CMIC_CMC0_MIIM_CTRL_OFFSET (0x3108c) 4969 #define CMIC_CMC1_MIIM_CTRL_OFFSET (0x3208c) 4970 #define CMIC_CMC2_MIIM_CTRL_OFFSET (0x3308c) 4971 #define CMIC_CMCx_MIIM_CTRL_OFFSET(x) (0x3108c + (0x1000 * x)) 4972 #define CMIC_CMC0_MIIM_PARAM_OFFSET (0x31080) 4973 #define CMIC_CMC1_MIIM_PARAM_OFFSET (0x32080) 4974 #define CMIC_CMC2_MIIM_PARAM_OFFSET (0x33080) 4975 #define CMIC_CMCx_MIIM_PARAM_OFFSET(x) (0x31080 + (0x1000 * x)) 4976 #define CMIC_CMC0_MIIM_READ_DATA_OFFSET (0x31084) 4977 #define CMIC_CMC1_MIIM_READ_DATA_OFFSET (0x32084) 4978 #define CMIC_CMC2_MIIM_READ_DATA_OFFSET (0x33084) 4979 #define CMIC_CMCx_MIIM_READ_DATA_OFFSET(x) (0x31084 + (0x1000 * x)) 4980 #define CMIC_CMC0_MIIM_STAT_OFFSET (0x31090) 4981 #define CMIC_CMC1_MIIM_STAT_OFFSET (0x32090) 4982 #define CMIC_CMC2_MIIM_STAT_OFFSET (0x33090) 4983 #define CMIC_CMCx_MIIM_STAT_OFFSET(x) (0x31090 + (0x1000 * x)) 4984 #define CMIC_CMC0_PCIE_IRQ_MASK0_OFFSET (0x31414) 4985 #define CMIC_CMC1_PCIE_IRQ_MASK0_OFFSET (0x32414) 4986 #define CMIC_CMC2_PCIE_IRQ_MASK0_OFFSET (0x33414) 4987 #define CMIC_CMCx_PCIE_IRQ_MASK0_OFFSET(x) (0x31414 + (0x1000 * x)) 4988 #define CMIC_CMC0_PCIE_IRQ_MASK1_OFFSET (0x31418) 4989 #define CMIC_CMC1_PCIE_IRQ_MASK1_OFFSET (0x32418) 4990 #define CMIC_CMC2_PCIE_IRQ_MASK1_OFFSET (0x33418) 4991 #define CMIC_CMCx_PCIE_IRQ_MASK1_OFFSET(x) (0x31418 + (0x1000 * x)) 4992 #define CMIC_CMC0_PCIE_IRQ_MASK2_OFFSET (0x3141c) 4993 #define CMIC_CMC1_PCIE_IRQ_MASK2_OFFSET (0x3241c) 4994 #define CMIC_CMC2_PCIE_IRQ_MASK2_OFFSET (0x3341c) 4995 #define CMIC_CMCx_PCIE_IRQ_MASK2_OFFSET(x) (0x3141c + (0x1000 * x)) 4996 #define CMIC_CMC0_PCIE_IRQ_MASK3_OFFSET (0x31420) 4997 #define CMIC_CMC1_PCIE_IRQ_MASK3_OFFSET (0x32420) 4998 #define CMIC_CMC2_PCIE_IRQ_MASK3_OFFSET (0x33420) 4999 #define CMIC_CMCx_PCIE_IRQ_MASK3_OFFSET(x) (0x31420 + (0x1000 * x)) 5000 #define CMIC_CMC0_PCIE_IRQ_MASK4_OFFSET (0x31424) 5001 #define CMIC_CMC1_PCIE_IRQ_MASK4_OFFSET (0x32424) 5002 #define CMIC_CMC2_PCIE_IRQ_MASK4_OFFSET (0x33424) 5003 #define CMIC_CMCx_PCIE_IRQ_MASK4_OFFSET(x) (0x31424 + (0x1000 * x)) 5004 #define CMIC_CMC0_PCIE_IRQ_MASK5_OFFSET (0x314b8) 5005 #define CMIC_CMC1_PCIE_IRQ_MASK5_OFFSET (0x324b8) 5006 #define CMIC_CMC2_PCIE_IRQ_MASK5_OFFSET (0x334b8) 5007 #define CMIC_CMCx_PCIE_IRQ_MASK5_OFFSET(x) (0x314b8 + (0x1000 * x)) 5008 #define CMIC_CMC0_PCIE_IRQ_MASK6_OFFSET (0x314bc) 5009 #define CMIC_CMC1_PCIE_IRQ_MASK6_OFFSET (0x324bc) 5010 #define CMIC_CMC2_PCIE_IRQ_MASK6_OFFSET (0x334bc) 5011 #define CMIC_CMCx_PCIE_IRQ_MASK6_OFFSET(x) (0x314bc + (0x1000 * x)) 5012 #define CMIC_CMC0_PCIE_MISCEL_OFFSET (0x31470) 5013 #define CMIC_CMC1_PCIE_MISCEL_OFFSET (0x32470) 5014 #define CMIC_CMC2_PCIE_MISCEL_OFFSET (0x33470) 5015 #define CMIC_CMCx_PCIE_MISCEL_OFFSET(x) (0x31470 + (0x1000 * x)) 5016 #define CMIC_CMC0_PKT_COUNT_CH0_RXPKT_OFFSET (0x31480) 5017 #define CMIC_CMC1_PKT_COUNT_CH0_RXPKT_OFFSET (0x32480) 5018 #define CMIC_CMC2_PKT_COUNT_CH0_RXPKT_OFFSET (0x33480) 5019 #define CMIC_CMCx_PKT_COUNT_CH0_RXPKT_OFFSET(x) (0x31480 + (0x1000 * x)) 5020 #define CMIC_CMC0_PKT_COUNT_CH0_TXPKT_OFFSET (0x31484) 5021 #define CMIC_CMC1_PKT_COUNT_CH0_TXPKT_OFFSET (0x32484) 5022 #define CMIC_CMC2_PKT_COUNT_CH0_TXPKT_OFFSET (0x33484) 5023 #define CMIC_CMCx_PKT_COUNT_CH0_TXPKT_OFFSET(x) (0x31484 + (0x1000 * x)) 5024 #define CMIC_CMC0_PKT_COUNT_CH1_RXPKT_OFFSET (0x31488) 5025 #define CMIC_CMC1_PKT_COUNT_CH1_RXPKT_OFFSET (0x32488) 5026 #define CMIC_CMC2_PKT_COUNT_CH1_RXPKT_OFFSET (0x33488) 5027 #define CMIC_CMCx_PKT_COUNT_CH1_RXPKT_OFFSET(x) (0x31488 + (0x1000 * x)) 5028 #define CMIC_CMC0_PKT_COUNT_CH1_TXPKT_OFFSET (0x3148c) 5029 #define CMIC_CMC1_PKT_COUNT_CH1_TXPKT_OFFSET (0x3248c) 5030 #define CMIC_CMC2_PKT_COUNT_CH1_TXPKT_OFFSET (0x3348c) 5031 #define CMIC_CMCx_PKT_COUNT_CH1_TXPKT_OFFSET(x) (0x3148c + (0x1000 * x)) 5032 #define CMIC_CMC0_PKT_COUNT_CH2_RXPKT_OFFSET (0x31490) 5033 #define CMIC_CMC1_PKT_COUNT_CH2_RXPKT_OFFSET (0x32490) 5034 #define CMIC_CMC2_PKT_COUNT_CH2_RXPKT_OFFSET (0x33490) 5035 #define CMIC_CMCx_PKT_COUNT_CH2_RXPKT_OFFSET(x) (0x31490 + (0x1000 * x)) 5036 #define CMIC_CMC0_PKT_COUNT_CH2_TXPKT_OFFSET (0x31494) 5037 #define CMIC_CMC1_PKT_COUNT_CH2_TXPKT_OFFSET (0x32494) 5038 #define CMIC_CMC2_PKT_COUNT_CH2_TXPKT_OFFSET (0x33494) 5039 #define CMIC_CMCx_PKT_COUNT_CH2_TXPKT_OFFSET(x) (0x31494 + (0x1000 * x)) 5040 #define CMIC_CMC0_PKT_COUNT_CH3_RXPKT_OFFSET (0x31498) 5041 #define CMIC_CMC1_PKT_COUNT_CH3_RXPKT_OFFSET (0x32498) 5042 #define CMIC_CMC2_PKT_COUNT_CH3_RXPKT_OFFSET (0x33498) 5043 #define CMIC_CMCx_PKT_COUNT_CH3_RXPKT_OFFSET(x) (0x31498 + (0x1000 * x)) 5044 #define CMIC_CMC0_PKT_COUNT_CH3_TXPKT_OFFSET (0x3149c) 5045 #define CMIC_CMC1_PKT_COUNT_CH3_TXPKT_OFFSET (0x3249c) 5046 #define CMIC_CMC2_PKT_COUNT_CH3_TXPKT_OFFSET (0x3349c) 5047 #define CMIC_CMCx_PKT_COUNT_CH3_TXPKT_OFFSET(x) (0x3149c + (0x1000 * x)) 5048 #define CMIC_CMC0_PKT_COUNT_RXPKT_OFFSET (0x314a0) 5049 #define CMIC_CMC1_PKT_COUNT_RXPKT_OFFSET (0x324a0) 5050 #define CMIC_CMC2_PKT_COUNT_RXPKT_OFFSET (0x334a0) 5051 #define CMIC_CMCx_PKT_COUNT_RXPKT_OFFSET(x) (0x314a0 + (0x1000 * x)) 5052 #define CMIC_CMC0_PKT_COUNT_TXPKT_OFFSET (0x314a4) 5053 #define CMIC_CMC1_PKT_COUNT_TXPKT_OFFSET (0x324a4) 5054 #define CMIC_CMC2_PKT_COUNT_TXPKT_OFFSET (0x334a4) 5055 #define CMIC_CMCx_PKT_COUNT_TXPKT_OFFSET(x) (0x314a4 + (0x1000 * x)) 5056 #define CMIC_CMC0_PROGRAMMABLE_COS_MASK0_OFFSET (0x3119c) 5057 #define CMIC_CMC1_PROGRAMMABLE_COS_MASK0_OFFSET (0x3219c) 5058 #define CMIC_CMC2_PROGRAMMABLE_COS_MASK0_OFFSET (0x3319c) 5059 #define CMIC_CMCx_PROGRAMMABLE_COS_MASK0_OFFSET(x) (0x3119c + (0x1000 * x)) 5060 #define CMIC_CMC0_PROGRAMMABLE_COS_MASK1_OFFSET (0x311a0) 5061 #define CMIC_CMC1_PROGRAMMABLE_COS_MASK1_OFFSET (0x321a0) 5062 #define CMIC_CMC2_PROGRAMMABLE_COS_MASK1_OFFSET (0x331a0) 5063 #define CMIC_CMCx_PROGRAMMABLE_COS_MASK1_OFFSET(x) (0x311a0 + (0x1000 * x)) 5064 #define CMIC_CMC0_RCPU_IRQ_MASK0_OFFSET (0x31450) 5065 #define CMIC_CMC1_RCPU_IRQ_MASK0_OFFSET (0x32450) 5066 #define CMIC_CMC2_RCPU_IRQ_MASK0_OFFSET (0x33450) 5067 #define CMIC_CMCx_RCPU_IRQ_MASK0_OFFSET(x) (0x31450 + (0x1000 * x)) 5068 #define CMIC_CMC0_RXBUF_THRESHOLD_CONFIG_OFFSET (0x31198) 5069 #define CMIC_CMC1_RXBUF_THRESHOLD_CONFIG_OFFSET (0x32198) 5070 #define CMIC_CMC2_RXBUF_THRESHOLD_CONFIG_OFFSET (0x33198) 5071 #define CMIC_CMCx_RXBUF_THRESHOLD_CONFIG_OFFSET(x) (0x31198 + (0x1000 * x)) 5072 #define CMIC_CMC0_SBUSDMA_CH0_CONTROL_OFFSET (0x31600) 5073 #define CMIC_CMC1_SBUSDMA_CH0_CONTROL_OFFSET (0x32600) 5074 #define CMIC_CMC2_SBUSDMA_CH0_CONTROL_OFFSET (0x33600) 5075 #define CMIC_CMCx_SBUSDMA_CH0_CONTROL_OFFSET(x) (0x31600 + (0x1000 * x)) 5076 #define CMIC_CMC0_SBUSDMA_CH0_COUNT_OFFSET (0x31608) 5077 #define CMIC_CMC1_SBUSDMA_CH0_COUNT_OFFSET (0x32608) 5078 #define CMIC_CMC2_SBUSDMA_CH0_COUNT_OFFSET (0x33608) 5079 #define CMIC_CMCx_SBUSDMA_CH0_COUNT_OFFSET(x) (0x31608 + (0x1000 * x)) 5080 #define CMIC_CMC0_SBUSDMA_CH0_CUR_DESC_ADDRESS_OFFSET (0x31628) 5081 #define CMIC_CMC1_SBUSDMA_CH0_CUR_DESC_ADDRESS_OFFSET (0x32628) 5082 #define CMIC_CMC2_SBUSDMA_CH0_CUR_DESC_ADDRESS_OFFSET (0x33628) 5083 #define CMIC_CMCx_SBUSDMA_CH0_CUR_DESC_ADDRESS_OFFSET(x) (0x31628 + (0x1000 * x)) 5084 #define CMIC_CMC0_SBUSDMA_CH0_CUR_HOSTMEM_ADDRESS_OFFSET (0x31620) 5085 #define CMIC_CMC1_SBUSDMA_CH0_CUR_HOSTMEM_ADDRESS_OFFSET (0x32620) 5086 #define CMIC_CMC2_SBUSDMA_CH0_CUR_HOSTMEM_ADDRESS_OFFSET (0x33620) 5087 #define CMIC_CMCx_SBUSDMA_CH0_CUR_HOSTMEM_ADDRESS_OFFSET(x) (0x31620 + (0x1000 * x)) 5088 #define CMIC_CMC0_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_COUNT_OFFSET (0x31630) 5089 #define CMIC_CMC1_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_COUNT_OFFSET (0x32630) 5090 #define CMIC_CMC2_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_COUNT_OFFSET (0x33630) 5091 #define CMIC_CMCx_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_COUNT_OFFSET(x) (0x31630 + (0x1000 * x)) 5092 #define CMIC_CMC0_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_OFFSET (0x31638) 5093 #define CMIC_CMC1_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_OFFSET (0x32638) 5094 #define CMIC_CMC2_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_OFFSET (0x33638) 5095 #define CMIC_CMCx_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_OFFSET(x) (0x31638 + (0x1000 * x)) 5096 #define CMIC_CMC0_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_OPCODE_OFFSET (0x3163c) 5097 #define CMIC_CMC1_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_OPCODE_OFFSET (0x3263c) 5098 #define CMIC_CMC2_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_OPCODE_OFFSET (0x3363c) 5099 #define CMIC_CMCx_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_OPCODE_OFFSET(x) (0x3163c + (0x1000 * x)) 5100 #define CMIC_CMC0_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_REQUEST_OFFSET (0x3162c) 5101 #define CMIC_CMC1_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_REQUEST_OFFSET (0x3262c) 5102 #define CMIC_CMC2_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_REQUEST_OFFSET (0x3362c) 5103 #define CMIC_CMCx_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_REQUEST_OFFSET(x) (0x3162c + (0x1000 * x)) 5104 #define CMIC_CMC0_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_SBUS_START_ADDRESS_OFFSET (0x31634) 5105 #define CMIC_CMC1_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_SBUS_START_ADDRESS_OFFSET (0x32634) 5106 #define CMIC_CMC2_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_SBUS_START_ADDRESS_OFFSET (0x33634) 5107 #define CMIC_CMCx_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_SBUS_START_ADDRESS_OFFSET(x) (0x31634 + (0x1000 * x)) 5108 #define CMIC_CMC0_SBUSDMA_CH0_CUR_SBUS_ADDRESS_OFFSET (0x31624) 5109 #define CMIC_CMC1_SBUSDMA_CH0_CUR_SBUS_ADDRESS_OFFSET (0x32624) 5110 #define CMIC_CMC2_SBUSDMA_CH0_CUR_SBUS_ADDRESS_OFFSET (0x33624) 5111 #define CMIC_CMCx_SBUSDMA_CH0_CUR_SBUS_ADDRESS_OFFSET(x) (0x31624 + (0x1000 * x)) 5112 #define CMIC_CMC0_SBUSDMA_CH0_DESC_START_ADDRESS_OFFSET (0x31618) 5113 #define CMIC_CMC1_SBUSDMA_CH0_DESC_START_ADDRESS_OFFSET (0x32618) 5114 #define CMIC_CMC2_SBUSDMA_CH0_DESC_START_ADDRESS_OFFSET (0x33618) 5115 #define CMIC_CMCx_SBUSDMA_CH0_DESC_START_ADDRESS_OFFSET(x) (0x31618 + (0x1000 * x)) 5116 #define CMIC_CMC0_SBUSDMA_CH0_HOSTMEM_START_ADDRESS_OFFSET (0x31614) 5117 #define CMIC_CMC1_SBUSDMA_CH0_HOSTMEM_START_ADDRESS_OFFSET (0x32614) 5118 #define CMIC_CMC2_SBUSDMA_CH0_HOSTMEM_START_ADDRESS_OFFSET (0x33614) 5119 #define CMIC_CMCx_SBUSDMA_CH0_HOSTMEM_START_ADDRESS_OFFSET(x) (0x31614 + (0x1000 * x)) 5120 #define CMIC_CMC0_SBUSDMA_CH0_ITER_COUNT_OFFSET (0x316fc) 5121 #define CMIC_CMC1_SBUSDMA_CH0_ITER_COUNT_OFFSET (0x326fc) 5122 #define CMIC_CMC2_SBUSDMA_CH0_ITER_COUNT_OFFSET (0x336fc) 5123 #define CMIC_CMCx_SBUSDMA_CH0_ITER_COUNT_OFFSET(x) (0x316fc + (0x1000 * x)) 5124 #define CMIC_CMC0_SBUSDMA_CH0_OPCODE_OFFSET (0x3160c) 5125 #define CMIC_CMC1_SBUSDMA_CH0_OPCODE_OFFSET (0x3260c) 5126 #define CMIC_CMC2_SBUSDMA_CH0_OPCODE_OFFSET (0x3360c) 5127 #define CMIC_CMCx_SBUSDMA_CH0_OPCODE_OFFSET(x) (0x3160c + (0x1000 * x)) 5128 #define CMIC_CMC0_SBUSDMA_CH0_REQUEST_OFFSET (0x31604) 5129 #define CMIC_CMC1_SBUSDMA_CH0_REQUEST_OFFSET (0x32604) 5130 #define CMIC_CMC2_SBUSDMA_CH0_REQUEST_OFFSET (0x33604) 5131 #define CMIC_CMCx_SBUSDMA_CH0_REQUEST_OFFSET(x) (0x31604 + (0x1000 * x)) 5132 #define CMIC_CMC0_SBUSDMA_CH0_SBUSDMA_DEBUG_OFFSET (0x31640) 5133 #define CMIC_CMC1_SBUSDMA_CH0_SBUSDMA_DEBUG_OFFSET (0x32640) 5134 #define CMIC_CMC2_SBUSDMA_CH0_SBUSDMA_DEBUG_OFFSET (0x33640) 5135 #define CMIC_CMCx_SBUSDMA_CH0_SBUSDMA_DEBUG_OFFSET(x) (0x31640 + (0x1000 * x)) 5136 #define CMIC_CMC0_SBUSDMA_CH0_SBUSDMA_DEBUG_CLR_OFFSET (0x31644) 5137 #define CMIC_CMC1_SBUSDMA_CH0_SBUSDMA_DEBUG_CLR_OFFSET (0x32644) 5138 #define CMIC_CMC2_SBUSDMA_CH0_SBUSDMA_DEBUG_CLR_OFFSET (0x33644) 5139 #define CMIC_CMCx_SBUSDMA_CH0_SBUSDMA_DEBUG_CLR_OFFSET(x) (0x31644 + (0x1000 * x)) 5140 #define CMIC_CMC0_SBUSDMA_CH0_SBUSDMA_ECCERR_ADDRESS_OFFSET (0x31648) 5141 #define CMIC_CMC1_SBUSDMA_CH0_SBUSDMA_ECCERR_ADDRESS_OFFSET (0x32648) 5142 #define CMIC_CMC2_SBUSDMA_CH0_SBUSDMA_ECCERR_ADDRESS_OFFSET (0x33648) 5143 #define CMIC_CMCx_SBUSDMA_CH0_SBUSDMA_ECCERR_ADDRESS_OFFSET(x) (0x31648 + (0x1000 * x)) 5144 #define CMIC_CMC0_SBUSDMA_CH0_SBUSDMA_ECCERR_CONTROL_OFFSET (0x3164c) 5145 #define CMIC_CMC1_SBUSDMA_CH0_SBUSDMA_ECCERR_CONTROL_OFFSET (0x3264c) 5146 #define CMIC_CMC2_SBUSDMA_CH0_SBUSDMA_ECCERR_CONTROL_OFFSET (0x3364c) 5147 #define CMIC_CMCx_SBUSDMA_CH0_SBUSDMA_ECCERR_CONTROL_OFFSET(x) (0x3164c + (0x1000 * x)) 5148 #define CMIC_CMC0_SBUSDMA_CH0_SBUS_START_ADDRESS_OFFSET (0x31610) 5149 #define CMIC_CMC1_SBUSDMA_CH0_SBUS_START_ADDRESS_OFFSET (0x32610) 5150 #define CMIC_CMC2_SBUSDMA_CH0_SBUS_START_ADDRESS_OFFSET (0x33610) 5151 #define CMIC_CMCx_SBUSDMA_CH0_SBUS_START_ADDRESS_OFFSET(x) (0x31610 + (0x1000 * x)) 5152 #define CMIC_CMC0_SBUSDMA_CH0_STATUS_OFFSET (0x3161c) 5153 #define CMIC_CMC1_SBUSDMA_CH0_STATUS_OFFSET (0x3261c) 5154 #define CMIC_CMC2_SBUSDMA_CH0_STATUS_OFFSET (0x3361c) 5155 #define CMIC_CMCx_SBUSDMA_CH0_STATUS_OFFSET(x) (0x3161c + (0x1000 * x)) 5156 #define CMIC_CMC0_SBUSDMA_CH0_TIMER_OFFSET (0x316f0) 5157 #define CMIC_CMC1_SBUSDMA_CH0_TIMER_OFFSET (0x326f0) 5158 #define CMIC_CMC2_SBUSDMA_CH0_TIMER_OFFSET (0x336f0) 5159 #define CMIC_CMCx_SBUSDMA_CH0_TIMER_OFFSET(x) (0x316f0 + (0x1000 * x)) 5160 #define CMIC_CMC0_SBUSDMA_CH0_TM_CONTROL_0_OFFSET (0x31800) 5161 #define CMIC_CMC1_SBUSDMA_CH0_TM_CONTROL_0_OFFSET (0x32800) 5162 #define CMIC_CMC2_SBUSDMA_CH0_TM_CONTROL_0_OFFSET (0x33800) 5163 #define CMIC_CMCx_SBUSDMA_CH0_TM_CONTROL_0_OFFSET(x) (0x31800 + (0x1000 * x)) 5164 #define CMIC_CMC0_SBUSDMA_CH0_TM_CONTROL_1_OFFSET (0x31804) 5165 #define CMIC_CMC1_SBUSDMA_CH0_TM_CONTROL_1_OFFSET (0x32804) 5166 #define CMIC_CMC2_SBUSDMA_CH0_TM_CONTROL_1_OFFSET (0x33804) 5167 #define CMIC_CMCx_SBUSDMA_CH0_TM_CONTROL_1_OFFSET(x) (0x31804 + (0x1000 * x)) 5168 #define CMIC_CMC0_SBUSDMA_CH0_TM_CONTROL_2_OFFSET (0x3180c) 5169 #define CMIC_CMC1_SBUSDMA_CH0_TM_CONTROL_2_OFFSET (0x3280c) 5170 #define CMIC_CMC2_SBUSDMA_CH0_TM_CONTROL_2_OFFSET (0x3380c) 5171 #define CMIC_CMCx_SBUSDMA_CH0_TM_CONTROL_2_OFFSET(x) (0x3180c + (0x1000 * x)) 5172 #define CMIC_CMC0_SBUSDMA_CH1_CONTROL_OFFSET (0x31650) 5173 #define CMIC_CMC1_SBUSDMA_CH1_CONTROL_OFFSET (0x32650) 5174 #define CMIC_CMC2_SBUSDMA_CH1_CONTROL_OFFSET (0x33650) 5175 #define CMIC_CMCx_SBUSDMA_CH1_CONTROL_OFFSET(x) (0x31650 + (0x1000 * x)) 5176 #define CMIC_CMC0_SBUSDMA_CH1_COUNT_OFFSET (0x31658) 5177 #define CMIC_CMC1_SBUSDMA_CH1_COUNT_OFFSET (0x32658) 5178 #define CMIC_CMC2_SBUSDMA_CH1_COUNT_OFFSET (0x33658) 5179 #define CMIC_CMCx_SBUSDMA_CH1_COUNT_OFFSET(x) (0x31658 + (0x1000 * x)) 5180 #define CMIC_CMC0_SBUSDMA_CH1_CUR_DESC_ADDRESS_OFFSET (0x31678) 5181 #define CMIC_CMC1_SBUSDMA_CH1_CUR_DESC_ADDRESS_OFFSET (0x32678) 5182 #define CMIC_CMC2_SBUSDMA_CH1_CUR_DESC_ADDRESS_OFFSET (0x33678) 5183 #define CMIC_CMCx_SBUSDMA_CH1_CUR_DESC_ADDRESS_OFFSET(x) (0x31678 + (0x1000 * x)) 5184 #define CMIC_CMC0_SBUSDMA_CH1_CUR_HOSTMEM_ADDRESS_OFFSET (0x31670) 5185 #define CMIC_CMC1_SBUSDMA_CH1_CUR_HOSTMEM_ADDRESS_OFFSET (0x32670) 5186 #define CMIC_CMC2_SBUSDMA_CH1_CUR_HOSTMEM_ADDRESS_OFFSET (0x33670) 5187 #define CMIC_CMCx_SBUSDMA_CH1_CUR_HOSTMEM_ADDRESS_OFFSET(x) (0x31670 + (0x1000 * x)) 5188 #define CMIC_CMC0_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_COUNT_OFFSET (0x31680) 5189 #define CMIC_CMC1_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_COUNT_OFFSET (0x32680) 5190 #define CMIC_CMC2_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_COUNT_OFFSET (0x33680) 5191 #define CMIC_CMCx_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_COUNT_OFFSET(x) (0x31680 + (0x1000 * x)) 5192 #define CMIC_CMC0_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_OFFSET (0x31688) 5193 #define CMIC_CMC1_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_OFFSET (0x32688) 5194 #define CMIC_CMC2_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_OFFSET (0x33688) 5195 #define CMIC_CMCx_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_OFFSET(x) (0x31688 + (0x1000 * x)) 5196 #define CMIC_CMC0_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_OPCODE_OFFSET (0x3168c) 5197 #define CMIC_CMC1_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_OPCODE_OFFSET (0x3268c) 5198 #define CMIC_CMC2_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_OPCODE_OFFSET (0x3368c) 5199 #define CMIC_CMCx_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_OPCODE_OFFSET(x) (0x3168c + (0x1000 * x)) 5200 #define CMIC_CMC0_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_REQUEST_OFFSET (0x3167c) 5201 #define CMIC_CMC1_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_REQUEST_OFFSET (0x3267c) 5202 #define CMIC_CMC2_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_REQUEST_OFFSET (0x3367c) 5203 #define CMIC_CMCx_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_REQUEST_OFFSET(x) (0x3167c + (0x1000 * x)) 5204 #define CMIC_CMC0_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_SBUS_START_ADDRESS_OFFSET (0x31684) 5205 #define CMIC_CMC1_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_SBUS_START_ADDRESS_OFFSET (0x32684) 5206 #define CMIC_CMC2_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_SBUS_START_ADDRESS_OFFSET (0x33684) 5207 #define CMIC_CMCx_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_SBUS_START_ADDRESS_OFFSET(x) (0x31684 + (0x1000 * x)) 5208 #define CMIC_CMC0_SBUSDMA_CH1_CUR_SBUS_ADDRESS_OFFSET (0x31674) 5209 #define CMIC_CMC1_SBUSDMA_CH1_CUR_SBUS_ADDRESS_OFFSET (0x32674) 5210 #define CMIC_CMC2_SBUSDMA_CH1_CUR_SBUS_ADDRESS_OFFSET (0x33674) 5211 #define CMIC_CMCx_SBUSDMA_CH1_CUR_SBUS_ADDRESS_OFFSET(x) (0x31674 + (0x1000 * x)) 5212 #define CMIC_CMC0_SBUSDMA_CH1_DESC_START_ADDRESS_OFFSET (0x31668) 5213 #define CMIC_CMC1_SBUSDMA_CH1_DESC_START_ADDRESS_OFFSET (0x32668) 5214 #define CMIC_CMC2_SBUSDMA_CH1_DESC_START_ADDRESS_OFFSET (0x33668) 5215 #define CMIC_CMCx_SBUSDMA_CH1_DESC_START_ADDRESS_OFFSET(x) (0x31668 + (0x1000 * x)) 5216 #define CMIC_CMC0_SBUSDMA_CH1_HOSTMEM_START_ADDRESS_OFFSET (0x31664) 5217 #define CMIC_CMC1_SBUSDMA_CH1_HOSTMEM_START_ADDRESS_OFFSET (0x32664) 5218 #define CMIC_CMC2_SBUSDMA_CH1_HOSTMEM_START_ADDRESS_OFFSET (0x33664) 5219 #define CMIC_CMCx_SBUSDMA_CH1_HOSTMEM_START_ADDRESS_OFFSET(x) (0x31664 + (0x1000 * x)) 5220 #define CMIC_CMC0_SBUSDMA_CH1_ITER_COUNT_OFFSET (0x31700) 5221 #define CMIC_CMC1_SBUSDMA_CH1_ITER_COUNT_OFFSET (0x32700) 5222 #define CMIC_CMC2_SBUSDMA_CH1_ITER_COUNT_OFFSET (0x33700) 5223 #define CMIC_CMCx_SBUSDMA_CH1_ITER_COUNT_OFFSET(x) (0x31700 + (0x1000 * x)) 5224 #define CMIC_CMC0_SBUSDMA_CH1_OPCODE_OFFSET (0x3165c) 5225 #define CMIC_CMC1_SBUSDMA_CH1_OPCODE_OFFSET (0x3265c) 5226 #define CMIC_CMC2_SBUSDMA_CH1_OPCODE_OFFSET (0x3365c) 5227 #define CMIC_CMCx_SBUSDMA_CH1_OPCODE_OFFSET(x) (0x3165c + (0x1000 * x)) 5228 #define CMIC_CMC0_SBUSDMA_CH1_REQUEST_OFFSET (0x31654) 5229 #define CMIC_CMC1_SBUSDMA_CH1_REQUEST_OFFSET (0x32654) 5230 #define CMIC_CMC2_SBUSDMA_CH1_REQUEST_OFFSET (0x33654) 5231 #define CMIC_CMCx_SBUSDMA_CH1_REQUEST_OFFSET(x) (0x31654 + (0x1000 * x)) 5232 #define CMIC_CMC0_SBUSDMA_CH1_SBUSDMA_DEBUG_OFFSET (0x31690) 5233 #define CMIC_CMC1_SBUSDMA_CH1_SBUSDMA_DEBUG_OFFSET (0x32690) 5234 #define CMIC_CMC2_SBUSDMA_CH1_SBUSDMA_DEBUG_OFFSET (0x33690) 5235 #define CMIC_CMCx_SBUSDMA_CH1_SBUSDMA_DEBUG_OFFSET(x) (0x31690 + (0x1000 * x)) 5236 #define CMIC_CMC0_SBUSDMA_CH1_SBUSDMA_DEBUG_CLR_OFFSET (0x31694) 5237 #define CMIC_CMC1_SBUSDMA_CH1_SBUSDMA_DEBUG_CLR_OFFSET (0x32694) 5238 #define CMIC_CMC2_SBUSDMA_CH1_SBUSDMA_DEBUG_CLR_OFFSET (0x33694) 5239 #define CMIC_CMCx_SBUSDMA_CH1_SBUSDMA_DEBUG_CLR_OFFSET(x) (0x31694 + (0x1000 * x)) 5240 #define CMIC_CMC0_SBUSDMA_CH1_SBUSDMA_ECCERR_ADDRESS_OFFSET (0x31698) 5241 #define CMIC_CMC1_SBUSDMA_CH1_SBUSDMA_ECCERR_ADDRESS_OFFSET (0x32698) 5242 #define CMIC_CMC2_SBUSDMA_CH1_SBUSDMA_ECCERR_ADDRESS_OFFSET (0x33698) 5243 #define CMIC_CMCx_SBUSDMA_CH1_SBUSDMA_ECCERR_ADDRESS_OFFSET(x) (0x31698 + (0x1000 * x)) 5244 #define CMIC_CMC0_SBUSDMA_CH1_SBUSDMA_ECCERR_CONTROL_OFFSET (0x3169c) 5245 #define CMIC_CMC1_SBUSDMA_CH1_SBUSDMA_ECCERR_CONTROL_OFFSET (0x3269c) 5246 #define CMIC_CMC2_SBUSDMA_CH1_SBUSDMA_ECCERR_CONTROL_OFFSET (0x3369c) 5247 #define CMIC_CMCx_SBUSDMA_CH1_SBUSDMA_ECCERR_CONTROL_OFFSET(x) (0x3169c + (0x1000 * x)) 5248 #define CMIC_CMC0_SBUSDMA_CH1_SBUS_START_ADDRESS_OFFSET (0x31660) 5249 #define CMIC_CMC1_SBUSDMA_CH1_SBUS_START_ADDRESS_OFFSET (0x32660) 5250 #define CMIC_CMC2_SBUSDMA_CH1_SBUS_START_ADDRESS_OFFSET (0x33660) 5251 #define CMIC_CMCx_SBUSDMA_CH1_SBUS_START_ADDRESS_OFFSET(x) (0x31660 + (0x1000 * x)) 5252 #define CMIC_CMC0_SBUSDMA_CH1_STATUS_OFFSET (0x3166c) 5253 #define CMIC_CMC1_SBUSDMA_CH1_STATUS_OFFSET (0x3266c) 5254 #define CMIC_CMC2_SBUSDMA_CH1_STATUS_OFFSET (0x3366c) 5255 #define CMIC_CMCx_SBUSDMA_CH1_STATUS_OFFSET(x) (0x3166c + (0x1000 * x)) 5256 #define CMIC_CMC0_SBUSDMA_CH1_TIMER_OFFSET (0x316f4) 5257 #define CMIC_CMC1_SBUSDMA_CH1_TIMER_OFFSET (0x326f4) 5258 #define CMIC_CMC2_SBUSDMA_CH1_TIMER_OFFSET (0x336f4) 5259 #define CMIC_CMCx_SBUSDMA_CH1_TIMER_OFFSET(x) (0x316f4 + (0x1000 * x)) 5260 #define CMIC_CMC0_SBUSDMA_CH1_TM_CONTROL_0_OFFSET (0x31810) 5261 #define CMIC_CMC1_SBUSDMA_CH1_TM_CONTROL_0_OFFSET (0x32810) 5262 #define CMIC_CMC2_SBUSDMA_CH1_TM_CONTROL_0_OFFSET (0x33810) 5263 #define CMIC_CMCx_SBUSDMA_CH1_TM_CONTROL_0_OFFSET(x) (0x31810 + (0x1000 * x)) 5264 #define CMIC_CMC0_SBUSDMA_CH1_TM_CONTROL_1_OFFSET (0x31814) 5265 #define CMIC_CMC1_SBUSDMA_CH1_TM_CONTROL_1_OFFSET (0x32814) 5266 #define CMIC_CMC2_SBUSDMA_CH1_TM_CONTROL_1_OFFSET (0x33814) 5267 #define CMIC_CMCx_SBUSDMA_CH1_TM_CONTROL_1_OFFSET(x) (0x31814 + (0x1000 * x)) 5268 #define CMIC_CMC0_SBUSDMA_CH1_TM_CONTROL_2_OFFSET (0x31818) 5269 #define CMIC_CMC1_SBUSDMA_CH1_TM_CONTROL_2_OFFSET (0x32818) 5270 #define CMIC_CMC2_SBUSDMA_CH1_TM_CONTROL_2_OFFSET (0x33818) 5271 #define CMIC_CMCx_SBUSDMA_CH1_TM_CONTROL_2_OFFSET(x) (0x31818 + (0x1000 * x)) 5272 #define CMIC_CMC0_SBUSDMA_CH2_CONTROL_OFFSET (0x316a0) 5273 #define CMIC_CMC1_SBUSDMA_CH2_CONTROL_OFFSET (0x326a0) 5274 #define CMIC_CMC2_SBUSDMA_CH2_CONTROL_OFFSET (0x336a0) 5275 #define CMIC_CMCx_SBUSDMA_CH2_CONTROL_OFFSET(x) (0x316a0 + (0x1000 * x)) 5276 #define CMIC_CMC0_SBUSDMA_CH2_COUNT_OFFSET (0x316a8) 5277 #define CMIC_CMC1_SBUSDMA_CH2_COUNT_OFFSET (0x326a8) 5278 #define CMIC_CMC2_SBUSDMA_CH2_COUNT_OFFSET (0x336a8) 5279 #define CMIC_CMCx_SBUSDMA_CH2_COUNT_OFFSET(x) (0x316a8 + (0x1000 * x)) 5280 #define CMIC_CMC0_SBUSDMA_CH2_CUR_DESC_ADDRESS_OFFSET (0x316c8) 5281 #define CMIC_CMC1_SBUSDMA_CH2_CUR_DESC_ADDRESS_OFFSET (0x326c8) 5282 #define CMIC_CMC2_SBUSDMA_CH2_CUR_DESC_ADDRESS_OFFSET (0x336c8) 5283 #define CMIC_CMCx_SBUSDMA_CH2_CUR_DESC_ADDRESS_OFFSET(x) (0x316c8 + (0x1000 * x)) 5284 #define CMIC_CMC0_SBUSDMA_CH2_CUR_HOSTMEM_ADDRESS_OFFSET (0x316c0) 5285 #define CMIC_CMC1_SBUSDMA_CH2_CUR_HOSTMEM_ADDRESS_OFFSET (0x326c0) 5286 #define CMIC_CMC2_SBUSDMA_CH2_CUR_HOSTMEM_ADDRESS_OFFSET (0x336c0) 5287 #define CMIC_CMCx_SBUSDMA_CH2_CUR_HOSTMEM_ADDRESS_OFFSET(x) (0x316c0 + (0x1000 * x)) 5288 #define CMIC_CMC0_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_COUNT_OFFSET (0x316d0) 5289 #define CMIC_CMC1_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_COUNT_OFFSET (0x326d0) 5290 #define CMIC_CMC2_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_COUNT_OFFSET (0x336d0) 5291 #define CMIC_CMCx_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_COUNT_OFFSET(x) (0x316d0 + (0x1000 * x)) 5292 #define CMIC_CMC0_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_OFFSET (0x316d8) 5293 #define CMIC_CMC1_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_OFFSET (0x326d8) 5294 #define CMIC_CMC2_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_OFFSET (0x336d8) 5295 #define CMIC_CMCx_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_OFFSET(x) (0x316d8 + (0x1000 * x)) 5296 #define CMIC_CMC0_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_OPCODE_OFFSET (0x316dc) 5297 #define CMIC_CMC1_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_OPCODE_OFFSET (0x326dc) 5298 #define CMIC_CMC2_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_OPCODE_OFFSET (0x336dc) 5299 #define CMIC_CMCx_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_OPCODE_OFFSET(x) (0x316dc + (0x1000 * x)) 5300 #define CMIC_CMC0_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_REQUEST_OFFSET (0x316cc) 5301 #define CMIC_CMC1_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_REQUEST_OFFSET (0x326cc) 5302 #define CMIC_CMC2_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_REQUEST_OFFSET (0x336cc) 5303 #define CMIC_CMCx_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_REQUEST_OFFSET(x) (0x316cc + (0x1000 * x)) 5304 #define CMIC_CMC0_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_SBUS_START_ADDRESS_OFFSET (0x316d4) 5305 #define CMIC_CMC1_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_SBUS_START_ADDRESS_OFFSET (0x326d4) 5306 #define CMIC_CMC2_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_SBUS_START_ADDRESS_OFFSET (0x336d4) 5307 #define CMIC_CMCx_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_SBUS_START_ADDRESS_OFFSET(x) (0x316d4 + (0x1000 * x)) 5308 #define CMIC_CMC0_SBUSDMA_CH2_CUR_SBUS_ADDRESS_OFFSET (0x316c4) 5309 #define CMIC_CMC1_SBUSDMA_CH2_CUR_SBUS_ADDRESS_OFFSET (0x326c4) 5310 #define CMIC_CMC2_SBUSDMA_CH2_CUR_SBUS_ADDRESS_OFFSET (0x336c4) 5311 #define CMIC_CMCx_SBUSDMA_CH2_CUR_SBUS_ADDRESS_OFFSET(x) (0x316c4 + (0x1000 * x)) 5312 #define CMIC_CMC0_SBUSDMA_CH2_DESC_START_ADDRESS_OFFSET (0x316b8) 5313 #define CMIC_CMC1_SBUSDMA_CH2_DESC_START_ADDRESS_OFFSET (0x326b8) 5314 #define CMIC_CMC2_SBUSDMA_CH2_DESC_START_ADDRESS_OFFSET (0x336b8) 5315 #define CMIC_CMCx_SBUSDMA_CH2_DESC_START_ADDRESS_OFFSET(x) (0x316b8 + (0x1000 * x)) 5316 #define CMIC_CMC0_SBUSDMA_CH2_HOSTMEM_START_ADDRESS_OFFSET (0x316b4) 5317 #define CMIC_CMC1_SBUSDMA_CH2_HOSTMEM_START_ADDRESS_OFFSET (0x326b4) 5318 #define CMIC_CMC2_SBUSDMA_CH2_HOSTMEM_START_ADDRESS_OFFSET (0x336b4) 5319 #define CMIC_CMCx_SBUSDMA_CH2_HOSTMEM_START_ADDRESS_OFFSET(x) (0x316b4 + (0x1000 * x)) 5320 #define CMIC_CMC0_SBUSDMA_CH2_ITER_COUNT_OFFSET (0x31704) 5321 #define CMIC_CMC1_SBUSDMA_CH2_ITER_COUNT_OFFSET (0x32704) 5322 #define CMIC_CMC2_SBUSDMA_CH2_ITER_COUNT_OFFSET (0x33704) 5323 #define CMIC_CMCx_SBUSDMA_CH2_ITER_COUNT_OFFSET(x) (0x31704 + (0x1000 * x)) 5324 #define CMIC_CMC0_SBUSDMA_CH2_OPCODE_OFFSET (0x316ac) 5325 #define CMIC_CMC1_SBUSDMA_CH2_OPCODE_OFFSET (0x326ac) 5326 #define CMIC_CMC2_SBUSDMA_CH2_OPCODE_OFFSET (0x336ac) 5327 #define CMIC_CMCx_SBUSDMA_CH2_OPCODE_OFFSET(x) (0x316ac + (0x1000 * x)) 5328 #define CMIC_CMC0_SBUSDMA_CH2_REQUEST_OFFSET (0x316a4) 5329 #define CMIC_CMC1_SBUSDMA_CH2_REQUEST_OFFSET (0x326a4) 5330 #define CMIC_CMC2_SBUSDMA_CH2_REQUEST_OFFSET (0x336a4) 5331 #define CMIC_CMCx_SBUSDMA_CH2_REQUEST_OFFSET(x) (0x316a4 + (0x1000 * x)) 5332 #define CMIC_CMC0_SBUSDMA_CH2_SBUSDMA_DEBUG_OFFSET (0x316e0) 5333 #define CMIC_CMC1_SBUSDMA_CH2_SBUSDMA_DEBUG_OFFSET (0x326e0) 5334 #define CMIC_CMC2_SBUSDMA_CH2_SBUSDMA_DEBUG_OFFSET (0x336e0) 5335 #define CMIC_CMCx_SBUSDMA_CH2_SBUSDMA_DEBUG_OFFSET(x) (0x316e0 + (0x1000 * x)) 5336 #define CMIC_CMC0_SBUSDMA_CH2_SBUSDMA_DEBUG_CLR_OFFSET (0x316e4) 5337 #define CMIC_CMC1_SBUSDMA_CH2_SBUSDMA_DEBUG_CLR_OFFSET (0x326e4) 5338 #define CMIC_CMC2_SBUSDMA_CH2_SBUSDMA_DEBUG_CLR_OFFSET (0x336e4) 5339 #define CMIC_CMCx_SBUSDMA_CH2_SBUSDMA_DEBUG_CLR_OFFSET(x) (0x316e4 + (0x1000 * x)) 5340 #define CMIC_CMC0_SBUSDMA_CH2_SBUSDMA_ECCERR_ADDRESS_OFFSET (0x316e8) 5341 #define CMIC_CMC1_SBUSDMA_CH2_SBUSDMA_ECCERR_ADDRESS_OFFSET (0x326e8) 5342 #define CMIC_CMC2_SBUSDMA_CH2_SBUSDMA_ECCERR_ADDRESS_OFFSET (0x336e8) 5343 #define CMIC_CMCx_SBUSDMA_CH2_SBUSDMA_ECCERR_ADDRESS_OFFSET(x) (0x316e8 + (0x1000 * x)) 5344 #define CMIC_CMC0_SBUSDMA_CH2_SBUSDMA_ECCERR_CONTROL_OFFSET (0x316ec) 5345 #define CMIC_CMC1_SBUSDMA_CH2_SBUSDMA_ECCERR_CONTROL_OFFSET (0x326ec) 5346 #define CMIC_CMC2_SBUSDMA_CH2_SBUSDMA_ECCERR_CONTROL_OFFSET (0x336ec) 5347 #define CMIC_CMCx_SBUSDMA_CH2_SBUSDMA_ECCERR_CONTROL_OFFSET(x) (0x316ec + (0x1000 * x)) 5348 #define CMIC_CMC0_SBUSDMA_CH2_SBUS_START_ADDRESS_OFFSET (0x316b0) 5349 #define CMIC_CMC1_SBUSDMA_CH2_SBUS_START_ADDRESS_OFFSET (0x326b0) 5350 #define CMIC_CMC2_SBUSDMA_CH2_SBUS_START_ADDRESS_OFFSET (0x336b0) 5351 #define CMIC_CMCx_SBUSDMA_CH2_SBUS_START_ADDRESS_OFFSET(x) (0x316b0 + (0x1000 * x)) 5352 #define CMIC_CMC0_SBUSDMA_CH2_STATUS_OFFSET (0x316bc) 5353 #define CMIC_CMC1_SBUSDMA_CH2_STATUS_OFFSET (0x326bc) 5354 #define CMIC_CMC2_SBUSDMA_CH2_STATUS_OFFSET (0x336bc) 5355 #define CMIC_CMCx_SBUSDMA_CH2_STATUS_OFFSET(x) (0x316bc + (0x1000 * x)) 5356 #define CMIC_CMC0_SBUSDMA_CH2_TIMER_OFFSET (0x316f8) 5357 #define CMIC_CMC1_SBUSDMA_CH2_TIMER_OFFSET (0x326f8) 5358 #define CMIC_CMC2_SBUSDMA_CH2_TIMER_OFFSET (0x336f8) 5359 #define CMIC_CMCx_SBUSDMA_CH2_TIMER_OFFSET(x) (0x316f8 + (0x1000 * x)) 5360 #define CMIC_CMC0_SBUSDMA_CH2_TM_CONTROL_0_OFFSET (0x3181c) 5361 #define CMIC_CMC1_SBUSDMA_CH2_TM_CONTROL_0_OFFSET (0x3281c) 5362 #define CMIC_CMC2_SBUSDMA_CH2_TM_CONTROL_0_OFFSET (0x3381c) 5363 #define CMIC_CMCx_SBUSDMA_CH2_TM_CONTROL_0_OFFSET(x) (0x3181c + (0x1000 * x)) 5364 #define CMIC_CMC0_SBUSDMA_CH2_TM_CONTROL_1_OFFSET (0x31820) 5365 #define CMIC_CMC1_SBUSDMA_CH2_TM_CONTROL_1_OFFSET (0x32820) 5366 #define CMIC_CMC2_SBUSDMA_CH2_TM_CONTROL_1_OFFSET (0x33820) 5367 #define CMIC_CMCx_SBUSDMA_CH2_TM_CONTROL_1_OFFSET(x) (0x31820 + (0x1000 * x)) 5368 #define CMIC_CMC0_SBUSDMA_CH2_TM_CONTROL_2_OFFSET (0x31824) 5369 #define CMIC_CMC1_SBUSDMA_CH2_TM_CONTROL_2_OFFSET (0x32824) 5370 #define CMIC_CMC2_SBUSDMA_CH2_TM_CONTROL_2_OFFSET (0x33824) 5371 #define CMIC_CMCx_SBUSDMA_CH2_TM_CONTROL_2_OFFSET(x) (0x31824 + (0x1000 * x)) 5372 #define CMIC_CMC0_SCHAN_ACK_DATA_BEAT_COUNT_OFFSET (0x31004) 5373 #define CMIC_CMC1_SCHAN_ACK_DATA_BEAT_COUNT_OFFSET (0x32004) 5374 #define CMIC_CMC2_SCHAN_ACK_DATA_BEAT_COUNT_OFFSET (0x33004) 5375 #define CMIC_CMCx_SCHAN_ACK_DATA_BEAT_COUNT_OFFSET(x) (0x31004 + (0x1000 * x)) 5376 #define CMIC_CMC0_SCHAN_CTRL_OFFSET (0x31000) 5377 #define CMIC_CMC1_SCHAN_CTRL_OFFSET (0x32000) 5378 #define CMIC_CMC2_SCHAN_CTRL_OFFSET (0x33000) 5379 #define CMIC_CMCx_SCHAN_CTRL_OFFSET(x) (0x31000 + (0x1000 * x)) 5380 #define CMIC_CMC0_SCHAN_ERR_OFFSET (0x31008) 5381 #define CMIC_CMC1_SCHAN_ERR_OFFSET (0x32008) 5382 #define CMIC_CMC2_SCHAN_ERR_OFFSET (0x33008) 5383 #define CMIC_CMCx_SCHAN_ERR_OFFSET(x) (0x31008 + (0x1000 * x)) 5384 #define CMIC_CMC0_SCHAN_MESSAGE_OFFSET (0x3100c) 5385 #define CMIC_CMC1_SCHAN_MESSAGE_OFFSET (0x3200c) 5386 #define CMIC_CMC2_SCHAN_MESSAGE_OFFSET (0x3300c) 5387 #define CMIC_CMCx_SCHAN_MESSAGE_OFFSET(x) (0x3100c + (0x1000 * x)) 5388 #define CMIC_CMC0_SCHAN_MESSAGE0_OFFSET (0x3100c) 5389 #define CMIC_CMC1_SCHAN_MESSAGE0_OFFSET (0x3200c) 5390 #define CMIC_CMC2_SCHAN_MESSAGE0_OFFSET (0x3300c) 5391 #define CMIC_CMCx_SCHAN_MESSAGE0_OFFSET(x) (0x3100c + (0x1000 * x)) 5392 #define CMIC_CMC0_SCHAN_MESSAGE1_OFFSET (0x31010) 5393 #define CMIC_CMC1_SCHAN_MESSAGE1_OFFSET (0x32010) 5394 #define CMIC_CMC2_SCHAN_MESSAGE1_OFFSET (0x33010) 5395 #define CMIC_CMCx_SCHAN_MESSAGE1_OFFSET(x) (0x31010 + (0x1000 * x)) 5396 #define CMIC_CMC0_SCHAN_MESSAGE10_OFFSET (0x31034) 5397 #define CMIC_CMC1_SCHAN_MESSAGE10_OFFSET (0x32034) 5398 #define CMIC_CMC2_SCHAN_MESSAGE10_OFFSET (0x33034) 5399 #define CMIC_CMCx_SCHAN_MESSAGE10_OFFSET(x) (0x31034 + (0x1000 * x)) 5400 #define CMIC_CMC0_SCHAN_MESSAGE11_OFFSET (0x31038) 5401 #define CMIC_CMC1_SCHAN_MESSAGE11_OFFSET (0x32038) 5402 #define CMIC_CMC2_SCHAN_MESSAGE11_OFFSET (0x33038) 5403 #define CMIC_CMCx_SCHAN_MESSAGE11_OFFSET(x) (0x31038 + (0x1000 * x)) 5404 #define CMIC_CMC0_SCHAN_MESSAGE12_OFFSET (0x3103c) 5405 #define CMIC_CMC1_SCHAN_MESSAGE12_OFFSET (0x3203c) 5406 #define CMIC_CMC2_SCHAN_MESSAGE12_OFFSET (0x3303c) 5407 #define CMIC_CMCx_SCHAN_MESSAGE12_OFFSET(x) (0x3103c + (0x1000 * x)) 5408 #define CMIC_CMC0_SCHAN_MESSAGE13_OFFSET (0x31040) 5409 #define CMIC_CMC1_SCHAN_MESSAGE13_OFFSET (0x32040) 5410 #define CMIC_CMC2_SCHAN_MESSAGE13_OFFSET (0x33040) 5411 #define CMIC_CMCx_SCHAN_MESSAGE13_OFFSET(x) (0x31040 + (0x1000 * x)) 5412 #define CMIC_CMC0_SCHAN_MESSAGE14_OFFSET (0x31044) 5413 #define CMIC_CMC1_SCHAN_MESSAGE14_OFFSET (0x32044) 5414 #define CMIC_CMC2_SCHAN_MESSAGE14_OFFSET (0x33044) 5415 #define CMIC_CMCx_SCHAN_MESSAGE14_OFFSET(x) (0x31044 + (0x1000 * x)) 5416 #define CMIC_CMC0_SCHAN_MESSAGE15_OFFSET (0x31048) 5417 #define CMIC_CMC1_SCHAN_MESSAGE15_OFFSET (0x32048) 5418 #define CMIC_CMC2_SCHAN_MESSAGE15_OFFSET (0x33048) 5419 #define CMIC_CMCx_SCHAN_MESSAGE15_OFFSET(x) (0x31048 + (0x1000 * x)) 5420 #define CMIC_CMC0_SCHAN_MESSAGE16_OFFSET (0x3104c) 5421 #define CMIC_CMC1_SCHAN_MESSAGE16_OFFSET (0x3204c) 5422 #define CMIC_CMC2_SCHAN_MESSAGE16_OFFSET (0x3304c) 5423 #define CMIC_CMCx_SCHAN_MESSAGE16_OFFSET(x) (0x3104c + (0x1000 * x)) 5424 #define CMIC_CMC0_SCHAN_MESSAGE17_OFFSET (0x31050) 5425 #define CMIC_CMC1_SCHAN_MESSAGE17_OFFSET (0x32050) 5426 #define CMIC_CMC2_SCHAN_MESSAGE17_OFFSET (0x33050) 5427 #define CMIC_CMCx_SCHAN_MESSAGE17_OFFSET(x) (0x31050 + (0x1000 * x)) 5428 #define CMIC_CMC0_SCHAN_MESSAGE18_OFFSET (0x31054) 5429 #define CMIC_CMC1_SCHAN_MESSAGE18_OFFSET (0x32054) 5430 #define CMIC_CMC2_SCHAN_MESSAGE18_OFFSET (0x33054) 5431 #define CMIC_CMCx_SCHAN_MESSAGE18_OFFSET(x) (0x31054 + (0x1000 * x)) 5432 #define CMIC_CMC0_SCHAN_MESSAGE19_OFFSET (0x31058) 5433 #define CMIC_CMC1_SCHAN_MESSAGE19_OFFSET (0x32058) 5434 #define CMIC_CMC2_SCHAN_MESSAGE19_OFFSET (0x33058) 5435 #define CMIC_CMCx_SCHAN_MESSAGE19_OFFSET(x) (0x31058 + (0x1000 * x)) 5436 #define CMIC_CMC0_SCHAN_MESSAGE2_OFFSET (0x31014) 5437 #define CMIC_CMC1_SCHAN_MESSAGE2_OFFSET (0x32014) 5438 #define CMIC_CMC2_SCHAN_MESSAGE2_OFFSET (0x33014) 5439 #define CMIC_CMCx_SCHAN_MESSAGE2_OFFSET(x) (0x31014 + (0x1000 * x)) 5440 #define CMIC_CMC0_SCHAN_MESSAGE20_OFFSET (0x3105c) 5441 #define CMIC_CMC1_SCHAN_MESSAGE20_OFFSET (0x3205c) 5442 #define CMIC_CMC2_SCHAN_MESSAGE20_OFFSET (0x3305c) 5443 #define CMIC_CMCx_SCHAN_MESSAGE20_OFFSET(x) (0x3105c + (0x1000 * x)) 5444 #define CMIC_CMC0_SCHAN_MESSAGE21_OFFSET (0x31060) 5445 #define CMIC_CMC1_SCHAN_MESSAGE21_OFFSET (0x32060) 5446 #define CMIC_CMC2_SCHAN_MESSAGE21_OFFSET (0x33060) 5447 #define CMIC_CMCx_SCHAN_MESSAGE21_OFFSET(x) (0x31060 + (0x1000 * x)) 5448 #define CMIC_CMC0_SCHAN_MESSAGE3_OFFSET (0x31018) 5449 #define CMIC_CMC1_SCHAN_MESSAGE3_OFFSET (0x32018) 5450 #define CMIC_CMC2_SCHAN_MESSAGE3_OFFSET (0x33018) 5451 #define CMIC_CMCx_SCHAN_MESSAGE3_OFFSET(x) (0x31018 + (0x1000 * x)) 5452 #define CMIC_CMC0_SCHAN_MESSAGE4_OFFSET (0x3101c) 5453 #define CMIC_CMC1_SCHAN_MESSAGE4_OFFSET (0x3201c) 5454 #define CMIC_CMC2_SCHAN_MESSAGE4_OFFSET (0x3301c) 5455 #define CMIC_CMCx_SCHAN_MESSAGE4_OFFSET(x) (0x3101c + (0x1000 * x)) 5456 #define CMIC_CMC0_SCHAN_MESSAGE5_OFFSET (0x31020) 5457 #define CMIC_CMC1_SCHAN_MESSAGE5_OFFSET (0x32020) 5458 #define CMIC_CMC2_SCHAN_MESSAGE5_OFFSET (0x33020) 5459 #define CMIC_CMCx_SCHAN_MESSAGE5_OFFSET(x) (0x31020 + (0x1000 * x)) 5460 #define CMIC_CMC0_SCHAN_MESSAGE6_OFFSET (0x31024) 5461 #define CMIC_CMC1_SCHAN_MESSAGE6_OFFSET (0x32024) 5462 #define CMIC_CMC2_SCHAN_MESSAGE6_OFFSET (0x33024) 5463 #define CMIC_CMCx_SCHAN_MESSAGE6_OFFSET(x) (0x31024 + (0x1000 * x)) 5464 #define CMIC_CMC0_SCHAN_MESSAGE7_OFFSET (0x31028) 5465 #define CMIC_CMC1_SCHAN_MESSAGE7_OFFSET (0x32028) 5466 #define CMIC_CMC2_SCHAN_MESSAGE7_OFFSET (0x33028) 5467 #define CMIC_CMCx_SCHAN_MESSAGE7_OFFSET(x) (0x31028 + (0x1000 * x)) 5468 #define CMIC_CMC0_SCHAN_MESSAGE8_OFFSET (0x3102c) 5469 #define CMIC_CMC1_SCHAN_MESSAGE8_OFFSET (0x3202c) 5470 #define CMIC_CMC2_SCHAN_MESSAGE8_OFFSET (0x3302c) 5471 #define CMIC_CMCx_SCHAN_MESSAGE8_OFFSET(x) (0x3102c + (0x1000 * x)) 5472 #define CMIC_CMC0_SCHAN_MESSAGE9_OFFSET (0x31030) 5473 #define CMIC_CMC1_SCHAN_MESSAGE9_OFFSET (0x32030) 5474 #define CMIC_CMC2_SCHAN_MESSAGE9_OFFSET (0x33030) 5475 #define CMIC_CMCx_SCHAN_MESSAGE9_OFFSET(x) (0x31030 + (0x1000 * x)) 5476 #define CMIC_CMC0_SLAM_DMA_CFG_OFFSET (0x3120c) 5477 #define CMIC_CMC1_SLAM_DMA_CFG_OFFSET (0x3220c) 5478 #define CMIC_CMC2_SLAM_DMA_CFG_OFFSET (0x3320c) 5479 #define CMIC_CMCx_SLAM_DMA_CFG_OFFSET(x) (0x3120c + (0x1000 * x)) 5480 #define CMIC_CMC0_SLAM_DMA_CUR_ENTRY_SBUS_ADDR_OFFSET (0x31214) 5481 #define CMIC_CMC1_SLAM_DMA_CUR_ENTRY_SBUS_ADDR_OFFSET (0x32214) 5482 #define CMIC_CMC2_SLAM_DMA_CUR_ENTRY_SBUS_ADDR_OFFSET (0x33214) 5483 #define CMIC_CMCx_SLAM_DMA_CUR_ENTRY_SBUS_ADDR_OFFSET(x) (0x31214 + (0x1000 * x)) 5484 #define CMIC_CMC0_SLAM_DMA_ENTRY_COUNT_OFFSET (0x31208) 5485 #define CMIC_CMC1_SLAM_DMA_ENTRY_COUNT_OFFSET (0x32208) 5486 #define CMIC_CMC2_SLAM_DMA_ENTRY_COUNT_OFFSET (0x33208) 5487 #define CMIC_CMCx_SLAM_DMA_ENTRY_COUNT_OFFSET(x) (0x31208 + (0x1000 * x)) 5488 #define CMIC_CMC0_SLAM_DMA_PCIMEM_START_ADDR_OFFSET (0x31200) 5489 #define CMIC_CMC1_SLAM_DMA_PCIMEM_START_ADDR_OFFSET (0x32200) 5490 #define CMIC_CMC2_SLAM_DMA_PCIMEM_START_ADDR_OFFSET (0x33200) 5491 #define CMIC_CMCx_SLAM_DMA_PCIMEM_START_ADDR_OFFSET(x) (0x31200 + (0x1000 * x)) 5492 #define CMIC_CMC0_SLAM_DMA_SBUS_CMD_CONFIG_OFFSET (0x31218) 5493 #define CMIC_CMC1_SLAM_DMA_SBUS_CMD_CONFIG_OFFSET (0x32218) 5494 #define CMIC_CMC2_SLAM_DMA_SBUS_CMD_CONFIG_OFFSET (0x33218) 5495 #define CMIC_CMCx_SLAM_DMA_SBUS_CMD_CONFIG_OFFSET(x) (0x31218 + (0x1000 * x)) 5496 #define CMIC_CMC0_SLAM_DMA_SBUS_START_ADDR_OFFSET (0x31204) 5497 #define CMIC_CMC1_SLAM_DMA_SBUS_START_ADDR_OFFSET (0x32204) 5498 #define CMIC_CMC2_SLAM_DMA_SBUS_START_ADDR_OFFSET (0x33204) 5499 #define CMIC_CMCx_SLAM_DMA_SBUS_START_ADDR_OFFSET(x) (0x31204 + (0x1000 * x)) 5500 #define CMIC_CMC0_SLAM_DMA_STAT_OFFSET (0x31210) 5501 #define CMIC_CMC1_SLAM_DMA_STAT_OFFSET (0x32210) 5502 #define CMIC_CMC2_SLAM_DMA_STAT_OFFSET (0x33210) 5503 #define CMIC_CMCx_SLAM_DMA_STAT_OFFSET(x) (0x31210 + (0x1000 * x)) 5504 #define CMIC_CMC0_STAT_OFFSET (0x3110c) 5505 #define CMIC_CMC1_STAT_OFFSET (0x3210c) 5506 #define CMIC_CMC2_STAT_OFFSET (0x3310c) 5507 #define CMIC_CMCx_STAT_OFFSET(x) (0x3110c + (0x1000 * x)) 5508 #define CMIC_CMC0_STAT_DMA_ADDR_OFFSET (0x311c0) 5509 #define CMIC_CMC1_STAT_DMA_ADDR_OFFSET (0x321c0) 5510 #define CMIC_CMC2_STAT_DMA_ADDR_OFFSET (0x331c0) 5511 #define CMIC_CMCx_STAT_DMA_ADDR_OFFSET(x) (0x311c0 + (0x1000 * x)) 5512 #define CMIC_CMC0_STAT_DMA_CFG_OFFSET (0x311c4) 5513 #define CMIC_CMC1_STAT_DMA_CFG_OFFSET (0x321c4) 5514 #define CMIC_CMC2_STAT_DMA_CFG_OFFSET (0x331c4) 5515 #define CMIC_CMCx_STAT_DMA_CFG_OFFSET(x) (0x311c4 + (0x1000 * x)) 5516 #define CMIC_CMC0_STAT_DMA_CURRENT_OFFSET (0x311d4) 5517 #define CMIC_CMC1_STAT_DMA_CURRENT_OFFSET (0x321d4) 5518 #define CMIC_CMC2_STAT_DMA_CURRENT_OFFSET (0x331d4) 5519 #define CMIC_CMCx_STAT_DMA_CURRENT_OFFSET(x) (0x311d4 + (0x1000 * x)) 5520 #define CMIC_CMC0_STAT_DMA_PORTS_0_OFFSET (0x311c8) 5521 #define CMIC_CMC1_STAT_DMA_PORTS_0_OFFSET (0x321c8) 5522 #define CMIC_CMC2_STAT_DMA_PORTS_0_OFFSET (0x331c8) 5523 #define CMIC_CMCx_STAT_DMA_PORTS_0_OFFSET(x) (0x311c8 + (0x1000 * x)) 5524 #define CMIC_CMC0_STAT_DMA_PORTS_1_OFFSET (0x311cc) 5525 #define CMIC_CMC1_STAT_DMA_PORTS_1_OFFSET (0x321cc) 5526 #define CMIC_CMC2_STAT_DMA_PORTS_1_OFFSET (0x331cc) 5527 #define CMIC_CMCx_STAT_DMA_PORTS_1_OFFSET(x) (0x311cc + (0x1000 * x)) 5528 #define CMIC_CMC0_STAT_DMA_PORTS_2_OFFSET (0x311d0) 5529 #define CMIC_CMC1_STAT_DMA_PORTS_2_OFFSET (0x321d0) 5530 #define CMIC_CMC2_STAT_DMA_PORTS_2_OFFSET (0x331d0) 5531 #define CMIC_CMCx_STAT_DMA_PORTS_2_OFFSET(x) (0x311d0 + (0x1000 * x)) 5532 #define CMIC_CMC0_STAT_DMA_SBUS_START_ADDRESS_OFFSET (0x311d8) 5533 #define CMIC_CMC1_STAT_DMA_SBUS_START_ADDRESS_OFFSET (0x321d8) 5534 #define CMIC_CMC2_STAT_DMA_SBUS_START_ADDRESS_OFFSET (0x331d8) 5535 #define CMIC_CMCx_STAT_DMA_SBUS_START_ADDRESS_OFFSET(x) (0x311d8 + (0x1000 * x)) 5536 #define CMIC_CMC0_STAT_DMA_STAT_OFFSET (0x311dc) 5537 #define CMIC_CMC1_STAT_DMA_STAT_OFFSET (0x321dc) 5538 #define CMIC_CMC2_STAT_DMA_STAT_OFFSET (0x331dc) 5539 #define CMIC_CMCx_STAT_DMA_STAT_OFFSET(x) (0x311dc + (0x1000 * x)) 5540 #define CMIC_CMC0_SW_INTR_CONFIG_OFFSET (0x314a8) 5541 #define CMIC_CMC1_SW_INTR_CONFIG_OFFSET (0x324a8) 5542 #define CMIC_CMC2_SW_INTR_CONFIG_OFFSET (0x334a8) 5543 #define CMIC_CMCx_SW_INTR_CONFIG_OFFSET(x) (0x314a8 + (0x1000 * x)) 5544 #define CMIC_CMC0_TABLE_DMA_CFG_OFFSET (0x3124c) 5545 #define CMIC_CMC1_TABLE_DMA_CFG_OFFSET (0x3224c) 5546 #define CMIC_CMC2_TABLE_DMA_CFG_OFFSET (0x3324c) 5547 #define CMIC_CMCx_TABLE_DMA_CFG_OFFSET(x) (0x3124c + (0x1000 * x)) 5548 #define CMIC_CMC0_TABLE_DMA_CUR_ENTRY_SBUS_ADDR_OFFSET (0x31254) 5549 #define CMIC_CMC1_TABLE_DMA_CUR_ENTRY_SBUS_ADDR_OFFSET (0x32254) 5550 #define CMIC_CMC2_TABLE_DMA_CUR_ENTRY_SBUS_ADDR_OFFSET (0x33254) 5551 #define CMIC_CMCx_TABLE_DMA_CUR_ENTRY_SBUS_ADDR_OFFSET(x) (0x31254 + (0x1000 * x)) 5552 #define CMIC_CMC0_TABLE_DMA_ENTRY_COUNT_OFFSET (0x31248) 5553 #define CMIC_CMC1_TABLE_DMA_ENTRY_COUNT_OFFSET (0x32248) 5554 #define CMIC_CMC2_TABLE_DMA_ENTRY_COUNT_OFFSET (0x33248) 5555 #define CMIC_CMCx_TABLE_DMA_ENTRY_COUNT_OFFSET(x) (0x31248 + (0x1000 * x)) 5556 #define CMIC_CMC0_TABLE_DMA_PCIMEM_START_ADDR_OFFSET (0x31240) 5557 #define CMIC_CMC1_TABLE_DMA_PCIMEM_START_ADDR_OFFSET (0x32240) 5558 #define CMIC_CMC2_TABLE_DMA_PCIMEM_START_ADDR_OFFSET (0x33240) 5559 #define CMIC_CMCx_TABLE_DMA_PCIMEM_START_ADDR_OFFSET(x) (0x31240 + (0x1000 * x)) 5560 #define CMIC_CMC0_TABLE_DMA_SBUS_CMD_CONFIG_OFFSET (0x31258) 5561 #define CMIC_CMC1_TABLE_DMA_SBUS_CMD_CONFIG_OFFSET (0x32258) 5562 #define CMIC_CMC2_TABLE_DMA_SBUS_CMD_CONFIG_OFFSET (0x33258) 5563 #define CMIC_CMCx_TABLE_DMA_SBUS_CMD_CONFIG_OFFSET(x) (0x31258 + (0x1000 * x)) 5564 #define CMIC_CMC0_TABLE_DMA_SBUS_START_ADDR_OFFSET (0x31244) 5565 #define CMIC_CMC1_TABLE_DMA_SBUS_START_ADDR_OFFSET (0x32244) 5566 #define CMIC_CMC2_TABLE_DMA_SBUS_START_ADDR_OFFSET (0x33244) 5567 #define CMIC_CMCx_TABLE_DMA_SBUS_START_ADDR_OFFSET(x) (0x31244 + (0x1000 * x)) 5568 #define CMIC_CMC0_TABLE_DMA_STAT_OFFSET (0x31250) 5569 #define CMIC_CMC1_TABLE_DMA_STAT_OFFSET (0x32250) 5570 #define CMIC_CMC2_TABLE_DMA_STAT_OFFSET (0x33250) 5571 #define CMIC_CMCx_TABLE_DMA_STAT_OFFSET(x) (0x31250 + (0x1000 * x)) 5572 #define CMIC_CMC0_TM_CONTROL_0_OFFSET (0x31100) 5573 #define CMIC_CMC1_TM_CONTROL_0_OFFSET (0x32100) 5574 #define CMIC_CMC2_TM_CONTROL_0_OFFSET (0x33100) 5575 #define CMIC_CMCx_TM_CONTROL_0_OFFSET(x) (0x31100 + (0x1000 * x)) 5576 #define CMIC_CMC0_TM_CONTROL_1_OFFSET (0x31104) 5577 #define CMIC_CMC1_TM_CONTROL_1_OFFSET (0x32104) 5578 #define CMIC_CMC2_TM_CONTROL_1_OFFSET (0x33104) 5579 #define CMIC_CMCx_TM_CONTROL_1_OFFSET(x) (0x31104 + (0x1000 * x)) 5580 #define CMIC_CMC0_UC0_IRQ_MASK0_OFFSET (0x31428) 5581 #define CMIC_CMC1_UC0_IRQ_MASK0_OFFSET (0x32428) 5582 #define CMIC_CMC2_UC0_IRQ_MASK0_OFFSET (0x33428) 5583 #define CMIC_CMCx_UC0_IRQ_MASK0_OFFSET(x) (0x31428 + (0x1000 * x)) 5584 #define CMIC_CMC0_UC0_IRQ_MASK1_OFFSET (0x3142c) 5585 #define CMIC_CMC1_UC0_IRQ_MASK1_OFFSET (0x3242c) 5586 #define CMIC_CMC2_UC0_IRQ_MASK1_OFFSET (0x3342c) 5587 #define CMIC_CMCx_UC0_IRQ_MASK1_OFFSET(x) (0x3142c + (0x1000 * x)) 5588 #define CMIC_CMC0_UC0_IRQ_MASK2_OFFSET (0x31430) 5589 #define CMIC_CMC1_UC0_IRQ_MASK2_OFFSET (0x32430) 5590 #define CMIC_CMC2_UC0_IRQ_MASK2_OFFSET (0x33430) 5591 #define CMIC_CMCx_UC0_IRQ_MASK2_OFFSET(x) (0x31430 + (0x1000 * x)) 5592 #define CMIC_CMC0_UC0_IRQ_MASK3_OFFSET (0x31434) 5593 #define CMIC_CMC1_UC0_IRQ_MASK3_OFFSET (0x32434) 5594 #define CMIC_CMC2_UC0_IRQ_MASK3_OFFSET (0x33434) 5595 #define CMIC_CMCx_UC0_IRQ_MASK3_OFFSET(x) (0x31434 + (0x1000 * x)) 5596 #define CMIC_CMC0_UC0_IRQ_MASK4_OFFSET (0x31438) 5597 #define CMIC_CMC1_UC0_IRQ_MASK4_OFFSET (0x32438) 5598 #define CMIC_CMC2_UC0_IRQ_MASK4_OFFSET (0x33438) 5599 #define CMIC_CMCx_UC0_IRQ_MASK4_OFFSET(x) (0x31438 + (0x1000 * x)) 5600 #define CMIC_CMC0_UC0_IRQ_MASK5_OFFSET (0x314c0) 5601 #define CMIC_CMC1_UC0_IRQ_MASK5_OFFSET (0x324c0) 5602 #define CMIC_CMC2_UC0_IRQ_MASK5_OFFSET (0x334c0) 5603 #define CMIC_CMCx_UC0_IRQ_MASK5_OFFSET(x) (0x314c0 + (0x1000 * x)) 5604 #define CMIC_CMC0_UC0_IRQ_MASK6_OFFSET (0x314c4) 5605 #define CMIC_CMC1_UC0_IRQ_MASK6_OFFSET (0x324c4) 5606 #define CMIC_CMC2_UC0_IRQ_MASK6_OFFSET (0x334c4) 5607 #define CMIC_CMCx_UC0_IRQ_MASK6_OFFSET(x) (0x314c4 + (0x1000 * x)) 5608 #define CMIC_CMC0_UC1_IRQ_MASK0_OFFSET (0x3143c) 5609 #define CMIC_CMC1_UC1_IRQ_MASK0_OFFSET (0x3243c) 5610 #define CMIC_CMC2_UC1_IRQ_MASK0_OFFSET (0x3343c) 5611 #define CMIC_CMCx_UC1_IRQ_MASK0_OFFSET(x) (0x3143c + (0x1000 * x)) 5612 #define CMIC_CMC0_UC1_IRQ_MASK1_OFFSET (0x31440) 5613 #define CMIC_CMC1_UC1_IRQ_MASK1_OFFSET (0x32440) 5614 #define CMIC_CMC2_UC1_IRQ_MASK1_OFFSET (0x33440) 5615 #define CMIC_CMCx_UC1_IRQ_MASK1_OFFSET(x) (0x31440 + (0x1000 * x)) 5616 #define CMIC_CMC0_UC1_IRQ_MASK2_OFFSET (0x31444) 5617 #define CMIC_CMC1_UC1_IRQ_MASK2_OFFSET (0x32444) 5618 #define CMIC_CMC2_UC1_IRQ_MASK2_OFFSET (0x33444) 5619 #define CMIC_CMCx_UC1_IRQ_MASK2_OFFSET(x) (0x31444 + (0x1000 * x)) 5620 #define CMIC_CMC0_UC1_IRQ_MASK3_OFFSET (0x31448) 5621 #define CMIC_CMC1_UC1_IRQ_MASK3_OFFSET (0x32448) 5622 #define CMIC_CMC2_UC1_IRQ_MASK3_OFFSET (0x33448) 5623 #define CMIC_CMCx_UC1_IRQ_MASK3_OFFSET(x) (0x31448 + (0x1000 * x)) 5624 #define CMIC_CMC0_UC1_IRQ_MASK4_OFFSET (0x3144c) 5625 #define CMIC_CMC1_UC1_IRQ_MASK4_OFFSET (0x3244c) 5626 #define CMIC_CMC2_UC1_IRQ_MASK4_OFFSET (0x3344c) 5627 #define CMIC_CMCx_UC1_IRQ_MASK4_OFFSET(x) (0x3144c + (0x1000 * x)) 5628 #define CMIC_CMC0_UC1_IRQ_MASK5_OFFSET (0x314c8) 5629 #define CMIC_CMC1_UC1_IRQ_MASK5_OFFSET (0x324c8) 5630 #define CMIC_CMC2_UC1_IRQ_MASK5_OFFSET (0x334c8) 5631 #define CMIC_CMCx_UC1_IRQ_MASK5_OFFSET(x) (0x314c8 + (0x1000 * x)) 5632 #define CMIC_CMC0_UC1_IRQ_MASK6_OFFSET (0x314cc) 5633 #define CMIC_CMC1_UC1_IRQ_MASK6_OFFSET (0x324cc) 5634 #define CMIC_CMC2_UC1_IRQ_MASK6_OFFSET (0x334cc) 5635 #define CMIC_CMCx_UC1_IRQ_MASK6_OFFSET(x) (0x314cc + (0x1000 * x)) 5636 #define CMIC_COMMON_BSPI_BIGENDIAN_OFFSET (0x10238) 5637 #define CMIC_COMMON_I2C_PIO_ENDIANESS_OFFSET (0x101fc) 5638 #define CMIC_COMMON_MIIM_ADDRESS_OFFSET (0x10088) 5639 #define CMIC_COMMON_MIIM_CTRL_OFFSET (0x1008c) 5640 #define CMIC_COMMON_MIIM_PARAM_OFFSET (0x10080) 5641 #define CMIC_COMMON_MIIM_READ_DATA_OFFSET (0x10084) 5642 #define CMIC_COMMON_MIIM_STAT_OFFSET (0x10090) 5643 #define CMIC_COMMON_PCIE_PIO_ENDIANESS_OFFSET (0x101ec) 5644 #define CMIC_COMMON_RPE_PIO_ENDIANESS_OFFSET (0x10200) 5645 #define CMIC_COMMON_SCHAN_ACK_DATA_BEAT_COUNT_OFFSET (0x10004) 5646 #define CMIC_COMMON_SCHAN_CTRL_OFFSET (0x10000) 5647 #define CMIC_COMMON_SCHAN_ERR_OFFSET (0x10008) 5648 #define CMIC_COMMON_SCHAN_MESSAGE_OFFSET (0x1000c) 5649 #define CMIC_COMMON_SCHAN_MESSAGE0_OFFSET (0x1000c) 5650 #define CMIC_COMMON_SCHAN_MESSAGE1_OFFSET (0x10010) 5651 #define CMIC_COMMON_SCHAN_MESSAGE10_OFFSET (0x10034) 5652 #define CMIC_COMMON_SCHAN_MESSAGE11_OFFSET (0x10038) 5653 #define CMIC_COMMON_SCHAN_MESSAGE12_OFFSET (0x1003c) 5654 #define CMIC_COMMON_SCHAN_MESSAGE13_OFFSET (0x10040) 5655 #define CMIC_COMMON_SCHAN_MESSAGE14_OFFSET (0x10044) 5656 #define CMIC_COMMON_SCHAN_MESSAGE15_OFFSET (0x10048) 5657 #define CMIC_COMMON_SCHAN_MESSAGE16_OFFSET (0x1004c) 5658 #define CMIC_COMMON_SCHAN_MESSAGE17_OFFSET (0x10050) 5659 #define CMIC_COMMON_SCHAN_MESSAGE18_OFFSET (0x10054) 5660 #define CMIC_COMMON_SCHAN_MESSAGE19_OFFSET (0x10058) 5661 #define CMIC_COMMON_SCHAN_MESSAGE2_OFFSET (0x10014) 5662 #define CMIC_COMMON_SCHAN_MESSAGE20_OFFSET (0x1005c) 5663 #define CMIC_COMMON_SCHAN_MESSAGE21_OFFSET (0x10060) 5664 #define CMIC_COMMON_SCHAN_MESSAGE3_OFFSET (0x10018) 5665 #define CMIC_COMMON_SCHAN_MESSAGE4_OFFSET (0x1001c) 5666 #define CMIC_COMMON_SCHAN_MESSAGE5_OFFSET (0x10020) 5667 #define CMIC_COMMON_SCHAN_MESSAGE6_OFFSET (0x10024) 5668 #define CMIC_COMMON_SCHAN_MESSAGE7_OFFSET (0x10028) 5669 #define CMIC_COMMON_SCHAN_MESSAGE8_OFFSET (0x1002c) 5670 #define CMIC_COMMON_SCHAN_MESSAGE9_OFFSET (0x10030) 5671 #define CMIC_COMMON_SPI_PIO_ENDIANESS_OFFSET (0x101f8) 5672 #define CMIC_COMMON_STRAP_STATUS_0_OFFSET (0x10240) 5673 #define CMIC_COMMON_STRAP_STATUS_1_OFFSET (0x10244) 5674 #define CMIC_COMMON_UC0_PIO_ENDIANESS_OFFSET (0x101f0) 5675 #define CMIC_COMMON_UC1_PIO_ENDIANESS_OFFSET (0x101f4) 5676 #define CMIC_CPS_RESET_OFFSET (0x10220) 5677 #define CMIC_DEV_REV_ID_OFFSET (0x10224) 5678 #define CMIC_DMA_IC_AR_ARB_MI0_OFFSET (0x1d408) 5679 #define CMIC_DMA_IC_AR_ARB_MI1_OFFSET (0x1d428) 5680 #define CMIC_DMA_IC_AW_ARB_MI0_OFFSET (0x1d40c) 5681 #define CMIC_DMA_IC_AW_ARB_MI1_OFFSET (0x1d42c) 5682 #define CMIC_DMA_IC_CFG_REG_0_OFFSET (0x1dfc0) 5683 #define CMIC_DMA_IC_CFG_REG_1_OFFSET (0x1dfc4) 5684 #define CMIC_DMA_IC_CFG_REG_2_OFFSET (0x1dfcc) 5685 #define CMIC_DMA_IC_ID_REG_0_OFFSET (0x1dff0) 5686 #define CMIC_DMA_IC_ID_REG_1_OFFSET (0x1dff4) 5687 #define CMIC_DMA_IC_ID_REG_2_OFFSET (0x1dff8) 5688 #define CMIC_DMA_IC_ID_REG_3_OFFSET (0x1dffc) 5689 #define CMIC_DMA_IC_PER_REG_0_OFFSET (0x1dfe0) 5690 #define CMIC_DMA_IC_PER_REG_1_OFFSET (0x1dfe4) 5691 #define CMIC_DMA_IC_PER_REG_2_OFFSET (0x1dfe8) 5692 #define CMIC_DMA_IC_PER_REG_3_OFFSET (0x1dfec) 5693 #define CMIC_FINE_GRAIN_COUNTERS_CTRL_OFFSET (0x25000) 5694 #define CMIC_FINE_GRAIN_COUNTERS_NS_VALUE_OFFSET (0x25004) 5695 #define CMIC_FINE_GRAIN_COUNTERS_SECOND_VALUE_OFFSET (0x25008) 5696 #define CMIC_FSCHAN_ADDRESS_OFFSET (0x30070) 5697 #define CMIC_FSCHAN_DATA32_OFFSET (0x30074) 5698 #define CMIC_FSCHAN_DATA64_HI_OFFSET (0x3007c) 5699 #define CMIC_FSCHAN_DATA64_LO_OFFSET (0x30078) 5700 #define CMIC_FSCHAN_ENABLE_PROGRAMMABLE_OPCODE_OFFSET (0x30064) 5701 #define CMIC_FSCHAN_OPCODE_OFFSET (0x3006c) 5702 #define CMIC_FSCHAN_STATUS_OFFSET (0x30068) 5703 #define CMIC_FSRF_STBY_CONTROL_OFFSET (0x10248) 5704 #define CMIC_GP_AUX_SEL_OFFSET (0x2028) 5705 #define CMIC_GP_DATA_IN_OFFSET (0x2000) 5706 #define CMIC_GP_DATA_OUT_OFFSET (0x2004) 5707 #define CMIC_GP_INIT_VAL_OFFSET (0x2030) 5708 #define CMIC_GP_INT_CLR_OFFSET (0x2024) 5709 #define CMIC_GP_INT_DE_OFFSET (0x2010) 5710 #define CMIC_GP_INT_EDGE_OFFSET (0x2014) 5711 #define CMIC_GP_INT_MSK_OFFSET (0x2018) 5712 #define CMIC_GP_INT_MSTAT_OFFSET (0x2020) 5713 #define CMIC_GP_INT_STAT_OFFSET (0x201c) 5714 #define CMIC_GP_INT_TYPE_OFFSET (0x200c) 5715 #define CMIC_GP_OUT_EN_OFFSET (0x2008) 5716 #define CMIC_GP_PAD_RES_OFFSET (0x2034) 5717 #define CMIC_GP_PRB_ENABLE_OFFSET (0x2048) 5718 #define CMIC_GP_PRB_OE_OFFSET (0x204c) 5719 #define CMIC_GP_RES_EN_OFFSET (0x2038) 5720 #define CMIC_GP_TEST_ENABLE_OFFSET (0x2044) 5721 #define CMIC_GP_TEST_INPUT_OFFSET (0x203c) 5722 #define CMIC_GP_TEST_OUTPUT_OFFSET (0x2040) 5723 #define CMIC_I2CM_SMBUS_ADDRESS_OFFSET (0x8) 5724 #define CMIC_I2CM_SMBUS_BIT_BANG_CONTROL_OFFSET (0x14) 5725 #define CMIC_I2CM_SMBUS_CONFIG_OFFSET (0x0) 5726 #define CMIC_I2CM_SMBUS_EVENT_ENABLE_OFFSET (0x38) 5727 #define CMIC_I2CM_SMBUS_EVENT_STATUS_OFFSET (0x3c) 5728 #define CMIC_I2CM_SMBUS_MASTER_COMMAND_OFFSET (0x30) 5729 #define CMIC_I2CM_SMBUS_MASTER_DATA_READ_OFFSET (0x44) 5730 #define CMIC_I2CM_SMBUS_MASTER_DATA_WRITE_OFFSET (0x40) 5731 #define CMIC_I2CM_SMBUS_MASTER_FIFO_CONTROL_OFFSET (0xc) 5732 #define CMIC_I2CM_SMBUS_SLAVE_COMMAND_OFFSET (0x34) 5733 #define CMIC_I2CM_SMBUS_SLAVE_DATA_READ_OFFSET (0x4c) 5734 #define CMIC_I2CM_SMBUS_SLAVE_DATA_WRITE_OFFSET (0x48) 5735 #define CMIC_I2CM_SMBUS_SLAVE_FIFO_CONTROL_OFFSET (0x10) 5736 #define CMIC_I2CM_SMBUS_TIMING_CONFIG_OFFSET (0x4) 5737 #define CMIC_INTR_PKT_PACING_DELAY_OFFSET (0x22244) 5738 #define CMIC_LEDUP0_CLK_DIV_OFFSET (0x2005c) 5739 #define CMIC_LEDUP0_CLK_PARAMS_OFFSET (0x20050) 5740 #define CMIC_LEDUP0_CTRL_OFFSET (0x20000) 5741 #define CMIC_LEDUP0_DATA_RAM_OFFSET (0x20400) 5742 #define CMIC_LEDUP0_DATA_RAM0_OFFSET (0x20400) 5743 #define CMIC_LEDUP0_DATA_RAM1_OFFSET (0x20404) 5744 #define CMIC_LEDUP0_DATA_RAM10_OFFSET (0x20428) 5745 #define CMIC_LEDUP0_DATA_RAM100_OFFSET (0x20590) 5746 #define CMIC_LEDUP0_DATA_RAM101_OFFSET (0x20594) 5747 #define CMIC_LEDUP0_DATA_RAM102_OFFSET (0x20598) 5748 #define CMIC_LEDUP0_DATA_RAM103_OFFSET (0x2059c) 5749 #define CMIC_LEDUP0_DATA_RAM104_OFFSET (0x205a0) 5750 #define CMIC_LEDUP0_DATA_RAM105_OFFSET (0x205a4) 5751 #define CMIC_LEDUP0_DATA_RAM106_OFFSET (0x205a8) 5752 #define CMIC_LEDUP0_DATA_RAM107_OFFSET (0x205ac) 5753 #define CMIC_LEDUP0_DATA_RAM108_OFFSET (0x205b0) 5754 #define CMIC_LEDUP0_DATA_RAM109_OFFSET (0x205b4) 5755 #define CMIC_LEDUP0_DATA_RAM11_OFFSET (0x2042c) 5756 #define CMIC_LEDUP0_DATA_RAM110_OFFSET (0x205b8) 5757 #define CMIC_LEDUP0_DATA_RAM111_OFFSET (0x205bc) 5758 #define CMIC_LEDUP0_DATA_RAM112_OFFSET (0x205c0) 5759 #define CMIC_LEDUP0_DATA_RAM113_OFFSET (0x205c4) 5760 #define CMIC_LEDUP0_DATA_RAM114_OFFSET (0x205c8) 5761 #define CMIC_LEDUP0_DATA_RAM115_OFFSET (0x205cc) 5762 #define CMIC_LEDUP0_DATA_RAM116_OFFSET (0x205d0) 5763 #define CMIC_LEDUP0_DATA_RAM117_OFFSET (0x205d4) 5764 #define CMIC_LEDUP0_DATA_RAM118_OFFSET (0x205d8) 5765 #define CMIC_LEDUP0_DATA_RAM119_OFFSET (0x205dc) 5766 #define CMIC_LEDUP0_DATA_RAM12_OFFSET (0x20430) 5767 #define CMIC_LEDUP0_DATA_RAM120_OFFSET (0x205e0) 5768 #define CMIC_LEDUP0_DATA_RAM121_OFFSET (0x205e4) 5769 #define CMIC_LEDUP0_DATA_RAM122_OFFSET (0x205e8) 5770 #define CMIC_LEDUP0_DATA_RAM123_OFFSET (0x205ec) 5771 #define CMIC_LEDUP0_DATA_RAM124_OFFSET (0x205f0) 5772 #define CMIC_LEDUP0_DATA_RAM125_OFFSET (0x205f4) 5773 #define CMIC_LEDUP0_DATA_RAM126_OFFSET (0x205f8) 5774 #define CMIC_LEDUP0_DATA_RAM127_OFFSET (0x205fc) 5775 #define CMIC_LEDUP0_DATA_RAM128_OFFSET (0x20600) 5776 #define CMIC_LEDUP0_DATA_RAM129_OFFSET (0x20604) 5777 #define CMIC_LEDUP0_DATA_RAM13_OFFSET (0x20434) 5778 #define CMIC_LEDUP0_DATA_RAM130_OFFSET (0x20608) 5779 #define CMIC_LEDUP0_DATA_RAM131_OFFSET (0x2060c) 5780 #define CMIC_LEDUP0_DATA_RAM132_OFFSET (0x20610) 5781 #define CMIC_LEDUP0_DATA_RAM133_OFFSET (0x20614) 5782 #define CMIC_LEDUP0_DATA_RAM134_OFFSET (0x20618) 5783 #define CMIC_LEDUP0_DATA_RAM135_OFFSET (0x2061c) 5784 #define CMIC_LEDUP0_DATA_RAM136_OFFSET (0x20620) 5785 #define CMIC_LEDUP0_DATA_RAM137_OFFSET (0x20624) 5786 #define CMIC_LEDUP0_DATA_RAM138_OFFSET (0x20628) 5787 #define CMIC_LEDUP0_DATA_RAM139_OFFSET (0x2062c) 5788 #define CMIC_LEDUP0_DATA_RAM14_OFFSET (0x20438) 5789 #define CMIC_LEDUP0_DATA_RAM140_OFFSET (0x20630) 5790 #define CMIC_LEDUP0_DATA_RAM141_OFFSET (0x20634) 5791 #define CMIC_LEDUP0_DATA_RAM142_OFFSET (0x20638) 5792 #define CMIC_LEDUP0_DATA_RAM143_OFFSET (0x2063c) 5793 #define CMIC_LEDUP0_DATA_RAM144_OFFSET (0x20640) 5794 #define CMIC_LEDUP0_DATA_RAM145_OFFSET (0x20644) 5795 #define CMIC_LEDUP0_DATA_RAM146_OFFSET (0x20648) 5796 #define CMIC_LEDUP0_DATA_RAM147_OFFSET (0x2064c) 5797 #define CMIC_LEDUP0_DATA_RAM148_OFFSET (0x20650) 5798 #define CMIC_LEDUP0_DATA_RAM149_OFFSET (0x20654) 5799 #define CMIC_LEDUP0_DATA_RAM15_OFFSET (0x2043c) 5800 #define CMIC_LEDUP0_DATA_RAM150_OFFSET (0x20658) 5801 #define CMIC_LEDUP0_DATA_RAM151_OFFSET (0x2065c) 5802 #define CMIC_LEDUP0_DATA_RAM152_OFFSET (0x20660) 5803 #define CMIC_LEDUP0_DATA_RAM153_OFFSET (0x20664) 5804 #define CMIC_LEDUP0_DATA_RAM154_OFFSET (0x20668) 5805 #define CMIC_LEDUP0_DATA_RAM155_OFFSET (0x2066c) 5806 #define CMIC_LEDUP0_DATA_RAM156_OFFSET (0x20670) 5807 #define CMIC_LEDUP0_DATA_RAM157_OFFSET (0x20674) 5808 #define CMIC_LEDUP0_DATA_RAM158_OFFSET (0x20678) 5809 #define CMIC_LEDUP0_DATA_RAM159_OFFSET (0x2067c) 5810 #define CMIC_LEDUP0_DATA_RAM16_OFFSET (0x20440) 5811 #define CMIC_LEDUP0_DATA_RAM160_OFFSET (0x20680) 5812 #define CMIC_LEDUP0_DATA_RAM161_OFFSET (0x20684) 5813 #define CMIC_LEDUP0_DATA_RAM162_OFFSET (0x20688) 5814 #define CMIC_LEDUP0_DATA_RAM163_OFFSET (0x2068c) 5815 #define CMIC_LEDUP0_DATA_RAM164_OFFSET (0x20690) 5816 #define CMIC_LEDUP0_DATA_RAM165_OFFSET (0x20694) 5817 #define CMIC_LEDUP0_DATA_RAM166_OFFSET (0x20698) 5818 #define CMIC_LEDUP0_DATA_RAM167_OFFSET (0x2069c) 5819 #define CMIC_LEDUP0_DATA_RAM168_OFFSET (0x206a0) 5820 #define CMIC_LEDUP0_DATA_RAM169_OFFSET (0x206a4) 5821 #define CMIC_LEDUP0_DATA_RAM17_OFFSET (0x20444) 5822 #define CMIC_LEDUP0_DATA_RAM170_OFFSET (0x206a8) 5823 #define CMIC_LEDUP0_DATA_RAM171_OFFSET (0x206ac) 5824 #define CMIC_LEDUP0_DATA_RAM172_OFFSET (0x206b0) 5825 #define CMIC_LEDUP0_DATA_RAM173_OFFSET (0x206b4) 5826 #define CMIC_LEDUP0_DATA_RAM174_OFFSET (0x206b8) 5827 #define CMIC_LEDUP0_DATA_RAM175_OFFSET (0x206bc) 5828 #define CMIC_LEDUP0_DATA_RAM176_OFFSET (0x206c0) 5829 #define CMIC_LEDUP0_DATA_RAM177_OFFSET (0x206c4) 5830 #define CMIC_LEDUP0_DATA_RAM178_OFFSET (0x206c8) 5831 #define CMIC_LEDUP0_DATA_RAM179_OFFSET (0x206cc) 5832 #define CMIC_LEDUP0_DATA_RAM18_OFFSET (0x20448) 5833 #define CMIC_LEDUP0_DATA_RAM180_OFFSET (0x206d0) 5834 #define CMIC_LEDUP0_DATA_RAM181_OFFSET (0x206d4) 5835 #define CMIC_LEDUP0_DATA_RAM182_OFFSET (0x206d8) 5836 #define CMIC_LEDUP0_DATA_RAM183_OFFSET (0x206dc) 5837 #define CMIC_LEDUP0_DATA_RAM184_OFFSET (0x206e0) 5838 #define CMIC_LEDUP0_DATA_RAM185_OFFSET (0x206e4) 5839 #define CMIC_LEDUP0_DATA_RAM186_OFFSET (0x206e8) 5840 #define CMIC_LEDUP0_DATA_RAM187_OFFSET (0x206ec) 5841 #define CMIC_LEDUP0_DATA_RAM188_OFFSET (0x206f0) 5842 #define CMIC_LEDUP0_DATA_RAM189_OFFSET (0x206f4) 5843 #define CMIC_LEDUP0_DATA_RAM19_OFFSET (0x2044c) 5844 #define CMIC_LEDUP0_DATA_RAM190_OFFSET (0x206f8) 5845 #define CMIC_LEDUP0_DATA_RAM191_OFFSET (0x206fc) 5846 #define CMIC_LEDUP0_DATA_RAM192_OFFSET (0x20700) 5847 #define CMIC_LEDUP0_DATA_RAM193_OFFSET (0x20704) 5848 #define CMIC_LEDUP0_DATA_RAM194_OFFSET (0x20708) 5849 #define CMIC_LEDUP0_DATA_RAM195_OFFSET (0x2070c) 5850 #define CMIC_LEDUP0_DATA_RAM196_OFFSET (0x20710) 5851 #define CMIC_LEDUP0_DATA_RAM197_OFFSET (0x20714) 5852 #define CMIC_LEDUP0_DATA_RAM198_OFFSET (0x20718) 5853 #define CMIC_LEDUP0_DATA_RAM199_OFFSET (0x2071c) 5854 #define CMIC_LEDUP0_DATA_RAM2_OFFSET (0x20408) 5855 #define CMIC_LEDUP0_DATA_RAM20_OFFSET (0x20450) 5856 #define CMIC_LEDUP0_DATA_RAM200_OFFSET (0x20720) 5857 #define CMIC_LEDUP0_DATA_RAM201_OFFSET (0x20724) 5858 #define CMIC_LEDUP0_DATA_RAM202_OFFSET (0x20728) 5859 #define CMIC_LEDUP0_DATA_RAM203_OFFSET (0x2072c) 5860 #define CMIC_LEDUP0_DATA_RAM204_OFFSET (0x20730) 5861 #define CMIC_LEDUP0_DATA_RAM205_OFFSET (0x20734) 5862 #define CMIC_LEDUP0_DATA_RAM206_OFFSET (0x20738) 5863 #define CMIC_LEDUP0_DATA_RAM207_OFFSET (0x2073c) 5864 #define CMIC_LEDUP0_DATA_RAM208_OFFSET (0x20740) 5865 #define CMIC_LEDUP0_DATA_RAM209_OFFSET (0x20744) 5866 #define CMIC_LEDUP0_DATA_RAM21_OFFSET (0x20454) 5867 #define CMIC_LEDUP0_DATA_RAM210_OFFSET (0x20748) 5868 #define CMIC_LEDUP0_DATA_RAM211_OFFSET (0x2074c) 5869 #define CMIC_LEDUP0_DATA_RAM212_OFFSET (0x20750) 5870 #define CMIC_LEDUP0_DATA_RAM213_OFFSET (0x20754) 5871 #define CMIC_LEDUP0_DATA_RAM214_OFFSET (0x20758) 5872 #define CMIC_LEDUP0_DATA_RAM215_OFFSET (0x2075c) 5873 #define CMIC_LEDUP0_DATA_RAM216_OFFSET (0x20760) 5874 #define CMIC_LEDUP0_DATA_RAM217_OFFSET (0x20764) 5875 #define CMIC_LEDUP0_DATA_RAM218_OFFSET (0x20768) 5876 #define CMIC_LEDUP0_DATA_RAM219_OFFSET (0x2076c) 5877 #define CMIC_LEDUP0_DATA_RAM22_OFFSET (0x20458) 5878 #define CMIC_LEDUP0_DATA_RAM220_OFFSET (0x20770) 5879 #define CMIC_LEDUP0_DATA_RAM221_OFFSET (0x20774) 5880 #define CMIC_LEDUP0_DATA_RAM222_OFFSET (0x20778) 5881 #define CMIC_LEDUP0_DATA_RAM223_OFFSET (0x2077c) 5882 #define CMIC_LEDUP0_DATA_RAM224_OFFSET (0x20780) 5883 #define CMIC_LEDUP0_DATA_RAM225_OFFSET (0x20784) 5884 #define CMIC_LEDUP0_DATA_RAM226_OFFSET (0x20788) 5885 #define CMIC_LEDUP0_DATA_RAM227_OFFSET (0x2078c) 5886 #define CMIC_LEDUP0_DATA_RAM228_OFFSET (0x20790) 5887 #define CMIC_LEDUP0_DATA_RAM229_OFFSET (0x20794) 5888 #define CMIC_LEDUP0_DATA_RAM23_OFFSET (0x2045c) 5889 #define CMIC_LEDUP0_DATA_RAM230_OFFSET (0x20798) 5890 #define CMIC_LEDUP0_DATA_RAM231_OFFSET (0x2079c) 5891 #define CMIC_LEDUP0_DATA_RAM232_OFFSET (0x207a0) 5892 #define CMIC_LEDUP0_DATA_RAM233_OFFSET (0x207a4) 5893 #define CMIC_LEDUP0_DATA_RAM234_OFFSET (0x207a8) 5894 #define CMIC_LEDUP0_DATA_RAM235_OFFSET (0x207ac) 5895 #define CMIC_LEDUP0_DATA_RAM236_OFFSET (0x207b0) 5896 #define CMIC_LEDUP0_DATA_RAM237_OFFSET (0x207b4) 5897 #define CMIC_LEDUP0_DATA_RAM238_OFFSET (0x207b8) 5898 #define CMIC_LEDUP0_DATA_RAM239_OFFSET (0x207bc) 5899 #define CMIC_LEDUP0_DATA_RAM24_OFFSET (0x20460) 5900 #define CMIC_LEDUP0_DATA_RAM240_OFFSET (0x207c0) 5901 #define CMIC_LEDUP0_DATA_RAM241_OFFSET (0x207c4) 5902 #define CMIC_LEDUP0_DATA_RAM242_OFFSET (0x207c8) 5903 #define CMIC_LEDUP0_DATA_RAM243_OFFSET (0x207cc) 5904 #define CMIC_LEDUP0_DATA_RAM244_OFFSET (0x207d0) 5905 #define CMIC_LEDUP0_DATA_RAM245_OFFSET (0x207d4) 5906 #define CMIC_LEDUP0_DATA_RAM246_OFFSET (0x207d8) 5907 #define CMIC_LEDUP0_DATA_RAM247_OFFSET (0x207dc) 5908 #define CMIC_LEDUP0_DATA_RAM248_OFFSET (0x207e0) 5909 #define CMIC_LEDUP0_DATA_RAM249_OFFSET (0x207e4) 5910 #define CMIC_LEDUP0_DATA_RAM25_OFFSET (0x20464) 5911 #define CMIC_LEDUP0_DATA_RAM250_OFFSET (0x207e8) 5912 #define CMIC_LEDUP0_DATA_RAM251_OFFSET (0x207ec) 5913 #define CMIC_LEDUP0_DATA_RAM252_OFFSET (0x207f0) 5914 #define CMIC_LEDUP0_DATA_RAM253_OFFSET (0x207f4) 5915 #define CMIC_LEDUP0_DATA_RAM254_OFFSET (0x207f8) 5916 #define CMIC_LEDUP0_DATA_RAM255_OFFSET (0x207fc) 5917 #define CMIC_LEDUP0_DATA_RAM26_OFFSET (0x20468) 5918 #define CMIC_LEDUP0_DATA_RAM27_OFFSET (0x2046c) 5919 #define CMIC_LEDUP0_DATA_RAM28_OFFSET (0x20470) 5920 #define CMIC_LEDUP0_DATA_RAM29_OFFSET (0x20474) 5921 #define CMIC_LEDUP0_DATA_RAM3_OFFSET (0x2040c) 5922 #define CMIC_LEDUP0_DATA_RAM30_OFFSET (0x20478) 5923 #define CMIC_LEDUP0_DATA_RAM31_OFFSET (0x2047c) 5924 #define CMIC_LEDUP0_DATA_RAM32_OFFSET (0x20480) 5925 #define CMIC_LEDUP0_DATA_RAM33_OFFSET (0x20484) 5926 #define CMIC_LEDUP0_DATA_RAM34_OFFSET (0x20488) 5927 #define CMIC_LEDUP0_DATA_RAM35_OFFSET (0x2048c) 5928 #define CMIC_LEDUP0_DATA_RAM36_OFFSET (0x20490) 5929 #define CMIC_LEDUP0_DATA_RAM37_OFFSET (0x20494) 5930 #define CMIC_LEDUP0_DATA_RAM38_OFFSET (0x20498) 5931 #define CMIC_LEDUP0_DATA_RAM39_OFFSET (0x2049c) 5932 #define CMIC_LEDUP0_DATA_RAM4_OFFSET (0x20410) 5933 #define CMIC_LEDUP0_DATA_RAM40_OFFSET (0x204a0) 5934 #define CMIC_LEDUP0_DATA_RAM41_OFFSET (0x204a4) 5935 #define CMIC_LEDUP0_DATA_RAM42_OFFSET (0x204a8) 5936 #define CMIC_LEDUP0_DATA_RAM43_OFFSET (0x204ac) 5937 #define CMIC_LEDUP0_DATA_RAM44_OFFSET (0x204b0) 5938 #define CMIC_LEDUP0_DATA_RAM45_OFFSET (0x204b4) 5939 #define CMIC_LEDUP0_DATA_RAM46_OFFSET (0x204b8) 5940 #define CMIC_LEDUP0_DATA_RAM47_OFFSET (0x204bc) 5941 #define CMIC_LEDUP0_DATA_RAM48_OFFSET (0x204c0) 5942 #define CMIC_LEDUP0_DATA_RAM49_OFFSET (0x204c4) 5943 #define CMIC_LEDUP0_DATA_RAM5_OFFSET (0x20414) 5944 #define CMIC_LEDUP0_DATA_RAM50_OFFSET (0x204c8) 5945 #define CMIC_LEDUP0_DATA_RAM51_OFFSET (0x204cc) 5946 #define CMIC_LEDUP0_DATA_RAM52_OFFSET (0x204d0) 5947 #define CMIC_LEDUP0_DATA_RAM53_OFFSET (0x204d4) 5948 #define CMIC_LEDUP0_DATA_RAM54_OFFSET (0x204d8) 5949 #define CMIC_LEDUP0_DATA_RAM55_OFFSET (0x204dc) 5950 #define CMIC_LEDUP0_DATA_RAM56_OFFSET (0x204e0) 5951 #define CMIC_LEDUP0_DATA_RAM57_OFFSET (0x204e4) 5952 #define CMIC_LEDUP0_DATA_RAM58_OFFSET (0x204e8) 5953 #define CMIC_LEDUP0_DATA_RAM59_OFFSET (0x204ec) 5954 #define CMIC_LEDUP0_DATA_RAM6_OFFSET (0x20418) 5955 #define CMIC_LEDUP0_DATA_RAM60_OFFSET (0x204f0) 5956 #define CMIC_LEDUP0_DATA_RAM61_OFFSET (0x204f4) 5957 #define CMIC_LEDUP0_DATA_RAM62_OFFSET (0x204f8) 5958 #define CMIC_LEDUP0_DATA_RAM63_OFFSET (0x204fc) 5959 #define CMIC_LEDUP0_DATA_RAM64_OFFSET (0x20500) 5960 #define CMIC_LEDUP0_DATA_RAM65_OFFSET (0x20504) 5961 #define CMIC_LEDUP0_DATA_RAM66_OFFSET (0x20508) 5962 #define CMIC_LEDUP0_DATA_RAM67_OFFSET (0x2050c) 5963 #define CMIC_LEDUP0_DATA_RAM68_OFFSET (0x20510) 5964 #define CMIC_LEDUP0_DATA_RAM69_OFFSET (0x20514) 5965 #define CMIC_LEDUP0_DATA_RAM7_OFFSET (0x2041c) 5966 #define CMIC_LEDUP0_DATA_RAM70_OFFSET (0x20518) 5967 #define CMIC_LEDUP0_DATA_RAM71_OFFSET (0x2051c) 5968 #define CMIC_LEDUP0_DATA_RAM72_OFFSET (0x20520) 5969 #define CMIC_LEDUP0_DATA_RAM73_OFFSET (0x20524) 5970 #define CMIC_LEDUP0_DATA_RAM74_OFFSET (0x20528) 5971 #define CMIC_LEDUP0_DATA_RAM75_OFFSET (0x2052c) 5972 #define CMIC_LEDUP0_DATA_RAM76_OFFSET (0x20530) 5973 #define CMIC_LEDUP0_DATA_RAM77_OFFSET (0x20534) 5974 #define CMIC_LEDUP0_DATA_RAM78_OFFSET (0x20538) 5975 #define CMIC_LEDUP0_DATA_RAM79_OFFSET (0x2053c) 5976 #define CMIC_LEDUP0_DATA_RAM8_OFFSET (0x20420) 5977 #define CMIC_LEDUP0_DATA_RAM80_OFFSET (0x20540) 5978 #define CMIC_LEDUP0_DATA_RAM81_OFFSET (0x20544) 5979 #define CMIC_LEDUP0_DATA_RAM82_OFFSET (0x20548) 5980 #define CMIC_LEDUP0_DATA_RAM83_OFFSET (0x2054c) 5981 #define CMIC_LEDUP0_DATA_RAM84_OFFSET (0x20550) 5982 #define CMIC_LEDUP0_DATA_RAM85_OFFSET (0x20554) 5983 #define CMIC_LEDUP0_DATA_RAM86_OFFSET (0x20558) 5984 #define CMIC_LEDUP0_DATA_RAM87_OFFSET (0x2055c) 5985 #define CMIC_LEDUP0_DATA_RAM88_OFFSET (0x20560) 5986 #define CMIC_LEDUP0_DATA_RAM89_OFFSET (0x20564) 5987 #define CMIC_LEDUP0_DATA_RAM9_OFFSET (0x20424) 5988 #define CMIC_LEDUP0_DATA_RAM90_OFFSET (0x20568) 5989 #define CMIC_LEDUP0_DATA_RAM91_OFFSET (0x2056c) 5990 #define CMIC_LEDUP0_DATA_RAM92_OFFSET (0x20570) 5991 #define CMIC_LEDUP0_DATA_RAM93_OFFSET (0x20574) 5992 #define CMIC_LEDUP0_DATA_RAM94_OFFSET (0x20578) 5993 #define CMIC_LEDUP0_DATA_RAM95_OFFSET (0x2057c) 5994 #define CMIC_LEDUP0_DATA_RAM96_OFFSET (0x20580) 5995 #define CMIC_LEDUP0_DATA_RAM97_OFFSET (0x20584) 5996 #define CMIC_LEDUP0_DATA_RAM98_OFFSET (0x20588) 5997 #define CMIC_LEDUP0_DATA_RAM99_OFFSET (0x2058c) 5998 #define CMIC_LEDUP0_ECC_CONFIG_OFFSET (0x20060) 5999 #define CMIC_LEDUP0_ECC_INTR_OFFSET (0x2006c) 6000 #define CMIC_LEDUP0_ECC_INTR_CLR_OFFSET (0x20070) 6001 #define CMIC_LEDUP0_ECC_INTR_ENABLE_OFFSET (0x20068) 6002 #define CMIC_LEDUP0_ECC_STATUS_OFFSET (0x20064) 6003 #define CMIC_LEDUP0_PORT_ORDER_REMAP_0_3_OFFSET (0x20010) 6004 #define CMIC_LEDUP0_PORT_ORDER_REMAP_12_15_OFFSET (0x2001c) 6005 #define CMIC_LEDUP0_PORT_ORDER_REMAP_16_19_OFFSET (0x20020) 6006 #define CMIC_LEDUP0_PORT_ORDER_REMAP_20_23_OFFSET (0x20024) 6007 #define CMIC_LEDUP0_PORT_ORDER_REMAP_24_27_OFFSET (0x20028) 6008 #define CMIC_LEDUP0_PORT_ORDER_REMAP_28_31_OFFSET (0x2002c) 6009 #define CMIC_LEDUP0_PORT_ORDER_REMAP_32_35_OFFSET (0x20030) 6010 #define CMIC_LEDUP0_PORT_ORDER_REMAP_36_39_OFFSET (0x20034) 6011 #define CMIC_LEDUP0_PORT_ORDER_REMAP_40_43_OFFSET (0x20038) 6012 #define CMIC_LEDUP0_PORT_ORDER_REMAP_44_47_OFFSET (0x2003c) 6013 #define CMIC_LEDUP0_PORT_ORDER_REMAP_48_51_OFFSET (0x20040) 6014 #define CMIC_LEDUP0_PORT_ORDER_REMAP_4_7_OFFSET (0x20014) 6015 #define CMIC_LEDUP0_PORT_ORDER_REMAP_52_55_OFFSET (0x20044) 6016 #define CMIC_LEDUP0_PORT_ORDER_REMAP_56_59_OFFSET (0x20048) 6017 #define CMIC_LEDUP0_PORT_ORDER_REMAP_60_63_OFFSET (0x2004c) 6018 #define CMIC_LEDUP0_PORT_ORDER_REMAP_8_11_OFFSET (0x20018) 6019 #define CMIC_LEDUP0_PROGRAM_RAM_OFFSET (0x20800) 6020 #define CMIC_LEDUP0_PROGRAM_RAM0_OFFSET (0x20800) 6021 #define CMIC_LEDUP0_PROGRAM_RAM1_OFFSET (0x20804) 6022 #define CMIC_LEDUP0_PROGRAM_RAM10_OFFSET (0x20828) 6023 #define CMIC_LEDUP0_PROGRAM_RAM100_OFFSET (0x20990) 6024 #define CMIC_LEDUP0_PROGRAM_RAM101_OFFSET (0x20994) 6025 #define CMIC_LEDUP0_PROGRAM_RAM102_OFFSET (0x20998) 6026 #define CMIC_LEDUP0_PROGRAM_RAM103_OFFSET (0x2099c) 6027 #define CMIC_LEDUP0_PROGRAM_RAM104_OFFSET (0x209a0) 6028 #define CMIC_LEDUP0_PROGRAM_RAM105_OFFSET (0x209a4) 6029 #define CMIC_LEDUP0_PROGRAM_RAM106_OFFSET (0x209a8) 6030 #define CMIC_LEDUP0_PROGRAM_RAM107_OFFSET (0x209ac) 6031 #define CMIC_LEDUP0_PROGRAM_RAM108_OFFSET (0x209b0) 6032 #define CMIC_LEDUP0_PROGRAM_RAM109_OFFSET (0x209b4) 6033 #define CMIC_LEDUP0_PROGRAM_RAM11_OFFSET (0x2082c) 6034 #define CMIC_LEDUP0_PROGRAM_RAM110_OFFSET (0x209b8) 6035 #define CMIC_LEDUP0_PROGRAM_RAM111_OFFSET (0x209bc) 6036 #define CMIC_LEDUP0_PROGRAM_RAM112_OFFSET (0x209c0) 6037 #define CMIC_LEDUP0_PROGRAM_RAM113_OFFSET (0x209c4) 6038 #define CMIC_LEDUP0_PROGRAM_RAM114_OFFSET (0x209c8) 6039 #define CMIC_LEDUP0_PROGRAM_RAM115_OFFSET (0x209cc) 6040 #define CMIC_LEDUP0_PROGRAM_RAM116_OFFSET (0x209d0) 6041 #define CMIC_LEDUP0_PROGRAM_RAM117_OFFSET (0x209d4) 6042 #define CMIC_LEDUP0_PROGRAM_RAM118_OFFSET (0x209d8) 6043 #define CMIC_LEDUP0_PROGRAM_RAM119_OFFSET (0x209dc) 6044 #define CMIC_LEDUP0_PROGRAM_RAM12_OFFSET (0x20830) 6045 #define CMIC_LEDUP0_PROGRAM_RAM120_OFFSET (0x209e0) 6046 #define CMIC_LEDUP0_PROGRAM_RAM121_OFFSET (0x209e4) 6047 #define CMIC_LEDUP0_PROGRAM_RAM122_OFFSET (0x209e8) 6048 #define CMIC_LEDUP0_PROGRAM_RAM123_OFFSET (0x209ec) 6049 #define CMIC_LEDUP0_PROGRAM_RAM124_OFFSET (0x209f0) 6050 #define CMIC_LEDUP0_PROGRAM_RAM125_OFFSET (0x209f4) 6051 #define CMIC_LEDUP0_PROGRAM_RAM126_OFFSET (0x209f8) 6052 #define CMIC_LEDUP0_PROGRAM_RAM127_OFFSET (0x209fc) 6053 #define CMIC_LEDUP0_PROGRAM_RAM128_OFFSET (0x20a00) 6054 #define CMIC_LEDUP0_PROGRAM_RAM129_OFFSET (0x20a04) 6055 #define CMIC_LEDUP0_PROGRAM_RAM13_OFFSET (0x20834) 6056 #define CMIC_LEDUP0_PROGRAM_RAM130_OFFSET (0x20a08) 6057 #define CMIC_LEDUP0_PROGRAM_RAM131_OFFSET (0x20a0c) 6058 #define CMIC_LEDUP0_PROGRAM_RAM132_OFFSET (0x20a10) 6059 #define CMIC_LEDUP0_PROGRAM_RAM133_OFFSET (0x20a14) 6060 #define CMIC_LEDUP0_PROGRAM_RAM134_OFFSET (0x20a18) 6061 #define CMIC_LEDUP0_PROGRAM_RAM135_OFFSET (0x20a1c) 6062 #define CMIC_LEDUP0_PROGRAM_RAM136_OFFSET (0x20a20) 6063 #define CMIC_LEDUP0_PROGRAM_RAM137_OFFSET (0x20a24) 6064 #define CMIC_LEDUP0_PROGRAM_RAM138_OFFSET (0x20a28) 6065 #define CMIC_LEDUP0_PROGRAM_RAM139_OFFSET (0x20a2c) 6066 #define CMIC_LEDUP0_PROGRAM_RAM14_OFFSET (0x20838) 6067 #define CMIC_LEDUP0_PROGRAM_RAM140_OFFSET (0x20a30) 6068 #define CMIC_LEDUP0_PROGRAM_RAM141_OFFSET (0x20a34) 6069 #define CMIC_LEDUP0_PROGRAM_RAM142_OFFSET (0x20a38) 6070 #define CMIC_LEDUP0_PROGRAM_RAM143_OFFSET (0x20a3c) 6071 #define CMIC_LEDUP0_PROGRAM_RAM144_OFFSET (0x20a40) 6072 #define CMIC_LEDUP0_PROGRAM_RAM145_OFFSET (0x20a44) 6073 #define CMIC_LEDUP0_PROGRAM_RAM146_OFFSET (0x20a48) 6074 #define CMIC_LEDUP0_PROGRAM_RAM147_OFFSET (0x20a4c) 6075 #define CMIC_LEDUP0_PROGRAM_RAM148_OFFSET (0x20a50) 6076 #define CMIC_LEDUP0_PROGRAM_RAM149_OFFSET (0x20a54) 6077 #define CMIC_LEDUP0_PROGRAM_RAM15_OFFSET (0x2083c) 6078 #define CMIC_LEDUP0_PROGRAM_RAM150_OFFSET (0x20a58) 6079 #define CMIC_LEDUP0_PROGRAM_RAM151_OFFSET (0x20a5c) 6080 #define CMIC_LEDUP0_PROGRAM_RAM152_OFFSET (0x20a60) 6081 #define CMIC_LEDUP0_PROGRAM_RAM153_OFFSET (0x20a64) 6082 #define CMIC_LEDUP0_PROGRAM_RAM154_OFFSET (0x20a68) 6083 #define CMIC_LEDUP0_PROGRAM_RAM155_OFFSET (0x20a6c) 6084 #define CMIC_LEDUP0_PROGRAM_RAM156_OFFSET (0x20a70) 6085 #define CMIC_LEDUP0_PROGRAM_RAM157_OFFSET (0x20a74) 6086 #define CMIC_LEDUP0_PROGRAM_RAM158_OFFSET (0x20a78) 6087 #define CMIC_LEDUP0_PROGRAM_RAM159_OFFSET (0x20a7c) 6088 #define CMIC_LEDUP0_PROGRAM_RAM16_OFFSET (0x20840) 6089 #define CMIC_LEDUP0_PROGRAM_RAM160_OFFSET (0x20a80) 6090 #define CMIC_LEDUP0_PROGRAM_RAM161_OFFSET (0x20a84) 6091 #define CMIC_LEDUP0_PROGRAM_RAM162_OFFSET (0x20a88) 6092 #define CMIC_LEDUP0_PROGRAM_RAM163_OFFSET (0x20a8c) 6093 #define CMIC_LEDUP0_PROGRAM_RAM164_OFFSET (0x20a90) 6094 #define CMIC_LEDUP0_PROGRAM_RAM165_OFFSET (0x20a94) 6095 #define CMIC_LEDUP0_PROGRAM_RAM166_OFFSET (0x20a98) 6096 #define CMIC_LEDUP0_PROGRAM_RAM167_OFFSET (0x20a9c) 6097 #define CMIC_LEDUP0_PROGRAM_RAM168_OFFSET (0x20aa0) 6098 #define CMIC_LEDUP0_PROGRAM_RAM169_OFFSET (0x20aa4) 6099 #define CMIC_LEDUP0_PROGRAM_RAM17_OFFSET (0x20844) 6100 #define CMIC_LEDUP0_PROGRAM_RAM170_OFFSET (0x20aa8) 6101 #define CMIC_LEDUP0_PROGRAM_RAM171_OFFSET (0x20aac) 6102 #define CMIC_LEDUP0_PROGRAM_RAM172_OFFSET (0x20ab0) 6103 #define CMIC_LEDUP0_PROGRAM_RAM173_OFFSET (0x20ab4) 6104 #define CMIC_LEDUP0_PROGRAM_RAM174_OFFSET (0x20ab8) 6105 #define CMIC_LEDUP0_PROGRAM_RAM175_OFFSET (0x20abc) 6106 #define CMIC_LEDUP0_PROGRAM_RAM176_OFFSET (0x20ac0) 6107 #define CMIC_LEDUP0_PROGRAM_RAM177_OFFSET (0x20ac4) 6108 #define CMIC_LEDUP0_PROGRAM_RAM178_OFFSET (0x20ac8) 6109 #define CMIC_LEDUP0_PROGRAM_RAM179_OFFSET (0x20acc) 6110 #define CMIC_LEDUP0_PROGRAM_RAM18_OFFSET (0x20848) 6111 #define CMIC_LEDUP0_PROGRAM_RAM180_OFFSET (0x20ad0) 6112 #define CMIC_LEDUP0_PROGRAM_RAM181_OFFSET (0x20ad4) 6113 #define CMIC_LEDUP0_PROGRAM_RAM182_OFFSET (0x20ad8) 6114 #define CMIC_LEDUP0_PROGRAM_RAM183_OFFSET (0x20adc) 6115 #define CMIC_LEDUP0_PROGRAM_RAM184_OFFSET (0x20ae0) 6116 #define CMIC_LEDUP0_PROGRAM_RAM185_OFFSET (0x20ae4) 6117 #define CMIC_LEDUP0_PROGRAM_RAM186_OFFSET (0x20ae8) 6118 #define CMIC_LEDUP0_PROGRAM_RAM187_OFFSET (0x20aec) 6119 #define CMIC_LEDUP0_PROGRAM_RAM188_OFFSET (0x20af0) 6120 #define CMIC_LEDUP0_PROGRAM_RAM189_OFFSET (0x20af4) 6121 #define CMIC_LEDUP0_PROGRAM_RAM19_OFFSET (0x2084c) 6122 #define CMIC_LEDUP0_PROGRAM_RAM190_OFFSET (0x20af8) 6123 #define CMIC_LEDUP0_PROGRAM_RAM191_OFFSET (0x20afc) 6124 #define CMIC_LEDUP0_PROGRAM_RAM192_OFFSET (0x20b00) 6125 #define CMIC_LEDUP0_PROGRAM_RAM193_OFFSET (0x20b04) 6126 #define CMIC_LEDUP0_PROGRAM_RAM194_OFFSET (0x20b08) 6127 #define CMIC_LEDUP0_PROGRAM_RAM195_OFFSET (0x20b0c) 6128 #define CMIC_LEDUP0_PROGRAM_RAM196_OFFSET (0x20b10) 6129 #define CMIC_LEDUP0_PROGRAM_RAM197_OFFSET (0x20b14) 6130 #define CMIC_LEDUP0_PROGRAM_RAM198_OFFSET (0x20b18) 6131 #define CMIC_LEDUP0_PROGRAM_RAM199_OFFSET (0x20b1c) 6132 #define CMIC_LEDUP0_PROGRAM_RAM2_OFFSET (0x20808) 6133 #define CMIC_LEDUP0_PROGRAM_RAM20_OFFSET (0x20850) 6134 #define CMIC_LEDUP0_PROGRAM_RAM200_OFFSET (0x20b20) 6135 #define CMIC_LEDUP0_PROGRAM_RAM201_OFFSET (0x20b24) 6136 #define CMIC_LEDUP0_PROGRAM_RAM202_OFFSET (0x20b28) 6137 #define CMIC_LEDUP0_PROGRAM_RAM203_OFFSET (0x20b2c) 6138 #define CMIC_LEDUP0_PROGRAM_RAM204_OFFSET (0x20b30) 6139 #define CMIC_LEDUP0_PROGRAM_RAM205_OFFSET (0x20b34) 6140 #define CMIC_LEDUP0_PROGRAM_RAM206_OFFSET (0x20b38) 6141 #define CMIC_LEDUP0_PROGRAM_RAM207_OFFSET (0x20b3c) 6142 #define CMIC_LEDUP0_PROGRAM_RAM208_OFFSET (0x20b40) 6143 #define CMIC_LEDUP0_PROGRAM_RAM209_OFFSET (0x20b44) 6144 #define CMIC_LEDUP0_PROGRAM_RAM21_OFFSET (0x20854) 6145 #define CMIC_LEDUP0_PROGRAM_RAM210_OFFSET (0x20b48) 6146 #define CMIC_LEDUP0_PROGRAM_RAM211_OFFSET (0x20b4c) 6147 #define CMIC_LEDUP0_PROGRAM_RAM212_OFFSET (0x20b50) 6148 #define CMIC_LEDUP0_PROGRAM_RAM213_OFFSET (0x20b54) 6149 #define CMIC_LEDUP0_PROGRAM_RAM214_OFFSET (0x20b58) 6150 #define CMIC_LEDUP0_PROGRAM_RAM215_OFFSET (0x20b5c) 6151 #define CMIC_LEDUP0_PROGRAM_RAM216_OFFSET (0x20b60) 6152 #define CMIC_LEDUP0_PROGRAM_RAM217_OFFSET (0x20b64) 6153 #define CMIC_LEDUP0_PROGRAM_RAM218_OFFSET (0x20b68) 6154 #define CMIC_LEDUP0_PROGRAM_RAM219_OFFSET (0x20b6c) 6155 #define CMIC_LEDUP0_PROGRAM_RAM22_OFFSET (0x20858) 6156 #define CMIC_LEDUP0_PROGRAM_RAM220_OFFSET (0x20b70) 6157 #define CMIC_LEDUP0_PROGRAM_RAM221_OFFSET (0x20b74) 6158 #define CMIC_LEDUP0_PROGRAM_RAM222_OFFSET (0x20b78) 6159 #define CMIC_LEDUP0_PROGRAM_RAM223_OFFSET (0x20b7c) 6160 #define CMIC_LEDUP0_PROGRAM_RAM224_OFFSET (0x20b80) 6161 #define CMIC_LEDUP0_PROGRAM_RAM225_OFFSET (0x20b84) 6162 #define CMIC_LEDUP0_PROGRAM_RAM226_OFFSET (0x20b88) 6163 #define CMIC_LEDUP0_PROGRAM_RAM227_OFFSET (0x20b8c) 6164 #define CMIC_LEDUP0_PROGRAM_RAM228_OFFSET (0x20b90) 6165 #define CMIC_LEDUP0_PROGRAM_RAM229_OFFSET (0x20b94) 6166 #define CMIC_LEDUP0_PROGRAM_RAM23_OFFSET (0x2085c) 6167 #define CMIC_LEDUP0_PROGRAM_RAM230_OFFSET (0x20b98) 6168 #define CMIC_LEDUP0_PROGRAM_RAM231_OFFSET (0x20b9c) 6169 #define CMIC_LEDUP0_PROGRAM_RAM232_OFFSET (0x20ba0) 6170 #define CMIC_LEDUP0_PROGRAM_RAM233_OFFSET (0x20ba4) 6171 #define CMIC_LEDUP0_PROGRAM_RAM234_OFFSET (0x20ba8) 6172 #define CMIC_LEDUP0_PROGRAM_RAM235_OFFSET (0x20bac) 6173 #define CMIC_LEDUP0_PROGRAM_RAM236_OFFSET (0x20bb0) 6174 #define CMIC_LEDUP0_PROGRAM_RAM237_OFFSET (0x20bb4) 6175 #define CMIC_LEDUP0_PROGRAM_RAM238_OFFSET (0x20bb8) 6176 #define CMIC_LEDUP0_PROGRAM_RAM239_OFFSET (0x20bbc) 6177 #define CMIC_LEDUP0_PROGRAM_RAM24_OFFSET (0x20860) 6178 #define CMIC_LEDUP0_PROGRAM_RAM240_OFFSET (0x20bc0) 6179 #define CMIC_LEDUP0_PROGRAM_RAM241_OFFSET (0x20bc4) 6180 #define CMIC_LEDUP0_PROGRAM_RAM242_OFFSET (0x20bc8) 6181 #define CMIC_LEDUP0_PROGRAM_RAM243_OFFSET (0x20bcc) 6182 #define CMIC_LEDUP0_PROGRAM_RAM244_OFFSET (0x20bd0) 6183 #define CMIC_LEDUP0_PROGRAM_RAM245_OFFSET (0x20bd4) 6184 #define CMIC_LEDUP0_PROGRAM_RAM246_OFFSET (0x20bd8) 6185 #define CMIC_LEDUP0_PROGRAM_RAM247_OFFSET (0x20bdc) 6186 #define CMIC_LEDUP0_PROGRAM_RAM248_OFFSET (0x20be0) 6187 #define CMIC_LEDUP0_PROGRAM_RAM249_OFFSET (0x20be4) 6188 #define CMIC_LEDUP0_PROGRAM_RAM25_OFFSET (0x20864) 6189 #define CMIC_LEDUP0_PROGRAM_RAM250_OFFSET (0x20be8) 6190 #define CMIC_LEDUP0_PROGRAM_RAM251_OFFSET (0x20bec) 6191 #define CMIC_LEDUP0_PROGRAM_RAM252_OFFSET (0x20bf0) 6192 #define CMIC_LEDUP0_PROGRAM_RAM253_OFFSET (0x20bf4) 6193 #define CMIC_LEDUP0_PROGRAM_RAM254_OFFSET (0x20bf8) 6194 #define CMIC_LEDUP0_PROGRAM_RAM255_OFFSET (0x20bfc) 6195 #define CMIC_LEDUP0_PROGRAM_RAM26_OFFSET (0x20868) 6196 #define CMIC_LEDUP0_PROGRAM_RAM27_OFFSET (0x2086c) 6197 #define CMIC_LEDUP0_PROGRAM_RAM28_OFFSET (0x20870) 6198 #define CMIC_LEDUP0_PROGRAM_RAM29_OFFSET (0x20874) 6199 #define CMIC_LEDUP0_PROGRAM_RAM3_OFFSET (0x2080c) 6200 #define CMIC_LEDUP0_PROGRAM_RAM30_OFFSET (0x20878) 6201 #define CMIC_LEDUP0_PROGRAM_RAM31_OFFSET (0x2087c) 6202 #define CMIC_LEDUP0_PROGRAM_RAM32_OFFSET (0x20880) 6203 #define CMIC_LEDUP0_PROGRAM_RAM33_OFFSET (0x20884) 6204 #define CMIC_LEDUP0_PROGRAM_RAM34_OFFSET (0x20888) 6205 #define CMIC_LEDUP0_PROGRAM_RAM35_OFFSET (0x2088c) 6206 #define CMIC_LEDUP0_PROGRAM_RAM36_OFFSET (0x20890) 6207 #define CMIC_LEDUP0_PROGRAM_RAM37_OFFSET (0x20894) 6208 #define CMIC_LEDUP0_PROGRAM_RAM38_OFFSET (0x20898) 6209 #define CMIC_LEDUP0_PROGRAM_RAM39_OFFSET (0x2089c) 6210 #define CMIC_LEDUP0_PROGRAM_RAM4_OFFSET (0x20810) 6211 #define CMIC_LEDUP0_PROGRAM_RAM40_OFFSET (0x208a0) 6212 #define CMIC_LEDUP0_PROGRAM_RAM41_OFFSET (0x208a4) 6213 #define CMIC_LEDUP0_PROGRAM_RAM42_OFFSET (0x208a8) 6214 #define CMIC_LEDUP0_PROGRAM_RAM43_OFFSET (0x208ac) 6215 #define CMIC_LEDUP0_PROGRAM_RAM44_OFFSET (0x208b0) 6216 #define CMIC_LEDUP0_PROGRAM_RAM45_OFFSET (0x208b4) 6217 #define CMIC_LEDUP0_PROGRAM_RAM46_OFFSET (0x208b8) 6218 #define CMIC_LEDUP0_PROGRAM_RAM47_OFFSET (0x208bc) 6219 #define CMIC_LEDUP0_PROGRAM_RAM48_OFFSET (0x208c0) 6220 #define CMIC_LEDUP0_PROGRAM_RAM49_OFFSET (0x208c4) 6221 #define CMIC_LEDUP0_PROGRAM_RAM5_OFFSET (0x20814) 6222 #define CMIC_LEDUP0_PROGRAM_RAM50_OFFSET (0x208c8) 6223 #define CMIC_LEDUP0_PROGRAM_RAM51_OFFSET (0x208cc) 6224 #define CMIC_LEDUP0_PROGRAM_RAM52_OFFSET (0x208d0) 6225 #define CMIC_LEDUP0_PROGRAM_RAM53_OFFSET (0x208d4) 6226 #define CMIC_LEDUP0_PROGRAM_RAM54_OFFSET (0x208d8) 6227 #define CMIC_LEDUP0_PROGRAM_RAM55_OFFSET (0x208dc) 6228 #define CMIC_LEDUP0_PROGRAM_RAM56_OFFSET (0x208e0) 6229 #define CMIC_LEDUP0_PROGRAM_RAM57_OFFSET (0x208e4) 6230 #define CMIC_LEDUP0_PROGRAM_RAM58_OFFSET (0x208e8) 6231 #define CMIC_LEDUP0_PROGRAM_RAM59_OFFSET (0x208ec) 6232 #define CMIC_LEDUP0_PROGRAM_RAM6_OFFSET (0x20818) 6233 #define CMIC_LEDUP0_PROGRAM_RAM60_OFFSET (0x208f0) 6234 #define CMIC_LEDUP0_PROGRAM_RAM61_OFFSET (0x208f4) 6235 #define CMIC_LEDUP0_PROGRAM_RAM62_OFFSET (0x208f8) 6236 #define CMIC_LEDUP0_PROGRAM_RAM63_OFFSET (0x208fc) 6237 #define CMIC_LEDUP0_PROGRAM_RAM64_OFFSET (0x20900) 6238 #define CMIC_LEDUP0_PROGRAM_RAM65_OFFSET (0x20904) 6239 #define CMIC_LEDUP0_PROGRAM_RAM66_OFFSET (0x20908) 6240 #define CMIC_LEDUP0_PROGRAM_RAM67_OFFSET (0x2090c) 6241 #define CMIC_LEDUP0_PROGRAM_RAM68_OFFSET (0x20910) 6242 #define CMIC_LEDUP0_PROGRAM_RAM69_OFFSET (0x20914) 6243 #define CMIC_LEDUP0_PROGRAM_RAM7_OFFSET (0x2081c) 6244 #define CMIC_LEDUP0_PROGRAM_RAM70_OFFSET (0x20918) 6245 #define CMIC_LEDUP0_PROGRAM_RAM71_OFFSET (0x2091c) 6246 #define CMIC_LEDUP0_PROGRAM_RAM72_OFFSET (0x20920) 6247 #define CMIC_LEDUP0_PROGRAM_RAM73_OFFSET (0x20924) 6248 #define CMIC_LEDUP0_PROGRAM_RAM74_OFFSET (0x20928) 6249 #define CMIC_LEDUP0_PROGRAM_RAM75_OFFSET (0x2092c) 6250 #define CMIC_LEDUP0_PROGRAM_RAM76_OFFSET (0x20930) 6251 #define CMIC_LEDUP0_PROGRAM_RAM77_OFFSET (0x20934) 6252 #define CMIC_LEDUP0_PROGRAM_RAM78_OFFSET (0x20938) 6253 #define CMIC_LEDUP0_PROGRAM_RAM79_OFFSET (0x2093c) 6254 #define CMIC_LEDUP0_PROGRAM_RAM8_OFFSET (0x20820) 6255 #define CMIC_LEDUP0_PROGRAM_RAM80_OFFSET (0x20940) 6256 #define CMIC_LEDUP0_PROGRAM_RAM81_OFFSET (0x20944) 6257 #define CMIC_LEDUP0_PROGRAM_RAM82_OFFSET (0x20948) 6258 #define CMIC_LEDUP0_PROGRAM_RAM83_OFFSET (0x2094c) 6259 #define CMIC_LEDUP0_PROGRAM_RAM84_OFFSET (0x20950) 6260 #define CMIC_LEDUP0_PROGRAM_RAM85_OFFSET (0x20954) 6261 #define CMIC_LEDUP0_PROGRAM_RAM86_OFFSET (0x20958) 6262 #define CMIC_LEDUP0_PROGRAM_RAM87_OFFSET (0x2095c) 6263 #define CMIC_LEDUP0_PROGRAM_RAM88_OFFSET (0x20960) 6264 #define CMIC_LEDUP0_PROGRAM_RAM89_OFFSET (0x20964) 6265 #define CMIC_LEDUP0_PROGRAM_RAM9_OFFSET (0x20824) 6266 #define CMIC_LEDUP0_PROGRAM_RAM90_OFFSET (0x20968) 6267 #define CMIC_LEDUP0_PROGRAM_RAM91_OFFSET (0x2096c) 6268 #define CMIC_LEDUP0_PROGRAM_RAM92_OFFSET (0x20970) 6269 #define CMIC_LEDUP0_PROGRAM_RAM93_OFFSET (0x20974) 6270 #define CMIC_LEDUP0_PROGRAM_RAM94_OFFSET (0x20978) 6271 #define CMIC_LEDUP0_PROGRAM_RAM95_OFFSET (0x2097c) 6272 #define CMIC_LEDUP0_PROGRAM_RAM96_OFFSET (0x20980) 6273 #define CMIC_LEDUP0_PROGRAM_RAM97_OFFSET (0x20984) 6274 #define CMIC_LEDUP0_PROGRAM_RAM98_OFFSET (0x20988) 6275 #define CMIC_LEDUP0_PROGRAM_RAM99_OFFSET (0x2098c) 6276 #define CMIC_LEDUP0_SCANCHAIN_ASSEMBLY_ST_ADDR_OFFSET (0x20008) 6277 #define CMIC_LEDUP0_SCANOUT_COUNT_UPPER_OFFSET (0x20054) 6278 #define CMIC_LEDUP0_STATUS_OFFSET (0x20004) 6279 #define CMIC_LEDUP0_TM_CONTROL_OFFSET (0x20058) 6280 #define CMIC_LEDUP1_CLK_DIV_OFFSET (0x2105c) 6281 #define CMIC_LEDUP1_CLK_PARAMS_OFFSET (0x21050) 6282 #define CMIC_LEDUP1_CTRL_OFFSET (0x21000) 6283 #define CMIC_LEDUP1_DATA_RAM_OFFSET (0x21400) 6284 #define CMIC_LEDUP1_DATA_RAM0_OFFSET (0x21400) 6285 #define CMIC_LEDUP1_DATA_RAM1_OFFSET (0x21404) 6286 #define CMIC_LEDUP1_DATA_RAM10_OFFSET (0x21428) 6287 #define CMIC_LEDUP1_DATA_RAM100_OFFSET (0x21590) 6288 #define CMIC_LEDUP1_DATA_RAM101_OFFSET (0x21594) 6289 #define CMIC_LEDUP1_DATA_RAM102_OFFSET (0x21598) 6290 #define CMIC_LEDUP1_DATA_RAM103_OFFSET (0x2159c) 6291 #define CMIC_LEDUP1_DATA_RAM104_OFFSET (0x215a0) 6292 #define CMIC_LEDUP1_DATA_RAM105_OFFSET (0x215a4) 6293 #define CMIC_LEDUP1_DATA_RAM106_OFFSET (0x215a8) 6294 #define CMIC_LEDUP1_DATA_RAM107_OFFSET (0x215ac) 6295 #define CMIC_LEDUP1_DATA_RAM108_OFFSET (0x215b0) 6296 #define CMIC_LEDUP1_DATA_RAM109_OFFSET (0x215b4) 6297 #define CMIC_LEDUP1_DATA_RAM11_OFFSET (0x2142c) 6298 #define CMIC_LEDUP1_DATA_RAM110_OFFSET (0x215b8) 6299 #define CMIC_LEDUP1_DATA_RAM111_OFFSET (0x215bc) 6300 #define CMIC_LEDUP1_DATA_RAM112_OFFSET (0x215c0) 6301 #define CMIC_LEDUP1_DATA_RAM113_OFFSET (0x215c4) 6302 #define CMIC_LEDUP1_DATA_RAM114_OFFSET (0x215c8) 6303 #define CMIC_LEDUP1_DATA_RAM115_OFFSET (0x215cc) 6304 #define CMIC_LEDUP1_DATA_RAM116_OFFSET (0x215d0) 6305 #define CMIC_LEDUP1_DATA_RAM117_OFFSET (0x215d4) 6306 #define CMIC_LEDUP1_DATA_RAM118_OFFSET (0x215d8) 6307 #define CMIC_LEDUP1_DATA_RAM119_OFFSET (0x215dc) 6308 #define CMIC_LEDUP1_DATA_RAM12_OFFSET (0x21430) 6309 #define CMIC_LEDUP1_DATA_RAM120_OFFSET (0x215e0) 6310 #define CMIC_LEDUP1_DATA_RAM121_OFFSET (0x215e4) 6311 #define CMIC_LEDUP1_DATA_RAM122_OFFSET (0x215e8) 6312 #define CMIC_LEDUP1_DATA_RAM123_OFFSET (0x215ec) 6313 #define CMIC_LEDUP1_DATA_RAM124_OFFSET (0x215f0) 6314 #define CMIC_LEDUP1_DATA_RAM125_OFFSET (0x215f4) 6315 #define CMIC_LEDUP1_DATA_RAM126_OFFSET (0x215f8) 6316 #define CMIC_LEDUP1_DATA_RAM127_OFFSET (0x215fc) 6317 #define CMIC_LEDUP1_DATA_RAM128_OFFSET (0x21600) 6318 #define CMIC_LEDUP1_DATA_RAM129_OFFSET (0x21604) 6319 #define CMIC_LEDUP1_DATA_RAM13_OFFSET (0x21434) 6320 #define CMIC_LEDUP1_DATA_RAM130_OFFSET (0x21608) 6321 #define CMIC_LEDUP1_DATA_RAM131_OFFSET (0x2160c) 6322 #define CMIC_LEDUP1_DATA_RAM132_OFFSET (0x21610) 6323 #define CMIC_LEDUP1_DATA_RAM133_OFFSET (0x21614) 6324 #define CMIC_LEDUP1_DATA_RAM134_OFFSET (0x21618) 6325 #define CMIC_LEDUP1_DATA_RAM135_OFFSET (0x2161c) 6326 #define CMIC_LEDUP1_DATA_RAM136_OFFSET (0x21620) 6327 #define CMIC_LEDUP1_DATA_RAM137_OFFSET (0x21624) 6328 #define CMIC_LEDUP1_DATA_RAM138_OFFSET (0x21628) 6329 #define CMIC_LEDUP1_DATA_RAM139_OFFSET (0x2162c) 6330 #define CMIC_LEDUP1_DATA_RAM14_OFFSET (0x21438) 6331 #define CMIC_LEDUP1_DATA_RAM140_OFFSET (0x21630) 6332 #define CMIC_LEDUP1_DATA_RAM141_OFFSET (0x21634) 6333 #define CMIC_LEDUP1_DATA_RAM142_OFFSET (0x21638) 6334 #define CMIC_LEDUP1_DATA_RAM143_OFFSET (0x2163c) 6335 #define CMIC_LEDUP1_DATA_RAM144_OFFSET (0x21640) 6336 #define CMIC_LEDUP1_DATA_RAM145_OFFSET (0x21644) 6337 #define CMIC_LEDUP1_DATA_RAM146_OFFSET (0x21648) 6338 #define CMIC_LEDUP1_DATA_RAM147_OFFSET (0x2164c) 6339 #define CMIC_LEDUP1_DATA_RAM148_OFFSET (0x21650) 6340 #define CMIC_LEDUP1_DATA_RAM149_OFFSET (0x21654) 6341 #define CMIC_LEDUP1_DATA_RAM15_OFFSET (0x2143c) 6342 #define CMIC_LEDUP1_DATA_RAM150_OFFSET (0x21658) 6343 #define CMIC_LEDUP1_DATA_RAM151_OFFSET (0x2165c) 6344 #define CMIC_LEDUP1_DATA_RAM152_OFFSET (0x21660) 6345 #define CMIC_LEDUP1_DATA_RAM153_OFFSET (0x21664) 6346 #define CMIC_LEDUP1_DATA_RAM154_OFFSET (0x21668) 6347 #define CMIC_LEDUP1_DATA_RAM155_OFFSET (0x2166c) 6348 #define CMIC_LEDUP1_DATA_RAM156_OFFSET (0x21670) 6349 #define CMIC_LEDUP1_DATA_RAM157_OFFSET (0x21674) 6350 #define CMIC_LEDUP1_DATA_RAM158_OFFSET (0x21678) 6351 #define CMIC_LEDUP1_DATA_RAM159_OFFSET (0x2167c) 6352 #define CMIC_LEDUP1_DATA_RAM16_OFFSET (0x21440) 6353 #define CMIC_LEDUP1_DATA_RAM160_OFFSET (0x21680) 6354 #define CMIC_LEDUP1_DATA_RAM161_OFFSET (0x21684) 6355 #define CMIC_LEDUP1_DATA_RAM162_OFFSET (0x21688) 6356 #define CMIC_LEDUP1_DATA_RAM163_OFFSET (0x2168c) 6357 #define CMIC_LEDUP1_DATA_RAM164_OFFSET (0x21690) 6358 #define CMIC_LEDUP1_DATA_RAM165_OFFSET (0x21694) 6359 #define CMIC_LEDUP1_DATA_RAM166_OFFSET (0x21698) 6360 #define CMIC_LEDUP1_DATA_RAM167_OFFSET (0x2169c) 6361 #define CMIC_LEDUP1_DATA_RAM168_OFFSET (0x216a0) 6362 #define CMIC_LEDUP1_DATA_RAM169_OFFSET (0x216a4) 6363 #define CMIC_LEDUP1_DATA_RAM17_OFFSET (0x21444) 6364 #define CMIC_LEDUP1_DATA_RAM170_OFFSET (0x216a8) 6365 #define CMIC_LEDUP1_DATA_RAM171_OFFSET (0x216ac) 6366 #define CMIC_LEDUP1_DATA_RAM172_OFFSET (0x216b0) 6367 #define CMIC_LEDUP1_DATA_RAM173_OFFSET (0x216b4) 6368 #define CMIC_LEDUP1_DATA_RAM174_OFFSET (0x216b8) 6369 #define CMIC_LEDUP1_DATA_RAM175_OFFSET (0x216bc) 6370 #define CMIC_LEDUP1_DATA_RAM176_OFFSET (0x216c0) 6371 #define CMIC_LEDUP1_DATA_RAM177_OFFSET (0x216c4) 6372 #define CMIC_LEDUP1_DATA_RAM178_OFFSET (0x216c8) 6373 #define CMIC_LEDUP1_DATA_RAM179_OFFSET (0x216cc) 6374 #define CMIC_LEDUP1_DATA_RAM18_OFFSET (0x21448) 6375 #define CMIC_LEDUP1_DATA_RAM180_OFFSET (0x216d0) 6376 #define CMIC_LEDUP1_DATA_RAM181_OFFSET (0x216d4) 6377 #define CMIC_LEDUP1_DATA_RAM182_OFFSET (0x216d8) 6378 #define CMIC_LEDUP1_DATA_RAM183_OFFSET (0x216dc) 6379 #define CMIC_LEDUP1_DATA_RAM184_OFFSET (0x216e0) 6380 #define CMIC_LEDUP1_DATA_RAM185_OFFSET (0x216e4) 6381 #define CMIC_LEDUP1_DATA_RAM186_OFFSET (0x216e8) 6382 #define CMIC_LEDUP1_DATA_RAM187_OFFSET (0x216ec) 6383 #define CMIC_LEDUP1_DATA_RAM188_OFFSET (0x216f0) 6384 #define CMIC_LEDUP1_DATA_RAM189_OFFSET (0x216f4) 6385 #define CMIC_LEDUP1_DATA_RAM19_OFFSET (0x2144c) 6386 #define CMIC_LEDUP1_DATA_RAM190_OFFSET (0x216f8) 6387 #define CMIC_LEDUP1_DATA_RAM191_OFFSET (0x216fc) 6388 #define CMIC_LEDUP1_DATA_RAM192_OFFSET (0x21700) 6389 #define CMIC_LEDUP1_DATA_RAM193_OFFSET (0x21704) 6390 #define CMIC_LEDUP1_DATA_RAM194_OFFSET (0x21708) 6391 #define CMIC_LEDUP1_DATA_RAM195_OFFSET (0x2170c) 6392 #define CMIC_LEDUP1_DATA_RAM196_OFFSET (0x21710) 6393 #define CMIC_LEDUP1_DATA_RAM197_OFFSET (0x21714) 6394 #define CMIC_LEDUP1_DATA_RAM198_OFFSET (0x21718) 6395 #define CMIC_LEDUP1_DATA_RAM199_OFFSET (0x2171c) 6396 #define CMIC_LEDUP1_DATA_RAM2_OFFSET (0x21408) 6397 #define CMIC_LEDUP1_DATA_RAM20_OFFSET (0x21450) 6398 #define CMIC_LEDUP1_DATA_RAM200_OFFSET (0x21720) 6399 #define CMIC_LEDUP1_DATA_RAM201_OFFSET (0x21724) 6400 #define CMIC_LEDUP1_DATA_RAM202_OFFSET (0x21728) 6401 #define CMIC_LEDUP1_DATA_RAM203_OFFSET (0x2172c) 6402 #define CMIC_LEDUP1_DATA_RAM204_OFFSET (0x21730) 6403 #define CMIC_LEDUP1_DATA_RAM205_OFFSET (0x21734) 6404 #define CMIC_LEDUP1_DATA_RAM206_OFFSET (0x21738) 6405 #define CMIC_LEDUP1_DATA_RAM207_OFFSET (0x2173c) 6406 #define CMIC_LEDUP1_DATA_RAM208_OFFSET (0x21740) 6407 #define CMIC_LEDUP1_DATA_RAM209_OFFSET (0x21744) 6408 #define CMIC_LEDUP1_DATA_RAM21_OFFSET (0x21454) 6409 #define CMIC_LEDUP1_DATA_RAM210_OFFSET (0x21748) 6410 #define CMIC_LEDUP1_DATA_RAM211_OFFSET (0x2174c) 6411 #define CMIC_LEDUP1_DATA_RAM212_OFFSET (0x21750) 6412 #define CMIC_LEDUP1_DATA_RAM213_OFFSET (0x21754) 6413 #define CMIC_LEDUP1_DATA_RAM214_OFFSET (0x21758) 6414 #define CMIC_LEDUP1_DATA_RAM215_OFFSET (0x2175c) 6415 #define CMIC_LEDUP1_DATA_RAM216_OFFSET (0x21760) 6416 #define CMIC_LEDUP1_DATA_RAM217_OFFSET (0x21764) 6417 #define CMIC_LEDUP1_DATA_RAM218_OFFSET (0x21768) 6418 #define CMIC_LEDUP1_DATA_RAM219_OFFSET (0x2176c) 6419 #define CMIC_LEDUP1_DATA_RAM22_OFFSET (0x21458) 6420 #define CMIC_LEDUP1_DATA_RAM220_OFFSET (0x21770) 6421 #define CMIC_LEDUP1_DATA_RAM221_OFFSET (0x21774) 6422 #define CMIC_LEDUP1_DATA_RAM222_OFFSET (0x21778) 6423 #define CMIC_LEDUP1_DATA_RAM223_OFFSET (0x2177c) 6424 #define CMIC_LEDUP1_DATA_RAM224_OFFSET (0x21780) 6425 #define CMIC_LEDUP1_DATA_RAM225_OFFSET (0x21784) 6426 #define CMIC_LEDUP1_DATA_RAM226_OFFSET (0x21788) 6427 #define CMIC_LEDUP1_DATA_RAM227_OFFSET (0x2178c) 6428 #define CMIC_LEDUP1_DATA_RAM228_OFFSET (0x21790) 6429 #define CMIC_LEDUP1_DATA_RAM229_OFFSET (0x21794) 6430 #define CMIC_LEDUP1_DATA_RAM23_OFFSET (0x2145c) 6431 #define CMIC_LEDUP1_DATA_RAM230_OFFSET (0x21798) 6432 #define CMIC_LEDUP1_DATA_RAM231_OFFSET (0x2179c) 6433 #define CMIC_LEDUP1_DATA_RAM232_OFFSET (0x217a0) 6434 #define CMIC_LEDUP1_DATA_RAM233_OFFSET (0x217a4) 6435 #define CMIC_LEDUP1_DATA_RAM234_OFFSET (0x217a8) 6436 #define CMIC_LEDUP1_DATA_RAM235_OFFSET (0x217ac) 6437 #define CMIC_LEDUP1_DATA_RAM236_OFFSET (0x217b0) 6438 #define CMIC_LEDUP1_DATA_RAM237_OFFSET (0x217b4) 6439 #define CMIC_LEDUP1_DATA_RAM238_OFFSET (0x217b8) 6440 #define CMIC_LEDUP1_DATA_RAM239_OFFSET (0x217bc) 6441 #define CMIC_LEDUP1_DATA_RAM24_OFFSET (0x21460) 6442 #define CMIC_LEDUP1_DATA_RAM240_OFFSET (0x217c0) 6443 #define CMIC_LEDUP1_DATA_RAM241_OFFSET (0x217c4) 6444 #define CMIC_LEDUP1_DATA_RAM242_OFFSET (0x217c8) 6445 #define CMIC_LEDUP1_DATA_RAM243_OFFSET (0x217cc) 6446 #define CMIC_LEDUP1_DATA_RAM244_OFFSET (0x217d0) 6447 #define CMIC_LEDUP1_DATA_RAM245_OFFSET (0x217d4) 6448 #define CMIC_LEDUP1_DATA_RAM246_OFFSET (0x217d8) 6449 #define CMIC_LEDUP1_DATA_RAM247_OFFSET (0x217dc) 6450 #define CMIC_LEDUP1_DATA_RAM248_OFFSET (0x217e0) 6451 #define CMIC_LEDUP1_DATA_RAM249_OFFSET (0x217e4) 6452 #define CMIC_LEDUP1_DATA_RAM25_OFFSET (0x21464) 6453 #define CMIC_LEDUP1_DATA_RAM250_OFFSET (0x217e8) 6454 #define CMIC_LEDUP1_DATA_RAM251_OFFSET (0x217ec) 6455 #define CMIC_LEDUP1_DATA_RAM252_OFFSET (0x217f0) 6456 #define CMIC_LEDUP1_DATA_RAM253_OFFSET (0x217f4) 6457 #define CMIC_LEDUP1_DATA_RAM254_OFFSET (0x217f8) 6458 #define CMIC_LEDUP1_DATA_RAM255_OFFSET (0x217fc) 6459 #define CMIC_LEDUP1_DATA_RAM26_OFFSET (0x21468) 6460 #define CMIC_LEDUP1_DATA_RAM27_OFFSET (0x2146c) 6461 #define CMIC_LEDUP1_DATA_RAM28_OFFSET (0x21470) 6462 #define CMIC_LEDUP1_DATA_RAM29_OFFSET (0x21474) 6463 #define CMIC_LEDUP1_DATA_RAM3_OFFSET (0x2140c) 6464 #define CMIC_LEDUP1_DATA_RAM30_OFFSET (0x21478) 6465 #define CMIC_LEDUP1_DATA_RAM31_OFFSET (0x2147c) 6466 #define CMIC_LEDUP1_DATA_RAM32_OFFSET (0x21480) 6467 #define CMIC_LEDUP1_DATA_RAM33_OFFSET (0x21484) 6468 #define CMIC_LEDUP1_DATA_RAM34_OFFSET (0x21488) 6469 #define CMIC_LEDUP1_DATA_RAM35_OFFSET (0x2148c) 6470 #define CMIC_LEDUP1_DATA_RAM36_OFFSET (0x21490) 6471 #define CMIC_LEDUP1_DATA_RAM37_OFFSET (0x21494) 6472 #define CMIC_LEDUP1_DATA_RAM38_OFFSET (0x21498) 6473 #define CMIC_LEDUP1_DATA_RAM39_OFFSET (0x2149c) 6474 #define CMIC_LEDUP1_DATA_RAM4_OFFSET (0x21410) 6475 #define CMIC_LEDUP1_DATA_RAM40_OFFSET (0x214a0) 6476 #define CMIC_LEDUP1_DATA_RAM41_OFFSET (0x214a4) 6477 #define CMIC_LEDUP1_DATA_RAM42_OFFSET (0x214a8) 6478 #define CMIC_LEDUP1_DATA_RAM43_OFFSET (0x214ac) 6479 #define CMIC_LEDUP1_DATA_RAM44_OFFSET (0x214b0) 6480 #define CMIC_LEDUP1_DATA_RAM45_OFFSET (0x214b4) 6481 #define CMIC_LEDUP1_DATA_RAM46_OFFSET (0x214b8) 6482 #define CMIC_LEDUP1_DATA_RAM47_OFFSET (0x214bc) 6483 #define CMIC_LEDUP1_DATA_RAM48_OFFSET (0x214c0) 6484 #define CMIC_LEDUP1_DATA_RAM49_OFFSET (0x214c4) 6485 #define CMIC_LEDUP1_DATA_RAM5_OFFSET (0x21414) 6486 #define CMIC_LEDUP1_DATA_RAM50_OFFSET (0x214c8) 6487 #define CMIC_LEDUP1_DATA_RAM51_OFFSET (0x214cc) 6488 #define CMIC_LEDUP1_DATA_RAM52_OFFSET (0x214d0) 6489 #define CMIC_LEDUP1_DATA_RAM53_OFFSET (0x214d4) 6490 #define CMIC_LEDUP1_DATA_RAM54_OFFSET (0x214d8) 6491 #define CMIC_LEDUP1_DATA_RAM55_OFFSET (0x214dc) 6492 #define CMIC_LEDUP1_DATA_RAM56_OFFSET (0x214e0) 6493 #define CMIC_LEDUP1_DATA_RAM57_OFFSET (0x214e4) 6494 #define CMIC_LEDUP1_DATA_RAM58_OFFSET (0x214e8) 6495 #define CMIC_LEDUP1_DATA_RAM59_OFFSET (0x214ec) 6496 #define CMIC_LEDUP1_DATA_RAM6_OFFSET (0x21418) 6497 #define CMIC_LEDUP1_DATA_RAM60_OFFSET (0x214f0) 6498 #define CMIC_LEDUP1_DATA_RAM61_OFFSET (0x214f4) 6499 #define CMIC_LEDUP1_DATA_RAM62_OFFSET (0x214f8) 6500 #define CMIC_LEDUP1_DATA_RAM63_OFFSET (0x214fc) 6501 #define CMIC_LEDUP1_DATA_RAM64_OFFSET (0x21500) 6502 #define CMIC_LEDUP1_DATA_RAM65_OFFSET (0x21504) 6503 #define CMIC_LEDUP1_DATA_RAM66_OFFSET (0x21508) 6504 #define CMIC_LEDUP1_DATA_RAM67_OFFSET (0x2150c) 6505 #define CMIC_LEDUP1_DATA_RAM68_OFFSET (0x21510) 6506 #define CMIC_LEDUP1_DATA_RAM69_OFFSET (0x21514) 6507 #define CMIC_LEDUP1_DATA_RAM7_OFFSET (0x2141c) 6508 #define CMIC_LEDUP1_DATA_RAM70_OFFSET (0x21518) 6509 #define CMIC_LEDUP1_DATA_RAM71_OFFSET (0x2151c) 6510 #define CMIC_LEDUP1_DATA_RAM72_OFFSET (0x21520) 6511 #define CMIC_LEDUP1_DATA_RAM73_OFFSET (0x21524) 6512 #define CMIC_LEDUP1_DATA_RAM74_OFFSET (0x21528) 6513 #define CMIC_LEDUP1_DATA_RAM75_OFFSET (0x2152c) 6514 #define CMIC_LEDUP1_DATA_RAM76_OFFSET (0x21530) 6515 #define CMIC_LEDUP1_DATA_RAM77_OFFSET (0x21534) 6516 #define CMIC_LEDUP1_DATA_RAM78_OFFSET (0x21538) 6517 #define CMIC_LEDUP1_DATA_RAM79_OFFSET (0x2153c) 6518 #define CMIC_LEDUP1_DATA_RAM8_OFFSET (0x21420) 6519 #define CMIC_LEDUP1_DATA_RAM80_OFFSET (0x21540) 6520 #define CMIC_LEDUP1_DATA_RAM81_OFFSET (0x21544) 6521 #define CMIC_LEDUP1_DATA_RAM82_OFFSET (0x21548) 6522 #define CMIC_LEDUP1_DATA_RAM83_OFFSET (0x2154c) 6523 #define CMIC_LEDUP1_DATA_RAM84_OFFSET (0x21550) 6524 #define CMIC_LEDUP1_DATA_RAM85_OFFSET (0x21554) 6525 #define CMIC_LEDUP1_DATA_RAM86_OFFSET (0x21558) 6526 #define CMIC_LEDUP1_DATA_RAM87_OFFSET (0x2155c) 6527 #define CMIC_LEDUP1_DATA_RAM88_OFFSET (0x21560) 6528 #define CMIC_LEDUP1_DATA_RAM89_OFFSET (0x21564) 6529 #define CMIC_LEDUP1_DATA_RAM9_OFFSET (0x21424) 6530 #define CMIC_LEDUP1_DATA_RAM90_OFFSET (0x21568) 6531 #define CMIC_LEDUP1_DATA_RAM91_OFFSET (0x2156c) 6532 #define CMIC_LEDUP1_DATA_RAM92_OFFSET (0x21570) 6533 #define CMIC_LEDUP1_DATA_RAM93_OFFSET (0x21574) 6534 #define CMIC_LEDUP1_DATA_RAM94_OFFSET (0x21578) 6535 #define CMIC_LEDUP1_DATA_RAM95_OFFSET (0x2157c) 6536 #define CMIC_LEDUP1_DATA_RAM96_OFFSET (0x21580) 6537 #define CMIC_LEDUP1_DATA_RAM97_OFFSET (0x21584) 6538 #define CMIC_LEDUP1_DATA_RAM98_OFFSET (0x21588) 6539 #define CMIC_LEDUP1_DATA_RAM99_OFFSET (0x2158c) 6540 #define CMIC_LEDUP1_ECC_CONFIG_OFFSET (0x21060) 6541 #define CMIC_LEDUP1_ECC_INTR_OFFSET (0x2106c) 6542 #define CMIC_LEDUP1_ECC_INTR_CLR_OFFSET (0x21070) 6543 #define CMIC_LEDUP1_ECC_INTR_ENABLE_OFFSET (0x21068) 6544 #define CMIC_LEDUP1_ECC_STATUS_OFFSET (0x21064) 6545 #define CMIC_LEDUP1_PORT_ORDER_REMAP_0_3_OFFSET (0x21010) 6546 #define CMIC_LEDUP1_PORT_ORDER_REMAP_12_15_OFFSET (0x2101c) 6547 #define CMIC_LEDUP1_PORT_ORDER_REMAP_16_19_OFFSET (0x21020) 6548 #define CMIC_LEDUP1_PORT_ORDER_REMAP_20_23_OFFSET (0x21024) 6549 #define CMIC_LEDUP1_PORT_ORDER_REMAP_24_27_OFFSET (0x21028) 6550 #define CMIC_LEDUP1_PORT_ORDER_REMAP_28_31_OFFSET (0x2102c) 6551 #define CMIC_LEDUP1_PORT_ORDER_REMAP_32_35_OFFSET (0x21030) 6552 #define CMIC_LEDUP1_PORT_ORDER_REMAP_36_39_OFFSET (0x21034) 6553 #define CMIC_LEDUP1_PORT_ORDER_REMAP_40_43_OFFSET (0x21038) 6554 #define CMIC_LEDUP1_PORT_ORDER_REMAP_44_47_OFFSET (0x2103c) 6555 #define CMIC_LEDUP1_PORT_ORDER_REMAP_48_51_OFFSET (0x21040) 6556 #define CMIC_LEDUP1_PORT_ORDER_REMAP_4_7_OFFSET (0x21014) 6557 #define CMIC_LEDUP1_PORT_ORDER_REMAP_52_55_OFFSET (0x21044) 6558 #define CMIC_LEDUP1_PORT_ORDER_REMAP_56_59_OFFSET (0x21048) 6559 #define CMIC_LEDUP1_PORT_ORDER_REMAP_60_63_OFFSET (0x2104c) 6560 #define CMIC_LEDUP1_PORT_ORDER_REMAP_8_11_OFFSET (0x21018) 6561 #define CMIC_LEDUP1_PROGRAM_RAM_OFFSET (0x21800) 6562 #define CMIC_LEDUP1_PROGRAM_RAM0_OFFSET (0x21800) 6563 #define CMIC_LEDUP1_PROGRAM_RAM1_OFFSET (0x21804) 6564 #define CMIC_LEDUP1_PROGRAM_RAM10_OFFSET (0x21828) 6565 #define CMIC_LEDUP1_PROGRAM_RAM100_OFFSET (0x21990) 6566 #define CMIC_LEDUP1_PROGRAM_RAM101_OFFSET (0x21994) 6567 #define CMIC_LEDUP1_PROGRAM_RAM102_OFFSET (0x21998) 6568 #define CMIC_LEDUP1_PROGRAM_RAM103_OFFSET (0x2199c) 6569 #define CMIC_LEDUP1_PROGRAM_RAM104_OFFSET (0x219a0) 6570 #define CMIC_LEDUP1_PROGRAM_RAM105_OFFSET (0x219a4) 6571 #define CMIC_LEDUP1_PROGRAM_RAM106_OFFSET (0x219a8) 6572 #define CMIC_LEDUP1_PROGRAM_RAM107_OFFSET (0x219ac) 6573 #define CMIC_LEDUP1_PROGRAM_RAM108_OFFSET (0x219b0) 6574 #define CMIC_LEDUP1_PROGRAM_RAM109_OFFSET (0x219b4) 6575 #define CMIC_LEDUP1_PROGRAM_RAM11_OFFSET (0x2182c) 6576 #define CMIC_LEDUP1_PROGRAM_RAM110_OFFSET (0x219b8) 6577 #define CMIC_LEDUP1_PROGRAM_RAM111_OFFSET (0x219bc) 6578 #define CMIC_LEDUP1_PROGRAM_RAM112_OFFSET (0x219c0) 6579 #define CMIC_LEDUP1_PROGRAM_RAM113_OFFSET (0x219c4) 6580 #define CMIC_LEDUP1_PROGRAM_RAM114_OFFSET (0x219c8) 6581 #define CMIC_LEDUP1_PROGRAM_RAM115_OFFSET (0x219cc) 6582 #define CMIC_LEDUP1_PROGRAM_RAM116_OFFSET (0x219d0) 6583 #define CMIC_LEDUP1_PROGRAM_RAM117_OFFSET (0x219d4) 6584 #define CMIC_LEDUP1_PROGRAM_RAM118_OFFSET (0x219d8) 6585 #define CMIC_LEDUP1_PROGRAM_RAM119_OFFSET (0x219dc) 6586 #define CMIC_LEDUP1_PROGRAM_RAM12_OFFSET (0x21830) 6587 #define CMIC_LEDUP1_PROGRAM_RAM120_OFFSET (0x219e0) 6588 #define CMIC_LEDUP1_PROGRAM_RAM121_OFFSET (0x219e4) 6589 #define CMIC_LEDUP1_PROGRAM_RAM122_OFFSET (0x219e8) 6590 #define CMIC_LEDUP1_PROGRAM_RAM123_OFFSET (0x219ec) 6591 #define CMIC_LEDUP1_PROGRAM_RAM124_OFFSET (0x219f0) 6592 #define CMIC_LEDUP1_PROGRAM_RAM125_OFFSET (0x219f4) 6593 #define CMIC_LEDUP1_PROGRAM_RAM126_OFFSET (0x219f8) 6594 #define CMIC_LEDUP1_PROGRAM_RAM127_OFFSET (0x219fc) 6595 #define CMIC_LEDUP1_PROGRAM_RAM128_OFFSET (0x21a00) 6596 #define CMIC_LEDUP1_PROGRAM_RAM129_OFFSET (0x21a04) 6597 #define CMIC_LEDUP1_PROGRAM_RAM13_OFFSET (0x21834) 6598 #define CMIC_LEDUP1_PROGRAM_RAM130_OFFSET (0x21a08) 6599 #define CMIC_LEDUP1_PROGRAM_RAM131_OFFSET (0x21a0c) 6600 #define CMIC_LEDUP1_PROGRAM_RAM132_OFFSET (0x21a10) 6601 #define CMIC_LEDUP1_PROGRAM_RAM133_OFFSET (0x21a14) 6602 #define CMIC_LEDUP1_PROGRAM_RAM134_OFFSET (0x21a18) 6603 #define CMIC_LEDUP1_PROGRAM_RAM135_OFFSET (0x21a1c) 6604 #define CMIC_LEDUP1_PROGRAM_RAM136_OFFSET (0x21a20) 6605 #define CMIC_LEDUP1_PROGRAM_RAM137_OFFSET (0x21a24) 6606 #define CMIC_LEDUP1_PROGRAM_RAM138_OFFSET (0x21a28) 6607 #define CMIC_LEDUP1_PROGRAM_RAM139_OFFSET (0x21a2c) 6608 #define CMIC_LEDUP1_PROGRAM_RAM14_OFFSET (0x21838) 6609 #define CMIC_LEDUP1_PROGRAM_RAM140_OFFSET (0x21a30) 6610 #define CMIC_LEDUP1_PROGRAM_RAM141_OFFSET (0x21a34) 6611 #define CMIC_LEDUP1_PROGRAM_RAM142_OFFSET (0x21a38) 6612 #define CMIC_LEDUP1_PROGRAM_RAM143_OFFSET (0x21a3c) 6613 #define CMIC_LEDUP1_PROGRAM_RAM144_OFFSET (0x21a40) 6614 #define CMIC_LEDUP1_PROGRAM_RAM145_OFFSET (0x21a44) 6615 #define CMIC_LEDUP1_PROGRAM_RAM146_OFFSET (0x21a48) 6616 #define CMIC_LEDUP1_PROGRAM_RAM147_OFFSET (0x21a4c) 6617 #define CMIC_LEDUP1_PROGRAM_RAM148_OFFSET (0x21a50) 6618 #define CMIC_LEDUP1_PROGRAM_RAM149_OFFSET (0x21a54) 6619 #define CMIC_LEDUP1_PROGRAM_RAM15_OFFSET (0x2183c) 6620 #define CMIC_LEDUP1_PROGRAM_RAM150_OFFSET (0x21a58) 6621 #define CMIC_LEDUP1_PROGRAM_RAM151_OFFSET (0x21a5c) 6622 #define CMIC_LEDUP1_PROGRAM_RAM152_OFFSET (0x21a60) 6623 #define CMIC_LEDUP1_PROGRAM_RAM153_OFFSET (0x21a64) 6624 #define CMIC_LEDUP1_PROGRAM_RAM154_OFFSET (0x21a68) 6625 #define CMIC_LEDUP1_PROGRAM_RAM155_OFFSET (0x21a6c) 6626 #define CMIC_LEDUP1_PROGRAM_RAM156_OFFSET (0x21a70) 6627 #define CMIC_LEDUP1_PROGRAM_RAM157_OFFSET (0x21a74) 6628 #define CMIC_LEDUP1_PROGRAM_RAM158_OFFSET (0x21a78) 6629 #define CMIC_LEDUP1_PROGRAM_RAM159_OFFSET (0x21a7c) 6630 #define CMIC_LEDUP1_PROGRAM_RAM16_OFFSET (0x21840) 6631 #define CMIC_LEDUP1_PROGRAM_RAM160_OFFSET (0x21a80) 6632 #define CMIC_LEDUP1_PROGRAM_RAM161_OFFSET (0x21a84) 6633 #define CMIC_LEDUP1_PROGRAM_RAM162_OFFSET (0x21a88) 6634 #define CMIC_LEDUP1_PROGRAM_RAM163_OFFSET (0x21a8c) 6635 #define CMIC_LEDUP1_PROGRAM_RAM164_OFFSET (0x21a90) 6636 #define CMIC_LEDUP1_PROGRAM_RAM165_OFFSET (0x21a94) 6637 #define CMIC_LEDUP1_PROGRAM_RAM166_OFFSET (0x21a98) 6638 #define CMIC_LEDUP1_PROGRAM_RAM167_OFFSET (0x21a9c) 6639 #define CMIC_LEDUP1_PROGRAM_RAM168_OFFSET (0x21aa0) 6640 #define CMIC_LEDUP1_PROGRAM_RAM169_OFFSET (0x21aa4) 6641 #define CMIC_LEDUP1_PROGRAM_RAM17_OFFSET (0x21844) 6642 #define CMIC_LEDUP1_PROGRAM_RAM170_OFFSET (0x21aa8) 6643 #define CMIC_LEDUP1_PROGRAM_RAM171_OFFSET (0x21aac) 6644 #define CMIC_LEDUP1_PROGRAM_RAM172_OFFSET (0x21ab0) 6645 #define CMIC_LEDUP1_PROGRAM_RAM173_OFFSET (0x21ab4) 6646 #define CMIC_LEDUP1_PROGRAM_RAM174_OFFSET (0x21ab8) 6647 #define CMIC_LEDUP1_PROGRAM_RAM175_OFFSET (0x21abc) 6648 #define CMIC_LEDUP1_PROGRAM_RAM176_OFFSET (0x21ac0) 6649 #define CMIC_LEDUP1_PROGRAM_RAM177_OFFSET (0x21ac4) 6650 #define CMIC_LEDUP1_PROGRAM_RAM178_OFFSET (0x21ac8) 6651 #define CMIC_LEDUP1_PROGRAM_RAM179_OFFSET (0x21acc) 6652 #define CMIC_LEDUP1_PROGRAM_RAM18_OFFSET (0x21848) 6653 #define CMIC_LEDUP1_PROGRAM_RAM180_OFFSET (0x21ad0) 6654 #define CMIC_LEDUP1_PROGRAM_RAM181_OFFSET (0x21ad4) 6655 #define CMIC_LEDUP1_PROGRAM_RAM182_OFFSET (0x21ad8) 6656 #define CMIC_LEDUP1_PROGRAM_RAM183_OFFSET (0x21adc) 6657 #define CMIC_LEDUP1_PROGRAM_RAM184_OFFSET (0x21ae0) 6658 #define CMIC_LEDUP1_PROGRAM_RAM185_OFFSET (0x21ae4) 6659 #define CMIC_LEDUP1_PROGRAM_RAM186_OFFSET (0x21ae8) 6660 #define CMIC_LEDUP1_PROGRAM_RAM187_OFFSET (0x21aec) 6661 #define CMIC_LEDUP1_PROGRAM_RAM188_OFFSET (0x21af0) 6662 #define CMIC_LEDUP1_PROGRAM_RAM189_OFFSET (0x21af4) 6663 #define CMIC_LEDUP1_PROGRAM_RAM19_OFFSET (0x2184c) 6664 #define CMIC_LEDUP1_PROGRAM_RAM190_OFFSET (0x21af8) 6665 #define CMIC_LEDUP1_PROGRAM_RAM191_OFFSET (0x21afc) 6666 #define CMIC_LEDUP1_PROGRAM_RAM192_OFFSET (0x21b00) 6667 #define CMIC_LEDUP1_PROGRAM_RAM193_OFFSET (0x21b04) 6668 #define CMIC_LEDUP1_PROGRAM_RAM194_OFFSET (0x21b08) 6669 #define CMIC_LEDUP1_PROGRAM_RAM195_OFFSET (0x21b0c) 6670 #define CMIC_LEDUP1_PROGRAM_RAM196_OFFSET (0x21b10) 6671 #define CMIC_LEDUP1_PROGRAM_RAM197_OFFSET (0x21b14) 6672 #define CMIC_LEDUP1_PROGRAM_RAM198_OFFSET (0x21b18) 6673 #define CMIC_LEDUP1_PROGRAM_RAM199_OFFSET (0x21b1c) 6674 #define CMIC_LEDUP1_PROGRAM_RAM2_OFFSET (0x21808) 6675 #define CMIC_LEDUP1_PROGRAM_RAM20_OFFSET (0x21850) 6676 #define CMIC_LEDUP1_PROGRAM_RAM200_OFFSET (0x21b20) 6677 #define CMIC_LEDUP1_PROGRAM_RAM201_OFFSET (0x21b24) 6678 #define CMIC_LEDUP1_PROGRAM_RAM202_OFFSET (0x21b28) 6679 #define CMIC_LEDUP1_PROGRAM_RAM203_OFFSET (0x21b2c) 6680 #define CMIC_LEDUP1_PROGRAM_RAM204_OFFSET (0x21b30) 6681 #define CMIC_LEDUP1_PROGRAM_RAM205_OFFSET (0x21b34) 6682 #define CMIC_LEDUP1_PROGRAM_RAM206_OFFSET (0x21b38) 6683 #define CMIC_LEDUP1_PROGRAM_RAM207_OFFSET (0x21b3c) 6684 #define CMIC_LEDUP1_PROGRAM_RAM208_OFFSET (0x21b40) 6685 #define CMIC_LEDUP1_PROGRAM_RAM209_OFFSET (0x21b44) 6686 #define CMIC_LEDUP1_PROGRAM_RAM21_OFFSET (0x21854) 6687 #define CMIC_LEDUP1_PROGRAM_RAM210_OFFSET (0x21b48) 6688 #define CMIC_LEDUP1_PROGRAM_RAM211_OFFSET (0x21b4c) 6689 #define CMIC_LEDUP1_PROGRAM_RAM212_OFFSET (0x21b50) 6690 #define CMIC_LEDUP1_PROGRAM_RAM213_OFFSET (0x21b54) 6691 #define CMIC_LEDUP1_PROGRAM_RAM214_OFFSET (0x21b58) 6692 #define CMIC_LEDUP1_PROGRAM_RAM215_OFFSET (0x21b5c) 6693 #define CMIC_LEDUP1_PROGRAM_RAM216_OFFSET (0x21b60) 6694 #define CMIC_LEDUP1_PROGRAM_RAM217_OFFSET (0x21b64) 6695 #define CMIC_LEDUP1_PROGRAM_RAM218_OFFSET (0x21b68) 6696 #define CMIC_LEDUP1_PROGRAM_RAM219_OFFSET (0x21b6c) 6697 #define CMIC_LEDUP1_PROGRAM_RAM22_OFFSET (0x21858) 6698 #define CMIC_LEDUP1_PROGRAM_RAM220_OFFSET (0x21b70) 6699 #define CMIC_LEDUP1_PROGRAM_RAM221_OFFSET (0x21b74) 6700 #define CMIC_LEDUP1_PROGRAM_RAM222_OFFSET (0x21b78) 6701 #define CMIC_LEDUP1_PROGRAM_RAM223_OFFSET (0x21b7c) 6702 #define CMIC_LEDUP1_PROGRAM_RAM224_OFFSET (0x21b80) 6703 #define CMIC_LEDUP1_PROGRAM_RAM225_OFFSET (0x21b84) 6704 #define CMIC_LEDUP1_PROGRAM_RAM226_OFFSET (0x21b88) 6705 #define CMIC_LEDUP1_PROGRAM_RAM227_OFFSET (0x21b8c) 6706 #define CMIC_LEDUP1_PROGRAM_RAM228_OFFSET (0x21b90) 6707 #define CMIC_LEDUP1_PROGRAM_RAM229_OFFSET (0x21b94) 6708 #define CMIC_LEDUP1_PROGRAM_RAM23_OFFSET (0x2185c) 6709 #define CMIC_LEDUP1_PROGRAM_RAM230_OFFSET (0x21b98) 6710 #define CMIC_LEDUP1_PROGRAM_RAM231_OFFSET (0x21b9c) 6711 #define CMIC_LEDUP1_PROGRAM_RAM232_OFFSET (0x21ba0) 6712 #define CMIC_LEDUP1_PROGRAM_RAM233_OFFSET (0x21ba4) 6713 #define CMIC_LEDUP1_PROGRAM_RAM234_OFFSET (0x21ba8) 6714 #define CMIC_LEDUP1_PROGRAM_RAM235_OFFSET (0x21bac) 6715 #define CMIC_LEDUP1_PROGRAM_RAM236_OFFSET (0x21bb0) 6716 #define CMIC_LEDUP1_PROGRAM_RAM237_OFFSET (0x21bb4) 6717 #define CMIC_LEDUP1_PROGRAM_RAM238_OFFSET (0x21bb8) 6718 #define CMIC_LEDUP1_PROGRAM_RAM239_OFFSET (0x21bbc) 6719 #define CMIC_LEDUP1_PROGRAM_RAM24_OFFSET (0x21860) 6720 #define CMIC_LEDUP1_PROGRAM_RAM240_OFFSET (0x21bc0) 6721 #define CMIC_LEDUP1_PROGRAM_RAM241_OFFSET (0x21bc4) 6722 #define CMIC_LEDUP1_PROGRAM_RAM242_OFFSET (0x21bc8) 6723 #define CMIC_LEDUP1_PROGRAM_RAM243_OFFSET (0x21bcc) 6724 #define CMIC_LEDUP1_PROGRAM_RAM244_OFFSET (0x21bd0) 6725 #define CMIC_LEDUP1_PROGRAM_RAM245_OFFSET (0x21bd4) 6726 #define CMIC_LEDUP1_PROGRAM_RAM246_OFFSET (0x21bd8) 6727 #define CMIC_LEDUP1_PROGRAM_RAM247_OFFSET (0x21bdc) 6728 #define CMIC_LEDUP1_PROGRAM_RAM248_OFFSET (0x21be0) 6729 #define CMIC_LEDUP1_PROGRAM_RAM249_OFFSET (0x21be4) 6730 #define CMIC_LEDUP1_PROGRAM_RAM25_OFFSET (0x21864) 6731 #define CMIC_LEDUP1_PROGRAM_RAM250_OFFSET (0x21be8) 6732 #define CMIC_LEDUP1_PROGRAM_RAM251_OFFSET (0x21bec) 6733 #define CMIC_LEDUP1_PROGRAM_RAM252_OFFSET (0x21bf0) 6734 #define CMIC_LEDUP1_PROGRAM_RAM253_OFFSET (0x21bf4) 6735 #define CMIC_LEDUP1_PROGRAM_RAM254_OFFSET (0x21bf8) 6736 #define CMIC_LEDUP1_PROGRAM_RAM255_OFFSET (0x21bfc) 6737 #define CMIC_LEDUP1_PROGRAM_RAM26_OFFSET (0x21868) 6738 #define CMIC_LEDUP1_PROGRAM_RAM27_OFFSET (0x2186c) 6739 #define CMIC_LEDUP1_PROGRAM_RAM28_OFFSET (0x21870) 6740 #define CMIC_LEDUP1_PROGRAM_RAM29_OFFSET (0x21874) 6741 #define CMIC_LEDUP1_PROGRAM_RAM3_OFFSET (0x2180c) 6742 #define CMIC_LEDUP1_PROGRAM_RAM30_OFFSET (0x21878) 6743 #define CMIC_LEDUP1_PROGRAM_RAM31_OFFSET (0x2187c) 6744 #define CMIC_LEDUP1_PROGRAM_RAM32_OFFSET (0x21880) 6745 #define CMIC_LEDUP1_PROGRAM_RAM33_OFFSET (0x21884) 6746 #define CMIC_LEDUP1_PROGRAM_RAM34_OFFSET (0x21888) 6747 #define CMIC_LEDUP1_PROGRAM_RAM35_OFFSET (0x2188c) 6748 #define CMIC_LEDUP1_PROGRAM_RAM36_OFFSET (0x21890) 6749 #define CMIC_LEDUP1_PROGRAM_RAM37_OFFSET (0x21894) 6750 #define CMIC_LEDUP1_PROGRAM_RAM38_OFFSET (0x21898) 6751 #define CMIC_LEDUP1_PROGRAM_RAM39_OFFSET (0x2189c) 6752 #define CMIC_LEDUP1_PROGRAM_RAM4_OFFSET (0x21810) 6753 #define CMIC_LEDUP1_PROGRAM_RAM40_OFFSET (0x218a0) 6754 #define CMIC_LEDUP1_PROGRAM_RAM41_OFFSET (0x218a4) 6755 #define CMIC_LEDUP1_PROGRAM_RAM42_OFFSET (0x218a8) 6756 #define CMIC_LEDUP1_PROGRAM_RAM43_OFFSET (0x218ac) 6757 #define CMIC_LEDUP1_PROGRAM_RAM44_OFFSET (0x218b0) 6758 #define CMIC_LEDUP1_PROGRAM_RAM45_OFFSET (0x218b4) 6759 #define CMIC_LEDUP1_PROGRAM_RAM46_OFFSET (0x218b8) 6760 #define CMIC_LEDUP1_PROGRAM_RAM47_OFFSET (0x218bc) 6761 #define CMIC_LEDUP1_PROGRAM_RAM48_OFFSET (0x218c0) 6762 #define CMIC_LEDUP1_PROGRAM_RAM49_OFFSET (0x218c4) 6763 #define CMIC_LEDUP1_PROGRAM_RAM5_OFFSET (0x21814) 6764 #define CMIC_LEDUP1_PROGRAM_RAM50_OFFSET (0x218c8) 6765 #define CMIC_LEDUP1_PROGRAM_RAM51_OFFSET (0x218cc) 6766 #define CMIC_LEDUP1_PROGRAM_RAM52_OFFSET (0x218d0) 6767 #define CMIC_LEDUP1_PROGRAM_RAM53_OFFSET (0x218d4) 6768 #define CMIC_LEDUP1_PROGRAM_RAM54_OFFSET (0x218d8) 6769 #define CMIC_LEDUP1_PROGRAM_RAM55_OFFSET (0x218dc) 6770 #define CMIC_LEDUP1_PROGRAM_RAM56_OFFSET (0x218e0) 6771 #define CMIC_LEDUP1_PROGRAM_RAM57_OFFSET (0x218e4) 6772 #define CMIC_LEDUP1_PROGRAM_RAM58_OFFSET (0x218e8) 6773 #define CMIC_LEDUP1_PROGRAM_RAM59_OFFSET (0x218ec) 6774 #define CMIC_LEDUP1_PROGRAM_RAM6_OFFSET (0x21818) 6775 #define CMIC_LEDUP1_PROGRAM_RAM60_OFFSET (0x218f0) 6776 #define CMIC_LEDUP1_PROGRAM_RAM61_OFFSET (0x218f4) 6777 #define CMIC_LEDUP1_PROGRAM_RAM62_OFFSET (0x218f8) 6778 #define CMIC_LEDUP1_PROGRAM_RAM63_OFFSET (0x218fc) 6779 #define CMIC_LEDUP1_PROGRAM_RAM64_OFFSET (0x21900) 6780 #define CMIC_LEDUP1_PROGRAM_RAM65_OFFSET (0x21904) 6781 #define CMIC_LEDUP1_PROGRAM_RAM66_OFFSET (0x21908) 6782 #define CMIC_LEDUP1_PROGRAM_RAM67_OFFSET (0x2190c) 6783 #define CMIC_LEDUP1_PROGRAM_RAM68_OFFSET (0x21910) 6784 #define CMIC_LEDUP1_PROGRAM_RAM69_OFFSET (0x21914) 6785 #define CMIC_LEDUP1_PROGRAM_RAM7_OFFSET (0x2181c) 6786 #define CMIC_LEDUP1_PROGRAM_RAM70_OFFSET (0x21918) 6787 #define CMIC_LEDUP1_PROGRAM_RAM71_OFFSET (0x2191c) 6788 #define CMIC_LEDUP1_PROGRAM_RAM72_OFFSET (0x21920) 6789 #define CMIC_LEDUP1_PROGRAM_RAM73_OFFSET (0x21924) 6790 #define CMIC_LEDUP1_PROGRAM_RAM74_OFFSET (0x21928) 6791 #define CMIC_LEDUP1_PROGRAM_RAM75_OFFSET (0x2192c) 6792 #define CMIC_LEDUP1_PROGRAM_RAM76_OFFSET (0x21930) 6793 #define CMIC_LEDUP1_PROGRAM_RAM77_OFFSET (0x21934) 6794 #define CMIC_LEDUP1_PROGRAM_RAM78_OFFSET (0x21938) 6795 #define CMIC_LEDUP1_PROGRAM_RAM79_OFFSET (0x2193c) 6796 #define CMIC_LEDUP1_PROGRAM_RAM8_OFFSET (0x21820) 6797 #define CMIC_LEDUP1_PROGRAM_RAM80_OFFSET (0x21940) 6798 #define CMIC_LEDUP1_PROGRAM_RAM81_OFFSET (0x21944) 6799 #define CMIC_LEDUP1_PROGRAM_RAM82_OFFSET (0x21948) 6800 #define CMIC_LEDUP1_PROGRAM_RAM83_OFFSET (0x2194c) 6801 #define CMIC_LEDUP1_PROGRAM_RAM84_OFFSET (0x21950) 6802 #define CMIC_LEDUP1_PROGRAM_RAM85_OFFSET (0x21954) 6803 #define CMIC_LEDUP1_PROGRAM_RAM86_OFFSET (0x21958) 6804 #define CMIC_LEDUP1_PROGRAM_RAM87_OFFSET (0x2195c) 6805 #define CMIC_LEDUP1_PROGRAM_RAM88_OFFSET (0x21960) 6806 #define CMIC_LEDUP1_PROGRAM_RAM89_OFFSET (0x21964) 6807 #define CMIC_LEDUP1_PROGRAM_RAM9_OFFSET (0x21824) 6808 #define CMIC_LEDUP1_PROGRAM_RAM90_OFFSET (0x21968) 6809 #define CMIC_LEDUP1_PROGRAM_RAM91_OFFSET (0x2196c) 6810 #define CMIC_LEDUP1_PROGRAM_RAM92_OFFSET (0x21970) 6811 #define CMIC_LEDUP1_PROGRAM_RAM93_OFFSET (0x21974) 6812 #define CMIC_LEDUP1_PROGRAM_RAM94_OFFSET (0x21978) 6813 #define CMIC_LEDUP1_PROGRAM_RAM95_OFFSET (0x2197c) 6814 #define CMIC_LEDUP1_PROGRAM_RAM96_OFFSET (0x21980) 6815 #define CMIC_LEDUP1_PROGRAM_RAM97_OFFSET (0x21984) 6816 #define CMIC_LEDUP1_PROGRAM_RAM98_OFFSET (0x21988) 6817 #define CMIC_LEDUP1_PROGRAM_RAM99_OFFSET (0x2198c) 6818 #define CMIC_LEDUP1_SCANCHAIN_ASSEMBLY_ST_ADDR_OFFSET (0x21008) 6819 #define CMIC_LEDUP1_SCANOUT_COUNT_UPPER_OFFSET (0x21054) 6820 #define CMIC_LEDUP1_STATUS_OFFSET (0x21004) 6821 #define CMIC_LEDUP1_TM_CONTROL_OFFSET (0x21058) 6822 #define CMIC_LEDUP2_CLK_DIV_OFFSET (0x2905c) 6823 #define CMIC_LEDUP2_CLK_PARAMS_OFFSET (0x29050) 6824 #define CMIC_LEDUP2_CTRL_OFFSET (0x29000) 6825 #define CMIC_LEDUP2_DATA_RAM_OFFSET (0x29400) 6826 #define CMIC_LEDUP2_DATA_RAM0_OFFSET (0x29400) 6827 #define CMIC_LEDUP2_DATA_RAM1_OFFSET (0x29404) 6828 #define CMIC_LEDUP2_DATA_RAM10_OFFSET (0x29428) 6829 #define CMIC_LEDUP2_DATA_RAM100_OFFSET (0x29590) 6830 #define CMIC_LEDUP2_DATA_RAM101_OFFSET (0x29594) 6831 #define CMIC_LEDUP2_DATA_RAM102_OFFSET (0x29598) 6832 #define CMIC_LEDUP2_DATA_RAM103_OFFSET (0x2959c) 6833 #define CMIC_LEDUP2_DATA_RAM104_OFFSET (0x295a0) 6834 #define CMIC_LEDUP2_DATA_RAM105_OFFSET (0x295a4) 6835 #define CMIC_LEDUP2_DATA_RAM106_OFFSET (0x295a8) 6836 #define CMIC_LEDUP2_DATA_RAM107_OFFSET (0x295ac) 6837 #define CMIC_LEDUP2_DATA_RAM108_OFFSET (0x295b0) 6838 #define CMIC_LEDUP2_DATA_RAM109_OFFSET (0x295b4) 6839 #define CMIC_LEDUP2_DATA_RAM11_OFFSET (0x2942c) 6840 #define CMIC_LEDUP2_DATA_RAM110_OFFSET (0x295b8) 6841 #define CMIC_LEDUP2_DATA_RAM111_OFFSET (0x295bc) 6842 #define CMIC_LEDUP2_DATA_RAM112_OFFSET (0x295c0) 6843 #define CMIC_LEDUP2_DATA_RAM113_OFFSET (0x295c4) 6844 #define CMIC_LEDUP2_DATA_RAM114_OFFSET (0x295c8) 6845 #define CMIC_LEDUP2_DATA_RAM115_OFFSET (0x295cc) 6846 #define CMIC_LEDUP2_DATA_RAM116_OFFSET (0x295d0) 6847 #define CMIC_LEDUP2_DATA_RAM117_OFFSET (0x295d4) 6848 #define CMIC_LEDUP2_DATA_RAM118_OFFSET (0x295d8) 6849 #define CMIC_LEDUP2_DATA_RAM119_OFFSET (0x295dc) 6850 #define CMIC_LEDUP2_DATA_RAM12_OFFSET (0x29430) 6851 #define CMIC_LEDUP2_DATA_RAM120_OFFSET (0x295e0) 6852 #define CMIC_LEDUP2_DATA_RAM121_OFFSET (0x295e4) 6853 #define CMIC_LEDUP2_DATA_RAM122_OFFSET (0x295e8) 6854 #define CMIC_LEDUP2_DATA_RAM123_OFFSET (0x295ec) 6855 #define CMIC_LEDUP2_DATA_RAM124_OFFSET (0x295f0) 6856 #define CMIC_LEDUP2_DATA_RAM125_OFFSET (0x295f4) 6857 #define CMIC_LEDUP2_DATA_RAM126_OFFSET (0x295f8) 6858 #define CMIC_LEDUP2_DATA_RAM127_OFFSET (0x295fc) 6859 #define CMIC_LEDUP2_DATA_RAM128_OFFSET (0x29600) 6860 #define CMIC_LEDUP2_DATA_RAM129_OFFSET (0x29604) 6861 #define CMIC_LEDUP2_DATA_RAM13_OFFSET (0x29434) 6862 #define CMIC_LEDUP2_DATA_RAM130_OFFSET (0x29608) 6863 #define CMIC_LEDUP2_DATA_RAM131_OFFSET (0x2960c) 6864 #define CMIC_LEDUP2_DATA_RAM132_OFFSET (0x29610) 6865 #define CMIC_LEDUP2_DATA_RAM133_OFFSET (0x29614) 6866 #define CMIC_LEDUP2_DATA_RAM134_OFFSET (0x29618) 6867 #define CMIC_LEDUP2_DATA_RAM135_OFFSET (0x2961c) 6868 #define CMIC_LEDUP2_DATA_RAM136_OFFSET (0x29620) 6869 #define CMIC_LEDUP2_DATA_RAM137_OFFSET (0x29624) 6870 #define CMIC_LEDUP2_DATA_RAM138_OFFSET (0x29628) 6871 #define CMIC_LEDUP2_DATA_RAM139_OFFSET (0x2962c) 6872 #define CMIC_LEDUP2_DATA_RAM14_OFFSET (0x29438) 6873 #define CMIC_LEDUP2_DATA_RAM140_OFFSET (0x29630) 6874 #define CMIC_LEDUP2_DATA_RAM141_OFFSET (0x29634) 6875 #define CMIC_LEDUP2_DATA_RAM142_OFFSET (0x29638) 6876 #define CMIC_LEDUP2_DATA_RAM143_OFFSET (0x2963c) 6877 #define CMIC_LEDUP2_DATA_RAM144_OFFSET (0x29640) 6878 #define CMIC_LEDUP2_DATA_RAM145_OFFSET (0x29644) 6879 #define CMIC_LEDUP2_DATA_RAM146_OFFSET (0x29648) 6880 #define CMIC_LEDUP2_DATA_RAM147_OFFSET (0x2964c) 6881 #define CMIC_LEDUP2_DATA_RAM148_OFFSET (0x29650) 6882 #define CMIC_LEDUP2_DATA_RAM149_OFFSET (0x29654) 6883 #define CMIC_LEDUP2_DATA_RAM15_OFFSET (0x2943c) 6884 #define CMIC_LEDUP2_DATA_RAM150_OFFSET (0x29658) 6885 #define CMIC_LEDUP2_DATA_RAM151_OFFSET (0x2965c) 6886 #define CMIC_LEDUP2_DATA_RAM152_OFFSET (0x29660) 6887 #define CMIC_LEDUP2_DATA_RAM153_OFFSET (0x29664) 6888 #define CMIC_LEDUP2_DATA_RAM154_OFFSET (0x29668) 6889 #define CMIC_LEDUP2_DATA_RAM155_OFFSET (0x2966c) 6890 #define CMIC_LEDUP2_DATA_RAM156_OFFSET (0x29670) 6891 #define CMIC_LEDUP2_DATA_RAM157_OFFSET (0x29674) 6892 #define CMIC_LEDUP2_DATA_RAM158_OFFSET (0x29678) 6893 #define CMIC_LEDUP2_DATA_RAM159_OFFSET (0x2967c) 6894 #define CMIC_LEDUP2_DATA_RAM16_OFFSET (0x29440) 6895 #define CMIC_LEDUP2_DATA_RAM160_OFFSET (0x29680) 6896 #define CMIC_LEDUP2_DATA_RAM161_OFFSET (0x29684) 6897 #define CMIC_LEDUP2_DATA_RAM162_OFFSET (0x29688) 6898 #define CMIC_LEDUP2_DATA_RAM163_OFFSET (0x2968c) 6899 #define CMIC_LEDUP2_DATA_RAM164_OFFSET (0x29690) 6900 #define CMIC_LEDUP2_DATA_RAM165_OFFSET (0x29694) 6901 #define CMIC_LEDUP2_DATA_RAM166_OFFSET (0x29698) 6902 #define CMIC_LEDUP2_DATA_RAM167_OFFSET (0x2969c) 6903 #define CMIC_LEDUP2_DATA_RAM168_OFFSET (0x296a0) 6904 #define CMIC_LEDUP2_DATA_RAM169_OFFSET (0x296a4) 6905 #define CMIC_LEDUP2_DATA_RAM17_OFFSET (0x29444) 6906 #define CMIC_LEDUP2_DATA_RAM170_OFFSET (0x296a8) 6907 #define CMIC_LEDUP2_DATA_RAM171_OFFSET (0x296ac) 6908 #define CMIC_LEDUP2_DATA_RAM172_OFFSET (0x296b0) 6909 #define CMIC_LEDUP2_DATA_RAM173_OFFSET (0x296b4) 6910 #define CMIC_LEDUP2_DATA_RAM174_OFFSET (0x296b8) 6911 #define CMIC_LEDUP2_DATA_RAM175_OFFSET (0x296bc) 6912 #define CMIC_LEDUP2_DATA_RAM176_OFFSET (0x296c0) 6913 #define CMIC_LEDUP2_DATA_RAM177_OFFSET (0x296c4) 6914 #define CMIC_LEDUP2_DATA_RAM178_OFFSET (0x296c8) 6915 #define CMIC_LEDUP2_DATA_RAM179_OFFSET (0x296cc) 6916 #define CMIC_LEDUP2_DATA_RAM18_OFFSET (0x29448) 6917 #define CMIC_LEDUP2_DATA_RAM180_OFFSET (0x296d0) 6918 #define CMIC_LEDUP2_DATA_RAM181_OFFSET (0x296d4) 6919 #define CMIC_LEDUP2_DATA_RAM182_OFFSET (0x296d8) 6920 #define CMIC_LEDUP2_DATA_RAM183_OFFSET (0x296dc) 6921 #define CMIC_LEDUP2_DATA_RAM184_OFFSET (0x296e0) 6922 #define CMIC_LEDUP2_DATA_RAM185_OFFSET (0x296e4) 6923 #define CMIC_LEDUP2_DATA_RAM186_OFFSET (0x296e8) 6924 #define CMIC_LEDUP2_DATA_RAM187_OFFSET (0x296ec) 6925 #define CMIC_LEDUP2_DATA_RAM188_OFFSET (0x296f0) 6926 #define CMIC_LEDUP2_DATA_RAM189_OFFSET (0x296f4) 6927 #define CMIC_LEDUP2_DATA_RAM19_OFFSET (0x2944c) 6928 #define CMIC_LEDUP2_DATA_RAM190_OFFSET (0x296f8) 6929 #define CMIC_LEDUP2_DATA_RAM191_OFFSET (0x296fc) 6930 #define CMIC_LEDUP2_DATA_RAM192_OFFSET (0x29700) 6931 #define CMIC_LEDUP2_DATA_RAM193_OFFSET (0x29704) 6932 #define CMIC_LEDUP2_DATA_RAM194_OFFSET (0x29708) 6933 #define CMIC_LEDUP2_DATA_RAM195_OFFSET (0x2970c) 6934 #define CMIC_LEDUP2_DATA_RAM196_OFFSET (0x29710) 6935 #define CMIC_LEDUP2_DATA_RAM197_OFFSET (0x29714) 6936 #define CMIC_LEDUP2_DATA_RAM198_OFFSET (0x29718) 6937 #define CMIC_LEDUP2_DATA_RAM199_OFFSET (0x2971c) 6938 #define CMIC_LEDUP2_DATA_RAM2_OFFSET (0x29408) 6939 #define CMIC_LEDUP2_DATA_RAM20_OFFSET (0x29450) 6940 #define CMIC_LEDUP2_DATA_RAM200_OFFSET (0x29720) 6941 #define CMIC_LEDUP2_DATA_RAM201_OFFSET (0x29724) 6942 #define CMIC_LEDUP2_DATA_RAM202_OFFSET (0x29728) 6943 #define CMIC_LEDUP2_DATA_RAM203_OFFSET (0x2972c) 6944 #define CMIC_LEDUP2_DATA_RAM204_OFFSET (0x29730) 6945 #define CMIC_LEDUP2_DATA_RAM205_OFFSET (0x29734) 6946 #define CMIC_LEDUP2_DATA_RAM206_OFFSET (0x29738) 6947 #define CMIC_LEDUP2_DATA_RAM207_OFFSET (0x2973c) 6948 #define CMIC_LEDUP2_DATA_RAM208_OFFSET (0x29740) 6949 #define CMIC_LEDUP2_DATA_RAM209_OFFSET (0x29744) 6950 #define CMIC_LEDUP2_DATA_RAM21_OFFSET (0x29454) 6951 #define CMIC_LEDUP2_DATA_RAM210_OFFSET (0x29748) 6952 #define CMIC_LEDUP2_DATA_RAM211_OFFSET (0x2974c) 6953 #define CMIC_LEDUP2_DATA_RAM212_OFFSET (0x29750) 6954 #define CMIC_LEDUP2_DATA_RAM213_OFFSET (0x29754) 6955 #define CMIC_LEDUP2_DATA_RAM214_OFFSET (0x29758) 6956 #define CMIC_LEDUP2_DATA_RAM215_OFFSET (0x2975c) 6957 #define CMIC_LEDUP2_DATA_RAM216_OFFSET (0x29760) 6958 #define CMIC_LEDUP2_DATA_RAM217_OFFSET (0x29764) 6959 #define CMIC_LEDUP2_DATA_RAM218_OFFSET (0x29768) 6960 #define CMIC_LEDUP2_DATA_RAM219_OFFSET (0x2976c) 6961 #define CMIC_LEDUP2_DATA_RAM22_OFFSET (0x29458) 6962 #define CMIC_LEDUP2_DATA_RAM220_OFFSET (0x29770) 6963 #define CMIC_LEDUP2_DATA_RAM221_OFFSET (0x29774) 6964 #define CMIC_LEDUP2_DATA_RAM222_OFFSET (0x29778) 6965 #define CMIC_LEDUP2_DATA_RAM223_OFFSET (0x2977c) 6966 #define CMIC_LEDUP2_DATA_RAM224_OFFSET (0x29780) 6967 #define CMIC_LEDUP2_DATA_RAM225_OFFSET (0x29784) 6968 #define CMIC_LEDUP2_DATA_RAM226_OFFSET (0x29788) 6969 #define CMIC_LEDUP2_DATA_RAM227_OFFSET (0x2978c) 6970 #define CMIC_LEDUP2_DATA_RAM228_OFFSET (0x29790) 6971 #define CMIC_LEDUP2_DATA_RAM229_OFFSET (0x29794) 6972 #define CMIC_LEDUP2_DATA_RAM23_OFFSET (0x2945c) 6973 #define CMIC_LEDUP2_DATA_RAM230_OFFSET (0x29798) 6974 #define CMIC_LEDUP2_DATA_RAM231_OFFSET (0x2979c) 6975 #define CMIC_LEDUP2_DATA_RAM232_OFFSET (0x297a0) 6976 #define CMIC_LEDUP2_DATA_RAM233_OFFSET (0x297a4) 6977 #define CMIC_LEDUP2_DATA_RAM234_OFFSET (0x297a8) 6978 #define CMIC_LEDUP2_DATA_RAM235_OFFSET (0x297ac) 6979 #define CMIC_LEDUP2_DATA_RAM236_OFFSET (0x297b0) 6980 #define CMIC_LEDUP2_DATA_RAM237_OFFSET (0x297b4) 6981 #define CMIC_LEDUP2_DATA_RAM238_OFFSET (0x297b8) 6982 #define CMIC_LEDUP2_DATA_RAM239_OFFSET (0x297bc) 6983 #define CMIC_LEDUP2_DATA_RAM24_OFFSET (0x29460) 6984 #define CMIC_LEDUP2_DATA_RAM240_OFFSET (0x297c0) 6985 #define CMIC_LEDUP2_DATA_RAM241_OFFSET (0x297c4) 6986 #define CMIC_LEDUP2_DATA_RAM242_OFFSET (0x297c8) 6987 #define CMIC_LEDUP2_DATA_RAM243_OFFSET (0x297cc) 6988 #define CMIC_LEDUP2_DATA_RAM244_OFFSET (0x297d0) 6989 #define CMIC_LEDUP2_DATA_RAM245_OFFSET (0x297d4) 6990 #define CMIC_LEDUP2_DATA_RAM246_OFFSET (0x297d8) 6991 #define CMIC_LEDUP2_DATA_RAM247_OFFSET (0x297dc) 6992 #define CMIC_LEDUP2_DATA_RAM248_OFFSET (0x297e0) 6993 #define CMIC_LEDUP2_DATA_RAM249_OFFSET (0x297e4) 6994 #define CMIC_LEDUP2_DATA_RAM25_OFFSET (0x29464) 6995 #define CMIC_LEDUP2_DATA_RAM250_OFFSET (0x297e8) 6996 #define CMIC_LEDUP2_DATA_RAM251_OFFSET (0x297ec) 6997 #define CMIC_LEDUP2_DATA_RAM252_OFFSET (0x297f0) 6998 #define CMIC_LEDUP2_DATA_RAM253_OFFSET (0x297f4) 6999 #define CMIC_LEDUP2_DATA_RAM254_OFFSET (0x297f8) 7000 #define CMIC_LEDUP2_DATA_RAM255_OFFSET (0x297fc) 7001 #define CMIC_LEDUP2_DATA_RAM26_OFFSET (0x29468) 7002 #define CMIC_LEDUP2_DATA_RAM27_OFFSET (0x2946c) 7003 #define CMIC_LEDUP2_DATA_RAM28_OFFSET (0x29470) 7004 #define CMIC_LEDUP2_DATA_RAM29_OFFSET (0x29474) 7005 #define CMIC_LEDUP2_DATA_RAM3_OFFSET (0x2940c) 7006 #define CMIC_LEDUP2_DATA_RAM30_OFFSET (0x29478) 7007 #define CMIC_LEDUP2_DATA_RAM31_OFFSET (0x2947c) 7008 #define CMIC_LEDUP2_DATA_RAM32_OFFSET (0x29480) 7009 #define CMIC_LEDUP2_DATA_RAM33_OFFSET (0x29484) 7010 #define CMIC_LEDUP2_DATA_RAM34_OFFSET (0x29488) 7011 #define CMIC_LEDUP2_DATA_RAM35_OFFSET (0x2948c) 7012 #define CMIC_LEDUP2_DATA_RAM36_OFFSET (0x29490) 7013 #define CMIC_LEDUP2_DATA_RAM37_OFFSET (0x29494) 7014 #define CMIC_LEDUP2_DATA_RAM38_OFFSET (0x29498) 7015 #define CMIC_LEDUP2_DATA_RAM39_OFFSET (0x2949c) 7016 #define CMIC_LEDUP2_DATA_RAM4_OFFSET (0x29410) 7017 #define CMIC_LEDUP2_DATA_RAM40_OFFSET (0x294a0) 7018 #define CMIC_LEDUP2_DATA_RAM41_OFFSET (0x294a4) 7019 #define CMIC_LEDUP2_DATA_RAM42_OFFSET (0x294a8) 7020 #define CMIC_LEDUP2_DATA_RAM43_OFFSET (0x294ac) 7021 #define CMIC_LEDUP2_DATA_RAM44_OFFSET (0x294b0) 7022 #define CMIC_LEDUP2_DATA_RAM45_OFFSET (0x294b4) 7023 #define CMIC_LEDUP2_DATA_RAM46_OFFSET (0x294b8) 7024 #define CMIC_LEDUP2_DATA_RAM47_OFFSET (0x294bc) 7025 #define CMIC_LEDUP2_DATA_RAM48_OFFSET (0x294c0) 7026 #define CMIC_LEDUP2_DATA_RAM49_OFFSET (0x294c4) 7027 #define CMIC_LEDUP2_DATA_RAM5_OFFSET (0x29414) 7028 #define CMIC_LEDUP2_DATA_RAM50_OFFSET (0x294c8) 7029 #define CMIC_LEDUP2_DATA_RAM51_OFFSET (0x294cc) 7030 #define CMIC_LEDUP2_DATA_RAM52_OFFSET (0x294d0) 7031 #define CMIC_LEDUP2_DATA_RAM53_OFFSET (0x294d4) 7032 #define CMIC_LEDUP2_DATA_RAM54_OFFSET (0x294d8) 7033 #define CMIC_LEDUP2_DATA_RAM55_OFFSET (0x294dc) 7034 #define CMIC_LEDUP2_DATA_RAM56_OFFSET (0x294e0) 7035 #define CMIC_LEDUP2_DATA_RAM57_OFFSET (0x294e4) 7036 #define CMIC_LEDUP2_DATA_RAM58_OFFSET (0x294e8) 7037 #define CMIC_LEDUP2_DATA_RAM59_OFFSET (0x294ec) 7038 #define CMIC_LEDUP2_DATA_RAM6_OFFSET (0x29418) 7039 #define CMIC_LEDUP2_DATA_RAM60_OFFSET (0x294f0) 7040 #define CMIC_LEDUP2_DATA_RAM61_OFFSET (0x294f4) 7041 #define CMIC_LEDUP2_DATA_RAM62_OFFSET (0x294f8) 7042 #define CMIC_LEDUP2_DATA_RAM63_OFFSET (0x294fc) 7043 #define CMIC_LEDUP2_DATA_RAM64_OFFSET (0x29500) 7044 #define CMIC_LEDUP2_DATA_RAM65_OFFSET (0x29504) 7045 #define CMIC_LEDUP2_DATA_RAM66_OFFSET (0x29508) 7046 #define CMIC_LEDUP2_DATA_RAM67_OFFSET (0x2950c) 7047 #define CMIC_LEDUP2_DATA_RAM68_OFFSET (0x29510) 7048 #define CMIC_LEDUP2_DATA_RAM69_OFFSET (0x29514) 7049 #define CMIC_LEDUP2_DATA_RAM7_OFFSET (0x2941c) 7050 #define CMIC_LEDUP2_DATA_RAM70_OFFSET (0x29518) 7051 #define CMIC_LEDUP2_DATA_RAM71_OFFSET (0x2951c) 7052 #define CMIC_LEDUP2_DATA_RAM72_OFFSET (0x29520) 7053 #define CMIC_LEDUP2_DATA_RAM73_OFFSET (0x29524) 7054 #define CMIC_LEDUP2_DATA_RAM74_OFFSET (0x29528) 7055 #define CMIC_LEDUP2_DATA_RAM75_OFFSET (0x2952c) 7056 #define CMIC_LEDUP2_DATA_RAM76_OFFSET (0x29530) 7057 #define CMIC_LEDUP2_DATA_RAM77_OFFSET (0x29534) 7058 #define CMIC_LEDUP2_DATA_RAM78_OFFSET (0x29538) 7059 #define CMIC_LEDUP2_DATA_RAM79_OFFSET (0x2953c) 7060 #define CMIC_LEDUP2_DATA_RAM8_OFFSET (0x29420) 7061 #define CMIC_LEDUP2_DATA_RAM80_OFFSET (0x29540) 7062 #define CMIC_LEDUP2_DATA_RAM81_OFFSET (0x29544) 7063 #define CMIC_LEDUP2_DATA_RAM82_OFFSET (0x29548) 7064 #define CMIC_LEDUP2_DATA_RAM83_OFFSET (0x2954c) 7065 #define CMIC_LEDUP2_DATA_RAM84_OFFSET (0x29550) 7066 #define CMIC_LEDUP2_DATA_RAM85_OFFSET (0x29554) 7067 #define CMIC_LEDUP2_DATA_RAM86_OFFSET (0x29558) 7068 #define CMIC_LEDUP2_DATA_RAM87_OFFSET (0x2955c) 7069 #define CMIC_LEDUP2_DATA_RAM88_OFFSET (0x29560) 7070 #define CMIC_LEDUP2_DATA_RAM89_OFFSET (0x29564) 7071 #define CMIC_LEDUP2_DATA_RAM9_OFFSET (0x29424) 7072 #define CMIC_LEDUP2_DATA_RAM90_OFFSET (0x29568) 7073 #define CMIC_LEDUP2_DATA_RAM91_OFFSET (0x2956c) 7074 #define CMIC_LEDUP2_DATA_RAM92_OFFSET (0x29570) 7075 #define CMIC_LEDUP2_DATA_RAM93_OFFSET (0x29574) 7076 #define CMIC_LEDUP2_DATA_RAM94_OFFSET (0x29578) 7077 #define CMIC_LEDUP2_DATA_RAM95_OFFSET (0x2957c) 7078 #define CMIC_LEDUP2_DATA_RAM96_OFFSET (0x29580) 7079 #define CMIC_LEDUP2_DATA_RAM97_OFFSET (0x29584) 7080 #define CMIC_LEDUP2_DATA_RAM98_OFFSET (0x29588) 7081 #define CMIC_LEDUP2_DATA_RAM99_OFFSET (0x2958c) 7082 #define CMIC_LEDUP2_ECC_CONFIG_OFFSET (0x29060) 7083 #define CMIC_LEDUP2_ECC_INTR_OFFSET (0x2906c) 7084 #define CMIC_LEDUP2_ECC_INTR_CLR_OFFSET (0x29070) 7085 #define CMIC_LEDUP2_ECC_INTR_ENABLE_OFFSET (0x29068) 7086 #define CMIC_LEDUP2_ECC_STATUS_OFFSET (0x29064) 7087 #define CMIC_LEDUP2_PORT_ORDER_REMAP_0_3_OFFSET (0x29010) 7088 #define CMIC_LEDUP2_PORT_ORDER_REMAP_12_15_OFFSET (0x2901c) 7089 #define CMIC_LEDUP2_PORT_ORDER_REMAP_16_19_OFFSET (0x29020) 7090 #define CMIC_LEDUP2_PORT_ORDER_REMAP_20_23_OFFSET (0x29024) 7091 #define CMIC_LEDUP2_PORT_ORDER_REMAP_24_27_OFFSET (0x29028) 7092 #define CMIC_LEDUP2_PORT_ORDER_REMAP_28_31_OFFSET (0x2902c) 7093 #define CMIC_LEDUP2_PORT_ORDER_REMAP_32_35_OFFSET (0x29030) 7094 #define CMIC_LEDUP2_PORT_ORDER_REMAP_36_39_OFFSET (0x29034) 7095 #define CMIC_LEDUP2_PORT_ORDER_REMAP_40_43_OFFSET (0x29038) 7096 #define CMIC_LEDUP2_PORT_ORDER_REMAP_44_47_OFFSET (0x2903c) 7097 #define CMIC_LEDUP2_PORT_ORDER_REMAP_48_51_OFFSET (0x29040) 7098 #define CMIC_LEDUP2_PORT_ORDER_REMAP_4_7_OFFSET (0x29014) 7099 #define CMIC_LEDUP2_PORT_ORDER_REMAP_52_55_OFFSET (0x29044) 7100 #define CMIC_LEDUP2_PORT_ORDER_REMAP_56_59_OFFSET (0x29048) 7101 #define CMIC_LEDUP2_PORT_ORDER_REMAP_60_63_OFFSET (0x2904c) 7102 #define CMIC_LEDUP2_PORT_ORDER_REMAP_8_11_OFFSET (0x29018) 7103 #define CMIC_LEDUP2_PROGRAM_RAM_OFFSET (0x29800) 7104 #define CMIC_LEDUP2_PROGRAM_RAM0_OFFSET (0x29800) 7105 #define CMIC_LEDUP2_PROGRAM_RAM1_OFFSET (0x29804) 7106 #define CMIC_LEDUP2_PROGRAM_RAM10_OFFSET (0x29828) 7107 #define CMIC_LEDUP2_PROGRAM_RAM100_OFFSET (0x29990) 7108 #define CMIC_LEDUP2_PROGRAM_RAM101_OFFSET (0x29994) 7109 #define CMIC_LEDUP2_PROGRAM_RAM102_OFFSET (0x29998) 7110 #define CMIC_LEDUP2_PROGRAM_RAM103_OFFSET (0x2999c) 7111 #define CMIC_LEDUP2_PROGRAM_RAM104_OFFSET (0x299a0) 7112 #define CMIC_LEDUP2_PROGRAM_RAM105_OFFSET (0x299a4) 7113 #define CMIC_LEDUP2_PROGRAM_RAM106_OFFSET (0x299a8) 7114 #define CMIC_LEDUP2_PROGRAM_RAM107_OFFSET (0x299ac) 7115 #define CMIC_LEDUP2_PROGRAM_RAM108_OFFSET (0x299b0) 7116 #define CMIC_LEDUP2_PROGRAM_RAM109_OFFSET (0x299b4) 7117 #define CMIC_LEDUP2_PROGRAM_RAM11_OFFSET (0x2982c) 7118 #define CMIC_LEDUP2_PROGRAM_RAM110_OFFSET (0x299b8) 7119 #define CMIC_LEDUP2_PROGRAM_RAM111_OFFSET (0x299bc) 7120 #define CMIC_LEDUP2_PROGRAM_RAM112_OFFSET (0x299c0) 7121 #define CMIC_LEDUP2_PROGRAM_RAM113_OFFSET (0x299c4) 7122 #define CMIC_LEDUP2_PROGRAM_RAM114_OFFSET (0x299c8) 7123 #define CMIC_LEDUP2_PROGRAM_RAM115_OFFSET (0x299cc) 7124 #define CMIC_LEDUP2_PROGRAM_RAM116_OFFSET (0x299d0) 7125 #define CMIC_LEDUP2_PROGRAM_RAM117_OFFSET (0x299d4) 7126 #define CMIC_LEDUP2_PROGRAM_RAM118_OFFSET (0x299d8) 7127 #define CMIC_LEDUP2_PROGRAM_RAM119_OFFSET (0x299dc) 7128 #define CMIC_LEDUP2_PROGRAM_RAM12_OFFSET (0x29830) 7129 #define CMIC_LEDUP2_PROGRAM_RAM120_OFFSET (0x299e0) 7130 #define CMIC_LEDUP2_PROGRAM_RAM121_OFFSET (0x299e4) 7131 #define CMIC_LEDUP2_PROGRAM_RAM122_OFFSET (0x299e8) 7132 #define CMIC_LEDUP2_PROGRAM_RAM123_OFFSET (0x299ec) 7133 #define CMIC_LEDUP2_PROGRAM_RAM124_OFFSET (0x299f0) 7134 #define CMIC_LEDUP2_PROGRAM_RAM125_OFFSET (0x299f4) 7135 #define CMIC_LEDUP2_PROGRAM_RAM126_OFFSET (0x299f8) 7136 #define CMIC_LEDUP2_PROGRAM_RAM127_OFFSET (0x299fc) 7137 #define CMIC_LEDUP2_PROGRAM_RAM128_OFFSET (0x29a00) 7138 #define CMIC_LEDUP2_PROGRAM_RAM129_OFFSET (0x29a04) 7139 #define CMIC_LEDUP2_PROGRAM_RAM13_OFFSET (0x29834) 7140 #define CMIC_LEDUP2_PROGRAM_RAM130_OFFSET (0x29a08) 7141 #define CMIC_LEDUP2_PROGRAM_RAM131_OFFSET (0x29a0c) 7142 #define CMIC_LEDUP2_PROGRAM_RAM132_OFFSET (0x29a10) 7143 #define CMIC_LEDUP2_PROGRAM_RAM133_OFFSET (0x29a14) 7144 #define CMIC_LEDUP2_PROGRAM_RAM134_OFFSET (0x29a18) 7145 #define CMIC_LEDUP2_PROGRAM_RAM135_OFFSET (0x29a1c) 7146 #define CMIC_LEDUP2_PROGRAM_RAM136_OFFSET (0x29a20) 7147 #define CMIC_LEDUP2_PROGRAM_RAM137_OFFSET (0x29a24) 7148 #define CMIC_LEDUP2_PROGRAM_RAM138_OFFSET (0x29a28) 7149 #define CMIC_LEDUP2_PROGRAM_RAM139_OFFSET (0x29a2c) 7150 #define CMIC_LEDUP2_PROGRAM_RAM14_OFFSET (0x29838) 7151 #define CMIC_LEDUP2_PROGRAM_RAM140_OFFSET (0x29a30) 7152 #define CMIC_LEDUP2_PROGRAM_RAM141_OFFSET (0x29a34) 7153 #define CMIC_LEDUP2_PROGRAM_RAM142_OFFSET (0x29a38) 7154 #define CMIC_LEDUP2_PROGRAM_RAM143_OFFSET (0x29a3c) 7155 #define CMIC_LEDUP2_PROGRAM_RAM144_OFFSET (0x29a40) 7156 #define CMIC_LEDUP2_PROGRAM_RAM145_OFFSET (0x29a44) 7157 #define CMIC_LEDUP2_PROGRAM_RAM146_OFFSET (0x29a48) 7158 #define CMIC_LEDUP2_PROGRAM_RAM147_OFFSET (0x29a4c) 7159 #define CMIC_LEDUP2_PROGRAM_RAM148_OFFSET (0x29a50) 7160 #define CMIC_LEDUP2_PROGRAM_RAM149_OFFSET (0x29a54) 7161 #define CMIC_LEDUP2_PROGRAM_RAM15_OFFSET (0x2983c) 7162 #define CMIC_LEDUP2_PROGRAM_RAM150_OFFSET (0x29a58) 7163 #define CMIC_LEDUP2_PROGRAM_RAM151_OFFSET (0x29a5c) 7164 #define CMIC_LEDUP2_PROGRAM_RAM152_OFFSET (0x29a60) 7165 #define CMIC_LEDUP2_PROGRAM_RAM153_OFFSET (0x29a64) 7166 #define CMIC_LEDUP2_PROGRAM_RAM154_OFFSET (0x29a68) 7167 #define CMIC_LEDUP2_PROGRAM_RAM155_OFFSET (0x29a6c) 7168 #define CMIC_LEDUP2_PROGRAM_RAM156_OFFSET (0x29a70) 7169 #define CMIC_LEDUP2_PROGRAM_RAM157_OFFSET (0x29a74) 7170 #define CMIC_LEDUP2_PROGRAM_RAM158_OFFSET (0x29a78) 7171 #define CMIC_LEDUP2_PROGRAM_RAM159_OFFSET (0x29a7c) 7172 #define CMIC_LEDUP2_PROGRAM_RAM16_OFFSET (0x29840) 7173 #define CMIC_LEDUP2_PROGRAM_RAM160_OFFSET (0x29a80) 7174 #define CMIC_LEDUP2_PROGRAM_RAM161_OFFSET (0x29a84) 7175 #define CMIC_LEDUP2_PROGRAM_RAM162_OFFSET (0x29a88) 7176 #define CMIC_LEDUP2_PROGRAM_RAM163_OFFSET (0x29a8c) 7177 #define CMIC_LEDUP2_PROGRAM_RAM164_OFFSET (0x29a90) 7178 #define CMIC_LEDUP2_PROGRAM_RAM165_OFFSET (0x29a94) 7179 #define CMIC_LEDUP2_PROGRAM_RAM166_OFFSET (0x29a98) 7180 #define CMIC_LEDUP2_PROGRAM_RAM167_OFFSET (0x29a9c) 7181 #define CMIC_LEDUP2_PROGRAM_RAM168_OFFSET (0x29aa0) 7182 #define CMIC_LEDUP2_PROGRAM_RAM169_OFFSET (0x29aa4) 7183 #define CMIC_LEDUP2_PROGRAM_RAM17_OFFSET (0x29844) 7184 #define CMIC_LEDUP2_PROGRAM_RAM170_OFFSET (0x29aa8) 7185 #define CMIC_LEDUP2_PROGRAM_RAM171_OFFSET (0x29aac) 7186 #define CMIC_LEDUP2_PROGRAM_RAM172_OFFSET (0x29ab0) 7187 #define CMIC_LEDUP2_PROGRAM_RAM173_OFFSET (0x29ab4) 7188 #define CMIC_LEDUP2_PROGRAM_RAM174_OFFSET (0x29ab8) 7189 #define CMIC_LEDUP2_PROGRAM_RAM175_OFFSET (0x29abc) 7190 #define CMIC_LEDUP2_PROGRAM_RAM176_OFFSET (0x29ac0) 7191 #define CMIC_LEDUP2_PROGRAM_RAM177_OFFSET (0x29ac4) 7192 #define CMIC_LEDUP2_PROGRAM_RAM178_OFFSET (0x29ac8) 7193 #define CMIC_LEDUP2_PROGRAM_RAM179_OFFSET (0x29acc) 7194 #define CMIC_LEDUP2_PROGRAM_RAM18_OFFSET (0x29848) 7195 #define CMIC_LEDUP2_PROGRAM_RAM180_OFFSET (0x29ad0) 7196 #define CMIC_LEDUP2_PROGRAM_RAM181_OFFSET (0x29ad4) 7197 #define CMIC_LEDUP2_PROGRAM_RAM182_OFFSET (0x29ad8) 7198 #define CMIC_LEDUP2_PROGRAM_RAM183_OFFSET (0x29adc) 7199 #define CMIC_LEDUP2_PROGRAM_RAM184_OFFSET (0x29ae0) 7200 #define CMIC_LEDUP2_PROGRAM_RAM185_OFFSET (0x29ae4) 7201 #define CMIC_LEDUP2_PROGRAM_RAM186_OFFSET (0x29ae8) 7202 #define CMIC_LEDUP2_PROGRAM_RAM187_OFFSET (0x29aec) 7203 #define CMIC_LEDUP2_PROGRAM_RAM188_OFFSET (0x29af0) 7204 #define CMIC_LEDUP2_PROGRAM_RAM189_OFFSET (0x29af4) 7205 #define CMIC_LEDUP2_PROGRAM_RAM19_OFFSET (0x2984c) 7206 #define CMIC_LEDUP2_PROGRAM_RAM190_OFFSET (0x29af8) 7207 #define CMIC_LEDUP2_PROGRAM_RAM191_OFFSET (0x29afc) 7208 #define CMIC_LEDUP2_PROGRAM_RAM192_OFFSET (0x29b00) 7209 #define CMIC_LEDUP2_PROGRAM_RAM193_OFFSET (0x29b04) 7210 #define CMIC_LEDUP2_PROGRAM_RAM194_OFFSET (0x29b08) 7211 #define CMIC_LEDUP2_PROGRAM_RAM195_OFFSET (0x29b0c) 7212 #define CMIC_LEDUP2_PROGRAM_RAM196_OFFSET (0x29b10) 7213 #define CMIC_LEDUP2_PROGRAM_RAM197_OFFSET (0x29b14) 7214 #define CMIC_LEDUP2_PROGRAM_RAM198_OFFSET (0x29b18) 7215 #define CMIC_LEDUP2_PROGRAM_RAM199_OFFSET (0x29b1c) 7216 #define CMIC_LEDUP2_PROGRAM_RAM2_OFFSET (0x29808) 7217 #define CMIC_LEDUP2_PROGRAM_RAM20_OFFSET (0x29850) 7218 #define CMIC_LEDUP2_PROGRAM_RAM200_OFFSET (0x29b20) 7219 #define CMIC_LEDUP2_PROGRAM_RAM201_OFFSET (0x29b24) 7220 #define CMIC_LEDUP2_PROGRAM_RAM202_OFFSET (0x29b28) 7221 #define CMIC_LEDUP2_PROGRAM_RAM203_OFFSET (0x29b2c) 7222 #define CMIC_LEDUP2_PROGRAM_RAM204_OFFSET (0x29b30) 7223 #define CMIC_LEDUP2_PROGRAM_RAM205_OFFSET (0x29b34) 7224 #define CMIC_LEDUP2_PROGRAM_RAM206_OFFSET (0x29b38) 7225 #define CMIC_LEDUP2_PROGRAM_RAM207_OFFSET (0x29b3c) 7226 #define CMIC_LEDUP2_PROGRAM_RAM208_OFFSET (0x29b40) 7227 #define CMIC_LEDUP2_PROGRAM_RAM209_OFFSET (0x29b44) 7228 #define CMIC_LEDUP2_PROGRAM_RAM21_OFFSET (0x29854) 7229 #define CMIC_LEDUP2_PROGRAM_RAM210_OFFSET (0x29b48) 7230 #define CMIC_LEDUP2_PROGRAM_RAM211_OFFSET (0x29b4c) 7231 #define CMIC_LEDUP2_PROGRAM_RAM212_OFFSET (0x29b50) 7232 #define CMIC_LEDUP2_PROGRAM_RAM213_OFFSET (0x29b54) 7233 #define CMIC_LEDUP2_PROGRAM_RAM214_OFFSET (0x29b58) 7234 #define CMIC_LEDUP2_PROGRAM_RAM215_OFFSET (0x29b5c) 7235 #define CMIC_LEDUP2_PROGRAM_RAM216_OFFSET (0x29b60) 7236 #define CMIC_LEDUP2_PROGRAM_RAM217_OFFSET (0x29b64) 7237 #define CMIC_LEDUP2_PROGRAM_RAM218_OFFSET (0x29b68) 7238 #define CMIC_LEDUP2_PROGRAM_RAM219_OFFSET (0x29b6c) 7239 #define CMIC_LEDUP2_PROGRAM_RAM22_OFFSET (0x29858) 7240 #define CMIC_LEDUP2_PROGRAM_RAM220_OFFSET (0x29b70) 7241 #define CMIC_LEDUP2_PROGRAM_RAM221_OFFSET (0x29b74) 7242 #define CMIC_LEDUP2_PROGRAM_RAM222_OFFSET (0x29b78) 7243 #define CMIC_LEDUP2_PROGRAM_RAM223_OFFSET (0x29b7c) 7244 #define CMIC_LEDUP2_PROGRAM_RAM224_OFFSET (0x29b80) 7245 #define CMIC_LEDUP2_PROGRAM_RAM225_OFFSET (0x29b84) 7246 #define CMIC_LEDUP2_PROGRAM_RAM226_OFFSET (0x29b88) 7247 #define CMIC_LEDUP2_PROGRAM_RAM227_OFFSET (0x29b8c) 7248 #define CMIC_LEDUP2_PROGRAM_RAM228_OFFSET (0x29b90) 7249 #define CMIC_LEDUP2_PROGRAM_RAM229_OFFSET (0x29b94) 7250 #define CMIC_LEDUP2_PROGRAM_RAM23_OFFSET (0x2985c) 7251 #define CMIC_LEDUP2_PROGRAM_RAM230_OFFSET (0x29b98) 7252 #define CMIC_LEDUP2_PROGRAM_RAM231_OFFSET (0x29b9c) 7253 #define CMIC_LEDUP2_PROGRAM_RAM232_OFFSET (0x29ba0) 7254 #define CMIC_LEDUP2_PROGRAM_RAM233_OFFSET (0x29ba4) 7255 #define CMIC_LEDUP2_PROGRAM_RAM234_OFFSET (0x29ba8) 7256 #define CMIC_LEDUP2_PROGRAM_RAM235_OFFSET (0x29bac) 7257 #define CMIC_LEDUP2_PROGRAM_RAM236_OFFSET (0x29bb0) 7258 #define CMIC_LEDUP2_PROGRAM_RAM237_OFFSET (0x29bb4) 7259 #define CMIC_LEDUP2_PROGRAM_RAM238_OFFSET (0x29bb8) 7260 #define CMIC_LEDUP2_PROGRAM_RAM239_OFFSET (0x29bbc) 7261 #define CMIC_LEDUP2_PROGRAM_RAM24_OFFSET (0x29860) 7262 #define CMIC_LEDUP2_PROGRAM_RAM240_OFFSET (0x29bc0) 7263 #define CMIC_LEDUP2_PROGRAM_RAM241_OFFSET (0x29bc4) 7264 #define CMIC_LEDUP2_PROGRAM_RAM242_OFFSET (0x29bc8) 7265 #define CMIC_LEDUP2_PROGRAM_RAM243_OFFSET (0x29bcc) 7266 #define CMIC_LEDUP2_PROGRAM_RAM244_OFFSET (0x29bd0) 7267 #define CMIC_LEDUP2_PROGRAM_RAM245_OFFSET (0x29bd4) 7268 #define CMIC_LEDUP2_PROGRAM_RAM246_OFFSET (0x29bd8) 7269 #define CMIC_LEDUP2_PROGRAM_RAM247_OFFSET (0x29bdc) 7270 #define CMIC_LEDUP2_PROGRAM_RAM248_OFFSET (0x29be0) 7271 #define CMIC_LEDUP2_PROGRAM_RAM249_OFFSET (0x29be4) 7272 #define CMIC_LEDUP2_PROGRAM_RAM25_OFFSET (0x29864) 7273 #define CMIC_LEDUP2_PROGRAM_RAM250_OFFSET (0x29be8) 7274 #define CMIC_LEDUP2_PROGRAM_RAM251_OFFSET (0x29bec) 7275 #define CMIC_LEDUP2_PROGRAM_RAM252_OFFSET (0x29bf0) 7276 #define CMIC_LEDUP2_PROGRAM_RAM253_OFFSET (0x29bf4) 7277 #define CMIC_LEDUP2_PROGRAM_RAM254_OFFSET (0x29bf8) 7278 #define CMIC_LEDUP2_PROGRAM_RAM255_OFFSET (0x29bfc) 7279 #define CMIC_LEDUP2_PROGRAM_RAM26_OFFSET (0x29868) 7280 #define CMIC_LEDUP2_PROGRAM_RAM27_OFFSET (0x2986c) 7281 #define CMIC_LEDUP2_PROGRAM_RAM28_OFFSET (0x29870) 7282 #define CMIC_LEDUP2_PROGRAM_RAM29_OFFSET (0x29874) 7283 #define CMIC_LEDUP2_PROGRAM_RAM3_OFFSET (0x2980c) 7284 #define CMIC_LEDUP2_PROGRAM_RAM30_OFFSET (0x29878) 7285 #define CMIC_LEDUP2_PROGRAM_RAM31_OFFSET (0x2987c) 7286 #define CMIC_LEDUP2_PROGRAM_RAM32_OFFSET (0x29880) 7287 #define CMIC_LEDUP2_PROGRAM_RAM33_OFFSET (0x29884) 7288 #define CMIC_LEDUP2_PROGRAM_RAM34_OFFSET (0x29888) 7289 #define CMIC_LEDUP2_PROGRAM_RAM35_OFFSET (0x2988c) 7290 #define CMIC_LEDUP2_PROGRAM_RAM36_OFFSET (0x29890) 7291 #define CMIC_LEDUP2_PROGRAM_RAM37_OFFSET (0x29894) 7292 #define CMIC_LEDUP2_PROGRAM_RAM38_OFFSET (0x29898) 7293 #define CMIC_LEDUP2_PROGRAM_RAM39_OFFSET (0x2989c) 7294 #define CMIC_LEDUP2_PROGRAM_RAM4_OFFSET (0x29810) 7295 #define CMIC_LEDUP2_PROGRAM_RAM40_OFFSET (0x298a0) 7296 #define CMIC_LEDUP2_PROGRAM_RAM41_OFFSET (0x298a4) 7297 #define CMIC_LEDUP2_PROGRAM_RAM42_OFFSET (0x298a8) 7298 #define CMIC_LEDUP2_PROGRAM_RAM43_OFFSET (0x298ac) 7299 #define CMIC_LEDUP2_PROGRAM_RAM44_OFFSET (0x298b0) 7300 #define CMIC_LEDUP2_PROGRAM_RAM45_OFFSET (0x298b4) 7301 #define CMIC_LEDUP2_PROGRAM_RAM46_OFFSET (0x298b8) 7302 #define CMIC_LEDUP2_PROGRAM_RAM47_OFFSET (0x298bc) 7303 #define CMIC_LEDUP2_PROGRAM_RAM48_OFFSET (0x298c0) 7304 #define CMIC_LEDUP2_PROGRAM_RAM49_OFFSET (0x298c4) 7305 #define CMIC_LEDUP2_PROGRAM_RAM5_OFFSET (0x29814) 7306 #define CMIC_LEDUP2_PROGRAM_RAM50_OFFSET (0x298c8) 7307 #define CMIC_LEDUP2_PROGRAM_RAM51_OFFSET (0x298cc) 7308 #define CMIC_LEDUP2_PROGRAM_RAM52_OFFSET (0x298d0) 7309 #define CMIC_LEDUP2_PROGRAM_RAM53_OFFSET (0x298d4) 7310 #define CMIC_LEDUP2_PROGRAM_RAM54_OFFSET (0x298d8) 7311 #define CMIC_LEDUP2_PROGRAM_RAM55_OFFSET (0x298dc) 7312 #define CMIC_LEDUP2_PROGRAM_RAM56_OFFSET (0x298e0) 7313 #define CMIC_LEDUP2_PROGRAM_RAM57_OFFSET (0x298e4) 7314 #define CMIC_LEDUP2_PROGRAM_RAM58_OFFSET (0x298e8) 7315 #define CMIC_LEDUP2_PROGRAM_RAM59_OFFSET (0x298ec) 7316 #define CMIC_LEDUP2_PROGRAM_RAM6_OFFSET (0x29818) 7317 #define CMIC_LEDUP2_PROGRAM_RAM60_OFFSET (0x298f0) 7318 #define CMIC_LEDUP2_PROGRAM_RAM61_OFFSET (0x298f4) 7319 #define CMIC_LEDUP2_PROGRAM_RAM62_OFFSET (0x298f8) 7320 #define CMIC_LEDUP2_PROGRAM_RAM63_OFFSET (0x298fc) 7321 #define CMIC_LEDUP2_PROGRAM_RAM64_OFFSET (0x29900) 7322 #define CMIC_LEDUP2_PROGRAM_RAM65_OFFSET (0x29904) 7323 #define CMIC_LEDUP2_PROGRAM_RAM66_OFFSET (0x29908) 7324 #define CMIC_LEDUP2_PROGRAM_RAM67_OFFSET (0x2990c) 7325 #define CMIC_LEDUP2_PROGRAM_RAM68_OFFSET (0x29910) 7326 #define CMIC_LEDUP2_PROGRAM_RAM69_OFFSET (0x29914) 7327 #define CMIC_LEDUP2_PROGRAM_RAM7_OFFSET (0x2981c) 7328 #define CMIC_LEDUP2_PROGRAM_RAM70_OFFSET (0x29918) 7329 #define CMIC_LEDUP2_PROGRAM_RAM71_OFFSET (0x2991c) 7330 #define CMIC_LEDUP2_PROGRAM_RAM72_OFFSET (0x29920) 7331 #define CMIC_LEDUP2_PROGRAM_RAM73_OFFSET (0x29924) 7332 #define CMIC_LEDUP2_PROGRAM_RAM74_OFFSET (0x29928) 7333 #define CMIC_LEDUP2_PROGRAM_RAM75_OFFSET (0x2992c) 7334 #define CMIC_LEDUP2_PROGRAM_RAM76_OFFSET (0x29930) 7335 #define CMIC_LEDUP2_PROGRAM_RAM77_OFFSET (0x29934) 7336 #define CMIC_LEDUP2_PROGRAM_RAM78_OFFSET (0x29938) 7337 #define CMIC_LEDUP2_PROGRAM_RAM79_OFFSET (0x2993c) 7338 #define CMIC_LEDUP2_PROGRAM_RAM8_OFFSET (0x29820) 7339 #define CMIC_LEDUP2_PROGRAM_RAM80_OFFSET (0x29940) 7340 #define CMIC_LEDUP2_PROGRAM_RAM81_OFFSET (0x29944) 7341 #define CMIC_LEDUP2_PROGRAM_RAM82_OFFSET (0x29948) 7342 #define CMIC_LEDUP2_PROGRAM_RAM83_OFFSET (0x2994c) 7343 #define CMIC_LEDUP2_PROGRAM_RAM84_OFFSET (0x29950) 7344 #define CMIC_LEDUP2_PROGRAM_RAM85_OFFSET (0x29954) 7345 #define CMIC_LEDUP2_PROGRAM_RAM86_OFFSET (0x29958) 7346 #define CMIC_LEDUP2_PROGRAM_RAM87_OFFSET (0x2995c) 7347 #define CMIC_LEDUP2_PROGRAM_RAM88_OFFSET (0x29960) 7348 #define CMIC_LEDUP2_PROGRAM_RAM89_OFFSET (0x29964) 7349 #define CMIC_LEDUP2_PROGRAM_RAM9_OFFSET (0x29824) 7350 #define CMIC_LEDUP2_PROGRAM_RAM90_OFFSET (0x29968) 7351 #define CMIC_LEDUP2_PROGRAM_RAM91_OFFSET (0x2996c) 7352 #define CMIC_LEDUP2_PROGRAM_RAM92_OFFSET (0x29970) 7353 #define CMIC_LEDUP2_PROGRAM_RAM93_OFFSET (0x29974) 7354 #define CMIC_LEDUP2_PROGRAM_RAM94_OFFSET (0x29978) 7355 #define CMIC_LEDUP2_PROGRAM_RAM95_OFFSET (0x2997c) 7356 #define CMIC_LEDUP2_PROGRAM_RAM96_OFFSET (0x29980) 7357 #define CMIC_LEDUP2_PROGRAM_RAM97_OFFSET (0x29984) 7358 #define CMIC_LEDUP2_PROGRAM_RAM98_OFFSET (0x29988) 7359 #define CMIC_LEDUP2_PROGRAM_RAM99_OFFSET (0x2998c) 7360 #define CMIC_LEDUP2_SCANCHAIN_ASSEMBLY_ST_ADDR_OFFSET (0x29008) 7361 #define CMIC_LEDUP2_SCANOUT_COUNT_UPPER_OFFSET (0x29054) 7362 #define CMIC_LEDUP2_STATUS_OFFSET (0x29004) 7363 #define CMIC_LEDUP2_TM_CONTROL_OFFSET (0x29058) 7364 #define CMIC_LEDUP3_CLK_DIV_OFFSET (0x2a05c) 7365 #define CMIC_LEDUP3_CLK_PARAMS_OFFSET (0x2a050) 7366 #define CMIC_LEDUP3_CTRL_OFFSET (0x2a000) 7367 #define CMIC_LEDUP3_DATA_RAM_OFFSET (0x2a400) 7368 #define CMIC_LEDUP3_ECC_CONFIG_OFFSET (0x2a060) 7369 #define CMIC_LEDUP3_ECC_INTR_OFFSET (0x2a06c) 7370 #define CMIC_LEDUP3_ECC_INTR_CLR_OFFSET (0x2a070) 7371 #define CMIC_LEDUP3_ECC_INTR_ENABLE_OFFSET (0x2a068) 7372 #define CMIC_LEDUP3_ECC_STATUS_OFFSET (0x2a064) 7373 #define CMIC_LEDUP3_PORT_ORDER_REMAP_0_3_OFFSET (0x2a010) 7374 #define CMIC_LEDUP3_PORT_ORDER_REMAP_12_15_OFFSET (0x2a01c) 7375 #define CMIC_LEDUP3_PORT_ORDER_REMAP_16_19_OFFSET (0x2a020) 7376 #define CMIC_LEDUP3_PORT_ORDER_REMAP_20_23_OFFSET (0x2a024) 7377 #define CMIC_LEDUP3_PORT_ORDER_REMAP_24_27_OFFSET (0x2a028) 7378 #define CMIC_LEDUP3_PORT_ORDER_REMAP_28_31_OFFSET (0x2a02c) 7379 #define CMIC_LEDUP3_PORT_ORDER_REMAP_32_35_OFFSET (0x2a030) 7380 #define CMIC_LEDUP3_PORT_ORDER_REMAP_36_39_OFFSET (0x2a034) 7381 #define CMIC_LEDUP3_PORT_ORDER_REMAP_40_43_OFFSET (0x2a038) 7382 #define CMIC_LEDUP3_PORT_ORDER_REMAP_44_47_OFFSET (0x2a03c) 7383 #define CMIC_LEDUP3_PORT_ORDER_REMAP_48_51_OFFSET (0x2a040) 7384 #define CMIC_LEDUP3_PORT_ORDER_REMAP_4_7_OFFSET (0x2a014) 7385 #define CMIC_LEDUP3_PORT_ORDER_REMAP_52_55_OFFSET (0x2a044) 7386 #define CMIC_LEDUP3_PORT_ORDER_REMAP_56_59_OFFSET (0x2a048) 7387 #define CMIC_LEDUP3_PORT_ORDER_REMAP_60_63_OFFSET (0x2a04c) 7388 #define CMIC_LEDUP3_PORT_ORDER_REMAP_8_11_OFFSET (0x2a018) 7389 #define CMIC_LEDUP3_PROGRAM_RAM_OFFSET (0x2a800) 7390 #define CMIC_LEDUP3_SCANCHAIN_ASSEMBLY_ST_ADDR_OFFSET (0x2a008) 7391 #define CMIC_LEDUP3_SCANOUT_COUNT_UPPER_OFFSET (0x2a054) 7392 #define CMIC_LEDUP3_STATUS_OFFSET (0x2a004) 7393 #define CMIC_LEDUP3_TM_CONTROL_OFFSET (0x2a058) 7394 #define CMIC_LEDUP4_CLK_DIV_OFFSET (0x2b05c) 7395 #define CMIC_LEDUP4_CLK_PARAMS_OFFSET (0x2b050) 7396 #define CMIC_LEDUP4_CTRL_OFFSET (0x2b000) 7397 #define CMIC_LEDUP4_DATA_RAM_OFFSET (0x2b400) 7398 #define CMIC_LEDUP4_ECC_CONFIG_OFFSET (0x2b060) 7399 #define CMIC_LEDUP4_ECC_INTR_OFFSET (0x2b06c) 7400 #define CMIC_LEDUP4_ECC_INTR_CLR_OFFSET (0x2b070) 7401 #define CMIC_LEDUP4_ECC_INTR_ENABLE_OFFSET (0x2b068) 7402 #define CMIC_LEDUP4_ECC_STATUS_OFFSET (0x2b064) 7403 #define CMIC_LEDUP4_PORT_ORDER_REMAP_0_3_OFFSET (0x2b010) 7404 #define CMIC_LEDUP4_PORT_ORDER_REMAP_12_15_OFFSET (0x2b01c) 7405 #define CMIC_LEDUP4_PORT_ORDER_REMAP_16_19_OFFSET (0x2b020) 7406 #define CMIC_LEDUP4_PORT_ORDER_REMAP_20_23_OFFSET (0x2b024) 7407 #define CMIC_LEDUP4_PORT_ORDER_REMAP_24_27_OFFSET (0x2b028) 7408 #define CMIC_LEDUP4_PORT_ORDER_REMAP_28_31_OFFSET (0x2b02c) 7409 #define CMIC_LEDUP4_PORT_ORDER_REMAP_32_35_OFFSET (0x2b030) 7410 #define CMIC_LEDUP4_PORT_ORDER_REMAP_36_39_OFFSET (0x2b034) 7411 #define CMIC_LEDUP4_PORT_ORDER_REMAP_40_43_OFFSET (0x2b038) 7412 #define CMIC_LEDUP4_PORT_ORDER_REMAP_44_47_OFFSET (0x2b03c) 7413 #define CMIC_LEDUP4_PORT_ORDER_REMAP_48_51_OFFSET (0x2b040) 7414 #define CMIC_LEDUP4_PORT_ORDER_REMAP_4_7_OFFSET (0x2b014) 7415 #define CMIC_LEDUP4_PORT_ORDER_REMAP_52_55_OFFSET (0x2b044) 7416 #define CMIC_LEDUP4_PORT_ORDER_REMAP_56_59_OFFSET (0x2b048) 7417 #define CMIC_LEDUP4_PORT_ORDER_REMAP_60_63_OFFSET (0x2b04c) 7418 #define CMIC_LEDUP4_PORT_ORDER_REMAP_8_11_OFFSET (0x2b018) 7419 #define CMIC_LEDUP4_PROGRAM_RAM_OFFSET (0x2b800) 7420 #define CMIC_LEDUP4_SCANCHAIN_ASSEMBLY_ST_ADDR_OFFSET (0x2b008) 7421 #define CMIC_LEDUP4_SCANOUT_COUNT_UPPER_OFFSET (0x2b054) 7422 #define CMIC_LEDUP4_STATUS_OFFSET (0x2b004) 7423 #define CMIC_LEDUP4_TM_CONTROL_OFFSET (0x2b058) 7424 #define CMIC_MIIM_AUTO_SCAN_ADDRESS_OFFSET (0x11010) 7425 #define CMIC_MIIM_BUS_SEL_MAP_103_96_OFFSET (0x1114c) 7426 #define CMIC_MIIM_BUS_SEL_MAP_109_100_OFFSET (0x11148) 7427 #define CMIC_MIIM_BUS_SEL_MAP_111_104_OFFSET (0x11150) 7428 #define CMIC_MIIM_BUS_SEL_MAP_119_110_OFFSET (0x1114c) 7429 #define CMIC_MIIM_BUS_SEL_MAP_119_112_OFFSET (0x111c0) 7430 #define CMIC_MIIM_BUS_SEL_MAP_127_120_OFFSET (0x11150) 7431 #define CMIC_MIIM_BUS_SEL_MAP_129_120_OFFSET (0x11150) 7432 #define CMIC_MIIM_BUS_SEL_MAP_135_128_OFFSET (0x111c8) 7433 #define CMIC_MIIM_BUS_SEL_MAP_139_130_OFFSET (0x111c0) 7434 #define CMIC_MIIM_BUS_SEL_MAP_143_136_OFFSET (0x111cc) 7435 #define CMIC_MIIM_BUS_SEL_MAP_149_140_OFFSET (0x111c4) 7436 #define CMIC_MIIM_BUS_SEL_MAP_151_144_OFFSET (0x111d0) 7437 #define CMIC_MIIM_BUS_SEL_MAP_159_150_OFFSET (0x111c8) 7438 #define CMIC_MIIM_BUS_SEL_MAP_159_152_OFFSET (0x111d4) 7439 #define CMIC_MIIM_BUS_SEL_MAP_15_8_OFFSET (0x11070) 7440 #define CMIC_MIIM_BUS_SEL_MAP_167_160_OFFSET (0x111d8) 7441 #define CMIC_MIIM_BUS_SEL_MAP_169_160_OFFSET (0x111cc) 7442 #define CMIC_MIIM_BUS_SEL_MAP_175_168_OFFSET (0x1123c) 7443 #define CMIC_MIIM_BUS_SEL_MAP_179_170_OFFSET (0x111d0) 7444 #define CMIC_MIIM_BUS_SEL_MAP_183_176_OFFSET (0x11240) 7445 #define CMIC_MIIM_BUS_SEL_MAP_189_180_OFFSET (0x111d4) 7446 #define CMIC_MIIM_BUS_SEL_MAP_191_184_OFFSET (0x11244) 7447 #define CMIC_MIIM_BUS_SEL_MAP_191_190_OFFSET (0x111d8) 7448 #define CMIC_MIIM_BUS_SEL_MAP_199_192_OFFSET (0x11248) 7449 #define CMIC_MIIM_BUS_SEL_MAP_19_10_OFFSET (0x11070) 7450 #define CMIC_MIIM_BUS_SEL_MAP_207_200_OFFSET (0x1124c) 7451 #define CMIC_MIIM_BUS_SEL_MAP_215_208_OFFSET (0x11250) 7452 #define CMIC_MIIM_BUS_SEL_MAP_223_216_OFFSET (0x11254) 7453 #define CMIC_MIIM_BUS_SEL_MAP_231_224_OFFSET (0x11258) 7454 #define CMIC_MIIM_BUS_SEL_MAP_239_232_OFFSET (0x1125c) 7455 #define CMIC_MIIM_BUS_SEL_MAP_23_16_OFFSET (0x11074) 7456 #define CMIC_MIIM_BUS_SEL_MAP_247_240_OFFSET (0x11260) 7457 #define CMIC_MIIM_BUS_SEL_MAP_255_248_OFFSET (0x11264) 7458 #define CMIC_MIIM_BUS_SEL_MAP_263_256_OFFSET (0x11268) 7459 #define CMIC_MIIM_BUS_SEL_MAP_271_264_OFFSET (0x1126c) 7460 #define CMIC_MIIM_BUS_SEL_MAP_279_272_OFFSET (0x11270) 7461 #define CMIC_MIIM_BUS_SEL_MAP_287_280_OFFSET (0x11274) 7462 #define CMIC_MIIM_BUS_SEL_MAP_295_288_OFFSET (0x11278) 7463 #define CMIC_MIIM_BUS_SEL_MAP_29_20_OFFSET (0x11074) 7464 #define CMIC_MIIM_BUS_SEL_MAP_303_296_OFFSET (0x1127c) 7465 #define CMIC_MIIM_BUS_SEL_MAP_311_304_OFFSET (0x11280) 7466 #define CMIC_MIIM_BUS_SEL_MAP_319_312_OFFSET (0x11284) 7467 #define CMIC_MIIM_BUS_SEL_MAP_31_24_OFFSET (0x11078) 7468 #define CMIC_MIIM_BUS_SEL_MAP_39_30_OFFSET (0x11078) 7469 #define CMIC_MIIM_BUS_SEL_MAP_39_32_OFFSET (0x1107c) 7470 #define CMIC_MIIM_BUS_SEL_MAP_47_40_OFFSET (0x11080) 7471 #define CMIC_MIIM_BUS_SEL_MAP_49_40_OFFSET (0x1107c) 7472 #define CMIC_MIIM_BUS_SEL_MAP_55_48_OFFSET (0x11084) 7473 #define CMIC_MIIM_BUS_SEL_MAP_59_50_OFFSET (0x11080) 7474 #define CMIC_MIIM_BUS_SEL_MAP_63_56_OFFSET (0x11088) 7475 #define CMIC_MIIM_BUS_SEL_MAP_69_60_OFFSET (0x11084) 7476 #define CMIC_MIIM_BUS_SEL_MAP_71_64_OFFSET (0x1108c) 7477 #define CMIC_MIIM_BUS_SEL_MAP_79_70_OFFSET (0x11088) 7478 #define CMIC_MIIM_BUS_SEL_MAP_79_72_OFFSET (0x11090) 7479 #define CMIC_MIIM_BUS_SEL_MAP_7_0_OFFSET (0x1106c) 7480 #define CMIC_MIIM_BUS_SEL_MAP_87_80_OFFSET (0x11144) 7481 #define CMIC_MIIM_BUS_SEL_MAP_89_80_OFFSET (0x1108c) 7482 #define CMIC_MIIM_BUS_SEL_MAP_95_88_OFFSET (0x11148) 7483 #define CMIC_MIIM_BUS_SEL_MAP_95_90_OFFSET (0x11090) 7484 #define CMIC_MIIM_BUS_SEL_MAP_99_90_OFFSET (0x11144) 7485 #define CMIC_MIIM_BUS_SEL_MAP_9_0_OFFSET (0x1106c) 7486 #define CMIC_MIIM_CLR_SCAN_STATUS_OFFSET (0x11124) 7487 #define CMIC_MIIM_CONFIG_OFFSET (0x11184) 7488 #define CMIC_MIIM_EXT_PHY_ADDR_MAP_103_100_OFFSET (0x11158) 7489 #define CMIC_MIIM_EXT_PHY_ADDR_MAP_107_104_OFFSET (0x1115c) 7490 #define CMIC_MIIM_EXT_PHY_ADDR_MAP_111_108_OFFSET (0x11160) 7491 #define CMIC_MIIM_EXT_PHY_ADDR_MAP_115_112_OFFSET (0x11164) 7492 #define CMIC_MIIM_EXT_PHY_ADDR_MAP_119_116_OFFSET (0x11168) 7493 #define CMIC_MIIM_EXT_PHY_ADDR_MAP_11_8_OFFSET (0x1109c) 7494 #define CMIC_MIIM_EXT_PHY_ADDR_MAP_123_120_OFFSET (0x1116c) 7495 #define CMIC_MIIM_EXT_PHY_ADDR_MAP_127_124_OFFSET (0x11170) 7496 #define CMIC_MIIM_EXT_PHY_ADDR_MAP_131_128_OFFSET (0x111dc) 7497 #define CMIC_MIIM_EXT_PHY_ADDR_MAP_135_132_OFFSET (0x111e0) 7498 #define CMIC_MIIM_EXT_PHY_ADDR_MAP_139_136_OFFSET (0x111e4) 7499 #define CMIC_MIIM_EXT_PHY_ADDR_MAP_143_140_OFFSET (0x111e8) 7500 #define CMIC_MIIM_EXT_PHY_ADDR_MAP_147_144_OFFSET (0x111ec) 7501 #define CMIC_MIIM_EXT_PHY_ADDR_MAP_151_148_OFFSET (0x111f0) 7502 #define CMIC_MIIM_EXT_PHY_ADDR_MAP_155_152_OFFSET (0x111f4) 7503 #define CMIC_MIIM_EXT_PHY_ADDR_MAP_159_156_OFFSET (0x111f8) 7504 #define CMIC_MIIM_EXT_PHY_ADDR_MAP_15_12_OFFSET (0x110a0) 7505 #define CMIC_MIIM_EXT_PHY_ADDR_MAP_163_160_OFFSET (0x111fc) 7506 #define CMIC_MIIM_EXT_PHY_ADDR_MAP_167_164_OFFSET (0x11200) 7507 #define CMIC_MIIM_EXT_PHY_ADDR_MAP_171_168_OFFSET (0x11204) 7508 #define CMIC_MIIM_EXT_PHY_ADDR_MAP_175_172_OFFSET (0x11208) 7509 #define CMIC_MIIM_EXT_PHY_ADDR_MAP_179_176_OFFSET (0x1120c) 7510 #define CMIC_MIIM_EXT_PHY_ADDR_MAP_183_180_OFFSET (0x11210) 7511 #define CMIC_MIIM_EXT_PHY_ADDR_MAP_187_184_OFFSET (0x11214) 7512 #define CMIC_MIIM_EXT_PHY_ADDR_MAP_191_188_OFFSET (0x11218) 7513 #define CMIC_MIIM_EXT_PHY_ADDR_MAP_195_192_OFFSET (0x11288) 7514 #define CMIC_MIIM_EXT_PHY_ADDR_MAP_199_196_OFFSET (0x1128c) 7515 #define CMIC_MIIM_EXT_PHY_ADDR_MAP_19_16_OFFSET (0x110a4) 7516 #define CMIC_MIIM_EXT_PHY_ADDR_MAP_203_200_OFFSET (0x11290) 7517 #define CMIC_MIIM_EXT_PHY_ADDR_MAP_207_204_OFFSET (0x11294) 7518 #define CMIC_MIIM_EXT_PHY_ADDR_MAP_211_208_OFFSET (0x11298) 7519 #define CMIC_MIIM_EXT_PHY_ADDR_MAP_215_212_OFFSET (0x1129c) 7520 #define CMIC_MIIM_EXT_PHY_ADDR_MAP_219_216_OFFSET (0x112a0) 7521 #define CMIC_MIIM_EXT_PHY_ADDR_MAP_223_220_OFFSET (0x112a4) 7522 #define CMIC_MIIM_EXT_PHY_ADDR_MAP_227_224_OFFSET (0x112a8) 7523 #define CMIC_MIIM_EXT_PHY_ADDR_MAP_231_228_OFFSET (0x112ac) 7524 #define CMIC_MIIM_EXT_PHY_ADDR_MAP_235_232_OFFSET (0x112b0) 7525 #define CMIC_MIIM_EXT_PHY_ADDR_MAP_239_236_OFFSET (0x112b4) 7526 #define CMIC_MIIM_EXT_PHY_ADDR_MAP_23_20_OFFSET (0x110a8) 7527 #define CMIC_MIIM_EXT_PHY_ADDR_MAP_243_240_OFFSET (0x112b8) 7528 #define CMIC_MIIM_EXT_PHY_ADDR_MAP_247_244_OFFSET (0x112bc) 7529 #define CMIC_MIIM_EXT_PHY_ADDR_MAP_251_248_OFFSET (0x112c0) 7530 #define CMIC_MIIM_EXT_PHY_ADDR_MAP_255_252_OFFSET (0x112c4) 7531 #define CMIC_MIIM_EXT_PHY_ADDR_MAP_259_256_OFFSET (0x112c8) 7532 #define CMIC_MIIM_EXT_PHY_ADDR_MAP_263_260_OFFSET (0x112cc) 7533 #define CMIC_MIIM_EXT_PHY_ADDR_MAP_267_264_OFFSET (0x112d0) 7534 #define CMIC_MIIM_EXT_PHY_ADDR_MAP_271_268_OFFSET (0x112d4) 7535 #define CMIC_MIIM_EXT_PHY_ADDR_MAP_275_272_OFFSET (0x112d8) 7536 #define CMIC_MIIM_EXT_PHY_ADDR_MAP_279_276_OFFSET (0x112dc) 7537 #define CMIC_MIIM_EXT_PHY_ADDR_MAP_27_24_OFFSET (0x110ac) 7538 #define CMIC_MIIM_EXT_PHY_ADDR_MAP_283_280_OFFSET (0x112e0) 7539 #define CMIC_MIIM_EXT_PHY_ADDR_MAP_287_284_OFFSET (0x112e4) 7540 #define CMIC_MIIM_EXT_PHY_ADDR_MAP_291_288_OFFSET (0x112e8) 7541 #define CMIC_MIIM_EXT_PHY_ADDR_MAP_295_292_OFFSET (0x112ec) 7542 #define CMIC_MIIM_EXT_PHY_ADDR_MAP_299_296_OFFSET (0x112f0) 7543 #define CMIC_MIIM_EXT_PHY_ADDR_MAP_303_300_OFFSET (0x112f4) 7544 #define CMIC_MIIM_EXT_PHY_ADDR_MAP_307_304_OFFSET (0x112f8) 7545 #define CMIC_MIIM_EXT_PHY_ADDR_MAP_311_308_OFFSET (0x112fc) 7546 #define CMIC_MIIM_EXT_PHY_ADDR_MAP_315_312_OFFSET (0x11300) 7547 #define CMIC_MIIM_EXT_PHY_ADDR_MAP_319_316_OFFSET (0x11304) 7548 #define CMIC_MIIM_EXT_PHY_ADDR_MAP_31_28_OFFSET (0x110b0) 7549 #define CMIC_MIIM_EXT_PHY_ADDR_MAP_35_32_OFFSET (0x110b4) 7550 #define CMIC_MIIM_EXT_PHY_ADDR_MAP_39_36_OFFSET (0x110b8) 7551 #define CMIC_MIIM_EXT_PHY_ADDR_MAP_3_0_OFFSET (0x11094) 7552 #define CMIC_MIIM_EXT_PHY_ADDR_MAP_43_40_OFFSET (0x110bc) 7553 #define CMIC_MIIM_EXT_PHY_ADDR_MAP_47_44_OFFSET (0x110c0) 7554 #define CMIC_MIIM_EXT_PHY_ADDR_MAP_51_48_OFFSET (0x110c4) 7555 #define CMIC_MIIM_EXT_PHY_ADDR_MAP_55_52_OFFSET (0x110c8) 7556 #define CMIC_MIIM_EXT_PHY_ADDR_MAP_59_56_OFFSET (0x110cc) 7557 #define CMIC_MIIM_EXT_PHY_ADDR_MAP_63_60_OFFSET (0x110d0) 7558 #define CMIC_MIIM_EXT_PHY_ADDR_MAP_67_64_OFFSET (0x110d4) 7559 #define CMIC_MIIM_EXT_PHY_ADDR_MAP_71_68_OFFSET (0x110d8) 7560 #define CMIC_MIIM_EXT_PHY_ADDR_MAP_75_72_OFFSET (0x110dc) 7561 #define CMIC_MIIM_EXT_PHY_ADDR_MAP_79_76_OFFSET (0x110e0) 7562 #define CMIC_MIIM_EXT_PHY_ADDR_MAP_7_4_OFFSET (0x11098) 7563 #define CMIC_MIIM_EXT_PHY_ADDR_MAP_83_80_OFFSET (0x110e4) 7564 #define CMIC_MIIM_EXT_PHY_ADDR_MAP_87_84_OFFSET (0x110e8) 7565 #define CMIC_MIIM_EXT_PHY_ADDR_MAP_91_88_OFFSET (0x110ec) 7566 #define CMIC_MIIM_EXT_PHY_ADDR_MAP_95_92_OFFSET (0x110f0) 7567 #define CMIC_MIIM_EXT_PHY_ADDR_MAP_99_96_OFFSET (0x11154) 7568 #define CMIC_MIIM_INT_SEL_MAP_0_OFFSET (0x11060) 7569 #define CMIC_MIIM_INT_SEL_MAP_1_OFFSET (0x11064) 7570 #define CMIC_MIIM_INT_SEL_MAP_2_OFFSET (0x11068) 7571 #define CMIC_MIIM_INT_SEL_MAP_3_OFFSET (0x11140) 7572 #define CMIC_MIIM_INT_SEL_MAP_4_OFFSET (0x111b8) 7573 #define CMIC_MIIM_INT_SEL_MAP_5_OFFSET (0x111bc) 7574 #define CMIC_MIIM_INT_SEL_MAP_6_OFFSET (0x11368) 7575 #define CMIC_MIIM_INT_SEL_MAP_7_OFFSET (0x1136c) 7576 #define CMIC_MIIM_INT_SEL_MAP_8_OFFSET (0x11370) 7577 #define CMIC_MIIM_INT_SEL_MAP_9_OFFSET (0x11374) 7578 #define CMIC_MIIM_LINK_STATUS_0_OFFSET (0x11018) 7579 #define CMIC_MIIM_LINK_STATUS_1_OFFSET (0x1101c) 7580 #define CMIC_MIIM_LINK_STATUS_2_OFFSET (0x11020) 7581 #define CMIC_MIIM_LINK_STATUS_3_OFFSET (0x11128) 7582 #define CMIC_MIIM_LINK_STATUS_4_OFFSET (0x11188) 7583 #define CMIC_MIIM_LINK_STATUS_5_OFFSET (0x1118c) 7584 #define CMIC_MIIM_LINK_STATUS_6_OFFSET (0x11308) 7585 #define CMIC_MIIM_LINK_STATUS_7_OFFSET (0x1130c) 7586 #define CMIC_MIIM_LINK_STATUS_8_OFFSET (0x11310) 7587 #define CMIC_MIIM_LINK_STATUS_9_OFFSET (0x11314) 7588 #define CMIC_MIIM_PAUSE_MIIM_ADDRESS_OFFSET (0x11014) 7589 #define CMIC_MIIM_PAUSE_SCAN_PORTS_0_OFFSET (0x11048) 7590 #define CMIC_MIIM_PAUSE_SCAN_PORTS_1_OFFSET (0x1104c) 7591 #define CMIC_MIIM_PAUSE_SCAN_PORTS_2_OFFSET (0x11050) 7592 #define CMIC_MIIM_PAUSE_SCAN_PORTS_3_OFFSET (0x11138) 7593 #define CMIC_MIIM_PAUSE_SCAN_PORTS_4_OFFSET (0x111a8) 7594 #define CMIC_MIIM_PAUSE_SCAN_PORTS_5_OFFSET (0x111ac) 7595 #define CMIC_MIIM_PAUSE_SCAN_PORTS_6_OFFSET (0x11348) 7596 #define CMIC_MIIM_PAUSE_SCAN_PORTS_7_OFFSET (0x1134c) 7597 #define CMIC_MIIM_PAUSE_SCAN_PORTS_8_OFFSET (0x11350) 7598 #define CMIC_MIIM_PAUSE_SCAN_PORTS_9_OFFSET (0x11354) 7599 #define CMIC_MIIM_PROTOCOL_MAP_0_OFFSET (0x11054) 7600 #define CMIC_MIIM_PROTOCOL_MAP_1_OFFSET (0x11058) 7601 #define CMIC_MIIM_PROTOCOL_MAP_2_OFFSET (0x1105c) 7602 #define CMIC_MIIM_PROTOCOL_MAP_3_OFFSET (0x1113c) 7603 #define CMIC_MIIM_PROTOCOL_MAP_4_OFFSET (0x111b0) 7604 #define CMIC_MIIM_PROTOCOL_MAP_5_OFFSET (0x111b4) 7605 #define CMIC_MIIM_PROTOCOL_MAP_6_OFFSET (0x11358) 7606 #define CMIC_MIIM_PROTOCOL_MAP_7_OFFSET (0x1135c) 7607 #define CMIC_MIIM_PROTOCOL_MAP_8_OFFSET (0x11360) 7608 #define CMIC_MIIM_PROTOCOL_MAP_9_OFFSET (0x11364) 7609 #define CMIC_MIIM_RX_PAUSE_CAPABILITY_0_OFFSET (0x110f4) 7610 #define CMIC_MIIM_RX_PAUSE_CAPABILITY_1_OFFSET (0x110f8) 7611 #define CMIC_MIIM_RX_PAUSE_CAPABILITY_2_OFFSET (0x110fc) 7612 #define CMIC_MIIM_RX_PAUSE_CAPABILITY_3_OFFSET (0x11174) 7613 #define CMIC_MIIM_RX_PAUSE_CAPABILITY_4_OFFSET (0x1121c) 7614 #define CMIC_MIIM_RX_PAUSE_CAPABILITY_5_OFFSET (0x11220) 7615 #define CMIC_MIIM_RX_PAUSE_CAPABILITY_6_OFFSET (0x11378) 7616 #define CMIC_MIIM_RX_PAUSE_CAPABILITY_7_OFFSET (0x1137c) 7617 #define CMIC_MIIM_RX_PAUSE_CAPABILITY_8_OFFSET (0x11380) 7618 #define CMIC_MIIM_RX_PAUSE_CAPABILITY_9_OFFSET (0x11384) 7619 #define CMIC_MIIM_RX_PAUSE_OVERRIDE_CONTROL_0_OFFSET (0x11100) 7620 #define CMIC_MIIM_RX_PAUSE_OVERRIDE_CONTROL_1_OFFSET (0x11104) 7621 #define CMIC_MIIM_RX_PAUSE_OVERRIDE_CONTROL_2_OFFSET (0x11108) 7622 #define CMIC_MIIM_RX_PAUSE_OVERRIDE_CONTROL_3_OFFSET (0x11178) 7623 #define CMIC_MIIM_RX_PAUSE_OVERRIDE_CONTROL_4_OFFSET (0x11224) 7624 #define CMIC_MIIM_RX_PAUSE_OVERRIDE_CONTROL_5_OFFSET (0x11228) 7625 #define CMIC_MIIM_RX_PAUSE_OVERRIDE_CONTROL_6_OFFSET (0x11388) 7626 #define CMIC_MIIM_RX_PAUSE_OVERRIDE_CONTROL_7_OFFSET (0x1138c) 7627 #define CMIC_MIIM_RX_PAUSE_OVERRIDE_CONTROL_8_OFFSET (0x11390) 7628 #define CMIC_MIIM_RX_PAUSE_OVERRIDE_CONTROL_9_OFFSET (0x11394) 7629 #define CMIC_MIIM_RX_PAUSE_STATUS_0_OFFSET (0x11024) 7630 #define CMIC_MIIM_RX_PAUSE_STATUS_1_OFFSET (0x11028) 7631 #define CMIC_MIIM_RX_PAUSE_STATUS_2_OFFSET (0x1102c) 7632 #define CMIC_MIIM_RX_PAUSE_STATUS_3_OFFSET (0x1112c) 7633 #define CMIC_MIIM_RX_PAUSE_STATUS_4_OFFSET (0x11190) 7634 #define CMIC_MIIM_RX_PAUSE_STATUS_5_OFFSET (0x11194) 7635 #define CMIC_MIIM_RX_PAUSE_STATUS_6_OFFSET (0x11318) 7636 #define CMIC_MIIM_RX_PAUSE_STATUS_7_OFFSET (0x1131c) 7637 #define CMIC_MIIM_RX_PAUSE_STATUS_8_OFFSET (0x11320) 7638 #define CMIC_MIIM_RX_PAUSE_STATUS_9_OFFSET (0x11324) 7639 #define CMIC_MIIM_SCAN_CTRL_OFFSET (0x11008) 7640 #define CMIC_MIIM_SCAN_PORTS_0_OFFSET (0x1103c) 7641 #define CMIC_MIIM_SCAN_PORTS_1_OFFSET (0x11040) 7642 #define CMIC_MIIM_SCAN_PORTS_2_OFFSET (0x11044) 7643 #define CMIC_MIIM_SCAN_PORTS_3_OFFSET (0x11134) 7644 #define CMIC_MIIM_SCAN_PORTS_4_OFFSET (0x111a0) 7645 #define CMIC_MIIM_SCAN_PORTS_5_OFFSET (0x111a4) 7646 #define CMIC_MIIM_SCAN_PORTS_6_OFFSET (0x11338) 7647 #define CMIC_MIIM_SCAN_PORTS_7_OFFSET (0x1133c) 7648 #define CMIC_MIIM_SCAN_PORTS_8_OFFSET (0x11340) 7649 #define CMIC_MIIM_SCAN_PORTS_9_OFFSET (0x11344) 7650 #define CMIC_MIIM_SCAN_STATUS_OFFSET (0x1100c) 7651 #define CMIC_MIIM_TX_PAUSE_CAPABILITY_0_OFFSET (0x1110c) 7652 #define CMIC_MIIM_TX_PAUSE_CAPABILITY_1_OFFSET (0x11110) 7653 #define CMIC_MIIM_TX_PAUSE_CAPABILITY_2_OFFSET (0x11114) 7654 #define CMIC_MIIM_TX_PAUSE_CAPABILITY_3_OFFSET (0x1117c) 7655 #define CMIC_MIIM_TX_PAUSE_CAPABILITY_4_OFFSET (0x1122c) 7656 #define CMIC_MIIM_TX_PAUSE_CAPABILITY_5_OFFSET (0x11230) 7657 #define CMIC_MIIM_TX_PAUSE_CAPABILITY_6_OFFSET (0x11398) 7658 #define CMIC_MIIM_TX_PAUSE_CAPABILITY_7_OFFSET (0x1139c) 7659 #define CMIC_MIIM_TX_PAUSE_CAPABILITY_8_OFFSET (0x113a0) 7660 #define CMIC_MIIM_TX_PAUSE_CAPABILITY_9_OFFSET (0x113a4) 7661 #define CMIC_MIIM_TX_PAUSE_OVERRIDE_CONTROL_0_OFFSET (0x11118) 7662 #define CMIC_MIIM_TX_PAUSE_OVERRIDE_CONTROL_1_OFFSET (0x1111c) 7663 #define CMIC_MIIM_TX_PAUSE_OVERRIDE_CONTROL_2_OFFSET (0x11120) 7664 #define CMIC_MIIM_TX_PAUSE_OVERRIDE_CONTROL_3_OFFSET (0x11180) 7665 #define CMIC_MIIM_TX_PAUSE_OVERRIDE_CONTROL_4_OFFSET (0x11234) 7666 #define CMIC_MIIM_TX_PAUSE_OVERRIDE_CONTROL_5_OFFSET (0x11238) 7667 #define CMIC_MIIM_TX_PAUSE_OVERRIDE_CONTROL_6_OFFSET (0x113a8) 7668 #define CMIC_MIIM_TX_PAUSE_OVERRIDE_CONTROL_7_OFFSET (0x113ac) 7669 #define CMIC_MIIM_TX_PAUSE_OVERRIDE_CONTROL_8_OFFSET (0x113b0) 7670 #define CMIC_MIIM_TX_PAUSE_OVERRIDE_CONTROL_9_OFFSET (0x113b4) 7671 #define CMIC_MIIM_TX_PAUSE_STATUS_0_OFFSET (0x11030) 7672 #define CMIC_MIIM_TX_PAUSE_STATUS_1_OFFSET (0x11034) 7673 #define CMIC_MIIM_TX_PAUSE_STATUS_2_OFFSET (0x11038) 7674 #define CMIC_MIIM_TX_PAUSE_STATUS_3_OFFSET (0x11130) 7675 #define CMIC_MIIM_TX_PAUSE_STATUS_4_OFFSET (0x11198) 7676 #define CMIC_MIIM_TX_PAUSE_STATUS_5_OFFSET (0x1119c) 7677 #define CMIC_MIIM_TX_PAUSE_STATUS_6_OFFSET (0x11328) 7678 #define CMIC_MIIM_TX_PAUSE_STATUS_7_OFFSET (0x1132c) 7679 #define CMIC_MIIM_TX_PAUSE_STATUS_8_OFFSET (0x11330) 7680 #define CMIC_MIIM_TX_PAUSE_STATUS_9_OFFSET (0x11334) 7681 #define CMIC_MISC_CONTROL_OFFSET (0x10198) 7682 #define CMIC_MISC_STATUS_OFFSET (0x1019c) 7683 #define CMIC_MMU_COSLC_COUNT_ADDR_OFFSET (0x23000) 7684 #define CMIC_MMU_COSLC_COUNT_DATA_OFFSET (0x23004) 7685 #define CMIC_OVERRIDE_STRAP_OFFSET (0x10234) 7686 #define CMIC_PCIE_CFG_ADDRESS_OFFSET (0x27000) 7687 #define CMIC_PCIE_CFG_READ_DATA_OFFSET (0x27008) 7688 #define CMIC_PCIE_CFG_WRITE_DATA_OFFSET (0x27004) 7689 #define CMIC_PCIE_CONFIG_OFFSET (0x10208) 7690 #define CMIC_PCIE_ERROR_STATUS_OFFSET (0x10214) 7691 #define CMIC_PCIE_ERROR_STATUS_CLR_OFFSET (0x10218) 7692 #define CMIC_PCIE_USERIF_PURGE_CONTROL_OFFSET (0x10260) 7693 #define CMIC_PCIE_USERIF_PURGE_STATUS_OFFSET (0x10264) 7694 #define CMIC_PCIE_USERIF_STATUS_OFFSET (0x10254) 7695 #define CMIC_PCIE_USERIF_STATUS_CLR_OFFSET (0x10258) 7696 #define CMIC_PCIE_USERIF_STATUS_MASK_OFFSET (0x1025c) 7697 #define CMIC_PCIE_USERIF_TIMEOUT_OFFSET (0x10250) 7698 #define CMIC_PIO_IC_AR_ARB_MI0_OFFSET (0x1c408) 7699 #define CMIC_PIO_IC_AR_ARB_MI1_OFFSET (0x1c428) 7700 #define CMIC_PIO_IC_AR_ARB_MI2_OFFSET (0x1c448) 7701 #define CMIC_PIO_IC_AR_ARB_MI3_OFFSET (0x1c468) 7702 #define CMIC_PIO_IC_AR_ARB_MI4_OFFSET (0x1c488) 7703 #define CMIC_PIO_IC_AR_ARB_MI5_OFFSET (0x1c4a8) 7704 #define CMIC_PIO_IC_AR_ARB_MI6_OFFSET (0x1c4c8) 7705 #define CMIC_PIO_IC_AR_ARB_MI7_OFFSET (0x1c4e8) 7706 #define CMIC_PIO_IC_AW_ARB_MI0_OFFSET (0x1c40c) 7707 #define CMIC_PIO_IC_AW_ARB_MI1_OFFSET (0x1c42c) 7708 #define CMIC_PIO_IC_AW_ARB_MI2_OFFSET (0x1c44c) 7709 #define CMIC_PIO_IC_AW_ARB_MI3_OFFSET (0x1c46c) 7710 #define CMIC_PIO_IC_AW_ARB_MI4_OFFSET (0x1c48c) 7711 #define CMIC_PIO_IC_AW_ARB_MI5_OFFSET (0x1c4ac) 7712 #define CMIC_PIO_IC_AW_ARB_MI6_OFFSET (0x1c4cc) 7713 #define CMIC_PIO_IC_AW_ARB_MI7_OFFSET (0x1c4ec) 7714 #define CMIC_PIO_IC_CFG_REG_0_OFFSET (0x1cfc0) 7715 #define CMIC_PIO_IC_CFG_REG_1_OFFSET (0x1cfc4) 7716 #define CMIC_PIO_IC_CFG_REG_2_OFFSET (0x1cfcc) 7717 #define CMIC_PIO_IC_ID_REG_0_OFFSET (0x1cff0) 7718 #define CMIC_PIO_IC_ID_REG_1_OFFSET (0x1cff4) 7719 #define CMIC_PIO_IC_ID_REG_2_OFFSET (0x1cff8) 7720 #define CMIC_PIO_IC_ID_REG_3_OFFSET (0x1cffc) 7721 #define CMIC_PIO_IC_PER_REG_0_OFFSET (0x1cfe0) 7722 #define CMIC_PIO_IC_PER_REG_1_OFFSET (0x1cfe4) 7723 #define CMIC_PIO_IC_PER_REG_2_OFFSET (0x1cfe8) 7724 #define CMIC_PIO_IC_PER_REG_3_OFFSET (0x1cfec) 7725 #define CMIC_PIO_MCS_ACCESS_PAGE_OFFSET (0x10204) 7726 #define CMIC_PKT_COS_0_OFFSET (0x2221c) 7727 #define CMIC_PKT_COS_1_OFFSET (0x22220) 7728 #define CMIC_PKT_COS_QUEUES_HI_OFFSET (0x222a4) 7729 #define CMIC_PKT_COS_QUEUES_LO_OFFSET (0x222a8) 7730 #define CMIC_PKT_COUNT_FROMCPU_OFFSET (0x222b8) 7731 #define CMIC_PKT_COUNT_FROMCPU_MH_OFFSET (0x222b4) 7732 #define CMIC_PKT_COUNT_INTR_OFFSET (0x222d4) 7733 #define CMIC_PKT_COUNT_PIO_OFFSET (0x222d0) 7734 #define CMIC_PKT_COUNT_PIO_REPLY_OFFSET (0x222cc) 7735 #define CMIC_PKT_COUNT_SCHAN_OFFSET (0x222ac) 7736 #define CMIC_PKT_COUNT_SCHAN_REP_OFFSET (0x222b0) 7737 #define CMIC_PKT_COUNT_TOCPUD_OFFSET (0x222c0) 7738 #define CMIC_PKT_COUNT_TOCPUDM_OFFSET (0x222bc) 7739 #define CMIC_PKT_COUNT_TOCPUE_OFFSET (0x222c8) 7740 #define CMIC_PKT_COUNT_TOCPUEM_OFFSET (0x222c4) 7741 #define CMIC_PKT_CTRL_OFFSET (0x22200) 7742 #define CMIC_PKT_ETHER_SIG_OFFSET (0x22218) 7743 #define CMIC_PKT_LMAC0_HI_OFFSET (0x22204) 7744 #define CMIC_PKT_LMAC0_LO_OFFSET (0x22208) 7745 #define CMIC_PKT_LMAC1_HI_OFFSET (0x2220c) 7746 #define CMIC_PKT_LMAC1_LO_OFFSET (0x22210) 7747 #define CMIC_PKT_PORTS_0_OFFSET (0x22224) 7748 #define CMIC_PKT_PORTS_1_OFFSET (0x22228) 7749 #define CMIC_PKT_PORTS_2_OFFSET (0x2222c) 7750 #define CMIC_PKT_PORTS_3_OFFSET (0x22250) 7751 #define CMIC_PKT_PORTS_4_OFFSET (0x22254) 7752 #define CMIC_PKT_PORTS_5_OFFSET (0x22258) 7753 #define CMIC_PKT_PORTS_6_OFFSET (0x2225c) 7754 #define CMIC_PKT_PORTS_7_OFFSET (0x22260) 7755 #define CMIC_PKT_PRI_MAP_TABLE_ENTRY_0_OFFSET (0x22100) 7756 #define CMIC_PKT_PRI_MAP_TABLE_ENTRY_1_OFFSET (0x22104) 7757 #define CMIC_PKT_PRI_MAP_TABLE_ENTRY_10_OFFSET (0x22128) 7758 #define CMIC_PKT_PRI_MAP_TABLE_ENTRY_11_OFFSET (0x2212c) 7759 #define CMIC_PKT_PRI_MAP_TABLE_ENTRY_12_OFFSET (0x22130) 7760 #define CMIC_PKT_PRI_MAP_TABLE_ENTRY_13_OFFSET (0x22134) 7761 #define CMIC_PKT_PRI_MAP_TABLE_ENTRY_14_OFFSET (0x22138) 7762 #define CMIC_PKT_PRI_MAP_TABLE_ENTRY_15_OFFSET (0x2213c) 7763 #define CMIC_PKT_PRI_MAP_TABLE_ENTRY_16_OFFSET (0x22140) 7764 #define CMIC_PKT_PRI_MAP_TABLE_ENTRY_17_OFFSET (0x22144) 7765 #define CMIC_PKT_PRI_MAP_TABLE_ENTRY_18_OFFSET (0x22148) 7766 #define CMIC_PKT_PRI_MAP_TABLE_ENTRY_19_OFFSET (0x2214c) 7767 #define CMIC_PKT_PRI_MAP_TABLE_ENTRY_2_OFFSET (0x22108) 7768 #define CMIC_PKT_PRI_MAP_TABLE_ENTRY_20_OFFSET (0x22150) 7769 #define CMIC_PKT_PRI_MAP_TABLE_ENTRY_21_OFFSET (0x22154) 7770 #define CMIC_PKT_PRI_MAP_TABLE_ENTRY_22_OFFSET (0x22158) 7771 #define CMIC_PKT_PRI_MAP_TABLE_ENTRY_23_OFFSET (0x2215c) 7772 #define CMIC_PKT_PRI_MAP_TABLE_ENTRY_24_OFFSET (0x22160) 7773 #define CMIC_PKT_PRI_MAP_TABLE_ENTRY_25_OFFSET (0x22164) 7774 #define CMIC_PKT_PRI_MAP_TABLE_ENTRY_26_OFFSET (0x22168) 7775 #define CMIC_PKT_PRI_MAP_TABLE_ENTRY_27_OFFSET (0x2216c) 7776 #define CMIC_PKT_PRI_MAP_TABLE_ENTRY_28_OFFSET (0x22170) 7777 #define CMIC_PKT_PRI_MAP_TABLE_ENTRY_29_OFFSET (0x22174) 7778 #define CMIC_PKT_PRI_MAP_TABLE_ENTRY_3_OFFSET (0x2210c) 7779 #define CMIC_PKT_PRI_MAP_TABLE_ENTRY_30_OFFSET (0x22178) 7780 #define CMIC_PKT_PRI_MAP_TABLE_ENTRY_31_OFFSET (0x2217c) 7781 #define CMIC_PKT_PRI_MAP_TABLE_ENTRY_32_OFFSET (0x22180) 7782 #define CMIC_PKT_PRI_MAP_TABLE_ENTRY_33_OFFSET (0x22184) 7783 #define CMIC_PKT_PRI_MAP_TABLE_ENTRY_34_OFFSET (0x22188) 7784 #define CMIC_PKT_PRI_MAP_TABLE_ENTRY_35_OFFSET (0x2218c) 7785 #define CMIC_PKT_PRI_MAP_TABLE_ENTRY_36_OFFSET (0x22190) 7786 #define CMIC_PKT_PRI_MAP_TABLE_ENTRY_37_OFFSET (0x22194) 7787 #define CMIC_PKT_PRI_MAP_TABLE_ENTRY_38_OFFSET (0x22198) 7788 #define CMIC_PKT_PRI_MAP_TABLE_ENTRY_39_OFFSET (0x2219c) 7789 #define CMIC_PKT_PRI_MAP_TABLE_ENTRY_4_OFFSET (0x22110) 7790 #define CMIC_PKT_PRI_MAP_TABLE_ENTRY_40_OFFSET (0x221a0) 7791 #define CMIC_PKT_PRI_MAP_TABLE_ENTRY_41_OFFSET (0x221a4) 7792 #define CMIC_PKT_PRI_MAP_TABLE_ENTRY_42_OFFSET (0x221a8) 7793 #define CMIC_PKT_PRI_MAP_TABLE_ENTRY_43_OFFSET (0x221ac) 7794 #define CMIC_PKT_PRI_MAP_TABLE_ENTRY_44_OFFSET (0x221b0) 7795 #define CMIC_PKT_PRI_MAP_TABLE_ENTRY_45_OFFSET (0x221b4) 7796 #define CMIC_PKT_PRI_MAP_TABLE_ENTRY_46_OFFSET (0x221b8) 7797 #define CMIC_PKT_PRI_MAP_TABLE_ENTRY_47_OFFSET (0x221bc) 7798 #define CMIC_PKT_PRI_MAP_TABLE_ENTRY_48_OFFSET (0x221c0) 7799 #define CMIC_PKT_PRI_MAP_TABLE_ENTRY_49_OFFSET (0x221c4) 7800 #define CMIC_PKT_PRI_MAP_TABLE_ENTRY_5_OFFSET (0x22114) 7801 #define CMIC_PKT_PRI_MAP_TABLE_ENTRY_50_OFFSET (0x221c8) 7802 #define CMIC_PKT_PRI_MAP_TABLE_ENTRY_51_OFFSET (0x221cc) 7803 #define CMIC_PKT_PRI_MAP_TABLE_ENTRY_52_OFFSET (0x221d0) 7804 #define CMIC_PKT_PRI_MAP_TABLE_ENTRY_53_OFFSET (0x221d4) 7805 #define CMIC_PKT_PRI_MAP_TABLE_ENTRY_54_OFFSET (0x221d8) 7806 #define CMIC_PKT_PRI_MAP_TABLE_ENTRY_55_OFFSET (0x221dc) 7807 #define CMIC_PKT_PRI_MAP_TABLE_ENTRY_56_OFFSET (0x221e0) 7808 #define CMIC_PKT_PRI_MAP_TABLE_ENTRY_57_OFFSET (0x221e4) 7809 #define CMIC_PKT_PRI_MAP_TABLE_ENTRY_58_OFFSET (0x221e8) 7810 #define CMIC_PKT_PRI_MAP_TABLE_ENTRY_59_OFFSET (0x221ec) 7811 #define CMIC_PKT_PRI_MAP_TABLE_ENTRY_6_OFFSET (0x22118) 7812 #define CMIC_PKT_PRI_MAP_TABLE_ENTRY_60_OFFSET (0x221f0) 7813 #define CMIC_PKT_PRI_MAP_TABLE_ENTRY_61_OFFSET (0x221f4) 7814 #define CMIC_PKT_PRI_MAP_TABLE_ENTRY_62_OFFSET (0x221f8) 7815 #define CMIC_PKT_PRI_MAP_TABLE_ENTRY_63_OFFSET (0x221fc) 7816 #define CMIC_PKT_PRI_MAP_TABLE_ENTRY_7_OFFSET (0x2211c) 7817 #define CMIC_PKT_PRI_MAP_TABLE_ENTRY_8_OFFSET (0x22120) 7818 #define CMIC_PKT_PRI_MAP_TABLE_ENTRY_9_OFFSET (0x22124) 7819 #define CMIC_PKT_REASON_0_TYPE_OFFSET (0x22370) 7820 #define CMIC_PKT_REASON_0_TYPE0_OFFSET (0x22370) 7821 #define CMIC_PKT_REASON_0_TYPE1_OFFSET (0x22374) 7822 #define CMIC_PKT_REASON_0_TYPE10_OFFSET (0x22398) 7823 #define CMIC_PKT_REASON_0_TYPE11_OFFSET (0x2239c) 7824 #define CMIC_PKT_REASON_0_TYPE12_OFFSET (0x223a0) 7825 #define CMIC_PKT_REASON_0_TYPE13_OFFSET (0x223a4) 7826 #define CMIC_PKT_REASON_0_TYPE14_OFFSET (0x223a8) 7827 #define CMIC_PKT_REASON_0_TYPE15_OFFSET (0x223ac) 7828 #define CMIC_PKT_REASON_0_TYPE2_OFFSET (0x22378) 7829 #define CMIC_PKT_REASON_0_TYPE3_OFFSET (0x2237c) 7830 #define CMIC_PKT_REASON_0_TYPE4_OFFSET (0x22380) 7831 #define CMIC_PKT_REASON_0_TYPE5_OFFSET (0x22384) 7832 #define CMIC_PKT_REASON_0_TYPE6_OFFSET (0x22388) 7833 #define CMIC_PKT_REASON_0_TYPE7_OFFSET (0x2238c) 7834 #define CMIC_PKT_REASON_0_TYPE8_OFFSET (0x22390) 7835 #define CMIC_PKT_REASON_0_TYPE9_OFFSET (0x22394) 7836 #define CMIC_PKT_REASON_1_TYPE_OFFSET (0x223b0) 7837 #define CMIC_PKT_REASON_1_TYPE0_OFFSET (0x223b0) 7838 #define CMIC_PKT_REASON_1_TYPE1_OFFSET (0x223b4) 7839 #define CMIC_PKT_REASON_1_TYPE10_OFFSET (0x223d8) 7840 #define CMIC_PKT_REASON_1_TYPE11_OFFSET (0x223dc) 7841 #define CMIC_PKT_REASON_1_TYPE12_OFFSET (0x223e0) 7842 #define CMIC_PKT_REASON_1_TYPE13_OFFSET (0x223e4) 7843 #define CMIC_PKT_REASON_1_TYPE14_OFFSET (0x223e8) 7844 #define CMIC_PKT_REASON_1_TYPE15_OFFSET (0x223ec) 7845 #define CMIC_PKT_REASON_1_TYPE2_OFFSET (0x223b8) 7846 #define CMIC_PKT_REASON_1_TYPE3_OFFSET (0x223bc) 7847 #define CMIC_PKT_REASON_1_TYPE4_OFFSET (0x223c0) 7848 #define CMIC_PKT_REASON_1_TYPE5_OFFSET (0x223c4) 7849 #define CMIC_PKT_REASON_1_TYPE6_OFFSET (0x223c8) 7850 #define CMIC_PKT_REASON_1_TYPE7_OFFSET (0x223cc) 7851 #define CMIC_PKT_REASON_1_TYPE8_OFFSET (0x223d0) 7852 #define CMIC_PKT_REASON_1_TYPE9_OFFSET (0x223d4) 7853 #define CMIC_PKT_REASON_2_TYPE_OFFSET (0x224f0) 7854 #define CMIC_PKT_REASON_2_TYPE0_OFFSET (0x224f0) 7855 #define CMIC_PKT_REASON_2_TYPE1_OFFSET (0x224f4) 7856 #define CMIC_PKT_REASON_2_TYPE10_OFFSET (0x22518) 7857 #define CMIC_PKT_REASON_2_TYPE11_OFFSET (0x2251c) 7858 #define CMIC_PKT_REASON_2_TYPE12_OFFSET (0x22520) 7859 #define CMIC_PKT_REASON_2_TYPE13_OFFSET (0x22524) 7860 #define CMIC_PKT_REASON_2_TYPE14_OFFSET (0x22528) 7861 #define CMIC_PKT_REASON_2_TYPE15_OFFSET (0x2252c) 7862 #define CMIC_PKT_REASON_2_TYPE2_OFFSET (0x224f8) 7863 #define CMIC_PKT_REASON_2_TYPE3_OFFSET (0x224fc) 7864 #define CMIC_PKT_REASON_2_TYPE4_OFFSET (0x22500) 7865 #define CMIC_PKT_REASON_2_TYPE5_OFFSET (0x22504) 7866 #define CMIC_PKT_REASON_2_TYPE6_OFFSET (0x22508) 7867 #define CMIC_PKT_REASON_2_TYPE7_OFFSET (0x2250c) 7868 #define CMIC_PKT_REASON_2_TYPE8_OFFSET (0x22510) 7869 #define CMIC_PKT_REASON_2_TYPE9_OFFSET (0x22514) 7870 #define CMIC_PKT_REASON_DIRECT_0_TYPE_OFFSET (0x223f0) 7871 #define CMIC_PKT_REASON_DIRECT_0_TYPE0_OFFSET (0x223f0) 7872 #define CMIC_PKT_REASON_DIRECT_0_TYPE1_OFFSET (0x223f4) 7873 #define CMIC_PKT_REASON_DIRECT_0_TYPE10_OFFSET (0x22418) 7874 #define CMIC_PKT_REASON_DIRECT_0_TYPE11_OFFSET (0x2241c) 7875 #define CMIC_PKT_REASON_DIRECT_0_TYPE12_OFFSET (0x22420) 7876 #define CMIC_PKT_REASON_DIRECT_0_TYPE13_OFFSET (0x22424) 7877 #define CMIC_PKT_REASON_DIRECT_0_TYPE14_OFFSET (0x22428) 7878 #define CMIC_PKT_REASON_DIRECT_0_TYPE15_OFFSET (0x2242c) 7879 #define CMIC_PKT_REASON_DIRECT_0_TYPE2_OFFSET (0x223f8) 7880 #define CMIC_PKT_REASON_DIRECT_0_TYPE3_OFFSET (0x223fc) 7881 #define CMIC_PKT_REASON_DIRECT_0_TYPE4_OFFSET (0x22400) 7882 #define CMIC_PKT_REASON_DIRECT_0_TYPE5_OFFSET (0x22404) 7883 #define CMIC_PKT_REASON_DIRECT_0_TYPE6_OFFSET (0x22408) 7884 #define CMIC_PKT_REASON_DIRECT_0_TYPE7_OFFSET (0x2240c) 7885 #define CMIC_PKT_REASON_DIRECT_0_TYPE8_OFFSET (0x22410) 7886 #define CMIC_PKT_REASON_DIRECT_0_TYPE9_OFFSET (0x22414) 7887 #define CMIC_PKT_REASON_DIRECT_1_TYPE_OFFSET (0x22430) 7888 #define CMIC_PKT_REASON_DIRECT_1_TYPE0_OFFSET (0x22430) 7889 #define CMIC_PKT_REASON_DIRECT_1_TYPE1_OFFSET (0x22434) 7890 #define CMIC_PKT_REASON_DIRECT_1_TYPE10_OFFSET (0x22458) 7891 #define CMIC_PKT_REASON_DIRECT_1_TYPE11_OFFSET (0x2245c) 7892 #define CMIC_PKT_REASON_DIRECT_1_TYPE12_OFFSET (0x22460) 7893 #define CMIC_PKT_REASON_DIRECT_1_TYPE13_OFFSET (0x22464) 7894 #define CMIC_PKT_REASON_DIRECT_1_TYPE14_OFFSET (0x22468) 7895 #define CMIC_PKT_REASON_DIRECT_1_TYPE15_OFFSET (0x2246c) 7896 #define CMIC_PKT_REASON_DIRECT_1_TYPE2_OFFSET (0x22438) 7897 #define CMIC_PKT_REASON_DIRECT_1_TYPE3_OFFSET (0x2243c) 7898 #define CMIC_PKT_REASON_DIRECT_1_TYPE4_OFFSET (0x22440) 7899 #define CMIC_PKT_REASON_DIRECT_1_TYPE5_OFFSET (0x22444) 7900 #define CMIC_PKT_REASON_DIRECT_1_TYPE6_OFFSET (0x22448) 7901 #define CMIC_PKT_REASON_DIRECT_1_TYPE7_OFFSET (0x2244c) 7902 #define CMIC_PKT_REASON_DIRECT_1_TYPE8_OFFSET (0x22450) 7903 #define CMIC_PKT_REASON_DIRECT_1_TYPE9_OFFSET (0x22454) 7904 #define CMIC_PKT_REASON_DIRECT_2_TYPE_OFFSET (0x22530) 7905 #define CMIC_PKT_REASON_DIRECT_2_TYPE0_OFFSET (0x22530) 7906 #define CMIC_PKT_REASON_DIRECT_2_TYPE1_OFFSET (0x22534) 7907 #define CMIC_PKT_REASON_DIRECT_2_TYPE10_OFFSET (0x22558) 7908 #define CMIC_PKT_REASON_DIRECT_2_TYPE11_OFFSET (0x2255c) 7909 #define CMIC_PKT_REASON_DIRECT_2_TYPE12_OFFSET (0x22560) 7910 #define CMIC_PKT_REASON_DIRECT_2_TYPE13_OFFSET (0x22564) 7911 #define CMIC_PKT_REASON_DIRECT_2_TYPE14_OFFSET (0x22568) 7912 #define CMIC_PKT_REASON_DIRECT_2_TYPE15_OFFSET (0x2256c) 7913 #define CMIC_PKT_REASON_DIRECT_2_TYPE2_OFFSET (0x22538) 7914 #define CMIC_PKT_REASON_DIRECT_2_TYPE3_OFFSET (0x2253c) 7915 #define CMIC_PKT_REASON_DIRECT_2_TYPE4_OFFSET (0x22540) 7916 #define CMIC_PKT_REASON_DIRECT_2_TYPE5_OFFSET (0x22544) 7917 #define CMIC_PKT_REASON_DIRECT_2_TYPE6_OFFSET (0x22548) 7918 #define CMIC_PKT_REASON_DIRECT_2_TYPE7_OFFSET (0x2254c) 7919 #define CMIC_PKT_REASON_DIRECT_2_TYPE8_OFFSET (0x22550) 7920 #define CMIC_PKT_REASON_DIRECT_2_TYPE9_OFFSET (0x22554) 7921 #define CMIC_PKT_REASON_MINI_0_TYPE_OFFSET (0x22470) 7922 #define CMIC_PKT_REASON_MINI_0_TYPE0_OFFSET (0x22470) 7923 #define CMIC_PKT_REASON_MINI_0_TYPE1_OFFSET (0x22474) 7924 #define CMIC_PKT_REASON_MINI_0_TYPE10_OFFSET (0x22498) 7925 #define CMIC_PKT_REASON_MINI_0_TYPE11_OFFSET (0x2249c) 7926 #define CMIC_PKT_REASON_MINI_0_TYPE12_OFFSET (0x224a0) 7927 #define CMIC_PKT_REASON_MINI_0_TYPE13_OFFSET (0x224a4) 7928 #define CMIC_PKT_REASON_MINI_0_TYPE14_OFFSET (0x224a8) 7929 #define CMIC_PKT_REASON_MINI_0_TYPE15_OFFSET (0x224ac) 7930 #define CMIC_PKT_REASON_MINI_0_TYPE2_OFFSET (0x22478) 7931 #define CMIC_PKT_REASON_MINI_0_TYPE3_OFFSET (0x2247c) 7932 #define CMIC_PKT_REASON_MINI_0_TYPE4_OFFSET (0x22480) 7933 #define CMIC_PKT_REASON_MINI_0_TYPE5_OFFSET (0x22484) 7934 #define CMIC_PKT_REASON_MINI_0_TYPE6_OFFSET (0x22488) 7935 #define CMIC_PKT_REASON_MINI_0_TYPE7_OFFSET (0x2248c) 7936 #define CMIC_PKT_REASON_MINI_0_TYPE8_OFFSET (0x22490) 7937 #define CMIC_PKT_REASON_MINI_0_TYPE9_OFFSET (0x22494) 7938 #define CMIC_PKT_REASON_MINI_1_TYPE_OFFSET (0x224b0) 7939 #define CMIC_PKT_REASON_MINI_1_TYPE0_OFFSET (0x224b0) 7940 #define CMIC_PKT_REASON_MINI_1_TYPE1_OFFSET (0x224b4) 7941 #define CMIC_PKT_REASON_MINI_1_TYPE10_OFFSET (0x224d8) 7942 #define CMIC_PKT_REASON_MINI_1_TYPE11_OFFSET (0x224dc) 7943 #define CMIC_PKT_REASON_MINI_1_TYPE12_OFFSET (0x224e0) 7944 #define CMIC_PKT_REASON_MINI_1_TYPE13_OFFSET (0x224e4) 7945 #define CMIC_PKT_REASON_MINI_1_TYPE14_OFFSET (0x224e8) 7946 #define CMIC_PKT_REASON_MINI_1_TYPE15_OFFSET (0x224ec) 7947 #define CMIC_PKT_REASON_MINI_1_TYPE2_OFFSET (0x224b8) 7948 #define CMIC_PKT_REASON_MINI_1_TYPE3_OFFSET (0x224bc) 7949 #define CMIC_PKT_REASON_MINI_1_TYPE4_OFFSET (0x224c0) 7950 #define CMIC_PKT_REASON_MINI_1_TYPE5_OFFSET (0x224c4) 7951 #define CMIC_PKT_REASON_MINI_1_TYPE6_OFFSET (0x224c8) 7952 #define CMIC_PKT_REASON_MINI_1_TYPE7_OFFSET (0x224cc) 7953 #define CMIC_PKT_REASON_MINI_1_TYPE8_OFFSET (0x224d0) 7954 #define CMIC_PKT_REASON_MINI_1_TYPE9_OFFSET (0x224d4) 7955 #define CMIC_PKT_REASON_MINI_2_TYPE_OFFSET (0x22570) 7956 #define CMIC_PKT_REASON_MINI_2_TYPE0_OFFSET (0x22570) 7957 #define CMIC_PKT_REASON_MINI_2_TYPE1_OFFSET (0x22574) 7958 #define CMIC_PKT_REASON_MINI_2_TYPE10_OFFSET (0x22598) 7959 #define CMIC_PKT_REASON_MINI_2_TYPE11_OFFSET (0x2259c) 7960 #define CMIC_PKT_REASON_MINI_2_TYPE12_OFFSET (0x225a0) 7961 #define CMIC_PKT_REASON_MINI_2_TYPE13_OFFSET (0x225a4) 7962 #define CMIC_PKT_REASON_MINI_2_TYPE14_OFFSET (0x225a8) 7963 #define CMIC_PKT_REASON_MINI_2_TYPE15_OFFSET (0x225ac) 7964 #define CMIC_PKT_REASON_MINI_2_TYPE2_OFFSET (0x22578) 7965 #define CMIC_PKT_REASON_MINI_2_TYPE3_OFFSET (0x2257c) 7966 #define CMIC_PKT_REASON_MINI_2_TYPE4_OFFSET (0x22580) 7967 #define CMIC_PKT_REASON_MINI_2_TYPE5_OFFSET (0x22584) 7968 #define CMIC_PKT_REASON_MINI_2_TYPE6_OFFSET (0x22588) 7969 #define CMIC_PKT_REASON_MINI_2_TYPE7_OFFSET (0x2258c) 7970 #define CMIC_PKT_REASON_MINI_2_TYPE8_OFFSET (0x22590) 7971 #define CMIC_PKT_REASON_MINI_2_TYPE9_OFFSET (0x22594) 7972 #define CMIC_PKT_RMAC_OFFSET (0x22230) 7973 #define CMIC_PKT_RMAC_HI_OFFSET (0x22234) 7974 #define CMIC_PKT_RMH0_OFFSET (0x22238) 7975 #define CMIC_PKT_RMH1_OFFSET (0x2223c) 7976 #define CMIC_PKT_RMH2_OFFSET (0x22240) 7977 #define CMIC_PKT_RMH3_OFFSET (0x22364) 7978 #define CMIC_PKT_VLAN_OFFSET (0x22214) 7979 #define CMIC_RATE_ADJUST_OFFSET (0x11000) 7980 #define CMIC_RATE_ADJUST_EXT_MDIO_OFFSET (0x11000) 7981 #define CMIC_RATE_ADJUST_INT_MDIO_OFFSET (0x11004) 7982 #define CMIC_RPE0_MAX_CELL_LIMIT_OFFSET (0x22604) 7983 #define CMIC_RPE1_MAX_CELL_LIMIT_OFFSET (0x22600) 7984 #define CMIC_RPE_DEBUG_OFFSET (0x22610) 7985 #define CMIC_RPE_IRQ_STAT0_OFFSET (0x22330) 7986 #define CMIC_RPE_IRQ_STAT1_OFFSET (0x22334) 7987 #define CMIC_RPE_IRQ_STAT2_OFFSET (0x22338) 7988 #define CMIC_RPE_IRQ_STAT3_OFFSET (0x2233c) 7989 #define CMIC_RPE_IRQ_STAT4_OFFSET (0x22340) 7990 #define CMIC_RPE_IRQ_STAT5_OFFSET (0x226b0) 7991 #define CMIC_RPE_IRQ_STAT6_OFFSET (0x226b4) 7992 #define CMIC_RPE_MAX_CELL_LIMIT_OFFSET (0x22368) 7993 #define CMIC_RPE_MIIM_ADDRESS_OFFSET (0x22088) 7994 #define CMIC_RPE_MIIM_CTRL_OFFSET (0x2208c) 7995 #define CMIC_RPE_MIIM_PARAM_OFFSET (0x22080) 7996 #define CMIC_RPE_MIIM_READ_DATA_OFFSET (0x22084) 7997 #define CMIC_RPE_MIIM_STAT_OFFSET (0x22090) 7998 #define CMIC_RPE_PCIE_IRQ_MASK0_OFFSET (0x22358) 7999 #define CMIC_RPE_RCPU_IRQ_MASK0_OFFSET (0x22344) 8000 #define CMIC_RPE_RCPU_IRQ_MASK1_OFFSET (0x22348) 8001 #define CMIC_RPE_RCPU_IRQ_MASK2_OFFSET (0x2234c) 8002 #define CMIC_RPE_RCPU_IRQ_MASK3_OFFSET (0x22350) 8003 #define CMIC_RPE_RCPU_IRQ_MASK4_OFFSET (0x22354) 8004 #define CMIC_RPE_RCPU_IRQ_MASK5_OFFSET (0x226b8) 8005 #define CMIC_RPE_RCPU_IRQ_MASK6_OFFSET (0x226bc) 8006 #define CMIC_RPE_STAT_OFFSET (0x22248) 8007 #define CMIC_RPE_STAT_CLR_OFFSET (0x2224c) 8008 #define CMIC_RPE_SW_INTR_CONFIG_OFFSET (0x2236c) 8009 #define CMIC_RPE_UC0_IRQ_MASK0_OFFSET (0x2235c) 8010 #define CMIC_RPE_UC1_IRQ_MASK0_OFFSET (0x22360) 8011 #define CMIC_RXBUF_BLOCK_DATABUF_ALLOC_OFFSET (0x1a01c) 8012 #define CMIC_RXBUF_BLOCK_STATUSBUF_ALLOC_OFFSET (0x1a018) 8013 #define CMIC_RXBUF_CONFIG_OFFSET (0x1a024) 8014 #define CMIC_RXBUF_DATABUF_MAX_FLIST_ENTRIES_OFFSET (0x1a00c) 8015 #define CMIC_RXBUF_DATABUF_NUM_FREE_ENTRIES_OFFSET (0x1a014) 8016 #define CMIC_RXBUF_DATABUF_TM_0_OFFSET (0x1a02c) 8017 #define CMIC_RXBUF_DATABUF_TM_1_OFFSET (0x1a030) 8018 #define CMIC_RXBUF_DATABUF_TM_2_OFFSET (0x1a034) 8019 #define CMIC_RXBUF_ECCERR_CONTROL_OFFSET (0x1a028) 8020 #define CMIC_RXBUF_EPINTF_BUF_DEPTH_OFFSET (0x1a020) 8021 #define CMIC_RXBUF_EPINTF_MAX_INTERFACE_CREDITS_OFFSET (0x1a004) 8022 #define CMIC_RXBUF_EPINTF_RELEASE_ALL_CREDITS_OFFSET (0x1a000) 8023 #define CMIC_RXBUF_MEM_CONTROL_0_OFFSET (0x1a02c) 8024 #define CMIC_RXBUF_STATBUF_TM_0_OFFSET (0x1a038) 8025 #define CMIC_RXBUF_STATBUF_TM_1_OFFSET (0x1a03c) 8026 #define CMIC_RXBUF_STATUSBUF_MAX_FLIST_ENTRIES_OFFSET (0x1a008) 8027 #define CMIC_RXBUF_STATUSBUF_NUM_FREE_ENTRIES_OFFSET (0x1a010) 8028 #define CMIC_SBUS_RING_MAP_0_7_OFFSET (0x10098) 8029 #define CMIC_SBUS_RING_MAP_104_111_OFFSET (0x100cc) 8030 #define CMIC_SBUS_RING_MAP_112_119_OFFSET (0x100d0) 8031 #define CMIC_SBUS_RING_MAP_120_127_OFFSET (0x100d4) 8032 #define CMIC_SBUS_RING_MAP_16_23_OFFSET (0x100a0) 8033 #define CMIC_SBUS_RING_MAP_24_31_OFFSET (0x100a4) 8034 #define CMIC_SBUS_RING_MAP_32_39_OFFSET (0x100a8) 8035 #define CMIC_SBUS_RING_MAP_40_47_OFFSET (0x100ac) 8036 #define CMIC_SBUS_RING_MAP_48_55_OFFSET (0x100b0) 8037 #define CMIC_SBUS_RING_MAP_56_63_OFFSET (0x100b4) 8038 #define CMIC_SBUS_RING_MAP_64_71_OFFSET (0x100b8) 8039 #define CMIC_SBUS_RING_MAP_72_79_OFFSET (0x100bc) 8040 #define CMIC_SBUS_RING_MAP_80_87_OFFSET (0x100c0) 8041 #define CMIC_SBUS_RING_MAP_88_95_OFFSET (0x100c4) 8042 #define CMIC_SBUS_RING_MAP_8_15_OFFSET (0x1009c) 8043 #define CMIC_SBUS_RING_MAP_96_103_OFFSET (0x100c8) 8044 #define CMIC_SBUS_TIMEOUT_OFFSET (0x10094) 8045 #define CMIC_SCHAN_RCPU_RPIO_MESSAGE_OFFSET (0x222d8) 8046 #define CMIC_SCHAN_RCPU_RPIO_MESSAGE0_OFFSET (0x222d8) 8047 #define CMIC_SCHAN_RCPU_RPIO_MESSAGE1_OFFSET (0x222dc) 8048 #define CMIC_SCHAN_RCPU_RPIO_MESSAGE10_OFFSET (0x22300) 8049 #define CMIC_SCHAN_RCPU_RPIO_MESSAGE11_OFFSET (0x22304) 8050 #define CMIC_SCHAN_RCPU_RPIO_MESSAGE12_OFFSET (0x22308) 8051 #define CMIC_SCHAN_RCPU_RPIO_MESSAGE13_OFFSET (0x2230c) 8052 #define CMIC_SCHAN_RCPU_RPIO_MESSAGE14_OFFSET (0x22310) 8053 #define CMIC_SCHAN_RCPU_RPIO_MESSAGE15_OFFSET (0x22314) 8054 #define CMIC_SCHAN_RCPU_RPIO_MESSAGE16_OFFSET (0x22318) 8055 #define CMIC_SCHAN_RCPU_RPIO_MESSAGE17_OFFSET (0x2231c) 8056 #define CMIC_SCHAN_RCPU_RPIO_MESSAGE18_OFFSET (0x22320) 8057 #define CMIC_SCHAN_RCPU_RPIO_MESSAGE19_OFFSET (0x22324) 8058 #define CMIC_SCHAN_RCPU_RPIO_MESSAGE2_OFFSET (0x222e0) 8059 #define CMIC_SCHAN_RCPU_RPIO_MESSAGE20_OFFSET (0x22328) 8060 #define CMIC_SCHAN_RCPU_RPIO_MESSAGE21_OFFSET (0x2232c) 8061 #define CMIC_SCHAN_RCPU_RPIO_MESSAGE3_OFFSET (0x222e4) 8062 #define CMIC_SCHAN_RCPU_RPIO_MESSAGE4_OFFSET (0x222e8) 8063 #define CMIC_SCHAN_RCPU_RPIO_MESSAGE5_OFFSET (0x222ec) 8064 #define CMIC_SCHAN_RCPU_RPIO_MESSAGE6_OFFSET (0x222f0) 8065 #define CMIC_SCHAN_RCPU_RPIO_MESSAGE7_OFFSET (0x222f4) 8066 #define CMIC_SCHAN_RCPU_RPIO_MESSAGE8_OFFSET (0x222f8) 8067 #define CMIC_SCHAN_RCPU_RPIO_MESSAGE9_OFFSET (0x222fc) 8068 #define CMIC_SEMAPHORE_1_OFFSET (0x10300) 8069 #define CMIC_SEMAPHORE_10_OFFSET (0x10348) 8070 #define CMIC_SEMAPHORE_10_SHADOW_OFFSET (0x1034c) 8071 #define CMIC_SEMAPHORE_11_OFFSET (0x10350) 8072 #define CMIC_SEMAPHORE_11_SHADOW_OFFSET (0x10354) 8073 #define CMIC_SEMAPHORE_12_OFFSET (0x10358) 8074 #define CMIC_SEMAPHORE_12_SHADOW_OFFSET (0x1035c) 8075 #define CMIC_SEMAPHORE_13_OFFSET (0x10360) 8076 #define CMIC_SEMAPHORE_13_SHADOW_OFFSET (0x10364) 8077 #define CMIC_SEMAPHORE_14_OFFSET (0x10368) 8078 #define CMIC_SEMAPHORE_14_SHADOW_OFFSET (0x1036c) 8079 #define CMIC_SEMAPHORE_15_OFFSET (0x10370) 8080 #define CMIC_SEMAPHORE_15_SHADOW_OFFSET (0x10374) 8081 #define CMIC_SEMAPHORE_16_OFFSET (0x10378) 8082 #define CMIC_SEMAPHORE_16_SHADOW_OFFSET (0x1037c) 8083 #define CMIC_SEMAPHORE_17_OFFSET (0x10380) 8084 #define CMIC_SEMAPHORE_17_SHADOW_OFFSET (0x10384) 8085 #define CMIC_SEMAPHORE_18_OFFSET (0x10388) 8086 #define CMIC_SEMAPHORE_18_SHADOW_OFFSET (0x1038c) 8087 #define CMIC_SEMAPHORE_19_OFFSET (0x10390) 8088 #define CMIC_SEMAPHORE_19_SHADOW_OFFSET (0x10394) 8089 #define CMIC_SEMAPHORE_1_SHADOW_OFFSET (0x10304) 8090 #define CMIC_SEMAPHORE_2_OFFSET (0x10308) 8091 #define CMIC_SEMAPHORE_20_OFFSET (0x10398) 8092 #define CMIC_SEMAPHORE_20_SHADOW_OFFSET (0x1039c) 8093 #define CMIC_SEMAPHORE_21_OFFSET (0x103a0) 8094 #define CMIC_SEMAPHORE_21_SHADOW_OFFSET (0x103a4) 8095 #define CMIC_SEMAPHORE_22_OFFSET (0x103a8) 8096 #define CMIC_SEMAPHORE_22_SHADOW_OFFSET (0x103ac) 8097 #define CMIC_SEMAPHORE_23_OFFSET (0x103b0) 8098 #define CMIC_SEMAPHORE_23_SHADOW_OFFSET (0x103b4) 8099 #define CMIC_SEMAPHORE_24_OFFSET (0x103b8) 8100 #define CMIC_SEMAPHORE_24_SHADOW_OFFSET (0x103bc) 8101 #define CMIC_SEMAPHORE_25_OFFSET (0x103c0) 8102 #define CMIC_SEMAPHORE_25_SHADOW_OFFSET (0x103c4) 8103 #define CMIC_SEMAPHORE_26_OFFSET (0x103c8) 8104 #define CMIC_SEMAPHORE_26_SHADOW_OFFSET (0x103cc) 8105 #define CMIC_SEMAPHORE_27_OFFSET (0x103d0) 8106 #define CMIC_SEMAPHORE_27_SHADOW_OFFSET (0x103d4) 8107 #define CMIC_SEMAPHORE_28_OFFSET (0x103d8) 8108 #define CMIC_SEMAPHORE_28_SHADOW_OFFSET (0x103dc) 8109 #define CMIC_SEMAPHORE_29_OFFSET (0x103e0) 8110 #define CMIC_SEMAPHORE_29_SHADOW_OFFSET (0x103e4) 8111 #define CMIC_SEMAPHORE_2_SHADOW_OFFSET (0x1030c) 8112 #define CMIC_SEMAPHORE_3_OFFSET (0x10310) 8113 #define CMIC_SEMAPHORE_30_OFFSET (0x103e8) 8114 #define CMIC_SEMAPHORE_30_SHADOW_OFFSET (0x103ec) 8115 #define CMIC_SEMAPHORE_31_OFFSET (0x103f0) 8116 #define CMIC_SEMAPHORE_31_SHADOW_OFFSET (0x103f4) 8117 #define CMIC_SEMAPHORE_32_OFFSET (0x103f8) 8118 #define CMIC_SEMAPHORE_32_SHADOW_OFFSET (0x103fc) 8119 #define CMIC_SEMAPHORE_3_SHADOW_OFFSET (0x10314) 8120 #define CMIC_SEMAPHORE_4_OFFSET (0x10318) 8121 #define CMIC_SEMAPHORE_4_SHADOW_OFFSET (0x1031c) 8122 #define CMIC_SEMAPHORE_5_OFFSET (0x10320) 8123 #define CMIC_SEMAPHORE_5_SHADOW_OFFSET (0x10324) 8124 #define CMIC_SEMAPHORE_6_OFFSET (0x10328) 8125 #define CMIC_SEMAPHORE_6_SHADOW_OFFSET (0x1032c) 8126 #define CMIC_SEMAPHORE_7_OFFSET (0x10330) 8127 #define CMIC_SEMAPHORE_7_SHADOW_OFFSET (0x10334) 8128 #define CMIC_SEMAPHORE_8_OFFSET (0x10338) 8129 #define CMIC_SEMAPHORE_8_SHADOW_OFFSET (0x1033c) 8130 #define CMIC_SEMAPHORE_9_OFFSET (0x10340) 8131 #define CMIC_SEMAPHORE_9_SHADOW_OFFSET (0x10344) 8132 #define CMIC_SER0_END_ADDR_0_OFFSET (0x12004) 8133 #define CMIC_SER0_END_ADDR_1_OFFSET (0x12014) 8134 #define CMIC_SER0_END_ADDR_10_OFFSET (0x120a4) 8135 #define CMIC_SER0_END_ADDR_11_OFFSET (0x120b4) 8136 #define CMIC_SER0_END_ADDR_12_OFFSET (0x120c4) 8137 #define CMIC_SER0_END_ADDR_13_OFFSET (0x120d4) 8138 #define CMIC_SER0_END_ADDR_14_OFFSET (0x120e4) 8139 #define CMIC_SER0_END_ADDR_15_OFFSET (0x120f4) 8140 #define CMIC_SER0_END_ADDR_16_OFFSET (0x12104) 8141 #define CMIC_SER0_END_ADDR_17_OFFSET (0x12114) 8142 #define CMIC_SER0_END_ADDR_18_OFFSET (0x12124) 8143 #define CMIC_SER0_END_ADDR_19_OFFSET (0x12134) 8144 #define CMIC_SER0_END_ADDR_2_OFFSET (0x12024) 8145 #define CMIC_SER0_END_ADDR_20_OFFSET (0x12144) 8146 #define CMIC_SER0_END_ADDR_21_OFFSET (0x12154) 8147 #define CMIC_SER0_END_ADDR_22_OFFSET (0x12164) 8148 #define CMIC_SER0_END_ADDR_23_OFFSET (0x12174) 8149 #define CMIC_SER0_END_ADDR_24_OFFSET (0x12184) 8150 #define CMIC_SER0_END_ADDR_25_OFFSET (0x12194) 8151 #define CMIC_SER0_END_ADDR_26_OFFSET (0x121a4) 8152 #define CMIC_SER0_END_ADDR_27_OFFSET (0x121b4) 8153 #define CMIC_SER0_END_ADDR_28_OFFSET (0x121c4) 8154 #define CMIC_SER0_END_ADDR_29_OFFSET (0x121d4) 8155 #define CMIC_SER0_END_ADDR_3_OFFSET (0x12034) 8156 #define CMIC_SER0_END_ADDR_30_OFFSET (0x121e4) 8157 #define CMIC_SER0_END_ADDR_31_OFFSET (0x121f4) 8158 #define CMIC_SER0_END_ADDR_4_OFFSET (0x12044) 8159 #define CMIC_SER0_END_ADDR_5_OFFSET (0x12054) 8160 #define CMIC_SER0_END_ADDR_6_OFFSET (0x12064) 8161 #define CMIC_SER0_END_ADDR_7_OFFSET (0x12074) 8162 #define CMIC_SER0_END_ADDR_8_OFFSET (0x12084) 8163 #define CMIC_SER0_END_ADDR_9_OFFSET (0x12094) 8164 #define CMIC_SER0_FAIL_CNT_OFFSET (0x12200) 8165 #define CMIC_SER0_FAIL_ENTRY_OFFSET (0x12204) 8166 #define CMIC_SER0_INTERLEAVE_PARITY_OFFSET (0x12214) 8167 #define CMIC_SER0_MEM_ADDR_OFFSET (0x1220c) 8168 #define CMIC_SER0_MEM_ADDR_0_OFFSET (0x12008) 8169 #define CMIC_SER0_MEM_ADDR_1_OFFSET (0x12018) 8170 #define CMIC_SER0_MEM_ADDR_10_OFFSET (0x120a8) 8171 #define CMIC_SER0_MEM_ADDR_11_OFFSET (0x120b8) 8172 #define CMIC_SER0_MEM_ADDR_12_OFFSET (0x120c8) 8173 #define CMIC_SER0_MEM_ADDR_13_OFFSET (0x120d8) 8174 #define CMIC_SER0_MEM_ADDR_14_OFFSET (0x120e8) 8175 #define CMIC_SER0_MEM_ADDR_15_OFFSET (0x120f8) 8176 #define CMIC_SER0_MEM_ADDR_16_OFFSET (0x12108) 8177 #define CMIC_SER0_MEM_ADDR_17_OFFSET (0x12118) 8178 #define CMIC_SER0_MEM_ADDR_18_OFFSET (0x12128) 8179 #define CMIC_SER0_MEM_ADDR_19_OFFSET (0x12138) 8180 #define CMIC_SER0_MEM_ADDR_2_OFFSET (0x12028) 8181 #define CMIC_SER0_MEM_ADDR_20_OFFSET (0x12148) 8182 #define CMIC_SER0_MEM_ADDR_21_OFFSET (0x12158) 8183 #define CMIC_SER0_MEM_ADDR_22_OFFSET (0x12168) 8184 #define CMIC_SER0_MEM_ADDR_23_OFFSET (0x12178) 8185 #define CMIC_SER0_MEM_ADDR_24_OFFSET (0x12188) 8186 #define CMIC_SER0_MEM_ADDR_25_OFFSET (0x12198) 8187 #define CMIC_SER0_MEM_ADDR_26_OFFSET (0x121a8) 8188 #define CMIC_SER0_MEM_ADDR_27_OFFSET (0x121b8) 8189 #define CMIC_SER0_MEM_ADDR_28_OFFSET (0x121c8) 8190 #define CMIC_SER0_MEM_ADDR_29_OFFSET (0x121d8) 8191 #define CMIC_SER0_MEM_ADDR_3_OFFSET (0x12038) 8192 #define CMIC_SER0_MEM_ADDR_30_OFFSET (0x121e8) 8193 #define CMIC_SER0_MEM_ADDR_31_OFFSET (0x121f8) 8194 #define CMIC_SER0_MEM_ADDR_4_OFFSET (0x12048) 8195 #define CMIC_SER0_MEM_ADDR_5_OFFSET (0x12058) 8196 #define CMIC_SER0_MEM_ADDR_6_OFFSET (0x12068) 8197 #define CMIC_SER0_MEM_ADDR_7_OFFSET (0x12078) 8198 #define CMIC_SER0_MEM_ADDR_8_OFFSET (0x12088) 8199 #define CMIC_SER0_MEM_ADDR_9_OFFSET (0x12098) 8200 #define CMIC_SER0_MEM_DATA_OFFSET (0x12208) 8201 #define CMIC_SER0_PARITY_MODE_SEL_15_0_OFFSET (0x12218) 8202 #define CMIC_SER0_PARITY_MODE_SEL_31_16_OFFSET (0x1221c) 8203 #define CMIC_SER0_POWER_DOWN_MEM_LOWER_OFFSET (0x12220) 8204 #define CMIC_SER0_POWER_DOWN_MEM_UPPER_OFFSET (0x12224) 8205 #define CMIC_SER0_PROTECT_ADDR_RANGE_VALID_OFFSET (0x12210) 8206 #define CMIC_SER0_RANGE0_DATAENTRY_LEN_OFFSET (0x1200c) 8207 #define CMIC_SER0_RANGE10_DATAENTRY_LEN_OFFSET (0x120ac) 8208 #define CMIC_SER0_RANGE11_DATAENTRY_LEN_OFFSET (0x120bc) 8209 #define CMIC_SER0_RANGE12_DATAENTRY_LEN_OFFSET (0x120cc) 8210 #define CMIC_SER0_RANGE13_DATAENTRY_LEN_OFFSET (0x120dc) 8211 #define CMIC_SER0_RANGE14_DATAENTRY_LEN_OFFSET (0x120ec) 8212 #define CMIC_SER0_RANGE15_DATAENTRY_LEN_OFFSET (0x120fc) 8213 #define CMIC_SER0_RANGE16_DATAENTRY_LEN_OFFSET (0x1210c) 8214 #define CMIC_SER0_RANGE17_DATAENTRY_LEN_OFFSET (0x1211c) 8215 #define CMIC_SER0_RANGE18_DATAENTRY_LEN_OFFSET (0x1212c) 8216 #define CMIC_SER0_RANGE19_DATAENTRY_LEN_OFFSET (0x1213c) 8217 #define CMIC_SER0_RANGE1_DATAENTRY_LEN_OFFSET (0x1201c) 8218 #define CMIC_SER0_RANGE20_DATAENTRY_LEN_OFFSET (0x1214c) 8219 #define CMIC_SER0_RANGE21_DATAENTRY_LEN_OFFSET (0x1215c) 8220 #define CMIC_SER0_RANGE22_DATAENTRY_LEN_OFFSET (0x1216c) 8221 #define CMIC_SER0_RANGE23_DATAENTRY_LEN_OFFSET (0x1217c) 8222 #define CMIC_SER0_RANGE24_DATAENTRY_LEN_OFFSET (0x1218c) 8223 #define CMIC_SER0_RANGE25_DATAENTRY_LEN_OFFSET (0x1219c) 8224 #define CMIC_SER0_RANGE26_DATAENTRY_LEN_OFFSET (0x121ac) 8225 #define CMIC_SER0_RANGE27_DATAENTRY_LEN_OFFSET (0x121bc) 8226 #define CMIC_SER0_RANGE28_DATAENTRY_LEN_OFFSET (0x121cc) 8227 #define CMIC_SER0_RANGE29_DATAENTRY_LEN_OFFSET (0x121dc) 8228 #define CMIC_SER0_RANGE2_DATAENTRY_LEN_OFFSET (0x1202c) 8229 #define CMIC_SER0_RANGE30_DATAENTRY_LEN_OFFSET (0x121ec) 8230 #define CMIC_SER0_RANGE31_DATAENTRY_LEN_OFFSET (0x121fc) 8231 #define CMIC_SER0_RANGE3_DATAENTRY_LEN_OFFSET (0x1203c) 8232 #define CMIC_SER0_RANGE4_DATAENTRY_LEN_OFFSET (0x1204c) 8233 #define CMIC_SER0_RANGE5_DATAENTRY_LEN_OFFSET (0x1205c) 8234 #define CMIC_SER0_RANGE6_DATAENTRY_LEN_OFFSET (0x1206c) 8235 #define CMIC_SER0_RANGE7_DATAENTRY_LEN_OFFSET (0x1207c) 8236 #define CMIC_SER0_RANGE8_DATAENTRY_LEN_OFFSET (0x1208c) 8237 #define CMIC_SER0_RANGE9_DATAENTRY_LEN_OFFSET (0x1209c) 8238 #define CMIC_SER0_START_ADDR_0_OFFSET (0x12000) 8239 #define CMIC_SER0_START_ADDR_1_OFFSET (0x12010) 8240 #define CMIC_SER0_START_ADDR_10_OFFSET (0x120a0) 8241 #define CMIC_SER0_START_ADDR_11_OFFSET (0x120b0) 8242 #define CMIC_SER0_START_ADDR_12_OFFSET (0x120c0) 8243 #define CMIC_SER0_START_ADDR_13_OFFSET (0x120d0) 8244 #define CMIC_SER0_START_ADDR_14_OFFSET (0x120e0) 8245 #define CMIC_SER0_START_ADDR_15_OFFSET (0x120f0) 8246 #define CMIC_SER0_START_ADDR_16_OFFSET (0x12100) 8247 #define CMIC_SER0_START_ADDR_17_OFFSET (0x12110) 8248 #define CMIC_SER0_START_ADDR_18_OFFSET (0x12120) 8249 #define CMIC_SER0_START_ADDR_19_OFFSET (0x12130) 8250 #define CMIC_SER0_START_ADDR_2_OFFSET (0x12020) 8251 #define CMIC_SER0_START_ADDR_20_OFFSET (0x12140) 8252 #define CMIC_SER0_START_ADDR_21_OFFSET (0x12150) 8253 #define CMIC_SER0_START_ADDR_22_OFFSET (0x12160) 8254 #define CMIC_SER0_START_ADDR_23_OFFSET (0x12170) 8255 #define CMIC_SER0_START_ADDR_24_OFFSET (0x12180) 8256 #define CMIC_SER0_START_ADDR_25_OFFSET (0x12190) 8257 #define CMIC_SER0_START_ADDR_26_OFFSET (0x121a0) 8258 #define CMIC_SER0_START_ADDR_27_OFFSET (0x121b0) 8259 #define CMIC_SER0_START_ADDR_28_OFFSET (0x121c0) 8260 #define CMIC_SER0_START_ADDR_29_OFFSET (0x121d0) 8261 #define CMIC_SER0_START_ADDR_3_OFFSET (0x12030) 8262 #define CMIC_SER0_START_ADDR_30_OFFSET (0x121e0) 8263 #define CMIC_SER0_START_ADDR_31_OFFSET (0x121f0) 8264 #define CMIC_SER0_START_ADDR_4_OFFSET (0x12040) 8265 #define CMIC_SER0_START_ADDR_5_OFFSET (0x12050) 8266 #define CMIC_SER0_START_ADDR_6_OFFSET (0x12060) 8267 #define CMIC_SER0_START_ADDR_7_OFFSET (0x12070) 8268 #define CMIC_SER0_START_ADDR_8_OFFSET (0x12080) 8269 #define CMIC_SER0_START_ADDR_9_OFFSET (0x12090) 8270 #define CMIC_SER1_END_ADDR_0_OFFSET (0x13004) 8271 #define CMIC_SER1_END_ADDR_1_OFFSET (0x13014) 8272 #define CMIC_SER1_END_ADDR_10_OFFSET (0x130a4) 8273 #define CMIC_SER1_END_ADDR_11_OFFSET (0x130b4) 8274 #define CMIC_SER1_END_ADDR_12_OFFSET (0x130c4) 8275 #define CMIC_SER1_END_ADDR_13_OFFSET (0x130d4) 8276 #define CMIC_SER1_END_ADDR_14_OFFSET (0x130e4) 8277 #define CMIC_SER1_END_ADDR_15_OFFSET (0x130f4) 8278 #define CMIC_SER1_END_ADDR_16_OFFSET (0x13104) 8279 #define CMIC_SER1_END_ADDR_17_OFFSET (0x13114) 8280 #define CMIC_SER1_END_ADDR_18_OFFSET (0x13124) 8281 #define CMIC_SER1_END_ADDR_19_OFFSET (0x13134) 8282 #define CMIC_SER1_END_ADDR_2_OFFSET (0x13024) 8283 #define CMIC_SER1_END_ADDR_20_OFFSET (0x13144) 8284 #define CMIC_SER1_END_ADDR_21_OFFSET (0x13154) 8285 #define CMIC_SER1_END_ADDR_22_OFFSET (0x13164) 8286 #define CMIC_SER1_END_ADDR_23_OFFSET (0x13174) 8287 #define CMIC_SER1_END_ADDR_24_OFFSET (0x13184) 8288 #define CMIC_SER1_END_ADDR_25_OFFSET (0x13194) 8289 #define CMIC_SER1_END_ADDR_26_OFFSET (0x131a4) 8290 #define CMIC_SER1_END_ADDR_27_OFFSET (0x131b4) 8291 #define CMIC_SER1_END_ADDR_28_OFFSET (0x131c4) 8292 #define CMIC_SER1_END_ADDR_29_OFFSET (0x131d4) 8293 #define CMIC_SER1_END_ADDR_3_OFFSET (0x13034) 8294 #define CMIC_SER1_END_ADDR_30_OFFSET (0x131e4) 8295 #define CMIC_SER1_END_ADDR_31_OFFSET (0x131f4) 8296 #define CMIC_SER1_END_ADDR_4_OFFSET (0x13044) 8297 #define CMIC_SER1_END_ADDR_5_OFFSET (0x13054) 8298 #define CMIC_SER1_END_ADDR_6_OFFSET (0x13064) 8299 #define CMIC_SER1_END_ADDR_7_OFFSET (0x13074) 8300 #define CMIC_SER1_END_ADDR_8_OFFSET (0x13084) 8301 #define CMIC_SER1_END_ADDR_9_OFFSET (0x13094) 8302 #define CMIC_SER1_FAIL_CNT_OFFSET (0x13200) 8303 #define CMIC_SER1_FAIL_ENTRY_OFFSET (0x13204) 8304 #define CMIC_SER1_INTERLEAVE_PARITY_OFFSET (0x13214) 8305 #define CMIC_SER1_MEM_ADDR_OFFSET (0x1320c) 8306 #define CMIC_SER1_MEM_ADDR_0_OFFSET (0x13008) 8307 #define CMIC_SER1_MEM_ADDR_1_OFFSET (0x13018) 8308 #define CMIC_SER1_MEM_ADDR_10_OFFSET (0x130a8) 8309 #define CMIC_SER1_MEM_ADDR_11_OFFSET (0x130b8) 8310 #define CMIC_SER1_MEM_ADDR_12_OFFSET (0x130c8) 8311 #define CMIC_SER1_MEM_ADDR_13_OFFSET (0x130d8) 8312 #define CMIC_SER1_MEM_ADDR_14_OFFSET (0x130e8) 8313 #define CMIC_SER1_MEM_ADDR_15_OFFSET (0x130f8) 8314 #define CMIC_SER1_MEM_ADDR_16_OFFSET (0x13108) 8315 #define CMIC_SER1_MEM_ADDR_17_OFFSET (0x13118) 8316 #define CMIC_SER1_MEM_ADDR_18_OFFSET (0x13128) 8317 #define CMIC_SER1_MEM_ADDR_19_OFFSET (0x13138) 8318 #define CMIC_SER1_MEM_ADDR_2_OFFSET (0x13028) 8319 #define CMIC_SER1_MEM_ADDR_20_OFFSET (0x13148) 8320 #define CMIC_SER1_MEM_ADDR_21_OFFSET (0x13158) 8321 #define CMIC_SER1_MEM_ADDR_22_OFFSET (0x13168) 8322 #define CMIC_SER1_MEM_ADDR_23_OFFSET (0x13178) 8323 #define CMIC_SER1_MEM_ADDR_24_OFFSET (0x13188) 8324 #define CMIC_SER1_MEM_ADDR_25_OFFSET (0x13198) 8325 #define CMIC_SER1_MEM_ADDR_26_OFFSET (0x131a8) 8326 #define CMIC_SER1_MEM_ADDR_27_OFFSET (0x131b8) 8327 #define CMIC_SER1_MEM_ADDR_28_OFFSET (0x131c8) 8328 #define CMIC_SER1_MEM_ADDR_29_OFFSET (0x131d8) 8329 #define CMIC_SER1_MEM_ADDR_3_OFFSET (0x13038) 8330 #define CMIC_SER1_MEM_ADDR_30_OFFSET (0x131e8) 8331 #define CMIC_SER1_MEM_ADDR_31_OFFSET (0x131f8) 8332 #define CMIC_SER1_MEM_ADDR_4_OFFSET (0x13048) 8333 #define CMIC_SER1_MEM_ADDR_5_OFFSET (0x13058) 8334 #define CMIC_SER1_MEM_ADDR_6_OFFSET (0x13068) 8335 #define CMIC_SER1_MEM_ADDR_7_OFFSET (0x13078) 8336 #define CMIC_SER1_MEM_ADDR_8_OFFSET (0x13088) 8337 #define CMIC_SER1_MEM_ADDR_9_OFFSET (0x13098) 8338 #define CMIC_SER1_MEM_DATA_OFFSET (0x13208) 8339 #define CMIC_SER1_PARITY_MODE_SEL_15_0_OFFSET (0x13218) 8340 #define CMIC_SER1_PARITY_MODE_SEL_31_16_OFFSET (0x1321c) 8341 #define CMIC_SER1_POWER_DOWN_MEM_LOWER_OFFSET (0x13220) 8342 #define CMIC_SER1_POWER_DOWN_MEM_UPPER_OFFSET (0x13224) 8343 #define CMIC_SER1_PROTECT_ADDR_RANGE_VALID_OFFSET (0x13210) 8344 #define CMIC_SER1_RANGE0_DATAENTRY_LEN_OFFSET (0x1300c) 8345 #define CMIC_SER1_RANGE10_DATAENTRY_LEN_OFFSET (0x130ac) 8346 #define CMIC_SER1_RANGE11_DATAENTRY_LEN_OFFSET (0x130bc) 8347 #define CMIC_SER1_RANGE12_DATAENTRY_LEN_OFFSET (0x130cc) 8348 #define CMIC_SER1_RANGE13_DATAENTRY_LEN_OFFSET (0x130dc) 8349 #define CMIC_SER1_RANGE14_DATAENTRY_LEN_OFFSET (0x130ec) 8350 #define CMIC_SER1_RANGE15_DATAENTRY_LEN_OFFSET (0x130fc) 8351 #define CMIC_SER1_RANGE16_DATAENTRY_LEN_OFFSET (0x1310c) 8352 #define CMIC_SER1_RANGE17_DATAENTRY_LEN_OFFSET (0x1311c) 8353 #define CMIC_SER1_RANGE18_DATAENTRY_LEN_OFFSET (0x1312c) 8354 #define CMIC_SER1_RANGE19_DATAENTRY_LEN_OFFSET (0x1313c) 8355 #define CMIC_SER1_RANGE1_DATAENTRY_LEN_OFFSET (0x1301c) 8356 #define CMIC_SER1_RANGE20_DATAENTRY_LEN_OFFSET (0x1314c) 8357 #define CMIC_SER1_RANGE21_DATAENTRY_LEN_OFFSET (0x1315c) 8358 #define CMIC_SER1_RANGE22_DATAENTRY_LEN_OFFSET (0x1316c) 8359 #define CMIC_SER1_RANGE23_DATAENTRY_LEN_OFFSET (0x1317c) 8360 #define CMIC_SER1_RANGE24_DATAENTRY_LEN_OFFSET (0x1318c) 8361 #define CMIC_SER1_RANGE25_DATAENTRY_LEN_OFFSET (0x1319c) 8362 #define CMIC_SER1_RANGE26_DATAENTRY_LEN_OFFSET (0x131ac) 8363 #define CMIC_SER1_RANGE27_DATAENTRY_LEN_OFFSET (0x131bc) 8364 #define CMIC_SER1_RANGE28_DATAENTRY_LEN_OFFSET (0x131cc) 8365 #define CMIC_SER1_RANGE29_DATAENTRY_LEN_OFFSET (0x131dc) 8366 #define CMIC_SER1_RANGE2_DATAENTRY_LEN_OFFSET (0x1302c) 8367 #define CMIC_SER1_RANGE30_DATAENTRY_LEN_OFFSET (0x131ec) 8368 #define CMIC_SER1_RANGE31_DATAENTRY_LEN_OFFSET (0x131fc) 8369 #define CMIC_SER1_RANGE3_DATAENTRY_LEN_OFFSET (0x1303c) 8370 #define CMIC_SER1_RANGE4_DATAENTRY_LEN_OFFSET (0x1304c) 8371 #define CMIC_SER1_RANGE5_DATAENTRY_LEN_OFFSET (0x1305c) 8372 #define CMIC_SER1_RANGE6_DATAENTRY_LEN_OFFSET (0x1306c) 8373 #define CMIC_SER1_RANGE7_DATAENTRY_LEN_OFFSET (0x1307c) 8374 #define CMIC_SER1_RANGE8_DATAENTRY_LEN_OFFSET (0x1308c) 8375 #define CMIC_SER1_RANGE9_DATAENTRY_LEN_OFFSET (0x1309c) 8376 #define CMIC_SER1_START_ADDR_0_OFFSET (0x13000) 8377 #define CMIC_SER1_START_ADDR_1_OFFSET (0x13010) 8378 #define CMIC_SER1_START_ADDR_10_OFFSET (0x130a0) 8379 #define CMIC_SER1_START_ADDR_11_OFFSET (0x130b0) 8380 #define CMIC_SER1_START_ADDR_12_OFFSET (0x130c0) 8381 #define CMIC_SER1_START_ADDR_13_OFFSET (0x130d0) 8382 #define CMIC_SER1_START_ADDR_14_OFFSET (0x130e0) 8383 #define CMIC_SER1_START_ADDR_15_OFFSET (0x130f0) 8384 #define CMIC_SER1_START_ADDR_16_OFFSET (0x13100) 8385 #define CMIC_SER1_START_ADDR_17_OFFSET (0x13110) 8386 #define CMIC_SER1_START_ADDR_18_OFFSET (0x13120) 8387 #define CMIC_SER1_START_ADDR_19_OFFSET (0x13130) 8388 #define CMIC_SER1_START_ADDR_2_OFFSET (0x13020) 8389 #define CMIC_SER1_START_ADDR_20_OFFSET (0x13140) 8390 #define CMIC_SER1_START_ADDR_21_OFFSET (0x13150) 8391 #define CMIC_SER1_START_ADDR_22_OFFSET (0x13160) 8392 #define CMIC_SER1_START_ADDR_23_OFFSET (0x13170) 8393 #define CMIC_SER1_START_ADDR_24_OFFSET (0x13180) 8394 #define CMIC_SER1_START_ADDR_25_OFFSET (0x13190) 8395 #define CMIC_SER1_START_ADDR_26_OFFSET (0x131a0) 8396 #define CMIC_SER1_START_ADDR_27_OFFSET (0x131b0) 8397 #define CMIC_SER1_START_ADDR_28_OFFSET (0x131c0) 8398 #define CMIC_SER1_START_ADDR_29_OFFSET (0x131d0) 8399 #define CMIC_SER1_START_ADDR_3_OFFSET (0x13030) 8400 #define CMIC_SER1_START_ADDR_30_OFFSET (0x131e0) 8401 #define CMIC_SER1_START_ADDR_31_OFFSET (0x131f0) 8402 #define CMIC_SER1_START_ADDR_4_OFFSET (0x13040) 8403 #define CMIC_SER1_START_ADDR_5_OFFSET (0x13050) 8404 #define CMIC_SER1_START_ADDR_6_OFFSET (0x13060) 8405 #define CMIC_SER1_START_ADDR_7_OFFSET (0x13070) 8406 #define CMIC_SER1_START_ADDR_8_OFFSET (0x13080) 8407 #define CMIC_SER1_START_ADDR_9_OFFSET (0x13090) 8408 #define CMIC_SER_END_ADDR_0_OFFSET (0x12004) 8409 #define CMIC_SER_END_ADDR_1_OFFSET (0x12014) 8410 #define CMIC_SER_END_ADDR_10_OFFSET (0x120a4) 8411 #define CMIC_SER_END_ADDR_11_OFFSET (0x120b4) 8412 #define CMIC_SER_END_ADDR_12_OFFSET (0x120c4) 8413 #define CMIC_SER_END_ADDR_13_OFFSET (0x120d4) 8414 #define CMIC_SER_END_ADDR_14_OFFSET (0x120e4) 8415 #define CMIC_SER_END_ADDR_15_OFFSET (0x120f4) 8416 #define CMIC_SER_END_ADDR_16_OFFSET (0x12104) 8417 #define CMIC_SER_END_ADDR_17_OFFSET (0x12114) 8418 #define CMIC_SER_END_ADDR_18_OFFSET (0x12124) 8419 #define CMIC_SER_END_ADDR_19_OFFSET (0x12134) 8420 #define CMIC_SER_END_ADDR_2_OFFSET (0x12024) 8421 #define CMIC_SER_END_ADDR_20_OFFSET (0x12144) 8422 #define CMIC_SER_END_ADDR_21_OFFSET (0x12154) 8423 #define CMIC_SER_END_ADDR_22_OFFSET (0x12164) 8424 #define CMIC_SER_END_ADDR_23_OFFSET (0x12174) 8425 #define CMIC_SER_END_ADDR_24_OFFSET (0x12184) 8426 #define CMIC_SER_END_ADDR_25_OFFSET (0x12194) 8427 #define CMIC_SER_END_ADDR_26_OFFSET (0x121a4) 8428 #define CMIC_SER_END_ADDR_27_OFFSET (0x121b4) 8429 #define CMIC_SER_END_ADDR_28_OFFSET (0x121c4) 8430 #define CMIC_SER_END_ADDR_29_OFFSET (0x121d4) 8431 #define CMIC_SER_END_ADDR_3_OFFSET (0x12034) 8432 #define CMIC_SER_END_ADDR_30_OFFSET (0x121e4) 8433 #define CMIC_SER_END_ADDR_31_OFFSET (0x121f4) 8434 #define CMIC_SER_END_ADDR_4_OFFSET (0x12044) 8435 #define CMIC_SER_END_ADDR_5_OFFSET (0x12054) 8436 #define CMIC_SER_END_ADDR_6_OFFSET (0x12064) 8437 #define CMIC_SER_END_ADDR_7_OFFSET (0x12074) 8438 #define CMIC_SER_END_ADDR_8_OFFSET (0x12084) 8439 #define CMIC_SER_END_ADDR_9_OFFSET (0x12094) 8440 #define CMIC_SER_FAIL_CNT_OFFSET (0x12200) 8441 #define CMIC_SER_FAIL_ENTRY_OFFSET (0x12204) 8442 #define CMIC_SER_INTERLEAVE_PARITY_OFFSET (0x12214) 8443 #define CMIC_SER_MEM_ADDR_OFFSET (0x1220c) 8444 #define CMIC_SER_MEM_ADDR_0_OFFSET (0x12008) 8445 #define CMIC_SER_MEM_ADDR_1_OFFSET (0x12018) 8446 #define CMIC_SER_MEM_ADDR_10_OFFSET (0x120a8) 8447 #define CMIC_SER_MEM_ADDR_11_OFFSET (0x120b8) 8448 #define CMIC_SER_MEM_ADDR_12_OFFSET (0x120c8) 8449 #define CMIC_SER_MEM_ADDR_13_OFFSET (0x120d8) 8450 #define CMIC_SER_MEM_ADDR_14_OFFSET (0x120e8) 8451 #define CMIC_SER_MEM_ADDR_15_OFFSET (0x120f8) 8452 #define CMIC_SER_MEM_ADDR_16_OFFSET (0x12108) 8453 #define CMIC_SER_MEM_ADDR_17_OFFSET (0x12118) 8454 #define CMIC_SER_MEM_ADDR_18_OFFSET (0x12128) 8455 #define CMIC_SER_MEM_ADDR_19_OFFSET (0x12138) 8456 #define CMIC_SER_MEM_ADDR_2_OFFSET (0x12028) 8457 #define CMIC_SER_MEM_ADDR_20_OFFSET (0x12148) 8458 #define CMIC_SER_MEM_ADDR_21_OFFSET (0x12158) 8459 #define CMIC_SER_MEM_ADDR_22_OFFSET (0x12168) 8460 #define CMIC_SER_MEM_ADDR_23_OFFSET (0x12178) 8461 #define CMIC_SER_MEM_ADDR_24_OFFSET (0x12188) 8462 #define CMIC_SER_MEM_ADDR_25_OFFSET (0x12198) 8463 #define CMIC_SER_MEM_ADDR_26_OFFSET (0x121a8) 8464 #define CMIC_SER_MEM_ADDR_27_OFFSET (0x121b8) 8465 #define CMIC_SER_MEM_ADDR_28_OFFSET (0x121c8) 8466 #define CMIC_SER_MEM_ADDR_29_OFFSET (0x121d8) 8467 #define CMIC_SER_MEM_ADDR_3_OFFSET (0x12038) 8468 #define CMIC_SER_MEM_ADDR_30_OFFSET (0x121e8) 8469 #define CMIC_SER_MEM_ADDR_31_OFFSET (0x121f8) 8470 #define CMIC_SER_MEM_ADDR_4_OFFSET (0x12048) 8471 #define CMIC_SER_MEM_ADDR_5_OFFSET (0x12058) 8472 #define CMIC_SER_MEM_ADDR_6_OFFSET (0x12068) 8473 #define CMIC_SER_MEM_ADDR_7_OFFSET (0x12078) 8474 #define CMIC_SER_MEM_ADDR_8_OFFSET (0x12088) 8475 #define CMIC_SER_MEM_ADDR_9_OFFSET (0x12098) 8476 #define CMIC_SER_MEM_DATA_OFFSET (0x12208) 8477 #define CMIC_SER_PARITY_MODE_SEL_15_0_OFFSET (0x12218) 8478 #define CMIC_SER_PARITY_MODE_SEL_31_16_OFFSET (0x1221c) 8479 #define CMIC_SER_POWER_DOWN_MEM_LOWER_OFFSET (0x12220) 8480 #define CMIC_SER_POWER_DOWN_MEM_UPPER_OFFSET (0x12224) 8481 #define CMIC_SER_PROTECT_ADDR_RANGE_VALID_OFFSET (0x12210) 8482 #define CMIC_SER_RANGE0_DATAENTRY_LEN_OFFSET (0x1200c) 8483 #define CMIC_SER_RANGE10_DATAENTRY_LEN_OFFSET (0x120ac) 8484 #define CMIC_SER_RANGE11_DATAENTRY_LEN_OFFSET (0x120bc) 8485 #define CMIC_SER_RANGE12_DATAENTRY_LEN_OFFSET (0x120cc) 8486 #define CMIC_SER_RANGE13_DATAENTRY_LEN_OFFSET (0x120dc) 8487 #define CMIC_SER_RANGE14_DATAENTRY_LEN_OFFSET (0x120ec) 8488 #define CMIC_SER_RANGE15_DATAENTRY_LEN_OFFSET (0x120fc) 8489 #define CMIC_SER_RANGE16_DATAENTRY_LEN_OFFSET (0x1210c) 8490 #define CMIC_SER_RANGE17_DATAENTRY_LEN_OFFSET (0x1211c) 8491 #define CMIC_SER_RANGE18_DATAENTRY_LEN_OFFSET (0x1212c) 8492 #define CMIC_SER_RANGE19_DATAENTRY_LEN_OFFSET (0x1213c) 8493 #define CMIC_SER_RANGE1_DATAENTRY_LEN_OFFSET (0x1201c) 8494 #define CMIC_SER_RANGE20_DATAENTRY_LEN_OFFSET (0x1214c) 8495 #define CMIC_SER_RANGE21_DATAENTRY_LEN_OFFSET (0x1215c) 8496 #define CMIC_SER_RANGE22_DATAENTRY_LEN_OFFSET (0x1216c) 8497 #define CMIC_SER_RANGE23_DATAENTRY_LEN_OFFSET (0x1217c) 8498 #define CMIC_SER_RANGE24_DATAENTRY_LEN_OFFSET (0x1218c) 8499 #define CMIC_SER_RANGE25_DATAENTRY_LEN_OFFSET (0x1219c) 8500 #define CMIC_SER_RANGE26_DATAENTRY_LEN_OFFSET (0x121ac) 8501 #define CMIC_SER_RANGE27_DATAENTRY_LEN_OFFSET (0x121bc) 8502 #define CMIC_SER_RANGE28_DATAENTRY_LEN_OFFSET (0x121cc) 8503 #define CMIC_SER_RANGE29_DATAENTRY_LEN_OFFSET (0x121dc) 8504 #define CMIC_SER_RANGE2_DATAENTRY_LEN_OFFSET (0x1202c) 8505 #define CMIC_SER_RANGE30_DATAENTRY_LEN_OFFSET (0x121ec) 8506 #define CMIC_SER_RANGE31_DATAENTRY_LEN_OFFSET (0x121fc) 8507 #define CMIC_SER_RANGE3_DATAENTRY_LEN_OFFSET (0x1203c) 8508 #define CMIC_SER_RANGE4_DATAENTRY_LEN_OFFSET (0x1204c) 8509 #define CMIC_SER_RANGE5_DATAENTRY_LEN_OFFSET (0x1205c) 8510 #define CMIC_SER_RANGE6_DATAENTRY_LEN_OFFSET (0x1206c) 8511 #define CMIC_SER_RANGE7_DATAENTRY_LEN_OFFSET (0x1207c) 8512 #define CMIC_SER_RANGE8_DATAENTRY_LEN_OFFSET (0x1208c) 8513 #define CMIC_SER_RANGE9_DATAENTRY_LEN_OFFSET (0x1209c) 8514 #define CMIC_SER_START_ADDR_0_OFFSET (0x12000) 8515 #define CMIC_SER_START_ADDR_1_OFFSET (0x12010) 8516 #define CMIC_SER_START_ADDR_10_OFFSET (0x120a0) 8517 #define CMIC_SER_START_ADDR_11_OFFSET (0x120b0) 8518 #define CMIC_SER_START_ADDR_12_OFFSET (0x120c0) 8519 #define CMIC_SER_START_ADDR_13_OFFSET (0x120d0) 8520 #define CMIC_SER_START_ADDR_14_OFFSET (0x120e0) 8521 #define CMIC_SER_START_ADDR_15_OFFSET (0x120f0) 8522 #define CMIC_SER_START_ADDR_16_OFFSET (0x12100) 8523 #define CMIC_SER_START_ADDR_17_OFFSET (0x12110) 8524 #define CMIC_SER_START_ADDR_18_OFFSET (0x12120) 8525 #define CMIC_SER_START_ADDR_19_OFFSET (0x12130) 8526 #define CMIC_SER_START_ADDR_2_OFFSET (0x12020) 8527 #define CMIC_SER_START_ADDR_20_OFFSET (0x12140) 8528 #define CMIC_SER_START_ADDR_21_OFFSET (0x12150) 8529 #define CMIC_SER_START_ADDR_22_OFFSET (0x12160) 8530 #define CMIC_SER_START_ADDR_23_OFFSET (0x12170) 8531 #define CMIC_SER_START_ADDR_24_OFFSET (0x12180) 8532 #define CMIC_SER_START_ADDR_25_OFFSET (0x12190) 8533 #define CMIC_SER_START_ADDR_26_OFFSET (0x121a0) 8534 #define CMIC_SER_START_ADDR_27_OFFSET (0x121b0) 8535 #define CMIC_SER_START_ADDR_28_OFFSET (0x121c0) 8536 #define CMIC_SER_START_ADDR_29_OFFSET (0x121d0) 8537 #define CMIC_SER_START_ADDR_3_OFFSET (0x12030) 8538 #define CMIC_SER_START_ADDR_30_OFFSET (0x121e0) 8539 #define CMIC_SER_START_ADDR_31_OFFSET (0x121f0) 8540 #define CMIC_SER_START_ADDR_4_OFFSET (0x12040) 8541 #define CMIC_SER_START_ADDR_5_OFFSET (0x12050) 8542 #define CMIC_SER_START_ADDR_6_OFFSET (0x12060) 8543 #define CMIC_SER_START_ADDR_7_OFFSET (0x12070) 8544 #define CMIC_SER_START_ADDR_8_OFFSET (0x12080) 8545 #define CMIC_SER_START_ADDR_9_OFFSET (0x12090) 8546 #define CMIC_SRAM_TM0_CONTROL_OFFSET (0x10188) 8547 #define CMIC_SRAM_TM1_CONTROL_OFFSET (0x1018c) 8548 #define CMIC_SRAM_TM2_CONTROL_OFFSET (0x10190) 8549 #define CMIC_SRAM_TM3_CONTROL_OFFSET (0x101a0) 8550 #define CMIC_STAT_DMA_BLKNUM_MAP_14_10_OFFSET (0x100cc) 8551 #define CMIC_STAT_DMA_BLKNUM_MAP_19_15_OFFSET (0x100d0) 8552 #define CMIC_STAT_DMA_BLKNUM_MAP_24_20_OFFSET (0x100d4) 8553 #define CMIC_STAT_DMA_BLKNUM_MAP_29_25_OFFSET (0x100d8) 8554 #define CMIC_STAT_DMA_BLKNUM_MAP_34_30_OFFSET (0x100dc) 8555 #define CMIC_STAT_DMA_BLKNUM_MAP_39_35_OFFSET (0x100e0) 8556 #define CMIC_STAT_DMA_BLKNUM_MAP_44_40_OFFSET (0x100e4) 8557 #define CMIC_STAT_DMA_BLKNUM_MAP_49_45_OFFSET (0x100e8) 8558 #define CMIC_STAT_DMA_BLKNUM_MAP_4_0_OFFSET (0x100c4) 8559 #define CMIC_STAT_DMA_BLKNUM_MAP_54_50_OFFSET (0x100ec) 8560 #define CMIC_STAT_DMA_BLKNUM_MAP_59_55_OFFSET (0x100f0) 8561 #define CMIC_STAT_DMA_BLKNUM_MAP_64_60_OFFSET (0x100f4) 8562 #define CMIC_STAT_DMA_BLKNUM_MAP_69_65_OFFSET (0x100f8) 8563 #define CMIC_STAT_DMA_BLKNUM_MAP_74_70_OFFSET (0x100fc) 8564 #define CMIC_STAT_DMA_BLKNUM_MAP_79_75_OFFSET (0x10100) 8565 #define CMIC_STAT_DMA_BLKNUM_MAP_84_80_OFFSET (0x10104) 8566 #define CMIC_STAT_DMA_BLKNUM_MAP_89_85_OFFSET (0x10108) 8567 #define CMIC_STAT_DMA_BLKNUM_MAP_94_90_OFFSET (0x1010c) 8568 #define CMIC_STAT_DMA_BLKNUM_MAP_95_OFFSET (0x10110) 8569 #define CMIC_STAT_DMA_BLKNUM_MAP_9_5_OFFSET (0x100c8) 8570 #define CMIC_STAT_DMA_EGR_STATS_CFG_OFFSET (0x10118) 8571 #define CMIC_STAT_DMA_ING_STATS_CFG_OFFSET (0x10114) 8572 #define CMIC_STAT_DMA_MAC_STATS_CFG_OFFSET (0x1011c) 8573 #define CMIC_STAT_DMA_PORTNUM_MAP_11_8_OFFSET (0x10128) 8574 #define CMIC_STAT_DMA_PORTNUM_MAP_15_12_OFFSET (0x1012c) 8575 #define CMIC_STAT_DMA_PORTNUM_MAP_19_16_OFFSET (0x10130) 8576 #define CMIC_STAT_DMA_PORTNUM_MAP_23_20_OFFSET (0x10134) 8577 #define CMIC_STAT_DMA_PORTNUM_MAP_27_24_OFFSET (0x10138) 8578 #define CMIC_STAT_DMA_PORTNUM_MAP_31_28_OFFSET (0x1013c) 8579 #define CMIC_STAT_DMA_PORTNUM_MAP_35_32_OFFSET (0x10140) 8580 #define CMIC_STAT_DMA_PORTNUM_MAP_39_36_OFFSET (0x10144) 8581 #define CMIC_STAT_DMA_PORTNUM_MAP_3_0_OFFSET (0x10120) 8582 #define CMIC_STAT_DMA_PORTNUM_MAP_43_40_OFFSET (0x10148) 8583 #define CMIC_STAT_DMA_PORTNUM_MAP_47_44_OFFSET (0x1014c) 8584 #define CMIC_STAT_DMA_PORTNUM_MAP_51_48_OFFSET (0x10150) 8585 #define CMIC_STAT_DMA_PORTNUM_MAP_55_52_OFFSET (0x10154) 8586 #define CMIC_STAT_DMA_PORTNUM_MAP_59_56_OFFSET (0x10158) 8587 #define CMIC_STAT_DMA_PORTNUM_MAP_63_60_OFFSET (0x1015c) 8588 #define CMIC_STAT_DMA_PORTNUM_MAP_67_64_OFFSET (0x10160) 8589 #define CMIC_STAT_DMA_PORTNUM_MAP_71_68_OFFSET (0x10164) 8590 #define CMIC_STAT_DMA_PORTNUM_MAP_75_72_OFFSET (0x10168) 8591 #define CMIC_STAT_DMA_PORTNUM_MAP_79_76_OFFSET (0x1016c) 8592 #define CMIC_STAT_DMA_PORTNUM_MAP_7_4_OFFSET (0x10124) 8593 #define CMIC_STAT_DMA_PORTNUM_MAP_83_80_OFFSET (0x10170) 8594 #define CMIC_STAT_DMA_PORTNUM_MAP_87_84_OFFSET (0x10174) 8595 #define CMIC_STAT_DMA_PORTNUM_MAP_91_88_OFFSET (0x10178) 8596 #define CMIC_STAT_DMA_PORTNUM_MAP_95_92_OFFSET (0x1017c) 8597 #define CMIC_STAT_DMA_PORT_TYPE_MAP_0_OFFSET (0x100b8) 8598 #define CMIC_STAT_DMA_PORT_TYPE_MAP_1_OFFSET (0x100bc) 8599 #define CMIC_STAT_DMA_PORT_TYPE_MAP_2_OFFSET (0x100c0) 8600 #define CMIC_SW_RST_OFFSET (0x1021c) 8601 #define CMIC_TIM0_TIMER1BGLOAD_OFFSET (0x24018) 8602 #define CMIC_TIM0_TIMER1CONTROL_OFFSET (0x24008) 8603 #define CMIC_TIM0_TIMER1INTCLR_OFFSET (0x2400c) 8604 #define CMIC_TIM0_TIMER1LOAD_OFFSET (0x24000) 8605 #define CMIC_TIM0_TIMER1MIS_OFFSET (0x24014) 8606 #define CMIC_TIM0_TIMER1RIS_OFFSET (0x24010) 8607 #define CMIC_TIM0_TIMER1VALUE_OFFSET (0x24004) 8608 #define CMIC_TIM0_TIMER2BGLOAD_OFFSET (0x24038) 8609 #define CMIC_TIM0_TIMER2CONTROL_OFFSET (0x24028) 8610 #define CMIC_TIM0_TIMER2INTCLR_OFFSET (0x2402c) 8611 #define CMIC_TIM0_TIMER2LOAD_OFFSET (0x24020) 8612 #define CMIC_TIM0_TIMER2MIS_OFFSET (0x24034) 8613 #define CMIC_TIM0_TIMER2RIS_OFFSET (0x24030) 8614 #define CMIC_TIM0_TIMER2VALUE_OFFSET (0x24024) 8615 #define CMIC_TIM0_TIMERITCR_OFFSET (0x24f00) 8616 #define CMIC_TIM0_TIMERITOP_OFFSET (0x24f04) 8617 #define CMIC_TIM0_TIMERPCELLID0_OFFSET (0x24ff0) 8618 #define CMIC_TIM0_TIMERPCELLID1_OFFSET (0x24ff4) 8619 #define CMIC_TIM0_TIMERPCELLID2_OFFSET (0x24ff8) 8620 #define CMIC_TIM0_TIMERPCELLID3_OFFSET (0x24ffc) 8621 #define CMIC_TIM0_TIMERPERIPHID0_OFFSET (0x24fe0) 8622 #define CMIC_TIM0_TIMERPERIPHID1_OFFSET (0x24fe4) 8623 #define CMIC_TIM0_TIMERPERIPHID2_OFFSET (0x24fe8) 8624 #define CMIC_TIM0_TIMERPERIPHID3_OFFSET (0x24fec) 8625 #define CMIC_TIM1_TIMER1BGLOAD_OFFSET (0x26018) 8626 #define CMIC_TIM1_TIMER1CONTROL_OFFSET (0x26008) 8627 #define CMIC_TIM1_TIMER1INTCLR_OFFSET (0x2600c) 8628 #define CMIC_TIM1_TIMER1LOAD_OFFSET (0x26000) 8629 #define CMIC_TIM1_TIMER1MIS_OFFSET (0x26014) 8630 #define CMIC_TIM1_TIMER1RIS_OFFSET (0x26010) 8631 #define CMIC_TIM1_TIMER1VALUE_OFFSET (0x26004) 8632 #define CMIC_TIM1_TIMER2BGLOAD_OFFSET (0x26038) 8633 #define CMIC_TIM1_TIMER2CONTROL_OFFSET (0x26028) 8634 #define CMIC_TIM1_TIMER2INTCLR_OFFSET (0x2602c) 8635 #define CMIC_TIM1_TIMER2LOAD_OFFSET (0x26020) 8636 #define CMIC_TIM1_TIMER2MIS_OFFSET (0x26034) 8637 #define CMIC_TIM1_TIMER2RIS_OFFSET (0x26030) 8638 #define CMIC_TIM1_TIMER2VALUE_OFFSET (0x26024) 8639 #define CMIC_TIM1_TIMERITCR_OFFSET (0x26f00) 8640 #define CMIC_TIM1_TIMERITOP_OFFSET (0x26f04) 8641 #define CMIC_TIM1_TIMERPCELLID0_OFFSET (0x26ff0) 8642 #define CMIC_TIM1_TIMERPCELLID1_OFFSET (0x26ff4) 8643 #define CMIC_TIM1_TIMERPCELLID2_OFFSET (0x26ff8) 8644 #define CMIC_TIM1_TIMERPCELLID3_OFFSET (0x26ffc) 8645 #define CMIC_TIM1_TIMERPERIPHID0_OFFSET (0x26fe0) 8646 #define CMIC_TIM1_TIMERPERIPHID1_OFFSET (0x26fe4) 8647 #define CMIC_TIM1_TIMERPERIPHID2_OFFSET (0x26fe8) 8648 #define CMIC_TIM1_TIMERPERIPHID3_OFFSET (0x26fec) 8649 #define CMIC_TIMESYNC_BROADSYNC0_CLK_COUNT_CTRL_OFFSET (0x10900) 8650 #define CMIC_TIMESYNC_BROADSYNC1_CLK_COUNT_CTRL_OFFSET (0x10904) 8651 #define CMIC_TIMESYNC_CAPTURE_STATUS_1_OFFSET (0x1090c) 8652 #define CMIC_TIMESYNC_CAPTURE_STATUS_CLR_1_OFFSET (0x10910) 8653 #define CMIC_TIMESYNC_COUNTER_CONFIG_SELECT_OFFSET (0x10600) 8654 #define CMIC_TIMESYNC_FIFO_ECC_CONFIG_OFFSET (0x10924) 8655 #define CMIC_TIMESYNC_FIFO_ECC_STATUS_OFFSET (0x10928) 8656 #define CMIC_TIMESYNC_FIFO_STATUS_OFFSET (0x1063c) 8657 #define CMIC_TIMESYNC_GPIO_0_CTRL_OFFSET (0x10640) 8658 #define CMIC_TIMESYNC_GPIO_0_DOWN_EVENT_CTRL_OFFSET (0x1064c) 8659 #define CMIC_TIMESYNC_GPIO_0_INPUT_DIVISOR_OFFSET (0x10658) 8660 #define CMIC_TIMESYNC_GPIO_0_OUTPUT_ENABLE_OFFSET (0x10644) 8661 #define CMIC_TIMESYNC_GPIO_0_PHASE_ADJUST_LOWER_OFFSET (0x10650) 8662 #define CMIC_TIMESYNC_GPIO_0_PHASE_ADJUST_UPPER_OFFSET (0x10654) 8663 #define CMIC_TIMESYNC_GPIO_0_UP_EVENT_CTRL_OFFSET (0x10648) 8664 #define CMIC_TIMESYNC_GPIO_1_CTRL_OFFSET (0x1065c) 8665 #define CMIC_TIMESYNC_GPIO_1_DOWN_EVENT_CTRL_OFFSET (0x10668) 8666 #define CMIC_TIMESYNC_GPIO_1_INPUT_DIVISOR_OFFSET (0x10674) 8667 #define CMIC_TIMESYNC_GPIO_1_OUTPUT_ENABLE_OFFSET (0x10660) 8668 #define CMIC_TIMESYNC_GPIO_1_PHASE_ADJUST_LOWER_OFFSET (0x1066c) 8669 #define CMIC_TIMESYNC_GPIO_1_PHASE_ADJUST_UPPER_OFFSET (0x10670) 8670 #define CMIC_TIMESYNC_GPIO_1_UP_EVENT_CTRL_OFFSET (0x10664) 8671 #define CMIC_TIMESYNC_GPIO_2_CTRL_OFFSET (0x10678) 8672 #define CMIC_TIMESYNC_GPIO_2_DOWN_EVENT_CTRL_OFFSET (0x10684) 8673 #define CMIC_TIMESYNC_GPIO_2_INPUT_DIVISOR_OFFSET (0x10690) 8674 #define CMIC_TIMESYNC_GPIO_2_OUTPUT_ENABLE_OFFSET (0x1067c) 8675 #define CMIC_TIMESYNC_GPIO_2_PHASE_ADJUST_LOWER_OFFSET (0x10688) 8676 #define CMIC_TIMESYNC_GPIO_2_PHASE_ADJUST_UPPER_OFFSET (0x1068c) 8677 #define CMIC_TIMESYNC_GPIO_2_UP_EVENT_CTRL_OFFSET (0x10680) 8678 #define CMIC_TIMESYNC_GPIO_3_CTRL_OFFSET (0x10694) 8679 #define CMIC_TIMESYNC_GPIO_3_DOWN_EVENT_CTRL_OFFSET (0x106a0) 8680 #define CMIC_TIMESYNC_GPIO_3_INPUT_DIVISOR_OFFSET (0x106ac) 8681 #define CMIC_TIMESYNC_GPIO_3_OUTPUT_ENABLE_OFFSET (0x10698) 8682 #define CMIC_TIMESYNC_GPIO_3_PHASE_ADJUST_LOWER_OFFSET (0x106a4) 8683 #define CMIC_TIMESYNC_GPIO_3_PHASE_ADJUST_UPPER_OFFSET (0x106a8) 8684 #define CMIC_TIMESYNC_GPIO_3_UP_EVENT_CTRL_OFFSET (0x1069c) 8685 #define CMIC_TIMESYNC_GPIO_4_CTRL_OFFSET (0x106b0) 8686 #define CMIC_TIMESYNC_GPIO_4_DOWN_EVENT_CTRL_OFFSET (0x106bc) 8687 #define CMIC_TIMESYNC_GPIO_4_INPUT_DIVISOR_OFFSET (0x106c8) 8688 #define CMIC_TIMESYNC_GPIO_4_OUTPUT_ENABLE_OFFSET (0x106b4) 8689 #define CMIC_TIMESYNC_GPIO_4_PHASE_ADJUST_LOWER_OFFSET (0x106c0) 8690 #define CMIC_TIMESYNC_GPIO_4_PHASE_ADJUST_UPPER_OFFSET (0x106c4) 8691 #define CMIC_TIMESYNC_GPIO_4_UP_EVENT_CTRL_OFFSET (0x106b8) 8692 #define CMIC_TIMESYNC_GPIO_5_CTRL_OFFSET (0x106cc) 8693 #define CMIC_TIMESYNC_GPIO_5_DOWN_EVENT_CTRL_OFFSET (0x106d8) 8694 #define CMIC_TIMESYNC_GPIO_5_INPUT_DIVISOR_OFFSET (0x106e4) 8695 #define CMIC_TIMESYNC_GPIO_5_OUTPUT_ENABLE_OFFSET (0x106d0) 8696 #define CMIC_TIMESYNC_GPIO_5_PHASE_ADJUST_LOWER_OFFSET (0x106dc) 8697 #define CMIC_TIMESYNC_GPIO_5_PHASE_ADJUST_UPPER_OFFSET (0x106e0) 8698 #define CMIC_TIMESYNC_GPIO_5_UP_EVENT_CTRL_OFFSET (0x106d4) 8699 #define CMIC_TIMESYNC_INPUT_TIME_FIFO_TS_LOWER_OFFSET (0x1062c) 8700 #define CMIC_TIMESYNC_INPUT_TIME_FIFO_TS_UPPER_OFFSET (0x10630) 8701 #define CMIC_TIMESYNC_INTERRUPT_CLR_OFFSET (0x1091c) 8702 #define CMIC_TIMESYNC_INTERRUPT_ENABLE_OFFSET (0x10914) 8703 #define CMIC_TIMESYNC_INTERRUPT_STATUS_OFFSET (0x10918) 8704 #define CMIC_TIMESYNC_SYNCE_CLK1_COUNT_CTRL_OFFSET (0x106e8) 8705 #define CMIC_TIMESYNC_SYNCE_CLK2_COUNT_CTRL_OFFSET (0x106ec) 8706 #define CMIC_TIMESYNC_SYNCE_CLK3_COUNT_CTRL_OFFSET (0x106f0) 8707 #define CMIC_TIMESYNC_SYNCE_CLK4_COUNT_CTRL_OFFSET (0x106f4) 8708 #define CMIC_TIMESYNC_SYNCE_CLK5_COUNT_CTRL_OFFSET (0x106f8) 8709 #define CMIC_TIMESYNC_TIME_CAPTURE_CONTROL_OFFSET (0x10908) 8710 #define CMIC_TIMESYNC_TIME_CAPTURE_MODE_OFFSET (0x10624) 8711 #define CMIC_TIMESYNC_TM_OFFSET (0x10920) 8712 #define CMIC_TIMESYNC_TS0_COUNTER_ENABLE_OFFSET (0x10604) 8713 #define CMIC_TIMESYNC_TS0_FREQ_CTRL_FRAC_OFFSET (0x10608) 8714 #define CMIC_TIMESYNC_TS0_FREQ_CTRL_LOWER_OFFSET (0x1060c) 8715 #define CMIC_TIMESYNC_TS0_FREQ_CTRL_UPPER_OFFSET (0x10610) 8716 #define CMIC_TIMESYNC_TS1_COUNTER_ENABLE_OFFSET (0x10614) 8717 #define CMIC_TIMESYNC_TS1_FREQ_CTRL_FRAC_OFFSET (0x10618) 8718 #define CMIC_TIMESYNC_TS1_FREQ_CTRL_LOWER_OFFSET (0x1061c) 8719 #define CMIC_TIMESYNC_TS1_FREQ_CTRL_UPPER_OFFSET (0x10620) 8720 #define CMIC_TS_CAPTURE_STATUS_OFFSET (0x10414) 8721 #define CMIC_TS_CAPTURE_STATUS_CLR_OFFSET (0x10418) 8722 #define CMIC_TS_FIFO_STATUS_OFFSET (0x1041c) 8723 #define CMIC_TS_FREQ_CTRL_LOWER_OFFSET (0x10400) 8724 #define CMIC_TS_FREQ_CTRL_UPPER_OFFSET (0x10404) 8725 #define CMIC_TS_GPIO_1_CTRL_OFFSET (0x10420) 8726 #define CMIC_TS_GPIO_1_DOWN_EVENT_CTRL_OFFSET (0x10428) 8727 #define CMIC_TS_GPIO_1_OUTPUT_ENABLE_OFFSET (0x10478) 8728 #define CMIC_TS_GPIO_1_PHASE_ADJUST_OFFSET (0x1047c) 8729 #define CMIC_TS_GPIO_1_UP_EVENT_CTRL_OFFSET (0x10424) 8730 #define CMIC_TS_GPIO_2_CTRL_OFFSET (0x1042c) 8731 #define CMIC_TS_GPIO_2_DOWN_EVENT_CTRL_OFFSET (0x10434) 8732 #define CMIC_TS_GPIO_2_OUTPUT_ENABLE_OFFSET (0x10480) 8733 #define CMIC_TS_GPIO_2_PHASE_ADJUST_OFFSET (0x10484) 8734 #define CMIC_TS_GPIO_2_UP_EVENT_CTRL_OFFSET (0x10430) 8735 #define CMIC_TS_GPIO_3_CTRL_OFFSET (0x10438) 8736 #define CMIC_TS_GPIO_3_DOWN_EVENT_CTRL_OFFSET (0x10440) 8737 #define CMIC_TS_GPIO_3_OUTPUT_ENABLE_OFFSET (0x10488) 8738 #define CMIC_TS_GPIO_3_PHASE_ADJUST_OFFSET (0x1048c) 8739 #define CMIC_TS_GPIO_3_UP_EVENT_CTRL_OFFSET (0x1043c) 8740 #define CMIC_TS_GPIO_4_CTRL_OFFSET (0x10444) 8741 #define CMIC_TS_GPIO_4_DOWN_EVENT_CTRL_OFFSET (0x1044c) 8742 #define CMIC_TS_GPIO_4_OUTPUT_ENABLE_OFFSET (0x10490) 8743 #define CMIC_TS_GPIO_4_PHASE_ADJUST_OFFSET (0x10494) 8744 #define CMIC_TS_GPIO_4_UP_EVENT_CTRL_OFFSET (0x10448) 8745 #define CMIC_TS_GPIO_5_CTRL_OFFSET (0x10450) 8746 #define CMIC_TS_GPIO_5_DOWN_EVENT_CTRL_OFFSET (0x10458) 8747 #define CMIC_TS_GPIO_5_OUTPUT_ENABLE_OFFSET (0x10498) 8748 #define CMIC_TS_GPIO_5_PHASE_ADJUST_OFFSET (0x1049c) 8749 #define CMIC_TS_GPIO_5_UP_EVENT_CTRL_OFFSET (0x10454) 8750 #define CMIC_TS_GPIO_6_CTRL_OFFSET (0x1045c) 8751 #define CMIC_TS_GPIO_6_DOWN_EVENT_CTRL_OFFSET (0x10464) 8752 #define CMIC_TS_GPIO_6_OUTPUT_ENABLE_OFFSET (0x104a0) 8753 #define CMIC_TS_GPIO_6_PHASE_ADJUST_OFFSET (0x104a4) 8754 #define CMIC_TS_GPIO_6_UP_EVENT_CTRL_OFFSET (0x10460) 8755 #define CMIC_TS_INPUT_TIME_FIFO_ID_OFFSET (0x10410) 8756 #define CMIC_TS_INPUT_TIME_FIFO_TS_OFFSET (0x1040c) 8757 #define CMIC_TS_L1_CLK_RECOVERED_CLK_BKUP_COUNT_CTRL_OFFSET (0x1046c) 8758 #define CMIC_TS_L1_CLK_RECOVERED_CLK_COUNT_CTRL_OFFSET (0x10468) 8759 #define CMIC_TS_LCPLL_CLK_COUNT_CTRL_OFFSET (0x10470) 8760 #define CMIC_TS_TIME_CAPTURE_CTRL_OFFSET (0x10408) 8761 #define CMIC_TXBUF_CMC0_PKT_CNT_OFFSET (0x1b010) 8762 #define CMIC_TXBUF_CMC1_PKT_CNT_OFFSET (0x1b014) 8763 #define CMIC_TXBUF_CMC2_PKT_CNT_OFFSET (0x1b018) 8764 #define CMIC_TXBUF_CONFIG_OFFSET (0x1b034) 8765 #define CMIC_TXBUF_DATABUF_MAX_FLIST_ENTRIES_OFFSET (0x1b030) 8766 #define CMIC_TXBUF_DATABUF_NUM_FREE_ENTRIES_OFFSET (0x1b028) 8767 #define CMIC_TXBUF_DATABUF_TM_0_OFFSET (0x1b044) 8768 #define CMIC_TXBUF_DATABUF_TM_1_OFFSET (0x1b048) 8769 #define CMIC_TXBUF_DEBUG_OFFSET (0x1b01c) 8770 #define CMIC_TXBUF_ECCERR_CONTROL_OFFSET (0x1b040) 8771 #define CMIC_TXBUF_IPINTF_BUF_DEPTH_OFFSET (0x1b024) 8772 #define CMIC_TXBUF_IPINTF_INTERFACE_CREDITS_OFFSET (0x1b02c) 8773 #define CMIC_TXBUF_MAX_BUF_LIMITS_OFFSET (0x1b000) 8774 #define CMIC_TXBUF_MHDRBUF_TM_0_OFFSET (0x1b04c) 8775 #define CMIC_TXBUF_MIN_BUF_LIMITS_OFFSET (0x1b004) 8776 #define CMIC_TXBUF_RPE_PKT_CNT_OFFSET (0x1b00c) 8777 #define CMIC_TXBUF_STAT_OFFSET (0x1b038) 8778 #define CMIC_TXBUF_STAT_CLR_OFFSET (0x1b03c) 8779 #define CMIC_TXBUF_TM_CONTROL_OFFSET (0x1b044) 8780 #define CMIC_TXBUF_TM_CONTROL_1_OFFSET (0x1b048) 8781 #define CMIC_UART0_CPR_OFFSET (0x30f4) 8782 #define CMIC_UART0_CTR_OFFSET (0x30fc) 8783 #define CMIC_UART0_DLH_IER_OFFSET (0x3004) 8784 #define CMIC_UART0_DMASA_OFFSET (0x30a8) 8785 #define CMIC_UART0_FAR_OFFSET (0x3070) 8786 #define CMIC_UART0_HTX_OFFSET (0x30a4) 8787 #define CMIC_UART0_IIR_FCR_OFFSET (0x3008) 8788 #define CMIC_UART0_LCR_OFFSET (0x300c) 8789 #define CMIC_UART0_LPDLH_OFFSET (0x3024) 8790 #define CMIC_UART0_LPDLL_OFFSET (0x3020) 8791 #define CMIC_UART0_LSR_OFFSET (0x3014) 8792 #define CMIC_UART0_MCR_OFFSET (0x3010) 8793 #define CMIC_UART0_MSR_OFFSET (0x3018) 8794 #define CMIC_UART0_RBR_THR_DLL_OFFSET (0x3000) 8795 #define CMIC_UART0_RFL_OFFSET (0x3084) 8796 #define CMIC_UART0_RFW_OFFSET (0x3078) 8797 #define CMIC_UART0_SBCR_OFFSET (0x3090) 8798 #define CMIC_UART0_SCR_OFFSET (0x301c) 8799 #define CMIC_UART0_SDMAM_OFFSET (0x3094) 8800 #define CMIC_UART0_SFE_OFFSET (0x3098) 8801 #define CMIC_UART0_SRBR_STHR_OFFSET (0x3030) 8802 #define CMIC_UART0_SRR_OFFSET (0x3088) 8803 #define CMIC_UART0_SRT_OFFSET (0x309c) 8804 #define CMIC_UART0_SRTS_OFFSET (0x308c) 8805 #define CMIC_UART0_STET_OFFSET (0x30a0) 8806 #define CMIC_UART0_TFL_OFFSET (0x3080) 8807 #define CMIC_UART0_TFR_OFFSET (0x3074) 8808 #define CMIC_UART0_UCV_OFFSET (0x30f8) 8809 #define CMIC_UART0_USR_OFFSET (0x307c) 8810 #define CMIC_UART1_CPR_OFFSET (0x40f4) 8811 #define CMIC_UART1_CTR_OFFSET (0x40fc) 8812 #define CMIC_UART1_DLH_IER_OFFSET (0x4004) 8813 #define CMIC_UART1_DMASA_OFFSET (0x40a8) 8814 #define CMIC_UART1_FAR_OFFSET (0x4070) 8815 #define CMIC_UART1_HTX_OFFSET (0x40a4) 8816 #define CMIC_UART1_IIR_FCR_OFFSET (0x4008) 8817 #define CMIC_UART1_LCR_OFFSET (0x400c) 8818 #define CMIC_UART1_LPDLH_OFFSET (0x4024) 8819 #define CMIC_UART1_LPDLL_OFFSET (0x4020) 8820 #define CMIC_UART1_LSR_OFFSET (0x4014) 8821 #define CMIC_UART1_MCR_OFFSET (0x4010) 8822 #define CMIC_UART1_MSR_OFFSET (0x4018) 8823 #define CMIC_UART1_RBR_THR_DLL_OFFSET (0x4000) 8824 #define CMIC_UART1_RFL_OFFSET (0x4084) 8825 #define CMIC_UART1_RFW_OFFSET (0x4078) 8826 #define CMIC_UART1_SBCR_OFFSET (0x4090) 8827 #define CMIC_UART1_SCR_OFFSET (0x401c) 8828 #define CMIC_UART1_SDMAM_OFFSET (0x4094) 8829 #define CMIC_UART1_SFE_OFFSET (0x4098) 8830 #define CMIC_UART1_SRBR_STHR_OFFSET (0x4030) 8831 #define CMIC_UART1_SRR_OFFSET (0x4088) 8832 #define CMIC_UART1_SRT_OFFSET (0x409c) 8833 #define CMIC_UART1_SRTS_OFFSET (0x408c) 8834 #define CMIC_UART1_STET_OFFSET (0x40a0) 8835 #define CMIC_UART1_TFL_OFFSET (0x4080) 8836 #define CMIC_UART1_TFR_OFFSET (0x4074) 8837 #define CMIC_UART1_UCV_OFFSET (0x40f8) 8838 #define CMIC_UART1_USR_OFFSET (0x407c) 8839 #define CMIC_UC0_CONFIG_OFFSET (0x1020c) 8840 #define CMIC_UC1_CONFIG_OFFSET (0x10210) 8841 #define CMIC_V3_MIIM_BUS_SEL_MAP_127_120_OFFSET (0x111c4) 8842 #define DMA_MCS_BUF_MEM_CONTROL_OFFSET (0x1026c) 8843 #define DMA_PCIE_BUF_MEM_CONTROL_OFFSET (0x10268) 8844 #define MSPI_CDRAM_00_OFFSET (0x1640) 8845 #define MSPI_CDRAM_01_OFFSET (0x1644) 8846 #define MSPI_CDRAM_02_OFFSET (0x1648) 8847 #define MSPI_CDRAM_03_OFFSET (0x164c) 8848 #define MSPI_CDRAM_04_OFFSET (0x1650) 8849 #define MSPI_CDRAM_05_OFFSET (0x1654) 8850 #define MSPI_CDRAM_06_OFFSET (0x1658) 8851 #define MSPI_CDRAM_07_OFFSET (0x165c) 8852 #define MSPI_CDRAM_08_OFFSET (0x1660) 8853 #define MSPI_CDRAM_09_OFFSET (0x1664) 8854 #define MSPI_CDRAM_10_OFFSET (0x1668) 8855 #define MSPI_CDRAM_11_OFFSET (0x166c) 8856 #define MSPI_CDRAM_12_OFFSET (0x1670) 8857 #define MSPI_CDRAM_13_OFFSET (0x1674) 8858 #define MSPI_CDRAM_14_OFFSET (0x1678) 8859 #define MSPI_CDRAM_15_OFFSET (0x167c) 8860 #define MSPI_CPTQP_OFFSET (0x1524) 8861 #define MSPI_ENDQP_OFFSET (0x1514) 8862 #define MSPI_NEWQP_OFFSET (0x1510) 8863 #define MSPI_RXRAM_00_OFFSET (0x15c0) 8864 #define MSPI_RXRAM_01_OFFSET (0x15c4) 8865 #define MSPI_RXRAM_02_OFFSET (0x15c8) 8866 #define MSPI_RXRAM_03_OFFSET (0x15cc) 8867 #define MSPI_RXRAM_04_OFFSET (0x15d0) 8868 #define MSPI_RXRAM_05_OFFSET (0x15d4) 8869 #define MSPI_RXRAM_06_OFFSET (0x15d8) 8870 #define MSPI_RXRAM_07_OFFSET (0x15dc) 8871 #define MSPI_RXRAM_08_OFFSET (0x15e0) 8872 #define MSPI_RXRAM_09_OFFSET (0x15e4) 8873 #define MSPI_RXRAM_10_OFFSET (0x15e8) 8874 #define MSPI_RXRAM_11_OFFSET (0x15ec) 8875 #define MSPI_RXRAM_12_OFFSET (0x15f0) 8876 #define MSPI_RXRAM_13_OFFSET (0x15f4) 8877 #define MSPI_RXRAM_14_OFFSET (0x15f8) 8878 #define MSPI_RXRAM_15_OFFSET (0x15fc) 8879 #define MSPI_RXRAM_16_OFFSET (0x1600) 8880 #define MSPI_RXRAM_17_OFFSET (0x1604) 8881 #define MSPI_RXRAM_18_OFFSET (0x1608) 8882 #define MSPI_RXRAM_19_OFFSET (0x160c) 8883 #define MSPI_RXRAM_20_OFFSET (0x1610) 8884 #define MSPI_RXRAM_21_OFFSET (0x1614) 8885 #define MSPI_RXRAM_22_OFFSET (0x1618) 8886 #define MSPI_RXRAM_23_OFFSET (0x161c) 8887 #define MSPI_RXRAM_24_OFFSET (0x1620) 8888 #define MSPI_RXRAM_25_OFFSET (0x1624) 8889 #define MSPI_RXRAM_26_OFFSET (0x1628) 8890 #define MSPI_RXRAM_27_OFFSET (0x162c) 8891 #define MSPI_RXRAM_28_OFFSET (0x1630) 8892 #define MSPI_RXRAM_29_OFFSET (0x1634) 8893 #define MSPI_RXRAM_30_OFFSET (0x1638) 8894 #define MSPI_RXRAM_31_OFFSET (0x163c) 8895 #define MSPI_SPCR0_LSB_OFFSET (0x1500) 8896 #define MSPI_SPCR0_MSB_OFFSET (0x1504) 8897 #define MSPI_SPCR1_LSB_OFFSET (0x1508) 8898 #define MSPI_SPCR1_MSB_OFFSET (0x150c) 8899 #define MSPI_SPCR2_OFFSET (0x1518) 8900 #define MSPI_STATUS_OFFSET (0x1520) 8901 #define MSPI_TXRAM_00_OFFSET (0x1540) 8902 #define MSPI_TXRAM_01_OFFSET (0x1544) 8903 #define MSPI_TXRAM_02_OFFSET (0x1548) 8904 #define MSPI_TXRAM_03_OFFSET (0x154c) 8905 #define MSPI_TXRAM_04_OFFSET (0x1550) 8906 #define MSPI_TXRAM_05_OFFSET (0x1554) 8907 #define MSPI_TXRAM_06_OFFSET (0x1558) 8908 #define MSPI_TXRAM_07_OFFSET (0x155c) 8909 #define MSPI_TXRAM_08_OFFSET (0x1560) 8910 #define MSPI_TXRAM_09_OFFSET (0x1564) 8911 #define MSPI_TXRAM_10_OFFSET (0x1568) 8912 #define MSPI_TXRAM_11_OFFSET (0x156c) 8913 #define MSPI_TXRAM_12_OFFSET (0x1570) 8914 #define MSPI_TXRAM_13_OFFSET (0x1574) 8915 #define MSPI_TXRAM_14_OFFSET (0x1578) 8916 #define MSPI_TXRAM_15_OFFSET (0x157c) 8917 #define MSPI_TXRAM_16_OFFSET (0x1580) 8918 #define MSPI_TXRAM_17_OFFSET (0x1584) 8919 #define MSPI_TXRAM_18_OFFSET (0x1588) 8920 #define MSPI_TXRAM_19_OFFSET (0x158c) 8921 #define MSPI_TXRAM_20_OFFSET (0x1590) 8922 #define MSPI_TXRAM_21_OFFSET (0x1594) 8923 #define MSPI_TXRAM_22_OFFSET (0x1598) 8924 #define MSPI_TXRAM_23_OFFSET (0x159c) 8925 #define MSPI_TXRAM_24_OFFSET (0x15a0) 8926 #define MSPI_TXRAM_25_OFFSET (0x15a4) 8927 #define MSPI_TXRAM_26_OFFSET (0x15a8) 8928 #define MSPI_TXRAM_27_OFFSET (0x15ac) 8929 #define MSPI_TXRAM_28_OFFSET (0x15b0) 8930 #define MSPI_TXRAM_29_OFFSET (0x15b4) 8931 #define MSPI_TXRAM_30_OFFSET (0x15b8) 8932 #define MSPI_TXRAM_31_OFFSET (0x15bc) 8933 #define PCIE_ADDR_MSB_63_TO_32_OFFSET (0x10270) 8934 #define PCIE_RST_CONTROL_OFFSET (0x10230) 8935 #define SMBUS_TIMING_CONFIG_2_OFFSET (0xb0) 8936 #define TD2P_CMIC_TIMESYNC_TM_OFFSET (0x104b0)