maverick2.h (13504B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * File: maverick2.h 8 */ 9 10 #ifndef _SOC_MAVERICK2_H_ 11 #define _SOC_MAVERICK2_H_ 12 13 #include <soc/drv.h> 14 #include <soc/trident3.h> 15 #include <soc/maverick2_tdm.h> 16 17 /* **************** TDM-related Macors and structs adopted from Tomahawk ---start************ */ 18 /* Device port */ 19 /* 64 General device port + 1 CPU/Mng + 1 Loopback*/ 20 #define _MV2_TDM_GDEV_PORTS_PER_PIPE 64 21 #define _MV2_TDM_DEV_PORTS_PER_PIPE (_MV2_TDM_GDEV_PORTS_PER_PIPE + 2) 22 #define _MV2_TDM_DEV_PORTS_PER_DEV \ 23 (_MV2_TDM_DEV_PORTS_PER_PIPE * MAVERICK2_TDM_PIPES_PER_DEV) 24 /* MMU port */ 25 #define _MV2_TDM_MMU_PORTS_OFFSET_PER_PIPE 64 26 #define _MV2_TDM_MMU_PORTS_PER_DEV (64 * 1) 27 /* ------------------------------------------------- */ 28 #define _MV2_TDM_LENGTH 512 29 #define _MV2_PKT_SCH_LENGTH 200 30 #define _MV2_TDM_SPEED_CLASS_MAX 5 31 32 typedef struct _soc_maverick2_tdm_pblk_info_s { 33 int pblk_hpipe_num; /* half pipeline info */ 34 int pblk_cal_idx; /* index to 8 HPIPEx_PBLK_CALENDARr */ 35 }_soc_maverick2_tdm_pblk_info_t; 36 37 typedef struct _soc_maverick2_tdm_pipe_s { 38 int idb_tdm[_MV2_TDM_LENGTH]; 39 int mmu_tdm[_MV2_TDM_LENGTH]; 40 int ovs_tdm[MAVERICK2_OVS_HPIPE_COUNT_PER_PIPE][MAVERICK2_TDM_OVS_GROUPS_PER_HPIPE][MAVERICK2_TDM_OVS_GROUP_LENGTH]; 41 int pkt_shaper_tdm[MAVERICK2_OVS_HPIPE_COUNT_PER_PIPE][_MV2_PKT_SCH_LENGTH]; 42 } _soc_maverick2_tdm_pipe_t; 43 44 typedef struct _soc_maverick2_tdm_temp_s { 45 _soc_maverick2_tdm_pipe_t tdm_pipe[MAVERICK2_TDM_PIPES_PER_DEV]; 46 _soc_maverick2_tdm_pblk_info_t pblk_info[MAVERICK2_TDM_PHY_PORTS_PER_DEV]; 47 int port_ratio[MAVERICK2_TDM_PBLKS_PER_DEV]; 48 int ovs_ratio_x1000[MAVERICK2_TDM_PIPES_PER_DEV][MAVERICK2_OVS_HPIPE_COUNT_PER_PIPE]; 49 50 } _soc_maverick2_tdm_temp_t; 51 52 /* **************** TDM-related Macors and structs adopted from Tomahawk ---end************ */ 53 54 55 56 57 /********************** SER begin ******************************/ 58 /* 2 dedicated banks for L2 59 * 2 dedicated banks for L3 60 * 8 banks for UFT 61 * 8 banks for IUAT (4 16k banks + 4 8k banks) 62 * 4 banks for EUAT (4 8k banks) 63 * 64 * For L2, since there is only single wide view, the LP is only available for single wide view. 65 * For L3 and UFT/UAT banks, since they can be assigned to any logical table which supports different views, 66 * LP is available for different views - single, double and quad. 67 */ 68 69 #define SOC_MV2_NUM_BANKS_L2 2 70 #define SOC_MV2_NUM_BANKS_L3 2 71 #define SOC_MV2_NUM_BANKS_UAT_16K 4 72 73 /* Dedicated L2 LP entries per bank */ 74 #define SOC_MV2_NUM_ENTRIES_L2_LP_BANK 4096 /* 1W */ 75 /* Dedicated L3 LP entries per bank */ 76 #define SOC_MV2_NUM_ENTRIES_L3_LP_BANK 3584 /* 2048(1W) + 1024(2W) + 512(4W) */ 77 78 #define SOC_MV2_NUM_ENTRIES_UAT_16K_LP_BANK 6144 /* 4096(1W) + 2048(2W) */ 79 #define SOC_MV2_NUM_ENTRIES_UAT_8K_LP_BANK 3072 /* 2048(1W) + 1024(2W) */ 80 81 /* UFT LP entries per bank */ 82 #define SOC_MV2_NUM_ENTRIES_UFT_LP_BANK 14336 /* 8192(1W) + 4096(2W) + 2048(4W) */ 83 84 extern int soc_mv2_ser_enable_all(int unit, int enable); 85 extern void soc_mv2_ser_error(void *unit_vp, void *d1, void *d2, 86 void *d3, void *d4); 87 extern int soc_mv2_mem_ser_control(int unit, soc_mem_t mem, 88 int copyno, int enable); 89 extern void soc_mv2_ser_register(int unit); 90 91 extern void soc_mv2_ser_test_register(int unit); 92 93 extern int soc_mv2_ser_lp_mem_info_get(int unit, soc_mem_t mem, int index, 94 soc_mem_t *hash_mem, int *hash_index); 95 96 /********************* SER end *********************************/ 97 98 99 100 101 extern int soc_mv2_mmu_config_shared_buf_recalc(int unit, int res, int thdi_shd, 102 int thdo_db_shd, int thdo_qe_shd, 103 int post_update); 104 105 #define CCLK_FREQ_1700MHZ 1700 106 #define CCLK_FREQ_1525MHZ 1525 107 #define CCLK_FREQ_1012MHZ 1012 108 109 extern soc_functions_t soc_maverick2_drv_funs; 110 extern int soc_maverick2_bond_info_init(int unit); 111 extern int soc_maverick2_mem_config(int unit); 112 extern int soc_maverick2_num_cosq_init(int unit); 113 extern int soc_maverick2_num_cosq_init_port(int unit, int port); 114 extern int soc_maverick2_port_config_init(int unit, uint16 dev_id); 115 extern int soc_maverick2_chip_reset(int unit); 116 extern int soc_maverick2_port_reset(int unit); 117 118 extern int soc_mv2_port_lanes_set(int unit, int phy_port, 119 int *lanes, int *port_bandwidth); 120 121 enum soc_mv2_port_ratio_e { 122 SOC_MV2_PORT_RATIO_SINGLE, 123 SOC_MV2_PORT_RATIO_DUAL_1_1, 124 SOC_MV2_PORT_RATIO_DUAL_2_1, 125 SOC_MV2_PORT_RATIO_DUAL_1_2, 126 SOC_MV2_PORT_RATIO_TRI_023_2_1_1, 127 SOC_MV2_PORT_RATIO_TRI_023_4_1_1, 128 SOC_MV2_PORT_RATIO_TRI_012_1_1_2, 129 SOC_MV2_PORT_RATIO_TRI_012_1_1_4, 130 SOC_MV2_PORT_RATIO_QUAD, 131 SOC_MV2_PORT_RATIO_COUNT 132 }; 133 134 extern int soc_mv2_port_schedule_tdm_init(int unit, 135 soc_port_schedule_state_t *port_schedule_state); 136 extern int soc_mv2_soc_tdm_update(int unit, 137 soc_port_schedule_state_t *port_schedule_state); 138 139 #define _MV2_PORTS_PER_PBLK 4 140 #define _MV2_PBLKS_PER_PIPE 20 141 #define _MV2_PIPES_PER_DEV 1 142 #define _MV2_XPES_PER_DEV 1 143 144 #define _MV2_PBLKS_PER_DEV(unit) (_MV2_PBLKS_PER_PIPE * NUM_PIPE(unit)) 145 146 #define _MV2_PORTS_PER_PIPE (_MV2_PORTS_PER_PBLK * _MV2_PBLKS_PER_PIPE) 147 #define _MV2_PORTS_PER_DEV(unit) (_MV2_PORTS_PER_PIPE * NUM_PIPE(unit)) 148 149 #define _MV2_SECTION_SIZE 32768 150 151 #define _MV2_MMU_MAX_PACKET_BYTES 9416 /* bytes */ 152 #define _MV2_MMU_PACKET_HEADER_BYTES 64 /* bytes */ 153 #define _MV2_MMU_JUMBO_FRAME_BYTES 9216 /* bytes */ 154 #define _MV2_MMU_DEFAULT_MTU_BYTES 1536 /* bytes */ 155 156 #define _MV2_MMU_PHYSICAL_CELLS_PER_XPE 131072 /* Total Physical cells per XPE */ 157 #define _MV2_MMU_TOTAL_CELLS_PER_XPE 129024 /* 31.5MB/XPE = 129024 cells/XPE */ 158 #define _MV2_MMU_RSVD_CELLS_CFAP_PER_XPE 556 /* Reserved CFAP cells per XPE */ 159 #define _MV2_MMU_CFAP_BANK_FULL_LIMIT 2047 /* CFAP Bank Full limit */ 160 161 #define _MV2_MMU_TOTAL_CELLS (_MV2_MMU_TOTAL_CELLS_PER_XPE * _MV2_XPES_PER_DEV) 162 #define _MV2_MMU_PHYSICAL_CELLS (_MV2_MMU_PHYSICAL_CELLS_PER_XPE * _MV2_XPES_PER_DEV) 163 164 #define _MV2_MMU_BYTES_PER_CELL 256 /* bytes (2048 bits) */ 165 #define _MV2_MMU_NUM_PG 8 166 #define _MV2_MMU_NUM_POOL 4 167 #define _MV2_MMU_NUM_RQE_QUEUES 11 168 #define _MV2_MMU_NUM_INT_PRI 16 169 170 #define SOC_MV2_MMU_CFG_QGROUP_MAX 34 171 172 #define SOC_MV2_MMU_PORT_STRIDE 0x7f /* MMU Port number space per pipe */ 173 174 #define SOC_MV2_NUM_CPU_QUEUES 48 /* CPU port has 48 MC Queues */ 175 #define SOC_MV2_NUM_UC_QUEUES_PER_PIPE 650 /* (64 General Ports + 1 Management Port) * 10 */ 176 #define SOC_MV2_NUM_MC_QUEUES_PER_PIPE 698 /* (64 General Ports + 1 CPU Port/Management Port +*/ 177 /* 1 Loop-back Port) * 10 */ 178 #define SOC_MV2_CPU_MCQ_BASE 650 /* CPU port MC queue base index */ 179 #define SOC_MV2_LB_MCQ_BASE 640 /* LB ports MC queue base index */ 180 #define SOC_MV2_MGMT_UCQ_BASE 630 /* Mgmt ports UC queue base index */ 181 #define SOC_MV2_MGMT_MCQ_BASE 630 /* Mgmt ports MC queue base index */ 182 183 /* Number of Unicast Queues per Port */ 184 #define SOC_MV2_NUM_UCAST_QUEUE_PER_PORT 10 185 /* Number of Multicast Queues per Port */ 186 #define SOC_MV2_NUM_MCAST_QUEUE_PER_PORT 10 187 /* Number of Scheduler Nodes(L0) per Port */ 188 #define SOC_MV2_NUM_SCHEDULER_PER_PORT 10 189 190 #define SOC_MV2_MMU_MCQ_ENTRY_PER_XPE 24576 191 #define SOC_MV2_MMU_RQE_ENTRY_PER_XPE 2048 192 #define _MV2_MMU_RQE_ENTRY_RSVD_PER_XPE 242 /* Reserved RQE QE per XPE */ 193 194 #define _MV2_MMU_TOTAL_MCQ_ENTRY(unit) SOC_MV2_MMU_MCQ_ENTRY_PER_XPE 195 #define _MV2_MMU_TOTAL_RQE_ENTRY(unit) SOC_MV2_MMU_RQE_ENTRY_PER_XPE 196 197 #define _MV2_MMU_CFAP_BANK_FULL_LIMIT 2047 /* CFAP Bank Full limit */ 198 #define _MV2_TDM_MCQE_RSVD_OVERSHOOT 12 /* Reserved MC egress queue entry 199 for TDM overshoot */ 200 #define _MV2_MCQE_RSVD_PER_MCQ 6 /* Reserved MC egress queue entry 201 per MC queue */ 202 203 typedef struct _soc_mv2_mmu_sw_config_info_s { 204 uint32 mmu_egr_queue_min; /* For CPU and loopback port */ 205 uint32 mmu_egr_qgrp_min; 206 uint32 mmu_total_pri_groups; 207 uint32 mmu_active_pri_groups; 208 uint32 mmu_pg_min; 209 uint32 mmu_port_min; 210 uint32 mmu_mc_egr_qentry_min; 211 uint32 mmu_rqe_qentry_min; 212 uint32 mmu_rqe_queue_min; 213 int ing_shared_total; 214 int egr_shared_total; 215 } _soc_mv2_mmu_sw_config_info_t; 216 217 extern void soc_maverick2_sbus_ring_map_config(int unit); 218 219 /************ FlexPort Start ********************/ 220 #define MV2_TDM_SPEED_ADJUST(speed) \ 221 SOC_PORTCTRL_HG2_TO_IEEE_BW_GET(speed) < 10000 ? 10000 : \ 222 SOC_PORTCTRL_HG2_TO_IEEE_BW_GET(speed); 223 224 #ifdef BCM_WARM_BOOT_SUPPORT 225 extern int soc_mv2_flexport_scache_allocate(int unit); 226 extern int soc_mv2_flexport_scache_sync(int unit); 227 extern int soc_mv2_flexport_scache_recovery(int unit); 228 extern int soc_mv2_tdm_scache_allocate(int unit); 229 extern int soc_mv2_tdm_scache_sync(int unit); 230 extern int soc_mv2_tdm_scache_recovery(int unit); 231 #endif /* BCM_WARM_BOOT_SUPPORT */ 232 233 extern int soc_mv2_mmu_config_init_port(int unit, int port); 234 /************ FlexPort End ********************/ 235 236 #if !defined(BCM_MV2_ASF_EXCLUDE) 237 /* 238 ============================= 239 MV2 ASF (cut-thru forwarding) 240 ============================= 241 */ 242 #define OUT 243 #define IN_OUT 244 245 /* ASF Modes */ 246 typedef enum { 247 _SOC_MV2_ASF_MODE_SAF = 0, /* store-and-forward */ 248 _SOC_MV2_ASF_MODE_SAME_SPEED = 1, /* same speed CT */ 249 _SOC_MV2_ASF_MODE_SLOW_TO_FAST = 2, /* slow to fast CT */ 250 _SOC_MV2_ASF_MODE_FAST_TO_SLOW = 3, /* fast to slow CT */ 251 _SOC_MV2_ASF_MODE_CFG_UPDATE = 4, /* internal cfg updates */ 252 _SOC_MV2_ASF_MODE_INIT = 5, /* init */ 253 _SOC_MV2_ASF_MODE_UNSUPPORTED = 6 254 } soc_mv2_asf_mode_e; 255 256 /* ASF MMU Cell Buffer Allocation Profiles */ 257 typedef enum { 258 _SOC_MV2_ASF_MEM_PROFILE_NONE = 0, /* No cut-through support */ 259 _SOC_MV2_ASF_MEM_PROFILE_SIMILAR = 1, /* Similar Speed Alloc Profile */ 260 _SOC_MV2_ASF_MEM_PROFILE_EXTREME = 2 /* Extreme Speed Alloc Profile */ 261 } soc_mv2_asf_mem_profile_e; 262 263 /* Latency modes */ 264 typedef enum { 265 _SOC_MV2_L2_LATENCY = 0, 266 _SOC_MV2_L3_LATENCY = 1, 267 _SOC_MV2_FULL_LATENCY = 2 268 } _soc_mv2_latency_mode_e; 269 270 extern int 271 soc_mv2_asf_init_start(int unit); 272 273 extern int 274 soc_mv2_asf_init_done(int unit); 275 276 extern int 277 soc_mv2_port_asf_init( 278 int unit, 279 soc_port_t port, 280 int port_speed, 281 soc_mv2_asf_mode_e mode); 282 283 extern int 284 soc_mv2_asf_deinit(int unit); 285 286 extern int 287 soc_mv2_port_asf_xmit_start_count_set( 288 int unit, 289 soc_port_t port, 290 int port_speed, 291 soc_mv2_asf_mode_e mode, 292 uint8 extra_cells); 293 294 extern int 295 soc_mv2_port_asf_mode_get( 296 int unit, 297 soc_port_t port, 298 int port_speed, 299 OUT soc_mv2_asf_mode_e* const mode); 300 301 extern int 302 soc_mv2_port_asf_mode_set( 303 int unit, 304 soc_port_t port, 305 int port_speed, 306 soc_mv2_asf_mode_e mode); 307 308 extern int 309 soc_mv2_port_asf_params_set( 310 int unit, 311 soc_port_t port, 312 int port_speed, 313 soc_mv2_asf_mode_e mode, 314 uint8 bubble_mop_disable, 315 uint8 ca_thresh, 316 int speed_encoding); 317 318 extern int 319 soc_mv2_port_asf_speed_to_mmu_cell_credit( 320 int unit, 321 soc_port_t port, 322 int port_speed, 323 OUT uint32 *mmu_cell_credit); 324 325 extern int 326 soc_mv2_port_asf_mmu_cell_credit_to_speed( 327 int unit, 328 soc_port_t port, 329 uint8 mmu_cell_credit, 330 OUT int *port_speed); 331 332 extern pbmp_t * 333 soc_mv2_port_asf_pause_bpmp_get(int unit); 334 335 #ifdef BCM_WARM_BOOT_SUPPORT 336 extern int 337 soc_mv2_asf_wb_memsz_get( 338 int unit, 339 OUT uint32* const wb_mem_sz, 340 uint16 scache_ver); 341 342 extern int 343 soc_mv2_asf_wb_sync( 344 int unit, 345 IN_OUT uint8* const wb_data); 346 347 extern int 348 soc_mv2_asf_wb_recover( 349 int unit, 350 uint8* const wb_data, 351 uint16 scache_ver); 352 #endif 353 354 extern int 355 soc_mv2_asf_pbmp_get(int unit); 356 357 extern int 358 soc_mv2_port_asf_show( 359 int unit, 360 soc_port_t port, 361 int port_speed); 362 363 extern int 364 soc_mv2_asf_config_dump(int unit); 365 366 extern int 367 soc_mv2_port_asf_config_dump( 368 int unit, 369 soc_port_t port, 370 int port_speed); 371 372 extern int 373 soc_mv2_port_asf_detach( 374 int unit, 375 soc_port_t port); 376 #endif 377 378 extern int 379 soc_mv2_lpm_flex_ip4entry0_to_1( 380 int u, 381 void *src, 382 void *dst, 383 uint32 key_type, 384 int copy_hit); 385 386 extern int 387 soc_mv2_lpm_flex_prefix_length_get( 388 int u, 389 void *entry, 390 int *ipv6, 391 int *vrf_id, 392 int *pfx, 393 uint32 key_type); 394 extern int soc_mv2_post_mmu_init_update(int unit); 395 #endif /* !_SOC_MAVERICK2_H_ */