katana2.h (20743B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * File: katana2.h 8 */ 9 10 #ifndef _SOC_KATANA2_H_ 11 #define _SOC_KATANA2_H_ 12 13 #include <soc/drv.h> 14 #include <soc/mem.h> 15 #include <soc/error.h> 16 17 typedef struct kt2_pbmp_s { 18 soc_pbmp_t *pbmp_gport_stack; 19 soc_pbmp_t *pbmp_mxq; 20 soc_pbmp_t *pbmp_mxq1g; 21 soc_pbmp_t *pbmp_mxq2p5g; 22 soc_pbmp_t *pbmp_mxq10g; 23 soc_pbmp_t *pbmp_mxq13g; 24 soc_pbmp_t *pbmp_mxq21g; 25 soc_pbmp_t *pbmp_xport_xe; 26 soc_pbmp_t *pbmp_valid; 27 soc_pbmp_t *pbmp_pp; 28 soc_pbmp_t *pbmp_linkphy; 29 }kt2_pbmp_t; 30 31 typedef enum bcmMxqConnection_s { 32 bcmMqxConnectionUniCore=0, 33 bcmMqxConnectionWarpCore=1 34 }bcmMxqConnection_t; 35 36 typedef enum bcmMxqCorePortMode_s { 37 bcmMxqCorePortModeSingle=0, 38 bcmMxqCorePortModeDual=1, 39 bcmMxqCorePortModeQuad=2 40 }bcmMxqCorePortMode_t; 41 42 typedef enum bcmMxqPhyPortMode_s { 43 bcmMxqPhyPortModeSingle=0, 44 bcmMxqPhyPortModeDual=1, /* Suspicious */ 45 bcmMxqPhyPortModeQuad=2 46 }bcmMxqPhyPortMode_t; 47 48 enum kt2_l2_hash_key_type_e { 49 /* WARNING: values given match hardware register; do not modify */ 50 KT2_L2_HASH_KEY_TYPE_BRIDGE = 0, 51 KT2_L2_HASH_KEY_TYPE_SINGLE_CROSS_CONNECT = 1, 52 KT2_L2_HASH_KEY_TYPE_DOUBLE_CROSS_CONNECT = 2, 53 KT2_L2_HASH_KEY_TYPE_VFI = 3, 54 KT2_L2_HASH_KEY_TYPE_BFD = 4, 55 KT2_L2_HASH_KEY_TYPE_VIF = 5, 56 KT2_L2_HASH_KEY_TYPE_PE_VID = 6, 57 KT2_L2_HASH_KEY_TYPE_COUNT 58 }; 59 60 enum kt2_l3_hash_key_type_e { 61 /* WARNING: values given match hardware register; do not modify */ 62 KT2_L3_HASH_KEY_TYPE_V4UC = 0, 63 KT2_L3_HASH_KEY_TYPE_V4MC = 1, 64 KT2_L3_HASH_KEY_TYPE_V6UC = 2, 65 KT2_L3_HASH_KEY_TYPE_V6MC = 3, 66 KT2_L3_HASH_KEY_TYPE_LMEP = 4, 67 KT2_L3_HASH_KEY_TYPE_RMEP = 5, 68 /* KT2_L3_HASH_KEY_TYPE_TRILL = 6, UNSUPPORTED */ 69 KT2_L3_HASH_KEY_TYPE_COUNT 70 }; 71 72 enum kt2_vlxlt_hash_key_type_e { 73 /* WARNING: values given match hardware register; do not modify */ 74 KT2_VLXLT_HASH_KEY_TYPE_IVID_OVID = 0, 75 KT2_VLXLT_HASH_KEY_TYPE_OTAG = 1, 76 KT2_VLXLT_HASH_KEY_TYPE_ITAG = 2, 77 KT2_VLXLT_HASH_KEY_TYPE_VLAN_MAC = 3, 78 KT2_VLXLT_HASH_KEY_TYPE_OVID = 4, 79 KT2_VLXLT_HASH_KEY_TYPE_IVID = 5, 80 KT2_VLXLT_HASH_KEY_TYPE_PRI_CFI = 6, 81 KT2_VLXLT_HASH_KEY_TYPE_HPAE = 7, 82 KT2_VLXLT_HASH_KEY_TYPE_VIF = 8, 83 KT2_VLXLT_HASH_KEY_TYPE_VIF_VLAN = 9, 84 KT2_VLXLT_HASH_KEY_TYPE_VIF_CVLAN = 10, 85 KT2_VLXLT_HASH_KEY_TYPE_VIF_OTAG = 11, 86 KT2_VLXLT_HASH_KEY_TYPE_VIF_ITAG = 12, 87 KT2_VLXLT_HASH_KEY_TYPE_LLTAG_VID = 13, 88 KT2_VLXLT_HASH_KEY_TYPE_LLVID_IVID = 14, 89 KT2_VLXLT_HASH_KEY_TYPE_LLVID_OVID = 15, 90 KT2_VLXLT_HASH_KEY_TYPE_COUNT 91 }; 92 93 enum kt2_evlxlt_hash_key_type_e { 94 /* WARNING: values given match hardware register; do not modify */ 95 KT2_EVLXLT_HASH_KEY_TYPE_VLAN_XLATE = 0, 96 KT2_EVLXLT_HASH_KEY_TYPE_VLAN_XLATE_DVP = 1, 97 KT2_EVLXLT_HASH_KEY_TYPE_ISID_XLATE = 3, 98 KT2_EVLXLT_HASH_KEY_TYPE_ISID_DVP_XLATE = 4, 99 KT2_EVLXLT_HASH_KEY_TYPE_COUNT 100 }; 101 102 enum kt2_mpls_hash_key_type_e { 103 /* WARNING: values given match hardware register; do not modify */ 104 KT2_MPLS_HASH_KEY_TYPE_MPLS = 0, 105 KT2_MPLS_HASH_KEY_TYPE_MIM_NVP = 1, 106 KT2_MPLS_HASH_KEY_TYPE_MIM_ISID = 2, 107 KT2_MPLS_HASH_KEY_TYPE_MIM_ISID_SVP = 3, 108 KT2_MPLS_HASH_KEY_TYPE_COUNT 109 }; 110 111 typedef enum bcm_cosq_recalc_type_e { 112 BCM_KT2_RECALC_SHARED_INT_DECREMENT, 113 BCM_KT2_RECALC_SHARED_INT_INCREMENT, 114 BCM_KT2_RECALC_SHARED_EXT_DECREMENT, 115 BCM_KT2_RECALC_SHARED_EXT_INCREMENT 116 } bcm_kt2_cosq_recalc_type_t; 117 118 #define KT2_MAX_TDM_FREQUENCY 11 /* 80,110,155,185:80,185:90 119 205:108 205:88 205:99, 95:16, 205:88*/ 120 #define KT2_MAX_SPEEDS 7 /* 1G,2G,2.5G,10G,13G,20G,21G */ 121 122 #define KT2_MAX_MXQBLOCKS 11 123 #define KT2_MAX_MXQPORTS_PER_BLOCK 4 124 #define KT2_LPBK_PORT 41 125 #define KT2_CMIC_PORT 0 126 #define KT2_OLP_PORT 40 127 #define KT2_IDLE1 62 /* Consecutive IDLE slots */ 128 #define KT2_IDLE 63 129 /* 0:CMIC Port 1-40:Physical Ports 41:Loopback Port */ 130 #define KT2_MAX_LOGICAL_PORTS 42 131 #define KT2_MAX_PHYSICAL_PORTS 40 132 133 134 #define SOC_KT2_MIN_SUBPORT_INDEX 42 135 #define SOC_KT2_MAX_SUBPORT_INDEX 169 136 #define SOC_KT2_MAX_SUBPORTS 128 137 #define SOC_KT2_MAX_LINKPHY_SUBPORTS_PER_PORT 64 138 #define SOC_KT2_MAX_TDM_SLOTS_PER_PORT 48 139 #define SOC_KT2_MAX_STREAMS_PER_SUBPORT BCM_SUBPORT_CONFIG_MAX_STREAMS 140 141 #define SOC_KT2_SUBPORT_GROUP_MAX (128) 142 #define SOC_KT2_SUBPORT_PORT_MAX (128) 143 144 #define SOC_KT2_SUBPORT_PP_PORT_INDEX_MIN (42) 145 #define SOC_KT2_SUBPORT_PP_PORT_INDEX_MAX (\ 146 SOC_KT2_SUBPORT_PP_PORT_INDEX_MIN + SOC_KT2_SUBPORT_PORT_MAX - 1) 147 148 #define SOC_KT2_LINKPHY_TX_DATA_BUF_START_ADDR_MAX 3399 149 #define SOC_KT2_LINKPHY_TX_DATA_BUF_END_ADDR_MIN 23 150 #define SOC_KT2_LINKPHY_TX_DATA_BUF_END_ADDR_MAX 3423 151 152 #define SOC_KT2_LINKPHY_BLOCK_MAX 2 153 #define SOC_KT2_LINKPHY_BLOCK_PORT_IDX_MAX 4 154 #define SOC_KT2_MAX_LINKPHY_PORTS 8 155 156 #define SOC_KT2_LINKPHY_TX_STREAM_START_ADDR_OFFSET 0x60 157 158 #define KT2_PORT_TYPE_ETHERNET 0 159 #define KT2_PORT_TYPE_HIGIG 1 160 #define KT2_PORT_TYPE_LOOPBACK 2 161 #define KT2_PORT_TYPE_CASCADED 4 162 #define KT2_PORT_TYPE_GPON_EPON 5 163 #define KT2_CASCADED_TYPE_LINKPHY 0 164 #define KT2_CASCADED_TYPE_SUBTAG 1 165 166 typedef struct tdm_cycles_info_s { 167 uint32 worse_tdm_slot_spacing; 168 uint32 optimal_tdm_slot_spacing; 169 uint32 min_tdm_cycles; 170 }tdm_cycles_info_t; 171 172 typedef struct kt2_tdm_pos_info_s { 173 uint16 total_slots; 174 int16 pos[SOC_KT2_MAX_TDM_SLOTS_PER_PORT]; 175 } kt2_tdm_pos_info_t; 176 177 typedef struct bcm56450_tdm_info_s { 178 uint8 tdm_freq; 179 uint8 tdm_size; 180 /* Display purpose only */ 181 uint8 row; 182 uint8 col; 183 }bcm56450_tdm_info_t; 184 185 typedef struct soc_kt2_sku_config_info_s { 186 /* Config values */ 187 int config; 188 int bcm56450_cfg_offset; 189 int bcm56452_cfg_offset; 190 int bcm56454_cfg_offset; 191 int bcm56455_cfg_offset; 192 int bcm56248_cfg_offset; 193 int olp_port; 194 int xfi_0; 195 int xfi_1; 196 } soc_kt2_sku_config_info_t; 197 198 extern int flex_io_operation_busy[SOC_MAX_NUM_DEVICES]; 199 200 typedef uint32 mxqspeeds_t[KT2_MAX_MXQBLOCKS][KT2_MAX_MXQPORTS_PER_BLOCK]; 201 typedef uint32 kt2_mxqblock_ports_t[KT2_MAX_MXQBLOCKS] 202 [KT2_MAX_MXQPORTS_PER_BLOCK]; 203 204 typedef uint32 kt2_speed_t[KT2_MAX_PHYSICAL_PORTS]; 205 typedef uint32 kt2_port_to_mxqblock_t[KT2_MAX_PHYSICAL_PORTS]; 206 typedef uint32 kt2_port_to_mxqblock_subports_t[KT2_MAX_PHYSICAL_PORTS]; 207 208 209 extern uint32 kt2_current_tdm[256]; 210 extern uint32 kt2_current_tdm_size; 211 212 extern kt2_port_to_mxqblock_subports_t 213 *kt2_port_to_mxqblock_subports[SOC_MAX_NUM_DEVICES]; 214 extern kt2_tdm_pos_info_t kt2_tdm_pos_info[KT2_MAX_MXQBLOCKS]; 215 extern soc_error_t soc_katana2_reconfigure_tdm(int unit,uint32 new_tdm_size, 216 uint32 *new_tdm); 217 218 extern kt2_mxqblock_ports_t *kt2_mxqblock_ports[SOC_MAX_NUM_DEVICES]; 219 extern mxqspeeds_t *mxqspeeds[SOC_MAX_NUM_DEVICES]; 220 extern uint8 kt2_tdm_update_flag; 221 extern tdm_cycles_info_t kt2_current_tdm_cycles_info[KT2_MAX_SPEEDS]; 222 223 224 extern int _soc_kt2_config_get(int unit, soc_kt2_sku_config_info_t *conf); 225 extern int soc_flex_io_operation_status_set(int unit, int value); 226 extern int soc_kt2_vlan_xlate_base_entry_to_key(int unit, void *entry, uint8 *key); 227 extern int soc_kt2_l2x_base_entry_to_key(int unit, uint32 *entry, uint8 *key); 228 extern int soc_kt2_l3x_base_entry_to_key(int unit, uint32 *entry, uint8 *key); 229 extern int soc_kt2_egr_vlan_xlate_base_entry_to_key(int unit, void *entry, uint8 *key); 230 extern int soc_kt2_mpls_base_entry_to_key(int unit, void *entry, uint8 *key); 231 extern uint32 soc_kt2_vlan_xlate_hash(int unit, int hash_sel, int key_nbits, void *base_entry, uint8 *key); 232 extern uint32 soc_kt2_egr_vlan_xlate_hash(int unit, int hash_sel, int key_nbits, void *base_entry, uint8 *key); 233 234 extern soc_functions_t soc_katana2_drv_funs; 235 236 extern int soc_katana2_pipe_mem_clear(int unit); 237 extern int soc_katana2_linkphy_mem_clear(int unit); 238 239 240 extern int soc_kt2_ser_mem_clear(int unit, soc_mem_t mem); 241 extern void soc_kt2_ser_fail(int unit); 242 243 extern int soc_kt2_mem_config(int unit, int dev_id); 244 extern int soc_kt2_temperature_monitor_get(int unit, 245 int temperature_max, 246 soc_switch_temperature_monitor_t *temperature_array, 247 int *temperature_count); 248 extern int soc_kt2_show_ring_osc(int unit); 249 extern int soc_kt2_show_material_process(int unit); 250 extern int soc_kt2_show_voltage(int unit); 251 252 extern int soc_kt2_linkphy_port_reg_blk_idx_get( 253 int unit, int port, int blktype, int *block, int *index); 254 extern int soc_kt2_linkphy_port_blk_idx_get( 255 int unit, int port, int *block, int *index); 256 extern int soc_kt2_linkphy_get_portid(int unit, int block, int index); 257 extern void soc_katana2_pbmp_init(int unit, kt2_pbmp_t kt2_pbmp); 258 extern void soc_katana2_subport_init(int unit); 259 extern soc_error_t 260 soc_katana2_tdm_feasibility_check(int unit, soc_port_t port, int speed); 261 extern soc_error_t 262 soc_katana2_update_tdm(int unit, soc_port_t port, int speed); 263 extern soc_error_t 264 soc_katana2_get_core_port_mode( 265 int unit,soc_port_t port,bcmMxqCorePortMode_t *mode); 266 extern soc_error_t 267 soc_katana2_get_phy_port_mode( 268 int unit, soc_port_t port,int speed, bcmMxqPhyPortMode_t *mode); 269 extern soc_error_t soc_katana2_get_port_mxqblock( 270 int unit, soc_port_t port,uint8 *mxqblock); 271 extern soc_error_t soc_katana2_get_phy_connection_mode( 272 int unit,soc_port_t port,int mxqblock, bcmMxqConnection_t *connection); 273 extern soc_error_t soc_katana2_port_lanes_get( 274 int unit, soc_port_t port, int *lanes); 275 extern soc_error_t soc_katana2_port_lanes_set( 276 int unit, soc_port_t port, int lanes); 277 extern void _katana2_phy_addr_default( 278 int unit, int port, uint16 *phy_addr, uint16 *phy_addr_int); 279 extern soc_error_t soc_katana2_port_enable_set( 280 int unit, soc_port_t port, int enable); 281 extern void soc_katana2_mxqblock_reset(int unit, uint8 mxqblock,int active_low); 282 extern int _soc_katana2_mmu_reconfigure(int unit, int port); 283 extern int soc_katana2_num_cosq_init(int unit); 284 extern void soc_kt2_blk_counter_config(int unit); 285 extern soc_error_t katana2_get_wc_phy_info(int unit, 286 soc_port_t port, 287 uint8 *lane_num, 288 uint8 *phy_mode, 289 uint8 *chip_num); 290 291 /* KT2 OAM */ 292 typedef int (*soc_kt2_oam_handler_t)(int unit, soc_field_t fault_field); 293 typedef int (*soc_kt2_linkphy_handler_t) (int unit, soc_port_t port, uint32 val); 294 typedef int (*soc_kt2_oam_ser_handler_t)(int unit, soc_mem_t mem, int index); 295 extern void soc_kt2_oam_handler_register(int unit, soc_kt2_oam_handler_t handler); 296 extern void soc_kt2_linkphy_handler_register(int unit, soc_kt2_linkphy_handler_t handler); 297 extern void soc_kt2_rxlp_interrupt_process(int unit, int port, uint32 rval); 298 299 extern void soc_kt2_parity_error(void *unit_vp, void *d1, void *d2, 300 void *d3, void *d4); 301 extern void soc_kt2_oam_ser_handler_register(int unit, 302 soc_kt2_oam_ser_handler_t handler); 303 extern int soc_kt2_oam_ser_process(int unit, soc_mem_t mem, int index); 304 305 /* KT2 cosq soc functions */ 306 extern int soc_kt2_cosq_stream_mapping_set(int unit); 307 extern int soc_kt2_cosq_port_coe_linkphy_status_set(int unit, soc_port_t port, 308 int enable); 309 extern int soc_kt2_cosq_s1_range_set(int unit, soc_port_t port, 310 int start_s1, int end_s1, int type); 311 extern int soc_kt2_cosq_repl_map_set(int unit, soc_port_t port, 312 int start, int end, int enable); 313 extern int soc_kt2_cosq_lp_repl_map_set(int unit, int stream, uint32 pp_port, 314 int enable); 315 extern int soc_kt2_cosq_s0_sched_set(int unit, int hw_index, int mode); 316 /* KT2 TDM related functions */ 317 extern void kt2_tdm_display(int unit, uint32 *tdm, uint32 total_tdm_slots, 318 uint32 row, uint32 col); 319 extern void kt2_tdm_replace(uint32 *tdm, uint32 total_tdm_slots, 320 uint32 src, uint32 dst,uint32 one_time); 321 extern void kt2_tdm_swap(uint32 *tdm, uint32 total_tdm_slots, 322 uint32 src, uint32 dst); 323 324 325 /********************************************************************** 326 * MMU, COSQ related prototypes. 327 */ 328 typedef enum { 329 SOC_KT2_SCHED_MODE_UNKNOWN = 0, 330 SOC_KT2_SCHED_MODE_STRICT, 331 SOC_KT2_SCHED_MODE_WRR, 332 SOC_KT2_SCHED_MODE_WDRR 333 } soc_kt2_sched_mode_e; 334 335 typedef enum { 336 SOC_KT2_NODE_LVL_ROOT = 0, 337 SOC_KT2_NODE_LVL_L0, 338 SOC_KT2_NODE_LVL_L1, 339 SOC_KT2_NODE_LVL_L2, 340 SOC_KT2_NODE_LVL_MAX 341 } soc_kt2_node_lvl_e; 342 343 typedef enum { 344 _SOC_KT2_COSQ_NODE_LVL_ROOT = 0, 345 _SOC_KT2_COSQ_NODE_LVL_S0, 346 _SOC_KT2_COSQ_NODE_LVL_S1, 347 _SOC_KT2_COSQ_NODE_LVL_L0, 348 _SOC_KT2_COSQ_NODE_LVL_L1, 349 _SOC_KT2_COSQ_NODE_LVL_L2, 350 _SOC_KT2_COSQ_NODE_LVL_MAX 351 } soc_kt2_cosq_node_lvl_e; 352 353 typedef enum soc_kt2_drop_limit_alpha_value_e { 354 SOC_KT2_COSQ_DROP_LIMIT_ALPHA_1_64, /* Use 1/64 as the alpha value for 355 dynamic threshold */ 356 SOC_KT2_COSQ_DROP_LIMIT_ALPHA_1_32, /* Use 1/32 as the alpha value for 357 dynamic threshold */ 358 SOC_KT2_COSQ_DROP_LIMIT_ALPHA_1_16, /* Use 1/16 as the alpha value for 359 dynamic threshold */ 360 SOC_KT2_COSQ_DROP_LIMIT_ALPHA_1_8, /* Use 1/8 as the alpha value for 361 dynamic threshold */ 362 SOC_KT2_COSQ_DROP_LIMIT_ALPHA_1_4, /* Use 1/4 as the alpha value for 363 dynamic threshold */ 364 SOC_KT2_COSQ_DROP_LIMIT_ALPHA_1_2, /* Use 1/2 as the alpha value for 365 dynamic threshold */ 366 SOC_KT2_COSQ_DROP_LIMIT_ALPHA_1, /* Use 1 as the alpha value for dynamic 367 threshold */ 368 SOC_KT2_COSQ_DROP_LIMIT_ALPHA_2, /* Use 2 as the alpha value for dynamic 369 threshold */ 370 SOC_KT2_COSQ_DROP_LIMIT_ALPHA_4, /* Use 4 as the alpha value for dynamic 371 threshold */ 372 SOC_KT2_COSQ_DROP_LIMIT_ALPHA_8, /* Use 8 as the alpha value for dynamic 373 threshold */ 374 SOC_KT2_COSQ_DROP_LIMIT_ALPHA_COUNT /* Must be the last entry! */ 375 } soc_kt2_drop_limit_alpha_value_t; 376 377 /* Worst case time = 256k * 768 * 8 @ 1Gbps = 1.6 sec */ 378 #define _SOC_COSQ_QUEUE_FLUSH_TIMEOUT_PACKING_DEFAULT 5900000 379 380 /* Worst case time = 256k * 2880 *8 @ 1Gbps = 5.9 sec */ 381 #define _SOC_COSQ_QUEUE_FLUSH_TIMEOUT_DEFAULT 1600000 382 #define _SOC_KT2_NODE_CONFIG_MEM(n) \ 383 (((n)==SOC_KT2_NODE_LVL_ROOT) ? LLS_PORT_CONFIGm : \ 384 (((n) == SOC_KT2_NODE_LVL_L0) ? LLS_L0_CONFIGm : \ 385 ((n) == SOC_KT2_NODE_LVL_L1 ? LLS_L1_CONFIGm : -1 ))) 386 #define _SOC_KT2_NODE_CONFIG_LINKPHY_MEM(n) \ 387 (((n)==_SOC_KT2_COSQ_NODE_LVL_ROOT) ? LLS_PORT_CONFIGm : \ 388 (((n) == _SOC_KT2_COSQ_NODE_LVL_S0) ? LLS_L0_CONFIGm : \ 389 (((n) == _SOC_KT2_COSQ_NODE_LVL_S1) ? LLS_S1_CONFIGm : \ 390 (((n) == _SOC_KT2_COSQ_NODE_LVL_L0) ? LLS_L0_CONFIGm : \ 391 ((n) == _SOC_KT2_COSQ_NODE_LVL_L1 ? LLS_L1_CONFIGm : -1 ))))) 392 393 394 #define _SOC_KT2_NODE_PARENT_MEM(n) \ 395 (((n)==SOC_KT2_NODE_LVL_L2) ? LLS_L2_PARENTm : \ 396 (((n) == SOC_KT2_NODE_LVL_L1) ? LLS_L1_PARENTm : \ 397 (((n) == SOC_KT2_NODE_LVL_L0) ? LLS_L0_PARENTm : -1 ))) 398 399 #define _SOC_KT2_NODE_WIEGHT_MEM(n) \ 400 (((n)==SOC_KT2_NODE_LVL_L0) ? LLS_L0_CHILD_WEIGHT_CFG_CNTm : \ 401 (((n) == SOC_KT2_NODE_LVL_L1) ? LLS_L1_CHILD_WEIGHT_CFG_CNTm : \ 402 (((n) == SOC_KT2_NODE_LVL_L2) ? LLS_L2_CHILD_WEIGHT_CFG_CNTm : -1 ))) 403 404 #define _SOC_KT2_NODE_WIEGHT_LINKPHY_MEM(n) \ 405 (((n)==_SOC_KT2_COSQ_NODE_LVL_S0) ? LLS_L0_CHILD_WEIGHT_CFG_CNTm : \ 406 (((n)==_SOC_KT2_COSQ_NODE_LVL_S1) ? LLS_L0_CHILD_WEIGHT_CFG_CNTm : \ 407 (((n)==_SOC_KT2_COSQ_NODE_LVL_L0) ? LLS_L0_CHILD_WEIGHT_CFG_CNTm : \ 408 (((n) == _SOC_KT2_COSQ_NODE_LVL_L1) ? LLS_L1_CHILD_WEIGHT_CFG_CNTm : \ 409 (((n) == _SOC_KT2_COSQ_NODE_LVL_L2) ? LLS_L2_CHILD_WEIGHT_CFG_CNTm : -1 ))))) 410 411 #define _SOC_IS_PP_PORT_LINKPHY_SUBTAG(unit, port) \ 412 (SOC_PBMP_MEMBER(SOC_INFO(unit).linkphy_pp_port_pbm, port) || \ 413 SOC_PBMP_MEMBER(SOC_INFO(unit).subtag_pp_port_pbm, port)) 414 415 #define _SOC_IS_PORT_LINKPHY_SUBTAG(unit, port) \ 416 (SOC_PBMP_MEMBER(SOC_INFO(unit).linkphy_allowed_pbm, port) || \ 417 SOC_PBMP_MEMBER(SOC_INFO(unit).subtag_allowed_pbm, port)) 418 419 extern int soc_kt2_dump_port_lls(int unit, int port, int subport); 420 extern int _soc_katana2_get_cfg_num(int unit, int *new_cfg_num); 421 extern int _soc_katana2_flexio_scache_allocate(int unit); 422 extern int _soc_katana2_flexio_scache_retrieve(int unit); 423 extern int _soc_katana2_flexio_scache_sync(int unit); 424 extern int soc_kt2_l3_defip_index_map(int unit, soc_mem_t mem, int index); 425 extern int soc_kt2_l3_defip_index_remap(int unit, soc_mem_t mem, int index); 426 extern int soc_kt2_l3_defip_mem_index_get(int unit, int pindex, soc_mem_t *mem); 427 extern int _soc_katana2_mem_parity_control(int unit, soc_mem_t mem, int copyno, int enable); 428 #if defined(SER_TR_TEST_SUPPORT) 429 extern int soc_katana2_ser_inject_error(int unit, uint32 flags, soc_mem_t mem, int pipe_target, int block, int index); 430 extern int _soc_katana2_mem_nack_error_test(int unit, _soc_ser_test_t test_type, int *test_errors); 431 extern int soc_katana2_ser_mem_test(int unit, soc_mem_t mem, _soc_ser_test_t test_type, int cmd); 432 extern int soc_katana2_ser_test(int unit, _soc_ser_test_t test_type); 433 extern soc_error_t soc_katana2_ser_error_injection_support(int unit, soc_mem_t mem, int pipe); 434 #endif 435 extern int soc_kt2_lls_bmap_alloc(int unit); 436 extern int soc_kt2_cosq_max_bucket_set(int unit, int port, 437 int index, uint32 level); 438 extern int soc_kt2_cosq_min_bucket_set(int unit, int port, 439 int index, uint32 level); 440 extern int soc_kt2_cosq_min_clear(int unit, int port, 441 int index, uint32 level); 442 extern int 443 _soc_kt2_cosq_min_bucket_get(int unit, int port, int index, int lvl, 444 uint32 *min, uint32 *matissa, 445 uint32 *exp, uint32 *cycle); 446 extern int _soc_kt2_cosq_begin_port_flush(int unit, int port, 447 int hw_index); 448 extern int _soc_kt2_cosq_end_port_flush(int unit, 449 int hw_index); 450 extern int soc_kt2_cosq_queue_enable(int unit, 451 int hw_index, int enable); 452 extern int 453 soc_kt2_mmu_config_shared_buf_recalc(int unit, int delta_size, bcm_kt2_cosq_recalc_type_t recalc_type); 454 455 extern int soc_kt2_mmu_get_shared_size(int unit, int *shared_size, int *shared_size_external); 456 extern int 457 soc_kt2_sched_get_node_config(int unit, soc_port_t port, int level, int index, 458 int *pnum_spri, int *pfirst_child, 459 int *pfirst_mc_child, uint32 *pucmap, 460 uint32 *pspmap); 461 extern int 462 soc_kt2_cosq_get_sched_mode(int unit, soc_port_t port, int level, int index, 463 soc_kt2_sched_mode_e *pmode, int *weight); 464 extern int 465 soc_kt2_cosq_s0_sched_get(int unit, int hw_index, soc_kt2_sched_mode_e *mode); 466 extern int 467 soc_kt2_cosq_two_s1s_in_s0_config_set(int unit, soc_port_t port, int enable); 468 extern uint32 469 soc_kt2_cosq_two_s1s_in_s0_config_get(int unit, soc_port_t port); 470 extern void soc_kt2_xport_type_update(int unit, soc_port_t port, int mode); 471 extern int 472 _bcm_kt2_is_pp_port_linkphy_subtag(int unit, int pp_port); 473 extern int 474 _soc_katana2_perq_flex_counters_init(int unit, uint32 drop_mask); 475 extern int 476 _soc_kt2_dfc_status_clear(int unit, int port, int stream_id); 477 extern int 478 soc_kt2_get_max_buffer_size(int unit, int external, int value); 479 #endif /* !_SOC_KATANA2_H_ */