ism.h (12026B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * ISM management routines 8 */ 9 10 #ifndef _SOC_ISM_H 11 #define _SOC_ISM_H 12 13 #include <shared/bitop.h> 14 #include <soc/types.h> 15 #include <soc/mem.h> 16 17 #ifdef BCM_ISM_SUPPORT 18 19 #define _ISM_BANK_SIZE_HALF 1 20 #define _ISM_BANK_SIZE_QUARTER 2 21 #define _ISM_BANK_SIZE_DISABLED 3 22 23 #define _ISM_SIZE_MODE_512 0 24 #define _ISM_SIZE_MODE_256 1 25 #define _ISM_SIZE_MODE_176 2 26 #define _ISM_SIZE_MODE_96 3 27 #define _ISM_SIZE_MODE_80 4 28 #define _ISM_SIZE_MODE_64 5 29 30 #define _CRITERIA_ENTRY 0 31 #define _CRITERIA_STAGE 1 32 #define _CRITERIA_BANK 2 33 34 typedef struct { 35 uint8 entry; 36 uint8 stage; 37 uint8 bank; 38 int8 mode; 39 uint32 index; 40 uint8 bidx; 41 } _soc_ism_sbo_t; 42 43 typedef enum soc_ism_mem_type_e { 44 SOC_ISM_MEM_VLAN_XLATE = 1, 45 SOC_ISM_MEM_L2_ENTRY, 46 SOC_ISM_MEM_L3_ENTRY, 47 SOC_ISM_MEM_EP_VLAN_XLATE, 48 SOC_ISM_MEM_MPLS, 49 SOC_ISM_MEM_ESM_L2, 50 SOC_ISM_MEM_ESM_L3, 51 SOC_ISM_MEM_ESM_ACL, 52 SOC_ISM_MEM_MAX = SOC_ISM_MEM_ESM_L2, 53 SOC_ISM_MEM_TOTAL = SOC_ISM_MEM_ESM_ACL 54 } soc_ism_mem_type_t; 55 56 typedef enum soc_mem_set_type_e { 57 SOC_MEM_SET_VLAN_XLATE = SOC_ISM_MEM_VLAN_XLATE, 58 SOC_MEM_SET_L2_ENTRY = SOC_ISM_MEM_L2_ENTRY, 59 SOC_MEM_SET_L3_ENTRY = SOC_ISM_MEM_L3_ENTRY, 60 SOC_MEM_SET_EP_VLAN_XLATE = SOC_ISM_MEM_EP_VLAN_XLATE, 61 SOC_MEM_SET_MPLS = SOC_ISM_MEM_MPLS, 62 SOC_MEM_SET_MAX = SOC_MEM_SET_MPLS 63 } soc_mem_set_type_t; 64 65 /* VLAN_XLATE/VLAN_MAC, L2_ENTRY, L3_ENTRY, EP_VLAN_XLATE, MPLS */ 66 #define _SOC_ISM_ENTRY_SIZE_QUANTA 1024 67 #define _SOC_ISM_ENTRIES_PER_BKT 4 68 #define _SOC_ISM_MAX_TABLES 5 69 #define _SOC_ISM_MAX_STAGES 4 70 #define _SOC_ISM_BANKS_PER_STAGE 5 71 #define _SOC_ISM_MAX_BANKS 20 72 #define _SOC_ISM_TOTAL_BANKS 64 73 #define _SOC_ISM_MAX_RAW_BANKS 8 74 #define _SOC_ISM_MAX_ISM_MEMS 10 75 #define _SOC_ISM_ENTRY_BITS 108 76 77 #define _SOC_ISM_BANKS_PER_STAGE_176 4 78 #define _SOC_ISM_BANKS_PER_STAGE_96 4 79 #define _SOC_ISM_BANKS_PER_STAGE_80 4 80 #define _SOC_ISM_MAX_BANKS_176 16 81 #define _SOC_ISM_MAX_BANKS_96 16 82 #define _SOC_ISM_MAX_BANKS_80 16 83 #define _SOC_ISM_TOTAL_BANKS_176 44 84 #define _SOC_ISM_TOTAL_BANKS_96 24 85 #define _SOC_ISM_TOTAL_BANKS_80 20 86 87 #define _SOC_ISM_BANK0_START 0 88 #define _SOC_ISM_BANK0_SIZE (1024*16) 89 #define _SOC_ISM_BANK1_START (_SOC_ISM_BANK0_START + _SOC_ISM_BANK0_SIZE) 90 #define _SOC_ISM_BANK1_SIZE (1024*8) 91 #define _SOC_ISM_BANK2_START (_SOC_ISM_BANK1_START + _SOC_ISM_BANK1_SIZE ) 92 #define _SOC_ISM_BANK2_SIZE (1024*4) 93 #define _SOC_ISM_BANK3_START (_SOC_ISM_BANK2_START + _SOC_ISM_BANK2_SIZE) 94 #define _SOC_ISM_BANK3_SIZE (1024*2) 95 #define _SOC_ISM_BANK4_START (_SOC_ISM_BANK3_START + _SOC_ISM_BANK3_SIZE) 96 #define _SOC_ISM_BANK4_SIZE (1024*2) 97 #define _SOC_ISM_STAGE_SIZE (_SOC_ISM_BANK4_START + _SOC_ISM_BANK4_SIZE) 98 #define _SOC_ISM_SIZE (_SOC_ISM_BANK0_SIZE + _SOC_ISM_BANK1_SIZE + \ 99 _SOC_ISM_BANK2_SIZE + _SOC_ISM_BANK3_SIZE + \ 100 _SOC_ISM_BANK4_SIZE) * _SOC_ISM_MAX_STAGES 101 102 #define _SOC_ISM_256_BANK0_START 0 103 #define _SOC_ISM_256_BANK0_SIZE (1024*8) 104 #define _SOC_ISM_256_BANK1_START (_SOC_ISM_256_BANK0_START + _SOC_ISM_256_BANK0_SIZE) 105 #define _SOC_ISM_256_BANK1_SIZE (1024*4) 106 #define _SOC_ISM_256_BANK2_START (_SOC_ISM_256_BANK1_START + _SOC_ISM_256_BANK1_SIZE ) 107 #define _SOC_ISM_256_BANK2_SIZE (1024*2) 108 #define _SOC_ISM_256_BANK3_START (_SOC_ISM_256_BANK2_START + _SOC_ISM_256_BANK2_SIZE) 109 #define _SOC_ISM_256_BANK3_SIZE (1024*1) 110 #define _SOC_ISM_256_BANK4_START (_SOC_ISM_256_BANK3_START + _SOC_ISM_256_BANK3_SIZE) 111 #define _SOC_ISM_256_BANK4_SIZE (1024*1) 112 #define _SOC_ISM_256_STAGE_SIZE (_SOC_ISM_256_BANK4_START + _SOC_ISM_256_BANK4_SIZE) 113 #define _SOC_ISM_256_SIZE (_SOC_ISM_256_BANK0_SIZE + _SOC_ISM_256_BANK1_SIZE + \ 114 _SOC_ISM_256_BANK2_SIZE + _SOC_ISM_256_BANK3_SIZE + \ 115 _SOC_ISM_256_BANK4_SIZE) * _SOC_ISM_MAX_STAGES 116 117 #define _SOC_ISM_256_176_BANK0_START 0 118 #define _SOC_ISM_256_176_BANK0_SIZE (1024*4) 119 #define _SOC_ISM_256_176_BANK1_START (_SOC_ISM_256_176_BANK0_START + _SOC_ISM_256_176_BANK0_SIZE) 120 #define _SOC_ISM_256_176_BANK1_SIZE (1024*4) 121 #define _SOC_ISM_256_176_BANK2_START (_SOC_ISM_256_176_BANK1_START + _SOC_ISM_256_176_BANK1_SIZE ) 122 #define _SOC_ISM_256_176_BANK2_SIZE (1024*2) 123 #define _SOC_ISM_256_176_BANK3_START (_SOC_ISM_256_176_BANK2_START + _SOC_ISM_256_176_BANK2_SIZE) 124 #define _SOC_ISM_256_176_BANK3_SIZE (1024*1) 125 #define _SOC_ISM_256_176_STAGE_SIZE (_SOC_ISM_256_176_BANK3_START + _SOC_ISM_256_176_BANK3_SIZE) 126 #define _SOC_ISM_256_176_SIZE (_SOC_ISM_256_176_BANK0_SIZE + _SOC_ISM_256_176_BANK1_SIZE + \ 127 _SOC_ISM_256_176_BANK2_SIZE + _SOC_ISM_256_176_BANK3_SIZE) * \ 128 _SOC_ISM_MAX_STAGES 129 130 #define _SOC_ISM_256_96_BANK1_START 0 131 #define _SOC_ISM_256_96_BANK1_SIZE (1024*2) 132 #define _SOC_ISM_256_96_BANK2_START (_SOC_ISM_256_96_BANK1_START + _SOC_ISM_256_96_BANK1_SIZE ) 133 #define _SOC_ISM_256_96_BANK2_SIZE (1024*2) 134 #define _SOC_ISM_256_96_BANK3_START (_SOC_ISM_256_96_BANK2_START + _SOC_ISM_256_96_BANK2_SIZE) 135 #define _SOC_ISM_256_96_BANK3_SIZE (1024*1) 136 #define _SOC_ISM_256_96_BANK4_START (_SOC_ISM_256_96_BANK3_START + _SOC_ISM_256_96_BANK3_SIZE) 137 #define _SOC_ISM_256_96_BANK4_SIZE (1024*1) 138 #define _SOC_ISM_256_96_STAGE_SIZE (_SOC_ISM_256_96_BANK4_START + _SOC_ISM_256_96_BANK4_SIZE) 139 #define _SOC_ISM_256_96_SIZE (_SOC_ISM_256_96_BANK1_SIZE + _SOC_ISM_256_96_BANK2_SIZE + \ 140 _SOC_ISM_256_96_BANK3_SIZE + _SOC_ISM_256_96_BANK4_SIZE) * \ 141 _SOC_ISM_MAX_STAGES 142 143 #define _SOC_ISM_256_80_BANK1_START 0 144 #define _SOC_ISM_256_80_BANK1_SIZE (1024*2) 145 #define _SOC_ISM_256_80_BANK2_START (_SOC_ISM_256_80_BANK1_START + _SOC_ISM_256_80_BANK1_SIZE ) 146 #define _SOC_ISM_256_80_BANK2_SIZE (1024*1) 147 #define _SOC_ISM_256_80_BANK3_START (_SOC_ISM_256_80_BANK2_START + _SOC_ISM_256_80_BANK2_SIZE) 148 #define _SOC_ISM_256_80_BANK3_SIZE (1024*1) 149 #define _SOC_ISM_256_80_BANK4_START (_SOC_ISM_256_80_BANK3_START + _SOC_ISM_256_80_BANK3_SIZE) 150 #define _SOC_ISM_256_80_BANK4_SIZE (1024*1) 151 #define _SOC_ISM_256_80_STAGE_SIZE (_SOC_ISM_256_80_BANK4_START + _SOC_ISM_256_80_BANK4_SIZE) 152 #define _SOC_ISM_256_80_SIZE (_SOC_ISM_256_80_BANK1_SIZE + _SOC_ISM_256_80_BANK2_SIZE + \ 153 _SOC_ISM_256_80_BANK3_SIZE + _SOC_ISM_256_80_BANK4_SIZE) * \ 154 _SOC_ISM_MAX_STAGES 155 156 typedef struct { 157 int count; 158 uint8 index[_SOC_ISM_MAX_RAW_BANKS]; 159 } _soc_ism_real_bank_map_t; 160 161 typedef struct { 162 char name[80]; 163 uint32 mem; /* Logical set */ 164 uint8 index; 165 uint8 epb; /* largest entries per bucket */ 166 } _soc_ism_table_index_t; 167 168 typedef struct { 169 uint32 mem; 170 uint32 size; /* Number of widest entries in 1k units */ 171 uint8 banks; 172 uint8 allocated_banks; 173 } soc_ism_mem_size_config_t; 174 175 typedef struct _soc_ism_s { 176 uint8 ism_mode; 177 uint32 *bank_raw_sizes; 178 uint32 total_entries; 179 uint8 banks_per_stage; 180 uint8 max_banks; 181 uint8 total_banks; 182 uint8 max_raw_banks; 183 _soc_ism_real_bank_map_t *real_bank_map; 184 } _soc_ism_t; 185 186 typedef struct { 187 uint8 banks[_SOC_ISM_MAX_BANKS]; 188 uint32 bank_size[_SOC_ISM_MAX_BANKS]; 189 uint8 count; 190 } _soc_ism_mem_banks_t; 191 192 typedef struct _soc_ism_pd_rf_s { 193 soc_reg_t pdr; 194 soc_field_t pdf[5]; 195 } _soc_ism_pd_rf_t; 196 197 typedef struct _soc_ism_pd_s { 198 _soc_ism_pd_rf_t reg_field[7]; 199 _soc_ism_pd_rf_t hit_reg_field[3]; 200 } _soc_ism_pd_t; 201 202 extern uint32 _soc_ism_bank_raw_sizes[]; 203 extern uint32 _soc_ism_bank_raw_sizes_256[]; 204 extern uint32 _soc_ism_bank_raw_sizes_256_176[]; 205 extern uint32 _soc_ism_bank_raw_sizes_256_96[]; 206 extern uint32 _soc_ism_bank_raw_sizes_256_80[]; 207 extern _soc_ism_real_bank_map_t _soc_ism_real_bank_map[]; 208 extern _soc_ism_real_bank_map_t _soc_ism_real_bank_map_176[]; 209 extern _soc_ism_real_bank_map_t _soc_ism_real_bank_map_96[]; 210 extern _soc_ism_real_bank_map_t _soc_ism_real_bank_map_80[]; 211 extern uint32 _soc_ism_bank_avail[SOC_MAX_NUM_DEVICES][_SOC_ISM_MAX_BANKS]; 212 extern int soc_ism_get_hash_mem_idx(int unit, soc_mem_t mem); 213 extern char *soc_ism_table_to_name(uint32 mem); 214 extern int soc_ism_mem_config(int unit, 215 soc_ism_mem_size_config_t *mem_cfg, 216 int count); 217 extern int soc_ism_hash_init(int unit); 218 extern int soc_ism_hw_config(int unit); 219 extern uint32 _soc_ism_bank_total(int unit); 220 /* Note: offset_config can only be called after hw_config */ 221 extern int soc_ism_hash_offset_config(int unit, uint8 bank, uint8 offset); 222 extern int soc_ism_hash_offset_config_get(int unit, uint8 bank, uint8 *offset); 223 extern int soc_ism_table_hash_config(int unit, soc_ism_mem_type_t table, 224 uint8 zero_lsb); 225 extern int soc_ism_mem_hash_config(int unit, soc_mem_t mem, uint8 zero_lsb); 226 extern int soc_ism_table_hash_config_get(int unit, soc_ism_mem_type_t table, 227 uint8 *zero_lsb); 228 extern int soc_ism_mem_hash_config_get(int unit, soc_mem_t mem, uint8 *zero_lsb); 229 extern int soc_ism_mem_max_key_bits_get(int unit, soc_mem_t mem); 230 extern int soc_ism_hash_max_offset_get(int unit, int *offset); 231 extern int soc_ism_hash_table_offset_config_get(int unit, soc_ism_mem_type_t table, 232 uint8 *offset, uint8 *count); 233 extern int soc_ism_hash_mem_offset_config_get(int unit, soc_mem_t mem, uint8 *offset, 234 uint8 *count); 235 extern int soc_ism_get_total_banks(int unit, int *count); 236 extern uint32 soc_ism_get_phy_bank_mask(int unit, uint32 bank_mask); 237 extern int soc_ism_get_banks(int unit, soc_ism_mem_type_t table, uint8 *banks, 238 uint32 *bank_size, uint8 *count); 239 extern int soc_ism_get_banks_for_mem(int unit, soc_mem_t mem, uint8 *banks, 240 uint32 *bank_size, uint8 *count); 241 extern int soc_ism_get_hash_bucket_mask(int buckets); 242 extern int soc_ism_get_hash_bits(int buckets); 243 extern void soc_ism_gen_key_from_keyfields(int unit, soc_mem_t mem, void *entry, 244 soc_field_t *keyflds, uint8 *key, 245 uint8 num_flds); 246 extern void soc_ism_gen_crc_key_from_keyfields(int unit, soc_mem_t mem, void *entry, 247 soc_field_t *keyflds, uint8 *key, 248 uint8 num_flds, uint16 *bit_count); 249 extern void soc_ism_resolve_entry_index(_soc_ism_sbo_t *sbo, uint8 num_banks); 250 extern int soc_gen_entry_from_key(int unit, soc_mem_t mem, uint8 *key, void *entry); 251 extern int soc_gen_key_from_entry(int unit, soc_mem_t mem, void *entry, void *key); 252 extern int soc_generic_gen_hash(int unit, uint32 zero_lsb, uint32 num_bits, 253 uint32 offset, uint32 mask, uint8 *key, 254 uint16 lsb); 255 256 extern int soc_generic_hash(int unit, soc_mem_t mem, void *entry, int32 banks, 257 uint8 op, int *index, uint32 *result, uint32 *base_idx, 258 uint8 *num_entries); 259 extern int soc_generic_get_hash_key(int unit, soc_mem_t mem, void *entry, 260 soc_field_t *keyf, soc_field_t *lsbf, 261 uint8 *num_flds); 262 extern int soc_mem_multi_hash_move(int unit, soc_mem_t mem, int32 banks, int copyno, 263 void *entry, SHR_BITDCL *bucket_trace, 264 _soc_ism_mem_banks_t *banks_info, int recurse_depth); 265 extern uint8 soc_ism_get_bucket_offset(int unit, soc_mem_t mem, int8 midx, void *new_entry, 266 void *existing_entry); 267 #endif /* BCM_ISM_SUPPORT */ 268 269 #endif /* _SOC_ISM_H */