i2c.h (53831B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * Constants and defines for the Broadcom StrataSwitch (BCM56xx) I2C 8 * Bus Driver interface controller operating in master mode. 9 * 10 * See also: Broadcom StrataSwitch (TM) Register Reference Guide 11 */ 12 13 #ifndef _SOC_I2C_H 14 #define _SOC_I2C_H 15 16 #ifdef INCLUDE_I2C 17 18 #include <sal/compiler.h> 19 #include <sal/core/sync.h> 20 #ifdef INCLUDE_CPU_I2C 21 #include <soc/error.h> 22 #endif 23 24 #define I2CBUS_VOID(_u) (SOC_CONTROL(_u)->i2c_bus) 25 #define I2CBUS(_u) ((soc_i2c_bus_t *)I2CBUS_VOID(_u)) 26 27 #define I2C_LOCK(unit) \ 28 sal_mutex_take(I2CBUS(unit)->i2cMutex, sal_mutex_FOREVER) 29 #define I2C_UNLOCK(unit) \ 30 sal_mutex_give(I2CBUS(unit)->i2cMutex) 31 32 #define _i2c_abs(x) ((x) < 0 ? -(x) : (x)) 33 34 /* 7bit address range */ 35 #define I2C_7BIT_START 0x07 36 #define I2C_7BIT_END 0x78 37 38 /* Definitions for CMIC_I2C_CTRL@0x00000128 */ 39 #define CI2CC_INT_EN 0x00000080 /* Interrupt enable */ 40 #define CI2CC_BUS_EN 0x00000040 /* Bus enable */ 41 #define CI2CC_MM_START 0x00000020 /* Send start */ 42 #define CI2CC_MM_STOP 0x00000010 /* Send stop */ 43 #define CI2CC_INT_FLAG 0x00000008 /* Interrupt pending */ 44 #define CI2CC_AACK 0x00000004 /* Send ACK pulse */ 45 46 /* All I2C registers are 8bits wide */ 47 #define CMIC_I2C_REG_MASK 0x000000ff 48 #define CMIC_I2C_SPEED_DEFAULT 400 /* 400Khz */ 49 #define CMIC_I2C_SPEED_SLOW_IO 110 /* 101Khz */ 50 51 /* Timeout values, for semaphore give/take operations */ 52 #define I2C_TIMEOUT (100 * MILLISECOND_USEC) 53 #define I2C_TIMEOUT_QT (1 * SECOND_USEC) 54 #define I2C_TIMEOUT_PLI (20 * SECOND_USEC) 55 /* Base I2C saddr address base for the SOC device(s). */ 56 /* Uses 7-bit "datasheet" convention. */ 57 #define SOC_I2C_SLAVE_BASE 0x10 58 59 /* Devices allowed per switch chip - arbitrary value selected here */ 60 #define MAX_I2C_DEVICES 100 61 62 /* Allow I2c devices to be accessed from CPU */ 63 #define FORCE_CPU_I2C_ACCESS -1 64 65 /* I2C Slave receive (read) bus address byte(s) */ 66 #define SOC_I2C_RX_ADDR(addr) (((addr)<<1) | (I2C_READ_MASK)) 67 /* I2C Slave transmit (write) bus address byte(s) */ 68 #define SOC_I2C_TX_ADDR(addr) (((addr)<<1) & ~(I2C_READ_MASK)) 69 70 /* I2C device name max length */ 71 #define SOC_I2C_DEV_NAME_MAX 20 72 73 /* 74 * I2C Bus Interface Controller Definitions 75 * 76 * Status codes: The 31 possible status codes of the CMIC_I2C_STAT 77 * register bits: 0-7, enumerated for namespace reasons. Note that 78 * all of the status codes are multiples of 8. 79 */ 80 81 typedef enum soc_i2c_status_e { 82 SOC_I2C_BERR = 0x00, 83 SOC_I2C_START_TX = 0x08, 84 SOC_I2C_REP_START_TX = 0x10, 85 SOC_I2C_ADDR_WR_BIT_TX_ACK_RX = 0x18, 86 SOC_I2C_ADDR_WR_BIT_TX_NO_ACK_RX = 0x20, 87 SOC_I2C_DATA_BYTE_TX_ACK_RX = 0x28, 88 SOC_I2C_DATA_BYTE_TX_NO_ACK_RX = 0x30, 89 SOC_I2C_ARB_LOST = 0x38, 90 SOC_I2C_ADDR_RD_BIT_TX_ACK_RX = 0x40, 91 SOC_I2C_ADDR_RD_BIT_TX_NO_ACK_RX = 0x48, 92 SOC_I2C_DATA_BYTE_RX_ACK_TX = 0x50, 93 SOC_I2C_DATA_BYTE_RX_NO_ACK_TX = 0x58, 94 SOC_I2C_SADDR_RX_WR_BIT_RX_ACK_TX = 0x60, 95 SOC_I2C_ARB_LOST_SADDR_RX_WR_BIT_RX_ACK_TX = 0x68, 96 SOC_I2C_GC_ADDR_RX_ACK_TX = 0x70, 97 SOC_I2C_ARB_LOST_GC_ADDR_RX_ACK_TX = 0x78, 98 SOC_I2C_DATA_BYTE_RX_AFTER_SADDR_RX_ACK_TX = 0x80, 99 SOC_I2C_DATA_BYTE_RX_AFTER_SADDR_RX_NO_ACK_TX = 0x88, 100 SOC_I2C_DATA_BYTE_RX_AFTER_GC_ADDR_RX_ACK_TX = 0x90, 101 SOC_I2C_DATA_BYTE_RX_AFTER_GC_ADDR_RX_NO_ACK_TX = 0x98, 102 SOC_I2C_STOP_OR_REP_START_COND_RX_IN_SLAVE_MODE = 0xA0, 103 SOC_I2C_SADDR_RX_RD_BIT_RX_ACK_TX = 0xA8, 104 SOC_I2C_ARB_LOST_IN_ADDR_PHASE_SADDR_RX_RD_BIT_RX_ACK_TX = 0xB0, 105 SOC_I2C_SM_DATA_BYTE_TX_ACK_RX = 0xB8, 106 SOC_I2C_SM_DATA_BYTE_TX_NO_ACK_RX = 0xC0, 107 SOC_I2C_SM_LAST_BYTE_TX_ACK_RX = 0xC8, 108 SOC_I2C_2ND_ADDR_BYTE_TX_WR_BIT_TX_ACK_RX = 0xD0, 109 SOC_I2C_2ND_ADDR_BYTE_TX_WR_BIT_TX_NO_ACK_RX = 0xD8, 110 SOC_I2C_2ND_ADDR_BYTE_TX_RD_BIT_TX_ACK_RX = 0xE0, 111 SOC_I2C_2ND_ADDR_BYTE_TX_RD_BIT_TX_NO_ACK_RX = 0xE8, 112 SOC_I2C_UNDEFINED = 0xF0, /* Not defined, for symmetry only */ 113 SOC_I2C_NO_STATUS = 0xF8, 114 SOC_I2C_NUM_STATUS_CODES /* Always last please */ 115 } soc_i2c_status_t; 116 117 118 /* 119 * CPU/Master Initiated actions. 120 */ 121 122 typedef enum soc_i2c_op_e { 123 SOC_I2C_IDLE, 124 SOC_I2C_START, 125 SOC_I2C_REP_START, 126 SOC_I2C_TX, 127 SOC_I2C_RX, 128 SOC_I2C_STOP, 129 SOC_I2C_PROBE 130 } soc_i2c_op_t; 131 132 /* Software Interfaces */ 133 134 typedef uint8 i2c_saddr_t; /* Device address in datasheet-speak */ 135 typedef uint8 i2c_bus_addr_t; /* Address byte on the I2C SDA line */ 136 137 /* Driver i/f */ 138 extern soc_i2c_status_t soc_i2c_stat(int unit); 139 extern int soc_i2c_device_present(int unit, i2c_saddr_t saddr); 140 extern int soc_i2c_probe(int unit); 141 extern int soc_i2c_attach(int unit, uint32 flags, int speed); 142 extern void soc_i2c_reset(int unit); 143 extern int soc_i2c_detach(int unit); 144 extern int soc_i2c_ack_poll(int unit, i2c_bus_addr_t bus_addr, int maxpolls); 145 extern int soc_i2c_start(int unit, i2c_bus_addr_t bus_addr); 146 extern int soc_i2c_rep_start(int unit, i2c_bus_addr_t bus_addr); 147 extern int soc_i2c_write_one_byte(int unit, uint8 data); 148 extern int soc_i2c_read_one_byte(int unit, uint8* data, int ack); 149 extern int soc_i2c_read_bytes(int unit, uint8* data, int* len, int ack_last_byte); 150 extern int soc_i2c_read_short(int unit, uint16* val, int ack); 151 extern int soc_i2c_stop(int unit); 152 extern void soc_i2c_intr(int unit); 153 extern i2c_saddr_t soc_i2c_addr(int unit, int i2c_devid); 154 extern void soc_i2c_next_bus_phase(int unit, int tx_ack); 155 extern int soc_i2c_wait(int unit); 156 extern void soc_i2c_show(int unit); 157 extern int soc_i2c_device_count(int unit); 158 extern int soc_i2c_devtype(int unit, int devid); 159 extern int soc_i2c_is_attached(int unit); 160 extern void soc_i2c_show_log(int unit, int reverse); 161 extern void soc_i2c_clear_log(int unit); 162 extern void soc_i2c_show_speeds(int unit); 163 extern char *soc_i2c_saddr_to_string(int unit, i2c_saddr_t saddr); 164 extern int soc_i2c_unload_devices(int unit); 165 166 /* 167 * SMB commands 168 */ 169 extern int soc_i2c_read_byte(int unit, i2c_saddr_t saddr, uint8* data); 170 extern int soc_i2c_write_byte(int unit, i2c_saddr_t saddr, uint8 data); 171 extern int soc_i2c_read_word(int unit, i2c_saddr_t saddr, uint16* data); 172 extern int soc_i2c_write_word(int unit, i2c_saddr_t saddr, uint16 data); 173 extern int soc_i2c_read_byte_data(int unit, i2c_saddr_t saddr, 174 uint8 com, uint8* val); 175 extern int soc_i2c_write_byte_data(int unit, i2c_saddr_t saddr, 176 uint8 com, uint8 val); 177 extern int soc_i2c_read_word_data(int unit, i2c_saddr_t saddr, 178 uint8 com, uint16* val); 179 extern int soc_i2c_write_word_data(int unit, i2c_saddr_t saddr, 180 uint8 com, uint16 val); 181 extern int soc_i2c_block_read(int unit, i2c_saddr_t saddr, 182 uint8 com, uint8* n, uint8* d); 183 extern int soc_i2c_block_write(int unit, i2c_saddr_t saddr, 184 uint8 com, uint8 n, uint8* d); 185 extern int soc_i2c_multi_write(int unit, i2c_saddr_t saddr, 186 uint8 com, uint8 n, uint8* d); 187 extern char *soc_i2c_status_message(soc_i2c_status_t code); 188 189 190 /* I2C Device IO defines */ 191 #define I2C_XADDR_MASK 0xf8 192 #define I2C_XADDR 0xf0 193 #define I2C_READ_MASK 0x01 194 195 /* I2C Device Attribute flags */ 196 #define I2C_DEV_NONE 0x0 197 #define I2C_DEV_OK 0x1 198 #define I2C_DEV_BUSY 0x2 199 #define I2C_DEV_TESTED 0x4 200 #define I2C_DEV_DRIVER 0X8 201 #define I2C_REG_STATIC 0x10 202 #define I2C_REG_DYNAMIC 0x11 203 204 /* 205 * I2C Driver i/f routines. 206 */ 207 typedef int (*i2c_read_func_t)(int unit, int devno, 208 uint16 addr, uint8* data, uint32* len); 209 typedef int (*i2c_write_func_t)(int unit, int devno, 210 uint16 addr, uint8* data, uint32 len); 211 typedef int (*i2c_ioc_func_t)(int unit, int devno, int opcode, 212 void* data, int len); 213 typedef int (*i2c_dev_init_func_t)(int unit, int devno, 214 void* data, int len); 215 typedef int (*i2c_dev_deinit_func_t)(int unit, int devno); 216 /* 217 * I2C Driver structure: definitions for managed device operations 218 */ 219 typedef struct i2c_driver_s { 220 uint8 flags; /* Device flags */ 221 int devno; /* Index into device descriptor table */ 222 uint32 id; /* Device Serial No, GUID, or identifier */ 223 i2c_read_func_t read; /* Read routine */ 224 i2c_write_func_t write; /* Write routine */ 225 i2c_ioc_func_t ioctl; /* io control routine */ 226 i2c_dev_init_func_t load; /* called once at startup */ 227 i2c_dev_deinit_func_t unload; /* called once at the end */ 228 } i2c_driver_t; 229 230 /* 231 * I2C Device Descriptor: One for every known device on the bus 232 */ 233 typedef struct i2c_dev_s { 234 char *devname; /* Device name, eg. "eeprom0" */ 235 i2c_saddr_t saddr; /* Slave address */ 236 i2c_driver_t *driver; /* Driver routines */ 237 void* testdata; /* Test data */ 238 int testlen; /* Size of test data */ 239 uint32 tbyte; /* Bytes transmitted */ 240 uint32 rbyte; /* Bytes received */ 241 char *desc; /* Description */ 242 void *priv_data; /* private data per i2c device */ 243 } i2c_device_t; 244 245 /* 246 * I2C BUS configuration parameters, one per Switch on a Chip (SOC) 247 * device 248 */ 249 typedef struct soc_i2c_bus_s { 250 uint32 flags; /* Bitmask of state : see below */ 251 uint32 frequency; /* Frequency */ 252 uint8 m_val; /* M for frequency setting */ 253 uint8 n_val; /* N for frequency setting */ 254 uint32 master_addr; /* SOC's slave address (reset default 0x44) */ 255 soc_i2c_op_t opcode; /* Current operation in progress */ 256 uint32 data; /* Data associate with operation */ 257 uint32 pio_retries; /* Max number of times to sleep for IFLG=0 */ 258 uint32 iflg_polls; /* Polls of IFLG on last operation (PIO)*/ 259 soc_i2c_status_t stat; /* STAT: current state of bus */ 260 sal_mutex_t i2cMutex; /* I2C state mutual exclusion */ 261 sal_sem_t i2cIntr; /* I2C interrupt notification */ 262 int i2cTimeout; /* Operation timeout in microseconds */ 263 uint32 rxBytes; /* Bytes in */ 264 uint32 txBytes; /* Bytes out */ 265 i2c_device_t *devs[MAX_I2C_DEVICES]; /* devices on this bus */ 266 } soc_i2c_bus_t; 267 268 /* Bus Controller flag bit values and their meanings */ 269 #define SOC_I2C_DETACHED 0x00 /* No status */ 270 #define SOC_I2C_MODE_PIO 0x01 /* PIO mode */ 271 #define SOC_I2C_MODE_INTR 0x02 /* Interrupt mode */ 272 #define SOC_I2C_ATTACHED 0x04 /* Driver attached */ 273 #define SOC_I2C_NO_PROBE 0x08 /* Do not Probe immediately after attach */ 274 #define SOC_I2C_DO_PROBE 0x10 /* Probe after attach */ 275 276 /* 277 * Software device object accessors. 278 */ 279 extern int soc_i2c_register(int unit, char *devname, 280 i2c_device_t *device); 281 extern i2c_device_t *soc_i2c_device(int unit, int devid); 282 extern const char *soc_i2c_devname(int unit, int devid); 283 extern int soc_i2c_devdesc_set(int unit, int devid, char *desc); 284 extern int soc_i2c_devdesc_get(int unit, int devid, char **desc); 285 extern i2c_device_t *soc_i2c_get_devices(int unit, int *count); 286 extern int soc_i2c_devopen(int unit, char *devname, uint32 flags, int speed); 287 void 288 soc_i2c_decode_flags(int unit, char *msg, uint32 flags); 289 290 291 extern int soc_i2c_custom_device_add(int unit, i2c_device_t *device); 292 extern int soc_i2c_custom_device_remove(int unit, i2c_device_t *device); 293 extern int soc_i2c_dev_driver_get(int unit, char *drv_name, i2c_driver_t **drv); 294 295 /* I2C devices, descriptions, slave addresses, and I/O control calls 296 * The only interfaces made available here are for the BCM I2C API 297 * See also: bcm/bcmi2c.h 298 */ 299 300 /* Generic opcodes for device low level config routine */ 301 #define I2C_LLC_DETECT 0 302 #define I2C_LLC_READ 1 303 #define I2C_LLC_RESET 2 304 305 /* LM75 Thermal Sensor chips */ 306 #define I2C_LM75_0 "temp0" 307 #define I2C_LM75_1 "temp1" 308 #define I2C_LM75_2 "temp2" 309 #define I2C_LM75_3 "temp3" 310 #define I2C_LM75_4 "temp4" 311 #define I2C_LM75_5 "temp5" 312 #define I2C_LM75_6 "temp6" 313 #define I2C_LM75_7 "temp7" 314 #define I2C_LM75_SADDR0 0x48 315 #define I2C_LM75_SADDR1 0x49 316 #define I2C_LM75_SADDR2 0x4A 317 #define I2C_LM75_SADDR3 0x4B 318 #define I2C_LM75_SADDR4 0x4C 319 #define I2C_LM75_SADDR5 0x4D 320 #define I2C_LM75_SADDR6 0x4E 321 #define I2C_LM75_SADDR7 0x4F 322 323 /* LM63 Thermal Sensor chip */ 324 #define I2C_LM63_0 "temp0" 325 #define I2C_LM63_SADDR0 0x4C 326 327 /* Max 664x temperature sensor */ 328 #define MAX664X_DEVICE_TYPE 0x00000004 /* Device ID */ 329 #define I2C_MAX664X_0 "temp0" 330 #define I2C_MAX664X_SADDR0 0x4C 331 332 /* 24C64 EEPROM Chips */ 333 #define I2C_NVRAM_0 "nvram0" 334 #define I2C_NVRAM_1 "nvram1" 335 #define I2C_NVRAM_56 "nvram_56" 336 #define I2C_NVRAM_SADDR0 0x50 337 #define I2C_NVRAM_SADDR1 0x54 338 #define I2C_NVRAM_SADDR56 0x56 339 340 /* XFP Modules */ 341 #define I2C_XFP_0 "nvram0" 342 #define I2C_XFP_SADDR0 0x50 343 344 /* PCI-E config space register Debug access */ 345 #define I2C_PCIE_0 "pcie0" 346 #define I2C_PCIE_SADDR0 0x44 347 348 /*LTC 3880 Chip */ 349 #define I2C_LTC3880_60 "ltc3880_60" 350 #define I2C_LTC3880_SADDR60 0x60 351 #define I2C_LTC3880_61 "ltc3880_61" 352 #define I2C_LTC3880_SADDR61 0x61 353 #define I2C_LTC3880_62 "ltc3880_62" 354 #define I2C_LTC3880_SADDR62 0x62 355 #define I2C_LTC3880_64 "ltc3880_64" 356 #define I2C_LTC3880_SADDR64 0x64 357 #define I2C_LTC3880_65 "ltc3880_65" 358 #define I2C_LTC3880_SADDR65 0x65 359 360 #define I2C_LTC3880_41 "ltc3880_41" 361 #define I2C_LTC3880_SADDR41 0x41 362 #define I2C_LTC3880_42 "ltc3880_42" 363 #define I2C_LTC3880_SADDR42 0x42 364 #define I2C_LTM4676_43 "ltm4676_43" 365 #define I2C_LTM4676_SADDR43 0x43 366 #define I2C_LTM4676_47 "ltm4676_47" 367 #define I2C_LTM4676_SADDR47 0x47 368 #define I2C_LTC3880_43 "ltc3880_43" 369 #define I2C_LTC3880_SADDR43 0x43 370 #define I2C_LTC3880_47 "ltc3880_47" 371 #define I2C_LTC3880_SADDR47 0x47 372 #define I2C_LTC3880_45 "ltc3880" 373 #define I2C_LTC3880_SADDR45 0x45 374 375 /* Max 664x temperature sensor */ 376 #define MAX669X_DEVICE_TYPE 0x0000004d /* Device ID */ 377 #define I2C_MAX669X_18 "temp_18" 378 #define I2C_MAX669X_SADDR18 0x18 379 380 /* Max 664x temperature sensor */ 381 #define I2C_MAX669X_19 "temp_19" 382 #define I2C_MAX669X_SADDR19 0x19 383 384 /* Generic Sense Resistor data */ 385 typedef struct i2c_ltc_s { 386 int idx; /* Index */ 387 char *function; /* Voltage source to configure */ 388 char *devname; /* Name of LTCXXXX device */ 389 int ch; /* Device channel */ 390 uint16 res_value; /* resistor value */ 391 int flag; /* 1:Device is configured */ 392 } i2c_ltc_t; 393 394 /* PM Bus Compliant LTC 3880, LTC 3882, LTC 3884 */ 395 #define PMBUS_CMD_PAGE 0x0 396 #define PMBUS_CMD_OPERATION 0x1 397 #define PMBUS_CMD_ON_OFF_CONFIG 0x2 398 #define PMBUS_CMD_CLEAR_FAULTS 0x3 399 #define PMBUS_CMD_WRITE_PROTECT 0x10 400 #define PMBUS_CMD_STORE_USER_ALL 0x15 401 #define PMBUS_CMD_CAPACITY 0x19 402 #define PMBUS_CMD_VOUT_MODE 0x20 403 #define PMBUS_CMD_VOUT_COMMAND 0x21 404 #define PMBUS_CMD_VOUT_MAX 0x24 405 #define PMBUS_CMD_VOUT_MARGIN_HIGH 0x25 406 #define PMBUS_CMD_VOUT_MARGIN_LOW 0x26 407 #define PMBUS_CMD_VIN_ON 0x35 408 #define PMBUS_CMD_VIN_OFF 0x36 409 #define PMBUS_CMD_IOUT_CAL_GAIN 0x38 410 #define PMBUS_CMD_VOUT_OV_FAULT_LIMIT 0x40 411 #define PMBUS_CMD_VOUT_OV_FAULT_RES 0x41 412 #define PMBUS_CMD_VOUT_OV_WARN_LIMIT 0x42 413 #define PMBUS_CMD_VOUT_UV_WARN_LIMIT 0x43 414 #define PMBUS_CMD_VOUT_UV_FAULT_LIMIT 0x44 415 #define PMBUS_CMD_POWER_GOOD_ON 0x5E 416 #define PMBUS_CMD_POWER_GOOD_OFF 0x5F 417 #define PMBUS_CMD_POWER_ON_DELAY 0x60 418 #define PMBUS_CMD_POWER_ON_FAULT_LIMIT 0x62 419 #define PMBUS_CMD_STATUS_BYTE 0x78 420 #define PMBUS_CMD_STATUS_WORD 0x79 421 #define PMBUS_CMD_READ_VOUT 0x8B 422 #define PMBUS_CMD_READ_IOUT 0x8C /* L11 Format */ 423 #define PMBUS_CMD_READ_POUT 0x96 /* L11 Format */ 424 #define PMBUS_CMD_MFR_ID 0x99 425 #define PMBUS_CMD_MFR_MODEL 0x9A 426 #define PMBUS_CMD_MFR_COMMON 0xEF 427 #define PMBUS_CMD_MFR_RESET 0xFD 428 429 /* PM Bus io control */ 430 #define PMBUS_IOC_SET_DAC 0x1 431 #define PMBUS_IOC_SET_VOUT 0x2 432 #define PMBUS_IOC_READ_VOUT 0x3 433 #define PMBUS_IOC_SET_SEQ 0x4 434 #define PMBUS_IOC_READ_SEQ 0x5 435 #define PMBUS_IOC_READ_IOUT 0x6 436 #define PMBUS_IOC_READ_POUT 0x7 437 438 #define LTC_MFR_ID "LTC" 439 #define LTC_3880_MFR_MODEL "LTC3880" 440 #define LTC_3882_MFR_MODEL "LTC3882" 441 #define LTM_4676_MFR_MODEL "LTM4676" 442 #define LTC_3884_MFR_MODEL "LTC3884" 443 444 /* GH2 Board */ 445 #define LTC3880_1_250V_MAX_DACVAL 5632 /* 1.375 V */ 446 #define LTC3880_1_250V_MIN_DACVAL 4608 /* 1.125 V */ 447 #define LTC3880_1_250V_MID_DACVAL 5120 /* 1.25 V */ 448 449 450 /* HR3 Board */ 451 #define LTC3880_1_0V_MAX_DACVAL 4505 /* 1.1V */ 452 #define LTC3880_1_0V_MIN_DACVAL 3686 /* 0.9V */ 453 #define LTC3880_1_0V_MID_DACVAL 4096 /* 1.0V */ 454 455 #define LTC3880_1_2V_MAX_DACVAL 5407 /* 1.32V */ 456 #define LTC3880_1_2V_MIN_DACVAL 4424 /* 1.08V */ 457 #define LTC3880_1_2V_MID_DACVAL 4915 /* 1.2V */ 458 459 /* special request to 0.549V(for 1.0 Vout) due to HR3's AVS circuit */ 460 #define LTC3880_0_549V_MAX_DACVAL 2473 /* 0.604V(for 1.1V) */ 461 #define LTC3880_0_549V_MIN_DACVAL 2024 /* 0.494V(for 0.9V) */ 462 #define LTC3880_0_549V_MID_DACVAL 2249 /* 0.549V(for 1.0V) */ 463 464 /* GH Board */ 465 #define LTC3880_MIN_DACVAL 4301 /* 1.05V */ 466 #define LTC3880_MAX_DACVAL 3481 /* 0.85V */ 467 #define LTC3880_MID_DACVAL 4096 /* 1.0V */ 468 469 #define LTC3880_2_5V_MAX_DACVAL 11264 /* 2.75 V */ 470 #define LTC3880_2_5V_MIN_DACVAL 9216 /* 2.25 V */ 471 #define LTC3880_2_5V_MID_DACVAL 10240 /* 2.5 V */ 472 473 #define LTC3880_1_80V_MAX_DACVAL 8110 /* 1.98 V */ 474 #define LTC3880_1_80V_MIN_DACVAL 6636 /* 1.62 V */ 475 #define LTC3880_1_80V_MID_DACVAL 7373 /* 1.8 V */ 476 477 /* GH2 Board */ 478 #define LTC3880_1_50V_MAX_DACVAL 6485 479 #define LTC3880_1_50V_MIN_DACVAL 5371 480 #define LTC3880_1_50V_MID_DACVAL 6144 481 482 /* Saber2 board DAC values */ 483 #define LTC3880_1V_MAX_DACVAL 2867 /* 0.78V */ 484 #define LTC3880_1V_MIN_DACVAL 4301 /* 1.05V */ 485 #define LTC3880_1V_MID_DACVAL 4092 /* 1.0V */ 486 487 #define LTC3880_1_5V_MAX_DACVAL 5371 488 #define LTC3880_1_5V_MIN_DACVAL 6485 489 #define LTC3880_1_5V_MID_DACVAL 6144 490 491 #define LTC3880_0_6V_MAX_DACVAL 1574 492 #define LTC3880_0_6V_MIN_DACVAL 2361 493 #define LTC3880_0_6V_MID_DACVAL 2361 494 495 #define LTC3880_3_3V_MAX_DACVAL 11827 496 #define LTC3880_3_3V_MIN_DACVAL 14267 497 #define LTC3880_3_3V_MID_DACVAL 13517 498 499 /*TomaHawk Board */ 500 #define I2C_PWCTRL_2_SADDR60 0x60 501 #define LTC3880_1_8V_MAX_DACVAL 0x1DEC /* VID code for 1.87 V */ 502 #define LTC3880_1_8V_MIN_DACVAL 0x187B /* VID code for 1.53 V */ 503 #define LTC3880_1_8V_MID_DACVAL 0x1B33 /* VID code for 1.7 V */ 504 #define LTC3880_1_25V_MAX_DACVAL 0x1600 /* VID code for 1.375 V */ 505 #define LTC3880_1_25V_MIN_DACVAL 0x1200 /* VID code for 1.125 V */ 506 #define LTC3880_1_25V_MID_DACVAL 0x1400 /* VID code for 1.25 V */ 507 #define LTC3880_1_8V_RES_CONFIG 0x27 /* 39 mohms, L11 format */ 508 #define LTC3880_1_25V_RES_CONFIG 0x3 /* in mohms, L11 format */ 509 510 #define I2C_LTC3880_CH0 0 511 #define I2C_LTC3880_CH1 1 512 #define I2C_BOTH_CH 0xFF 513 514 /* Sequencing Ranges */ 515 #define LTC_SEQ_MAX 83000 516 #define LTC_SEQ_MIN 0 517 518 /*LTC 3884 Chip */ 519 #define I2C_LTC3884_42 "ltc3884_42" 520 #define I2C_LTC3884_SADDR42 0x42 521 #define I2C_LTC3884_43 "ltc3884_43" 522 #define I2C_LTC3884_SADDR43 0x43 523 #define I2C_LTC3884_46 "ltc3884_46" 524 #define I2C_LTC3884_SADDR46 0x46 525 526 /*LTC 3882 Chip */ 527 #define I2C_LTC3882_0 "ltc3882-0" 528 #define I2C_LTC3882_SADDR0 0x46 529 #define I2C_LTC3882_1 "ltc3882-1" 530 #define I2C_LTC3882_SADDR1 0x47 531 #define I2C_LTC3882_55 "ltc3882_55" 532 #define I2C_LTC3882_SADDR55 0x55 533 #define I2C_LTC3882_66 "ltc3882_66" 534 #define I2C_LTC3882_SADDR66 0x66 535 #define I2C_LTC3882_77 "ltc3882_77" 536 #define I2C_LTC3882_SADDR77 0x77 537 538 #define LTC3882_ANLG_MAX_DACVAL 0x127B /* VID code for 1.155 V */ 539 #define LTC3882_ANLG_MIN_DACVAL 0x0F1F /* VID code for .945 V */ 540 #define LTC3882_ANLG_MID_DACVAL 0x10CD /* VID code for 1.05 V */ 541 #define LTC3882_3_3V_MAX_DACVAL 0x3A14 /* VID code for 3.63 V */ 542 #define LTC3882_3_3V_MIN_DACVAL 0x2F85 /* VID code for 2.97 V */ 543 #define LTC3882_3_3V_MID_DACVAL 0x34CD /* VID code for 3.3 V */ 544 545 /* Sense Resistor Config */ 546 #define LTC3880_ANLG_RES_CONFIG 0x1 547 #define LTC3882_ANLG_RES_CONFIG 0x1 /* in mohms */ 548 #define LTC3882_3_3V_RES_CONFIG 0x1 /* in mohms */ 549 #define LTC3880_1_8V_RES_CONFIG 0x27 /* in mohms */ 550 551 #define LTC3880_CORE_RES_CONFIG 0x1 552 #define LTC3880_IPROC_CORE_RES_CONFIG 0x1 553 #define LTC3880_DDR_RES_CONFIG 0x1 /* in mohms */ 554 #define LTC3880_3_3V_RES_CONFIG 0x1 555 556 /*LTC 2974 Chip */ 557 #define I2C_LTC2974_0 "ltc2974" 558 #define I2C_LTC2974_SADDR0 0x64 559 #define I2C_LTC2974_5C "ltc2974_5C" 560 #define I2C_LTC2974_SADDR5C 0x5C 561 #define I2C_LTC2974_63 "ltc2974_63" 562 #define I2C_LTC2974_SADDR63 0x63 563 #define I2C_LTC2974_64 "ltc2974_64" 564 #define I2C_LTC2974_SADDR64 0x64 565 566 #define I2C_LTM4678_40 "ltm4678_40" 567 #define I2C_LTM4678_SADDR40 0x40 568 #define I2C_LTM4678_41 "ltm4678_41" 569 #define I2C_LTM4678_SADDR41 0x41 570 571 #define I2C_ISL68127_60 "isl68127_60" 572 #define I2C_ISL68127_SADDR60 0x60 573 #define I2C_ISL68127_61 "isl68127_61" 574 #define I2C_ISL68127_SADDR61 0x61 575 576 577 /* LTC 2974 channels */ 578 #define I2C_LTC2974_CH0 0 579 #define I2C_LTC2974_CH1 1 580 #define I2C_LTC2974_CH2 2 581 #define I2C_LTC2974_CH3 3 582 583 /* LTC 2974 channels */ 584 #define I2C_LTM4678_CH0 0 585 #define I2C_LTM4678_CH1 1 586 587 /* ISL 68127 channels */ 588 #define I2C_ISL68127_CH0 0 589 #define I2C_ISL68127_CH1 1 590 591 /* LTC 2974 resisitor config */ 592 #define LTC2974_RES_CONFIG 0x2 /* in mohms */ 593 594 #define LTM4678_RES_CONFIG 0x2 /* in mohms */ 595 596 /* Tomahawk PVT board */ 597 #define LTC388x_0_6V_DACVAL 0x099A /* VID code for 0.6V */ 598 #define LTC388x_1V_DACVAL 0x1000 /* VID code for 1V */ 599 #define LTC388x_1_5V_DACVAL 0x1800 /* VID code for 1.5V */ 600 #define LTC388x_1_2V_DACVAL 0x1333 /* VID code for 1.2V */ 601 #define LTC388x_1_8V_DACVAL 0x1CCD /* VID code for 1.8V */ 602 #define LTC388x_2_5V_DACVAL 0x2800 /* VID code for 2.5V */ 603 #define LTC388x_3_3V_DACVAL 0x34CD /* VID code for 3.3V */ 604 #define LTC388x_3_6V_DACVAL 0x399A /* VID code for 3.6V */ 605 606 /* Apache SVK */ 607 #define LTC388x_3_0V_DACVAL 0x3000 /* VID code for 3.0V */ 608 #define LTC388x_3_4V_DACVAL 0x3666 /* VID code for 3.4V */ 609 #define LTC388x_3_2V_DACVAL 0x3333 /* VID code for 3.2V */ 610 #define LTC2974_1_31V_DACVAL 0x14F6 /* VID code for 1.31V */ 611 #define LTC2974_1_01V_DACVAL 0x1029 /* VID code for 1.01V */ 612 #define LTC2974_1_25V_DACVAL 0x1400 /* VID code for 1.25V */ 613 614 /* Metrolite board DAC values */ 615 #define LTC2974_1_5V_DACVAL 12288 /* 1.5V */ 616 #define LTC2974_1_1V_DACVAL 9011 /* 1.1V */ 617 #define LTC2974_1V_DACVAL 8192 /* 1.0V */ 618 #define LTC2974_0_9V_DACVAL 7373 /* 0.9V */ 619 #define LTC2974_0_6V_DACVAL 4915 /* 0.6V */ 620 621 #define LTC2974_3_3V_DACVAL 27034 /* 3.3V */ 622 #define LTC2974_2_97V_DACVAL 24330 /* 2.97V */ 623 #define LTC2974_3_63V_DACVAL 29737 /* 3.63V */ 624 625 #define LTC2974_1_8V_DACVAL 14746 /* 1.8V */ 626 #define LTC2974_1_98V_DACVAL 16220 /* 1.98V */ 627 #define LTC2974_1_62V_DACVAL 13271 /* 1.62V */ 628 629 /*Tomahawk2 board DAC values */ 630 #define LTC2974_0_8V_DACVAL 6554 /* 0.8V */ 631 #define LTC2974_1_2V_DACVAL 9830 /* 1.2V */ 632 #define LTC2974_1_35V_DACVAL 11059 /* 1.35V */ 633 #define LTC2974_1_95V_DACVAL 15974 /* 1.95V */ 634 #define LTC2974_3_4V_DACVAL 27853 /* 3.4V */ 635 636 /* Helix5 board DAC values */ 637 #define LTC388x_1_04V_DACVAL 0x109D /* 1.04V */ 638 #define LTC388x_0_72V_DACVAL 0x0B8C /* 0.72V */ 639 #define LTC388x_0_88V_DACVAL 0x0E14 /* 0.88V */ 640 #define LTC388x_0_94V_DACVAL 0x0F1B /* 0.94V */ 641 #define LTC388x_0_66V_DACVAL 0x0A7F /* 0.66V */ 642 #define LTC388x_0_80V_DACVAL 0x0CCD /* 0.80V */ 643 #define LTC2974_1_32V_DACVAL 0x151F /* 1.32V */ 644 #define LTC2974_1_08V_DACVAL 0x1148 /* 1.08V */ 645 #define LTC2974_0_97V_DACVAL 0x0F7D /* 0.97V */ 646 #define LTC2974_0_79V_DACVAL 0x0CAC /* 0.79V */ 647 #define LTC2974_0_88V_DACVAL 0x0E14 /* 0.88V */ 648 #define LTC2974_2_75V_DACVAL 0x2C00 /* 2.75V */ 649 #define LTC2974_2_25V_DACVAL 0x2400 /* 2.25V */ 650 #define LTC2974_2_50V_DACVAL 0x2800 /* 2.50V */ 651 #define LTC2974_3_80V_DACVAL 0x3CB8 /* 3.80V */ 652 #define LTC2974_2_71V_DACVAL 0x2B4C /* 2.71V */ 653 #define LTC2974_5_50V_DACVAL 0x5800 /* 5.50V */ 654 #define LTC2974_4_50V_DACVAL 0x4800 /* 4.50V */ 655 #define LTC2974_5_0V_DACVAL 0x5000 /* 5.0V */ 656 657 658 /* Generic ADC IOCTL Commands */ 659 #define I2C_ADC_DUMP_ALL 0xE001 660 #define I2C_ADC_QUERY_CHANNEL 0xE002 661 #define I2C_ADC_SET_SAMPLES 0xE003 662 #define I2C_ADC_SET_BOARD_TYPE 0xE004 663 664 /* Generic ADC data */ 665 typedef struct i2c_adc_s { 666 #ifdef COMPILER_HAS_DOUBLE 667 double val; 668 double min; 669 double max; 670 double delta; 671 #else 672 int val; 673 int min; 674 int max; 675 int delta; 676 #endif 677 int nsamples; 678 } i2c_adc_t; 679 680 /*IOCTL TH LTC 3880 Commands */ 681 #define I2C_LTC_IOC_READ_VOUT 8 /* LTC read VOUT operation */ 682 #define I2C_LTC_IOC_NOMINAL 9 /* LTC set nominal voltage */ 683 #define I2C_LTC_IOC_SET_VOUT 10 /* LTC set vout operation */ 684 #define I2C_LTC_IOC_READ_IOUT 11 /* LTC read current operation */ 685 #define I2C_LTC_IOC_READ_POUT 12 /* LTC read power operation */ 686 #define I2C_LTC_IOC_SET_CALTAB I2C_DAC_IOC_SET_CALTAB /* LTC device calibration */ 687 #define I2C_LTC_IOC_SET_CONFIG 13 /* LTC device setting config */ 688 #define I2C_LTC_IOC_SET_RCONFIG 14 /* LTC setting Resistor config */ 689 #define I2C_SET_SEQ 15 /* LTC setting sequencing duration */ 690 #define I2C_READ_SEQ 16 /* LTC reading sequencing duration */ 691 692 /* regulator IOCTL commands */ 693 #define I2C_REGULATOR_IOC_VOLT_GET 0xA001 694 #define I2C_REGULATOR_IOC_VOLT_SET 0xA002 695 696 /* MAX127 ADC chips */ 697 #define I2C_ADC_0 "adc0" 698 #define I2C_ADC_1 "adc1" 699 #define I2C_ADC_2 "adc2" 700 #define I2C_ADC_3 "adc3" 701 #define I2C_ADC_SADDR0 0x28 702 #define I2C_ADC_SADDR1 0x29 703 #define I2C_ADC_SADDR2 0x2A 704 #define I2C_ADC_SADDR3 0x2B 705 706 #define I2C_ADC_CH0 0x0 /* MAX127 ADC Channel select 0 */ 707 #define I2C_ADC_CH1 0x1 /* MAX127 ADC Channel select 1 */ 708 #define I2C_ADC_CH2 0x2 /* MAX127 ADC Channel select 2 */ 709 #define I2C_ADC_CH3 0x3 /* MAX127 ADC Channel select 3 */ 710 #define I2C_ADC_CH4 0x4 /* MAX127 ADC Channel select 4 */ 711 #define I2C_ADC_CH5 0x5 /* MAX127 ADC Channel select 5 */ 712 #define I2C_ADC_CH6 0x6 /* MAX127 ADC Channel select 6 */ 713 #define I2C_ADC_CH7 0x7 /* MAX127 ADC Channel select 7 */ 714 715 /* MAX127 Type 716 * Polarity, min/max, value, reset range and current 717 * range structure. Used by ioctl() interface to query ADC 718 * after last operation. 719 */ 720 typedef struct max127_s { 721 #ifdef COMPILER_HAS_DOUBLE 722 double val; 723 double min; 724 double max; 725 double delta; 726 uint8 cr; 727 uint8 cv; 728 uint8 r; 729 #else 730 int val; 731 int min; 732 int max; 733 int delta; 734 int cr; 735 int cv; 736 #endif 737 } max127_t; 738 739 740 741 /* Cypress W311/W229 clock chips */ 742 #define I2C_PLL_0 "pll0" 743 #define I2C_PLL_SADDR0 0x69 744 #define I2C_PLL_SETW311 0x01 /* Enable W311 mode */ 745 #define I2C_PLL_W311_SETSPEED 0x00 /* Set the speed of a clock */ 746 #define I2C_PLL_W311_SPREAD 0x02 /* Set the spread spectrum mode */ 747 #define I2C_PLL_W311_GETSPREAD 0x04 /* Get On/Off state */ 748 #define I2C_PLL_W311_GETSPEED 0x08 /* Get Speed */ 749 750 /* Spread spectrum settings */ 751 #define I2C_PLL_SPREAD_NONE 0x00 /* No spread spectrum */ 752 #define I2C_PLL_SPREAD_NEG5 0x01 /* -0.50% */ 753 #define I2C_PLL_SPREAD_5_5 0x02 /* +/- 0.50% */ 754 #define I2C_PLL_SPREAD_2_5 0x03 /* +/- 0.25% */ 755 #define I2C_PLL_SPREAD_3_8 0x04 /* +/- 0.38% */ 756 757 758 /* PCF8574 Parallel port chips */ 759 #define I2C_LPT_0 "lpt0" 760 #define I2C_LPT_1 "lpt1" 761 #define I2C_LPT_2 "lpt2" 762 #define I2C_LPT_3 "lpt3" 763 #define I2C_LPT_4 "lpt4" 764 #define I2C_LPT_5 "lpt5" 765 #define I2C_LPT_6 "lpt6" 766 #define I2C_LPT_7 "lpt7" 767 #define I2C_LPT_SADDR0 0x20 768 #define I2C_LPT_SADDR1 0x27 769 #define I2C_LPT_SADDR2 0x23 770 #define I2C_LPT_SADDR3 0x26 771 #define I2C_LPT_SADDR4 0x21 772 #define I2C_LPT_SADDR5 0x22 773 #define I2C_LPT_SADDR6 0x24 774 #define I2C_LPT_SADDR7 0x25 775 776 /* LPT Mux: magic values written to lpt0 port to make new devices appear*/ 777 #define I2C_LPT_P48MUX_CLOCK_A 0x00 /* Core/Turbo clock and VDD_A */ 778 #define I2C_LPT_P48MUX_SDRAM_A 0x01 /* SDRAM clock A */ 779 #define I2C_LPT_P48MUX_CLOCK_B 0x02 /* Core clock B */ 780 #define I2C_LPT_P48MUX_SDRAM_B 0x03 /* SDRAM clock B */ 781 #define I2C_LPT_P48MUX_VDD_A 0x04 /* ADC VDD_A / DAC VDD_A */ 782 #define I2C_LPT_P48MUX_VDD_B 0x08 /* ADC VDD_B / DAC VDD_B */ 783 #define I2C_LPT_P48MUX_VDD_T 0x0c /* ADC TRef /DAC TRef */ 784 785 786 /* Linear Tech 1427 DAC chips */ 787 #define I2C_DAC_0 "dac0" 788 #define I2C_DAC_SADDR0 0x2C 789 #define I2C_DAC_IOC_SETDAC_MIN 0 /* DAC ops set output to MIN */ 790 #define I2C_DAC_IOC_SETDAC_MAX 1 /* DAC ops set output to MAX */ 791 #define I2C_DAC_IOC_CALIBRATE_MIN 2 /* DAC set min calibration value */ 792 #define I2C_DAC_IOC_CALIBRATE_MAX 3 /* DAC set max calibration value */ 793 #define I2C_DAC_IOC_CALIBRATE_STEP 4 /* DAC set step calibration value */ 794 #define I2C_DAC_IOC_SET_VOUT 5 /* DAC set VOUT operation */ 795 #define I2C_DAC_IOC_SET_CALTAB 6 /* Upload DAC calibration table */ 796 #define I2C_DAC_IOC_SETDAC_MID 7 /* Reset DAC to its H/W midrange */ 797 #define I2C_DAC_CAL_A 0 /* Calibration index:VDD Core A */ 798 #define I2C_DAC_CAL_B 1 /* Calibration index:VDD Core B */ 799 #define I2C_DAC_CAL_P 2 /* Calibration index:VDD PHY */ 800 #define I2C_DAC_CAL_T 3 /* Calibration index:VDD Turbo */ 801 802 /* 803 * DAC Calibration table for various ADC inputs and DAC chips. 804 * The ioctl call indexes this table with the len parameter 805 * and store the associated DAC Volts/Step value after setting max/min 806 * via reads from a MAX127 A/D device. 807 */ 808 typedef struct dac_calibrate_s { 809 int idx; 810 char *name; 811 #ifdef COMPILER_HAS_DOUBLE 812 double max; 813 double min; 814 double step; 815 #else 816 int max; 817 int min; 818 int step; 819 #endif 820 short dac_last_val; 821 short dac_max_hwval; 822 short dac_min_hwval; 823 short dac_mid_hwval; 824 short use_max; 825 } dac_calibrate_t; 826 827 /* 828 * The LTC-1427-50 is a 10bit DAC. 829 */ 830 #define LTC1427_VALID_BITS 0x03ff 831 832 /* On HUMV/Bradley/GW slow part, max and min should be set to 960 and 64 833 * to prevent the system crashes during voltage calibration. 834 */ 835 #define LTC1427_MAX_DACVAL 1023 836 #define LTC1427_MIN_DACVAL 0 837 #define LTC1427_MID_DACVAL 512 838 839 /* 840 * LM75 Device Driver Temperature probe and display 841 * See: drv/i2c/lm75.c 842 */ 843 extern void soc_i2c_lm75_temperature_show(int unit); 844 extern void soc_i2c_lm75_monitor(int unit, int enable, int nsecs); 845 846 /* 847 * LM63 Device Driver Temperature probe and display 848 * See: drv/i2c/lm63.c 849 */ 850 extern void soc_i2c_lm63_temperature_show(int unit); 851 extern void soc_i2c_lm63_monitor(int unit, int enable, int nsecs); 852 853 /* 854 * MAX664x Device Driver Temperature probe and display 855 * See: drv/i2c/max664x.c 856 */ 857 extern void soc_i2c_max664x_temperature_show(int unit); 858 extern void soc_i2c_max664x_monitor(int unit, int enable, int nsecs); 859 860 /* 861 * MAX669x Device Driver Temperature probe and display 862 * See: drv/i2c/max669x.c 863 */ 864 extern void soc_i2c_max669x_temperature_show(int unit); 865 extern void soc_i2c_max669x_monitor(int unit, int enable, int nsecs); 866 867 /* Matrix Orbital LCD Controllers See also: www.matrix-orbital.com */ 868 #define I2C_LCD_0 "lcd0" 869 #define I2C_LCD_SADDR0 0x2E 870 #define I2C_LCD_CLS 1 871 #define I2C_LCD_CONTRAST 2 872 #define I2C_LCD_CONFIG 3 873 874 /* Cypress 2239x clock chips */ 875 #define I2C_XPLL_0 "clk0" 876 #define I2C_XPLL_SADDR0 0x6A 877 878 #define I2C_XPLL_1 "clk0" 879 #define I2C_XPLL_SADDR1 0x69 880 881 #define I2C_XPLL_PLL1 0x01 882 #define I2C_XPLL_PCI I2C_XPLL_PLL1 883 #define I2C_XPLL_SET_PCI I2C_XPLL_PLL1 884 #define I2C_XPLL_SET_PLL1 I2C_XPLL_SET_PCI 885 886 #define I2C_XPLL_PLL2 0x02 887 #define I2C_XPLL_SDRAM I2C_XPLL_PLL2 888 #define I2C_XPLL_SET_SDRAM I2C_XPLL_PLL2 889 #define I2C_XPLL_SET_PLL2 I2C_XPLL_SET_SDRAM 890 891 #define I2C_XPLL_PLL3 0x03 892 #define I2C_XPLL_CORE I2C_XPLL_PLL3 893 #define I2C_XPLL_SET_CORE I2C_XPLL_PLL3 894 #define I2C_XPLL_SET_PLL3 I2C_XPLL_SET_CORE 895 896 #define I2C_XPLL_GET_OP(x) ((x) + 10) 897 898 #define I2C_XPLL_GET_PCI I2C_XPLL_GET_OP(I2C_XPLL_PLL1) 899 #define I2C_XPLL_GET_PLL1 I2C_XPLL_GET_PCI 900 901 #define I2C_XPLL_GET_SDRAM I2C_XPLL_GET_OP(I2C_XPLL_PLL2) 902 #define I2C_XPLL_GET_PLL2 I2C_XPLL_GET_SDRAM 903 904 #define I2C_XPLL_GET_CORE I2C_XPLL_GET_OP(I2C_XPLL_PLL3) 905 #define I2C_XPLL_GET_PLL3 I2C_XPLL_GET_CORE 906 907 /* Cypress 22150 clock chip */ 908 #define I2C_XPLL1_0 "clk0" 909 #define I2C_XPLL1_SADDR0 0x6B 910 911 912 /* User IO */ 913 #define I2C_XPLL_GET_REG 0x40 914 #define I2C_XPLL_SET_REG 0x80 915 916 917 /* PowerDsine 63000 PoE Microcontroller Unit */ 918 #define I2C_POE_0 "poe0" 919 #define I2C_POE_SADDR0 0x38 920 921 /* Linear Tech 4258 Powered Ethernet (POE) chips */ 922 #define I2C_POE_1 "poe1" 923 #define I2C_POE_2 "poe2" 924 #define I2C_POE_3 "poe3" 925 #define I2C_POE_4 "poe4" 926 #define I2C_POE_5 "poe5" 927 #define I2C_POE_6 "poe6" 928 #define I2C_POE_SADDR1 0x21 929 #define I2C_POE_SADDR2 0x22 930 #define I2C_POE_SADDR3 0x23 931 #define I2C_POE_SADDR4 0x24 932 #define I2C_POE_SADDR5 0x25 933 #define I2C_POE_SADDR6 0x26 934 #define I2C_POE_IOC_AUTO 1 935 #define I2C_POE_IOC_SHUTDOWN 2 936 #define I2C_POE_IOC_ENABLE_PORT 3 937 #define I2C_POE_IOC_DISABLE_PORT 4 938 #define I2C_POE_IOC_REG_DUMP 5 939 #define I2C_POE_IOC_STATUS 6 940 #define I2C_POE_IOC_CLEAR 7 941 #define I2C_POE_IOC_RESCAN 8 942 943 944 /* Maxim 5478 Digital Potentiometer chips */ 945 /* 946 * ioctl request structure 947 */ 948 typedef struct max5478_s { 949 uint8 wiper; 950 uint8 value; 951 } max5478_t; 952 953 #define I2C_POT_0 "pot0" 954 #define I2C_POT_SADDR0 0x2D 955 #define I2C_POT_IOC_SET 1 /* POT ioctl request */ 956 957 #define I2C_POT_MSG_WIPER_A 0 /* Msg command */ 958 #define I2C_POT_MSG_WIPER_B 1 /* Msg command */ 959 960 /* Broadcom BCM59101 POE */ 961 #define I2C_POE_7 "poe7" 962 #define I2C_POE_8 "poe8" 963 #define I2C_POE_9 "poe9" 964 #define I2C_POE_10 "poe10" 965 #define I2C_POE_SADDR7 0x20 966 #define I2C_POE_SADDR8 0x28 967 #define I2C_POE_SADDR9 0x50 968 #define I2C_POE_SADDR10 0x58 969 970 #define PCA9548_CHANNEL_NUM 8 /* Number of device channels */ 971 972 973 #define I2C_9505_INPUT_PORT(p) (p) 974 #define I2C_9505_OUTPUT_PORT(p) (0x8 + (p)) 975 976 #define I2C_IOP_IN(port) I2C_9505_INPUT_PORT(port) 977 #define I2C_IOP_OUT(port) I2C_9505_OUTPUT_PORT(port) 978 979 typedef struct iop_bit_config_s { 980 char *name; 981 int dev; 982 int port; 983 int pos; 984 int size; 985 int rw; 986 int def; 987 } iop_bit_config_t; 988 989 990 #if defined(SHADOW_SVK) 991 992 /* PCA9548 8-channel i2c switch */ 993 #define I2C_SW_0 "mux6" 994 #define I2C_SW_1 "mux7" 995 #define I2C_SW_SADDR0 0x76 996 #define I2C_SW_SADDR1 0x77 997 998 999 1000 /* PCA9505 40-bit i2c bus I/O port */ 1001 #define I2C_IOP_0 "iop0" 1002 #define I2C_IOP_1 "iop1" 1003 #define I2C_IOP_SADDR0 0x24 1004 #define I2C_IOP_SADDR1 0x22 1005 1006 /* Board ID is in IOP1, port 1 */ 1007 #define I2C_IOP_1_BRD_ID 1 1008 1009 #define I2C_MUX_0 "mux2" 1010 #define I2C_MUX_SADDR0 0x72 1011 1012 #define I2C_MUX_3 "mux3" 1013 #define I2C_MUX_SADDR3 0x73 1014 1015 #define I2C_MUX_4 "mux4" 1016 #define I2C_MUX_SADDR4 0x74 1017 1018 #define I2C_MUX_5 "mux5" 1019 #define I2C_MUX_SADDR5 0x75 1020 1021 #define I2C_MUX_6 "mux6" 1022 #define I2C_MUX_SADDR6 0x76 1023 1024 #define I2C_MUX_7 "mux7" 1025 #define I2C_MUX_SADDR7 0x77 1026 1027 #define I2C_MUX_70 "mux_70" 1028 #define I2C_MUX_SADDR70 0x70 1029 1030 #else /* Non C3/Shadow */ 1031 1032 1033 /* PCA9548 8-channel I2C Switch */ 1034 #define I2C_MUX_0 "mux0" 1035 #define I2C_MUX_SADDR0 0x72 1036 1037 #define I2C_MUX_3 "mux3" 1038 #define I2C_MUX_SADDR3 0x73 1039 1040 #define I2C_MUX_4 "mux4" 1041 #define I2C_MUX_SADDR4 0x74 1042 1043 #define I2C_MUX_5 "mux5" 1044 #define I2C_MUX_SADDR5 0x75 1045 1046 #define I2C_MUX_6 "mux6" 1047 #define I2C_MUX_SADDR6 0x76 1048 1049 #define I2C_MUX_7 "mux7" 1050 #define I2C_MUX_SADDR7 0x77 1051 1052 #define I2C_MUX_70 "mux_70" 1053 #define I2C_MUX_SADDR70 0x70 1054 1055 #endif /* SHADOW_SVK */ 1056 1057 1058 /* ADP4000 an integrated power control IC */ 1059 #define I2C_PWCTRL_0 "pwctrl0" 1060 #define I2C_PWCTRL_1 "pwctrl1" 1061 #define I2C_PWCTRL_2 "pwctrl2" 1062 #define I2C_PWCTRL_SADDR0 0x65 1063 #define I2C_PWCTRL_SADDR1 0x63 1064 #define I2C_PWCTRL_SADDR2 0x62 1065 #define I2C_ADP4000_CMD_OPERATION 0x1 1066 #define I2C_ADP4000_CMD_ON_OFF_CONFIG 0x2 1067 #define I2C_ADP4000_CMD_CLEAR_FAULTS 0x3 1068 #define I2C_ADP4000_CMD_WRITE_PROTECT 0x10 1069 #define I2C_ADP4000_CMD_CAPACITY 0x19 1070 #define I2C_ADP4000_CMD_VOUT_MODE 0x20 1071 #define I2C_ADP4000_CMD_VOUT_CMD 0x21 1072 #define I2C_ADP4000_CMD_STATUS_BYTE 0x78 1073 #define I2C_ADP4000_CMD_STATUS_WORD 0x79 1074 #define I2C_ADP4000_CMD_RESET 0xD0 1075 #define I2C_ADP4000_CMD_CONFIG_1A 0xD2 1076 #define I2C_ADP4000_CMD_CONFIG_1B 0xD3 1077 1078 #define ADP4000_MAX_DACVAL 0x72 /* VID code for 0.9V */ 1079 #define ADP4000_MIN_DACVAL 0x52 /* VID code for 1.1V */ 1080 #define ADP4000_ANLG_MIN_DACVAL 0x22 /* VID code for 1.4V */ 1081 #define ADP4000_MID_DACVAL 0x62 /* VID code for 1.0V */ 1082 1083 /* NCP4200 an intergrated power control IC */ 1084 #define NCP4200_MAX_DACVAL 0x6A /* VID code for 0.95V */ 1085 #define NCP4200_MIN_DACVAL 0x52 /* VID code for 1.1V */ 1086 #define NCP4200_ANLG_MIN_DACVAL 0x22 /* VID code for 1.4V */ 1087 #define NCP4200_MID_DACVAL 0x62 /* VID code for 1.0V */ 1088 #ifdef COMPILER_HAS_DOUBLE 1089 1090 #define NCP4200_MAX_VOL 1.1 /* 1.1V */ 1091 #define NCP4200_MIN_VOL 0.95 /* 0.95V */ 1092 #define NCP4200_MID_VOL 1.0 /* 1.0V */ 1093 #define NCP4200_DAC_STEP 0.00625 /* 0.00625V */ 1094 #else 1095 #define NCP4200_MAX_VOL 1100000 /* 1100000 uV */ 1096 #define NCP4200_MIN_VOL 950000 /* 950000 uV */ 1097 #define NCP4200_MID_VOL 1000000 /* 1000000 uV */ 1098 #define NCP4200_DAC_STEP 6250 /* 625 uV */ 1099 #endif 1100 1101 /* NCP81233 an integrated power control IC */ 1102 #define I2C_NCP81233_0 "ncp81233_0" 1103 #define I2C_NCP81233_SADDR0 0x70 1104 #define I2C_NCP81233_CH0 0 1105 1106 #define NCP81233_MAX_DACVAL 0xAB /* VID code for 1.1V */ 1107 #define NCP81233_MIN_DACVAL 0x6F /* VID code for 0.8V */ 1108 #define NCP81233_MID_DACVAL 0x93 /* VID code for 0.98V */ 1109 1110 #ifdef COMPILER_HAS_DOUBLE 1111 #define NCP81233_MAX_VOL 1.1 /* 1.1V */ 1112 #define NCP81233_MIN_VOL 0.8 /* 0.8V */ 1113 #define NCP81233_MID_VOL 0.98 /* 0.98V */ 1114 #define NCP81233_DAC_STEP 0.005 /* 0.005V */ 1115 #else 1116 #define NCP81233_MAX_VOL 1100000 /* 1100000 uV */ 1117 #define NCP81233_MIN_VOL 800000 /* 800000 uV */ 1118 #define NCP81233_MID_VOL 980000 /* 980000 uV */ 1119 #define NCP81233_DAC_STEP 5000 /* 5000 uV */ 1120 #endif 1121 1122 /* Summit SMM665c */ 1123 #define SMM665C_ADDR_BIT_A2 1 /* Pulled up in SVK */ 1124 #define SMM665C_ADDR_BIT_A1 1 /* Default on chip */ 1125 #define SMM665C_ADDR_BIT_A0 0 1126 #define SMM665C_ADDR_BIT_SA0 1 1127 1128 #define SMM665C_ADDR ((SMM665C_ADDR_BIT_SA0 << 3) |(SMM665C_ADDR_BIT_A2 << 2)) 1129 1130 #define SMM665C_CONTROL_SADDR (SMM665C_ADDR | \ 1131 (SMM665C_ADDR_BIT_A1 << 1) | \ 1132 SMM665C_ADDR_BIT_A0) 1133 #define SMM665C_INTMEM_BANKA_SADDR (0x10 | SMM665C_ADDR ) 1134 #define SMM665C_INTMEM_BANKB_SADDR (0x10 | SMM665C_ADDR | 1) 1135 #define SMM665C_CONFIG_SADDR (0x10 | SMM665C_ADDR | 3) 1136 1137 /* Summit SMM665c ADOC */ 1138 #define I2C_ADOC_0 "adoc0" 1139 #define I2C_ADOC_SADDR0 (0x40 | SMM665C_CONTROL_SADDR) /* 0x4E */ 1140 #define I2C_ADOC_SADDR1 (0x40 | SMM665C_INTMEM_BANKA_SADDR) /* 0x5C */ 1141 #define I2C_ADOC_SADDR2 (0x40 | SMM665C_INTMEM_BANKB_SADDR) /* 0x5D */ 1142 #define I2C_ADOC_SADDR3 (0x40 | SMM665C_CONFIG_SADDR) /* 0x5F */ 1143 1144 /* Values to fill in dac_params struct 1145 * Note: these are voltage limits, dac value and multiplier 1146 * is computed internally. 1147 */ 1148 #define SMM655_VOLTAGE_RANGE 7 /* Variation allowed in percentage */ 1149 1150 #define SMM665_CORE_MID 1000 /* in mV */ 1151 #define SMM665_CORE_MIN (SMM665_CORE_MID - \ 1152 (SMM655_VOLTAGE_RANGE * SMM665_CORE_MID) / 100) 1153 #define SMM665_CORE_MAX (SMM665_CORE_MID + \ 1154 (SMM655_VOLTAGE_RANGE * SMM665_CORE_MID) / 100) 1155 1156 #define SMM665_ANLG_MID 1000 /* in mV */ 1157 #define SMM665_ANLG_MIN (SMM665_ANLG_MID - \ 1158 (SMM655_VOLTAGE_RANGE * SMM665_ANLG_MID) / 100) 1159 #define SMM665_ANLG_MAX (SMM665_ANLG_MID + \ 1160 (SMM655_VOLTAGE_RANGE * SMM665_ANLG_MID) / 100) 1161 1162 #define SMM665_1_5_MID 1500 /* in mV */ 1163 #define SMM665_1_5_MIN (SMM665_1_5_MID - \ 1164 (SMM655_VOLTAGE_RANGE * SMM665_1_5_MID) / 100) 1165 #define SMM665_1_5_MAX (SMM665_1_5_MID - \ 1166 (SMM655_VOLTAGE_RANGE * SMM665_1_5_MID) / 100) 1167 1168 #define SMM665_3_3_MID 3300 /* in mV */ 1169 #define SMM665_3_3_MIN (SMM665_3_3_MID - \ 1170 (SMM655_VOLTAGE_RANGE * SMM665_3_3_MID) / 100) 1171 1172 #define SMM665_3_3_MAX (SMM665_3_3_MID + \ 1173 (SMM655_VOLTAGE_RANGE * SMM665_3_3_MID) / 100) 1174 1175 #define SMM665_1_2_MID 1200 /* in mV */ 1176 #define SMM665_1_2_MIN (SMM665_1_2_MID - \ 1177 (SMM655_VOLTAGE_RANGE * SMM665_1_2_MID) / 100) 1178 1179 #define SMM665_1_2_MAX (SMM665_1_2_MID + \ 1180 (SMM655_VOLTAGE_RANGE * SMM665_1_2_MID) / 100) 1181 1182 #define SMM665_TCAM_MID 1800 /* in mV */ 1183 #define SMM665_TCAM_MIN (SMM665_TCAM_MID - \ 1184 (SMM655_VOLTAGE_RANGE * SMM665_TCAM_MID) / 100) 1185 #define SMM665_TCAM_MAX (SMM665_TCAM_MID + \ 1186 (SMM655_VOLTAGE_RANGE * SMM665_TCAM_MID) / 100) 1187 1188 #define SMM665_0_9_MID 900 /* in mV */ 1189 #define SMM665_0_9_MIN (SMM665_0_9_MID - \ 1190 (SMM655_VOLTAGE_RANGE * SMM665_0_9_MID) / 100) 1191 #define SMM665_0_9_MAX (SMM665_0_9_MID + \ 1192 (SMM655_VOLTAGE_RANGE * SMM665_0_9_MID) / 100) 1193 1194 1195 /* Device Types */ 1196 #define LM75_DEVICE_TYPE 0x00000001 /* Maxim Lm75 Temperature sensor */ 1197 #define LC24C64_DEVICE_TYPE 0x00000002 /* 24C64 eeprom */ 1198 #define XFP_DEVICE_TYPE 0x00000002 /* XFP device */ 1199 #define PCIE_DEVICE_TYPE 0x00000002 /* PCIE */ 1200 #define MAX127_DEVICE_TYPE 0x00000003 /* Maxmim 127 DAS */ 1201 #define W229B_DEVICE_TYPE 0x00000004 /* Cypress W229/W311 Pll/clock */ 1202 #define PCF8574_DEVICE_TYPE 0x00000005 /* NXP 8574 8bit IO expander */ 1203 #define LTC1427_DEVICE_TYPE 0x00000006 /* Linear Tech 1427 DAC */ 1204 #define LCD_DEVICE_TYPE 0x00000007 /* Max Orbital LCD Controllers */ 1205 #define CY2239X_DEVICE_TYPE 0x00000008 /* Cypress 2239x clock chips */ 1206 #define CY22150_DEVICE_TYPE 0x00000009 /* Cypress 22150 clock chip */ 1207 #define PD63000_DEVICE_TYPE 0x0000000A /* PowerDsine 63000 PoE controller */ 1208 #define LTC4258_DEVICE_TYPE 0x0000000B /* Linear Tech 4258 PoE chips */ 1209 #define MAX5478_DEVICE_TYPE 0x0000000C /* Maxim 5478 Digital POT */ 1210 #define BCM59101_DEVICE_TYPE 0x0000000D /* Broadcom 59101 PoE */ 1211 #define PCA9548_DEVICE_TYPE 0x0000000E /* NXP 9548 8-ch I2C Switch */ 1212 #define PCA9505_DEVICE_TYPE 0x0000000F /* NXP 9505 40-bit IO */ 1213 #define ADP4000_DEVICE_TYPE 0x00000010 /* ADP 4000 Power control */ 1214 #define SMM665C_DEVICE_TYPE 0x00000011 /* Summit 665C Active DC Output ctrl */ 1215 #define CXP_DEVICE_TYPE 0x00000012 /* CXP transceiver */ 1216 #define LTC3880_DEVICE_TYPE 0x00000013 /* LTC 3880 Voltage Controller */ 1217 #define LTC3882_DEVICE_TYPE 0x00000014 /* LTC 3882 Voltage Controller */ 1218 #define LTC2974_DEVICE_TYPE 0x00000015 /* LTC 2974 Voltage Sensor */ 1219 #define LTM4676_DEVICE_TYPE 0x00000016 /* LTM 4676 voltage controller */ 1220 #define LTC3884_DEVICE_TYPE 0x00000017 /* LTC 3884 Voltage Controller */ 1221 #define LM63_DEVICE_TYPE 0x00000018 /* LM63 Temperature Sensor */ 1222 #define PMBUS_DEVICE_TYPE 0x00000019 /* PMBUS Power control */ 1223 #define LTM4678_DEVICE_TYPE 0x0000001A /* LTM 4678 Voltage Regularor/Sensor */ 1224 #define ISL68127_DEVICE_TYPE 0x0000001B /* ISL 68127 Voltage Regularor/Sensor */ 1225 1226 #if defined(BCM_CMICM_SUPPORT) || defined(BCM_CMICX_SUPPORT) || defined(BCM_IPROC_SUPPORT) 1227 #define SMBUS_QUICK_CMD 0 1228 #define SMBUS_SEND_BYTE 1 1229 #define SMBUS_RECEIVE_BYTE 2 1230 #define SMBUS_WRITE_BYTE 3 1231 #define SMBUS_READ_BYTE 4 1232 #define SMBUS_WRITE_WORD 5 1233 #define SMBUS_READ_WORD 6 1234 #define SMBUS_BLOCK_WRITE 7 1235 #define SMBUS_BLOCK_READ 8 1236 #define SMBUS_PROCESS_CALL 9 1237 #define SMBUS_BLOCK_PROCESS_CALL 10 1238 1239 extern int smbus_start_wait(int unit); 1240 extern int smbus_quick_command(int unit, uint8 addr); 1241 extern int cmicx_smbus_start_wait(int unit); 1242 extern int cmicx_smbus_quick_command(int unit, uint8 addr); 1243 extern int iproc_smbus_start_wait(int unit); 1244 extern int iproc_smbus_quick_command(int unit, uint8 addr); 1245 1246 #endif /* CMICM || CMICX Support */ 1247 1248 1249 /* CXP Transceiver */ 1250 #define I2C_CXP_0 "cxp0" 1251 #define I2C_CXP_SADDR0 0x50 1252 #define I2C_CXP_VENDOR_NAME 0 1253 #define I2C_CXP_VENDOR_OUI 1 1254 #define I2C_CXP_VENDOR_PART_NUM 2 1255 #define I2C_CXP_VENDOR_REV_ID 3 1256 #define I2C_CXP_VENDOR_SERIAL 4 1257 #define I2C_CXP_VENDOR_DATE 5 1258 #define I2C_CXP_VENDOR_LOT 6 1259 #define I2C_CXP_TX_CAPABILITY 7 1260 #define I2C_CXP_TX_STATUS 8 1261 #define I2C_CXP_TX_CHANNEL_STATUS 9 1262 #define I2C_CXP_TX_CHANNEL_CTRL 10 1263 #define I2C_CXP_TX_OUTPUT_STATUS 11 1264 #define I2C_CXP_TX_OUTPUT_CTRL 12 1265 #define I2C_CXP_TX_LOS_STATUS 13 1266 #define I2C_CXP_TX_LOS_MASK 14 1267 #define I2C_CXP_RX_CAPABILITY 15 1268 #define I2C_CXP_RX_STATUS 16 1269 #define I2C_CXP_RX_CHANNEL_STATUS 17 1270 #define I2C_CXP_RX_CHANNEL_CTRL 18 1271 #define I2C_CXP_RX_OUTPUT_STATUS 19 1272 #define I2C_CXP_RX_OUTPUT_CTRL 20 1273 #define I2C_CXP_RX_LOS_STATUS 21 1274 #define I2C_CXP_RX_LOS_MASK 22 1275 1276 1277 #if defined(__DUNE_GTO_BCM_CPU__) || defined(__DUNE_WRX_BCM_CPU__) || defined(__DUNE_SLK_BCM_CPU__) || defined(INCLUDE_CPU_I2C) 1278 typedef enum { 1279 CPU_I2C_ALEN_NONE_DLEN_BYTE = 0x1, 1280 CPU_I2C_ALEN_NONE_DLEN_WORD = 0x2, 1281 CPU_I2C_ALEN_NONE_DLEN_LONG = 0x4, 1282 CPU_I2C_ALEN_BYTE_DLEN_BYTE = 0x11, 1283 CPU_I2C_ALEN_BYTE_DLEN_WORD = 0x12, 1284 CPU_I2C_ALEN_WORD_DLEN_WORD = 0x22, 1285 CPU_I2C_ALEN_BYTE_DLEN_LONG = 0x14, 1286 CPU_I2C_ALEN_WORD_DLEN_LONG = 0x24, 1287 CPU_I2C_ALEN_LONG_DLEN_LONG = 0x44, 1288 CPU_I2C_ALEN_LAST 1289 } CPU_I2C_BUS_LEN; 1290 1291 /* The I2C bus number to used based on CPU card */ 1292 #if defined(__DUNE_WRX_BCM_CPU__) 1293 #define CPU_I2C_BUS_NUM_DEFAULT 0 1294 #else 1295 #define CPU_I2C_BUS_NUM_DEFAULT 1 1296 #endif 1297 extern uint8 cpu_i2c_bus_num_default; 1298 1299 /* write value to the given address in the given chip */ 1300 int cpu_i2c_write(int chip, int addr, CPU_I2C_BUS_LEN alen, int val); 1301 1302 #ifdef INCLUDE_CPU_I2C 1303 /* perform an I2C read operation on an I2C device connected to the CPU */ 1304 soc_error_t cpu_i2c_read_generic( 1305 uint8 i2c_bus, /* The number of the I2C bus to access on */ 1306 uint16 i2c_dev,/* the device on the I2C bus (slave address) to be accessed */ 1307 uint8 alen, /* the length of the address in bytes, should be between 0 and 4. */ 1308 uint8 dlen, /* the length of the data to read. */ 1309 uint32 addr, /* The address in the device to be accessed (register address). Used if alen>0 */ 1310 uint8 *data); /* the buffer for the data to be read. */ 1311 /* perform an I2C write operation on an I2C device connected to the CPU */ 1312 soc_error_t cpu_i2c_write_generic( 1313 uint8 i2c_bus, /* The number of the I2C bus to access on */ 1314 uint16 i2c_dev,/* the device on the I2C bus (slave address) to be accessed */ 1315 uint8 alen, /* the length of the address in bytes, should be between 0 and 4. */ 1316 uint8 dlen, /* the length of the data to read. */ 1317 uint32 addr, /* The address in the device to be accessed (register address). Used if alen>0 */ 1318 uint8 *data); /* the buffer for the data to be read. */ 1319 /* Write to the internal device Address space using I2C */ 1320 soc_error_t cpu_i2c_device_read( 1321 uint8 i2c_bus, /* The number of the I2C bus to access on */ 1322 uint8 i2c_dev, /* the device on the I2C bus (slave address) to be accessed */ 1323 uint32 addr, /* The address to access in the internal device address space */ 1324 uint32 *value);/* the value to be read. */ 1325 /* Write to the internal device Address space using I2C */ 1326 soc_error_t cpu_i2c_device_write( 1327 uint8 i2c_bus, /* The number of the I2C bus to access on */ 1328 uint8 i2c_dev, /* the device on the I2C bus (slave address) to be accessed */ 1329 uint32 addr, /* The address to access in the internal device address space */ 1330 uint32 value); /* the value to be written. */ 1331 #endif /* INCLUDE_CPU_I2C */ 1332 1333 /* read a block of data from a device */ 1334 int cpu_i2c_block_read(int bus, i2c_saddr_t saddr, uint8 reg, uint8 *data, uint8 *len); 1335 1336 /* write a block of data to a device */ 1337 int cpu_i2c_block_write(int bus, i2c_saddr_t saddr, uint8 reg, uint8 *data, uint8 len); 1338 1339 #ifndef __KERNEL__ 1340 /* read value from the given address in the given chip */ 1341 int cpu_i2c_read(int chip, int addr, CPU_I2C_BUS_LEN alen, int* p_val); 1342 #endif /* __KERNEL__ */ 1343 1344 /* CPU Driver i/f */ 1345 extern int cpu_i2c_register(int unit, char *devname, 1346 i2c_device_t *device); 1347 extern i2c_device_t *cpu_i2c_device(int unit, int devid); 1348 extern const char *cpu_i2c_devname(int unit, int devid); 1349 extern int cpu_i2c_devdesc_set(int unit, int devid, char *desc); 1350 extern int cpu_i2c_devdesc_get(int unit, int devid, char **desc); 1351 extern i2c_device_t *cpu_i2c_get_devices(int unit, int *count); 1352 extern int cpu_i2c_dev_open(int unit, char *devname, uint32 flags, 1353 int speed); 1354 extern int cpu_i2c_dev_write(int unit, int devno, uint16 addr, uint8 *data, 1355 uint32 len); 1356 extern int cpu_i2c_dev_read(int unit, int devno, uint16 addr, uint8 *data, 1357 uint32 *len); 1358 extern int cpu_i2c_dev_ioctl(int unit, int devno, int cmd, void *data, 1359 int len); 1360 1361 extern soc_i2c_status_t cpu_i2c_stat(int unit); 1362 extern int cpu_i2c_device_present(int unit, i2c_saddr_t saddr); 1363 extern int cpu_i2c_probe(int unit); 1364 extern int cpu_i2c_attach(int unit, uint32 flags, int speed); 1365 extern void cpu_i2c_reset(int unit); 1366 extern int cpu_i2c_detach(int unit); 1367 extern int cpu_i2c_ack_poll(int unit, i2c_bus_addr_t bus_addr, int maxpolls); 1368 extern int cpu_i2c_start(int unit, i2c_bus_addr_t bus_addr); 1369 extern int cpu_i2c_rep_start(int unit, i2c_bus_addr_t bus_addr); 1370 extern int cpu_i2c_write_one_byte(int unit, uint8 data); 1371 extern int cpu_i2c_read_one_byte(int unit, uint8* data, int ack); 1372 extern int cpu_i2c_read_bytes(int unit, uint8* data, int* len, int ack_last_byte); 1373 extern int cpu_i2c_read_short(int unit, uint16* val, int ack); 1374 extern int cpu_i2c_stop(int unit); 1375 extern void cpu_i2c_intr(int unit); 1376 extern i2c_saddr_t cpu_i2c_addr(int unit, int i2c_devid); 1377 extern void cpu_i2c_next_bus_phase(int unit, int tx_ack); 1378 extern int cpu_i2c_wait(int unit); 1379 extern void cpu_i2c_show(int unit); 1380 extern int cpu_i2c_device_count(int unit); 1381 extern int cpu_i2c_devtype(int unit, int devid); 1382 extern int cpu_i2c_is_attached(int unit); 1383 extern void cpu_i2c_show_log(int unit, int reverse); 1384 extern void cpu_i2c_clear_log(int unit); 1385 extern void cpu_i2c_show_speeds(int unit); 1386 extern char *cpu_i2c_saddr_to_string(int unit, i2c_saddr_t saddr); 1387 extern int cpu_i2c_devopen(int unit, char *devname, uint32 flags, 1388 int speed); 1389 extern int cpu_i2c_defaultbus(void); 1390 extern int cpu_i2c_access(int devid); 1391 1392 #endif /* defined(__DUNE_GTO_BCM_CPU__) || defined(__DUNE_WRX_BCM_CPU__) || defined(__DUNE_SLK_BCM_CPU__) || defined(INCLUDE_CPU_I2C) */ 1393 1394 #if defined(SHADOW_SVK) 1395 extern int 1396 pio_flag_to_dev(char* field, int *dev, int *port, int *pos, int *size, int *rw); 1397 extern int 1398 pio_devname(int dev, char **name); 1399 #endif 1400 1401 #endif /* INCLUDE_I2C */ 1402 1403 #endif /* !_SOC_I2C_H */