hurricane3.h (5160B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * File: hurricane3.h 8 */ 9 10 #ifndef _SOC_HURRICANE3_H_ 11 #define _SOC_HURRICANE3_H_ 12 13 #include <soc/drv.h> 14 #include <soc/mem.h> 15 #include <shared/sram.h> 16 17 enum soc_hr3_chip_sku_e { 18 SOC_HR3_SKU_HURRICANE3 = 0, 19 SOC_HR3_SKU_HURRICANE3LITE = 1, 20 SOC_HR3_SKU_BUCKHOUND = 2, 21 SOC_HR3_SKU_FOXHOUND2 = 3 22 }; 23 24 enum soc_hr3_port_mode_e { 25 /* WARNING: values given match hardware register; do not modify */ 26 SOC_HR3_PORT_MODE_QUAD = 0, 27 SOC_HR3_PORT_MODE_TRI_012 = 1, 28 SOC_HR3_PORT_MODE_TRI_023 = 2, 29 SOC_HR3_PORT_MODE_DUAL = 3, 30 SOC_HR3_PORT_MODE_SINGLE = 4 31 }; 32 33 enum soc_hr3_port_ratio_e { 34 SOC_HR3_PORT_RATIO_SINGLE, 35 SOC_HR3_PORT_RATIO_SINGLE_XAUI, 36 SOC_HR3_PORT_RATIO_DUAL_1_1, 37 SOC_HR3_PORT_RATIO_DUAL_2_1, 38 SOC_HR3_PORT_RATIO_DUAL_1_2, 39 SOC_HR3_PORT_RATIO_DUAL_2_2, 40 SOC_HR3_PORT_RATIO_TRI_012_1_1_2, 41 SOC_HR3_PORT_RATIO_QUAD, 42 SOC_HR3_PORT_RATIO_OCTAL, 43 SOC_HR3_PORT_RATIO_NONE, 44 SOC_HR3_PORT_RATIO_COUNT 45 }; 46 47 enum soc_hr3_port_core_type_e { 48 SOC_HR3_PORT_CORE_TYPE_TSC, 49 SOC_HR3_PORT_CORE_TYPE_QTC, 50 SOC_HR3_PORT_CORE_TYPE_COUNT 51 }; 52 53 54 enum HR3_VLXL_HASH_KEY_TYPE { 55 /* WARNING: values given match hardware register; do not modify */ 56 HR3_VLXLT_HASH_KEY_TYPE_IVID_OVID = 0, 57 HR3_VLXLT_HASH_KEY_TYPE_OTAG = 1, 58 HR3_VLXLT_HASH_KEY_TYPE_ITAG = 2, 59 HR3_VLXLT_HASH_KEY_TYPE_VLAN_MAC = 3, 60 HR3_VLXLT_HASH_KEY_TYPE_OVID = 4, 61 HR3_VLXLT_HASH_KEY_TYPE_IVID = 5, 62 HR3_VLXLT_HASH_KEY_TYPE_PRI_CFI = 6, 63 HR3_VLXLT_HASH_KEY_TYPE_HPAE = 7, 64 HR3_VLXLT_HASH_KEY_TYPE_PAYLOAD_IVID_OVID = 8, 65 HR3_VLXLT_HASH_KEY_TYPE_PAYLOAD_OTAG = 9, 66 HR3_VLXLT_HASH_KEY_TYPE_PAYLOAD_ITAG = 10, 67 HR3_VLXLT_HASH_KEY_TYPE_PAYLOAD_OVID = 11, 68 HR3_VLXLT_HASH_KEY_TYPE_PAYLOAD_IVID = 12, 69 HR3_VLXLT_HASH_KEY_TYPE_PAYLOAD_COUNT 70 }; 71 72 #define HR3LITE_LPM_WAR 73 74 #ifdef HR3LITE_LPM_WAR 75 #define NEED_HR3LITE_LPM_SHADOW(_mem) \ 76 (((_mem) == L3_DEFIPm) || ((_mem) == L3_DEFIP_DATA_ONLYm) || \ 77 ((_mem) == L3_DEFIP_HIT_ONLYm)) 78 #define IS_HR3LITE_LPM_SHADOW_HIT_INDEX(_id) \ 79 (((_id) >= 32) && ((_id) <= 63)) 80 #define HR3LITE_LPM_HIT_INDEX2(_id) \ 81 (IS_HR3LITE_LPM_SHADOW_HIT_INDEX((_id)) ? (512 + ((_id) - 32)) : (-1)) 82 #endif /* HR3LITE_LPM_WAR*/ 83 84 #define HR3_L3_IIF_HW_SIZE 512 85 86 extern int soc_hurricane3_chip_sku_get(int unit, int *sku); 87 extern int soc_hurricane3_port_config_init(int unit, uint16 dev_id); 88 extern int soc_hurricane3_mem_config(int unit, int dev_id); 89 90 extern int soc_hurricane3_chip_reset(int unit); 91 extern int soc_greyhound_tsc_reset(int unit); 92 93 extern int soc_hr3_temperature_monitor_get(int unit, 94 int temperature_max, 95 soc_switch_temperature_monitor_t *temperature_array, 96 int *temperature_count); 97 98 extern void soc_hr3_l2_overflow_interrupt_handler(int unit); 99 extern int soc_hr3_l2_overflow_intr_disable(int unit); 100 extern int soc_hr3_l2_overflow_intr_enable(int unit); 101 extern int soc_hr3_l2_overflow_fill(int unit, uint8 zeros_or_ones); 102 extern int soc_hr3_l2_overflow_sync_init(int unit); 103 extern void soc_hr3_l2_overflow_sync(int unit); 104 extern int soc_hr3_l2_overflow_sync_cleanup(int unit); 105 extern int soc_hr3_l2_overflow_start(int unit); 106 extern int soc_hr3_l2_overflow_stop(int unit); 107 108 109 extern soc_functions_t soc_hurricane3_drv_funs; 110 111 extern int _soc_hurricane3_features(int unit, soc_feature_t feature); 112 113 typedef int (*soc_hr3_oam_handler_t)(int unit, 114 soc_field_t fault_field); 115 typedef int (*soc_hr3_oam_ser_handler_t)(int unit, 116 soc_mem_t mem, int index); 117 extern void soc_hr3_oam_ser_handler_register(int unit, soc_hr3_oam_ser_handler_t handler); 118 extern void soc_hr3_oam_handler_register(int unit, soc_hr3_oam_handler_t handler); 119 extern void soc_hr3_ser_register(int unit); 120 extern int soc_hr3_ser_enable_all(int unit, int enable); 121 extern int soc_hr3_oam_ser_process(int unit, soc_mem_t mem, int index); 122 extern int _soc_hr3_process_l2_overflow(int unit); 123 extern int soc_hr3_tcam_ser_init(int unit); 124 extern int soc_hr3_process_oam_interrupt(int unit); 125 extern int _soc_hr3_mem_parity_control(int unit, soc_mem_t mem, 126 int copyno, int enable); 127 #ifdef SER_TR_TEST_SUPPORT 128 extern void soc_hr3_ser_test_register(int unit); 129 extern int ser_test_hr3_mem_index_remap( 130 int unit, ser_test_data_t *test_data, int *mem_has_ecc); 131 #endif /* SER_TR_TEST_SUPPORT */ 132 133 134 extern uint32 soc_hr3_vlan_xlate_hash(int unit, int hash_sel, int key_nbits, 135 void *base_entry, uint8 *key); 136 137 extern int soc_hr3_vlan_xlate_base_entry_to_key(int unit, uint32 *entry, 138 uint8 *key); 139 #ifdef INCLUDE_AVS 140 extern int soc_hr3_avs_init(int unit); 141 #endif 142 143 extern int soc_hurricane3_sbus_tsc_block(int unit, int phy_port, int *blk); 144 extern int soc_hurricane3_tsc_reset(int unit); 145 146 extern int soc_hurricane3_pgw_rx_fifo_reset(int unit, int port, int reset); 147 148 extern int soc_hurricane3_tsc_core_reset(int unit, int port, int reset_delay_us); 149 150 #endif /* !_SOC_HURRICANE3_H_ */