higig.h (31874B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * File: higig.h 8 */ 9 10 #include <soc/defs.h> 11 #include <soc/enet.h> 12 13 #ifndef _SOC_HIGIG_H 14 #define _SOC_HIGIG_H 15 16 #if defined(BCM_XGS_SUPPORT) || \ 17 defined(BCM_PETRA_SUPPORT) || defined(BCM_DNX_SUPPORT) 18 19 /**************************************************************************** 20 * Higig Header Format 21 * 22 * On BCM5670/BCM5675 (Hercules/Hercules1.5), to send or receive packets 23 * on an HG port, the following HIGIG header is always prepended to 24 * an UNTAGGED ethernet frame. 25 * 26 * ANSI only permits signed or unsigned int for bit field type. This 27 * structure will only work for compilers for which uint32 is unsigned 28 * int, and which completely pack bit fields beginning at the MSbit for 29 * big-endian machines and at the LSbit for little-endian machines. 30 * 31 * NOTE: these structures already put the the individual bytes in memory 32 * in big endian order for both big- and little-endian machines, so no 33 * further swapping is required. 34 */ 35 36 typedef union soc_higig_hdr_u { 37 struct { 38 uint8 bytes[12]; 39 } overlay0; 40 41 #if defined(LE_HOST) 42 43 struct { /* Byte # */ 44 uint32 start:8; /* 0 */ 45 uint32 hgi:8; /* 1 */ 46 uint32 vlan_id_hi:4; /* 2 */ 47 uint32 vlan_cfi:1; 48 uint32 vlan_pri:3; 49 uint32 vlan_id_lo:8; /* 3 */ 50 uint32 opcode:3; /* 4 */ 51 uint32 src_mod:5; 52 uint32 src_port:6; /* 5 */ 53 uint32 pfm:2; 54 uint32 cos:3; /* 6 */ 55 uint32 dst_port:5; 56 uint32 dst_mod:5; /* 7 */ 57 uint32 cng:1; 58 uint32 hdr_format:2; 59 uint32 mirror:1; /* 8 */ 60 uint32 mirror_done:1; 61 uint32 mirror_only:1; 62 uint32 ingress_tagged:1; 63 uint32 dst_tgid:3; 64 uint32 dst_t:1; 65 uint32 _rsvd1:8; /* 9 */ 66 uint32 _rsvd2:8; /* 10 */ 67 uint32 _rsvd3:8; /* 11 */ 68 } overlay1; 69 70 struct { /* Byte # */ 71 uint32 _rsvd1:8; /* 0 */ 72 uint32 _rsvd2:8; /* 1 */ 73 uint32 _rsvd3:8; /* 2 */ 74 uint32 _rsvd4:8; /* 3 */ 75 uint32 _rsvd5:8; /* 4 */ 76 uint32 tgid:6; /* 5 */ 77 uint32 _rsvd6:2; 78 uint32 _rsvd7:3; /* 6 */ 79 uint32 l2mc_ptr_lo:5; 80 uint32 l2mc_ptr_hi:5; /* 7 */ 81 uint32 _rsvd8:3; 82 uint32 ctag_hi:8; /* 8 */ 83 uint32 ctag_lo:8; /* 9 */ 84 uint32 _rsvd9:8; /* 10 */ 85 uint32 _rsvd10:8; /* 11 */ 86 } overlay2; 87 88 struct { /* Byte # */ 89 uint32 start:8; /* 0 */ 90 uint32 dst_mod_6:1; /* 1 */ 91 uint32 src_mod_6:1; 92 uint32 hdr_ext_len:3; 93 uint32 cng_hi:1; 94 uint32 hgi:2; 95 uint32 vlan_id_hi:4; /* 2 */ 96 uint32 vlan_cfi:1; 97 uint32 vlan_pri:3; 98 uint32 vlan_id_lo:8; /* 3 */ 99 uint32 opcode:3; /* 4 */ 100 uint32 src_mod:5; 101 uint32 src_port:6; /* 5 */ 102 uint32 pfm:2; 103 uint32 cos:3; /* 6 */ 104 uint32 dst_port:5; 105 uint32 dst_mod:5; /* 7 */ 106 uint32 cng:1; 107 uint32 hdr_format:2; 108 uint32 mirror:1; /* 8 */ 109 uint32 mirror_done:1; 110 uint32 mirror_only:1; 111 uint32 ingress_tagged:1; 112 uint32 dst_tgid:3; 113 uint32 dst_t:1; 114 uint32 vc_label_19_16:4; /* 9 */ 115 uint32 label_present:1; 116 uint32 l3:1; 117 uint32 dst_mod_5:1; 118 uint32 src_mod_5:1; 119 uint32 vc_label_15_8:8; /* 10 */ 120 uint32 vc_label_7_0:8; /* 11 */ 121 } hgp_overlay1; 122 123 struct { /* Byte # */ 124 uint32 start:8; /* 0 */ 125 uint32 dst_mod_6:1; /* 1 */ 126 uint32 src_mod_6:1; 127 uint32 hdr_ext_len:3; 128 uint32 cng_hi:1; 129 uint32 hgi:2; 130 uint32 vlan_id_hi:4; /* 2 */ 131 uint32 vlan_cfi:1; 132 uint32 vlan_pri:3; 133 uint32 vlan_id_lo:8; /* 3 */ 134 uint32 opcode:3; /* 4 */ 135 uint32 src_mod:5; 136 uint32 src_port:6; /* 5 */ 137 uint32 pfm:2; 138 uint32 cos:3; /* 6 */ 139 uint32 dst_port:5; 140 uint32 dst_mod:5; /* 7 */ 141 uint32 cng:1; 142 uint32 hdr_format:2; 143 uint32 mirror:1; /* 8 */ 144 uint32 mirror_done:1; 145 uint32 mirror_only:1; 146 uint32 ingress_tagged:1; 147 uint32 lag_failover:1; 148 uint32 donot_learn:1; 149 uint32 donot_modify:1; 150 uint32 dst_t:1; 151 uint32 vc_label_19_16:4; /* 9 */ 152 uint32 label_present:1; 153 uint32 l3:1; 154 uint32 dst_mod_5:1; 155 uint32 src_mod_5:1; 156 uint32 vc_label_15_8:8; /* 10 */ 157 uint32 vc_label_7_0:8; /* 11 */ 158 } hgp_overlay2; 159 160 #else /* !LE_HOST */ 161 162 struct { /* Byte # */ 163 uint32 start:8; /* 0 */ 164 uint32 hgi:8; /* 1 */ 165 uint32 vlan_pri:3; /* 2 */ 166 uint32 vlan_cfi:1; 167 uint32 vlan_id_hi:4; 168 uint32 vlan_id_lo:8; /* 3 */ 169 uint32 src_mod:5; /* 4 */ 170 uint32 opcode:3; 171 uint32 pfm:2; /* 5 */ 172 uint32 src_port:6; 173 uint32 dst_port:5; /* 6 */ 174 uint32 cos:3; 175 uint32 hdr_format:2; /* 7 */ 176 uint32 cng:1; 177 uint32 dst_mod:5; 178 uint32 dst_t:1; /* 8 */ 179 uint32 dst_tgid:3; 180 uint32 ingress_tagged:1; 181 uint32 mirror_only:1; 182 uint32 mirror_done:1; 183 uint32 mirror:1; 184 uint32 _rsvd1:8; /* 9 */ 185 uint32 _rsvd2:8; /* 10 */ 186 uint32 _rsvd3:8; /* 11 */ 187 } overlay1; 188 189 struct { /* Byte # */ 190 uint32 _rsvd1:8; /* 0 */ 191 uint32 _rsvd2:8; /* 1 */ 192 uint32 _rsvd3:8; /* 2 */ 193 uint32 _rsvd4:8; /* 3 */ 194 uint32 _rsvd5:8; /* 4 */ 195 uint32 _rsvd6:2; /* 5 */ 196 uint32 tgid:6; 197 uint32 l2mc_ptr_lo:5; /* 6 */ 198 uint32 _rsvd7:3; 199 uint32 _rsvd8:3; /* 7 */ 200 uint32 l2mc_ptr_hi:5; 201 uint32 ctag_hi:8; /* 8 */ 202 uint32 ctag_lo:8; /* 9 */ 203 uint32 _rsvd9:8; /* 10 */ 204 uint32 _rsvd10:8; /* 11 */ 205 } overlay2; 206 207 struct { /* Byte # */ 208 uint32 start:8; /* 0 */ 209 uint32 hgi:2; /* 1 */ 210 uint32 cng_hi:1; 211 uint32 hdr_ext_len:3; 212 uint32 src_mod_6:1; 213 uint32 dst_mod_6:1; 214 uint32 vlan_pri:3; /* 2 */ 215 uint32 vlan_cfi:1; 216 uint32 vlan_id_hi:4; 217 uint32 vlan_id_lo:8; /* 3 */ 218 uint32 src_mod:5; /* 4 */ 219 uint32 opcode:3; 220 uint32 pfm:2; /* 5 */ 221 uint32 src_port:6; 222 uint32 dst_port:5; /* 6 */ 223 uint32 cos:3; 224 uint32 hdr_format:2; /* 7 */ 225 uint32 cng:1; 226 uint32 dst_mod:5; 227 uint32 dst_t:1; /* 8 */ 228 uint32 dst_tgid:3; 229 uint32 ingress_tagged:1; 230 uint32 mirror_only:1; 231 uint32 mirror_done:1; 232 uint32 mirror:1; 233 uint32 src_mod_5:1; /* 9 */ 234 uint32 dst_mod_5:1; 235 uint32 l3:1; 236 uint32 label_present:1; 237 uint32 vc_label_19_16:4; 238 uint32 vc_label_15_8:8; /* 10 */ 239 uint32 vc_label_7_0:8; /* 11 */ 240 } hgp_overlay1; 241 242 struct { /* Byte # */ 243 uint32 start:8; /* 0 */ 244 uint32 hgi:2; /* 1 */ 245 uint32 cng_hi:1; 246 uint32 hdr_ext_len:3; 247 uint32 src_mod_6:1; 248 uint32 dst_mod_6:1; 249 uint32 vlan_pri:3; /* 2 */ 250 uint32 vlan_cfi:1; 251 uint32 vlan_id_hi:4; 252 uint32 vlan_id_lo:8; /* 3 */ 253 uint32 src_mod:5; /* 4 */ 254 uint32 opcode:3; 255 uint32 pfm:2; /* 5 */ 256 uint32 src_port:6; 257 uint32 dst_port:5; /* 6 */ 258 uint32 cos:3; 259 uint32 hdr_format:2; /* 7 */ 260 uint32 cng:1; 261 uint32 dst_mod:5; 262 uint32 dst_t:1; /* 8 */ 263 uint32 donot_modify:1; 264 uint32 donot_learn:1; 265 uint32 lag_failover:1; 266 uint32 ingress_tagged:1; 267 uint32 mirror_only:1; 268 uint32 mirror_done:1; 269 uint32 mirror:1; 270 uint32 src_mod_5:1; /* 9 */ 271 uint32 dst_mod_5:1; 272 uint32 l3:1; 273 uint32 label_present:1; 274 uint32 vc_label_19_16:4; 275 uint32 vc_label_15_8:8; /* 10 */ 276 uint32 vc_label_7_0:8; /* 11 */ 277 } hgp_overlay2; 278 279 #endif /* !LE_HOST */ 280 281 } soc_higig_hdr_t; 282 283 #define SOC_HIGIG_HDR_SIZE ((int) sizeof(soc_higig_hdr_t)) 284 285 /* 286 * Higig Header Field Manipulation 287 */ 288 289 typedef enum { 290 /* NOTE: strings in soc_higig_field_names[] must match */ 291 HG_invalid = -1, 292 HG_start = 0, 293 HG_hgi, 294 HG_vlan_tag, /* aggregate of pri, cfi, and id */ 295 HG_vlan_pri, 296 HG_vlan_cfi, 297 HG_vlan_id, 298 HG_src_mod, 299 HG_opcode, 300 HG_pfm, 301 HG_src_port, 302 HG_dst_port, 303 HG_cos, 304 HG_hdr_format, 305 HG_cng, 306 HG_dst_mod, 307 HG_dst_t, 308 HG_dst_tgid, 309 HG_ingress_tagged, 310 HG_mirror_only, 311 HG_mirror_done, 312 HG_mirror, 313 HG_tgid, 314 HG_l2mc_ptr, 315 HG_ctag, 316 HG_hdr_ext_len, /* HG+ fields */ 317 HG_l3, 318 HG_donot_modify, 319 HG_donot_learn, 320 HG_lag_failover, 321 HG_label_present, 322 HG_vc_label, 323 #if defined(BCM_HIGIG2_SUPPORT) 324 HG_tc, /* HG2 fields */ 325 HG_mcst, 326 HG_mgid, 327 HG_lbid, 328 HG_dp, 329 HG_ehv, 330 HG_ppd_type, 331 HG_src_t, 332 HG_multipoint, 333 HG_fwd_type, 334 HG_dst_vp, 335 HG_src_vp, 336 HG_vni, 337 HG_data_container_type, 338 HG_data_container, 339 HG_preserve_dscp, 340 HG_preserve_dot1p, 341 HG_dst_type, 342 HG_src_type, 343 HG_deferred_drop, 344 HG_vxlt_done, 345 HG_deferred_change_pkt_pri, 346 HG_new_pkt_pri, 347 HG_deferred_change_dscp, 348 HG_new_dscp, 349 HG_label_overlay_type, 350 HG_protection_status, 351 HG_replication_id, 352 #endif /* BCM_HIGIG2_SUPPORT */ 353 HG_COUNT 354 } soc_higig_field_t; 355 356 #if defined(BCM_HIGIG2_SUPPORT) 357 #define SOC_HIGIG2_FIELD_NAMES_INIT \ 358 "tc", /* HG2 fields */ \ 359 "mcst", \ 360 "mgid", \ 361 "lbid", \ 362 "dp", \ 363 "ehv", \ 364 "ppd_type", \ 365 "src_t", \ 366 "multipoint", \ 367 "fwd_type", \ 368 "dst_vp", \ 369 "src_vp", \ 370 "vni", \ 371 "data_container_type", \ 372 "data_container", \ 373 "preserve_dscp", \ 374 "preserve_dot1p", \ 375 "dst_type", \ 376 "src_type", \ 377 "deferred_drop", \ 378 "vxlt_done", \ 379 "deferred_change_pkt_pri", \ 380 "new_pkt_pri", \ 381 "deferred_change_dscp", \ 382 "new_dscp", \ 383 "label_overlay_type", \ 384 "protection_status", \ 385 "replication_id", 386 #else 387 #define SOC_HIGIG2_FIELD_NAMES_INIT 388 #endif /* BCM_HIGIG2_SUPPORT */ 389 390 /* NOTE: strings must match soc_higig_field_t */ 391 #define SOC_HIGIG_FIELD_NAMES_INIT \ 392 "start", \ 393 "hgi", \ 394 "vlan_tag", \ 395 "vlan_pri", \ 396 "vlan_cfi", \ 397 "vlan_id", \ 398 "src_mod", \ 399 "opcode", \ 400 "pfm", \ 401 "src_port", \ 402 "dst_port", \ 403 "cos", \ 404 "hdr_format", \ 405 "cng", \ 406 "dst_mod", \ 407 "dst_t", \ 408 "dst_tgid", \ 409 "ingress_tagged", \ 410 "mirror_only", \ 411 "mirror_done", \ 412 "mirror", \ 413 "tgid", \ 414 "l2mc_ptr", \ 415 "ctag", \ 416 "hdr_ext_len", /* HG+ fields */ \ 417 "l3", \ 418 "donot_modify", \ 419 "donot_learn", \ 420 "lag_failover", \ 421 "label_present", \ 422 "vc_label", \ 423 SOC_HIGIG2_FIELD_NAMES_INIT \ 424 NULL 425 426 #ifdef BCM_HIGIG2_SUPPORT 427 428 #define SOC_HIGIG2_START 0xfc /* Higig2 Module Header for CMIC TX */ 429 430 typedef union soc_higig2_hdr_u { 431 struct { 432 uint8 bytes[16]; 433 } overlay0; 434 435 #if defined(LE_HOST) 436 437 struct { /* Byte # */ 438 /* "Legacy" PPD Overlay 1 */ 439 uint32 start:8; /* 0 */ 440 uint32 tc:4; /* 1 */ 441 uint32 mcst:1; 442 uint32 _rsvd1:3; 443 uint32 dst_mod:8; /* 2 */ 444 uint32 dst_port:8; /* 3 */ 445 uint32 src_mod:8; /* 4 */ 446 uint32 src_port:8; /* 5 */ 447 uint32 lbid:8; /* 6 */ 448 uint32 ppd_type:3; /* 7 */ 449 uint32 _rsvd2:2; 450 uint32 ehv:1; 451 uint32 dp:2; 452 uint32 mirror:1; /* 8 */ 453 uint32 mirror_done:1; 454 uint32 mirror_only:1; 455 uint32 ingress_tagged:1; 456 uint32 lag_failover:1; 457 uint32 donot_learn:1; 458 uint32 donot_modify:1; 459 uint32 dst_t:1; 460 uint32 vc_label_19_16:4; /* 9 */ 461 uint32 label_present:1; 462 uint32 l3:1; 463 uint32 label_overlay_type:2; 464 uint32 vc_label_15_8:8; /* 10 */ 465 uint32 vc_label_7_0:8; /* 11 */ 466 uint32 vlan_id_hi:4; /* 12 */ 467 uint32 vlan_cfi:1; 468 uint32 vlan_pri:3; 469 uint32 vlan_id_lo:8; /* 13 */ 470 uint32 opcode:3; /* 14 */ 471 uint32 preserve_dot1p:1; 472 uint32 preserve_dscp:1; 473 uint32 src_t:1; 474 uint32 pfm:2; 475 uint32 _rsvd5:5; /* 15 */ 476 uint32 hdr_ext_len:3; 477 } ppd_overlay1; 478 479 struct { /* Byte # */ 480 /* "Legacy" PPD Overlay 2 */ 481 uint32 start:8; /* 0 */ 482 uint32 tc:4; /* 1 */ 483 uint32 mcst:1; 484 uint32 _rsvd1:3; 485 uint32 dst_mod:8; /* 2 */ 486 uint32 dst_port:8; /* 3 */ 487 uint32 src_mod:8; /* 4 */ 488 uint32 src_port:8; /* 5 */ 489 uint32 lbid:8; /* 6 */ 490 uint32 ppd_type:3; /* 7 */ 491 uint32 _rsvd2:2; 492 uint32 ehv:1; 493 uint32 dp:2; 494 uint32 ctag_hi:8; /* 8 */ 495 uint32 ctag_lo:8; /* 9 */ 496 uint32 _rsvd3:8; /* 10 */ 497 uint32 _rsvd4:8; /* 11 */ 498 uint32 vlan_id_hi:4; /* 12 */ 499 uint32 vlan_cfi:1; 500 uint32 vlan_pri:3; 501 uint32 vlan_id_lo:8; /* 13 */ 502 uint32 opcode:3; /* 14 */ 503 uint32 _rsvd5:2; 504 uint32 src_t:1; 505 uint32 pfm:2; 506 uint32 _rsvd6:5; /* 15 */ 507 uint32 hdr_ext_len:3; 508 } ppd_overlay2; 509 510 struct { /* Byte # */ 511 /* "Next Gen" PPD Overlay 3 */ 512 uint32 start:8; /* 0 */ 513 uint32 tc:4; /* 1 */ 514 uint32 mcst:1; 515 uint32 _rsvd1:3; 516 uint32 dst_mod:8; /* 2 */ 517 uint32 dst_port:8; /* 3 */ 518 uint32 src_mod:8; /* 4 */ 519 uint32 src_port:8; /* 5 */ 520 uint32 lbid:8; /* 6 */ 521 uint32 ppd_type:3; /* 7 */ 522 uint32 _rsvd2:2; 523 uint32 ehv:1; 524 uint32 dp:2; 525 uint32 vni_mid:2; /* 8 */ 526 uint32 fwd_type:5; 527 uint32 multipoint:1; 528 uint32 vni_low:8; /* 9 */ 529 uint32 dst_vp_high:8; /* 10 */ 530 uint32 dst_vp_low:8; /* 11 */ 531 uint32 src_vp_high:8; /* 12 */ 532 uint32 src_vp_low:8; /* 13 */ 533 uint32 opcode:3; /* 14 */ 534 uint32 protection_status:1; 535 uint32 lag_failover:1; 536 uint32 donot_learn:1; 537 uint32 donot_modify:1; 538 uint32 mirror:1; 539 uint32 source_type:1; /* 15 */ 540 uint32 dest_type:1; 541 uint32 preserve_dot1p:1; 542 uint32 preserve_dscp:1; 543 uint32 vni_high:4; 544 } ppd_overlay3; 545 546 struct { /* Byte # */ 547 /* "Offload Engine" PPD Overlay 4 */ 548 uint32 start:8; /* 0 */ 549 uint32 tc:4; /* 1 */ 550 uint32 mcst:1; 551 uint32 _rsvd1:3; 552 uint32 dst_mod:8; /* 2 */ 553 uint32 dst_port:8; /* 3 */ 554 uint32 src_mod:8; /* 4 */ 555 uint32 src_port:8; /* 5 */ 556 uint32 lbid:8; /* 6 */ 557 uint32 ppd_type:3; /* 7 */ 558 uint32 _rsvd2:2; 559 uint32 ehv:1; 560 uint32 dp:2; 561 562 union { 563 /* The data container has several sub-formats */ 564 struct { /* Byte # */ 565 /* Abstract data container */ 566 uint8 bytes[4]; /* 8-11 */ 567 } abstract; 568 569 struct { /* Byte # */ 570 uint32 ctag_hi:8; /* 8 */ 571 uint32 ctag_lo:8; /* 9 */ 572 uint32 deferred_change_dscp:1; /* 10 */ 573 uint32 new_pkt_pri:3; 574 uint32 deferred_change_pkt_pri:1; 575 uint32 vxlt_done:2; 576 uint32 deferred_drop:1; 577 uint32 _rsvd1:2; /* 11 */ 578 uint32 new_dscp:6; 579 } offload_engine; 580 } data_container; 581 582 uint32 src_vp_high:8; /* 12 */ 583 uint32 src_vp_low:8; /* 13 */ 584 uint32 opcode:3; /* 14 */ 585 uint32 source_type:1; 586 uint32 _rsvd3:1; 587 uint32 donot_learn:1; 588 uint32 preserve_dot1p:1; 589 uint32 preserve_dscp:1; 590 uint32 data_container_type:4; /* 15 */ 591 uint32 _rsvd4:4; 592 } ppd_overlay4; 593 594 #else /* !LE_HOST */ 595 596 struct { /* Byte # */ 597 /* "Legacy" PPD Overlay 1 */ 598 uint32 start:8; /* 0 */ 599 uint32 _rsvd1:3; /* 1 */ 600 uint32 mcst:1; 601 uint32 tc:4; 602 uint32 dst_mod:8; /* 2 */ 603 uint32 dst_port:8; /* 3 */ 604 uint32 src_mod:8; /* 4 */ 605 uint32 src_port:8; /* 5 */ 606 uint32 lbid:8; /* 6 */ 607 uint32 dp:2; /* 7 */ 608 uint32 ehv:1; 609 uint32 _rsvd2:2; 610 uint32 ppd_type:3; 611 uint32 dst_t:1; /* 8 */ 612 uint32 donot_modify:1; 613 uint32 donot_learn:1; 614 uint32 lag_failover:1; 615 uint32 ingress_tagged:1; 616 uint32 mirror_only:1; 617 uint32 mirror_done:1; 618 uint32 mirror:1; 619 uint32 label_overlay_type:2; /* 9 */ 620 uint32 l3:1; 621 uint32 label_present:1; 622 uint32 vc_label_19_16:4; 623 uint32 vc_label_15_8:8; /* 10 */ 624 uint32 vc_label_7_0:8; /* 11 */ 625 uint32 vlan_pri:3; /* 12 */ 626 uint32 vlan_cfi:1; 627 uint32 vlan_id_hi:4; 628 uint32 vlan_id_lo:8; /* 13 */ 629 uint32 pfm:2; /* 14 */ 630 uint32 src_t:1; 631 uint32 preserve_dscp:1; 632 uint32 preserve_dot1p:1; 633 uint32 opcode:3; 634 uint32 hdr_ext_len:3; /* 15 */ 635 uint32 _rsvd5:5; 636 } ppd_overlay1; 637 638 struct { /* Byte # */ 639 /* "Legacy" PPD Overlay 2 */ 640 uint32 start:8; /* 0 */ 641 uint32 _rsvd1:3; /* 1 */ 642 uint32 mcst:1; 643 uint32 tc:4; 644 uint32 dst_mod:8; /* 2 */ 645 uint32 dst_port:8; /* 3 */ 646 uint32 src_mod:8; /* 4 */ 647 uint32 src_port:8; /* 5 */ 648 uint32 lbid:8; /* 6 */ 649 uint32 dp:2; /* 7 */ 650 uint32 ehv:1; 651 uint32 _rsvd2:2; 652 uint32 ppd_type:3; 653 uint32 ctag_hi:8; /* 8 */ 654 uint32 ctag_lo:8; /* 9 */ 655 uint32 _rsvd3:8; /* 10 */ 656 uint32 _rsvd4:8; /* 11 */ 657 uint32 vlan_pri:3; /* 12 */ 658 uint32 vlan_cfi:1; 659 uint32 vlan_id_hi:4; 660 uint32 vlan_id_lo:8; /* 13 */ 661 uint32 pfm:2; /* 14 */ 662 uint32 src_t:1; 663 uint32 _rsvd5:2; 664 uint32 opcode:3; 665 uint32 hdr_ext_len:3; /* 15 */ 666 uint32 _rsvd6:5; 667 } ppd_overlay2; 668 669 struct { /* Byte # */ 670 /* "Next Gen" PPD Overlay 3 */ 671 uint32 start:8; /* 0 */ 672 uint32 _rsvd1:3; /* 1 */ 673 uint32 mcst:1; 674 uint32 tc:4; 675 uint32 dst_mod:8; /* 2 */ 676 uint32 dst_port:8; /* 3 */ 677 uint32 src_mod:8; /* 4 */ 678 uint32 src_port:8; /* 5 */ 679 uint32 lbid:8; /* 6 */ 680 uint32 dp:2; /* 7 */ 681 uint32 ehv:1; 682 uint32 _rsvd2:2; 683 uint32 ppd_type:3; 684 uint32 multipoint:1; /* 8 */ 685 uint32 fwd_type:5; 686 uint32 vni_mid:2; 687 uint32 vni_low:8; /* 9 */ 688 uint32 dst_vp_high:8; /* 10 */ 689 uint32 dst_vp_low:8; /* 11 */ 690 uint32 src_vp_high:8; /* 12 */ 691 uint32 src_vp_low:8; /* 13 */ 692 uint32 mirror:1; /* 14 */ 693 uint32 donot_modify:1; 694 uint32 donot_learn:1; 695 uint32 lag_failover:1; 696 uint32 protection_status:1; 697 uint32 opcode:3; 698 uint32 vni_high:4; /* 15 */ 699 uint32 preserve_dscp:1; 700 uint32 preserve_dot1p:1; 701 uint32 dest_type:1; 702 uint32 source_type:1; 703 } ppd_overlay3; 704 705 struct { /* Byte # */ 706 /* "Offload Engine" PPD Overlay 4 */ 707 uint32 start:8; /* 0 */ 708 uint32 _rsvd1:3; /* 1 */ 709 uint32 mcst:1; 710 uint32 tc:4; 711 uint32 dst_mod:8; /* 2 */ 712 uint32 dst_port:8; /* 3 */ 713 uint32 src_mod:8; /* 4 */ 714 uint32 src_port:8; /* 5 */ 715 uint32 lbid:8; /* 6 */ 716 uint32 dp:2; /* 7 */ 717 uint32 ehv:1; 718 uint32 _rsvd2:2; 719 uint32 ppd_type:3; 720 721 union { 722 /* The data container has several sub-formats */ 723 struct { /* Byte # */ 724 /* Abstract data container */ 725 uint8 bytes[4]; /* 8-11 */ 726 } abstract; 727 728 struct { /* Byte # */ 729 uint32 ctag_hi:8; /* 8 */ 730 uint32 ctag_lo:8; /* 9 */ 731 uint32 deferred_drop:1; /* 10 */ 732 uint32 vxlt_done:2; 733 uint32 deferred_change_pkt_pri:1; 734 uint32 new_pkt_pri:3; 735 uint32 deferred_change_dscp:1; 736 uint32 new_dscp:6; /* 11 */ 737 uint32 _rsvd1:2; 738 } offload_engine; 739 } data_container; 740 741 uint32 src_vp_high:8; /* 12 */ 742 uint32 src_vp_low:8; /* 13 */ 743 uint32 preserve_dscp:1; /* 14 */ 744 uint32 preserve_dot1p:1; 745 uint32 donot_learn:1; 746 uint32 _rsvd3:1; 747 uint32 source_type:1; 748 uint32 opcode:3; 749 uint32 _rsvd4:4; /* 15 */ 750 uint32 data_container_type:4; 751 } ppd_overlay4; 752 #endif /* !LE_HOST */ 753 754 } soc_higig2_hdr_t; 755 756 #define SOC_HIGIG2_LABEL_OVERLAY_TYPE_VC_LABEL 0 757 #define SOC_HIGIG2_LABEL_OVERLAY_TYPE_SYSTEM_INGRESS_PORT 1 758 #define SOC_HIGIG2_LABEL_OVERLAY_TYPE_MIRROR_CLASS_TAG 2 759 #define SOC_HIGIG2_LABEL_OVERLAY_TYPE_QTAG 3 760 761 #define SOC_HIGIG2_HDR_SIZE ((int) sizeof(soc_higig2_hdr_t)) 762 763 extern uint32 soc_higig2_field_get(int unit, soc_higig2_hdr_t *hg, 764 soc_higig_field_t field); 765 extern void soc_higig2_field_set(int unit, soc_higig2_hdr_t *hg, 766 soc_higig_field_t field, uint32 val); 767 extern void soc_higig2_dump(int unit, char *pfx, soc_higig2_hdr_t *hg); 768 769 #endif /* BCM_HIGIG2_SUPPORT */ 770 771 extern soc_higig_field_t soc_higig_name_to_field(int unit, char *name); 772 extern char *soc_higig_field_to_name(int unit, soc_higig_field_t f); 773 774 extern uint32 soc_higig_field_get(int unit, soc_higig_hdr_t *hg, 775 soc_higig_field_t field); 776 extern void soc_higig_field_set(int unit, soc_higig_hdr_t *hg, 777 soc_higig_field_t field, uint32 val); 778 779 extern void soc_higig_dump(int unit, char *pfx, soc_higig_hdr_t *hg); 780 781 /* HIGIG Header field default values */ 782 783 /* default SOP Symbol */ 784 #define SOC_HIGIG_START 0xfb /* Default Start for BIGMAC */ 785 786 /* HGI */ 787 #define SOC_HIGIG_HGI 0x80 /* Default HGI */ 788 #define SOC_HIGIG_HGI_MASK 0xc0 /* HGI field mask */ 789 790 /* Module header Op-Codes */ 791 #define SOC_HIGIG_OP_CPU 0x00 /* CPU Frame */ 792 #define SOC_HIGIG_OP_UC 0x01 /* Unicast Frame */ 793 #define SOC_HIGIG_OP_BC 0x02 /* Broadcast or DLF frame */ 794 #define SOC_HIGIG_OP_MC 0x03 /* Multicast Frame */ 795 #define SOC_HIGIG_OP_IPMC 0x04 /* IP Multicast Frame */ 796 797 #define SOC_HIGIG_DST_MOD_CPU 0x00 798 799 /* Header Format */ 800 #define SOC_HIGIG_HDR_DEFAULT 0x00 801 #define SOC_HIGIG_HDR_CLASS_TAG 0x01 802 #define SOC_HIGIG_HDR_EXT_LEN 0x02 803 #define SOC_HIGIG_HDR_RSVD2 0x03 804 805 #if defined(BCM_XGS_SUPPORT) 806 807 /* XGS Frame format */ 808 typedef struct xgs_pkt_s { 809 soc_higig_hdr_t higig_hdr; 810 enet_hdr_t enet_hdr; 811 } xgs_pkt_t; 812 813 /* Hercules Header modes */ 814 #define SOC_XGS_ENCAP_IEEE 0x00 /* Standard IEEE 802.3 (Default) */ 815 #define SOC_XGS_ENCAP_HIGIG 0x01 /* Broadcom HIGIG Format */ 816 #define SOC_XGS_ENCAP_ALLYR 0x02 /* BCM5632 compatible mode */ 817 #define SOC_XGS_ENCAP_RSVP 0x03 /* Reserved */ 818 819 /**************************************************************************** 820 * BCM5632 Header Format 821 * When the MAC is in BCM5632 header mode, we prepend the following 822 * two words of data to a standard 802.3 Ethernet Frame. 823 * 824 * ANSI only permits signed or unsigned int for bit field type. This 825 * structure will only work for compilers for which uint32 is unsigned 826 * int, and which completely pack bit fields beginning at the MSbit for 827 * big-endian machines and at the LSbit for little-endian machines. 828 * 829 * NOTE: these structures already put the the individual bytes in memory 830 * in big endian order for both big- and little-endian machines, so no 831 * further swapping is required. 832 */ 833 834 typedef union soc_bcm5632_hdr_u { 835 struct { 836 uint8 bytes[8]; 837 } overlay0; 838 839 #if defined(LE_HOST) 840 841 struct { /* Byte # */ 842 uint32 d_portid:6; /* 0 */ 843 uint32 _rsvd1:2; 844 uint32 _rsvd2:8; /* 1 */ 845 uint32 _rsvd3:8; /* 2 */ 846 uint32 _rsvd4:8; /* 3 */ 847 848 uint32 start:8; /* 4 */ 849 uint32 length_hi:8; /* 5 */ 850 uint32 length_lo:8; /* 6 */ 851 uint32 s_portid:6; /* 7 */ 852 uint32 _rsvd5:2; 853 } overlay1; 854 855 #else /* !LE_HOST */ 856 857 struct { /* Byte # */ 858 uint32 _rsvd1:2; /* 0 */ 859 uint32 d_portid:6; 860 uint32 _rsvd2:8; /* 1 */ 861 uint32 _rsvd3:8; /* 2 */ 862 uint32 _rsvd4:8; /* 3 */ 863 864 uint32 start:8; /* 4 */ 865 uint32 length_hi:8; /* 5 */ 866 uint32 length_lo:8; /* 6 */ 867 uint32 _rsvd5:2; /* 7 */ 868 uint32 s_portid:6; 869 } overlay1; 870 871 #endif 872 873 } soc_bcm5632_hdr_t; 874 875 #define SOC_BCM5632_HDR_SIZE ((int) sizeof(soc_bcm5632_hdr_t)) 876 877 /* BCM5632 Frame format */ 878 typedef struct b5632_pkt_s { 879 soc_bcm5632_hdr_t b5632_hdr; 880 enet_hdr_t enet_hdr; 881 } b5632_pkt_t; 882 883 /* BCM5632 Header field default values */ 884 885 /* HGI */ 886 #define SOC_BCM5632_HGI 0x00 /* Default HGI for BCM5632 */ 887 888 #endif /* defined(BCM_XGS_SUPPORT) */ 889 890 891 #define SOC_HIGIG_HDR_MAX_MODID 0xFF 892 #define SOC_HIGIG_E2ECC_MAX_PORT_STATUS 64 893 894 /* E2ECC Header */ 895 typedef union soc_higig_e2ecc_hdr_u { 896 struct { 897 uint8 bytes[32]; 898 } overlay0; 899 900 struct { 901 uint32 words[8]; 902 } overlay1; 903 904 } soc_higig_e2ecc_hdr_t; 905 906 907 #endif /* defined(BCM_XGS_SUPPORT) || defined(BCM_PETRA_SUPPORT)*/ 908 909 #endif /* !_SOC_HIGIG_H */