helix5_tdm.h (6347B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * File: helix5_tdm.h 8 */ 9 10 #ifndef _SOC_HELIX5_TDM_H_ 11 #define _SOC_HELIX5_TDM_H_ 12 13 #include <soc/esw/port.h> 14 15 /*** START SDK API COMMON CODE ***/ 16 17 /* TD3 specific defines */ 18 #define HELIX5_TDM_PORTS_PER_PBLK 4 19 #define HELIX5_TDM_PBLKS_PER_PIPE 19 20 #define HELIX5_TDM_PBLKS_PER_HPIPE 8 21 #define HELIX5_TDM_PIPES_PER_DEV 1 22 #define HELIX5_TDM_HPIPES_PER_PIPE 2 23 24 #define HELIX5_TDM_PBLKS_PER_DEV \ 25 (HELIX5_TDM_PBLKS_PER_PIPE * HELIX5_TDM_PIPES_PER_DEV) 26 #define HELIX5_TDM_GPORTS_PER_HPIPE \ 27 (HELIX5_TDM_PORTS_PER_PBLK * HELIX5_TDM_PBLKS_PER_HPIPE) 28 #define HELIX5_TDM_GPORTS_PER_PIPE \ 29 (HELIX5_TDM_PORTS_PER_PBLK * HELIX5_TDM_PBLKS_PER_PIPE) 30 #define HELIX5_TDM_GPORTS_PER_DEV \ 31 (HELIX5_TDM_GPORTS_PER_PIPE * HELIX5_TDM_PIPES_PER_DEV) 32 33 /* Physical port */ 34 /* 64 General device port + 1 CPU + 1 FAE + 1 Loopback */ 35 #define HELIX5_TDM_PHY_PORTS_PER_PIPE \ 36 (HELIX5_TDM_GPORTS_PER_PIPE + 3) 37 #define HELIX5_TDM_PHY_PORTS_PER_DEV \ 38 (HELIX5_TDM_PHY_PORTS_PER_PIPE * HELIX5_TDM_PIPES_PER_DEV) 39 #define HELIX5_TDM_PHY_MGMT0 999 /* unused */ 40 #define HELIX5_TDM_PHY_MGMT1 999 /* unused */ 41 #define HELIX5_TDM_DEV_MGMT0 999 /* unused */ 42 #define HELIX5_TDM_DEV_MGMT1 999 /* unused */ 43 44 /* MMU ancillary port number */ 45 #define HX5_NUM_EXT_PORTS 79 46 #define HELIX5_TDM_MMU_OVSB_TOKEN 0x48 47 #define HELIX5_TDM_MMU_NULL_TOKEN 0x49 48 #define HELIX5_TDM_MMU_PURG_TOKEN 0x4A 49 #define HELIX5_TDM_MMU_UNUSED_TOKEN 0xFF 50 #define HELIX5_TDM_MMU_MGMT1_TOKEN 0x3f 51 52 /* IDB ancillary port number */ 53 #define HELIX5_TDM_IDB_OVSB_TOKEN 0x48 54 #define HELIX5_TDM_IDB_NULL_TOKEN 0x49 55 #define HELIX5_TDM_IDB_SBUS_TOKEN 0x4A 56 #define HELIX5_TDM_IDB_OPT1_TOKEN 0x4A 57 #define HELIX5_TDM_IDB_OPT2_TOKEN 0x4B 58 #define HELIX5_TDM_IDB_UNUSED_TOKEN 0xFF 59 #define HELIX5_TDM_IDB_FAE_TOKEN 0x45 60 61 /* Oversub groups */ 62 #define HELIX5_TDM_OVS_GROUPS_PER_PIPE 12 63 #define HELIX5_TDM_OVS_GROUPS_PER_HPIPE 6 64 #define HELIX5_TDM_OVS_GROUP_LENGTH 12 65 #define HELIX5_OVS_HPIPE_COUNT_PER_PIPE 2 66 67 /*** START SDK API COMMON CODE ***/ 68 extern void _soc_hx5_tdm_print_port_map(int unit, soc_port_map_type_t *port_map); 69 extern void _soc_hx5_tdm_print_tdm_info(int unit, soc_tdm_schedule_t *tdm_info, 70 int hpipe, int is_ing); 71 extern void _soc_hx5_tdm_print_port_resource(int unit, 72 soc_port_resource_t *port_info, int entry_num); 73 extern void _soc_hx5_tdm_print_schedule_state(int unit, 74 soc_port_schedule_state_t *sch_info); 75 extern int _soc_hx5_tdm_calculation(int unit, 76 soc_port_schedule_state_t *sch_info); 77 extern int _soc_hx5_tdm_set_idb_calendar(int unit, 78 soc_port_schedule_state_t *sch_info); 79 extern int _soc_hx5_tdm_set_idb_hsp(int unit, 80 soc_port_schedule_state_t *sch_info); 81 extern int _soc_hx5_tdm_set_idb_pkt_calendar(int unit, 82 soc_port_schedule_state_t *sch_info); 83 extern int _soc_hx5_tdm_set_idb_ppe_credit(int unit, 84 soc_port_schedule_state_t *sch_info, 85 int full_credit_threshold_0, 86 int opp_credit_threshold_0, 87 int full_credit_threshold_1, 88 int opp_credit_threshold_1 ); 89 extern int _soc_hx5_tdm_set_idb_opportunistic(int unit, 90 soc_port_schedule_state_t *sch_info, 91 int cpu_op_en, int lb_opp_en, int opp1_port_en, 92 int opp2_port_en, int opp_ovr_sub_en); 93 extern int _soc_hx5_tdm_set_ovs_group_sel(int unit, 94 soc_port_schedule_state_t *sch_info, 95 int set_idb, int set_mmu); 96 extern int _soc_hx5_tdm_set_ovs_group(int unit, 97 soc_port_schedule_state_t *sch_info); 98 extern int _soc_hx5_tdm_set_mmu_calendar(int unit, 99 soc_port_schedule_state_t *sch_info); 100 extern int _soc_hx5_tdm_set_mmu_hsp(int unit, 101 soc_port_schedule_state_t *sch_info); 102 extern int _soc_hx5_tdm_set_mmu_opportunistic(int unit, 103 soc_port_schedule_state_t *sch_info, 104 int cpu_op_en, int lb_opp_en, int opp1_port_en, 105 int opp2_port_en, int opp_ovr_sub_en); 106 107 extern int soc_hx5_tdm_set_idb_dpp_ctrl(int unit, 108 soc_port_schedule_state_t *schedule_state, 109 int credits); 110 extern int soc_hx5_tdm_init(int unit, soc_port_schedule_state_t *schedule_state); 111 112 extern int _soc_hx5_tdm_get_mport_2_hp_num( uint32 mmu_port_num); 113 114 extern int _soc_hx5_tdm_get_cal_id( uint32 phy_num); 115 116 extern int _soc_hx5_tdm_get_phy_port_base ( uint32 pm_num); 117 118 extern int _soc_hx5_tdm_get_sis_port_spacing_e(int unit, int phy_port); 119 120 extern void soc_hx5_tdm_get_port_ratio(int unit, 121 soc_port_schedule_state_t *sch_info, 122 int pm_num, int *pm_mode, int prev_or_new); 123 extern void _soc_hx5_tdm_get_pipe_map(int unit, 124 soc_port_schedule_state_t *sch_info, 125 uint32 *pipe_map); 126 extern void _soc_hx5_tdm_get_ovs_pipe_map(int unit, 127 soc_port_schedule_state_t *sch_info, 128 uint32 *ovs_pipe_map); 129 extern int _soc_hx5_tdm_get_speed_ovs_class(int unit, int speed); 130 extern int _soc_hx5_tdm_get_same_port_spacing_e(int unit, int speed); 131 132 extern void soc_helix5_port_schedule_speed_remap(int unit, 133 soc_port_schedule_state_t *port_schedule_state); 134 135 /*** END SDK API COMMON CODE ***/ 136 137 #endif /* !_SOC_HELIX5_TDM_H_ */