helix5.h (25234B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * File: helix5.h 8 */ 9 10 #ifndef _SOC_HELIX5_H_ 11 #define _SOC_HELIX5_H_ 12 13 #include <soc/drv.h> 14 #include <soc/trident3.h> 15 #include <soc/helix5_tdm.h> 16 17 /* **************** TDM-related Macors and structs adopted from Tomahawk ---start************ */ 18 /* Device port */ 19 /* 69 General device port + 1 CPU + 1 Loopback */ 20 #define _HX5_TDM_GDEV_PORTS_PER_PIPE 69 21 #define _HX5_TDM_DEV_PORTS_PER_PIPE (_HX5_TDM_GDEV_PORTS_PER_PIPE + 2) 22 #define _HX5_TDM_DEV_PORTS_PER_DEV \ 23 (_HX5_TDM_DEV_PORTS_PER_PIPE * HELIX5_TDM_PIPES_PER_DEV) 24 /* MMU port */ 25 #define _HX5_TDM_MMU_PORTS_OFFSET_PER_PIPE 69 26 #define _HX5_TDM_MMU_PORTS_PER_DEV (69 * 1) 27 /* ------------------------------------------------- */ 28 #define _HX5_TDM_LENGTH 512 29 #define _HX5_PKT_SCH_LENGTH 160 30 #define _HX5_TDM_SPEED_CLASS_MAX 5 31 32 #define HX5_CLK_450MHZ 450 33 #define HX5_CLK_400MHZ 400 34 #define HX5_CLK_543MHZ 543 35 #define HX5_CLK_668MHZ 668 36 #define HX5_CLK_812MHZ 812 37 #define HX5_CLK_893MHZ 893 38 #define HX5_CLK_931MHZ 931 39 40 #define HX5_ICID_LENGTH_BYTES 8 /* ICID length in bytes */ 41 42 typedef struct _soc_helix5_tdm_pblk_info_s { 43 int pblk_hpipe_num; /* half pipeline info */ 44 int pblk_cal_idx; /* index to 8 HPIPEx_PBLK_CALENDARr */ 45 }_soc_helix5_tdm_pblk_info_t; 46 47 typedef struct _soc_helix5_tdm_pipe_s { 48 int idb_tdm[_HX5_TDM_LENGTH]; 49 int mmu_tdm[_HX5_TDM_LENGTH]; 50 int ovs_tdm[HELIX5_OVS_HPIPE_COUNT_PER_PIPE][HELIX5_TDM_OVS_GROUPS_PER_HPIPE][HELIX5_TDM_OVS_GROUP_LENGTH]; 51 int pkt_shaper_tdm[HELIX5_OVS_HPIPE_COUNT_PER_PIPE][_HX5_PKT_SCH_LENGTH]; 52 } _soc_helix5_tdm_pipe_t; 53 54 typedef struct _soc_helix5_tdm_temp_s { 55 _soc_helix5_tdm_pipe_t tdm_pipe[HELIX5_TDM_PIPES_PER_DEV]; 56 _soc_helix5_tdm_pblk_info_t pblk_info[HELIX5_TDM_PHY_PORTS_PER_DEV]; 57 int port_ratio[HELIX5_TDM_PBLKS_PER_DEV]; 58 int ovs_ratio_x1000[HELIX5_TDM_PIPES_PER_DEV][HELIX5_OVS_HPIPE_COUNT_PER_PIPE]; 59 60 } _soc_helix5_tdm_temp_t; 61 62 /* **************** TDM-related Macors and structs adopted from Tomahawk ---end************ */ 63 64 65 /********************** SER begin ******************************/ 66 67 /* 2 dedicated banks for L2 68 * 2 dedicated banks for L3 69 * 6 banks for UFT 70 * 8 banks for IUAT 71 * 4 banks for EUAT 72 * 73 * For L2, since there is only single wide view, the LP is only available for single wide view. 74 * For L3 and UFT/UAT banks, since they can be assigned to any logical table which supports different views, 75 * LP is available for different views - single, double and quad. 76 */ 77 78 /* Dedicated L2 and L3 entries - 8k per bank */ 79 #define SOC_HX5_NUM_ENTRIES_L2 16384 80 #define SOC_HX5_NUM_ENTRIES_L3 16384 81 #define SOC_HX5_NUM_BANKS_L2 2 82 #define SOC_HX5_NUM_BANKS_L3 2 83 84 /* Dedicated L2 LP entries per bank */ 85 #define SOC_HX5_NUM_ENTRIES_L2_LP_BANK 2048 /* 1W */ 86 /* Dedicated L3 LP entries per bank */ 87 #define SOC_HX5_NUM_ENTRIES_L3_LP_BANK 3584 /* 2048(1W) + 1024(2W) + 512(4W) */ 88 89 /* Same for ingress and egress UAT */ 90 #define SOC_HX5_NUM_ENTRIES_UAT_LP_BANK 1536 /* 1024(1W) + 512(2W) */ 91 92 /* UFT entries per bank */ 93 #define SOC_HX5_NUM_ENTRIES_UFT_BANK 16384 94 /* UFT LP entries per bank */ 95 #define SOC_HX5_NUM_ENTRIES_UFT_LP_BANK 7168 /* 4096(1W) + 2048(2W) + 1024(4W) */ 96 97 #define SOC_HX5_NUM_XOR_RAM_UFT 2 98 #define SOC_HX5_NUM_ENTRIES_XOR_RAM 8192 99 100 extern int 101 soc_helix5_mem_sram_info_get(int unit, soc_mem_t mem, int index, 102 _soc_ser_sram_info_t *sram_info); 103 104 extern int soc_hx5_ser_enable_all(int unit, int enable); 105 extern void soc_hx5_ser_error(void *unit_vp, void *d1, void *d2, 106 void *d3, void *d4); 107 extern int soc_hx5_mem_ser_control(int unit, soc_mem_t mem, 108 int copyno, int enable); 109 extern void soc_hx5_ser_register(int unit); 110 111 extern void soc_hx5_ser_test_register(int unit); 112 113 extern int soc_hx5_ser_lp_mem_info_get(int unit, soc_mem_t mem, int index, 114 soc_mem_t *hash_mem, int *hash_index); 115 /********************* SER end *********************************/ 116 117 118 extern int soc_hx5_mmu_config_shared_buf_recalc(int unit, int res, int thdi_shd, 119 int thdo_db_shd, int thdo_qe_shd, 120 int post_update); 121 122 extern soc_functions_t soc_helix5_drv_funs; 123 extern int soc_helix5_mem_config(int unit); 124 extern int soc_helix5_num_cosq_init(int unit); 125 extern int soc_helix5_num_cosq_init_port(int unit, int port); 126 extern int soc_hx5_port_oversub_get(int unit, int phy_port, int logical_port); 127 extern int soc_helix5_port_config_init(int unit, uint16 dev_id); 128 extern int soc_helix5_chip_reset(int unit); 129 extern int soc_helix5_port_reset(int unit); 130 131 extern int soc_helix5_port_obm_info_get(int unit, soc_port_t port, 132 int *obm_id, int *lane); 133 134 /* Counter */ 135 extern int soc_counter_helix5_status_enable(int unit, int enable); 136 extern int soc_counter_helix5_non_dma_init(int unit, int nports, 137 int non_dma_start_index, 138 int *non_dma_entries); 139 extern int soc_counter_helix5_get_info(int unit, soc_port_t port, 140 soc_reg_t id, int *base_index, 141 int *num_entries); 142 extern int soc_counter_helix5_eviction_enable(int unit, int enable); 143 extern void soc_counter_helix5_eviction_flags_update(int unit, 144 uint32 flags, 145 int enable); 146 extern int soc_counter_helix5_generic_get_info(int unit, soc_ctr_control_info_t ctrl_info, 147 soc_reg_t id, int *base_index, int *num_entries); 148 typedef int (*_soc_hx5_bst_hw_cb)(int unit); 149 extern int soc_hx5_set_bst_callback(int unit, _soc_hx5_bst_hw_cb cb); 150 extern int _soc_hx5_process_mmu_bst(int unit, int xpe, soc_field_t field); 151 extern int _bcm_hx5_pfc_reg_index_get(int unit, soc_port_t port, soc_port_t *mport, int *index); 152 153 #define IS_OVERSUB_PORT(unit,port) \ 154 (SOC_PBMP_MEMBER(PBMP_OVERSUB(unit), port)) 155 156 enum soc_hx5_port_ratio_e { 157 SOC_HX5_PORT_RATIO_SINGLE, 158 SOC_HX5_PORT_RATIO_DUAL_1_1, 159 SOC_HX5_PORT_RATIO_DUAL_2_1, 160 SOC_HX5_PORT_RATIO_DUAL_1_2, 161 SOC_HX5_PORT_RATIO_TRI_023_2_1_1, 162 SOC_HX5_PORT_RATIO_TRI_023_4_1_1, 163 SOC_HX5_PORT_RATIO_TRI_012_1_1_2, 164 SOC_HX5_PORT_RATIO_TRI_012_1_1_4, 165 SOC_HX5_PORT_RATIO_QUAD, 166 SOC_HX5_PORT_RATIO_QSGMII0, 167 SOC_HX5_PORT_RATIO_QSGMII1, 168 SOC_HX5_PORT_RATIO_COUNT 169 }; 170 171 typedef int (*_soc_hx5_tcb_hw_cb)(int unit); 172 extern int soc_hx5_set_tcb_callback(int unit, _soc_hx5_tcb_hw_cb cb); 173 extern int _soc_hx5_process_mmu_tcb(int unit, int xpe, soc_field_t field); 174 175 extern int soc_hx5_shared_hash_mem_bucket_read(int unit, int ent, 176 int key_type, int *width, 177 soc_mem_t base_mem, soc_mem_t *mem, 178 void *bkt_entry, void *entry); 179 extern int soc_hx5_hash_mem_status_get(int unit, soc_mem_t mem, 180 void* entry, uint32 *valid); 181 extern int soc_helix5_hash_bank_count_get(int unit, soc_mem_t mem, 182 int *num_banks); 183 extern int soc_helix5_hash_bank_bitmap_get(int unit, soc_mem_t mem, 184 uint32 *bitmap); 185 extern int soc_hx5_hash_bank_phy_bitmap_get(int unit, soc_mem_t mem, 186 uint32 *bitmap); 187 extern int soc_hx5_hash_bank_number_get(int unit, soc_mem_t mem, 188 int seq_num, int *bank_num); 189 extern int soc_hx5_hash_seq_number_get(int unit, soc_mem_t mem, 190 int bank_num, int *seq_num); 191 extern int soc_hx5_hash_bank_info_get(int unit, soc_mem_t mem, 192 int bank, 193 int *entries_per_bank, 194 int *entries_per_row, 195 int *entries_per_bucket, 196 int *bank_base, 197 int *bucket_offset); 198 extern int soc_hx5_hash_bucket_get(int unit, int mem, int bank, 199 uint32 *entry, uint32 *bucket); 200 extern int soc_hx5_hash_index_get(int unit, int mem, int bank, int bucket); 201 extern int soc_hx5_hash_offset_get(int unit, soc_mem_t mem, int bank, 202 int *hash_offset, int *use_lsb); 203 extern int soc_hx5_hash_offset_set(int unit, soc_mem_t mem, int bank, 204 int hash_offset, int use_lsb); 205 extern uint32 soc_hx5_l2x_hash(int unit, int bank, int hash_offset, 206 int use_lsb, int key_nbits, void *base_entry, 207 uint8 *key1, uint8 *key2); 208 extern int soc_hx5_l2x_base_entry_to_key(int unit, int bank, uint32 *entry, 209 uint8 *key); 210 extern uint32 soc_hx5_l2x_entry_hash(int unit, int bank, int hash_offset, 211 int use_lsb, uint32 *entry); 212 extern uint32 soc_hx5_l2x_bank_entry_hash(int unit, int bank, uint32 *entry); 213 extern uint32 soc_hx5_l3x_hash(int unit, int bank, int hash_offset, 214 int use_lsb, int key_nbits, void *base_entry, 215 uint8 *key1, uint8 *key2); 216 extern int soc_hx5_l3x_base_entry_to_key(int unit, int bank, uint32 *entry, 217 uint8 *key); 218 extern uint32 soc_hx5_l3x_entry_hash(int unit, int bank, int hash_offset, 219 int use_lsb, uint32 *entry); 220 extern uint32 soc_hx5_l3x_bank_entry_hash(int unit, int bank, uint32 *entry); 221 extern uint32 soc_hx5_exact_match_hash(int unit, int bank, int hash_offset, 222 int use_lsb, int key_nbits, 223 void *base_entry, uint8 *key1, 224 uint8 *key2); 225 extern int soc_hx5_exact_match_base_entry_to_key(int unit, int bank, uint32 *entry, 226 uint8 *key); 227 extern uint32 soc_hx5_exact_match_entry_hash(int unit, int bank, 228 int hash_offset, int use_lsb, 229 uint32 *entry); 230 extern uint32 soc_hx5_exact_match_bank_entry_hash(int unit, int bank, 231 uint32 *entry); 232 extern uint32 soc_hx5_mpls_hash(int unit, soc_mem_t mem, int bank, int hash_offset, int use_lsb, 233 int key_nbits, void *base_entry, uint8 *key1, uint8 *key2); 234 extern int soc_hx5_mpls_base_entry_to_key(int unit, soc_mem_t mem, int bank, void *entry, 235 uint8 *key); 236 extern uint32 soc_hx5_mpls_entry_hash(int unit, soc_mem_t mem, int bank, int hash_offset, 237 int use_lsb, uint32 *entry); 238 extern uint32 soc_hx5_mpls_bank_entry_hash(int unit, soc_mem_t mem, int bank, uint32 *entry); 239 extern uint32 soc_hx5_vlan_xlate_hash(int unit, soc_mem_t mem, int bank, int hash_offset, 240 int use_lsb, int key_nbits, void *base_entry, 241 uint8 *key1, uint8 *key2); 242 extern int soc_hx5_vlan_xlate_base_entry_to_key(int unit, soc_mem_t mem, int bank, 243 void *entry, uint8 *key); 244 extern uint32 soc_hx5_vlan_xlate_entry_hash(int unit, soc_mem_t mem, int bank, int hash_offset, 245 int use_lsb, uint32 *entry); 246 extern uint32 soc_hx5_vlan_xlate_bank_entry_hash(int unit, soc_mem_t mem, int bank, 247 uint32 *entry); 248 extern uint32 soc_hx5_egr_vlan_xlate_hash(int unit, soc_mem_t mem, int bank, int hash_offset, 249 int use_lsb, int key_nbits, void *base_entry, 250 uint8 *key1, uint8 *key2); 251 extern int soc_hx5_egr_vlan_xlate_base_entry_to_key(int unit, soc_mem_t mem, 252 int bank, void *entry, uint8 *key); 253 extern uint32 soc_hx5_egr_vlan_xlate_entry_hash(int unit, soc_mem_t mem, int bank, int hash_offset, 254 int use_lsb, uint32 *entry); 255 extern uint32 soc_hx5_egr_vlan_xlate_bank_entry_hash(int unit, soc_mem_t mem, 256 int bank, uint32 *entry); 257 extern uint32 soc_hx5_ing_vp_vlan_member_hash(int unit, int bank, int hash_offset, 258 int use_lsb, int key_nbits, void *base_entry, 259 uint8 *key1, uint8 *key2); 260 extern int soc_hx5_ing_vp_vlan_member_base_entry_to_key(int unit, 261 int bank, 262 void *entry, 263 uint8 *key); 264 extern uint32 soc_hx5_ing_vp_vlan_member_entry_hash(int unit, int bank, int hash_offset, 265 int use_lsb, uint32 *entry); 266 extern uint32 soc_hx5_ing_vp_vlan_member_bank_entry_hash(int unit, int bank, 267 uint32 *entry); 268 extern uint32 soc_hx5_egr_vp_vlan_member_hash(int unit, int bank, int hash_offset, 269 int use_lsb, int key_nbits, void *base_entry, 270 uint8 *key1, uint8 *key2); 271 extern int soc_hx5_egr_vp_vlan_member_base_entry_to_key(int unit, 272 int bank, 273 void *entry, 274 uint8 *key); 275 extern uint32 soc_hx5_egr_vp_vlan_member_entry_hash(int unit, int bank, int hash_offset, 276 int use_lsb, uint32 *entry); 277 extern uint32 soc_hx5_egr_vp_vlan_member_bank_entry_hash(int unit, int bank, 278 uint32 *entry); 279 280 extern int soc_helix5_bond_info_init(int unit); 281 extern int soc_hx5_port_schedule_tdm_init(int unit, 282 soc_port_schedule_state_t *port_schedule_state); 283 extern int soc_hx5_soc_tdm_update(int unit, 284 soc_port_schedule_state_t *port_schedule_state); 285 286 typedef enum { 287 SOC_HX5_SCHED_MODE_UNKNOWN = 0, 288 SOC_HX5_SCHED_MODE_STRICT, 289 SOC_HX5_SCHED_MODE_WRR, 290 SOC_HX5_SCHED_MODE_WERR 291 } soc_hx5_sched_mode_e; 292 293 typedef enum { 294 SOC_HX5_NODE_LVL_ROOT = 0, 295 SOC_HX5_NODE_LVL_L0, 296 SOC_HX5_NODE_LVL_L1, 297 SOC_HX5_NODE_LVL_L2, 298 SOC_HX5_NODE_LVL_L3, 299 SOC_HX5_NODE_LVL_MAX 300 } soc_hx5_node_lvl_e; 301 302 typedef enum { 303 _SOC_HX5_INDEX_STYLE_BUCKET, 304 _SOC_HX5_INDEX_STYLE_BUCKET_MODE, 305 _SOC_HX5_INDEX_STYLE_WRED, 306 _SOC_HX5_INDEX_STYLE_WRED_DROP_THRESH, 307 _SOC_HX5_INDEX_STYLE_SCHEDULER, 308 _SOC_HX5_INDEX_STYLE_PERQ_XMT, 309 _SOC_HX5_INDEX_STYLE_UCAST_DROP, 310 _SOC_HX5_INDEX_STYLE_UCAST_QUEUE, 311 _SOC_HX5_INDEX_STYLE_MCAST_QUEUE, 312 _SOC_HX5_INDEX_STYLE_EXT_UCAST_QUEUE, 313 _SOC_HX5_INDEX_STYLE_EGR_POOL, 314 _SOC_HX5_INDEX_STYLE_COUNT 315 } soc_hx5_index_style_t; 316 317 typedef enum soc_hx5_drop_limit_alpha_value_e { 318 SOC_HX5_COSQ_DROP_LIMIT_ALPHA_1_128, /* Use 1/128 as the alpha value for 319 dynamic threshold */ 320 SOC_HX5_COSQ_DROP_LIMIT_ALPHA_1_64, /* Use 1/64 as the alpha value for 321 dynamic threshold */ 322 SOC_HX5_COSQ_DROP_LIMIT_ALPHA_1_32, /* Use 1/32 as the alpha value for 323 dynamic threshold */ 324 SOC_HX5_COSQ_DROP_LIMIT_ALPHA_1_16, /* Use 1/16 as the alpha value for 325 dynamic threshold */ 326 SOC_HX5_COSQ_DROP_LIMIT_ALPHA_1_8, /* Use 1/8 as the alpha value for 327 dynamic threshold */ 328 SOC_HX5_COSQ_DROP_LIMIT_ALPHA_1_4, /* Use 1/4 as the alpha value for 329 dynamic threshold */ 330 SOC_HX5_COSQ_DROP_LIMIT_ALPHA_1_2, /* Use 1/2 as the alpha value for 331 dynamic threshold */ 332 SOC_HX5_COSQ_DROP_LIMIT_ALPHA_1, /* Use 1 as the alpha value for dynamic 333 threshold */ 334 SOC_HX5_COSQ_DROP_LIMIT_ALPHA_2, /* Use 2 as the alpha value for dynamic 335 threshold */ 336 SOC_HX5_COSQ_DROP_LIMIT_ALPHA_4, /* Use 4 as the alpha value for dynamic 337 threshold */ 338 SOC_HX5_COSQ_DROP_LIMIT_ALPHA_8, /* Use 8 as the alpha value for dynamic 339 threshold */ 340 SOC_HX5_COSQ_DROP_LIMIT_ALPHA_COUNT /* Must be the last entry! */ 341 } soc_hx5_drop_limit_alpha_value_t; 342 343 #define _HX5_PORTS_PER_PBLK 4 344 #define _HX5_PORTS_PER_PMQ_PBLK 16 345 #define _HX5_PBLKS_PER_PIPE 19 346 #define _HX5_PIPES_PER_DEV 1 347 #define _HX5_XPES_PER_DEV 1 348 #define _HX5_OBMS_PER_PIPE 10 349 350 #define _HX5_PBLKS_PER_DEV(unit) (_HX5_PBLKS_PER_PIPE * NUM_PIPE(unit)) 351 352 #define _HX5_PORTS_PER_PIPE (_HX5_PORTS_PER_PBLK * _HX5_PBLKS_PER_PIPE) 353 #define _HX5_PORTS_PER_DEV(unit) (_HX5_PORTS_PER_PIPE * NUM_PIPE(unit)) 354 355 #define _HX5_SECTION_SIZE 32768 356 357 #define _HX5_MMU_MAX_PACKET_BYTES 9416 /* bytes */ 358 #define _HX5_MMU_PACKET_HEADER_BYTES 64 /* bytes */ 359 #define _HX5_MMU_JUMBO_FRAME_BYTES 9216 /* bytes */ 360 #define _HX5_MMU_DEFAULT_MTU_BYTES 1536 /* bytes */ 361 362 #define _HX5_MMU_PHYSICAL_CELLS_PER_XPE 36*1024 /* Total Physical cells per XPE */ 363 #define _HX5_MMU_TOTAL_CELLS_PER_XPE 32768 /* 32MBE */ 364 #define _HX5_MMU_RSVD_CELLS_CFAP_PER_XPE 346 /* Reserved CFAP cells per XPE */ 365 #define _HX5_MMU_CFAP_BANK_FULL_LIMIT 1023 /* CFAP Bank Full limit */ 366 367 #define _HX5_MMU_TOTAL_CELLS (_HX5_MMU_TOTAL_CELLS_PER_XPE * _HX5_XPES_PER_DEV) 368 #define _HX5_MMU_PHYSICAL_CELLS (_HX5_MMU_PHYSICAL_CELLS_PER_XPE * _HX5_XPES_PER_DEV) 369 370 #define _HX5_MMU_BYTES_PER_CELL 256 /* bytes (2048 bits) */ 371 #define _HX5_MMU_NUM_PG 8 372 #define _HX5_MMU_NUM_POOL 4 373 #define _HX5_MMU_NUM_RQE_QUEUES 11 374 #define _HX5_MMU_NUM_LBK_QUEUES 10 375 #define _HX5_MMU_NUM_INT_PRI 16 376 377 #define SOC_HX5_MMU_CFG_QGROUP_MAX 34 378 379 #define SOC_HX5_MMU_PORT_STRIDE 0x7f /* MMU Port number space per pipe */ 380 381 #define SOC_HX5_NUM_CPU_QUEUES 48 /* CPU port has 48 MC Queues */ 382 #define SOC_HX5_NUM_UC_QUEUES_PER_PIPE 1280 /* (54 Downlink Ports * 16 + (8 Uplink + 8 Stacking) * 26) */ 383 #define SOC_HX5_NUM_MC_QUEUES_PER_PIPE 1338 /* (54 Downlink Ports * 16 + (8 Uplink + 8 Stacking) * 26) + 1 CPU Port +*/ 384 /* 1 Loop-back Port) * 10 */ 385 #define _BCM_HX5_MMU_L3_MC_CPU_QBASE 2570 386 #define _BCM_HX5_MMU_L3_MC_LB_QBASE 2560 387 388 #define SOC_HX5_CPU_MCQ_BASE 1290 /* CPU port MC queue base index */ 389 #define SOC_HX5_LB_MCQ_BASE 1280 /* LB ports MC queue base index */ 390 #define SOC_HX5_DOWNLINK_PORTQ_BASE (26 * 16) /* 16 (8 UPlink + 8 Stacking) * 26 queues */ 391 392 393 /* Number of Unicast Queues per Downlink Port 394 Queues 0 - 7 for wireless traffic and 8 - 15 for wired traffic*/ 395 #define SOC_HX5_NUM_UCAST_QUEUE_PER_PORT 16 396 /* Number of Multicast Queues per Downlink Port 397 Queues 0 - 7 for wireless traffic and 8 - 15 for wired traffic*/ 398 #define SOC_HX5_NUM_MCAST_QUEUE_PER_PORT 16 399 /* Number of Scheduler Nodes per Downlink Port */ 400 #define SOC_HX5_NUM_SCHEDULER_PER_PORT 19 401 402 /* Number of Unicast Queues per HG/Stacking Port 403 Queues 0 - 7 for transit traffic and 8 - 15 for wireless traffic, 16 - 23 is for wired traffic */ 404 #define SOC_HX5_NUM_UCAST_QUEUE_PER_ST_PORT 26 405 /* Number of Multicast Queues per HG/Stacking Port 406 Queues 0 - 7 for transit traffic and 8 - 15 for wireless traffic, 16 - 23 is for wired traffic */ 407 #define SOC_HX5_NUM_MCAST_QUEUE_PER_ST_PORT 26 408 /* Number of Scheduler Nodes per HG/Stacking Port */ 409 #define SOC_HX5_NUM_SCHEDULER_PER_ST_PORT 33 410 #define SOC_HX5_NUM_SCHEDULER_PER_CPU_PORT 12 411 412 #define SOC_HX5_MMU_MCQ_ENTRY_PER_XPE 24576 413 #define SOC_HX5_MMU_RQE_ENTRY_PER_XPE 2048 414 #define _HX5_MMU_RQE_ENTRY_RSVD_PER_XPE 242 /* Reserved RQE QE per XPE */ 415 #define _HX5_MAX_MMU_MCQE_PER_XPE 1338 /* MAX MMU MC QE */ 416 417 #define _HX5_MMU_TOTAL_MCQ_ENTRY(unit) SOC_HX5_MMU_MCQ_ENTRY_PER_XPE 418 #define _HX5_MMU_TOTAL_RQE_ENTRY(unit) SOC_HX5_MMU_RQE_ENTRY_PER_XPE 419 420 #define _HX5_TDM_MCQE_RSVD_OVERSHOOT 12 /* Reserved MC egress queue entry 421 for TDM overshoot */ 422 #define _HX5_MCQE_RSVD_PER_MCQ 6 /* Reserved MC egress queue entry 423 per MC queue */ 424 /* MMU pktstats control flags */ 425 #define _HX5_MMU_PSTATS_ENABLE 0x0001 /* Packetized/OOB Stat mode is enabled */ 426 #define _HX5_MMU_PSTATS_PKT_MOD 0x0002 /* Packetized mode is enabled. OOB Stat mode is disabled */ 427 #define _HX5_MMU_PSTATS_HWM_MOD 0x0004 /* Report High Watermark values */ 428 #define _HX5_MMU_PSTATS_RESET_ON_READ 0x0008 /* Enable Hardware clear-on read */ 429 #define _HX5_MMU_PSTATS_MOR_EN 0x0010 /* Enable MOR capability */ 430 #define _HX5_MMU_PSTATS_SYNC 0x8000 /* Read from device else the buffer */ 431 432 /* Per pipe WRED config memory base index */ 433 #define _HX5_WRED_PER_PIPE_UC_QUEUES_BASE 0 434 #define _HX5_WRED_PER_PIPE_PORT_SP_BASE 1280 /* (16 * 26) UPlink + (54 * 16) Dw link */ 435 #define _HX5_WRED_PER_PIPE_GLOBAL_SP_BASE 1560 /* (4 global service pools) */ 436 437 438 extern void soc_helix5_mmu_pstats_tbl_config(int unit); 439 extern int soc_helix5_mmu_pstats_mode_set(int unit, uint32 flags); 440 extern int soc_helix5_mmu_pstats_mode_get(int unit, uint32 *flags); 441 extern int soc_helix5_mmu_pstats_mor_enable(int unit); 442 extern int soc_helix5_mmu_pstats_mor_disable(int unit); 443 444 typedef struct _soc_hx5_mmu_sw_config_info_s { 445 uint32 mmu_egr_queue_min; /* For CPU and loopback port */ 446 uint32 mmu_egr_qgrp_min; 447 uint32 mmu_total_pri_groups; 448 uint32 mmu_active_pri_groups; 449 uint32 mmu_pg_min; 450 uint32 mmu_port_min; 451 uint32 mmu_mc_egr_qentry_min; 452 uint32 mmu_rqe_qentry_min; 453 uint32 mmu_rqe_queue_min; 454 int ing_shared_total; 455 int egr_shared_total; 456 } _soc_hx5_mmu_sw_config_info_t; 457 458 extern int 459 soc_helix5_temperature_monitor_get(int unit, int temperature_max, 460 soc_switch_temperature_monitor_t *temperature_array, 461 int *temperature_count); 462 extern void 463 soc_helix5_temperature_intr(void *unit_vp, void *d1, void *d2, 464 void *d3, void *d4); 465 extern int 466 soc_helix5_mmu_port_flush_hw(int unit, soc_port_t port, uint32 drain_timeout); 467 468 extern void soc_helix5_port_qsgmii_mode_get(int unit, soc_port_t port, int* qsgmii_mode); 469 extern void soc_helix5_sbus_ring_map_config(int unit); 470 471 /************ FlexPort Start ********************/ 472 extern int soc_hx5_mmu_config_init_port(int unit, int port); 473 #ifdef BCM_WARM_BOOT_SUPPORT 474 extern int soc_hx5_flexport_scache_allocate(int unit); 475 extern int soc_hx5_flexport_scache_sync(int unit); 476 extern int soc_hx5_flexport_scache_recovery(int unit); 477 extern int soc_hx5_tdm_scache_allocate(int unit); 478 extern int soc_hx5_tdm_scache_sync(int unit); 479 extern int soc_hx5_tdm_scache_recovery(int unit); 480 #endif /* BCM_WARM_BOOT_SUPPORT */ 481 482 extern int 483 soc_hx5_support_speeds(int unit, int port, uint32 *speed_mask); 484 485 /************ FlexPort End ********************/ 486 487 extern int 488 soc_hx5_lpm_flex_ip4entry0_to_1( 489 int u, 490 void *src, 491 void *dst, 492 uint32 key_type, 493 int copy_hit); 494 495 extern int 496 soc_hx5_lpm_flex_prefix_length_get( 497 int u, 498 void *entry, 499 int *ipv6, 500 int *vrf_id, 501 int *pfx, 502 uint32 key_type); 503 504 extern int soc_hx5_reg_blk_index_get(int unit, soc_reg_t reg, soc_port_t port, 505 pbmp_t *bm, int *block, int *index, int invalid_blk_check); 506 extern int 507 soc_hx5_mpls_hash_control_set(int *hash_entry); 508 509 extern int 510 soc_helix5_show_voltage(int unit); 511 512 extern int 513 soc_helix5_icid_get(int unit, int max_size, uint8 *buffer, int *actual_size); 514 515 #endif /* !_SOC_HELIX5_H_ */