hash.h (15411B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * Hash table calculation routines 8 */ 9 10 #ifndef _SOC_HASH_H 11 #define _SOC_HASH_H 12 13 #include <soc/mem.h> 14 15 #if defined(BCM_ESW_SUPPORT) || defined(BCM_SAND_SUPPORT) || defined(PORTMOD_SUPPORT) 16 #ifdef BCM_XGS3_SWITCH_SUPPORT 17 typedef struct soc_xgs3_ecmp_hash_s{ 18 ip_addr_t dip; /* IPv4 destination IP. */ 19 ip_addr_t sip; /* IPv4 source IP. */ 20 ip6_addr_t dip6; /* IPv6 destination IP. */ 21 ip6_addr_t sip6; /* IPv6 source IP. */ 22 uint16 l4_src_port; /* TCP/UDP source port. */ 23 uint16 l4_dst_port; /* TCP/UDP destination port. */ 24 uint8 v6; /* IPv6 flag. */ 25 int ecmp_count; /* Ecmp group size. */ 26 } soc_xgs3_ecmp_hash_t; 27 #endif /* BCM_XGS3_SWITCH_SUPPORT */ 28 29 extern uint32 soc_draco_crc32(uint8 *data, int data_size); 30 extern uint16 soc_draco_crc16(uint8 *data, int data_size); 31 #ifdef BCM_XGS_SWITCH_SUPPORT /* DPPCOMPILEENABLE */ 32 extern uint32 soc_crc32b(uint8 *data, int data_nbits); 33 extern uint16 soc_crc16b(uint8 *data, int data_nbits); 34 35 extern void soc_draco_l2x_base_entry_to_key(int unit, l2x_entry_t *entry, 36 uint8 *key); 37 #endif 38 extern void soc_draco_l2x_param_to_key(sal_mac_addr_t mac, int vid, 39 uint8 *key); 40 #ifdef BCM_XGS3_SWITCH_SUPPORT 41 extern uint32 soc_xgs3_l3_ecmp_hash(int unit, soc_xgs3_ecmp_hash_t *data); 42 #endif /* BCM_XGS3_SWITCH_SUPPORT */ 43 extern uint32 soc_draco_trunk_hash(sal_mac_addr_t da, 44 sal_mac_addr_t sa, int tgsize); 45 extern uint32 soc_fb_l2_hash(int unit, int hash_sel, uint8 *key); 46 47 extern uint32 soc_fb_l3_hash(int unit, int hash_sel, 48 int key_nbits, uint8 *key); 49 extern int soc_fb_l3x_base_entry_to_key(int unit, 50 uint32 *entry, 51 uint8 *key); 52 extern uint32 soc_fb_l3x2_entry_hash(int unit, uint32 *entry); 53 extern uint32 soc_fb_vlan_mac_hash(int unit, int hash_sel, uint8 *key); 54 extern int soc_fb_rv_vlanmac_hash_sel_get(int unit, int dual, int *hash_sel); 55 56 #if defined(BCM_FIREBOLT2_SUPPORT) || defined(BCM_TRX_SUPPORT) \ 57 || defined(BCM_RAPTOR_SUPPORT) 58 extern int soc_fb_l2x_entry_bank_hash_sel_get(int unit, int bank, 59 int *hash_sel); 60 extern uint32 soc_fb_l2x_entry_hash(int unit, int hash_sel, uint32 *entry); 61 extern int soc_fb_l3x_entry_bank_hash_sel_get(int unit, int bank, 62 int *hash_sel); 63 extern uint32 soc_fb_l3x_entry_hash(int unit, int hash_sel, uint32 *entry); 64 extern int soc_fb_l3x_bank_entry_hash(int unit, int bank, uint32 *entry); 65 66 #endif /* BCM_FIREBOLT2_SUPPORT || BCM_TRX_SUPPORT || BCM_RAPTOR_SUPPORT */ 67 68 #define FB2_HASH_VRF_BITS 6 69 #define FB2_HASH_VRF_MASK 0x3f 70 71 /* Triumph functions */ 72 extern int soc_tr_hash_sel_get(int unit, soc_mem_t mem, int bank, 73 int *hash_sel); 74 extern uint32 soc_tr_l2x_hash(int unit, int hash_sel, int key_nbits, 75 void *base_entry, uint8 *key); 76 extern int soc_tr_l2x_base_entry_to_key(int unit, void *entry, 77 uint8 *key); 78 extern uint32 soc_tr_l2x_entry_hash(int unit, int hash_sel, uint32 *entry); 79 extern uint32 soc_tr_l2x_bank_entry_hash(int unit, int bank, uint32 *entry); 80 81 extern uint32 soc_tr_vlan_xlate_hash(int unit, int hash_sel, int key_nbits, 82 void *base_entry, uint8 *key); 83 extern int soc_tr_vlan_xlate_base_entry_to_key(int unit, void *entry, 84 uint8 *key); 85 extern uint32 soc_tr_vlan_xlate_entry_hash(int unit, int hash_sel, 86 uint32 *entry); 87 extern uint32 soc_tr_vlan_xlate_bank_entry_hash(int unit, int bank, 88 uint32 *entry); 89 90 extern uint32 soc_tr_egr_vlan_xlate_hash(int unit, int hash_sel, 91 int key_nbits, void *base_entry, 92 uint8 *key); 93 extern int soc_tr_egr_vlan_xlate_base_entry_to_key(int unit, void *entry, 94 uint8 *key); 95 extern uint32 soc_tr_egr_vlan_xlate_entry_hash(int unit, int hash_sel, 96 uint32 *entry); 97 extern uint32 soc_tr_egr_vlan_xlate_bank_entry_hash(int unit, int bank, 98 uint32 *entry); 99 extern uint32 soc_tr_mpls_hash(int unit, int hash_sel, int key_nbits, 100 void *base_entry, uint8 *key); 101 extern int soc_tr_mpls_base_entry_to_key(int unit, void *entry, 102 uint8 *key); 103 extern uint32 soc_tr_mpls_entry_hash(int unit, int hash_sel, uint32 *entry); 104 extern uint32 soc_tr_mpls_bank_entry_hash(int unit, int bank, uint32 *entry); 105 106 extern uint32 soc_tr3_ft_session_entry_hash(int unit, soc_mem_t, int hash_sel, 107 uint32 *entry); 108 extern int soc_tr3_ft_session_entry_to_key(int unit, soc_mem_t mem, 109 void *entry, uint8 *key); 110 extern uint32 soc_tr3_wlan_entry_hash(int unit, soc_mem_t, int hash_sel, 111 uint32 *entry); 112 extern int soc_tr3_wlan_base_entry_to_key(int unit, soc_mem_t mem, 113 void *entry, uint8 *key); 114 extern int soc_dual_hash_recurse_depth_get(int unit, soc_mem_t mem); 115 extern int soc_multi_hash_recurse_depth_get(int unit, soc_mem_t mem); 116 117 extern int soc_td2_hash_offset_set(int unit, soc_mem_t mem, int bank, 118 int hash_offset, int use_lsb); 119 120 #if defined(BCM_TRIDENT2_SUPPORT) 121 extern int 122 soc_td2_hash_sel_get(int unit, soc_mem_t mem, int bank, int *hash_sel); 123 #endif 124 #if defined(BCM_TRIDENT2_SUPPORT) || defined(BCM_TRIDENT2PLUS_SUPPORT) || \ 125 defined(BCM_TOMAHAWK_SUPPORT) 126 extern int soc_td2x_th_l2x_hash(int unit, uint32 *base_entry, int *num_banks, 127 int *bucket_array, int *index_array, 128 uint8 *hash_key); 129 extern int 130 soc_td2x_th_l3x_hash(int unit, soc_mem_t mem, uint32 *base_entry, int *num_banks, 131 int *bucket_array, int *index_array, int *phy_bank_array, 132 int *entry_num_array); 133 #endif 134 135 #define TRX_HASH_VRF_BITS 11 136 #define TRX_HASH_VRF_MASK 0x7ff 137 138 enum XGS_HASH { 139 /* WARNING: values given match hardware register; do not modify */ 140 XGS_HASH_CRC16_UPPER = 0, 141 XGS_HASH_CRC16_LOWER = 1, 142 XGS_HASH_LSB = 2, 143 XGS_HASH_ZERO = 3, 144 XGS_HASH_CRC32_UPPER = 4, 145 XGS_HASH_CRC32_LOWER = 5, 146 XGS_HASH_COUNT 147 }; 148 149 enum FB_HASH { 150 /* WARNING: values given match hardware register; do not modify */ 151 FB_HASH_ZERO = 0, 152 FB_HASH_CRC32_UPPER = 1, 153 FB_HASH_CRC32_LOWER = 2, 154 FB_HASH_LSB = 3, 155 FB_HASH_CRC16_LOWER = 4, 156 FB_HASH_CRC16_UPPER = 5, 157 FB_HASH_COUNT 158 }; 159 160 enum XGS_HASH_KEY_TYPE { 161 /* WARNING: values given match hardware register; do not modify */ 162 XGS_HASH_KEY_TYPE_L2 = 0, 163 XGS_HASH_KEY_TYPE_L3UC = 1, 164 XGS_HASH_KEY_TYPE_L3MC = 2, 165 XGS_HASH_KEY_TYPE_COUNT 166 }; 167 168 enum TR_L3_HASH_KEY_TYPE { 169 /* WARNING: values given match hardware register; do not modify */ 170 TR_L3_HASH_KEY_TYPE_V4UC = 0, 171 TR_L3_HASH_KEY_TYPE_V4MC = 1, 172 TR_L3_HASH_KEY_TYPE_V6UC = 2, 173 TR_L3_HASH_KEY_TYPE_V6MC = 3, 174 TR_L3_HASH_KEY_TYPE_LMEP = 4, 175 TR_L3_HASH_KEY_TYPE_RMEP = 5, 176 TR_L3_HASH_KEY_TYPE_TRILL = 6, 177 TR_L3_HASH_KEY_TYPE_COUNT 178 }; 179 180 enum TR_L2_HASH_KEY_TYPE { 181 /* WARNING: values given match hardware register; do not modify */ 182 TR_L2_HASH_KEY_TYPE_BRIDGE = 0, 183 TR_L2_HASH_KEY_TYPE_SINGLE_CROSS_CONNECT = 1, 184 TR_L2_HASH_KEY_TYPE_DOUBLE_CROSS_CONNECT = 2, 185 TR_L2_HASH_KEY_TYPE_VFI = 3, 186 TR_L2_HASH_KEY_TYPE_VIF = 4, 187 TR_L2_HASH_KEY_TYPE_TRILL_NONUC_ACCESS = 5, 188 TR_L2_HASH_KEY_TYPE_TRILL_NONUC_NETWORK_LONG = 6, 189 TR_L2_HASH_KEY_TYPE_TRILL_NONUC_NETWORK_SHORT = 7, 190 TR_L2_HASH_KEY_TYPE_PE_VID = 9, 191 TR_L2_HASH_KEY_TYPE_COUNT 192 }; 193 194 enum KT_L2_HASH_KEY_TYPE { 195 /* WARNING: values given match hardware register; do not modify */ 196 KT_L2_HASH_KEY_TYPE_BRIDGE = 0, 197 KT_L2_HASH_KEY_TYPE_SINGLE_CROSS_CONNECT = 1, 198 KT_L2_HASH_KEY_TYPE_DOUBLE_CROSS_CONNECT = 2, 199 KT_L2_HASH_KEY_TYPE_VFI = 3, 200 KT_L2_HASH_KEY_TYPE_BFD = 4, 201 KT_L2_HASH_KEY_TYPE_COUNT 202 }; 203 204 /* Vlan Xlate common key types */ 205 enum VLXLT_HASH_KEY_TYPE { 206 VLXLT_HASH_KEY_TYPE_IVID_OVID, 207 VLXLT_HASH_KEY_TYPE_OTAG, 208 VLXLT_HASH_KEY_TYPE_ITAG, 209 VLXLT_HASH_KEY_TYPE_VLAN_MAC, 210 VLXLT_HASH_KEY_TYPE_OVID, 211 VLXLT_HASH_KEY_TYPE_IVID, 212 VLXLT_HASH_KEY_TYPE_PRI_CFI, 213 VLXLT_HASH_KEY_TYPE_HPAE, 214 VLXLT_HASH_KEY_TYPE_VIF, 215 VLXLT_HASH_KEY_TYPE_VIF_VLAN, 216 VLXLT_HASH_KEY_TYPE_VIF_CVLAN, 217 VLXLT_HASH_KEY_TYPE_VIF_OTAG, 218 VLXLT_HASH_KEY_TYPE_VIF_ITAG, 219 VLXLT_HASH_KEY_TYPE_L2GRE_DIP, 220 VLXLT_HASH_KEY_TYPE_VLAN_MAC_PORT, 221 VLXLT_HASH_KEY_TYPE_IVID_OVID_VSAN, 222 VLXLT_HASH_KEY_TYPE_IVID_VSAN, 223 VLXLT_HASH_KEY_TYPE_OVID_VSAN, 224 VLXLT_HASH_KEY_TYPE_VXLAN_DIP, 225 VLXLT_HASH_KEY_TYPE_LLVID, 226 VLXLT_HASH_KEY_TYPE_LLVID_OVID, 227 VLXLT_HASK_KEY_TYPE_LLVID_IVID, 228 VLXLT_HASH_KEY_TYPE_PAYLOAD_IVID_OVID, 229 VLXLT_HASH_KEY_TYPE_PAYLOAD_OTAG, 230 VLXLT_HASH_KEY_TYPE_PAYLOAD_ITAG, 231 VLXLT_HASH_KEY_TYPE_PAYLOAD_OVID, 232 VLXLT_HASH_KEY_TYPE_PAYLOAD_IVID, 233 VLXLT_HASH_KEY_TYPE_VNID, 234 VLXLT_HASH_KEY_TYPE_COUNT 235 }; 236 237 /* Egress Vlan Xlate common key types */ 238 enum EGR_VLXLT_HASH_KEY_TYPE { 239 EGR_VLXLT_HASH_KEY_TYPE_IVID_OVID_VSAN, 240 EGR_VLXLT_HASH_KEY_TYPE_OVID_VSAN, 241 EGR_VLXLT_HASH_KEY_TYPE_IVID_VSAN, 242 EGR_VLXLT_HASH_KEY_TYPE_IVID_OVID, 243 EGR_VLXLT_HASH_KEY_TYPE_IVID, 244 EGR_VLXLT_HASH_KEY_TYPE_OVID, 245 EGR_VLXLT_HASH_KEY_TYPE_VSAN 246 }; 247 248 /* Triumph key type values */ 249 enum TR_VLXL_HASH_KEY_TYPE { 250 /* WARNING: values given match hardware register; do not modify */ 251 TR_VLXLT_HASH_KEY_TYPE_IVID_OVID = 0, 252 TR_VLXLT_HASH_KEY_TYPE_OTAG = 1, 253 TR_VLXLT_HASH_KEY_TYPE_ITAG = 2, 254 TR_VLXLT_HASH_KEY_TYPE_VLAN_MAC = 3, 255 TR_VLXLT_HASH_KEY_TYPE_OVID = 4, 256 TR_VLXLT_HASH_KEY_TYPE_IVID = 5, 257 TR_VLXLT_HASH_KEY_TYPE_PRI_CFI = 6, 258 TR_VLXLT_HASH_KEY_TYPE_HPAE = 7, /* Not supported until TR2 */ 259 TR_VLXLT_HASH_KEY_TYPE_VIF = 8, 260 TR_VLXLT_HASH_KEY_TYPE_VIF_VLAN = 9, 261 TR_VLXLT_HASH_KEY_TYPE_VLAN_MAC_PORT = 14, 262 TR_VLXLT_HASH_KEY_TYPE_COUNT 263 }; 264 265 /* Triumph3 key type values */ 266 enum TR3_VLXL_HASH_KEY_TYPE { 267 /* WARNING: values given match hardware register; do not modify */ 268 TR3_VLXLT_HASH_KEY_TYPE_IVID_OVID = 0, 269 TR3_VLXLT_X_HASH_KEY_TYPE_IVID_OVID = 1, 270 TR3_VLXLT_HASH_KEY_TYPE_OVID = 2, 271 TR3_VLXLT_X_HASH_KEY_TYPE_OVID = 3, 272 TR3_VLXLT_HASH_KEY_TYPE_IVID = 4, 273 TR3_VLXLT_X_HASH_KEY_TYPE_IVID = 5, 274 TR3_VLXLT_HASH_KEY_TYPE_OTAG = 6, 275 TR3_VLXLT_X_HASH_KEY_TYPE_OTAG = 7, 276 TR3_VLXLT_HASH_KEY_TYPE_ITAG = 8, 277 TR3_VLXLT_X_HASH_KEY_TYPE_ITAG = 9, 278 TR3_VLXLT_HASH_KEY_TYPE_PRI_CFI = 10, 279 TR3_VLXLT_X_HASH_KEY_TYPE_PRI_CFI = 11, 280 TR3_VLXLT_HASH_KEY_TYPE_IVID_OVID_SVP = 12, 281 TR3_VLXLT_X_HASH_KEY_TYPE_IVID_OVID_SVP = 13, 282 TR3_VLXLT_HASH_KEY_TYPE_OVID_SVP = 14, 283 TR3_VLXLT_X_HASH_KEY_TYPE_OVID_SVP = 15, 284 TR3_VLXLT_HASH_KEY_TYPE_VLAN_MAC = 20, 285 TR3_VLXLT_HASH_KEY_TYPE_VIF = 21, 286 TR3_VLXLT_HASH_KEY_TYPE_VIF_VLAN = 22, 287 TR3_VLXLT_HASH_KEY_TYPE_VIF_CVLAN = 23, 288 TR3_VLXLT_HASH_KEY_TYPE_VIF_OTAG = 24, 289 TR3_VLXLT_HASH_KEY_TYPE_VIF_ITAG = 25, 290 TR3_VLXLT_HASH_KEY_TYPE_L2GRE_DIP = 26, 291 TR3_VLXLT_HASH_KEY_TYPE_HPAE = 27, 292 TR3_VLXLT_HASH_KEY_TYPE_COUNT 293 }; 294 295 /* Triumph3 PORT_TABLE key type values in VT_KEY_TYPE(_2) differs from 296 * VLAN_XLATE(_2).KEY_TYPE values 297 */ 298 enum TR3_PT_VLXL_HASH_KEY_TYPE { 299 /* WARNING: values given match hardware register; do not modify */ 300 TR3_PT_XLT_KEY_TYPE_IVID_OVID = 0, 301 TR3_PT_XLT_KEY_TYPE_OTAG = 1, 302 TR3_PT_XLT_KEY_TYPE_ITAG = 2, 303 TR3_PT_XLT_KEY_TYPE_VLAN_MAC = 3, 304 TR3_PT_XLT_KEY_TYPE_OVID = 4, 305 TR3_PT_XLT_KEY_TYPE_IVID = 5, 306 TR3_PT_XLT_KEY_TYPE_PRI_CFI = 6, 307 TR3_PT_XLT_KEY_TYPE_HPAE = 7, 308 TR3_PT_XLT_KEY_TYPE_VIF = 8, 309 TR3_PT_XLT_KEY_TYPE_VIF_VLAN = 9, 310 TR3_PT_XLT_KEY_TYPE_VIF_CVLAN = 10, 311 TR3_PT_XLT_KEY_TYPE_VIF_OTAG = 11, 312 TR3_PT_XLT_KEY_TYPE_VIF_ITAG = 12, 313 TR3_PT_XLT_KEY_TYPE_COUNT 314 }; 315 316 /* KT2 PORT_TABLE and VLAN_XLATE key type values 317 */ 318 enum KT2_PT_VLXL_HASH_KEY_TYPE { 319 /* WARNING: values given match hardware register; do not modify */ 320 KT2_PT_XLT_KEY_TYPE_IVID_OVID = 0, 321 KT2_PT_XLT_KEY_TYPE_OTAG = 1, 322 KT2_PT_XLT_KEY_TYPE_ITAG = 2, 323 KT2_PT_XLT_KEY_TYPE_VLAN_MAC = 3, /* Reserved in Kt2, not used */ 324 KT2_PT_XLT_KEY_TYPE_OVID = 4, 325 KT2_PT_XLT_KEY_TYPE_IVID = 5, 326 KT2_PT_XLT_KEY_TYPE_PRI_CFI = 6, 327 KT2_PT_XLT_KEY_TYPE_HPAE = 7, /* Reserved in KT2, not used */ 328 KT2_PT_XLT_KEY_TYPE_VIF = 8, 329 KT2_PT_XLT_KEY_TYPE_VIF_VLAN = 9, 330 KT2_PT_XLT_KEY_TYPE_VIF_CVLAN = 10, 331 KT2_PT_XLT_KEY_TYPE_VIF_OTAG = 11, 332 KT2_PT_XLT_KEY_TYPE_VIF_ITAG = 12, 333 KT2_PT_XLT_KEY_TYPE_LLVID = 13, /* LLTAG VLAN ID */ 334 KT2_PT_XLT_KEY_TYPE_LLVID_IVID = 14, /* LLTAG VLAN ID plus inner VLAN ID */ 335 KT2_PT_XLT_KEY_TYPE_LLVID_OVID = 15, /* LLTAG VLAN ID plus inner VLAN ID */ 336 KT2_PT_XLT_KEY_TYPE_COUNT 337 }; 338 339 #ifdef SOC_ROBUST_HASH 340 extern int 341 soc_robust_hash_get(int unit, soc_robust_hash_config_t *rbh_cfg, int bank, 342 uint8 *key, int n_bits); 343 extern int 344 soc_robust_hash_get2(int unit, soc_robust_hash_config_t *rbh_cfg, int bank, 345 uint8 *key, int n_bits); 346 extern int 347 soc_robust_hash_table_set(int unit, soc_robust_hash_config_t *rbh_cfg, 348 int seed); 349 350 #define ROBUSTHASH(_u) ((SOC_CONTROL(_u))->soc_robust_hash_config) 351 #endif /* SOC_ROBUST_HASH */ 352 353 #if defined(BCM_TRIDENT3_SUPPORT) || defined(BCM_TOMAHAWK3_SUPPORT) 354 /* Maximum hash key size is 415b (L3) + 16b (Robust Hash) */ 355 #define XGS_HASH_KEY_SIZE (52 + 2) 356 #else 357 #define XGS_HASH_KEY_SIZE 10 358 #endif 359 #define SOC_LYNX_DMUX_MASK 0x3f /* Lynx Mux/Demux only uses 6 bits */ 360 361 #define SOC_L3_TUNNEL_BUCKET_SIZE 8 362 #define SOC_MPLS_ENTRY_BUCKET_SIZE 8 363 #define SOC_VLAN_XLATE_BUCKET_SIZE 8 364 #define SOC_EGR_VLAN_XLATE_BUCKET_SIZE 8 365 #define SOC_VLAN_MAC_BUCKET_SIZE 8 366 #define SOC_WLAN_BUCKET_SIZE 8 367 #define SOC_ING_VP_VLAN_MEMBER_BUCKET_SIZE 8 368 #define SOC_EGR_VP_VLAN_MEMBER_BUCKET_SIZE 8 369 #define SOC_ING_DNAT_ADDRESS_TYPE_BUCKET_SIZE 8 370 #define SOC_L2_ENDPOINT_ID_BUCKET_SIZE 8 371 #define SOC_ENDPOINT_QUEUE_MAP_BUCKET_SIZE 8 372 #define SOC_EGR_MP_GROUP_BUCKET_SIZE 8 373 #define SOC_FT_SESSION_BUCKET_SIZE 8 374 #define SOC_SUBPORT_ID_TO_SGPP_MAP_BUCKET_SIZE 8 375 #endif /* BCM_ESW_SUPPORT || BCM_SAND_SUPPORT || PORTMOD_SUPPORT*/ 376 377 #endif /* !_SOC_HASH_H */