greyhound2.h (8216B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * File: greyhound2.h 8 */ 9 10 #ifndef _SOC_GREYHOUND2_H_ 11 #define _SOC_GREYHOUND2_H_ 12 13 #include <soc/drv.h> 14 #include <soc/mem.h> 15 #include <bcm/types.h> 16 #include <shared/sram.h> 17 18 enum soc_gh2_chip_sku_e { 19 SOC_GH2_SKU_HURRICANE3MG = 0, 20 SOC_GH2_SKU_QUARTZ = 1, 21 SOC_GH2_SKU_EMULATION = 2 22 }; 23 24 enum gh2_l2_hash_key_type_e { 25 /* WARNING: values given match hardware register; do not modify */ 26 GH2_L2_HASH_KEY_TYPE_BRIDGE = 0, 27 GH2_L2_HASH_KEY_TYPE_SINGLE_CROSS_CONNECT = 1, 28 GH2_L2_HASH_KEY_TYPE_DOUBLE_CROSS_CONNECT = 2, 29 GH2_L2_HASH_KEY_TYPE_VFI = 3, 30 GH2_L2_HASH_KEY_TYPE_VIF = 5, 31 GH2_L2_HASH_KEY_TYPE_PE_VID = 6, 32 GH2_L2_HASH_KEY_TYPE_VFI_MULTICAST = 7, 33 GH2_L2_HASH_KEY_TYPE_COUNT 34 }; 35 36 enum soc_gh2_port_mode_e { 37 /* WARNING: values given match hardware register; do not modify */ 38 SOC_GH2_PORT_MODE_QUAD = 0, 39 SOC_GH2_PORT_MODE_TRI_012 = 1, 40 SOC_GH2_PORT_MODE_TRI_023 = 2, 41 SOC_GH2_PORT_MODE_DUAL = 3, 42 SOC_GH2_PORT_MODE_SINGLE = 4, 43 SOC_GH2_PORT_MODE_TDM_DISABLE = 5 44 }; 45 46 enum soc_gh2_port_ratio_e { 47 SOC_GH2_PORT_RATIO_SINGLE, /* portN: 4 lanes */ 48 SOC_GH2_PORT_RATIO_SINGLE_XAUI, /* portN: 4 lanes, XAUI mode */ 49 SOC_GH2_PORT_RATIO_DUAL_2_2, /* portN: 2 lanes, portN+1: 2 lanes */ 50 SOC_GH2_PORT_RATIO_TRI_012, /* portN: 1 lane, portN+1: 1 lane, 51 portN+2: 2 lanes */ 52 SOC_GH2_PORT_RATIO_TRI_023, /* portN: 2 lanes, portN+1: 1 lane, 53 portN+2: 1 lane */ 54 SOC_GH2_PORT_RATIO_QUAD, /* portN: 1 lane, portN+1: 1 lane, 55 portN+2: 1 lane, portN+3: 1 lane */ 56 SOC_GH2_PORT_RATIO_COUNT 57 }; 58 59 enum soc_gh2_port_core_type_e { 60 SOC_GH2_PORT_CORE_TYPE_TSC, 61 SOC_GH2_PORT_CORE_TYPE_QTC, 62 SOC_GH2_PORT_CORE_TYPE_COUNT 63 }; 64 65 enum gh2_vlxlt_hash_key_type_e { 66 /* WARNING: values given match hardware register; do not modify */ 67 GH2_VLXLT_HASH_KEY_TYPE_IVID_OVID = 0, 68 GH2_VLXLT_HASH_KEY_TYPE_OTAG = 1, 69 GH2_VLXLT_HASH_KEY_TYPE_ITAG = 2, 70 GH2_VLXLT_HASH_KEY_TYPE_VLAN_MAC = 3, 71 GH2_VLXLT_HASH_KEY_TYPE_OVID = 4, 72 GH2_VLXLT_HASH_KEY_TYPE_IVID = 5, 73 GH2_VLXLT_HASH_KEY_TYPE_PRI_CFI = 6, 74 GH2_VLXLT_HASH_KEY_TYPE_HPAE = 7, 75 GH2_VLXLT_HASH_KEY_TYPE_PAYLOAD_IVID_OVID = 8, 76 GH2_VLXLT_HASH_KEY_TYPE_PAYLOAD_OTAG = 9, 77 GH2_VLXLT_HASH_KEY_TYPE_PAYLOAD_ITAG = 10, 78 GH2_VLXLT_HASH_KEY_TYPE_PAYLOAD_OVID = 11, 79 GH2_VLXLT_HASH_KEY_TYPE_PAYLOAD_IVID = 12, 80 GH2_VLXLT_HASH_KEY_TYPE_VNID = 13, 81 GH2_VLXLT_HASH_KEY_TYPE_PAYLOAD_COUNT 82 }; 83 84 /* MMU port index 58~65 in GH2 is with 64 COSQ */ 85 #define SOC_GH2_64Q_MMU_PORT_IDX_MIN 58 86 #define SOC_GH2_64Q_MMU_PORT_IDX_MAX 65 87 88 /* Per port COSQ and QGROUP number */ 89 #define SOC_GH2_QGROUP_PER_PORT_NUM 8 90 #define SOC_GH2_QLAYER_COSQ_PER_QGROUP_NUM 8 91 #define SOC_GH2_QLAYER_COSQ_PER_PORT_NUM (SOC_GH2_QGROUP_PER_PORT_NUM * \ 92 SOC_GH2_QLAYER_COSQ_PER_QGROUP_NUM) 93 94 #define SOC_GH2_LEGACY_QUEUE_NUM 8 95 #define SOC_GH2_2LEVEL_QUEUE_NUM SOC_GH2_QLAYER_COSQ_PER_PORT_NUM 96 97 extern void soc_esw_timesync_intr(int unit); 98 99 extern int 100 soc_gh2_l2x_base_entry_to_key(int unit, uint32 *entry, uint8 *key); 101 102 extern int 103 soc_gh2_64q_port_check(int unit, soc_port_t port, int *is_64q_port); 104 extern int 105 soc_gh2_mmu_bucket_qlayer_index(int unit, int p, int q, int *idx); 106 extern int 107 soc_gh2_mmu_bucket_qgroup_index(int unit, int p, int g, int *idx); 108 109 extern void soc_gh2_ser_cmic_interrupt_enable(int unit, int enable); 110 extern void soc_gh2_ser_fail(int unit); 111 extern int soc_gh2_ser_process_all(int unit, uint32 cmic_rval); 112 extern int soc_gh2_ser_enable_all(int unit, int enable); 113 extern int soc_gh2_oam_ser_process(int unit, soc_mem_t mem, int index); 114 extern int soc_gh2_chip_sku_get(int unit, int *sku); 115 extern int soc_gh2_tcam_ser_init(int unit); 116 extern int soc_gh2_oam_ser_process(int unit, soc_mem_t mem, int index); 117 extern int _soc_gh2_process_l2_overflow(int unit); 118 extern int _soc_gh2_mem_parity_control(int unit, soc_mem_t mem, 119 int copyno, int enable); 120 #ifdef SER_TR_TEST_SUPPORT 121 extern void soc_gh2_ser_test_register(int unit); 122 extern int ser_test_greyhound2_mem_index_remap( 123 int unit, ser_test_data_t *test_data, int *mem_has_ecc); 124 #endif /* SER_TR_TEST_SUPPORT */ 125 126 extern int soc_greyhound2_port_config_init(int unit, uint16 dev_id); 127 extern int soc_greyhound2_mem_config(int unit, int dev_id); 128 extern int soc_greyhound2_chip_reset(int unit); 129 extern int soc_greyhound2_sbus_tsc_block(int unit, int phy_port, int *blk); 130 extern int soc_greyhound2_tsc_reset(int unit); 131 extern int _soc_greyhound2_features(int unit, soc_feature_t feature); 132 133 extern int 134 soc_gh2_temperature_monitor_get(int unit, int temperature_max, 135 soc_switch_temperature_monitor_t *temperature_array, 136 int *temperature_count); 137 138 139 extern void soc_hu3_l2_overflow_interrupt_handler(int unit); 140 extern int soc_hu3_l2_overflow_disable(int unit); 141 extern int soc_hu3_l2_overflow_enable(int unit); 142 extern int soc_hu3_l2_overflow_fill(int unit, uint8 zeros_or_ones); 143 extern int soc_hu3_l2_overflow_stop(int unit); 144 extern int soc_hu3_l2_overflow_start(int unit); 145 extern int soc_hu3_l2_overflow_sync(int unit); 146 147 typedef int (*soc_gh2_cosq_event_handler_t)(int unit); 148 extern int 149 soc_gh2_cosq_event_handler_register(int unit, 150 soc_gh2_cosq_event_handler_t handler); 151 typedef int (*soc_gh2_tsn_event_handler_t)(int, uint8, uint8, uint8); 152 extern int 153 soc_gh2_tsn_event_handler_register(int unit, 154 soc_gh2_tsn_event_handler_t handler); 155 typedef int (*soc_gh2_taf_event_handler_t)(int unit 156 ); 157 extern int 158 soc_gh2_taf_event_handler_register(int unit, 159 soc_gh2_taf_event_handler_t handler); 160 161 162 extern soc_functions_t soc_greyhound2_drv_funs; 163 164 extern soc_error_t 165 soc_greyhound2_granular_speed_get(int unit, soc_port_t port, int *speed); 166 167 extern int 168 soc_greyhound2_port_speed_update(int unit, soc_port_t port, int speed); 169 extern int 170 soc_greyhound2_port_hg_speed_get(int unit, soc_port_t port, int *speed); 171 172 #ifdef BCM_WARM_BOOT_SUPPORT 173 extern int soc_gh2_port_init_speed_scache_sync(int unit); 174 #endif /* BCM_WARM_BOOT_SUPPORT */ 175 176 extern int 177 soc_greyhound2_bond_info_init(int unit); 178 typedef int (*soc_gh2_oam_handler_t)(int unit, 179 soc_field_t fault_field); 180 typedef int (*soc_gh2_oam_ser_handler_t)(int unit, 181 soc_mem_t mem, int index); 182 extern void soc_gh2_oam_ser_handler_register(int unit, soc_gh2_oam_ser_handler_t handler); 183 extern void soc_gh2_oam_handler_register(int unit, soc_gh2_oam_handler_t handler); 184 185 extern int soc_greyhound2_pgw_encap_field_modify(int unit, 186 soc_port_t lport, 187 soc_field_t field, 188 uint32 val); 189 extern int soc_greyhound2_pgw_encap_field_get(int unit, 190 soc_port_t lport, 191 soc_field_t field, 192 uint32 *val); 193 194 extern int soc_gh2_tdm_size_get(int unit, int *tdm_size); 195 extern int soc_gh2_tdm_size_set(int unit, int tdm_size); 196 197 /* Library-private functions exported from hash.c */ 198 extern uint32 199 soc_gh2_vlan_xlate_hash( 200 int unit, 201 int hash_sel, 202 int key_nbits, 203 void *base_entry, 204 uint8 *key); 205 206 extern int 207 soc_gh2_vlan_xlate_base_entry_to_key( 208 int unit, 209 uint32 *entry, 210 uint8 *key); 211 212 /* The first physical port number of each core */ 213 #define GH2_PHY_PORT_OFFSET_QTC0 26 214 #define GH2_PHY_PORT_OFFSET_QTC1 42 215 #define GH2_PHY_PORT_OFFSET_TSCE0 58 216 #define GH2_PHY_PORT_OFFSET_TSCE1 62 217 #define GH2_PHY_PORT_OFFSET_TSCE2 66 218 #define GH2_PHY_PORT_OFFSET_TSCE3 70 219 #define GH2_PHY_PORT_OFFSET_TSCE4 74 220 #define GH2_PHY_PORT_OFFSET_TSCE5 78 221 #define GH2_PHY_PORT_OFFSET_TSCE6 82 222 #define GH2_PHY_PORT_OFFSET_TSCF0 86 223 224 /* Validate if port configuration require TDM reallocation. */ 225 extern int 226 soc_greyhound2_auto_tdm_realloc(int unit); 227 228 #endif /* !_SOC_GREYHOUND2_H_ */