trident3_mmu_defines.h (6275B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * $File: trident3_mmu_defines.h 8 */ 9 10 11 #ifndef TRIDENT3_MMU_DEFINES_H 12 #define TRIDENT3_MMU_DEFINES_H 13 14 /*! @file trident3_mmu_defines.h 15 * @brief Macros used in APIs of MMU for Tomahawk2. 16 * Details are shown below. 17 */ 18 19 #define TD3_MMU_NUM_L0_NODES_PER_HSP_PORT 10 20 #define TD3_MMU_NUM_L0_NODES_FOR_CPU_PORT 48 21 #define TD3_MMU_NUM_UCQ_PER_HSP_PORT 10 22 #define TD3_MMU_NUM_MCQ_PER_HSP_PORT 10 23 #define TD3_MMU_NUM_MCQ_FOR_CPU_PORT 48 24 #define TD3_MMU_CPU_PORT_NUM 64 25 #define TD3_MMU_MGMT_PORT_NUM 64 26 #define TD3_MMU_MAX_PORTS_PER_PIPE 66 27 #define TD3_MMU_NUM_HSP_PORTS_PER_PIPE 66 28 #define TD3_MMU_LPBK_PORT_NUM 65 29 #define TD3_INVALID_MMU_PORT 255 30 #define TD3_INVALID_PHY_PORT_NUMBER 255 31 #define TD3_INVALID_DEV_PORT_NUMBER 255 32 #define TD3_MMU_PORT_PIPE_OFFSET 128 33 #define TD3_MMU_MCQ_NUMBER_START 660 34 #define TD3_MMU_NUM_UCQ 650 35 #define TD3_MMU_NUM_MC_QUEUES 698 36 #define TD3_MMU_NUM_MCQ_FP_PORTS 640 37 #define TD3_MMU_LPBK_PORT_L1_START TD3_MMU_MCQ_NUMBER_START+ \ 38 TD3_MMU_NUM_MCQ_FP_PORTS 39 #define TD3_MMU_MGMT_CPU_PORT_L1_START TD3_MMU_LPBK_PORT_L1_START+ \ 40 TD3_MMU_NUM_MCQ_PER_HSP_PORT 41 #define TD3_MMU_PIPE1_QUEUE_START TD3_MMU_NUM_UC_QUEUES+TD3_MMU_NUM_MC_QUEUES 42 43 44 #define TD3_MMU_BST_TRACK_MODE 0 45 #define TD3_MMU_BST_WMARK_MODE 1 46 #define TD3_MMU_MEM_ADDR__MEMIDX_WIDTH 16 47 #define TD3_MMU_NUM_PGS 8 48 #define TD3_MMU_NUM_SPS 4 49 #define TD3_MMU_NUM_COS 10 50 #define TD3_MMU_NUM_UC_QUEUES 650 51 #define TD3_MMU_NUM_PORTS_PER_PIPE 66 52 #define TD3_MMU_ACC_TYPE__ADDR_SPLIT_DIST 10 53 #define TD3_MMU_ACC_TYPE__ADDR_SPLIT_SPLIT 12 54 #define TD3_MMU_ACC_TYPE__DATA_SPLIT 14 55 #define TD3_MMU_ACC_TYPE__DUPLICATE 9 56 #define TD3_MMU_ACC_TYPE__SINGLE 20 57 #define TD3_MMU_ACC_TYPE__UNIQUE 31 58 #define TD3_MMU_ACC_TYPE__UNIQUE_PIPE0 0 59 #define TD3_MMU_ACC_TYPE__UNIQUE_PIPE1 1 60 #define TD3_MMU_ACC_TYPE__UNIQUE_PIPE2 2 61 #define TD3_MMU_ACC_TYPE__UNIQUE_PIPE3 3 62 #define TD3_MMU_BASE_TYPE__XPE 5 63 #define TD3_MMU_BASE_TYPE__CHIP 4 64 #define TD3_MMU_BASE_TYPE__SLICE 6 65 #define TD3_MMU_BASE_TYPE__EPORT 1 66 #define TD3_MMU_BASE_TYPE__IPIPE 2 67 #define TD3_MMU_BASE_TYPE__EPIPE 3 68 #define TD3_MMU_BASE_TYPE__IPORT 0 69 #define TD3_MMU_BASE_TYPE__LAYER 7 70 #define TD3_MMU_THDU_UCQ_PER_PORT 10 71 #define TD3_MMU_THDI_PG_MIN_LIMIT_LOSSLESS 8 72 #define TD3_MMU_THDI_PG_MIN_LIMIT_LOSSY 0 73 #define TD3_MMU_THDI_PG_HDRM_LIMIT_LOSSY 0 74 #define TD3_MMU_THDI_SP_MAX_LIMIT 53248 75 #define TD3_MMU_THDI_SP_RESUME_LIMIT 53232 76 #define TD3_MMU_NUM_SPEEDS 7 77 #define TD3_MMU_NUM_PORT_COLOR_DROP_ENTRIES 5 78 79 #define TD3_MMU_THDI_PORT_XON_ENABLE_VAL 65535 80 #define TD3_MMU_THDU_QGRP_MIN_LIMIT_LOSELESS 16 81 #define TD3_MMU_THDU_QGRP_MIN_LIMIT_LOSSY TD3_MMU_THDU_QGRP_MIN_LIMIT_LOSELESS 82 #define TD3_MMU_THDU_QUEUE_SHARED_ALPHA_LOSSY 8 83 #define TD3_MMU_THDU_QUEUE_SHARED_ALPHA_LOSSLESS 52296 84 #define TD3_MMU_THDU_QUEUE_SHARED_LIMIT_LOSSY 8 85 #define TD3_MMU_THDU_QUEUE_SHARED_LIMIT_LOSSLESS 52296 86 #define TD3_MMU_THDU_QUEUE_LIMIT_DYNAMIC_LOSSY 1 87 #define TD3_MMU_THDU_QUEUE_LIMIT_DYNAMIC_LOSSLESS 0 88 #define TD3_MMU_THDU_QUEUE_COLOR_LIMIT_DYNAMIC_LOSSY 1 89 #define TD3_MMU_THDU_QUEUE_COLOR_LIMIT_DYNAMIC_LOSSLESS 0 90 #define TD3_MMU_THDU_QUEUE_LIMIT_ENABLE_LOSSY 1 91 #define TD3_MMU_THDU_QUEUE_LIMIT_ENABLE_LOSSLESS 0 92 #define TD3_MMU_NUM_CT_SPEED_GROUPS 12 93 #define TD3_MAX_NUM_CELLS 37 /* (9416-192)/256 + 1 SOP Cell */ 94 #define TD3_CT_FIFO_WAIT 15 /*Refer to port_down seq. in TH2 flexport arch */ 95 #define TD3_MMU_PAUSE_PG 7 /*PG7-Used for Initial PG_Min/hdrm + for Pause */ 96 97 typedef enum pipe_s 98 { 99 TD3_IPIPE, 100 TD3_EPIPE 101 } pipe_t; 102 103 #define TD3_MMU_MEM_ADDR__MEMIDX_WIDTH 16 104 #define TD3_MMU_FLUSH_OFF 0 105 #define TD3_MMU_FLUSH_ON 1 106 #define TD3_PKTSTATS_ON 1 107 #define TD3_MMU_THD_RX_ENABLED 1 108 #define TD3_MMU_THD_RX_DISABLED 0 109 110 #define TD3_MMU_IS_CPU_PORT(pipe, port) ((pipe == 0) && \ 111 (port == TD3_MMU_CPU_PORT_NUM)) 112 #define TD3_MMU_IS_MGMT_PORT(pipe, \ 113 port) ((pipe == 1) && \ 114 (port == TD3_MMU_MGMT_PORT_NUM)) 115 #define TD3_MMU_IS_LPBK_PORT(port) (port == TD3_MMU_LPBK_PORT_NUM) 116 #define TD3_MMU_GET_PIPE_NUM(port, pipe) \ 117 pipe = port/TD3_MMU_PORT_PIPE_OFFSET 118 #define TD3_MMU_PIPE_NUM(port) port/TD3_MMU_PORT_PIPE_OFFSET 119 120 #define TD3_MMU_HANDLE_ENUMS_EPIPE_DUPLICATE(mem_name) \ 121 soc_mem_t mem_name ## _enums[4][2] = \ 122 {{mem_name ## _PIPE0m, \ 123 -1}, \ 124 {mem_name ## _PIPE1m, \ 125 -1}, {mem_name ## _PIPE2m, -1}, {mem_name ## _PIPE3m, -1}} 126 127 #define TD3_MMU_HANDLE_ENUMS_IPIPE_DUPLICATE(mem_name) \ 128 soc_mem_t mem_name ## _enums[4][2] = \ 129 {{mem_name ## _PIPE0m, \ 130 -1}, \ 131 {mem_name ## _PIPE1m, \ 132 -1}, {mem_name ## _PIPE2m, -1}, {mem_name ## _PIPE3m, -1}} 133 134 #define TD3_MMU_HANDLE_ENUMS_EPIPE_UNIQUE(mem_name) \ 135 soc_mem_t mem_name ## _enums[4][2] = \ 136 {{mem_name ## _XPE0_PIPE0m, \ 137 mem_name ## _XPE2_PIPE0m}, \ 138 {mem_name ## _XPE0_PIPE1m, \ 139 mem_name ## _XPE2_PIPE1m}, \ 140 {mem_name ## _XPE1_PIPE2m, \ 141 mem_name ## _XPE3_PIPE2m}, \ 142 {mem_name ## _XPE1_PIPE3m, mem_name ## _XPE3_PIPE3m}}; \ 143 144 #define TD3_MMU_HANDLE_ENUMS_IPIPE_UNIQUE(mem_name) \ 145 soc_mem_t mem_name ## _enums[4][2] = \ 146 {{mem_name ## _XPE0_PIPE0m, \ 147 mem_name ## _XPE1_PIPE0m}, \ 148 {mem_name ## _XPE2_PIPE1m, \ 149 mem_name ## _XPE3_PIPE1m}, \ 150 {mem_name ## _XPE2_PIPE2m, \ 151 mem_name ## _XPE3_PIPE2m}, \ 152 {mem_name ## _XPE0_PIPE3m, mem_name ## _XPE1_PIPE3m}}; \ 153 154 #define TD3_MMU_GET_HANDLE(mem_name, base_index, acc_index, handle) \ 155 handle = mem_name ## _enums[base_index][acc_index] 156 157 /* START - FlexPort types as defined in SDK. */ 158 typedef enum { 159 TD3_SPEED_10G_ETH_DECODE = 1, 160 TD3_SPEED_10G_HG_DECODE = 2, 161 TD3_SPEED_20G_ETH_DECODE = 3, 162 TD3_SPEED_20G_HG_DECODE = 4, 163 TD3_SPEED_25G_ETH_DECODE = 5, 164 TD3_SPEED_25G_HG_DECODE = 6, 165 TD3_SPEED_40G_ETH_DECODE = 7, 166 TD3_SPEED_40G_HG_DECODE = 8, 167 TD3_SPEED_50G_ETH_DECODE = 9, 168 TD3_SPEED_50G_HG_DECODE = 10, 169 TD3_SPEED_100G_ETH_DECODE = 11, 170 TD3_SPEED_100G_HG_DECODE = 12 171 } _soc_td3_ct_speed_decode_e; 172 173 #endif /* TRIDENT3_MMU_DEFINES_H */